1//===-- PPCRegisterInfo.h - PowerPC Register Information Impl ---*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the PowerPC implementation of the TargetRegisterInfo
10// class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_POWERPC_PPCREGISTERINFO_H
15#define LLVM_LIB_TARGET_POWERPC_PPCREGISTERINFO_H
16
17#include "MCTargetDesc/PPCMCTargetDesc.h"
18#include "llvm/ADT/DenseMap.h"
19
20#define GET_REGINFO_HEADER
21#include "PPCGenRegisterInfo.inc"
22
23namespace llvm {
24class PPCTargetMachine;
25
26inline static unsigned getCRFromCRBit(unsigned SrcReg) {
27 unsigned Reg = 0;
28 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
29 SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
30 Reg = PPC::CR0;
31 else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
32 SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN)
33 Reg = PPC::CR1;
34 else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT ||
35 SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN)
36 Reg = PPC::CR2;
37 else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT ||
38 SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN)
39 Reg = PPC::CR3;
40 else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT ||
41 SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN)
42 Reg = PPC::CR4;
43 else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT ||
44 SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN)
45 Reg = PPC::CR5;
46 else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT ||
47 SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN)
48 Reg = PPC::CR6;
49 else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT ||
50 SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN)
51 Reg = PPC::CR7;
52
53 assert(Reg != 0 && "Invalid CR bit register");
54 return Reg;
55}
56
57class PPCRegisterInfo : public PPCGenRegisterInfo {
58 DenseMap<unsigned, unsigned> ImmToIdxMap;
59 const PPCTargetMachine &TM;
60
61 void spillRegPair(MachineBasicBlock &MBB, MachineBasicBlock::iterator II,
62 DebugLoc DL, const TargetInstrInfo &TII,
63 unsigned FrameIndex, bool IsLittleEndian, bool IsKilled,
64 Register Reg, int Offset) const;
65
66public:
67 PPCRegisterInfo(const PPCTargetMachine &TM);
68
69 /// getMappedIdxOpcForImmOpc - Return the mapped index form load/store opcode
70 /// for a given imm form load/store opcode \p ImmFormOpcode.
71 /// FIXME: move this to PPCInstrInfo class.
72 unsigned getMappedIdxOpcForImmOpc(unsigned ImmOpcode) const {
73 auto It = ImmToIdxMap.find(Val: ImmOpcode);
74 if (It == ImmToIdxMap.end())
75 return PPC::INSTRUCTION_LIST_END;
76 return It->second;
77 }
78
79 const TargetRegisterClass *
80 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
81
82 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
83 MachineFunction &MF) const override;
84
85 const TargetRegisterClass *
86 getLargestLegalSuperClass(const TargetRegisterClass *RC,
87 const MachineFunction &MF) const override;
88
89 /// Code Generation virtual methods...
90 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
91 const uint32_t *getCallPreservedMask(const MachineFunction &MF,
92 CallingConv::ID CC) const override;
93 const uint32_t *getNoPreservedMask() const override;
94
95 void adjustStackMapLiveOutMask(uint32_t *Mask) const override;
96
97 BitVector getReservedRegs(const MachineFunction &MF) const override;
98 bool isAsmClobberable(const MachineFunction &MF,
99 MCRegister PhysReg) const override;
100 bool isCallerPreservedPhysReg(MCRegister PhysReg,
101 const MachineFunction &MF) const override;
102
103 // Provide hints to the register allocator for allocating subregisters
104 // of primed and unprimed accumulators. For example, if accumulator
105 // ACC5 is assigned, we also want to assign UACC5 to the input.
106 // Similarly if UACC5 is assigned, we want to assign VSRp10, VSRp11
107 // to its inputs.
108 bool getRegAllocationHints(Register VirtReg, ArrayRef<MCPhysReg> Order,
109 SmallVectorImpl<MCPhysReg> &Hints,
110 const MachineFunction &MF, const VirtRegMap *VRM,
111 const LiveRegMatrix *Matrix) const override;
112
113 /// We require the register scavenger.
114 bool requiresRegisterScavenging(const MachineFunction &MF) const override {
115 return true;
116 }
117
118 bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
119
120 bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override;
121
122 void lowerDynamicAlloc(MachineBasicBlock::iterator II) const;
123 void lowerDynamicAreaOffset(MachineBasicBlock::iterator II) const;
124 void prepareDynamicAlloca(MachineBasicBlock::iterator II,
125 Register &NegSizeReg, bool &KillNegSizeReg,
126 Register &FramePointer) const;
127 void lowerPrepareProbedAlloca(MachineBasicBlock::iterator II) const;
128 void lowerCRSpilling(MachineBasicBlock::iterator II,
129 unsigned FrameIndex) const;
130 void lowerCRRestore(MachineBasicBlock::iterator II,
131 unsigned FrameIndex) const;
132 void lowerCRBitSpilling(MachineBasicBlock::iterator II,
133 unsigned FrameIndex) const;
134 void lowerCRBitRestore(MachineBasicBlock::iterator II,
135 unsigned FrameIndex) const;
136
137 void lowerOctWordSpilling(MachineBasicBlock::iterator II,
138 unsigned FrameIndex) const;
139 void lowerACCSpilling(MachineBasicBlock::iterator II,
140 unsigned FrameIndex) const;
141 void lowerACCRestore(MachineBasicBlock::iterator II,
142 unsigned FrameIndex) const;
143
144 void lowerWACCSpilling(MachineBasicBlock::iterator II,
145 unsigned FrameIndex) const;
146 void lowerWACCRestore(MachineBasicBlock::iterator II,
147 unsigned FrameIndex) const;
148
149 void lowerQuadwordSpilling(MachineBasicBlock::iterator II,
150 unsigned FrameIndex) const;
151 void lowerQuadwordRestore(MachineBasicBlock::iterator II,
152 unsigned FrameIndex) const;
153
154 void lowerDMRSpilling(MachineBasicBlock::iterator II,
155 unsigned FrameIndex) const;
156 void lowerDMRRestore(MachineBasicBlock::iterator II,
157 unsigned FrameIndex) const;
158
159 static void emitAccCopyInfo(MachineBasicBlock &MBB, MCRegister DestReg,
160 MCRegister SrcReg);
161
162 bool hasReservedSpillSlot(const MachineFunction &MF, Register Reg,
163 int &FrameIdx) const override;
164 bool eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
165 unsigned FIOperandNum,
166 RegScavenger *RS = nullptr) const override;
167
168 // Support for virtual base registers.
169 bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
170 Register materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx,
171 int64_t Offset) const override;
172 void resolveFrameIndex(MachineInstr &MI, Register BaseReg,
173 int64_t Offset) const override;
174 bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg,
175 int64_t Offset) const override;
176
177 // Debug information queries.
178 Register getFrameRegister(const MachineFunction &MF) const override;
179
180 // Base pointer (stack realignment) support.
181 Register getBaseRegister(const MachineFunction &MF) const;
182 bool hasBasePointer(const MachineFunction &MF) const;
183
184 bool isNonallocatableRegisterCalleeSave(MCRegister Reg) const override {
185 return Reg == PPC::LR || Reg == PPC::LR8;
186 }
187
188 bool isVirtualFrameRegister(MCRegister Reg) const override {
189 return Reg == PPC::FP || Reg == PPC::FP8;
190 }
191};
192
193} // end namespace llvm
194
195#endif
196