1//===-- RISCVMCTargetDesc.h - RISC-V Target Descriptions --------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file provides RISC-V specific target descriptions.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVMCTARGETDESC_H
14#define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVMCTARGETDESC_H
15
16#include "llvm/MC/MCTargetOptions.h"
17#include "llvm/Support/DataTypes.h"
18#include <memory>
19
20namespace llvm {
21class MCAsmBackend;
22class MCCodeEmitter;
23class MCContext;
24class MCInstrInfo;
25class MCObjectTargetWriter;
26class MCRegisterInfo;
27class MCRelocationInfo;
28class MCSubtargetInfo;
29class Target;
30
31MCCodeEmitter *createRISCVMCCodeEmitter(const MCInstrInfo &MCII,
32 MCContext &Ctx);
33
34MCAsmBackend *createRISCVAsmBackend(const Target &T, const MCSubtargetInfo &STI,
35 const MCRegisterInfo &MRI,
36 const MCTargetOptions &Options);
37
38std::unique_ptr<MCObjectTargetWriter> createRISCVELFObjectWriter(uint8_t OSABI,
39 bool Is64Bit);
40std::unique_ptr<MCObjectTargetWriter>
41createRISCVMachObjectWriter(uint32_t CPUType, uint32_t CPUSubtype);
42} // namespace llvm
43
44// Defines symbolic names for RISC-V registers.
45#define GET_REGINFO_ENUM
46#include "RISCVGenRegisterInfo.inc"
47
48// Defines symbolic names for RISC-V instructions.
49#define GET_INSTRINFO_ENUM
50#define GET_INSTRINFO_MC_HELPER_DECLS
51#include "RISCVGenInstrInfo.inc"
52
53#define GET_SUBTARGETINFO_ENUM
54#include "RISCVGenSubtargetInfo.inc"
55
56#endif
57