1//===-- SPIRVISelLowering.h - SPIR-V DAG Lowering Interface -----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that SPIR-V uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_SPIRV_SPIRVISELLOWERING_H
15#define LLVM_LIB_TARGET_SPIRV_SPIRVISELLOWERING_H
16
17#include "SPIRVGlobalRegistry.h"
18#include "llvm/CodeGen/TargetLowering.h"
19#include <set>
20
21namespace llvm {
22class SPIRVSubtarget;
23
24class SPIRVTargetLowering : public TargetLowering {
25 const SPIRVSubtarget &STI;
26
27 // Record of already processed machine functions
28 mutable std::set<const MachineFunction *> ProcessedMF;
29
30public:
31 explicit SPIRVTargetLowering(const TargetMachine &TM,
32 const SPIRVSubtarget &ST);
33
34 // Stop IRTranslator breaking up FMA instrs to preserve types information.
35 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
36 EVT) const override {
37 return true;
38 }
39
40 // prevent creation of jump tables
41 bool areJTsAllowed(const Function *) const override { return false; }
42
43 // This is to prevent sexts of non-i64 vector indices which are generated
44 // within general IRTranslator hence type generation for it is omitted.
45 unsigned getVectorIdxWidth(const DataLayout &DL) const override { return 32; }
46 unsigned getNumRegistersForCallingConv(LLVMContext &Context,
47 CallingConv::ID CC,
48 EVT VT) const override;
49 MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC,
50 EVT VT) const override;
51 void getTgtMemIntrinsic(SmallVectorImpl<IntrinsicInfo> &Infos,
52 const CallBase &I, MachineFunction &MF,
53 unsigned Intrinsic) const override;
54
55 std::pair<unsigned, const TargetRegisterClass *>
56 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
57 StringRef Constraint, MVT VT) const override;
58 unsigned
59 getNumRegisters(LLVMContext &Context, EVT VT,
60 std::optional<MVT> RegisterVT = std::nullopt) const override {
61 return 1;
62 }
63
64 // Call the default implementation and finalize target lowering by inserting
65 // extra instructions required to preserve validity of SPIR-V code imposed by
66 // the standard.
67 void finalizeLowering(MachineFunction &MF) const override;
68
69 MVT getPreferredSwitchConditionType(LLVMContext &Context,
70 EVT ConditionVT) const override {
71 return ConditionVT.getSimpleVT();
72 }
73
74 bool enforcePtrTypeCompatibility(MachineInstr &I, unsigned PtrOpIdx,
75 unsigned OpIdx) const;
76 bool insertLogicalCopyOnResult(MachineInstr &I,
77 SPIRVType *NewResultType) const;
78};
79} // namespace llvm
80
81#endif // LLVM_LIB_TARGET_SPIRV_SPIRVISELLOWERING_H
82