1//===-- SPIRVISelLowering.h - SPIR-V DAG Lowering Interface -----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that SPIR-V uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_SPIRV_SPIRVISELLOWERING_H
15#define LLVM_LIB_TARGET_SPIRV_SPIRVISELLOWERING_H
16
17#include "SPIRVGlobalRegistry.h"
18#include "llvm/CodeGen/TargetLowering.h"
19
20namespace llvm {
21class SPIRVSubtarget;
22
23class SPIRVTargetLowering : public TargetLowering {
24 const SPIRVSubtarget &STI;
25
26public:
27 explicit SPIRVTargetLowering(const TargetMachine &TM,
28 const SPIRVSubtarget &ST);
29
30 // Stop IRTranslator breaking up FMA instrs to preserve types information.
31 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
32 EVT) const override {
33 return true;
34 }
35
36 // prevent creation of jump tables
37 bool areJTsAllowed(const Function *) const override { return false; }
38
39 // This is to prevent sexts of non-i64 vector indices which are generated
40 // within general IRTranslator hence type generation for it is omitted.
41 unsigned getVectorIdxWidth(const DataLayout &DL) const override { return 32; }
42 unsigned getNumRegistersForCallingConv(LLVMContext &Context,
43 CallingConv::ID CC,
44 EVT VT) const override;
45 MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC,
46 EVT VT) const override;
47 void getTgtMemIntrinsic(SmallVectorImpl<IntrinsicInfo> &Infos,
48 const CallBase &I, MachineFunction &MF,
49 unsigned Intrinsic) const override;
50
51 ConstraintType getConstraintType(StringRef Constraint) const override;
52
53 std::pair<unsigned, const TargetRegisterClass *>
54 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
55 StringRef Constraint, MVT VT) const override;
56 unsigned
57 getNumRegisters(LLVMContext &Context, EVT VT,
58 std::optional<MVT> RegisterVT = std::nullopt) const override {
59 return 1;
60 }
61
62 // Call the default implementation and finalize target lowering by inserting
63 // extra instructions required to preserve validity of SPIR-V code imposed by
64 // the standard.
65 void finalizeLowering(MachineFunction &MF) const override;
66
67 MVT getPreferredSwitchConditionType(LLVMContext &Context,
68 EVT ConditionVT) const override {
69 return ConditionVT.getSimpleVT();
70 }
71
72 bool enforcePtrTypeCompatibility(MachineInstr &I, unsigned PtrOpIdx,
73 unsigned OpIdx) const;
74 bool insertLogicalCopyOnResult(MachineInstr &I,
75 SPIRVTypeInst NewResultType) const;
76
77 AtomicExpansionKind
78 shouldExpandAtomicRMWInIR(const AtomicRMWInst *RMW) const override;
79 AtomicExpansionKind
80 shouldCastAtomicRMWIInIR(AtomicRMWInst *RMWI) const override;
81
82 bool shouldIssueAtomicLoadForAtomicEmulationLoop() const override {
83 return false;
84 }
85};
86} // namespace llvm
87
88#endif // LLVM_LIB_TARGET_SPIRV_SPIRVISELLOWERING_H
89