1//===-- VVPNodes.def - Lists & properties of VE Vector Predication Nodes --===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines all VVP_* SDNodes and their properties
10//
11//===----------------------------------------------------------------------===//
12
13/// HANDLE_VP_TO_VVP(VPOPC, VVPOPC)
14/// \p VPOPC is the VP_* SDNode opcode.
15/// \p VVPOPC is the VVP_* SDNode opcode.
16#ifndef HANDLE_VP_TO_VVP
17#define HANDLE_VP_TO_VVP(VPOPC, VVPOPC)
18#endif
19
20/// ADD_VVP_OP(VVPNAME,SDNAME)
21/// \p VVPName is a VVP SDNode operator.
22/// \p SDNAME is the generic SD opcode corresponding to \p VVPName.
23#ifndef ADD_VVP_OP
24#define ADD_VVP_OP(X, Y)
25#endif
26
27/// ADD_UNARY_VVP_OP(VVPNAME,SDNAME)
28/// \p VVPName is a VVP Unary operator.
29/// \p SDNAME is the generic SD opcode corresponding to \p VVPName.
30#ifndef ADD_UNARY_VVP_OP
31#define ADD_UNARY_VVP_OP(VVPNAME,SDNAME) \
32 ADD_VVP_OP(VVPNAME,SDNAME)
33#endif
34
35/// ADD_BINARY_VVP_OP(VVPNAME,SDNAME)
36/// \p VVPName is a VVP Binary operator.
37/// \p SDNAME is the generic SD opcode corresponding to \p VVPName.
38#ifndef ADD_BINARY_VVP_OP
39#define ADD_BINARY_VVP_OP(VVPNAME,SDNAME) \
40 ADD_VVP_OP(VVPNAME,SDNAME)
41#endif
42
43/// ADD_TERNARY_VVP_OP(VVPNAME,SDNAME)
44/// \p VVPName is a VVP Ternary operator.
45/// \p SDNAME is the generic SD opcode corresponding to \p VVPName.
46#ifndef ADD_TERNARY_VVP_OP
47#define ADD_TERNARY_VVP_OP(VVPNAME,SDNAME) \
48 ADD_VVP_OP(VVPNAME,SDNAME)
49#endif
50
51#ifndef ADD_BINARY_VVP_OP_COMPACT
52#define ADD_BINARY_VVP_OP_COMPACT(NAME) \
53 ADD_BINARY_VVP_OP(VVP_##NAME,NAME)
54#endif
55
56/// REGISTER_PACKED(OPC)
57/// \p OPC The VVP opcode of the operation.
58#ifndef REGISTER_PACKED
59#define REGISTER_PACKED(OPC)
60#endif
61
62/// ADD_REDUCE_VVP_OP(OPC)
63/// \p OPC The VVP opcode of the operation.
64/// \p SDNAME The standard opcode of the operation.
65#ifndef ADD_REDUCE_VVP_OP
66#define ADD_REDUCE_VVP_OP(OPC, SDNAME) ADD_VVP_OP(OPC, SDNAME)
67#endif
68
69// Scalar standard ISD to perform this reduction.
70#ifndef HANDLE_VVP_REDUCE_TO_SCALAR
71#define HANDLE_VVP_REDUCE_TO_SCALAR(VVP_RED_ISD, REDUCE_ISD)
72#endif
73
74/// Reductions.
75#define HELPER_REDUCTION(OPC, SCALAR_OPC) \
76 ADD_REDUCE_VVP_OP(VVP_REDUCE_##OPC,VECREDUCE_##OPC) \
77 HANDLE_VP_TO_VVP(VP_REDUCE_##OPC, VVP_REDUCE_##OPC) \
78 HANDLE_VVP_REDUCE_TO_SCALAR(VVP_REDUCE_##OPC, SCALAR_OPC)
79
80HELPER_REDUCTION(ADD, ADD)
81HELPER_REDUCTION(AND, AND)
82HELPER_REDUCTION(OR, OR)
83HELPER_REDUCTION(XOR, XOR)
84HELPER_REDUCTION(SMAX, SMAX)
85
86#undef HELPER_REDUCTION
87
88ADD_VVP_OP(VVP_LOAD,LOAD) HANDLE_VP_TO_VVP(VP_LOAD, VVP_LOAD) REGISTER_PACKED(VVP_LOAD)
89ADD_VVP_OP(VVP_STORE,STORE) HANDLE_VP_TO_VVP(VP_STORE, VVP_STORE) REGISTER_PACKED(VVP_STORE)
90
91ADD_VVP_OP(VVP_GATHER, MGATHER) HANDLE_VP_TO_VVP(VP_GATHER, VVP_GATHER)
92ADD_VVP_OP(VVP_SCATTER, MSCATTER) HANDLE_VP_TO_VVP(VP_SCATTER, VVP_SCATTER)
93
94// Integer arithmetic.
95ADD_BINARY_VVP_OP_COMPACT(ADD) REGISTER_PACKED(VVP_ADD)
96ADD_BINARY_VVP_OP_COMPACT(SUB) REGISTER_PACKED(VVP_SUB)
97ADD_BINARY_VVP_OP_COMPACT(MUL)
98ADD_BINARY_VVP_OP_COMPACT(UDIV)
99HANDLE_VP_TO_VVP(VP_UDIV, VVP_UDIV)
100ADD_BINARY_VVP_OP_COMPACT(SDIV)
101HANDLE_VP_TO_VVP(VP_SDIV, VVP_SDIV)
102
103ADD_BINARY_VVP_OP(VVP_SRA,SRA) REGISTER_PACKED(VVP_SRA)
104ADD_BINARY_VVP_OP(VVP_SRL,SRL) REGISTER_PACKED(VVP_SRL)
105ADD_BINARY_VVP_OP_COMPACT(SHL) REGISTER_PACKED(VVP_SHL)
106
107ADD_BINARY_VVP_OP_COMPACT(AND) REGISTER_PACKED(VVP_AND)
108ADD_BINARY_VVP_OP_COMPACT(OR) REGISTER_PACKED(VVP_OR)
109ADD_BINARY_VVP_OP_COMPACT(XOR) REGISTER_PACKED(VVP_XOR)
110
111// FP arithmetic.
112ADD_UNARY_VVP_OP(VVP_FNEG, FNEG) REGISTER_PACKED(VVP_FNEG)
113ADD_BINARY_VVP_OP_COMPACT(FADD) REGISTER_PACKED(VVP_FADD)
114ADD_BINARY_VVP_OP_COMPACT(FSUB) REGISTER_PACKED(VVP_FSUB)
115ADD_BINARY_VVP_OP_COMPACT(FMUL) REGISTER_PACKED(VVP_FMUL)
116ADD_BINARY_VVP_OP_COMPACT(FDIV)
117
118ADD_TERNARY_VVP_OP(VVP_FFMA,FMA) REGISTER_PACKED(VVP_FFMA)
119
120ADD_VVP_OP(VVP_SETCC, SETCC)
121
122// Shuffles.
123ADD_VVP_OP(VVP_SELECT,VSELECT) REGISTER_PACKED(VVP_SELECT)
124HANDLE_VP_TO_VVP(VP_MERGE, VVP_SELECT)
125
126
127#undef ADD_BINARY_VVP_OP
128#undef ADD_TERNARY_VVP_OP
129#undef ADD_UNARY_VVP_OP
130#undef ADD_BINARY_VVP_OP_COMPACT
131#undef ADD_REDUCE_VVP_OP
132#undef ADD_VVP_OP
133#undef HANDLE_VP_TO_VVP
134#undef HANDLE_VVP_REDUCE_TO_SCALAR
135#undef REGISTER_PACKED
136