1//- WebAssemblyISelLowering.h - WebAssembly DAG Lowering Interface -*- C++ -*-//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// \file
10/// This file defines the interfaces that WebAssembly uses to lower LLVM
11/// code into a selection DAG.
12///
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYISELLOWERING_H
16#define LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYISELLOWERING_H
17
18#include "llvm/CodeGen/TargetLowering.h"
19
20namespace llvm {
21
22class WebAssemblySubtarget;
23
24class WebAssemblyTargetLowering final : public TargetLowering {
25public:
26 WebAssemblyTargetLowering(const TargetMachine &TM,
27 const WebAssemblySubtarget &STI);
28
29private:
30 /// Keep a pointer to the WebAssemblySubtarget around so that we can make the
31 /// right decision when generating code for different targets.
32 const WebAssemblySubtarget *Subtarget;
33
34 AtomicExpansionKind
35 shouldExpandAtomicRMWInIR(const AtomicRMWInst *) const override;
36 bool shouldScalarizeBinop(SDValue VecOp) const override;
37 FastISel *
38 createFastISel(FunctionLoweringInfo &FuncInfo,
39 const TargetLibraryInfo *LibInfo,
40 const LibcallLoweringInfo *LibcallLowering) const override;
41 MVT getScalarShiftAmountTy(const DataLayout &DL, EVT) const override;
42 MachineBasicBlock *
43 EmitInstrWithCustomInserter(MachineInstr &MI,
44 MachineBasicBlock *MBB) const override;
45 std::pair<unsigned, const TargetRegisterClass *>
46 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
47 StringRef Constraint, MVT VT) const override;
48 bool isCheapToSpeculateCttz(Type *Ty) const override;
49 bool isCheapToSpeculateCtlz(Type *Ty) const override;
50 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
51 unsigned AS,
52 Instruction *I = nullptr) const override;
53 bool allowsMisalignedMemoryAccesses(EVT, unsigned AddrSpace, Align Alignment,
54 MachineMemOperand::Flags Flags,
55 unsigned *Fast) const override;
56 bool isIntDivCheap(EVT VT, AttributeList Attr) const override;
57 bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
58 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
59 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
60 EVT VT) const override;
61 void getTgtMemIntrinsic(SmallVectorImpl<IntrinsicInfo> &Infos,
62 const CallBase &I, MachineFunction &MF,
63 unsigned Intrinsic) const override;
64
65 void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known,
66 const APInt &DemandedElts,
67 const SelectionDAG &DAG,
68 unsigned Depth) const override;
69
70 TargetLoweringBase::LegalizeTypeAction
71 getPreferredVectorAction(MVT VT) const override;
72 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
73 EVT VT) const override;
74
75 bool isProfitableToCombineMinNumMaxNum(EVT VT) const override {
76 // Prefer leaving cmp + select alone to form pmin/pmax,
77 // or relaxed_fmin/relaxed_fmax with appropriate FMF.
78 return false;
79 }
80
81 SDValue LowerCall(CallLoweringInfo &CLI,
82 SmallVectorImpl<SDValue> &InVals) const override;
83 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
84 bool isVarArg,
85 const SmallVectorImpl<ISD::OutputArg> &Outs,
86 LLVMContext &Context, const Type *RetTy) const override;
87 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
88 const SmallVectorImpl<ISD::OutputArg> &Outs,
89 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl,
90 SelectionDAG &DAG) const override;
91 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
92 bool IsVarArg,
93 const SmallVectorImpl<ISD::InputArg> &Ins,
94 const SDLoc &DL, SelectionDAG &DAG,
95 SmallVectorImpl<SDValue> &InVals) const override;
96
97 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
98 SelectionDAG &DAG) const override;
99
100 bool
101 shouldSimplifyDemandedVectorElts(SDValue Op,
102 const TargetLoweringOpt &TLO) const override;
103
104 // Custom lowering hooks.
105 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
106 SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
107 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
108 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
109 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
110 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
111 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
112 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
113 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
114 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
115 SDValue LowerCopyToReg(SDValue Op, SelectionDAG &DAG) const;
116 SDValue LowerIntrinsic(SDValue Op, SelectionDAG &DAG) const;
117 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
118 SDValue LowerEXTEND_VECTOR_INREG(SDValue Op, SelectionDAG &DAG) const;
119 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
120 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
121 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
122 SDValue LowerAccessVectorElement(SDValue Op, SelectionDAG &DAG) const;
123 SDValue LowerShift(SDValue Op, SelectionDAG &DAG) const;
124 SDValue LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const;
125 SDValue LowerFMIN(SDValue Op, SelectionDAG &DAG) const;
126 SDValue LowerFMAX(SDValue Op, SelectionDAG &DAG) const;
127 SDValue LowerLoad(SDValue Op, SelectionDAG &DAG) const;
128 SDValue LowerStore(SDValue Op, SelectionDAG &DAG) const;
129 SDValue LowerMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
130 SDValue Replace128Op(SDNode *N, SelectionDAG &DAG) const;
131 SDValue LowerUADDO(SDValue Op, SelectionDAG &DAG) const;
132
133 // Custom DAG combine hooks
134 SDValue
135 PerformDAGCombine(SDNode *N,
136 TargetLowering::DAGCombinerInfo &DCI) const override;
137};
138
139namespace WebAssembly {
140FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
141 const TargetLibraryInfo *libInfo,
142 const LibcallLoweringInfo *libcallLowering);
143} // end namespace WebAssembly
144
145} // end namespace llvm
146
147#endif
148