1//===-- ARMTargetParser - Parser for ARM target features --------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements a target parser to recognise ARM hardware features
10// such as FPU/CPU/ARCH/extensions and specific support such as HWDIV.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/TargetParser/ARMTargetParser.h"
15#include "llvm/ADT/StringSwitch.h"
16#include "llvm/Support/Format.h"
17#include "llvm/Support/raw_ostream.h"
18#include "llvm/TargetParser/ARMTargetParserCommon.h"
19#include "llvm/TargetParser/Triple.h"
20
21using namespace llvm;
22
23static StringRef getHWDivSynonym(StringRef HWDiv) {
24 return StringSwitch<StringRef>(HWDiv)
25 .Case(S: "thumb,arm", Value: "arm,thumb")
26 .Default(Value: HWDiv);
27}
28
29// Allows partial match, ex. "v7a" matches "armv7a".
30ARM::ArchKind ARM::parseArch(StringRef Arch) {
31 Arch = getCanonicalArchName(Arch);
32 StringRef Syn = getArchSynonym(Arch);
33 for (const auto &A : ARMArchNames) {
34 if (A.Name.ends_with(Suffix: Syn))
35 return A.ID;
36 }
37 return ArchKind::INVALID;
38}
39
40// Version number (ex. v7 = 7).
41unsigned ARM::parseArchVersion(StringRef Arch) {
42 Arch = getCanonicalArchName(Arch);
43 switch (parseArch(Arch)) {
44 case ArchKind::ARMV4:
45 case ArchKind::ARMV4T:
46 return 4;
47 case ArchKind::ARMV5T:
48 case ArchKind::ARMV5TE:
49 case ArchKind::IWMMXT:
50 case ArchKind::IWMMXT2:
51 case ArchKind::XSCALE:
52 case ArchKind::ARMV5TEJ:
53 return 5;
54 case ArchKind::ARMV6:
55 case ArchKind::ARMV6K:
56 case ArchKind::ARMV6T2:
57 case ArchKind::ARMV6KZ:
58 case ArchKind::ARMV6M:
59 return 6;
60 case ArchKind::ARMV7A:
61 case ArchKind::ARMV7VE:
62 case ArchKind::ARMV7R:
63 case ArchKind::ARMV7M:
64 case ArchKind::ARMV7S:
65 case ArchKind::ARMV7EM:
66 case ArchKind::ARMV7K:
67 return 7;
68 case ArchKind::ARMV8A:
69 case ArchKind::ARMV8_1A:
70 case ArchKind::ARMV8_2A:
71 case ArchKind::ARMV8_3A:
72 case ArchKind::ARMV8_4A:
73 case ArchKind::ARMV8_5A:
74 case ArchKind::ARMV8_6A:
75 case ArchKind::ARMV8_7A:
76 case ArchKind::ARMV8_8A:
77 case ArchKind::ARMV8_9A:
78 case ArchKind::ARMV8R:
79 case ArchKind::ARMV8MBaseline:
80 case ArchKind::ARMV8MMainline:
81 case ArchKind::ARMV8_1MMainline:
82 return 8;
83 case ArchKind::ARMV9A:
84 case ArchKind::ARMV9_1A:
85 case ArchKind::ARMV9_2A:
86 case ArchKind::ARMV9_3A:
87 case ArchKind::ARMV9_4A:
88 case ArchKind::ARMV9_5A:
89 case ArchKind::ARMV9_6A:
90 case ArchKind::ARMV9_7A:
91 return 9;
92 case ArchKind::INVALID:
93 return 0;
94 }
95 llvm_unreachable("Unhandled architecture");
96}
97
98static ARM::ProfileKind getProfileKind(ARM::ArchKind AK) {
99 switch (AK) {
100 case ARM::ArchKind::ARMV6M:
101 case ARM::ArchKind::ARMV7M:
102 case ARM::ArchKind::ARMV7EM:
103 case ARM::ArchKind::ARMV8MMainline:
104 case ARM::ArchKind::ARMV8MBaseline:
105 case ARM::ArchKind::ARMV8_1MMainline:
106 return ARM::ProfileKind::M;
107 case ARM::ArchKind::ARMV7R:
108 case ARM::ArchKind::ARMV8R:
109 return ARM::ProfileKind::R;
110 case ARM::ArchKind::ARMV7A:
111 case ARM::ArchKind::ARMV7VE:
112 case ARM::ArchKind::ARMV7K:
113 case ARM::ArchKind::ARMV8A:
114 case ARM::ArchKind::ARMV8_1A:
115 case ARM::ArchKind::ARMV8_2A:
116 case ARM::ArchKind::ARMV8_3A:
117 case ARM::ArchKind::ARMV8_4A:
118 case ARM::ArchKind::ARMV8_5A:
119 case ARM::ArchKind::ARMV8_6A:
120 case ARM::ArchKind::ARMV8_7A:
121 case ARM::ArchKind::ARMV8_8A:
122 case ARM::ArchKind::ARMV8_9A:
123 case ARM::ArchKind::ARMV9A:
124 case ARM::ArchKind::ARMV9_1A:
125 case ARM::ArchKind::ARMV9_2A:
126 case ARM::ArchKind::ARMV9_3A:
127 case ARM::ArchKind::ARMV9_4A:
128 case ARM::ArchKind::ARMV9_5A:
129 case ARM::ArchKind::ARMV9_6A:
130 case ARM::ArchKind::ARMV9_7A:
131 return ARM::ProfileKind::A;
132 case ARM::ArchKind::ARMV4:
133 case ARM::ArchKind::ARMV4T:
134 case ARM::ArchKind::ARMV5T:
135 case ARM::ArchKind::ARMV5TE:
136 case ARM::ArchKind::ARMV5TEJ:
137 case ARM::ArchKind::ARMV6:
138 case ARM::ArchKind::ARMV6K:
139 case ARM::ArchKind::ARMV6T2:
140 case ARM::ArchKind::ARMV6KZ:
141 case ARM::ArchKind::ARMV7S:
142 case ARM::ArchKind::IWMMXT:
143 case ARM::ArchKind::IWMMXT2:
144 case ARM::ArchKind::XSCALE:
145 case ARM::ArchKind::INVALID:
146 return ARM::ProfileKind::INVALID;
147 }
148 llvm_unreachable("Unhandled architecture");
149}
150
151// Profile A/R/M
152ARM::ProfileKind ARM::parseArchProfile(StringRef Arch) {
153 Arch = getCanonicalArchName(Arch);
154 return getProfileKind(AK: parseArch(Arch));
155}
156
157bool ARM::getFPUFeatures(ARM::FPUKind FPUKind,
158 std::vector<StringRef> &Features) {
159
160 if (FPUKind >= FK_LAST || FPUKind == FK_INVALID)
161 return false;
162
163 static const struct FPUFeatureNameInfo {
164 const char *PlusName, *MinusName;
165 FPUVersion MinVersion;
166 FPURestriction MaxRestriction;
167 } FPUFeatureInfoList[] = {
168 // We have to specify the + and - versions of the name in full so
169 // that we can return them as static StringRefs.
170 //
171 // Also, the SubtargetFeatures ending in just "sp" are listed here
172 // under FPURestriction::None, which is the only FPURestriction in
173 // which they would be valid (since FPURestriction::SP doesn't
174 // exist).
175 {.PlusName: "+vfp2", .MinusName: "-vfp2", .MinVersion: FPUVersion::VFPV2, .MaxRestriction: FPURestriction::D16},
176 {.PlusName: "+vfp2sp", .MinusName: "-vfp2sp", .MinVersion: FPUVersion::VFPV2, .MaxRestriction: FPURestriction::SP_D16},
177 {.PlusName: "+vfp3", .MinusName: "-vfp3", .MinVersion: FPUVersion::VFPV3, .MaxRestriction: FPURestriction::None},
178 {.PlusName: "+vfp3d16", .MinusName: "-vfp3d16", .MinVersion: FPUVersion::VFPV3, .MaxRestriction: FPURestriction::D16},
179 {.PlusName: "+vfp3d16sp", .MinusName: "-vfp3d16sp", .MinVersion: FPUVersion::VFPV3, .MaxRestriction: FPURestriction::SP_D16},
180 {.PlusName: "+vfp3sp", .MinusName: "-vfp3sp", .MinVersion: FPUVersion::VFPV3, .MaxRestriction: FPURestriction::None},
181 {.PlusName: "+fp16", .MinusName: "-fp16", .MinVersion: FPUVersion::VFPV3_FP16, .MaxRestriction: FPURestriction::SP_D16},
182 {.PlusName: "+vfp4", .MinusName: "-vfp4", .MinVersion: FPUVersion::VFPV4, .MaxRestriction: FPURestriction::None},
183 {.PlusName: "+vfp4d16", .MinusName: "-vfp4d16", .MinVersion: FPUVersion::VFPV4, .MaxRestriction: FPURestriction::D16},
184 {.PlusName: "+vfp4d16sp", .MinusName: "-vfp4d16sp", .MinVersion: FPUVersion::VFPV4, .MaxRestriction: FPURestriction::SP_D16},
185 {.PlusName: "+vfp4sp", .MinusName: "-vfp4sp", .MinVersion: FPUVersion::VFPV4, .MaxRestriction: FPURestriction::None},
186 {.PlusName: "+fp-armv8", .MinusName: "-fp-armv8", .MinVersion: FPUVersion::VFPV5, .MaxRestriction: FPURestriction::None},
187 {.PlusName: "+fp-armv8d16", .MinusName: "-fp-armv8d16", .MinVersion: FPUVersion::VFPV5, .MaxRestriction: FPURestriction::D16},
188 {.PlusName: "+fp-armv8d16sp", .MinusName: "-fp-armv8d16sp", .MinVersion: FPUVersion::VFPV5, .MaxRestriction: FPURestriction::SP_D16},
189 {.PlusName: "+fp-armv8sp", .MinusName: "-fp-armv8sp", .MinVersion: FPUVersion::VFPV5, .MaxRestriction: FPURestriction::None},
190 {.PlusName: "+fullfp16", .MinusName: "-fullfp16", .MinVersion: FPUVersion::VFPV5_FULLFP16, .MaxRestriction: FPURestriction::SP_D16},
191 {.PlusName: "+fp64", .MinusName: "-fp64", .MinVersion: FPUVersion::VFPV2, .MaxRestriction: FPURestriction::D16},
192 {.PlusName: "+d32", .MinusName: "-d32", .MinVersion: FPUVersion::VFPV3, .MaxRestriction: FPURestriction::None},
193 };
194
195 for (const auto &Info: FPUFeatureInfoList) {
196 if (FPUNames[FPUKind].FPUVer >= Info.MinVersion &&
197 FPUNames[FPUKind].Restriction <= Info.MaxRestriction)
198 Features.push_back(x: Info.PlusName);
199 else
200 Features.push_back(x: Info.MinusName);
201 }
202
203 static const struct NeonFeatureNameInfo {
204 const char *PlusName, *MinusName;
205 NeonSupportLevel MinSupportLevel;
206 } NeonFeatureInfoList[] = {
207 {.PlusName: "+neon", .MinusName: "-neon", .MinSupportLevel: NeonSupportLevel::Neon},
208 {.PlusName: "+sha2", .MinusName: "-sha2", .MinSupportLevel: NeonSupportLevel::Crypto},
209 {.PlusName: "+aes", .MinusName: "-aes", .MinSupportLevel: NeonSupportLevel::Crypto},
210 };
211
212 for (const auto &Info: NeonFeatureInfoList) {
213 if (FPUNames[FPUKind].NeonSupport >= Info.MinSupportLevel)
214 Features.push_back(x: Info.PlusName);
215 else
216 Features.push_back(x: Info.MinusName);
217 }
218
219 return true;
220}
221
222ARM::FPUKind ARM::parseFPU(StringRef FPU) {
223 StringRef Syn = getFPUSynonym(FPU);
224 for (const auto &F : FPUNames) {
225 if (Syn == F.Name)
226 return F.ID;
227 }
228 return FK_INVALID;
229}
230
231ARM::NeonSupportLevel ARM::getFPUNeonSupportLevel(ARM::FPUKind FPUKind) {
232 if (FPUKind >= FK_LAST)
233 return NeonSupportLevel::None;
234 return FPUNames[FPUKind].NeonSupport;
235}
236
237StringRef ARM::getFPUSynonym(StringRef FPU) {
238 return StringSwitch<StringRef>(FPU)
239 .Cases(CaseStrings: {"fpa", "fpe2", "fpe3", "maverick"}, Value: "invalid") // Unsupported
240 .Case(S: "vfp2", Value: "vfpv2")
241 .Case(S: "vfp3", Value: "vfpv3")
242 .Case(S: "vfp4", Value: "vfpv4")
243 .Case(S: "vfp3-d16", Value: "vfpv3-d16")
244 .Case(S: "vfp4-d16", Value: "vfpv4-d16")
245 .Cases(CaseStrings: {"fp4-sp-d16", "vfpv4-sp-d16"}, Value: "fpv4-sp-d16")
246 .Cases(CaseStrings: {"fp4-dp-d16", "fpv4-dp-d16"}, Value: "vfpv4-d16")
247 .Case(S: "fp5-sp-d16", Value: "fpv5-sp-d16")
248 .Cases(CaseStrings: {"fp5-dp-d16", "fpv5-dp-d16"}, Value: "fpv5-d16")
249 // FIXME: Clang uses it, but it's bogus, since neon defaults to vfpv3.
250 .Case(S: "neon-vfpv3", Value: "neon")
251 .Default(Value: FPU);
252}
253
254StringRef ARM::getFPUName(ARM::FPUKind FPUKind) {
255 if (FPUKind >= FK_LAST)
256 return StringRef();
257 return FPUNames[FPUKind].Name;
258}
259
260ARM::FPUVersion ARM::getFPUVersion(ARM::FPUKind FPUKind) {
261 if (FPUKind >= FK_LAST)
262 return FPUVersion::NONE;
263 return FPUNames[FPUKind].FPUVer;
264}
265
266ARM::FPURestriction ARM::getFPURestriction(ARM::FPUKind FPUKind) {
267 if (FPUKind >= FK_LAST)
268 return FPURestriction::None;
269 return FPUNames[FPUKind].Restriction;
270}
271
272ARM::FPUKind ARM::getDefaultFPU(StringRef CPU, ARM::ArchKind AK) {
273 if (CPU == "generic")
274 return ARM::ARMArchNames[static_cast<unsigned>(AK)].DefaultFPU;
275
276 return StringSwitch<ARM::FPUKind>(CPU)
277#define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \
278 .Case(NAME, DEFAULT_FPU)
279#include "llvm/TargetParser/ARMTargetParser.def"
280 .Default(Value: ARM::FK_INVALID);
281}
282
283uint64_t ARM::getDefaultExtensions(StringRef CPU, ARM::ArchKind AK) {
284 if (CPU == "generic")
285 return ARM::ARMArchNames[static_cast<unsigned>(AK)].ArchBaseExtensions;
286
287 return StringSwitch<uint64_t>(CPU)
288#define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \
289 .Case(NAME, \
290 ARMArchNames[static_cast<unsigned>(ArchKind::ID)].ArchBaseExtensions | \
291 DEFAULT_EXT)
292#include "llvm/TargetParser/ARMTargetParser.def"
293 .Default(Value: ARM::AEK_INVALID);
294}
295
296bool ARM::getHWDivFeatures(uint64_t HWDivKind,
297 std::vector<StringRef> &Features) {
298
299 if (HWDivKind == AEK_INVALID)
300 return false;
301
302 if (HWDivKind & AEK_HWDIVARM)
303 Features.push_back(x: "+hwdiv-arm");
304 else
305 Features.push_back(x: "-hwdiv-arm");
306
307 if (HWDivKind & AEK_HWDIVTHUMB)
308 Features.push_back(x: "+hwdiv");
309 else
310 Features.push_back(x: "-hwdiv");
311
312 return true;
313}
314
315bool ARM::getExtensionFeatures(uint64_t Extensions,
316 std::vector<StringRef> &Features) {
317
318 if (Extensions == AEK_INVALID)
319 return false;
320
321 for (const auto &AE : ARCHExtNames) {
322 if ((Extensions & AE.ID) == AE.ID && !AE.Feature.empty())
323 Features.push_back(x: AE.Feature);
324 else if (!AE.NegFeature.empty())
325 Features.push_back(x: AE.NegFeature);
326 }
327
328 return getHWDivFeatures(HWDivKind: Extensions, Features);
329}
330
331StringRef ARM::getArchName(ARM::ArchKind AK) {
332 return ARMArchNames[static_cast<unsigned>(AK)].Name;
333}
334
335StringRef ARM::getCPUAttr(ARM::ArchKind AK) {
336 return ARMArchNames[static_cast<unsigned>(AK)].CPUAttr;
337}
338
339StringRef ARM::getSubArch(ARM::ArchKind AK) {
340 return ARMArchNames[static_cast<unsigned>(AK)].getSubArch();
341}
342
343unsigned ARM::getArchAttr(ARM::ArchKind AK) {
344 return ARMArchNames[static_cast<unsigned>(AK)].ArchAttr;
345}
346
347StringRef ARM::getArchExtName(uint64_t ArchExtKind) {
348 for (const auto &AE : ARCHExtNames) {
349 if (ArchExtKind == AE.ID)
350 return AE.Name;
351 }
352 return StringRef();
353}
354
355static bool stripNegationPrefix(StringRef &Name) {
356 return Name.consume_front(Prefix: "no");
357}
358
359StringRef ARM::getArchExtFeature(StringRef ArchExt) {
360 bool Negated = stripNegationPrefix(Name&: ArchExt);
361 for (const auto &AE : ARCHExtNames) {
362 if (!AE.Feature.empty() && ArchExt == AE.Name)
363 return StringRef(Negated ? AE.NegFeature : AE.Feature);
364 }
365
366 return StringRef();
367}
368
369static ARM::FPUKind findDoublePrecisionFPU(ARM::FPUKind InputFPUKind) {
370 if (InputFPUKind == ARM::FK_INVALID || InputFPUKind == ARM::FK_NONE)
371 return ARM::FK_INVALID;
372
373 const ARM::FPUName &InputFPU = ARM::FPUNames[InputFPUKind];
374
375 // If the input FPU already supports double-precision, then there
376 // isn't any different FPU we can return here.
377 if (ARM::isDoublePrecision(restriction: InputFPU.Restriction))
378 return InputFPUKind;
379
380 // Otherwise, look for an FPU entry with all the same fields, except
381 // that it supports double precision.
382 for (const ARM::FPUName &CandidateFPU : ARM::FPUNames) {
383 if (CandidateFPU.FPUVer == InputFPU.FPUVer &&
384 CandidateFPU.NeonSupport == InputFPU.NeonSupport &&
385 ARM::has32Regs(restriction: CandidateFPU.Restriction) ==
386 ARM::has32Regs(restriction: InputFPU.Restriction) &&
387 ARM::isDoublePrecision(restriction: CandidateFPU.Restriction)) {
388 return CandidateFPU.ID;
389 }
390 }
391
392 // nothing found
393 return ARM::FK_INVALID;
394}
395
396static ARM::FPUKind findSinglePrecisionFPU(ARM::FPUKind InputFPUKind) {
397 if (InputFPUKind == ARM::FK_INVALID || InputFPUKind == ARM::FK_NONE)
398 return ARM::FK_INVALID;
399
400 const ARM::FPUName &InputFPU = ARM::FPUNames[InputFPUKind];
401
402 // If the input FPU already is single-precision only, then there
403 // isn't any different FPU we can return here.
404 if (!ARM::isDoublePrecision(restriction: InputFPU.Restriction))
405 return InputFPUKind;
406
407 // Otherwise, look for an FPU entry that has the same FPUVer
408 // and is not Double Precision. We want to allow for changing of
409 // NEON Support and Restrictions so CPU's such as Cortex-R52 can
410 // select between SP Only and Full DP modes.
411 for (const ARM::FPUName &CandidateFPU : ARM::FPUNames) {
412 if (CandidateFPU.FPUVer == InputFPU.FPUVer &&
413 !ARM::isDoublePrecision(restriction: CandidateFPU.Restriction)) {
414 return CandidateFPU.ID;
415 }
416 }
417
418 // nothing found
419 return ARM::FK_INVALID;
420}
421
422bool ARM::appendArchExtFeatures(StringRef CPU, ARM::ArchKind AK,
423 StringRef ArchExt,
424 std::vector<StringRef> &Features,
425 ARM::FPUKind &ArgFPUKind) {
426
427 size_t StartingNumFeatures = Features.size();
428 const bool Negated = stripNegationPrefix(Name&: ArchExt);
429 uint64_t ID = parseArchExt(ArchExt);
430
431 if (ID == AEK_INVALID)
432 return false;
433
434 for (const auto &AE : ARCHExtNames) {
435 if (Negated) {
436 if ((AE.ID & ID) == ID && !AE.NegFeature.empty())
437 Features.push_back(x: AE.NegFeature);
438 } else {
439 if ((AE.ID & ID) == AE.ID && !AE.Feature.empty())
440 Features.push_back(x: AE.Feature);
441 }
442 }
443
444 if (CPU == "")
445 CPU = "generic";
446
447 if (ArchExt == "fp" || ArchExt == "fp.dp") {
448 const ARM::FPUKind DefaultFPU = getDefaultFPU(CPU, AK);
449 ARM::FPUKind FPUKind;
450 if (ArchExt == "fp.dp") {
451 const bool IsDP = ArgFPUKind != ARM::FK_INVALID &&
452 ArgFPUKind != ARM::FK_NONE &&
453 isDoublePrecision(restriction: getFPURestriction(FPUKind: ArgFPUKind));
454 if (Negated) {
455 /* If there is no FPU selected yet, we still need to set ArgFPUKind, as
456 * leaving it as FK_INVALID, would cause default FPU to be selected
457 * later and that could be double precision one. */
458 if (ArgFPUKind != ARM::FK_INVALID && !IsDP)
459 return true;
460 FPUKind = findSinglePrecisionFPU(InputFPUKind: DefaultFPU);
461 if (FPUKind == ARM::FK_INVALID)
462 FPUKind = ARM::FK_NONE;
463 } else {
464 if (IsDP)
465 return true;
466 FPUKind = findDoublePrecisionFPU(InputFPUKind: DefaultFPU);
467 if (FPUKind == ARM::FK_INVALID)
468 return false;
469 }
470 } else if (Negated) {
471 FPUKind = ARM::FK_NONE;
472 } else {
473 FPUKind = DefaultFPU;
474 }
475 ArgFPUKind = FPUKind;
476 return true;
477 }
478 return StartingNumFeatures != Features.size();
479}
480
481ARM::ArchKind ARM::convertV9toV8(ARM::ArchKind AK) {
482 if (getProfileKind(AK) != ProfileKind::A)
483 return ARM::ArchKind::INVALID;
484 if (AK < ARM::ArchKind::ARMV9A || AK > ARM::ArchKind::ARMV9_3A)
485 return ARM::ArchKind::INVALID;
486 unsigned AK_v8 = static_cast<unsigned>(ARM::ArchKind::ARMV8_5A);
487 AK_v8 += static_cast<unsigned>(AK) -
488 static_cast<unsigned>(ARM::ArchKind::ARMV9A);
489 return static_cast<ARM::ArchKind>(AK_v8);
490}
491
492StringRef ARM::getDefaultCPU(StringRef Arch) {
493 ArchKind AK = parseArch(Arch);
494 if (AK == ArchKind::INVALID)
495 return StringRef();
496
497 // Look for multiple AKs to find the default for pair AK+Name.
498 for (const auto &CPU : CPUNames) {
499 if (CPU.ArchID == AK && CPU.Default)
500 return CPU.Name;
501 }
502
503 // If we can't find a default then target the architecture instead
504 return "generic";
505}
506
507uint64_t ARM::parseHWDiv(StringRef HWDiv) {
508 StringRef Syn = getHWDivSynonym(HWDiv);
509 for (const auto &D : HWDivNames) {
510 if (Syn == D.Name)
511 return D.ID;
512 }
513 return AEK_INVALID;
514}
515
516uint64_t ARM::parseArchExt(StringRef ArchExt) {
517 for (const auto &A : ARCHExtNames) {
518 if (ArchExt == A.Name)
519 return A.ID;
520 }
521 return AEK_INVALID;
522}
523
524ARM::ArchKind ARM::parseCPUArch(StringRef CPU) {
525 for (const auto &C : CPUNames) {
526 if (CPU == C.Name)
527 return C.ArchID;
528 }
529 return ArchKind::INVALID;
530}
531
532void ARM::fillValidCPUArchList(SmallVectorImpl<StringRef> &Values) {
533 for (const auto &Arch : CPUNames) {
534 if (Arch.ArchID != ArchKind::INVALID)
535 Values.push_back(Elt: Arch.Name);
536 }
537}
538
539StringRef ARM::computeDefaultTargetABI(const Triple &TT) {
540 StringRef ArchName = TT.getArchName();
541
542 if (TT.isOSBinFormatMachO()) {
543 if (TT.getEnvironment() == Triple::EABI ||
544 TT.getOS() == Triple::UnknownOS ||
545 parseArchProfile(Arch: ArchName) == ProfileKind::M)
546 return "aapcs";
547 if (TT.isWatchABI())
548 return "aapcs16";
549 return "apcs-gnu";
550 } else if (TT.isOSWindows())
551 // FIXME: this is invalid for WindowsCE.
552 return "aapcs";
553
554 // Select the default based on the platform.
555 switch (TT.getEnvironment()) {
556 case Triple::Android:
557 case Triple::GNUEABI:
558 case Triple::GNUEABIT64:
559 case Triple::GNUEABIHF:
560 case Triple::GNUEABIHFT64:
561 case Triple::MuslEABI:
562 case Triple::MuslEABIHF:
563 case Triple::OpenHOS:
564 return "aapcs-linux";
565 case Triple::EABIHF:
566 case Triple::EABI:
567 return "aapcs";
568 default:
569 if (TT.isOSNetBSD())
570 return "apcs-gnu";
571 if (TT.isOSFreeBSD() || TT.isOSFuchsia() || TT.isOSOpenBSD() ||
572 TT.isOSHaiku() || TT.isOHOSFamily())
573 return "aapcs-linux";
574 return "aapcs";
575 }
576}
577
578ARM::ARMABI ARM::computeTargetABI(const Triple &TT, StringRef ABIName) {
579 if (ABIName.empty())
580 ABIName = ARM::computeDefaultTargetABI(TT);
581
582 if (ABIName == "aapcs16")
583 return ARM_ABI_AAPCS16;
584
585 if (ABIName.starts_with(Prefix: "aapcs"))
586 return ARM_ABI_AAPCS;
587
588 if (ABIName.starts_with(Prefix: "apcs"))
589 return ARM_ABI_APCS;
590
591 return ARM_ABI_UNKNOWN;
592}
593
594StringRef ARM::getARMCPUForArch(const llvm::Triple &Triple, StringRef MArch) {
595 if (MArch.empty())
596 MArch = Triple.getArchName();
597 MArch = llvm::ARM::getCanonicalArchName(Arch: MArch);
598
599 // Some defaults are forced.
600 switch (Triple.getOS()) {
601 case llvm::Triple::FreeBSD:
602 case llvm::Triple::NetBSD:
603 case llvm::Triple::OpenBSD:
604 case llvm::Triple::Haiku:
605 if (!MArch.empty() && MArch == "v6")
606 return "arm1176jzf-s";
607 if (!MArch.empty() && MArch == "v7")
608 return "cortex-a8";
609 break;
610 case llvm::Triple::Win32:
611 // FIXME: this is invalid for WindowsCE
612 if (llvm::ARM::parseArchVersion(Arch: MArch) <= 7)
613 return "cortex-a9";
614 break;
615 case llvm::Triple::IOS:
616 case llvm::Triple::MacOSX:
617 case llvm::Triple::TvOS:
618 case llvm::Triple::WatchOS:
619 case llvm::Triple::DriverKit:
620 case llvm::Triple::XROS:
621 if (MArch == "v7k")
622 return "cortex-a7";
623 break;
624 default:
625 break;
626 }
627
628 if (MArch.empty())
629 return StringRef();
630
631 StringRef CPU = llvm::ARM::getDefaultCPU(Arch: MArch);
632 if (!CPU.empty() && CPU != "invalid")
633 return CPU;
634
635 // If no specific architecture version is requested, return the minimum CPU
636 // required by the OS and environment.
637 switch (Triple.getOS()) {
638 case llvm::Triple::Haiku:
639 return "arm1176jzf-s";
640 case llvm::Triple::NetBSD:
641 switch (Triple.getEnvironment()) {
642 case llvm::Triple::EABI:
643 case llvm::Triple::EABIHF:
644 case llvm::Triple::GNUEABI:
645 case llvm::Triple::GNUEABIHF:
646 return "arm926ej-s";
647 default:
648 return "strongarm";
649 }
650 case llvm::Triple::OpenBSD:
651 return "cortex-a8";
652 case llvm::Triple::Fuchsia:
653 return "cortex-a53";
654 default:
655 switch (Triple.getEnvironment()) {
656 case llvm::Triple::EABIHF:
657 case llvm::Triple::GNUEABIHF:
658 case llvm::Triple::GNUEABIHFT64:
659 case llvm::Triple::MuslEABIHF:
660 return "arm1176jzf-s";
661 default:
662 return "arm7tdmi";
663 }
664 }
665
666 llvm_unreachable("invalid arch name");
667}
668
669void ARM::PrintSupportedExtensions(StringMap<StringRef> DescMap) {
670 outs() << "All available -march extensions for ARM\n\n"
671 << " " << left_justify(Str: "Name", Width: 20)
672 << (DescMap.empty() ? "\n" : "Description\n");
673 for (const auto &Ext : ARCHExtNames) {
674 // Extensions without a feature cannot be used with -march.
675 if (!Ext.Feature.empty()) {
676 std::string Description = DescMap[Ext.Name].str();
677 // With SIMD, this links to the NEON feature, so the description should be
678 // taken from here, as SIMD does not exist in TableGen.
679 if (Ext.Name == "simd")
680 Description = DescMap["neon"].str();
681 outs() << " "
682 << format(Fmt: Description.empty() ? "%s\n" : "%-20s%s\n",
683 Vals: Ext.Name.str().c_str(), Vals: Description.c_str());
684 }
685 }
686}
687