1//===-- ARMTargetParser - Parser for ARM target features --------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements a target parser to recognise ARM hardware features
10// such as FPU/CPU/ARCH/extensions and specific support such as HWDIV.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/TargetParser/ARMTargetParser.h"
15#include "llvm/ADT/StringSwitch.h"
16#include "llvm/Support/Format.h"
17#include "llvm/Support/raw_ostream.h"
18#include "llvm/TargetParser/ARMTargetParserCommon.h"
19#include "llvm/TargetParser/Triple.h"
20
21using namespace llvm;
22
23static StringRef getHWDivSynonym(StringRef HWDiv) {
24 return StringSwitch<StringRef>(HWDiv)
25 .Case(S: "thumb,arm", Value: "arm,thumb")
26 .Default(Value: HWDiv);
27}
28
29// Allows partial match, ex. "v7a" matches "armv7a".
30ARM::ArchKind ARM::parseArch(StringRef Arch) {
31 Arch = getCanonicalArchName(Arch);
32 StringRef Syn = getArchSynonym(Arch);
33 for (const auto &A : ARMArchNames) {
34 if (A.Name.ends_with(Suffix: Syn))
35 return A.ID;
36 }
37 return ArchKind::INVALID;
38}
39
40// Version number (ex. v7 = 7).
41unsigned ARM::parseArchVersion(StringRef Arch) {
42 Arch = getCanonicalArchName(Arch);
43 switch (parseArch(Arch)) {
44 case ArchKind::ARMV4:
45 case ArchKind::ARMV4T:
46 return 4;
47 case ArchKind::ARMV5T:
48 case ArchKind::ARMV5TE:
49 case ArchKind::IWMMXT:
50 case ArchKind::IWMMXT2:
51 case ArchKind::XSCALE:
52 case ArchKind::ARMV5TEJ:
53 return 5;
54 case ArchKind::ARMV6:
55 case ArchKind::ARMV6K:
56 case ArchKind::ARMV6T2:
57 case ArchKind::ARMV6KZ:
58 case ArchKind::ARMV6M:
59 return 6;
60 case ArchKind::ARMV7A:
61 case ArchKind::ARMV7VE:
62 case ArchKind::ARMV7R:
63 case ArchKind::ARMV7M:
64 case ArchKind::ARMV7S:
65 case ArchKind::ARMV7EM:
66 case ArchKind::ARMV7K:
67 return 7;
68 case ArchKind::ARMV8A:
69 case ArchKind::ARMV8_1A:
70 case ArchKind::ARMV8_2A:
71 case ArchKind::ARMV8_3A:
72 case ArchKind::ARMV8_4A:
73 case ArchKind::ARMV8_5A:
74 case ArchKind::ARMV8_6A:
75 case ArchKind::ARMV8_7A:
76 case ArchKind::ARMV8_8A:
77 case ArchKind::ARMV8_9A:
78 case ArchKind::ARMV8R:
79 case ArchKind::ARMV8MBaseline:
80 case ArchKind::ARMV8MMainline:
81 case ArchKind::ARMV8_1MMainline:
82 return 8;
83 case ArchKind::ARMV9A:
84 case ArchKind::ARMV9_1A:
85 case ArchKind::ARMV9_2A:
86 case ArchKind::ARMV9_3A:
87 case ArchKind::ARMV9_4A:
88 case ArchKind::ARMV9_5A:
89 case ArchKind::ARMV9_6A:
90 case ArchKind::ARMV9_7A:
91 case ArchKind::ARMV9_8A:
92 return 9;
93 case ArchKind::INVALID:
94 return 0;
95 }
96 llvm_unreachable("Unhandled architecture");
97}
98
99static ARM::ProfileKind getProfileKind(ARM::ArchKind AK) {
100 switch (AK) {
101 case ARM::ArchKind::ARMV6M:
102 case ARM::ArchKind::ARMV7M:
103 case ARM::ArchKind::ARMV7EM:
104 case ARM::ArchKind::ARMV8MMainline:
105 case ARM::ArchKind::ARMV8MBaseline:
106 case ARM::ArchKind::ARMV8_1MMainline:
107 return ARM::ProfileKind::M;
108 case ARM::ArchKind::ARMV7R:
109 case ARM::ArchKind::ARMV8R:
110 return ARM::ProfileKind::R;
111 case ARM::ArchKind::ARMV7A:
112 case ARM::ArchKind::ARMV7VE:
113 case ARM::ArchKind::ARMV7K:
114 case ARM::ArchKind::ARMV8A:
115 case ARM::ArchKind::ARMV8_1A:
116 case ARM::ArchKind::ARMV8_2A:
117 case ARM::ArchKind::ARMV8_3A:
118 case ARM::ArchKind::ARMV8_4A:
119 case ARM::ArchKind::ARMV8_5A:
120 case ARM::ArchKind::ARMV8_6A:
121 case ARM::ArchKind::ARMV8_7A:
122 case ARM::ArchKind::ARMV8_8A:
123 case ARM::ArchKind::ARMV8_9A:
124 case ARM::ArchKind::ARMV9A:
125 case ARM::ArchKind::ARMV9_1A:
126 case ARM::ArchKind::ARMV9_2A:
127 case ARM::ArchKind::ARMV9_3A:
128 case ARM::ArchKind::ARMV9_4A:
129 case ARM::ArchKind::ARMV9_5A:
130 case ARM::ArchKind::ARMV9_6A:
131 case ARM::ArchKind::ARMV9_7A:
132 case ARM::ArchKind::ARMV9_8A:
133 return ARM::ProfileKind::A;
134 case ARM::ArchKind::ARMV4:
135 case ARM::ArchKind::ARMV4T:
136 case ARM::ArchKind::ARMV5T:
137 case ARM::ArchKind::ARMV5TE:
138 case ARM::ArchKind::ARMV5TEJ:
139 case ARM::ArchKind::ARMV6:
140 case ARM::ArchKind::ARMV6K:
141 case ARM::ArchKind::ARMV6T2:
142 case ARM::ArchKind::ARMV6KZ:
143 case ARM::ArchKind::ARMV7S:
144 case ARM::ArchKind::IWMMXT:
145 case ARM::ArchKind::IWMMXT2:
146 case ARM::ArchKind::XSCALE:
147 case ARM::ArchKind::INVALID:
148 return ARM::ProfileKind::INVALID;
149 }
150 llvm_unreachable("Unhandled architecture");
151}
152
153// Profile A/R/M
154ARM::ProfileKind ARM::parseArchProfile(StringRef Arch) {
155 Arch = getCanonicalArchName(Arch);
156 return getProfileKind(AK: parseArch(Arch));
157}
158
159bool ARM::getFPUFeatures(ARM::FPUKind FPUKind,
160 std::vector<StringRef> &Features) {
161
162 if (FPUKind >= FK_LAST || FPUKind == FK_INVALID)
163 return false;
164
165 static const struct FPUFeatureNameInfo {
166 const char *PlusName, *MinusName;
167 FPUVersion MinVersion;
168 FPURestriction MaxRestriction;
169 } FPUFeatureInfoList[] = {
170 // We have to specify the + and - versions of the name in full so
171 // that we can return them as static StringRefs.
172 //
173 // Also, the SubtargetFeatures ending in just "sp" are listed here
174 // under FPURestriction::None, which is the only FPURestriction in
175 // which they would be valid (since FPURestriction::SP doesn't
176 // exist).
177 {.PlusName: "+vfp2", .MinusName: "-vfp2", .MinVersion: FPUVersion::VFPV2, .MaxRestriction: FPURestriction::D16},
178 {.PlusName: "+vfp2sp", .MinusName: "-vfp2sp", .MinVersion: FPUVersion::VFPV2, .MaxRestriction: FPURestriction::SP_D16},
179 {.PlusName: "+vfp3", .MinusName: "-vfp3", .MinVersion: FPUVersion::VFPV3, .MaxRestriction: FPURestriction::None},
180 {.PlusName: "+vfp3d16", .MinusName: "-vfp3d16", .MinVersion: FPUVersion::VFPV3, .MaxRestriction: FPURestriction::D16},
181 {.PlusName: "+vfp3d16sp", .MinusName: "-vfp3d16sp", .MinVersion: FPUVersion::VFPV3, .MaxRestriction: FPURestriction::SP_D16},
182 {.PlusName: "+vfp3sp", .MinusName: "-vfp3sp", .MinVersion: FPUVersion::VFPV3, .MaxRestriction: FPURestriction::None},
183 {.PlusName: "+fp16", .MinusName: "-fp16", .MinVersion: FPUVersion::VFPV3_FP16, .MaxRestriction: FPURestriction::SP_D16},
184 {.PlusName: "+vfp4", .MinusName: "-vfp4", .MinVersion: FPUVersion::VFPV4, .MaxRestriction: FPURestriction::None},
185 {.PlusName: "+vfp4d16", .MinusName: "-vfp4d16", .MinVersion: FPUVersion::VFPV4, .MaxRestriction: FPURestriction::D16},
186 {.PlusName: "+vfp4d16sp", .MinusName: "-vfp4d16sp", .MinVersion: FPUVersion::VFPV4, .MaxRestriction: FPURestriction::SP_D16},
187 {.PlusName: "+vfp4sp", .MinusName: "-vfp4sp", .MinVersion: FPUVersion::VFPV4, .MaxRestriction: FPURestriction::None},
188 {.PlusName: "+fp-armv8", .MinusName: "-fp-armv8", .MinVersion: FPUVersion::VFPV5, .MaxRestriction: FPURestriction::None},
189 {.PlusName: "+fp-armv8d16", .MinusName: "-fp-armv8d16", .MinVersion: FPUVersion::VFPV5, .MaxRestriction: FPURestriction::D16},
190 {.PlusName: "+fp-armv8d16sp", .MinusName: "-fp-armv8d16sp", .MinVersion: FPUVersion::VFPV5, .MaxRestriction: FPURestriction::SP_D16},
191 {.PlusName: "+fp-armv8sp", .MinusName: "-fp-armv8sp", .MinVersion: FPUVersion::VFPV5, .MaxRestriction: FPURestriction::None},
192 {.PlusName: "+fullfp16", .MinusName: "-fullfp16", .MinVersion: FPUVersion::VFPV5_FULLFP16, .MaxRestriction: FPURestriction::SP_D16},
193 {.PlusName: "+fp64", .MinusName: "-fp64", .MinVersion: FPUVersion::VFPV2, .MaxRestriction: FPURestriction::D16},
194 {.PlusName: "+d32", .MinusName: "-d32", .MinVersion: FPUVersion::VFPV3, .MaxRestriction: FPURestriction::None},
195 };
196
197 for (const auto &Info: FPUFeatureInfoList) {
198 if (FPUNames[FPUKind].FPUVer >= Info.MinVersion &&
199 FPUNames[FPUKind].Restriction <= Info.MaxRestriction)
200 Features.push_back(x: Info.PlusName);
201 else
202 Features.push_back(x: Info.MinusName);
203 }
204
205 static const struct NeonFeatureNameInfo {
206 const char *PlusName, *MinusName;
207 NeonSupportLevel MinSupportLevel;
208 } NeonFeatureInfoList[] = {
209 {.PlusName: "+neon", .MinusName: "-neon", .MinSupportLevel: NeonSupportLevel::Neon},
210 {.PlusName: "+sha2", .MinusName: "-sha2", .MinSupportLevel: NeonSupportLevel::Crypto},
211 {.PlusName: "+aes", .MinusName: "-aes", .MinSupportLevel: NeonSupportLevel::Crypto},
212 };
213
214 for (const auto &Info: NeonFeatureInfoList) {
215 if (FPUNames[FPUKind].NeonSupport >= Info.MinSupportLevel)
216 Features.push_back(x: Info.PlusName);
217 else
218 Features.push_back(x: Info.MinusName);
219 }
220
221 return true;
222}
223
224ARM::FPUKind ARM::parseFPU(StringRef FPU) {
225 StringRef Syn = getFPUSynonym(FPU);
226 for (const auto &F : FPUNames) {
227 if (Syn == F.Name)
228 return F.ID;
229 }
230 return FK_INVALID;
231}
232
233ARM::NeonSupportLevel ARM::getFPUNeonSupportLevel(ARM::FPUKind FPUKind) {
234 if (FPUKind >= FK_LAST)
235 return NeonSupportLevel::None;
236 return FPUNames[FPUKind].NeonSupport;
237}
238
239StringRef ARM::getFPUSynonym(StringRef FPU) {
240 return StringSwitch<StringRef>(FPU)
241 .Cases(CaseStrings: {"fpa", "fpe2", "fpe3", "maverick"}, Value: "invalid") // Unsupported
242 .Case(S: "vfp2", Value: "vfpv2")
243 .Case(S: "vfp3", Value: "vfpv3")
244 .Case(S: "vfp4", Value: "vfpv4")
245 .Case(S: "vfp3-d16", Value: "vfpv3-d16")
246 .Case(S: "vfp4-d16", Value: "vfpv4-d16")
247 .Cases(CaseStrings: {"fp4-sp-d16", "vfpv4-sp-d16"}, Value: "fpv4-sp-d16")
248 .Cases(CaseStrings: {"fp4-dp-d16", "fpv4-dp-d16"}, Value: "vfpv4-d16")
249 .Case(S: "fp5-sp-d16", Value: "fpv5-sp-d16")
250 .Cases(CaseStrings: {"fp5-dp-d16", "fpv5-dp-d16"}, Value: "fpv5-d16")
251 // FIXME: Clang uses it, but it's bogus, since neon defaults to vfpv3.
252 .Case(S: "neon-vfpv3", Value: "neon")
253 .Default(Value: FPU);
254}
255
256StringRef ARM::getFPUName(ARM::FPUKind FPUKind) {
257 if (FPUKind >= FK_LAST)
258 return StringRef();
259 return FPUNames[FPUKind].Name;
260}
261
262ARM::FPUVersion ARM::getFPUVersion(ARM::FPUKind FPUKind) {
263 if (FPUKind >= FK_LAST)
264 return FPUVersion::NONE;
265 return FPUNames[FPUKind].FPUVer;
266}
267
268ARM::FPURestriction ARM::getFPURestriction(ARM::FPUKind FPUKind) {
269 if (FPUKind >= FK_LAST)
270 return FPURestriction::None;
271 return FPUNames[FPUKind].Restriction;
272}
273
274ARM::FPUKind ARM::getDefaultFPU(StringRef CPU, ARM::ArchKind AK) {
275 if (CPU == "generic")
276 return ARM::ARMArchNames[static_cast<unsigned>(AK)].DefaultFPU;
277
278 return StringSwitch<ARM::FPUKind>(CPU)
279#define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \
280 .Case(NAME, DEFAULT_FPU)
281#include "llvm/TargetParser/ARMTargetParser.def"
282 .Default(Value: ARM::FK_INVALID);
283}
284
285uint64_t ARM::getDefaultExtensions(StringRef CPU, ARM::ArchKind AK) {
286 if (CPU == "generic")
287 return ARM::ARMArchNames[static_cast<unsigned>(AK)].ArchBaseExtensions;
288
289 return StringSwitch<uint64_t>(CPU)
290#define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \
291 .Case(NAME, \
292 ARMArchNames[static_cast<unsigned>(ArchKind::ID)].ArchBaseExtensions | \
293 DEFAULT_EXT)
294#include "llvm/TargetParser/ARMTargetParser.def"
295 .Default(Value: ARM::AEK_INVALID);
296}
297
298bool ARM::getHWDivFeatures(uint64_t HWDivKind,
299 std::vector<StringRef> &Features) {
300
301 if (HWDivKind == AEK_INVALID)
302 return false;
303
304 if (HWDivKind & AEK_HWDIVARM)
305 Features.push_back(x: "+hwdiv-arm");
306 else
307 Features.push_back(x: "-hwdiv-arm");
308
309 if (HWDivKind & AEK_HWDIVTHUMB)
310 Features.push_back(x: "+hwdiv");
311 else
312 Features.push_back(x: "-hwdiv");
313
314 return true;
315}
316
317bool ARM::getExtensionFeatures(uint64_t Extensions,
318 std::vector<StringRef> &Features) {
319
320 if (Extensions == AEK_INVALID)
321 return false;
322
323 for (const auto &AE : ARCHExtNames) {
324 if ((Extensions & AE.ID) == AE.ID && !AE.Feature.empty())
325 Features.push_back(x: AE.Feature);
326 else if (!AE.NegFeature.empty())
327 Features.push_back(x: AE.NegFeature);
328 }
329
330 return getHWDivFeatures(HWDivKind: Extensions, Features);
331}
332
333StringRef ARM::getArchName(ARM::ArchKind AK) {
334 return ARMArchNames[static_cast<unsigned>(AK)].Name;
335}
336
337StringRef ARM::getCPUAttr(ARM::ArchKind AK) {
338 return ARMArchNames[static_cast<unsigned>(AK)].CPUAttr;
339}
340
341StringRef ARM::getSubArch(ARM::ArchKind AK) {
342 return ARMArchNames[static_cast<unsigned>(AK)].getSubArch();
343}
344
345unsigned ARM::getArchAttr(ARM::ArchKind AK) {
346 return ARMArchNames[static_cast<unsigned>(AK)].ArchAttr;
347}
348
349StringRef ARM::getArchExtName(uint64_t ArchExtKind) {
350 for (const auto &AE : ARCHExtNames) {
351 if (ArchExtKind == AE.ID)
352 return AE.Name;
353 }
354 return StringRef();
355}
356
357static bool stripNegationPrefix(StringRef &Name) {
358 return Name.consume_front(Prefix: "no");
359}
360
361StringRef ARM::getArchExtFeature(StringRef ArchExt) {
362 bool Negated = stripNegationPrefix(Name&: ArchExt);
363 for (const auto &AE : ARCHExtNames) {
364 if (!AE.Feature.empty() && ArchExt == AE.Name)
365 return StringRef(Negated ? AE.NegFeature : AE.Feature);
366 }
367
368 return StringRef();
369}
370
371static ARM::FPUKind findDoublePrecisionFPU(ARM::FPUKind InputFPUKind) {
372 if (InputFPUKind == ARM::FK_INVALID || InputFPUKind == ARM::FK_NONE)
373 return ARM::FK_INVALID;
374
375 const ARM::FPUName &InputFPU = ARM::FPUNames[InputFPUKind];
376
377 // If the input FPU already supports double-precision, then there
378 // isn't any different FPU we can return here.
379 if (ARM::isDoublePrecision(restriction: InputFPU.Restriction))
380 return InputFPUKind;
381
382 // Otherwise, look for an FPU entry with all the same fields, except
383 // that it supports double precision.
384 for (const ARM::FPUName &CandidateFPU : ARM::FPUNames) {
385 if (CandidateFPU.FPUVer == InputFPU.FPUVer &&
386 CandidateFPU.NeonSupport == InputFPU.NeonSupport &&
387 ARM::has32Regs(restriction: CandidateFPU.Restriction) ==
388 ARM::has32Regs(restriction: InputFPU.Restriction) &&
389 ARM::isDoublePrecision(restriction: CandidateFPU.Restriction)) {
390 return CandidateFPU.ID;
391 }
392 }
393
394 // nothing found
395 return ARM::FK_INVALID;
396}
397
398static ARM::FPUKind findSinglePrecisionFPU(ARM::FPUKind InputFPUKind) {
399 if (InputFPUKind == ARM::FK_INVALID || InputFPUKind == ARM::FK_NONE)
400 return ARM::FK_INVALID;
401
402 const ARM::FPUName &InputFPU = ARM::FPUNames[InputFPUKind];
403
404 // If the input FPU already is single-precision only, then there
405 // isn't any different FPU we can return here.
406 if (!ARM::isDoublePrecision(restriction: InputFPU.Restriction))
407 return InputFPUKind;
408
409 // Otherwise, look for an FPU entry that has the same FPUVer
410 // and is not Double Precision. We want to allow for changing of
411 // NEON Support and Restrictions so CPU's such as Cortex-R52 can
412 // select between SP Only and Full DP modes.
413 for (const ARM::FPUName &CandidateFPU : ARM::FPUNames) {
414 if (CandidateFPU.FPUVer == InputFPU.FPUVer &&
415 !ARM::isDoublePrecision(restriction: CandidateFPU.Restriction)) {
416 return CandidateFPU.ID;
417 }
418 }
419
420 // nothing found
421 return ARM::FK_INVALID;
422}
423
424bool ARM::appendArchExtFeatures(StringRef CPU, ARM::ArchKind AK,
425 StringRef ArchExt,
426 std::vector<StringRef> &Features,
427 ARM::FPUKind &ArgFPUKind) {
428
429 size_t StartingNumFeatures = Features.size();
430 const bool Negated = stripNegationPrefix(Name&: ArchExt);
431 uint64_t ID = parseArchExt(ArchExt);
432
433 if (ID == AEK_INVALID)
434 return false;
435
436 for (const auto &AE : ARCHExtNames) {
437 if (Negated) {
438 if ((AE.ID & ID) == ID && !AE.NegFeature.empty())
439 Features.push_back(x: AE.NegFeature);
440 } else {
441 if ((AE.ID & ID) == AE.ID && !AE.Feature.empty())
442 Features.push_back(x: AE.Feature);
443 }
444 }
445
446 if (CPU == "")
447 CPU = "generic";
448
449 if (ArchExt == "fp" || ArchExt == "fp.dp") {
450 const ARM::FPUKind DefaultFPU = getDefaultFPU(CPU, AK);
451 ARM::FPUKind FPUKind;
452 if (ArchExt == "fp.dp") {
453 const bool IsDP = ArgFPUKind != ARM::FK_INVALID &&
454 ArgFPUKind != ARM::FK_NONE &&
455 isDoublePrecision(restriction: getFPURestriction(FPUKind: ArgFPUKind));
456 if (Negated) {
457 /* If there is no FPU selected yet, we still need to set ArgFPUKind, as
458 * leaving it as FK_INVALID, would cause default FPU to be selected
459 * later and that could be double precision one. */
460 if (ArgFPUKind != ARM::FK_INVALID && !IsDP)
461 return true;
462 FPUKind = findSinglePrecisionFPU(InputFPUKind: DefaultFPU);
463 if (FPUKind == ARM::FK_INVALID)
464 FPUKind = ARM::FK_NONE;
465 } else {
466 if (IsDP)
467 return true;
468 FPUKind = findDoublePrecisionFPU(InputFPUKind: DefaultFPU);
469 if (FPUKind == ARM::FK_INVALID)
470 return false;
471 }
472 } else if (Negated) {
473 FPUKind = ARM::FK_NONE;
474 } else {
475 FPUKind = DefaultFPU;
476 }
477 ArgFPUKind = FPUKind;
478 return true;
479 }
480 return StartingNumFeatures != Features.size();
481}
482
483ARM::ArchKind ARM::convertV9toV8(ARM::ArchKind AK) {
484 if (getProfileKind(AK) != ProfileKind::A)
485 return ARM::ArchKind::INVALID;
486 if (AK < ARM::ArchKind::ARMV9A || AK > ARM::ArchKind::ARMV9_3A)
487 return ARM::ArchKind::INVALID;
488 unsigned AK_v8 = static_cast<unsigned>(ARM::ArchKind::ARMV8_5A);
489 AK_v8 += static_cast<unsigned>(AK) -
490 static_cast<unsigned>(ARM::ArchKind::ARMV9A);
491 return static_cast<ARM::ArchKind>(AK_v8);
492}
493
494StringRef ARM::getDefaultCPU(StringRef Arch) {
495 ArchKind AK = parseArch(Arch);
496 if (AK == ArchKind::INVALID)
497 return StringRef();
498
499 // Look for multiple AKs to find the default for pair AK+Name.
500 for (const auto &CPU : CPUNames) {
501 if (CPU.ArchID == AK && CPU.Default)
502 return CPU.Name;
503 }
504
505 // If we can't find a default then target the architecture instead
506 return "generic";
507}
508
509uint64_t ARM::parseHWDiv(StringRef HWDiv) {
510 StringRef Syn = getHWDivSynonym(HWDiv);
511 for (const auto &D : HWDivNames) {
512 if (Syn == D.Name)
513 return D.ID;
514 }
515 return AEK_INVALID;
516}
517
518uint64_t ARM::parseArchExt(StringRef ArchExt) {
519 for (const auto &A : ARCHExtNames) {
520 if (ArchExt == A.Name)
521 return A.ID;
522 }
523 return AEK_INVALID;
524}
525
526ARM::ArchKind ARM::parseCPUArch(StringRef CPU) {
527 for (const auto &C : CPUNames) {
528 if (CPU == C.Name)
529 return C.ArchID;
530 }
531 return ArchKind::INVALID;
532}
533
534void ARM::fillValidCPUArchList(SmallVectorImpl<StringRef> &Values) {
535 for (const auto &Arch : CPUNames) {
536 if (Arch.ArchID != ArchKind::INVALID)
537 Values.push_back(Elt: Arch.Name);
538 }
539}
540
541StringRef ARM::computeDefaultTargetABI(const Triple &TT) {
542 StringRef ArchName = TT.getArchName();
543
544 if (TT.isOSBinFormatMachO()) {
545 if (TT.getEnvironment() == Triple::EABI ||
546 TT.getOS() == Triple::UnknownOS ||
547 parseArchProfile(Arch: ArchName) == ProfileKind::M)
548 return "aapcs";
549 if (TT.isWatchABI())
550 return "aapcs16";
551 return "apcs-gnu";
552 } else if (TT.isOSWindows())
553 // FIXME: this is invalid for WindowsCE.
554 return "aapcs";
555
556 // Select the default based on the platform.
557 switch (TT.getEnvironment()) {
558 case Triple::Android:
559 case Triple::GNUEABI:
560 case Triple::GNUEABIT64:
561 case Triple::GNUEABIHF:
562 case Triple::GNUEABIHFT64:
563 case Triple::MuslEABI:
564 case Triple::MuslEABIHF:
565 case Triple::OpenHOS:
566 return "aapcs-linux";
567 case Triple::EABIHF:
568 case Triple::EABI:
569 return "aapcs";
570 default:
571 if (TT.isOSNetBSD())
572 return "apcs-gnu";
573 if (TT.isOSFreeBSD() || TT.isOSFuchsia() || TT.isOSOpenBSD() ||
574 TT.isOSHaiku() || TT.isOHOSFamily())
575 return "aapcs-linux";
576 return "aapcs";
577 }
578}
579
580ARM::ARMABI ARM::computeTargetABI(const Triple &TT, StringRef ABIName) {
581 if (ABIName.empty())
582 ABIName = ARM::computeDefaultTargetABI(TT);
583
584 if (ABIName == "aapcs16")
585 return ARM_ABI_AAPCS16;
586
587 if (ABIName.starts_with(Prefix: "aapcs"))
588 return ARM_ABI_AAPCS;
589
590 if (ABIName.starts_with(Prefix: "apcs"))
591 return ARM_ABI_APCS;
592
593 return ARM_ABI_UNKNOWN;
594}
595
596StringRef ARM::getARMCPUForArch(const llvm::Triple &Triple, StringRef MArch) {
597 if (MArch.empty())
598 MArch = Triple.getArchName();
599 MArch = llvm::ARM::getCanonicalArchName(Arch: MArch);
600
601 // Some defaults are forced.
602 switch (Triple.getOS()) {
603 case llvm::Triple::FreeBSD:
604 case llvm::Triple::NetBSD:
605 case llvm::Triple::OpenBSD:
606 case llvm::Triple::Haiku:
607 if (!MArch.empty() && MArch == "v6")
608 return "arm1176jzf-s";
609 if (!MArch.empty() && MArch == "v7")
610 return "cortex-a8";
611 break;
612 case llvm::Triple::Win32:
613 // FIXME: this is invalid for WindowsCE
614 if (llvm::ARM::parseArchVersion(Arch: MArch) <= 7)
615 return "cortex-a9";
616 break;
617 case llvm::Triple::IOS:
618 case llvm::Triple::MacOSX:
619 case llvm::Triple::TvOS:
620 case llvm::Triple::WatchOS:
621 case llvm::Triple::DriverKit:
622 case llvm::Triple::XROS:
623 if (MArch == "v7k")
624 return "cortex-a7";
625 break;
626 default:
627 break;
628 }
629
630 if (MArch.empty())
631 return StringRef();
632
633 StringRef CPU = llvm::ARM::getDefaultCPU(Arch: MArch);
634 if (!CPU.empty() && CPU != "invalid")
635 return CPU;
636
637 // If no specific architecture version is requested, return the minimum CPU
638 // required by the OS and environment.
639 switch (Triple.getOS()) {
640 case llvm::Triple::Haiku:
641 return "arm1176jzf-s";
642 case llvm::Triple::NetBSD:
643 switch (Triple.getEnvironment()) {
644 case llvm::Triple::EABI:
645 case llvm::Triple::EABIHF:
646 case llvm::Triple::GNUEABI:
647 case llvm::Triple::GNUEABIHF:
648 return "arm926ej-s";
649 default:
650 return "strongarm";
651 }
652 case llvm::Triple::OpenBSD:
653 return "cortex-a8";
654 case llvm::Triple::Fuchsia:
655 return "cortex-a53";
656 default:
657 switch (Triple.getEnvironment()) {
658 case llvm::Triple::EABIHF:
659 case llvm::Triple::GNUEABIHF:
660 case llvm::Triple::GNUEABIHFT64:
661 case llvm::Triple::MuslEABIHF:
662 return "arm1176jzf-s";
663 default:
664 return "arm7tdmi";
665 }
666 }
667
668 llvm_unreachable("invalid arch name");
669}
670
671void ARM::PrintSupportedExtensions(StringMap<StringRef> DescMap) {
672 outs() << "All available -march extensions for ARM\n\n"
673 << " " << left_justify(Str: "Name", Width: 20)
674 << (DescMap.empty() ? "\n" : "Description\n");
675 for (const auto &Ext : ARCHExtNames) {
676 // Extensions without a feature cannot be used with -march.
677 if (!Ext.Feature.empty()) {
678 std::string Description = DescMap[Ext.Name].str();
679 // With SIMD, this links to the NEON feature, so the description should be
680 // taken from here, as SIMD does not exist in TableGen.
681 if (Ext.Name == "simd")
682 Description = DescMap["neon"].str();
683 outs() << " "
684 << format(Fmt: Description.empty() ? "%s\n" : "%-20s%s\n",
685 Vals: Ext.Name.str().c_str(), Vals: Description.c_str());
686 }
687 }
688}
689