1//===--- TargetDataLayout.cpp - Map Triple to LLVM data layout string -----===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "llvm/ADT/StringRef.h"
10#include "llvm/Support/CommandLine.h"
11#include "llvm/TargetParser/ARMTargetParser.h"
12#include "llvm/TargetParser/Triple.h"
13#include <cstring>
14using namespace llvm;
15
16static StringRef getManglingComponent(const Triple &T) {
17 if (T.isOSBinFormatGOFF())
18 return "-m:l";
19 if (T.isOSBinFormatMachO())
20 return "-m:o";
21 if ((T.isOSWindows() || T.isUEFI()) && T.isOSBinFormatCOFF())
22 return T.getArch() == Triple::x86 ? "-m:x" : "-m:w";
23 if (T.isOSBinFormatXCOFF())
24 return "-m:a";
25 return "-m:e";
26}
27
28static std::string computeARMDataLayout(const Triple &TT, StringRef ABIName) {
29 auto ABI = ARM::computeTargetABI(TT, ABIName);
30 std::string Ret;
31
32 if (TT.isLittleEndian())
33 // Little endian.
34 Ret += "e";
35 else
36 // Big endian.
37 Ret += "E";
38
39 Ret += getManglingComponent(T: TT);
40
41 // Pointers are 32 bits and aligned to 32 bits.
42 Ret += "-p:32:32";
43
44 // Function pointers are aligned to 8 bits (because the LSB stores the
45 // ARM/Thumb state).
46 Ret += "-Fi8";
47
48 // ABIs other than APCS have 64 bit integers with natural alignment.
49 if (ABI != ARM::ARM_ABI_APCS)
50 Ret += "-i64:64";
51
52 // We have 64 bits floats. The APCS ABI requires them to be aligned to 32
53 // bits, others to 64 bits. We always try to align to 64 bits.
54 if (ABI == ARM::ARM_ABI_APCS)
55 Ret += "-f64:32:64";
56
57 // We have 128 and 64 bit vectors. The APCS ABI aligns them to 32 bits, others
58 // to 64. We always ty to give them natural alignment.
59 if (ABI == ARM::ARM_ABI_APCS)
60 Ret += "-v64:32:64-v128:32:128";
61 else if (ABI != ARM::ARM_ABI_AAPCS16)
62 Ret += "-v128:64:128";
63
64 // Try to align aggregates to 32 bits (the default is 64 bits, which has no
65 // particular hardware support on 32-bit ARM).
66 Ret += "-a:0:32";
67
68 // Integer registers are 32 bits.
69 Ret += "-n32";
70
71 // The stack is 64 bit aligned on AAPCS and 32 bit aligned everywhere else.
72 if (ABI == ARM::ARM_ABI_AAPCS16)
73 Ret += "-S128";
74 else if (ABI == ARM::ARM_ABI_AAPCS)
75 Ret += "-S64";
76 else
77 Ret += "-S32";
78
79 return Ret;
80}
81
82// Helper function to build a DataLayout string
83static std::string computeAArch64DataLayout(const Triple &TT) {
84 if (TT.isOSBinFormatMachO()) {
85 if (TT.getArch() == Triple::aarch64_32)
86 return "e-m:o-p:32:32-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-"
87 "n32:64-S128-Fn32";
88 return "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-"
89 "Fn32";
90 }
91 if (TT.isOSBinFormatCOFF())
92 return "e-m:w-p270:32:32-p271:32:32-p272:64:64-p:64:64-i32:32-i64:64-i128:"
93 "128-n32:64-S128-Fn32";
94 std::string Endian = TT.isLittleEndian() ? "e" : "E";
95 std::string Ptr32 = TT.getEnvironment() == Triple::GNUILP32 ? "-p:32:32" : "";
96 return Endian + "-m:e" + Ptr32 +
97 "-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-"
98 "n32:64-S128-Fn32";
99}
100
101// DataLayout: little or big endian
102static std::string computeBPFDataLayout(const Triple &TT) {
103 if (TT.getArch() == Triple::bpfeb)
104 return "E-m:e-p:64:64-i64:64-i128:128-n32:64-S128";
105 else
106 return "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128";
107}
108
109static std::string computeCSKYDataLayout(const Triple &TT) {
110 // CSKY is always 32-bit target with the CSKYv2 ABI as prefer now.
111 // It's a 4-byte aligned stack with ELF mangling only.
112 // Only support little endian for now.
113 // TODO: Add support for big endian.
114 return "e-m:e-S32-p:32:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:32"
115 "-v128:32:32-a:0:32-Fi32-n32";
116}
117
118static std::string computeLoongArchDataLayout(const Triple &TT) {
119 if (TT.isLoongArch64())
120 return "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128";
121 assert(TT.isLoongArch32() && "only LA32 and LA64 are currently supported");
122 return "e-m:e-p:32:32-i64:64-n32-S128";
123}
124
125static std::string computeM68kDataLayout(const Triple &TT) {
126 std::string Ret = "";
127 // M68k is Big Endian
128 Ret += "E";
129
130 // FIXME how to wire it with the used object format?
131 Ret += "-m:e";
132
133 // M68k pointers are always 32 bit wide even for 16-bit CPUs.
134 // The ABI only specifies 16-bit alignment.
135 // On at least the 68020+ with a 32-bit bus, there is a performance benefit
136 // to having 32-bit alignment.
137 Ret += "-p:32:16:32";
138
139 // Bytes do not require special alignment, words are word aligned and
140 // long words are word aligned at minimum.
141 Ret += "-i8:8:8-i16:16:16-i32:16:32";
142
143 // FIXME no floats at the moment
144
145 // The registers can hold 8, 16, 32 bits
146 Ret += "-n8:16:32";
147
148 Ret += "-a:0:16-S16";
149
150 return Ret;
151}
152
153namespace {
154enum class MipsABI { Unknown, O32, N32, N64 };
155}
156
157// FIXME: This duplicates MipsABIInfo::computeTargetABI, but duplicating this is
158// preferable to violating layering rules. Ideally that information should live
159// in LLVM TargetParser, but for now we just duplicate some ABI name string
160// logic for simplicity.
161static MipsABI getMipsABI(const Triple &TT, StringRef ABIName) {
162 if (ABIName.starts_with(Prefix: "o32"))
163 return MipsABI::O32;
164 if (ABIName.starts_with(Prefix: "n32"))
165 return MipsABI::N32;
166 if (ABIName.starts_with(Prefix: "n64"))
167 return MipsABI::N64;
168 if (TT.isABIN32())
169 return MipsABI::N32;
170 assert(ABIName.empty() && "Unknown ABI option for MIPS");
171
172 if (TT.isMIPS64())
173 return MipsABI::N64;
174 return MipsABI::O32;
175}
176
177static std::string computeMipsDataLayout(const Triple &TT, StringRef ABIName) {
178 std::string Ret;
179 MipsABI ABI = getMipsABI(TT, ABIName);
180
181 // There are both little and big endian mips.
182 if (TT.isLittleEndian())
183 Ret += "e";
184 else
185 Ret += "E";
186
187 if (ABI == MipsABI::O32)
188 Ret += "-m:m";
189 else
190 Ret += "-m:e";
191
192 // Pointers are 32 bit on some ABIs.
193 if (ABI != MipsABI::N64)
194 Ret += "-p:32:32";
195
196 // 8 and 16 bit integers only need to have natural alignment, but try to
197 // align them to 32 bits. 64 bit integers have natural alignment.
198 Ret += "-i8:8:32-i16:16:32-i64:64";
199
200 // 32 bit registers are always available and the stack is at least 64 bit
201 // aligned. On N64 64 bit registers are also available and the stack is
202 // 128 bit aligned.
203 if (ABI == MipsABI::N64 || ABI == MipsABI::N32)
204 Ret += "-i128:128-n32:64-S128";
205 else
206 Ret += "-n32-S64";
207
208 return Ret;
209}
210
211static std::string computePowerDataLayout(const Triple &T, StringRef ABIName) {
212 bool is64Bit = T.isPPC64();
213 std::string Ret;
214
215 // Most PPC* platforms are big endian, PPC(64)LE is little endian.
216 if (T.isLittleEndian())
217 Ret = "e";
218 else
219 Ret = "E";
220
221 Ret += getManglingComponent(T);
222
223 // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
224 // pointers.
225 if (!is64Bit || T.getOS() == Triple::Lv2)
226 Ret += "-p:32:32";
227
228 // If the target ABI uses function descriptors, then the alignment of function
229 // pointers depends on the alignment used to emit the descriptor. Otherwise,
230 // function pointers are aligned to 32 bits because the instructions must be.
231 if ((T.getArch() == Triple::ppc64 &&
232 (!T.isPPC64ELFv2ABI() && ABIName != "elfv2"))) {
233 Ret += "-Fi64";
234 } else if (T.isOSAIX()) {
235 Ret += is64Bit ? "-Fi64" : "-Fi32";
236 } else {
237 Ret += "-Fn32";
238 }
239
240 // Note, the alignment values for f64 and i64 on ppc64 in Darwin
241 // documentation are wrong; these are correct (i.e. "what gcc does").
242 Ret += "-i64:64";
243
244 // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
245 if (is64Bit)
246 Ret += "-i128:128-n32:64";
247 else
248 Ret += "-n32";
249
250 // The ABI alignment for doubles on AIX is 4 bytes.
251 if (T.isOSAIX())
252 Ret += "-f64:32:64";
253
254 // Specify the vector alignment explicitly. For v256i1 and v512i1, the
255 // calculated alignment would be 256*alignment(i1) and 512*alignment(i1),
256 // which is 256 and 512 bytes - way over aligned.
257 if (is64Bit && (T.isOSAIX() || T.isOSLinux()))
258 Ret += "-S128-v256:256:256-v512:512:512";
259
260 return Ret;
261}
262
263static std::string computeAMDDataLayout(const Triple &TT) {
264 if (TT.getArch() == Triple::r600) {
265 // 32-bit pointers.
266 return "e-m:e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
267 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1";
268 }
269
270 // 32-bit private, local, and region pointers. 64-bit global, constant and
271 // flat. 160-bit non-integral fat buffer pointers that include a 128-bit
272 // buffer descriptor and a 32-bit offset, which are indexed by 32-bit values
273 // (address space 7), and 128-bit non-integral buffer resourcees (address
274 // space 8) which cannot be non-trivilally accessed by LLVM memory operations
275 // like getelementptr.
276 return "e-m:e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
277 "-p7:160:256:256:32-p8:128:128:128:48-p9:192:256:256:32-i64:64-"
278 "v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-"
279 "v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9";
280}
281
282static std::string computeRISCVDataLayout(const Triple &TT, StringRef ABIName) {
283 if (TT.isOSBinFormatMachO()) {
284 assert(TT.isLittleEndian() && "Invalid endianness");
285 assert(TT.isArch32Bit() && "Invalid triple");
286 assert((ABIName != "ilp32e") && "Invalid ABI.");
287 return "e-m:o-p:32:32-i64:64-n32-S128";
288 }
289
290 std::string Ret;
291
292 if (TT.isLittleEndian())
293 Ret += "e";
294 else
295 Ret += "E";
296
297 Ret += "-m:e";
298
299 // Pointer and integer sizes.
300 if (TT.isRISCV64()) {
301 Ret += "-p:64:64-i64:64-i128:128";
302 Ret += "-n32:64";
303 } else {
304 assert(TT.isRISCV32() && "only RV32 and RV64 are currently supported");
305 Ret += "-p:32:32-i64:64";
306 Ret += "-n32";
307 }
308
309 // Stack alignment based on ABI.
310 StringRef ABI = ABIName;
311 if (ABI == "ilp32e")
312 Ret += "-S32";
313 else if (ABI == "lp64e")
314 Ret += "-S64";
315 else
316 Ret += "-S128";
317
318 return Ret;
319}
320
321static std::string computeSparcDataLayout(const Triple &T) {
322 const bool Is64Bit = T.isSPARC64();
323
324 // Sparc is typically big endian, but some are little.
325 std::string Ret = T.getArch() == Triple::sparcel ? "e" : "E";
326 Ret += "-m:e";
327
328 // Some ABIs have 32bit pointers.
329 if (!Is64Bit)
330 Ret += "-p:32:32";
331
332 // Alignments for 64 bit integers.
333 Ret += "-i64:64";
334
335 // Alignments for 128 bit integers.
336 // This is not specified in the ABI document but is the de facto standard.
337 Ret += "-i128:128";
338
339 // On SparcV9 128 floats are aligned to 128 bits, on others only to 64.
340 // On SparcV9 registers can hold 64 or 32 bits, on others only 32.
341 if (Is64Bit)
342 Ret += "-n32:64";
343 else
344 Ret += "-f128:64-n32";
345
346 if (Is64Bit)
347 Ret += "-S128";
348 else
349 Ret += "-S64";
350
351 return Ret;
352}
353
354static std::string computeSystemZDataLayout(const Triple &TT) {
355 std::string Ret;
356
357 // Big endian.
358 Ret += "E";
359
360 // The natural stack alignment is 64 bits.
361 Ret += "-S64";
362
363 // Data mangling.
364 Ret += getManglingComponent(T: TT);
365
366 // Special features for z/OS.
367 if (TT.isOSzOS()) {
368 // Custom address space for ptr32.
369 Ret += "-p1:32:32";
370 }
371
372 // Make sure that global data has at least 16 bits of alignment by
373 // default, so that we can refer to it using LARL. We don't have any
374 // special requirements for stack variables though.
375 Ret += "-i1:8:16-i8:8:16";
376
377 // 64-bit integers are naturally aligned.
378 Ret += "-i64:64";
379
380 // 128-bit floats are aligned only to 64 bits.
381 Ret += "-f128:64";
382
383 // The DataLayout string always holds a vector alignment of 64 bits, see
384 // comment in clang/lib/Basic/Targets/SystemZ.h.
385 Ret += "-v128:64";
386
387 // We prefer 16 bits of aligned for all globals; see above.
388 Ret += "-a:8:16";
389
390 // Integer registers are 32 or 64 bits.
391 Ret += "-n32:64";
392
393 return Ret;
394}
395
396static std::string computeX86DataLayout(const Triple &TT) {
397 bool Is64Bit = TT.isX86_64();
398
399 // X86 is little endian
400 std::string Ret = "e";
401
402 Ret += getManglingComponent(T: TT);
403 // X86 and x32 have 32 bit pointers.
404 if (!Is64Bit || TT.isX32())
405 Ret += "-p:32:32";
406
407 // Address spaces for 32 bit signed, 32 bit unsigned, and 64 bit pointers.
408 Ret += "-p270:32:32-p271:32:32-p272:64:64";
409
410 // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
411 // 128 bit integers are not specified in the 32-bit ABIs but are used
412 // internally for lowering f128, so we match the alignment to that.
413 if (Is64Bit || TT.isOSWindows())
414 Ret += "-i64:64-i128:128";
415 else if (TT.isOSIAMCU())
416 Ret += "-i64:32-f64:32";
417 else
418 Ret += "-i128:128-f64:32:64";
419
420 // Some ABIs align long double to 128 bits, others to 32.
421 if (TT.isOSIAMCU())
422 ; // No f80
423 else if (Is64Bit || TT.isOSDarwin() || TT.isWindowsMSVCEnvironment())
424 Ret += "-f80:128";
425 else
426 Ret += "-f80:32";
427
428 if (TT.isOSIAMCU())
429 Ret += "-f128:32";
430
431 // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
432 if (Is64Bit)
433 Ret += "-n8:16:32:64";
434 else
435 Ret += "-n8:16:32";
436
437 // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
438 if ((!Is64Bit && TT.isOSWindows()) || TT.isOSIAMCU())
439 Ret += "-a:0:32-S32";
440 else
441 Ret += "-S128";
442
443 return Ret;
444}
445
446static std::string computeNVPTXDataLayout(const Triple &T, StringRef ABIName) {
447 bool Is64Bit = T.getArch() == Triple::nvptx64;
448 std::string Ret = "e";
449
450 // Tensor Memory (addrspace:6) is always 32-bits.
451 // Distributed Shared Memory (addrspace:7) follows shared memory
452 // (addrspace:3).
453 if (!Is64Bit)
454 Ret += "-p:32:32-p6:32:32-p7:32:32";
455 else if (ABIName == "shortptr")
456 Ret += "-p3:32:32-p4:32:32-p5:32:32-p6:32:32-p7:32:32";
457 else
458 Ret += "-p6:32:32";
459
460 Ret += "-i64:64-i128:128-i256:256-v16:16-v32:32-n16:32:64";
461
462 return Ret;
463}
464
465static std::string computeSPIRVDataLayout(const Triple &TT) {
466 const auto Arch = TT.getArch();
467 // TODO: this probably needs to be revisited:
468 // Logical SPIR-V has no pointer size, so any fixed pointer size would be
469 // wrong. The choice to default to 32 or 64 is just motivated by another
470 // memory model used for graphics: PhysicalStorageBuffer64. But it shouldn't
471 // mean anything.
472 if (Arch == Triple::spirv32)
473 return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-"
474 "v256:256-v512:512-v1024:1024-n8:16:32:64-G1";
475 if (Arch == Triple::spirv)
476 return "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-"
477 "v512:512-v1024:1024-n8:16:32:64-G10";
478 if (TT.getVendor() == Triple::VendorType::AMD &&
479 TT.getOS() == Triple::OSType::AMDHSA)
480 return "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-"
481 "v512:512-v1024:1024-n32:64-S32-G1-P4-A0";
482 if (TT.getVendor() == Triple::VendorType::Intel)
483 return "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-"
484 "v512:512-v1024:1024-n8:16:32:64-G1-P9-A0";
485 return "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-"
486 "v512:512-v1024:1024-n8:16:32:64-G1";
487}
488
489static std::string computeLanaiDataLayout() {
490 // Data layout (keep in sync with clang/lib/Basic/Targets.cpp)
491 return "E" // Big endian
492 "-m:e" // ELF name manging
493 "-p:32:32" // 32-bit pointers, 32 bit aligned
494 "-i64:64" // 64 bit integers, 64 bit aligned
495 "-a:0:32" // 32 bit alignment of objects of aggregate type
496 "-n32" // 32 bit native integer width
497 "-S64"; // 64 bit natural stack alignment
498}
499
500static std::string computeWebAssemblyDataLayout(const Triple &TT) {
501 return TT.getArch() == Triple::wasm64
502 ? (TT.isOSEmscripten() ? "e-m:e-p:64:64-p10:8:8-p20:8:8-i64:64-"
503 "i128:128-f128:64-n32:64-S128-ni:1:10:20"
504 : "e-m:e-p:64:64-p10:8:8-p20:8:8-i64:64-"
505 "i128:128-n32:64-S128-ni:1:10:20")
506 : (TT.isOSEmscripten() ? "e-m:e-p:32:32-p10:8:8-p20:8:8-i64:64-"
507 "i128:128-f128:64-n32:64-S128-ni:1:10:20"
508 : "e-m:e-p:32:32-p10:8:8-p20:8:8-i64:64-"
509 "i128:128-n32:64-S128-ni:1:10:20");
510}
511
512static std::string computeVEDataLayout(const Triple &T) {
513 // Aurora VE is little endian
514 std::string Ret = "e";
515
516 // Use ELF mangling
517 Ret += "-m:e";
518
519 // Alignments for 64 bit integers.
520 Ret += "-i64:64";
521
522 // VE supports 32 bit and 64 bits integer on registers
523 Ret += "-n32:64";
524
525 // Stack alignment is 128 bits
526 Ret += "-S128";
527
528 // Vector alignments are 64 bits
529 // Need to define all of them. Otherwise, each alignment becomes
530 // the size of each data by default.
531 Ret += "-v64:64:64"; // for v2f32
532 Ret += "-v128:64:64";
533 Ret += "-v256:64:64";
534 Ret += "-v512:64:64";
535 Ret += "-v1024:64:64";
536 Ret += "-v2048:64:64";
537 Ret += "-v4096:64:64";
538 Ret += "-v8192:64:64";
539 Ret += "-v16384:64:64"; // for v256f64
540
541 return Ret;
542}
543
544std::string Triple::computeDataLayout(StringRef ABIName) const {
545 switch (getArch()) {
546 case Triple::arm:
547 case Triple::armeb:
548 case Triple::thumb:
549 case Triple::thumbeb:
550 return computeARMDataLayout(TT: *this, ABIName);
551 case Triple::aarch64:
552 case Triple::aarch64_be:
553 case Triple::aarch64_32:
554 return computeAArch64DataLayout(TT: *this);
555 case Triple::arc:
556 return "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-"
557 "f32:32:32-i64:32-f64:32-a:0:32-n32";
558 case Triple::avr:
559 return "e-P1-p:16:8-i8:8-i16:8-i32:8-i64:8-f32:8-f64:8-n8:16-a:8";
560 case Triple::bpfel:
561 case Triple::bpfeb:
562 return computeBPFDataLayout(TT: *this);
563 case Triple::csky:
564 return computeCSKYDataLayout(TT: *this);
565 case Triple::dxil:
566 // TODO: We need to align vectors on the element size generally, but for now
567 // we hard code this for 3-element 32- and 64-bit vectors as a workaround.
568 // See https://github.com/llvm/llvm-project/issues/123968
569 return "e-m:e-p:32:32-i1:32-i8:8-i16:16-i32:32-i64:64-f16:16-"
570 "f32:32-f64:64-n8:16:32:64-v48:16:16-v96:32:32-v192:64:64";
571 case Triple::hexagon:
572 return "e-m:e-p:32:32:32-a:0-n16:32-"
573 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
574 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048";
575 case Triple::loongarch32:
576 case Triple::loongarch64:
577 return computeLoongArchDataLayout(TT: *this);
578 case Triple::m68k:
579 return computeM68kDataLayout(TT: *this);
580 case Triple::mips:
581 case Triple::mipsel:
582 case Triple::mips64:
583 case Triple::mips64el:
584 return computeMipsDataLayout(TT: *this, ABIName);
585 case Triple::msp430:
586 return "e-m:e-p:16:16-i32:16-i64:16-f32:16-f64:16-a:8-n8:16-S16";
587 case Triple::ppc:
588 case Triple::ppcle:
589 case Triple::ppc64:
590 case Triple::ppc64le:
591 return computePowerDataLayout(T: *this, ABIName);
592 case Triple::r600:
593 case Triple::amdgcn:
594 return computeAMDDataLayout(TT: *this);
595 case Triple::riscv32:
596 case Triple::riscv64:
597 case Triple::riscv32be:
598 case Triple::riscv64be:
599 return computeRISCVDataLayout(TT: *this, ABIName);
600 case Triple::sparc:
601 case Triple::sparcv9:
602 case Triple::sparcel:
603 return computeSparcDataLayout(T: *this);
604 case Triple::systemz:
605 return computeSystemZDataLayout(TT: *this);
606 case Triple::tce:
607 case Triple::tcele:
608 case Triple::x86:
609 case Triple::x86_64:
610 return computeX86DataLayout(TT: *this);
611 case Triple::xcore:
612 return "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32-f64:32-a:0:32-n32";
613 case Triple::xtensa:
614 return "e-m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32";
615 case Triple::nvptx:
616 case Triple::nvptx64:
617 return computeNVPTXDataLayout(T: *this, ABIName);
618 case Triple::spir:
619 case Triple::spir64:
620 case Triple::spirv:
621 case Triple::spirv32:
622 case Triple::spirv64:
623 return computeSPIRVDataLayout(TT: *this);
624 case Triple::lanai:
625 return computeLanaiDataLayout();
626 case Triple::wasm32:
627 case Triple::wasm64:
628 return computeWebAssemblyDataLayout(TT: *this);
629 case Triple::ve:
630 return computeVEDataLayout(T: *this);
631
632 case Triple::amdil:
633 case Triple::amdil64:
634 case Triple::hsail:
635 case Triple::hsail64:
636 case Triple::kalimba:
637 case Triple::shave:
638 case Triple::renderscript32:
639 case Triple::renderscript64:
640 // These are all virtual ISAs with no LLVM backend, and therefore no fixed
641 // LLVM data layout.
642 return "";
643
644 case Triple::UnknownArch:
645 return "";
646 }
647 llvm_unreachable("Invalid arch");
648}
649