1//===--- TargetDataLayout.cpp - Map Triple to LLVM data layout string -----===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "llvm/ADT/StringRef.h"
10#include "llvm/TargetParser/ARMTargetParser.h"
11#include "llvm/TargetParser/Triple.h"
12using namespace llvm;
13
14static StringRef getManglingComponent(const Triple &T) {
15 if (T.isOSBinFormatGOFF())
16 return "-m:l";
17 if (T.isOSBinFormatMachO())
18 return "-m:o";
19 if (T.isOSWindowsOrUEFI() && T.isOSBinFormatCOFF())
20 return T.getArch() == Triple::x86 ? "-m:x" : "-m:w";
21 if (T.isOSBinFormatXCOFF())
22 return "-m:a";
23 return "-m:e";
24}
25
26static std::string computeARMDataLayout(const Triple &TT, StringRef ABIName) {
27 auto ABI = ARM::computeTargetABI(TT, ABIName);
28 std::string Ret;
29 Ret.reserve(res_arg: 128);
30
31 Ret += TT.isLittleEndian() ? 'e' : 'E';
32 Ret += getManglingComponent(T: TT);
33
34 // Pointers are 32 bits and aligned to 32 bits.
35 // Function pointers are aligned to 8 bits (because the LSB stores the
36 // ARM/Thumb state).
37 Ret += "-p:32:32-Fi8";
38
39 // ABIs other than APCS have 64 bit integers with natural alignment.
40 //
41 // We have 64 bits floats. The APCS ABI requires them to be aligned to 32
42 // bits, others to 64 bits. We always try to align to 64 bits.
43 //
44 // We have 128 and 64 bit vectors. The APCS ABI aligns them to 32 bits, others
45 // to 64. We always try to give them natural alignment.
46 if (ABI == ARM::ARM_ABI_APCS)
47 Ret += "-f64:32:64-v64:32:64-v128:32:128";
48 else if (ABI == ARM::ARM_ABI_AAPCS16)
49 Ret += "-i64:64";
50 else
51 Ret += "-i64:64-v128:64:128";
52
53 // Try to align aggregates to 32 bits (the default is 64 bits, which has no
54 // particular hardware support on 32-bit ARM).
55 Ret += "-a:0:32-n32";
56
57 // The stack is 64 bit aligned on AAPCS and 32 bit aligned everywhere else
58 if (ABI == ARM::ARM_ABI_AAPCS16)
59 Ret += "-S128";
60 else if (ABI == ARM::ARM_ABI_AAPCS)
61 Ret += "-S64";
62 else
63 Ret += "-S32";
64
65 return Ret;
66}
67
68static std::string computeAArch64DataLayout(const Triple &TT) {
69 if (TT.isOSBinFormatMachO()) {
70 if (TT.getArch() == Triple::aarch64_32)
71 return "e-m:o-p:32:32-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-"
72 "n32:64-S128-Fn32";
73 return "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-"
74 "Fn32";
75 }
76 if (TT.isOSBinFormatCOFF())
77 return "e-m:w-p270:32:32-p271:32:32-p272:64:64-p:64:64-i32:32-i64:64-"
78 "i128:128-n32:64-S128-Fn32";
79
80 std::string Ret = TT.isLittleEndian() ? "e-m:e" : "E-m:e";
81 if (TT.getEnvironment() == Triple::GNUILP32)
82 Ret += "-p:32:32";
83 Ret += "-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-"
84 "n32:64-S128-Fn32";
85 return Ret;
86}
87
88static std::string computeBPFDataLayout(const Triple &TT) {
89 if (TT.getArch() == Triple::bpfeb)
90 return "E-m:e-p:64:64-i64:64-i128:128-n32:64-S128";
91 return "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128";
92}
93
94static std::string computeCSKYDataLayout(const Triple &TT) {
95 // CSKY is always 32-bit target with the CSKYv2 ABI as prefer now.
96 // It's a 4-byte aligned stack with ELF mangling only.
97 // Only support little endian for now.
98 // TODO: Add support for big endian.
99 return "e-m:e-S32-p:32:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:32"
100 "-v128:32:32-a:0:32-Fi32-n32";
101}
102
103static std::string computeLoongArchDataLayout(const Triple &TT) {
104 if (TT.isLoongArch64())
105 return "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128";
106 assert(TT.isLoongArch32() && "only LA32 and LA64 are currently supported");
107 return "e-m:e-p:32:32-i64:64-n32-S128";
108}
109
110// The Linux m68k target uses the ABI used
111// by Sun Microsystems for the old a.out-based binaries: 16-bit
112// alignment of int/long/pointer.
113//
114// NetBSD/m68k on the other hand uses the SVR4 ABI, which
115// aligns int/long/pointer/objects/stack on 32-bit boundaries.
116//
117// For now we just fix this for NetBSD/m68k.
118//
119// Ref. https://github.com/llvm/llvm-project/issues/199826
120
121static std::string computeM68kDataLayout(const Triple &TT) {
122 // FIXME how to wire it with the used object format?
123 // FIXME no floats at the moment
124 if (TT.isOSNetBSD()) {
125 // NetBSD/m68k aligns long/pointer/stack/objects on 32-bits,
126 // ref. comment above.
127 // Bytes do not require special alignment,
128 // 16-bit ints are 16-bit aligned and
129 // 32-bit ints are 32-bit aligned
130 // The registers can hold 8, 16, 32 bits
131 // object and stack alignment is also 32 bits
132 return "E-m:e-p:32:32:32-i8:8:8-i16:16:16-i32:32:32-n8:16:32-a:0:32-S32";
133 }
134
135 // M68k pointers are always 32 bit wide even for 16-bit CPUs.
136 // The ABI only specifies 16-bit alignment.
137 // On at least the 68020+ with a 32-bit bus, there is a performance benefit
138 // to having 32-bit alignment.
139 // Bytes do not require special alignment, words are word aligned and
140 // long words are word aligned at minimum.
141 // The registers can hold 8, 16, 32 bits
142 return "E-m:e-p:32:16:32-i8:8:8-i16:16:16-i32:16:32-n8:16:32-a:0:16-S16";
143}
144
145namespace {
146enum class MipsABI { O32, N32, N64 };
147}
148
149// FIXME: This duplicates MipsABIInfo::computeTargetABI, but duplicating this is
150// preferable to violating layering rules. Ideally that information should live
151// in LLVM TargetParser, but for now we just duplicate some ABI name string
152// logic for simplicity.
153static MipsABI getMipsABI(const Triple &TT, StringRef ABIName) {
154 if (ABIName.starts_with(Prefix: "o32"))
155 return MipsABI::O32;
156 if (ABIName.starts_with(Prefix: "n32"))
157 return MipsABI::N32;
158 if (ABIName.starts_with(Prefix: "n64"))
159 return MipsABI::N64;
160 if (TT.isABIN32())
161 return MipsABI::N32;
162 assert(ABIName.empty() && "Unknown ABI option for MIPS");
163
164 if (TT.isMIPS64())
165 return MipsABI::N64;
166 return MipsABI::O32;
167}
168
169static std::string computeMipsDataLayout(const Triple &TT, StringRef ABIName) {
170 std::string Ret = TT.isLittleEndian() ? "e" : "E";
171
172 // Pointers are 32 bit on some ABIs.
173 //
174 // 8 and 16 bit integers only need to have natural alignment, but try to
175 // align them to 32 bits. 64 bit integers have natural alignment.
176 //
177 // 32 bit registers are always available and the stack is at least 64 bit
178 // aligned. On N32 and N64 64 bit registers are also available and the stack
179 // is 128 bit aligned.
180 switch (getMipsABI(TT, ABIName)) {
181 case MipsABI::O32:
182 Ret += "-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
183 break;
184 case MipsABI::N32:
185 Ret += "-m:e-p:32:32-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
186 break;
187 case MipsABI::N64:
188 Ret += "-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
189 break;
190 }
191
192 return Ret;
193}
194
195static std::string computePowerDataLayout(const Triple &T, StringRef ABIName) {
196 bool is64Bit = T.isPPC64();
197 std::string Ret;
198 Ret.reserve(res_arg: 128);
199
200 Ret += T.isLittleEndian() ? 'e' : 'E';
201 Ret += getManglingComponent(T);
202
203 // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
204 // pointers.
205 if (!is64Bit || T.getOS() == Triple::Lv2)
206 Ret += "-p:32:32";
207
208 // If the target ABI uses function descriptors, then the alignment of function
209 // pointers depends on the alignment used to emit the descriptor. Otherwise,
210 // function pointers are aligned to 32 bits because the instructions must be.
211 if ((T.getArch() == Triple::ppc64 &&
212 (!T.isPPC64ELFv2ABI() && ABIName != "elfv2"))) {
213 Ret += "-Fi64";
214 } else if (T.isOSAIX()) {
215 Ret += is64Bit ? "-Fi64" : "-Fi32";
216 } else {
217 Ret += "-Fn32";
218 }
219
220 // Note, the alignment values for f64 and i64 on ppc64 in Darwin
221 // documentation are wrong; these are correct (i.e. "what gcc does").
222 // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
223 Ret += is64Bit ? "-i64:64-i128:128-n32:64" : "-i64:64-n32";
224
225 // The ABI alignment for doubles on AIX is 4 bytes.
226 if (T.isOSAIX())
227 Ret += "-f64:32:64";
228
229 // Specify the vector alignment explicitly. For v256i1 and v512i1, the
230 // calculated alignment would be 256*alignment(i1) and 512*alignment(i1),
231 // which is 256 and 512 bytes - way over aligned.
232 if (is64Bit && (T.isOSAIX() || T.isOSLinux()))
233 Ret += "-S128-v256:256:256-v512:512:512";
234
235 return Ret;
236}
237
238static std::string computeAMDDataLayout(const Triple &TT) {
239 if (TT.getArch() == Triple::r600)
240 return "e-m:e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
241 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1";
242
243 // 32-bit private, local, and region pointers. 64-bit global, constant and
244 // flat. 160-bit non-integral fat buffer pointers that include a 128-bit
245 // buffer descriptor and a 32-bit offset, which are indexed by 32-bit values
246 // (address space 7), and 128-bit non-integral buffer resourcees (address
247 // space 8) which cannot be non-trivilally accessed by LLVM memory operations
248 // like getelementptr.
249 return "e-m:e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
250 "-p7:160:256:256:32-p8:128:128:128:48-p9:192:256:256:32-p10:32:32"
251 "-p11:32:32-p12:32:32-p13:32:32-p14:32:32-p15:32:32"
252 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256"
253 "-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9";
254}
255
256static std::string computeRISCVDataLayout(const Triple &TT, StringRef ABIName) {
257 if (TT.isOSBinFormatMachO()) {
258 assert(TT.isLittleEndian() && "Invalid endianness");
259 assert(TT.isArch32Bit() && "Invalid triple");
260 assert((ABIName != "ilp32e") && "Invalid ABI.");
261 return "e-m:o-p:32:32-i64:64-n32-S128";
262 }
263
264 std::string Ret;
265 Ret.reserve(res_arg: 128);
266 Ret += TT.isLittleEndian() ? "e-m:e" : "E-m:e";
267
268 // TODO: Maybe we should move RISCVABI to TargetParser, so we can reuse that
269 // logic here instead of duplicating the string handling?
270 bool IsPureCapABI = ABIName.starts_with(Prefix: "il32pc64") ||
271 ABIName.starts_with(Prefix: "l64pc128") ||
272 ABIName.starts_with(Prefix: "cheriot");
273
274 if (TT.isRISCV64()) {
275 Ret += "-p:64:64";
276 if (IsPureCapABI)
277 Ret += "-pe200:128:128:128:64";
278 Ret += "-i64:64-i128:128-n32:64";
279 } else {
280 assert(TT.isRISCV32() && "only RV32 and RV64 are currently supported");
281 Ret += "-p:32:32";
282 if (IsPureCapABI)
283 Ret += "-pe200:64:64:64:32";
284 Ret += "-i64:64-n32";
285 }
286
287 if (ABIName == "ilp32e")
288 Ret += "-S32";
289 else if (ABIName == "lp64e")
290 Ret += "-S64";
291 else
292 Ret += "-S128";
293
294 // TODO: Support non-purecap CHERI ABIs.
295 if (IsPureCapABI)
296 Ret += "-A200-P200-G200";
297
298 return Ret;
299}
300
301static std::string computeSparcDataLayout(const Triple &T) {
302 // Sparc is typically big endian, but some are little.
303 // Some ABIs have 32bit pointers.
304 // The alignment of 128 bit integers is not specified in the ABI document but
305 // is the de facto standard.
306 // On SparcV9 128 floats are aligned to 128 bits, on others only to 64.
307 // On SparcV9 registers can hold 64 or 32 bits, on others only 32.
308 if (T.isSPARC64())
309 return "E-m:e-i64:64-i128:128-n32:64-S128";
310 if (T.getArch() == Triple::sparcel)
311 return "e-m:e-p:32:32-i64:64-i128:128-f128:64-n32-S64";
312 return "E-m:e-p:32:32-i64:64-i128:128-f128:64-n32-S64";
313}
314
315static std::string computeSystemZDataLayout(const Triple &TT) {
316 // Big endian. The natural stack alignment is 64 bits.
317 std::string Ret = "E-S64";
318
319 Ret += getManglingComponent(T: TT);
320
321 // Special features for z/OS.
322 if (TT.isOSzOS()) {
323 // Custom address space for ptr32.
324 Ret += "-p1:32:32";
325 }
326
327 // Make sure that global data has at least 16 bits of alignment by
328 // default, so that we can refer to it using LARL. We don't have any
329 // special requirements for stack variables though.
330 //
331 // 64-bit integers are naturally aligned. 128-bit floats are aligned only to
332 // 64 bits.
333 //
334 // The DataLayout string always holds a vector alignment of 64 bits, see
335 // comment in clang/lib/Basic/Targets/SystemZ.h.
336 //
337 // We prefer 16 bits of aligned for all globals; see above.
338 //
339 // Integer registers are 32 or 64 bits.
340 Ret += "-i1:8:16-i8:8:16-i64:64-f128:64-v128:64-a:8:16-n32:64";
341
342 return Ret;
343}
344
345static std::string computeX86DataLayout(const Triple &TT) {
346 bool Is64Bit = TT.isX86_64();
347 std::string Ret;
348 Ret.reserve(res_arg: 128);
349
350 // X86 is little endian
351 Ret += 'e';
352 Ret += getManglingComponent(T: TT);
353
354 // X86 and x32 have 32 bit pointers.
355 if (!Is64Bit || TT.isX32())
356 Ret += "-p:32:32";
357
358 // Address spaces for 32 bit signed, 32 bit unsigned, and 64 bit pointers.
359 Ret += "-p270:32:32-p271:32:32-p272:64:64";
360
361 // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
362 // 128 bit integers are not specified in the 32-bit ABIs but are used
363 // internally for lowering f128, so we match the alignment to that.
364 if (Is64Bit || TT.isOSWindows())
365 Ret += "-i64:64-i128:128";
366 else if (TT.isOSIAMCU())
367 Ret += "-i64:32-f64:32";
368 else
369 Ret += "-i128:128-f64:32:64";
370
371 // Some ABIs align long double to 128 bits, others to 32. IAMCU has no f80.
372 if (TT.isOSIAMCU())
373 Ret += "-f128:32";
374 else if (Is64Bit || TT.isOSDarwin() || TT.isWindowsMSVCEnvironment())
375 Ret += "-f80:128";
376 else
377 Ret += "-f80:32";
378
379 // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
380 Ret += Is64Bit ? "-n8:16:32:64" : "-n8:16:32";
381
382 // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
383 if ((!Is64Bit && TT.isOSWindows()) || TT.isOSIAMCU())
384 Ret += "-a:0:32-S32";
385 else
386 Ret += "-S128";
387
388 return Ret;
389}
390
391static std::string computeNVPTXDataLayout(const Triple &T, StringRef ABIName) {
392 if (T.getArch() == Triple::nvptx)
393 return "e-p:32:32-i64:64-i128:128-i256:256-v16:16-v32:32-n16:32:64";
394
395 // Keep the pointer specifications sorted by address space.
396 //
397 // In shortptr mode, specify the following address spaces as 32-bits:
398 // - shared (addrspace:3)
399 // - constant (addrspace:4)
400 // - local (addrspace:5)
401 // - shared cluster (addrspace:7)
402 // - entry parameter (addrspace:101)
403 //
404 // Tensor Memory (addrspace:6) is always 32-bits.
405 if (ABIName == "shortptr")
406 return "e-p3:32:32-p4:32:32-p5:32:32-p6:32:32-p7:32:32-p101:32:32-i64:64-"
407 "i128:128-i256:256-v16:16-v32:32-n16:32:64";
408 return "e-p6:32:32-i64:64-i128:128-i256:256-v16:16-v32:32-n16:32:64";
409}
410
411static std::string computeSPIRVDataLayout(const Triple &TT) {
412 const auto Arch = TT.getArch();
413 // TODO: this probably needs to be revisited:
414 // Logical SPIR-V has no pointer size, so any fixed pointer size would be
415 // wrong. The choice to default to 32 or 64 is just motivated by another
416 // memory model used for graphics: PhysicalStorageBuffer64. But it shouldn't
417 // mean anything.
418 if (Arch == Triple::spirv32)
419 return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-"
420 "v256:256-v512:512-v1024:1024-n8:16:32:64-G1";
421 if (Arch == Triple::spirv)
422 return "e-ve-i64:64-n8:16:32:64-G10";
423 if (TT.getVendor() == Triple::VendorType::AMD &&
424 TT.getOS() == Triple::OSType::AMDHSA)
425 return "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-"
426 "v512:512-v1024:1024-n32:64-S32-G1-P4-A0";
427 if (TT.getVendor() == Triple::VendorType::Intel)
428 return "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-"
429 "v512:512-v1024:1024-n8:16:32:64-G1-P9-A0";
430 return "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-"
431 "v512:512-v1024:1024-n8:16:32:64-G1";
432}
433
434static std::string computeLanaiDataLayout() {
435 // Data layout (keep in sync with clang/lib/Basic/Targets.cpp)
436 return "E" // Big endian
437 "-m:e" // ELF name manging
438 "-p:32:32" // 32-bit pointers, 32 bit aligned
439 "-i64:64" // 64 bit integers, 64 bit aligned
440 "-a:0:32" // 32 bit alignment of objects of aggregate type
441 "-n32" // 32 bit native integer width
442 "-S64"; // 64 bit natural stack alignment
443}
444
445static std::string computeWebAssemblyDataLayout(const Triple &TT) {
446 return TT.getArch() == Triple::wasm64
447 ? (TT.isOSEmscripten() ? "e-m:e-p:64:64-p10:8:8-p20:8:8-i64:64-"
448 "i128:128-f128:64-n32:64-S128-ni:1:10:20"
449 : "e-m:e-p:64:64-p10:8:8-p20:8:8-i64:64-"
450 "i128:128-n32:64-S128-ni:1:10:20")
451 : (TT.isOSEmscripten() ? "e-m:e-p:32:32-p10:8:8-p20:8:8-i64:64-"
452 "i128:128-f128:64-n32:64-S128-ni:1:10:20"
453 : "e-m:e-p:32:32-p10:8:8-p20:8:8-i64:64-"
454 "i128:128-n32:64-S128-ni:1:10:20");
455}
456
457static std::string computeVEDataLayout(const Triple &T) {
458 // Aurora VE is little endian with ELF mangling. 64 bit integers are 64 bit
459 // aligned. VE supports 32 bit and 64 bits integer on registers. Stack
460 // alignment is 128 bits.
461 //
462 // Vector alignments are 64 bits, from v64 (v2f32) to v16384 (v256f64).
463 // Need to define all of them. Otherwise, each alignment becomes the size of
464 // each data by default.
465 return "e-m:e-i64:64-n32:64-S128-v64:64:64-v128:64:64-v256:64:64-v512:64:64-"
466 "v1024:64:64-v2048:64:64-v4096:64:64-v8192:64:64-v16384:64:64";
467}
468
469std::string Triple::computeDataLayout(StringRef ABIName) const {
470 switch (getArch()) {
471 case Triple::arm:
472 case Triple::armeb:
473 case Triple::thumb:
474 case Triple::thumbeb:
475 return computeARMDataLayout(TT: *this, ABIName);
476 case Triple::aarch64:
477 case Triple::aarch64_be:
478 case Triple::aarch64_32:
479 return computeAArch64DataLayout(TT: *this);
480 case Triple::arc:
481 return "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-"
482 "f32:32:32-i64:32-f64:32-a:0:32-n32";
483 case Triple::avr:
484 return "e-P1-p:16:8-i8:8-i16:8-i32:8-i64:8-f32:8-f64:8-n8:16-a:8";
485 case Triple::bpfel:
486 case Triple::bpfeb:
487 return computeBPFDataLayout(TT: *this);
488 case Triple::csky:
489 return computeCSKYDataLayout(TT: *this);
490 case Triple::dxil:
491 return "e-m:e-ve-p:32:32-i1:32-i8:8-i16:16-i32:32-i64:64-f16:16-"
492 "f32:32-f64:64-n8:16:32:64";
493 case Triple::hexagon:
494 return "e-m:e-p:32:32:32-a:0-n16:32-"
495 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
496 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048";
497 case Triple::loongarch32:
498 case Triple::loongarch64:
499 return computeLoongArchDataLayout(TT: *this);
500 case Triple::m68k:
501 return computeM68kDataLayout(TT: *this);
502 case Triple::mips:
503 case Triple::mipsel:
504 case Triple::mips64:
505 case Triple::mips64el:
506 return computeMipsDataLayout(TT: *this, ABIName);
507 case Triple::msp430:
508 return "e-m:e-p:16:16-i32:16-i64:16-f32:16-f64:16-a:8-n8:16-S16";
509 case Triple::ppc:
510 case Triple::ppcle:
511 case Triple::ppc64:
512 case Triple::ppc64le:
513 return computePowerDataLayout(T: *this, ABIName);
514 case Triple::amdgpu:
515 case Triple::r600:
516 return computeAMDDataLayout(TT: *this);
517 case Triple::riscv32:
518 case Triple::riscv64:
519 case Triple::riscv32be:
520 case Triple::riscv64be:
521 return computeRISCVDataLayout(TT: *this, ABIName);
522 case Triple::sparc:
523 case Triple::sparcv9:
524 case Triple::sparcel:
525 return computeSparcDataLayout(T: *this);
526 case Triple::systemz:
527 return computeSystemZDataLayout(TT: *this);
528 case Triple::tce:
529 return "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:32-"
530 "f16:16:16-f32:32:32-f64:32:32-v64:64:64-i128:128-v128:128:128-"
531 "v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048-"
532 "v4096:4096:4096-a0:0:32-n32";
533 case Triple::tcele:
534 return "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:32-"
535 "f16:16:16-f32:32:32-f64:32:32-v64:64:64-i128:128-v128:128:128-"
536 "v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048-"
537 "v4096:4096:4096-a0:0:32-n32";
538 case Triple::tcele64:
539 return "e-p:64:64:64-i1:8:64-i8:8:64-i16:16:64-i32:32:64-i64:64:64-"
540 "f16:16:64-f32:32:64-f64:64:64-v64:64:64-i128:128-v128:128:128-"
541 "v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048-"
542 "v4096:4096:4096-a0:0:64-n64";
543 case Triple::x86:
544 case Triple::x86_64:
545 return computeX86DataLayout(TT: *this);
546 case Triple::xcore:
547 return "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32-f64:32-a:0:32-n32";
548 case Triple::xtensa:
549 return "e-m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32";
550 case Triple::nvptx:
551 case Triple::nvptx64:
552 return computeNVPTXDataLayout(T: *this, ABIName);
553 case Triple::spir:
554 case Triple::spir64:
555 case Triple::spirv:
556 case Triple::spirv32:
557 case Triple::spirv64:
558 return computeSPIRVDataLayout(TT: *this);
559 case Triple::lanai:
560 return computeLanaiDataLayout();
561 case Triple::wasm32:
562 case Triple::wasm64:
563 return computeWebAssemblyDataLayout(TT: *this);
564 case Triple::ve:
565 return computeVEDataLayout(T: *this);
566
567 case Triple::amdil:
568 case Triple::amdil64:
569 case Triple::hsail:
570 case Triple::hsail64:
571 case Triple::kalimba:
572 case Triple::shave:
573 case Triple::renderscript32:
574 case Triple::renderscript64:
575 // These are all virtual ISAs with no LLVM backend, and therefore no fixed
576 // LLVM data layout.
577 return "";
578
579 case Triple::UnknownArch:
580 return "";
581 }
582 llvm_unreachable("Invalid arch");
583}
584