1//===-- X86TargetParser - Parser for X86 features ---------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements a target parser to recognise X86 hardware features.
10//
11//===----------------------------------------------------------------------===//
12
13#include "llvm/TargetParser/X86TargetParser.h"
14#include "llvm/ADT/Bitset.h"
15#include "llvm/ADT/StringSwitch.h"
16#include <numeric>
17
18using namespace llvm;
19using namespace llvm::X86;
20
21namespace {
22
23using FeatureBitset = Bitset<X86::CPU_FEATURE_MAX>;
24
25struct ProcInfo {
26 StringLiteral Name;
27 X86::CPUKind Kind;
28 unsigned KeyFeature;
29 FeatureBitset Features;
30 char Mangling;
31 bool OnlyForCPUDispatchSpecific;
32};
33
34struct FeatureInfo {
35 StringLiteral NameWithPlus;
36 FeatureBitset ImpliedFeatures;
37
38 StringRef getName(bool WithPlus = false) const {
39 assert(NameWithPlus[0] == '+' && "Expected string to start with '+'");
40 if (WithPlus)
41 return NameWithPlus;
42 return NameWithPlus.drop_front();
43 }
44};
45
46} // end anonymous namespace
47
48#define X86_FEATURE(ENUM, STRING) \
49 constexpr FeatureBitset Feature##ENUM = {X86::FEATURE_##ENUM};
50#include "llvm/TargetParser/X86TargetParser.def"
51
52// Pentium with MMX.
53constexpr FeatureBitset FeaturesPentiumMMX =
54 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX;
55
56// Pentium 2 and 3.
57constexpr FeatureBitset FeaturesPentium2 =
58 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | FeatureFXSR | FeatureCMOV;
59constexpr FeatureBitset FeaturesPentium3 = FeaturesPentium2 | FeatureSSE;
60
61// Pentium 4 CPUs
62constexpr FeatureBitset FeaturesPentium4 = FeaturesPentium3 | FeatureSSE2;
63constexpr FeatureBitset FeaturesPrescott = FeaturesPentium4 | FeatureSSE3;
64constexpr FeatureBitset FeaturesNocona =
65 FeaturesPrescott | Feature64BIT | FeatureCMPXCHG16B;
66
67// Basic 64-bit capable CPU.
68constexpr FeatureBitset FeaturesX86_64 = FeaturesPentium4 | Feature64BIT;
69constexpr FeatureBitset FeaturesX86_64_V2 = FeaturesX86_64 | FeatureSAHF |
70 FeaturePOPCNT | FeatureCRC32 |
71 FeatureSSE4_2 | FeatureCMPXCHG16B;
72constexpr FeatureBitset FeaturesX86_64_V3 =
73 FeaturesX86_64_V2 | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureF16C |
74 FeatureFMA | FeatureLZCNT | FeatureMOVBE | FeatureXSAVE;
75constexpr FeatureBitset FeaturesX86_64_V4 = FeaturesX86_64_V3 |
76 FeatureAVX512BW | FeatureAVX512CD |
77 FeatureAVX512DQ | FeatureAVX512VL;
78
79// Intel Core CPUs
80constexpr FeatureBitset FeaturesCore2 =
81 FeaturesNocona | FeatureSAHF | FeatureSSSE3;
82constexpr FeatureBitset FeaturesPenryn = FeaturesCore2 | FeatureSSE4_1;
83constexpr FeatureBitset FeaturesNehalem =
84 FeaturesPenryn | FeaturePOPCNT | FeatureCRC32 | FeatureSSE4_2;
85constexpr FeatureBitset FeaturesWestmere = FeaturesNehalem | FeaturePCLMUL;
86constexpr FeatureBitset FeaturesSandyBridge =
87 FeaturesWestmere | FeatureAVX | FeatureXSAVE | FeatureXSAVEOPT;
88constexpr FeatureBitset FeaturesIvyBridge =
89 FeaturesSandyBridge | FeatureF16C | FeatureFSGSBASE | FeatureRDRND;
90constexpr FeatureBitset FeaturesHaswell =
91 FeaturesIvyBridge | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureFMA |
92 FeatureINVPCID | FeatureLZCNT | FeatureMOVBE;
93constexpr FeatureBitset FeaturesBroadwell =
94 FeaturesHaswell | FeatureADX | FeaturePRFCHW | FeatureRDSEED;
95
96// Intel Knights Landing and Knights Mill
97// Knights Landing has feature parity with Broadwell.
98constexpr FeatureBitset FeaturesKNL =
99 FeaturesBroadwell | FeatureAES | FeatureAVX512F | FeatureAVX512CD;
100constexpr FeatureBitset FeaturesKNM = FeaturesKNL | FeatureAVX512VPOPCNTDQ;
101
102// Intel Skylake processors.
103constexpr FeatureBitset FeaturesSkylakeClient =
104 FeaturesBroadwell | FeatureAES | FeatureCLFLUSHOPT | FeatureXSAVEC |
105 FeatureXSAVES | FeatureSGX;
106// SkylakeServer inherits all SkylakeClient features except SGX.
107// FIXME: That doesn't match gcc.
108constexpr FeatureBitset FeaturesSkylakeServer =
109 (FeaturesSkylakeClient & ~FeatureSGX) | FeatureAVX512F | FeatureAVX512CD |
110 FeatureAVX512DQ | FeatureAVX512BW | FeatureAVX512VL | FeatureCLWB |
111 FeaturePKU;
112constexpr FeatureBitset FeaturesCascadeLake =
113 FeaturesSkylakeServer | FeatureAVX512VNNI;
114constexpr FeatureBitset FeaturesCooperLake =
115 FeaturesCascadeLake | FeatureAVX512BF16;
116
117// Intel 10nm processors.
118constexpr FeatureBitset FeaturesCannonlake =
119 FeaturesSkylakeClient | FeatureAVX512F | FeatureAVX512CD | FeatureAVX512DQ |
120 FeatureAVX512BW | FeatureAVX512VL | FeatureAVX512IFMA | FeatureAVX512VBMI |
121 FeaturePKU | FeatureSHA;
122constexpr FeatureBitset FeaturesICLClient =
123 FeaturesCannonlake | FeatureAVX512BITALG | FeatureAVX512VBMI2 |
124 FeatureAVX512VNNI | FeatureAVX512VPOPCNTDQ | FeatureGFNI | FeatureRDPID |
125 FeatureVAES | FeatureVPCLMULQDQ;
126constexpr FeatureBitset FeaturesRocketlake = FeaturesICLClient & ~FeatureSGX;
127constexpr FeatureBitset FeaturesICLServer =
128 FeaturesICLClient | FeatureCLWB | FeaturePCONFIG | FeatureWBNOINVD;
129constexpr FeatureBitset FeaturesTigerlake =
130 FeaturesICLClient | FeatureAVX512VP2INTERSECT | FeatureMOVDIR64B |
131 FeatureCLWB | FeatureMOVDIRI | FeatureSHSTK | FeatureKL | FeatureWIDEKL;
132constexpr FeatureBitset FeaturesSapphireRapids =
133 FeaturesICLServer | FeatureAMX_BF16 | FeatureAMX_INT8 | FeatureAMX_TILE |
134 FeatureAVX512BF16 | FeatureAVX512FP16 | FeatureAVXVNNI | FeatureCLDEMOTE |
135 FeatureENQCMD | FeatureMOVDIR64B | FeatureMOVDIRI | FeaturePTWRITE |
136 FeatureSERIALIZE | FeatureSHSTK | FeatureTSXLDTRK | FeatureUINTR |
137 FeatureWAITPKG | FeatureAVX512DQ | FeatureAVX512VL;
138constexpr FeatureBitset FeaturesGraniteRapids =
139 FeaturesSapphireRapids | FeatureAMX_FP16 | FeaturePREFETCHI;
140constexpr FeatureBitset FeaturesDiamondRapids =
141 FeaturesGraniteRapids | FeatureAMX_COMPLEX | FeatureAVX10_2 |
142 FeatureCMPCCXADD | FeatureAVXIFMA | FeatureAVXNECONVERT |
143 FeatureAVXVNNIINT8 | FeatureAVXVNNIINT16 | FeatureSHA512 | FeatureSM3 |
144 FeatureSM4 | FeatureEGPR | FeatureZU | FeatureCCMP | FeaturePush2Pop2 |
145 FeaturePPX | FeatureNDD | FeatureNF | FeatureMOVRS | FeatureAMX_MOVRS |
146 FeatureAMX_AVX512 | FeatureAMX_FP8 | FeatureAMX_TF32;
147
148// Intel Atom processors.
149// Bonnell has feature parity with Core2 and adds MOVBE.
150constexpr FeatureBitset FeaturesBonnell = FeaturesCore2 | FeatureMOVBE;
151// Silvermont has parity with Westmere and Bonnell plus PRFCHW and RDRND.
152constexpr FeatureBitset FeaturesSilvermont =
153 FeaturesBonnell | FeaturesWestmere | FeaturePRFCHW | FeatureRDRND;
154constexpr FeatureBitset FeaturesGoldmont =
155 FeaturesSilvermont | FeatureAES | FeatureCLFLUSHOPT | FeatureFSGSBASE |
156 FeatureRDSEED | FeatureSHA | FeatureXSAVE | FeatureXSAVEC |
157 FeatureXSAVEOPT | FeatureXSAVES;
158constexpr FeatureBitset FeaturesGoldmontPlus =
159 FeaturesGoldmont | FeaturePTWRITE | FeatureRDPID | FeatureSGX;
160constexpr FeatureBitset FeaturesTremont =
161 FeaturesGoldmontPlus | FeatureCLWB | FeatureGFNI;
162constexpr FeatureBitset FeaturesAlderlake =
163 FeaturesTremont | FeatureADX | FeatureBMI | FeatureBMI2 | FeatureF16C |
164 FeatureFMA | FeatureINVPCID | FeatureLZCNT | FeaturePCONFIG | FeaturePKU |
165 FeatureSERIALIZE | FeatureSHSTK | FeatureVAES | FeatureVPCLMULQDQ |
166 FeatureMOVDIR64B | FeatureMOVDIRI | FeatureWAITPKG | FeatureAVXVNNI |
167 FeatureHRESET | FeatureWIDEKL;
168constexpr FeatureBitset FeaturesArrowlake =
169 FeaturesAlderlake | FeatureCMPCCXADD | FeatureAVXIFMA | FeatureUINTR |
170 FeatureENQCMD | FeatureAVXNECONVERT | FeatureAVXVNNIINT8;
171constexpr FeatureBitset FeaturesSierraforest =
172 FeaturesArrowlake | FeatureCLDEMOTE;
173constexpr FeatureBitset FeaturesArrowlakeS =
174 FeaturesArrowlake | FeatureAVXVNNIINT16 | FeatureSHA512 | FeatureSM3 |
175 FeatureSM4;
176constexpr FeatureBitset FeaturesPantherlake =
177 (FeaturesArrowlakeS ^ FeatureWIDEKL);
178constexpr FeatureBitset FeaturesNovalake =
179 FeaturesPantherlake | FeaturePREFETCHI | FeatureAVX10_2 | FeatureMOVRS |
180 FeatureEGPR | FeatureZU | FeatureCCMP | FeaturePush2Pop2 | FeaturePPX |
181 FeatureNDD | FeatureNF;
182constexpr FeatureBitset FeaturesClearwaterforest =
183 (FeaturesSierraforest ^ FeatureWIDEKL) | FeatureAVXVNNIINT16 |
184 FeatureSHA512 | FeatureSM3 | FeatureSM4 | FeaturePREFETCHI | FeatureUSERMSR;
185
186// Geode Processor.
187constexpr FeatureBitset FeaturesGeode =
188 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | FeaturePRFCHW;
189
190// K6 processor.
191constexpr FeatureBitset FeaturesK6 = FeatureX87 | FeatureCMPXCHG8B | FeatureMMX;
192
193// K7 and K8 architecture processors.
194constexpr FeatureBitset FeaturesAthlon =
195 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | FeaturePRFCHW;
196constexpr FeatureBitset FeaturesAthlonXP =
197 FeaturesAthlon | FeatureFXSR | FeatureSSE;
198constexpr FeatureBitset FeaturesK8 =
199 FeaturesAthlonXP | FeatureSSE2 | Feature64BIT;
200constexpr FeatureBitset FeaturesK8SSE3 = FeaturesK8 | FeatureSSE3;
201constexpr FeatureBitset FeaturesAMDFAM10 =
202 FeaturesK8SSE3 | FeatureCMPXCHG16B | FeatureLZCNT | FeaturePOPCNT |
203 FeaturePRFCHW | FeatureSAHF | FeatureSSE4_A;
204
205// Bobcat architecture processors.
206constexpr FeatureBitset FeaturesBTVER1 =
207 FeatureX87 | FeatureCMPXCHG8B | FeatureCMPXCHG16B | Feature64BIT |
208 FeatureFXSR | FeatureLZCNT | FeatureMMX | FeaturePOPCNT | FeaturePRFCHW |
209 FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_A |
210 FeatureSAHF;
211constexpr FeatureBitset FeaturesBTVER2 =
212 FeaturesBTVER1 | FeatureAES | FeatureAVX | FeatureBMI | FeatureCRC32 |
213 FeatureF16C | FeatureMOVBE | FeaturePCLMUL | FeatureXSAVE | FeatureXSAVEOPT;
214
215// AMD Bulldozer architecture processors.
216constexpr FeatureBitset FeaturesBDVER1 =
217 FeatureX87 | FeatureAES | FeatureAVX | FeatureCMPXCHG8B |
218 FeatureCMPXCHG16B | FeatureCRC32 | Feature64BIT | FeatureFMA4 |
219 FeatureFXSR | FeatureLWP | FeatureLZCNT | FeatureMMX | FeaturePCLMUL |
220 FeaturePOPCNT | FeaturePRFCHW | FeatureSAHF | FeatureSSE | FeatureSSE2 |
221 FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_1 | FeatureSSE4_2 | FeatureSSE4_A |
222 FeatureXOP | FeatureXSAVE;
223constexpr FeatureBitset FeaturesBDVER2 =
224 FeaturesBDVER1 | FeatureBMI | FeatureFMA | FeatureF16C | FeatureTBM;
225constexpr FeatureBitset FeaturesBDVER3 =
226 FeaturesBDVER2 | FeatureFSGSBASE | FeatureXSAVEOPT;
227constexpr FeatureBitset FeaturesBDVER4 = FeaturesBDVER3 | FeatureAVX2 |
228 FeatureBMI2 | FeatureMOVBE |
229 FeatureMWAITX | FeatureRDRND;
230
231// AMD Zen architecture processors.
232constexpr FeatureBitset FeaturesZNVER1 =
233 FeatureX87 | FeatureADX | FeatureAES | FeatureAVX | FeatureAVX2 |
234 FeatureBMI | FeatureBMI2 | FeatureCLFLUSHOPT | FeatureCLZERO |
235 FeatureCMPXCHG8B | FeatureCMPXCHG16B | FeatureCRC32 | Feature64BIT |
236 FeatureF16C | FeatureFMA | FeatureFSGSBASE | FeatureFXSR | FeatureLZCNT |
237 FeatureMMX | FeatureMOVBE | FeatureMWAITX | FeaturePCLMUL | FeaturePOPCNT |
238 FeaturePRFCHW | FeatureRDRND | FeatureRDSEED | FeatureSAHF | FeatureSHA |
239 FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_1 |
240 FeatureSSE4_2 | FeatureSSE4_A | FeatureXSAVE | FeatureXSAVEC |
241 FeatureXSAVEOPT | FeatureXSAVES;
242constexpr FeatureBitset FeaturesZNVER2 = FeaturesZNVER1 | FeatureCLWB |
243 FeatureRDPID | FeatureRDPRU |
244 FeatureWBNOINVD;
245static constexpr FeatureBitset FeaturesZNVER3 = FeaturesZNVER2 |
246 FeatureINVPCID | FeaturePKU |
247 FeatureVAES | FeatureVPCLMULQDQ;
248static constexpr FeatureBitset FeaturesZNVER4 =
249 FeaturesZNVER3 | FeatureAVX512F | FeatureAVX512CD | FeatureAVX512DQ |
250 FeatureAVX512BW | FeatureAVX512VL | FeatureAVX512IFMA | FeatureAVX512VBMI |
251 FeatureAVX512VBMI2 | FeatureAVX512VNNI | FeatureAVX512BITALG |
252 FeatureAVX512VPOPCNTDQ | FeatureAVX512BF16 | FeatureGFNI | FeatureSHSTK;
253
254static constexpr FeatureBitset FeaturesZNVER5 =
255 FeaturesZNVER4 | FeatureAVXVNNI | FeatureMOVDIRI | FeatureMOVDIR64B |
256 FeatureAVX512VP2INTERSECT | FeaturePREFETCHI | FeatureAVXVNNI;
257
258// D151696 tranplanted Mangling and OnlyForCPUDispatchSpecific from
259// X86TargetParser.def to here. They are assigned by following ways:
260// 1. Copy the mangling from the original CPU_SPEICIFC MACROs. If no, assign
261// to '\0' by default, which means not support cpu_specific/dispatch feature.
262// 2. set OnlyForCPUDispatchSpecific as true if this cpu name was not
263// listed here before, which means it doesn't support -march, -mtune and so on.
264// FIXME: Remove OnlyForCPUDispatchSpecific after all CPUs here support both
265// cpu_dispatch/specific() feature and -march, -mtune, and so on.
266// clang-format off
267constexpr ProcInfo Processors[] = {
268 // Empty processor. Include X87 and CMPXCHG8 for backwards compatibility.
269 { .Name: {""}, .Kind: CK_None, .KeyFeature: ~0U, .Features: FeatureX87 | FeatureCMPXCHG8B, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false },
270 { .Name: {"generic"}, .Kind: CK_None, .KeyFeature: ~0U, .Features: FeatureX87 | FeatureCMPXCHG8B | Feature64BIT, .Mangling: 'A', .OnlyForCPUDispatchSpecific: true },
271 // i386-generation processors.
272 { .Name: {"i386"}, .Kind: CK_i386, .KeyFeature: ~0U, .Features: FeatureX87, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false },
273 // i486-generation processors.
274 { .Name: {"i486"}, .Kind: CK_i486, .KeyFeature: ~0U, .Features: FeatureX87, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false },
275 { .Name: {"winchip-c6"}, .Kind: CK_WinChipC6, .KeyFeature: ~0U, .Features: FeaturesPentiumMMX, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false },
276 { .Name: {"winchip2"}, .Kind: CK_WinChip2, .KeyFeature: ~0U, .Features: FeaturesPentiumMMX | FeaturePRFCHW, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false },
277 { .Name: {"c3"}, .Kind: CK_C3, .KeyFeature: ~0U, .Features: FeaturesPentiumMMX | FeaturePRFCHW, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false },
278 // i586-generation processors, P5 microarchitecture based.
279 { .Name: {"i586"}, .Kind: CK_i586, .KeyFeature: ~0U, .Features: FeatureX87 | FeatureCMPXCHG8B, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false },
280 { .Name: {"pentium"}, .Kind: CK_Pentium, .KeyFeature: ~0U, .Features: FeatureX87 | FeatureCMPXCHG8B, .Mangling: 'B', .OnlyForCPUDispatchSpecific: false },
281 { .Name: {"pentium-mmx"}, .Kind: CK_PentiumMMX, .KeyFeature: ~0U, .Features: FeaturesPentiumMMX, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false },
282 { .Name: {"pentium_mmx"}, .Kind: CK_PentiumMMX, .KeyFeature: ~0U, .Features: FeaturesPentiumMMX, .Mangling: 'D', .OnlyForCPUDispatchSpecific: true },
283 // i686-generation processors, P6 / Pentium M microarchitecture based.
284 { .Name: {"pentiumpro"}, .Kind: CK_PentiumPro, .KeyFeature: ~0U, .Features: FeatureCMOV | FeatureX87 | FeatureCMPXCHG8B, .Mangling: 'C', .OnlyForCPUDispatchSpecific: false },
285 { .Name: {"pentium_pro"}, .Kind: CK_PentiumPro, .KeyFeature: ~0U, .Features: FeatureCMOV | FeatureX87 | FeatureCMPXCHG8B, .Mangling: 'C', .OnlyForCPUDispatchSpecific: true },
286 { .Name: {"i686"}, .Kind: CK_i686, .KeyFeature: ~0U, .Features: FeatureCMOV | FeatureX87 | FeatureCMPXCHG8B, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false },
287 { .Name: {"pentium2"}, .Kind: CK_Pentium2, .KeyFeature: ~0U, .Features: FeaturesPentium2, .Mangling: 'E', .OnlyForCPUDispatchSpecific: false },
288 { .Name: {"pentium_ii"}, .Kind: CK_Pentium2, .KeyFeature: ~0U, .Features: FeaturesPentium2, .Mangling: 'E', .OnlyForCPUDispatchSpecific: true },
289 { .Name: {"pentium3"}, .Kind: CK_Pentium3, .KeyFeature: ~0U, .Features: FeaturesPentium3, .Mangling: 'H', .OnlyForCPUDispatchSpecific: false },
290 { .Name: {"pentium3m"}, .Kind: CK_Pentium3, .KeyFeature: ~0U, .Features: FeaturesPentium3, .Mangling: 'H', .OnlyForCPUDispatchSpecific: false },
291 { .Name: {"pentium_iii"}, .Kind: CK_Pentium3, .KeyFeature: ~0U, .Features: FeaturesPentium3, .Mangling: 'H', .OnlyForCPUDispatchSpecific: true },
292 { .Name: {"pentium_iii_no_xmm_regs"}, .Kind: CK_Pentium3, .KeyFeature: ~0U, .Features: FeaturesPentium3, .Mangling: 'H', .OnlyForCPUDispatchSpecific: true },
293 { .Name: {"pentium-m"}, .Kind: CK_PentiumM, .KeyFeature: ~0U, .Features: FeaturesPentium4, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false },
294 { .Name: {"pentium_m"}, .Kind: CK_PentiumM, .KeyFeature: ~0U, .Features: FeaturesPentium4, .Mangling: 'K', .OnlyForCPUDispatchSpecific: true },
295 { .Name: {"c3-2"}, .Kind: CK_C3_2, .KeyFeature: ~0U, .Features: FeaturesPentium3, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false },
296 { .Name: {"yonah"}, .Kind: CK_Yonah, .KeyFeature: ~0U, .Features: FeaturesPrescott, .Mangling: 'L', .OnlyForCPUDispatchSpecific: false },
297 // Netburst microarchitecture based processors.
298 { .Name: {"pentium4"}, .Kind: CK_Pentium4, .KeyFeature: ~0U, .Features: FeaturesPentium4, .Mangling: 'J', .OnlyForCPUDispatchSpecific: false },
299 { .Name: {"pentium4m"}, .Kind: CK_Pentium4, .KeyFeature: ~0U, .Features: FeaturesPentium4, .Mangling: 'J', .OnlyForCPUDispatchSpecific: false },
300 { .Name: {"pentium_4"}, .Kind: CK_Pentium4, .KeyFeature: ~0U, .Features: FeaturesPentium4, .Mangling: 'J', .OnlyForCPUDispatchSpecific: true },
301 { .Name: {"pentium_4_sse3"}, .Kind: CK_Prescott, .KeyFeature: ~0U, .Features: FeaturesPrescott, .Mangling: 'L', .OnlyForCPUDispatchSpecific: true },
302 { .Name: {"prescott"}, .Kind: CK_Prescott, .KeyFeature: ~0U, .Features: FeaturesPrescott, .Mangling: 'L', .OnlyForCPUDispatchSpecific: false },
303 { .Name: {"nocona"}, .Kind: CK_Nocona, .KeyFeature: ~0U, .Features: FeaturesNocona, .Mangling: 'L', .OnlyForCPUDispatchSpecific: false },
304 // Core microarchitecture based processors.
305 { .Name: {"core2"}, .Kind: CK_Core2, .KeyFeature: FEATURE_SSSE3, .Features: FeaturesCore2, .Mangling: 'M', .OnlyForCPUDispatchSpecific: false },
306 { .Name: {"core_2_duo_ssse3"}, .Kind: CK_Core2, .KeyFeature: ~0U, .Features: FeaturesCore2, .Mangling: 'M', .OnlyForCPUDispatchSpecific: true },
307 { .Name: {"penryn"}, .Kind: CK_Penryn, .KeyFeature: ~0U, .Features: FeaturesPenryn, .Mangling: 'N', .OnlyForCPUDispatchSpecific: false },
308 { .Name: {"core_2_duo_sse4_1"}, .Kind: CK_Penryn, .KeyFeature: ~0U, .Features: FeaturesPenryn, .Mangling: 'N', .OnlyForCPUDispatchSpecific: true },
309 // Atom processors
310 { .Name: {"bonnell"}, .Kind: CK_Bonnell, .KeyFeature: FEATURE_SSSE3, .Features: FeaturesBonnell, .Mangling: 'O', .OnlyForCPUDispatchSpecific: false },
311 { .Name: {"atom"}, .Kind: CK_Bonnell, .KeyFeature: FEATURE_SSSE3, .Features: FeaturesBonnell, .Mangling: 'O', .OnlyForCPUDispatchSpecific: false },
312 { .Name: {"silvermont"}, .Kind: CK_Silvermont, .KeyFeature: FEATURE_SSE4_2, .Features: FeaturesSilvermont, .Mangling: 'c', .OnlyForCPUDispatchSpecific: false },
313 { .Name: {"slm"}, .Kind: CK_Silvermont, .KeyFeature: FEATURE_SSE4_2, .Features: FeaturesSilvermont, .Mangling: 'c', .OnlyForCPUDispatchSpecific: false },
314 { .Name: {"atom_sse4_2"}, .Kind: CK_Nehalem, .KeyFeature: FEATURE_SSE4_2, .Features: FeaturesNehalem, .Mangling: 'c', .OnlyForCPUDispatchSpecific: true },
315 { .Name: {"atom_sse4_2_movbe"}, .Kind: CK_Goldmont, .KeyFeature: FEATURE_SSE4_2, .Features: FeaturesGoldmont, .Mangling: 'd', .OnlyForCPUDispatchSpecific: true },
316 { .Name: {"goldmont"}, .Kind: CK_Goldmont, .KeyFeature: FEATURE_SSE4_2, .Features: FeaturesGoldmont, .Mangling: 'i', .OnlyForCPUDispatchSpecific: false },
317 { .Name: {"goldmont-plus"}, .Kind: CK_GoldmontPlus, .KeyFeature: FEATURE_SSE4_2, .Features: FeaturesGoldmontPlus, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false },
318 { .Name: {"goldmont_plus"}, .Kind: CK_GoldmontPlus, .KeyFeature: FEATURE_SSE4_2, .Features: FeaturesGoldmontPlus, .Mangling: 'd', .OnlyForCPUDispatchSpecific: true },
319 { .Name: {"tremont"}, .Kind: CK_Tremont, .KeyFeature: FEATURE_SSE4_2, .Features: FeaturesTremont, .Mangling: 'd', .OnlyForCPUDispatchSpecific: false },
320 // Nehalem microarchitecture based processors.
321 { .Name: {"nehalem"}, .Kind: CK_Nehalem, .KeyFeature: FEATURE_SSE4_2, .Features: FeaturesNehalem, .Mangling: 'P', .OnlyForCPUDispatchSpecific: false },
322 { .Name: {"core_i7_sse4_2"}, .Kind: CK_Nehalem, .KeyFeature: FEATURE_SSE4_2, .Features: FeaturesNehalem, .Mangling: 'P', .OnlyForCPUDispatchSpecific: true },
323 { .Name: {"corei7"}, .Kind: CK_Nehalem, .KeyFeature: FEATURE_SSE4_2, .Features: FeaturesNehalem, .Mangling: 'P', .OnlyForCPUDispatchSpecific: false },
324 // Westmere microarchitecture based processors.
325 { .Name: {"westmere"}, .Kind: CK_Westmere, .KeyFeature: FEATURE_PCLMUL, .Features: FeaturesWestmere, .Mangling: 'Q', .OnlyForCPUDispatchSpecific: false },
326 { .Name: {"core_aes_pclmulqdq"}, .Kind: CK_Nehalem, .KeyFeature: FEATURE_SSE4_2, .Features: FeaturesNehalem, .Mangling: 'Q', .OnlyForCPUDispatchSpecific: true },
327 // Sandy Bridge microarchitecture based processors.
328 { .Name: {"sandybridge"}, .Kind: CK_SandyBridge, .KeyFeature: FEATURE_AVX, .Features: FeaturesSandyBridge, .Mangling: 'R', .OnlyForCPUDispatchSpecific: false },
329 { .Name: {"core_2nd_gen_avx"}, .Kind: CK_SandyBridge, .KeyFeature: FEATURE_AVX, .Features: FeaturesSandyBridge, .Mangling: 'R', .OnlyForCPUDispatchSpecific: true },
330 { .Name: {"corei7-avx"}, .Kind: CK_SandyBridge, .KeyFeature: FEATURE_AVX, .Features: FeaturesSandyBridge, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false },
331 // Ivy Bridge microarchitecture based processors.
332 { .Name: {"ivybridge"}, .Kind: CK_IvyBridge, .KeyFeature: FEATURE_AVX, .Features: FeaturesIvyBridge, .Mangling: 'S', .OnlyForCPUDispatchSpecific: false },
333 { .Name: {"core_3rd_gen_avx"}, .Kind: CK_IvyBridge, .KeyFeature: FEATURE_AVX, .Features: FeaturesIvyBridge, .Mangling: 'S', .OnlyForCPUDispatchSpecific: true },
334 { .Name: {"core-avx-i"}, .Kind: CK_IvyBridge, .KeyFeature: FEATURE_AVX, .Features: FeaturesIvyBridge, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false },
335 // Haswell microarchitecture based processors.
336 { .Name: {"haswell"}, .Kind: CK_Haswell, .KeyFeature: FEATURE_AVX2, .Features: FeaturesHaswell, .Mangling: 'V', .OnlyForCPUDispatchSpecific: false },
337 { .Name: {"core-avx2"}, .Kind: CK_Haswell, .KeyFeature: FEATURE_AVX2, .Features: FeaturesHaswell, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false },
338 { .Name: {"core_4th_gen_avx"}, .Kind: CK_Haswell, .KeyFeature: FEATURE_AVX2, .Features: FeaturesHaswell, .Mangling: 'V', .OnlyForCPUDispatchSpecific: true },
339 { .Name: {"core_4th_gen_avx_tsx"}, .Kind: CK_Haswell, .KeyFeature: FEATURE_AVX2, .Features: FeaturesHaswell, .Mangling: 'W', .OnlyForCPUDispatchSpecific: true },
340 // Broadwell microarchitecture based processors.
341 { .Name: {"broadwell"}, .Kind: CK_Broadwell, .KeyFeature: FEATURE_AVX2, .Features: FeaturesBroadwell, .Mangling: 'X', .OnlyForCPUDispatchSpecific: false },
342 { .Name: {"core_5th_gen_avx"}, .Kind: CK_Broadwell, .KeyFeature: FEATURE_AVX2, .Features: FeaturesBroadwell, .Mangling: 'X', .OnlyForCPUDispatchSpecific: true },
343 { .Name: {"core_5th_gen_avx_tsx"}, .Kind: CK_Broadwell, .KeyFeature: FEATURE_AVX2, .Features: FeaturesBroadwell, .Mangling: 'Y', .OnlyForCPUDispatchSpecific: true },
344 // Skylake client microarchitecture based processors.
345 { .Name: {"skylake"}, .Kind: CK_SkylakeClient, .KeyFeature: FEATURE_AVX2, .Features: FeaturesSkylakeClient, .Mangling: 'b', .OnlyForCPUDispatchSpecific: false },
346 // Skylake server microarchitecture based processors.
347 { .Name: {"skylake-avx512"}, .Kind: CK_SkylakeServer, .KeyFeature: FEATURE_AVX512F, .Features: FeaturesSkylakeServer, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false },
348 { .Name: {"skx"}, .Kind: CK_SkylakeServer, .KeyFeature: FEATURE_AVX512F, .Features: FeaturesSkylakeServer, .Mangling: 'a', .OnlyForCPUDispatchSpecific: false },
349 { .Name: {"skylake_avx512"}, .Kind: CK_SkylakeServer, .KeyFeature: FEATURE_AVX512F, .Features: FeaturesSkylakeServer, .Mangling: 'a', .OnlyForCPUDispatchSpecific: true },
350 // Cascadelake Server microarchitecture based processors.
351 { .Name: {"cascadelake"}, .Kind: CK_Cascadelake, .KeyFeature: FEATURE_AVX512VNNI, .Features: FeaturesCascadeLake, .Mangling: 'o', .OnlyForCPUDispatchSpecific: false },
352 // Cooperlake Server microarchitecture based processors.
353 { .Name: {"cooperlake"}, .Kind: CK_Cooperlake, .KeyFeature: FEATURE_AVX512BF16, .Features: FeaturesCooperLake, .Mangling: 'f', .OnlyForCPUDispatchSpecific: false },
354 // Cannonlake client microarchitecture based processors.
355 { .Name: {"cannonlake"}, .Kind: CK_Cannonlake, .KeyFeature: FEATURE_AVX512VBMI, .Features: FeaturesCannonlake, .Mangling: 'e', .OnlyForCPUDispatchSpecific: false },
356 // Icelake client microarchitecture based processors.
357 { .Name: {"icelake-client"}, .Kind: CK_IcelakeClient, .KeyFeature: FEATURE_AVX512VBMI2, .Features: FeaturesICLClient, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false },
358 { .Name: {"icelake_client"}, .Kind: CK_IcelakeClient, .KeyFeature: FEATURE_AVX512VBMI2, .Features: FeaturesICLClient, .Mangling: 'k', .OnlyForCPUDispatchSpecific: true },
359 // Rocketlake microarchitecture based processors.
360 { .Name: {"rocketlake"}, .Kind: CK_Rocketlake, .KeyFeature: FEATURE_AVX512VBMI2, .Features: FeaturesRocketlake, .Mangling: 'k', .OnlyForCPUDispatchSpecific: false },
361 // Icelake server microarchitecture based processors.
362 { .Name: {"icelake-server"}, .Kind: CK_IcelakeServer, .KeyFeature: FEATURE_AVX512VBMI2, .Features: FeaturesICLServer, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false },
363 { .Name: {"icelake_server"}, .Kind: CK_IcelakeServer, .KeyFeature: FEATURE_AVX512VBMI2, .Features: FeaturesICLServer, .Mangling: 'k', .OnlyForCPUDispatchSpecific: true },
364 // Tigerlake microarchitecture based processors.
365 { .Name: {"tigerlake"}, .Kind: CK_Tigerlake, .KeyFeature: FEATURE_AVX512VP2INTERSECT, .Features: FeaturesTigerlake, .Mangling: 'l', .OnlyForCPUDispatchSpecific: false },
366 // Sapphire Rapids microarchitecture based processors.
367 { .Name: {"sapphirerapids"}, .Kind: CK_SapphireRapids, .KeyFeature: FEATURE_AVX512FP16, .Features: FeaturesSapphireRapids, .Mangling: 'n', .OnlyForCPUDispatchSpecific: false },
368 // Alderlake microarchitecture based processors.
369 { .Name: {"alderlake"}, .Kind: CK_Alderlake, .KeyFeature: FEATURE_AVX2, .Features: FeaturesAlderlake, .Mangling: 'p', .OnlyForCPUDispatchSpecific: false },
370 // Raptorlake microarchitecture based processors.
371 { .Name: {"raptorlake"}, .Kind: CK_Raptorlake, .KeyFeature: FEATURE_AVX2, .Features: FeaturesAlderlake, .Mangling: 'p', .OnlyForCPUDispatchSpecific: false },
372 // Meteorlake microarchitecture based processors.
373 { .Name: {"meteorlake"}, .Kind: CK_Meteorlake, .KeyFeature: FEATURE_AVX2, .Features: FeaturesAlderlake, .Mangling: 'p', .OnlyForCPUDispatchSpecific: false },
374 // Arrowlake microarchitecture based processors.
375 { .Name: {"arrowlake"}, .Kind: CK_Arrowlake, .KeyFeature: FEATURE_AVX2, .Features: FeaturesArrowlake, .Mangling: 'p', .OnlyForCPUDispatchSpecific: false },
376 { .Name: {"arrowlake-s"}, .Kind: CK_ArrowlakeS, .KeyFeature: FEATURE_AVX2, .Features: FeaturesArrowlakeS, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false },
377 { .Name: {"arrowlake_s"}, .Kind: CK_ArrowlakeS, .KeyFeature: FEATURE_AVX2, .Features: FeaturesArrowlakeS, .Mangling: 'p', .OnlyForCPUDispatchSpecific: true },
378 // Lunarlake microarchitecture based processors.
379 { .Name: {"lunarlake"}, .Kind: CK_Lunarlake, .KeyFeature: FEATURE_AVX2, .Features: FeaturesArrowlakeS, .Mangling: 'p', .OnlyForCPUDispatchSpecific: false },
380 // Gracemont microarchitecture based processors.
381 { .Name: {"gracemont"}, .Kind: CK_Gracemont, .KeyFeature: FEATURE_AVX2, .Features: FeaturesAlderlake, .Mangling: 'p', .OnlyForCPUDispatchSpecific: false },
382 // Pantherlake microarchitecture based processors.
383 { .Name: {"pantherlake"}, .Kind: CK_Lunarlake, .KeyFeature: FEATURE_AVX2, .Features: FeaturesPantherlake, .Mangling: 'p', .OnlyForCPUDispatchSpecific: false },
384 { .Name: {"wildcatlake"}, .Kind: CK_Lunarlake, .KeyFeature: FEATURE_AVX2, .Features: FeaturesPantherlake, .Mangling: 'p', .OnlyForCPUDispatchSpecific: false },
385 // Novalake microarchitecture based processors.
386 { .Name: {"novalake"}, .Kind: CK_Novalake, .KeyFeature: FEATURE_AVX2, .Features: FeaturesNovalake, .Mangling: 'r', .OnlyForCPUDispatchSpecific: false },
387 // Sierraforest microarchitecture based processors.
388 { .Name: {"sierraforest"}, .Kind: CK_Sierraforest, .KeyFeature: FEATURE_AVX2, .Features: FeaturesSierraforest, .Mangling: 'p', .OnlyForCPUDispatchSpecific: false },
389 // Grandridge microarchitecture based processors.
390 { .Name: {"grandridge"}, .Kind: CK_Grandridge, .KeyFeature: FEATURE_AVX2, .Features: FeaturesSierraforest, .Mangling: 'p', .OnlyForCPUDispatchSpecific: false },
391 // Granite Rapids microarchitecture based processors.
392 { .Name: {"graniterapids"}, .Kind: CK_Graniterapids, .KeyFeature: FEATURE_AVX512FP16, .Features: FeaturesGraniteRapids, .Mangling: 'n', .OnlyForCPUDispatchSpecific: false },
393 // Granite Rapids D microarchitecture based processors.
394 { .Name: {"graniterapids-d"}, .Kind: CK_GraniterapidsD, .KeyFeature: FEATURE_AVX512FP16, .Features: FeaturesGraniteRapids | FeatureAMX_COMPLEX, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false },
395 { .Name: {"graniterapids_d"}, .Kind: CK_GraniterapidsD, .KeyFeature: FEATURE_AVX512FP16, .Features: FeaturesGraniteRapids | FeatureAMX_COMPLEX, .Mangling: 'n', .OnlyForCPUDispatchSpecific: true },
396 // Emerald Rapids microarchitecture based processors.
397 { .Name: {"emeraldrapids"}, .Kind: CK_Emeraldrapids, .KeyFeature: FEATURE_AVX512FP16, .Features: FeaturesSapphireRapids, .Mangling: 'n', .OnlyForCPUDispatchSpecific: false },
398 // Clearwaterforest microarchitecture based processors.
399 { .Name: {"clearwaterforest"}, .Kind: CK_Lunarlake, .KeyFeature: FEATURE_AVX2, .Features: FeaturesClearwaterforest, .Mangling: 'p', .OnlyForCPUDispatchSpecific: false },
400 // Diamond Rapids microarchitecture based processors.
401 { .Name: {"diamondrapids"}, .Kind: CK_Diamondrapids, .KeyFeature: FEATURE_AVX10_2, .Features: FeaturesDiamondRapids, .Mangling: 'z', .OnlyForCPUDispatchSpecific: false },
402 // Knights Landing processor.
403 { .Name: {"knl"}, .Kind: CK_KNL, .KeyFeature: FEATURE_AVX512F, .Features: FeaturesKNL, .Mangling: 'Z', .OnlyForCPUDispatchSpecific: false },
404 { .Name: {"mic_avx512"}, .Kind: CK_KNL, .KeyFeature: FEATURE_AVX512F, .Features: FeaturesKNL, .Mangling: 'Z', .OnlyForCPUDispatchSpecific: true },
405 // Knights Mill processor.
406 { .Name: {"knm"}, .Kind: CK_KNM, .KeyFeature: FEATURE_AVX5124FMAPS, .Features: FeaturesKNM, .Mangling: 'j', .OnlyForCPUDispatchSpecific: false },
407 // Lakemont microarchitecture based processors.
408 { .Name: {"lakemont"}, .Kind: CK_Lakemont, .KeyFeature: ~0U, .Features: FeatureCMPXCHG8B, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false },
409 // K6 architecture processors.
410 { .Name: {"k6"}, .Kind: CK_K6, .KeyFeature: ~0U, .Features: FeaturesK6, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false },
411 { .Name: {"k6-2"}, .Kind: CK_K6_2, .KeyFeature: ~0U, .Features: FeaturesK6 | FeaturePRFCHW, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false },
412 { .Name: {"k6-3"}, .Kind: CK_K6_3, .KeyFeature: ~0U, .Features: FeaturesK6 | FeaturePRFCHW, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false },
413 // K7 architecture processors.
414 { .Name: {"athlon"}, .Kind: CK_Athlon, .KeyFeature: ~0U, .Features: FeaturesAthlon, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false },
415 { .Name: {"athlon-tbird"}, .Kind: CK_Athlon, .KeyFeature: ~0U, .Features: FeaturesAthlon, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false },
416 { .Name: {"athlon-xp"}, .Kind: CK_AthlonXP, .KeyFeature: ~0U, .Features: FeaturesAthlonXP, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false },
417 { .Name: {"athlon-mp"}, .Kind: CK_AthlonXP, .KeyFeature: ~0U, .Features: FeaturesAthlonXP, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false },
418 { .Name: {"athlon-4"}, .Kind: CK_AthlonXP, .KeyFeature: ~0U, .Features: FeaturesAthlonXP, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false },
419 // K8 architecture processors.
420 { .Name: {"k8"}, .Kind: CK_K8, .KeyFeature: ~0U, .Features: FeaturesK8, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false },
421 { .Name: {"athlon64"}, .Kind: CK_K8, .KeyFeature: ~0U, .Features: FeaturesK8, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false },
422 { .Name: {"athlon-fx"}, .Kind: CK_K8, .KeyFeature: ~0U, .Features: FeaturesK8, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false },
423 { .Name: {"opteron"}, .Kind: CK_K8, .KeyFeature: ~0U, .Features: FeaturesK8, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false },
424 { .Name: {"k8-sse3"}, .Kind: CK_K8SSE3, .KeyFeature: ~0U, .Features: FeaturesK8SSE3, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false },
425 { .Name: {"athlon64-sse3"}, .Kind: CK_K8SSE3, .KeyFeature: ~0U, .Features: FeaturesK8SSE3, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false },
426 { .Name: {"opteron-sse3"}, .Kind: CK_K8SSE3, .KeyFeature: ~0U, .Features: FeaturesK8SSE3, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false },
427 { .Name: {"amdfam10"}, .Kind: CK_AMDFAM10, .KeyFeature: FEATURE_SSE4_A, .Features: FeaturesAMDFAM10, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false },
428 { .Name: {"barcelona"}, .Kind: CK_AMDFAM10, .KeyFeature: FEATURE_SSE4_A, .Features: FeaturesAMDFAM10, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false },
429 // Bobcat architecture processors.
430 { .Name: {"btver1"}, .Kind: CK_BTVER1, .KeyFeature: FEATURE_SSE4_A, .Features: FeaturesBTVER1, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false },
431 { .Name: {"btver2"}, .Kind: CK_BTVER2, .KeyFeature: FEATURE_BMI, .Features: FeaturesBTVER2, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false },
432 // Bulldozer architecture processors.
433 { .Name: {"bdver1"}, .Kind: CK_BDVER1, .KeyFeature: FEATURE_XOP, .Features: FeaturesBDVER1, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false },
434 { .Name: {"bdver2"}, .Kind: CK_BDVER2, .KeyFeature: FEATURE_FMA, .Features: FeaturesBDVER2, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false },
435 { .Name: {"bdver3"}, .Kind: CK_BDVER3, .KeyFeature: FEATURE_FMA, .Features: FeaturesBDVER3, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false },
436 { .Name: {"bdver4"}, .Kind: CK_BDVER4, .KeyFeature: FEATURE_AVX2, .Features: FeaturesBDVER4, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false },
437 // Zen architecture processors.
438 { .Name: {"znver1"}, .Kind: CK_ZNVER1, .KeyFeature: FEATURE_AVX2, .Features: FeaturesZNVER1, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false },
439 { .Name: {"znver2"}, .Kind: CK_ZNVER2, .KeyFeature: FEATURE_AVX2, .Features: FeaturesZNVER2, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false },
440 { .Name: {"znver3"}, .Kind: CK_ZNVER3, .KeyFeature: FEATURE_AVX2, .Features: FeaturesZNVER3, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false },
441 { .Name: {"znver4"}, .Kind: CK_ZNVER4, .KeyFeature: FEATURE_AVX512VBMI2, .Features: FeaturesZNVER4, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false },
442 { .Name: {"znver5"}, .Kind: CK_ZNVER5, .KeyFeature: FEATURE_AVX512VP2INTERSECT, .Features: FeaturesZNVER5, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false },
443 // Generic 64-bit processor.
444 { .Name: {"x86-64"}, .Kind: CK_x86_64, .KeyFeature: FEATURE_SSE2 , .Features: FeaturesX86_64, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false },
445 { .Name: {"x86-64-v2"}, .Kind: CK_x86_64_v2, .KeyFeature: FEATURE_SSE4_2 , .Features: FeaturesX86_64_V2, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false },
446 { .Name: {"x86-64-v3"}, .Kind: CK_x86_64_v3, .KeyFeature: FEATURE_AVX2, .Features: FeaturesX86_64_V3, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false },
447 { .Name: {"x86-64-v4"}, .Kind: CK_x86_64_v4, .KeyFeature: FEATURE_AVX512VL, .Features: FeaturesX86_64_V4, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false },
448 // Geode processors.
449 { .Name: {"geode"}, .Kind: CK_Geode, .KeyFeature: ~0U, .Features: FeaturesGeode, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false },
450};
451// clang-format on
452
453constexpr const char *NoTuneList[] = {"x86-64-v2", "x86-64-v3", "x86-64-v4"};
454
455X86::CPUKind llvm::X86::parseArchX86(StringRef CPU, bool Only64Bit) {
456 for (const auto &P : Processors)
457 if (!P.OnlyForCPUDispatchSpecific && P.Name == CPU &&
458 (P.Features[FEATURE_64BIT] || !Only64Bit))
459 return P.Kind;
460
461 return CK_None;
462}
463
464X86::CPUKind llvm::X86::parseTuneCPU(StringRef CPU, bool Only64Bit) {
465 if (llvm::is_contained(Range: NoTuneList, Element: CPU))
466 return CK_None;
467 return parseArchX86(CPU, Only64Bit);
468}
469
470void llvm::X86::fillValidCPUArchList(SmallVectorImpl<StringRef> &Values,
471 bool Only64Bit) {
472 for (const auto &P : Processors)
473 if (!P.OnlyForCPUDispatchSpecific && !P.Name.empty() &&
474 (P.Features[FEATURE_64BIT] || !Only64Bit))
475 Values.emplace_back(Args: P.Name);
476}
477
478void llvm::X86::fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values,
479 bool Only64Bit) {
480 for (const ProcInfo &P : Processors)
481 if (!P.OnlyForCPUDispatchSpecific && !P.Name.empty() &&
482 (P.Features[FEATURE_64BIT] || !Only64Bit) &&
483 !llvm::is_contained(Range: NoTuneList, Element: P.Name))
484 Values.emplace_back(Args: P.Name);
485}
486
487ProcessorFeatures llvm::X86::getKeyFeature(X86::CPUKind Kind) {
488 // FIXME: Can we avoid a linear search here? The table might be sorted by
489 // CPUKind so we could binary search?
490 for (const auto &P : Processors) {
491 if (P.Kind == Kind) {
492 assert(P.KeyFeature != ~0U && "Processor does not have a key feature.");
493 return static_cast<ProcessorFeatures>(P.KeyFeature);
494 }
495 }
496
497 llvm_unreachable("Unable to find CPU kind!");
498}
499
500// Features with no dependencies.
501constexpr FeatureBitset ImpliedFeatures64BIT = {};
502constexpr FeatureBitset ImpliedFeaturesADX = {};
503constexpr FeatureBitset ImpliedFeaturesBMI = {};
504constexpr FeatureBitset ImpliedFeaturesBMI2 = {};
505constexpr FeatureBitset ImpliedFeaturesCLDEMOTE = {};
506constexpr FeatureBitset ImpliedFeaturesCLFLUSHOPT = {};
507constexpr FeatureBitset ImpliedFeaturesCLWB = {};
508constexpr FeatureBitset ImpliedFeaturesCLZERO = {};
509constexpr FeatureBitset ImpliedFeaturesCMOV = {};
510constexpr FeatureBitset ImpliedFeaturesCMPXCHG16B = {};
511constexpr FeatureBitset ImpliedFeaturesCMPXCHG8B = {};
512constexpr FeatureBitset ImpliedFeaturesCRC32 = {};
513constexpr FeatureBitset ImpliedFeaturesENQCMD = {};
514constexpr FeatureBitset ImpliedFeaturesFSGSBASE = {};
515constexpr FeatureBitset ImpliedFeaturesFXSR = {};
516constexpr FeatureBitset ImpliedFeaturesINVPCID = {};
517constexpr FeatureBitset ImpliedFeaturesLWP = {};
518constexpr FeatureBitset ImpliedFeaturesLZCNT = {};
519constexpr FeatureBitset ImpliedFeaturesMMX = {};
520constexpr FeatureBitset ImpliedFeaturesMWAITX = {};
521constexpr FeatureBitset ImpliedFeaturesMOVBE = {};
522constexpr FeatureBitset ImpliedFeaturesMOVDIR64B = {};
523constexpr FeatureBitset ImpliedFeaturesMOVDIRI = {};
524constexpr FeatureBitset ImpliedFeaturesPCONFIG = {};
525constexpr FeatureBitset ImpliedFeaturesPOPCNT = {};
526constexpr FeatureBitset ImpliedFeaturesPKU = {};
527constexpr FeatureBitset ImpliedFeaturesPRFCHW = {};
528constexpr FeatureBitset ImpliedFeaturesPTWRITE = {};
529constexpr FeatureBitset ImpliedFeaturesRDPID = {};
530constexpr FeatureBitset ImpliedFeaturesRDPRU = {};
531constexpr FeatureBitset ImpliedFeaturesRDRND = {};
532constexpr FeatureBitset ImpliedFeaturesRDSEED = {};
533constexpr FeatureBitset ImpliedFeaturesRTM = {};
534constexpr FeatureBitset ImpliedFeaturesSAHF = {};
535constexpr FeatureBitset ImpliedFeaturesSERIALIZE = {};
536constexpr FeatureBitset ImpliedFeaturesSGX = {};
537constexpr FeatureBitset ImpliedFeaturesSHSTK = {};
538constexpr FeatureBitset ImpliedFeaturesTBM = {};
539constexpr FeatureBitset ImpliedFeaturesTSXLDTRK = {};
540constexpr FeatureBitset ImpliedFeaturesUINTR = {};
541constexpr FeatureBitset ImpliedFeaturesUSERMSR = {};
542constexpr FeatureBitset ImpliedFeaturesWAITPKG = {};
543constexpr FeatureBitset ImpliedFeaturesWBNOINVD = {};
544constexpr FeatureBitset ImpliedFeaturesVZEROUPPER = {};
545constexpr FeatureBitset ImpliedFeaturesX87 = {};
546constexpr FeatureBitset ImpliedFeaturesXSAVE = {};
547
548// Not really CPU features, but need to be in the table because clang uses
549// target features to communicate them to the backend.
550constexpr FeatureBitset ImpliedFeaturesRETPOLINE_EXTERNAL_THUNK = {};
551constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_BRANCHES = {};
552constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_CALLS = {};
553constexpr FeatureBitset ImpliedFeaturesLVI_CFI = {};
554constexpr FeatureBitset ImpliedFeaturesLVI_LOAD_HARDENING = {};
555
556// XSAVE features are dependent on basic XSAVE.
557constexpr FeatureBitset ImpliedFeaturesXSAVEC = FeatureXSAVE;
558constexpr FeatureBitset ImpliedFeaturesXSAVEOPT = FeatureXSAVE;
559constexpr FeatureBitset ImpliedFeaturesXSAVES = FeatureXSAVE;
560
561// SSE/AVX/AVX512F chain.
562constexpr FeatureBitset ImpliedFeaturesSSE = {};
563constexpr FeatureBitset ImpliedFeaturesSSE2 = FeatureSSE;
564constexpr FeatureBitset ImpliedFeaturesSSE3 = FeatureSSE2;
565constexpr FeatureBitset ImpliedFeaturesSSSE3 = FeatureSSE3;
566constexpr FeatureBitset ImpliedFeaturesSSE4_1 = FeatureSSSE3;
567constexpr FeatureBitset ImpliedFeaturesSSE4_2 = FeatureSSE4_1;
568constexpr FeatureBitset ImpliedFeaturesAVX = FeatureSSE4_2;
569constexpr FeatureBitset ImpliedFeaturesAVX2 = FeatureAVX;
570constexpr FeatureBitset ImpliedFeaturesEVEX512 = {};
571constexpr FeatureBitset ImpliedFeaturesAVX512F =
572 FeatureAVX2 | FeatureF16C | FeatureFMA;
573
574// Vector extensions that build on SSE or AVX.
575constexpr FeatureBitset ImpliedFeaturesAES = FeatureSSE2;
576constexpr FeatureBitset ImpliedFeaturesF16C = FeatureAVX;
577constexpr FeatureBitset ImpliedFeaturesFMA = FeatureAVX;
578constexpr FeatureBitset ImpliedFeaturesGFNI = FeatureSSE2;
579constexpr FeatureBitset ImpliedFeaturesPCLMUL = FeatureSSE2;
580constexpr FeatureBitset ImpliedFeaturesSHA = FeatureSSE2;
581constexpr FeatureBitset ImpliedFeaturesVAES = FeatureAES | FeatureAVX2;
582constexpr FeatureBitset ImpliedFeaturesVPCLMULQDQ = FeatureAVX | FeaturePCLMUL;
583constexpr FeatureBitset ImpliedFeaturesSM3 = FeatureAVX;
584constexpr FeatureBitset ImpliedFeaturesSM4 = FeatureAVX2;
585
586// AVX512 features.
587constexpr FeatureBitset ImpliedFeaturesAVX512CD = FeatureAVX512F;
588constexpr FeatureBitset ImpliedFeaturesAVX512BW = FeatureAVX512F;
589constexpr FeatureBitset ImpliedFeaturesAVX512DQ = FeatureAVX512F;
590constexpr FeatureBitset ImpliedFeaturesAVX512VL = FeatureAVX512F;
591
592constexpr FeatureBitset ImpliedFeaturesAVX512BF16 = FeatureAVX512BW;
593constexpr FeatureBitset ImpliedFeaturesAVX512BITALG = FeatureAVX512BW;
594constexpr FeatureBitset ImpliedFeaturesAVX512IFMA = FeatureAVX512F;
595constexpr FeatureBitset ImpliedFeaturesAVX512VNNI = FeatureAVX512F;
596constexpr FeatureBitset ImpliedFeaturesAVX512VPOPCNTDQ = FeatureAVX512F;
597constexpr FeatureBitset ImpliedFeaturesAVX512VBMI = FeatureAVX512BW;
598constexpr FeatureBitset ImpliedFeaturesAVX512VBMI2 = FeatureAVX512BW;
599constexpr FeatureBitset ImpliedFeaturesAVX512VP2INTERSECT = FeatureAVX512F;
600
601// FIXME: These two aren't really implemented and just exist in the feature
602// list for __builtin_cpu_supports. So omit their dependencies.
603constexpr FeatureBitset ImpliedFeaturesAVX5124FMAPS = {};
604constexpr FeatureBitset ImpliedFeaturesAVX5124VNNIW = {};
605
606// SSE4_A->FMA4->XOP chain.
607constexpr FeatureBitset ImpliedFeaturesSSE4_A = FeatureSSE3;
608constexpr FeatureBitset ImpliedFeaturesFMA4 = FeatureAVX | FeatureSSE4_A;
609constexpr FeatureBitset ImpliedFeaturesXOP = FeatureFMA4;
610
611// AMX Features
612constexpr FeatureBitset ImpliedFeaturesAMX_TILE = {};
613constexpr FeatureBitset ImpliedFeaturesAMX_BF16 = FeatureAMX_TILE;
614constexpr FeatureBitset ImpliedFeaturesAMX_FP16 = FeatureAMX_TILE;
615constexpr FeatureBitset ImpliedFeaturesAMX_INT8 = FeatureAMX_TILE;
616constexpr FeatureBitset ImpliedFeaturesAMX_COMPLEX = FeatureAMX_TILE;
617constexpr FeatureBitset ImpliedFeaturesAMX_FP8 = FeatureAMX_TILE;
618constexpr FeatureBitset ImpliedFeaturesAMX_MOVRS = FeatureAMX_TILE;
619constexpr FeatureBitset ImpliedFeaturesAMX_AVX512 =
620 FeatureAMX_TILE | FeatureAVX10_2;
621constexpr FeatureBitset ImpliedFeaturesAMX_TF32 = FeatureAMX_TILE;
622constexpr FeatureBitset ImpliedFeaturesHRESET = {};
623
624constexpr FeatureBitset ImpliedFeaturesPREFETCHI = {};
625constexpr FeatureBitset ImpliedFeaturesCMPCCXADD = {};
626constexpr FeatureBitset ImpliedFeaturesRAOINT = {};
627constexpr FeatureBitset ImpliedFeaturesAVXVNNIINT16 = FeatureAVX2;
628constexpr FeatureBitset ImpliedFeaturesAVXVNNIINT8 = FeatureAVX2;
629constexpr FeatureBitset ImpliedFeaturesAVXIFMA = FeatureAVX2;
630constexpr FeatureBitset ImpliedFeaturesAVXNECONVERT = FeatureAVX2;
631constexpr FeatureBitset ImpliedFeaturesSHA512 = FeatureAVX2;
632constexpr FeatureBitset ImpliedFeaturesAVX512FP16 = FeatureAVX512BW;
633// Key Locker Features
634constexpr FeatureBitset ImpliedFeaturesKL = FeatureSSE2;
635constexpr FeatureBitset ImpliedFeaturesWIDEKL = FeatureKL;
636
637// AVXVNNI Features
638constexpr FeatureBitset ImpliedFeaturesAVXVNNI = FeatureAVX2;
639
640// AVX10 Features
641constexpr FeatureBitset ImpliedFeaturesAVX10_1 =
642 FeatureAVX512CD | FeatureAVX512VBMI | FeatureAVX512IFMA |
643 FeatureAVX512VNNI | FeatureAVX512BF16 | FeatureAVX512VPOPCNTDQ |
644 FeatureAVX512VBMI2 | FeatureAVX512BITALG | FeatureAVX512FP16 |
645 FeatureAVX512DQ | FeatureAVX512VL;
646constexpr FeatureBitset ImpliedFeaturesAVX10_2 = FeatureAVX10_1;
647
648// APX Features
649constexpr FeatureBitset ImpliedFeaturesEGPR = {};
650constexpr FeatureBitset ImpliedFeaturesPush2Pop2 = {};
651constexpr FeatureBitset ImpliedFeaturesPPX = {};
652constexpr FeatureBitset ImpliedFeaturesNDD = {};
653constexpr FeatureBitset ImpliedFeaturesCCMP = {};
654constexpr FeatureBitset ImpliedFeaturesNF = {};
655constexpr FeatureBitset ImpliedFeaturesCF = {};
656constexpr FeatureBitset ImpliedFeaturesZU = {};
657
658constexpr FeatureBitset ImpliedFeaturesAPXF =
659 ImpliedFeaturesEGPR | ImpliedFeaturesPush2Pop2 | ImpliedFeaturesPPX |
660 ImpliedFeaturesNDD | ImpliedFeaturesCCMP | ImpliedFeaturesNF |
661 ImpliedFeaturesCF | ImpliedFeaturesZU;
662
663constexpr FeatureBitset ImpliedFeaturesMOVRS = {};
664
665constexpr FeatureInfo FeatureInfos[] = {
666#define X86_FEATURE(ENUM, STR) {{"+" STR}, ImpliedFeatures##ENUM},
667#include "llvm/TargetParser/X86TargetParser.def"
668};
669
670void llvm::X86::getFeaturesForCPU(StringRef CPU,
671 SmallVectorImpl<StringRef> &EnabledFeatures,
672 bool NeedPlus) {
673 auto I = llvm::find_if(Range: Processors,
674 P: [&](const ProcInfo &P) { return P.Name == CPU; });
675 assert(I != std::end(Processors) && "Processor not found!");
676
677 FeatureBitset Bits = I->Features;
678
679 // Remove the 64-bit feature which we only use to validate if a CPU can
680 // be used with 64-bit mode.
681 Bits &= ~Feature64BIT;
682
683 // Add the string version of all set bits.
684 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
685 if (Bits[i] && !FeatureInfos[i].getName(WithPlus: NeedPlus).empty())
686 EnabledFeatures.push_back(Elt: FeatureInfos[i].getName(WithPlus: NeedPlus));
687}
688
689// For each feature that is (transitively) implied by this feature, set it.
690static void getImpliedEnabledFeatures(FeatureBitset &Bits,
691 const FeatureBitset &Implies) {
692 // Fast path: Implies is often empty.
693 if (!Implies.any())
694 return;
695 FeatureBitset Prev;
696 Bits |= Implies;
697 do {
698 Prev = Bits;
699 for (unsigned i = CPU_FEATURE_MAX; i;)
700 if (Bits[--i])
701 Bits |= FeatureInfos[i].ImpliedFeatures;
702 } while (Prev != Bits);
703}
704
705/// Create bit vector of features that are implied disabled if the feature
706/// passed in Value is disabled.
707static void getImpliedDisabledFeatures(FeatureBitset &Bits, unsigned Value) {
708 // Check all features looking for any dependent on this feature. If we find
709 // one, mark it and recursively find any feature that depend on it.
710 FeatureBitset Prev;
711 Bits.set(Value);
712 do {
713 Prev = Bits;
714 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
715 if ((FeatureInfos[i].ImpliedFeatures & Bits).any())
716 Bits.set(i);
717 } while (Prev != Bits);
718}
719
720void llvm::X86::updateImpliedFeatures(
721 StringRef Feature, bool Enabled,
722 StringMap<bool> &Features) {
723 auto I = llvm::find_if(Range: FeatureInfos, P: [&](const FeatureInfo &FI) {
724 return FI.getName() == Feature;
725 });
726 if (I == std::end(arr: FeatureInfos)) {
727 // FIXME: This shouldn't happen, but may not have all features in the table
728 // yet.
729 return;
730 }
731
732 FeatureBitset ImpliedBits;
733 if (Enabled)
734 getImpliedEnabledFeatures(Bits&: ImpliedBits, Implies: I->ImpliedFeatures);
735 else
736 getImpliedDisabledFeatures(Bits&: ImpliedBits,
737 Value: std::distance(first: std::begin(arr: FeatureInfos), last: I));
738
739 // Update the map entry for all implied features.
740 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
741 if (ImpliedBits[i] && !FeatureInfos[i].getName().empty())
742 Features[FeatureInfos[i].getName()] = Enabled;
743}
744
745char llvm::X86::getCPUDispatchMangling(StringRef CPU) {
746 auto I = llvm::find_if(Range: Processors,
747 P: [&](const ProcInfo &P) { return P.Name == CPU; });
748 assert(I != std::end(Processors) && "Processor not found!");
749 assert(I->Mangling != '\0' && "Processor dooesn't support function multiversion!");
750 return I->Mangling;
751}
752
753bool llvm::X86::validateCPUSpecificCPUDispatch(StringRef Name) {
754 auto I = llvm::find_if(Range: Processors,
755 P: [&](const ProcInfo &P) { return P.Name == Name; });
756 return I != std::end(arr: Processors);
757}
758
759std::array<uint32_t, 4>
760llvm::X86::getCpuSupportsMask(ArrayRef<StringRef> FeatureStrs) {
761 // Processor features and mapping to processor feature value.
762 std::array<uint32_t, 4> FeatureMask{};
763 for (StringRef FeatureStr : FeatureStrs) {
764 unsigned Feature = StringSwitch<unsigned>(FeatureStr)
765#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY, ABI_VALUE) .Case(STR, ABI_VALUE)
766#define X86_MICROARCH_LEVEL(ENUM, STR, PRIORITY, ABI_VALUE) \
767 .Case(STR, ABI_VALUE)
768#include "llvm/TargetParser/X86TargetParser.def"
769 ;
770 assert(Feature / 32 < FeatureMask.size());
771 FeatureMask[Feature / 32] |= 1U << (Feature % 32);
772 }
773 return FeatureMask;
774}
775
776unsigned llvm::X86::getFeaturePriority(ProcessorFeatures Feat) {
777#ifndef NDEBUG
778 // Check that priorities are set properly in the .def file. We expect that
779 // "compat" features are assigned non-duplicate consecutive priorities
780 // starting from one (1, ..., MAX_PRIORITY) and multiple zeros.
781#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY, ABI_VALUE) PRIORITY,
782 unsigned Priorities[] = {
783#include "llvm/TargetParser/X86TargetParser.def"
784 };
785 std::array<unsigned, std::size(Priorities)> HelperList;
786 std::iota(HelperList.begin(), HelperList.begin() + MAX_PRIORITY + 1, 0);
787 for (size_t i = MAX_PRIORITY + 1; i != std::size(Priorities); ++i)
788 HelperList[i] = 0;
789 assert(std::is_permutation(HelperList.begin(), HelperList.end(),
790 std::begin(Priorities), std::end(Priorities)) &&
791 "Priorities don't form consecutive range!");
792#endif
793
794 switch (Feat) {
795#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY, ABI_VALUE) \
796 case X86::FEATURE_##ENUM: \
797 return PRIORITY;
798#include "llvm/TargetParser/X86TargetParser.def"
799 default:
800 llvm_unreachable("No Feature Priority for non-CPUSupports Features");
801 }
802}
803