1//===-- X86TargetParser - Parser for X86 features ---------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements a target parser to recognise X86 hardware features.
10//
11//===----------------------------------------------------------------------===//
12
13#include "llvm/TargetParser/X86TargetParser.h"
14#include "llvm/ADT/Bitset.h"
15#include "llvm/ADT/Enum.h"
16#include "llvm/ADT/StringSwitch.h"
17#include <numeric>
18
19using namespace llvm;
20using namespace llvm::X86;
21
22namespace {
23
24using FeatureBitset = Bitset<X86::CPU_FEATURE_MAX>;
25
26struct ProcInfo {
27 X86::CPUKind Kind;
28 unsigned KeyFeature;
29 FeatureBitset Features;
30 char Mangling;
31 bool OnlyForCPUDispatchSpecific;
32};
33
34} // end anonymous namespace
35
36#define X86_FEATURE(ENUM, STRING) \
37 constexpr FeatureBitset Feature##ENUM = {X86::FEATURE_##ENUM};
38#include "llvm/TargetParser/X86TargetParser.def"
39
40// Pentium with MMX.
41constexpr FeatureBitset FeaturesPentiumMMX =
42 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX;
43
44// Pentium 2 and 3.
45constexpr FeatureBitset FeaturesPentium2 =
46 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | FeatureFXSR | FeatureCMOV;
47constexpr FeatureBitset FeaturesPentium3 = FeaturesPentium2 | FeatureSSE;
48
49// Pentium 4 CPUs
50constexpr FeatureBitset FeaturesPentium4 = FeaturesPentium3 | FeatureSSE2;
51constexpr FeatureBitset FeaturesPrescott = FeaturesPentium4 | FeatureSSE3;
52constexpr FeatureBitset FeaturesNocona =
53 FeaturesPrescott | Feature64BIT | FeatureCMPXCHG16B;
54
55// Basic 64-bit capable CPU.
56constexpr FeatureBitset FeaturesX86_64 = FeaturesPentium4 | Feature64BIT;
57constexpr FeatureBitset FeaturesX86_64_V2 = FeaturesX86_64 | FeatureSAHF |
58 FeaturePOPCNT | FeatureCRC32 |
59 FeatureSSE4_2 | FeatureCMPXCHG16B;
60constexpr FeatureBitset FeaturesX86_64_V3 =
61 FeaturesX86_64_V2 | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureF16C |
62 FeatureFMA | FeatureLZCNT | FeatureMOVBE | FeatureXSAVE;
63constexpr FeatureBitset FeaturesX86_64_V4 = FeaturesX86_64_V3 |
64 FeatureAVX512BW | FeatureAVX512CD |
65 FeatureAVX512DQ | FeatureAVX512VL;
66
67// Intel Core CPUs
68constexpr FeatureBitset FeaturesCore2 =
69 FeaturesNocona | FeatureSAHF | FeatureSSSE3;
70constexpr FeatureBitset FeaturesPenryn = FeaturesCore2 | FeatureSSE4_1;
71constexpr FeatureBitset FeaturesNehalem =
72 FeaturesPenryn | FeaturePOPCNT | FeatureCRC32 | FeatureSSE4_2;
73constexpr FeatureBitset FeaturesWestmere = FeaturesNehalem | FeaturePCLMUL;
74constexpr FeatureBitset FeaturesSandyBridge =
75 FeaturesWestmere | FeatureAVX | FeatureXSAVE | FeatureXSAVEOPT;
76constexpr FeatureBitset FeaturesIvyBridge =
77 FeaturesSandyBridge | FeatureF16C | FeatureFSGSBASE | FeatureRDRND;
78constexpr FeatureBitset FeaturesHaswell =
79 FeaturesIvyBridge | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureFMA |
80 FeatureINVPCID | FeatureLZCNT | FeatureMOVBE;
81constexpr FeatureBitset FeaturesBroadwell =
82 FeaturesHaswell | FeatureADX | FeaturePRFCHW | FeatureRDSEED;
83
84// Intel Knights Landing and Knights Mill
85// Knights Landing has feature parity with Broadwell.
86constexpr FeatureBitset FeaturesKNL =
87 FeaturesBroadwell | FeatureAES | FeatureAVX512F | FeatureAVX512CD;
88constexpr FeatureBitset FeaturesKNM = FeaturesKNL | FeatureAVX512VPOPCNTDQ;
89
90// Intel Skylake processors.
91constexpr FeatureBitset FeaturesSkylakeClient =
92 FeaturesBroadwell | FeatureAES | FeatureCLFLUSHOPT | FeatureXSAVEC |
93 FeatureXSAVES | FeatureSGX;
94// SkylakeServer inherits all SkylakeClient features except SGX.
95// FIXME: That doesn't match gcc.
96constexpr FeatureBitset FeaturesSkylakeServer =
97 (FeaturesSkylakeClient & ~FeatureSGX) | FeatureAVX512F | FeatureAVX512CD |
98 FeatureAVX512DQ | FeatureAVX512BW | FeatureAVX512VL | FeatureCLWB |
99 FeaturePKU;
100constexpr FeatureBitset FeaturesCascadeLake =
101 FeaturesSkylakeServer | FeatureAVX512VNNI;
102constexpr FeatureBitset FeaturesCooperLake =
103 FeaturesCascadeLake | FeatureAVX512BF16;
104
105// Intel 10nm processors.
106constexpr FeatureBitset FeaturesCannonlake =
107 FeaturesSkylakeClient | FeatureAVX512F | FeatureAVX512CD | FeatureAVX512DQ |
108 FeatureAVX512BW | FeatureAVX512VL | FeatureAVX512IFMA | FeatureAVX512VBMI |
109 FeaturePKU | FeatureSHA;
110constexpr FeatureBitset FeaturesICLClient =
111 FeaturesCannonlake | FeatureAVX512BITALG | FeatureAVX512VBMI2 |
112 FeatureAVX512VNNI | FeatureAVX512VPOPCNTDQ | FeatureGFNI | FeatureRDPID |
113 FeatureVAES | FeatureVPCLMULQDQ;
114constexpr FeatureBitset FeaturesRocketlake = FeaturesICLClient & ~FeatureSGX;
115constexpr FeatureBitset FeaturesICLServer =
116 FeaturesICLClient | FeatureCLWB | FeaturePCONFIG | FeatureWBNOINVD;
117constexpr FeatureBitset FeaturesTigerlake =
118 FeaturesICLClient | FeatureAVX512VP2INTERSECT | FeatureMOVDIR64B |
119 FeatureCLWB | FeatureMOVDIRI | FeatureSHSTK | FeatureKL | FeatureWIDEKL;
120constexpr FeatureBitset FeaturesSapphireRapids =
121 FeaturesICLServer | FeatureAMX_BF16 | FeatureAMX_INT8 | FeatureAMX_TILE |
122 FeatureAVX512BF16 | FeatureAVX512FP16 | FeatureAVXVNNI | FeatureCLDEMOTE |
123 FeatureENQCMD | FeatureMOVDIR64B | FeatureMOVDIRI | FeaturePTWRITE |
124 FeatureSERIALIZE | FeatureSHSTK | FeatureTSXLDTRK | FeatureUINTR |
125 FeatureWAITPKG | FeatureAVX512DQ | FeatureAVX512VL;
126constexpr FeatureBitset FeaturesGraniteRapids =
127 FeaturesSapphireRapids | FeatureAMX_FP16 | FeaturePREFETCHI;
128constexpr FeatureBitset FeaturesDiamondRapids =
129 FeaturesGraniteRapids | FeatureAMX_COMPLEX | FeatureAVX10_2 |
130 FeatureCMPCCXADD | FeatureAVXIFMA | FeatureAVXNECONVERT |
131 FeatureAVXVNNIINT8 | FeatureAVXVNNIINT16 | FeatureSHA512 | FeatureSM3 |
132 FeatureSM4 | FeatureEGPR | FeatureZU | FeatureCCMP | FeaturePush2Pop2 |
133 FeaturePPX | FeatureNDD | FeatureNF | FeatureJMPABS | FeatureMOVRS |
134 FeatureAMX_MOVRS | FeatureAMX_AVX512 | FeatureAMX_FP8;
135
136// Intel Atom processors.
137// Bonnell has feature parity with Core2 and adds MOVBE.
138constexpr FeatureBitset FeaturesBonnell = FeaturesCore2 | FeatureMOVBE;
139// Silvermont has parity with Westmere and Bonnell plus PRFCHW and RDRND.
140constexpr FeatureBitset FeaturesSilvermont =
141 FeaturesBonnell | FeaturesWestmere | FeaturePRFCHW | FeatureRDRND;
142constexpr FeatureBitset FeaturesGoldmont =
143 FeaturesSilvermont | FeatureAES | FeatureCLFLUSHOPT | FeatureFSGSBASE |
144 FeatureRDSEED | FeatureSHA | FeatureXSAVE | FeatureXSAVEC |
145 FeatureXSAVEOPT | FeatureXSAVES;
146constexpr FeatureBitset FeaturesGoldmontPlus =
147 FeaturesGoldmont | FeaturePTWRITE | FeatureRDPID | FeatureSGX;
148constexpr FeatureBitset FeaturesTremont =
149 FeaturesGoldmontPlus | FeatureCLWB | FeatureGFNI;
150constexpr FeatureBitset FeaturesAlderlake =
151 FeaturesTremont | FeatureADX | FeatureBMI | FeatureBMI2 | FeatureF16C |
152 FeatureFMA | FeatureINVPCID | FeatureLZCNT | FeaturePCONFIG | FeaturePKU |
153 FeatureSERIALIZE | FeatureSHSTK | FeatureVAES | FeatureVPCLMULQDQ |
154 FeatureMOVDIR64B | FeatureMOVDIRI | FeatureWAITPKG | FeatureAVXVNNI |
155 FeatureHRESET | FeatureWIDEKL;
156constexpr FeatureBitset FeaturesArrowlake =
157 FeaturesAlderlake | FeatureCMPCCXADD | FeatureAVXIFMA | FeatureUINTR |
158 FeatureENQCMD | FeatureAVXNECONVERT | FeatureAVXVNNIINT8;
159constexpr FeatureBitset FeaturesSierraforest =
160 FeaturesArrowlake | FeatureCLDEMOTE;
161constexpr FeatureBitset FeaturesArrowlakeS =
162 FeaturesArrowlake | FeatureAVXVNNIINT16 | FeatureSHA512 | FeatureSM3 |
163 FeatureSM4;
164constexpr FeatureBitset FeaturesPantherlake =
165 (FeaturesArrowlakeS ^ FeatureWIDEKL);
166constexpr FeatureBitset FeaturesNovalake =
167 FeaturesPantherlake | FeaturePREFETCHI | FeatureAVX10_2 | FeatureMOVRS |
168 FeatureEGPR | FeatureZU | FeatureCCMP | FeaturePush2Pop2 | FeaturePPX |
169 FeatureNDD | FeatureNF | FeatureJMPABS;
170constexpr FeatureBitset FeaturesClearwaterforest =
171 (FeaturesSierraforest ^ FeatureWIDEKL) | FeatureAVXVNNIINT16 |
172 FeatureSHA512 | FeatureSM3 | FeatureSM4 | FeaturePREFETCHI | FeatureUSERMSR;
173
174// Geode Processor.
175constexpr FeatureBitset FeaturesGeode =
176 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | FeaturePRFCHW;
177
178// K6 processor.
179constexpr FeatureBitset FeaturesK6 = FeatureX87 | FeatureCMPXCHG8B | FeatureMMX;
180
181// K7 and K8 architecture processors.
182constexpr FeatureBitset FeaturesAthlon =
183 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | FeaturePRFCHW;
184constexpr FeatureBitset FeaturesAthlonXP =
185 FeaturesAthlon | FeatureFXSR | FeatureSSE;
186constexpr FeatureBitset FeaturesK8 =
187 FeaturesAthlonXP | FeatureSSE2 | Feature64BIT;
188constexpr FeatureBitset FeaturesK8SSE3 = FeaturesK8 | FeatureSSE3;
189constexpr FeatureBitset FeaturesAMDFAM10 =
190 FeaturesK8SSE3 | FeatureCMPXCHG16B | FeatureLZCNT | FeaturePOPCNT |
191 FeaturePRFCHW | FeatureSAHF | FeatureSSE4_A;
192
193// Bobcat architecture processors.
194constexpr FeatureBitset FeaturesBTVER1 =
195 FeatureX87 | FeatureCMPXCHG8B | FeatureCMPXCHG16B | Feature64BIT |
196 FeatureFXSR | FeatureLZCNT | FeatureMMX | FeaturePOPCNT | FeaturePRFCHW |
197 FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_A |
198 FeatureSAHF;
199constexpr FeatureBitset FeaturesBTVER2 =
200 FeaturesBTVER1 | FeatureAES | FeatureAVX | FeatureBMI | FeatureCRC32 |
201 FeatureF16C | FeatureMOVBE | FeaturePCLMUL | FeatureXSAVE | FeatureXSAVEOPT;
202
203// AMD Bulldozer architecture processors.
204constexpr FeatureBitset FeaturesBDVER1 =
205 FeatureX87 | FeatureAES | FeatureAVX | FeatureCMPXCHG8B |
206 FeatureCMPXCHG16B | FeatureCRC32 | Feature64BIT | FeatureFMA4 |
207 FeatureFXSR | FeatureLWP | FeatureLZCNT | FeatureMMX | FeaturePCLMUL |
208 FeaturePOPCNT | FeaturePRFCHW | FeatureSAHF | FeatureSSE | FeatureSSE2 |
209 FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_1 | FeatureSSE4_2 | FeatureSSE4_A |
210 FeatureXOP | FeatureXSAVE;
211constexpr FeatureBitset FeaturesBDVER2 =
212 FeaturesBDVER1 | FeatureBMI | FeatureFMA | FeatureF16C | FeatureTBM;
213constexpr FeatureBitset FeaturesBDVER3 =
214 FeaturesBDVER2 | FeatureFSGSBASE | FeatureXSAVEOPT;
215constexpr FeatureBitset FeaturesBDVER4 = FeaturesBDVER3 | FeatureAVX2 |
216 FeatureBMI2 | FeatureMOVBE |
217 FeatureMWAITX | FeatureRDRND;
218
219// AMD Zen architecture processors.
220constexpr FeatureBitset FeaturesZNVER1 =
221 FeatureX87 | FeatureADX | FeatureAES | FeatureAVX | FeatureAVX2 |
222 FeatureBMI | FeatureBMI2 | FeatureCLFLUSHOPT | FeatureCLZERO |
223 FeatureCMPXCHG8B | FeatureCMPXCHG16B | FeatureCRC32 | Feature64BIT |
224 FeatureF16C | FeatureFMA | FeatureFSGSBASE | FeatureFXSR | FeatureLZCNT |
225 FeatureMMX | FeatureMOVBE | FeatureMWAITX | FeaturePCLMUL | FeaturePOPCNT |
226 FeaturePRFCHW | FeatureRDRND | FeatureRDSEED | FeatureSAHF | FeatureSHA |
227 FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_1 |
228 FeatureSSE4_2 | FeatureSSE4_A | FeatureXSAVE | FeatureXSAVEC |
229 FeatureXSAVEOPT | FeatureXSAVES;
230constexpr FeatureBitset FeaturesZNVER2 = FeaturesZNVER1 | FeatureCLWB |
231 FeatureRDPID | FeatureRDPRU |
232 FeatureWBNOINVD;
233static constexpr FeatureBitset FeaturesZNVER3 = FeaturesZNVER2 |
234 FeatureINVPCID | FeaturePKU |
235 FeatureVAES | FeatureVPCLMULQDQ;
236static constexpr FeatureBitset FeaturesZNVER4 =
237 FeaturesZNVER3 | FeatureAVX512F | FeatureAVX512CD | FeatureAVX512DQ |
238 FeatureAVX512BW | FeatureAVX512VL | FeatureAVX512IFMA | FeatureAVX512VBMI |
239 FeatureAVX512VBMI2 | FeatureAVX512VNNI | FeatureAVX512BITALG |
240 FeatureAVX512VPOPCNTDQ | FeatureAVX512BF16 | FeatureGFNI | FeatureSHSTK;
241
242static constexpr FeatureBitset FeaturesZNVER5 =
243 FeaturesZNVER4 | FeatureAVXVNNI | FeatureMOVDIRI | FeatureMOVDIR64B |
244 FeatureAVX512VP2INTERSECT | FeaturePREFETCHI | FeatureAVXVNNI;
245
246static constexpr FeatureBitset FeaturesZNVER6 =
247 FeaturesZNVER5 | FeatureAVXVNNIINT8 | FeatureAVX512FP16 | FeatureAVXIFMA |
248 FeatureAVXNECONVERT | FeatureAVX512BMM;
249
250// Hygon architecture processors.
251constexpr FeatureBitset FeaturesC86_4G_M4 =
252 FeatureX87 | FeatureADX | FeatureAES | FeatureAVX | FeatureAVX2 |
253 FeatureBMI | FeatureBMI2 | FeatureCLFLUSHOPT | FeatureCLZERO |
254 FeatureCMPXCHG8B | FeatureCMPXCHG16B | FeatureCRC32 | Feature64BIT |
255 FeatureF16C | FeatureFMA | FeatureFSGSBASE | FeatureFXSR | FeatureLZCNT |
256 FeatureMMX | FeatureMOVBE | FeatureMWAITX | FeaturePCLMUL | FeaturePOPCNT |
257 FeaturePRFCHW | FeatureRDRND | FeatureRDSEED | FeatureSAHF | FeatureSHA |
258 FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_1 |
259 FeatureSSE4_2 | FeatureSSE4_A | FeatureXSAVE | FeatureXSAVEC |
260 FeatureXSAVEOPT | FeatureXSAVES;
261
262static constexpr FeatureBitset FeaturesC86_4G_M6 = FeaturesC86_4G_M4;
263
264static constexpr FeatureBitset FeaturesC86_4G_M7 =
265 FeaturesC86_4G_M4 | FeatureAVX512BF16 | FeatureAVX512BITALG |
266 FeatureAVX512BW | FeatureAVX512CD | FeatureAVX512DQ | FeatureAVX512F |
267 FeatureAVX512IFMA | FeatureAVX512VBMI | FeatureAVX512VBMI2 |
268 FeatureAVX512VL | FeatureAVX512VNNI | FeatureAVX512VPOPCNTDQ | FeatureCLWB |
269 FeatureCMOV | FeatureGFNI | FeatureVAES | FeatureVPCLMULQDQ |
270 FeatureWBNOINVD;
271
272static constexpr FeatureBitset FeaturesC86_4G_M8 =
273 FeaturesC86_4G_M7 | FeatureSHSTK;
274
275// D151696 tranplanted Mangling and OnlyForCPUDispatchSpecific from
276// X86TargetParser.def to here. They are assigned by following ways:
277// 1. Copy the mangling from the original CPU_SPEICIFC MACROs. If no, assign
278// to '\0' by default, which means not support cpu_specific/dispatch feature.
279// 2. set OnlyForCPUDispatchSpecific as true if this cpu name was not
280// listed here before, which means it doesn't support -march, -mtune and so on.
281// FIXME: Remove OnlyForCPUDispatchSpecific after all CPUs here support both
282// cpu_dispatch/specific() feature and -march, -mtune, and so on.
283// clang-format off
284constexpr EnumStringDef<ProcInfo> ProcessorDefs[] = {
285 // Empty processor. Include X87 and CMPXCHG8 for backwards compatibility.
286 { .Names: {""}, .Value: {.Kind: CK_None, .KeyFeature: ~0U, .Features: FeatureX87 | FeatureCMPXCHG8B, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false} },
287 { .Names: {"generic"}, .Value: {.Kind: CK_None, .KeyFeature: ~0U, .Features: FeatureX87 | FeatureCMPXCHG8B | Feature64BIT, .Mangling: 'A', .OnlyForCPUDispatchSpecific: true} },
288 // i386-generation processors.
289 { .Names: {"i386"}, .Value: {.Kind: CK_i386, .KeyFeature: ~0U, .Features: FeatureX87, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false} },
290 // i486-generation processors.
291 { .Names: {"i486"}, .Value: {.Kind: CK_i486, .KeyFeature: ~0U, .Features: FeatureX87, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false} },
292 { .Names: {"winchip-c6"}, .Value: {.Kind: CK_WinChipC6, .KeyFeature: ~0U, .Features: FeaturesPentiumMMX, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false} },
293 { .Names: {"winchip2"}, .Value: {.Kind: CK_WinChip2, .KeyFeature: ~0U, .Features: FeaturesPentiumMMX | FeaturePRFCHW, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false} },
294 { .Names: {"c3"}, .Value: {.Kind: CK_C3, .KeyFeature: ~0U, .Features: FeaturesPentiumMMX | FeaturePRFCHW, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false} },
295 // i586-generation processors, P5 microarchitecture based.
296 { .Names: {"i586"}, .Value: {.Kind: CK_i586, .KeyFeature: ~0U, .Features: FeatureX87 | FeatureCMPXCHG8B, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false} },
297 { .Names: {"pentium"}, .Value: {.Kind: CK_Pentium, .KeyFeature: ~0U, .Features: FeatureX87 | FeatureCMPXCHG8B, .Mangling: 'B', .OnlyForCPUDispatchSpecific: false} },
298 { .Names: {"pentium-mmx"}, .Value: {.Kind: CK_PentiumMMX, .KeyFeature: ~0U, .Features: FeaturesPentiumMMX, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false} },
299 { .Names: {"pentium_mmx"}, .Value: {.Kind: CK_PentiumMMX, .KeyFeature: ~0U, .Features: FeaturesPentiumMMX, .Mangling: 'D', .OnlyForCPUDispatchSpecific: true} },
300 // i686-generation processors, P6 / Pentium M microarchitecture based.
301 { .Names: {"pentiumpro"}, .Value: {.Kind: CK_PentiumPro, .KeyFeature: ~0U, .Features: FeatureCMOV | FeatureX87 | FeatureCMPXCHG8B, .Mangling: 'C', .OnlyForCPUDispatchSpecific: false} },
302 { .Names: {"pentium_pro"}, .Value: {.Kind: CK_PentiumPro, .KeyFeature: ~0U, .Features: FeatureCMOV | FeatureX87 | FeatureCMPXCHG8B, .Mangling: 'C', .OnlyForCPUDispatchSpecific: true} },
303 { .Names: {"i686"}, .Value: {.Kind: CK_i686, .KeyFeature: ~0U, .Features: FeatureCMOV | FeatureX87 | FeatureCMPXCHG8B, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false} },
304 { .Names: {"pentium2"}, .Value: {.Kind: CK_Pentium2, .KeyFeature: ~0U, .Features: FeaturesPentium2, .Mangling: 'E', .OnlyForCPUDispatchSpecific: false} },
305 { .Names: {"pentium_ii"}, .Value: {.Kind: CK_Pentium2, .KeyFeature: ~0U, .Features: FeaturesPentium2, .Mangling: 'E', .OnlyForCPUDispatchSpecific: true} },
306 { .Names: {"pentium3"}, .Value: {.Kind: CK_Pentium3, .KeyFeature: ~0U, .Features: FeaturesPentium3, .Mangling: 'H', .OnlyForCPUDispatchSpecific: false} },
307 { .Names: {"pentium3m"}, .Value: {.Kind: CK_Pentium3, .KeyFeature: ~0U, .Features: FeaturesPentium3, .Mangling: 'H', .OnlyForCPUDispatchSpecific: false} },
308 { .Names: {"pentium_iii"}, .Value: {.Kind: CK_Pentium3, .KeyFeature: ~0U, .Features: FeaturesPentium3, .Mangling: 'H', .OnlyForCPUDispatchSpecific: true} },
309 { .Names: {"pentium_iii_no_xmm_regs"}, .Value: {.Kind: CK_Pentium3, .KeyFeature: ~0U, .Features: FeaturesPentium3, .Mangling: 'H', .OnlyForCPUDispatchSpecific: true} },
310 { .Names: {"pentium-m"}, .Value: {.Kind: CK_PentiumM, .KeyFeature: ~0U, .Features: FeaturesPentium4, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false} },
311 { .Names: {"pentium_m"}, .Value: {.Kind: CK_PentiumM, .KeyFeature: ~0U, .Features: FeaturesPentium4, .Mangling: 'K', .OnlyForCPUDispatchSpecific: true} },
312 { .Names: {"c3-2"}, .Value: {.Kind: CK_C3_2, .KeyFeature: ~0U, .Features: FeaturesPentium3, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false} },
313 { .Names: {"yonah"}, .Value: {.Kind: CK_Yonah, .KeyFeature: ~0U, .Features: FeaturesPrescott, .Mangling: 'L', .OnlyForCPUDispatchSpecific: false} },
314 // Netburst microarchitecture based processors.
315 { .Names: {"pentium4"}, .Value: {.Kind: CK_Pentium4, .KeyFeature: ~0U, .Features: FeaturesPentium4, .Mangling: 'J', .OnlyForCPUDispatchSpecific: false} },
316 { .Names: {"pentium4m"}, .Value: {.Kind: CK_Pentium4, .KeyFeature: ~0U, .Features: FeaturesPentium4, .Mangling: 'J', .OnlyForCPUDispatchSpecific: false} },
317 { .Names: {"pentium_4"}, .Value: {.Kind: CK_Pentium4, .KeyFeature: ~0U, .Features: FeaturesPentium4, .Mangling: 'J', .OnlyForCPUDispatchSpecific: true} },
318 { .Names: {"pentium_4_sse3"}, .Value: {.Kind: CK_Prescott, .KeyFeature: ~0U, .Features: FeaturesPrescott, .Mangling: 'L', .OnlyForCPUDispatchSpecific: true} },
319 { .Names: {"prescott"}, .Value: {.Kind: CK_Prescott, .KeyFeature: ~0U, .Features: FeaturesPrescott, .Mangling: 'L', .OnlyForCPUDispatchSpecific: false} },
320 { .Names: {"nocona"}, .Value: {.Kind: CK_Nocona, .KeyFeature: ~0U, .Features: FeaturesNocona, .Mangling: 'L', .OnlyForCPUDispatchSpecific: false} },
321 // Core microarchitecture based processors.
322 { .Names: {"core2"}, .Value: {.Kind: CK_Core2, .KeyFeature: FEATURE_SSSE3, .Features: FeaturesCore2, .Mangling: 'M', .OnlyForCPUDispatchSpecific: false} },
323 { .Names: {"core_2_duo_ssse3"}, .Value: {.Kind: CK_Core2, .KeyFeature: ~0U, .Features: FeaturesCore2, .Mangling: 'M', .OnlyForCPUDispatchSpecific: true} },
324 { .Names: {"penryn"}, .Value: {.Kind: CK_Penryn, .KeyFeature: ~0U, .Features: FeaturesPenryn, .Mangling: 'N', .OnlyForCPUDispatchSpecific: false} },
325 { .Names: {"core_2_duo_sse4_1"}, .Value: {.Kind: CK_Penryn, .KeyFeature: ~0U, .Features: FeaturesPenryn, .Mangling: 'N', .OnlyForCPUDispatchSpecific: true} },
326 // Atom processors
327 { .Names: {"bonnell"}, .Value: {.Kind: CK_Bonnell, .KeyFeature: FEATURE_SSSE3, .Features: FeaturesBonnell, .Mangling: 'O', .OnlyForCPUDispatchSpecific: false} },
328 { .Names: {"atom"}, .Value: {.Kind: CK_Bonnell, .KeyFeature: FEATURE_SSSE3, .Features: FeaturesBonnell, .Mangling: 'O', .OnlyForCPUDispatchSpecific: false} },
329 { .Names: {"silvermont"}, .Value: {.Kind: CK_Silvermont, .KeyFeature: FEATURE_SSE4_2, .Features: FeaturesSilvermont, .Mangling: 'c', .OnlyForCPUDispatchSpecific: false} },
330 { .Names: {"slm"}, .Value: {.Kind: CK_Silvermont, .KeyFeature: FEATURE_SSE4_2, .Features: FeaturesSilvermont, .Mangling: 'c', .OnlyForCPUDispatchSpecific: false} },
331 { .Names: {"atom_sse4_2"}, .Value: {.Kind: CK_Nehalem, .KeyFeature: FEATURE_SSE4_2, .Features: FeaturesNehalem, .Mangling: 'c', .OnlyForCPUDispatchSpecific: true} },
332 { .Names: {"atom_sse4_2_movbe"}, .Value: {.Kind: CK_Goldmont, .KeyFeature: FEATURE_SSE4_2, .Features: FeaturesGoldmont, .Mangling: 'd', .OnlyForCPUDispatchSpecific: true} },
333 { .Names: {"goldmont"}, .Value: {.Kind: CK_Goldmont, .KeyFeature: FEATURE_SSE4_2, .Features: FeaturesGoldmont, .Mangling: 'i', .OnlyForCPUDispatchSpecific: false} },
334 { .Names: {"goldmont-plus"}, .Value: {.Kind: CK_GoldmontPlus, .KeyFeature: FEATURE_SSE4_2, .Features: FeaturesGoldmontPlus, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false} },
335 { .Names: {"goldmont_plus"}, .Value: {.Kind: CK_GoldmontPlus, .KeyFeature: FEATURE_SSE4_2, .Features: FeaturesGoldmontPlus, .Mangling: 'd', .OnlyForCPUDispatchSpecific: true} },
336 { .Names: {"tremont"}, .Value: {.Kind: CK_Tremont, .KeyFeature: FEATURE_SSE4_2, .Features: FeaturesTremont, .Mangling: 'd', .OnlyForCPUDispatchSpecific: false} },
337 // Nehalem microarchitecture based processors.
338 { .Names: {"nehalem"}, .Value: {.Kind: CK_Nehalem, .KeyFeature: FEATURE_SSE4_2, .Features: FeaturesNehalem, .Mangling: 'P', .OnlyForCPUDispatchSpecific: false} },
339 { .Names: {"core_i7_sse4_2"}, .Value: {.Kind: CK_Nehalem, .KeyFeature: FEATURE_SSE4_2, .Features: FeaturesNehalem, .Mangling: 'P', .OnlyForCPUDispatchSpecific: true} },
340 { .Names: {"corei7"}, .Value: {.Kind: CK_Nehalem, .KeyFeature: FEATURE_SSE4_2, .Features: FeaturesNehalem, .Mangling: 'P', .OnlyForCPUDispatchSpecific: false} },
341 // Westmere microarchitecture based processors.
342 { .Names: {"westmere"}, .Value: {.Kind: CK_Westmere, .KeyFeature: FEATURE_PCLMUL, .Features: FeaturesWestmere, .Mangling: 'Q', .OnlyForCPUDispatchSpecific: false} },
343 { .Names: {"core_aes_pclmulqdq"}, .Value: {.Kind: CK_Nehalem, .KeyFeature: FEATURE_SSE4_2, .Features: FeaturesNehalem, .Mangling: 'Q', .OnlyForCPUDispatchSpecific: true} },
344 // Sandy Bridge microarchitecture based processors.
345 { .Names: {"sandybridge"}, .Value: {.Kind: CK_SandyBridge, .KeyFeature: FEATURE_AVX, .Features: FeaturesSandyBridge, .Mangling: 'R', .OnlyForCPUDispatchSpecific: false} },
346 { .Names: {"core_2nd_gen_avx"}, .Value: {.Kind: CK_SandyBridge, .KeyFeature: FEATURE_AVX, .Features: FeaturesSandyBridge, .Mangling: 'R', .OnlyForCPUDispatchSpecific: true} },
347 { .Names: {"corei7-avx"}, .Value: {.Kind: CK_SandyBridge, .KeyFeature: FEATURE_AVX, .Features: FeaturesSandyBridge, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false} },
348 // Ivy Bridge microarchitecture based processors.
349 { .Names: {"ivybridge"}, .Value: {.Kind: CK_IvyBridge, .KeyFeature: FEATURE_AVX, .Features: FeaturesIvyBridge, .Mangling: 'S', .OnlyForCPUDispatchSpecific: false} },
350 { .Names: {"core_3rd_gen_avx"}, .Value: {.Kind: CK_IvyBridge, .KeyFeature: FEATURE_AVX, .Features: FeaturesIvyBridge, .Mangling: 'S', .OnlyForCPUDispatchSpecific: true} },
351 { .Names: {"core-avx-i"}, .Value: {.Kind: CK_IvyBridge, .KeyFeature: FEATURE_AVX, .Features: FeaturesIvyBridge, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false} },
352 // Haswell microarchitecture based processors.
353 { .Names: {"haswell"}, .Value: {.Kind: CK_Haswell, .KeyFeature: FEATURE_AVX2, .Features: FeaturesHaswell, .Mangling: 'V', .OnlyForCPUDispatchSpecific: false} },
354 { .Names: {"core-avx2"}, .Value: {.Kind: CK_Haswell, .KeyFeature: FEATURE_AVX2, .Features: FeaturesHaswell, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false} },
355 { .Names: {"core_4th_gen_avx"}, .Value: {.Kind: CK_Haswell, .KeyFeature: FEATURE_AVX2, .Features: FeaturesHaswell, .Mangling: 'V', .OnlyForCPUDispatchSpecific: true} },
356 { .Names: {"core_4th_gen_avx_tsx"}, .Value: {.Kind: CK_Haswell, .KeyFeature: FEATURE_AVX2, .Features: FeaturesHaswell, .Mangling: 'W', .OnlyForCPUDispatchSpecific: true} },
357 // Broadwell microarchitecture based processors.
358 { .Names: {"broadwell"}, .Value: {.Kind: CK_Broadwell, .KeyFeature: FEATURE_AVX2, .Features: FeaturesBroadwell, .Mangling: 'X', .OnlyForCPUDispatchSpecific: false} },
359 { .Names: {"core_5th_gen_avx"}, .Value: {.Kind: CK_Broadwell, .KeyFeature: FEATURE_AVX2, .Features: FeaturesBroadwell, .Mangling: 'X', .OnlyForCPUDispatchSpecific: true} },
360 { .Names: {"core_5th_gen_avx_tsx"}, .Value: {.Kind: CK_Broadwell, .KeyFeature: FEATURE_AVX2, .Features: FeaturesBroadwell, .Mangling: 'Y', .OnlyForCPUDispatchSpecific: true} },
361 // Skylake client microarchitecture based processors.
362 { .Names: {"skylake"}, .Value: {.Kind: CK_SkylakeClient, .KeyFeature: FEATURE_AVX2, .Features: FeaturesSkylakeClient, .Mangling: 'b', .OnlyForCPUDispatchSpecific: false} },
363 // Skylake server microarchitecture based processors.
364 { .Names: {"skylake-avx512"}, .Value: {.Kind: CK_SkylakeServer, .KeyFeature: FEATURE_AVX512F, .Features: FeaturesSkylakeServer, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false} },
365 { .Names: {"skx"}, .Value: {.Kind: CK_SkylakeServer, .KeyFeature: FEATURE_AVX512F, .Features: FeaturesSkylakeServer, .Mangling: 'a', .OnlyForCPUDispatchSpecific: false} },
366 { .Names: {"skylake_avx512"}, .Value: {.Kind: CK_SkylakeServer, .KeyFeature: FEATURE_AVX512F, .Features: FeaturesSkylakeServer, .Mangling: 'a', .OnlyForCPUDispatchSpecific: true} },
367 // Cascadelake Server microarchitecture based processors.
368 { .Names: {"cascadelake"}, .Value: {.Kind: CK_Cascadelake, .KeyFeature: FEATURE_AVX512VNNI, .Features: FeaturesCascadeLake, .Mangling: 'o', .OnlyForCPUDispatchSpecific: false} },
369 // Cooperlake Server microarchitecture based processors.
370 { .Names: {"cooperlake"}, .Value: {.Kind: CK_Cooperlake, .KeyFeature: FEATURE_AVX512BF16, .Features: FeaturesCooperLake, .Mangling: 'f', .OnlyForCPUDispatchSpecific: false} },
371 // Cannonlake client microarchitecture based processors.
372 { .Names: {"cannonlake"}, .Value: {.Kind: CK_Cannonlake, .KeyFeature: FEATURE_AVX512VBMI, .Features: FeaturesCannonlake, .Mangling: 'e', .OnlyForCPUDispatchSpecific: false} },
373 // Icelake client microarchitecture based processors.
374 { .Names: {"icelake-client"}, .Value: {.Kind: CK_IcelakeClient, .KeyFeature: FEATURE_AVX512VBMI2, .Features: FeaturesICLClient, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false} },
375 { .Names: {"icelake_client"}, .Value: {.Kind: CK_IcelakeClient, .KeyFeature: FEATURE_AVX512VBMI2, .Features: FeaturesICLClient, .Mangling: 'k', .OnlyForCPUDispatchSpecific: true} },
376 // Rocketlake microarchitecture based processors.
377 { .Names: {"rocketlake"}, .Value: {.Kind: CK_Rocketlake, .KeyFeature: FEATURE_AVX512VBMI2, .Features: FeaturesRocketlake, .Mangling: 'k', .OnlyForCPUDispatchSpecific: false} },
378 // Icelake server microarchitecture based processors.
379 { .Names: {"icelake-server"}, .Value: {.Kind: CK_IcelakeServer, .KeyFeature: FEATURE_AVX512VBMI2, .Features: FeaturesICLServer, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false} },
380 { .Names: {"icelake_server"}, .Value: {.Kind: CK_IcelakeServer, .KeyFeature: FEATURE_AVX512VBMI2, .Features: FeaturesICLServer, .Mangling: 'k', .OnlyForCPUDispatchSpecific: true} },
381 // Tigerlake microarchitecture based processors.
382 { .Names: {"tigerlake"}, .Value: {.Kind: CK_Tigerlake, .KeyFeature: FEATURE_AVX512VP2INTERSECT, .Features: FeaturesTigerlake, .Mangling: 'l', .OnlyForCPUDispatchSpecific: false} },
383 // Sapphire Rapids microarchitecture based processors.
384 { .Names: {"sapphirerapids"}, .Value: {.Kind: CK_SapphireRapids, .KeyFeature: FEATURE_AVX512FP16, .Features: FeaturesSapphireRapids, .Mangling: 'n', .OnlyForCPUDispatchSpecific: false} },
385 // Alderlake microarchitecture based processors.
386 { .Names: {"alderlake"}, .Value: {.Kind: CK_Alderlake, .KeyFeature: FEATURE_AVX2, .Features: FeaturesAlderlake, .Mangling: 'p', .OnlyForCPUDispatchSpecific: false} },
387 // Raptorlake microarchitecture based processors.
388 { .Names: {"raptorlake"}, .Value: {.Kind: CK_Raptorlake, .KeyFeature: FEATURE_AVX2, .Features: FeaturesAlderlake, .Mangling: 'p', .OnlyForCPUDispatchSpecific: false} },
389 // Meteorlake microarchitecture based processors.
390 { .Names: {"meteorlake"}, .Value: {.Kind: CK_Meteorlake, .KeyFeature: FEATURE_AVX2, .Features: FeaturesAlderlake, .Mangling: 'p', .OnlyForCPUDispatchSpecific: false} },
391 // Arrowlake microarchitecture based processors.
392 { .Names: {"arrowlake"}, .Value: {.Kind: CK_Arrowlake, .KeyFeature: FEATURE_AVX2, .Features: FeaturesArrowlake, .Mangling: 'p', .OnlyForCPUDispatchSpecific: false} },
393 { .Names: {"arrowlake-s"}, .Value: {.Kind: CK_ArrowlakeS, .KeyFeature: FEATURE_AVX2, .Features: FeaturesArrowlakeS, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false} },
394 { .Names: {"arrowlake_s"}, .Value: {.Kind: CK_ArrowlakeS, .KeyFeature: FEATURE_AVX2, .Features: FeaturesArrowlakeS, .Mangling: 'p', .OnlyForCPUDispatchSpecific: true} },
395 // Lunarlake microarchitecture based processors.
396 { .Names: {"lunarlake"}, .Value: {.Kind: CK_Lunarlake, .KeyFeature: FEATURE_AVX2, .Features: FeaturesArrowlakeS, .Mangling: 'p', .OnlyForCPUDispatchSpecific: false} },
397 // Gracemont microarchitecture based processors.
398 { .Names: {"gracemont"}, .Value: {.Kind: CK_Gracemont, .KeyFeature: FEATURE_AVX2, .Features: FeaturesAlderlake, .Mangling: 'p', .OnlyForCPUDispatchSpecific: false} },
399 // Pantherlake microarchitecture based processors.
400 { .Names: {"pantherlake"}, .Value: {.Kind: CK_Lunarlake, .KeyFeature: FEATURE_AVX2, .Features: FeaturesPantherlake, .Mangling: 'p', .OnlyForCPUDispatchSpecific: false} },
401 { .Names: {"wildcatlake"}, .Value: {.Kind: CK_Lunarlake, .KeyFeature: FEATURE_AVX2, .Features: FeaturesPantherlake, .Mangling: 'p', .OnlyForCPUDispatchSpecific: false} },
402 // Novalake microarchitecture based processors.
403 { .Names: {"novalake"}, .Value: {.Kind: CK_Novalake, .KeyFeature: FEATURE_AVX2, .Features: FeaturesNovalake, .Mangling: 'r', .OnlyForCPUDispatchSpecific: false} },
404 // Sierraforest microarchitecture based processors.
405 { .Names: {"sierraforest"}, .Value: {.Kind: CK_Sierraforest, .KeyFeature: FEATURE_AVX2, .Features: FeaturesSierraforest, .Mangling: 'p', .OnlyForCPUDispatchSpecific: false} },
406 // Grandridge microarchitecture based processors.
407 { .Names: {"grandridge"}, .Value: {.Kind: CK_Grandridge, .KeyFeature: FEATURE_AVX2, .Features: FeaturesSierraforest, .Mangling: 'p', .OnlyForCPUDispatchSpecific: false} },
408 // Granite Rapids microarchitecture based processors.
409 { .Names: {"graniterapids"}, .Value: {.Kind: CK_Graniterapids, .KeyFeature: FEATURE_AVX512FP16, .Features: FeaturesGraniteRapids, .Mangling: 'n', .OnlyForCPUDispatchSpecific: false} },
410 // Granite Rapids D microarchitecture based processors.
411 { .Names: {"graniterapids-d"}, .Value: {.Kind: CK_GraniterapidsD, .KeyFeature: FEATURE_AVX512FP16, .Features: FeaturesGraniteRapids | FeatureAMX_COMPLEX, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false} },
412 { .Names: {"graniterapids_d"}, .Value: {.Kind: CK_GraniterapidsD, .KeyFeature: FEATURE_AVX512FP16, .Features: FeaturesGraniteRapids | FeatureAMX_COMPLEX, .Mangling: 'n', .OnlyForCPUDispatchSpecific: true} },
413 // Emerald Rapids microarchitecture based processors.
414 { .Names: {"emeraldrapids"}, .Value: {.Kind: CK_Emeraldrapids, .KeyFeature: FEATURE_AVX512FP16, .Features: FeaturesSapphireRapids, .Mangling: 'n', .OnlyForCPUDispatchSpecific: false} },
415 // Clearwaterforest microarchitecture based processors.
416 { .Names: {"clearwaterforest"}, .Value: {.Kind: CK_Lunarlake, .KeyFeature: FEATURE_AVX2, .Features: FeaturesClearwaterforest, .Mangling: 'p', .OnlyForCPUDispatchSpecific: false} },
417 // Diamond Rapids microarchitecture based processors.
418 { .Names: {"diamondrapids"}, .Value: {.Kind: CK_Diamondrapids, .KeyFeature: FEATURE_AVX10_2, .Features: FeaturesDiamondRapids, .Mangling: 'z', .OnlyForCPUDispatchSpecific: false} },
419 // Knights Landing processor.
420 { .Names: {"knl"}, .Value: {.Kind: CK_KNL, .KeyFeature: FEATURE_AVX512F, .Features: FeaturesKNL, .Mangling: 'Z', .OnlyForCPUDispatchSpecific: false} },
421 { .Names: {"mic_avx512"}, .Value: {.Kind: CK_KNL, .KeyFeature: FEATURE_AVX512F, .Features: FeaturesKNL, .Mangling: 'Z', .OnlyForCPUDispatchSpecific: true} },
422 // Knights Mill processor.
423 { .Names: {"knm"}, .Value: {.Kind: CK_KNM, .KeyFeature: FEATURE_AVX5124FMAPS, .Features: FeaturesKNM, .Mangling: 'j', .OnlyForCPUDispatchSpecific: false} },
424 // Lakemont microarchitecture based processors.
425 { .Names: {"lakemont"}, .Value: {.Kind: CK_Lakemont, .KeyFeature: ~0U, .Features: FeatureCMPXCHG8B, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false} },
426 // K6 architecture processors.
427 { .Names: {"k6"}, .Value: {.Kind: CK_K6, .KeyFeature: ~0U, .Features: FeaturesK6, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false} },
428 { .Names: {"k6-2"}, .Value: {.Kind: CK_K6_2, .KeyFeature: ~0U, .Features: FeaturesK6 | FeaturePRFCHW, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false} },
429 { .Names: {"k6-3"}, .Value: {.Kind: CK_K6_3, .KeyFeature: ~0U, .Features: FeaturesK6 | FeaturePRFCHW, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false} },
430 // K7 architecture processors.
431 { .Names: {"athlon"}, .Value: {.Kind: CK_Athlon, .KeyFeature: ~0U, .Features: FeaturesAthlon, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false} },
432 { .Names: {"athlon-tbird"}, .Value: {.Kind: CK_Athlon, .KeyFeature: ~0U, .Features: FeaturesAthlon, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false} },
433 { .Names: {"athlon-xp"}, .Value: {.Kind: CK_AthlonXP, .KeyFeature: ~0U, .Features: FeaturesAthlonXP, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false} },
434 { .Names: {"athlon-mp"}, .Value: {.Kind: CK_AthlonXP, .KeyFeature: ~0U, .Features: FeaturesAthlonXP, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false} },
435 { .Names: {"athlon-4"}, .Value: {.Kind: CK_AthlonXP, .KeyFeature: ~0U, .Features: FeaturesAthlonXP, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false} },
436 // K8 architecture processors.
437 { .Names: {"k8"}, .Value: {.Kind: CK_K8, .KeyFeature: ~0U, .Features: FeaturesK8, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false} },
438 { .Names: {"athlon64"}, .Value: {.Kind: CK_K8, .KeyFeature: ~0U, .Features: FeaturesK8, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false} },
439 { .Names: {"athlon-fx"}, .Value: {.Kind: CK_K8, .KeyFeature: ~0U, .Features: FeaturesK8, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false} },
440 { .Names: {"opteron"}, .Value: {.Kind: CK_K8, .KeyFeature: ~0U, .Features: FeaturesK8, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false} },
441 { .Names: {"k8-sse3"}, .Value: {.Kind: CK_K8SSE3, .KeyFeature: ~0U, .Features: FeaturesK8SSE3, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false} },
442 { .Names: {"athlon64-sse3"}, .Value: {.Kind: CK_K8SSE3, .KeyFeature: ~0U, .Features: FeaturesK8SSE3, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false} },
443 { .Names: {"opteron-sse3"}, .Value: {.Kind: CK_K8SSE3, .KeyFeature: ~0U, .Features: FeaturesK8SSE3, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false} },
444 { .Names: {"amdfam10"}, .Value: {.Kind: CK_AMDFAM10, .KeyFeature: FEATURE_SSE4_A, .Features: FeaturesAMDFAM10, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false} },
445 { .Names: {"barcelona"}, .Value: {.Kind: CK_AMDFAM10, .KeyFeature: FEATURE_SSE4_A, .Features: FeaturesAMDFAM10, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false} },
446 // Bobcat architecture processors.
447 { .Names: {"btver1"}, .Value: {.Kind: CK_BTVER1, .KeyFeature: FEATURE_SSE4_A, .Features: FeaturesBTVER1, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false} },
448 { .Names: {"btver2"}, .Value: {.Kind: CK_BTVER2, .KeyFeature: FEATURE_BMI, .Features: FeaturesBTVER2, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false} },
449 // Bulldozer architecture processors.
450 { .Names: {"bdver1"}, .Value: {.Kind: CK_BDVER1, .KeyFeature: FEATURE_XOP, .Features: FeaturesBDVER1, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false} },
451 { .Names: {"bdver2"}, .Value: {.Kind: CK_BDVER2, .KeyFeature: FEATURE_FMA, .Features: FeaturesBDVER2, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false} },
452 { .Names: {"bdver3"}, .Value: {.Kind: CK_BDVER3, .KeyFeature: FEATURE_FMA, .Features: FeaturesBDVER3, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false} },
453 { .Names: {"bdver4"}, .Value: {.Kind: CK_BDVER4, .KeyFeature: FEATURE_AVX2, .Features: FeaturesBDVER4, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false} },
454 // Zen architecture processors.
455 { .Names: {"znver1"}, .Value: {.Kind: CK_ZNVER1, .KeyFeature: FEATURE_AVX2, .Features: FeaturesZNVER1, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false} },
456 { .Names: {"znver2"}, .Value: {.Kind: CK_ZNVER2, .KeyFeature: FEATURE_AVX2, .Features: FeaturesZNVER2, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false} },
457 { .Names: {"znver3"}, .Value: {.Kind: CK_ZNVER3, .KeyFeature: FEATURE_AVX2, .Features: FeaturesZNVER3, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false} },
458 { .Names: {"znver4"}, .Value: {.Kind: CK_ZNVER4, .KeyFeature: FEATURE_AVX512VBMI2, .Features: FeaturesZNVER4, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false} },
459 { .Names: {"znver5"}, .Value: {.Kind: CK_ZNVER5, .KeyFeature: FEATURE_AVX512VP2INTERSECT, .Features: FeaturesZNVER5, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false} },
460 { .Names: {"znver6"}, .Value: {.Kind: CK_ZNVER6, .KeyFeature: FEATURE_AVX512FP16, .Features: FeaturesZNVER6, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false} },
461 // Hygon processors.
462 { .Names: {"c86-4g-m4"}, .Value: {.Kind: CK_C86_4G_M4, .KeyFeature: FEATURE_AVX2, .Features: FeaturesC86_4G_M4 , .Mangling: '\0', .OnlyForCPUDispatchSpecific: false} },
463 { .Names: {"c86-4g-m6"}, .Value: {.Kind: CK_C86_4G_M6, .KeyFeature: FEATURE_AVX2, .Features: FeaturesC86_4G_M6 , .Mangling: '\0', .OnlyForCPUDispatchSpecific: false} },
464 { .Names: {"c86-4g-m7"}, .Value: {.Kind: CK_C86_4G_M7, .KeyFeature: FEATURE_AVX512VBMI2, .Features: FeaturesC86_4G_M7 , .Mangling: '\0', .OnlyForCPUDispatchSpecific: false} },
465 { .Names: {"c86-4g-m8"}, .Value: {.Kind: CK_C86_4G_M8, .KeyFeature: FEATURE_AVX512VBMI2, .Features: FeaturesC86_4G_M8 , .Mangling: '\0', .OnlyForCPUDispatchSpecific: false} },
466 // Generic 64-bit processor.
467 { .Names: {"x86-64"}, .Value: {.Kind: CK_x86_64, .KeyFeature: FEATURE_SSE2 , .Features: FeaturesX86_64, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false} },
468 { .Names: {"x86-64-v2"}, .Value: {.Kind: CK_x86_64_v2, .KeyFeature: FEATURE_SSE4_2 , .Features: FeaturesX86_64_V2, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false} },
469 { .Names: {"x86-64-v3"}, .Value: {.Kind: CK_x86_64_v3, .KeyFeature: FEATURE_AVX2, .Features: FeaturesX86_64_V3, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false} },
470 { .Names: {"x86-64-v4"}, .Value: {.Kind: CK_x86_64_v4, .KeyFeature: FEATURE_AVX512VL, .Features: FeaturesX86_64_V4, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false} },
471 // Geode processors.
472 { .Names: {"geode"}, .Value: {.Kind: CK_Geode, .KeyFeature: ~0U, .Features: FeaturesGeode, .Mangling: '\0', .OnlyForCPUDispatchSpecific: false} },
473};
474// clang-format on
475constexpr auto Processors = BUILD_ENUM_STRINGS(ProcessorDefs);
476
477constexpr const char *NoTuneList[] = {"x86-64-v2", "x86-64-v3", "x86-64-v4"};
478
479X86::CPUKind llvm::X86::parseArchX86(StringRef CPU, bool Only64Bit) {
480 for (const auto &P : Processors)
481 if (!P.value().OnlyForCPUDispatchSpecific && P.name() == CPU &&
482 (P.value().Features[FEATURE_64BIT] || !Only64Bit))
483 return P.value().Kind;
484
485 return CK_None;
486}
487
488X86::CPUKind llvm::X86::parseTuneCPU(StringRef CPU, bool Only64Bit) {
489 if (llvm::is_contained(Range: NoTuneList, Element: CPU))
490 return CK_None;
491 return parseArchX86(CPU, Only64Bit);
492}
493
494void llvm::X86::fillValidCPUArchList(SmallVectorImpl<StringRef> &Values,
495 bool Only64Bit) {
496 for (const auto &P : Processors)
497 if (!P.value().OnlyForCPUDispatchSpecific && !P.name().empty() &&
498 (P.value().Features[FEATURE_64BIT] || !Only64Bit))
499 Values.emplace_back(Args: P.name());
500}
501
502void llvm::X86::fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values,
503 bool Only64Bit) {
504 for (const auto &P : Processors)
505 if (!P.value().OnlyForCPUDispatchSpecific && !P.name().empty() &&
506 (P.value().Features[FEATURE_64BIT] || !Only64Bit) &&
507 !llvm::is_contained(Range: NoTuneList, Element: P.name()))
508 Values.emplace_back(Args: P.name());
509}
510
511ProcessorFeatures llvm::X86::getKeyFeature(X86::CPUKind Kind) {
512 // FIXME: Can we avoid a linear search here? The table might be sorted by
513 // CPUKind so we could binary search?
514 for (const auto &P : Processors) {
515 if (P.value().Kind == Kind) {
516 assert(P.value().KeyFeature != ~0U &&
517 "Processor does not have a key feature.");
518 return static_cast<ProcessorFeatures>(P.value().KeyFeature);
519 }
520 }
521
522 llvm_unreachable("Unable to find CPU kind!");
523}
524
525// Features with no dependencies.
526constexpr FeatureBitset ImpliedFeatures64BIT = {};
527constexpr FeatureBitset ImpliedFeaturesADX = {};
528constexpr FeatureBitset ImpliedFeaturesBMI = {};
529constexpr FeatureBitset ImpliedFeaturesBMI2 = {};
530constexpr FeatureBitset ImpliedFeaturesCLDEMOTE = {};
531constexpr FeatureBitset ImpliedFeaturesCLFLUSHOPT = {};
532constexpr FeatureBitset ImpliedFeaturesCLWB = {};
533constexpr FeatureBitset ImpliedFeaturesCLZERO = {};
534constexpr FeatureBitset ImpliedFeaturesCMOV = {};
535constexpr FeatureBitset ImpliedFeaturesCMPXCHG16B = {};
536constexpr FeatureBitset ImpliedFeaturesCMPXCHG8B = {};
537constexpr FeatureBitset ImpliedFeaturesCRC32 = {};
538constexpr FeatureBitset ImpliedFeaturesENQCMD = {};
539constexpr FeatureBitset ImpliedFeaturesFSGSBASE = {};
540constexpr FeatureBitset ImpliedFeaturesFXSR = {};
541constexpr FeatureBitset ImpliedFeaturesINVPCID = {};
542constexpr FeatureBitset ImpliedFeaturesLWP = {};
543constexpr FeatureBitset ImpliedFeaturesLZCNT = {};
544constexpr FeatureBitset ImpliedFeaturesMMX = {};
545constexpr FeatureBitset ImpliedFeaturesMWAITX = {};
546constexpr FeatureBitset ImpliedFeaturesMOVBE = {};
547constexpr FeatureBitset ImpliedFeaturesMOVDIR64B = {};
548constexpr FeatureBitset ImpliedFeaturesMOVDIRI = {};
549constexpr FeatureBitset ImpliedFeaturesPCONFIG = {};
550constexpr FeatureBitset ImpliedFeaturesPOPCNT = {};
551constexpr FeatureBitset ImpliedFeaturesPKU = {};
552constexpr FeatureBitset ImpliedFeaturesPRFCHW = {};
553constexpr FeatureBitset ImpliedFeaturesPTWRITE = {};
554constexpr FeatureBitset ImpliedFeaturesRDPID = {};
555constexpr FeatureBitset ImpliedFeaturesRDPRU = {};
556constexpr FeatureBitset ImpliedFeaturesRDRND = {};
557constexpr FeatureBitset ImpliedFeaturesRDSEED = {};
558constexpr FeatureBitset ImpliedFeaturesRTM = {};
559constexpr FeatureBitset ImpliedFeaturesSAHF = {};
560constexpr FeatureBitset ImpliedFeaturesSERIALIZE = {};
561constexpr FeatureBitset ImpliedFeaturesSGX = {};
562constexpr FeatureBitset ImpliedFeaturesSHSTK = {};
563constexpr FeatureBitset ImpliedFeaturesTBM = {};
564constexpr FeatureBitset ImpliedFeaturesTSXLDTRK = {};
565constexpr FeatureBitset ImpliedFeaturesUINTR = {};
566constexpr FeatureBitset ImpliedFeaturesUSERMSR = {};
567constexpr FeatureBitset ImpliedFeaturesWAITPKG = {};
568constexpr FeatureBitset ImpliedFeaturesWBNOINVD = {};
569constexpr FeatureBitset ImpliedFeaturesVZEROUPPER = {};
570constexpr FeatureBitset ImpliedFeaturesX87 = {};
571constexpr FeatureBitset ImpliedFeaturesXSAVE = {};
572
573// Not really CPU features, but need to be in the table because clang uses
574// target features to communicate them to the backend.
575constexpr FeatureBitset ImpliedFeaturesRETPOLINE_EXTERNAL_THUNK = {};
576constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_BRANCHES = {};
577constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_CALLS = {};
578constexpr FeatureBitset ImpliedFeaturesLVI_CFI = {};
579constexpr FeatureBitset ImpliedFeaturesLVI_LOAD_HARDENING = {};
580
581// XSAVE features are dependent on basic XSAVE.
582constexpr FeatureBitset ImpliedFeaturesXSAVEC = FeatureXSAVE;
583constexpr FeatureBitset ImpliedFeaturesXSAVEOPT = FeatureXSAVE;
584constexpr FeatureBitset ImpliedFeaturesXSAVES = FeatureXSAVE;
585
586// SSE/AVX/AVX512F chain.
587constexpr FeatureBitset ImpliedFeaturesSSE = {};
588constexpr FeatureBitset ImpliedFeaturesSSE2 = FeatureSSE;
589constexpr FeatureBitset ImpliedFeaturesSSE3 = FeatureSSE2;
590constexpr FeatureBitset ImpliedFeaturesSSSE3 = FeatureSSE3;
591constexpr FeatureBitset ImpliedFeaturesSSE4_1 = FeatureSSSE3;
592constexpr FeatureBitset ImpliedFeaturesSSE4_2 = FeatureSSE4_1;
593constexpr FeatureBitset ImpliedFeaturesAVX = FeatureSSE4_2;
594constexpr FeatureBitset ImpliedFeaturesAVX2 = FeatureAVX;
595constexpr FeatureBitset ImpliedFeaturesEVEX512 = {};
596constexpr FeatureBitset ImpliedFeaturesAVX512F =
597 FeatureAVX2 | FeatureF16C | FeatureFMA;
598
599// Vector extensions that build on SSE or AVX.
600constexpr FeatureBitset ImpliedFeaturesAES = FeatureSSE2;
601constexpr FeatureBitset ImpliedFeaturesF16C = FeatureAVX;
602constexpr FeatureBitset ImpliedFeaturesFMA = FeatureAVX;
603constexpr FeatureBitset ImpliedFeaturesGFNI = FeatureSSE2;
604constexpr FeatureBitset ImpliedFeaturesPCLMUL = FeatureSSE2;
605constexpr FeatureBitset ImpliedFeaturesSHA = FeatureSSE2;
606constexpr FeatureBitset ImpliedFeaturesVAES = FeatureAES | FeatureAVX2;
607constexpr FeatureBitset ImpliedFeaturesVPCLMULQDQ = FeatureAVX | FeaturePCLMUL;
608constexpr FeatureBitset ImpliedFeaturesSM3 = FeatureAVX;
609constexpr FeatureBitset ImpliedFeaturesSM4 = FeatureAVX2;
610
611// AVX512 features.
612constexpr FeatureBitset ImpliedFeaturesAVX512CD = FeatureAVX512F;
613constexpr FeatureBitset ImpliedFeaturesAVX512BW = FeatureAVX512F;
614constexpr FeatureBitset ImpliedFeaturesAVX512DQ = FeatureAVX512F;
615constexpr FeatureBitset ImpliedFeaturesAVX512VL = FeatureAVX512F;
616
617constexpr FeatureBitset ImpliedFeaturesAVX512BF16 = FeatureAVX512BW;
618constexpr FeatureBitset ImpliedFeaturesAVX512BITALG = FeatureAVX512BW;
619constexpr FeatureBitset ImpliedFeaturesAVX512BMM = FeatureAVX512BW;
620constexpr FeatureBitset ImpliedFeaturesAVX512IFMA = FeatureAVX512F;
621constexpr FeatureBitset ImpliedFeaturesAVX512VNNI = FeatureAVX512F;
622constexpr FeatureBitset ImpliedFeaturesAVX512VPOPCNTDQ = FeatureAVX512F;
623constexpr FeatureBitset ImpliedFeaturesAVX512VBMI = FeatureAVX512BW;
624constexpr FeatureBitset ImpliedFeaturesAVX512VBMI2 = FeatureAVX512BW;
625constexpr FeatureBitset ImpliedFeaturesAVX512VP2INTERSECT = FeatureAVX512F;
626
627// FIXME: These two aren't really implemented and just exist in the feature
628// list for __builtin_cpu_supports. So omit their dependencies.
629constexpr FeatureBitset ImpliedFeaturesAVX5124FMAPS = {};
630constexpr FeatureBitset ImpliedFeaturesAVX5124VNNIW = {};
631
632// SSE4_A->FMA4->XOP chain.
633constexpr FeatureBitset ImpliedFeaturesSSE4_A = FeatureSSE3;
634constexpr FeatureBitset ImpliedFeaturesFMA4 = FeatureAVX | FeatureSSE4_A;
635constexpr FeatureBitset ImpliedFeaturesXOP = FeatureFMA4;
636
637// AMX Features
638constexpr FeatureBitset ImpliedFeaturesAMX_TILE = {};
639constexpr FeatureBitset ImpliedFeaturesAMX_BF16 = FeatureAMX_TILE;
640constexpr FeatureBitset ImpliedFeaturesAMX_FP16 = FeatureAMX_TILE;
641constexpr FeatureBitset ImpliedFeaturesAMX_INT8 = FeatureAMX_TILE;
642constexpr FeatureBitset ImpliedFeaturesAMX_COMPLEX = FeatureAMX_TILE;
643constexpr FeatureBitset ImpliedFeaturesAMX_FP8 = FeatureAMX_TILE;
644constexpr FeatureBitset ImpliedFeaturesAMX_MOVRS = FeatureAMX_TILE;
645constexpr FeatureBitset ImpliedFeaturesAMX_AVX512 =
646 FeatureAMX_TILE | FeatureAVX10_2;
647constexpr FeatureBitset ImpliedFeaturesHRESET = {};
648
649constexpr FeatureBitset ImpliedFeaturesPREFETCHI = {};
650constexpr FeatureBitset ImpliedFeaturesCMPCCXADD = {};
651constexpr FeatureBitset ImpliedFeaturesRAOINT = {};
652constexpr FeatureBitset ImpliedFeaturesAVXVNNIINT16 = FeatureAVX2;
653constexpr FeatureBitset ImpliedFeaturesAVXVNNIINT8 = FeatureAVX2;
654constexpr FeatureBitset ImpliedFeaturesAVXIFMA = FeatureAVX2;
655constexpr FeatureBitset ImpliedFeaturesAVXNECONVERT = FeatureAVX2;
656constexpr FeatureBitset ImpliedFeaturesSHA512 = FeatureAVX2;
657constexpr FeatureBitset ImpliedFeaturesAVX512FP16 = FeatureAVX512BW;
658// Key Locker Features
659constexpr FeatureBitset ImpliedFeaturesKL = FeatureSSE2;
660constexpr FeatureBitset ImpliedFeaturesWIDEKL = FeatureKL;
661
662// AVXVNNI Features
663constexpr FeatureBitset ImpliedFeaturesAVXVNNI = FeatureAVX2;
664
665// AVX10 Features
666constexpr FeatureBitset ImpliedFeaturesAVX10_1 =
667 FeatureAVX512CD | FeatureAVX512VBMI | FeatureAVX512IFMA |
668 FeatureAVX512VNNI | FeatureAVX512BF16 | FeatureAVX512VPOPCNTDQ |
669 FeatureAVX512VBMI2 | FeatureAVX512BITALG | FeatureAVX512FP16 |
670 FeatureAVX512DQ | FeatureAVX512VL;
671constexpr FeatureBitset ImpliedFeaturesAVX10_2 = FeatureAVX10_1;
672
673// APX Features
674constexpr FeatureBitset ImpliedFeaturesEGPR = {};
675constexpr FeatureBitset ImpliedFeaturesPush2Pop2 = {};
676constexpr FeatureBitset ImpliedFeaturesPPX = {};
677constexpr FeatureBitset ImpliedFeaturesNDD = {};
678constexpr FeatureBitset ImpliedFeaturesCCMP = {};
679constexpr FeatureBitset ImpliedFeaturesNF = {};
680constexpr FeatureBitset ImpliedFeaturesCF = {};
681constexpr FeatureBitset ImpliedFeaturesZU = {};
682constexpr FeatureBitset ImpliedFeaturesJMPABS = {};
683
684constexpr FeatureBitset ImpliedFeaturesAPXF =
685 ImpliedFeaturesEGPR | ImpliedFeaturesPush2Pop2 | ImpliedFeaturesPPX |
686 ImpliedFeaturesNDD | ImpliedFeaturesCCMP | ImpliedFeaturesNF |
687 ImpliedFeaturesCF | ImpliedFeaturesZU | ImpliedFeaturesJMPABS;
688
689constexpr FeatureBitset ImpliedFeaturesMOVRS = {};
690
691constexpr EnumStringDef<FeatureBitset> FeatureInfoDefs[] = {
692#define X86_FEATURE(ENUM, STR) {{"+" STR}, ImpliedFeatures##ENUM},
693#include "llvm/TargetParser/X86TargetParser.def"
694};
695constexpr auto FeatureInfos = BUILD_ENUM_STRINGS(FeatureInfoDefs);
696
697void llvm::X86::getFeaturesForCPU(StringRef CPU,
698 SmallVectorImpl<StringRef> &EnabledFeatures,
699 bool NeedPlus) {
700 auto I =
701 llvm::find_if(Range: Processors, P: [&](const auto &P) { return P.name() == CPU; });
702 assert(I != std::end(Processors) && "Processor not found!");
703
704 FeatureBitset Bits = I->value().Features;
705
706 // Remove the 64-bit feature which we only use to validate if a CPU can
707 // be used with 64-bit mode.
708 Bits &= ~Feature64BIT;
709
710 // Add the string version of all set bits.
711 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i) {
712 StringRef Name = FeatureInfos[i].name().drop_front(N: !NeedPlus);
713 if (Bits[i] && !Name.empty())
714 EnabledFeatures.push_back(Elt: Name);
715 }
716}
717
718// For each feature that is (transitively) implied by this feature, set it.
719static void getImpliedEnabledFeatures(FeatureBitset &Bits,
720 const FeatureBitset &Implies) {
721 // Fast path: Implies is often empty.
722 if (!Implies.any())
723 return;
724 FeatureBitset Prev;
725 Bits |= Implies;
726 do {
727 Prev = Bits;
728 for (unsigned i = CPU_FEATURE_MAX; i;)
729 if (Bits[--i])
730 Bits |= FeatureInfos[i].value();
731 } while (Prev != Bits);
732}
733
734/// Create bit vector of features that are implied disabled if the feature
735/// passed in Value is disabled.
736static void getImpliedDisabledFeatures(FeatureBitset &Bits, unsigned Value) {
737 // Check all features looking for any dependent on this feature. If we find
738 // one, mark it and recursively find any feature that depend on it.
739 FeatureBitset Prev;
740 Bits.set(Value);
741 do {
742 Prev = Bits;
743 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
744 if ((FeatureInfos[i].value() & Bits).any())
745 Bits.set(i);
746 } while (Prev != Bits);
747}
748
749void llvm::X86::updateImpliedFeatures(
750 StringRef Feature, bool Enabled,
751 StringMap<bool> &Features) {
752 auto I = llvm::find_if(Range: FeatureInfos, P: [&](const auto &FI) {
753 return FI.name().drop_front() == Feature;
754 });
755 if (I == std::end(cont: FeatureInfos)) {
756 // FIXME: This shouldn't happen, but may not have all features in the table
757 // yet.
758 return;
759 }
760
761 FeatureBitset ImpliedBits;
762 if (Enabled)
763 getImpliedEnabledFeatures(Bits&: ImpliedBits, Implies: I->value());
764 else
765 getImpliedDisabledFeatures(Bits&: ImpliedBits,
766 Value: std::distance(first: std::begin(cont: FeatureInfos), last: I));
767
768 // Update the map entry for all implied features.
769 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i) {
770 StringRef Name = FeatureInfos[i].name().drop_front();
771 if (ImpliedBits[i] && !Name.empty())
772 Features[Name] = Enabled;
773 }
774}
775
776char llvm::X86::getCPUDispatchMangling(StringRef CPU) {
777 auto I =
778 llvm::find_if(Range: Processors, P: [&](const auto &P) { return P.name() == CPU; });
779 assert(I != std::end(Processors) && "Processor not found!");
780 assert(I->value().Mangling != '\0' &&
781 "Processor dooesn't support function multiversion!");
782 return I->value().Mangling;
783}
784
785bool llvm::X86::validateCPUSpecificCPUDispatch(StringRef Name) {
786 auto I = llvm::find_if(Range: Processors,
787 P: [&](const auto &P) { return P.name() == Name; });
788 return I != std::end(cont: Processors);
789}
790
791std::array<uint32_t, 4>
792llvm::X86::getCpuSupportsMask(ArrayRef<StringRef> FeatureStrs) {
793 // Processor features and mapping to processor feature value.
794 std::array<uint32_t, 4> FeatureMask{};
795 for (StringRef FeatureStr : FeatureStrs) {
796 // ABI_VALUE is used to match values in compiler-rt/libgcc
797 unsigned Feature = StringSwitch<unsigned>(FeatureStr)
798#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY, ABI_VALUE) .Case(STR, ABI_VALUE)
799#define X86_MICROARCH_LEVEL(ENUM, STR, PRIORITY, ABI_VALUE) \
800 .Case(STR, ABI_VALUE)
801#include "llvm/TargetParser/X86TargetParser.def"
802 ;
803 assert(Feature / 32 < FeatureMask.size());
804 FeatureMask[Feature / 32] |= 1U << (Feature % 32);
805 }
806 return FeatureMask;
807}
808
809unsigned llvm::X86::getFeaturePriority(ProcessorFeatures Feat) {
810#ifndef NDEBUG
811 // Check that priorities are set properly in the .def file. We expect that
812 // "compat" features are assigned non-duplicate consecutive priorities
813 // starting from one (1, ..., MAX_PRIORITY) and multiple zeros.
814#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY, ABI_VALUE) PRIORITY,
815 unsigned Priorities[] = {
816#include "llvm/TargetParser/X86TargetParser.def"
817 };
818 std::array<unsigned, std::size(Priorities)> HelperList;
819 std::iota(HelperList.begin(), HelperList.begin() + MAX_PRIORITY + 1, 0);
820 for (size_t i = MAX_PRIORITY + 1; i != std::size(Priorities); ++i)
821 HelperList[i] = 0;
822 assert(std::is_permutation(HelperList.begin(), HelperList.end(),
823 std::begin(Priorities), std::end(Priorities)) &&
824 "Priorities don't form consecutive range!");
825#endif
826
827 switch (Feat) {
828#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY, ABI_VALUE) \
829 case X86::FEATURE_##ENUM: \
830 return PRIORITY;
831#include "llvm/TargetParser/X86TargetParser.def"
832 default:
833 llvm_unreachable("No Feature Priority for non-CPUSupports Features");
834 }
835}
836