1//===- SeedCollection.cpp - Seed collection pass --------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "llvm/Transforms/Vectorize/SandboxVectorizer/Passes/SeedCollection.h"
10#include "llvm/Analysis/TargetTransformInfo.h"
11#include "llvm/SandboxIR/Module.h"
12#include "llvm/SandboxIR/Region.h"
13#include "llvm/Transforms/Vectorize/SandboxVectorizer/SandboxVectorizerPassBuilder.h"
14#include "llvm/Transforms/Vectorize/SandboxVectorizer/SeedCollector.h"
15#include "llvm/Transforms/Vectorize/SandboxVectorizer/VecUtils.h"
16
17namespace llvm {
18
19static cl::opt<unsigned>
20 OverrideVecRegBits("sbvec-vec-reg-bits", cl::init(Val: 0), cl::Hidden,
21 cl::desc("Override the vector register size in bits, "
22 "which is otherwise found by querying TTI."));
23static cl::opt<bool>
24 AllowNonPow2("sbvec-allow-non-pow2", cl::init(Val: false), cl::Hidden,
25 cl::desc("Allow non-power-of-2 vectorization."));
26
27#define LoadSeedsDef "loads"
28#define StoreSeedsDef "stores"
29cl::opt<std::string> CollectSeeds(
30 "sbvec-collect-seeds", cl::init(StoreSeedsDef), cl::Hidden,
31 cl::desc("Collect these seeds. Use empty for none or a comma-separated "
32 "list of '" StoreSeedsDef "' and '" LoadSeedsDef "'."));
33
34namespace sandboxir {
35
36SeedCollection::SeedCollection(StringRef Pipeline, StringRef AuxArg)
37 : FunctionPass("seed-collection"),
38 RPM("rpm", Pipeline, SandboxVectorizerPassBuilder::createRegionPass) {
39 if (!AuxArg.empty()) {
40 if (AuxArg != DiffTypesArgStr) {
41 std::string ErrStr;
42 raw_string_ostream ErrSS(ErrStr);
43 ErrSS << "SeedCollection only supports '" << DiffTypesArgStr
44 << "' aux argument!\n";
45 reportFatalUsageError(reason: ErrStr.c_str());
46 }
47 AllowDiffTypes = true;
48 }
49}
50
51bool SeedCollection::runOnFunction(Function &F, const Analyses &A) {
52 bool Change = false;
53 const auto &DL = F.getParent()->getDataLayout();
54 unsigned VecRegBits =
55 OverrideVecRegBits != 0
56 ? OverrideVecRegBits
57 : A.getTTI()
58 .getRegisterBitWidth(K: TargetTransformInfo::RGK_FixedWidthVector)
59 .getFixedValue();
60 bool CollectStores = CollectSeeds.find(StoreSeedsDef) != std::string::npos;
61 bool CollectLoads = CollectSeeds.find(LoadSeedsDef) != std::string::npos;
62
63 // TODO: Start from innermost BBs first
64 for (auto &BB : F) {
65 SeedCollector SC(&BB, A.getScalarEvolution(), CollectStores, CollectLoads,
66 AllowDiffTypes);
67 for (SeedBundle &Seeds : SC.getStoreSeeds()) {
68 unsigned ElmBits =
69 Utils::getNumBits(Ty: VecUtils::getElementType(Ty: Utils::getExpectedType(
70 V: Seeds[Seeds.getFirstUnusedElementIdx()])),
71 DL);
72
73 auto DivideBy2 = [](unsigned Num) {
74 auto Floor = VecUtils::getFloorPowerOf2(Num);
75 if (Floor == Num)
76 return Floor / 2;
77 return Floor;
78 };
79 // Try to create the largest vector supported by the target. If it fails
80 // reduce the vector size by half.
81 for (unsigned SliceElms = std::min(a: VecRegBits / ElmBits,
82 b: Seeds.getNumUnusedBits() / ElmBits);
83 SliceElms >= 2u; SliceElms = DivideBy2(SliceElms)) {
84 if (Seeds.allUsed())
85 break;
86 // Keep trying offsets after FirstUnusedElementIdx, until we vectorize
87 // the slice. This could be quite expensive, so we enforce a limit.
88 for (unsigned Offset = Seeds.getFirstUnusedElementIdx(),
89 OE = Seeds.size();
90 Offset + 1 < OE; Offset += 1) {
91 // Seeds are getting used as we vectorize, so skip them.
92 if (Seeds.isUsed(Element: Offset))
93 continue;
94 if (Seeds.allUsed())
95 break;
96
97 auto SeedSlice =
98 Seeds.getSlice(StartIdx: Offset, MaxVecRegBits: SliceElms * ElmBits, ForcePowOf2: !AllowNonPow2);
99 if (SeedSlice.empty())
100 continue;
101
102 assert(SeedSlice.size() >= 2 && "Should have been rejected!");
103
104 // Create a region containing the seed slice.
105 auto &Ctx = F.getContext();
106 Region Rgn(Ctx, A.getTTI());
107 Rgn.setAux(SeedSlice);
108 // Run the region pass pipeline.
109 Change |= RPM.runOnRegion(R&: Rgn, A);
110 Rgn.clearAux();
111 }
112 }
113 }
114 }
115 return Change;
116}
117} // namespace sandboxir
118} // namespace llvm
119