1//===- CodeGenRegisters.cpp - Register and RegisterClass Info -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines structures to encapsulate information gleaned from the
10// target register and register class definitions.
11//
12//===----------------------------------------------------------------------===//
13
14#include "CodeGenRegisters.h"
15#include "llvm/ADT/ArrayRef.h"
16#include "llvm/ADT/BitVector.h"
17#include "llvm/ADT/DenseMap.h"
18#include "llvm/ADT/IntEqClasses.h"
19#include "llvm/ADT/PointerUnion.h"
20#include "llvm/ADT/PostOrderIterator.h"
21#include "llvm/ADT/STLExtras.h"
22#include "llvm/ADT/SetVector.h"
23#include "llvm/ADT/SmallPtrSet.h"
24#include "llvm/ADT/SmallSet.h"
25#include "llvm/ADT/SmallVector.h"
26#include "llvm/ADT/StringRef.h"
27#include "llvm/ADT/StringSet.h"
28#include "llvm/ADT/Twine.h"
29#include "llvm/Support/Debug.h"
30#include "llvm/Support/raw_ostream.h"
31#include "llvm/TableGen/Error.h"
32#include "llvm/TableGen/Record.h"
33#include "llvm/TableGen/TGTimer.h"
34#include <algorithm>
35#include <cassert>
36#include <cstdint>
37#include <iterator>
38#include <map>
39#include <queue>
40#include <string>
41#include <tuple>
42#include <utility>
43#include <vector>
44
45using namespace llvm;
46
47#define DEBUG_TYPE "regalloc-emitter"
48
49//===----------------------------------------------------------------------===//
50// CodeGenSubRegIndex
51//===----------------------------------------------------------------------===//
52
53CodeGenSubRegIndex::CodeGenSubRegIndex(const Record *R, unsigned Enum,
54 const CodeGenHwModes &CGH)
55 : TheDef(R), Name(R->getName().str()), EnumValue(Enum),
56 AllSuperRegsCovered(true), Artificial(true) {
57 if (R->getValue(Name: "Namespace"))
58 Namespace = R->getValueAsString(FieldName: "Namespace").str();
59
60 if (const Record *RV = R->getValueAsOptionalDef(FieldName: "SubRegRanges"))
61 Range = SubRegRangeByHwMode(RV, CGH);
62 if (!Range.hasDefault())
63 Range.insertSubRegRangeForMode(Mode: DefaultMode, Info: SubRegRange(R));
64}
65
66CodeGenSubRegIndex::CodeGenSubRegIndex(StringRef N, StringRef Nspace,
67 unsigned Enum)
68 : TheDef(nullptr), Name(N.str()), Namespace(Nspace.str()),
69 Range(SubRegRange(-1, -1)), EnumValue(Enum), AllSuperRegsCovered(true),
70 Artificial(true) {}
71
72std::string CodeGenSubRegIndex::getQualifiedName() const {
73 std::string N = getNamespace();
74 if (!N.empty())
75 N += "::";
76 N += getName();
77 return N;
78}
79
80void CodeGenSubRegIndex::updateComponents(CodeGenRegBank &RegBank) {
81 if (!TheDef)
82 return;
83
84 std::vector<const Record *> Comps =
85 TheDef->getValueAsListOfDefs(FieldName: "ComposedOf");
86 if (!Comps.empty()) {
87 if (Comps.size() != 2)
88 PrintFatalError(ErrorLoc: TheDef->getLoc(),
89 Msg: "ComposedOf must have exactly two entries");
90 CodeGenSubRegIndex *A = RegBank.getSubRegIdx(Comps[0]);
91 CodeGenSubRegIndex *B = RegBank.getSubRegIdx(Comps[1]);
92 CodeGenSubRegIndex *X = A->addComposite(A: B, B: this, CGH: RegBank.getHwModes());
93 if (X)
94 PrintFatalError(ErrorLoc: TheDef->getLoc(), Msg: "Ambiguous ComposedOf entries");
95 }
96
97 std::vector<const Record *> Parts =
98 TheDef->getValueAsListOfDefs(FieldName: "CoveringSubRegIndices");
99 if (!Parts.empty()) {
100 if (Parts.size() < 2)
101 PrintFatalError(ErrorLoc: TheDef->getLoc(),
102 Msg: "CoveringSubRegIndices must have two or more entries");
103 SmallVector<CodeGenSubRegIndex *, 8> IdxParts;
104 for (const Record *Part : Parts)
105 IdxParts.push_back(Elt: RegBank.getSubRegIdx(Part));
106 setConcatenationOf(IdxParts);
107 }
108}
109
110LaneBitmask CodeGenSubRegIndex::computeLaneMask() const {
111 // Already computed?
112 if (LaneMask.any())
113 return LaneMask;
114
115 // Recursion guard, shouldn't be required.
116 LaneMask = LaneBitmask::getAll();
117
118 // The lane mask is simply the union of all sub-indices.
119 LaneBitmask M;
120 for (const auto &C : Composed)
121 M |= C.second->computeLaneMask();
122 assert(M.any() && "Missing lane mask, sub-register cycle?");
123 LaneMask = M;
124 return LaneMask;
125}
126
127void CodeGenSubRegIndex::setConcatenationOf(
128 ArrayRef<CodeGenSubRegIndex *> Parts) {
129 if (ConcatenationOf.empty()) {
130 ConcatenationOf.assign(in_start: Parts.begin(), in_end: Parts.end());
131 return;
132 }
133 assert(llvm::equal(Parts, ConcatenationOf) && "parts consistent");
134}
135
136void CodeGenSubRegIndex::computeConcatTransitiveClosure() {
137 for (SmallVectorImpl<CodeGenSubRegIndex *>::iterator I =
138 ConcatenationOf.begin();
139 I != ConcatenationOf.end();
140 /*empty*/) {
141 CodeGenSubRegIndex *SubIdx = *I;
142 SubIdx->computeConcatTransitiveClosure();
143#ifndef NDEBUG
144 for (CodeGenSubRegIndex *SRI : SubIdx->ConcatenationOf)
145 assert(SRI->ConcatenationOf.empty() && "No transitive closure?");
146#endif
147
148 if (SubIdx->ConcatenationOf.empty()) {
149 ++I;
150 } else {
151 I = ConcatenationOf.erase(CI: I);
152 I = ConcatenationOf.insert(I, From: SubIdx->ConcatenationOf.begin(),
153 To: SubIdx->ConcatenationOf.end());
154 I += SubIdx->ConcatenationOf.size();
155 }
156 }
157}
158
159//===----------------------------------------------------------------------===//
160// CodeGenRegister
161//===----------------------------------------------------------------------===//
162
163CodeGenRegister::CodeGenRegister(const Record *R, unsigned Enum)
164 : TheDef(R), EnumValue(Enum),
165 CostPerUse(R->getValueAsListOfInts(FieldName: "CostPerUse")),
166 CoveredBySubRegs(R->getValueAsBit(FieldName: "CoveredBySubRegs")),
167 Constant(R->getValueAsBit(FieldName: "isConstant")), SubRegsComplete(false),
168 SuperRegsComplete(false), TopoSig(~0u) {
169 Artificial = R->getValueAsBit(FieldName: "isArtificial");
170}
171
172void CodeGenRegister::buildObjectGraph(CodeGenRegBank &RegBank) {
173 std::vector<const Record *> SRIs =
174 TheDef->getValueAsListOfDefs(FieldName: "SubRegIndices");
175 std::vector<const Record *> SRs = TheDef->getValueAsListOfDefs(FieldName: "SubRegs");
176
177 for (const auto &[SRI, SR] : zip_equal(t&: SRIs, u&: SRs)) {
178 ExplicitSubRegIndices.push_back(Elt: RegBank.getSubRegIdx(SRI));
179 ExplicitSubRegs.push_back(Elt: RegBank.getReg(SR));
180 }
181
182 // Also compute leading super-registers. Each register has a list of
183 // covered-by-subregs super-registers where it appears as the first explicit
184 // sub-register.
185 //
186 // This is used by computeSecondarySubRegs() to find candidates.
187 if (CoveredBySubRegs && !ExplicitSubRegs.empty())
188 ExplicitSubRegs.front()->LeadingSuperRegs.push_back(x: this);
189
190 // Add ad hoc alias links. This is a symmetric relationship between two
191 // registers, so build a symmetric graph by adding links in both ends.
192 for (const Record *Alias : TheDef->getValueAsListOfDefs(FieldName: "Aliases")) {
193 CodeGenRegister *Reg = RegBank.getReg(Alias);
194 ExplicitAliases.push_back(Elt: Reg);
195 Reg->ExplicitAliases.push_back(Elt: this);
196 }
197}
198
199// Inherit register units from subregisters.
200// Return true if the RegUnits changed.
201bool CodeGenRegister::inheritRegUnits(CodeGenRegBank &RegBank) {
202 bool changed = false;
203 for (const auto &[_, SR] : SubRegs) {
204 // Merge the subregister's units into this register's RegUnits.
205 changed |= (RegUnits |= SR->RegUnits);
206 }
207
208 return changed;
209}
210
211const CodeGenRegister::SubRegMap &
212CodeGenRegister::computeSubRegs(CodeGenRegBank &RegBank) {
213 // Only compute this map once.
214 if (SubRegsComplete)
215 return SubRegs;
216 SubRegsComplete = true;
217
218 HasDisjunctSubRegs = ExplicitSubRegs.size() > 1;
219
220 // First insert the explicit subregs and make sure they are fully indexed.
221 for (auto [SR, Idx] : zip_equal(t&: ExplicitSubRegs, u&: ExplicitSubRegIndices)) {
222 if (!SR->Artificial)
223 Idx->Artificial = false;
224 if (!SubRegs.try_emplace(k: Idx, args&: SR).second)
225 PrintFatalError(ErrorLoc: TheDef->getLoc(), Msg: "SubRegIndex " + Idx->getName() +
226 " appears twice in Register " +
227 getName());
228 // Map explicit sub-registers first, so the names take precedence.
229 // The inherited sub-registers are mapped below.
230 SubReg2Idx.try_emplace(Key: SR, Args&: Idx);
231 }
232
233 // Keep track of inherited subregs and how they can be reached.
234 SmallPtrSet<CodeGenRegister *, 8> Orphans;
235
236 // Clone inherited subregs and place duplicate entries in Orphans.
237 // Here the order is important - earlier subregs take precedence.
238 for (CodeGenRegister *ESR : ExplicitSubRegs) {
239 const SubRegMap &Map = ESR->computeSubRegs(RegBank);
240 HasDisjunctSubRegs |= ESR->HasDisjunctSubRegs;
241
242 for (const auto &SR : Map) {
243 if (!SubRegs.insert(x: SR).second)
244 Orphans.insert(Ptr: SR.second);
245 }
246 }
247
248 // Expand any composed subreg indices.
249 // If dsub_2 has ComposedOf = [qsub_1, dsub_0], and this register has a
250 // qsub_1 subreg, add a dsub_2 subreg. Keep growing Indices and process
251 // expanded subreg indices recursively.
252 SmallVector<CodeGenSubRegIndex *, 8> Indices = ExplicitSubRegIndices;
253 for (unsigned i = 0; i != Indices.size(); ++i) {
254 CodeGenSubRegIndex *Idx = Indices[i];
255 const CodeGenSubRegIndex::CompMap &Comps = Idx->getComposites();
256 CodeGenRegister *SR = SubRegs[Idx];
257 const SubRegMap &Map = SR->computeSubRegs(RegBank);
258
259 // Look at the possible compositions of Idx.
260 // They may not all be supported by SR.
261 for (auto [Key, Val] : Comps) {
262 SubRegMap::const_iterator SRI = Map.find(x: Key);
263 if (SRI == Map.end())
264 continue; // Idx + I->first doesn't exist in SR.
265 // Add `Val` as a name for the subreg SRI->second, assuming it is
266 // orphaned, and the name isn't already used for something else.
267 if (SubRegs.count(x: Val) || !Orphans.erase(Ptr: SRI->second))
268 continue;
269 // We found a new name for the orphaned sub-register.
270 SubRegs.try_emplace(k: Val, args: SRI->second);
271 Indices.push_back(Elt: Val);
272 }
273 }
274
275 // Now Orphans contains the inherited subregisters without a direct index.
276 // Create inferred indexes for all missing entries.
277 // Work backwards in the Indices vector in order to compose subregs bottom-up.
278 // Consider this subreg sequence:
279 //
280 // qsub_1 -> dsub_0 -> ssub_0
281 //
282 // The qsub_1 -> dsub_0 composition becomes dsub_2, so the ssub_0 register
283 // can be reached in two different ways:
284 //
285 // qsub_1 -> ssub_0
286 // dsub_2 -> ssub_0
287 //
288 // We pick the latter composition because another register may have [dsub_0,
289 // dsub_1, dsub_2] subregs without necessarily having a qsub_1 subreg. The
290 // dsub_2 -> ssub_0 composition can be shared.
291 while (!Indices.empty() && !Orphans.empty()) {
292 CodeGenSubRegIndex *Idx = Indices.pop_back_val();
293 CodeGenRegister *SR = SubRegs[Idx];
294 const SubRegMap &Map = SR->computeSubRegs(RegBank);
295 for (const auto &[SRI, SubReg] : Map)
296 if (Orphans.erase(Ptr: SubReg))
297 SubRegs[RegBank.getCompositeSubRegIndex(A: Idx, B: SRI)] = SubReg;
298 }
299
300 // Compute the inverse SubReg -> Idx map.
301 for (auto &[SRI, SubReg] : SubRegs) {
302 if (SubReg == this) {
303 ArrayRef<SMLoc> Loc;
304 if (TheDef)
305 Loc = TheDef->getLoc();
306 PrintFatalError(ErrorLoc: Loc, Msg: "Register " + getName() +
307 " has itself as a sub-register");
308 }
309
310 // Compute AllSuperRegsCovered.
311 if (!CoveredBySubRegs)
312 SRI->AllSuperRegsCovered = false;
313
314 // Ensure that every sub-register has a unique name.
315 DenseMap<const CodeGenRegister *, CodeGenSubRegIndex *>::iterator Ins =
316 SubReg2Idx.try_emplace(Key: SubReg, Args: SRI).first;
317 if (Ins->second == SRI)
318 continue;
319 // Trouble: Two different names for SubReg.second.
320 ArrayRef<SMLoc> Loc;
321 if (TheDef)
322 Loc = TheDef->getLoc();
323 PrintFatalError(ErrorLoc: Loc, Msg: "Sub-register can't have two names: " +
324 SubReg->getName() + " available as " +
325 SRI->getName() + " and " + Ins->second->getName());
326 }
327
328 // Derive possible names for sub-register concatenations from any explicit
329 // sub-registers. By doing this before computeSecondarySubRegs(), we ensure
330 // that getConcatSubRegIndex() won't invent any concatenated indices that the
331 // user already specified.
332 for (auto [Idx, SR] : enumerate(First&: ExplicitSubRegs)) {
333 if (!SR->CoveredBySubRegs || SR->Artificial)
334 continue;
335
336 // SR is composed of multiple sub-regs. Find their names in this register.
337 bool AnyArtificial = false;
338 SmallVector<CodeGenSubRegIndex *, 8> Parts;
339 for (unsigned j = 0, e = SR->ExplicitSubRegs.size(); j != e; ++j) {
340 CodeGenSubRegIndex &I = *SR->ExplicitSubRegIndices[j];
341 if (I.Artificial) {
342 AnyArtificial = true;
343 break;
344 }
345 Parts.push_back(Elt: getSubRegIndex(Reg: SR->ExplicitSubRegs[j]));
346 }
347
348 if (AnyArtificial)
349 continue;
350
351 // Offer this as an existing spelling for the concatenation of Parts.
352 ExplicitSubRegIndices[Idx]->setConcatenationOf(Parts);
353 }
354
355 // Initialize RegUnitList. Because getSubRegs is called recursively, this
356 // processes the register hierarchy in postorder.
357 if (ExplicitSubRegs.empty()) {
358 // Create one register unit per leaf register. These units correspond to the
359 // maximal cliques in the register overlap graph which is optimal.
360 RegUnits.set(RegBank.newRegUnit(R0: this));
361 } else {
362 // Inherit all sub-register units. It is good enough to look at the explicit
363 // sub-registers, the other registers won't contribute any more units.
364 for (const CodeGenRegister *SR : ExplicitSubRegs)
365 RegUnits |= SR->RegUnits;
366 }
367
368 // When there is ad hoc aliasing, we simply create one unit per edge in the
369 // undirected ad hoc aliasing graph. Technically, we could do better by
370 // identifying maximal cliques in the ad hoc graph, but cliques larger than 2
371 // are extremely rare anyway (I've never seen one), so we don't bother with
372 // the added complexity.
373 for (CodeGenRegister *AR : ExplicitAliases) {
374 // Only visit each edge once.
375 if (AR->SubRegsComplete)
376 continue;
377 // Create a RegUnit representing this alias edge, and add it to both
378 // registers.
379 unsigned Unit = RegBank.newRegUnit(R0: this, R1: AR);
380 RegUnits.set(Unit);
381 AR->RegUnits.set(Unit);
382 }
383
384 // We have now computed the native register units. More may be adopted later
385 // for balancing purposes.
386 NativeRegUnits = RegUnits;
387
388 return SubRegs;
389}
390
391// In a register that is covered by its sub-registers, try to find redundant
392// sub-registers. For example:
393//
394// QQ0 = {Q0, Q1}
395// Q0 = {D0, D1}
396// Q1 = {D2, D3}
397//
398// We can infer that D1_D2 is also a sub-register, even if it wasn't named in
399// the register definition.
400//
401// The explicitly specified registers form a tree. This function discovers
402// sub-register relationships that would force a DAG.
403//
404void CodeGenRegister::computeSecondarySubRegs(CodeGenRegBank &RegBank) {
405 SmallVector<SubRegMap::value_type, 8> NewSubRegs;
406
407 std::queue<std::pair<CodeGenSubRegIndex *, CodeGenRegister *>> SubRegQueue;
408 for (auto [SRI, SubReg] : SubRegs)
409 SubRegQueue.emplace(args: SRI, args&: SubReg);
410
411 // Look at the leading super-registers of each sub-register. Those are the
412 // candidates for new sub-registers, assuming they are fully contained in
413 // this register.
414 while (!SubRegQueue.empty()) {
415 auto [SubRegIdx, SubReg] = SubRegQueue.front();
416 SubRegQueue.pop();
417
418 const CodeGenRegister::SuperRegList &Leads = SubReg->LeadingSuperRegs;
419 for (const CodeGenRegister *Cand : Leads) {
420 // Already got this sub-register?
421 if (Cand == this || getSubRegIndex(Reg: Cand))
422 continue;
423 // Check if each component of Cand is already a sub-register.
424 assert(!Cand->ExplicitSubRegs.empty() &&
425 "Super-register has no sub-registers");
426 if (Cand->ExplicitSubRegs.size() == 1)
427 continue;
428 SmallVector<CodeGenSubRegIndex *, 8> Parts;
429 // We know that the first component is (SubRegIdx,SubReg). However we
430 // may still need to split it into smaller subregister parts.
431 assert(Cand->ExplicitSubRegs[0] == SubReg && "LeadingSuperRegs correct");
432 assert(getSubRegIndex(SubReg) == SubRegIdx && "LeadingSuperRegs correct");
433 for (CodeGenRegister *SubReg : Cand->ExplicitSubRegs) {
434 if (CodeGenSubRegIndex *SubRegIdx = getSubRegIndex(Reg: SubReg)) {
435 if (SubRegIdx->ConcatenationOf.empty())
436 Parts.push_back(Elt: SubRegIdx);
437 else
438 append_range(C&: Parts, R&: SubRegIdx->ConcatenationOf);
439 } else {
440 // Sub-register doesn't exist.
441 Parts.clear();
442 break;
443 }
444 }
445 // There is nothing to do if some Cand sub-register is not part of this
446 // register.
447 if (Parts.empty())
448 continue;
449
450 // Each part of Cand is a sub-register of this. Make the full Cand also
451 // a sub-register with a concatenated sub-register index.
452 CodeGenSubRegIndex *Concat =
453 RegBank.getConcatSubRegIndex(Parts, CGH: RegBank.getHwModes());
454 std::pair<CodeGenSubRegIndex *, CodeGenRegister *> NewSubReg = {
455 Concat, const_cast<CodeGenRegister *>(Cand)};
456
457 if (!SubRegs.insert(x&: NewSubReg).second)
458 continue;
459
460 // We inserted a new subregister.
461 NewSubRegs.push_back(Elt: NewSubReg);
462 SubRegQueue.push(x: NewSubReg);
463 SubReg2Idx.try_emplace(Key: Cand, Args&: Concat);
464 }
465 }
466
467 // Create sub-register index composition maps for the synthesized indices.
468 for (auto [NewIdx, NewSubReg] : NewSubRegs) {
469 for (auto [SRI, SubReg] : NewSubReg->SubRegs) {
470 CodeGenSubRegIndex *SubIdx = getSubRegIndex(Reg: SubReg);
471 if (!SubIdx)
472 PrintFatalError(ErrorLoc: TheDef->getLoc(), Msg: "No SubRegIndex for " +
473 SubReg->getName() + " in " +
474 getName());
475 NewIdx->addComposite(A: SRI, B: SubIdx, CGH: RegBank.getHwModes());
476 }
477 }
478}
479
480void CodeGenRegister::computeSuperRegs(CodeGenRegBank &RegBank) {
481 // Only visit each register once.
482 if (SuperRegsComplete)
483 return;
484 SuperRegsComplete = true;
485
486 // Make sure all sub-registers have been visited first, so the super-reg
487 // lists will be topologically ordered.
488 for (auto SubReg : SubRegs)
489 SubReg.second->computeSuperRegs(RegBank);
490
491 // Now add this as a super-register on all sub-registers.
492 // Also compute the TopoSigId in post-order.
493 TopoSigId Id;
494 for (auto SubReg : SubRegs) {
495 // Topological signature computed from SubIdx, TopoId(SubReg).
496 // Loops and idempotent indices have TopoSig = ~0u.
497 Id.push_back(Elt: SubReg.first->EnumValue);
498 Id.push_back(Elt: SubReg.second->TopoSig);
499
500 // Don't add duplicate entries.
501 if (!SubReg.second->SuperRegs.empty() &&
502 SubReg.second->SuperRegs.back() == this)
503 continue;
504 SubReg.second->SuperRegs.push_back(x: this);
505 }
506 TopoSig = RegBank.getTopoSig(Id);
507}
508
509void CodeGenRegister::addSubRegsPreOrder(
510 SetVector<const CodeGenRegister *> &OSet, CodeGenRegBank &RegBank) const {
511 assert(SubRegsComplete && "Must precompute sub-registers");
512 for (CodeGenRegister *SR : ExplicitSubRegs) {
513 if (OSet.insert(X: SR))
514 SR->addSubRegsPreOrder(OSet, RegBank);
515 }
516 // Add any secondary sub-registers that weren't part of the explicit tree.
517 OSet.insert_range(R: llvm::make_second_range(c: SubRegs));
518}
519
520// Get the sum of this register's unit weights.
521unsigned CodeGenRegister::getWeight(const CodeGenRegBank &RegBank) const {
522 unsigned Weight = 0;
523 for (unsigned RegUnit : RegUnits)
524 Weight += RegBank.getRegUnit(RUID: RegUnit).Weight;
525 return Weight;
526}
527
528//===----------------------------------------------------------------------===//
529// RegisterTuples
530//===----------------------------------------------------------------------===//
531
532// A RegisterTuples def is used to generate pseudo-registers from lists of
533// sub-registers. We provide a SetTheory expander class that returns the new
534// registers.
535namespace {
536
537struct TupleExpander : SetTheory::Expander {
538 // Reference to SynthDefs in the containing CodeGenRegBank, to keep track of
539 // the synthesized definitions for their lifetime.
540 std::vector<std::unique_ptr<Record>> &SynthDefs;
541
542 // Track all synthesized tuple names in order to detect duplicate definitions.
543 llvm::StringSet<> TupleNames;
544
545 TupleExpander(std::vector<std::unique_ptr<Record>> &SynthDefs)
546 : SynthDefs(SynthDefs) {}
547
548 void expand(SetTheory &ST, const Record *Def,
549 SetTheory::RecSet &Elts) override {
550 std::vector<const Record *> Indices =
551 Def->getValueAsListOfDefs(FieldName: "SubRegIndices");
552 unsigned Dim = Indices.size();
553 const ListInit *SubRegs = Def->getValueAsListInit(FieldName: "SubRegs");
554
555 // Evaluate the sub-register lists to be zipped.
556 unsigned Length = ~0u;
557 SmallVector<SetTheory::RecSet, 4> Lists(Dim);
558 for (unsigned i = 0; i != Dim; ++i) {
559 ST.evaluate(Expr: SubRegs->getElement(Idx: i), Elts&: Lists[i], Loc: Def->getLoc());
560 Length = std::min(a: Length, b: unsigned(Lists[i].size()));
561 }
562
563 if (Length == 0)
564 return;
565
566 // Precompute some types.
567 const Record *RegisterCl = Def->getRecords().getClass(Name: "Register");
568 const RecTy *RegisterRecTy = RecordRecTy::get(Class: RegisterCl);
569 std::vector<StringRef> RegNames =
570 Def->getValueAsListOfStrings(FieldName: "RegAsmNames");
571
572 // Zip them up.
573 RecordKeeper &RK = Def->getRecords();
574 for (unsigned n = 0; n != Length; ++n) {
575 std::string Name;
576 const Record *Proto = Lists[0][n];
577 std::vector<Init *> Tuple;
578 for (unsigned i = 0; i != Dim; ++i) {
579 const Record *Reg = Lists[i][n];
580 if (i)
581 Name += '_';
582 Name += Reg->getName();
583 Tuple.push_back(x: Reg->getDefInit());
584 }
585
586 // Take the cost list of the first register in the tuple.
587 const ListInit *CostList = Proto->getValueAsListInit(FieldName: "CostPerUse");
588 SmallVector<const Init *, 2> CostPerUse(CostList->getElements());
589
590 const StringInit *AsmName = StringInit::get(RK, "");
591 if (!RegNames.empty()) {
592 if (RegNames.size() <= n)
593 PrintFatalError(ErrorLoc: Def->getLoc(),
594 Msg: "Register tuple definition missing name for '" +
595 Name + "'.");
596 AsmName = StringInit::get(RK, RegNames[n]);
597 }
598
599 // Create a new Record representing the synthesized register. This record
600 // is only for consumption by CodeGenRegister, it is not added to the
601 // RecordKeeper.
602 SynthDefs.emplace_back(
603 args: std::make_unique<Record>(args&: Name, args: Def->getLoc(), args&: Def->getRecords()));
604 Record *NewReg = SynthDefs.back().get();
605 Elts.insert(X: NewReg);
606
607 // Detect duplicates among synthesized registers.
608 const auto Res = TupleNames.insert(key: NewReg->getName());
609 if (!Res.second)
610 PrintFatalError(ErrorLoc: Def->getLoc(),
611 Msg: "Register tuple redefines register '" + Name + "'.");
612
613 // Copy Proto super-classes.
614 for (const auto &[Super, Loc] : Proto->getDirectSuperClasses())
615 NewReg->addDirectSuperClass(R: Super, Range: Loc);
616
617 // Copy Proto fields.
618 for (RecordVal RV : Proto->getValues()) {
619 // Skip existing fields, like NAME.
620 if (NewReg->getValue(Name: RV.getNameInit()))
621 continue;
622
623 StringRef Field = RV.getName();
624
625 // Replace the sub-register list with Tuple.
626 if (Field == "SubRegs")
627 RV.setValue(ListInit::get(Range: Tuple, EltTy: RegisterRecTy));
628
629 if (Field == "AsmName")
630 RV.setValue(AsmName);
631
632 // CostPerUse is aggregated from all Tuple members.
633 if (Field == "CostPerUse")
634 RV.setValue(ListInit::get(Range: CostPerUse, EltTy: CostList->getElementType()));
635
636 // Composite registers are always covered by sub-registers.
637 if (Field == "CoveredBySubRegs")
638 RV.setValue(BitInit::get(RK, V: true));
639
640 // Copy fields from the RegisterTuples def.
641 if (Field == "SubRegIndices") {
642 NewReg->addValue(RV: *Def->getValue(Name: Field));
643 continue;
644 }
645
646 // Some fields get their default uninitialized value.
647 if (Field == "DwarfNumbers" || Field == "DwarfAlias" ||
648 Field == "Aliases") {
649 if (const RecordVal *DefRV = RegisterCl->getValue(Name: Field))
650 NewReg->addValue(RV: *DefRV);
651 continue;
652 }
653
654 // Everything else is copied from Proto.
655 NewReg->addValue(RV);
656 }
657 }
658 }
659};
660
661} // end anonymous namespace
662
663//===----------------------------------------------------------------------===//
664// CodeGenRegisterClass
665//===----------------------------------------------------------------------===//
666
667static void sortAndUniqueRegisters(CodeGenRegister::Vec &M) {
668 llvm::sort(C&: M, Comp: deref<std::less<>>());
669 M.erase(first: llvm::unique(R&: M, P: deref<std::equal_to<>>()), last: M.end());
670}
671
672CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank,
673 const Record *R)
674 : TheDef(R), Name(R->getName().str()),
675 RegsWithSuperRegsTopoSigs(RegBank.getNumTopoSigs()), EnumValue(-1),
676 TSFlags(0) {
677 GeneratePressureSet = R->getValueAsBit(FieldName: "GeneratePressureSet");
678 for (const Record *Type : R->getValueAsListOfDefs(FieldName: "RegTypes"))
679 VTs.push_back(Elt: getValueTypeByHwMode(Rec: Type, CGH: RegBank.getHwModes()));
680
681 // Allocation order 0 is the full set. AltOrders provides others.
682 const SetTheory::RecVec *Elements = RegBank.getSets().expand(Set: R);
683 const ListInit *AltOrders = R->getValueAsListInit(FieldName: "AltOrders");
684 Orders.resize(new_size: 1 + AltOrders->size());
685
686 // Default allocation order always contains all registers.
687 MemberBV.resize(N: RegBank.getRegisters().size());
688 Artificial = true;
689 for (const Record *Element : *Elements) {
690 Orders[0].push_back(Elt: Element);
691 const CodeGenRegister *Reg = RegBank.getReg(Element);
692 Members.push_back(x: Reg);
693 MemberBV.set(CodeGenRegBank::getRegIndex(Reg));
694 Artificial &= Reg->Artificial;
695 if (!Reg->getSuperRegs().empty())
696 RegsWithSuperRegsTopoSigs.set(Reg->getTopoSig());
697 }
698 sortAndUniqueRegisters(M&: Members);
699
700 // Alternative allocation orders may be subsets.
701 SetTheory::RecSet Order;
702 for (auto [Idx, AltOrderElem] : enumerate(First: AltOrders->getElements())) {
703 RegBank.getSets().evaluate(Expr: AltOrderElem, Elts&: Order, Loc: R->getLoc());
704 Orders[1 + Idx].append(in_start: Order.begin(), in_end: Order.end());
705 // Verify that all altorder members are regclass members.
706 while (!Order.empty()) {
707 CodeGenRegister *Reg = RegBank.getReg(Order.back());
708 Order.pop_back();
709 if (!contains(Reg))
710 PrintFatalError(ErrorLoc: R->getLoc(), Msg: " AltOrder register " + Reg->getName() +
711 " is not a class member");
712 }
713 }
714
715 Namespace = R->getValueAsString(FieldName: "Namespace");
716
717 if (const Record *RV = R->getValueAsOptionalDef(FieldName: "RegInfos"))
718 RSI = RegSizeInfoByHwMode(RV, RegBank.getHwModes());
719 unsigned Size = R->getValueAsInt(FieldName: "Size");
720 if (!RSI.hasDefault() && Size == 0 && !VTs[0].isSimple())
721 PrintFatalError(ErrorLoc: R->getLoc(), Msg: "Impossible to determine register size");
722 if (!RSI.hasDefault()) {
723 RegSizeInfo RI;
724 RI.RegSize = RI.SpillSize =
725 Size ? Size : VTs[0].getSimple().getSizeInBits();
726 RI.SpillAlignment = R->getValueAsInt(FieldName: "Alignment");
727 RSI.insertRegSizeForMode(Mode: DefaultMode, Info: RI);
728 }
729
730 int CopyCostParsed = R->getValueAsInt(FieldName: "CopyCost");
731 Allocatable = R->getValueAsBit(FieldName: "isAllocatable");
732 AltOrderSelect = R->getValueAsString(FieldName: "AltOrderSelect");
733 int AllocationPriority = R->getValueAsInt(FieldName: "AllocationPriority");
734 if (!isUInt<5>(x: AllocationPriority))
735 PrintFatalError(ErrorLoc: R->getLoc(), Msg: "AllocationPriority out of range [0,31]");
736 this->AllocationPriority = AllocationPriority;
737
738 GlobalPriority = R->getValueAsBit(FieldName: "GlobalPriority");
739
740 const BitsInit *TSF = R->getValueAsBitsInit(FieldName: "TSFlags");
741 TSFlags = uint8_t(*TSF->convertInitializerToInt());
742
743 // Saturate negative costs to the maximum
744 if (CopyCostParsed < 0)
745 CopyCost = std::numeric_limits<uint8_t>::max();
746 else if (!isUInt<8>(x: CopyCostParsed))
747 PrintFatalError(ErrorLoc: R->getLoc(), Msg: "'CopyCost' must be an 8-bit value");
748
749 CopyCost = CopyCostParsed;
750}
751
752// Create an inferred register class that was missing from the .td files.
753// Most properties will be inherited from the closest super-class after the
754// class structure has been computed.
755CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank,
756 StringRef Name, Key Props)
757 : Members(*Props.Members), TheDef(nullptr), Name(Name.str()),
758 RegsWithSuperRegsTopoSigs(RegBank.getNumTopoSigs()), EnumValue(-1),
759 RSI(Props.RSI), CopyCost(0), Allocatable(true), AllocationPriority(0),
760 GlobalPriority(false), TSFlags(0) {
761 MemberBV.resize(N: RegBank.getRegisters().size());
762 Artificial = true;
763 GeneratePressureSet = false;
764 for (const auto R : Members) {
765 MemberBV.set(CodeGenRegBank::getRegIndex(Reg: R));
766 if (!R->getSuperRegs().empty())
767 RegsWithSuperRegsTopoSigs.set(R->getTopoSig());
768 Artificial &= R->Artificial;
769 }
770}
771
772// Compute inherited properties for a synthesized register class.
773void CodeGenRegisterClass::inheritProperties(CodeGenRegBank &RegBank) {
774 assert(!getDef() && "Only synthesized classes can inherit properties");
775 assert(!SuperClasses.empty() && "Synthesized class without super class");
776
777 // The last super-class is the smallest one in topological order. Check for
778 // allocatable super-classes and inherit from the nearest allocatable one if
779 // any.
780 auto NearestAllocSCRIt =
781 find_if(Range: reverse(C&: SuperClasses),
782 P: [&](const CodeGenRegisterClass *S) { return S->Allocatable; });
783 CodeGenRegisterClass &Super = NearestAllocSCRIt == SuperClasses.rend()
784 ? *SuperClasses.back()
785 : **NearestAllocSCRIt;
786
787 // Most properties are copied directly.
788 // Exceptions are members, size, and alignment
789 Namespace = Super.Namespace;
790 VTs = Super.VTs;
791 CopyCost = Super.CopyCost;
792 Allocatable = Super.Allocatable;
793 AltOrderSelect = Super.AltOrderSelect;
794 AllocationPriority = Super.AllocationPriority;
795 GlobalPriority = Super.GlobalPriority;
796 TSFlags = Super.TSFlags;
797 GeneratePressureSet |= Super.GeneratePressureSet;
798
799 // Copy all allocation orders, filter out foreign registers from the larger
800 // super-class.
801 Orders.resize(new_size: Super.Orders.size());
802 for (auto [Idx, Outer] : enumerate(First&: Super.Orders))
803 for (const Record *Reg : Outer)
804 if (contains(RegBank.getReg(Reg)))
805 Orders[Idx].push_back(Elt: Reg);
806}
807
808bool CodeGenRegisterClass::hasType(const ValueTypeByHwMode &VT) const {
809 if (llvm::is_contained(Range: VTs, Element: VT))
810 return true;
811
812 // If VT is not identical to any of this class's types, but is a simple
813 // type, check if any of the types for this class contain it under some
814 // mode.
815 // The motivating example came from RISC-V, where (likely because of being
816 // guarded by "64-bit" predicate), the type of X5 was {*:[i64]}, but the
817 // type in GRC was {*:[i32], m1:[i64]}.
818 if (VT.isSimple()) {
819 MVT T = VT.getSimple();
820 for (const ValueTypeByHwMode &OurVT : VTs) {
821 if (llvm::is_contained(Range: llvm::make_second_range(c: OurVT), Element: T))
822 return true;
823 }
824 }
825 return false;
826}
827
828bool CodeGenRegisterClass::contains(const CodeGenRegister *Reg) const {
829 return MemberBV.test(Idx: CodeGenRegBank::getRegIndex(Reg));
830}
831
832unsigned CodeGenRegisterClass::getWeight(const CodeGenRegBank &RegBank) const {
833 if (TheDef && !TheDef->isValueUnset(FieldName: "Weight"))
834 return TheDef->getValueAsInt(FieldName: "Weight");
835
836 if (Members.empty() || Artificial)
837 return 0;
838
839 return (*Members.begin())->getWeight(RegBank);
840}
841
842// This is a simple lexicographical order that can be used to search for sets.
843// It is not the same as the topological order provided by TopoOrderRC.
844bool CodeGenRegisterClass::Key::operator<(
845 const CodeGenRegisterClass::Key &B) const {
846 assert(Members && B.Members);
847
848 // Lexicographical comparison. Ignores artificial registers when asked.
849 auto IA = Members->begin(), EA = Members->end();
850 auto IB = B.Members->begin(), EB = B.Members->end();
851 for (;;) {
852 while (IgnoreArtificialMembers && IA != EA && (*IA)->Artificial)
853 ++IA;
854 while (IgnoreArtificialMembers && IB != EB && (*IB)->Artificial)
855 ++IB;
856 if (IA == EA && IB == EB)
857 break;
858 if (IA == EA || IB == EB)
859 return IA == EA;
860 if (**IA != **IB)
861 return **IA < **IB;
862 ++IA;
863 ++IB;
864 }
865 return RSI < B.RSI;
866}
867
868// Returns true if RC is a strict subclass.
869// RC is a sub-class of this class if it is a valid replacement for any
870// instruction operand where a register of this classis required. It must
871// satisfy these conditions:
872//
873// 1. All RC registers are also in this.
874// 2. The RC spill size must not be smaller than our spill size.
875// 3. RC spill alignment must be compatible with ours.
876//
877static bool testSubClass(const CodeGenRegisterClass *A,
878 const CodeGenRegisterClass *B) {
879 return A->RSI.isSubClassOf(I: B->RSI) &&
880 llvm::includes(Range1: A->getMembers(), Range2: B->getMembers(), C: deref<std::less<>>());
881}
882
883/// Sorting predicate for register classes. This provides a topological
884/// ordering that arranges all register classes before their sub-classes.
885///
886/// Register classes with the same registers, spill size, and alignment form a
887/// clique. They will be ordered alphabetically.
888///
889static bool TopoOrderRC(const CodeGenRegisterClass &A,
890 const CodeGenRegisterClass &B) {
891 if (&A == &B)
892 return false;
893
894 constexpr size_t SIZET_MAX = std::numeric_limits<size_t>::max();
895
896 // Sort in the following order:
897 // (a) first by register size in ascending order.
898 // (b) then by set size in descending order.
899 // (c) finally, by name as a tie breaker.
900 //
901 // For set size, note that the classes' allocation order may not have been
902 // computed yet, but the members set is always valid. Also, since we use
903 // std::tie() < operator for ordering, we can achieve the descending set size
904 // ordering by using (SIZET_MAX - set_size) in the std::tie.
905 return std::tuple(A.RSI, SIZET_MAX - A.getMembers().size(),
906 StringRef(A.getName())) <
907 std::tuple(B.RSI, SIZET_MAX - B.getMembers().size(),
908 StringRef(B.getName()));
909}
910
911std::string CodeGenRegisterClass::getNamespaceQualification() const {
912 return Namespace.empty() ? "" : (Namespace + "::").str();
913}
914
915std::string CodeGenRegisterClass::getQualifiedName() const {
916 return getNamespaceQualification() + getName();
917}
918
919std::string CodeGenRegisterClass::getIdName() const {
920 return getName() + "RegClassID";
921}
922
923std::string CodeGenRegisterClass::getQualifiedIdName() const {
924 return getNamespaceQualification() + getIdName();
925}
926
927// Compute sub-classes of all register classes.
928// Assume the classes are ordered topologically.
929void CodeGenRegisterClass::computeSubClasses(CodeGenRegBank &RegBank) {
930 std::list<CodeGenRegisterClass> &RegClasses = RegBank.getRegClasses();
931
932 const size_t NumRegClasses = RegClasses.size();
933 // Visit backwards so sub-classes are seen first.
934 for (auto I = RegClasses.rbegin(), E = RegClasses.rend(); I != E; ++I) {
935 CodeGenRegisterClass &RC = *I;
936 RC.SubClasses.resize(N: NumRegClasses);
937 RC.SubClasses.set(RC.EnumValue);
938 if (RC.Artificial)
939 continue;
940
941 // Normally, all subclasses have IDs >= rci, unless RC is part of a clique.
942 for (auto I2 = I.base(), E2 = RegClasses.end(); I2 != E2; ++I2) {
943 CodeGenRegisterClass &SubRC = *I2;
944 if (RC.SubClasses.test(Idx: SubRC.EnumValue))
945 continue;
946 if (!testSubClass(A: &RC, B: &SubRC))
947 continue;
948 // SubRC is a sub-class. Grap all its sub-classes so we won't have to
949 // check them again.
950 RC.SubClasses |= SubRC.SubClasses;
951 }
952
953 // Sweep up missed clique members. They will be immediately preceding RC.
954 for (auto I2 = std::next(x: I); I2 != E && testSubClass(A: &RC, B: &*I2); ++I2)
955 RC.SubClasses.set(I2->EnumValue);
956 }
957
958 // Compute the SuperClasses lists from the SubClasses vectors.
959 for (auto &RC : RegClasses) {
960 const BitVector &SC = RC.getSubClasses();
961 auto I = RegClasses.begin();
962 for (int s = 0, next_s = SC.find_first(); next_s != -1;
963 next_s = SC.find_next(Prev: s)) {
964 std::advance(i&: I, n: next_s - s);
965 s = next_s;
966 if (&*I == &RC)
967 continue;
968 I->SuperClasses.push_back(Elt: &RC);
969 }
970 }
971
972 // With the class hierarchy in place, let synthesized register classes inherit
973 // properties from their closest super-class. The iteration order here can
974 // propagate properties down multiple levels.
975 for (CodeGenRegisterClass &RC : RegClasses)
976 if (!RC.getDef())
977 RC.inheritProperties(RegBank);
978}
979
980std::optional<std::pair<CodeGenRegisterClass *, CodeGenRegisterClass *>>
981CodeGenRegisterClass::getMatchingSubClassWithSubRegs(
982 CodeGenRegBank &RegBank, const CodeGenSubRegIndex *SubIdx) const {
983 auto WeakSizeOrder = [this](const CodeGenRegisterClass *A,
984 const CodeGenRegisterClass *B) {
985 // If there are multiple, identical register classes, prefer the original
986 // register class.
987 if (A == B)
988 return false;
989 if (A->getMembers().size() == B->getMembers().size()) {
990 if (A->getBaseClassOrder() != B->getBaseClassOrder())
991 return A->getBaseClassOrder() > B->getBaseClassOrder();
992 return A == this;
993 }
994 return A->getMembers().size() > B->getMembers().size();
995 };
996
997 std::list<CodeGenRegisterClass> &RegClasses = RegBank.getRegClasses();
998
999 // Find all the subclasses of this one that fully support the sub-register
1000 // index and order them by size. BiggestSuperRC should always be first.
1001 CodeGenRegisterClass *BiggestSuperRegRC = getSubClassWithSubReg(SubIdx);
1002 if (!BiggestSuperRegRC)
1003 return std::nullopt;
1004 BitVector SuperRegRCsBV = BiggestSuperRegRC->getSubClasses();
1005 std::vector<CodeGenRegisterClass *> SuperRegRCs;
1006 for (auto &RC : RegClasses)
1007 if (SuperRegRCsBV[RC.EnumValue])
1008 SuperRegRCs.emplace_back(args: &RC);
1009 llvm::stable_sort(Range&: SuperRegRCs, C: WeakSizeOrder);
1010
1011 assert((SuperRegRCs.front() == BiggestSuperRegRC ||
1012 SuperRegRCs.front()->getBaseClassOrder() >
1013 BiggestSuperRegRC->getBaseClassOrder()) &&
1014 "Biggest class wasn't first");
1015
1016 // Find all the subreg classes and order them by size too.
1017 std::vector<std::pair<CodeGenRegisterClass *, BitVector>> SuperRegClasses;
1018 for (auto &RC : RegClasses) {
1019 BitVector SuperRegClassesBV(RegClasses.size());
1020 RC.getSuperRegClasses(SubIdx, Out&: SuperRegClassesBV);
1021 if (SuperRegClassesBV.any())
1022 SuperRegClasses.emplace_back(args: &RC, args&: SuperRegClassesBV);
1023 }
1024 llvm::stable_sort(Range&: SuperRegClasses,
1025 C: [&](const std::pair<CodeGenRegisterClass *, BitVector> &A,
1026 const std::pair<CodeGenRegisterClass *, BitVector> &B) {
1027 return WeakSizeOrder(A.first, B.first);
1028 });
1029
1030 // Find the biggest subclass and subreg class such that R:subidx is in the
1031 // subreg class for all R in subclass.
1032 //
1033 // For example:
1034 // All registers in X86's GR64 have a sub_32bit subregister but no class
1035 // exists that contains all the 32-bit subregisters because GR64 contains RIP
1036 // but GR32 does not contain EIP. Instead, we constrain SuperRegRC to
1037 // GR32_with_sub_8bit (which is identical to GR32_with_sub_32bit) and then,
1038 // having excluded RIP, we are able to find a SubRegRC (GR32).
1039 CodeGenRegisterClass *ChosenSuperRegClass = nullptr;
1040 CodeGenRegisterClass *SubRegRC = nullptr;
1041 for (CodeGenRegisterClass *SuperRegRC : SuperRegRCs) {
1042 for (const auto &[SuperRegClass, SuperRegClassBV] : SuperRegClasses) {
1043 if (SuperRegClassBV[SuperRegRC->EnumValue]) {
1044 SubRegRC = SuperRegClass;
1045 ChosenSuperRegClass = SuperRegRC;
1046
1047 // If SubRegRC is bigger than SuperRegRC then there are members of
1048 // SubRegRC that don't have super registers via SubIdx. Keep looking to
1049 // find a better fit and fall back on this one if there isn't one.
1050 //
1051 // This is intended to prevent X86 from making odd choices such as
1052 // picking LOW32_ADDR_ACCESS_RBP instead of GR32 in the example above.
1053 // LOW32_ADDR_ACCESS_RBP is a valid choice but contains registers that
1054 // aren't subregisters of SuperRegRC whereas GR32 has a direct 1:1
1055 // mapping.
1056 if (SuperRegRC->getMembers().size() >= SubRegRC->getMembers().size())
1057 return std::pair(ChosenSuperRegClass, SubRegRC);
1058 }
1059 }
1060
1061 // If we found a fit but it wasn't quite ideal because SubRegRC had excess
1062 // registers, then we're done.
1063 if (ChosenSuperRegClass)
1064 return std::pair(ChosenSuperRegClass, SubRegRC);
1065 }
1066
1067 return std::nullopt;
1068}
1069
1070void CodeGenRegisterClass::getSuperRegClasses(const CodeGenSubRegIndex *SubIdx,
1071 BitVector &Out) const {
1072 auto FindI = SuperRegClasses.find(Val: SubIdx);
1073 if (FindI == SuperRegClasses.end())
1074 return;
1075 for (CodeGenRegisterClass *RC : FindI->second)
1076 Out.set(RC->EnumValue);
1077}
1078
1079// Populate a unique sorted list of units from a register set.
1080void CodeGenRegisterClass::buildRegUnitSet(
1081 const CodeGenRegBank &RegBank, std::vector<unsigned> &RegUnits) const {
1082 std::vector<unsigned> TmpUnits;
1083 for (const CodeGenRegister *Reg : Members) {
1084 for (unsigned UnitI : Reg->getRegUnits()) {
1085 const RegUnit &RU = RegBank.getRegUnit(RUID: UnitI);
1086 if (!RU.Artificial)
1087 TmpUnits.push_back(x: UnitI);
1088 }
1089 }
1090 llvm::sort(C&: TmpUnits);
1091 std::unique_copy(first: TmpUnits.begin(), last: TmpUnits.end(),
1092 result: std::back_inserter(x&: RegUnits));
1093}
1094
1095// Combine our super classes of the given sub-register index with all of their
1096// super classes in turn.
1097void CodeGenRegisterClass::extendSuperRegClasses(CodeGenSubRegIndex *SubIdx) {
1098 auto It = SuperRegClasses.find(Val: SubIdx);
1099 if (It == SuperRegClasses.end())
1100 return;
1101
1102 SmallVector<CodeGenRegisterClass *> MidRCs;
1103 llvm::append_range(C&: MidRCs, R&: It->second);
1104
1105 for (CodeGenRegisterClass *MidRC : MidRCs) {
1106 for (auto &Pair : MidRC->SuperRegClasses) {
1107 CodeGenSubRegIndex *ComposedSubIdx = Pair.first->compose(Idx: SubIdx);
1108 if (!ComposedSubIdx)
1109 continue;
1110
1111 for (CodeGenRegisterClass *SuperRC : Pair.second)
1112 addSuperRegClass(SubIdx: ComposedSubIdx, SuperRC);
1113 }
1114 }
1115}
1116
1117//===----------------------------------------------------------------------===//
1118// CodeGenRegisterCategory
1119//===----------------------------------------------------------------------===//
1120
1121CodeGenRegisterCategory::CodeGenRegisterCategory(CodeGenRegBank &RegBank,
1122 const Record *R)
1123 : TheDef(R), Name(R->getName().str()) {
1124 for (const Record *RegClass : R->getValueAsListOfDefs(FieldName: "Classes"))
1125 Classes.push_back(x: RegBank.getRegClass(RegClass));
1126}
1127
1128//===----------------------------------------------------------------------===//
1129// CodeGenRegBank
1130//===----------------------------------------------------------------------===//
1131
1132CodeGenRegBank::CodeGenRegBank(const RecordKeeper &Records,
1133 const CodeGenHwModes &Modes,
1134 const bool RegistersAreIntervals)
1135 : Records(Records), CGH(Modes),
1136 RegistersAreIntervals(RegistersAreIntervals) {
1137 // Configure register Sets to understand register classes and tuples.
1138 Sets.addFieldExpander(ClassName: "RegisterClass", FieldName: "MemberList");
1139 Sets.addFieldExpander(ClassName: "CalleeSavedRegs", FieldName: "SaveList");
1140 Sets.addExpander(ClassName: "RegisterTuples",
1141 std::make_unique<TupleExpander>(args&: SynthDefs));
1142
1143 // Read in the user-defined (named) sub-register indices.
1144 // More indices will be synthesized later.
1145 for (const Record *SRI : Records.getAllDerivedDefinitions(ClassName: "SubRegIndex"))
1146 getSubRegIdx(SRI);
1147 // Build composite maps from ComposedOf fields.
1148 for (auto &Idx : SubRegIndices)
1149 Idx.updateComponents(RegBank&: *this);
1150
1151 // Read in the register and register tuple definitions.
1152 const RecordKeeper &RC = Records;
1153 std::vector<const Record *> Regs = RC.getAllDerivedDefinitions(ClassName: "Register");
1154 if (!Regs.empty() && Regs[0]->isSubClassOf(Name: "X86Reg")) {
1155 // For X86, we need to sort Registers and RegisterTuples together to list
1156 // new registers and register tuples at a later position. So that we can
1157 // reduce unnecessary iterations on unsupported registers in LiveVariables.
1158 // TODO: Remove this logic when migrate from LiveVariables to LiveIntervals
1159 // completely.
1160 for (const Record *R : Records.getAllDerivedDefinitions(ClassName: "RegisterTuples")) {
1161 // Expand tuples and merge the vectors
1162 std::vector<const Record *> TupRegs = *Sets.expand(Set: R);
1163 llvm::append_range(C&: Regs, R&: TupRegs);
1164 }
1165
1166 llvm::sort(C&: Regs, Comp: LessRecordRegister());
1167 // Assign the enumeration values.
1168 for (const Record *Reg : Regs)
1169 getReg(Reg);
1170 } else {
1171 llvm::sort(C&: Regs, Comp: LessRecordRegister());
1172 // Assign the enumeration values.
1173 for (const Record *Reg : Regs)
1174 getReg(Reg);
1175
1176 // Expand tuples and number the new registers.
1177 for (const Record *R : Records.getAllDerivedDefinitions(ClassName: "RegisterTuples")) {
1178 std::vector<const Record *> TupRegs = *Sets.expand(Set: R);
1179 llvm::sort(C&: TupRegs, Comp: LessRecordRegister());
1180 for (const Record *RC : TupRegs)
1181 getReg(RC);
1182 }
1183 }
1184
1185 // Now all the registers are known. Build the object graph of explicit
1186 // register-register references.
1187 for (CodeGenRegister &Reg : Registers)
1188 Reg.buildObjectGraph(RegBank&: *this);
1189
1190 // Compute register name map.
1191 for (CodeGenRegister &Reg : Registers)
1192 // FIXME: This could just be RegistersByName[name] = register, except that
1193 // causes some failures in MIPS - perhaps they have duplicate register name
1194 // entries? (or maybe there's a reason for it - I don't know much about this
1195 // code, just drive-by refactoring)
1196 RegistersByName.try_emplace(Key: Reg.TheDef->getValueAsString(FieldName: "AsmName"), Args: &Reg);
1197
1198 // Precompute all sub-register maps.
1199 // This will create Composite entries for all inferred sub-register indices.
1200 for (CodeGenRegister &Reg : Registers)
1201 Reg.computeSubRegs(RegBank&: *this);
1202
1203 // Compute transitive closure of subregister index ConcatenationOf vectors
1204 // and initialize ConcatIdx map.
1205 for (CodeGenSubRegIndex &SRI : SubRegIndices) {
1206 SRI.computeConcatTransitiveClosure();
1207 if (!SRI.ConcatenationOf.empty())
1208 ConcatIdx.try_emplace(
1209 k: SmallVector<CodeGenSubRegIndex *, 8>(SRI.ConcatenationOf.begin(),
1210 SRI.ConcatenationOf.end()),
1211 args: &SRI);
1212 }
1213
1214 // Infer even more sub-registers by combining leading super-registers.
1215 for (CodeGenRegister &Reg : Registers)
1216 if (Reg.CoveredBySubRegs)
1217 Reg.computeSecondarySubRegs(RegBank&: *this);
1218
1219 // After the sub-register graph is complete, compute the topologically
1220 // ordered SuperRegs list.
1221 for (CodeGenRegister &Reg : Registers)
1222 Reg.computeSuperRegs(RegBank&: *this);
1223
1224 // For each pair of Reg:SR, if both are non-artificial, mark the
1225 // corresponding sub-register index as non-artificial.
1226 for (CodeGenRegister &Reg : Registers) {
1227 if (Reg.Artificial)
1228 continue;
1229 for (auto [SRI, SR] : Reg.getSubRegs()) {
1230 if (!SR->Artificial)
1231 SRI->Artificial = false;
1232 }
1233 }
1234
1235 computeSubRegIndicesRPOT();
1236
1237 // Native register units are associated with a leaf register. They've all been
1238 // discovered now.
1239 NumNativeRegUnits = RegUnits.size();
1240
1241 // Read in register class definitions.
1242 ArrayRef<const Record *> RCs =
1243 Records.getAllDerivedDefinitions(ClassName: "RegisterClass");
1244 if (RCs.empty())
1245 PrintFatalError(Msg: "No 'RegisterClass' subclasses defined!");
1246
1247 // Allocate user-defined register classes.
1248 for (const Record *R : RCs) {
1249 RegClasses.emplace_back(args&: *this, args&: R);
1250 CodeGenRegisterClass &RC = RegClasses.back();
1251 if (!RC.Artificial)
1252 addToMaps(&RC);
1253 }
1254
1255 // Infer missing classes to create a full algebra.
1256 computeInferredRegisterClasses();
1257
1258 // Order register classes topologically and assign enum values.
1259 RegClasses.sort(comp: TopoOrderRC);
1260 for (auto [Idx, RC] : enumerate(First&: RegClasses))
1261 RC.EnumValue = Idx;
1262 CodeGenRegisterClass::computeSubClasses(RegBank&: *this);
1263
1264 // Read in the register category definitions.
1265 for (const Record *R : Records.getAllDerivedDefinitions(ClassName: "RegisterCategory"))
1266 RegCategories.emplace_back(args&: *this, args&: R);
1267}
1268
1269// Create a synthetic CodeGenSubRegIndex without a corresponding Record.
1270CodeGenSubRegIndex *CodeGenRegBank::createSubRegIndex(StringRef Name,
1271 StringRef Namespace) {
1272 SubRegIndices.emplace_back(args&: Name, args&: Namespace, args: SubRegIndices.size() + 1);
1273 return &SubRegIndices.back();
1274}
1275
1276CodeGenSubRegIndex *CodeGenRegBank::getSubRegIdx(const Record *Def) {
1277 CodeGenSubRegIndex *&Idx = Def2SubRegIdx[Def];
1278 if (Idx)
1279 return Idx;
1280 SubRegIndices.emplace_back(args&: Def, args: SubRegIndices.size() + 1, args: getHwModes());
1281 Idx = &SubRegIndices.back();
1282 return Idx;
1283}
1284
1285const CodeGenSubRegIndex *
1286CodeGenRegBank::findSubRegIdx(const Record *Def) const {
1287 return Def2SubRegIdx.at(Val: Def);
1288}
1289
1290CodeGenRegister *CodeGenRegBank::getReg(const Record *Def) {
1291 CodeGenRegister *&Reg = Def2Reg[Def];
1292 if (Reg)
1293 return Reg;
1294 Registers.emplace_back(args&: Def, args: Registers.size() + 1);
1295 Reg = &Registers.back();
1296 return Reg;
1297}
1298
1299void CodeGenRegBank::addToMaps(CodeGenRegisterClass *RC) {
1300 if (const Record *Def = RC->getDef())
1301 Def2RC.try_emplace(Key: Def, Args&: RC);
1302
1303 // Duplicate classes are rejected by insert().
1304 // That's OK, we only care about the properties handled by CGRC::Key.
1305 CodeGenRegisterClass::Key K(*RC, /*IgnoreArtificialMembers=*/true);
1306 Key2RC.try_emplace(k: K, args&: RC);
1307}
1308
1309// Create a synthetic sub-class if it is missing.
1310std::pair<CodeGenRegisterClass *, bool>
1311CodeGenRegBank::getOrCreateSubClass(const CodeGenRegisterClass *RC,
1312 const CodeGenRegister::Vec *Members,
1313 StringRef Name) {
1314 // Synthetic sub-class has the same size and alignment as RC.
1315 CodeGenRegisterClass::Key K(Members, RC->RSI,
1316 /*IgnoreArtificialMembers=*/true);
1317 RCKeyMap::const_iterator FoundI = Key2RC.find(x: K);
1318 if (FoundI != Key2RC.end())
1319 return {FoundI->second, false};
1320
1321 // Sub-class doesn't exist, create a new one.
1322 RegClasses.emplace_back(args&: *this, args&: Name, args&: K);
1323 addToMaps(RC: &RegClasses.back());
1324 return {&RegClasses.back(), true};
1325}
1326
1327CodeGenRegisterClass *CodeGenRegBank::getRegClass(const Record *Def,
1328 ArrayRef<SMLoc> Loc) const {
1329 assert(Def->isSubClassOf("RegisterClassLike"));
1330 if (CodeGenRegisterClass *RC = Def2RC.lookup(Val: Def))
1331 return RC;
1332
1333 ArrayRef<SMLoc> DiagLoc = Loc.empty() ? Def->getLoc() : Loc;
1334 // TODO: Ideally we should update the API to allow resolving HwMode.
1335 if (Def->isSubClassOf(Name: "RegClassByHwMode"))
1336 PrintError(ErrorLoc: DiagLoc, Msg: "cannot resolve HwMode for " + Def->getName());
1337 else
1338 PrintError(ErrorLoc: DiagLoc, Msg: Def->getName() + " is not a known RegisterClass!");
1339 PrintFatalNote(ErrorLoc: Def->getLoc(), Msg: Def->getName() + " defined here");
1340}
1341
1342CodeGenSubRegIndex *
1343CodeGenRegBank::getCompositeSubRegIndex(CodeGenSubRegIndex *A,
1344 CodeGenSubRegIndex *B) {
1345 // Look for an existing entry.
1346 CodeGenSubRegIndex *Comp = A->compose(Idx: B);
1347 if (Comp)
1348 return Comp;
1349
1350 // None exists, synthesize one.
1351 std::string Name = A->getName() + "_then_" + B->getName();
1352 Comp = createSubRegIndex(Name, Namespace: A->getNamespace());
1353 A->addComposite(A: B, B: Comp, CGH: getHwModes());
1354 return Comp;
1355}
1356
1357CodeGenSubRegIndex *CodeGenRegBank::getConcatSubRegIndex(
1358 const SmallVector<CodeGenSubRegIndex *, 8> &Parts,
1359 const CodeGenHwModes &CGH) {
1360 assert(Parts.size() > 1 && "Need two parts to concatenate");
1361#ifndef NDEBUG
1362 for (CodeGenSubRegIndex *Idx : Parts) {
1363 assert(Idx->ConcatenationOf.empty() && "No transitive closure?");
1364 }
1365#endif
1366
1367 // Look for an existing entry.
1368 CodeGenSubRegIndex *&Idx = ConcatIdx[Parts];
1369 if (Idx)
1370 return Idx;
1371
1372 // None exists, synthesize one.
1373 std::string Name = Parts.front()->getName();
1374 const unsigned UnknownSize = (uint16_t)-1;
1375
1376 for (const CodeGenSubRegIndex *Part : ArrayRef(Parts).drop_front()) {
1377 Name += '_';
1378 Name += Part->getName();
1379 }
1380
1381 Idx = createSubRegIndex(Name, Namespace: Parts.front()->getNamespace());
1382 Idx->ConcatenationOf.assign(in_start: Parts.begin(), in_end: Parts.end());
1383
1384 unsigned NumModes = CGH.getNumModeIds();
1385 for (unsigned M = 0; M < NumModes; ++M) {
1386 const CodeGenSubRegIndex *FirstPart = Parts.front();
1387
1388 // Determine whether all parts are contiguous.
1389 bool IsContinuous = true;
1390 const SubRegRange &FirstPartRange = FirstPart->Range.get(Mode: M);
1391 unsigned Size = FirstPartRange.Size;
1392 unsigned LastOffset = FirstPartRange.Offset;
1393 unsigned LastSize = FirstPartRange.Size;
1394
1395 for (const CodeGenSubRegIndex *Part : ArrayRef(Parts).drop_front()) {
1396 const SubRegRange &PartRange = Part->Range.get(Mode: M);
1397 if (Size == UnknownSize || PartRange.Size == UnknownSize)
1398 Size = UnknownSize;
1399 else
1400 Size += PartRange.Size;
1401 if (LastSize == UnknownSize ||
1402 PartRange.Offset != (LastOffset + LastSize))
1403 IsContinuous = false;
1404 LastOffset = PartRange.Offset;
1405 LastSize = PartRange.Size;
1406 }
1407 unsigned Offset = IsContinuous ? FirstPartRange.Offset : -1;
1408 Idx->Range.get(Mode: M) = SubRegRange(Size, Offset);
1409 }
1410
1411 return Idx;
1412}
1413
1414void CodeGenRegBank::computeComposites() {
1415 using RegMap = std::map<const CodeGenRegister *, const CodeGenRegister *>;
1416
1417 // Subreg -> { Reg->Reg }, where the right-hand side is the mapping from
1418 // register to (sub)register associated with the action of the left-hand
1419 // side subregister.
1420 std::map<const CodeGenSubRegIndex *, RegMap> SubRegAction;
1421 for (const CodeGenRegister &R : Registers) {
1422 const CodeGenRegister::SubRegMap &SM = R.getSubRegs();
1423 for (auto [SRI, SubReg] : SM)
1424 SubRegAction[SRI].try_emplace(k: &R, args&: SubReg);
1425 }
1426
1427 // Calculate the composition of two subregisters as compositions of their
1428 // associated actions.
1429 auto compose = [&SubRegAction](const CodeGenSubRegIndex *Sub1,
1430 const CodeGenSubRegIndex *Sub2) {
1431 RegMap C;
1432 const RegMap &Img1 = SubRegAction.at(k: Sub1);
1433 const RegMap &Img2 = SubRegAction.at(k: Sub2);
1434 for (auto [R, SubReg] : Img1) {
1435 auto F = Img2.find(x: SubReg);
1436 if (F != Img2.end())
1437 C.try_emplace(k: R, args: F->second);
1438 }
1439 return C;
1440 };
1441
1442 // Check if the two maps agree on the intersection of their domains.
1443 auto agree = [](const RegMap &Map1, const RegMap &Map2) {
1444 // Technically speaking, an empty map agrees with any other map, but
1445 // this could flag false positives. We're interested in non-vacuous
1446 // agreements.
1447 if (Map1.empty() || Map2.empty())
1448 return false;
1449 for (auto [K, V] : Map1) {
1450 auto F = Map2.find(x: K);
1451 if (F == Map2.end() || V != F->second)
1452 return false;
1453 }
1454 return true;
1455 };
1456
1457 using CompositePair =
1458 std::pair<const CodeGenSubRegIndex *, const CodeGenSubRegIndex *>;
1459 SmallSet<CompositePair, 4> UserDefined;
1460 for (const CodeGenSubRegIndex &Idx : SubRegIndices)
1461 for (auto P : Idx.getComposites())
1462 UserDefined.insert(V: {&Idx, P.first});
1463
1464 // Keep track of TopoSigs visited. We only need to visit each TopoSig once,
1465 // and many registers will share TopoSigs on regular architectures.
1466 BitVector TopoSigs(getNumTopoSigs());
1467
1468 for (const CodeGenRegister &Reg1 : Registers) {
1469 // Skip identical subreg structures already processed.
1470 if (TopoSigs.test(Idx: Reg1.getTopoSig()))
1471 continue;
1472 TopoSigs.set(Reg1.getTopoSig());
1473
1474 const CodeGenRegister::SubRegMap &SRM1 = Reg1.getSubRegs();
1475 for (auto [Idx1, Reg2] : SRM1) {
1476 // Ignore identity compositions.
1477 if (&Reg1 == Reg2)
1478 continue;
1479 const CodeGenRegister::SubRegMap &SRM2 = Reg2->getSubRegs();
1480 // Try composing Idx1 with another SubRegIndex.
1481 for (auto I2 : SRM2) {
1482 CodeGenSubRegIndex *Idx2 = I2.first;
1483 CodeGenRegister *Reg3 = I2.second;
1484 // Ignore identity compositions.
1485 if (Reg2 == Reg3)
1486 continue;
1487 // OK Reg1:IdxPair == Reg3. Find the index with Reg:Idx == Reg3.
1488 CodeGenSubRegIndex *Idx3 = Reg1.getSubRegIndex(Reg: Reg3);
1489 assert(Idx3 && "Sub-register doesn't have an index");
1490
1491 // Conflicting composition? Emit a warning but allow it.
1492 if (CodeGenSubRegIndex *Prev =
1493 Idx1->addComposite(A: Idx2, B: Idx3, CGH: getHwModes())) {
1494 // If the composition was not user-defined, always emit a warning.
1495 if (!UserDefined.contains(V: {Idx1, Idx2}) ||
1496 agree(compose(Idx1, Idx2), SubRegAction.at(k: Idx3)))
1497 PrintWarning(Msg: Twine("SubRegIndex ") + Idx1->getQualifiedName() +
1498 " and " + Idx2->getQualifiedName() +
1499 " compose ambiguously as " + Prev->getQualifiedName() +
1500 " or " + Idx3->getQualifiedName());
1501 }
1502 }
1503 }
1504 }
1505}
1506
1507// Compute lane masks. This is similar to register units, but at the
1508// sub-register index level. Each bit in the lane mask is like a register unit
1509// class, and two lane masks will have a bit in common if two sub-register
1510// indices overlap in some register.
1511//
1512// Conservatively share a lane mask bit if two sub-register indices overlap in
1513// some registers, but not in others. That shouldn't happen a lot.
1514void CodeGenRegBank::computeSubRegLaneMasks() {
1515 // First assign individual bits to all the leaf indices.
1516 unsigned Bit = 0;
1517 // Determine mask of lanes that cover their registers.
1518 CoveringLanes = LaneBitmask::getAll();
1519 for (CodeGenSubRegIndex &Idx : SubRegIndices) {
1520 if (Idx.getComposites().empty()) {
1521 if (Bit >= LaneBitmask::BitWidth) {
1522 PrintFatalError(
1523 Msg: Twine("Ran out of lanemask bits to represent subregister ") +
1524 Idx.getName());
1525 }
1526 Idx.LaneMask = LaneBitmask::getLane(Lane: Bit);
1527 ++Bit;
1528 } else {
1529 Idx.LaneMask = LaneBitmask::getNone();
1530 }
1531 }
1532
1533 // Compute transformation sequences for composeSubRegIndexLaneMask. The idea
1534 // here is that for each possible target subregister we look at the leafs
1535 // in the subregister graph that compose for this target and create
1536 // transformation sequences for the lanemasks. Each step in the sequence
1537 // consists of a bitmask and a bitrotate operation. As the rotation amounts
1538 // are usually the same for many subregisters we can easily combine the steps
1539 // by combining the masks.
1540 for (const CodeGenSubRegIndex &Idx : SubRegIndices) {
1541 const CodeGenSubRegIndex::CompMap &Composites = Idx.getComposites();
1542 auto &LaneTransforms = Idx.CompositionLaneMaskTransform;
1543
1544 if (Composites.empty()) {
1545 // Moving from a class with no subregisters we just had a single lane:
1546 // The subregister must be a leaf subregister and only occupies 1 bit.
1547 // Move the bit from the class without subregisters into that position.
1548 unsigned DstBit = Idx.LaneMask.getHighestLane();
1549 assert(Idx.LaneMask == LaneBitmask::getLane(DstBit) &&
1550 "Must be a leaf subregister");
1551 MaskRolPair MaskRol = {.Mask: LaneBitmask::getLane(Lane: 0), .RotateLeft: (uint8_t)DstBit};
1552 LaneTransforms.push_back(Elt: MaskRol);
1553 } else {
1554 // Go through all leaf subregisters and find the ones that compose with
1555 // Idx. These make out all possible valid bits in the lane mask we want to
1556 // transform. Looking only at the leafs ensure that only a single bit in
1557 // the mask is set.
1558 unsigned NextBit = 0;
1559 for (CodeGenSubRegIndex &Idx2 : SubRegIndices) {
1560 // Skip non-leaf subregisters.
1561 if (!Idx2.getComposites().empty())
1562 continue;
1563 // Replicate the behaviour from the lane mask generation loop above.
1564 unsigned SrcBit = NextBit;
1565 LaneBitmask SrcMask = LaneBitmask::getLane(Lane: SrcBit);
1566 if (NextBit < LaneBitmask::BitWidth - 1)
1567 ++NextBit;
1568 assert(Idx2.LaneMask == SrcMask);
1569
1570 // Get the composed subregister if there is any.
1571 auto C = Composites.find(x: &Idx2);
1572 if (C == Composites.end())
1573 continue;
1574 const CodeGenSubRegIndex *Composite = C->second;
1575 // The Composed subreg should be a leaf subreg too
1576 assert(Composite->getComposites().empty());
1577
1578 // Create Mask+Rotate operation and merge with existing ops if possible.
1579 unsigned DstBit = Composite->LaneMask.getHighestLane();
1580 int Shift = DstBit - SrcBit;
1581 uint8_t RotateLeft =
1582 Shift >= 0 ? (uint8_t)Shift : LaneBitmask::BitWidth + Shift;
1583 for (MaskRolPair &I : LaneTransforms) {
1584 if (I.RotateLeft == RotateLeft) {
1585 I.Mask |= SrcMask;
1586 SrcMask = LaneBitmask::getNone();
1587 }
1588 }
1589 if (SrcMask.any()) {
1590 MaskRolPair MaskRol = {.Mask: SrcMask, .RotateLeft: RotateLeft};
1591 LaneTransforms.push_back(Elt: MaskRol);
1592 }
1593 }
1594 }
1595
1596 // Optimize if the transformation consists of one step only: Set mask to
1597 // 0xffffffff (including some irrelevant invalid bits) so that it should
1598 // merge with more entries later while compressing the table.
1599 if (LaneTransforms.size() == 1)
1600 LaneTransforms[0].Mask = LaneBitmask::getAll();
1601
1602 // Further compression optimization: For invalid compositions resulting
1603 // in a sequence with 0 entries we can just pick any other. Choose
1604 // Mask 0xffffffff with Rotation 0.
1605 if (LaneTransforms.size() == 0) {
1606 MaskRolPair P = {.Mask: LaneBitmask::getAll(), .RotateLeft: 0};
1607 LaneTransforms.push_back(Elt: P);
1608 }
1609 }
1610
1611 // FIXME: What if ad-hoc aliasing introduces overlaps that aren't represented
1612 // by the sub-register graph? This doesn't occur in any known targets.
1613
1614 // Inherit lanes from composites.
1615 for (const CodeGenSubRegIndex &Idx : SubRegIndices) {
1616 LaneBitmask Mask = Idx.computeLaneMask();
1617 // If some super-registers without CoveredBySubRegs use this index, we can
1618 // no longer assume that the lanes are covering their registers.
1619 if (!Idx.AllSuperRegsCovered)
1620 CoveringLanes &= ~Mask;
1621 }
1622
1623 // Compute lane mask combinations for register classes.
1624 for (auto &RegClass : RegClasses) {
1625 LaneBitmask LaneMask;
1626 for (const CodeGenSubRegIndex &SubRegIndex : SubRegIndices) {
1627 if (RegClass.getSubClassWithSubReg(SubIdx: &SubRegIndex) == nullptr)
1628 continue;
1629 LaneMask |= SubRegIndex.LaneMask;
1630 }
1631
1632 // For classes without any subregisters set LaneMask to 1 instead of 0.
1633 // This makes it easier for client code to handle classes uniformly.
1634 if (LaneMask.none())
1635 LaneMask = LaneBitmask::getLane(Lane: 0);
1636
1637 RegClass.LaneMask = LaneMask;
1638 }
1639}
1640
1641namespace {
1642
1643// A directed graph on sub-register indices with a virtual source node that
1644// has an arc to all other nodes, and an arc from A to B if sub-register index
1645// B can be obtained by composing A with some other sub-register index.
1646struct SubRegIndexCompositionGraph {
1647 std::deque<CodeGenSubRegIndex> &SubRegIndices;
1648 CodeGenSubRegIndex::CompMap EntryNode;
1649
1650 SubRegIndexCompositionGraph(std::deque<CodeGenSubRegIndex> &SubRegIndices)
1651 : SubRegIndices(SubRegIndices) {
1652 for (CodeGenSubRegIndex &Idx : SubRegIndices) {
1653 EntryNode.try_emplace(k: &Idx, args: &Idx);
1654 }
1655 }
1656};
1657
1658} // namespace
1659
1660template <> struct llvm::GraphTraits<SubRegIndexCompositionGraph> {
1661 using NodeRef =
1662 PointerUnion<CodeGenSubRegIndex *, const CodeGenSubRegIndex::CompMap *>;
1663
1664 // Using a reverse iterator causes sub-register indices to appear in their
1665 // more natural order in RPOT.
1666 using CompMapIt = CodeGenSubRegIndex::CompMap::const_reverse_iterator;
1667 struct ChildIteratorType
1668 : public iterator_adaptor_base<
1669 ChildIteratorType, CompMapIt,
1670 std::iterator_traits<CompMapIt>::iterator_category, NodeRef> {
1671 ChildIteratorType(CompMapIt I)
1672 : ChildIteratorType::iterator_adaptor_base(I) {}
1673
1674 NodeRef operator*() const { return wrapped()->second; }
1675 };
1676
1677 static NodeRef getEntryNode(const SubRegIndexCompositionGraph &G) {
1678 return &G.EntryNode;
1679 }
1680
1681 static const CodeGenSubRegIndex::CompMap *children(NodeRef N) {
1682 if (auto *Idx = dyn_cast<CodeGenSubRegIndex *>(Val&: N))
1683 return &Idx->getComposites();
1684 return cast<const CodeGenSubRegIndex::CompMap *>(Val&: N);
1685 }
1686
1687 static ChildIteratorType child_begin(NodeRef N) {
1688 return ChildIteratorType(children(N)->rbegin());
1689 }
1690 static ChildIteratorType child_end(NodeRef N) {
1691 return ChildIteratorType(children(N)->rend());
1692 }
1693
1694 static auto nodes_begin(SubRegIndexCompositionGraph *G) {
1695 return G->SubRegIndices.begin();
1696 }
1697 static auto nodes_end(SubRegIndexCompositionGraph *G) {
1698 return G->SubRegIndices.end();
1699 }
1700
1701 static unsigned size(SubRegIndexCompositionGraph *G) {
1702 return G->SubRegIndices.size();
1703 }
1704};
1705
1706void CodeGenRegBank::computeSubRegIndicesRPOT() {
1707 SubRegIndexCompositionGraph G(SubRegIndices);
1708 ReversePostOrderTraversal<SubRegIndexCompositionGraph> RPOT(G);
1709 for (const auto N : RPOT) {
1710 if (auto *Idx = dyn_cast<CodeGenSubRegIndex *>(Val: N))
1711 SubRegIndicesRPOT.push_back(x: Idx);
1712 }
1713}
1714
1715namespace {
1716
1717// UberRegSet is a helper class for computeRegUnitWeights. Each UberRegSet is
1718// the transitive closure of the union of overlapping register
1719// classes. Together, the UberRegSets form a partition of the registers. If we
1720// consider overlapping register classes to be connected, then each UberRegSet
1721// is a set of connected components.
1722//
1723// An UberRegSet will likely be a horizontal slice of register names of
1724// the same width. Nontrivial subregisters should then be in a separate
1725// UberRegSet. But this property isn't required for valid computation of
1726// register unit weights.
1727//
1728// A Weight field caches the max per-register unit weight in each UberRegSet.
1729//
1730// A set of SingularDeterminants flags single units of some register in this set
1731// for which the unit weight equals the set weight. These units should not have
1732// their weight increased.
1733struct UberRegSet {
1734 CodeGenRegister::Vec Regs;
1735 unsigned Weight = 0;
1736 CodeGenRegister::RegUnitList SingularDeterminants;
1737
1738 UberRegSet() = default;
1739};
1740
1741} // end anonymous namespace
1742
1743// Partition registers into UberRegSets, where each set is the transitive
1744// closure of the union of overlapping register classes.
1745//
1746// UberRegSets[0] is a special non-allocatable set.
1747static void computeUberSets(std::vector<UberRegSet> &UberSets,
1748 std::vector<UberRegSet *> &RegSets,
1749 CodeGenRegBank &RegBank) {
1750 const auto &Registers = RegBank.getRegisters();
1751
1752 // The Register EnumValue is one greater than its index into Registers.
1753 assert(Registers.size() == Registers.back().EnumValue &&
1754 "register enum value mismatch");
1755
1756 // For simplicitly make the SetID the same as EnumValue.
1757 IntEqClasses UberSetIDs(Registers.size() + 1);
1758 BitVector AllocatableRegs(Registers.size() + 1);
1759 for (CodeGenRegisterClass &RegClass : RegBank.getRegClasses()) {
1760 if (!RegClass.Allocatable)
1761 continue;
1762
1763 // Ignore artificial registers. They may be members of register
1764 // classes that together include registers and their subregisters,
1765 // in which case it is impossible to normalize the weights of
1766 // their register units.
1767 CodeGenRegister::Vec Regs;
1768 for (const CodeGenRegister *Reg : RegClass.getMembers()) {
1769 if (!Reg->Artificial)
1770 Regs.push_back(x: Reg);
1771 }
1772
1773 if (Regs.empty())
1774 continue;
1775
1776 unsigned USetID = UberSetIDs.findLeader(a: (*Regs.begin())->EnumValue);
1777 assert(USetID && "register number 0 is invalid");
1778
1779 AllocatableRegs.set((*Regs.begin())->EnumValue);
1780 for (const CodeGenRegister *CGR : llvm::drop_begin(RangeOrContainer&: Regs)) {
1781 AllocatableRegs.set(CGR->EnumValue);
1782 UberSetIDs.join(a: USetID, b: CGR->EnumValue);
1783 }
1784 }
1785 // Combine non-allocatable regs.
1786 for (const CodeGenRegister &Reg : Registers) {
1787 unsigned RegNum = Reg.EnumValue;
1788 if (AllocatableRegs.test(Idx: RegNum))
1789 continue;
1790
1791 UberSetIDs.join(a: 0, b: RegNum);
1792 }
1793 UberSetIDs.compress();
1794
1795 // Make the first UberSet a special unallocatable set.
1796 unsigned ZeroID = UberSetIDs[0];
1797
1798 // Insert Registers into the UberSets formed by union-find.
1799 // Do not resize after this.
1800 UberSets.resize(new_size: UberSetIDs.getNumClasses());
1801 for (auto [Idx, Reg] : enumerate(First: Registers)) {
1802 unsigned USetID = UberSetIDs[Reg.EnumValue];
1803 if (!USetID)
1804 USetID = ZeroID;
1805 else if (USetID == ZeroID)
1806 USetID = 0;
1807
1808 UberRegSet *USet = &UberSets[USetID];
1809 USet->Regs.push_back(x: &Reg);
1810 RegSets[Idx] = USet;
1811 }
1812}
1813
1814// Recompute each UberSet weight after changing unit weights.
1815static void computeUberWeights(MutableArrayRef<UberRegSet> UberSets,
1816 CodeGenRegBank &RegBank) {
1817 // Skip the first unallocatable set.
1818 for (UberRegSet &S : UberSets.drop_front()) {
1819 // Initialize all unit weights in this set, and remember the max units/reg.
1820 unsigned MaxWeight = 0;
1821 for (const CodeGenRegister *R : S.Regs) {
1822 unsigned Weight = 0;
1823 for (unsigned U : R->getRegUnits()) {
1824 if (!RegBank.getRegUnit(RUID: U).Artificial) {
1825 unsigned UWeight = RegBank.getRegUnit(RUID: U).Weight;
1826 if (!UWeight) {
1827 UWeight = 1;
1828 RegBank.increaseRegUnitWeight(RUID: U, Inc: UWeight);
1829 }
1830 Weight += UWeight;
1831 }
1832 }
1833 MaxWeight = std::max(a: MaxWeight, b: Weight);
1834 }
1835 if (S.Weight != MaxWeight) {
1836 LLVM_DEBUG({
1837 dbgs() << "UberSet " << &S - UberSets.begin() << " Weight "
1838 << MaxWeight;
1839 for (const CodeGenRegister *R : S.Regs)
1840 dbgs() << " " << R->getName();
1841 dbgs() << '\n';
1842 });
1843 // Update the set weight.
1844 S.Weight = MaxWeight;
1845 }
1846
1847 // Find singular determinants.
1848 for (const CodeGenRegister *R : S.Regs)
1849 if (R->getRegUnits().count() == 1 && R->getWeight(RegBank) == S.Weight)
1850 S.SingularDeterminants |= R->getRegUnits();
1851 }
1852}
1853
1854// normalizeWeight is a computeRegUnitWeights helper that adjusts the weight of
1855// a register and its subregisters so that they have the same weight as their
1856// UberSet. Self-recursion processes the subregister tree in postorder so
1857// subregisters are normalized first.
1858//
1859// Side effects:
1860// - creates new adopted register units
1861// - causes superregisters to inherit adopted units
1862// - increases the weight of "singular" units
1863// - induces recomputation of UberWeights.
1864static bool normalizeWeight(CodeGenRegister *Reg,
1865 std::vector<UberRegSet> &UberSets,
1866 std::vector<UberRegSet *> &RegSets,
1867 BitVector &NormalRegs,
1868 CodeGenRegister::RegUnitList &NormalUnits,
1869 CodeGenRegBank &RegBank) {
1870 NormalRegs.resize(N: std::max(a: Reg->EnumValue + 1, b: NormalRegs.size()));
1871 if (NormalRegs.test(Idx: Reg->EnumValue))
1872 return false;
1873 NormalRegs.set(Reg->EnumValue);
1874
1875 bool Changed = false;
1876 const CodeGenRegister::SubRegMap &SRM = Reg->getSubRegs();
1877 for (auto SRI : SRM) {
1878 if (SRI.second == Reg)
1879 continue; // self-cycles happen
1880
1881 Changed |= normalizeWeight(Reg: SRI.second, UberSets, RegSets, NormalRegs,
1882 NormalUnits, RegBank);
1883 }
1884 // Postorder register normalization.
1885
1886 // Inherit register units newly adopted by subregisters.
1887 if (Reg->inheritRegUnits(RegBank))
1888 computeUberWeights(UberSets, RegBank);
1889
1890 // Check if this register is too skinny for its UberRegSet.
1891 UberRegSet *UberSet = RegSets[RegBank.getRegIndex(Reg)];
1892
1893 unsigned RegWeight = Reg->getWeight(RegBank);
1894 if (UberSet->Weight > RegWeight) {
1895 // A register unit's weight can be adjusted only if it is the singular unit
1896 // for this register, has not been used to normalize a subregister's set,
1897 // and has not already been used to singularly determine this UberRegSet.
1898 unsigned AdjustUnit = *Reg->getRegUnits().begin();
1899 if (Reg->getRegUnits().count() != 1 || NormalUnits.test(Idx: AdjustUnit) ||
1900 UberSet->SingularDeterminants.test(Idx: AdjustUnit)) {
1901 // We don't have an adjustable unit, so adopt a new one.
1902 AdjustUnit = RegBank.newRegUnit(Weight: UberSet->Weight - RegWeight);
1903 Reg->adoptRegUnit(RUID: AdjustUnit);
1904 // Adopting a unit does not immediately require recomputing set weights.
1905 } else {
1906 // Adjust the existing single unit.
1907 if (!RegBank.getRegUnit(RUID: AdjustUnit).Artificial)
1908 RegBank.increaseRegUnitWeight(RUID: AdjustUnit, Inc: UberSet->Weight - RegWeight);
1909 // The unit may be shared among sets and registers within this set.
1910 computeUberWeights(UberSets, RegBank);
1911 }
1912 Changed = true;
1913 }
1914
1915 // Mark these units normalized so superregisters can't change their weights.
1916 NormalUnits |= Reg->getRegUnits();
1917
1918 return Changed;
1919}
1920
1921// Compute a weight for each register unit created during getSubRegs.
1922//
1923// The goal is that two registers in the same class will have the same weight,
1924// where each register's weight is defined as sum of its units' weights.
1925void CodeGenRegBank::computeRegUnitWeights() {
1926 std::vector<UberRegSet> UberSets;
1927 std::vector<UberRegSet *> RegSets(Registers.size());
1928 computeUberSets(UberSets, RegSets, RegBank&: *this);
1929 // UberSets and RegSets are now immutable.
1930
1931 computeUberWeights(UberSets, RegBank&: *this);
1932
1933 // Iterate over each Register, normalizing the unit weights until reaching
1934 // a fix point.
1935 unsigned NumIters = 0;
1936 for (bool Changed = true; Changed; ++NumIters) {
1937 assert(NumIters <= NumNativeRegUnits && "Runaway register unit weights");
1938 (void)NumIters;
1939 Changed = false;
1940 for (CodeGenRegister &Reg : Registers) {
1941 CodeGenRegister::RegUnitList NormalUnits;
1942 BitVector NormalRegs;
1943 Changed |= normalizeWeight(Reg: &Reg, UberSets, RegSets, NormalRegs,
1944 NormalUnits, RegBank&: *this);
1945 }
1946 }
1947}
1948
1949// isContiguous is a enforceRegUnitIntervals helper that returns true if all
1950// units in Units form a contiguous interval.
1951static bool isContiguous(const CodeGenRegister::RegUnitList &Units) {
1952 unsigned LastUnit = Units.find_first();
1953 for (auto ThisUnit : llvm::make_range(x: ++Units.begin(), y: Units.end())) {
1954 if (ThisUnit != LastUnit + 1)
1955 return false;
1956 LastUnit = ThisUnit;
1957 }
1958 return true;
1959}
1960
1961// Enforce that all registers are intervals of regunits if the target
1962// requests this property. This will renumber regunits to ensure the
1963// interval property holds, or error out if it cannot be satisfied.
1964void CodeGenRegBank::enforceRegUnitIntervals() {
1965 if (!RegistersAreIntervals)
1966 return;
1967
1968 LLVM_DEBUG(dbgs() << "Enforcing regunit intervals for target\n");
1969 std::vector<unsigned> RegUnitRenumbering(RegUnits.size(), ~0u);
1970
1971 // RegUnits that have been renumbered from X -> Y. Y is what is marked so that
1972 // it doesn't create a chain of swaps.
1973 SparseBitVector<> DontRenumberUnits;
1974
1975 auto GetRenumberedUnit = [&](unsigned RegUnit) -> unsigned {
1976 if (unsigned RenumberedUnit = RegUnitRenumbering[RegUnit];
1977 RenumberedUnit != ~0u)
1978 return RenumberedUnit;
1979 return RegUnit;
1980 };
1981
1982 // Process registers in definition order
1983 for (CodeGenRegister &Reg : Registers) {
1984 LLVM_DEBUG(dbgs() << "Processing register " << Reg.getName() << "\n");
1985 const auto &Units = Reg.getNativeRegUnits();
1986 if (Units.empty())
1987 continue;
1988 SparseBitVector<> RenumberedUnits;
1989 // First renumber all the units for this register according to previous
1990 // renumbering.
1991 LLVM_DEBUG(dbgs() << " Original (Renumbered) units:");
1992 for (unsigned U : Units) {
1993 LLVM_DEBUG(dbgs() << " " << U << "(" << GetRenumberedUnit(U) << "), ");
1994 RenumberedUnits.set(GetRenumberedUnit(U));
1995 }
1996 LLVM_DEBUG(dbgs() << "\n");
1997
1998 unsigned LastUnit = RenumberedUnits.find_first();
1999 for (auto ThisUnit :
2000 llvm::make_range(x: ++RenumberedUnits.begin(), y: RenumberedUnits.end())) {
2001 if (ThisUnit != LastUnit + 1) {
2002 if (DontRenumberUnits.test(Idx: LastUnit + 1)) {
2003 PrintFatalError(
2004 Msg: "cannot enforce regunit intervals for register " + Reg.getName() +
2005 ": unit " + Twine(LastUnit + 1) +
2006 " (root: " + RegUnits[LastUnit + 1].Roots[0]->getName() +
2007 ") has already been renumbered and cannot be swapped");
2008 }
2009 LLVM_DEBUG(dbgs() << " Renumbering unit " << ThisUnit << " to "
2010 << (LastUnit + 1) << "\n");
2011 RegUnitRenumbering[LastUnit + 1] = ThisUnit;
2012 RegUnitRenumbering[ThisUnit] = LastUnit + 1;
2013 DontRenumberUnits.set(LastUnit + 1);
2014 ThisUnit = LastUnit + 1;
2015 }
2016 LastUnit = ThisUnit;
2017 }
2018 }
2019
2020 // Apply the renumbering to all registers
2021 for (CodeGenRegister &Reg : Registers) {
2022 CodeGenRegister::RegUnitList NewRegUnits;
2023 for (unsigned OldUnit : Reg.getRegUnits())
2024 NewRegUnits.set(GetRenumberedUnit(OldUnit));
2025 Reg.setNewRegUnits(NewRegUnits);
2026
2027 CodeGenRegister::RegUnitList NewNativeUnits;
2028 for (unsigned OldUnit : Reg.getNativeRegUnits())
2029 NewNativeUnits.set(GetRenumberedUnit(OldUnit));
2030 if (!isContiguous(Units: NewNativeUnits)) {
2031 PrintFatalError(Msg: "cannot enforce regunit intervals, final "
2032 "renumbering did not produce contiguous units "
2033 "for register " +
2034 Reg.getName() + "\n");
2035 }
2036 Reg.NativeRegUnits = NewNativeUnits;
2037 }
2038}
2039
2040// Find a set in UniqueSets with the same elements as Set.
2041// Return an iterator into UniqueSets.
2042static std::vector<RegUnitSet>::const_iterator
2043findRegUnitSet(const std::vector<RegUnitSet> &UniqueSets,
2044 const RegUnitSet &Set) {
2045 return llvm::find_if(
2046 Range: UniqueSets, P: [&Set](const RegUnitSet &I) { return I.Units == Set.Units; });
2047}
2048
2049// Return true if the RUSubSet is a subset of RUSuperSet.
2050static bool isRegUnitSubSet(const std::vector<unsigned> &RUSubSet,
2051 const std::vector<unsigned> &RUSuperSet) {
2052 return llvm::includes(Range1: RUSuperSet, Range2: RUSubSet);
2053}
2054
2055/// Iteratively prune unit sets. Prune subsets that are close to the superset,
2056/// but with one or two registers removed. We occasionally have registers like
2057/// APSR and PC thrown in with the general registers. We also see many
2058/// special-purpose register subsets, such as tail-call and Thumb
2059/// encodings. Generating all possible overlapping sets is combinatorial and
2060/// overkill for modeling pressure. Ideally we could fix this statically in
2061/// tablegen by (1) having the target define register classes that only include
2062/// the allocatable registers and marking other classes as non-allocatable and
2063/// (2) having a way to mark special purpose classes as "don't-care" classes for
2064/// the purpose of pressure. However, we make an attempt to handle targets that
2065/// are not nicely defined by merging nearly identical register unit sets
2066/// statically. This generates smaller tables. Then, dynamically, we adjust the
2067/// set limit by filtering the reserved registers.
2068///
2069/// Merge sets only if the units have the same weight. For example, on ARM,
2070/// Q-tuples with ssub index 0 include all S regs but also include D16+. We
2071/// should not expand the S set to include D regs.
2072void CodeGenRegBank::pruneUnitSets() {
2073 assert(RegClassUnitSets.empty() && "this invalidates RegClassUnitSets");
2074
2075 // Form an equivalence class of UnitSets with no significant difference.
2076 std::vector<unsigned> SuperSetIDs;
2077 unsigned EndIdx = RegUnitSets.size();
2078 for (auto [SubIdx, SubSet] : enumerate(First&: RegUnitSets)) {
2079 unsigned SuperIdx = 0;
2080 for (; SuperIdx != EndIdx; ++SuperIdx) {
2081 if (SuperIdx == SubIdx)
2082 continue;
2083
2084 unsigned UnitWeight = RegUnits[SubSet.Units[0]].Weight;
2085 const RegUnitSet &SuperSet = RegUnitSets[SuperIdx];
2086 if (isRegUnitSubSet(RUSubSet: SubSet.Units, RUSuperSet: SuperSet.Units) &&
2087 (SubSet.Units.size() + 3 > SuperSet.Units.size()) &&
2088 UnitWeight == RegUnits[SuperSet.Units[0]].Weight &&
2089 UnitWeight == RegUnits[SuperSet.Units.back()].Weight) {
2090 LLVM_DEBUG({
2091 dbgs() << "UnitSet " << SubIdx << " subsumed by " << SuperIdx << '\n';
2092 });
2093 // We can pick any of the set names for the merged set. Go for the
2094 // shortest one to avoid picking the name of one of the classes that are
2095 // artificially created by tablegen. So "FPR128_lo" instead of
2096 // "QQQQ_with_qsub3_in_FPR128_lo".
2097 if (RegUnitSets[SubIdx].Name.size() < RegUnitSets[SuperIdx].Name.size())
2098 RegUnitSets[SuperIdx].Name = RegUnitSets[SubIdx].Name;
2099 break;
2100 }
2101 }
2102 if (SuperIdx == EndIdx)
2103 SuperSetIDs.push_back(x: SubIdx);
2104 }
2105 // Populate PrunedUnitSets with each equivalence class's superset.
2106 std::vector<RegUnitSet> PrunedUnitSets;
2107 PrunedUnitSets.reserve(n: SuperSetIDs.size());
2108 for (unsigned SuperIdx : SuperSetIDs) {
2109 PrunedUnitSets.emplace_back(args&: RegUnitSets[SuperIdx].Name);
2110 PrunedUnitSets.back().Units = std::move(RegUnitSets[SuperIdx].Units);
2111 }
2112 RegUnitSets = std::move(PrunedUnitSets);
2113}
2114
2115// Create a RegUnitSet for each RegClass that contains all units in the class
2116// including adopted units that are necessary to model register pressure. Then
2117// iteratively compute RegUnitSets such that the union of any two overlapping
2118// RegUnitSets is represented.
2119//
2120// RegisterInfoEmitter will map each RegClass to its RegUnitClass and any
2121// RegUnitSet that is a superset of that RegUnitClass.
2122void CodeGenRegBank::computeRegUnitSets() {
2123 assert(RegUnitSets.empty() && "dirty RegUnitSets");
2124
2125#ifndef NDEBUG
2126 // Helper to print register unit sets.
2127 auto PrintRegUnitSets = [this]() {
2128 for (auto [USIdx, US] : enumerate(RegUnitSets)) {
2129 dbgs() << "UnitSet " << USIdx << " " << US.Name << ":";
2130 printRegUnitNames(US.Units);
2131 }
2132 };
2133#endif // NDEBUG
2134
2135 // Compute a unique RegUnitSet for each RegClass.
2136 auto &RegClasses = getRegClasses();
2137 for (CodeGenRegisterClass &RC : RegClasses) {
2138 if (!RC.Allocatable || RC.Artificial || !RC.GeneratePressureSet)
2139 continue;
2140
2141 // Compute a sorted list of units in this class.
2142 RegUnitSet RUSet(RC.getName());
2143 RC.buildRegUnitSet(RegBank: *this, RegUnits&: RUSet.Units);
2144
2145 // Find an existing RegUnitSet.
2146 if (findRegUnitSet(UniqueSets: RegUnitSets, Set: RUSet) == RegUnitSets.end())
2147 RegUnitSets.push_back(x: std::move(RUSet));
2148 }
2149
2150 if (RegUnitSets.empty())
2151 PrintFatalError(Msg: "RegUnitSets cannot be empty!");
2152
2153 LLVM_DEBUG({
2154 dbgs() << "\nBefore pruning:\n";
2155 PrintRegUnitSets();
2156 });
2157
2158 // Iteratively prune unit sets.
2159 pruneUnitSets();
2160
2161 LLVM_DEBUG({
2162 dbgs() << "\nBefore union:\n";
2163 PrintRegUnitSets();
2164 dbgs() << "\nUnion sets:\n";
2165 });
2166
2167 // Iterate over all unit sets, including new ones added by this loop.
2168 // FIXME: Since `EndIdx` is computed just once during loop initialization,
2169 // does this really iterate over new unit sets added by this loop?
2170 unsigned NumRegUnitSubSets = RegUnitSets.size();
2171 for (unsigned Idx = 0, EndIdx = RegUnitSets.size(); Idx != EndIdx; ++Idx) {
2172 // In theory, this is combinatorial. In practice, it needs to be bounded
2173 // by a small number of sets for regpressure to be efficient.
2174 // If the assert is hit, we need to implement pruning.
2175 assert(Idx < (2 * NumRegUnitSubSets) && "runaway unit set inference");
2176
2177 // Compare new sets with all original classes.
2178 for (unsigned SearchIdx = (Idx >= NumRegUnitSubSets) ? 0 : Idx + 1;
2179 SearchIdx != EndIdx; ++SearchIdx) {
2180 std::vector<unsigned> Intersection;
2181 std::set_intersection(
2182 first1: RegUnitSets[Idx].Units.begin(), last1: RegUnitSets[Idx].Units.end(),
2183 first2: RegUnitSets[SearchIdx].Units.begin(),
2184 last2: RegUnitSets[SearchIdx].Units.end(), result: std::back_inserter(x&: Intersection));
2185 if (Intersection.empty())
2186 continue;
2187
2188 RegUnitSet RUSet(RegUnitSets[Idx].Name + "_with_" +
2189 RegUnitSets[SearchIdx].Name);
2190 std::set_union(first1: RegUnitSets[Idx].Units.begin(),
2191 last1: RegUnitSets[Idx].Units.end(),
2192 first2: RegUnitSets[SearchIdx].Units.begin(),
2193 last2: RegUnitSets[SearchIdx].Units.end(),
2194 result: std::inserter(x&: RUSet.Units, i: RUSet.Units.begin()));
2195
2196 // Find an existing RegUnitSet, or add the union to the unique sets.
2197 if (findRegUnitSet(UniqueSets: RegUnitSets, Set: RUSet) == RegUnitSets.end()) {
2198 LLVM_DEBUG({
2199 dbgs() << "UnitSet " << RegUnitSets.size() << " " << RUSet.Name
2200 << ":";
2201 printRegUnitNames(RUSet.Units);
2202 });
2203 RegUnitSets.push_back(x: std::move(RUSet));
2204 }
2205 }
2206 }
2207
2208 // Iteratively prune unit sets after inferring supersets.
2209 pruneUnitSets();
2210
2211 LLVM_DEBUG({
2212 dbgs() << '\n';
2213 PrintRegUnitSets();
2214 });
2215
2216 // For each register class, list the UnitSets that are supersets.
2217 RegClassUnitSets.resize(new_size: RegClasses.size());
2218 for (CodeGenRegisterClass &RC : RegClasses) {
2219 if (!RC.Allocatable)
2220 continue;
2221
2222 // Recompute the sorted list of units in this class.
2223 std::vector<unsigned> RCRegUnits;
2224 RC.buildRegUnitSet(RegBank: *this, RegUnits&: RCRegUnits);
2225
2226 // Don't increase pressure for unallocatable regclasses.
2227 if (RCRegUnits.empty())
2228 continue;
2229
2230 LLVM_DEBUG({
2231 dbgs() << "RC " << RC.getName() << " Units:\n";
2232 printRegUnitNames(RCRegUnits);
2233 dbgs() << "UnitSetIDs:";
2234 });
2235
2236 // Find all supersets.
2237 for (const auto &[USIdx, Set] : enumerate(First&: RegUnitSets)) {
2238 if (isRegUnitSubSet(RUSubSet: RCRegUnits, RUSuperSet: Set.Units)) {
2239 LLVM_DEBUG(dbgs() << " " << USIdx);
2240 RegClassUnitSets[RC.EnumValue].push_back(x: USIdx);
2241 }
2242 }
2243 LLVM_DEBUG(dbgs() << '\n');
2244 assert(
2245 (!RegClassUnitSets[RC.EnumValue].empty() || !RC.GeneratePressureSet) &&
2246 "missing unit set for regclass");
2247 }
2248
2249 // For each register unit, ensure that we have the list of UnitSets that
2250 // contain the unit. Normally, this matches an existing list of UnitSets for a
2251 // register class. If not, we create a new entry in RegClassUnitSets as a
2252 // "fake" register class.
2253 for (unsigned UnitIdx = 0, UnitEnd = NumNativeRegUnits; UnitIdx < UnitEnd;
2254 ++UnitIdx) {
2255 std::vector<unsigned> RUSets;
2256 for (auto [Idx, S] : enumerate(First&: RegUnitSets))
2257 if (is_contained(Range&: S.Units, Element: UnitIdx))
2258 RUSets.push_back(x: Idx);
2259
2260 unsigned RCUnitSetsIdx = 0;
2261 for (unsigned e = RegClassUnitSets.size(); RCUnitSetsIdx != e;
2262 ++RCUnitSetsIdx) {
2263 if (RegClassUnitSets[RCUnitSetsIdx] == RUSets) {
2264 break;
2265 }
2266 }
2267 RegUnits[UnitIdx].RegClassUnitSetsIdx = RCUnitSetsIdx;
2268 if (RCUnitSetsIdx == RegClassUnitSets.size()) {
2269 // Create a new list of UnitSets as a "fake" register class.
2270 RegClassUnitSets.push_back(x: std::move(RUSets));
2271 }
2272 }
2273}
2274
2275void CodeGenRegBank::computeRegUnitLaneMasks() {
2276 for (CodeGenRegister &Register : Registers) {
2277 // Create an initial lane mask for all register units.
2278 const auto &RegUnits = Register.getRegUnits();
2279 CodeGenRegister::RegUnitLaneMaskList RegUnitLaneMasks(
2280 RegUnits.count(), LaneBitmask::getAll());
2281 // Iterate through SubRegisters.
2282 using SubRegMap = CodeGenRegister::SubRegMap;
2283 const SubRegMap &SubRegs = Register.getSubRegs();
2284 for (auto [SubRegIndex, SubReg] : SubRegs) {
2285 // Ignore non-leaf subregisters, their lane masks are fully covered by
2286 // the leaf subregisters anyway.
2287 if (!SubReg->getSubRegs().empty())
2288 continue;
2289 LaneBitmask LaneMask = SubRegIndex->LaneMask;
2290 // Distribute LaneMask to Register Units touched.
2291 for (unsigned SUI : SubReg->getRegUnits()) {
2292 bool Found = false;
2293 unsigned u = 0;
2294 for (unsigned RU : RegUnits) {
2295 if (SUI == RU) {
2296 RegUnitLaneMasks[u] &= LaneMask;
2297 assert(!Found);
2298 Found = true;
2299 }
2300 ++u;
2301 }
2302 (void)Found;
2303 assert(Found);
2304 }
2305 }
2306 Register.setRegUnitLaneMasks(RegUnitLaneMasks);
2307 }
2308}
2309
2310void CodeGenRegBank::computeDerivedInfo() {
2311 computeComposites();
2312 computeSubRegLaneMasks();
2313
2314 // Compute a weight for each register unit created during getSubRegs.
2315 // This may create adopted register units (with unit # >= NumNativeRegUnits).
2316 Records.getTimer().startTimer(Name: "Compute reg unit weights");
2317 computeRegUnitWeights();
2318 Records.getTimer().stopTimer();
2319
2320 // Enforce regunit intervals if requested by the target.
2321 Records.getTimer().startTimer(Name: "Enforce regunit intervals");
2322 enforceRegUnitIntervals();
2323 Records.getTimer().stopTimer();
2324
2325 // Compute a unique set of RegUnitSets. One for each RegClass and inferred
2326 // supersets for the union of overlapping sets.
2327 computeRegUnitSets();
2328
2329 computeRegUnitLaneMasks();
2330
2331 // Compute register class HasDisjunctSubRegs/CoveredBySubRegs flag.
2332 for (CodeGenRegisterClass &RC : RegClasses) {
2333 RC.HasDisjunctSubRegs = false;
2334 RC.CoveredBySubRegs = true;
2335 for (const CodeGenRegister *Reg : RC.getMembers()) {
2336 RC.HasDisjunctSubRegs |= Reg->HasDisjunctSubRegs;
2337 RC.CoveredBySubRegs &= Reg->CoveredBySubRegs;
2338 }
2339 }
2340
2341 // Get the weight of each set.
2342 for (auto [Idx, US] : enumerate(First&: RegUnitSets))
2343 RegUnitSets[Idx].Weight = getRegUnitSetWeight(Units: US.Units);
2344
2345 // Find the order of each set.
2346 RegUnitSetOrder.reserve(n: RegUnitSets.size());
2347 for (unsigned Idx : seq<unsigned>(Size: RegUnitSets.size()))
2348 RegUnitSetOrder.push_back(x: Idx);
2349
2350 llvm::stable_sort(Range&: RegUnitSetOrder, C: [this](unsigned ID1, unsigned ID2) {
2351 return getRegPressureSet(Idx: ID1).Units.size() <
2352 getRegPressureSet(Idx: ID2).Units.size();
2353 });
2354 for (unsigned Idx = 0, EndIdx = RegUnitSets.size(); Idx != EndIdx; ++Idx)
2355 RegUnitSets[RegUnitSetOrder[Idx]].Order = Idx;
2356}
2357
2358//
2359// Synthesize missing register class intersections.
2360//
2361// Make sure that sub-classes of RC exists such that getCommonSubClass(RC, X)
2362// returns a maximal register class for all X.
2363//
2364void CodeGenRegBank::inferCommonSubClass(CodeGenRegisterClass *RC) {
2365 assert(!RegClasses.empty());
2366 // Stash the iterator to the last element so that this loop doesn't visit
2367 // elements added by the getOrCreateSubClass call within it.
2368 for (auto I = RegClasses.begin(), E = std::prev(x: RegClasses.end());
2369 I != std::next(x: E); ++I) {
2370 CodeGenRegisterClass *RC1 = RC;
2371 CodeGenRegisterClass *RC2 = &*I;
2372 if (RC1 == RC2)
2373 continue;
2374
2375 // Compute the set intersection of RC1 and RC2.
2376 const CodeGenRegister::Vec &Memb1 = RC1->getMembers();
2377 const CodeGenRegister::Vec &Memb2 = RC2->getMembers();
2378 CodeGenRegister::Vec Intersection;
2379 std::set_intersection(first1: Memb1.begin(), last1: Memb1.end(), first2: Memb2.begin(),
2380 last2: Memb2.end(),
2381 result: std::inserter(x&: Intersection, i: Intersection.begin()),
2382 comp: deref<std::less<>>());
2383
2384 // Skip disjoint class pairs.
2385 if (Intersection.empty())
2386 continue;
2387
2388 // Skip casses where the intersection is composed of artificial
2389 // registers.
2390 if (llvm::all_of(Range&: Intersection, P: [](const CodeGenRegister *Reg) {
2391 return Reg->Artificial;
2392 }))
2393 continue;
2394
2395 // If RC1 and RC2 have different spill sizes or alignments, use the
2396 // stricter one for sub-classing. If they are equal, prefer RC1.
2397 if (RC2->RSI.hasStricterSpillThan(I: RC1->RSI))
2398 std::swap(a&: RC1, b&: RC2);
2399
2400 getOrCreateSubClass(RC: RC1, Members: &Intersection,
2401 Name: RC1->getName() + "_and_" + RC2->getName());
2402 }
2403}
2404
2405//
2406// Synthesize missing sub-classes for getSubClassWithSubReg().
2407//
2408// Make sure that the set of registers in RC with a given SubIdx sub-register
2409// form a register class. Update RC->SubClassWithSubReg.
2410//
2411void CodeGenRegBank::inferSubClassWithSubReg(CodeGenRegisterClass *RC) {
2412 // Map SubRegIndex to set of registers in RC supporting that SubRegIndex.
2413 using SubReg2SetMap = std::map<const CodeGenSubRegIndex *,
2414 CodeGenRegister::Vec, deref<std::less<>>>;
2415
2416 // Compute the set of registers supporting each SubRegIndex.
2417 SubReg2SetMap SRSets;
2418 for (const CodeGenRegister *R : RC->getMembers()) {
2419 if (R->Artificial)
2420 continue;
2421 const CodeGenRegister::SubRegMap &SRM = R->getSubRegs();
2422 for (auto [I, _] : SRM)
2423 SRSets[I].push_back(x: R);
2424 }
2425
2426 // Find matching classes for all SRSets entries. Iterate in SubRegIndex
2427 // numerical order to visit synthetic indices last.
2428 for (const CodeGenSubRegIndex &SubIdx : SubRegIndices) {
2429 SubReg2SetMap::const_iterator I = SRSets.find(x: &SubIdx);
2430 // Unsupported SubRegIndex. Skip it.
2431 if (I == SRSets.end())
2432 continue;
2433 // In most cases, all RC registers support the SubRegIndex.
2434 auto IsNotArtificial = [](const CodeGenRegister *R) {
2435 return !R->Artificial;
2436 };
2437 if (I->second.size() ==
2438 (size_t)count_if(Range: RC->getMembers(), P: IsNotArtificial)) {
2439 RC->setSubClassWithSubReg(SubIdx: &SubIdx, SubRC: RC);
2440 continue;
2441 }
2442 if (SubIdx.Artificial)
2443 continue;
2444 // This is a real subset. See if we have a matching class.
2445 CodeGenRegisterClass *SubRC =
2446 getOrCreateSubClass(RC, Members: &I->second,
2447 Name: RC->getName() + "_with_" + I->first->getName())
2448 .first;
2449 RC->setSubClassWithSubReg(SubIdx: &SubIdx, SubRC);
2450 }
2451}
2452
2453//
2454// Synthesize missing sub-classes of RC for getMatchingSuperRegClass().
2455//
2456// Create sub-classes of RC such that getMatchingSuperRegClass(RC, SubIdx, X)
2457// has a maximal result for any SubIdx and any X >= FirstSubRegRC.
2458//
2459
2460void CodeGenRegBank::inferMatchingSuperRegClass(
2461 CodeGenRegisterClass *RC,
2462 std::list<CodeGenRegisterClass>::iterator FirstSubRegRC) {
2463 DenseSet<const CodeGenSubRegIndex *> ImpliedSubRegIndices;
2464 std::vector<const CodeGenRegister *> SubRegs;
2465 BitVector TopoSigs(getNumTopoSigs());
2466
2467 // Iterate subregister indices in topological order to visit larger indices
2468 // first. This allows us to skip the smaller indices in many cases because
2469 // their inferred super-register classes are implied.
2470 for (CodeGenSubRegIndex *SubIdx : SubRegIndicesRPOT) {
2471 // Skip indexes that aren't fully supported by RC's registers. This was
2472 // computed by inferSubClassWithSubReg() above which should have been
2473 // called first.
2474 if (RC->getSubClassWithSubReg(SubIdx) != RC)
2475 continue;
2476
2477 if (ImpliedSubRegIndices.contains(V: SubIdx))
2478 continue;
2479
2480 // Build list of (Sub, Super) pairs for this SubIdx, sorted by Sub. Note
2481 // that the list may contain entries with the same Sub but different Supers.
2482 SubRegs.clear();
2483 TopoSigs.reset();
2484 for (const CodeGenRegister *Super : RC->getMembers()) {
2485 if (Super->Artificial)
2486 continue;
2487 const CodeGenRegister *Sub = Super->getSubRegs().find(x: SubIdx)->second;
2488 assert(Sub && "Missing sub-register");
2489 SubRegs.push_back(x: Sub);
2490 TopoSigs.set(Sub->getTopoSig());
2491 }
2492
2493 // Iterate over sub-register class candidates. Ignore classes created by
2494 // this loop. They will never be useful.
2495 // Store an iterator to the last element (not end) so that this loop doesn't
2496 // visit newly inserted elements.
2497 assert(!RegClasses.empty());
2498 for (auto I = FirstSubRegRC, E = std::prev(x: RegClasses.end());
2499 I != std::next(x: E); ++I) {
2500 CodeGenRegisterClass &SubRC = *I;
2501 if (SubRC.Artificial)
2502 continue;
2503 // Topological shortcut: SubRC members have the wrong shape.
2504 if (!TopoSigs.anyCommon(RHS: SubRC.getRegsWithSuperRegsTopoSigs()))
2505 continue;
2506 // Compute the subset of RC that maps into SubRC.
2507 CodeGenRegister::Vec SubSetVec;
2508 auto IsNotArtificial = [](const CodeGenRegister *R) {
2509 return !R->Artificial;
2510 };
2511 auto NonArtificialMembers =
2512 make_filter_range(Range: RC->getMembers(), Pred: IsNotArtificial);
2513 for (const auto &[Sub, Super] :
2514 zip_equal(t&: SubRegs, u&: NonArtificialMembers)) {
2515 if (SubRC.contains(Reg: Sub))
2516 SubSetVec.push_back(x: Super);
2517 }
2518
2519 if (SubSetVec.empty())
2520 continue;
2521
2522 // RC injects completely into SubRC.
2523 if (SubSetVec.size() ==
2524 (size_t)count_if(Range: RC->getMembers(), P: IsNotArtificial)) {
2525 SubRC.addSuperRegClass(SubIdx, SuperRC: RC);
2526
2527 // We can skip checking subregister indices that can be composed from
2528 // the current SubIdx.
2529 //
2530 // Proof sketch: Let SubRC' be another register class and SubSubIdx
2531 // a subregister index that can be composed from SubIdx.
2532 //
2533 // Calling this function with SubRC in place of RC ensures the existence
2534 // of a subclass X of SubRC with the registers that have subregisters in
2535 // SubRC'.
2536 //
2537 // The set of registers in RC with SubSubIdx in SubRC' is equal to the
2538 // set of registers in RC with SubIdx in X (because every register in
2539 // RC has a corresponding subregister in SubRC), and so checking the
2540 // pair (SubSubIdx, SubRC') is redundant with checking (SubIdx, X).
2541 for (const auto &SubSubIdx : SubIdx->getComposites())
2542 ImpliedSubRegIndices.insert(V: SubSubIdx.second);
2543
2544 continue;
2545 }
2546
2547 // Only a subset of RC maps into SubRC. Make sure it is represented by a
2548 // class.
2549 //
2550 // The name of the inferred register class follows the template
2551 // "<RC>_with_<SubIdx>_in_<SubRC>".
2552 //
2553 // When SubRC is already an inferred class, prefer a name of the form
2554 // "<RC>_with_<CompositeSubIdx>_in_<SubSubRC>" over a chain of the form
2555 // "<RC>_with_<SubIdx>_in_<OtherRc>_with_<SubSubIdx>_in_<SubSubRC>".
2556 CodeGenSubRegIndex *CompositeSubIdx = SubIdx;
2557 CodeGenRegisterClass *CompositeSubRC = &SubRC;
2558 if (CodeGenSubRegIndex *SubSubIdx = SubRC.getInferredFromSubRegIdx()) {
2559 auto It = SubIdx->getComposites().find(x: SubSubIdx);
2560 if (It != SubIdx->getComposites().end()) {
2561 CompositeSubIdx = It->second;
2562 CompositeSubRC = SubRC.getInferredFromRC();
2563 }
2564 }
2565
2566 auto [SubSetRC, Inserted] = getOrCreateSubClass(
2567 RC, Members: &SubSetVec,
2568 Name: RC->getName() + "_with_" + CompositeSubIdx->getName() + "_in_" +
2569 CompositeSubRC->getName());
2570
2571 if (Inserted)
2572 SubSetRC->setInferredFrom(Idx: CompositeSubIdx, RC: CompositeSubRC);
2573 }
2574 }
2575}
2576
2577//
2578// Infer missing register classes.
2579//
2580void CodeGenRegBank::computeInferredRegisterClasses() {
2581 assert(!RegClasses.empty());
2582 // When this function is called, the register classes have not been sorted
2583 // and assigned EnumValues yet. That means getSubClasses(),
2584 // getSuperClasses(), and hasSubClass() functions are defunct.
2585
2586 Records.getTimer().startTimer(Name: "Compute inferred register classes");
2587
2588 // Use one-before-the-end so it doesn't move forward when new elements are
2589 // added.
2590 auto FirstNewRC = std::prev(x: RegClasses.end());
2591
2592 // Visit all register classes, including the ones being added by the loop.
2593 // Watch out for iterator invalidation here.
2594 for (auto I = RegClasses.begin(), E = RegClasses.end(); I != E; ++I) {
2595 CodeGenRegisterClass *RC = &*I;
2596 if (RC->Artificial)
2597 continue;
2598
2599 // Synthesize answers for getSubClassWithSubReg().
2600 inferSubClassWithSubReg(RC);
2601
2602 // Synthesize answers for getCommonSubClass().
2603 inferCommonSubClass(RC);
2604
2605 // Synthesize answers for getMatchingSuperRegClass().
2606 inferMatchingSuperRegClass(RC);
2607
2608 // New register classes are created while this loop is running, and we need
2609 // to visit all of them. In particular, inferMatchingSuperRegClass needs
2610 // to match old super-register classes with sub-register classes created
2611 // after inferMatchingSuperRegClass was called. At this point,
2612 // inferMatchingSuperRegClass has checked SuperRC = [0..rci] with SubRC =
2613 // [0..FirstNewRC). We need to cover SubRC = [FirstNewRC..rci].
2614 if (I == FirstNewRC) {
2615 auto NextNewRC = std::prev(x: RegClasses.end());
2616 for (auto I2 = RegClasses.begin(), E2 = std::next(x: FirstNewRC); I2 != E2;
2617 ++I2)
2618 inferMatchingSuperRegClass(RC: &*I2, FirstSubRegRC: E2);
2619 FirstNewRC = NextNewRC;
2620 }
2621 }
2622
2623 Records.getTimer().startTimer(Name: "Extend super-register classes");
2624
2625 // Compute the transitive closure for super-register classes.
2626 //
2627 // By iterating over sub-register indices in topological order, we only ever
2628 // add super-register classes for sub-register indices that have not already
2629 // been visited. That allows computing the transitive closure in a single
2630 // pass.
2631 for (CodeGenSubRegIndex *SubIdx : SubRegIndicesRPOT) {
2632 for (CodeGenRegisterClass &SubRC : RegClasses)
2633 SubRC.extendSuperRegClasses(SubIdx);
2634 }
2635
2636 Records.getTimer().stopTimer();
2637}
2638
2639/// getRegisterClassForRegister - Find the register class that contains the
2640/// specified physical register. If the register is not in a register class,
2641/// return null. If the register is in multiple classes, and the classes have a
2642/// superset-subset relationship and the same set of types, return the
2643/// superclass. Otherwise return null.
2644const CodeGenRegisterClass *
2645CodeGenRegBank::getRegClassForRegister(const Record *R) {
2646 const CodeGenRegister *Reg = getReg(Def: R);
2647 const CodeGenRegisterClass *FoundRC = nullptr;
2648 for (const CodeGenRegisterClass &RC : getRegClasses()) {
2649 if (!RC.contains(Reg))
2650 continue;
2651
2652 // If this is the first class that contains the register,
2653 // make a note of it and go on to the next class.
2654 if (!FoundRC) {
2655 FoundRC = &RC;
2656 continue;
2657 }
2658
2659 // If a register's classes have different types, return null.
2660 if (RC.getValueTypes() != FoundRC->getValueTypes())
2661 return nullptr;
2662
2663 // Check to see if the previously found class that contains
2664 // the register is a subclass of the current class. If so,
2665 // prefer the superclass.
2666 if (RC.hasSubClass(RC: FoundRC)) {
2667 FoundRC = &RC;
2668 continue;
2669 }
2670
2671 // Check to see if the previously found class that contains
2672 // the register is a superclass of the current class. If so,
2673 // prefer the superclass.
2674 if (FoundRC->hasSubClass(RC: &RC))
2675 continue;
2676
2677 // Multiple classes, and neither is a superclass of the other.
2678 // Return null.
2679 return nullptr;
2680 }
2681 return FoundRC;
2682}
2683
2684bool CodeGenRegBank::regClassContainsReg(const Record *RegClassDef,
2685 const Record *RegDef,
2686 ArrayRef<SMLoc> Loc) {
2687 // Check all four combinations of Register[ByHwMode] X RegClass[ByHwMode],
2688 // starting with the two RegClassByHwMode cases.
2689 unsigned NumModes = CGH.getNumModeIds();
2690 std::optional<RegisterByHwMode> RegByMode;
2691 CodeGenRegister *Reg = nullptr;
2692 if (RegDef->isSubClassOf(Name: "RegisterByHwMode"))
2693 RegByMode = RegisterByHwMode(RegDef, *this);
2694 else
2695 Reg = getReg(Def: RegDef);
2696 if (RegClassDef->isSubClassOf(Name: "RegClassByHwMode")) {
2697 RegClassByHwMode RC(RegClassDef, *this);
2698 for (unsigned M = 0; M < NumModes; ++M) {
2699 if (RC.hasMode(M) && !RC.get(Mode: M)->contains(Reg: Reg ? Reg : RegByMode->get(Mode: M)))
2700 return false;
2701 }
2702 return true;
2703 }
2704 // Otherwise we have a plain register class, check Register[ByHwMode]
2705 CodeGenRegisterClass *RC = getRegClass(Def: RegClassDef, Loc);
2706 if (Reg)
2707 return RC->contains(Reg);
2708 for (unsigned M = 0; M < NumModes; ++M) {
2709 if (RegByMode->hasMode(M) && !RC->contains(Reg: RegByMode->get(Mode: M)))
2710 return false;
2711 }
2712 return true; // RegByMode contained for all possible modes.
2713}
2714
2715const CodeGenRegisterClass *
2716CodeGenRegBank::getMinimalPhysRegClass(const Record *RegRecord,
2717 ValueTypeByHwMode *VT) {
2718 const CodeGenRegister *Reg = getReg(Def: RegRecord);
2719 const CodeGenRegisterClass *BestRC = nullptr;
2720 for (const CodeGenRegisterClass &RC : getRegClasses()) {
2721 if ((!VT || RC.hasType(VT: *VT)) && RC.contains(Reg) &&
2722 (!BestRC || BestRC->hasSubClass(RC: &RC)))
2723 BestRC = &RC;
2724 }
2725
2726 assert(BestRC && "Couldn't find the register class");
2727 return BestRC;
2728}
2729
2730const CodeGenRegisterClass *
2731CodeGenRegBank::getSuperRegForSubReg(const ValueTypeByHwMode &ValueTy,
2732 const CodeGenSubRegIndex *SubIdx,
2733 bool MustBeAllocatable) const {
2734 std::vector<const CodeGenRegisterClass *> Candidates;
2735 auto &RegClasses = getRegClasses();
2736
2737 // Try to find a register class which supports ValueTy, and also contains
2738 // SubIdx.
2739 for (const CodeGenRegisterClass &RC : RegClasses) {
2740 // Is there a subclass of this class which contains this subregister index?
2741 const CodeGenRegisterClass *SubClassWithSubReg =
2742 RC.getSubClassWithSubReg(SubIdx);
2743 if (!SubClassWithSubReg)
2744 continue;
2745
2746 // We have a class. Check if it supports this value type.
2747 if (!llvm::is_contained(Range: SubClassWithSubReg->VTs, Element: ValueTy))
2748 continue;
2749
2750 // If necessary, check that it is allocatable.
2751 if (MustBeAllocatable && !SubClassWithSubReg->Allocatable)
2752 continue;
2753
2754 // We have a register class which supports both the value type and
2755 // subregister index. Remember it.
2756 Candidates.push_back(x: SubClassWithSubReg);
2757 }
2758
2759 // If we didn't find anything, we're done.
2760 if (Candidates.empty())
2761 return nullptr;
2762
2763 // Find and return the largest of our candidate classes.
2764 llvm::stable_sort(Range&: Candidates, C: [&](const CodeGenRegisterClass *A,
2765 const CodeGenRegisterClass *B) {
2766 if (A->getMembers().size() > B->getMembers().size())
2767 return true;
2768
2769 if (A->getMembers().size() < B->getMembers().size())
2770 return false;
2771
2772 // Order by name as a tie-breaker.
2773 return StringRef(A->getName()) < B->getName();
2774 });
2775
2776 return Candidates[0];
2777}
2778
2779BitVector
2780CodeGenRegBank::computeCoveredRegisters(ArrayRef<const Record *> Regs) {
2781 SetVector<const CodeGenRegister *> Set;
2782
2783 // First add Regs with all sub-registers.
2784 for (const Record *RegDef : Regs) {
2785 CodeGenRegister *Reg = getReg(Def: RegDef);
2786 if (Set.insert(X: Reg))
2787 // Reg is new, add all sub-registers.
2788 // The pre-ordering is not important here.
2789 Reg->addSubRegsPreOrder(OSet&: Set, RegBank&: *this);
2790 }
2791
2792 // Second, find all super-registers that are completely covered by the set.
2793 for (unsigned i = 0; i != Set.size(); ++i) {
2794 for (const CodeGenRegister *Super : Set[i]->getSuperRegs()) {
2795 if (!Super->CoveredBySubRegs || Set.contains(key: Super))
2796 continue;
2797 // This new super-register is covered by its sub-registers.
2798 bool AllSubsInSet = true;
2799 const CodeGenRegister::SubRegMap &SRM = Super->getSubRegs();
2800 for (auto [_, SR] : SRM)
2801 if (!Set.contains(key: SR)) {
2802 AllSubsInSet = false;
2803 break;
2804 }
2805 // All sub-registers in Set, add Super as well.
2806 // We will visit Super later to recheck its super-registers.
2807 if (AllSubsInSet)
2808 Set.insert(X: Super);
2809 }
2810 }
2811
2812 // Convert to BitVector.
2813 BitVector BV(Registers.size() + 1);
2814 for (const CodeGenRegister *Reg : Set)
2815 BV.set(Reg->EnumValue);
2816 return BV;
2817}
2818
2819void CodeGenRegBank::printRegUnitNames(ArrayRef<unsigned> Units) const {
2820 for (unsigned Unit : Units) {
2821 if (Unit < NumNativeRegUnits)
2822 dbgs() << ' ' << RegUnits[Unit].Roots[0]->getName();
2823 else
2824 dbgs() << " #" << Unit;
2825 }
2826 dbgs() << '\n';
2827}
2828