1//===-- elfnix_tlv.aarch64.s ---------------------------------------*- ASM -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file is a part of the ORC runtime support library.
10//
11//===----------------------------------------------------------------------===//
12
13// The content of this file is aarch64-only
14#if defined(__arm64__) || defined(__aarch64__)
15
16#include "builtins/assembly.h"
17
18#define REGISTER_SAVE_SPACE_SIZE 32 * 24
19
20 TEXT_SECTION
21
22 // returns address of TLV in x0, all other registers preserved
23 // TODO: add fast-path for repeat access
24 .globl ___orc_rt_elfnix_tlsdesc_resolver
25___orc_rt_elfnix_tlsdesc_resolver:
26 sub sp, sp, #REGISTER_SAVE_SPACE_SIZE
27 stp x29, x30, [sp, #16 * 1]
28 stp x27, x28, [sp, #16 * 2]
29 stp x25, x26, [sp, #16 * 3]
30 stp x23, x24, [sp, #16 * 4]
31 stp x21, x22, [sp, #16 * 5]
32 stp x19, x20, [sp, #16 * 6]
33 stp x17, x18, [sp, #16 * 7]
34 stp x15, x16, [sp, #16 * 8]
35 stp x13, x14, [sp, #16 * 9]
36 stp x11, x12, [sp, #16 * 10]
37 stp x9, x10, [sp, #16 * 11]
38 stp x7, x8, [sp, #16 * 12]
39 stp x5, x6, [sp, #16 * 13]
40 stp x3, x4, [sp, #16 * 14]
41 stp x1, x2, [sp, #16 * 15]
42 stp q30, q31, [sp, #32 * 8]
43 stp q28, q29, [sp, #32 * 9]
44 stp q26, q27, [sp, #32 * 10]
45 stp q24, q25, [sp, #32 * 11]
46 stp q22, q23, [sp, #32 * 12]
47 stp q20, q21, [sp, #32 * 13]
48 stp q18, q19, [sp, #32 * 14]
49 stp q16, q17, [sp, #32 * 15]
50 stp q14, q15, [sp, #32 * 16]
51 stp q12, q13, [sp, #32 * 17]
52 stp q10, q11, [sp, #32 * 18]
53 stp q8, q9, [sp, #32 * 19]
54 stp q6, q7, [sp, #32 * 20]
55 stp q4, q5, [sp, #32 * 21]
56 stp q2, q3, [sp, #32 * 22]
57 stp q0, q1, [sp, #32 * 23]
58
59 mrs x1, TPIDR_EL0 // get thread pointer
60 bl ___orc_rt_elfnix_tlsdesc_resolver_impl
61
62 ldp q0, q1, [sp, #32 * 23]
63 ldp q2, q3, [sp, #32 * 22]
64 ldp q4, q5, [sp, #32 * 21]
65 ldp q6, q7, [sp, #32 * 20]
66 ldp q8, q9, [sp, #32 * 19]
67 ldp q10, q11, [sp, #32 * 18]
68 ldp q12, q13, [sp, #32 * 17]
69 ldp q14, q15, [sp, #32 * 16]
70 ldp q16, q17, [sp, #32 * 15]
71 ldp q18, q19, [sp, #32 * 14]
72 ldp q20, q21, [sp, #32 * 13]
73 ldp q22, q23, [sp, #32 * 12]
74 ldp q24, q25, [sp, #32 * 11]
75 ldp q26, q27, [sp, #32 * 10]
76 ldp q28, q29, [sp, #32 * 9]
77 ldp q30, q31, [sp, #32 * 8]
78 ldp x1, x2, [sp, #16 * 15]
79 ldp x3, x4, [sp, #16 * 14]
80 ldp x5, x6, [sp, #16 * 13]
81 ldp x7, x8, [sp, #16 * 12]
82 ldp x9, x10, [sp, #16 * 11]
83 ldp x11, x12, [sp, #16 * 10]
84 ldp x13, x14, [sp, #16 * 9]
85 ldp x15, x16, [sp, #16 * 8]
86 ldp x17, x18, [sp, #16 * 7]
87 ldp x19, x20, [sp, #16 * 6]
88 ldp x21, x22, [sp, #16 * 5]
89 ldp x23, x24, [sp, #16 * 4]
90 ldp x25, x26, [sp, #16 * 3]
91 ldp x27, x28, [sp, #16 * 2]
92 ldp x29, x30, [sp, #16 * 1]
93 add sp, sp, #REGISTER_SAVE_SPACE_SIZE
94 ret
95
96#endif // defined(__arm64__) || defined(__aarch64__)
97