1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Calling Convention Implementation Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifndef GET_CC_REGISTER_LISTS
10
11bool llvm::CC_AArch64_AAPCS(unsigned ValNo, MVT ValVT,
12 MVT LocVT, CCValAssign::LocInfo LocInfo,
13 ISD::ArgFlagsTy ArgFlags, CCState &State);
14bool llvm::CC_AArch64_Arm64EC_CFGuard_Check(unsigned ValNo, MVT ValVT,
15 MVT LocVT, CCValAssign::LocInfo LocInfo,
16 ISD::ArgFlagsTy ArgFlags, CCState &State);
17bool llvm::CC_AArch64_Arm64EC_Thunk(unsigned ValNo, MVT ValVT,
18 MVT LocVT, CCValAssign::LocInfo LocInfo,
19 ISD::ArgFlagsTy ArgFlags, CCState &State);
20bool llvm::CC_AArch64_Arm64EC_Thunk_Native(unsigned ValNo, MVT ValVT,
21 MVT LocVT, CCValAssign::LocInfo LocInfo,
22 ISD::ArgFlagsTy ArgFlags, CCState &State);
23bool llvm::CC_AArch64_Arm64EC_VarArg(unsigned ValNo, MVT ValVT,
24 MVT LocVT, CCValAssign::LocInfo LocInfo,
25 ISD::ArgFlagsTy ArgFlags, CCState &State);
26bool llvm::CC_AArch64_DarwinPCS(unsigned ValNo, MVT ValVT,
27 MVT LocVT, CCValAssign::LocInfo LocInfo,
28 ISD::ArgFlagsTy ArgFlags, CCState &State);
29bool llvm::CC_AArch64_DarwinPCS_ILP32_VarArg(unsigned ValNo, MVT ValVT,
30 MVT LocVT, CCValAssign::LocInfo LocInfo,
31 ISD::ArgFlagsTy ArgFlags, CCState &State);
32bool llvm::CC_AArch64_DarwinPCS_VarArg(unsigned ValNo, MVT ValVT,
33 MVT LocVT, CCValAssign::LocInfo LocInfo,
34 ISD::ArgFlagsTy ArgFlags, CCState &State);
35bool llvm::CC_AArch64_GHC(unsigned ValNo, MVT ValVT,
36 MVT LocVT, CCValAssign::LocInfo LocInfo,
37 ISD::ArgFlagsTy ArgFlags, CCState &State);
38bool llvm::CC_AArch64_Preserve_None(unsigned ValNo, MVT ValVT,
39 MVT LocVT, CCValAssign::LocInfo LocInfo,
40 ISD::ArgFlagsTy ArgFlags, CCState &State);
41bool llvm::CC_AArch64_Win64PCS(unsigned ValNo, MVT ValVT,
42 MVT LocVT, CCValAssign::LocInfo LocInfo,
43 ISD::ArgFlagsTy ArgFlags, CCState &State);
44bool llvm::CC_AArch64_Win64_CFGuard_Check(unsigned ValNo, MVT ValVT,
45 MVT LocVT, CCValAssign::LocInfo LocInfo,
46 ISD::ArgFlagsTy ArgFlags, CCState &State);
47bool llvm::CC_AArch64_Win64_VarArg(unsigned ValNo, MVT ValVT,
48 MVT LocVT, CCValAssign::LocInfo LocInfo,
49 ISD::ArgFlagsTy ArgFlags, CCState &State);
50bool llvm::RetCC_AArch64_AAPCS(unsigned ValNo, MVT ValVT,
51 MVT LocVT, CCValAssign::LocInfo LocInfo,
52 ISD::ArgFlagsTy ArgFlags, CCState &State);
53bool llvm::RetCC_AArch64_Arm64EC_CFGuard_Check(unsigned ValNo, MVT ValVT,
54 MVT LocVT, CCValAssign::LocInfo LocInfo,
55 ISD::ArgFlagsTy ArgFlags, CCState &State);
56bool llvm::RetCC_AArch64_Arm64EC_Thunk(unsigned ValNo, MVT ValVT,
57 MVT LocVT, CCValAssign::LocInfo LocInfo,
58 ISD::ArgFlagsTy ArgFlags, CCState &State);
59
60
61bool llvm::CC_AArch64_AAPCS(unsigned ValNo, MVT ValVT,
62 MVT LocVT, CCValAssign::LocInfo LocInfo,
63 ISD::ArgFlagsTy ArgFlags, CCState &State) {
64
65 if (ArgFlags.isNest()) {
66 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X15)) {
67 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
68 return false;
69 }
70 }
71
72 if (LocVT == MVT::iPTR) {
73 LocVT = MVT::i64;
74 LocInfo = CCValAssign::BCvt;
75 }
76
77 if (LocVT == MVT::v2f32) {
78 LocVT = MVT::v2i32;
79 LocInfo = CCValAssign::BCvt;
80 }
81
82 if (LocVT == MVT::v2f64 ||
83 LocVT == MVT::v4f32) {
84 LocVT = MVT::v2i64;
85 LocInfo = CCValAssign::BCvt;
86 }
87
88 if (State.getMachineFunction().getDataLayout().isBigEndian()) {
89 if (LocVT == MVT::v2i32 ||
90 LocVT == MVT::v2f32 ||
91 LocVT == MVT::v4i16 ||
92 LocVT == MVT::v4f16 ||
93 LocVT == MVT::v4bf16 ||
94 LocVT == MVT::v8i8) {
95 LocVT = MVT::f64;
96 LocInfo = CCValAssign::BCvt;
97 }
98 }
99
100 if (State.getMachineFunction().getDataLayout().isBigEndian()) {
101 if (LocVT == MVT::v2i64 ||
102 LocVT == MVT::v2f64 ||
103 LocVT == MVT::v4i32 ||
104 LocVT == MVT::v4f32 ||
105 LocVT == MVT::v8i16 ||
106 LocVT == MVT::v8f16 ||
107 LocVT == MVT::v8bf16 ||
108 LocVT == MVT::v16i8) {
109 LocVT = MVT::f128;
110 LocInfo = CCValAssign::BCvt;
111 }
112 }
113
114 if (ArgFlags.isInReg()) {
115 if (LocVT == MVT::i64) {
116 if (ArgFlags.isSRet()) {
117 if (LocVT == MVT::i64) {
118 static const MCPhysReg RegList1[] = {
119 AArch64::X0, AArch64::X1
120 };
121 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
122 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
123 return false;
124 }
125 }
126 }
127 }
128 }
129
130 if (ArgFlags.isSRet()) {
131 if (LocVT == MVT::i64) {
132 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X8)) {
133 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
134 return false;
135 }
136 }
137 }
138
139 if (ArgFlags.isByVal()) {
140 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 8, MinAlign: Align(8), ArgFlags);
141 return false;
142 }
143
144 if (ArgFlags.isSwiftSelf()) {
145 if (LocVT == MVT::i64) {
146 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X20)) {
147 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
148 return false;
149 }
150 }
151 }
152
153 if (ArgFlags.isSwiftError()) {
154 if (LocVT == MVT::i64) {
155 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X21)) {
156 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
157 return false;
158 }
159 }
160 }
161
162 if (ArgFlags.isSwiftAsync()) {
163 if (LocVT == MVT::i64) {
164 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X22)) {
165 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
166 return false;
167 }
168 }
169 }
170
171 if (ArgFlags.isInConsecutiveRegs()) {
172 if (CC_AArch64_Custom_Block(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
173 return false;
174 }
175
176 if (LocVT == MVT::nxv16i8 ||
177 LocVT == MVT::nxv8i16 ||
178 LocVT == MVT::nxv4i32 ||
179 LocVT == MVT::nxv2i64 ||
180 LocVT == MVT::nxv2f16 ||
181 LocVT == MVT::nxv4f16 ||
182 LocVT == MVT::nxv8f16 ||
183 LocVT == MVT::nxv2bf16 ||
184 LocVT == MVT::nxv4bf16 ||
185 LocVT == MVT::nxv8bf16 ||
186 LocVT == MVT::nxv2f32 ||
187 LocVT == MVT::nxv4f32 ||
188 LocVT == MVT::nxv2f64) {
189 static const MCPhysReg RegList2[] = {
190 AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7
191 };
192 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
193 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
194 return false;
195 }
196 }
197
198 if (LocVT == MVT::nxv16i8 ||
199 LocVT == MVT::nxv8i16 ||
200 LocVT == MVT::nxv4i32 ||
201 LocVT == MVT::nxv2i64 ||
202 LocVT == MVT::nxv2f16 ||
203 LocVT == MVT::nxv4f16 ||
204 LocVT == MVT::nxv8f16 ||
205 LocVT == MVT::nxv2bf16 ||
206 LocVT == MVT::nxv4bf16 ||
207 LocVT == MVT::nxv8bf16 ||
208 LocVT == MVT::nxv2f32 ||
209 LocVT == MVT::nxv4f32 ||
210 LocVT == MVT::nxv2f64) {
211 LocVT = MVT::i64;
212 LocInfo = CCValAssign::Indirect;
213 }
214
215 if (LocVT == MVT::nxv1i1 ||
216 LocVT == MVT::nxv2i1 ||
217 LocVT == MVT::nxv4i1 ||
218 LocVT == MVT::nxv8i1 ||
219 LocVT == MVT::nxv16i1 ||
220 LocVT == MVT::aarch64svcount) {
221 static const MCPhysReg RegList3[] = {
222 AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3
223 };
224 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
225 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
226 return false;
227 }
228 }
229
230 if (LocVT == MVT::nxv1i1 ||
231 LocVT == MVT::nxv2i1 ||
232 LocVT == MVT::nxv4i1 ||
233 LocVT == MVT::nxv8i1 ||
234 LocVT == MVT::nxv16i1 ||
235 LocVT == MVT::aarch64svcount) {
236 LocVT = MVT::i64;
237 LocInfo = CCValAssign::Indirect;
238 }
239
240 if (LocVT == MVT::i1 ||
241 LocVT == MVT::i8 ||
242 LocVT == MVT::i16) {
243 LocVT = MVT::i32;
244 if (ArgFlags.isSExt())
245 LocInfo = CCValAssign::SExt;
246 else if (ArgFlags.isZExt())
247 LocInfo = CCValAssign::ZExt;
248 else
249 LocInfo = CCValAssign::AExt;
250 }
251
252 if (LocVT == MVT::i32) {
253 static const MCPhysReg RegList4[] = {
254 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
255 };
256 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
257 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
258 return false;
259 }
260 }
261
262 if (LocVT == MVT::i64) {
263 if (ArgFlags.isSplit()) {
264 static const MCPhysReg RegList5[] = {
265 AArch64::X0, AArch64::X2, AArch64::X4, AArch64::X6
266 };
267 static const MCPhysReg RegList6[] = {
268 AArch64::X0, AArch64::X1, AArch64::X3, AArch64::X5
269 };
270 if (MCRegister Reg = State.AllocateReg(Regs: RegList5, ShadowRegs: RegList6)) {
271 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
272 return false;
273 }
274 }
275 }
276
277 if (LocVT == MVT::i64) {
278 if (ArgFlags.isSplit()) {
279 static const MCPhysReg ShadowRegList7[] = {
280 AArch64::X7
281 };
282 int64_t Offset8 = State.AllocateStack(Size: 8, Alignment: Align(16), ShadowRegs: ShadowRegList7);
283 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset8, LocVT, HTP: LocInfo));
284 return false;
285 }
286 }
287
288 if (LocVT == MVT::i64) {
289 static const MCPhysReg RegList9[] = {
290 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
291 };
292 if (MCRegister Reg = State.AllocateReg(Regs: RegList9)) {
293 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
294 return false;
295 }
296 }
297
298 if (LocVT == MVT::f16) {
299 static const MCPhysReg RegList10[] = {
300 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
301 };
302 if (MCRegister Reg = State.AllocateReg(Regs: RegList10)) {
303 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
304 return false;
305 }
306 }
307
308 if (LocVT == MVT::bf16) {
309 static const MCPhysReg RegList11[] = {
310 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
311 };
312 if (MCRegister Reg = State.AllocateReg(Regs: RegList11)) {
313 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
314 return false;
315 }
316 }
317
318 if (LocVT == MVT::f32) {
319 static const MCPhysReg RegList12[] = {
320 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7
321 };
322 if (MCRegister Reg = State.AllocateReg(Regs: RegList12)) {
323 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
324 return false;
325 }
326 }
327
328 if (LocVT == MVT::f64) {
329 static const MCPhysReg RegList13[] = {
330 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
331 };
332 if (MCRegister Reg = State.AllocateReg(Regs: RegList13)) {
333 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
334 return false;
335 }
336 }
337
338 if (LocVT == MVT::v1i64 ||
339 LocVT == MVT::v2i32 ||
340 LocVT == MVT::v4i16 ||
341 LocVT == MVT::v8i8 ||
342 LocVT == MVT::v1f64 ||
343 LocVT == MVT::v2f32 ||
344 LocVT == MVT::v4f16 ||
345 LocVT == MVT::v4bf16) {
346 static const MCPhysReg RegList14[] = {
347 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
348 };
349 if (MCRegister Reg = State.AllocateReg(Regs: RegList14)) {
350 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
351 return false;
352 }
353 }
354
355 if (LocVT == MVT::f128 ||
356 LocVT == MVT::v2i64 ||
357 LocVT == MVT::v4i32 ||
358 LocVT == MVT::v8i16 ||
359 LocVT == MVT::v16i8 ||
360 LocVT == MVT::v4f32 ||
361 LocVT == MVT::v2f64 ||
362 LocVT == MVT::v8f16 ||
363 LocVT == MVT::v8bf16) {
364 static const MCPhysReg RegList15[] = {
365 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
366 };
367 if (MCRegister Reg = State.AllocateReg(Regs: RegList15)) {
368 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
369 return false;
370 }
371 }
372
373 if (LocVT == MVT::i1 ||
374 LocVT == MVT::i8 ||
375 LocVT == MVT::i16 ||
376 LocVT == MVT::f16 ||
377 LocVT == MVT::bf16) {
378 int64_t Offset16 = State.AllocateStack(Size: 8, Alignment: Align(8));
379 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset16, LocVT, HTP: LocInfo));
380 return false;
381 }
382
383 if (LocVT == MVT::i32 ||
384 LocVT == MVT::f32) {
385 int64_t Offset17 = State.AllocateStack(Size: 8, Alignment: Align(8));
386 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset17, LocVT, HTP: LocInfo));
387 return false;
388 }
389
390 if (LocVT == MVT::i64 ||
391 LocVT == MVT::f64 ||
392 LocVT == MVT::v1f64 ||
393 LocVT == MVT::v2f32 ||
394 LocVT == MVT::v1i64 ||
395 LocVT == MVT::v2i32 ||
396 LocVT == MVT::v4i16 ||
397 LocVT == MVT::v8i8 ||
398 LocVT == MVT::v4f16 ||
399 LocVT == MVT::v4bf16) {
400 int64_t Offset18 = State.AllocateStack(Size: 8, Alignment: Align(8));
401 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset18, LocVT, HTP: LocInfo));
402 return false;
403 }
404
405 if (LocVT == MVT::f128 ||
406 LocVT == MVT::v2i64 ||
407 LocVT == MVT::v4i32 ||
408 LocVT == MVT::v8i16 ||
409 LocVT == MVT::v16i8 ||
410 LocVT == MVT::v4f32 ||
411 LocVT == MVT::v2f64 ||
412 LocVT == MVT::v8f16 ||
413 LocVT == MVT::v8bf16) {
414 int64_t Offset19 = State.AllocateStack(Size: 16, Alignment: Align(16));
415 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset19, LocVT, HTP: LocInfo));
416 return false;
417 }
418
419 return true; // CC didn't match.
420}
421
422
423bool llvm::CC_AArch64_Arm64EC_CFGuard_Check(unsigned ValNo, MVT ValVT,
424 MVT LocVT, CCValAssign::LocInfo LocInfo,
425 ISD::ArgFlagsTy ArgFlags, CCState &State) {
426
427 if (LocVT == MVT::i64) {
428 static const MCPhysReg RegList1[] = {
429 AArch64::X11, AArch64::X10, AArch64::X9
430 };
431 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
432 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
433 return false;
434 }
435 }
436
437 return true; // CC didn't match.
438}
439
440
441bool llvm::CC_AArch64_Arm64EC_Thunk(unsigned ValNo, MVT ValVT,
442 MVT LocVT, CCValAssign::LocInfo LocInfo,
443 ISD::ArgFlagsTy ArgFlags, CCState &State) {
444
445 if (ArgFlags.isInReg()) {
446 if (LocVT == MVT::i64) {
447 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X4)) {
448 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
449 return false;
450 }
451 }
452 }
453
454 if (ArgFlags.isByVal()) {
455 LocVT = MVT::i64;
456 LocInfo = CCValAssign::Indirect;
457 }
458
459 if (LocVT == MVT::i1 ||
460 LocVT == MVT::i8 ||
461 LocVT == MVT::i16) {
462 LocVT = MVT::i32;
463 if (ArgFlags.isSExt())
464 LocInfo = CCValAssign::SExt;
465 else if (ArgFlags.isZExt())
466 LocInfo = CCValAssign::ZExt;
467 else
468 LocInfo = CCValAssign::AExt;
469 }
470
471 if (ArgFlags.isNest()) {
472 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X4)) {
473 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
474 return false;
475 }
476 }
477
478 if (ArgFlags.isSwiftError()) {
479 if (LocVT == MVT::i64) {
480 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X19)) {
481 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
482 return false;
483 }
484 }
485 }
486
487 if (ArgFlags.isSwiftSelf()) {
488 if (LocVT == MVT::i64) {
489 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X20)) {
490 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
491 return false;
492 }
493 }
494 }
495
496 if (ArgFlags.isSwiftAsync()) {
497 if (LocVT == MVT::i64) {
498 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X21)) {
499 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
500 return false;
501 }
502 }
503 }
504
505 if (ArgFlags.isCFGuardTarget()) {
506 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X8)) {
507 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
508 return false;
509 }
510 }
511
512 if (LocVT == MVT::v16i8 ||
513 LocVT == MVT::v8i16 ||
514 LocVT == MVT::v4i32 ||
515 LocVT == MVT::v2i64 ||
516 LocVT == MVT::v8f16 ||
517 LocVT == MVT::v4f32 ||
518 LocVT == MVT::v2f64) {
519 LocVT = MVT::i64;
520 LocInfo = CCValAssign::Indirect;
521 }
522
523 if (LocVT == MVT::v32i8 ||
524 LocVT == MVT::v16i16 ||
525 LocVT == MVT::v8i32 ||
526 LocVT == MVT::v4i64 ||
527 LocVT == MVT::v16f16 ||
528 LocVT == MVT::v8f32 ||
529 LocVT == MVT::v4f64) {
530 LocVT = MVT::i64;
531 LocInfo = CCValAssign::Indirect;
532 }
533
534 if (LocVT == MVT::v64i8 ||
535 LocVT == MVT::v32i16 ||
536 LocVT == MVT::v16i32 ||
537 LocVT == MVT::v32f16 ||
538 LocVT == MVT::v16f32 ||
539 LocVT == MVT::v8f64 ||
540 LocVT == MVT::v8i64) {
541 LocVT = MVT::i64;
542 LocInfo = CCValAssign::Indirect;
543 }
544
545 if (LocVT == MVT::f80) {
546 LocVT = MVT::i64;
547 LocInfo = CCValAssign::Indirect;
548 }
549
550 if (LocVT == MVT::x86mmx) {
551 LocVT = MVT::i64;
552 LocInfo = CCValAssign::BCvt;
553 }
554
555 if (LocVT == MVT::f16) {
556 static const MCPhysReg RegList1[] = {
557 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3
558 };
559 static const MCPhysReg RegList2[] = {
560 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3
561 };
562 if (MCRegister Reg = State.AllocateReg(Regs: RegList1, ShadowRegs: RegList2)) {
563 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
564 return false;
565 }
566 }
567
568 if (LocVT == MVT::f32) {
569 static const MCPhysReg RegList3[] = {
570 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3
571 };
572 static const MCPhysReg RegList4[] = {
573 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3
574 };
575 if (MCRegister Reg = State.AllocateReg(Regs: RegList3, ShadowRegs: RegList4)) {
576 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
577 return false;
578 }
579 }
580
581 if (LocVT == MVT::f64) {
582 static const MCPhysReg RegList5[] = {
583 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3
584 };
585 static const MCPhysReg RegList6[] = {
586 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3
587 };
588 if (MCRegister Reg = State.AllocateReg(Regs: RegList5, ShadowRegs: RegList6)) {
589 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
590 return false;
591 }
592 }
593
594 if (LocVT == MVT::i32) {
595 static const MCPhysReg RegList7[] = {
596 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3
597 };
598 static const MCPhysReg RegList8[] = {
599 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3
600 };
601 if (MCRegister Reg = State.AllocateReg(Regs: RegList7, ShadowRegs: RegList8)) {
602 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
603 return false;
604 }
605 }
606
607 if (LocVT == MVT::i64) {
608 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X9)) {
609 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
610 return false;
611 }
612 }
613
614 if (LocVT == MVT::i64) {
615 static const MCPhysReg RegList9[] = {
616 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3
617 };
618 static const MCPhysReg RegList10[] = {
619 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3
620 };
621 if (MCRegister Reg = State.AllocateReg(Regs: RegList9, ShadowRegs: RegList10)) {
622 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
623 return false;
624 }
625 }
626
627 if (LocVT == MVT::i8 ||
628 LocVT == MVT::i16 ||
629 LocVT == MVT::i32 ||
630 LocVT == MVT::i64 ||
631 LocVT == MVT::f16 ||
632 LocVT == MVT::f32 ||
633 LocVT == MVT::f64) {
634 int64_t Offset11 = State.AllocateStack(Size: 8, Alignment: Align(8));
635 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset11, LocVT, HTP: LocInfo));
636 return false;
637 }
638
639 return true; // CC didn't match.
640}
641
642
643bool llvm::CC_AArch64_Arm64EC_Thunk_Native(unsigned ValNo, MVT ValVT,
644 MVT LocVT, CCValAssign::LocInfo LocInfo,
645 ISD::ArgFlagsTy ArgFlags, CCState &State) {
646
647 if (LocVT == MVT::i64) {
648 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X9)) {
649 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
650 return false;
651 }
652 }
653
654 if (!CC_AArch64_AAPCS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
655 return false;
656
657 return true; // CC didn't match.
658}
659
660
661bool llvm::CC_AArch64_Arm64EC_VarArg(unsigned ValNo, MVT ValVT,
662 MVT LocVT, CCValAssign::LocInfo LocInfo,
663 ISD::ArgFlagsTy ArgFlags, CCState &State) {
664
665 if (ArgFlags.isNest()) {
666 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X15)) {
667 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
668 return false;
669 }
670 }
671
672 if (LocVT == MVT::f16 ||
673 LocVT == MVT::bf16) {
674 LocVT = MVT::i16;
675 LocInfo = CCValAssign::BCvt;
676 }
677
678 if (LocVT == MVT::f32) {
679 LocVT = MVT::i32;
680 LocInfo = CCValAssign::BCvt;
681 }
682
683 if (LocVT == MVT::f64 ||
684 LocVT == MVT::v1f64 ||
685 LocVT == MVT::v1i64 ||
686 LocVT == MVT::v2f32 ||
687 LocVT == MVT::v2i32 ||
688 LocVT == MVT::v4i16 ||
689 LocVT == MVT::v4f16 ||
690 LocVT == MVT::v4bf16 ||
691 LocVT == MVT::v8i8 ||
692 LocVT == MVT::iPTR) {
693 LocVT = MVT::i64;
694 LocInfo = CCValAssign::BCvt;
695 }
696
697 if (LocVT == MVT::f128 ||
698 LocVT == MVT::v2f64 ||
699 LocVT == MVT::v2i64 ||
700 LocVT == MVT::v4i32 ||
701 LocVT == MVT::v4f32 ||
702 LocVT == MVT::v8i16 ||
703 LocVT == MVT::v8f16 ||
704 LocVT == MVT::v8bf16 ||
705 LocVT == MVT::v16i8) {
706 LocVT = MVT::i64;
707 LocInfo = CCValAssign::Indirect;
708 }
709
710 if (LocVT == MVT::nxv16i8 ||
711 LocVT == MVT::nxv8i16 ||
712 LocVT == MVT::nxv4i32 ||
713 LocVT == MVT::nxv2i64 ||
714 LocVT == MVT::nxv2f16 ||
715 LocVT == MVT::nxv4f16 ||
716 LocVT == MVT::nxv8f16 ||
717 LocVT == MVT::nxv2bf16 ||
718 LocVT == MVT::nxv4bf16 ||
719 LocVT == MVT::nxv8bf16 ||
720 LocVT == MVT::nxv2f32 ||
721 LocVT == MVT::nxv4f32 ||
722 LocVT == MVT::nxv2f64) {
723 LocVT = MVT::i64;
724 LocInfo = CCValAssign::Indirect;
725 }
726
727 if (LocVT == MVT::nxv2i1 ||
728 LocVT == MVT::nxv4i1 ||
729 LocVT == MVT::nxv8i1 ||
730 LocVT == MVT::nxv16i1) {
731 LocVT = MVT::i64;
732 LocInfo = CCValAssign::Indirect;
733 }
734
735 if (ArgFlags.isInReg()) {
736 if (LocVT == MVT::i64) {
737 if (ArgFlags.isSRet()) {
738 if (LocVT == MVT::i64) {
739 static const MCPhysReg RegList1[] = {
740 AArch64::X0, AArch64::X1
741 };
742 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
743 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
744 return false;
745 }
746 }
747 }
748 }
749 }
750
751 if (ArgFlags.isSRet()) {
752 if (LocVT == MVT::i64) {
753 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X8)) {
754 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
755 return false;
756 }
757 }
758 }
759
760 if (ArgFlags.isByVal()) {
761 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 8, MinAlign: Align(8), ArgFlags);
762 return false;
763 }
764
765 if (LocVT == MVT::i1 ||
766 LocVT == MVT::i8 ||
767 LocVT == MVT::i16) {
768 LocVT = MVT::i32;
769 if (ArgFlags.isSExt())
770 LocInfo = CCValAssign::SExt;
771 else if (ArgFlags.isZExt())
772 LocInfo = CCValAssign::ZExt;
773 else
774 LocInfo = CCValAssign::AExt;
775 }
776
777 if (LocVT == MVT::i32) {
778 static const MCPhysReg RegList2[] = {
779 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3
780 };
781 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
782 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
783 return false;
784 }
785 }
786
787 if (LocVT == MVT::i64) {
788 static const MCPhysReg RegList3[] = {
789 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3
790 };
791 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
792 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
793 return false;
794 }
795 }
796
797 if (LocVT == MVT::i32 ||
798 LocVT == MVT::i64) {
799 int64_t Offset4 = State.AllocateStack(Size: 8, Alignment: Align(8));
800 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset4, LocVT, HTP: LocInfo));
801 return false;
802 }
803
804 return true; // CC didn't match.
805}
806
807
808bool llvm::CC_AArch64_DarwinPCS(unsigned ValNo, MVT ValVT,
809 MVT LocVT, CCValAssign::LocInfo LocInfo,
810 ISD::ArgFlagsTy ArgFlags, CCState &State) {
811
812 if (ArgFlags.isNest()) {
813 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X15)) {
814 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
815 return false;
816 }
817 }
818
819 if (LocVT == MVT::iPTR) {
820 LocVT = MVT::i64;
821 LocInfo = CCValAssign::BCvt;
822 }
823
824 if (LocVT == MVT::v2f32) {
825 LocVT = MVT::v2i32;
826 LocInfo = CCValAssign::BCvt;
827 }
828
829 if (LocVT == MVT::v2f64 ||
830 LocVT == MVT::v4f32 ||
831 LocVT == MVT::f128) {
832 LocVT = MVT::v2i64;
833 LocInfo = CCValAssign::BCvt;
834 }
835
836 if (ArgFlags.isSRet()) {
837 if (LocVT == MVT::i64) {
838 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X8)) {
839 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
840 return false;
841 }
842 }
843 }
844
845 if (ArgFlags.isByVal()) {
846 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 8, MinAlign: Align(8), ArgFlags);
847 return false;
848 }
849
850 if (ArgFlags.isSwiftSelf()) {
851 if (LocVT == MVT::i64) {
852 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X20)) {
853 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
854 return false;
855 }
856 }
857 }
858
859 if (ArgFlags.isSwiftError()) {
860 if (LocVT == MVT::i64) {
861 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X21)) {
862 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
863 return false;
864 }
865 }
866 }
867
868 if (ArgFlags.isSwiftAsync()) {
869 if (LocVT == MVT::i64) {
870 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X22)) {
871 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
872 return false;
873 }
874 }
875 }
876
877 if (ArgFlags.isInConsecutiveRegs()) {
878 if (CC_AArch64_Custom_Block(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
879 return false;
880 }
881
882 if (LocVT == MVT::nxv16i8 ||
883 LocVT == MVT::nxv8i16 ||
884 LocVT == MVT::nxv4i32 ||
885 LocVT == MVT::nxv2i64 ||
886 LocVT == MVT::nxv2f16 ||
887 LocVT == MVT::nxv4f16 ||
888 LocVT == MVT::nxv8f16 ||
889 LocVT == MVT::nxv2bf16 ||
890 LocVT == MVT::nxv4bf16 ||
891 LocVT == MVT::nxv8bf16 ||
892 LocVT == MVT::nxv2f32 ||
893 LocVT == MVT::nxv4f32 ||
894 LocVT == MVT::nxv2f64) {
895 static const MCPhysReg RegList1[] = {
896 AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7
897 };
898 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
899 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
900 return false;
901 }
902 }
903
904 if (LocVT == MVT::nxv16i8 ||
905 LocVT == MVT::nxv8i16 ||
906 LocVT == MVT::nxv4i32 ||
907 LocVT == MVT::nxv2i64 ||
908 LocVT == MVT::nxv2f16 ||
909 LocVT == MVT::nxv4f16 ||
910 LocVT == MVT::nxv8f16 ||
911 LocVT == MVT::nxv2bf16 ||
912 LocVT == MVT::nxv4bf16 ||
913 LocVT == MVT::nxv8bf16 ||
914 LocVT == MVT::nxv2f32 ||
915 LocVT == MVT::nxv4f32 ||
916 LocVT == MVT::nxv2f64) {
917 LocVT = MVT::i64;
918 LocInfo = CCValAssign::Indirect;
919 }
920
921 if (LocVT == MVT::nxv1i1 ||
922 LocVT == MVT::nxv2i1 ||
923 LocVT == MVT::nxv4i1 ||
924 LocVT == MVT::nxv8i1 ||
925 LocVT == MVT::nxv16i1 ||
926 LocVT == MVT::aarch64svcount) {
927 static const MCPhysReg RegList2[] = {
928 AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3
929 };
930 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
931 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
932 return false;
933 }
934 }
935
936 if (LocVT == MVT::nxv1i1 ||
937 LocVT == MVT::nxv2i1 ||
938 LocVT == MVT::nxv4i1 ||
939 LocVT == MVT::nxv8i1 ||
940 LocVT == MVT::nxv16i1 ||
941 LocVT == MVT::aarch64svcount) {
942 LocVT = MVT::i64;
943 LocInfo = CCValAssign::Indirect;
944 }
945
946 if (LocVT == MVT::i1 ||
947 LocVT == MVT::i8 ||
948 LocVT == MVT::i16) {
949 LocVT = MVT::i32;
950 if (ArgFlags.isSExt())
951 LocInfo = CCValAssign::SExt;
952 else if (ArgFlags.isZExt())
953 LocInfo = CCValAssign::ZExt;
954 else
955 LocInfo = CCValAssign::AExt;
956 }
957
958 if (LocVT == MVT::i32) {
959 static const MCPhysReg RegList3[] = {
960 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
961 };
962 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
963 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
964 return false;
965 }
966 }
967
968 if (LocVT == MVT::i64) {
969 if (ArgFlags.isSplit()) {
970 static const MCPhysReg RegList4[] = {
971 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6
972 };
973 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
974 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
975 return false;
976 }
977 }
978 }
979
980 if (LocVT == MVT::i64) {
981 if (ArgFlags.isSplit()) {
982 static const MCPhysReg ShadowRegList5[] = {
983 AArch64::X7
984 };
985 int64_t Offset6 = State.AllocateStack(Size: 8, Alignment: Align(16), ShadowRegs: ShadowRegList5);
986 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset6, LocVT, HTP: LocInfo));
987 return false;
988 }
989 }
990
991 if (LocVT == MVT::i64) {
992 static const MCPhysReg RegList7[] = {
993 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
994 };
995 if (MCRegister Reg = State.AllocateReg(Regs: RegList7)) {
996 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
997 return false;
998 }
999 }
1000
1001 if (LocVT == MVT::f16) {
1002 static const MCPhysReg RegList8[] = {
1003 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
1004 };
1005 if (MCRegister Reg = State.AllocateReg(Regs: RegList8)) {
1006 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1007 return false;
1008 }
1009 }
1010
1011 if (LocVT == MVT::bf16) {
1012 static const MCPhysReg RegList9[] = {
1013 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
1014 };
1015 if (MCRegister Reg = State.AllocateReg(Regs: RegList9)) {
1016 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1017 return false;
1018 }
1019 }
1020
1021 if (LocVT == MVT::f32) {
1022 static const MCPhysReg RegList10[] = {
1023 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7
1024 };
1025 if (MCRegister Reg = State.AllocateReg(Regs: RegList10)) {
1026 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1027 return false;
1028 }
1029 }
1030
1031 if (LocVT == MVT::f64) {
1032 static const MCPhysReg RegList11[] = {
1033 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
1034 };
1035 if (MCRegister Reg = State.AllocateReg(Regs: RegList11)) {
1036 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1037 return false;
1038 }
1039 }
1040
1041 if (LocVT == MVT::v1i64 ||
1042 LocVT == MVT::v2i32 ||
1043 LocVT == MVT::v4i16 ||
1044 LocVT == MVT::v8i8 ||
1045 LocVT == MVT::v1f64 ||
1046 LocVT == MVT::v2f32 ||
1047 LocVT == MVT::v4f16 ||
1048 LocVT == MVT::v4bf16) {
1049 static const MCPhysReg RegList12[] = {
1050 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
1051 };
1052 if (MCRegister Reg = State.AllocateReg(Regs: RegList12)) {
1053 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1054 return false;
1055 }
1056 }
1057
1058 if (LocVT == MVT::v2i64 ||
1059 LocVT == MVT::v4i32 ||
1060 LocVT == MVT::v8i16 ||
1061 LocVT == MVT::v16i8 ||
1062 LocVT == MVT::v4f32 ||
1063 LocVT == MVT::v2f64 ||
1064 LocVT == MVT::v8f16 ||
1065 LocVT == MVT::v8bf16) {
1066 static const MCPhysReg RegList13[] = {
1067 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
1068 };
1069 if (MCRegister Reg = State.AllocateReg(Regs: RegList13)) {
1070 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1071 return false;
1072 }
1073 }
1074
1075 if (ValVT == MVT::i1 || ValVT == MVT::i8) {
1076 int64_t Offset14 = State.AllocateStack(Size: 1, Alignment: Align(1));
1077 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset14, LocVT, HTP: LocInfo));
1078 return false;
1079 }
1080
1081 if (ValVT == MVT::i16 || ValVT == MVT::f16 || ValVT == MVT::bf16) {
1082 int64_t Offset15 = State.AllocateStack(Size: 2, Alignment: Align(2));
1083 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset15, LocVT, HTP: LocInfo));
1084 return false;
1085 }
1086
1087 if (LocVT == MVT::i32 ||
1088 LocVT == MVT::f32) {
1089 int64_t Offset16 = State.AllocateStack(Size: 4, Alignment: Align(4));
1090 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset16, LocVT, HTP: LocInfo));
1091 return false;
1092 }
1093
1094 if (ArgFlags.isPointer()) {
1095 if (State.getMachineFunction().getDataLayout().getPointerSize() == 4) {
1096 LocVT = MVT::i32;
1097 LocInfo = CCValAssign::Trunc;
1098 }
1099 }
1100
1101 if (ArgFlags.isPointer()) {
1102 if (State.getMachineFunction().getDataLayout().getPointerSize() == 4) {
1103 int64_t Offset17 = State.AllocateStack(Size: 4, Alignment: Align(4));
1104 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset17, LocVT, HTP: LocInfo));
1105 return false;
1106 }
1107 }
1108
1109 if (LocVT == MVT::i64 ||
1110 LocVT == MVT::f64 ||
1111 LocVT == MVT::v1f64 ||
1112 LocVT == MVT::v2f32 ||
1113 LocVT == MVT::v1i64 ||
1114 LocVT == MVT::v2i32 ||
1115 LocVT == MVT::v4i16 ||
1116 LocVT == MVT::v8i8 ||
1117 LocVT == MVT::v4f16 ||
1118 LocVT == MVT::v4bf16) {
1119 int64_t Offset18 = State.AllocateStack(Size: 8, Alignment: Align(8));
1120 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset18, LocVT, HTP: LocInfo));
1121 return false;
1122 }
1123
1124 if (LocVT == MVT::v2i64 ||
1125 LocVT == MVT::v4i32 ||
1126 LocVT == MVT::v8i16 ||
1127 LocVT == MVT::v16i8 ||
1128 LocVT == MVT::v4f32 ||
1129 LocVT == MVT::v2f64 ||
1130 LocVT == MVT::v8f16 ||
1131 LocVT == MVT::v8bf16) {
1132 int64_t Offset19 = State.AllocateStack(Size: 16, Alignment: Align(16));
1133 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset19, LocVT, HTP: LocInfo));
1134 return false;
1135 }
1136
1137 return true; // CC didn't match.
1138}
1139
1140
1141bool llvm::CC_AArch64_DarwinPCS_ILP32_VarArg(unsigned ValNo, MVT ValVT,
1142 MVT LocVT, CCValAssign::LocInfo LocInfo,
1143 ISD::ArgFlagsTy ArgFlags, CCState &State) {
1144
1145 if (ArgFlags.isNest()) {
1146 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X15)) {
1147 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1148 return false;
1149 }
1150 }
1151
1152 if (LocVT == MVT::v2f32) {
1153 LocVT = MVT::v2i32;
1154 LocInfo = CCValAssign::BCvt;
1155 }
1156
1157 if (LocVT == MVT::v2f64 ||
1158 LocVT == MVT::v4f32 ||
1159 LocVT == MVT::f128) {
1160 LocVT = MVT::v2i64;
1161 LocInfo = CCValAssign::BCvt;
1162 }
1163
1164 if (LocVT == MVT::i8 ||
1165 LocVT == MVT::i16) {
1166 LocVT = MVT::i32;
1167 if (ArgFlags.isSExt())
1168 LocInfo = CCValAssign::SExt;
1169 else if (ArgFlags.isZExt())
1170 LocInfo = CCValAssign::ZExt;
1171 else
1172 LocInfo = CCValAssign::AExt;
1173 }
1174
1175 if (LocVT == MVT::f16 ||
1176 LocVT == MVT::bf16) {
1177 LocVT = MVT::f32;
1178 LocInfo = CCValAssign::FPExt;
1179 }
1180
1181 if (ArgFlags.isPointer()) {
1182 if (State.getMachineFunction().getDataLayout().getPointerSize() == 4) {
1183 LocVT = MVT::i32;
1184 LocInfo = CCValAssign::Trunc;
1185 }
1186 }
1187
1188 if (LocVT == MVT::i32 ||
1189 LocVT == MVT::f32) {
1190 int64_t Offset1 = State.AllocateStack(Size: 4, Alignment: Align(4));
1191 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset1, LocVT, HTP: LocInfo));
1192 return false;
1193 }
1194
1195 if (LocVT == MVT::i64) {
1196 if (ArgFlags.isSplit()) {
1197 int64_t Offset2 = State.AllocateStack(Size: 8, Alignment: Align(16));
1198 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset2, LocVT, HTP: LocInfo));
1199 return false;
1200 }
1201 }
1202
1203 if (LocVT == MVT::i64 ||
1204 LocVT == MVT::f64 ||
1205 LocVT == MVT::v1i64 ||
1206 LocVT == MVT::v2i32 ||
1207 LocVT == MVT::v4i16 ||
1208 LocVT == MVT::v8i8 ||
1209 LocVT == MVT::v1f64 ||
1210 LocVT == MVT::v2f32 ||
1211 LocVT == MVT::v4f16 ||
1212 LocVT == MVT::v4bf16) {
1213 int64_t Offset3 = State.AllocateStack(Size: 8, Alignment: Align(8));
1214 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset3, LocVT, HTP: LocInfo));
1215 return false;
1216 }
1217
1218 if (LocVT == MVT::v2i64 ||
1219 LocVT == MVT::v4i32 ||
1220 LocVT == MVT::v8i16 ||
1221 LocVT == MVT::v16i8 ||
1222 LocVT == MVT::v4f32 ||
1223 LocVT == MVT::v2f64 ||
1224 LocVT == MVT::v8f16 ||
1225 LocVT == MVT::v8bf16) {
1226 int64_t Offset4 = State.AllocateStack(Size: 16, Alignment: Align(16));
1227 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset4, LocVT, HTP: LocInfo));
1228 return false;
1229 }
1230
1231 return true; // CC didn't match.
1232}
1233
1234
1235bool llvm::CC_AArch64_DarwinPCS_VarArg(unsigned ValNo, MVT ValVT,
1236 MVT LocVT, CCValAssign::LocInfo LocInfo,
1237 ISD::ArgFlagsTy ArgFlags, CCState &State) {
1238
1239 if (ArgFlags.isNest()) {
1240 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X15)) {
1241 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1242 return false;
1243 }
1244 }
1245
1246 if (LocVT == MVT::iPTR) {
1247 LocVT = MVT::i64;
1248 LocInfo = CCValAssign::BCvt;
1249 }
1250
1251 if (LocVT == MVT::v2f32) {
1252 LocVT = MVT::v2i32;
1253 LocInfo = CCValAssign::BCvt;
1254 }
1255
1256 if (LocVT == MVT::v2f64 ||
1257 LocVT == MVT::v4f32 ||
1258 LocVT == MVT::f128) {
1259 LocVT = MVT::v2i64;
1260 LocInfo = CCValAssign::BCvt;
1261 }
1262
1263 if (ArgFlags.isInConsecutiveRegs()) {
1264 if (CC_AArch64_Custom_Stack_Block(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1265 return false;
1266 }
1267
1268 if (LocVT == MVT::i8 ||
1269 LocVT == MVT::i16 ||
1270 LocVT == MVT::i32) {
1271 LocVT = MVT::i64;
1272 if (ArgFlags.isSExt())
1273 LocInfo = CCValAssign::SExt;
1274 else if (ArgFlags.isZExt())
1275 LocInfo = CCValAssign::ZExt;
1276 else
1277 LocInfo = CCValAssign::AExt;
1278 }
1279
1280 if (LocVT == MVT::f16 ||
1281 LocVT == MVT::bf16 ||
1282 LocVT == MVT::f32) {
1283 LocVT = MVT::f64;
1284 LocInfo = CCValAssign::FPExt;
1285 }
1286
1287 if (LocVT == MVT::i64) {
1288 if (ArgFlags.isSplit()) {
1289 int64_t Offset1 = State.AllocateStack(Size: 8, Alignment: Align(16));
1290 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset1, LocVT, HTP: LocInfo));
1291 return false;
1292 }
1293 }
1294
1295 if (LocVT == MVT::i64 ||
1296 LocVT == MVT::f64 ||
1297 LocVT == MVT::v1i64 ||
1298 LocVT == MVT::v2i32 ||
1299 LocVT == MVT::v4i16 ||
1300 LocVT == MVT::v8i8 ||
1301 LocVT == MVT::v1f64 ||
1302 LocVT == MVT::v2f32 ||
1303 LocVT == MVT::v4f16 ||
1304 LocVT == MVT::v4bf16) {
1305 int64_t Offset2 = State.AllocateStack(Size: 8, Alignment: Align(8));
1306 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset2, LocVT, HTP: LocInfo));
1307 return false;
1308 }
1309
1310 if (LocVT == MVT::v2i64 ||
1311 LocVT == MVT::v4i32 ||
1312 LocVT == MVT::v8i16 ||
1313 LocVT == MVT::v16i8 ||
1314 LocVT == MVT::v4f32 ||
1315 LocVT == MVT::v2f64 ||
1316 LocVT == MVT::v8f16 ||
1317 LocVT == MVT::v8bf16) {
1318 int64_t Offset3 = State.AllocateStack(Size: 16, Alignment: Align(16));
1319 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset3, LocVT, HTP: LocInfo));
1320 return false;
1321 }
1322
1323 return true; // CC didn't match.
1324}
1325
1326
1327bool llvm::CC_AArch64_GHC(unsigned ValNo, MVT ValVT,
1328 MVT LocVT, CCValAssign::LocInfo LocInfo,
1329 ISD::ArgFlagsTy ArgFlags, CCState &State) {
1330
1331 if (ArgFlags.isNest()) {
1332 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X15)) {
1333 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1334 return false;
1335 }
1336 }
1337
1338 if (LocVT == MVT::iPTR) {
1339 LocVT = MVT::i64;
1340 LocInfo = CCValAssign::BCvt;
1341 }
1342
1343 if (LocVT == MVT::v1i64 ||
1344 LocVT == MVT::v2i32 ||
1345 LocVT == MVT::v4i16 ||
1346 LocVT == MVT::v8i8 ||
1347 LocVT == MVT::v2f32) {
1348 LocVT = MVT::f64;
1349 LocInfo = CCValAssign::BCvt;
1350 }
1351
1352 if (LocVT == MVT::v2i64 ||
1353 LocVT == MVT::v4i32 ||
1354 LocVT == MVT::v8i16 ||
1355 LocVT == MVT::v16i8 ||
1356 LocVT == MVT::v4f32 ||
1357 LocVT == MVT::f128) {
1358 LocVT = MVT::v2f64;
1359 LocInfo = CCValAssign::BCvt;
1360 }
1361
1362 if (LocVT == MVT::v2f64) {
1363 static const MCPhysReg RegList1[] = {
1364 AArch64::Q4, AArch64::Q5
1365 };
1366 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
1367 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1368 return false;
1369 }
1370 }
1371
1372 if (LocVT == MVT::f32) {
1373 static const MCPhysReg RegList2[] = {
1374 AArch64::S8, AArch64::S9, AArch64::S10, AArch64::S11
1375 };
1376 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
1377 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1378 return false;
1379 }
1380 }
1381
1382 if (LocVT == MVT::f64) {
1383 static const MCPhysReg RegList3[] = {
1384 AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15
1385 };
1386 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
1387 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1388 return false;
1389 }
1390 }
1391
1392 if (LocVT == MVT::i8 ||
1393 LocVT == MVT::i16 ||
1394 LocVT == MVT::i32) {
1395 LocVT = MVT::i64;
1396 if (ArgFlags.isSExt())
1397 LocInfo = CCValAssign::SExt;
1398 else if (ArgFlags.isZExt())
1399 LocInfo = CCValAssign::ZExt;
1400 else
1401 LocInfo = CCValAssign::AExt;
1402 }
1403
1404 if (LocVT == MVT::i64) {
1405 static const MCPhysReg RegList4[] = {
1406 AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28
1407 };
1408 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
1409 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1410 return false;
1411 }
1412 }
1413
1414 return true; // CC didn't match.
1415}
1416
1417
1418bool llvm::CC_AArch64_Preserve_None(unsigned ValNo, MVT ValVT,
1419 MVT LocVT, CCValAssign::LocInfo LocInfo,
1420 ISD::ArgFlagsTy ArgFlags, CCState &State) {
1421
1422 if (State.isVarArg()) {
1423 if (State.getMachineFunction().getSubtarget<AArch64Subtarget>().isTargetDarwin()) {
1424 if (!CC_AArch64_DarwinPCS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1425 return false;
1426 }
1427 }
1428
1429 if (State.isVarArg()) {
1430 if (State.getMachineFunction().getSubtarget<AArch64Subtarget>().isTargetWindows()) {
1431 if (!CC_AArch64_Win64PCS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1432 return false;
1433 }
1434 }
1435
1436 if (State.isVarArg()) {
1437 if (!CC_AArch64_AAPCS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1438 return false;
1439 }
1440
1441 if (LocVT == MVT::i32) {
1442 static const MCPhysReg RegList1[] = {
1443 AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W9
1444 };
1445 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
1446 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1447 return false;
1448 }
1449 }
1450
1451 if (LocVT == MVT::i64) {
1452 static const MCPhysReg RegList2[] = {
1453 AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X9
1454 };
1455 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
1456 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1457 return false;
1458 }
1459 }
1460
1461 if (!State.getMachineFunction().getSubtarget<AArch64Subtarget>().isTargetWindows()) {
1462 if (LocVT == MVT::i32) {
1463 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::W15)) {
1464 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1465 return false;
1466 }
1467 }
1468 }
1469
1470 if (!State.getMachineFunction().getSubtarget<AArch64Subtarget>().isTargetWindows()) {
1471 if (LocVT == MVT::i64) {
1472 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X15)) {
1473 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1474 return false;
1475 }
1476 }
1477 }
1478
1479 if (!CC_AArch64_AAPCS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1480 return false;
1481
1482 return true; // CC didn't match.
1483}
1484
1485
1486bool llvm::CC_AArch64_Win64PCS(unsigned ValNo, MVT ValVT,
1487 MVT LocVT, CCValAssign::LocInfo LocInfo,
1488 ISD::ArgFlagsTy ArgFlags, CCState &State) {
1489
1490 if (ArgFlags.isNest()) {
1491 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X15)) {
1492 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1493 return false;
1494 }
1495 }
1496
1497 if (LocVT == MVT::iPTR) {
1498 LocVT = MVT::i64;
1499 LocInfo = CCValAssign::BCvt;
1500 }
1501
1502 if (LocVT == MVT::v2f32) {
1503 LocVT = MVT::v2i32;
1504 LocInfo = CCValAssign::BCvt;
1505 }
1506
1507 if (LocVT == MVT::v2f64 ||
1508 LocVT == MVT::v4f32) {
1509 LocVT = MVT::v2i64;
1510 LocInfo = CCValAssign::BCvt;
1511 }
1512
1513 if (State.getMachineFunction().getDataLayout().isBigEndian()) {
1514 if (LocVT == MVT::v2i32 ||
1515 LocVT == MVT::v2f32 ||
1516 LocVT == MVT::v4i16 ||
1517 LocVT == MVT::v4f16 ||
1518 LocVT == MVT::v4bf16 ||
1519 LocVT == MVT::v8i8) {
1520 LocVT = MVT::f64;
1521 LocInfo = CCValAssign::BCvt;
1522 }
1523 }
1524
1525 if (State.getMachineFunction().getDataLayout().isBigEndian()) {
1526 if (LocVT == MVT::v2i64 ||
1527 LocVT == MVT::v2f64 ||
1528 LocVT == MVT::v4i32 ||
1529 LocVT == MVT::v4f32 ||
1530 LocVT == MVT::v8i16 ||
1531 LocVT == MVT::v8f16 ||
1532 LocVT == MVT::v8bf16 ||
1533 LocVT == MVT::v16i8) {
1534 LocVT = MVT::f128;
1535 LocInfo = CCValAssign::BCvt;
1536 }
1537 }
1538
1539 if (ArgFlags.isInReg()) {
1540 if (LocVT == MVT::i64) {
1541 if (ArgFlags.isSRet()) {
1542 if (LocVT == MVT::i64) {
1543 static const MCPhysReg RegList1[] = {
1544 AArch64::X0, AArch64::X1
1545 };
1546 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
1547 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1548 return false;
1549 }
1550 }
1551 }
1552 }
1553 }
1554
1555 if (ArgFlags.isSRet()) {
1556 if (LocVT == MVT::i64) {
1557 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X8)) {
1558 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1559 return false;
1560 }
1561 }
1562 }
1563
1564 if (ArgFlags.isByVal()) {
1565 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 8, MinAlign: Align(8), ArgFlags);
1566 return false;
1567 }
1568
1569 if (ArgFlags.isSwiftSelf()) {
1570 if (LocVT == MVT::i64) {
1571 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X20)) {
1572 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1573 return false;
1574 }
1575 }
1576 }
1577
1578 if (ArgFlags.isSwiftError()) {
1579 if (LocVT == MVT::i64) {
1580 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X21)) {
1581 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1582 return false;
1583 }
1584 }
1585 }
1586
1587 if (ArgFlags.isSwiftAsync()) {
1588 if (LocVT == MVT::i64) {
1589 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X22)) {
1590 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1591 return false;
1592 }
1593 }
1594 }
1595
1596 if (ArgFlags.isInConsecutiveRegs()) {
1597 if (CC_AArch64_Custom_Block(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1598 return false;
1599 }
1600
1601 if (LocVT == MVT::nxv16i8 ||
1602 LocVT == MVT::nxv8i16 ||
1603 LocVT == MVT::nxv4i32 ||
1604 LocVT == MVT::nxv2i64 ||
1605 LocVT == MVT::nxv2f16 ||
1606 LocVT == MVT::nxv4f16 ||
1607 LocVT == MVT::nxv8f16 ||
1608 LocVT == MVT::nxv2bf16 ||
1609 LocVT == MVT::nxv4bf16 ||
1610 LocVT == MVT::nxv8bf16 ||
1611 LocVT == MVT::nxv2f32 ||
1612 LocVT == MVT::nxv4f32 ||
1613 LocVT == MVT::nxv2f64) {
1614 static const MCPhysReg RegList2[] = {
1615 AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7
1616 };
1617 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
1618 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1619 return false;
1620 }
1621 }
1622
1623 if (LocVT == MVT::nxv16i8 ||
1624 LocVT == MVT::nxv8i16 ||
1625 LocVT == MVT::nxv4i32 ||
1626 LocVT == MVT::nxv2i64 ||
1627 LocVT == MVT::nxv2f16 ||
1628 LocVT == MVT::nxv4f16 ||
1629 LocVT == MVT::nxv8f16 ||
1630 LocVT == MVT::nxv2bf16 ||
1631 LocVT == MVT::nxv4bf16 ||
1632 LocVT == MVT::nxv8bf16 ||
1633 LocVT == MVT::nxv2f32 ||
1634 LocVT == MVT::nxv4f32 ||
1635 LocVT == MVT::nxv2f64) {
1636 LocVT = MVT::i64;
1637 LocInfo = CCValAssign::Indirect;
1638 }
1639
1640 if (LocVT == MVT::nxv1i1 ||
1641 LocVT == MVT::nxv2i1 ||
1642 LocVT == MVT::nxv4i1 ||
1643 LocVT == MVT::nxv8i1 ||
1644 LocVT == MVT::nxv16i1 ||
1645 LocVT == MVT::aarch64svcount) {
1646 static const MCPhysReg RegList3[] = {
1647 AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3
1648 };
1649 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
1650 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1651 return false;
1652 }
1653 }
1654
1655 if (LocVT == MVT::nxv1i1 ||
1656 LocVT == MVT::nxv2i1 ||
1657 LocVT == MVT::nxv4i1 ||
1658 LocVT == MVT::nxv8i1 ||
1659 LocVT == MVT::nxv16i1 ||
1660 LocVT == MVT::aarch64svcount) {
1661 LocVT = MVT::i64;
1662 LocInfo = CCValAssign::Indirect;
1663 }
1664
1665 if (LocVT == MVT::i1 ||
1666 LocVT == MVT::i8 ||
1667 LocVT == MVT::i16) {
1668 LocVT = MVT::i32;
1669 if (ArgFlags.isSExt())
1670 LocInfo = CCValAssign::SExt;
1671 else if (ArgFlags.isZExt())
1672 LocInfo = CCValAssign::ZExt;
1673 else
1674 LocInfo = CCValAssign::AExt;
1675 }
1676
1677 if (LocVT == MVT::i32) {
1678 static const MCPhysReg RegList4[] = {
1679 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
1680 };
1681 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
1682 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1683 return false;
1684 }
1685 }
1686
1687 if (LocVT == MVT::i64) {
1688 if (ArgFlags.isSplit()) {
1689 static const MCPhysReg RegList5[] = {
1690 AArch64::X0, AArch64::X2, AArch64::X4, AArch64::X6
1691 };
1692 static const MCPhysReg RegList6[] = {
1693 AArch64::X0, AArch64::X1, AArch64::X3, AArch64::X5
1694 };
1695 if (MCRegister Reg = State.AllocateReg(Regs: RegList5, ShadowRegs: RegList6)) {
1696 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1697 return false;
1698 }
1699 }
1700 }
1701
1702 if (LocVT == MVT::i64) {
1703 if (ArgFlags.isSplit()) {
1704 static const MCPhysReg ShadowRegList7[] = {
1705 AArch64::X7
1706 };
1707 int64_t Offset8 = State.AllocateStack(Size: 8, Alignment: Align(16), ShadowRegs: ShadowRegList7);
1708 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset8, LocVT, HTP: LocInfo));
1709 return false;
1710 }
1711 }
1712
1713 if (LocVT == MVT::i64) {
1714 static const MCPhysReg RegList9[] = {
1715 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
1716 };
1717 if (MCRegister Reg = State.AllocateReg(Regs: RegList9)) {
1718 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1719 return false;
1720 }
1721 }
1722
1723 if (LocVT == MVT::f16) {
1724 static const MCPhysReg RegList10[] = {
1725 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
1726 };
1727 if (MCRegister Reg = State.AllocateReg(Regs: RegList10)) {
1728 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1729 return false;
1730 }
1731 }
1732
1733 if (LocVT == MVT::bf16) {
1734 static const MCPhysReg RegList11[] = {
1735 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
1736 };
1737 if (MCRegister Reg = State.AllocateReg(Regs: RegList11)) {
1738 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1739 return false;
1740 }
1741 }
1742
1743 if (LocVT == MVT::f32) {
1744 static const MCPhysReg RegList12[] = {
1745 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7
1746 };
1747 if (MCRegister Reg = State.AllocateReg(Regs: RegList12)) {
1748 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1749 return false;
1750 }
1751 }
1752
1753 if (LocVT == MVT::f64) {
1754 static const MCPhysReg RegList13[] = {
1755 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
1756 };
1757 if (MCRegister Reg = State.AllocateReg(Regs: RegList13)) {
1758 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1759 return false;
1760 }
1761 }
1762
1763 if (LocVT == MVT::v1i64 ||
1764 LocVT == MVT::v2i32 ||
1765 LocVT == MVT::v4i16 ||
1766 LocVT == MVT::v8i8 ||
1767 LocVT == MVT::v1f64 ||
1768 LocVT == MVT::v2f32 ||
1769 LocVT == MVT::v4f16 ||
1770 LocVT == MVT::v4bf16) {
1771 static const MCPhysReg RegList14[] = {
1772 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
1773 };
1774 if (MCRegister Reg = State.AllocateReg(Regs: RegList14)) {
1775 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1776 return false;
1777 }
1778 }
1779
1780 if (LocVT == MVT::f128 ||
1781 LocVT == MVT::v2i64 ||
1782 LocVT == MVT::v4i32 ||
1783 LocVT == MVT::v8i16 ||
1784 LocVT == MVT::v16i8 ||
1785 LocVT == MVT::v4f32 ||
1786 LocVT == MVT::v2f64 ||
1787 LocVT == MVT::v8f16 ||
1788 LocVT == MVT::v8bf16) {
1789 static const MCPhysReg RegList15[] = {
1790 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
1791 };
1792 if (MCRegister Reg = State.AllocateReg(Regs: RegList15)) {
1793 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1794 return false;
1795 }
1796 }
1797
1798 if (LocVT == MVT::i1 ||
1799 LocVT == MVT::i8 ||
1800 LocVT == MVT::i16 ||
1801 LocVT == MVT::f16 ||
1802 LocVT == MVT::bf16) {
1803 int64_t Offset16 = State.AllocateStack(Size: 8, Alignment: Align(8));
1804 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset16, LocVT, HTP: LocInfo));
1805 return false;
1806 }
1807
1808 if (LocVT == MVT::i32 ||
1809 LocVT == MVT::f32) {
1810 int64_t Offset17 = State.AllocateStack(Size: 8, Alignment: Align(8));
1811 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset17, LocVT, HTP: LocInfo));
1812 return false;
1813 }
1814
1815 if (LocVT == MVT::i64 ||
1816 LocVT == MVT::f64 ||
1817 LocVT == MVT::v1f64 ||
1818 LocVT == MVT::v2f32 ||
1819 LocVT == MVT::v1i64 ||
1820 LocVT == MVT::v2i32 ||
1821 LocVT == MVT::v4i16 ||
1822 LocVT == MVT::v8i8 ||
1823 LocVT == MVT::v4f16 ||
1824 LocVT == MVT::v4bf16) {
1825 int64_t Offset18 = State.AllocateStack(Size: 8, Alignment: Align(8));
1826 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset18, LocVT, HTP: LocInfo));
1827 return false;
1828 }
1829
1830 if (LocVT == MVT::f128 ||
1831 LocVT == MVT::v2i64 ||
1832 LocVT == MVT::v4i32 ||
1833 LocVT == MVT::v8i16 ||
1834 LocVT == MVT::v16i8 ||
1835 LocVT == MVT::v4f32 ||
1836 LocVT == MVT::v2f64 ||
1837 LocVT == MVT::v8f16 ||
1838 LocVT == MVT::v8bf16) {
1839 int64_t Offset19 = State.AllocateStack(Size: 16, Alignment: Align(16));
1840 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset19, LocVT, HTP: LocInfo));
1841 return false;
1842 }
1843
1844 return true; // CC didn't match.
1845}
1846
1847
1848bool llvm::CC_AArch64_Win64_CFGuard_Check(unsigned ValNo, MVT ValVT,
1849 MVT LocVT, CCValAssign::LocInfo LocInfo,
1850 ISD::ArgFlagsTy ArgFlags, CCState &State) {
1851
1852 if (LocVT == MVT::i64) {
1853 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X15)) {
1854 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1855 return false;
1856 }
1857 }
1858
1859 return true; // CC didn't match.
1860}
1861
1862
1863bool llvm::CC_AArch64_Win64_VarArg(unsigned ValNo, MVT ValVT,
1864 MVT LocVT, CCValAssign::LocInfo LocInfo,
1865 ISD::ArgFlagsTy ArgFlags, CCState &State) {
1866
1867 if (LocVT == MVT::f16 ||
1868 LocVT == MVT::bf16) {
1869 LocVT = MVT::i16;
1870 LocInfo = CCValAssign::BCvt;
1871 }
1872
1873 if (LocVT == MVT::f32) {
1874 LocVT = MVT::i32;
1875 LocInfo = CCValAssign::BCvt;
1876 }
1877
1878 if (LocVT == MVT::f64) {
1879 LocVT = MVT::i64;
1880 LocInfo = CCValAssign::BCvt;
1881 }
1882
1883 if (!CC_AArch64_Win64PCS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1884 return false;
1885
1886 return true; // CC didn't match.
1887}
1888
1889
1890bool llvm::RetCC_AArch64_AAPCS(unsigned ValNo, MVT ValVT,
1891 MVT LocVT, CCValAssign::LocInfo LocInfo,
1892 ISD::ArgFlagsTy ArgFlags, CCState &State) {
1893
1894 if (LocVT == MVT::iPTR) {
1895 LocVT = MVT::i64;
1896 LocInfo = CCValAssign::BCvt;
1897 }
1898
1899 if (LocVT == MVT::v2f32) {
1900 LocVT = MVT::v2i32;
1901 LocInfo = CCValAssign::BCvt;
1902 }
1903
1904 if (LocVT == MVT::v2f64 ||
1905 LocVT == MVT::v4f32) {
1906 LocVT = MVT::v2i64;
1907 LocInfo = CCValAssign::BCvt;
1908 }
1909
1910 if (ArgFlags.isInConsecutiveRegs()) {
1911 if (CC_AArch64_Custom_Block(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1912 return false;
1913 }
1914
1915 if (ArgFlags.isSwiftError()) {
1916 if (LocVT == MVT::i64) {
1917 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X21)) {
1918 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1919 return false;
1920 }
1921 }
1922 }
1923
1924 if (State.getMachineFunction().getDataLayout().isBigEndian()) {
1925 if (LocVT == MVT::v2i32 ||
1926 LocVT == MVT::v2f32 ||
1927 LocVT == MVT::v4i16 ||
1928 LocVT == MVT::v4f16 ||
1929 LocVT == MVT::v4bf16 ||
1930 LocVT == MVT::v8i8) {
1931 LocVT = MVT::f64;
1932 LocInfo = CCValAssign::BCvt;
1933 }
1934 }
1935
1936 if (State.getMachineFunction().getDataLayout().isBigEndian()) {
1937 if (LocVT == MVT::v2i64 ||
1938 LocVT == MVT::v2f64 ||
1939 LocVT == MVT::v4i32 ||
1940 LocVT == MVT::v4f32 ||
1941 LocVT == MVT::v8i16 ||
1942 LocVT == MVT::v8f16 ||
1943 LocVT == MVT::v8bf16 ||
1944 LocVT == MVT::v16i8) {
1945 LocVT = MVT::f128;
1946 LocInfo = CCValAssign::BCvt;
1947 }
1948 }
1949
1950 if (LocVT == MVT::i1 ||
1951 LocVT == MVT::i8 ||
1952 LocVT == MVT::i16) {
1953 LocVT = MVT::i32;
1954 if (ArgFlags.isSExt())
1955 LocInfo = CCValAssign::SExt;
1956 else if (ArgFlags.isZExt())
1957 LocInfo = CCValAssign::ZExt;
1958 else
1959 LocInfo = CCValAssign::AExt;
1960 }
1961
1962 if (LocVT == MVT::i32) {
1963 static const MCPhysReg RegList1[] = {
1964 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
1965 };
1966 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
1967 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1968 return false;
1969 }
1970 }
1971
1972 if (LocVT == MVT::i64) {
1973 static const MCPhysReg RegList2[] = {
1974 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
1975 };
1976 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
1977 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1978 return false;
1979 }
1980 }
1981
1982 if (LocVT == MVT::f16) {
1983 static const MCPhysReg RegList3[] = {
1984 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
1985 };
1986 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
1987 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1988 return false;
1989 }
1990 }
1991
1992 if (LocVT == MVT::bf16) {
1993 static const MCPhysReg RegList4[] = {
1994 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
1995 };
1996 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
1997 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1998 return false;
1999 }
2000 }
2001
2002 if (LocVT == MVT::f32) {
2003 static const MCPhysReg RegList5[] = {
2004 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7
2005 };
2006 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
2007 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2008 return false;
2009 }
2010 }
2011
2012 if (LocVT == MVT::f64) {
2013 static const MCPhysReg RegList6[] = {
2014 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
2015 };
2016 if (MCRegister Reg = State.AllocateReg(Regs: RegList6)) {
2017 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2018 return false;
2019 }
2020 }
2021
2022 if (LocVT == MVT::v1i64 ||
2023 LocVT == MVT::v2i32 ||
2024 LocVT == MVT::v4i16 ||
2025 LocVT == MVT::v8i8 ||
2026 LocVT == MVT::v1f64 ||
2027 LocVT == MVT::v2f32 ||
2028 LocVT == MVT::v4f16 ||
2029 LocVT == MVT::v4bf16) {
2030 static const MCPhysReg RegList7[] = {
2031 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
2032 };
2033 if (MCRegister Reg = State.AllocateReg(Regs: RegList7)) {
2034 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2035 return false;
2036 }
2037 }
2038
2039 if (LocVT == MVT::f128 ||
2040 LocVT == MVT::v2i64 ||
2041 LocVT == MVT::v4i32 ||
2042 LocVT == MVT::v8i16 ||
2043 LocVT == MVT::v16i8 ||
2044 LocVT == MVT::v4f32 ||
2045 LocVT == MVT::v2f64 ||
2046 LocVT == MVT::v8f16 ||
2047 LocVT == MVT::v8bf16) {
2048 static const MCPhysReg RegList8[] = {
2049 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
2050 };
2051 if (MCRegister Reg = State.AllocateReg(Regs: RegList8)) {
2052 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2053 return false;
2054 }
2055 }
2056
2057 if (LocVT == MVT::nxv16i8 ||
2058 LocVT == MVT::nxv8i16 ||
2059 LocVT == MVT::nxv4i32 ||
2060 LocVT == MVT::nxv2i64 ||
2061 LocVT == MVT::nxv2f16 ||
2062 LocVT == MVT::nxv4f16 ||
2063 LocVT == MVT::nxv8f16 ||
2064 LocVT == MVT::nxv2bf16 ||
2065 LocVT == MVT::nxv4bf16 ||
2066 LocVT == MVT::nxv8bf16 ||
2067 LocVT == MVT::nxv2f32 ||
2068 LocVT == MVT::nxv4f32 ||
2069 LocVT == MVT::nxv2f64) {
2070 static const MCPhysReg RegList9[] = {
2071 AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7
2072 };
2073 if (MCRegister Reg = State.AllocateReg(Regs: RegList9)) {
2074 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2075 return false;
2076 }
2077 }
2078
2079 if (LocVT == MVT::nxv1i1 ||
2080 LocVT == MVT::nxv2i1 ||
2081 LocVT == MVT::nxv4i1 ||
2082 LocVT == MVT::nxv8i1 ||
2083 LocVT == MVT::nxv16i1 ||
2084 LocVT == MVT::aarch64svcount) {
2085 static const MCPhysReg RegList10[] = {
2086 AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3
2087 };
2088 if (MCRegister Reg = State.AllocateReg(Regs: RegList10)) {
2089 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2090 return false;
2091 }
2092 }
2093
2094 return true; // CC didn't match.
2095}
2096
2097
2098bool llvm::RetCC_AArch64_Arm64EC_CFGuard_Check(unsigned ValNo, MVT ValVT,
2099 MVT LocVT, CCValAssign::LocInfo LocInfo,
2100 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2101
2102 if (LocVT == MVT::i64) {
2103 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X11)) {
2104 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2105 return false;
2106 }
2107 }
2108
2109 return true; // CC didn't match.
2110}
2111
2112
2113bool llvm::RetCC_AArch64_Arm64EC_Thunk(unsigned ValNo, MVT ValVT,
2114 MVT LocVT, CCValAssign::LocInfo LocInfo,
2115 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2116
2117 if (LocVT == MVT::x86mmx) {
2118 LocVT = MVT::i64;
2119 LocInfo = CCValAssign::BCvt;
2120 }
2121
2122 if (LocVT == MVT::f16) {
2123 static const MCPhysReg RegList1[] = {
2124 AArch64::H0, AArch64::H1
2125 };
2126 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
2127 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2128 return false;
2129 }
2130 }
2131
2132 if (LocVT == MVT::f32) {
2133 static const MCPhysReg RegList2[] = {
2134 AArch64::S0, AArch64::S1
2135 };
2136 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
2137 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2138 return false;
2139 }
2140 }
2141
2142 if (LocVT == MVT::f64) {
2143 static const MCPhysReg RegList3[] = {
2144 AArch64::D0, AArch64::D1
2145 };
2146 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
2147 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2148 return false;
2149 }
2150 }
2151
2152 if (LocVT == MVT::f128) {
2153 static const MCPhysReg RegList4[] = {
2154 AArch64::Q0, AArch64::Q1
2155 };
2156 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
2157 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2158 return false;
2159 }
2160 }
2161
2162 if (ArgFlags.isSwiftError()) {
2163 if (LocVT == MVT::i64) {
2164 if (MCRegister Reg = State.AllocateReg(Reg: AArch64::X19)) {
2165 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2166 return false;
2167 }
2168 }
2169 }
2170
2171 if (LocVT == MVT::i1 ||
2172 LocVT == MVT::i8 ||
2173 LocVT == MVT::i16) {
2174 LocVT = MVT::i32;
2175 if (ArgFlags.isSExt())
2176 LocInfo = CCValAssign::SExt;
2177 else if (ArgFlags.isZExt())
2178 LocInfo = CCValAssign::ZExt;
2179 else
2180 LocInfo = CCValAssign::AExt;
2181 }
2182
2183 if (LocVT == MVT::i32) {
2184 static const MCPhysReg RegList5[] = {
2185 AArch64::W8, AArch64::W1, AArch64::W0
2186 };
2187 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
2188 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2189 return false;
2190 }
2191 }
2192
2193 if (LocVT == MVT::i64) {
2194 static const MCPhysReg RegList6[] = {
2195 AArch64::X8, AArch64::X1, AArch64::X0
2196 };
2197 if (MCRegister Reg = State.AllocateReg(Regs: RegList6)) {
2198 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2199 return false;
2200 }
2201 }
2202
2203 if (LocVT == MVT::v16i8 ||
2204 LocVT == MVT::v8i16 ||
2205 LocVT == MVT::v4i32 ||
2206 LocVT == MVT::v2i64 ||
2207 LocVT == MVT::v8f16 ||
2208 LocVT == MVT::v4f32 ||
2209 LocVT == MVT::v2f64) {
2210 static const MCPhysReg RegList7[] = {
2211 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3
2212 };
2213 if (MCRegister Reg = State.AllocateReg(Regs: RegList7)) {
2214 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2215 return false;
2216 }
2217 }
2218
2219 return true; // CC didn't match.
2220}
2221
2222#else
2223
2224const MCRegister CC_AArch64_AAPCS_ArgRegs[] = { AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7, AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7, AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::X0, AArch64::X1, AArch64::X15, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7 };
2225const MCRegister CC_AArch64_Arm64EC_CFGuard_Check_ArgRegs[] = { AArch64::X10, AArch64::X11, AArch64::X9 };
2226const MCRegister CC_AArch64_Arm64EC_Thunk_ArgRegs[] = { AArch64::X4, AArch64::X8, AArch64::X9 };
2227const MCRegister CC_AArch64_Arm64EC_Thunk_Native_ArgRegs[] = { AArch64::X9 };
2228const MCRegister CC_AArch64_Arm64EC_VarArg_ArgRegs[] = { AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::X0, AArch64::X1, AArch64::X15, AArch64::X2, AArch64::X3, AArch64::X8 };
2229const MCRegister CC_AArch64_DarwinPCS_ArgRegs[] = { AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7, AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7, AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::X0, AArch64::X1, AArch64::X15, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7 };
2230const MCRegister CC_AArch64_DarwinPCS_ILP32_VarArg_ArgRegs[] = { AArch64::X15 };
2231const MCRegister CC_AArch64_DarwinPCS_VarArg_ArgRegs[] = { AArch64::X15 };
2232const MCRegister CC_AArch64_GHC_ArgRegs[] = { AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::Q4, AArch64::Q5, AArch64::S10, AArch64::S11, AArch64::S8, AArch64::S9, AArch64::X15, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28 };
2233const MCRegister CC_AArch64_Preserve_None_ArgRegs[] = { AArch64::W0, AArch64::W1, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W2, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W9, AArch64::X0, AArch64::X1, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X2, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X9 };
2234const MCRegister CC_AArch64_Win64PCS_ArgRegs[] = { AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7, AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7, AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::X0, AArch64::X1, AArch64::X15, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7 };
2235const MCRegister CC_AArch64_Win64_CFGuard_Check_ArgRegs[] = { AArch64::X15 };
2236const MCRegister CC_AArch64_Win64_VarArg_ArgRegs[] = { 0 };
2237const MCRegister RetCC_AArch64_AAPCS_ArgRegs[] = { AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7, AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7, AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7 };
2238const MCRegister RetCC_AArch64_Arm64EC_CFGuard_Check_ArgRegs[] = { AArch64::X11 };
2239const MCRegister RetCC_AArch64_Arm64EC_Thunk_ArgRegs[] = { AArch64::D0, AArch64::D1, AArch64::H0, AArch64::H1, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::S0, AArch64::S1, AArch64::W0, AArch64::W1, AArch64::W8, AArch64::X0, AArch64::X1, AArch64::X8 };
2240
2241// Registers used by Swift.
2242const MCRegister CC_AArch64_AAPCS_Swift_ArgRegs[] = { AArch64::X20, AArch64::X21, AArch64::X22 };
2243const MCRegister CC_AArch64_Arm64EC_Thunk_Swift_ArgRegs[] = { AArch64::X19, AArch64::X20, AArch64::X21 };
2244const MCRegister CC_AArch64_DarwinPCS_Swift_ArgRegs[] = { AArch64::X20, AArch64::X21, AArch64::X22 };
2245const MCRegister CC_AArch64_Win64PCS_Swift_ArgRegs[] = { AArch64::X20, AArch64::X21, AArch64::X22 };
2246const MCRegister RetCC_AArch64_AAPCS_Swift_ArgRegs[] = { AArch64::X21 };
2247const MCRegister RetCC_AArch64_Arm64EC_Thunk_Swift_ArgRegs[] = { AArch64::X19 };
2248
2249#endif // CC_REGISTER_LIST
2250