1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11namespace llvm::R600 {
12 enum {
13 PHI = 0,
14 INLINEASM = 1,
15 INLINEASM_BR = 2,
16 CFI_INSTRUCTION = 3,
17 EH_LABEL = 4,
18 GC_LABEL = 5,
19 ANNOTATION_LABEL = 6,
20 KILL = 7,
21 EXTRACT_SUBREG = 8,
22 INSERT_SUBREG = 9,
23 IMPLICIT_DEF = 10,
24 INIT_UNDEF = 11,
25 SUBREG_TO_REG = 12,
26 COPY_TO_REGCLASS = 13,
27 DBG_VALUE = 14,
28 DBG_VALUE_LIST = 15,
29 DBG_INSTR_REF = 16,
30 DBG_PHI = 17,
31 DBG_LABEL = 18,
32 REG_SEQUENCE = 19,
33 COPY = 20,
34 BUNDLE = 21,
35 LIFETIME_START = 22,
36 LIFETIME_END = 23,
37 PSEUDO_PROBE = 24,
38 ARITH_FENCE = 25,
39 STACKMAP = 26,
40 FENTRY_CALL = 27,
41 PATCHPOINT = 28,
42 LOAD_STACK_GUARD = 29,
43 PREALLOCATED_SETUP = 30,
44 PREALLOCATED_ARG = 31,
45 STATEPOINT = 32,
46 LOCAL_ESCAPE = 33,
47 FAULTING_OP = 34,
48 PATCHABLE_OP = 35,
49 PATCHABLE_FUNCTION_ENTER = 36,
50 PATCHABLE_RET = 37,
51 PATCHABLE_FUNCTION_EXIT = 38,
52 PATCHABLE_TAIL_CALL = 39,
53 PATCHABLE_EVENT_CALL = 40,
54 PATCHABLE_TYPED_EVENT_CALL = 41,
55 ICALL_BRANCH_FUNNEL = 42,
56 FAKE_USE = 43,
57 MEMBARRIER = 44,
58 JUMP_TABLE_DEBUG_INFO = 45,
59 CONVERGENCECTRL_ENTRY = 46,
60 CONVERGENCECTRL_ANCHOR = 47,
61 CONVERGENCECTRL_LOOP = 48,
62 CONVERGENCECTRL_GLUE = 49,
63 G_ASSERT_SEXT = 50,
64 G_ASSERT_ZEXT = 51,
65 G_ASSERT_ALIGN = 52,
66 G_ADD = 53,
67 G_SUB = 54,
68 G_MUL = 55,
69 G_SDIV = 56,
70 G_UDIV = 57,
71 G_SREM = 58,
72 G_UREM = 59,
73 G_SDIVREM = 60,
74 G_UDIVREM = 61,
75 G_AND = 62,
76 G_OR = 63,
77 G_XOR = 64,
78 G_ABDS = 65,
79 G_ABDU = 66,
80 G_IMPLICIT_DEF = 67,
81 G_PHI = 68,
82 G_FRAME_INDEX = 69,
83 G_GLOBAL_VALUE = 70,
84 G_PTRAUTH_GLOBAL_VALUE = 71,
85 G_CONSTANT_POOL = 72,
86 G_EXTRACT = 73,
87 G_UNMERGE_VALUES = 74,
88 G_INSERT = 75,
89 G_MERGE_VALUES = 76,
90 G_BUILD_VECTOR = 77,
91 G_BUILD_VECTOR_TRUNC = 78,
92 G_CONCAT_VECTORS = 79,
93 G_PTRTOINT = 80,
94 G_INTTOPTR = 81,
95 G_BITCAST = 82,
96 G_FREEZE = 83,
97 G_CONSTANT_FOLD_BARRIER = 84,
98 G_INTRINSIC_FPTRUNC_ROUND = 85,
99 G_INTRINSIC_TRUNC = 86,
100 G_INTRINSIC_ROUND = 87,
101 G_INTRINSIC_LRINT = 88,
102 G_INTRINSIC_LLRINT = 89,
103 G_INTRINSIC_ROUNDEVEN = 90,
104 G_READCYCLECOUNTER = 91,
105 G_READSTEADYCOUNTER = 92,
106 G_LOAD = 93,
107 G_SEXTLOAD = 94,
108 G_ZEXTLOAD = 95,
109 G_INDEXED_LOAD = 96,
110 G_INDEXED_SEXTLOAD = 97,
111 G_INDEXED_ZEXTLOAD = 98,
112 G_STORE = 99,
113 G_INDEXED_STORE = 100,
114 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 101,
115 G_ATOMIC_CMPXCHG = 102,
116 G_ATOMICRMW_XCHG = 103,
117 G_ATOMICRMW_ADD = 104,
118 G_ATOMICRMW_SUB = 105,
119 G_ATOMICRMW_AND = 106,
120 G_ATOMICRMW_NAND = 107,
121 G_ATOMICRMW_OR = 108,
122 G_ATOMICRMW_XOR = 109,
123 G_ATOMICRMW_MAX = 110,
124 G_ATOMICRMW_MIN = 111,
125 G_ATOMICRMW_UMAX = 112,
126 G_ATOMICRMW_UMIN = 113,
127 G_ATOMICRMW_FADD = 114,
128 G_ATOMICRMW_FSUB = 115,
129 G_ATOMICRMW_FMAX = 116,
130 G_ATOMICRMW_FMIN = 117,
131 G_ATOMICRMW_FMAXIMUM = 118,
132 G_ATOMICRMW_FMINIMUM = 119,
133 G_ATOMICRMW_UINC_WRAP = 120,
134 G_ATOMICRMW_UDEC_WRAP = 121,
135 G_ATOMICRMW_USUB_COND = 122,
136 G_ATOMICRMW_USUB_SAT = 123,
137 G_FENCE = 124,
138 G_PREFETCH = 125,
139 G_BRCOND = 126,
140 G_BRINDIRECT = 127,
141 G_INVOKE_REGION_START = 128,
142 G_INTRINSIC = 129,
143 G_INTRINSIC_W_SIDE_EFFECTS = 130,
144 G_INTRINSIC_CONVERGENT = 131,
145 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 132,
146 G_ANYEXT = 133,
147 G_TRUNC = 134,
148 G_CONSTANT = 135,
149 G_FCONSTANT = 136,
150 G_VASTART = 137,
151 G_VAARG = 138,
152 G_SEXT = 139,
153 G_SEXT_INREG = 140,
154 G_ZEXT = 141,
155 G_SHL = 142,
156 G_LSHR = 143,
157 G_ASHR = 144,
158 G_FSHL = 145,
159 G_FSHR = 146,
160 G_ROTR = 147,
161 G_ROTL = 148,
162 G_ICMP = 149,
163 G_FCMP = 150,
164 G_SCMP = 151,
165 G_UCMP = 152,
166 G_SELECT = 153,
167 G_UADDO = 154,
168 G_UADDE = 155,
169 G_USUBO = 156,
170 G_USUBE = 157,
171 G_SADDO = 158,
172 G_SADDE = 159,
173 G_SSUBO = 160,
174 G_SSUBE = 161,
175 G_UMULO = 162,
176 G_SMULO = 163,
177 G_UMULH = 164,
178 G_SMULH = 165,
179 G_UADDSAT = 166,
180 G_SADDSAT = 167,
181 G_USUBSAT = 168,
182 G_SSUBSAT = 169,
183 G_USHLSAT = 170,
184 G_SSHLSAT = 171,
185 G_SMULFIX = 172,
186 G_UMULFIX = 173,
187 G_SMULFIXSAT = 174,
188 G_UMULFIXSAT = 175,
189 G_SDIVFIX = 176,
190 G_UDIVFIX = 177,
191 G_SDIVFIXSAT = 178,
192 G_UDIVFIXSAT = 179,
193 G_FADD = 180,
194 G_FSUB = 181,
195 G_FMUL = 182,
196 G_FMA = 183,
197 G_FMAD = 184,
198 G_FDIV = 185,
199 G_FREM = 186,
200 G_FPOW = 187,
201 G_FPOWI = 188,
202 G_FEXP = 189,
203 G_FEXP2 = 190,
204 G_FEXP10 = 191,
205 G_FLOG = 192,
206 G_FLOG2 = 193,
207 G_FLOG10 = 194,
208 G_FLDEXP = 195,
209 G_FFREXP = 196,
210 G_FNEG = 197,
211 G_FPEXT = 198,
212 G_FPTRUNC = 199,
213 G_FPTOSI = 200,
214 G_FPTOUI = 201,
215 G_SITOFP = 202,
216 G_UITOFP = 203,
217 G_FPTOSI_SAT = 204,
218 G_FPTOUI_SAT = 205,
219 G_FABS = 206,
220 G_FCOPYSIGN = 207,
221 G_IS_FPCLASS = 208,
222 G_FCANONICALIZE = 209,
223 G_FMINNUM = 210,
224 G_FMAXNUM = 211,
225 G_FMINNUM_IEEE = 212,
226 G_FMAXNUM_IEEE = 213,
227 G_FMINIMUM = 214,
228 G_FMAXIMUM = 215,
229 G_FMINIMUMNUM = 216,
230 G_FMAXIMUMNUM = 217,
231 G_GET_FPENV = 218,
232 G_SET_FPENV = 219,
233 G_RESET_FPENV = 220,
234 G_GET_FPMODE = 221,
235 G_SET_FPMODE = 222,
236 G_RESET_FPMODE = 223,
237 G_PTR_ADD = 224,
238 G_PTRMASK = 225,
239 G_SMIN = 226,
240 G_SMAX = 227,
241 G_UMIN = 228,
242 G_UMAX = 229,
243 G_ABS = 230,
244 G_LROUND = 231,
245 G_LLROUND = 232,
246 G_BR = 233,
247 G_BRJT = 234,
248 G_VSCALE = 235,
249 G_INSERT_SUBVECTOR = 236,
250 G_EXTRACT_SUBVECTOR = 237,
251 G_INSERT_VECTOR_ELT = 238,
252 G_EXTRACT_VECTOR_ELT = 239,
253 G_SHUFFLE_VECTOR = 240,
254 G_SPLAT_VECTOR = 241,
255 G_STEP_VECTOR = 242,
256 G_VECTOR_COMPRESS = 243,
257 G_CTTZ = 244,
258 G_CTTZ_ZERO_UNDEF = 245,
259 G_CTLZ = 246,
260 G_CTLZ_ZERO_UNDEF = 247,
261 G_CTPOP = 248,
262 G_BSWAP = 249,
263 G_BITREVERSE = 250,
264 G_FCEIL = 251,
265 G_FCOS = 252,
266 G_FSIN = 253,
267 G_FSINCOS = 254,
268 G_FTAN = 255,
269 G_FACOS = 256,
270 G_FASIN = 257,
271 G_FATAN = 258,
272 G_FATAN2 = 259,
273 G_FCOSH = 260,
274 G_FSINH = 261,
275 G_FTANH = 262,
276 G_FSQRT = 263,
277 G_FFLOOR = 264,
278 G_FRINT = 265,
279 G_FNEARBYINT = 266,
280 G_ADDRSPACE_CAST = 267,
281 G_BLOCK_ADDR = 268,
282 G_JUMP_TABLE = 269,
283 G_DYN_STACKALLOC = 270,
284 G_STACKSAVE = 271,
285 G_STACKRESTORE = 272,
286 G_STRICT_FADD = 273,
287 G_STRICT_FSUB = 274,
288 G_STRICT_FMUL = 275,
289 G_STRICT_FDIV = 276,
290 G_STRICT_FREM = 277,
291 G_STRICT_FMA = 278,
292 G_STRICT_FSQRT = 279,
293 G_STRICT_FLDEXP = 280,
294 G_READ_REGISTER = 281,
295 G_WRITE_REGISTER = 282,
296 G_MEMCPY = 283,
297 G_MEMCPY_INLINE = 284,
298 G_MEMMOVE = 285,
299 G_MEMSET = 286,
300 G_BZERO = 287,
301 G_TRAP = 288,
302 G_DEBUGTRAP = 289,
303 G_UBSANTRAP = 290,
304 G_VECREDUCE_SEQ_FADD = 291,
305 G_VECREDUCE_SEQ_FMUL = 292,
306 G_VECREDUCE_FADD = 293,
307 G_VECREDUCE_FMUL = 294,
308 G_VECREDUCE_FMAX = 295,
309 G_VECREDUCE_FMIN = 296,
310 G_VECREDUCE_FMAXIMUM = 297,
311 G_VECREDUCE_FMINIMUM = 298,
312 G_VECREDUCE_ADD = 299,
313 G_VECREDUCE_MUL = 300,
314 G_VECREDUCE_AND = 301,
315 G_VECREDUCE_OR = 302,
316 G_VECREDUCE_XOR = 303,
317 G_VECREDUCE_SMAX = 304,
318 G_VECREDUCE_SMIN = 305,
319 G_VECREDUCE_UMAX = 306,
320 G_VECREDUCE_UMIN = 307,
321 G_SBFX = 308,
322 G_UBFX = 309,
323 BRANCH = 310,
324 BRANCH_COND_f32 = 311,
325 BRANCH_COND_i32 = 312,
326 BREAK = 313,
327 BREAKC_f32 = 314,
328 BREAKC_i32 = 315,
329 BREAK_LOGICALNZ_f32 = 316,
330 BREAK_LOGICALNZ_i32 = 317,
331 BREAK_LOGICALZ_f32 = 318,
332 BREAK_LOGICALZ_i32 = 319,
333 CONST_COPY = 320,
334 CONTINUE = 321,
335 CONTINUEC_f32 = 322,
336 CONTINUEC_i32 = 323,
337 CONTINUE_LOGICALNZ_f32 = 324,
338 CONTINUE_LOGICALNZ_i32 = 325,
339 CONTINUE_LOGICALZ_f32 = 326,
340 CONTINUE_LOGICALZ_i32 = 327,
341 CUBE_eg_pseudo = 328,
342 CUBE_r600_pseudo = 329,
343 DEFAULT = 330,
344 DOT_4 = 331,
345 DUMMY_CHAIN = 332,
346 ELSE = 333,
347 END = 334,
348 ENDFUNC = 335,
349 ENDIF = 336,
350 ENDLOOP = 337,
351 ENDMAIN = 338,
352 ENDSWITCH = 339,
353 FABS_R600 = 340,
354 FNEG_R600 = 341,
355 FUNC = 342,
356 IFC_f32 = 343,
357 IFC_i32 = 344,
358 IF_LOGICALNZ_f32 = 345,
359 IF_LOGICALNZ_i32 = 346,
360 IF_LOGICALZ_f32 = 347,
361 IF_LOGICALZ_i32 = 348,
362 IF_PREDICATE_SET = 349,
363 JUMP = 350,
364 JUMP_COND = 351,
365 MASK_WRITE = 352,
366 MOV_IMM_F32 = 353,
367 MOV_IMM_GLOBAL_ADDR = 354,
368 MOV_IMM_I32 = 355,
369 PRED_X = 356,
370 R600_EXTRACT_ELT_V2 = 357,
371 R600_EXTRACT_ELT_V4 = 358,
372 R600_INSERT_ELT_V2 = 359,
373 R600_INSERT_ELT_V4 = 360,
374 R600_RegisterLoad = 361,
375 R600_RegisterStore = 362,
376 RETDYN = 363,
377 RETURN = 364,
378 TXD = 365,
379 TXD_SHADOW = 366,
380 WHILELOOP = 367,
381 ADD = 368,
382 ADDC_UINT = 369,
383 ADD_INT = 370,
384 ALU_CLAUSE = 371,
385 AND_INT = 372,
386 ASHR_eg = 373,
387 ASHR_r600 = 374,
388 BCNT_INT = 375,
389 BFE_INT_eg = 376,
390 BFE_UINT_eg = 377,
391 BFI_INT_eg = 378,
392 BFM_INT_eg = 379,
393 BIT_ALIGN_INT_eg = 380,
394 CEIL = 381,
395 CF_ALU = 382,
396 CF_ALU_BREAK = 383,
397 CF_ALU_CONTINUE = 384,
398 CF_ALU_ELSE_AFTER = 385,
399 CF_ALU_POP_AFTER = 386,
400 CF_ALU_PUSH_BEFORE = 387,
401 CF_CALL_FS_EG = 388,
402 CF_CALL_FS_R600 = 389,
403 CF_CONTINUE_EG = 390,
404 CF_CONTINUE_R600 = 391,
405 CF_ELSE_EG = 392,
406 CF_ELSE_R600 = 393,
407 CF_END_CM = 394,
408 CF_END_EG = 395,
409 CF_END_R600 = 396,
410 CF_JUMP_EG = 397,
411 CF_JUMP_R600 = 398,
412 CF_PUSH_EG = 399,
413 CF_PUSH_ELSE_R600 = 400,
414 CF_TC_EG = 401,
415 CF_TC_R600 = 402,
416 CF_VC_EG = 403,
417 CF_VC_R600 = 404,
418 CNDE_INT = 405,
419 CNDE_eg = 406,
420 CNDE_r600 = 407,
421 CNDGE_INT = 408,
422 CNDGE_eg = 409,
423 CNDGE_r600 = 410,
424 CNDGT_INT = 411,
425 CNDGT_eg = 412,
426 CNDGT_r600 = 413,
427 COS_cm = 414,
428 COS_eg = 415,
429 COS_r600 = 416,
430 COS_r700 = 417,
431 CUBE_eg_real = 418,
432 CUBE_r600_real = 419,
433 DOT4_eg = 420,
434 DOT4_r600 = 421,
435 EG_ExportBuf = 422,
436 EG_ExportSwz = 423,
437 END_LOOP_EG = 424,
438 END_LOOP_R600 = 425,
439 EXP_IEEE_cm = 426,
440 EXP_IEEE_eg = 427,
441 EXP_IEEE_r600 = 428,
442 FETCH_CLAUSE = 429,
443 FFBH_UINT = 430,
444 FFBL_INT = 431,
445 FLOOR = 432,
446 FLT16_TO_FLT32 = 433,
447 FLT32_TO_FLT16 = 434,
448 FLT_TO_INT_eg = 435,
449 FLT_TO_INT_r600 = 436,
450 FLT_TO_UINT_eg = 437,
451 FLT_TO_UINT_r600 = 438,
452 FMA_eg = 439,
453 FRACT = 440,
454 GROUP_BARRIER = 441,
455 INTERP_LOAD_P0 = 442,
456 INTERP_PAIR_XY = 443,
457 INTERP_PAIR_ZW = 444,
458 INTERP_VEC_LOAD = 445,
459 INTERP_XY = 446,
460 INTERP_ZW = 447,
461 INT_TO_FLT_eg = 448,
462 INT_TO_FLT_r600 = 449,
463 KILLGT = 450,
464 LDS_ADD = 451,
465 LDS_ADD_RET = 452,
466 LDS_AND = 453,
467 LDS_AND_RET = 454,
468 LDS_BYTE_READ_RET = 455,
469 LDS_BYTE_WRITE = 456,
470 LDS_CMPST = 457,
471 LDS_CMPST_RET = 458,
472 LDS_MAX_INT = 459,
473 LDS_MAX_INT_RET = 460,
474 LDS_MAX_UINT = 461,
475 LDS_MAX_UINT_RET = 462,
476 LDS_MIN_INT = 463,
477 LDS_MIN_INT_RET = 464,
478 LDS_MIN_UINT = 465,
479 LDS_MIN_UINT_RET = 466,
480 LDS_OR = 467,
481 LDS_OR_RET = 468,
482 LDS_READ_RET = 469,
483 LDS_SHORT_READ_RET = 470,
484 LDS_SHORT_WRITE = 471,
485 LDS_SUB = 472,
486 LDS_SUB_RET = 473,
487 LDS_UBYTE_READ_RET = 474,
488 LDS_USHORT_READ_RET = 475,
489 LDS_WRITE = 476,
490 LDS_WRXCHG = 477,
491 LDS_WRXCHG_RET = 478,
492 LDS_XOR = 479,
493 LDS_XOR_RET = 480,
494 LITERALS = 481,
495 LOG_CLAMPED_eg = 482,
496 LOG_CLAMPED_r600 = 483,
497 LOG_IEEE_cm = 484,
498 LOG_IEEE_eg = 485,
499 LOG_IEEE_r600 = 486,
500 LOOP_BREAK_EG = 487,
501 LOOP_BREAK_R600 = 488,
502 LSHL_eg = 489,
503 LSHL_r600 = 490,
504 LSHR_eg = 491,
505 LSHR_r600 = 492,
506 MAX = 493,
507 MAX_DX10 = 494,
508 MAX_INT = 495,
509 MAX_UINT = 496,
510 MIN = 497,
511 MIN_DX10 = 498,
512 MIN_INT = 499,
513 MIN_UINT = 500,
514 MOV = 501,
515 MOVA_INT_eg = 502,
516 MUL = 503,
517 MULADD_IEEE_eg = 504,
518 MULADD_IEEE_r600 = 505,
519 MULADD_INT24_cm = 506,
520 MULADD_UINT24_eg = 507,
521 MULADD_eg = 508,
522 MULADD_r600 = 509,
523 MULHI_INT_cm = 510,
524 MULHI_INT_cm24 = 511,
525 MULHI_INT_eg = 512,
526 MULHI_INT_r600 = 513,
527 MULHI_UINT24_eg = 514,
528 MULHI_UINT_cm = 515,
529 MULHI_UINT_cm24 = 516,
530 MULHI_UINT_eg = 517,
531 MULHI_UINT_r600 = 518,
532 MULLO_INT_cm = 519,
533 MULLO_INT_eg = 520,
534 MULLO_INT_r600 = 521,
535 MULLO_UINT_cm = 522,
536 MULLO_UINT_eg = 523,
537 MULLO_UINT_r600 = 524,
538 MUL_IEEE = 525,
539 MUL_INT24_cm = 526,
540 MUL_LIT_eg = 527,
541 MUL_LIT_r600 = 528,
542 MUL_UINT24_eg = 529,
543 NOT_INT = 530,
544 OR_INT = 531,
545 PAD = 532,
546 POP_EG = 533,
547 POP_R600 = 534,
548 PRED_SETE = 535,
549 PRED_SETE_INT = 536,
550 PRED_SETGE = 537,
551 PRED_SETGE_INT = 538,
552 PRED_SETGT = 539,
553 PRED_SETGT_INT = 540,
554 PRED_SETNE = 541,
555 PRED_SETNE_INT = 542,
556 R600_ExportBuf = 543,
557 R600_ExportSwz = 544,
558 RAT_ATOMIC_ADD_NORET = 545,
559 RAT_ATOMIC_ADD_RTN = 546,
560 RAT_ATOMIC_AND_NORET = 547,
561 RAT_ATOMIC_AND_RTN = 548,
562 RAT_ATOMIC_CMPXCHG_INT_NORET = 549,
563 RAT_ATOMIC_CMPXCHG_INT_RTN = 550,
564 RAT_ATOMIC_DEC_UINT_NORET = 551,
565 RAT_ATOMIC_DEC_UINT_RTN = 552,
566 RAT_ATOMIC_INC_UINT_NORET = 553,
567 RAT_ATOMIC_INC_UINT_RTN = 554,
568 RAT_ATOMIC_MAX_INT_NORET = 555,
569 RAT_ATOMIC_MAX_INT_RTN = 556,
570 RAT_ATOMIC_MAX_UINT_NORET = 557,
571 RAT_ATOMIC_MAX_UINT_RTN = 558,
572 RAT_ATOMIC_MIN_INT_NORET = 559,
573 RAT_ATOMIC_MIN_INT_RTN = 560,
574 RAT_ATOMIC_MIN_UINT_NORET = 561,
575 RAT_ATOMIC_MIN_UINT_RTN = 562,
576 RAT_ATOMIC_OR_NORET = 563,
577 RAT_ATOMIC_OR_RTN = 564,
578 RAT_ATOMIC_RSUB_NORET = 565,
579 RAT_ATOMIC_RSUB_RTN = 566,
580 RAT_ATOMIC_SUB_NORET = 567,
581 RAT_ATOMIC_SUB_RTN = 568,
582 RAT_ATOMIC_XCHG_INT_NORET = 569,
583 RAT_ATOMIC_XCHG_INT_RTN = 570,
584 RAT_ATOMIC_XOR_NORET = 571,
585 RAT_ATOMIC_XOR_RTN = 572,
586 RAT_MSKOR = 573,
587 RAT_STORE_DWORD128 = 574,
588 RAT_STORE_DWORD32 = 575,
589 RAT_STORE_DWORD64 = 576,
590 RAT_STORE_TYPED_cm = 577,
591 RAT_STORE_TYPED_eg = 578,
592 RAT_WRITE_CACHELESS_128_eg = 579,
593 RAT_WRITE_CACHELESS_32_eg = 580,
594 RAT_WRITE_CACHELESS_64_eg = 581,
595 RECIPSQRT_CLAMPED_cm = 582,
596 RECIPSQRT_CLAMPED_eg = 583,
597 RECIPSQRT_CLAMPED_r600 = 584,
598 RECIPSQRT_IEEE_cm = 585,
599 RECIPSQRT_IEEE_eg = 586,
600 RECIPSQRT_IEEE_r600 = 587,
601 RECIP_CLAMPED_cm = 588,
602 RECIP_CLAMPED_eg = 589,
603 RECIP_CLAMPED_r600 = 590,
604 RECIP_IEEE_cm = 591,
605 RECIP_IEEE_eg = 592,
606 RECIP_IEEE_r600 = 593,
607 RECIP_UINT_eg = 594,
608 RECIP_UINT_r600 = 595,
609 RNDNE = 596,
610 SETE = 597,
611 SETE_DX10 = 598,
612 SETE_INT = 599,
613 SETGE_DX10 = 600,
614 SETGE_INT = 601,
615 SETGE_UINT = 602,
616 SETGT_DX10 = 603,
617 SETGT_INT = 604,
618 SETGT_UINT = 605,
619 SETNE_DX10 = 606,
620 SETNE_INT = 607,
621 SGE = 608,
622 SGT = 609,
623 SIN_cm = 610,
624 SIN_eg = 611,
625 SIN_r600 = 612,
626 SIN_r700 = 613,
627 SNE = 614,
628 SUBB_UINT = 615,
629 SUB_INT = 616,
630 TEX_GET_GRADIENTS_H = 617,
631 TEX_GET_GRADIENTS_V = 618,
632 TEX_GET_TEXTURE_RESINFO = 619,
633 TEX_LD = 620,
634 TEX_LDPTR = 621,
635 TEX_SAMPLE = 622,
636 TEX_SAMPLE_C = 623,
637 TEX_SAMPLE_C_G = 624,
638 TEX_SAMPLE_C_L = 625,
639 TEX_SAMPLE_C_LB = 626,
640 TEX_SAMPLE_G = 627,
641 TEX_SAMPLE_L = 628,
642 TEX_SAMPLE_LB = 629,
643 TEX_SET_GRADIENTS_H = 630,
644 TEX_SET_GRADIENTS_V = 631,
645 TEX_VTX_CONSTBUF = 632,
646 TEX_VTX_TEXBUF = 633,
647 TRUNC = 634,
648 UINT_TO_FLT_eg = 635,
649 UINT_TO_FLT_r600 = 636,
650 VTX_READ_128_cm = 637,
651 VTX_READ_128_eg = 638,
652 VTX_READ_16_cm = 639,
653 VTX_READ_16_eg = 640,
654 VTX_READ_32_cm = 641,
655 VTX_READ_32_eg = 642,
656 VTX_READ_64_cm = 643,
657 VTX_READ_64_eg = 644,
658 VTX_READ_8_cm = 645,
659 VTX_READ_8_eg = 646,
660 WHILE_LOOP_EG = 647,
661 WHILE_LOOP_R600 = 648,
662 XOR_INT = 649,
663 INSTRUCTION_LIST_END = 650
664 };
665
666} // end namespace llvm::R600
667#endif // GET_INSTRINFO_ENUM
668
669#ifdef GET_INSTRINFO_SCHED_ENUM
670#undef GET_INSTRINFO_SCHED_ENUM
671namespace llvm::R600::Sched {
672
673 enum {
674 NoInstrModel = 0,
675 NullALU = 1,
676 VecALU = 2,
677 AnyALU = 3,
678 TransALU = 4,
679 XALU = 5,
680 SCHED_LIST_END = 6
681 };
682} // end namespace llvm::R600::Sched
683#endif // GET_INSTRINFO_SCHED_ENUM
684
685#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
686namespace llvm {
687
688struct R600InstrTable {
689 MCInstrDesc Insts[650];
690 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
691 MCOperandInfo OperandInfo[462];
692 static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps");
693 MCPhysReg ImplicitOps[1];
694};
695
696} // end namespace llvm
697#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
698
699#ifdef GET_INSTRINFO_MC_DESC
700#undef GET_INSTRINFO_MC_DESC
701namespace llvm {
702
703static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0);
704static constexpr unsigned R600ImpOpBase = sizeof R600InstrTable::OperandInfo / (sizeof(MCPhysReg));
705
706extern const R600InstrTable R600Descs = {
707 {
708 { 649, 21, 1, 0, 3, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #649 = XOR_INT
709 { 648, 1, 0, 0, 1, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #648 = WHILE_LOOP_R600
710 { 647, 1, 0, 0, 1, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #647 = WHILE_LOOP_EG
711 { 646, 4, 1, 0, 1, 0, 0, 450, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // Inst #646 = VTX_READ_8_eg
712 { 645, 4, 1, 0, 1, 0, 0, 450, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // Inst #645 = VTX_READ_8_cm
713 { 644, 4, 1, 0, 1, 0, 0, 458, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // Inst #644 = VTX_READ_64_eg
714 { 643, 4, 1, 0, 1, 0, 0, 458, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // Inst #643 = VTX_READ_64_cm
715 { 642, 4, 1, 0, 1, 0, 0, 454, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // Inst #642 = VTX_READ_32_eg
716 { 641, 4, 1, 0, 1, 0, 0, 454, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // Inst #641 = VTX_READ_32_cm
717 { 640, 4, 1, 0, 1, 0, 0, 450, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // Inst #640 = VTX_READ_16_eg
718 { 639, 4, 1, 0, 1, 0, 0, 450, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // Inst #639 = VTX_READ_16_cm
719 { 638, 4, 1, 0, 1, 0, 0, 446, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // Inst #638 = VTX_READ_128_eg
720 { 637, 4, 1, 0, 1, 0, 0, 446, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // Inst #637 = VTX_READ_128_cm
721 { 636, 14, 1, 0, 4, 0, 0, 284, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #636 = UINT_TO_FLT_r600
722 { 635, 14, 1, 0, 4, 0, 0, 284, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #635 = UINT_TO_FLT_eg
723 { 634, 14, 1, 0, 3, 0, 0, 284, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #634 = TRUNC
724 { 633, 4, 1, 0, 1, 0, 0, 446, R600ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1000ULL }, // Inst #633 = TEX_VTX_TEXBUF
725 { 632, 4, 1, 0, 1, 0, 0, 446, R600ImpOpBase + 0, 0, 0x1000ULL }, // Inst #632 = TEX_VTX_CONSTBUF
726 { 631, 19, 1, 0, 1, 0, 0, 427, R600ImpOpBase + 0, 0, 0x2000ULL }, // Inst #631 = TEX_SET_GRADIENTS_V
727 { 630, 19, 1, 0, 1, 0, 0, 427, R600ImpOpBase + 0, 0, 0x2000ULL }, // Inst #630 = TEX_SET_GRADIENTS_H
728 { 629, 19, 1, 0, 1, 0, 0, 427, R600ImpOpBase + 0, 0, 0x2000ULL }, // Inst #629 = TEX_SAMPLE_LB
729 { 628, 19, 1, 0, 1, 0, 0, 427, R600ImpOpBase + 0, 0, 0x2000ULL }, // Inst #628 = TEX_SAMPLE_L
730 { 627, 19, 1, 0, 1, 0, 0, 427, R600ImpOpBase + 0, 0, 0x2000ULL }, // Inst #627 = TEX_SAMPLE_G
731 { 626, 19, 1, 0, 1, 0, 0, 427, R600ImpOpBase + 0, 0, 0x2000ULL }, // Inst #626 = TEX_SAMPLE_C_LB
732 { 625, 19, 1, 0, 1, 0, 0, 427, R600ImpOpBase + 0, 0, 0x2000ULL }, // Inst #625 = TEX_SAMPLE_C_L
733 { 624, 19, 1, 0, 1, 0, 0, 427, R600ImpOpBase + 0, 0, 0x2000ULL }, // Inst #624 = TEX_SAMPLE_C_G
734 { 623, 19, 1, 0, 1, 0, 0, 427, R600ImpOpBase + 0, 0, 0x2000ULL }, // Inst #623 = TEX_SAMPLE_C
735 { 622, 19, 1, 0, 1, 0, 0, 427, R600ImpOpBase + 0, 0, 0x2000ULL }, // Inst #622 = TEX_SAMPLE
736 { 621, 19, 1, 0, 1, 0, 0, 427, R600ImpOpBase + 0, 0, 0x2000ULL }, // Inst #621 = TEX_LDPTR
737 { 620, 19, 1, 0, 1, 0, 0, 427, R600ImpOpBase + 0, 0, 0x2000ULL }, // Inst #620 = TEX_LD
738 { 619, 19, 1, 0, 1, 0, 0, 427, R600ImpOpBase + 0, 0, 0x2000ULL }, // Inst #619 = TEX_GET_TEXTURE_RESINFO
739 { 618, 19, 1, 0, 1, 0, 0, 427, R600ImpOpBase + 0, 0, 0x2000ULL }, // Inst #618 = TEX_GET_GRADIENTS_V
740 { 617, 19, 1, 0, 1, 0, 0, 427, R600ImpOpBase + 0, 0, 0x2000ULL }, // Inst #617 = TEX_GET_GRADIENTS_H
741 { 616, 21, 1, 0, 3, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #616 = SUB_INT
742 { 615, 21, 1, 0, 3, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #615 = SUBB_UINT
743 { 614, 21, 1, 0, 3, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #614 = SNE
744 { 613, 14, 1, 0, 4, 0, 0, 284, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4610ULL }, // Inst #613 = SIN_r700
745 { 612, 14, 1, 0, 4, 0, 0, 284, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4610ULL }, // Inst #612 = SIN_r600
746 { 611, 14, 1, 0, 4, 0, 0, 284, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4610ULL }, // Inst #611 = SIN_eg
747 { 610, 14, 1, 0, 4, 0, 0, 284, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4650ULL }, // Inst #610 = SIN_cm
748 { 609, 21, 1, 0, 3, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #609 = SGT
749 { 608, 21, 1, 0, 3, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #608 = SGE
750 { 607, 21, 1, 0, 3, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #607 = SETNE_INT
751 { 606, 21, 1, 0, 3, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #606 = SETNE_DX10
752 { 605, 21, 1, 0, 3, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #605 = SETGT_UINT
753 { 604, 21, 1, 0, 3, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #604 = SETGT_INT
754 { 603, 21, 1, 0, 3, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #603 = SETGT_DX10
755 { 602, 21, 1, 0, 3, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #602 = SETGE_UINT
756 { 601, 21, 1, 0, 3, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #601 = SETGE_INT
757 { 600, 21, 1, 0, 3, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #600 = SETGE_DX10
758 { 599, 21, 1, 0, 3, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #599 = SETE_INT
759 { 598, 21, 1, 0, 3, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #598 = SETE_DX10
760 { 597, 21, 1, 0, 3, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #597 = SETE
761 { 596, 14, 1, 0, 3, 0, 0, 284, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #596 = RNDNE
762 { 595, 14, 1, 0, 4, 0, 0, 284, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #595 = RECIP_UINT_r600
763 { 594, 14, 1, 0, 4, 0, 0, 284, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #594 = RECIP_UINT_eg
764 { 593, 14, 1, 0, 4, 0, 0, 284, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #593 = RECIP_IEEE_r600
765 { 592, 14, 1, 0, 4, 0, 0, 284, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #592 = RECIP_IEEE_eg
766 { 591, 14, 1, 0, 4, 0, 0, 284, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4640ULL }, // Inst #591 = RECIP_IEEE_cm
767 { 590, 14, 1, 0, 4, 0, 0, 284, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #590 = RECIP_CLAMPED_r600
768 { 589, 14, 1, 0, 4, 0, 0, 284, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #589 = RECIP_CLAMPED_eg
769 { 588, 14, 1, 0, 4, 0, 0, 284, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4640ULL }, // Inst #588 = RECIP_CLAMPED_cm
770 { 587, 14, 1, 0, 4, 0, 0, 284, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #587 = RECIPSQRT_IEEE_r600
771 { 586, 14, 1, 0, 4, 0, 0, 284, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #586 = RECIPSQRT_IEEE_eg
772 { 585, 14, 1, 0, 4, 0, 0, 284, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4640ULL }, // Inst #585 = RECIPSQRT_IEEE_cm
773 { 584, 14, 1, 0, 4, 0, 0, 284, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #584 = RECIPSQRT_CLAMPED_r600
774 { 583, 14, 1, 0, 4, 0, 0, 284, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #583 = RECIPSQRT_CLAMPED_eg
775 { 582, 14, 1, 0, 4, 0, 0, 284, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4640ULL }, // Inst #582 = RECIPSQRT_CLAMPED_cm
776 { 581, 3, 0, 0, 1, 0, 0, 424, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x20000ULL }, // Inst #581 = RAT_WRITE_CACHELESS_64_eg
777 { 580, 3, 0, 0, 1, 0, 0, 421, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x20000ULL }, // Inst #580 = RAT_WRITE_CACHELESS_32_eg
778 { 579, 3, 0, 0, 1, 0, 0, 418, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x20000ULL }, // Inst #579 = RAT_WRITE_CACHELESS_128_eg
779 { 578, 4, 0, 0, 1, 0, 0, 414, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #578 = RAT_STORE_TYPED_eg
780 { 577, 4, 0, 0, 1, 0, 0, 414, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #577 = RAT_STORE_TYPED_cm
781 { 576, 2, 0, 0, 1, 0, 0, 412, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x20000ULL }, // Inst #576 = RAT_STORE_DWORD64
782 { 575, 2, 0, 0, 1, 0, 0, 410, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x20000ULL }, // Inst #575 = RAT_STORE_DWORD32
783 { 574, 2, 0, 0, 1, 0, 0, 408, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x20000ULL }, // Inst #574 = RAT_STORE_DWORD128
784 { 573, 2, 0, 0, 1, 0, 0, 408, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x20000ULL }, // Inst #573 = RAT_MSKOR
785 { 572, 3, 1, 0, 1, 0, 0, 405, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #572 = RAT_ATOMIC_XOR_RTN
786 { 571, 3, 1, 0, 1, 0, 0, 405, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #571 = RAT_ATOMIC_XOR_NORET
787 { 570, 3, 1, 0, 1, 0, 0, 405, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #570 = RAT_ATOMIC_XCHG_INT_RTN
788 { 569, 3, 1, 0, 1, 0, 0, 405, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #569 = RAT_ATOMIC_XCHG_INT_NORET
789 { 568, 3, 1, 0, 1, 0, 0, 405, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #568 = RAT_ATOMIC_SUB_RTN
790 { 567, 3, 1, 0, 1, 0, 0, 405, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #567 = RAT_ATOMIC_SUB_NORET
791 { 566, 3, 1, 0, 1, 0, 0, 405, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #566 = RAT_ATOMIC_RSUB_RTN
792 { 565, 3, 1, 0, 1, 0, 0, 405, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #565 = RAT_ATOMIC_RSUB_NORET
793 { 564, 3, 1, 0, 1, 0, 0, 405, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #564 = RAT_ATOMIC_OR_RTN
794 { 563, 3, 1, 0, 1, 0, 0, 405, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #563 = RAT_ATOMIC_OR_NORET
795 { 562, 3, 1, 0, 1, 0, 0, 405, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #562 = RAT_ATOMIC_MIN_UINT_RTN
796 { 561, 3, 1, 0, 1, 0, 0, 405, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #561 = RAT_ATOMIC_MIN_UINT_NORET
797 { 560, 3, 1, 0, 1, 0, 0, 405, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #560 = RAT_ATOMIC_MIN_INT_RTN
798 { 559, 3, 1, 0, 1, 0, 0, 405, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #559 = RAT_ATOMIC_MIN_INT_NORET
799 { 558, 3, 1, 0, 1, 0, 0, 405, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #558 = RAT_ATOMIC_MAX_UINT_RTN
800 { 557, 3, 1, 0, 1, 0, 0, 405, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #557 = RAT_ATOMIC_MAX_UINT_NORET
801 { 556, 3, 1, 0, 1, 0, 0, 405, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #556 = RAT_ATOMIC_MAX_INT_RTN
802 { 555, 3, 1, 0, 1, 0, 0, 405, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #555 = RAT_ATOMIC_MAX_INT_NORET
803 { 554, 3, 1, 0, 1, 0, 0, 405, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #554 = RAT_ATOMIC_INC_UINT_RTN
804 { 553, 3, 1, 0, 1, 0, 0, 405, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #553 = RAT_ATOMIC_INC_UINT_NORET
805 { 552, 3, 1, 0, 1, 0, 0, 405, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #552 = RAT_ATOMIC_DEC_UINT_RTN
806 { 551, 3, 1, 0, 1, 0, 0, 405, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #551 = RAT_ATOMIC_DEC_UINT_NORET
807 { 550, 3, 1, 0, 1, 0, 0, 405, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #550 = RAT_ATOMIC_CMPXCHG_INT_RTN
808 { 549, 3, 1, 0, 1, 0, 0, 405, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #549 = RAT_ATOMIC_CMPXCHG_INT_NORET
809 { 548, 3, 1, 0, 1, 0, 0, 405, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #548 = RAT_ATOMIC_AND_RTN
810 { 547, 3, 1, 0, 1, 0, 0, 405, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #547 = RAT_ATOMIC_AND_NORET
811 { 546, 3, 1, 0, 1, 0, 0, 405, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #546 = RAT_ATOMIC_ADD_RTN
812 { 545, 3, 1, 0, 1, 0, 0, 405, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #545 = RAT_ATOMIC_ADD_NORET
813 { 544, 9, 0, 0, 1, 0, 0, 333, R600ImpOpBase + 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #544 = R600_ExportSwz
814 { 543, 7, 0, 0, 1, 0, 0, 326, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #543 = R600_ExportBuf
815 { 542, 21, 1, 0, 3, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #542 = PRED_SETNE_INT
816 { 541, 21, 1, 0, 3, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #541 = PRED_SETNE
817 { 540, 21, 1, 0, 3, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #540 = PRED_SETGT_INT
818 { 539, 21, 1, 0, 3, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #539 = PRED_SETGT
819 { 538, 21, 1, 0, 3, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #538 = PRED_SETGE_INT
820 { 537, 21, 1, 0, 3, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #537 = PRED_SETGE
821 { 536, 21, 1, 0, 3, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #536 = PRED_SETE_INT
822 { 535, 21, 1, 0, 3, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #535 = PRED_SETE
823 { 534, 2, 0, 0, 1, 0, 0, 21, R600ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #534 = POP_R600
824 { 533, 2, 0, 0, 1, 0, 0, 21, R600ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #533 = POP_EG
825 { 532, 0, 0, 0, 1, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #532 = PAD
826 { 531, 21, 1, 0, 3, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #531 = OR_INT
827 { 530, 14, 1, 0, 3, 0, 0, 284, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #530 = NOT_INT
828 { 529, 21, 1, 0, 2, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #529 = MUL_UINT24_eg
829 { 528, 19, 1, 0, 3, 0, 0, 298, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #528 = MUL_LIT_r600
830 { 527, 19, 1, 0, 3, 0, 0, 298, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #527 = MUL_LIT_eg
831 { 526, 21, 1, 0, 2, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #526 = MUL_INT24_cm
832 { 525, 21, 1, 0, 3, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #525 = MUL_IEEE
833 { 524, 21, 1, 0, 4, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #524 = MULLO_UINT_r600
834 { 523, 21, 1, 0, 4, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #523 = MULLO_UINT_eg
835 { 522, 21, 1, 0, 4, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a40ULL }, // Inst #522 = MULLO_UINT_cm
836 { 521, 21, 1, 0, 4, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #521 = MULLO_INT_r600
837 { 520, 21, 1, 0, 4, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #520 = MULLO_INT_eg
838 { 519, 21, 1, 0, 4, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a40ULL }, // Inst #519 = MULLO_INT_cm
839 { 518, 21, 1, 0, 4, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #518 = MULHI_UINT_r600
840 { 517, 21, 1, 0, 4, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #517 = MULHI_UINT_eg
841 { 516, 21, 1, 0, 2, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a40ULL }, // Inst #516 = MULHI_UINT_cm24
842 { 515, 21, 1, 0, 4, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a40ULL }, // Inst #515 = MULHI_UINT_cm
843 { 514, 21, 1, 0, 2, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #514 = MULHI_UINT24_eg
844 { 513, 21, 1, 0, 4, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #513 = MULHI_INT_r600
845 { 512, 21, 1, 0, 4, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #512 = MULHI_INT_eg
846 { 511, 21, 1, 0, 2, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a40ULL }, // Inst #511 = MULHI_INT_cm24
847 { 510, 21, 1, 0, 4, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a40ULL }, // Inst #510 = MULHI_INT_cm
848 { 509, 19, 1, 0, 3, 0, 0, 298, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #509 = MULADD_r600
849 { 508, 19, 1, 0, 3, 0, 0, 298, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #508 = MULADD_eg
850 { 507, 19, 1, 0, 2, 0, 0, 298, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #507 = MULADD_UINT24_eg
851 { 506, 19, 1, 0, 2, 0, 0, 298, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #506 = MULADD_INT24_cm
852 { 505, 19, 1, 0, 3, 0, 0, 298, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #505 = MULADD_IEEE_r600
853 { 504, 19, 1, 0, 3, 0, 0, 298, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #504 = MULADD_IEEE_eg
854 { 503, 21, 1, 0, 3, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #503 = MUL
855 { 502, 14, 1, 0, 2, 0, 0, 284, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x4600ULL }, // Inst #502 = MOVA_INT_eg
856 { 501, 14, 1, 0, 3, 0, 0, 284, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #501 = MOV
857 { 500, 21, 1, 0, 3, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #500 = MIN_UINT
858 { 499, 21, 1, 0, 3, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #499 = MIN_INT
859 { 498, 21, 1, 0, 3, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #498 = MIN_DX10
860 { 497, 21, 1, 0, 3, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #497 = MIN
861 { 496, 21, 1, 0, 3, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #496 = MAX_UINT
862 { 495, 21, 1, 0, 3, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #495 = MAX_INT
863 { 494, 21, 1, 0, 3, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #494 = MAX_DX10
864 { 493, 21, 1, 0, 3, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #493 = MAX
865 { 492, 21, 1, 0, 3, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #492 = LSHR_r600
866 { 491, 21, 1, 0, 3, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #491 = LSHR_eg
867 { 490, 21, 1, 0, 3, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #490 = LSHL_r600
868 { 489, 21, 1, 0, 3, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #489 = LSHL_eg
869 { 488, 1, 0, 0, 1, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #488 = LOOP_BREAK_R600
870 { 487, 1, 0, 0, 1, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #487 = LOOP_BREAK_EG
871 { 486, 14, 1, 0, 4, 0, 0, 284, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #486 = LOG_IEEE_r600
872 { 485, 14, 1, 0, 4, 0, 0, 284, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #485 = LOG_IEEE_eg
873 { 484, 14, 1, 0, 4, 0, 0, 284, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4640ULL }, // Inst #484 = LOG_IEEE_cm
874 { 483, 14, 1, 0, 3, 0, 0, 284, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #483 = LOG_CLAMPED_r600
875 { 482, 14, 1, 0, 3, 0, 0, 284, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #482 = LOG_CLAMPED_eg
876 { 481, 2, 0, 0, 1, 0, 0, 13, R600ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #481 = LITERALS
877 { 480, 10, 1, 0, 5, 0, 0, 363, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // Inst #480 = LDS_XOR_RET
878 { 479, 9, 0, 0, 5, 0, 0, 354, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // Inst #479 = LDS_XOR
879 { 478, 10, 1, 0, 5, 0, 0, 363, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // Inst #478 = LDS_WRXCHG_RET
880 { 477, 9, 0, 0, 5, 0, 0, 354, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // Inst #477 = LDS_WRXCHG
881 { 476, 9, 0, 0, 5, 0, 0, 354, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x14200ULL }, // Inst #476 = LDS_WRITE
882 { 475, 7, 1, 0, 5, 0, 0, 373, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL }, // Inst #475 = LDS_USHORT_READ_RET
883 { 474, 7, 1, 0, 5, 0, 0, 373, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL }, // Inst #474 = LDS_UBYTE_READ_RET
884 { 473, 10, 1, 0, 5, 0, 0, 363, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // Inst #473 = LDS_SUB_RET
885 { 472, 9, 0, 0, 5, 0, 0, 354, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // Inst #472 = LDS_SUB
886 { 471, 9, 0, 0, 5, 0, 0, 354, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x14200ULL }, // Inst #471 = LDS_SHORT_WRITE
887 { 470, 7, 1, 0, 5, 0, 0, 373, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL }, // Inst #470 = LDS_SHORT_READ_RET
888 { 469, 7, 1, 0, 5, 0, 0, 373, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL }, // Inst #469 = LDS_READ_RET
889 { 468, 10, 1, 0, 5, 0, 0, 363, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // Inst #468 = LDS_OR_RET
890 { 467, 9, 0, 0, 5, 0, 0, 354, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // Inst #467 = LDS_OR
891 { 466, 10, 1, 0, 5, 0, 0, 363, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // Inst #466 = LDS_MIN_UINT_RET
892 { 465, 9, 0, 0, 5, 0, 0, 354, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // Inst #465 = LDS_MIN_UINT
893 { 464, 10, 1, 0, 5, 0, 0, 363, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // Inst #464 = LDS_MIN_INT_RET
894 { 463, 9, 0, 0, 5, 0, 0, 354, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // Inst #463 = LDS_MIN_INT
895 { 462, 10, 1, 0, 5, 0, 0, 363, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // Inst #462 = LDS_MAX_UINT_RET
896 { 461, 9, 0, 0, 5, 0, 0, 354, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // Inst #461 = LDS_MAX_UINT
897 { 460, 10, 1, 0, 5, 0, 0, 363, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // Inst #460 = LDS_MAX_INT_RET
898 { 459, 9, 0, 0, 5, 0, 0, 354, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // Inst #459 = LDS_MAX_INT
899 { 458, 13, 1, 0, 5, 0, 0, 392, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x44200ULL }, // Inst #458 = LDS_CMPST_RET
900 { 457, 12, 0, 0, 5, 0, 0, 380, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44200ULL }, // Inst #457 = LDS_CMPST
901 { 456, 9, 0, 0, 5, 0, 0, 354, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x14200ULL }, // Inst #456 = LDS_BYTE_WRITE
902 { 455, 7, 1, 0, 5, 0, 0, 373, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL }, // Inst #455 = LDS_BYTE_READ_RET
903 { 454, 10, 1, 0, 5, 0, 0, 363, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // Inst #454 = LDS_AND_RET
904 { 453, 9, 0, 0, 5, 0, 0, 354, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // Inst #453 = LDS_AND
905 { 452, 10, 1, 0, 5, 0, 0, 363, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // Inst #452 = LDS_ADD_RET
906 { 451, 9, 0, 0, 5, 0, 0, 354, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // Inst #451 = LDS_ADD
907 { 450, 21, 1, 0, 3, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x4a00ULL }, // Inst #450 = KILLGT
908 { 449, 14, 1, 0, 4, 0, 0, 284, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #449 = INT_TO_FLT_r600
909 { 448, 14, 1, 0, 4, 0, 0, 284, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #448 = INT_TO_FLT_eg
910 { 447, 21, 1, 0, 3, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #447 = INTERP_ZW
911 { 446, 21, 1, 0, 3, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #446 = INTERP_XY
912 { 445, 2, 1, 0, 1, 0, 0, 352, R600ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #445 = INTERP_VEC_LOAD
913 { 444, 5, 2, 0, 1, 0, 0, 347, R600ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #444 = INTERP_PAIR_ZW
914 { 443, 5, 2, 0, 1, 0, 0, 342, R600ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #443 = INTERP_PAIR_XY
915 { 442, 14, 1, 0, 3, 0, 0, 284, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #442 = INTERP_LOAD_P0
916 { 441, 0, 0, 0, 3, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x4000ULL }, // Inst #441 = GROUP_BARRIER
917 { 440, 14, 1, 0, 3, 0, 0, 284, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #440 = FRACT
918 { 439, 19, 1, 0, 2, 0, 0, 298, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #439 = FMA_eg
919 { 438, 14, 1, 0, 4, 0, 0, 284, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #438 = FLT_TO_UINT_r600
920 { 437, 14, 1, 0, 4, 0, 0, 284, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #437 = FLT_TO_UINT_eg
921 { 436, 14, 1, 0, 4, 0, 0, 284, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #436 = FLT_TO_INT_r600
922 { 435, 14, 1, 0, 3, 0, 0, 284, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #435 = FLT_TO_INT_eg
923 { 434, 14, 1, 0, 2, 0, 0, 284, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #434 = FLT32_TO_FLT16
924 { 433, 14, 1, 0, 2, 0, 0, 284, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #433 = FLT16_TO_FLT32
925 { 432, 14, 1, 0, 3, 0, 0, 284, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #432 = FLOOR
926 { 431, 14, 1, 0, 2, 0, 0, 284, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #431 = FFBL_INT
927 { 430, 14, 1, 0, 2, 0, 0, 284, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #430 = FFBH_UINT
928 { 429, 1, 0, 0, 1, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #429 = FETCH_CLAUSE
929 { 428, 14, 1, 0, 4, 0, 0, 284, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #428 = EXP_IEEE_r600
930 { 427, 14, 1, 0, 4, 0, 0, 284, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #427 = EXP_IEEE_eg
931 { 426, 14, 1, 0, 4, 0, 0, 284, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4640ULL }, // Inst #426 = EXP_IEEE_cm
932 { 425, 1, 0, 0, 1, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #425 = END_LOOP_R600
933 { 424, 1, 0, 0, 1, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #424 = END_LOOP_EG
934 { 423, 9, 0, 0, 1, 0, 0, 333, R600ImpOpBase + 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #423 = EG_ExportSwz
935 { 422, 7, 0, 0, 1, 0, 0, 326, R600ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #422 = EG_ExportBuf
936 { 421, 21, 1, 0, 3, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #421 = DOT4_r600
937 { 420, 21, 1, 0, 3, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #420 = DOT4_eg
938 { 419, 21, 1, 0, 3, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #419 = CUBE_r600_real
939 { 418, 21, 1, 0, 3, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #418 = CUBE_eg_real
940 { 417, 14, 1, 0, 4, 0, 0, 284, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4610ULL }, // Inst #417 = COS_r700
941 { 416, 14, 1, 0, 4, 0, 0, 284, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4610ULL }, // Inst #416 = COS_r600
942 { 415, 14, 1, 0, 4, 0, 0, 284, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4610ULL }, // Inst #415 = COS_eg
943 { 414, 14, 1, 0, 4, 0, 0, 284, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4650ULL }, // Inst #414 = COS_cm
944 { 413, 19, 1, 0, 2, 0, 0, 298, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #413 = CNDGT_r600
945 { 412, 19, 1, 0, 2, 0, 0, 298, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #412 = CNDGT_eg
946 { 411, 19, 1, 0, 3, 0, 0, 298, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #411 = CNDGT_INT
947 { 410, 19, 1, 0, 2, 0, 0, 298, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #410 = CNDGE_r600
948 { 409, 19, 1, 0, 2, 0, 0, 298, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #409 = CNDGE_eg
949 { 408, 19, 1, 0, 3, 0, 0, 298, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #408 = CNDGE_INT
950 { 407, 19, 1, 0, 3, 0, 0, 298, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #407 = CNDE_r600
951 { 406, 19, 1, 0, 3, 0, 0, 298, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #406 = CNDE_eg
952 { 405, 19, 1, 0, 3, 0, 0, 298, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #405 = CNDE_INT
953 { 404, 2, 0, 0, 1, 0, 0, 21, R600ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #404 = CF_VC_R600
954 { 403, 2, 0, 0, 1, 0, 0, 21, R600ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #403 = CF_VC_EG
955 { 402, 2, 0, 0, 1, 0, 0, 21, R600ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #402 = CF_TC_R600
956 { 401, 2, 0, 0, 1, 0, 0, 21, R600ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #401 = CF_TC_EG
957 { 400, 1, 0, 0, 1, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #400 = CF_PUSH_ELSE_R600
958 { 399, 2, 0, 0, 1, 0, 0, 21, R600ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #399 = CF_PUSH_EG
959 { 398, 2, 0, 0, 1, 0, 0, 21, R600ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #398 = CF_JUMP_R600
960 { 397, 2, 0, 0, 1, 0, 0, 21, R600ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #397 = CF_JUMP_EG
961 { 396, 0, 0, 0, 1, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #396 = CF_END_R600
962 { 395, 0, 0, 0, 1, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #395 = CF_END_EG
963 { 394, 0, 0, 0, 1, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #394 = CF_END_CM
964 { 393, 2, 0, 0, 1, 0, 0, 21, R600ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #393 = CF_ELSE_R600
965 { 392, 2, 0, 0, 1, 0, 0, 21, R600ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #392 = CF_ELSE_EG
966 { 391, 1, 0, 0, 1, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #391 = CF_CONTINUE_R600
967 { 390, 1, 0, 0, 1, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #390 = CF_CONTINUE_EG
968 { 389, 0, 0, 0, 1, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #389 = CF_CALL_FS_R600
969 { 388, 0, 0, 0, 1, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #388 = CF_CALL_FS_EG
970 { 387, 9, 0, 0, 1, 0, 0, 317, R600ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #387 = CF_ALU_PUSH_BEFORE
971 { 386, 9, 0, 0, 1, 0, 0, 317, R600ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #386 = CF_ALU_POP_AFTER
972 { 385, 9, 0, 0, 1, 0, 0, 317, R600ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #385 = CF_ALU_ELSE_AFTER
973 { 384, 9, 0, 0, 1, 0, 0, 317, R600ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #384 = CF_ALU_CONTINUE
974 { 383, 9, 0, 0, 1, 0, 0, 317, R600ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #383 = CF_ALU_BREAK
975 { 382, 9, 0, 0, 1, 0, 0, 317, R600ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #382 = CF_ALU
976 { 381, 14, 1, 0, 3, 0, 0, 284, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #381 = CEIL
977 { 380, 19, 1, 0, 2, 0, 0, 298, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #380 = BIT_ALIGN_INT_eg
978 { 379, 21, 1, 0, 2, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #379 = BFM_INT_eg
979 { 378, 19, 1, 0, 2, 0, 0, 298, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #378 = BFI_INT_eg
980 { 377, 19, 1, 0, 2, 0, 0, 298, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #377 = BFE_UINT_eg
981 { 376, 19, 1, 0, 2, 0, 0, 298, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #376 = BFE_INT_eg
982 { 375, 14, 1, 0, 2, 0, 0, 284, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #375 = BCNT_INT
983 { 374, 21, 1, 0, 3, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #374 = ASHR_r600
984 { 373, 21, 1, 0, 3, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #373 = ASHR_eg
985 { 372, 21, 1, 0, 3, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #372 = AND_INT
986 { 371, 1, 0, 0, 1, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #371 = ALU_CLAUSE
987 { 370, 21, 1, 0, 3, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #370 = ADD_INT
988 { 369, 21, 1, 0, 3, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #369 = ADDC_UINT
989 { 368, 21, 1, 0, 3, 0, 0, 263, R600ImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #368 = ADD
990 { 367, 0, 0, 0, 1, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #367 = WHILELOOP
991 { 366, 7, 1, 0, 1, 0, 0, 256, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2000ULL }, // Inst #366 = TXD_SHADOW
992 { 365, 7, 1, 0, 1, 0, 0, 256, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2000ULL }, // Inst #365 = TXD
993 { 364, 0, 0, 0, 1, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #364 = RETURN
994 { 363, 0, 0, 0, 1, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #363 = RETDYN
995 { 362, 4, 0, 0, 1, 0, 0, 252, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000000000000000ULL }, // Inst #362 = R600_RegisterStore
996 { 361, 4, 1, 0, 1, 0, 0, 252, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8000000000000000ULL }, // Inst #361 = R600_RegisterLoad
997 { 360, 4, 1, 0, 3, 0, 0, 248, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #360 = R600_INSERT_ELT_V4
998 { 359, 4, 1, 0, 3, 0, 0, 244, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #359 = R600_INSERT_ELT_V2
999 { 358, 3, 1, 0, 3, 0, 0, 241, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #358 = R600_EXTRACT_ELT_V4
1000 { 357, 3, 1, 0, 3, 0, 0, 238, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #357 = R600_EXTRACT_ELT_V2
1001 { 356, 4, 1, 0, 1, 0, 0, 234, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x180ULL }, // Inst #356 = PRED_X
1002 { 355, 2, 1, 0, 1, 0, 0, 157, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #355 = MOV_IMM_I32
1003 { 354, 2, 1, 0, 1, 0, 0, 157, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #354 = MOV_IMM_GLOBAL_ADDR
1004 { 353, 2, 1, 0, 1, 0, 0, 157, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #353 = MOV_IMM_F32
1005 { 352, 1, 0, 0, 1, 0, 0, 156, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #352 = MASK_WRITE
1006 { 351, 2, 0, 0, 3, 0, 0, 232, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #351 = JUMP_COND
1007 { 350, 1, 0, 0, 3, 0, 0, 0, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #350 = JUMP
1008 { 349, 1, 0, 0, 1, 0, 0, 156, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #349 = IF_PREDICATE_SET
1009 { 348, 1, 0, 0, 1, 0, 0, 156, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #348 = IF_LOGICALZ_i32
1010 { 347, 1, 0, 0, 1, 0, 0, 156, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #347 = IF_LOGICALZ_f32
1011 { 346, 1, 0, 0, 1, 0, 0, 156, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #346 = IF_LOGICALNZ_i32
1012 { 345, 1, 0, 0, 1, 0, 0, 156, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #345 = IF_LOGICALNZ_f32
1013 { 344, 2, 0, 0, 1, 0, 0, 154, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #344 = IFC_i32
1014 { 343, 2, 0, 0, 1, 0, 0, 154, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #343 = IFC_f32
1015 { 342, 0, 0, 0, 1, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #342 = FUNC
1016 { 341, 2, 1, 0, 1, 0, 0, 154, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #341 = FNEG_R600
1017 { 340, 2, 1, 0, 1, 0, 0, 154, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #340 = FABS_R600
1018 { 339, 0, 0, 0, 1, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #339 = ENDSWITCH
1019 { 338, 0, 0, 0, 1, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #338 = ENDMAIN
1020 { 337, 0, 0, 0, 1, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #337 = ENDLOOP
1021 { 336, 0, 0, 0, 1, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #336 = ENDIF
1022 { 335, 0, 0, 0, 1, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #335 = ENDFUNC
1023 { 334, 0, 0, 0, 1, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #334 = END
1024 { 333, 0, 0, 0, 1, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #333 = ELSE
1025 { 332, 0, 0, 0, 1, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #332 = DUMMY_CHAIN
1026 { 331, 71, 1, 0, 3, 0, 0, 161, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL }, // Inst #331 = DOT_4
1027 { 330, 0, 0, 0, 1, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #330 = DEFAULT
1028 { 329, 2, 1, 0, 2, 0, 0, 159, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #329 = CUBE_r600_pseudo
1029 { 328, 2, 1, 0, 2, 0, 0, 159, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #328 = CUBE_eg_pseudo
1030 { 327, 1, 0, 0, 1, 0, 0, 156, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #327 = CONTINUE_LOGICALZ_i32
1031 { 326, 1, 0, 0, 1, 0, 0, 156, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #326 = CONTINUE_LOGICALZ_f32
1032 { 325, 1, 0, 0, 1, 0, 0, 156, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #325 = CONTINUE_LOGICALNZ_i32
1033 { 324, 1, 0, 0, 1, 0, 0, 156, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #324 = CONTINUE_LOGICALNZ_f32
1034 { 323, 2, 0, 0, 1, 0, 0, 154, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #323 = CONTINUEC_i32
1035 { 322, 2, 0, 0, 1, 0, 0, 154, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #322 = CONTINUEC_f32
1036 { 321, 0, 0, 0, 1, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #321 = CONTINUE
1037 { 320, 2, 1, 0, 1, 0, 0, 157, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #320 = CONST_COPY
1038 { 319, 1, 0, 0, 1, 0, 0, 156, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #319 = BREAK_LOGICALZ_i32
1039 { 318, 1, 0, 0, 1, 0, 0, 156, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #318 = BREAK_LOGICALZ_f32
1040 { 317, 1, 0, 0, 1, 0, 0, 156, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #317 = BREAK_LOGICALNZ_i32
1041 { 316, 1, 0, 0, 1, 0, 0, 156, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #316 = BREAK_LOGICALNZ_f32
1042 { 315, 2, 0, 0, 1, 0, 0, 154, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #315 = BREAKC_i32
1043 { 314, 2, 0, 0, 1, 0, 0, 154, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #314 = BREAKC_f32
1044 { 313, 0, 0, 0, 1, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #313 = BREAK
1045 { 312, 2, 0, 0, 1, 0, 0, 152, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #312 = BRANCH_COND_i32
1046 { 311, 2, 0, 0, 1, 0, 0, 152, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #311 = BRANCH_COND_f32
1047 { 310, 1, 0, 0, 1, 0, 0, 0, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #310 = BRANCH
1048 { 309, 4, 1, 0, 0, 0, 0, 148, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #309 = G_UBFX
1049 { 308, 4, 1, 0, 0, 0, 0, 148, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #308 = G_SBFX
1050 { 307, 2, 1, 0, 0, 0, 0, 61, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #307 = G_VECREDUCE_UMIN
1051 { 306, 2, 1, 0, 0, 0, 0, 61, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #306 = G_VECREDUCE_UMAX
1052 { 305, 2, 1, 0, 0, 0, 0, 61, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #305 = G_VECREDUCE_SMIN
1053 { 304, 2, 1, 0, 0, 0, 0, 61, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #304 = G_VECREDUCE_SMAX
1054 { 303, 2, 1, 0, 0, 0, 0, 61, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #303 = G_VECREDUCE_XOR
1055 { 302, 2, 1, 0, 0, 0, 0, 61, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #302 = G_VECREDUCE_OR
1056 { 301, 2, 1, 0, 0, 0, 0, 61, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #301 = G_VECREDUCE_AND
1057 { 300, 2, 1, 0, 0, 0, 0, 61, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #300 = G_VECREDUCE_MUL
1058 { 299, 2, 1, 0, 0, 0, 0, 61, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #299 = G_VECREDUCE_ADD
1059 { 298, 2, 1, 0, 0, 0, 0, 61, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #298 = G_VECREDUCE_FMINIMUM
1060 { 297, 2, 1, 0, 0, 0, 0, 61, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #297 = G_VECREDUCE_FMAXIMUM
1061 { 296, 2, 1, 0, 0, 0, 0, 61, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #296 = G_VECREDUCE_FMIN
1062 { 295, 2, 1, 0, 0, 0, 0, 61, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #295 = G_VECREDUCE_FMAX
1063 { 294, 2, 1, 0, 0, 0, 0, 61, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #294 = G_VECREDUCE_FMUL
1064 { 293, 2, 1, 0, 0, 0, 0, 61, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #293 = G_VECREDUCE_FADD
1065 { 292, 3, 1, 0, 0, 0, 0, 131, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #292 = G_VECREDUCE_SEQ_FMUL
1066 { 291, 3, 1, 0, 0, 0, 0, 131, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #291 = G_VECREDUCE_SEQ_FADD
1067 { 290, 1, 0, 0, 0, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #290 = G_UBSANTRAP
1068 { 289, 0, 0, 0, 0, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #289 = G_DEBUGTRAP
1069 { 288, 0, 0, 0, 0, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #288 = G_TRAP
1070 { 287, 3, 0, 0, 0, 0, 0, 58, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #287 = G_BZERO
1071 { 286, 4, 0, 0, 0, 0, 0, 144, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #286 = G_MEMSET
1072 { 285, 4, 0, 0, 0, 0, 0, 144, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #285 = G_MEMMOVE
1073 { 284, 3, 0, 0, 0, 0, 0, 131, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #284 = G_MEMCPY_INLINE
1074 { 283, 4, 0, 0, 0, 0, 0, 144, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #283 = G_MEMCPY
1075 { 282, 2, 0, 0, 0, 0, 0, 142, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #282 = G_WRITE_REGISTER
1076 { 281, 2, 1, 0, 0, 0, 0, 51, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #281 = G_READ_REGISTER
1077 { 280, 3, 1, 0, 0, 0, 0, 101, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #280 = G_STRICT_FLDEXP
1078 { 279, 2, 1, 0, 0, 0, 0, 67, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #279 = G_STRICT_FSQRT
1079 { 278, 4, 1, 0, 0, 0, 0, 46, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #278 = G_STRICT_FMA
1080 { 277, 3, 1, 0, 0, 0, 0, 43, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #277 = G_STRICT_FREM
1081 { 276, 3, 1, 0, 0, 0, 0, 43, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #276 = G_STRICT_FDIV
1082 { 275, 3, 1, 0, 0, 0, 0, 43, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #275 = G_STRICT_FMUL
1083 { 274, 3, 1, 0, 0, 0, 0, 43, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #274 = G_STRICT_FSUB
1084 { 273, 3, 1, 0, 0, 0, 0, 43, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #273 = G_STRICT_FADD
1085 { 272, 1, 0, 0, 0, 0, 0, 50, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #272 = G_STACKRESTORE
1086 { 271, 1, 1, 0, 0, 0, 0, 50, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #271 = G_STACKSAVE
1087 { 270, 3, 1, 0, 0, 0, 0, 69, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #270 = G_DYN_STACKALLOC
1088 { 269, 2, 1, 0, 0, 0, 0, 51, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #269 = G_JUMP_TABLE
1089 { 268, 2, 1, 0, 0, 0, 0, 51, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #268 = G_BLOCK_ADDR
1090 { 267, 2, 1, 0, 0, 0, 0, 61, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #267 = G_ADDRSPACE_CAST
1091 { 266, 2, 1, 0, 0, 0, 0, 67, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #266 = G_FNEARBYINT
1092 { 265, 2, 1, 0, 0, 0, 0, 67, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #265 = G_FRINT
1093 { 264, 2, 1, 0, 0, 0, 0, 67, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #264 = G_FFLOOR
1094 { 263, 2, 1, 0, 0, 0, 0, 67, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #263 = G_FSQRT
1095 { 262, 2, 1, 0, 0, 0, 0, 67, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #262 = G_FTANH
1096 { 261, 2, 1, 0, 0, 0, 0, 67, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #261 = G_FSINH
1097 { 260, 2, 1, 0, 0, 0, 0, 67, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #260 = G_FCOSH
1098 { 259, 3, 1, 0, 0, 0, 0, 43, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #259 = G_FATAN2
1099 { 258, 2, 1, 0, 0, 0, 0, 67, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #258 = G_FATAN
1100 { 257, 2, 1, 0, 0, 0, 0, 67, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #257 = G_FASIN
1101 { 256, 2, 1, 0, 0, 0, 0, 67, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #256 = G_FACOS
1102 { 255, 2, 1, 0, 0, 0, 0, 67, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #255 = G_FTAN
1103 { 254, 3, 2, 0, 0, 0, 0, 43, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #254 = G_FSINCOS
1104 { 253, 2, 1, 0, 0, 0, 0, 67, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #253 = G_FSIN
1105 { 252, 2, 1, 0, 0, 0, 0, 67, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #252 = G_FCOS
1106 { 251, 2, 1, 0, 0, 0, 0, 67, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #251 = G_FCEIL
1107 { 250, 2, 1, 0, 0, 0, 0, 67, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #250 = G_BITREVERSE
1108 { 249, 2, 1, 0, 0, 0, 0, 67, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #249 = G_BSWAP
1109 { 248, 2, 1, 0, 0, 0, 0, 61, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #248 = G_CTPOP
1110 { 247, 2, 1, 0, 0, 0, 0, 61, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #247 = G_CTLZ_ZERO_UNDEF
1111 { 246, 2, 1, 0, 0, 0, 0, 61, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #246 = G_CTLZ
1112 { 245, 2, 1, 0, 0, 0, 0, 61, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #245 = G_CTTZ_ZERO_UNDEF
1113 { 244, 2, 1, 0, 0, 0, 0, 61, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #244 = G_CTTZ
1114 { 243, 4, 1, 0, 0, 0, 0, 138, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #243 = G_VECTOR_COMPRESS
1115 { 242, 2, 1, 0, 0, 0, 0, 51, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #242 = G_STEP_VECTOR
1116 { 241, 2, 1, 0, 0, 0, 0, 61, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #241 = G_SPLAT_VECTOR
1117 { 240, 4, 1, 0, 0, 0, 0, 134, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #240 = G_SHUFFLE_VECTOR
1118 { 239, 3, 1, 0, 0, 0, 0, 131, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #239 = G_EXTRACT_VECTOR_ELT
1119 { 238, 4, 1, 0, 0, 0, 0, 127, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #238 = G_INSERT_VECTOR_ELT
1120 { 237, 3, 1, 0, 0, 0, 0, 58, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #237 = G_EXTRACT_SUBVECTOR
1121 { 236, 4, 1, 0, 0, 0, 0, 63, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #236 = G_INSERT_SUBVECTOR
1122 { 235, 2, 1, 0, 0, 0, 0, 51, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #235 = G_VSCALE
1123 { 234, 3, 0, 0, 0, 0, 0, 124, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #234 = G_BRJT
1124 { 233, 1, 0, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #233 = G_BR
1125 { 232, 2, 1, 0, 0, 0, 0, 61, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #232 = G_LLROUND
1126 { 231, 2, 1, 0, 0, 0, 0, 61, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #231 = G_LROUND
1127 { 230, 2, 1, 0, 0, 0, 0, 67, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #230 = G_ABS
1128 { 229, 3, 1, 0, 0, 0, 0, 43, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #229 = G_UMAX
1129 { 228, 3, 1, 0, 0, 0, 0, 43, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #228 = G_UMIN
1130 { 227, 3, 1, 0, 0, 0, 0, 43, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #227 = G_SMAX
1131 { 226, 3, 1, 0, 0, 0, 0, 43, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #226 = G_SMIN
1132 { 225, 3, 1, 0, 0, 0, 0, 101, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #225 = G_PTRMASK
1133 { 224, 3, 1, 0, 0, 0, 0, 101, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #224 = G_PTR_ADD
1134 { 223, 0, 0, 0, 0, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #223 = G_RESET_FPMODE
1135 { 222, 1, 0, 0, 0, 0, 0, 50, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #222 = G_SET_FPMODE
1136 { 221, 1, 1, 0, 0, 0, 0, 50, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #221 = G_GET_FPMODE
1137 { 220, 0, 0, 0, 0, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #220 = G_RESET_FPENV
1138 { 219, 1, 0, 0, 0, 0, 0, 50, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #219 = G_SET_FPENV
1139 { 218, 1, 1, 0, 0, 0, 0, 50, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #218 = G_GET_FPENV
1140 { 217, 3, 1, 0, 0, 0, 0, 43, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #217 = G_FMAXIMUMNUM
1141 { 216, 3, 1, 0, 0, 0, 0, 43, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #216 = G_FMINIMUMNUM
1142 { 215, 3, 1, 0, 0, 0, 0, 43, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #215 = G_FMAXIMUM
1143 { 214, 3, 1, 0, 0, 0, 0, 43, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #214 = G_FMINIMUM
1144 { 213, 3, 1, 0, 0, 0, 0, 43, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #213 = G_FMAXNUM_IEEE
1145 { 212, 3, 1, 0, 0, 0, 0, 43, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #212 = G_FMINNUM_IEEE
1146 { 211, 3, 1, 0, 0, 0, 0, 43, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #211 = G_FMAXNUM
1147 { 210, 3, 1, 0, 0, 0, 0, 43, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #210 = G_FMINNUM
1148 { 209, 2, 1, 0, 0, 0, 0, 67, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #209 = G_FCANONICALIZE
1149 { 208, 3, 1, 0, 0, 0, 0, 98, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #208 = G_IS_FPCLASS
1150 { 207, 3, 1, 0, 0, 0, 0, 101, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #207 = G_FCOPYSIGN
1151 { 206, 2, 1, 0, 0, 0, 0, 67, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #206 = G_FABS
1152 { 205, 2, 1, 0, 0, 0, 0, 61, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #205 = G_FPTOUI_SAT
1153 { 204, 2, 1, 0, 0, 0, 0, 61, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #204 = G_FPTOSI_SAT
1154 { 203, 2, 1, 0, 0, 0, 0, 61, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #203 = G_UITOFP
1155 { 202, 2, 1, 0, 0, 0, 0, 61, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #202 = G_SITOFP
1156 { 201, 2, 1, 0, 0, 0, 0, 61, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #201 = G_FPTOUI
1157 { 200, 2, 1, 0, 0, 0, 0, 61, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #200 = G_FPTOSI
1158 { 199, 2, 1, 0, 0, 0, 0, 61, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #199 = G_FPTRUNC
1159 { 198, 2, 1, 0, 0, 0, 0, 61, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #198 = G_FPEXT
1160 { 197, 2, 1, 0, 0, 0, 0, 67, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #197 = G_FNEG
1161 { 196, 3, 2, 0, 0, 0, 0, 91, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #196 = G_FFREXP
1162 { 195, 3, 1, 0, 0, 0, 0, 101, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #195 = G_FLDEXP
1163 { 194, 2, 1, 0, 0, 0, 0, 67, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #194 = G_FLOG10
1164 { 193, 2, 1, 0, 0, 0, 0, 67, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #193 = G_FLOG2
1165 { 192, 2, 1, 0, 0, 0, 0, 67, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #192 = G_FLOG
1166 { 191, 2, 1, 0, 0, 0, 0, 67, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #191 = G_FEXP10
1167 { 190, 2, 1, 0, 0, 0, 0, 67, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #190 = G_FEXP2
1168 { 189, 2, 1, 0, 0, 0, 0, 67, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #189 = G_FEXP
1169 { 188, 3, 1, 0, 0, 0, 0, 101, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #188 = G_FPOWI
1170 { 187, 3, 1, 0, 0, 0, 0, 43, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #187 = G_FPOW
1171 { 186, 3, 1, 0, 0, 0, 0, 43, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #186 = G_FREM
1172 { 185, 3, 1, 0, 0, 0, 0, 43, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #185 = G_FDIV
1173 { 184, 4, 1, 0, 0, 0, 0, 46, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #184 = G_FMAD
1174 { 183, 4, 1, 0, 0, 0, 0, 46, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #183 = G_FMA
1175 { 182, 3, 1, 0, 0, 0, 0, 43, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #182 = G_FMUL
1176 { 181, 3, 1, 0, 0, 0, 0, 43, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #181 = G_FSUB
1177 { 180, 3, 1, 0, 0, 0, 0, 43, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #180 = G_FADD
1178 { 179, 4, 1, 0, 0, 0, 0, 120, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #179 = G_UDIVFIXSAT
1179 { 178, 4, 1, 0, 0, 0, 0, 120, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #178 = G_SDIVFIXSAT
1180 { 177, 4, 1, 0, 0, 0, 0, 120, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #177 = G_UDIVFIX
1181 { 176, 4, 1, 0, 0, 0, 0, 120, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #176 = G_SDIVFIX
1182 { 175, 4, 1, 0, 0, 0, 0, 120, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #175 = G_UMULFIXSAT
1183 { 174, 4, 1, 0, 0, 0, 0, 120, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #174 = G_SMULFIXSAT
1184 { 173, 4, 1, 0, 0, 0, 0, 120, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #173 = G_UMULFIX
1185 { 172, 4, 1, 0, 0, 0, 0, 120, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #172 = G_SMULFIX
1186 { 171, 3, 1, 0, 0, 0, 0, 101, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #171 = G_SSHLSAT
1187 { 170, 3, 1, 0, 0, 0, 0, 101, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #170 = G_USHLSAT
1188 { 169, 3, 1, 0, 0, 0, 0, 43, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #169 = G_SSUBSAT
1189 { 168, 3, 1, 0, 0, 0, 0, 43, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #168 = G_USUBSAT
1190 { 167, 3, 1, 0, 0, 0, 0, 43, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #167 = G_SADDSAT
1191 { 166, 3, 1, 0, 0, 0, 0, 43, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #166 = G_UADDSAT
1192 { 165, 3, 1, 0, 0, 0, 0, 43, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #165 = G_SMULH
1193 { 164, 3, 1, 0, 0, 0, 0, 43, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #164 = G_UMULH
1194 { 163, 4, 2, 0, 0, 0, 0, 87, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #163 = G_SMULO
1195 { 162, 4, 2, 0, 0, 0, 0, 87, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #162 = G_UMULO
1196 { 161, 5, 2, 0, 0, 0, 0, 115, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #161 = G_SSUBE
1197 { 160, 4, 2, 0, 0, 0, 0, 87, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #160 = G_SSUBO
1198 { 159, 5, 2, 0, 0, 0, 0, 115, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #159 = G_SADDE
1199 { 158, 4, 2, 0, 0, 0, 0, 87, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #158 = G_SADDO
1200 { 157, 5, 2, 0, 0, 0, 0, 115, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #157 = G_USUBE
1201 { 156, 4, 2, 0, 0, 0, 0, 87, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #156 = G_USUBO
1202 { 155, 5, 2, 0, 0, 0, 0, 115, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #155 = G_UADDE
1203 { 154, 4, 2, 0, 0, 0, 0, 87, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #154 = G_UADDO
1204 { 153, 4, 1, 0, 0, 0, 0, 87, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #153 = G_SELECT
1205 { 152, 3, 1, 0, 0, 0, 0, 112, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #152 = G_UCMP
1206 { 151, 3, 1, 0, 0, 0, 0, 112, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #151 = G_SCMP
1207 { 150, 4, 1, 0, 0, 0, 0, 108, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #150 = G_FCMP
1208 { 149, 4, 1, 0, 0, 0, 0, 108, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #149 = G_ICMP
1209 { 148, 3, 1, 0, 0, 0, 0, 101, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #148 = G_ROTL
1210 { 147, 3, 1, 0, 0, 0, 0, 101, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #147 = G_ROTR
1211 { 146, 4, 1, 0, 0, 0, 0, 104, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #146 = G_FSHR
1212 { 145, 4, 1, 0, 0, 0, 0, 104, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #145 = G_FSHL
1213 { 144, 3, 1, 0, 0, 0, 0, 101, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #144 = G_ASHR
1214 { 143, 3, 1, 0, 0, 0, 0, 101, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #143 = G_LSHR
1215 { 142, 3, 1, 0, 0, 0, 0, 101, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #142 = G_SHL
1216 { 141, 2, 1, 0, 0, 0, 0, 61, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #141 = G_ZEXT
1217 { 140, 3, 1, 0, 0, 0, 0, 40, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #140 = G_SEXT_INREG
1218 { 139, 2, 1, 0, 0, 0, 0, 61, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #139 = G_SEXT
1219 { 138, 3, 1, 0, 0, 0, 0, 98, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #138 = G_VAARG
1220 { 137, 1, 0, 0, 0, 0, 0, 50, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #137 = G_VASTART
1221 { 136, 2, 1, 0, 0, 0, 0, 51, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #136 = G_FCONSTANT
1222 { 135, 2, 1, 0, 0, 0, 0, 51, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #135 = G_CONSTANT
1223 { 134, 2, 1, 0, 0, 0, 0, 61, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #134 = G_TRUNC
1224 { 133, 2, 1, 0, 0, 0, 0, 61, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #133 = G_ANYEXT
1225 { 132, 1, 0, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #132 = G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
1226 { 131, 1, 0, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #131 = G_INTRINSIC_CONVERGENT
1227 { 130, 1, 0, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #130 = G_INTRINSIC_W_SIDE_EFFECTS
1228 { 129, 1, 0, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #129 = G_INTRINSIC
1229 { 128, 0, 0, 0, 0, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #128 = G_INVOKE_REGION_START
1230 { 127, 1, 0, 0, 0, 0, 0, 50, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #127 = G_BRINDIRECT
1231 { 126, 2, 0, 0, 0, 0, 0, 51, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #126 = G_BRCOND
1232 { 125, 4, 0, 0, 0, 0, 0, 94, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #125 = G_PREFETCH
1233 { 124, 2, 0, 0, 0, 0, 0, 21, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #124 = G_FENCE
1234 { 123, 3, 1, 0, 0, 0, 0, 91, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #123 = G_ATOMICRMW_USUB_SAT
1235 { 122, 3, 1, 0, 0, 0, 0, 91, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #122 = G_ATOMICRMW_USUB_COND
1236 { 121, 3, 1, 0, 0, 0, 0, 91, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #121 = G_ATOMICRMW_UDEC_WRAP
1237 { 120, 3, 1, 0, 0, 0, 0, 91, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #120 = G_ATOMICRMW_UINC_WRAP
1238 { 119, 3, 1, 0, 0, 0, 0, 91, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #119 = G_ATOMICRMW_FMINIMUM
1239 { 118, 3, 1, 0, 0, 0, 0, 91, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #118 = G_ATOMICRMW_FMAXIMUM
1240 { 117, 3, 1, 0, 0, 0, 0, 91, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #117 = G_ATOMICRMW_FMIN
1241 { 116, 3, 1, 0, 0, 0, 0, 91, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #116 = G_ATOMICRMW_FMAX
1242 { 115, 3, 1, 0, 0, 0, 0, 91, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #115 = G_ATOMICRMW_FSUB
1243 { 114, 3, 1, 0, 0, 0, 0, 91, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #114 = G_ATOMICRMW_FADD
1244 { 113, 3, 1, 0, 0, 0, 0, 91, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #113 = G_ATOMICRMW_UMIN
1245 { 112, 3, 1, 0, 0, 0, 0, 91, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #112 = G_ATOMICRMW_UMAX
1246 { 111, 3, 1, 0, 0, 0, 0, 91, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #111 = G_ATOMICRMW_MIN
1247 { 110, 3, 1, 0, 0, 0, 0, 91, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #110 = G_ATOMICRMW_MAX
1248 { 109, 3, 1, 0, 0, 0, 0, 91, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #109 = G_ATOMICRMW_XOR
1249 { 108, 3, 1, 0, 0, 0, 0, 91, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #108 = G_ATOMICRMW_OR
1250 { 107, 3, 1, 0, 0, 0, 0, 91, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #107 = G_ATOMICRMW_NAND
1251 { 106, 3, 1, 0, 0, 0, 0, 91, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #106 = G_ATOMICRMW_AND
1252 { 105, 3, 1, 0, 0, 0, 0, 91, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #105 = G_ATOMICRMW_SUB
1253 { 104, 3, 1, 0, 0, 0, 0, 91, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #104 = G_ATOMICRMW_ADD
1254 { 103, 3, 1, 0, 0, 0, 0, 91, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #103 = G_ATOMICRMW_XCHG
1255 { 102, 4, 1, 0, 0, 0, 0, 87, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #102 = G_ATOMIC_CMPXCHG
1256 { 101, 5, 2, 0, 0, 0, 0, 82, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #101 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
1257 { 100, 5, 1, 0, 0, 0, 0, 77, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #100 = G_INDEXED_STORE
1258 { 99, 2, 0, 0, 0, 0, 0, 61, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #99 = G_STORE
1259 { 98, 5, 2, 0, 0, 0, 0, 72, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #98 = G_INDEXED_ZEXTLOAD
1260 { 97, 5, 2, 0, 0, 0, 0, 72, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #97 = G_INDEXED_SEXTLOAD
1261 { 96, 5, 2, 0, 0, 0, 0, 72, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #96 = G_INDEXED_LOAD
1262 { 95, 2, 1, 0, 0, 0, 0, 61, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #95 = G_ZEXTLOAD
1263 { 94, 2, 1, 0, 0, 0, 0, 61, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #94 = G_SEXTLOAD
1264 { 93, 2, 1, 0, 0, 0, 0, 61, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #93 = G_LOAD
1265 { 92, 1, 1, 0, 0, 0, 0, 50, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #92 = G_READSTEADYCOUNTER
1266 { 91, 1, 1, 0, 0, 0, 0, 50, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #91 = G_READCYCLECOUNTER
1267 { 90, 2, 1, 0, 0, 0, 0, 67, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #90 = G_INTRINSIC_ROUNDEVEN
1268 { 89, 2, 1, 0, 0, 0, 0, 61, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #89 = G_INTRINSIC_LLRINT
1269 { 88, 2, 1, 0, 0, 0, 0, 61, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #88 = G_INTRINSIC_LRINT
1270 { 87, 2, 1, 0, 0, 0, 0, 67, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #87 = G_INTRINSIC_ROUND
1271 { 86, 2, 1, 0, 0, 0, 0, 67, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #86 = G_INTRINSIC_TRUNC
1272 { 85, 3, 1, 0, 0, 0, 0, 69, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #85 = G_INTRINSIC_FPTRUNC_ROUND
1273 { 84, 2, 1, 0, 0, 0, 0, 67, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #84 = G_CONSTANT_FOLD_BARRIER
1274 { 83, 2, 1, 0, 0, 0, 0, 67, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #83 = G_FREEZE
1275 { 82, 2, 1, 0, 0, 0, 0, 61, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #82 = G_BITCAST
1276 { 81, 2, 1, 0, 0, 0, 0, 61, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #81 = G_INTTOPTR
1277 { 80, 2, 1, 0, 0, 0, 0, 61, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #80 = G_PTRTOINT
1278 { 79, 2, 1, 0, 0, 0, 0, 61, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #79 = G_CONCAT_VECTORS
1279 { 78, 2, 1, 0, 0, 0, 0, 61, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #78 = G_BUILD_VECTOR_TRUNC
1280 { 77, 2, 1, 0, 0, 0, 0, 61, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #77 = G_BUILD_VECTOR
1281 { 76, 2, 1, 0, 0, 0, 0, 61, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #76 = G_MERGE_VALUES
1282 { 75, 4, 1, 0, 0, 0, 0, 63, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #75 = G_INSERT
1283 { 74, 2, 1, 0, 0, 0, 0, 61, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #74 = G_UNMERGE_VALUES
1284 { 73, 3, 1, 0, 0, 0, 0, 58, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #73 = G_EXTRACT
1285 { 72, 2, 1, 0, 0, 0, 0, 51, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #72 = G_CONSTANT_POOL
1286 { 71, 5, 1, 0, 0, 0, 0, 53, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #71 = G_PTRAUTH_GLOBAL_VALUE
1287 { 70, 2, 1, 0, 0, 0, 0, 51, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #70 = G_GLOBAL_VALUE
1288 { 69, 2, 1, 0, 0, 0, 0, 51, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #69 = G_FRAME_INDEX
1289 { 68, 1, 1, 0, 0, 0, 0, 50, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #68 = G_PHI
1290 { 67, 1, 1, 0, 0, 0, 0, 50, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #67 = G_IMPLICIT_DEF
1291 { 66, 3, 1, 0, 0, 0, 0, 43, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #66 = G_ABDU
1292 { 65, 3, 1, 0, 0, 0, 0, 43, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #65 = G_ABDS
1293 { 64, 3, 1, 0, 0, 0, 0, 43, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #64 = G_XOR
1294 { 63, 3, 1, 0, 0, 0, 0, 43, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #63 = G_OR
1295 { 62, 3, 1, 0, 0, 0, 0, 43, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #62 = G_AND
1296 { 61, 4, 2, 0, 0, 0, 0, 46, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #61 = G_UDIVREM
1297 { 60, 4, 2, 0, 0, 0, 0, 46, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #60 = G_SDIVREM
1298 { 59, 3, 1, 0, 0, 0, 0, 43, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #59 = G_UREM
1299 { 58, 3, 1, 0, 0, 0, 0, 43, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #58 = G_SREM
1300 { 57, 3, 1, 0, 0, 0, 0, 43, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #57 = G_UDIV
1301 { 56, 3, 1, 0, 0, 0, 0, 43, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #56 = G_SDIV
1302 { 55, 3, 1, 0, 0, 0, 0, 43, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #55 = G_MUL
1303 { 54, 3, 1, 0, 0, 0, 0, 43, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #54 = G_SUB
1304 { 53, 3, 1, 0, 0, 0, 0, 43, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #53 = G_ADD
1305 { 52, 3, 1, 0, 0, 0, 0, 40, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #52 = G_ASSERT_ALIGN
1306 { 51, 3, 1, 0, 0, 0, 0, 40, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #51 = G_ASSERT_ZEXT
1307 { 50, 3, 1, 0, 0, 0, 0, 40, R600ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #50 = G_ASSERT_SEXT
1308 { 49, 1, 0, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #49 = CONVERGENCECTRL_GLUE
1309 { 48, 2, 1, 0, 0, 0, 0, 13, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #48 = CONVERGENCECTRL_LOOP
1310 { 47, 1, 1, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #47 = CONVERGENCECTRL_ANCHOR
1311 { 46, 1, 1, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #46 = CONVERGENCECTRL_ENTRY
1312 { 45, 1, 0, 0, 0, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #45 = JUMP_TABLE_DEBUG_INFO
1313 { 44, 0, 0, 0, 0, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #44 = MEMBARRIER
1314 { 43, 0, 0, 0, 0, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #43 = FAKE_USE
1315 { 42, 0, 0, 0, 0, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #42 = ICALL_BRANCH_FUNNEL
1316 { 41, 3, 0, 0, 0, 0, 0, 37, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #41 = PATCHABLE_TYPED_EVENT_CALL
1317 { 40, 2, 0, 0, 0, 0, 0, 35, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #40 = PATCHABLE_EVENT_CALL
1318 { 39, 0, 0, 0, 0, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #39 = PATCHABLE_TAIL_CALL
1319 { 38, 0, 0, 0, 0, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #38 = PATCHABLE_FUNCTION_EXIT
1320 { 37, 0, 0, 0, 0, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #37 = PATCHABLE_RET
1321 { 36, 0, 0, 0, 0, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #36 = PATCHABLE_FUNCTION_ENTER
1322 { 35, 0, 0, 0, 0, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #35 = PATCHABLE_OP
1323 { 34, 1, 1, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #34 = FAULTING_OP
1324 { 33, 2, 0, 0, 0, 0, 0, 33, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #33 = LOCAL_ESCAPE
1325 { 32, 0, 0, 0, 0, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #32 = STATEPOINT
1326 { 31, 3, 1, 0, 0, 0, 0, 30, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #31 = PREALLOCATED_ARG
1327 { 30, 1, 0, 0, 0, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #30 = PREALLOCATED_SETUP
1328 { 29, 1, 1, 0, 0, 0, 0, 29, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #29 = LOAD_STACK_GUARD
1329 { 28, 6, 1, 0, 0, 0, 0, 23, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #28 = PATCHPOINT
1330 { 27, 0, 0, 0, 0, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #27 = FENTRY_CALL
1331 { 26, 2, 0, 0, 0, 0, 0, 21, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #26 = STACKMAP
1332 { 25, 2, 1, 0, 0, 0, 0, 19, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #25 = ARITH_FENCE
1333 { 24, 4, 0, 0, 0, 0, 0, 15, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #24 = PSEUDO_PROBE
1334 { 23, 1, 0, 0, 0, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #23 = LIFETIME_END
1335 { 22, 1, 0, 0, 0, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #22 = LIFETIME_START
1336 { 21, 0, 0, 0, 0, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #21 = BUNDLE
1337 { 20, 2, 1, 0, 0, 0, 0, 13, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #20 = COPY
1338 { 19, 2, 1, 0, 0, 0, 0, 13, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #19 = REG_SEQUENCE
1339 { 18, 1, 0, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #18 = DBG_LABEL
1340 { 17, 0, 0, 0, 0, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #17 = DBG_PHI
1341 { 16, 0, 0, 0, 0, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #16 = DBG_INSTR_REF
1342 { 15, 0, 0, 0, 0, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #15 = DBG_VALUE_LIST
1343 { 14, 0, 0, 0, 0, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #14 = DBG_VALUE
1344 { 13, 3, 1, 0, 0, 0, 0, 2, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #13 = COPY_TO_REGCLASS
1345 { 12, 4, 1, 0, 0, 0, 0, 9, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #12 = SUBREG_TO_REG
1346 { 11, 1, 1, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #11 = INIT_UNDEF
1347 { 10, 1, 1, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #10 = IMPLICIT_DEF
1348 { 9, 4, 1, 0, 0, 0, 0, 5, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #9 = INSERT_SUBREG
1349 { 8, 3, 1, 0, 0, 0, 0, 2, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #8 = EXTRACT_SUBREG
1350 { 7, 0, 0, 0, 0, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #7 = KILL
1351 { 6, 1, 0, 0, 0, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #6 = ANNOTATION_LABEL
1352 { 5, 1, 0, 0, 0, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #5 = GC_LABEL
1353 { 4, 1, 0, 0, 0, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #4 = EH_LABEL
1354 { 3, 1, 0, 0, 0, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #3 = CFI_INSTRUCTION
1355 { 2, 0, 0, 0, 0, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2 = INLINEASM_BR
1356 { 1, 0, 0, 0, 0, 0, 0, 1, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #1 = INLINEASM
1357 { 0, 1, 1, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #0 = PHI
1358 }, {
1359 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1360 /* 1 */
1361 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1362 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1363 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1364 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1365 /* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1366 /* 15 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1367 /* 19 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
1368 /* 21 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1369 /* 23 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1370 /* 29 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
1371 /* 30 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1372 /* 33 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1373 /* 35 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1374 /* 37 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1375 /* 40 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1376 /* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1377 /* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1378 /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1379 /* 51 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1380 /* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1381 /* 58 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1382 /* 61 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1383 /* 63 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1384 /* 67 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1385 /* 69 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1386 /* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1387 /* 77 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1388 /* 82 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1389 /* 87 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1390 /* 91 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1391 /* 94 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1392 /* 98 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1393 /* 101 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1394 /* 104 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1395 /* 108 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1396 /* 112 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1397 /* 115 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1398 /* 120 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1399 /* 124 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1400 /* 127 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1401 /* 131 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1402 /* 134 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1403 /* 138 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1404 /* 142 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1405 /* 144 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1406 /* 148 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1407 /* 152 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1408 /* 154 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1409 /* 156 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1410 /* 157 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1411 /* 159 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1412 /* 161 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_ZRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_ZRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1413 /* 232 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Predicate_BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1414 /* 234 */ { R600::R600_Predicate_BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1415 /* 238 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg64VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1416 /* 241 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1417 /* 244 */ { R600::R600_Reg64VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg64VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1418 /* 248 */ { R600::R600_Reg128VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1419 /* 252 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1420 /* 256 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1421 /* 263 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1422 /* 284 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1423 /* 298 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1424 /* 317 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1425 /* 326 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1426 /* 333 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1427 /* 342 */ { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1428 /* 347 */ { R600::R600_TReg32_ZRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1429 /* 352 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1430 /* 354 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1431 /* 363 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1432 /* 373 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1433 /* 380 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1434 /* 392 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1435 /* 405 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1436 /* 408 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1437 /* 410 */ { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1438 /* 412 */ { R600::R600_Reg64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1439 /* 414 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1440 /* 418 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1441 /* 421 */ { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1442 /* 424 */ { R600::R600_Reg64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1443 /* 427 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1444 /* 446 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1445 /* 450 */ { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1446 /* 454 */ { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1447 /* 458 */ { R600::R600_Reg64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1448 }, {
1449 /* 0 */
1450 }
1451};
1452
1453
1454#ifdef __GNUC__
1455#pragma GCC diagnostic push
1456#pragma GCC diagnostic ignored "-Woverlength-strings"
1457#endif
1458extern const char R600InstrNameData[] = {
1459 /* 0 */ "CF_TC_R600\000"
1460 /* 11 */ "CF_VC_R600\000"
1461 /* 22 */ "CF_END_R600\000"
1462 /* 34 */ "CF_ELSE_R600\000"
1463 /* 47 */ "CF_PUSH_ELSE_R600\000"
1464 /* 65 */ "CF_CONTINUE_R600\000"
1465 /* 82 */ "FNEG_R600\000"
1466 /* 92 */ "LOOP_BREAK_R600\000"
1467 /* 108 */ "CF_JUMP_R600\000"
1468 /* 121 */ "END_LOOP_R600\000"
1469 /* 135 */ "WHILE_LOOP_R600\000"
1470 /* 151 */ "POP_R600\000"
1471 /* 160 */ "FABS_R600\000"
1472 /* 170 */ "CF_CALL_FS_R600\000"
1473 /* 186 */ "DOT4_r600\000"
1474 /* 196 */ "MULADD_r600\000"
1475 /* 208 */ "LOG_CLAMPED_r600\000"
1476 /* 225 */ "RECIP_CLAMPED_r600\000"
1477 /* 244 */ "RECIPSQRT_CLAMPED_r600\000"
1478 /* 267 */ "CNDE_r600\000"
1479 /* 277 */ "MULADD_IEEE_r600\000"
1480 /* 294 */ "LOG_IEEE_r600\000"
1481 /* 308 */ "RECIP_IEEE_r600\000"
1482 /* 324 */ "EXP_IEEE_r600\000"
1483 /* 338 */ "RECIPSQRT_IEEE_r600\000"
1484 /* 358 */ "CNDGE_r600\000"
1485 /* 369 */ "LSHL_r600\000"
1486 /* 379 */ "SIN_r600\000"
1487 /* 388 */ "ASHR_r600\000"
1488 /* 398 */ "LSHR_r600\000"
1489 /* 408 */ "COS_r600\000"
1490 /* 417 */ "CNDGT_r600\000"
1491 /* 428 */ "MUL_LIT_r600\000"
1492 /* 441 */ "UINT_TO_FLT_r600\000"
1493 /* 458 */ "MULHI_UINT_r600\000"
1494 /* 474 */ "MULLO_UINT_r600\000"
1495 /* 490 */ "FLT_TO_UINT_r600\000"
1496 /* 507 */ "RECIP_UINT_r600\000"
1497 /* 523 */ "MULHI_INT_r600\000"
1498 /* 538 */ "MULLO_INT_r600\000"
1499 /* 553 */ "FLT_TO_INT_r600\000"
1500 /* 569 */ "SIN_r700\000"
1501 /* 578 */ "COS_r700\000"
1502 /* 587 */ "G_FLOG10\000"
1503 /* 596 */ "G_FEXP10\000"
1504 /* 605 */ "SETGE_DX10\000"
1505 /* 616 */ "SETNE_DX10\000"
1506 /* 627 */ "SETE_DX10\000"
1507 /* 637 */ "MIN_DX10\000"
1508 /* 646 */ "SETGT_DX10\000"
1509 /* 657 */ "MAX_DX10\000"
1510 /* 666 */ "INTERP_LOAD_P0\000"
1511 /* 681 */ "RAT_STORE_DWORD32\000"
1512 /* 699 */ "MOV_IMM_F32\000"
1513 /* 711 */ "MOV_IMM_I32\000"
1514 /* 723 */ "FLT16_TO_FLT32\000"
1515 /* 738 */ "CONTINUEC_f32\000"
1516 /* 752 */ "IFC_f32\000"
1517 /* 760 */ "BREAKC_f32\000"
1518 /* 771 */ "BRANCH_COND_f32\000"
1519 /* 787 */ "CONTINUE_LOGICALZ_f32\000"
1520 /* 809 */ "IF_LOGICALZ_f32\000"
1521 /* 825 */ "BREAK_LOGICALZ_f32\000"
1522 /* 844 */ "CONTINUE_LOGICALNZ_f32\000"
1523 /* 867 */ "IF_LOGICALNZ_f32\000"
1524 /* 884 */ "BREAK_LOGICALNZ_f32\000"
1525 /* 904 */ "CONTINUEC_i32\000"
1526 /* 918 */ "IFC_i32\000"
1527 /* 926 */ "BREAKC_i32\000"
1528 /* 937 */ "BRANCH_COND_i32\000"
1529 /* 953 */ "CONTINUE_LOGICALZ_i32\000"
1530 /* 975 */ "IF_LOGICALZ_i32\000"
1531 /* 991 */ "BREAK_LOGICALZ_i32\000"
1532 /* 1010 */ "CONTINUE_LOGICALNZ_i32\000"
1533 /* 1033 */ "IF_LOGICALNZ_i32\000"
1534 /* 1050 */ "BREAK_LOGICALNZ_i32\000"
1535 /* 1070 */ "G_FLOG2\000"
1536 /* 1078 */ "G_FATAN2\000"
1537 /* 1087 */ "G_FEXP2\000"
1538 /* 1095 */ "R600_EXTRACT_ELT_V2\000"
1539 /* 1115 */ "R600_INSERT_ELT_V2\000"
1540 /* 1134 */ "MULHI_UINT_cm24\000"
1541 /* 1150 */ "MULHI_INT_cm24\000"
1542 /* 1165 */ "RAT_STORE_DWORD64\000"
1543 /* 1183 */ "R600_EXTRACT_ELT_V4\000"
1544 /* 1203 */ "R600_INSERT_ELT_V4\000"
1545 /* 1222 */ "DOT_4\000"
1546 /* 1228 */ "FLT32_TO_FLT16\000"
1547 /* 1243 */ "RAT_STORE_DWORD128\000"
1548 /* 1262 */ "G_FMA\000"
1549 /* 1268 */ "G_STRICT_FMA\000"
1550 /* 1281 */ "TEX_SAMPLE_C_LB\000"
1551 /* 1297 */ "TEX_SAMPLE_LB\000"
1552 /* 1311 */ "G_FSUB\000"
1553 /* 1318 */ "G_STRICT_FSUB\000"
1554 /* 1332 */ "G_ATOMICRMW_FSUB\000"
1555 /* 1349 */ "G_SUB\000"
1556 /* 1355 */ "LDS_SUB\000"
1557 /* 1363 */ "G_ATOMICRMW_SUB\000"
1558 /* 1379 */ "G_INTRINSIC\000"
1559 /* 1391 */ "ENDFUNC\000"
1560 /* 1399 */ "G_FPTRUNC\000"
1561 /* 1409 */ "G_INTRINSIC_TRUNC\000"
1562 /* 1427 */ "G_TRUNC\000"
1563 /* 1435 */ "G_BUILD_VECTOR_TRUNC\000"
1564 /* 1456 */ "G_DYN_STACKALLOC\000"
1565 /* 1473 */ "TEX_SAMPLE_C\000"
1566 /* 1486 */ "G_FMAD\000"
1567 /* 1493 */ "G_INDEXED_SEXTLOAD\000"
1568 /* 1512 */ "G_SEXTLOAD\000"
1569 /* 1523 */ "G_INDEXED_ZEXTLOAD\000"
1570 /* 1542 */ "G_ZEXTLOAD\000"
1571 /* 1553 */ "INTERP_VEC_LOAD\000"
1572 /* 1569 */ "G_INDEXED_LOAD\000"
1573 /* 1584 */ "G_LOAD\000"
1574 /* 1591 */ "PAD\000"
1575 /* 1595 */ "G_VECREDUCE_FADD\000"
1576 /* 1612 */ "G_FADD\000"
1577 /* 1619 */ "G_VECREDUCE_SEQ_FADD\000"
1578 /* 1640 */ "G_STRICT_FADD\000"
1579 /* 1654 */ "G_ATOMICRMW_FADD\000"
1580 /* 1671 */ "G_VECREDUCE_ADD\000"
1581 /* 1687 */ "G_ADD\000"
1582 /* 1693 */ "G_PTR_ADD\000"
1583 /* 1703 */ "LDS_ADD\000"
1584 /* 1711 */ "G_ATOMICRMW_ADD\000"
1585 /* 1727 */ "TEX_LD\000"
1586 /* 1734 */ "G_ATOMICRMW_NAND\000"
1587 /* 1751 */ "G_VECREDUCE_AND\000"
1588 /* 1767 */ "G_AND\000"
1589 /* 1773 */ "LDS_AND\000"
1590 /* 1781 */ "G_ATOMICRMW_AND\000"
1591 /* 1797 */ "LIFETIME_END\000"
1592 /* 1810 */ "G_BRCOND\000"
1593 /* 1819 */ "G_ATOMICRMW_USUB_COND\000"
1594 /* 1841 */ "JUMP_COND\000"
1595 /* 1851 */ "G_LLROUND\000"
1596 /* 1861 */ "G_LROUND\000"
1597 /* 1870 */ "G_INTRINSIC_ROUND\000"
1598 /* 1888 */ "G_INTRINSIC_FPTRUNC_ROUND\000"
1599 /* 1914 */ "LOAD_STACK_GUARD\000"
1600 /* 1931 */ "TXD\000"
1601 /* 1935 */ "PSEUDO_PROBE\000"
1602 /* 1948 */ "G_SSUBE\000"
1603 /* 1956 */ "G_USUBE\000"
1604 /* 1964 */ "G_FENCE\000"
1605 /* 1972 */ "ARITH_FENCE\000"
1606 /* 1984 */ "REG_SEQUENCE\000"
1607 /* 1997 */ "G_SADDE\000"
1608 /* 2005 */ "G_UADDE\000"
1609 /* 2013 */ "G_GET_FPMODE\000"
1610 /* 2026 */ "G_RESET_FPMODE\000"
1611 /* 2041 */ "G_SET_FPMODE\000"
1612 /* 2054 */ "MUL_IEEE\000"
1613 /* 2063 */ "G_FMINNUM_IEEE\000"
1614 /* 2078 */ "G_FMAXNUM_IEEE\000"
1615 /* 2093 */ "SGE\000"
1616 /* 2097 */ "PRED_SETGE\000"
1617 /* 2108 */ "G_VSCALE\000"
1618 /* 2117 */ "G_JUMP_TABLE\000"
1619 /* 2130 */ "BUNDLE\000"
1620 /* 2137 */ "TEX_SAMPLE\000"
1621 /* 2148 */ "RNDNE\000"
1622 /* 2154 */ "G_MEMCPY_INLINE\000"
1623 /* 2170 */ "SNE\000"
1624 /* 2174 */ "PRED_SETNE\000"
1625 /* 2185 */ "LOCAL_ESCAPE\000"
1626 /* 2198 */ "CF_ALU_PUSH_BEFORE\000"
1627 /* 2217 */ "G_STACKRESTORE\000"
1628 /* 2232 */ "G_INDEXED_STORE\000"
1629 /* 2248 */ "G_STORE\000"
1630 /* 2256 */ "ELSE\000"
1631 /* 2261 */ "G_BITREVERSE\000"
1632 /* 2274 */ "FETCH_CLAUSE\000"
1633 /* 2287 */ "ALU_CLAUSE\000"
1634 /* 2298 */ "FAKE_USE\000"
1635 /* 2307 */ "PRED_SETE\000"
1636 /* 2317 */ "LDS_BYTE_WRITE\000"
1637 /* 2332 */ "MASK_WRITE\000"
1638 /* 2343 */ "LDS_WRITE\000"
1639 /* 2353 */ "LDS_SHORT_WRITE\000"
1640 /* 2369 */ "DBG_VALUE\000"
1641 /* 2379 */ "G_GLOBAL_VALUE\000"
1642 /* 2394 */ "G_PTRAUTH_GLOBAL_VALUE\000"
1643 /* 2417 */ "CONVERGENCECTRL_GLUE\000"
1644 /* 2438 */ "CF_ALU_CONTINUE\000"
1645 /* 2454 */ "G_STACKSAVE\000"
1646 /* 2466 */ "G_MEMMOVE\000"
1647 /* 2476 */ "G_FREEZE\000"
1648 /* 2485 */ "G_FCANONICALIZE\000"
1649 /* 2501 */ "G_CTLZ_ZERO_UNDEF\000"
1650 /* 2519 */ "G_CTTZ_ZERO_UNDEF\000"
1651 /* 2537 */ "INIT_UNDEF\000"
1652 /* 2548 */ "G_IMPLICIT_DEF\000"
1653 /* 2563 */ "DBG_INSTR_REF\000"
1654 /* 2577 */ "ENDIF\000"
1655 /* 2583 */ "TEX_VTX_CONSTBUF\000"
1656 /* 2600 */ "TEX_VTX_TEXBUF\000"
1657 /* 2615 */ "G_FNEG\000"
1658 /* 2622 */ "EXTRACT_SUBREG\000"
1659 /* 2637 */ "INSERT_SUBREG\000"
1660 /* 2651 */ "G_SEXT_INREG\000"
1661 /* 2664 */ "SUBREG_TO_REG\000"
1662 /* 2678 */ "CF_TC_EG\000"
1663 /* 2687 */ "CF_VC_EG\000"
1664 /* 2696 */ "CF_END_EG\000"
1665 /* 2706 */ "CF_ELSE_EG\000"
1666 /* 2717 */ "CF_CONTINUE_EG\000"
1667 /* 2732 */ "CF_PUSH_EG\000"
1668 /* 2743 */ "LOOP_BREAK_EG\000"
1669 /* 2757 */ "CF_JUMP_EG\000"
1670 /* 2768 */ "END_LOOP_EG\000"
1671 /* 2780 */ "WHILE_LOOP_EG\000"
1672 /* 2794 */ "POP_EG\000"
1673 /* 2801 */ "CF_CALL_FS_EG\000"
1674 /* 2815 */ "G_ATOMIC_CMPXCHG\000"
1675 /* 2832 */ "LDS_WRXCHG\000"
1676 /* 2843 */ "G_ATOMICRMW_XCHG\000"
1677 /* 2860 */ "G_FLOG\000"
1678 /* 2867 */ "G_VAARG\000"
1679 /* 2875 */ "PREALLOCATED_ARG\000"
1680 /* 2892 */ "TEX_SAMPLE_C_G\000"
1681 /* 2907 */ "TEX_SAMPLE_G\000"
1682 /* 2920 */ "BRANCH\000"
1683 /* 2927 */ "G_PREFETCH\000"
1684 /* 2938 */ "ENDSWITCH\000"
1685 /* 2948 */ "G_SMULH\000"
1686 /* 2956 */ "G_UMULH\000"
1687 /* 2964 */ "G_FTANH\000"
1688 /* 2972 */ "G_FSINH\000"
1689 /* 2980 */ "G_FCOSH\000"
1690 /* 2988 */ "TEX_GET_GRADIENTS_H\000"
1691 /* 3008 */ "TEX_SET_GRADIENTS_H\000"
1692 /* 3028 */ "DBG_PHI\000"
1693 /* 3036 */ "G_FPTOSI\000"
1694 /* 3045 */ "G_FPTOUI\000"
1695 /* 3054 */ "G_FPOWI\000"
1696 /* 3062 */ "CF_ALU_BREAK\000"
1697 /* 3075 */ "G_PTRMASK\000"
1698 /* 3085 */ "GC_LABEL\000"
1699 /* 3094 */ "DBG_LABEL\000"
1700 /* 3104 */ "EH_LABEL\000"
1701 /* 3113 */ "ANNOTATION_LABEL\000"
1702 /* 3130 */ "ICALL_BRANCH_FUNNEL\000"
1703 /* 3150 */ "G_FSHL\000"
1704 /* 3157 */ "G_SHL\000"
1705 /* 3163 */ "G_FCEIL\000"
1706 /* 3171 */ "PATCHABLE_TAIL_CALL\000"
1707 /* 3191 */ "PATCHABLE_TYPED_EVENT_CALL\000"
1708 /* 3218 */ "PATCHABLE_EVENT_CALL\000"
1709 /* 3239 */ "FENTRY_CALL\000"
1710 /* 3251 */ "KILL\000"
1711 /* 3256 */ "G_CONSTANT_POOL\000"
1712 /* 3272 */ "G_ROTL\000"
1713 /* 3279 */ "G_VECREDUCE_FMUL\000"
1714 /* 3296 */ "G_FMUL\000"
1715 /* 3303 */ "G_VECREDUCE_SEQ_FMUL\000"
1716 /* 3324 */ "G_STRICT_FMUL\000"
1717 /* 3338 */ "G_VECREDUCE_MUL\000"
1718 /* 3354 */ "G_MUL\000"
1719 /* 3360 */ "TEX_SAMPLE_C_L\000"
1720 /* 3375 */ "TEX_SAMPLE_L\000"
1721 /* 3388 */ "CF_END_CM\000"
1722 /* 3398 */ "G_FREM\000"
1723 /* 3405 */ "G_STRICT_FREM\000"
1724 /* 3419 */ "G_SREM\000"
1725 /* 3426 */ "G_UREM\000"
1726 /* 3433 */ "G_SDIVREM\000"
1727 /* 3443 */ "G_UDIVREM\000"
1728 /* 3453 */ "INLINEASM\000"
1729 /* 3463 */ "G_VECREDUCE_FMINIMUM\000"
1730 /* 3484 */ "G_FMINIMUM\000"
1731 /* 3495 */ "G_ATOMICRMW_FMINIMUM\000"
1732 /* 3516 */ "G_VECREDUCE_FMAXIMUM\000"
1733 /* 3537 */ "G_FMAXIMUM\000"
1734 /* 3548 */ "G_ATOMICRMW_FMAXIMUM\000"
1735 /* 3569 */ "G_FMINIMUMNUM\000"
1736 /* 3583 */ "G_FMAXIMUMNUM\000"
1737 /* 3597 */ "G_FMINNUM\000"
1738 /* 3607 */ "G_FMAXNUM\000"
1739 /* 3617 */ "G_FATAN\000"
1740 /* 3625 */ "G_FTAN\000"
1741 /* 3632 */ "G_INTRINSIC_ROUNDEVEN\000"
1742 /* 3654 */ "G_ASSERT_ALIGN\000"
1743 /* 3669 */ "G_FCOPYSIGN\000"
1744 /* 3681 */ "DUMMY_CHAIN\000"
1745 /* 3693 */ "ENDMAIN\000"
1746 /* 3701 */ "G_VECREDUCE_FMIN\000"
1747 /* 3718 */ "G_ATOMICRMW_FMIN\000"
1748 /* 3735 */ "G_VECREDUCE_SMIN\000"
1749 /* 3752 */ "G_SMIN\000"
1750 /* 3759 */ "G_VECREDUCE_UMIN\000"
1751 /* 3776 */ "G_UMIN\000"
1752 /* 3783 */ "G_ATOMICRMW_UMIN\000"
1753 /* 3800 */ "G_ATOMICRMW_MIN\000"
1754 /* 3816 */ "G_FASIN\000"
1755 /* 3824 */ "G_FSIN\000"
1756 /* 3831 */ "CFI_INSTRUCTION\000"
1757 /* 3847 */ "RETURN\000"
1758 /* 3854 */ "RAT_ATOMIC_RSUB_RTN\000"
1759 /* 3874 */ "RAT_ATOMIC_SUB_RTN\000"
1760 /* 3893 */ "RAT_ATOMIC_ADD_RTN\000"
1761 /* 3912 */ "RAT_ATOMIC_AND_RTN\000"
1762 /* 3931 */ "RAT_ATOMIC_XOR_RTN\000"
1763 /* 3950 */ "RAT_ATOMIC_OR_RTN\000"
1764 /* 3968 */ "RAT_ATOMIC_DEC_UINT_RTN\000"
1765 /* 3992 */ "RAT_ATOMIC_INC_UINT_RTN\000"
1766 /* 4016 */ "RAT_ATOMIC_MIN_UINT_RTN\000"
1767 /* 4040 */ "RAT_ATOMIC_MAX_UINT_RTN\000"
1768 /* 4064 */ "RAT_ATOMIC_CMPXCHG_INT_RTN\000"
1769 /* 4091 */ "RAT_ATOMIC_XCHG_INT_RTN\000"
1770 /* 4115 */ "RAT_ATOMIC_MIN_INT_RTN\000"
1771 /* 4138 */ "RAT_ATOMIC_MAX_INT_RTN\000"
1772 /* 4161 */ "RETDYN\000"
1773 /* 4168 */ "G_SSUBO\000"
1774 /* 4176 */ "G_USUBO\000"
1775 /* 4184 */ "G_SADDO\000"
1776 /* 4192 */ "G_UADDO\000"
1777 /* 4200 */ "TEX_GET_TEXTURE_RESINFO\000"
1778 /* 4224 */ "JUMP_TABLE_DEBUG_INFO\000"
1779 /* 4246 */ "G_SMULO\000"
1780 /* 4254 */ "G_UMULO\000"
1781 /* 4262 */ "G_BZERO\000"
1782 /* 4270 */ "STACKMAP\000"
1783 /* 4279 */ "G_DEBUGTRAP\000"
1784 /* 4291 */ "G_UBSANTRAP\000"
1785 /* 4303 */ "G_TRAP\000"
1786 /* 4310 */ "G_ATOMICRMW_UDEC_WRAP\000"
1787 /* 4332 */ "G_ATOMICRMW_UINC_WRAP\000"
1788 /* 4354 */ "G_BSWAP\000"
1789 /* 4362 */ "G_SITOFP\000"
1790 /* 4371 */ "G_UITOFP\000"
1791 /* 4380 */ "G_FCMP\000"
1792 /* 4387 */ "G_ICMP\000"
1793 /* 4394 */ "G_SCMP\000"
1794 /* 4401 */ "G_UCMP\000"
1795 /* 4408 */ "JUMP\000"
1796 /* 4413 */ "ENDLOOP\000"
1797 /* 4421 */ "WHILELOOP\000"
1798 /* 4431 */ "CONVERGENCECTRL_LOOP\000"
1799 /* 4452 */ "G_CTPOP\000"
1800 /* 4460 */ "PATCHABLE_OP\000"
1801 /* 4473 */ "FAULTING_OP\000"
1802 /* 4485 */ "PREALLOCATED_SETUP\000"
1803 /* 4504 */ "G_FLDEXP\000"
1804 /* 4513 */ "G_STRICT_FLDEXP\000"
1805 /* 4529 */ "G_FEXP\000"
1806 /* 4536 */ "G_FFREXP\000"
1807 /* 4545 */ "G_BR\000"
1808 /* 4550 */ "INLINEASM_BR\000"
1809 /* 4563 */ "G_BLOCK_ADDR\000"
1810 /* 4576 */ "MOV_IMM_GLOBAL_ADDR\000"
1811 /* 4596 */ "MEMBARRIER\000"
1812 /* 4607 */ "G_CONSTANT_FOLD_BARRIER\000"
1813 /* 4631 */ "GROUP_BARRIER\000"
1814 /* 4645 */ "CF_ALU_ELSE_AFTER\000"
1815 /* 4663 */ "CF_ALU_POP_AFTER\000"
1816 /* 4680 */ "PATCHABLE_FUNCTION_ENTER\000"
1817 /* 4705 */ "G_READCYCLECOUNTER\000"
1818 /* 4724 */ "G_READSTEADYCOUNTER\000"
1819 /* 4744 */ "G_READ_REGISTER\000"
1820 /* 4760 */ "G_WRITE_REGISTER\000"
1821 /* 4777 */ "G_ASHR\000"
1822 /* 4784 */ "G_FSHR\000"
1823 /* 4791 */ "G_LSHR\000"
1824 /* 4798 */ "CONVERGENCECTRL_ANCHOR\000"
1825 /* 4821 */ "RAT_MSKOR\000"
1826 /* 4831 */ "G_FFLOOR\000"
1827 /* 4840 */ "G_EXTRACT_SUBVECTOR\000"
1828 /* 4860 */ "G_INSERT_SUBVECTOR\000"
1829 /* 4879 */ "G_BUILD_VECTOR\000"
1830 /* 4894 */ "G_SHUFFLE_VECTOR\000"
1831 /* 4911 */ "G_STEP_VECTOR\000"
1832 /* 4925 */ "G_SPLAT_VECTOR\000"
1833 /* 4940 */ "G_VECREDUCE_XOR\000"
1834 /* 4956 */ "G_XOR\000"
1835 /* 4962 */ "LDS_XOR\000"
1836 /* 4970 */ "G_ATOMICRMW_XOR\000"
1837 /* 4986 */ "G_VECREDUCE_OR\000"
1838 /* 5001 */ "G_OR\000"
1839 /* 5006 */ "LDS_OR\000"
1840 /* 5013 */ "G_ATOMICRMW_OR\000"
1841 /* 5028 */ "G_ROTR\000"
1842 /* 5035 */ "TEX_LDPTR\000"
1843 /* 5045 */ "G_INTTOPTR\000"
1844 /* 5056 */ "G_FABS\000"
1845 /* 5063 */ "G_ABS\000"
1846 /* 5069 */ "G_ABDS\000"
1847 /* 5076 */ "G_UNMERGE_VALUES\000"
1848 /* 5093 */ "G_MERGE_VALUES\000"
1849 /* 5108 */ "LITERALS\000"
1850 /* 5117 */ "G_FACOS\000"
1851 /* 5125 */ "G_FCOS\000"
1852 /* 5132 */ "G_FSINCOS\000"
1853 /* 5142 */ "G_CONCAT_VECTORS\000"
1854 /* 5159 */ "COPY_TO_REGCLASS\000"
1855 /* 5176 */ "G_IS_FPCLASS\000"
1856 /* 5189 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000"
1857 /* 5219 */ "G_VECTOR_COMPRESS\000"
1858 /* 5237 */ "G_INTRINSIC_W_SIDE_EFFECTS\000"
1859 /* 5264 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000"
1860 /* 5302 */ "G_SSUBSAT\000"
1861 /* 5312 */ "G_USUBSAT\000"
1862 /* 5322 */ "G_SADDSAT\000"
1863 /* 5332 */ "G_UADDSAT\000"
1864 /* 5342 */ "G_SSHLSAT\000"
1865 /* 5352 */ "G_USHLSAT\000"
1866 /* 5362 */ "G_SMULFIXSAT\000"
1867 /* 5375 */ "G_UMULFIXSAT\000"
1868 /* 5388 */ "G_SDIVFIXSAT\000"
1869 /* 5401 */ "G_UDIVFIXSAT\000"
1870 /* 5414 */ "G_ATOMICRMW_USUB_SAT\000"
1871 /* 5435 */ "G_FPTOSI_SAT\000"
1872 /* 5448 */ "G_FPTOUI_SAT\000"
1873 /* 5461 */ "FRACT\000"
1874 /* 5467 */ "G_EXTRACT\000"
1875 /* 5477 */ "G_SELECT\000"
1876 /* 5486 */ "G_BRINDIRECT\000"
1877 /* 5499 */ "RAT_ATOMIC_RSUB_NORET\000"
1878 /* 5521 */ "RAT_ATOMIC_SUB_NORET\000"
1879 /* 5542 */ "RAT_ATOMIC_ADD_NORET\000"
1880 /* 5563 */ "RAT_ATOMIC_AND_NORET\000"
1881 /* 5584 */ "RAT_ATOMIC_XOR_NORET\000"
1882 /* 5605 */ "RAT_ATOMIC_OR_NORET\000"
1883 /* 5625 */ "RAT_ATOMIC_DEC_UINT_NORET\000"
1884 /* 5651 */ "RAT_ATOMIC_INC_UINT_NORET\000"
1885 /* 5677 */ "RAT_ATOMIC_MIN_UINT_NORET\000"
1886 /* 5703 */ "RAT_ATOMIC_MAX_UINT_NORET\000"
1887 /* 5729 */ "RAT_ATOMIC_CMPXCHG_INT_NORET\000"
1888 /* 5758 */ "RAT_ATOMIC_XCHG_INT_NORET\000"
1889 /* 5784 */ "RAT_ATOMIC_MIN_INT_NORET\000"
1890 /* 5809 */ "RAT_ATOMIC_MAX_INT_NORET\000"
1891 /* 5834 */ "LDS_SUB_RET\000"
1892 /* 5846 */ "LDS_UBYTE_READ_RET\000"
1893 /* 5865 */ "LDS_BYTE_READ_RET\000"
1894 /* 5883 */ "LDS_READ_RET\000"
1895 /* 5896 */ "LDS_USHORT_READ_RET\000"
1896 /* 5916 */ "LDS_SHORT_READ_RET\000"
1897 /* 5935 */ "LDS_ADD_RET\000"
1898 /* 5947 */ "LDS_AND_RET\000"
1899 /* 5959 */ "PATCHABLE_RET\000"
1900 /* 5973 */ "LDS_WRXCHG_RET\000"
1901 /* 5988 */ "LDS_XOR_RET\000"
1902 /* 6000 */ "LDS_OR_RET\000"
1903 /* 6011 */ "LDS_MIN_UINT_RET\000"
1904 /* 6028 */ "LDS_MAX_UINT_RET\000"
1905 /* 6045 */ "LDS_MIN_INT_RET\000"
1906 /* 6061 */ "LDS_MAX_INT_RET\000"
1907 /* 6077 */ "LDS_CMPST_RET\000"
1908 /* 6091 */ "G_MEMSET\000"
1909 /* 6100 */ "IF_PREDICATE_SET\000"
1910 /* 6117 */ "KILLGT\000"
1911 /* 6124 */ "SGT\000"
1912 /* 6128 */ "PRED_SETGT\000"
1913 /* 6139 */ "PATCHABLE_FUNCTION_EXIT\000"
1914 /* 6163 */ "G_BRJT\000"
1915 /* 6170 */ "G_EXTRACT_VECTOR_ELT\000"
1916 /* 6191 */ "G_INSERT_VECTOR_ELT\000"
1917 /* 6211 */ "DEFAULT\000"
1918 /* 6219 */ "G_FCONSTANT\000"
1919 /* 6231 */ "G_CONSTANT\000"
1920 /* 6242 */ "G_INTRINSIC_CONVERGENT\000"
1921 /* 6265 */ "STATEPOINT\000"
1922 /* 6276 */ "PATCHPOINT\000"
1923 /* 6287 */ "G_PTRTOINT\000"
1924 /* 6298 */ "G_FRINT\000"
1925 /* 6306 */ "G_INTRINSIC_LLRINT\000"
1926 /* 6325 */ "G_INTRINSIC_LRINT\000"
1927 /* 6343 */ "SUBB_UINT\000"
1928 /* 6353 */ "ADDC_UINT\000"
1929 /* 6363 */ "SETGE_UINT\000"
1930 /* 6374 */ "FFBH_UINT\000"
1931 /* 6384 */ "LDS_MIN_UINT\000"
1932 /* 6397 */ "SETGT_UINT\000"
1933 /* 6408 */ "LDS_MAX_UINT\000"
1934 /* 6421 */ "G_FNEARBYINT\000"
1935 /* 6434 */ "SUB_INT\000"
1936 /* 6442 */ "ADD_INT\000"
1937 /* 6450 */ "AND_INT\000"
1938 /* 6458 */ "CNDE_INT\000"
1939 /* 6467 */ "CNDGE_INT\000"
1940 /* 6477 */ "PRED_SETGE_INT\000"
1941 /* 6492 */ "PRED_SETNE_INT\000"
1942 /* 6507 */ "PRED_SETE_INT\000"
1943 /* 6521 */ "FFBL_INT\000"
1944 /* 6530 */ "LDS_MIN_INT\000"
1945 /* 6542 */ "XOR_INT\000"
1946 /* 6550 */ "CNDGT_INT\000"
1947 /* 6560 */ "PRED_SETGT_INT\000"
1948 /* 6575 */ "BCNT_INT\000"
1949 /* 6584 */ "NOT_INT\000"
1950 /* 6592 */ "LDS_MAX_INT\000"
1951 /* 6604 */ "G_VASTART\000"
1952 /* 6614 */ "LIFETIME_START\000"
1953 /* 6629 */ "G_INVOKE_REGION_START\000"
1954 /* 6651 */ "G_INSERT\000"
1955 /* 6660 */ "G_FSQRT\000"
1956 /* 6668 */ "G_STRICT_FSQRT\000"
1957 /* 6683 */ "G_BITCAST\000"
1958 /* 6693 */ "G_ADDRSPACE_CAST\000"
1959 /* 6710 */ "DBG_VALUE_LIST\000"
1960 /* 6725 */ "LDS_CMPST\000"
1961 /* 6735 */ "G_FPEXT\000"
1962 /* 6743 */ "G_SEXT\000"
1963 /* 6750 */ "G_ASSERT_SEXT\000"
1964 /* 6764 */ "G_ANYEXT\000"
1965 /* 6773 */ "G_ZEXT\000"
1966 /* 6780 */ "G_ASSERT_ZEXT\000"
1967 /* 6794 */ "G_ABDU\000"
1968 /* 6801 */ "CF_ALU\000"
1969 /* 6808 */ "G_FDIV\000"
1970 /* 6815 */ "G_STRICT_FDIV\000"
1971 /* 6829 */ "G_SDIV\000"
1972 /* 6836 */ "G_UDIV\000"
1973 /* 6843 */ "G_GET_FPENV\000"
1974 /* 6855 */ "G_RESET_FPENV\000"
1975 /* 6869 */ "G_SET_FPENV\000"
1976 /* 6881 */ "MOV\000"
1977 /* 6885 */ "TEX_GET_GRADIENTS_V\000"
1978 /* 6905 */ "TEX_SET_GRADIENTS_V\000"
1979 /* 6925 */ "TXD_SHADOW\000"
1980 /* 6936 */ "G_FPOW\000"
1981 /* 6943 */ "INTERP_ZW\000"
1982 /* 6953 */ "INTERP_PAIR_ZW\000"
1983 /* 6968 */ "G_VECREDUCE_FMAX\000"
1984 /* 6985 */ "G_ATOMICRMW_FMAX\000"
1985 /* 7002 */ "G_VECREDUCE_SMAX\000"
1986 /* 7019 */ "G_SMAX\000"
1987 /* 7026 */ "G_VECREDUCE_UMAX\000"
1988 /* 7043 */ "G_UMAX\000"
1989 /* 7050 */ "G_ATOMICRMW_UMAX\000"
1990 /* 7067 */ "G_ATOMICRMW_MAX\000"
1991 /* 7083 */ "G_FRAME_INDEX\000"
1992 /* 7097 */ "G_SBFX\000"
1993 /* 7104 */ "G_UBFX\000"
1994 /* 7111 */ "G_SMULFIX\000"
1995 /* 7121 */ "G_UMULFIX\000"
1996 /* 7131 */ "G_SDIVFIX\000"
1997 /* 7141 */ "G_UDIVFIX\000"
1998 /* 7151 */ "PRED_X\000"
1999 /* 7158 */ "G_MEMCPY\000"
2000 /* 7167 */ "CONST_COPY\000"
2001 /* 7178 */ "CONVERGENCECTRL_ENTRY\000"
2002 /* 7200 */ "INTERP_XY\000"
2003 /* 7210 */ "INTERP_PAIR_XY\000"
2004 /* 7225 */ "G_CTLZ\000"
2005 /* 7232 */ "G_CTTZ\000"
2006 /* 7239 */ "R600_RegisterLoad\000"
2007 /* 7257 */ "R600_RegisterStore\000"
2008 /* 7276 */ "R600_ExportBuf\000"
2009 /* 7291 */ "EG_ExportBuf\000"
2010 /* 7304 */ "VTX_READ_32_eg\000"
2011 /* 7319 */ "RAT_WRITE_CACHELESS_32_eg\000"
2012 /* 7345 */ "MULADD_UINT24_eg\000"
2013 /* 7362 */ "MULHI_UINT24_eg\000"
2014 /* 7378 */ "MUL_UINT24_eg\000"
2015 /* 7392 */ "VTX_READ_64_eg\000"
2016 /* 7407 */ "RAT_WRITE_CACHELESS_64_eg\000"
2017 /* 7433 */ "DOT4_eg\000"
2018 /* 7441 */ "VTX_READ_16_eg\000"
2019 /* 7456 */ "VTX_READ_128_eg\000"
2020 /* 7472 */ "RAT_WRITE_CACHELESS_128_eg\000"
2021 /* 7499 */ "VTX_READ_8_eg\000"
2022 /* 7513 */ "FMA_eg\000"
2023 /* 7520 */ "MULADD_eg\000"
2024 /* 7530 */ "LOG_CLAMPED_eg\000"
2025 /* 7545 */ "RECIP_CLAMPED_eg\000"
2026 /* 7562 */ "RECIPSQRT_CLAMPED_eg\000"
2027 /* 7583 */ "RAT_STORE_TYPED_eg\000"
2028 /* 7602 */ "CNDE_eg\000"
2029 /* 7610 */ "MULADD_IEEE_eg\000"
2030 /* 7625 */ "LOG_IEEE_eg\000"
2031 /* 7637 */ "RECIP_IEEE_eg\000"
2032 /* 7651 */ "EXP_IEEE_eg\000"
2033 /* 7663 */ "RECIPSQRT_IEEE_eg\000"
2034 /* 7681 */ "CNDGE_eg\000"
2035 /* 7690 */ "LSHL_eg\000"
2036 /* 7698 */ "SIN_eg\000"
2037 /* 7705 */ "ASHR_eg\000"
2038 /* 7713 */ "LSHR_eg\000"
2039 /* 7721 */ "COS_eg\000"
2040 /* 7728 */ "CNDGT_eg\000"
2041 /* 7737 */ "MUL_LIT_eg\000"
2042 /* 7748 */ "UINT_TO_FLT_eg\000"
2043 /* 7763 */ "BFE_UINT_eg\000"
2044 /* 7775 */ "MULHI_UINT_eg\000"
2045 /* 7789 */ "MULLO_UINT_eg\000"
2046 /* 7803 */ "FLT_TO_UINT_eg\000"
2047 /* 7818 */ "RECIP_UINT_eg\000"
2048 /* 7832 */ "MOVA_INT_eg\000"
2049 /* 7844 */ "BFE_INT_eg\000"
2050 /* 7855 */ "BFI_INT_eg\000"
2051 /* 7866 */ "MULHI_INT_eg\000"
2052 /* 7879 */ "BFM_INT_eg\000"
2053 /* 7890 */ "BIT_ALIGN_INT_eg\000"
2054 /* 7907 */ "MULLO_INT_eg\000"
2055 /* 7920 */ "FLT_TO_INT_eg\000"
2056 /* 7934 */ "CUBE_r600_real\000"
2057 /* 7949 */ "CUBE_eg_real\000"
2058 /* 7962 */ "VTX_READ_32_cm\000"
2059 /* 7977 */ "MULADD_INT24_cm\000"
2060 /* 7993 */ "MUL_INT24_cm\000"
2061 /* 8006 */ "VTX_READ_64_cm\000"
2062 /* 8021 */ "VTX_READ_16_cm\000"
2063 /* 8036 */ "VTX_READ_128_cm\000"
2064 /* 8052 */ "VTX_READ_8_cm\000"
2065 /* 8066 */ "RECIP_CLAMPED_cm\000"
2066 /* 8083 */ "RECIPSQRT_CLAMPED_cm\000"
2067 /* 8104 */ "RAT_STORE_TYPED_cm\000"
2068 /* 8123 */ "LOG_IEEE_cm\000"
2069 /* 8135 */ "RECIP_IEEE_cm\000"
2070 /* 8149 */ "EXP_IEEE_cm\000"
2071 /* 8161 */ "RECIPSQRT_IEEE_cm\000"
2072 /* 8179 */ "SIN_cm\000"
2073 /* 8186 */ "COS_cm\000"
2074 /* 8193 */ "MULHI_UINT_cm\000"
2075 /* 8207 */ "MULLO_UINT_cm\000"
2076 /* 8221 */ "MULHI_INT_cm\000"
2077 /* 8234 */ "MULLO_INT_cm\000"
2078 /* 8247 */ "CUBE_r600_pseudo\000"
2079 /* 8264 */ "CUBE_eg_pseudo\000"
2080 /* 8279 */ "R600_ExportSwz\000"
2081 /* 8294 */ "EG_ExportSwz\000"
2082};
2083#ifdef __GNUC__
2084#pragma GCC diagnostic pop
2085#endif
2086
2087extern const unsigned R600InstrNameIndices[] = {
2088 3032U, 3453U, 4550U, 3831U, 3104U, 3085U, 3113U, 3251U,
2089 2622U, 2637U, 2550U, 2537U, 2664U, 5159U, 2369U, 6710U,
2090 2563U, 3028U, 3094U, 1984U, 7173U, 2130U, 6614U, 1797U,
2091 1935U, 1972U, 4270U, 3239U, 6276U, 1914U, 4485U, 2875U,
2092 6265U, 2185U, 4473U, 4460U, 4680U, 5959U, 6139U, 3171U,
2093 3218U, 3191U, 3130U, 2298U, 4596U, 4224U, 7178U, 4798U,
2094 4431U, 2417U, 6750U, 6780U, 3654U, 1687U, 1349U, 3354U,
2095 6829U, 6836U, 3419U, 3426U, 3433U, 3443U, 1767U, 5001U,
2096 4956U, 5069U, 6794U, 2548U, 3030U, 7083U, 2379U, 2394U,
2097 3256U, 5467U, 5076U, 6651U, 5093U, 4879U, 1435U, 5142U,
2098 6287U, 5045U, 6683U, 2476U, 4607U, 1888U, 1409U, 1870U,
2099 6325U, 6306U, 3632U, 4705U, 4724U, 1584U, 1512U, 1542U,
2100 1569U, 1493U, 1523U, 2248U, 2232U, 5189U, 2815U, 2843U,
2101 1711U, 1363U, 1781U, 1734U, 5013U, 4970U, 7067U, 3800U,
2102 7050U, 3783U, 1654U, 1332U, 6985U, 3718U, 3548U, 3495U,
2103 4332U, 4310U, 1819U, 5414U, 1964U, 2927U, 1810U, 5486U,
2104 6629U, 1379U, 5237U, 6242U, 5264U, 6764U, 1427U, 6231U,
2105 6219U, 6604U, 2867U, 6743U, 2651U, 6773U, 3157U, 4791U,
2106 4777U, 3150U, 4784U, 5028U, 3272U, 4387U, 4380U, 4394U,
2107 4401U, 5477U, 4192U, 2005U, 4176U, 1956U, 4184U, 1997U,
2108 4168U, 1948U, 4254U, 4246U, 2956U, 2948U, 5332U, 5322U,
2109 5312U, 5302U, 5352U, 5342U, 7111U, 7121U, 5362U, 5375U,
2110 7131U, 7141U, 5388U, 5401U, 1612U, 1311U, 3296U, 1262U,
2111 1486U, 6808U, 3398U, 6936U, 3054U, 4529U, 1087U, 596U,
2112 2860U, 1070U, 587U, 4504U, 4536U, 2615U, 6735U, 1399U,
2113 3036U, 3045U, 4362U, 4371U, 5435U, 5448U, 5056U, 3669U,
2114 5176U, 2485U, 3597U, 3607U, 2063U, 2078U, 3484U, 3537U,
2115 3569U, 3583U, 6843U, 6869U, 6855U, 2013U, 2041U, 2026U,
2116 1693U, 3075U, 3752U, 7019U, 3776U, 7043U, 5063U, 1861U,
2117 1851U, 4545U, 6163U, 2108U, 4860U, 4840U, 6191U, 6170U,
2118 4894U, 4925U, 4911U, 5219U, 7232U, 2519U, 7225U, 2501U,
2119 4452U, 4354U, 2261U, 3163U, 5125U, 3824U, 5132U, 3625U,
2120 5117U, 3816U, 3617U, 1078U, 2980U, 2972U, 2964U, 6660U,
2121 4831U, 6298U, 6421U, 6693U, 4563U, 2117U, 1456U, 2454U,
2122 2217U, 1640U, 1318U, 3324U, 6815U, 3405U, 1268U, 6668U,
2123 4513U, 4744U, 4760U, 7158U, 2154U, 2466U, 6091U, 4262U,
2124 4303U, 4279U, 4291U, 1619U, 3303U, 1595U, 3279U, 6968U,
2125 3701U, 3516U, 3463U, 1671U, 3338U, 1751U, 4986U, 4940U,
2126 7002U, 3735U, 7026U, 3759U, 7097U, 7104U, 2920U, 771U,
2127 937U, 3069U, 760U, 926U, 884U, 1050U, 825U, 991U,
2128 7167U, 2445U, 738U, 904U, 844U, 1010U, 787U, 953U,
2129 8264U, 8247U, 6211U, 1222U, 3681U, 2256U, 1806U, 1391U,
2130 2577U, 4413U, 3693U, 2938U, 160U, 82U, 1394U, 752U,
2131 918U, 867U, 1033U, 809U, 975U, 6100U, 4408U, 1841U,
2132 2332U, 699U, 4576U, 711U, 7151U, 1095U, 1183U, 1115U,
2133 1203U, 7239U, 7257U, 4161U, 3847U, 1931U, 6925U, 4421U,
2134 1608U, 6353U, 6442U, 2287U, 6450U, 7705U, 388U, 6575U,
2135 7844U, 7763U, 7855U, 7879U, 7890U, 3166U, 6801U, 3062U,
2136 2438U, 4645U, 4663U, 2198U, 2801U, 170U, 2717U, 65U,
2137 2706U, 34U, 3388U, 2696U, 22U, 2757U, 108U, 2732U,
2138 47U, 2678U, 0U, 2687U, 11U, 6458U, 7602U, 267U,
2139 6467U, 7681U, 358U, 6550U, 7728U, 417U, 8186U, 7721U,
2140 408U, 578U, 7949U, 7934U, 7433U, 186U, 7291U, 8294U,
2141 2768U, 121U, 8149U, 7651U, 324U, 2274U, 6374U, 6521U,
2142 4834U, 723U, 1228U, 7920U, 553U, 7803U, 490U, 7513U,
2143 5461U, 4631U, 666U, 7210U, 6953U, 1553U, 7200U, 6943U,
2144 7749U, 442U, 6117U, 1703U, 5935U, 1773U, 5947U, 5865U,
2145 2317U, 6725U, 6077U, 6592U, 6061U, 6408U, 6028U, 6530U,
2146 6045U, 6384U, 6011U, 5006U, 6000U, 5883U, 5916U, 2353U,
2147 1355U, 5834U, 5846U, 5896U, 2343U, 2832U, 5973U, 4962U,
2148 5988U, 5108U, 7530U, 208U, 8123U, 7625U, 294U, 2743U,
2149 92U, 7690U, 369U, 7713U, 398U, 6981U, 657U, 6596U,
2150 6412U, 3714U, 637U, 6534U, 6388U, 6881U, 7832U, 3292U,
2151 7610U, 277U, 7977U, 7345U, 7520U, 196U, 8221U, 1150U,
2152 7866U, 523U, 7362U, 8193U, 1134U, 7775U, 458U, 8234U,
2153 7907U, 538U, 8207U, 7789U, 474U, 2054U, 7993U, 7737U,
2154 428U, 7378U, 6584U, 6543U, 1591U, 2794U, 151U, 2307U,
2155 6507U, 2097U, 6477U, 6128U, 6560U, 2174U, 6492U, 7276U,
2156 8279U, 5542U, 3893U, 5563U, 3912U, 5729U, 4064U, 5625U,
2157 3968U, 5651U, 3992U, 5809U, 4138U, 5703U, 4040U, 5784U,
2158 4115U, 5677U, 4016U, 5605U, 3950U, 5499U, 3854U, 5521U,
2159 3874U, 5758U, 4091U, 5584U, 3931U, 4821U, 1243U, 681U,
2160 1165U, 8104U, 7583U, 7472U, 7319U, 7407U, 8083U, 7562U,
2161 244U, 8161U, 7663U, 338U, 8066U, 7545U, 225U, 8135U,
2162 7637U, 308U, 7818U, 507U, 2148U, 2312U, 627U, 6512U,
2163 605U, 6482U, 6363U, 646U, 6565U, 6397U, 616U, 6497U,
2164 2093U, 6124U, 8179U, 7698U, 379U, 569U, 2170U, 6343U,
2165 6434U, 2988U, 6885U, 4200U, 1727U, 5035U, 2137U, 1473U,
2166 2892U, 3360U, 1281U, 2907U, 3375U, 1297U, 3008U, 6905U,
2167 2583U, 2600U, 1403U, 7748U, 441U, 8036U, 7456U, 8021U,
2168 7441U, 7962U, 7304U, 8006U, 7392U, 8052U, 7499U, 2780U,
2169 135U, 6542U,
2170};
2171
2172static inline void InitR600MCInstrInfo(MCInstrInfo *II) {
2173 II->InitMCInstrInfo(R600Descs.Insts, R600InstrNameIndices, R600InstrNameData, nullptr, nullptr, 650);
2174}
2175
2176} // end namespace llvm
2177#endif // GET_INSTRINFO_MC_DESC
2178
2179#ifdef GET_INSTRINFO_HEADER
2180#undef GET_INSTRINFO_HEADER
2181namespace llvm {
2182struct R600GenInstrInfo : public TargetInstrInfo {
2183 explicit R600GenInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
2184 ~R600GenInstrInfo() override = default;
2185
2186};
2187} // end namespace llvm
2188#endif // GET_INSTRINFO_HEADER
2189
2190#ifdef GET_INSTRINFO_HELPER_DECLS
2191#undef GET_INSTRINFO_HELPER_DECLS
2192
2193
2194#endif // GET_INSTRINFO_HELPER_DECLS
2195
2196#ifdef GET_INSTRINFO_HELPERS
2197#undef GET_INSTRINFO_HELPERS
2198
2199#endif // GET_INSTRINFO_HELPERS
2200
2201#ifdef GET_INSTRINFO_CTOR_DTOR
2202#undef GET_INSTRINFO_CTOR_DTOR
2203namespace llvm {
2204extern const R600InstrTable R600Descs;
2205extern const unsigned R600InstrNameIndices[];
2206extern const char R600InstrNameData[];
2207R600GenInstrInfo::R600GenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
2208 : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
2209 InitMCInstrInfo(R600Descs.Insts, R600InstrNameIndices, R600InstrNameData, nullptr, nullptr, 650);
2210}
2211} // end namespace llvm
2212#endif // GET_INSTRINFO_CTOR_DTOR
2213
2214#ifdef GET_INSTRINFO_OPERAND_ENUM
2215#undef GET_INSTRINFO_OPERAND_ENUM
2216namespace llvm::R600 {
2217enum class OpName {
2218 ADDR = 0,
2219 COUNT = 1,
2220 Enabled = 2,
2221 KCACHE_ADDR0 = 3,
2222 KCACHE_ADDR1 = 4,
2223 KCACHE_BANK0 = 5,
2224 KCACHE_BANK1 = 6,
2225 KCACHE_MODE0 = 7,
2226 KCACHE_MODE1 = 8,
2227 addr = 9,
2228 bank_swizzle = 10,
2229 chan = 11,
2230 clamp = 12,
2231 clamp_W = 13,
2232 clamp_X = 14,
2233 clamp_Y = 15,
2234 clamp_Z = 16,
2235 dst = 17,
2236 dst_rel = 18,
2237 dst_rel_W = 19,
2238 dst_rel_X = 20,
2239 dst_rel_Y = 21,
2240 dst_rel_Z = 22,
2241 last = 23,
2242 literal = 24,
2243 literal0 = 25,
2244 literal1 = 26,
2245 omod = 27,
2246 omod_W = 28,
2247 omod_X = 29,
2248 omod_Y = 30,
2249 omod_Z = 31,
2250 pred_sel = 32,
2251 pred_sel_W = 33,
2252 pred_sel_X = 34,
2253 pred_sel_Y = 35,
2254 pred_sel_Z = 36,
2255 src0 = 37,
2256 src0_W = 38,
2257 src0_X = 39,
2258 src0_Y = 40,
2259 src0_Z = 41,
2260 src0_abs = 42,
2261 src0_abs_W = 43,
2262 src0_abs_X = 44,
2263 src0_abs_Y = 45,
2264 src0_abs_Z = 46,
2265 src0_neg = 47,
2266 src0_neg_W = 48,
2267 src0_neg_X = 49,
2268 src0_neg_Y = 50,
2269 src0_neg_Z = 51,
2270 src0_rel = 52,
2271 src0_rel_W = 53,
2272 src0_rel_X = 54,
2273 src0_rel_Y = 55,
2274 src0_rel_Z = 56,
2275 src0_sel = 57,
2276 src0_sel_W = 58,
2277 src0_sel_X = 59,
2278 src0_sel_Y = 60,
2279 src0_sel_Z = 61,
2280 src1 = 62,
2281 src1_W = 63,
2282 src1_X = 64,
2283 src1_Y = 65,
2284 src1_Z = 66,
2285 src1_abs = 67,
2286 src1_abs_W = 68,
2287 src1_abs_X = 69,
2288 src1_abs_Y = 70,
2289 src1_abs_Z = 71,
2290 src1_neg = 72,
2291 src1_neg_W = 73,
2292 src1_neg_X = 74,
2293 src1_neg_Y = 75,
2294 src1_neg_Z = 76,
2295 src1_rel = 77,
2296 src1_rel_W = 78,
2297 src1_rel_X = 79,
2298 src1_rel_Y = 80,
2299 src1_rel_Z = 81,
2300 src1_sel = 82,
2301 src1_sel_W = 83,
2302 src1_sel_X = 84,
2303 src1_sel_Y = 85,
2304 src1_sel_Z = 86,
2305 src2 = 87,
2306 src2_neg = 88,
2307 src2_rel = 89,
2308 src2_sel = 90,
2309 update_exec_mask = 91,
2310 update_exec_mask_W = 92,
2311 update_exec_mask_X = 93,
2312 update_exec_mask_Y = 94,
2313 update_exec_mask_Z = 95,
2314 update_pred = 96,
2315 update_pred_W = 97,
2316 update_pred_X = 98,
2317 update_pred_Y = 99,
2318 update_pred_Z = 100,
2319 val = 101,
2320 write = 102,
2321 write_W = 103,
2322 write_X = 104,
2323 write_Y = 105,
2324 write_Z = 106,
2325 NUM_OPERAND_NAMES = 107,
2326}; // enum class OpName
2327
2328LLVM_READONLY
2329int16_t getNamedOperandIdx(uint16_t Opcode, OpName Name);
2330} // end namespace llvm::R600
2331#endif //GET_INSTRINFO_OPERAND_ENUM
2332
2333#ifdef GET_INSTRINFO_NAMED_OPS
2334#undef GET_INSTRINFO_NAMED_OPS
2335namespace llvm::R600 {
2336LLVM_READONLY
2337int16_t getNamedOperandIdx(uint16_t Opcode, OpName Name) {
2338 assert(Name != OpName::NUM_OPERAND_NAMES);
2339 static constexpr int8_t OperandMap[][107] = {
2340 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2341 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 9, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, 7, -1, -1, -1, -1, -1, -1, -1, -1, 8, -1, -1, -1, -1, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2, -1, -1, -1, -1, 3, -1, -1, -1, -1, 4, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5, -1, -1, -1, -1, 6, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2342 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 12, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, 10, -1, -1, -1, -1, -1, -1, -1, -1, 11, -1, -1, -1, -1, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2, -1, -1, -1, -1, 3, -1, -1, -1, -1, 4, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5, -1, -1, -1, -1, 6, -1, -1, -1, -1, 7, -1, 8, 9, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2343 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 6, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, 4, -1, -1, -1, -1, -1, -1, -1, -1, 5, -1, -1, -1, -1, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2, -1, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2344 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 18, -1, 2, -1, -1, -1, -1, 0, 1, -1, -1, -1, -1, 15, 17, -1, -1, -1, -1, -1, -1, -1, 16, -1, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4, -1, -1, -1, -1, 5, -1, -1, -1, -1, 6, -1, -1, -1, -1, 7, -1, -1, -1, -1, -1, -1, -1, -1, -1, 8, -1, -1, -1, -1, 9, -1, -1, -1, -1, 10, -1, -1, -1, -1, 11, 12, 13, 14, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2345 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 13, -1, 4, -1, -1, -1, -1, 0, 3, -1, -1, -1, -1, 10, 12, -1, -1, 2, -1, -1, -1, -1, 11, -1, -1, -1, -1, 5, -1, -1, -1, -1, 8, -1, -1, -1, -1, 6, -1, -1, -1, -1, 7, -1, -1, -1, -1, 9, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, -1, -1, -1, -1, },
2346 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 20, -1, 6, -1, -1, -1, -1, 0, 5, -1, -1, -1, -1, 17, 19, -1, -1, 4, -1, -1, -1, -1, 18, -1, -1, -1, -1, 7, -1, -1, -1, -1, 10, -1, -1, -1, -1, 8, -1, -1, -1, -1, 9, -1, -1, -1, -1, 11, -1, -1, -1, -1, 12, -1, -1, -1, -1, 15, -1, -1, -1, -1, 13, -1, -1, -1, -1, 14, -1, -1, -1, -1, 16, -1, -1, -1, -1, -1, -1, -1, -1, 1, -1, -1, -1, -1, 2, -1, -1, -1, -1, -1, 3, -1, -1, -1, -1, },
2347 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 57, 6, 23, 40, 0, -1, 56, 5, 22, 39, -1, -1, 69, 70, -1, 55, 4, 21, 38, -1, 68, 17, 34, 51, -1, 58, 7, 24, 41, -1, 61, 10, 27, 44, -1, 59, 8, 25, 42, -1, 60, 9, 26, 43, -1, 62, 11, 28, 45, -1, 63, 12, 29, 46, -1, 66, 15, 32, 49, -1, 64, 13, 30, 47, -1, 65, 14, 31, 48, -1, 67, 16, 33, 50, -1, -1, -1, -1, -1, 52, 1, 18, 35, -1, 53, 2, 19, 36, -1, -1, 54, 3, 20, 37, },
2348 {-1, -1, -1, -1, -1, -1, -1, -1, -1, 1, -1, 3, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2349 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 8, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 6, -1, -1, -1, -1, -1, -1, -1, -1, 7, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, -1, -1, -1, -1, 2, -1, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4, -1, -1, -1, -1, 5, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2350 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 11, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 9, -1, -1, -1, -1, -1, -1, -1, -1, 10, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, -1, -1, -1, -1, 2, -1, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4, -1, -1, -1, -1, 5, -1, -1, -1, -1, 6, -1, 7, 8, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2351 {-1, -1, -1, -1, -1, -1, -1, -1, -1, 1, -1, 3, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, },
2352 {0, 7, 8, 5, 6, 1, 2, 3, 4, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2353 };
2354 switch(Opcode) {
2355 case R600::CUBE_eg_pseudo:
2356 case R600::CUBE_r600_pseudo:
2357 return OperandMap[0][static_cast<unsigned>(Name)];
2358 case R600::LDS_ADD_RET:
2359 case R600::LDS_AND_RET:
2360 case R600::LDS_MAX_INT_RET:
2361 case R600::LDS_MAX_UINT_RET:
2362 case R600::LDS_MIN_INT_RET:
2363 case R600::LDS_MIN_UINT_RET:
2364 case R600::LDS_OR_RET:
2365 case R600::LDS_SUB_RET:
2366 case R600::LDS_WRXCHG_RET:
2367 case R600::LDS_XOR_RET:
2368 return OperandMap[1][static_cast<unsigned>(Name)];
2369 case R600::LDS_CMPST_RET:
2370 return OperandMap[2][static_cast<unsigned>(Name)];
2371 case R600::LDS_BYTE_READ_RET:
2372 case R600::LDS_READ_RET:
2373 case R600::LDS_SHORT_READ_RET:
2374 case R600::LDS_UBYTE_READ_RET:
2375 case R600::LDS_USHORT_READ_RET:
2376 return OperandMap[3][static_cast<unsigned>(Name)];
2377 case R600::BFE_INT_eg:
2378 case R600::BFE_UINT_eg:
2379 case R600::BFI_INT_eg:
2380 case R600::BIT_ALIGN_INT_eg:
2381 case R600::CNDE_INT:
2382 case R600::CNDE_eg:
2383 case R600::CNDE_r600:
2384 case R600::CNDGE_INT:
2385 case R600::CNDGE_eg:
2386 case R600::CNDGE_r600:
2387 case R600::CNDGT_INT:
2388 case R600::CNDGT_eg:
2389 case R600::CNDGT_r600:
2390 case R600::FMA_eg:
2391 case R600::MULADD_IEEE_eg:
2392 case R600::MULADD_IEEE_r600:
2393 case R600::MULADD_INT24_cm:
2394 case R600::MULADD_UINT24_eg:
2395 case R600::MULADD_eg:
2396 case R600::MULADD_r600:
2397 case R600::MUL_LIT_eg:
2398 case R600::MUL_LIT_r600:
2399 return OperandMap[4][static_cast<unsigned>(Name)];
2400 case R600::BCNT_INT:
2401 case R600::CEIL:
2402 case R600::COS_cm:
2403 case R600::COS_eg:
2404 case R600::COS_r600:
2405 case R600::COS_r700:
2406 case R600::EXP_IEEE_cm:
2407 case R600::EXP_IEEE_eg:
2408 case R600::EXP_IEEE_r600:
2409 case R600::FFBH_UINT:
2410 case R600::FFBL_INT:
2411 case R600::FLOOR:
2412 case R600::FLT16_TO_FLT32:
2413 case R600::FLT32_TO_FLT16:
2414 case R600::FLT_TO_INT_eg:
2415 case R600::FLT_TO_INT_r600:
2416 case R600::FLT_TO_UINT_eg:
2417 case R600::FLT_TO_UINT_r600:
2418 case R600::FRACT:
2419 case R600::INTERP_LOAD_P0:
2420 case R600::INT_TO_FLT_eg:
2421 case R600::INT_TO_FLT_r600:
2422 case R600::LOG_CLAMPED_eg:
2423 case R600::LOG_CLAMPED_r600:
2424 case R600::LOG_IEEE_cm:
2425 case R600::LOG_IEEE_eg:
2426 case R600::LOG_IEEE_r600:
2427 case R600::MOV:
2428 case R600::MOVA_INT_eg:
2429 case R600::NOT_INT:
2430 case R600::RECIPSQRT_CLAMPED_cm:
2431 case R600::RECIPSQRT_CLAMPED_eg:
2432 case R600::RECIPSQRT_CLAMPED_r600:
2433 case R600::RECIPSQRT_IEEE_cm:
2434 case R600::RECIPSQRT_IEEE_eg:
2435 case R600::RECIPSQRT_IEEE_r600:
2436 case R600::RECIP_CLAMPED_cm:
2437 case R600::RECIP_CLAMPED_eg:
2438 case R600::RECIP_CLAMPED_r600:
2439 case R600::RECIP_IEEE_cm:
2440 case R600::RECIP_IEEE_eg:
2441 case R600::RECIP_IEEE_r600:
2442 case R600::RECIP_UINT_eg:
2443 case R600::RECIP_UINT_r600:
2444 case R600::RNDNE:
2445 case R600::SIN_cm:
2446 case R600::SIN_eg:
2447 case R600::SIN_r600:
2448 case R600::SIN_r700:
2449 case R600::TRUNC:
2450 case R600::UINT_TO_FLT_eg:
2451 case R600::UINT_TO_FLT_r600:
2452 return OperandMap[5][static_cast<unsigned>(Name)];
2453 case R600::ADD:
2454 case R600::ADDC_UINT:
2455 case R600::ADD_INT:
2456 case R600::AND_INT:
2457 case R600::ASHR_eg:
2458 case R600::ASHR_r600:
2459 case R600::BFM_INT_eg:
2460 case R600::CUBE_eg_real:
2461 case R600::CUBE_r600_real:
2462 case R600::DOT4_eg:
2463 case R600::DOT4_r600:
2464 case R600::INTERP_XY:
2465 case R600::INTERP_ZW:
2466 case R600::KILLGT:
2467 case R600::LSHL_eg:
2468 case R600::LSHL_r600:
2469 case R600::LSHR_eg:
2470 case R600::LSHR_r600:
2471 case R600::MAX:
2472 case R600::MAX_DX10:
2473 case R600::MAX_INT:
2474 case R600::MAX_UINT:
2475 case R600::MIN:
2476 case R600::MIN_DX10:
2477 case R600::MIN_INT:
2478 case R600::MIN_UINT:
2479 case R600::MUL:
2480 case R600::MULHI_INT_cm:
2481 case R600::MULHI_INT_cm24:
2482 case R600::MULHI_INT_eg:
2483 case R600::MULHI_INT_r600:
2484 case R600::MULHI_UINT24_eg:
2485 case R600::MULHI_UINT_cm:
2486 case R600::MULHI_UINT_cm24:
2487 case R600::MULHI_UINT_eg:
2488 case R600::MULHI_UINT_r600:
2489 case R600::MULLO_INT_cm:
2490 case R600::MULLO_INT_eg:
2491 case R600::MULLO_INT_r600:
2492 case R600::MULLO_UINT_cm:
2493 case R600::MULLO_UINT_eg:
2494 case R600::MULLO_UINT_r600:
2495 case R600::MUL_IEEE:
2496 case R600::MUL_INT24_cm:
2497 case R600::MUL_UINT24_eg:
2498 case R600::OR_INT:
2499 case R600::PRED_SETE:
2500 case R600::PRED_SETE_INT:
2501 case R600::PRED_SETGE:
2502 case R600::PRED_SETGE_INT:
2503 case R600::PRED_SETGT:
2504 case R600::PRED_SETGT_INT:
2505 case R600::PRED_SETNE:
2506 case R600::PRED_SETNE_INT:
2507 case R600::SETE:
2508 case R600::SETE_DX10:
2509 case R600::SETE_INT:
2510 case R600::SETGE_DX10:
2511 case R600::SETGE_INT:
2512 case R600::SETGE_UINT:
2513 case R600::SETGT_DX10:
2514 case R600::SETGT_INT:
2515 case R600::SETGT_UINT:
2516 case R600::SETNE_DX10:
2517 case R600::SETNE_INT:
2518 case R600::SGE:
2519 case R600::SGT:
2520 case R600::SNE:
2521 case R600::SUBB_UINT:
2522 case R600::SUB_INT:
2523 case R600::XOR_INT:
2524 return OperandMap[6][static_cast<unsigned>(Name)];
2525 case R600::DOT_4:
2526 return OperandMap[7][static_cast<unsigned>(Name)];
2527 case R600::R600_RegisterLoad:
2528 return OperandMap[8][static_cast<unsigned>(Name)];
2529 case R600::LDS_ADD:
2530 case R600::LDS_AND:
2531 case R600::LDS_BYTE_WRITE:
2532 case R600::LDS_MAX_INT:
2533 case R600::LDS_MAX_UINT:
2534 case R600::LDS_MIN_INT:
2535 case R600::LDS_MIN_UINT:
2536 case R600::LDS_OR:
2537 case R600::LDS_SHORT_WRITE:
2538 case R600::LDS_SUB:
2539 case R600::LDS_WRITE:
2540 case R600::LDS_WRXCHG:
2541 case R600::LDS_XOR:
2542 return OperandMap[9][static_cast<unsigned>(Name)];
2543 case R600::LDS_CMPST:
2544 return OperandMap[10][static_cast<unsigned>(Name)];
2545 case R600::R600_RegisterStore:
2546 return OperandMap[11][static_cast<unsigned>(Name)];
2547 case R600::CF_ALU:
2548 case R600::CF_ALU_BREAK:
2549 case R600::CF_ALU_CONTINUE:
2550 case R600::CF_ALU_ELSE_AFTER:
2551 case R600::CF_ALU_POP_AFTER:
2552 case R600::CF_ALU_PUSH_BEFORE:
2553 return OperandMap[12][static_cast<unsigned>(Name)];
2554 default: return -1;
2555 }
2556}
2557} // end namespace llvm::R600
2558#endif //GET_INSTRINFO_NAMED_OPS
2559
2560#ifdef GET_INSTRINFO_MC_HELPER_DECLS
2561#undef GET_INSTRINFO_MC_HELPER_DECLS
2562
2563namespace llvm {
2564class MCInst;
2565class FeatureBitset;
2566
2567namespace R600_MC {
2568
2569void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
2570
2571} // end namespace R600_MC
2572} // end namespace llvm
2573
2574#endif // GET_INSTRINFO_MC_HELPER_DECLS
2575
2576#ifdef GET_INSTRINFO_MC_HELPERS
2577#undef GET_INSTRINFO_MC_HELPERS
2578
2579namespace llvm::R600_MC {
2580} // end namespace llvm::R600_MC
2581#endif // GET_GENISTRINFO_MC_HELPERS
2582
2583#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
2584 defined(GET_AVAILABLE_OPCODE_CHECKER)
2585#define GET_COMPUTE_FEATURES
2586#endif
2587#ifdef GET_COMPUTE_FEATURES
2588#undef GET_COMPUTE_FEATURES
2589namespace llvm::R600_MC {
2590// Bits for subtarget features that participate in instruction matching.
2591enum SubtargetFeatureBits : uint8_t {
2592};
2593
2594inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
2595 FeatureBitset Features;
2596 return Features;
2597}
2598
2599inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
2600 enum : uint8_t {
2601 CEFBS_None,
2602 };
2603
2604 static constexpr FeatureBitset FeatureBitsets[] = {
2605 {}, // CEFBS_None
2606 };
2607 static constexpr uint8_t RequiredFeaturesRefs[] = {
2608 CEFBS_None, // PHI = 0
2609 CEFBS_None, // INLINEASM = 1
2610 CEFBS_None, // INLINEASM_BR = 2
2611 CEFBS_None, // CFI_INSTRUCTION = 3
2612 CEFBS_None, // EH_LABEL = 4
2613 CEFBS_None, // GC_LABEL = 5
2614 CEFBS_None, // ANNOTATION_LABEL = 6
2615 CEFBS_None, // KILL = 7
2616 CEFBS_None, // EXTRACT_SUBREG = 8
2617 CEFBS_None, // INSERT_SUBREG = 9
2618 CEFBS_None, // IMPLICIT_DEF = 10
2619 CEFBS_None, // INIT_UNDEF = 11
2620 CEFBS_None, // SUBREG_TO_REG = 12
2621 CEFBS_None, // COPY_TO_REGCLASS = 13
2622 CEFBS_None, // DBG_VALUE = 14
2623 CEFBS_None, // DBG_VALUE_LIST = 15
2624 CEFBS_None, // DBG_INSTR_REF = 16
2625 CEFBS_None, // DBG_PHI = 17
2626 CEFBS_None, // DBG_LABEL = 18
2627 CEFBS_None, // REG_SEQUENCE = 19
2628 CEFBS_None, // COPY = 20
2629 CEFBS_None, // BUNDLE = 21
2630 CEFBS_None, // LIFETIME_START = 22
2631 CEFBS_None, // LIFETIME_END = 23
2632 CEFBS_None, // PSEUDO_PROBE = 24
2633 CEFBS_None, // ARITH_FENCE = 25
2634 CEFBS_None, // STACKMAP = 26
2635 CEFBS_None, // FENTRY_CALL = 27
2636 CEFBS_None, // PATCHPOINT = 28
2637 CEFBS_None, // LOAD_STACK_GUARD = 29
2638 CEFBS_None, // PREALLOCATED_SETUP = 30
2639 CEFBS_None, // PREALLOCATED_ARG = 31
2640 CEFBS_None, // STATEPOINT = 32
2641 CEFBS_None, // LOCAL_ESCAPE = 33
2642 CEFBS_None, // FAULTING_OP = 34
2643 CEFBS_None, // PATCHABLE_OP = 35
2644 CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 36
2645 CEFBS_None, // PATCHABLE_RET = 37
2646 CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 38
2647 CEFBS_None, // PATCHABLE_TAIL_CALL = 39
2648 CEFBS_None, // PATCHABLE_EVENT_CALL = 40
2649 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 41
2650 CEFBS_None, // ICALL_BRANCH_FUNNEL = 42
2651 CEFBS_None, // FAKE_USE = 43
2652 CEFBS_None, // MEMBARRIER = 44
2653 CEFBS_None, // JUMP_TABLE_DEBUG_INFO = 45
2654 CEFBS_None, // CONVERGENCECTRL_ENTRY = 46
2655 CEFBS_None, // CONVERGENCECTRL_ANCHOR = 47
2656 CEFBS_None, // CONVERGENCECTRL_LOOP = 48
2657 CEFBS_None, // CONVERGENCECTRL_GLUE = 49
2658 CEFBS_None, // G_ASSERT_SEXT = 50
2659 CEFBS_None, // G_ASSERT_ZEXT = 51
2660 CEFBS_None, // G_ASSERT_ALIGN = 52
2661 CEFBS_None, // G_ADD = 53
2662 CEFBS_None, // G_SUB = 54
2663 CEFBS_None, // G_MUL = 55
2664 CEFBS_None, // G_SDIV = 56
2665 CEFBS_None, // G_UDIV = 57
2666 CEFBS_None, // G_SREM = 58
2667 CEFBS_None, // G_UREM = 59
2668 CEFBS_None, // G_SDIVREM = 60
2669 CEFBS_None, // G_UDIVREM = 61
2670 CEFBS_None, // G_AND = 62
2671 CEFBS_None, // G_OR = 63
2672 CEFBS_None, // G_XOR = 64
2673 CEFBS_None, // G_ABDS = 65
2674 CEFBS_None, // G_ABDU = 66
2675 CEFBS_None, // G_IMPLICIT_DEF = 67
2676 CEFBS_None, // G_PHI = 68
2677 CEFBS_None, // G_FRAME_INDEX = 69
2678 CEFBS_None, // G_GLOBAL_VALUE = 70
2679 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE = 71
2680 CEFBS_None, // G_CONSTANT_POOL = 72
2681 CEFBS_None, // G_EXTRACT = 73
2682 CEFBS_None, // G_UNMERGE_VALUES = 74
2683 CEFBS_None, // G_INSERT = 75
2684 CEFBS_None, // G_MERGE_VALUES = 76
2685 CEFBS_None, // G_BUILD_VECTOR = 77
2686 CEFBS_None, // G_BUILD_VECTOR_TRUNC = 78
2687 CEFBS_None, // G_CONCAT_VECTORS = 79
2688 CEFBS_None, // G_PTRTOINT = 80
2689 CEFBS_None, // G_INTTOPTR = 81
2690 CEFBS_None, // G_BITCAST = 82
2691 CEFBS_None, // G_FREEZE = 83
2692 CEFBS_None, // G_CONSTANT_FOLD_BARRIER = 84
2693 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND = 85
2694 CEFBS_None, // G_INTRINSIC_TRUNC = 86
2695 CEFBS_None, // G_INTRINSIC_ROUND = 87
2696 CEFBS_None, // G_INTRINSIC_LRINT = 88
2697 CEFBS_None, // G_INTRINSIC_LLRINT = 89
2698 CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 90
2699 CEFBS_None, // G_READCYCLECOUNTER = 91
2700 CEFBS_None, // G_READSTEADYCOUNTER = 92
2701 CEFBS_None, // G_LOAD = 93
2702 CEFBS_None, // G_SEXTLOAD = 94
2703 CEFBS_None, // G_ZEXTLOAD = 95
2704 CEFBS_None, // G_INDEXED_LOAD = 96
2705 CEFBS_None, // G_INDEXED_SEXTLOAD = 97
2706 CEFBS_None, // G_INDEXED_ZEXTLOAD = 98
2707 CEFBS_None, // G_STORE = 99
2708 CEFBS_None, // G_INDEXED_STORE = 100
2709 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 101
2710 CEFBS_None, // G_ATOMIC_CMPXCHG = 102
2711 CEFBS_None, // G_ATOMICRMW_XCHG = 103
2712 CEFBS_None, // G_ATOMICRMW_ADD = 104
2713 CEFBS_None, // G_ATOMICRMW_SUB = 105
2714 CEFBS_None, // G_ATOMICRMW_AND = 106
2715 CEFBS_None, // G_ATOMICRMW_NAND = 107
2716 CEFBS_None, // G_ATOMICRMW_OR = 108
2717 CEFBS_None, // G_ATOMICRMW_XOR = 109
2718 CEFBS_None, // G_ATOMICRMW_MAX = 110
2719 CEFBS_None, // G_ATOMICRMW_MIN = 111
2720 CEFBS_None, // G_ATOMICRMW_UMAX = 112
2721 CEFBS_None, // G_ATOMICRMW_UMIN = 113
2722 CEFBS_None, // G_ATOMICRMW_FADD = 114
2723 CEFBS_None, // G_ATOMICRMW_FSUB = 115
2724 CEFBS_None, // G_ATOMICRMW_FMAX = 116
2725 CEFBS_None, // G_ATOMICRMW_FMIN = 117
2726 CEFBS_None, // G_ATOMICRMW_FMAXIMUM = 118
2727 CEFBS_None, // G_ATOMICRMW_FMINIMUM = 119
2728 CEFBS_None, // G_ATOMICRMW_UINC_WRAP = 120
2729 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP = 121
2730 CEFBS_None, // G_ATOMICRMW_USUB_COND = 122
2731 CEFBS_None, // G_ATOMICRMW_USUB_SAT = 123
2732 CEFBS_None, // G_FENCE = 124
2733 CEFBS_None, // G_PREFETCH = 125
2734 CEFBS_None, // G_BRCOND = 126
2735 CEFBS_None, // G_BRINDIRECT = 127
2736 CEFBS_None, // G_INVOKE_REGION_START = 128
2737 CEFBS_None, // G_INTRINSIC = 129
2738 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 130
2739 CEFBS_None, // G_INTRINSIC_CONVERGENT = 131
2740 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 132
2741 CEFBS_None, // G_ANYEXT = 133
2742 CEFBS_None, // G_TRUNC = 134
2743 CEFBS_None, // G_CONSTANT = 135
2744 CEFBS_None, // G_FCONSTANT = 136
2745 CEFBS_None, // G_VASTART = 137
2746 CEFBS_None, // G_VAARG = 138
2747 CEFBS_None, // G_SEXT = 139
2748 CEFBS_None, // G_SEXT_INREG = 140
2749 CEFBS_None, // G_ZEXT = 141
2750 CEFBS_None, // G_SHL = 142
2751 CEFBS_None, // G_LSHR = 143
2752 CEFBS_None, // G_ASHR = 144
2753 CEFBS_None, // G_FSHL = 145
2754 CEFBS_None, // G_FSHR = 146
2755 CEFBS_None, // G_ROTR = 147
2756 CEFBS_None, // G_ROTL = 148
2757 CEFBS_None, // G_ICMP = 149
2758 CEFBS_None, // G_FCMP = 150
2759 CEFBS_None, // G_SCMP = 151
2760 CEFBS_None, // G_UCMP = 152
2761 CEFBS_None, // G_SELECT = 153
2762 CEFBS_None, // G_UADDO = 154
2763 CEFBS_None, // G_UADDE = 155
2764 CEFBS_None, // G_USUBO = 156
2765 CEFBS_None, // G_USUBE = 157
2766 CEFBS_None, // G_SADDO = 158
2767 CEFBS_None, // G_SADDE = 159
2768 CEFBS_None, // G_SSUBO = 160
2769 CEFBS_None, // G_SSUBE = 161
2770 CEFBS_None, // G_UMULO = 162
2771 CEFBS_None, // G_SMULO = 163
2772 CEFBS_None, // G_UMULH = 164
2773 CEFBS_None, // G_SMULH = 165
2774 CEFBS_None, // G_UADDSAT = 166
2775 CEFBS_None, // G_SADDSAT = 167
2776 CEFBS_None, // G_USUBSAT = 168
2777 CEFBS_None, // G_SSUBSAT = 169
2778 CEFBS_None, // G_USHLSAT = 170
2779 CEFBS_None, // G_SSHLSAT = 171
2780 CEFBS_None, // G_SMULFIX = 172
2781 CEFBS_None, // G_UMULFIX = 173
2782 CEFBS_None, // G_SMULFIXSAT = 174
2783 CEFBS_None, // G_UMULFIXSAT = 175
2784 CEFBS_None, // G_SDIVFIX = 176
2785 CEFBS_None, // G_UDIVFIX = 177
2786 CEFBS_None, // G_SDIVFIXSAT = 178
2787 CEFBS_None, // G_UDIVFIXSAT = 179
2788 CEFBS_None, // G_FADD = 180
2789 CEFBS_None, // G_FSUB = 181
2790 CEFBS_None, // G_FMUL = 182
2791 CEFBS_None, // G_FMA = 183
2792 CEFBS_None, // G_FMAD = 184
2793 CEFBS_None, // G_FDIV = 185
2794 CEFBS_None, // G_FREM = 186
2795 CEFBS_None, // G_FPOW = 187
2796 CEFBS_None, // G_FPOWI = 188
2797 CEFBS_None, // G_FEXP = 189
2798 CEFBS_None, // G_FEXP2 = 190
2799 CEFBS_None, // G_FEXP10 = 191
2800 CEFBS_None, // G_FLOG = 192
2801 CEFBS_None, // G_FLOG2 = 193
2802 CEFBS_None, // G_FLOG10 = 194
2803 CEFBS_None, // G_FLDEXP = 195
2804 CEFBS_None, // G_FFREXP = 196
2805 CEFBS_None, // G_FNEG = 197
2806 CEFBS_None, // G_FPEXT = 198
2807 CEFBS_None, // G_FPTRUNC = 199
2808 CEFBS_None, // G_FPTOSI = 200
2809 CEFBS_None, // G_FPTOUI = 201
2810 CEFBS_None, // G_SITOFP = 202
2811 CEFBS_None, // G_UITOFP = 203
2812 CEFBS_None, // G_FPTOSI_SAT = 204
2813 CEFBS_None, // G_FPTOUI_SAT = 205
2814 CEFBS_None, // G_FABS = 206
2815 CEFBS_None, // G_FCOPYSIGN = 207
2816 CEFBS_None, // G_IS_FPCLASS = 208
2817 CEFBS_None, // G_FCANONICALIZE = 209
2818 CEFBS_None, // G_FMINNUM = 210
2819 CEFBS_None, // G_FMAXNUM = 211
2820 CEFBS_None, // G_FMINNUM_IEEE = 212
2821 CEFBS_None, // G_FMAXNUM_IEEE = 213
2822 CEFBS_None, // G_FMINIMUM = 214
2823 CEFBS_None, // G_FMAXIMUM = 215
2824 CEFBS_None, // G_FMINIMUMNUM = 216
2825 CEFBS_None, // G_FMAXIMUMNUM = 217
2826 CEFBS_None, // G_GET_FPENV = 218
2827 CEFBS_None, // G_SET_FPENV = 219
2828 CEFBS_None, // G_RESET_FPENV = 220
2829 CEFBS_None, // G_GET_FPMODE = 221
2830 CEFBS_None, // G_SET_FPMODE = 222
2831 CEFBS_None, // G_RESET_FPMODE = 223
2832 CEFBS_None, // G_PTR_ADD = 224
2833 CEFBS_None, // G_PTRMASK = 225
2834 CEFBS_None, // G_SMIN = 226
2835 CEFBS_None, // G_SMAX = 227
2836 CEFBS_None, // G_UMIN = 228
2837 CEFBS_None, // G_UMAX = 229
2838 CEFBS_None, // G_ABS = 230
2839 CEFBS_None, // G_LROUND = 231
2840 CEFBS_None, // G_LLROUND = 232
2841 CEFBS_None, // G_BR = 233
2842 CEFBS_None, // G_BRJT = 234
2843 CEFBS_None, // G_VSCALE = 235
2844 CEFBS_None, // G_INSERT_SUBVECTOR = 236
2845 CEFBS_None, // G_EXTRACT_SUBVECTOR = 237
2846 CEFBS_None, // G_INSERT_VECTOR_ELT = 238
2847 CEFBS_None, // G_EXTRACT_VECTOR_ELT = 239
2848 CEFBS_None, // G_SHUFFLE_VECTOR = 240
2849 CEFBS_None, // G_SPLAT_VECTOR = 241
2850 CEFBS_None, // G_STEP_VECTOR = 242
2851 CEFBS_None, // G_VECTOR_COMPRESS = 243
2852 CEFBS_None, // G_CTTZ = 244
2853 CEFBS_None, // G_CTTZ_ZERO_UNDEF = 245
2854 CEFBS_None, // G_CTLZ = 246
2855 CEFBS_None, // G_CTLZ_ZERO_UNDEF = 247
2856 CEFBS_None, // G_CTPOP = 248
2857 CEFBS_None, // G_BSWAP = 249
2858 CEFBS_None, // G_BITREVERSE = 250
2859 CEFBS_None, // G_FCEIL = 251
2860 CEFBS_None, // G_FCOS = 252
2861 CEFBS_None, // G_FSIN = 253
2862 CEFBS_None, // G_FSINCOS = 254
2863 CEFBS_None, // G_FTAN = 255
2864 CEFBS_None, // G_FACOS = 256
2865 CEFBS_None, // G_FASIN = 257
2866 CEFBS_None, // G_FATAN = 258
2867 CEFBS_None, // G_FATAN2 = 259
2868 CEFBS_None, // G_FCOSH = 260
2869 CEFBS_None, // G_FSINH = 261
2870 CEFBS_None, // G_FTANH = 262
2871 CEFBS_None, // G_FSQRT = 263
2872 CEFBS_None, // G_FFLOOR = 264
2873 CEFBS_None, // G_FRINT = 265
2874 CEFBS_None, // G_FNEARBYINT = 266
2875 CEFBS_None, // G_ADDRSPACE_CAST = 267
2876 CEFBS_None, // G_BLOCK_ADDR = 268
2877 CEFBS_None, // G_JUMP_TABLE = 269
2878 CEFBS_None, // G_DYN_STACKALLOC = 270
2879 CEFBS_None, // G_STACKSAVE = 271
2880 CEFBS_None, // G_STACKRESTORE = 272
2881 CEFBS_None, // G_STRICT_FADD = 273
2882 CEFBS_None, // G_STRICT_FSUB = 274
2883 CEFBS_None, // G_STRICT_FMUL = 275
2884 CEFBS_None, // G_STRICT_FDIV = 276
2885 CEFBS_None, // G_STRICT_FREM = 277
2886 CEFBS_None, // G_STRICT_FMA = 278
2887 CEFBS_None, // G_STRICT_FSQRT = 279
2888 CEFBS_None, // G_STRICT_FLDEXP = 280
2889 CEFBS_None, // G_READ_REGISTER = 281
2890 CEFBS_None, // G_WRITE_REGISTER = 282
2891 CEFBS_None, // G_MEMCPY = 283
2892 CEFBS_None, // G_MEMCPY_INLINE = 284
2893 CEFBS_None, // G_MEMMOVE = 285
2894 CEFBS_None, // G_MEMSET = 286
2895 CEFBS_None, // G_BZERO = 287
2896 CEFBS_None, // G_TRAP = 288
2897 CEFBS_None, // G_DEBUGTRAP = 289
2898 CEFBS_None, // G_UBSANTRAP = 290
2899 CEFBS_None, // G_VECREDUCE_SEQ_FADD = 291
2900 CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 292
2901 CEFBS_None, // G_VECREDUCE_FADD = 293
2902 CEFBS_None, // G_VECREDUCE_FMUL = 294
2903 CEFBS_None, // G_VECREDUCE_FMAX = 295
2904 CEFBS_None, // G_VECREDUCE_FMIN = 296
2905 CEFBS_None, // G_VECREDUCE_FMAXIMUM = 297
2906 CEFBS_None, // G_VECREDUCE_FMINIMUM = 298
2907 CEFBS_None, // G_VECREDUCE_ADD = 299
2908 CEFBS_None, // G_VECREDUCE_MUL = 300
2909 CEFBS_None, // G_VECREDUCE_AND = 301
2910 CEFBS_None, // G_VECREDUCE_OR = 302
2911 CEFBS_None, // G_VECREDUCE_XOR = 303
2912 CEFBS_None, // G_VECREDUCE_SMAX = 304
2913 CEFBS_None, // G_VECREDUCE_SMIN = 305
2914 CEFBS_None, // G_VECREDUCE_UMAX = 306
2915 CEFBS_None, // G_VECREDUCE_UMIN = 307
2916 CEFBS_None, // G_SBFX = 308
2917 CEFBS_None, // G_UBFX = 309
2918 CEFBS_None, // BRANCH = 310
2919 CEFBS_None, // BRANCH_COND_f32 = 311
2920 CEFBS_None, // BRANCH_COND_i32 = 312
2921 CEFBS_None, // BREAK = 313
2922 CEFBS_None, // BREAKC_f32 = 314
2923 CEFBS_None, // BREAKC_i32 = 315
2924 CEFBS_None, // BREAK_LOGICALNZ_f32 = 316
2925 CEFBS_None, // BREAK_LOGICALNZ_i32 = 317
2926 CEFBS_None, // BREAK_LOGICALZ_f32 = 318
2927 CEFBS_None, // BREAK_LOGICALZ_i32 = 319
2928 CEFBS_None, // CONST_COPY = 320
2929 CEFBS_None, // CONTINUE = 321
2930 CEFBS_None, // CONTINUEC_f32 = 322
2931 CEFBS_None, // CONTINUEC_i32 = 323
2932 CEFBS_None, // CONTINUE_LOGICALNZ_f32 = 324
2933 CEFBS_None, // CONTINUE_LOGICALNZ_i32 = 325
2934 CEFBS_None, // CONTINUE_LOGICALZ_f32 = 326
2935 CEFBS_None, // CONTINUE_LOGICALZ_i32 = 327
2936 CEFBS_None, // CUBE_eg_pseudo = 328
2937 CEFBS_None, // CUBE_r600_pseudo = 329
2938 CEFBS_None, // DEFAULT = 330
2939 CEFBS_None, // DOT_4 = 331
2940 CEFBS_None, // DUMMY_CHAIN = 332
2941 CEFBS_None, // ELSE = 333
2942 CEFBS_None, // END = 334
2943 CEFBS_None, // ENDFUNC = 335
2944 CEFBS_None, // ENDIF = 336
2945 CEFBS_None, // ENDLOOP = 337
2946 CEFBS_None, // ENDMAIN = 338
2947 CEFBS_None, // ENDSWITCH = 339
2948 CEFBS_None, // FABS_R600 = 340
2949 CEFBS_None, // FNEG_R600 = 341
2950 CEFBS_None, // FUNC = 342
2951 CEFBS_None, // IFC_f32 = 343
2952 CEFBS_None, // IFC_i32 = 344
2953 CEFBS_None, // IF_LOGICALNZ_f32 = 345
2954 CEFBS_None, // IF_LOGICALNZ_i32 = 346
2955 CEFBS_None, // IF_LOGICALZ_f32 = 347
2956 CEFBS_None, // IF_LOGICALZ_i32 = 348
2957 CEFBS_None, // IF_PREDICATE_SET = 349
2958 CEFBS_None, // JUMP = 350
2959 CEFBS_None, // JUMP_COND = 351
2960 CEFBS_None, // MASK_WRITE = 352
2961 CEFBS_None, // MOV_IMM_F32 = 353
2962 CEFBS_None, // MOV_IMM_GLOBAL_ADDR = 354
2963 CEFBS_None, // MOV_IMM_I32 = 355
2964 CEFBS_None, // PRED_X = 356
2965 CEFBS_None, // R600_EXTRACT_ELT_V2 = 357
2966 CEFBS_None, // R600_EXTRACT_ELT_V4 = 358
2967 CEFBS_None, // R600_INSERT_ELT_V2 = 359
2968 CEFBS_None, // R600_INSERT_ELT_V4 = 360
2969 CEFBS_None, // R600_RegisterLoad = 361
2970 CEFBS_None, // R600_RegisterStore = 362
2971 CEFBS_None, // RETDYN = 363
2972 CEFBS_None, // RETURN = 364
2973 CEFBS_None, // TXD = 365
2974 CEFBS_None, // TXD_SHADOW = 366
2975 CEFBS_None, // WHILELOOP = 367
2976 CEFBS_None, // ADD = 368
2977 CEFBS_None, // ADDC_UINT = 369
2978 CEFBS_None, // ADD_INT = 370
2979 CEFBS_None, // ALU_CLAUSE = 371
2980 CEFBS_None, // AND_INT = 372
2981 CEFBS_None, // ASHR_eg = 373
2982 CEFBS_None, // ASHR_r600 = 374
2983 CEFBS_None, // BCNT_INT = 375
2984 CEFBS_None, // BFE_INT_eg = 376
2985 CEFBS_None, // BFE_UINT_eg = 377
2986 CEFBS_None, // BFI_INT_eg = 378
2987 CEFBS_None, // BFM_INT_eg = 379
2988 CEFBS_None, // BIT_ALIGN_INT_eg = 380
2989 CEFBS_None, // CEIL = 381
2990 CEFBS_None, // CF_ALU = 382
2991 CEFBS_None, // CF_ALU_BREAK = 383
2992 CEFBS_None, // CF_ALU_CONTINUE = 384
2993 CEFBS_None, // CF_ALU_ELSE_AFTER = 385
2994 CEFBS_None, // CF_ALU_POP_AFTER = 386
2995 CEFBS_None, // CF_ALU_PUSH_BEFORE = 387
2996 CEFBS_None, // CF_CALL_FS_EG = 388
2997 CEFBS_None, // CF_CALL_FS_R600 = 389
2998 CEFBS_None, // CF_CONTINUE_EG = 390
2999 CEFBS_None, // CF_CONTINUE_R600 = 391
3000 CEFBS_None, // CF_ELSE_EG = 392
3001 CEFBS_None, // CF_ELSE_R600 = 393
3002 CEFBS_None, // CF_END_CM = 394
3003 CEFBS_None, // CF_END_EG = 395
3004 CEFBS_None, // CF_END_R600 = 396
3005 CEFBS_None, // CF_JUMP_EG = 397
3006 CEFBS_None, // CF_JUMP_R600 = 398
3007 CEFBS_None, // CF_PUSH_EG = 399
3008 CEFBS_None, // CF_PUSH_ELSE_R600 = 400
3009 CEFBS_None, // CF_TC_EG = 401
3010 CEFBS_None, // CF_TC_R600 = 402
3011 CEFBS_None, // CF_VC_EG = 403
3012 CEFBS_None, // CF_VC_R600 = 404
3013 CEFBS_None, // CNDE_INT = 405
3014 CEFBS_None, // CNDE_eg = 406
3015 CEFBS_None, // CNDE_r600 = 407
3016 CEFBS_None, // CNDGE_INT = 408
3017 CEFBS_None, // CNDGE_eg = 409
3018 CEFBS_None, // CNDGE_r600 = 410
3019 CEFBS_None, // CNDGT_INT = 411
3020 CEFBS_None, // CNDGT_eg = 412
3021 CEFBS_None, // CNDGT_r600 = 413
3022 CEFBS_None, // COS_cm = 414
3023 CEFBS_None, // COS_eg = 415
3024 CEFBS_None, // COS_r600 = 416
3025 CEFBS_None, // COS_r700 = 417
3026 CEFBS_None, // CUBE_eg_real = 418
3027 CEFBS_None, // CUBE_r600_real = 419
3028 CEFBS_None, // DOT4_eg = 420
3029 CEFBS_None, // DOT4_r600 = 421
3030 CEFBS_None, // EG_ExportBuf = 422
3031 CEFBS_None, // EG_ExportSwz = 423
3032 CEFBS_None, // END_LOOP_EG = 424
3033 CEFBS_None, // END_LOOP_R600 = 425
3034 CEFBS_None, // EXP_IEEE_cm = 426
3035 CEFBS_None, // EXP_IEEE_eg = 427
3036 CEFBS_None, // EXP_IEEE_r600 = 428
3037 CEFBS_None, // FETCH_CLAUSE = 429
3038 CEFBS_None, // FFBH_UINT = 430
3039 CEFBS_None, // FFBL_INT = 431
3040 CEFBS_None, // FLOOR = 432
3041 CEFBS_None, // FLT16_TO_FLT32 = 433
3042 CEFBS_None, // FLT32_TO_FLT16 = 434
3043 CEFBS_None, // FLT_TO_INT_eg = 435
3044 CEFBS_None, // FLT_TO_INT_r600 = 436
3045 CEFBS_None, // FLT_TO_UINT_eg = 437
3046 CEFBS_None, // FLT_TO_UINT_r600 = 438
3047 CEFBS_None, // FMA_eg = 439
3048 CEFBS_None, // FRACT = 440
3049 CEFBS_None, // GROUP_BARRIER = 441
3050 CEFBS_None, // INTERP_LOAD_P0 = 442
3051 CEFBS_None, // INTERP_PAIR_XY = 443
3052 CEFBS_None, // INTERP_PAIR_ZW = 444
3053 CEFBS_None, // INTERP_VEC_LOAD = 445
3054 CEFBS_None, // INTERP_XY = 446
3055 CEFBS_None, // INTERP_ZW = 447
3056 CEFBS_None, // INT_TO_FLT_eg = 448
3057 CEFBS_None, // INT_TO_FLT_r600 = 449
3058 CEFBS_None, // KILLGT = 450
3059 CEFBS_None, // LDS_ADD = 451
3060 CEFBS_None, // LDS_ADD_RET = 452
3061 CEFBS_None, // LDS_AND = 453
3062 CEFBS_None, // LDS_AND_RET = 454
3063 CEFBS_None, // LDS_BYTE_READ_RET = 455
3064 CEFBS_None, // LDS_BYTE_WRITE = 456
3065 CEFBS_None, // LDS_CMPST = 457
3066 CEFBS_None, // LDS_CMPST_RET = 458
3067 CEFBS_None, // LDS_MAX_INT = 459
3068 CEFBS_None, // LDS_MAX_INT_RET = 460
3069 CEFBS_None, // LDS_MAX_UINT = 461
3070 CEFBS_None, // LDS_MAX_UINT_RET = 462
3071 CEFBS_None, // LDS_MIN_INT = 463
3072 CEFBS_None, // LDS_MIN_INT_RET = 464
3073 CEFBS_None, // LDS_MIN_UINT = 465
3074 CEFBS_None, // LDS_MIN_UINT_RET = 466
3075 CEFBS_None, // LDS_OR = 467
3076 CEFBS_None, // LDS_OR_RET = 468
3077 CEFBS_None, // LDS_READ_RET = 469
3078 CEFBS_None, // LDS_SHORT_READ_RET = 470
3079 CEFBS_None, // LDS_SHORT_WRITE = 471
3080 CEFBS_None, // LDS_SUB = 472
3081 CEFBS_None, // LDS_SUB_RET = 473
3082 CEFBS_None, // LDS_UBYTE_READ_RET = 474
3083 CEFBS_None, // LDS_USHORT_READ_RET = 475
3084 CEFBS_None, // LDS_WRITE = 476
3085 CEFBS_None, // LDS_WRXCHG = 477
3086 CEFBS_None, // LDS_WRXCHG_RET = 478
3087 CEFBS_None, // LDS_XOR = 479
3088 CEFBS_None, // LDS_XOR_RET = 480
3089 CEFBS_None, // LITERALS = 481
3090 CEFBS_None, // LOG_CLAMPED_eg = 482
3091 CEFBS_None, // LOG_CLAMPED_r600 = 483
3092 CEFBS_None, // LOG_IEEE_cm = 484
3093 CEFBS_None, // LOG_IEEE_eg = 485
3094 CEFBS_None, // LOG_IEEE_r600 = 486
3095 CEFBS_None, // LOOP_BREAK_EG = 487
3096 CEFBS_None, // LOOP_BREAK_R600 = 488
3097 CEFBS_None, // LSHL_eg = 489
3098 CEFBS_None, // LSHL_r600 = 490
3099 CEFBS_None, // LSHR_eg = 491
3100 CEFBS_None, // LSHR_r600 = 492
3101 CEFBS_None, // MAX = 493
3102 CEFBS_None, // MAX_DX10 = 494
3103 CEFBS_None, // MAX_INT = 495
3104 CEFBS_None, // MAX_UINT = 496
3105 CEFBS_None, // MIN = 497
3106 CEFBS_None, // MIN_DX10 = 498
3107 CEFBS_None, // MIN_INT = 499
3108 CEFBS_None, // MIN_UINT = 500
3109 CEFBS_None, // MOV = 501
3110 CEFBS_None, // MOVA_INT_eg = 502
3111 CEFBS_None, // MUL = 503
3112 CEFBS_None, // MULADD_IEEE_eg = 504
3113 CEFBS_None, // MULADD_IEEE_r600 = 505
3114 CEFBS_None, // MULADD_INT24_cm = 506
3115 CEFBS_None, // MULADD_UINT24_eg = 507
3116 CEFBS_None, // MULADD_eg = 508
3117 CEFBS_None, // MULADD_r600 = 509
3118 CEFBS_None, // MULHI_INT_cm = 510
3119 CEFBS_None, // MULHI_INT_cm24 = 511
3120 CEFBS_None, // MULHI_INT_eg = 512
3121 CEFBS_None, // MULHI_INT_r600 = 513
3122 CEFBS_None, // MULHI_UINT24_eg = 514
3123 CEFBS_None, // MULHI_UINT_cm = 515
3124 CEFBS_None, // MULHI_UINT_cm24 = 516
3125 CEFBS_None, // MULHI_UINT_eg = 517
3126 CEFBS_None, // MULHI_UINT_r600 = 518
3127 CEFBS_None, // MULLO_INT_cm = 519
3128 CEFBS_None, // MULLO_INT_eg = 520
3129 CEFBS_None, // MULLO_INT_r600 = 521
3130 CEFBS_None, // MULLO_UINT_cm = 522
3131 CEFBS_None, // MULLO_UINT_eg = 523
3132 CEFBS_None, // MULLO_UINT_r600 = 524
3133 CEFBS_None, // MUL_IEEE = 525
3134 CEFBS_None, // MUL_INT24_cm = 526
3135 CEFBS_None, // MUL_LIT_eg = 527
3136 CEFBS_None, // MUL_LIT_r600 = 528
3137 CEFBS_None, // MUL_UINT24_eg = 529
3138 CEFBS_None, // NOT_INT = 530
3139 CEFBS_None, // OR_INT = 531
3140 CEFBS_None, // PAD = 532
3141 CEFBS_None, // POP_EG = 533
3142 CEFBS_None, // POP_R600 = 534
3143 CEFBS_None, // PRED_SETE = 535
3144 CEFBS_None, // PRED_SETE_INT = 536
3145 CEFBS_None, // PRED_SETGE = 537
3146 CEFBS_None, // PRED_SETGE_INT = 538
3147 CEFBS_None, // PRED_SETGT = 539
3148 CEFBS_None, // PRED_SETGT_INT = 540
3149 CEFBS_None, // PRED_SETNE = 541
3150 CEFBS_None, // PRED_SETNE_INT = 542
3151 CEFBS_None, // R600_ExportBuf = 543
3152 CEFBS_None, // R600_ExportSwz = 544
3153 CEFBS_None, // RAT_ATOMIC_ADD_NORET = 545
3154 CEFBS_None, // RAT_ATOMIC_ADD_RTN = 546
3155 CEFBS_None, // RAT_ATOMIC_AND_NORET = 547
3156 CEFBS_None, // RAT_ATOMIC_AND_RTN = 548
3157 CEFBS_None, // RAT_ATOMIC_CMPXCHG_INT_NORET = 549
3158 CEFBS_None, // RAT_ATOMIC_CMPXCHG_INT_RTN = 550
3159 CEFBS_None, // RAT_ATOMIC_DEC_UINT_NORET = 551
3160 CEFBS_None, // RAT_ATOMIC_DEC_UINT_RTN = 552
3161 CEFBS_None, // RAT_ATOMIC_INC_UINT_NORET = 553
3162 CEFBS_None, // RAT_ATOMIC_INC_UINT_RTN = 554
3163 CEFBS_None, // RAT_ATOMIC_MAX_INT_NORET = 555
3164 CEFBS_None, // RAT_ATOMIC_MAX_INT_RTN = 556
3165 CEFBS_None, // RAT_ATOMIC_MAX_UINT_NORET = 557
3166 CEFBS_None, // RAT_ATOMIC_MAX_UINT_RTN = 558
3167 CEFBS_None, // RAT_ATOMIC_MIN_INT_NORET = 559
3168 CEFBS_None, // RAT_ATOMIC_MIN_INT_RTN = 560
3169 CEFBS_None, // RAT_ATOMIC_MIN_UINT_NORET = 561
3170 CEFBS_None, // RAT_ATOMIC_MIN_UINT_RTN = 562
3171 CEFBS_None, // RAT_ATOMIC_OR_NORET = 563
3172 CEFBS_None, // RAT_ATOMIC_OR_RTN = 564
3173 CEFBS_None, // RAT_ATOMIC_RSUB_NORET = 565
3174 CEFBS_None, // RAT_ATOMIC_RSUB_RTN = 566
3175 CEFBS_None, // RAT_ATOMIC_SUB_NORET = 567
3176 CEFBS_None, // RAT_ATOMIC_SUB_RTN = 568
3177 CEFBS_None, // RAT_ATOMIC_XCHG_INT_NORET = 569
3178 CEFBS_None, // RAT_ATOMIC_XCHG_INT_RTN = 570
3179 CEFBS_None, // RAT_ATOMIC_XOR_NORET = 571
3180 CEFBS_None, // RAT_ATOMIC_XOR_RTN = 572
3181 CEFBS_None, // RAT_MSKOR = 573
3182 CEFBS_None, // RAT_STORE_DWORD128 = 574
3183 CEFBS_None, // RAT_STORE_DWORD32 = 575
3184 CEFBS_None, // RAT_STORE_DWORD64 = 576
3185 CEFBS_None, // RAT_STORE_TYPED_cm = 577
3186 CEFBS_None, // RAT_STORE_TYPED_eg = 578
3187 CEFBS_None, // RAT_WRITE_CACHELESS_128_eg = 579
3188 CEFBS_None, // RAT_WRITE_CACHELESS_32_eg = 580
3189 CEFBS_None, // RAT_WRITE_CACHELESS_64_eg = 581
3190 CEFBS_None, // RECIPSQRT_CLAMPED_cm = 582
3191 CEFBS_None, // RECIPSQRT_CLAMPED_eg = 583
3192 CEFBS_None, // RECIPSQRT_CLAMPED_r600 = 584
3193 CEFBS_None, // RECIPSQRT_IEEE_cm = 585
3194 CEFBS_None, // RECIPSQRT_IEEE_eg = 586
3195 CEFBS_None, // RECIPSQRT_IEEE_r600 = 587
3196 CEFBS_None, // RECIP_CLAMPED_cm = 588
3197 CEFBS_None, // RECIP_CLAMPED_eg = 589
3198 CEFBS_None, // RECIP_CLAMPED_r600 = 590
3199 CEFBS_None, // RECIP_IEEE_cm = 591
3200 CEFBS_None, // RECIP_IEEE_eg = 592
3201 CEFBS_None, // RECIP_IEEE_r600 = 593
3202 CEFBS_None, // RECIP_UINT_eg = 594
3203 CEFBS_None, // RECIP_UINT_r600 = 595
3204 CEFBS_None, // RNDNE = 596
3205 CEFBS_None, // SETE = 597
3206 CEFBS_None, // SETE_DX10 = 598
3207 CEFBS_None, // SETE_INT = 599
3208 CEFBS_None, // SETGE_DX10 = 600
3209 CEFBS_None, // SETGE_INT = 601
3210 CEFBS_None, // SETGE_UINT = 602
3211 CEFBS_None, // SETGT_DX10 = 603
3212 CEFBS_None, // SETGT_INT = 604
3213 CEFBS_None, // SETGT_UINT = 605
3214 CEFBS_None, // SETNE_DX10 = 606
3215 CEFBS_None, // SETNE_INT = 607
3216 CEFBS_None, // SGE = 608
3217 CEFBS_None, // SGT = 609
3218 CEFBS_None, // SIN_cm = 610
3219 CEFBS_None, // SIN_eg = 611
3220 CEFBS_None, // SIN_r600 = 612
3221 CEFBS_None, // SIN_r700 = 613
3222 CEFBS_None, // SNE = 614
3223 CEFBS_None, // SUBB_UINT = 615
3224 CEFBS_None, // SUB_INT = 616
3225 CEFBS_None, // TEX_GET_GRADIENTS_H = 617
3226 CEFBS_None, // TEX_GET_GRADIENTS_V = 618
3227 CEFBS_None, // TEX_GET_TEXTURE_RESINFO = 619
3228 CEFBS_None, // TEX_LD = 620
3229 CEFBS_None, // TEX_LDPTR = 621
3230 CEFBS_None, // TEX_SAMPLE = 622
3231 CEFBS_None, // TEX_SAMPLE_C = 623
3232 CEFBS_None, // TEX_SAMPLE_C_G = 624
3233 CEFBS_None, // TEX_SAMPLE_C_L = 625
3234 CEFBS_None, // TEX_SAMPLE_C_LB = 626
3235 CEFBS_None, // TEX_SAMPLE_G = 627
3236 CEFBS_None, // TEX_SAMPLE_L = 628
3237 CEFBS_None, // TEX_SAMPLE_LB = 629
3238 CEFBS_None, // TEX_SET_GRADIENTS_H = 630
3239 CEFBS_None, // TEX_SET_GRADIENTS_V = 631
3240 CEFBS_None, // TEX_VTX_CONSTBUF = 632
3241 CEFBS_None, // TEX_VTX_TEXBUF = 633
3242 CEFBS_None, // TRUNC = 634
3243 CEFBS_None, // UINT_TO_FLT_eg = 635
3244 CEFBS_None, // UINT_TO_FLT_r600 = 636
3245 CEFBS_None, // VTX_READ_128_cm = 637
3246 CEFBS_None, // VTX_READ_128_eg = 638
3247 CEFBS_None, // VTX_READ_16_cm = 639
3248 CEFBS_None, // VTX_READ_16_eg = 640
3249 CEFBS_None, // VTX_READ_32_cm = 641
3250 CEFBS_None, // VTX_READ_32_eg = 642
3251 CEFBS_None, // VTX_READ_64_cm = 643
3252 CEFBS_None, // VTX_READ_64_eg = 644
3253 CEFBS_None, // VTX_READ_8_cm = 645
3254 CEFBS_None, // VTX_READ_8_eg = 646
3255 CEFBS_None, // WHILE_LOOP_EG = 647
3256 CEFBS_None, // WHILE_LOOP_R600 = 648
3257 CEFBS_None, // XOR_INT = 649
3258 };
3259
3260 assert(Opcode < 650);
3261 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
3262}
3263
3264} // end namespace llvm::R600_MC
3265#endif // GET_COMPUTE_FEATURES
3266
3267#ifdef GET_AVAILABLE_OPCODE_CHECKER
3268#undef GET_AVAILABLE_OPCODE_CHECKER
3269namespace llvm::R600_MC {
3270bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
3271 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
3272 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
3273 FeatureBitset MissingFeatures =
3274 (AvailableFeatures & RequiredFeatures) ^
3275 RequiredFeatures;
3276 return !MissingFeatures.any();
3277}
3278} // end namespace llvm::R600_MC
3279#endif // GET_AVAILABLE_OPCODE_CHECKER
3280
3281#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
3282#undef ENABLE_INSTR_PREDICATE_VERIFIER
3283#include <sstream>
3284
3285namespace llvm::R600_MC {
3286#ifndef NDEBUG
3287static const char *SubtargetFeatureNames[] = {
3288 nullptr
3289};
3290
3291#endif // NDEBUG
3292
3293void verifyInstructionPredicates(
3294 unsigned Opcode, const FeatureBitset &Features) {
3295#ifndef NDEBUG
3296 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
3297 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
3298 FeatureBitset MissingFeatures =
3299 (AvailableFeatures & RequiredFeatures) ^
3300 RequiredFeatures;
3301 if (MissingFeatures.any()) {
3302 std::ostringstream Msg;
3303 Msg << "Attempting to emit " << &R600InstrNameData[R600InstrNameIndices[Opcode]]
3304 << " instruction but the ";
3305 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
3306 if (MissingFeatures.test(i))
3307 Msg << SubtargetFeatureNames[i] << " ";
3308 Msg << "predicate(s) are not met";
3309 report_fatal_error(Msg.str().c_str());
3310 }
3311#endif // NDEBUG
3312}
3313} // end namespace llvm::R600_MC
3314#endif // ENABLE_INSTR_PREDICATE_VERIFIER
3315
3316#ifdef GET_INSTRMAP_INFO
3317#undef GET_INSTRMAP_INFO
3318namespace llvm::R600 {
3319
3320enum DisableEncoding {
3321 DisableEncoding_
3322};
3323
3324// getLDSNoRetOp
3325LLVM_READONLY
3326int getLDSNoRetOp(uint16_t Opcode) {
3327 using namespace R600;
3328 static constexpr uint16_t Table[][2] = {
3329 { LDS_ADD_RET, LDS_ADD },
3330 { LDS_AND_RET, LDS_AND },
3331 { LDS_MAX_INT_RET, LDS_MAX_INT },
3332 { LDS_MAX_UINT_RET, LDS_MAX_UINT },
3333 { LDS_MIN_INT_RET, LDS_MIN_INT },
3334 { LDS_MIN_UINT_RET, LDS_MIN_UINT },
3335 { LDS_OR_RET, LDS_OR },
3336 { LDS_SUB_RET, LDS_SUB },
3337 { LDS_WRXCHG_RET, LDS_WRXCHG },
3338 { LDS_XOR_RET, LDS_XOR },
3339 }; // End of Table
3340
3341 unsigned mid;
3342 unsigned start = 0;
3343 unsigned end = 10;
3344 while (start < end) {
3345 mid = start + (end - start) / 2;
3346 if (Opcode == Table[mid][0])
3347 break;
3348 if (Opcode < Table[mid][0])
3349 end = mid;
3350 else
3351 start = mid + 1;
3352 }
3353 if (start == end)
3354 return -1; // Instruction doesn't exist in this table.
3355
3356 return Table[mid][1];
3357}
3358
3359} // end namespace llvm::R600
3360#endif // GET_INSTRMAP_INFO
3361
3362