1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register Enum Values *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_REGINFO_ENUM
11#undef GET_REGINFO_ENUM
12
13namespace llvm {
14
15class MCRegisterClass;
16extern const MCRegisterClass R600MCRegisterClasses[];
17
18namespace R600 {
19enum : unsigned {
20 NoRegister,
21 ALU_CONST = 1,
22 ALU_LITERAL_W = 2,
23 ALU_LITERAL_X = 3,
24 ALU_LITERAL_Y = 4,
25 ALU_LITERAL_Z = 5,
26 ALU_PARAM = 6,
27 AR_X = 7,
28 HALF = 8,
29 INDIRECT_BASE_ADDR = 9,
30 LDS_DIRECT_A = 10,
31 LDS_DIRECT_B = 11,
32 NEG_HALF = 12,
33 NEG_ONE = 13,
34 ONE = 14,
35 ONE_INT = 15,
36 OQA = 16,
37 OQAP = 17,
38 OQB = 18,
39 OQBP = 19,
40 PREDICATE_BIT = 20,
41 PRED_SEL_OFF = 21,
42 PRED_SEL_ONE = 22,
43 PRED_SEL_ZERO = 23,
44 PS = 24,
45 PV_W = 25,
46 PV_X = 26,
47 PV_Y = 27,
48 PV_Z = 28,
49 ZERO = 29,
50 ArrayBase448 = 30,
51 ArrayBase449 = 31,
52 ArrayBase450 = 32,
53 ArrayBase451 = 33,
54 ArrayBase452 = 34,
55 ArrayBase453 = 35,
56 ArrayBase454 = 36,
57 ArrayBase455 = 37,
58 ArrayBase456 = 38,
59 ArrayBase457 = 39,
60 ArrayBase458 = 40,
61 ArrayBase459 = 41,
62 ArrayBase460 = 42,
63 ArrayBase461 = 43,
64 ArrayBase462 = 44,
65 ArrayBase463 = 45,
66 ArrayBase464 = 46,
67 ArrayBase465 = 47,
68 ArrayBase466 = 48,
69 ArrayBase467 = 49,
70 ArrayBase468 = 50,
71 ArrayBase469 = 51,
72 ArrayBase470 = 52,
73 ArrayBase471 = 53,
74 ArrayBase472 = 54,
75 ArrayBase473 = 55,
76 ArrayBase474 = 56,
77 ArrayBase475 = 57,
78 ArrayBase476 = 58,
79 ArrayBase477 = 59,
80 ArrayBase478 = 60,
81 ArrayBase479 = 61,
82 ArrayBase480 = 62,
83 Addr0_W = 63,
84 Addr1_W = 64,
85 Addr2_W = 65,
86 Addr3_W = 66,
87 Addr4_W = 67,
88 Addr5_W = 68,
89 Addr6_W = 69,
90 Addr7_W = 70,
91 Addr8_W = 71,
92 Addr9_W = 72,
93 Addr10_W = 73,
94 Addr11_W = 74,
95 Addr12_W = 75,
96 Addr13_W = 76,
97 Addr14_W = 77,
98 Addr15_W = 78,
99 Addr16_W = 79,
100 Addr17_W = 80,
101 Addr18_W = 81,
102 Addr19_W = 82,
103 Addr20_W = 83,
104 Addr21_W = 84,
105 Addr22_W = 85,
106 Addr23_W = 86,
107 Addr24_W = 87,
108 Addr25_W = 88,
109 Addr26_W = 89,
110 Addr27_W = 90,
111 Addr28_W = 91,
112 Addr29_W = 92,
113 Addr30_W = 93,
114 Addr31_W = 94,
115 Addr32_W = 95,
116 Addr33_W = 96,
117 Addr34_W = 97,
118 Addr35_W = 98,
119 Addr36_W = 99,
120 Addr37_W = 100,
121 Addr38_W = 101,
122 Addr39_W = 102,
123 Addr40_W = 103,
124 Addr41_W = 104,
125 Addr42_W = 105,
126 Addr43_W = 106,
127 Addr44_W = 107,
128 Addr45_W = 108,
129 Addr46_W = 109,
130 Addr47_W = 110,
131 Addr48_W = 111,
132 Addr49_W = 112,
133 Addr50_W = 113,
134 Addr51_W = 114,
135 Addr52_W = 115,
136 Addr53_W = 116,
137 Addr54_W = 117,
138 Addr55_W = 118,
139 Addr56_W = 119,
140 Addr57_W = 120,
141 Addr58_W = 121,
142 Addr59_W = 122,
143 Addr60_W = 123,
144 Addr61_W = 124,
145 Addr62_W = 125,
146 Addr63_W = 126,
147 Addr64_W = 127,
148 Addr65_W = 128,
149 Addr66_W = 129,
150 Addr67_W = 130,
151 Addr68_W = 131,
152 Addr69_W = 132,
153 Addr70_W = 133,
154 Addr71_W = 134,
155 Addr72_W = 135,
156 Addr73_W = 136,
157 Addr74_W = 137,
158 Addr75_W = 138,
159 Addr76_W = 139,
160 Addr77_W = 140,
161 Addr78_W = 141,
162 Addr79_W = 142,
163 Addr80_W = 143,
164 Addr81_W = 144,
165 Addr82_W = 145,
166 Addr83_W = 146,
167 Addr84_W = 147,
168 Addr85_W = 148,
169 Addr86_W = 149,
170 Addr87_W = 150,
171 Addr88_W = 151,
172 Addr89_W = 152,
173 Addr90_W = 153,
174 Addr91_W = 154,
175 Addr92_W = 155,
176 Addr93_W = 156,
177 Addr94_W = 157,
178 Addr95_W = 158,
179 Addr96_W = 159,
180 Addr97_W = 160,
181 Addr98_W = 161,
182 Addr99_W = 162,
183 Addr100_W = 163,
184 Addr101_W = 164,
185 Addr102_W = 165,
186 Addr103_W = 166,
187 Addr104_W = 167,
188 Addr105_W = 168,
189 Addr106_W = 169,
190 Addr107_W = 170,
191 Addr108_W = 171,
192 Addr109_W = 172,
193 Addr110_W = 173,
194 Addr111_W = 174,
195 Addr112_W = 175,
196 Addr113_W = 176,
197 Addr114_W = 177,
198 Addr115_W = 178,
199 Addr116_W = 179,
200 Addr117_W = 180,
201 Addr118_W = 181,
202 Addr119_W = 182,
203 Addr120_W = 183,
204 Addr121_W = 184,
205 Addr122_W = 185,
206 Addr123_W = 186,
207 Addr124_W = 187,
208 Addr125_W = 188,
209 Addr126_W = 189,
210 Addr127_W = 190,
211 Addr0_X = 191,
212 Addr1_X = 192,
213 Addr2_X = 193,
214 Addr3_X = 194,
215 Addr4_X = 195,
216 Addr5_X = 196,
217 Addr6_X = 197,
218 Addr7_X = 198,
219 Addr8_X = 199,
220 Addr9_X = 200,
221 Addr10_X = 201,
222 Addr11_X = 202,
223 Addr12_X = 203,
224 Addr13_X = 204,
225 Addr14_X = 205,
226 Addr15_X = 206,
227 Addr16_X = 207,
228 Addr17_X = 208,
229 Addr18_X = 209,
230 Addr19_X = 210,
231 Addr20_X = 211,
232 Addr21_X = 212,
233 Addr22_X = 213,
234 Addr23_X = 214,
235 Addr24_X = 215,
236 Addr25_X = 216,
237 Addr26_X = 217,
238 Addr27_X = 218,
239 Addr28_X = 219,
240 Addr29_X = 220,
241 Addr30_X = 221,
242 Addr31_X = 222,
243 Addr32_X = 223,
244 Addr33_X = 224,
245 Addr34_X = 225,
246 Addr35_X = 226,
247 Addr36_X = 227,
248 Addr37_X = 228,
249 Addr38_X = 229,
250 Addr39_X = 230,
251 Addr40_X = 231,
252 Addr41_X = 232,
253 Addr42_X = 233,
254 Addr43_X = 234,
255 Addr44_X = 235,
256 Addr45_X = 236,
257 Addr46_X = 237,
258 Addr47_X = 238,
259 Addr48_X = 239,
260 Addr49_X = 240,
261 Addr50_X = 241,
262 Addr51_X = 242,
263 Addr52_X = 243,
264 Addr53_X = 244,
265 Addr54_X = 245,
266 Addr55_X = 246,
267 Addr56_X = 247,
268 Addr57_X = 248,
269 Addr58_X = 249,
270 Addr59_X = 250,
271 Addr60_X = 251,
272 Addr61_X = 252,
273 Addr62_X = 253,
274 Addr63_X = 254,
275 Addr64_X = 255,
276 Addr65_X = 256,
277 Addr66_X = 257,
278 Addr67_X = 258,
279 Addr68_X = 259,
280 Addr69_X = 260,
281 Addr70_X = 261,
282 Addr71_X = 262,
283 Addr72_X = 263,
284 Addr73_X = 264,
285 Addr74_X = 265,
286 Addr75_X = 266,
287 Addr76_X = 267,
288 Addr77_X = 268,
289 Addr78_X = 269,
290 Addr79_X = 270,
291 Addr80_X = 271,
292 Addr81_X = 272,
293 Addr82_X = 273,
294 Addr83_X = 274,
295 Addr84_X = 275,
296 Addr85_X = 276,
297 Addr86_X = 277,
298 Addr87_X = 278,
299 Addr88_X = 279,
300 Addr89_X = 280,
301 Addr90_X = 281,
302 Addr91_X = 282,
303 Addr92_X = 283,
304 Addr93_X = 284,
305 Addr94_X = 285,
306 Addr95_X = 286,
307 Addr96_X = 287,
308 Addr97_X = 288,
309 Addr98_X = 289,
310 Addr99_X = 290,
311 Addr100_X = 291,
312 Addr101_X = 292,
313 Addr102_X = 293,
314 Addr103_X = 294,
315 Addr104_X = 295,
316 Addr105_X = 296,
317 Addr106_X = 297,
318 Addr107_X = 298,
319 Addr108_X = 299,
320 Addr109_X = 300,
321 Addr110_X = 301,
322 Addr111_X = 302,
323 Addr112_X = 303,
324 Addr113_X = 304,
325 Addr114_X = 305,
326 Addr115_X = 306,
327 Addr116_X = 307,
328 Addr117_X = 308,
329 Addr118_X = 309,
330 Addr119_X = 310,
331 Addr120_X = 311,
332 Addr121_X = 312,
333 Addr122_X = 313,
334 Addr123_X = 314,
335 Addr124_X = 315,
336 Addr125_X = 316,
337 Addr126_X = 317,
338 Addr127_X = 318,
339 Addr0_Y = 319,
340 Addr1_Y = 320,
341 Addr2_Y = 321,
342 Addr3_Y = 322,
343 Addr4_Y = 323,
344 Addr5_Y = 324,
345 Addr6_Y = 325,
346 Addr7_Y = 326,
347 Addr8_Y = 327,
348 Addr9_Y = 328,
349 Addr10_Y = 329,
350 Addr11_Y = 330,
351 Addr12_Y = 331,
352 Addr13_Y = 332,
353 Addr14_Y = 333,
354 Addr15_Y = 334,
355 Addr16_Y = 335,
356 Addr17_Y = 336,
357 Addr18_Y = 337,
358 Addr19_Y = 338,
359 Addr20_Y = 339,
360 Addr21_Y = 340,
361 Addr22_Y = 341,
362 Addr23_Y = 342,
363 Addr24_Y = 343,
364 Addr25_Y = 344,
365 Addr26_Y = 345,
366 Addr27_Y = 346,
367 Addr28_Y = 347,
368 Addr29_Y = 348,
369 Addr30_Y = 349,
370 Addr31_Y = 350,
371 Addr32_Y = 351,
372 Addr33_Y = 352,
373 Addr34_Y = 353,
374 Addr35_Y = 354,
375 Addr36_Y = 355,
376 Addr37_Y = 356,
377 Addr38_Y = 357,
378 Addr39_Y = 358,
379 Addr40_Y = 359,
380 Addr41_Y = 360,
381 Addr42_Y = 361,
382 Addr43_Y = 362,
383 Addr44_Y = 363,
384 Addr45_Y = 364,
385 Addr46_Y = 365,
386 Addr47_Y = 366,
387 Addr48_Y = 367,
388 Addr49_Y = 368,
389 Addr50_Y = 369,
390 Addr51_Y = 370,
391 Addr52_Y = 371,
392 Addr53_Y = 372,
393 Addr54_Y = 373,
394 Addr55_Y = 374,
395 Addr56_Y = 375,
396 Addr57_Y = 376,
397 Addr58_Y = 377,
398 Addr59_Y = 378,
399 Addr60_Y = 379,
400 Addr61_Y = 380,
401 Addr62_Y = 381,
402 Addr63_Y = 382,
403 Addr64_Y = 383,
404 Addr65_Y = 384,
405 Addr66_Y = 385,
406 Addr67_Y = 386,
407 Addr68_Y = 387,
408 Addr69_Y = 388,
409 Addr70_Y = 389,
410 Addr71_Y = 390,
411 Addr72_Y = 391,
412 Addr73_Y = 392,
413 Addr74_Y = 393,
414 Addr75_Y = 394,
415 Addr76_Y = 395,
416 Addr77_Y = 396,
417 Addr78_Y = 397,
418 Addr79_Y = 398,
419 Addr80_Y = 399,
420 Addr81_Y = 400,
421 Addr82_Y = 401,
422 Addr83_Y = 402,
423 Addr84_Y = 403,
424 Addr85_Y = 404,
425 Addr86_Y = 405,
426 Addr87_Y = 406,
427 Addr88_Y = 407,
428 Addr89_Y = 408,
429 Addr90_Y = 409,
430 Addr91_Y = 410,
431 Addr92_Y = 411,
432 Addr93_Y = 412,
433 Addr94_Y = 413,
434 Addr95_Y = 414,
435 Addr96_Y = 415,
436 Addr97_Y = 416,
437 Addr98_Y = 417,
438 Addr99_Y = 418,
439 Addr100_Y = 419,
440 Addr101_Y = 420,
441 Addr102_Y = 421,
442 Addr103_Y = 422,
443 Addr104_Y = 423,
444 Addr105_Y = 424,
445 Addr106_Y = 425,
446 Addr107_Y = 426,
447 Addr108_Y = 427,
448 Addr109_Y = 428,
449 Addr110_Y = 429,
450 Addr111_Y = 430,
451 Addr112_Y = 431,
452 Addr113_Y = 432,
453 Addr114_Y = 433,
454 Addr115_Y = 434,
455 Addr116_Y = 435,
456 Addr117_Y = 436,
457 Addr118_Y = 437,
458 Addr119_Y = 438,
459 Addr120_Y = 439,
460 Addr121_Y = 440,
461 Addr122_Y = 441,
462 Addr123_Y = 442,
463 Addr124_Y = 443,
464 Addr125_Y = 444,
465 Addr126_Y = 445,
466 Addr127_Y = 446,
467 Addr0_Z = 447,
468 Addr1_Z = 448,
469 Addr2_Z = 449,
470 Addr3_Z = 450,
471 Addr4_Z = 451,
472 Addr5_Z = 452,
473 Addr6_Z = 453,
474 Addr7_Z = 454,
475 Addr8_Z = 455,
476 Addr9_Z = 456,
477 Addr10_Z = 457,
478 Addr11_Z = 458,
479 Addr12_Z = 459,
480 Addr13_Z = 460,
481 Addr14_Z = 461,
482 Addr15_Z = 462,
483 Addr16_Z = 463,
484 Addr17_Z = 464,
485 Addr18_Z = 465,
486 Addr19_Z = 466,
487 Addr20_Z = 467,
488 Addr21_Z = 468,
489 Addr22_Z = 469,
490 Addr23_Z = 470,
491 Addr24_Z = 471,
492 Addr25_Z = 472,
493 Addr26_Z = 473,
494 Addr27_Z = 474,
495 Addr28_Z = 475,
496 Addr29_Z = 476,
497 Addr30_Z = 477,
498 Addr31_Z = 478,
499 Addr32_Z = 479,
500 Addr33_Z = 480,
501 Addr34_Z = 481,
502 Addr35_Z = 482,
503 Addr36_Z = 483,
504 Addr37_Z = 484,
505 Addr38_Z = 485,
506 Addr39_Z = 486,
507 Addr40_Z = 487,
508 Addr41_Z = 488,
509 Addr42_Z = 489,
510 Addr43_Z = 490,
511 Addr44_Z = 491,
512 Addr45_Z = 492,
513 Addr46_Z = 493,
514 Addr47_Z = 494,
515 Addr48_Z = 495,
516 Addr49_Z = 496,
517 Addr50_Z = 497,
518 Addr51_Z = 498,
519 Addr52_Z = 499,
520 Addr53_Z = 500,
521 Addr54_Z = 501,
522 Addr55_Z = 502,
523 Addr56_Z = 503,
524 Addr57_Z = 504,
525 Addr58_Z = 505,
526 Addr59_Z = 506,
527 Addr60_Z = 507,
528 Addr61_Z = 508,
529 Addr62_Z = 509,
530 Addr63_Z = 510,
531 Addr64_Z = 511,
532 Addr65_Z = 512,
533 Addr66_Z = 513,
534 Addr67_Z = 514,
535 Addr68_Z = 515,
536 Addr69_Z = 516,
537 Addr70_Z = 517,
538 Addr71_Z = 518,
539 Addr72_Z = 519,
540 Addr73_Z = 520,
541 Addr74_Z = 521,
542 Addr75_Z = 522,
543 Addr76_Z = 523,
544 Addr77_Z = 524,
545 Addr78_Z = 525,
546 Addr79_Z = 526,
547 Addr80_Z = 527,
548 Addr81_Z = 528,
549 Addr82_Z = 529,
550 Addr83_Z = 530,
551 Addr84_Z = 531,
552 Addr85_Z = 532,
553 Addr86_Z = 533,
554 Addr87_Z = 534,
555 Addr88_Z = 535,
556 Addr89_Z = 536,
557 Addr90_Z = 537,
558 Addr91_Z = 538,
559 Addr92_Z = 539,
560 Addr93_Z = 540,
561 Addr94_Z = 541,
562 Addr95_Z = 542,
563 Addr96_Z = 543,
564 Addr97_Z = 544,
565 Addr98_Z = 545,
566 Addr99_Z = 546,
567 Addr100_Z = 547,
568 Addr101_Z = 548,
569 Addr102_Z = 549,
570 Addr103_Z = 550,
571 Addr104_Z = 551,
572 Addr105_Z = 552,
573 Addr106_Z = 553,
574 Addr107_Z = 554,
575 Addr108_Z = 555,
576 Addr109_Z = 556,
577 Addr110_Z = 557,
578 Addr111_Z = 558,
579 Addr112_Z = 559,
580 Addr113_Z = 560,
581 Addr114_Z = 561,
582 Addr115_Z = 562,
583 Addr116_Z = 563,
584 Addr117_Z = 564,
585 Addr118_Z = 565,
586 Addr119_Z = 566,
587 Addr120_Z = 567,
588 Addr121_Z = 568,
589 Addr122_Z = 569,
590 Addr123_Z = 570,
591 Addr124_Z = 571,
592 Addr125_Z = 572,
593 Addr126_Z = 573,
594 Addr127_Z = 574,
595 T0_W = 575,
596 T1_W = 576,
597 T2_W = 577,
598 T3_W = 578,
599 T4_W = 579,
600 T5_W = 580,
601 T6_W = 581,
602 T7_W = 582,
603 T8_W = 583,
604 T9_W = 584,
605 T10_W = 585,
606 T11_W = 586,
607 T12_W = 587,
608 T13_W = 588,
609 T14_W = 589,
610 T15_W = 590,
611 T16_W = 591,
612 T17_W = 592,
613 T18_W = 593,
614 T19_W = 594,
615 T20_W = 595,
616 T21_W = 596,
617 T22_W = 597,
618 T23_W = 598,
619 T24_W = 599,
620 T25_W = 600,
621 T26_W = 601,
622 T27_W = 602,
623 T28_W = 603,
624 T29_W = 604,
625 T30_W = 605,
626 T31_W = 606,
627 T32_W = 607,
628 T33_W = 608,
629 T34_W = 609,
630 T35_W = 610,
631 T36_W = 611,
632 T37_W = 612,
633 T38_W = 613,
634 T39_W = 614,
635 T40_W = 615,
636 T41_W = 616,
637 T42_W = 617,
638 T43_W = 618,
639 T44_W = 619,
640 T45_W = 620,
641 T46_W = 621,
642 T47_W = 622,
643 T48_W = 623,
644 T49_W = 624,
645 T50_W = 625,
646 T51_W = 626,
647 T52_W = 627,
648 T53_W = 628,
649 T54_W = 629,
650 T55_W = 630,
651 T56_W = 631,
652 T57_W = 632,
653 T58_W = 633,
654 T59_W = 634,
655 T60_W = 635,
656 T61_W = 636,
657 T62_W = 637,
658 T63_W = 638,
659 T64_W = 639,
660 T65_W = 640,
661 T66_W = 641,
662 T67_W = 642,
663 T68_W = 643,
664 T69_W = 644,
665 T70_W = 645,
666 T71_W = 646,
667 T72_W = 647,
668 T73_W = 648,
669 T74_W = 649,
670 T75_W = 650,
671 T76_W = 651,
672 T77_W = 652,
673 T78_W = 653,
674 T79_W = 654,
675 T80_W = 655,
676 T81_W = 656,
677 T82_W = 657,
678 T83_W = 658,
679 T84_W = 659,
680 T85_W = 660,
681 T86_W = 661,
682 T87_W = 662,
683 T88_W = 663,
684 T89_W = 664,
685 T90_W = 665,
686 T91_W = 666,
687 T92_W = 667,
688 T93_W = 668,
689 T94_W = 669,
690 T95_W = 670,
691 T96_W = 671,
692 T97_W = 672,
693 T98_W = 673,
694 T99_W = 674,
695 T100_W = 675,
696 T101_W = 676,
697 T102_W = 677,
698 T103_W = 678,
699 T104_W = 679,
700 T105_W = 680,
701 T106_W = 681,
702 T107_W = 682,
703 T108_W = 683,
704 T109_W = 684,
705 T110_W = 685,
706 T111_W = 686,
707 T112_W = 687,
708 T113_W = 688,
709 T114_W = 689,
710 T115_W = 690,
711 T116_W = 691,
712 T117_W = 692,
713 T118_W = 693,
714 T119_W = 694,
715 T120_W = 695,
716 T121_W = 696,
717 T122_W = 697,
718 T123_W = 698,
719 T124_W = 699,
720 T125_W = 700,
721 T126_W = 701,
722 T127_W = 702,
723 T0_X = 703,
724 T1_X = 704,
725 T2_X = 705,
726 T3_X = 706,
727 T4_X = 707,
728 T5_X = 708,
729 T6_X = 709,
730 T7_X = 710,
731 T8_X = 711,
732 T9_X = 712,
733 T10_X = 713,
734 T11_X = 714,
735 T12_X = 715,
736 T13_X = 716,
737 T14_X = 717,
738 T15_X = 718,
739 T16_X = 719,
740 T17_X = 720,
741 T18_X = 721,
742 T19_X = 722,
743 T20_X = 723,
744 T21_X = 724,
745 T22_X = 725,
746 T23_X = 726,
747 T24_X = 727,
748 T25_X = 728,
749 T26_X = 729,
750 T27_X = 730,
751 T28_X = 731,
752 T29_X = 732,
753 T30_X = 733,
754 T31_X = 734,
755 T32_X = 735,
756 T33_X = 736,
757 T34_X = 737,
758 T35_X = 738,
759 T36_X = 739,
760 T37_X = 740,
761 T38_X = 741,
762 T39_X = 742,
763 T40_X = 743,
764 T41_X = 744,
765 T42_X = 745,
766 T43_X = 746,
767 T44_X = 747,
768 T45_X = 748,
769 T46_X = 749,
770 T47_X = 750,
771 T48_X = 751,
772 T49_X = 752,
773 T50_X = 753,
774 T51_X = 754,
775 T52_X = 755,
776 T53_X = 756,
777 T54_X = 757,
778 T55_X = 758,
779 T56_X = 759,
780 T57_X = 760,
781 T58_X = 761,
782 T59_X = 762,
783 T60_X = 763,
784 T61_X = 764,
785 T62_X = 765,
786 T63_X = 766,
787 T64_X = 767,
788 T65_X = 768,
789 T66_X = 769,
790 T67_X = 770,
791 T68_X = 771,
792 T69_X = 772,
793 T70_X = 773,
794 T71_X = 774,
795 T72_X = 775,
796 T73_X = 776,
797 T74_X = 777,
798 T75_X = 778,
799 T76_X = 779,
800 T77_X = 780,
801 T78_X = 781,
802 T79_X = 782,
803 T80_X = 783,
804 T81_X = 784,
805 T82_X = 785,
806 T83_X = 786,
807 T84_X = 787,
808 T85_X = 788,
809 T86_X = 789,
810 T87_X = 790,
811 T88_X = 791,
812 T89_X = 792,
813 T90_X = 793,
814 T91_X = 794,
815 T92_X = 795,
816 T93_X = 796,
817 T94_X = 797,
818 T95_X = 798,
819 T96_X = 799,
820 T97_X = 800,
821 T98_X = 801,
822 T99_X = 802,
823 T100_X = 803,
824 T101_X = 804,
825 T102_X = 805,
826 T103_X = 806,
827 T104_X = 807,
828 T105_X = 808,
829 T106_X = 809,
830 T107_X = 810,
831 T108_X = 811,
832 T109_X = 812,
833 T110_X = 813,
834 T111_X = 814,
835 T112_X = 815,
836 T113_X = 816,
837 T114_X = 817,
838 T115_X = 818,
839 T116_X = 819,
840 T117_X = 820,
841 T118_X = 821,
842 T119_X = 822,
843 T120_X = 823,
844 T121_X = 824,
845 T122_X = 825,
846 T123_X = 826,
847 T124_X = 827,
848 T125_X = 828,
849 T126_X = 829,
850 T127_X = 830,
851 T0_XY = 831,
852 T1_XY = 832,
853 T2_XY = 833,
854 T3_XY = 834,
855 T4_XY = 835,
856 T5_XY = 836,
857 T6_XY = 837,
858 T7_XY = 838,
859 T8_XY = 839,
860 T9_XY = 840,
861 T10_XY = 841,
862 T11_XY = 842,
863 T12_XY = 843,
864 T13_XY = 844,
865 T14_XY = 845,
866 T15_XY = 846,
867 T16_XY = 847,
868 T17_XY = 848,
869 T18_XY = 849,
870 T19_XY = 850,
871 T20_XY = 851,
872 T21_XY = 852,
873 T22_XY = 853,
874 T23_XY = 854,
875 T24_XY = 855,
876 T25_XY = 856,
877 T26_XY = 857,
878 T27_XY = 858,
879 T28_XY = 859,
880 T29_XY = 860,
881 T30_XY = 861,
882 T31_XY = 862,
883 T32_XY = 863,
884 T33_XY = 864,
885 T34_XY = 865,
886 T35_XY = 866,
887 T36_XY = 867,
888 T37_XY = 868,
889 T38_XY = 869,
890 T39_XY = 870,
891 T40_XY = 871,
892 T41_XY = 872,
893 T42_XY = 873,
894 T43_XY = 874,
895 T44_XY = 875,
896 T45_XY = 876,
897 T46_XY = 877,
898 T47_XY = 878,
899 T48_XY = 879,
900 T49_XY = 880,
901 T50_XY = 881,
902 T51_XY = 882,
903 T52_XY = 883,
904 T53_XY = 884,
905 T54_XY = 885,
906 T55_XY = 886,
907 T56_XY = 887,
908 T57_XY = 888,
909 T58_XY = 889,
910 T59_XY = 890,
911 T60_XY = 891,
912 T61_XY = 892,
913 T62_XY = 893,
914 T63_XY = 894,
915 T64_XY = 895,
916 T65_XY = 896,
917 T66_XY = 897,
918 T67_XY = 898,
919 T68_XY = 899,
920 T69_XY = 900,
921 T70_XY = 901,
922 T71_XY = 902,
923 T72_XY = 903,
924 T73_XY = 904,
925 T74_XY = 905,
926 T75_XY = 906,
927 T76_XY = 907,
928 T77_XY = 908,
929 T78_XY = 909,
930 T79_XY = 910,
931 T80_XY = 911,
932 T81_XY = 912,
933 T82_XY = 913,
934 T83_XY = 914,
935 T84_XY = 915,
936 T85_XY = 916,
937 T86_XY = 917,
938 T87_XY = 918,
939 T88_XY = 919,
940 T89_XY = 920,
941 T90_XY = 921,
942 T91_XY = 922,
943 T92_XY = 923,
944 T93_XY = 924,
945 T94_XY = 925,
946 T95_XY = 926,
947 T96_XY = 927,
948 T97_XY = 928,
949 T98_XY = 929,
950 T99_XY = 930,
951 T100_XY = 931,
952 T101_XY = 932,
953 T102_XY = 933,
954 T103_XY = 934,
955 T104_XY = 935,
956 T105_XY = 936,
957 T106_XY = 937,
958 T107_XY = 938,
959 T108_XY = 939,
960 T109_XY = 940,
961 T110_XY = 941,
962 T111_XY = 942,
963 T112_XY = 943,
964 T113_XY = 944,
965 T114_XY = 945,
966 T115_XY = 946,
967 T116_XY = 947,
968 T117_XY = 948,
969 T118_XY = 949,
970 T119_XY = 950,
971 T120_XY = 951,
972 T121_XY = 952,
973 T122_XY = 953,
974 T123_XY = 954,
975 T124_XY = 955,
976 T125_XY = 956,
977 T126_XY = 957,
978 T127_XY = 958,
979 T0_XYZW = 959,
980 T1_XYZW = 960,
981 T2_XYZW = 961,
982 T3_XYZW = 962,
983 T4_XYZW = 963,
984 T5_XYZW = 964,
985 T6_XYZW = 965,
986 T7_XYZW = 966,
987 T8_XYZW = 967,
988 T9_XYZW = 968,
989 T10_XYZW = 969,
990 T11_XYZW = 970,
991 T12_XYZW = 971,
992 T13_XYZW = 972,
993 T14_XYZW = 973,
994 T15_XYZW = 974,
995 T16_XYZW = 975,
996 T17_XYZW = 976,
997 T18_XYZW = 977,
998 T19_XYZW = 978,
999 T20_XYZW = 979,
1000 T21_XYZW = 980,
1001 T22_XYZW = 981,
1002 T23_XYZW = 982,
1003 T24_XYZW = 983,
1004 T25_XYZW = 984,
1005 T26_XYZW = 985,
1006 T27_XYZW = 986,
1007 T28_XYZW = 987,
1008 T29_XYZW = 988,
1009 T30_XYZW = 989,
1010 T31_XYZW = 990,
1011 T32_XYZW = 991,
1012 T33_XYZW = 992,
1013 T34_XYZW = 993,
1014 T35_XYZW = 994,
1015 T36_XYZW = 995,
1016 T37_XYZW = 996,
1017 T38_XYZW = 997,
1018 T39_XYZW = 998,
1019 T40_XYZW = 999,
1020 T41_XYZW = 1000,
1021 T42_XYZW = 1001,
1022 T43_XYZW = 1002,
1023 T44_XYZW = 1003,
1024 T45_XYZW = 1004,
1025 T46_XYZW = 1005,
1026 T47_XYZW = 1006,
1027 T48_XYZW = 1007,
1028 T49_XYZW = 1008,
1029 T50_XYZW = 1009,
1030 T51_XYZW = 1010,
1031 T52_XYZW = 1011,
1032 T53_XYZW = 1012,
1033 T54_XYZW = 1013,
1034 T55_XYZW = 1014,
1035 T56_XYZW = 1015,
1036 T57_XYZW = 1016,
1037 T58_XYZW = 1017,
1038 T59_XYZW = 1018,
1039 T60_XYZW = 1019,
1040 T61_XYZW = 1020,
1041 T62_XYZW = 1021,
1042 T63_XYZW = 1022,
1043 T64_XYZW = 1023,
1044 T65_XYZW = 1024,
1045 T66_XYZW = 1025,
1046 T67_XYZW = 1026,
1047 T68_XYZW = 1027,
1048 T69_XYZW = 1028,
1049 T70_XYZW = 1029,
1050 T71_XYZW = 1030,
1051 T72_XYZW = 1031,
1052 T73_XYZW = 1032,
1053 T74_XYZW = 1033,
1054 T75_XYZW = 1034,
1055 T76_XYZW = 1035,
1056 T77_XYZW = 1036,
1057 T78_XYZW = 1037,
1058 T79_XYZW = 1038,
1059 T80_XYZW = 1039,
1060 T81_XYZW = 1040,
1061 T82_XYZW = 1041,
1062 T83_XYZW = 1042,
1063 T84_XYZW = 1043,
1064 T85_XYZW = 1044,
1065 T86_XYZW = 1045,
1066 T87_XYZW = 1046,
1067 T88_XYZW = 1047,
1068 T89_XYZW = 1048,
1069 T90_XYZW = 1049,
1070 T91_XYZW = 1050,
1071 T92_XYZW = 1051,
1072 T93_XYZW = 1052,
1073 T94_XYZW = 1053,
1074 T95_XYZW = 1054,
1075 T96_XYZW = 1055,
1076 T97_XYZW = 1056,
1077 T98_XYZW = 1057,
1078 T99_XYZW = 1058,
1079 T100_XYZW = 1059,
1080 T101_XYZW = 1060,
1081 T102_XYZW = 1061,
1082 T103_XYZW = 1062,
1083 T104_XYZW = 1063,
1084 T105_XYZW = 1064,
1085 T106_XYZW = 1065,
1086 T107_XYZW = 1066,
1087 T108_XYZW = 1067,
1088 T109_XYZW = 1068,
1089 T110_XYZW = 1069,
1090 T111_XYZW = 1070,
1091 T112_XYZW = 1071,
1092 T113_XYZW = 1072,
1093 T114_XYZW = 1073,
1094 T115_XYZW = 1074,
1095 T116_XYZW = 1075,
1096 T117_XYZW = 1076,
1097 T118_XYZW = 1077,
1098 T119_XYZW = 1078,
1099 T120_XYZW = 1079,
1100 T121_XYZW = 1080,
1101 T122_XYZW = 1081,
1102 T123_XYZW = 1082,
1103 T124_XYZW = 1083,
1104 T125_XYZW = 1084,
1105 T126_XYZW = 1085,
1106 T127_XYZW = 1086,
1107 T0_Y = 1087,
1108 T1_Y = 1088,
1109 T2_Y = 1089,
1110 T3_Y = 1090,
1111 T4_Y = 1091,
1112 T5_Y = 1092,
1113 T6_Y = 1093,
1114 T7_Y = 1094,
1115 T8_Y = 1095,
1116 T9_Y = 1096,
1117 T10_Y = 1097,
1118 T11_Y = 1098,
1119 T12_Y = 1099,
1120 T13_Y = 1100,
1121 T14_Y = 1101,
1122 T15_Y = 1102,
1123 T16_Y = 1103,
1124 T17_Y = 1104,
1125 T18_Y = 1105,
1126 T19_Y = 1106,
1127 T20_Y = 1107,
1128 T21_Y = 1108,
1129 T22_Y = 1109,
1130 T23_Y = 1110,
1131 T24_Y = 1111,
1132 T25_Y = 1112,
1133 T26_Y = 1113,
1134 T27_Y = 1114,
1135 T28_Y = 1115,
1136 T29_Y = 1116,
1137 T30_Y = 1117,
1138 T31_Y = 1118,
1139 T32_Y = 1119,
1140 T33_Y = 1120,
1141 T34_Y = 1121,
1142 T35_Y = 1122,
1143 T36_Y = 1123,
1144 T37_Y = 1124,
1145 T38_Y = 1125,
1146 T39_Y = 1126,
1147 T40_Y = 1127,
1148 T41_Y = 1128,
1149 T42_Y = 1129,
1150 T43_Y = 1130,
1151 T44_Y = 1131,
1152 T45_Y = 1132,
1153 T46_Y = 1133,
1154 T47_Y = 1134,
1155 T48_Y = 1135,
1156 T49_Y = 1136,
1157 T50_Y = 1137,
1158 T51_Y = 1138,
1159 T52_Y = 1139,
1160 T53_Y = 1140,
1161 T54_Y = 1141,
1162 T55_Y = 1142,
1163 T56_Y = 1143,
1164 T57_Y = 1144,
1165 T58_Y = 1145,
1166 T59_Y = 1146,
1167 T60_Y = 1147,
1168 T61_Y = 1148,
1169 T62_Y = 1149,
1170 T63_Y = 1150,
1171 T64_Y = 1151,
1172 T65_Y = 1152,
1173 T66_Y = 1153,
1174 T67_Y = 1154,
1175 T68_Y = 1155,
1176 T69_Y = 1156,
1177 T70_Y = 1157,
1178 T71_Y = 1158,
1179 T72_Y = 1159,
1180 T73_Y = 1160,
1181 T74_Y = 1161,
1182 T75_Y = 1162,
1183 T76_Y = 1163,
1184 T77_Y = 1164,
1185 T78_Y = 1165,
1186 T79_Y = 1166,
1187 T80_Y = 1167,
1188 T81_Y = 1168,
1189 T82_Y = 1169,
1190 T83_Y = 1170,
1191 T84_Y = 1171,
1192 T85_Y = 1172,
1193 T86_Y = 1173,
1194 T87_Y = 1174,
1195 T88_Y = 1175,
1196 T89_Y = 1176,
1197 T90_Y = 1177,
1198 T91_Y = 1178,
1199 T92_Y = 1179,
1200 T93_Y = 1180,
1201 T94_Y = 1181,
1202 T95_Y = 1182,
1203 T96_Y = 1183,
1204 T97_Y = 1184,
1205 T98_Y = 1185,
1206 T99_Y = 1186,
1207 T100_Y = 1187,
1208 T101_Y = 1188,
1209 T102_Y = 1189,
1210 T103_Y = 1190,
1211 T104_Y = 1191,
1212 T105_Y = 1192,
1213 T106_Y = 1193,
1214 T107_Y = 1194,
1215 T108_Y = 1195,
1216 T109_Y = 1196,
1217 T110_Y = 1197,
1218 T111_Y = 1198,
1219 T112_Y = 1199,
1220 T113_Y = 1200,
1221 T114_Y = 1201,
1222 T115_Y = 1202,
1223 T116_Y = 1203,
1224 T117_Y = 1204,
1225 T118_Y = 1205,
1226 T119_Y = 1206,
1227 T120_Y = 1207,
1228 T121_Y = 1208,
1229 T122_Y = 1209,
1230 T123_Y = 1210,
1231 T124_Y = 1211,
1232 T125_Y = 1212,
1233 T126_Y = 1213,
1234 T127_Y = 1214,
1235 T0_Z = 1215,
1236 T1_Z = 1216,
1237 T2_Z = 1217,
1238 T3_Z = 1218,
1239 T4_Z = 1219,
1240 T5_Z = 1220,
1241 T6_Z = 1221,
1242 T7_Z = 1222,
1243 T8_Z = 1223,
1244 T9_Z = 1224,
1245 T10_Z = 1225,
1246 T11_Z = 1226,
1247 T12_Z = 1227,
1248 T13_Z = 1228,
1249 T14_Z = 1229,
1250 T15_Z = 1230,
1251 T16_Z = 1231,
1252 T17_Z = 1232,
1253 T18_Z = 1233,
1254 T19_Z = 1234,
1255 T20_Z = 1235,
1256 T21_Z = 1236,
1257 T22_Z = 1237,
1258 T23_Z = 1238,
1259 T24_Z = 1239,
1260 T25_Z = 1240,
1261 T26_Z = 1241,
1262 T27_Z = 1242,
1263 T28_Z = 1243,
1264 T29_Z = 1244,
1265 T30_Z = 1245,
1266 T31_Z = 1246,
1267 T32_Z = 1247,
1268 T33_Z = 1248,
1269 T34_Z = 1249,
1270 T35_Z = 1250,
1271 T36_Z = 1251,
1272 T37_Z = 1252,
1273 T38_Z = 1253,
1274 T39_Z = 1254,
1275 T40_Z = 1255,
1276 T41_Z = 1256,
1277 T42_Z = 1257,
1278 T43_Z = 1258,
1279 T44_Z = 1259,
1280 T45_Z = 1260,
1281 T46_Z = 1261,
1282 T47_Z = 1262,
1283 T48_Z = 1263,
1284 T49_Z = 1264,
1285 T50_Z = 1265,
1286 T51_Z = 1266,
1287 T52_Z = 1267,
1288 T53_Z = 1268,
1289 T54_Z = 1269,
1290 T55_Z = 1270,
1291 T56_Z = 1271,
1292 T57_Z = 1272,
1293 T58_Z = 1273,
1294 T59_Z = 1274,
1295 T60_Z = 1275,
1296 T61_Z = 1276,
1297 T62_Z = 1277,
1298 T63_Z = 1278,
1299 T64_Z = 1279,
1300 T65_Z = 1280,
1301 T66_Z = 1281,
1302 T67_Z = 1282,
1303 T68_Z = 1283,
1304 T69_Z = 1284,
1305 T70_Z = 1285,
1306 T71_Z = 1286,
1307 T72_Z = 1287,
1308 T73_Z = 1288,
1309 T74_Z = 1289,
1310 T75_Z = 1290,
1311 T76_Z = 1291,
1312 T77_Z = 1292,
1313 T78_Z = 1293,
1314 T79_Z = 1294,
1315 T80_Z = 1295,
1316 T81_Z = 1296,
1317 T82_Z = 1297,
1318 T83_Z = 1298,
1319 T84_Z = 1299,
1320 T85_Z = 1300,
1321 T86_Z = 1301,
1322 T87_Z = 1302,
1323 T88_Z = 1303,
1324 T89_Z = 1304,
1325 T90_Z = 1305,
1326 T91_Z = 1306,
1327 T92_Z = 1307,
1328 T93_Z = 1308,
1329 T94_Z = 1309,
1330 T95_Z = 1310,
1331 T96_Z = 1311,
1332 T97_Z = 1312,
1333 T98_Z = 1313,
1334 T99_Z = 1314,
1335 T100_Z = 1315,
1336 T101_Z = 1316,
1337 T102_Z = 1317,
1338 T103_Z = 1318,
1339 T104_Z = 1319,
1340 T105_Z = 1320,
1341 T106_Z = 1321,
1342 T107_Z = 1322,
1343 T108_Z = 1323,
1344 T109_Z = 1324,
1345 T110_Z = 1325,
1346 T111_Z = 1326,
1347 T112_Z = 1327,
1348 T113_Z = 1328,
1349 T114_Z = 1329,
1350 T115_Z = 1330,
1351 T116_Z = 1331,
1352 T117_Z = 1332,
1353 T118_Z = 1333,
1354 T119_Z = 1334,
1355 T120_Z = 1335,
1356 T121_Z = 1336,
1357 T122_Z = 1337,
1358 T123_Z = 1338,
1359 T124_Z = 1339,
1360 T125_Z = 1340,
1361 T126_Z = 1341,
1362 T127_Z = 1342,
1363 V01_W = 1343,
1364 V23_W = 1344,
1365 V0123_W = 1345,
1366 V01_X = 1346,
1367 V23_X = 1347,
1368 V0123_X = 1348,
1369 V01_Y = 1349,
1370 V23_Y = 1350,
1371 V0123_Y = 1351,
1372 V01_Z = 1352,
1373 V23_Z = 1353,
1374 V0123_Z = 1354,
1375 KC0_128_W = 1355,
1376 KC0_129_W = 1356,
1377 KC0_130_W = 1357,
1378 KC0_131_W = 1358,
1379 KC0_132_W = 1359,
1380 KC0_133_W = 1360,
1381 KC0_134_W = 1361,
1382 KC0_135_W = 1362,
1383 KC0_136_W = 1363,
1384 KC0_137_W = 1364,
1385 KC0_138_W = 1365,
1386 KC0_139_W = 1366,
1387 KC0_140_W = 1367,
1388 KC0_141_W = 1368,
1389 KC0_142_W = 1369,
1390 KC0_143_W = 1370,
1391 KC0_144_W = 1371,
1392 KC0_145_W = 1372,
1393 KC0_146_W = 1373,
1394 KC0_147_W = 1374,
1395 KC0_148_W = 1375,
1396 KC0_149_W = 1376,
1397 KC0_150_W = 1377,
1398 KC0_151_W = 1378,
1399 KC0_152_W = 1379,
1400 KC0_153_W = 1380,
1401 KC0_154_W = 1381,
1402 KC0_155_W = 1382,
1403 KC0_156_W = 1383,
1404 KC0_157_W = 1384,
1405 KC0_158_W = 1385,
1406 KC0_159_W = 1386,
1407 KC1_160_W = 1387,
1408 KC1_161_W = 1388,
1409 KC1_162_W = 1389,
1410 KC1_163_W = 1390,
1411 KC1_164_W = 1391,
1412 KC1_165_W = 1392,
1413 KC1_166_W = 1393,
1414 KC1_167_W = 1394,
1415 KC1_168_W = 1395,
1416 KC1_169_W = 1396,
1417 KC1_170_W = 1397,
1418 KC1_171_W = 1398,
1419 KC1_172_W = 1399,
1420 KC1_173_W = 1400,
1421 KC1_174_W = 1401,
1422 KC1_175_W = 1402,
1423 KC1_176_W = 1403,
1424 KC1_177_W = 1404,
1425 KC1_178_W = 1405,
1426 KC1_179_W = 1406,
1427 KC1_180_W = 1407,
1428 KC1_181_W = 1408,
1429 KC1_182_W = 1409,
1430 KC1_183_W = 1410,
1431 KC1_184_W = 1411,
1432 KC1_185_W = 1412,
1433 KC1_186_W = 1413,
1434 KC1_187_W = 1414,
1435 KC1_188_W = 1415,
1436 KC1_189_W = 1416,
1437 KC1_190_W = 1417,
1438 KC1_191_W = 1418,
1439 KC0_128_X = 1419,
1440 KC0_129_X = 1420,
1441 KC0_130_X = 1421,
1442 KC0_131_X = 1422,
1443 KC0_132_X = 1423,
1444 KC0_133_X = 1424,
1445 KC0_134_X = 1425,
1446 KC0_135_X = 1426,
1447 KC0_136_X = 1427,
1448 KC0_137_X = 1428,
1449 KC0_138_X = 1429,
1450 KC0_139_X = 1430,
1451 KC0_140_X = 1431,
1452 KC0_141_X = 1432,
1453 KC0_142_X = 1433,
1454 KC0_143_X = 1434,
1455 KC0_144_X = 1435,
1456 KC0_145_X = 1436,
1457 KC0_146_X = 1437,
1458 KC0_147_X = 1438,
1459 KC0_148_X = 1439,
1460 KC0_149_X = 1440,
1461 KC0_150_X = 1441,
1462 KC0_151_X = 1442,
1463 KC0_152_X = 1443,
1464 KC0_153_X = 1444,
1465 KC0_154_X = 1445,
1466 KC0_155_X = 1446,
1467 KC0_156_X = 1447,
1468 KC0_157_X = 1448,
1469 KC0_158_X = 1449,
1470 KC0_159_X = 1450,
1471 KC1_160_X = 1451,
1472 KC1_161_X = 1452,
1473 KC1_162_X = 1453,
1474 KC1_163_X = 1454,
1475 KC1_164_X = 1455,
1476 KC1_165_X = 1456,
1477 KC1_166_X = 1457,
1478 KC1_167_X = 1458,
1479 KC1_168_X = 1459,
1480 KC1_169_X = 1460,
1481 KC1_170_X = 1461,
1482 KC1_171_X = 1462,
1483 KC1_172_X = 1463,
1484 KC1_173_X = 1464,
1485 KC1_174_X = 1465,
1486 KC1_175_X = 1466,
1487 KC1_176_X = 1467,
1488 KC1_177_X = 1468,
1489 KC1_178_X = 1469,
1490 KC1_179_X = 1470,
1491 KC1_180_X = 1471,
1492 KC1_181_X = 1472,
1493 KC1_182_X = 1473,
1494 KC1_183_X = 1474,
1495 KC1_184_X = 1475,
1496 KC1_185_X = 1476,
1497 KC1_186_X = 1477,
1498 KC1_187_X = 1478,
1499 KC1_188_X = 1479,
1500 KC1_189_X = 1480,
1501 KC1_190_X = 1481,
1502 KC1_191_X = 1482,
1503 KC0_128_XYZW = 1483,
1504 KC0_129_XYZW = 1484,
1505 KC0_130_XYZW = 1485,
1506 KC0_131_XYZW = 1486,
1507 KC0_132_XYZW = 1487,
1508 KC0_133_XYZW = 1488,
1509 KC0_134_XYZW = 1489,
1510 KC0_135_XYZW = 1490,
1511 KC0_136_XYZW = 1491,
1512 KC0_137_XYZW = 1492,
1513 KC0_138_XYZW = 1493,
1514 KC0_139_XYZW = 1494,
1515 KC0_140_XYZW = 1495,
1516 KC0_141_XYZW = 1496,
1517 KC0_142_XYZW = 1497,
1518 KC0_143_XYZW = 1498,
1519 KC0_144_XYZW = 1499,
1520 KC0_145_XYZW = 1500,
1521 KC0_146_XYZW = 1501,
1522 KC0_147_XYZW = 1502,
1523 KC0_148_XYZW = 1503,
1524 KC0_149_XYZW = 1504,
1525 KC0_150_XYZW = 1505,
1526 KC0_151_XYZW = 1506,
1527 KC0_152_XYZW = 1507,
1528 KC0_153_XYZW = 1508,
1529 KC0_154_XYZW = 1509,
1530 KC0_155_XYZW = 1510,
1531 KC0_156_XYZW = 1511,
1532 KC0_157_XYZW = 1512,
1533 KC0_158_XYZW = 1513,
1534 KC0_159_XYZW = 1514,
1535 KC1_160_XYZW = 1515,
1536 KC1_161_XYZW = 1516,
1537 KC1_162_XYZW = 1517,
1538 KC1_163_XYZW = 1518,
1539 KC1_164_XYZW = 1519,
1540 KC1_165_XYZW = 1520,
1541 KC1_166_XYZW = 1521,
1542 KC1_167_XYZW = 1522,
1543 KC1_168_XYZW = 1523,
1544 KC1_169_XYZW = 1524,
1545 KC1_170_XYZW = 1525,
1546 KC1_171_XYZW = 1526,
1547 KC1_172_XYZW = 1527,
1548 KC1_173_XYZW = 1528,
1549 KC1_174_XYZW = 1529,
1550 KC1_175_XYZW = 1530,
1551 KC1_176_XYZW = 1531,
1552 KC1_177_XYZW = 1532,
1553 KC1_178_XYZW = 1533,
1554 KC1_179_XYZW = 1534,
1555 KC1_180_XYZW = 1535,
1556 KC1_181_XYZW = 1536,
1557 KC1_182_XYZW = 1537,
1558 KC1_183_XYZW = 1538,
1559 KC1_184_XYZW = 1539,
1560 KC1_185_XYZW = 1540,
1561 KC1_186_XYZW = 1541,
1562 KC1_187_XYZW = 1542,
1563 KC1_188_XYZW = 1543,
1564 KC1_189_XYZW = 1544,
1565 KC1_190_XYZW = 1545,
1566 KC1_191_XYZW = 1546,
1567 KC0_128_Y = 1547,
1568 KC0_129_Y = 1548,
1569 KC0_130_Y = 1549,
1570 KC0_131_Y = 1550,
1571 KC0_132_Y = 1551,
1572 KC0_133_Y = 1552,
1573 KC0_134_Y = 1553,
1574 KC0_135_Y = 1554,
1575 KC0_136_Y = 1555,
1576 KC0_137_Y = 1556,
1577 KC0_138_Y = 1557,
1578 KC0_139_Y = 1558,
1579 KC0_140_Y = 1559,
1580 KC0_141_Y = 1560,
1581 KC0_142_Y = 1561,
1582 KC0_143_Y = 1562,
1583 KC0_144_Y = 1563,
1584 KC0_145_Y = 1564,
1585 KC0_146_Y = 1565,
1586 KC0_147_Y = 1566,
1587 KC0_148_Y = 1567,
1588 KC0_149_Y = 1568,
1589 KC0_150_Y = 1569,
1590 KC0_151_Y = 1570,
1591 KC0_152_Y = 1571,
1592 KC0_153_Y = 1572,
1593 KC0_154_Y = 1573,
1594 KC0_155_Y = 1574,
1595 KC0_156_Y = 1575,
1596 KC0_157_Y = 1576,
1597 KC0_158_Y = 1577,
1598 KC0_159_Y = 1578,
1599 KC1_160_Y = 1579,
1600 KC1_161_Y = 1580,
1601 KC1_162_Y = 1581,
1602 KC1_163_Y = 1582,
1603 KC1_164_Y = 1583,
1604 KC1_165_Y = 1584,
1605 KC1_166_Y = 1585,
1606 KC1_167_Y = 1586,
1607 KC1_168_Y = 1587,
1608 KC1_169_Y = 1588,
1609 KC1_170_Y = 1589,
1610 KC1_171_Y = 1590,
1611 KC1_172_Y = 1591,
1612 KC1_173_Y = 1592,
1613 KC1_174_Y = 1593,
1614 KC1_175_Y = 1594,
1615 KC1_176_Y = 1595,
1616 KC1_177_Y = 1596,
1617 KC1_178_Y = 1597,
1618 KC1_179_Y = 1598,
1619 KC1_180_Y = 1599,
1620 KC1_181_Y = 1600,
1621 KC1_182_Y = 1601,
1622 KC1_183_Y = 1602,
1623 KC1_184_Y = 1603,
1624 KC1_185_Y = 1604,
1625 KC1_186_Y = 1605,
1626 KC1_187_Y = 1606,
1627 KC1_188_Y = 1607,
1628 KC1_189_Y = 1608,
1629 KC1_190_Y = 1609,
1630 KC1_191_Y = 1610,
1631 KC0_128_Z = 1611,
1632 KC0_129_Z = 1612,
1633 KC0_130_Z = 1613,
1634 KC0_131_Z = 1614,
1635 KC0_132_Z = 1615,
1636 KC0_133_Z = 1616,
1637 KC0_134_Z = 1617,
1638 KC0_135_Z = 1618,
1639 KC0_136_Z = 1619,
1640 KC0_137_Z = 1620,
1641 KC0_138_Z = 1621,
1642 KC0_139_Z = 1622,
1643 KC0_140_Z = 1623,
1644 KC0_141_Z = 1624,
1645 KC0_142_Z = 1625,
1646 KC0_143_Z = 1626,
1647 KC0_144_Z = 1627,
1648 KC0_145_Z = 1628,
1649 KC0_146_Z = 1629,
1650 KC0_147_Z = 1630,
1651 KC0_148_Z = 1631,
1652 KC0_149_Z = 1632,
1653 KC0_150_Z = 1633,
1654 KC0_151_Z = 1634,
1655 KC0_152_Z = 1635,
1656 KC0_153_Z = 1636,
1657 KC0_154_Z = 1637,
1658 KC0_155_Z = 1638,
1659 KC0_156_Z = 1639,
1660 KC0_157_Z = 1640,
1661 KC0_158_Z = 1641,
1662 KC0_159_Z = 1642,
1663 KC1_160_Z = 1643,
1664 KC1_161_Z = 1644,
1665 KC1_162_Z = 1645,
1666 KC1_163_Z = 1646,
1667 KC1_164_Z = 1647,
1668 KC1_165_Z = 1648,
1669 KC1_166_Z = 1649,
1670 KC1_167_Z = 1650,
1671 KC1_168_Z = 1651,
1672 KC1_169_Z = 1652,
1673 KC1_170_Z = 1653,
1674 KC1_171_Z = 1654,
1675 KC1_172_Z = 1655,
1676 KC1_173_Z = 1656,
1677 KC1_174_Z = 1657,
1678 KC1_175_Z = 1658,
1679 KC1_176_Z = 1659,
1680 KC1_177_Z = 1660,
1681 KC1_178_Z = 1661,
1682 KC1_179_Z = 1662,
1683 KC1_180_Z = 1663,
1684 KC1_181_Z = 1664,
1685 KC1_182_Z = 1665,
1686 KC1_183_Z = 1666,
1687 KC1_184_Z = 1667,
1688 KC1_185_Z = 1668,
1689 KC1_186_Z = 1669,
1690 KC1_187_Z = 1670,
1691 KC1_188_Z = 1671,
1692 KC1_189_Z = 1672,
1693 KC1_190_Z = 1673,
1694 KC1_191_Z = 1674,
1695 NUM_TARGET_REGS // 1675
1696};
1697} // end namespace R600
1698
1699// Register classes
1700
1701namespace R600 {
1702enum {
1703 R600_Reg32RegClassID = 0,
1704 R600_TReg32RegClassID = 1,
1705 R600_TReg32_XRegClassID = 2,
1706 R600_AddrRegClassID = 3,
1707 R600_KC0RegClassID = 4,
1708 R600_KC1RegClassID = 5,
1709 R600_TReg32_WRegClassID = 6,
1710 R600_TReg32_YRegClassID = 7,
1711 R600_TReg32_ZRegClassID = 8,
1712 R600_ArrayBaseRegClassID = 9,
1713 R600_KC0_WRegClassID = 10,
1714 R600_KC0_XRegClassID = 11,
1715 R600_KC0_YRegClassID = 12,
1716 R600_KC0_ZRegClassID = 13,
1717 R600_KC1_WRegClassID = 14,
1718 R600_KC1_XRegClassID = 15,
1719 R600_KC1_YRegClassID = 16,
1720 R600_KC1_ZRegClassID = 17,
1721 R600_LDS_SRC_REGRegClassID = 18,
1722 R600_PredicateRegClassID = 19,
1723 R600_Addr_WRegClassID = 20,
1724 R600_Addr_YRegClassID = 21,
1725 R600_Addr_ZRegClassID = 22,
1726 R600_LDS_SRC_REG_and_R600_Reg32RegClassID = 23,
1727 R600_Predicate_BitRegClassID = 24,
1728 R600_Reg64RegClassID = 25,
1729 R600_Reg64VerticalRegClassID = 26,
1730 R600_Reg64Vertical_with_sub0_in_R600_TReg32_WRegClassID = 27,
1731 R600_Reg64Vertical_with_sub0_in_R600_TReg32_XRegClassID = 28,
1732 R600_Reg64Vertical_with_sub0_in_R600_TReg32_YRegClassID = 29,
1733 R600_Reg64Vertical_with_sub0_in_R600_TReg32_ZRegClassID = 30,
1734 R600_Reg128RegClassID = 31,
1735 R600_Reg128VerticalRegClassID = 32,
1736 R600_Reg128Vertical_with_sub0_in_R600_TReg32_WRegClassID = 33,
1737 R600_Reg128Vertical_with_sub0_in_R600_TReg32_XRegClassID = 34,
1738 R600_Reg128Vertical_with_sub0_in_R600_TReg32_YRegClassID = 35,
1739 R600_Reg128Vertical_with_sub0_in_R600_TReg32_ZRegClassID = 36,
1740
1741};
1742} // end namespace R600
1743
1744
1745// Subregister indices
1746
1747namespace R600 {
1748enum : uint16_t {
1749 NoSubRegister,
1750 sub0, // 1
1751 sub1, // 2
1752 sub2, // 3
1753 sub3, // 4
1754 sub4, // 5
1755 sub5, // 6
1756 sub6, // 7
1757 sub7, // 8
1758 sub8, // 9
1759 sub9, // 10
1760 sub10, // 11
1761 sub11, // 12
1762 sub12, // 13
1763 sub13, // 14
1764 sub14, // 15
1765 sub15, // 16
1766 NUM_TARGET_SUBREGS
1767};
1768} // end namespace R600
1769
1770// Register pressure sets enum.
1771namespace R600 {
1772enum RegisterPressureSets {
1773 R600_LDS_SRC_REG_and_R600_Reg32 = 0,
1774 R600_Predicate_Bit = 1,
1775 R600_Predicate = 2,
1776 R600_Reg64Vertical_with_sub0_in_R600_TReg32_W = 3,
1777 R600_Reg64Vertical_with_sub0_in_R600_TReg32_X = 4,
1778 R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y = 5,
1779 R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z = 6,
1780 R600_Reg64Vertical = 7,
1781 R600_ArrayBase = 8,
1782 R600_TReg32_W = 9,
1783 R600_TReg32_Y = 10,
1784 R600_TReg32_Z = 11,
1785 R600_Reg64 = 12,
1786 R600_TReg32_X = 13,
1787 R600_Reg64_with_R600_Reg64Vertical = 14,
1788 R600_TReg32_W_with_R600_Reg64Vertical = 15,
1789 R600_TReg32_Y_with_R600_Reg64Vertical = 16,
1790 R600_TReg32_Z_with_R600_Reg64Vertical = 17,
1791 R600_TReg32_X_with_R600_Reg64Vertical = 18,
1792 R600_TReg32_Y_with_R600_Reg64 = 19,
1793 R600_TReg32_X_with_R600_Reg64 = 20,
1794 R600_TReg32 = 21,
1795 R600_Reg32 = 22,
1796};
1797} // end namespace R600
1798
1799} // end namespace llvm
1800
1801#endif // GET_REGINFO_ENUM
1802
1803/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
1804|* *|
1805|* MC Register Information *|
1806|* *|
1807|* Automatically generated file, do not edit! *|
1808|* *|
1809\*===----------------------------------------------------------------------===*/
1810
1811
1812#ifdef GET_REGINFO_MC_DESC
1813#undef GET_REGINFO_MC_DESC
1814
1815namespace llvm {
1816
1817extern const int16_t R600RegDiffLists[] = {
1818 /* 0 */ -256, 384, 128, -640, 0,
1819 /* 5 */ -64, 128, 64, -256, 0,
1820 /* 10 */ -128, 0,
1821 /* 12 */ -64, 0,
1822 /* 14 */ -768, 1, 0,
1823 /* 17 */ -767, 1, 0,
1824 /* 20 */ -643, 1, 0,
1825 /* 23 */ -642, 1, 0,
1826 /* 26 */ -262, 1, 0,
1827 /* 29 */ -261, 1, 0,
1828 /* 32 */ -137, 1, 0,
1829 /* 35 */ -136, 1, 0,
1830 /* 38 */ -770, 1, 1, 1, 0,
1831 /* 43 */ -645, 1, 1, 1, 0,
1832 /* 48 */ -264, 1, 1, 1, 0,
1833 /* 53 */ -139, 1, 1, 1, 0,
1834 /* 58 */ 64, 64, 1, 0,
1835 /* 62 */ 64, 65, 1, 0,
1836 /* 66 */ 64, 66, 1, 0,
1837 /* 70 */ 64, 67, 1, 0,
1838 /* 74 */ 64, 68, 1, 0,
1839 /* 78 */ 64, 69, 1, 0,
1840 /* 82 */ 64, 70, 1, 0,
1841 /* 86 */ 64, 71, 1, 0,
1842 /* 90 */ 64, 72, 1, 0,
1843 /* 94 */ 64, 73, 1, 0,
1844 /* 98 */ 64, 74, 1, 0,
1845 /* 102 */ 64, 75, 1, 0,
1846 /* 106 */ 64, 76, 1, 0,
1847 /* 110 */ 64, 77, 1, 0,
1848 /* 114 */ 64, 78, 1, 0,
1849 /* 118 */ 64, 79, 1, 0,
1850 /* 122 */ 64, 80, 1, 0,
1851 /* 126 */ 64, 81, 1, 0,
1852 /* 130 */ 64, 82, 1, 0,
1853 /* 134 */ 64, 83, 1, 0,
1854 /* 138 */ 64, 84, 1, 0,
1855 /* 142 */ 64, 85, 1, 0,
1856 /* 146 */ 64, 86, 1, 0,
1857 /* 150 */ 64, 87, 1, 0,
1858 /* 154 */ 64, 88, 1, 0,
1859 /* 158 */ 64, 89, 1, 0,
1860 /* 162 */ 64, 90, 1, 0,
1861 /* 166 */ 64, 91, 1, 0,
1862 /* 170 */ 64, 92, 1, 0,
1863 /* 174 */ 64, 93, 1, 0,
1864 /* 178 */ 64, 94, 1, 0,
1865 /* 182 */ 64, 95, 1, 0,
1866 /* 186 */ 64, 96, 1, 0,
1867 /* 190 */ 64, 97, 1, 0,
1868 /* 194 */ 64, 98, 1, 0,
1869 /* 198 */ 64, 99, 1, 0,
1870 /* 202 */ 64, 100, 1, 0,
1871 /* 206 */ 64, 101, 1, 0,
1872 /* 210 */ 64, 102, 1, 0,
1873 /* 214 */ 64, 103, 1, 0,
1874 /* 218 */ 64, 104, 1, 0,
1875 /* 222 */ 64, 105, 1, 0,
1876 /* 226 */ 64, 106, 1, 0,
1877 /* 230 */ 64, 107, 1, 0,
1878 /* 234 */ 64, 108, 1, 0,
1879 /* 238 */ 64, 109, 1, 0,
1880 /* 242 */ 64, 110, 1, 0,
1881 /* 246 */ 64, 111, 1, 0,
1882 /* 250 */ 64, 112, 1, 0,
1883 /* 254 */ 64, 113, 1, 0,
1884 /* 258 */ 64, 114, 1, 0,
1885 /* 262 */ 64, 115, 1, 0,
1886 /* 266 */ 64, 116, 1, 0,
1887 /* 270 */ 64, 117, 1, 0,
1888 /* 274 */ 64, 118, 1, 0,
1889 /* 278 */ 64, 119, 1, 0,
1890 /* 282 */ 64, 120, 1, 0,
1891 /* 286 */ 64, 121, 1, 0,
1892 /* 290 */ 64, 122, 1, 0,
1893 /* 294 */ 64, 123, 1, 0,
1894 /* 298 */ 64, 124, 1, 0,
1895 /* 302 */ 64, 125, 1, 0,
1896 /* 306 */ 64, 126, 1, 0,
1897 /* 310 */ 64, 127, 1, 0,
1898 /* 314 */ 384, 382, 1, 0,
1899 /* 318 */ 384, 383, 1, 0,
1900 /* 322 */ 128, 128, 385, 1, 0,
1901 /* 327 */ 128, 128, 386, 1, 0,
1902 /* 332 */ -256, 128, 388, 1, 0,
1903 /* 337 */ -256, 128, 389, 1, 0,
1904 /* 342 */ -256, 391, 1, 0,
1905 /* 346 */ -256, 392, 1, 0,
1906 /* 350 */ 384, 383, 2, 0,
1907 /* 354 */ 384, 384, 2, 0,
1908 /* 358 */ 128, 128, 386, 2, 0,
1909 /* 363 */ 128, 128, 387, 2, 0,
1910 /* 368 */ -256, 128, 389, 2, 0,
1911 /* 373 */ -256, 128, 390, 2, 0,
1912 /* 378 */ -256, 392, 2, 0,
1913 /* 382 */ -256, 393, 2, 0,
1914 /* 386 */ 64, 0,
1915 /* 388 */ -256, 128, 0,
1916 /* 391 */ 128, 128, 128, 0,
1917 /* 395 */ -128, 384, 0,
1918};
1919
1920extern const LaneBitmask R600LaneMaskLists[] = {
1921 /* 0 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000002),
1922 /* 2 */ LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000004),
1923 /* 6 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008),
1924 /* 10 */ LaneBitmask(0xFFFFFFFFFFFFFFFF),
1925};
1926
1927extern const uint16_t R600SubRegIdxLists[] = {
1928 /* 0 */ 1, 2,
1929 /* 2 */ 1, 2, 3, 4,
1930};
1931
1932
1933#ifdef __GNUC__
1934#pragma GCC diagnostic push
1935#pragma GCC diagnostic ignored "-Woverlength-strings"
1936#endif
1937extern const char R600RegStrings[] = {
1938 /* 0 */ "ArrayBase450\000"
1939 /* 13 */ "ArrayBase460\000"
1940 /* 26 */ "ArrayBase470\000"
1941 /* 39 */ "ArrayBase480\000"
1942 /* 52 */ "ArrayBase451\000"
1943 /* 65 */ "ArrayBase461\000"
1944 /* 78 */ "ArrayBase471\000"
1945 /* 91 */ "ArrayBase452\000"
1946 /* 104 */ "ArrayBase462\000"
1947 /* 117 */ "ArrayBase472\000"
1948 /* 130 */ "ArrayBase453\000"
1949 /* 143 */ "ArrayBase463\000"
1950 /* 156 */ "ArrayBase473\000"
1951 /* 169 */ "ArrayBase454\000"
1952 /* 182 */ "ArrayBase464\000"
1953 /* 195 */ "ArrayBase474\000"
1954 /* 208 */ "ArrayBase455\000"
1955 /* 221 */ "ArrayBase465\000"
1956 /* 234 */ "ArrayBase475\000"
1957 /* 247 */ "ArrayBase456\000"
1958 /* 260 */ "ArrayBase466\000"
1959 /* 273 */ "ArrayBase476\000"
1960 /* 286 */ "ArrayBase457\000"
1961 /* 299 */ "ArrayBase467\000"
1962 /* 312 */ "ArrayBase477\000"
1963 /* 325 */ "ArrayBase448\000"
1964 /* 338 */ "ArrayBase458\000"
1965 /* 351 */ "ArrayBase468\000"
1966 /* 364 */ "ArrayBase478\000"
1967 /* 377 */ "ArrayBase449\000"
1968 /* 390 */ "ArrayBase459\000"
1969 /* 403 */ "ArrayBase469\000"
1970 /* 416 */ "ArrayBase479\000"
1971 /* 429 */ "OQA\000"
1972 /* 433 */ "LDS_DIRECT_A\000"
1973 /* 446 */ "OQB\000"
1974 /* 450 */ "LDS_DIRECT_B\000"
1975 /* 463 */ "NEG_ONE\000"
1976 /* 471 */ "PRED_SEL_ONE\000"
1977 /* 484 */ "PRED_SEL_OFF\000"
1978 /* 497 */ "NEG_HALF\000"
1979 /* 506 */ "ALU_PARAM\000"
1980 /* 516 */ "PRED_SEL_ZERO\000"
1981 /* 530 */ "OQAP\000"
1982 /* 535 */ "OQBP\000"
1983 /* 540 */ "INDIRECT_BASE_ADDR\000"
1984 /* 559 */ "PS\000"
1985 /* 562 */ "PREDICATE_BIT\000"
1986 /* 576 */ "ONE_INT\000"
1987 /* 584 */ "ALU_CONST\000"
1988 /* 594 */ "T100_XYZW\000"
1989 /* 604 */ "T110_XYZW\000"
1990 /* 614 */ "T10_XYZW\000"
1991 /* 623 */ "T120_XYZW\000"
1992 /* 633 */ "T20_XYZW\000"
1993 /* 642 */ "KC0_130_XYZW\000"
1994 /* 655 */ "T30_XYZW\000"
1995 /* 664 */ "KC0_140_XYZW\000"
1996 /* 677 */ "T40_XYZW\000"
1997 /* 686 */ "KC0_150_XYZW\000"
1998 /* 699 */ "T50_XYZW\000"
1999 /* 708 */ "KC1_160_XYZW\000"
2000 /* 721 */ "T60_XYZW\000"
2001 /* 730 */ "KC1_170_XYZW\000"
2002 /* 743 */ "T70_XYZW\000"
2003 /* 752 */ "KC1_180_XYZW\000"
2004 /* 765 */ "T80_XYZW\000"
2005 /* 774 */ "KC1_190_XYZW\000"
2006 /* 787 */ "T90_XYZW\000"
2007 /* 796 */ "T0_XYZW\000"
2008 /* 804 */ "T101_XYZW\000"
2009 /* 814 */ "T111_XYZW\000"
2010 /* 824 */ "T11_XYZW\000"
2011 /* 833 */ "T121_XYZW\000"
2012 /* 843 */ "T21_XYZW\000"
2013 /* 852 */ "KC0_131_XYZW\000"
2014 /* 865 */ "T31_XYZW\000"
2015 /* 874 */ "KC0_141_XYZW\000"
2016 /* 887 */ "T41_XYZW\000"
2017 /* 896 */ "KC0_151_XYZW\000"
2018 /* 909 */ "T51_XYZW\000"
2019 /* 918 */ "KC1_161_XYZW\000"
2020 /* 931 */ "T61_XYZW\000"
2021 /* 940 */ "KC1_171_XYZW\000"
2022 /* 953 */ "T71_XYZW\000"
2023 /* 962 */ "KC1_181_XYZW\000"
2024 /* 975 */ "T81_XYZW\000"
2025 /* 984 */ "KC1_191_XYZW\000"
2026 /* 997 */ "T91_XYZW\000"
2027 /* 1006 */ "T1_XYZW\000"
2028 /* 1014 */ "T102_XYZW\000"
2029 /* 1024 */ "T112_XYZW\000"
2030 /* 1034 */ "T12_XYZW\000"
2031 /* 1043 */ "T122_XYZW\000"
2032 /* 1053 */ "T22_XYZW\000"
2033 /* 1062 */ "KC0_132_XYZW\000"
2034 /* 1075 */ "T32_XYZW\000"
2035 /* 1084 */ "KC0_142_XYZW\000"
2036 /* 1097 */ "T42_XYZW\000"
2037 /* 1106 */ "KC0_152_XYZW\000"
2038 /* 1119 */ "T52_XYZW\000"
2039 /* 1128 */ "KC1_162_XYZW\000"
2040 /* 1141 */ "T62_XYZW\000"
2041 /* 1150 */ "KC1_172_XYZW\000"
2042 /* 1163 */ "T72_XYZW\000"
2043 /* 1172 */ "KC1_182_XYZW\000"
2044 /* 1185 */ "T82_XYZW\000"
2045 /* 1194 */ "T92_XYZW\000"
2046 /* 1203 */ "T2_XYZW\000"
2047 /* 1211 */ "T103_XYZW\000"
2048 /* 1221 */ "T113_XYZW\000"
2049 /* 1231 */ "T13_XYZW\000"
2050 /* 1240 */ "T123_XYZW\000"
2051 /* 1250 */ "T23_XYZW\000"
2052 /* 1259 */ "KC0_133_XYZW\000"
2053 /* 1272 */ "T33_XYZW\000"
2054 /* 1281 */ "KC0_143_XYZW\000"
2055 /* 1294 */ "T43_XYZW\000"
2056 /* 1303 */ "KC0_153_XYZW\000"
2057 /* 1316 */ "T53_XYZW\000"
2058 /* 1325 */ "KC1_163_XYZW\000"
2059 /* 1338 */ "T63_XYZW\000"
2060 /* 1347 */ "KC1_173_XYZW\000"
2061 /* 1360 */ "T73_XYZW\000"
2062 /* 1369 */ "KC1_183_XYZW\000"
2063 /* 1382 */ "T83_XYZW\000"
2064 /* 1391 */ "T93_XYZW\000"
2065 /* 1400 */ "T3_XYZW\000"
2066 /* 1408 */ "T104_XYZW\000"
2067 /* 1418 */ "T114_XYZW\000"
2068 /* 1428 */ "T14_XYZW\000"
2069 /* 1437 */ "T124_XYZW\000"
2070 /* 1447 */ "T24_XYZW\000"
2071 /* 1456 */ "KC0_134_XYZW\000"
2072 /* 1469 */ "T34_XYZW\000"
2073 /* 1478 */ "KC0_144_XYZW\000"
2074 /* 1491 */ "T44_XYZW\000"
2075 /* 1500 */ "KC0_154_XYZW\000"
2076 /* 1513 */ "T54_XYZW\000"
2077 /* 1522 */ "KC1_164_XYZW\000"
2078 /* 1535 */ "T64_XYZW\000"
2079 /* 1544 */ "KC1_174_XYZW\000"
2080 /* 1557 */ "T74_XYZW\000"
2081 /* 1566 */ "KC1_184_XYZW\000"
2082 /* 1579 */ "T84_XYZW\000"
2083 /* 1588 */ "T94_XYZW\000"
2084 /* 1597 */ "T4_XYZW\000"
2085 /* 1605 */ "T105_XYZW\000"
2086 /* 1615 */ "T115_XYZW\000"
2087 /* 1625 */ "T15_XYZW\000"
2088 /* 1634 */ "T125_XYZW\000"
2089 /* 1644 */ "T25_XYZW\000"
2090 /* 1653 */ "KC0_135_XYZW\000"
2091 /* 1666 */ "T35_XYZW\000"
2092 /* 1675 */ "KC0_145_XYZW\000"
2093 /* 1688 */ "T45_XYZW\000"
2094 /* 1697 */ "KC0_155_XYZW\000"
2095 /* 1710 */ "T55_XYZW\000"
2096 /* 1719 */ "KC1_165_XYZW\000"
2097 /* 1732 */ "T65_XYZW\000"
2098 /* 1741 */ "KC1_175_XYZW\000"
2099 /* 1754 */ "T75_XYZW\000"
2100 /* 1763 */ "KC1_185_XYZW\000"
2101 /* 1776 */ "T85_XYZW\000"
2102 /* 1785 */ "T95_XYZW\000"
2103 /* 1794 */ "T5_XYZW\000"
2104 /* 1802 */ "T106_XYZW\000"
2105 /* 1812 */ "T116_XYZW\000"
2106 /* 1822 */ "T16_XYZW\000"
2107 /* 1831 */ "T126_XYZW\000"
2108 /* 1841 */ "T26_XYZW\000"
2109 /* 1850 */ "KC0_136_XYZW\000"
2110 /* 1863 */ "T36_XYZW\000"
2111 /* 1872 */ "KC0_146_XYZW\000"
2112 /* 1885 */ "T46_XYZW\000"
2113 /* 1894 */ "KC0_156_XYZW\000"
2114 /* 1907 */ "T56_XYZW\000"
2115 /* 1916 */ "KC1_166_XYZW\000"
2116 /* 1929 */ "T66_XYZW\000"
2117 /* 1938 */ "KC1_176_XYZW\000"
2118 /* 1951 */ "T76_XYZW\000"
2119 /* 1960 */ "KC1_186_XYZW\000"
2120 /* 1973 */ "T86_XYZW\000"
2121 /* 1982 */ "T96_XYZW\000"
2122 /* 1991 */ "T6_XYZW\000"
2123 /* 1999 */ "T107_XYZW\000"
2124 /* 2009 */ "T117_XYZW\000"
2125 /* 2019 */ "T17_XYZW\000"
2126 /* 2028 */ "T127_XYZW\000"
2127 /* 2038 */ "T27_XYZW\000"
2128 /* 2047 */ "KC0_137_XYZW\000"
2129 /* 2060 */ "T37_XYZW\000"
2130 /* 2069 */ "KC0_147_XYZW\000"
2131 /* 2082 */ "T47_XYZW\000"
2132 /* 2091 */ "KC0_157_XYZW\000"
2133 /* 2104 */ "T57_XYZW\000"
2134 /* 2113 */ "KC1_167_XYZW\000"
2135 /* 2126 */ "T67_XYZW\000"
2136 /* 2135 */ "KC1_177_XYZW\000"
2137 /* 2148 */ "T77_XYZW\000"
2138 /* 2157 */ "KC1_187_XYZW\000"
2139 /* 2170 */ "T87_XYZW\000"
2140 /* 2179 */ "T97_XYZW\000"
2141 /* 2188 */ "T7_XYZW\000"
2142 /* 2196 */ "T108_XYZW\000"
2143 /* 2206 */ "T118_XYZW\000"
2144 /* 2216 */ "T18_XYZW\000"
2145 /* 2225 */ "KC0_128_XYZW\000"
2146 /* 2238 */ "T28_XYZW\000"
2147 /* 2247 */ "KC0_138_XYZW\000"
2148 /* 2260 */ "T38_XYZW\000"
2149 /* 2269 */ "KC0_148_XYZW\000"
2150 /* 2282 */ "T48_XYZW\000"
2151 /* 2291 */ "KC0_158_XYZW\000"
2152 /* 2304 */ "T58_XYZW\000"
2153 /* 2313 */ "KC1_168_XYZW\000"
2154 /* 2326 */ "T68_XYZW\000"
2155 /* 2335 */ "KC1_178_XYZW\000"
2156 /* 2348 */ "T78_XYZW\000"
2157 /* 2357 */ "KC1_188_XYZW\000"
2158 /* 2370 */ "T88_XYZW\000"
2159 /* 2379 */ "T98_XYZW\000"
2160 /* 2388 */ "T8_XYZW\000"
2161 /* 2396 */ "T109_XYZW\000"
2162 /* 2406 */ "T119_XYZW\000"
2163 /* 2416 */ "T19_XYZW\000"
2164 /* 2425 */ "KC0_129_XYZW\000"
2165 /* 2438 */ "T29_XYZW\000"
2166 /* 2447 */ "KC0_139_XYZW\000"
2167 /* 2460 */ "T39_XYZW\000"
2168 /* 2469 */ "KC0_149_XYZW\000"
2169 /* 2482 */ "T49_XYZW\000"
2170 /* 2491 */ "KC0_159_XYZW\000"
2171 /* 2504 */ "T59_XYZW\000"
2172 /* 2513 */ "KC1_169_XYZW\000"
2173 /* 2526 */ "T69_XYZW\000"
2174 /* 2535 */ "KC1_179_XYZW\000"
2175 /* 2548 */ "T79_XYZW\000"
2176 /* 2557 */ "KC1_189_XYZW\000"
2177 /* 2570 */ "T89_XYZW\000"
2178 /* 2579 */ "T99_XYZW\000"
2179 /* 2588 */ "T9_XYZW\000"
2180 /* 2596 */ "T100_W\000"
2181 /* 2603 */ "Addr100_W\000"
2182 /* 2613 */ "T110_W\000"
2183 /* 2620 */ "Addr110_W\000"
2184 /* 2630 */ "T10_W\000"
2185 /* 2636 */ "Addr10_W\000"
2186 /* 2645 */ "T120_W\000"
2187 /* 2652 */ "Addr120_W\000"
2188 /* 2662 */ "T20_W\000"
2189 /* 2668 */ "Addr20_W\000"
2190 /* 2677 */ "KC0_130_W\000"
2191 /* 2687 */ "T30_W\000"
2192 /* 2693 */ "Addr30_W\000"
2193 /* 2702 */ "KC0_140_W\000"
2194 /* 2712 */ "T40_W\000"
2195 /* 2718 */ "Addr40_W\000"
2196 /* 2727 */ "KC0_150_W\000"
2197 /* 2737 */ "T50_W\000"
2198 /* 2743 */ "Addr50_W\000"
2199 /* 2752 */ "KC1_160_W\000"
2200 /* 2762 */ "T60_W\000"
2201 /* 2768 */ "Addr60_W\000"
2202 /* 2777 */ "KC1_170_W\000"
2203 /* 2787 */ "T70_W\000"
2204 /* 2793 */ "Addr70_W\000"
2205 /* 2802 */ "KC1_180_W\000"
2206 /* 2812 */ "T80_W\000"
2207 /* 2818 */ "Addr80_W\000"
2208 /* 2827 */ "KC1_190_W\000"
2209 /* 2837 */ "T90_W\000"
2210 /* 2843 */ "Addr90_W\000"
2211 /* 2852 */ "T0_W\000"
2212 /* 2857 */ "Addr0_W\000"
2213 /* 2865 */ "T101_W\000"
2214 /* 2872 */ "Addr101_W\000"
2215 /* 2882 */ "V01_W\000"
2216 /* 2888 */ "T111_W\000"
2217 /* 2895 */ "Addr111_W\000"
2218 /* 2905 */ "T11_W\000"
2219 /* 2911 */ "Addr11_W\000"
2220 /* 2920 */ "T121_W\000"
2221 /* 2927 */ "Addr121_W\000"
2222 /* 2937 */ "T21_W\000"
2223 /* 2943 */ "Addr21_W\000"
2224 /* 2952 */ "KC0_131_W\000"
2225 /* 2962 */ "T31_W\000"
2226 /* 2968 */ "Addr31_W\000"
2227 /* 2977 */ "KC0_141_W\000"
2228 /* 2987 */ "T41_W\000"
2229 /* 2993 */ "Addr41_W\000"
2230 /* 3002 */ "KC0_151_W\000"
2231 /* 3012 */ "T51_W\000"
2232 /* 3018 */ "Addr51_W\000"
2233 /* 3027 */ "KC1_161_W\000"
2234 /* 3037 */ "T61_W\000"
2235 /* 3043 */ "Addr61_W\000"
2236 /* 3052 */ "KC1_171_W\000"
2237 /* 3062 */ "T71_W\000"
2238 /* 3068 */ "Addr71_W\000"
2239 /* 3077 */ "KC1_181_W\000"
2240 /* 3087 */ "T81_W\000"
2241 /* 3093 */ "Addr81_W\000"
2242 /* 3102 */ "KC1_191_W\000"
2243 /* 3112 */ "T91_W\000"
2244 /* 3118 */ "Addr91_W\000"
2245 /* 3127 */ "T1_W\000"
2246 /* 3132 */ "Addr1_W\000"
2247 /* 3140 */ "T102_W\000"
2248 /* 3147 */ "Addr102_W\000"
2249 /* 3157 */ "T112_W\000"
2250 /* 3164 */ "Addr112_W\000"
2251 /* 3174 */ "T12_W\000"
2252 /* 3180 */ "Addr12_W\000"
2253 /* 3189 */ "T122_W\000"
2254 /* 3196 */ "Addr122_W\000"
2255 /* 3206 */ "T22_W\000"
2256 /* 3212 */ "Addr22_W\000"
2257 /* 3221 */ "KC0_132_W\000"
2258 /* 3231 */ "T32_W\000"
2259 /* 3237 */ "Addr32_W\000"
2260 /* 3246 */ "KC0_142_W\000"
2261 /* 3256 */ "T42_W\000"
2262 /* 3262 */ "Addr42_W\000"
2263 /* 3271 */ "KC0_152_W\000"
2264 /* 3281 */ "T52_W\000"
2265 /* 3287 */ "Addr52_W\000"
2266 /* 3296 */ "KC1_162_W\000"
2267 /* 3306 */ "T62_W\000"
2268 /* 3312 */ "Addr62_W\000"
2269 /* 3321 */ "KC1_172_W\000"
2270 /* 3331 */ "T72_W\000"
2271 /* 3337 */ "Addr72_W\000"
2272 /* 3346 */ "KC1_182_W\000"
2273 /* 3356 */ "T82_W\000"
2274 /* 3362 */ "Addr82_W\000"
2275 /* 3371 */ "T92_W\000"
2276 /* 3377 */ "Addr92_W\000"
2277 /* 3386 */ "T2_W\000"
2278 /* 3391 */ "Addr2_W\000"
2279 /* 3399 */ "T103_W\000"
2280 /* 3406 */ "Addr103_W\000"
2281 /* 3416 */ "T113_W\000"
2282 /* 3423 */ "Addr113_W\000"
2283 /* 3433 */ "T13_W\000"
2284 /* 3439 */ "Addr13_W\000"
2285 /* 3448 */ "V0123_W\000"
2286 /* 3456 */ "T123_W\000"
2287 /* 3463 */ "Addr123_W\000"
2288 /* 3473 */ "T23_W\000"
2289 /* 3479 */ "V23_W\000"
2290 /* 3485 */ "Addr23_W\000"
2291 /* 3494 */ "KC0_133_W\000"
2292 /* 3504 */ "T33_W\000"
2293 /* 3510 */ "Addr33_W\000"
2294 /* 3519 */ "KC0_143_W\000"
2295 /* 3529 */ "T43_W\000"
2296 /* 3535 */ "Addr43_W\000"
2297 /* 3544 */ "KC0_153_W\000"
2298 /* 3554 */ "T53_W\000"
2299 /* 3560 */ "Addr53_W\000"
2300 /* 3569 */ "KC1_163_W\000"
2301 /* 3579 */ "T63_W\000"
2302 /* 3585 */ "Addr63_W\000"
2303 /* 3594 */ "KC1_173_W\000"
2304 /* 3604 */ "T73_W\000"
2305 /* 3610 */ "Addr73_W\000"
2306 /* 3619 */ "KC1_183_W\000"
2307 /* 3629 */ "T83_W\000"
2308 /* 3635 */ "Addr83_W\000"
2309 /* 3644 */ "T93_W\000"
2310 /* 3650 */ "Addr93_W\000"
2311 /* 3659 */ "T3_W\000"
2312 /* 3664 */ "Addr3_W\000"
2313 /* 3672 */ "T104_W\000"
2314 /* 3679 */ "Addr104_W\000"
2315 /* 3689 */ "T114_W\000"
2316 /* 3696 */ "Addr114_W\000"
2317 /* 3706 */ "T14_W\000"
2318 /* 3712 */ "Addr14_W\000"
2319 /* 3721 */ "T124_W\000"
2320 /* 3728 */ "Addr124_W\000"
2321 /* 3738 */ "T24_W\000"
2322 /* 3744 */ "Addr24_W\000"
2323 /* 3753 */ "KC0_134_W\000"
2324 /* 3763 */ "T34_W\000"
2325 /* 3769 */ "Addr34_W\000"
2326 /* 3778 */ "KC0_144_W\000"
2327 /* 3788 */ "T44_W\000"
2328 /* 3794 */ "Addr44_W\000"
2329 /* 3803 */ "KC0_154_W\000"
2330 /* 3813 */ "T54_W\000"
2331 /* 3819 */ "Addr54_W\000"
2332 /* 3828 */ "KC1_164_W\000"
2333 /* 3838 */ "T64_W\000"
2334 /* 3844 */ "Addr64_W\000"
2335 /* 3853 */ "KC1_174_W\000"
2336 /* 3863 */ "T74_W\000"
2337 /* 3869 */ "Addr74_W\000"
2338 /* 3878 */ "KC1_184_W\000"
2339 /* 3888 */ "T84_W\000"
2340 /* 3894 */ "Addr84_W\000"
2341 /* 3903 */ "T94_W\000"
2342 /* 3909 */ "Addr94_W\000"
2343 /* 3918 */ "T4_W\000"
2344 /* 3923 */ "Addr4_W\000"
2345 /* 3931 */ "T105_W\000"
2346 /* 3938 */ "Addr105_W\000"
2347 /* 3948 */ "T115_W\000"
2348 /* 3955 */ "Addr115_W\000"
2349 /* 3965 */ "T15_W\000"
2350 /* 3971 */ "Addr15_W\000"
2351 /* 3980 */ "T125_W\000"
2352 /* 3987 */ "Addr125_W\000"
2353 /* 3997 */ "T25_W\000"
2354 /* 4003 */ "Addr25_W\000"
2355 /* 4012 */ "KC0_135_W\000"
2356 /* 4022 */ "T35_W\000"
2357 /* 4028 */ "Addr35_W\000"
2358 /* 4037 */ "KC0_145_W\000"
2359 /* 4047 */ "T45_W\000"
2360 /* 4053 */ "Addr45_W\000"
2361 /* 4062 */ "KC0_155_W\000"
2362 /* 4072 */ "T55_W\000"
2363 /* 4078 */ "Addr55_W\000"
2364 /* 4087 */ "KC1_165_W\000"
2365 /* 4097 */ "T65_W\000"
2366 /* 4103 */ "Addr65_W\000"
2367 /* 4112 */ "KC1_175_W\000"
2368 /* 4122 */ "T75_W\000"
2369 /* 4128 */ "Addr75_W\000"
2370 /* 4137 */ "KC1_185_W\000"
2371 /* 4147 */ "T85_W\000"
2372 /* 4153 */ "Addr85_W\000"
2373 /* 4162 */ "T95_W\000"
2374 /* 4168 */ "Addr95_W\000"
2375 /* 4177 */ "T5_W\000"
2376 /* 4182 */ "Addr5_W\000"
2377 /* 4190 */ "T106_W\000"
2378 /* 4197 */ "Addr106_W\000"
2379 /* 4207 */ "T116_W\000"
2380 /* 4214 */ "Addr116_W\000"
2381 /* 4224 */ "T16_W\000"
2382 /* 4230 */ "Addr16_W\000"
2383 /* 4239 */ "T126_W\000"
2384 /* 4246 */ "Addr126_W\000"
2385 /* 4256 */ "T26_W\000"
2386 /* 4262 */ "Addr26_W\000"
2387 /* 4271 */ "KC0_136_W\000"
2388 /* 4281 */ "T36_W\000"
2389 /* 4287 */ "Addr36_W\000"
2390 /* 4296 */ "KC0_146_W\000"
2391 /* 4306 */ "T46_W\000"
2392 /* 4312 */ "Addr46_W\000"
2393 /* 4321 */ "KC0_156_W\000"
2394 /* 4331 */ "T56_W\000"
2395 /* 4337 */ "Addr56_W\000"
2396 /* 4346 */ "KC1_166_W\000"
2397 /* 4356 */ "T66_W\000"
2398 /* 4362 */ "Addr66_W\000"
2399 /* 4371 */ "KC1_176_W\000"
2400 /* 4381 */ "T76_W\000"
2401 /* 4387 */ "Addr76_W\000"
2402 /* 4396 */ "KC1_186_W\000"
2403 /* 4406 */ "T86_W\000"
2404 /* 4412 */ "Addr86_W\000"
2405 /* 4421 */ "T96_W\000"
2406 /* 4427 */ "Addr96_W\000"
2407 /* 4436 */ "T6_W\000"
2408 /* 4441 */ "Addr6_W\000"
2409 /* 4449 */ "T107_W\000"
2410 /* 4456 */ "Addr107_W\000"
2411 /* 4466 */ "T117_W\000"
2412 /* 4473 */ "Addr117_W\000"
2413 /* 4483 */ "T17_W\000"
2414 /* 4489 */ "Addr17_W\000"
2415 /* 4498 */ "T127_W\000"
2416 /* 4505 */ "Addr127_W\000"
2417 /* 4515 */ "T27_W\000"
2418 /* 4521 */ "Addr27_W\000"
2419 /* 4530 */ "KC0_137_W\000"
2420 /* 4540 */ "T37_W\000"
2421 /* 4546 */ "Addr37_W\000"
2422 /* 4555 */ "KC0_147_W\000"
2423 /* 4565 */ "T47_W\000"
2424 /* 4571 */ "Addr47_W\000"
2425 /* 4580 */ "KC0_157_W\000"
2426 /* 4590 */ "T57_W\000"
2427 /* 4596 */ "Addr57_W\000"
2428 /* 4605 */ "KC1_167_W\000"
2429 /* 4615 */ "T67_W\000"
2430 /* 4621 */ "Addr67_W\000"
2431 /* 4630 */ "KC1_177_W\000"
2432 /* 4640 */ "T77_W\000"
2433 /* 4646 */ "Addr77_W\000"
2434 /* 4655 */ "KC1_187_W\000"
2435 /* 4665 */ "T87_W\000"
2436 /* 4671 */ "Addr87_W\000"
2437 /* 4680 */ "T97_W\000"
2438 /* 4686 */ "Addr97_W\000"
2439 /* 4695 */ "T7_W\000"
2440 /* 4700 */ "Addr7_W\000"
2441 /* 4708 */ "T108_W\000"
2442 /* 4715 */ "Addr108_W\000"
2443 /* 4725 */ "T118_W\000"
2444 /* 4732 */ "Addr118_W\000"
2445 /* 4742 */ "T18_W\000"
2446 /* 4748 */ "Addr18_W\000"
2447 /* 4757 */ "KC0_128_W\000"
2448 /* 4767 */ "T28_W\000"
2449 /* 4773 */ "Addr28_W\000"
2450 /* 4782 */ "KC0_138_W\000"
2451 /* 4792 */ "T38_W\000"
2452 /* 4798 */ "Addr38_W\000"
2453 /* 4807 */ "KC0_148_W\000"
2454 /* 4817 */ "T48_W\000"
2455 /* 4823 */ "Addr48_W\000"
2456 /* 4832 */ "KC0_158_W\000"
2457 /* 4842 */ "T58_W\000"
2458 /* 4848 */ "Addr58_W\000"
2459 /* 4857 */ "KC1_168_W\000"
2460 /* 4867 */ "T68_W\000"
2461 /* 4873 */ "Addr68_W\000"
2462 /* 4882 */ "KC1_178_W\000"
2463 /* 4892 */ "T78_W\000"
2464 /* 4898 */ "Addr78_W\000"
2465 /* 4907 */ "KC1_188_W\000"
2466 /* 4917 */ "T88_W\000"
2467 /* 4923 */ "Addr88_W\000"
2468 /* 4932 */ "T98_W\000"
2469 /* 4938 */ "Addr98_W\000"
2470 /* 4947 */ "T8_W\000"
2471 /* 4952 */ "Addr8_W\000"
2472 /* 4960 */ "T109_W\000"
2473 /* 4967 */ "Addr109_W\000"
2474 /* 4977 */ "T119_W\000"
2475 /* 4984 */ "Addr119_W\000"
2476 /* 4994 */ "T19_W\000"
2477 /* 5000 */ "Addr19_W\000"
2478 /* 5009 */ "KC0_129_W\000"
2479 /* 5019 */ "T29_W\000"
2480 /* 5025 */ "Addr29_W\000"
2481 /* 5034 */ "KC0_139_W\000"
2482 /* 5044 */ "T39_W\000"
2483 /* 5050 */ "Addr39_W\000"
2484 /* 5059 */ "KC0_149_W\000"
2485 /* 5069 */ "T49_W\000"
2486 /* 5075 */ "Addr49_W\000"
2487 /* 5084 */ "KC0_159_W\000"
2488 /* 5094 */ "T59_W\000"
2489 /* 5100 */ "Addr59_W\000"
2490 /* 5109 */ "KC1_169_W\000"
2491 /* 5119 */ "T69_W\000"
2492 /* 5125 */ "Addr69_W\000"
2493 /* 5134 */ "KC1_179_W\000"
2494 /* 5144 */ "T79_W\000"
2495 /* 5150 */ "Addr79_W\000"
2496 /* 5159 */ "KC1_189_W\000"
2497 /* 5169 */ "T89_W\000"
2498 /* 5175 */ "Addr89_W\000"
2499 /* 5184 */ "T99_W\000"
2500 /* 5190 */ "Addr99_W\000"
2501 /* 5199 */ "T9_W\000"
2502 /* 5204 */ "Addr9_W\000"
2503 /* 5212 */ "ALU_LITERAL_W\000"
2504 /* 5226 */ "PV_W\000"
2505 /* 5231 */ "T100_X\000"
2506 /* 5238 */ "Addr100_X\000"
2507 /* 5248 */ "T110_X\000"
2508 /* 5255 */ "Addr110_X\000"
2509 /* 5265 */ "T10_X\000"
2510 /* 5271 */ "Addr10_X\000"
2511 /* 5280 */ "T120_X\000"
2512 /* 5287 */ "Addr120_X\000"
2513 /* 5297 */ "T20_X\000"
2514 /* 5303 */ "Addr20_X\000"
2515 /* 5312 */ "KC0_130_X\000"
2516 /* 5322 */ "T30_X\000"
2517 /* 5328 */ "Addr30_X\000"
2518 /* 5337 */ "KC0_140_X\000"
2519 /* 5347 */ "T40_X\000"
2520 /* 5353 */ "Addr40_X\000"
2521 /* 5362 */ "KC0_150_X\000"
2522 /* 5372 */ "T50_X\000"
2523 /* 5378 */ "Addr50_X\000"
2524 /* 5387 */ "KC1_160_X\000"
2525 /* 5397 */ "T60_X\000"
2526 /* 5403 */ "Addr60_X\000"
2527 /* 5412 */ "KC1_170_X\000"
2528 /* 5422 */ "T70_X\000"
2529 /* 5428 */ "Addr70_X\000"
2530 /* 5437 */ "KC1_180_X\000"
2531 /* 5447 */ "T80_X\000"
2532 /* 5453 */ "Addr80_X\000"
2533 /* 5462 */ "KC1_190_X\000"
2534 /* 5472 */ "T90_X\000"
2535 /* 5478 */ "Addr90_X\000"
2536 /* 5487 */ "T0_X\000"
2537 /* 5492 */ "Addr0_X\000"
2538 /* 5500 */ "T101_X\000"
2539 /* 5507 */ "Addr101_X\000"
2540 /* 5517 */ "V01_X\000"
2541 /* 5523 */ "T111_X\000"
2542 /* 5530 */ "Addr111_X\000"
2543 /* 5540 */ "T11_X\000"
2544 /* 5546 */ "Addr11_X\000"
2545 /* 5555 */ "T121_X\000"
2546 /* 5562 */ "Addr121_X\000"
2547 /* 5572 */ "T21_X\000"
2548 /* 5578 */ "Addr21_X\000"
2549 /* 5587 */ "KC0_131_X\000"
2550 /* 5597 */ "T31_X\000"
2551 /* 5603 */ "Addr31_X\000"
2552 /* 5612 */ "KC0_141_X\000"
2553 /* 5622 */ "T41_X\000"
2554 /* 5628 */ "Addr41_X\000"
2555 /* 5637 */ "KC0_151_X\000"
2556 /* 5647 */ "T51_X\000"
2557 /* 5653 */ "Addr51_X\000"
2558 /* 5662 */ "KC1_161_X\000"
2559 /* 5672 */ "T61_X\000"
2560 /* 5678 */ "Addr61_X\000"
2561 /* 5687 */ "KC1_171_X\000"
2562 /* 5697 */ "T71_X\000"
2563 /* 5703 */ "Addr71_X\000"
2564 /* 5712 */ "KC1_181_X\000"
2565 /* 5722 */ "T81_X\000"
2566 /* 5728 */ "Addr81_X\000"
2567 /* 5737 */ "KC1_191_X\000"
2568 /* 5747 */ "T91_X\000"
2569 /* 5753 */ "Addr91_X\000"
2570 /* 5762 */ "T1_X\000"
2571 /* 5767 */ "Addr1_X\000"
2572 /* 5775 */ "T102_X\000"
2573 /* 5782 */ "Addr102_X\000"
2574 /* 5792 */ "T112_X\000"
2575 /* 5799 */ "Addr112_X\000"
2576 /* 5809 */ "T12_X\000"
2577 /* 5815 */ "Addr12_X\000"
2578 /* 5824 */ "T122_X\000"
2579 /* 5831 */ "Addr122_X\000"
2580 /* 5841 */ "T22_X\000"
2581 /* 5847 */ "Addr22_X\000"
2582 /* 5856 */ "KC0_132_X\000"
2583 /* 5866 */ "T32_X\000"
2584 /* 5872 */ "Addr32_X\000"
2585 /* 5881 */ "KC0_142_X\000"
2586 /* 5891 */ "T42_X\000"
2587 /* 5897 */ "Addr42_X\000"
2588 /* 5906 */ "KC0_152_X\000"
2589 /* 5916 */ "T52_X\000"
2590 /* 5922 */ "Addr52_X\000"
2591 /* 5931 */ "KC1_162_X\000"
2592 /* 5941 */ "T62_X\000"
2593 /* 5947 */ "Addr62_X\000"
2594 /* 5956 */ "KC1_172_X\000"
2595 /* 5966 */ "T72_X\000"
2596 /* 5972 */ "Addr72_X\000"
2597 /* 5981 */ "KC1_182_X\000"
2598 /* 5991 */ "T82_X\000"
2599 /* 5997 */ "Addr82_X\000"
2600 /* 6006 */ "T92_X\000"
2601 /* 6012 */ "Addr92_X\000"
2602 /* 6021 */ "T2_X\000"
2603 /* 6026 */ "Addr2_X\000"
2604 /* 6034 */ "T103_X\000"
2605 /* 6041 */ "Addr103_X\000"
2606 /* 6051 */ "T113_X\000"
2607 /* 6058 */ "Addr113_X\000"
2608 /* 6068 */ "T13_X\000"
2609 /* 6074 */ "Addr13_X\000"
2610 /* 6083 */ "V0123_X\000"
2611 /* 6091 */ "T123_X\000"
2612 /* 6098 */ "Addr123_X\000"
2613 /* 6108 */ "T23_X\000"
2614 /* 6114 */ "V23_X\000"
2615 /* 6120 */ "Addr23_X\000"
2616 /* 6129 */ "KC0_133_X\000"
2617 /* 6139 */ "T33_X\000"
2618 /* 6145 */ "Addr33_X\000"
2619 /* 6154 */ "KC0_143_X\000"
2620 /* 6164 */ "T43_X\000"
2621 /* 6170 */ "Addr43_X\000"
2622 /* 6179 */ "KC0_153_X\000"
2623 /* 6189 */ "T53_X\000"
2624 /* 6195 */ "Addr53_X\000"
2625 /* 6204 */ "KC1_163_X\000"
2626 /* 6214 */ "T63_X\000"
2627 /* 6220 */ "Addr63_X\000"
2628 /* 6229 */ "KC1_173_X\000"
2629 /* 6239 */ "T73_X\000"
2630 /* 6245 */ "Addr73_X\000"
2631 /* 6254 */ "KC1_183_X\000"
2632 /* 6264 */ "T83_X\000"
2633 /* 6270 */ "Addr83_X\000"
2634 /* 6279 */ "T93_X\000"
2635 /* 6285 */ "Addr93_X\000"
2636 /* 6294 */ "T3_X\000"
2637 /* 6299 */ "Addr3_X\000"
2638 /* 6307 */ "T104_X\000"
2639 /* 6314 */ "Addr104_X\000"
2640 /* 6324 */ "T114_X\000"
2641 /* 6331 */ "Addr114_X\000"
2642 /* 6341 */ "T14_X\000"
2643 /* 6347 */ "Addr14_X\000"
2644 /* 6356 */ "T124_X\000"
2645 /* 6363 */ "Addr124_X\000"
2646 /* 6373 */ "T24_X\000"
2647 /* 6379 */ "Addr24_X\000"
2648 /* 6388 */ "KC0_134_X\000"
2649 /* 6398 */ "T34_X\000"
2650 /* 6404 */ "Addr34_X\000"
2651 /* 6413 */ "KC0_144_X\000"
2652 /* 6423 */ "T44_X\000"
2653 /* 6429 */ "Addr44_X\000"
2654 /* 6438 */ "KC0_154_X\000"
2655 /* 6448 */ "T54_X\000"
2656 /* 6454 */ "Addr54_X\000"
2657 /* 6463 */ "KC1_164_X\000"
2658 /* 6473 */ "T64_X\000"
2659 /* 6479 */ "Addr64_X\000"
2660 /* 6488 */ "KC1_174_X\000"
2661 /* 6498 */ "T74_X\000"
2662 /* 6504 */ "Addr74_X\000"
2663 /* 6513 */ "KC1_184_X\000"
2664 /* 6523 */ "T84_X\000"
2665 /* 6529 */ "Addr84_X\000"
2666 /* 6538 */ "T94_X\000"
2667 /* 6544 */ "Addr94_X\000"
2668 /* 6553 */ "T4_X\000"
2669 /* 6558 */ "Addr4_X\000"
2670 /* 6566 */ "T105_X\000"
2671 /* 6573 */ "Addr105_X\000"
2672 /* 6583 */ "T115_X\000"
2673 /* 6590 */ "Addr115_X\000"
2674 /* 6600 */ "T15_X\000"
2675 /* 6606 */ "Addr15_X\000"
2676 /* 6615 */ "T125_X\000"
2677 /* 6622 */ "Addr125_X\000"
2678 /* 6632 */ "T25_X\000"
2679 /* 6638 */ "Addr25_X\000"
2680 /* 6647 */ "KC0_135_X\000"
2681 /* 6657 */ "T35_X\000"
2682 /* 6663 */ "Addr35_X\000"
2683 /* 6672 */ "KC0_145_X\000"
2684 /* 6682 */ "T45_X\000"
2685 /* 6688 */ "Addr45_X\000"
2686 /* 6697 */ "KC0_155_X\000"
2687 /* 6707 */ "T55_X\000"
2688 /* 6713 */ "Addr55_X\000"
2689 /* 6722 */ "KC1_165_X\000"
2690 /* 6732 */ "T65_X\000"
2691 /* 6738 */ "Addr65_X\000"
2692 /* 6747 */ "KC1_175_X\000"
2693 /* 6757 */ "T75_X\000"
2694 /* 6763 */ "Addr75_X\000"
2695 /* 6772 */ "KC1_185_X\000"
2696 /* 6782 */ "T85_X\000"
2697 /* 6788 */ "Addr85_X\000"
2698 /* 6797 */ "T95_X\000"
2699 /* 6803 */ "Addr95_X\000"
2700 /* 6812 */ "T5_X\000"
2701 /* 6817 */ "Addr5_X\000"
2702 /* 6825 */ "T106_X\000"
2703 /* 6832 */ "Addr106_X\000"
2704 /* 6842 */ "T116_X\000"
2705 /* 6849 */ "Addr116_X\000"
2706 /* 6859 */ "T16_X\000"
2707 /* 6865 */ "Addr16_X\000"
2708 /* 6874 */ "T126_X\000"
2709 /* 6881 */ "Addr126_X\000"
2710 /* 6891 */ "T26_X\000"
2711 /* 6897 */ "Addr26_X\000"
2712 /* 6906 */ "KC0_136_X\000"
2713 /* 6916 */ "T36_X\000"
2714 /* 6922 */ "Addr36_X\000"
2715 /* 6931 */ "KC0_146_X\000"
2716 /* 6941 */ "T46_X\000"
2717 /* 6947 */ "Addr46_X\000"
2718 /* 6956 */ "KC0_156_X\000"
2719 /* 6966 */ "T56_X\000"
2720 /* 6972 */ "Addr56_X\000"
2721 /* 6981 */ "KC1_166_X\000"
2722 /* 6991 */ "T66_X\000"
2723 /* 6997 */ "Addr66_X\000"
2724 /* 7006 */ "KC1_176_X\000"
2725 /* 7016 */ "T76_X\000"
2726 /* 7022 */ "Addr76_X\000"
2727 /* 7031 */ "KC1_186_X\000"
2728 /* 7041 */ "T86_X\000"
2729 /* 7047 */ "Addr86_X\000"
2730 /* 7056 */ "T96_X\000"
2731 /* 7062 */ "Addr96_X\000"
2732 /* 7071 */ "T6_X\000"
2733 /* 7076 */ "Addr6_X\000"
2734 /* 7084 */ "T107_X\000"
2735 /* 7091 */ "Addr107_X\000"
2736 /* 7101 */ "T117_X\000"
2737 /* 7108 */ "Addr117_X\000"
2738 /* 7118 */ "T17_X\000"
2739 /* 7124 */ "Addr17_X\000"
2740 /* 7133 */ "T127_X\000"
2741 /* 7140 */ "Addr127_X\000"
2742 /* 7150 */ "T27_X\000"
2743 /* 7156 */ "Addr27_X\000"
2744 /* 7165 */ "KC0_137_X\000"
2745 /* 7175 */ "T37_X\000"
2746 /* 7181 */ "Addr37_X\000"
2747 /* 7190 */ "KC0_147_X\000"
2748 /* 7200 */ "T47_X\000"
2749 /* 7206 */ "Addr47_X\000"
2750 /* 7215 */ "KC0_157_X\000"
2751 /* 7225 */ "T57_X\000"
2752 /* 7231 */ "Addr57_X\000"
2753 /* 7240 */ "KC1_167_X\000"
2754 /* 7250 */ "T67_X\000"
2755 /* 7256 */ "Addr67_X\000"
2756 /* 7265 */ "KC1_177_X\000"
2757 /* 7275 */ "T77_X\000"
2758 /* 7281 */ "Addr77_X\000"
2759 /* 7290 */ "KC1_187_X\000"
2760 /* 7300 */ "T87_X\000"
2761 /* 7306 */ "Addr87_X\000"
2762 /* 7315 */ "T97_X\000"
2763 /* 7321 */ "Addr97_X\000"
2764 /* 7330 */ "T7_X\000"
2765 /* 7335 */ "Addr7_X\000"
2766 /* 7343 */ "T108_X\000"
2767 /* 7350 */ "Addr108_X\000"
2768 /* 7360 */ "T118_X\000"
2769 /* 7367 */ "Addr118_X\000"
2770 /* 7377 */ "T18_X\000"
2771 /* 7383 */ "Addr18_X\000"
2772 /* 7392 */ "KC0_128_X\000"
2773 /* 7402 */ "T28_X\000"
2774 /* 7408 */ "Addr28_X\000"
2775 /* 7417 */ "KC0_138_X\000"
2776 /* 7427 */ "T38_X\000"
2777 /* 7433 */ "Addr38_X\000"
2778 /* 7442 */ "KC0_148_X\000"
2779 /* 7452 */ "T48_X\000"
2780 /* 7458 */ "Addr48_X\000"
2781 /* 7467 */ "KC0_158_X\000"
2782 /* 7477 */ "T58_X\000"
2783 /* 7483 */ "Addr58_X\000"
2784 /* 7492 */ "KC1_168_X\000"
2785 /* 7502 */ "T68_X\000"
2786 /* 7508 */ "Addr68_X\000"
2787 /* 7517 */ "KC1_178_X\000"
2788 /* 7527 */ "T78_X\000"
2789 /* 7533 */ "Addr78_X\000"
2790 /* 7542 */ "KC1_188_X\000"
2791 /* 7552 */ "T88_X\000"
2792 /* 7558 */ "Addr88_X\000"
2793 /* 7567 */ "T98_X\000"
2794 /* 7573 */ "Addr98_X\000"
2795 /* 7582 */ "T8_X\000"
2796 /* 7587 */ "Addr8_X\000"
2797 /* 7595 */ "T109_X\000"
2798 /* 7602 */ "Addr109_X\000"
2799 /* 7612 */ "T119_X\000"
2800 /* 7619 */ "Addr119_X\000"
2801 /* 7629 */ "T19_X\000"
2802 /* 7635 */ "Addr19_X\000"
2803 /* 7644 */ "KC0_129_X\000"
2804 /* 7654 */ "T29_X\000"
2805 /* 7660 */ "Addr29_X\000"
2806 /* 7669 */ "KC0_139_X\000"
2807 /* 7679 */ "T39_X\000"
2808 /* 7685 */ "Addr39_X\000"
2809 /* 7694 */ "KC0_149_X\000"
2810 /* 7704 */ "T49_X\000"
2811 /* 7710 */ "Addr49_X\000"
2812 /* 7719 */ "KC0_159_X\000"
2813 /* 7729 */ "T59_X\000"
2814 /* 7735 */ "Addr59_X\000"
2815 /* 7744 */ "KC1_169_X\000"
2816 /* 7754 */ "T69_X\000"
2817 /* 7760 */ "Addr69_X\000"
2818 /* 7769 */ "KC1_179_X\000"
2819 /* 7779 */ "T79_X\000"
2820 /* 7785 */ "Addr79_X\000"
2821 /* 7794 */ "KC1_189_X\000"
2822 /* 7804 */ "T89_X\000"
2823 /* 7810 */ "Addr89_X\000"
2824 /* 7819 */ "T99_X\000"
2825 /* 7825 */ "Addr99_X\000"
2826 /* 7834 */ "T9_X\000"
2827 /* 7839 */ "Addr9_X\000"
2828 /* 7847 */ "ALU_LITERAL_X\000"
2829 /* 7861 */ "AR_X\000"
2830 /* 7866 */ "PV_X\000"
2831 /* 7871 */ "T100_XY\000"
2832 /* 7879 */ "T110_XY\000"
2833 /* 7887 */ "T10_XY\000"
2834 /* 7894 */ "T120_XY\000"
2835 /* 7902 */ "T20_XY\000"
2836 /* 7909 */ "T30_XY\000"
2837 /* 7916 */ "T40_XY\000"
2838 /* 7923 */ "T50_XY\000"
2839 /* 7930 */ "T60_XY\000"
2840 /* 7937 */ "T70_XY\000"
2841 /* 7944 */ "T80_XY\000"
2842 /* 7951 */ "T90_XY\000"
2843 /* 7958 */ "T0_XY\000"
2844 /* 7964 */ "T101_XY\000"
2845 /* 7972 */ "T111_XY\000"
2846 /* 7980 */ "T11_XY\000"
2847 /* 7987 */ "T121_XY\000"
2848 /* 7995 */ "T21_XY\000"
2849 /* 8002 */ "T31_XY\000"
2850 /* 8009 */ "T41_XY\000"
2851 /* 8016 */ "T51_XY\000"
2852 /* 8023 */ "T61_XY\000"
2853 /* 8030 */ "T71_XY\000"
2854 /* 8037 */ "T81_XY\000"
2855 /* 8044 */ "T91_XY\000"
2856 /* 8051 */ "T1_XY\000"
2857 /* 8057 */ "T102_XY\000"
2858 /* 8065 */ "T112_XY\000"
2859 /* 8073 */ "T12_XY\000"
2860 /* 8080 */ "T122_XY\000"
2861 /* 8088 */ "T22_XY\000"
2862 /* 8095 */ "T32_XY\000"
2863 /* 8102 */ "T42_XY\000"
2864 /* 8109 */ "T52_XY\000"
2865 /* 8116 */ "T62_XY\000"
2866 /* 8123 */ "T72_XY\000"
2867 /* 8130 */ "T82_XY\000"
2868 /* 8137 */ "T92_XY\000"
2869 /* 8144 */ "T2_XY\000"
2870 /* 8150 */ "T103_XY\000"
2871 /* 8158 */ "T113_XY\000"
2872 /* 8166 */ "T13_XY\000"
2873 /* 8173 */ "T123_XY\000"
2874 /* 8181 */ "T23_XY\000"
2875 /* 8188 */ "T33_XY\000"
2876 /* 8195 */ "T43_XY\000"
2877 /* 8202 */ "T53_XY\000"
2878 /* 8209 */ "T63_XY\000"
2879 /* 8216 */ "T73_XY\000"
2880 /* 8223 */ "T83_XY\000"
2881 /* 8230 */ "T93_XY\000"
2882 /* 8237 */ "T3_XY\000"
2883 /* 8243 */ "T104_XY\000"
2884 /* 8251 */ "T114_XY\000"
2885 /* 8259 */ "T14_XY\000"
2886 /* 8266 */ "T124_XY\000"
2887 /* 8274 */ "T24_XY\000"
2888 /* 8281 */ "T34_XY\000"
2889 /* 8288 */ "T44_XY\000"
2890 /* 8295 */ "T54_XY\000"
2891 /* 8302 */ "T64_XY\000"
2892 /* 8309 */ "T74_XY\000"
2893 /* 8316 */ "T84_XY\000"
2894 /* 8323 */ "T94_XY\000"
2895 /* 8330 */ "T4_XY\000"
2896 /* 8336 */ "T105_XY\000"
2897 /* 8344 */ "T115_XY\000"
2898 /* 8352 */ "T15_XY\000"
2899 /* 8359 */ "T125_XY\000"
2900 /* 8367 */ "T25_XY\000"
2901 /* 8374 */ "T35_XY\000"
2902 /* 8381 */ "T45_XY\000"
2903 /* 8388 */ "T55_XY\000"
2904 /* 8395 */ "T65_XY\000"
2905 /* 8402 */ "T75_XY\000"
2906 /* 8409 */ "T85_XY\000"
2907 /* 8416 */ "T95_XY\000"
2908 /* 8423 */ "T5_XY\000"
2909 /* 8429 */ "T106_XY\000"
2910 /* 8437 */ "T116_XY\000"
2911 /* 8445 */ "T16_XY\000"
2912 /* 8452 */ "T126_XY\000"
2913 /* 8460 */ "T26_XY\000"
2914 /* 8467 */ "T36_XY\000"
2915 /* 8474 */ "T46_XY\000"
2916 /* 8481 */ "T56_XY\000"
2917 /* 8488 */ "T66_XY\000"
2918 /* 8495 */ "T76_XY\000"
2919 /* 8502 */ "T86_XY\000"
2920 /* 8509 */ "T96_XY\000"
2921 /* 8516 */ "T6_XY\000"
2922 /* 8522 */ "T107_XY\000"
2923 /* 8530 */ "T117_XY\000"
2924 /* 8538 */ "T17_XY\000"
2925 /* 8545 */ "T127_XY\000"
2926 /* 8553 */ "T27_XY\000"
2927 /* 8560 */ "T37_XY\000"
2928 /* 8567 */ "T47_XY\000"
2929 /* 8574 */ "T57_XY\000"
2930 /* 8581 */ "T67_XY\000"
2931 /* 8588 */ "T77_XY\000"
2932 /* 8595 */ "T87_XY\000"
2933 /* 8602 */ "T97_XY\000"
2934 /* 8609 */ "T7_XY\000"
2935 /* 8615 */ "T108_XY\000"
2936 /* 8623 */ "T118_XY\000"
2937 /* 8631 */ "T18_XY\000"
2938 /* 8638 */ "T28_XY\000"
2939 /* 8645 */ "T38_XY\000"
2940 /* 8652 */ "T48_XY\000"
2941 /* 8659 */ "T58_XY\000"
2942 /* 8666 */ "T68_XY\000"
2943 /* 8673 */ "T78_XY\000"
2944 /* 8680 */ "T88_XY\000"
2945 /* 8687 */ "T98_XY\000"
2946 /* 8694 */ "T8_XY\000"
2947 /* 8700 */ "T109_XY\000"
2948 /* 8708 */ "T119_XY\000"
2949 /* 8716 */ "T19_XY\000"
2950 /* 8723 */ "T29_XY\000"
2951 /* 8730 */ "T39_XY\000"
2952 /* 8737 */ "T49_XY\000"
2953 /* 8744 */ "T59_XY\000"
2954 /* 8751 */ "T69_XY\000"
2955 /* 8758 */ "T79_XY\000"
2956 /* 8765 */ "T89_XY\000"
2957 /* 8772 */ "T99_XY\000"
2958 /* 8779 */ "T9_XY\000"
2959 /* 8785 */ "T100_Y\000"
2960 /* 8792 */ "Addr100_Y\000"
2961 /* 8802 */ "T110_Y\000"
2962 /* 8809 */ "Addr110_Y\000"
2963 /* 8819 */ "T10_Y\000"
2964 /* 8825 */ "Addr10_Y\000"
2965 /* 8834 */ "T120_Y\000"
2966 /* 8841 */ "Addr120_Y\000"
2967 /* 8851 */ "T20_Y\000"
2968 /* 8857 */ "Addr20_Y\000"
2969 /* 8866 */ "KC0_130_Y\000"
2970 /* 8876 */ "T30_Y\000"
2971 /* 8882 */ "Addr30_Y\000"
2972 /* 8891 */ "KC0_140_Y\000"
2973 /* 8901 */ "T40_Y\000"
2974 /* 8907 */ "Addr40_Y\000"
2975 /* 8916 */ "KC0_150_Y\000"
2976 /* 8926 */ "T50_Y\000"
2977 /* 8932 */ "Addr50_Y\000"
2978 /* 8941 */ "KC1_160_Y\000"
2979 /* 8951 */ "T60_Y\000"
2980 /* 8957 */ "Addr60_Y\000"
2981 /* 8966 */ "KC1_170_Y\000"
2982 /* 8976 */ "T70_Y\000"
2983 /* 8982 */ "Addr70_Y\000"
2984 /* 8991 */ "KC1_180_Y\000"
2985 /* 9001 */ "T80_Y\000"
2986 /* 9007 */ "Addr80_Y\000"
2987 /* 9016 */ "KC1_190_Y\000"
2988 /* 9026 */ "T90_Y\000"
2989 /* 9032 */ "Addr90_Y\000"
2990 /* 9041 */ "T0_Y\000"
2991 /* 9046 */ "Addr0_Y\000"
2992 /* 9054 */ "T101_Y\000"
2993 /* 9061 */ "Addr101_Y\000"
2994 /* 9071 */ "V01_Y\000"
2995 /* 9077 */ "T111_Y\000"
2996 /* 9084 */ "Addr111_Y\000"
2997 /* 9094 */ "T11_Y\000"
2998 /* 9100 */ "Addr11_Y\000"
2999 /* 9109 */ "T121_Y\000"
3000 /* 9116 */ "Addr121_Y\000"
3001 /* 9126 */ "T21_Y\000"
3002 /* 9132 */ "Addr21_Y\000"
3003 /* 9141 */ "KC0_131_Y\000"
3004 /* 9151 */ "T31_Y\000"
3005 /* 9157 */ "Addr31_Y\000"
3006 /* 9166 */ "KC0_141_Y\000"
3007 /* 9176 */ "T41_Y\000"
3008 /* 9182 */ "Addr41_Y\000"
3009 /* 9191 */ "KC0_151_Y\000"
3010 /* 9201 */ "T51_Y\000"
3011 /* 9207 */ "Addr51_Y\000"
3012 /* 9216 */ "KC1_161_Y\000"
3013 /* 9226 */ "T61_Y\000"
3014 /* 9232 */ "Addr61_Y\000"
3015 /* 9241 */ "KC1_171_Y\000"
3016 /* 9251 */ "T71_Y\000"
3017 /* 9257 */ "Addr71_Y\000"
3018 /* 9266 */ "KC1_181_Y\000"
3019 /* 9276 */ "T81_Y\000"
3020 /* 9282 */ "Addr81_Y\000"
3021 /* 9291 */ "KC1_191_Y\000"
3022 /* 9301 */ "T91_Y\000"
3023 /* 9307 */ "Addr91_Y\000"
3024 /* 9316 */ "T1_Y\000"
3025 /* 9321 */ "Addr1_Y\000"
3026 /* 9329 */ "T102_Y\000"
3027 /* 9336 */ "Addr102_Y\000"
3028 /* 9346 */ "T112_Y\000"
3029 /* 9353 */ "Addr112_Y\000"
3030 /* 9363 */ "T12_Y\000"
3031 /* 9369 */ "Addr12_Y\000"
3032 /* 9378 */ "T122_Y\000"
3033 /* 9385 */ "Addr122_Y\000"
3034 /* 9395 */ "T22_Y\000"
3035 /* 9401 */ "Addr22_Y\000"
3036 /* 9410 */ "KC0_132_Y\000"
3037 /* 9420 */ "T32_Y\000"
3038 /* 9426 */ "Addr32_Y\000"
3039 /* 9435 */ "KC0_142_Y\000"
3040 /* 9445 */ "T42_Y\000"
3041 /* 9451 */ "Addr42_Y\000"
3042 /* 9460 */ "KC0_152_Y\000"
3043 /* 9470 */ "T52_Y\000"
3044 /* 9476 */ "Addr52_Y\000"
3045 /* 9485 */ "KC1_162_Y\000"
3046 /* 9495 */ "T62_Y\000"
3047 /* 9501 */ "Addr62_Y\000"
3048 /* 9510 */ "KC1_172_Y\000"
3049 /* 9520 */ "T72_Y\000"
3050 /* 9526 */ "Addr72_Y\000"
3051 /* 9535 */ "KC1_182_Y\000"
3052 /* 9545 */ "T82_Y\000"
3053 /* 9551 */ "Addr82_Y\000"
3054 /* 9560 */ "T92_Y\000"
3055 /* 9566 */ "Addr92_Y\000"
3056 /* 9575 */ "T2_Y\000"
3057 /* 9580 */ "Addr2_Y\000"
3058 /* 9588 */ "T103_Y\000"
3059 /* 9595 */ "Addr103_Y\000"
3060 /* 9605 */ "T113_Y\000"
3061 /* 9612 */ "Addr113_Y\000"
3062 /* 9622 */ "T13_Y\000"
3063 /* 9628 */ "Addr13_Y\000"
3064 /* 9637 */ "V0123_Y\000"
3065 /* 9645 */ "T123_Y\000"
3066 /* 9652 */ "Addr123_Y\000"
3067 /* 9662 */ "T23_Y\000"
3068 /* 9668 */ "V23_Y\000"
3069 /* 9674 */ "Addr23_Y\000"
3070 /* 9683 */ "KC0_133_Y\000"
3071 /* 9693 */ "T33_Y\000"
3072 /* 9699 */ "Addr33_Y\000"
3073 /* 9708 */ "KC0_143_Y\000"
3074 /* 9718 */ "T43_Y\000"
3075 /* 9724 */ "Addr43_Y\000"
3076 /* 9733 */ "KC0_153_Y\000"
3077 /* 9743 */ "T53_Y\000"
3078 /* 9749 */ "Addr53_Y\000"
3079 /* 9758 */ "KC1_163_Y\000"
3080 /* 9768 */ "T63_Y\000"
3081 /* 9774 */ "Addr63_Y\000"
3082 /* 9783 */ "KC1_173_Y\000"
3083 /* 9793 */ "T73_Y\000"
3084 /* 9799 */ "Addr73_Y\000"
3085 /* 9808 */ "KC1_183_Y\000"
3086 /* 9818 */ "T83_Y\000"
3087 /* 9824 */ "Addr83_Y\000"
3088 /* 9833 */ "T93_Y\000"
3089 /* 9839 */ "Addr93_Y\000"
3090 /* 9848 */ "T3_Y\000"
3091 /* 9853 */ "Addr3_Y\000"
3092 /* 9861 */ "T104_Y\000"
3093 /* 9868 */ "Addr104_Y\000"
3094 /* 9878 */ "T114_Y\000"
3095 /* 9885 */ "Addr114_Y\000"
3096 /* 9895 */ "T14_Y\000"
3097 /* 9901 */ "Addr14_Y\000"
3098 /* 9910 */ "T124_Y\000"
3099 /* 9917 */ "Addr124_Y\000"
3100 /* 9927 */ "T24_Y\000"
3101 /* 9933 */ "Addr24_Y\000"
3102 /* 9942 */ "KC0_134_Y\000"
3103 /* 9952 */ "T34_Y\000"
3104 /* 9958 */ "Addr34_Y\000"
3105 /* 9967 */ "KC0_144_Y\000"
3106 /* 9977 */ "T44_Y\000"
3107 /* 9983 */ "Addr44_Y\000"
3108 /* 9992 */ "KC0_154_Y\000"
3109 /* 10002 */ "T54_Y\000"
3110 /* 10008 */ "Addr54_Y\000"
3111 /* 10017 */ "KC1_164_Y\000"
3112 /* 10027 */ "T64_Y\000"
3113 /* 10033 */ "Addr64_Y\000"
3114 /* 10042 */ "KC1_174_Y\000"
3115 /* 10052 */ "T74_Y\000"
3116 /* 10058 */ "Addr74_Y\000"
3117 /* 10067 */ "KC1_184_Y\000"
3118 /* 10077 */ "T84_Y\000"
3119 /* 10083 */ "Addr84_Y\000"
3120 /* 10092 */ "T94_Y\000"
3121 /* 10098 */ "Addr94_Y\000"
3122 /* 10107 */ "T4_Y\000"
3123 /* 10112 */ "Addr4_Y\000"
3124 /* 10120 */ "T105_Y\000"
3125 /* 10127 */ "Addr105_Y\000"
3126 /* 10137 */ "T115_Y\000"
3127 /* 10144 */ "Addr115_Y\000"
3128 /* 10154 */ "T15_Y\000"
3129 /* 10160 */ "Addr15_Y\000"
3130 /* 10169 */ "T125_Y\000"
3131 /* 10176 */ "Addr125_Y\000"
3132 /* 10186 */ "T25_Y\000"
3133 /* 10192 */ "Addr25_Y\000"
3134 /* 10201 */ "KC0_135_Y\000"
3135 /* 10211 */ "T35_Y\000"
3136 /* 10217 */ "Addr35_Y\000"
3137 /* 10226 */ "KC0_145_Y\000"
3138 /* 10236 */ "T45_Y\000"
3139 /* 10242 */ "Addr45_Y\000"
3140 /* 10251 */ "KC0_155_Y\000"
3141 /* 10261 */ "T55_Y\000"
3142 /* 10267 */ "Addr55_Y\000"
3143 /* 10276 */ "KC1_165_Y\000"
3144 /* 10286 */ "T65_Y\000"
3145 /* 10292 */ "Addr65_Y\000"
3146 /* 10301 */ "KC1_175_Y\000"
3147 /* 10311 */ "T75_Y\000"
3148 /* 10317 */ "Addr75_Y\000"
3149 /* 10326 */ "KC1_185_Y\000"
3150 /* 10336 */ "T85_Y\000"
3151 /* 10342 */ "Addr85_Y\000"
3152 /* 10351 */ "T95_Y\000"
3153 /* 10357 */ "Addr95_Y\000"
3154 /* 10366 */ "T5_Y\000"
3155 /* 10371 */ "Addr5_Y\000"
3156 /* 10379 */ "T106_Y\000"
3157 /* 10386 */ "Addr106_Y\000"
3158 /* 10396 */ "T116_Y\000"
3159 /* 10403 */ "Addr116_Y\000"
3160 /* 10413 */ "T16_Y\000"
3161 /* 10419 */ "Addr16_Y\000"
3162 /* 10428 */ "T126_Y\000"
3163 /* 10435 */ "Addr126_Y\000"
3164 /* 10445 */ "T26_Y\000"
3165 /* 10451 */ "Addr26_Y\000"
3166 /* 10460 */ "KC0_136_Y\000"
3167 /* 10470 */ "T36_Y\000"
3168 /* 10476 */ "Addr36_Y\000"
3169 /* 10485 */ "KC0_146_Y\000"
3170 /* 10495 */ "T46_Y\000"
3171 /* 10501 */ "Addr46_Y\000"
3172 /* 10510 */ "KC0_156_Y\000"
3173 /* 10520 */ "T56_Y\000"
3174 /* 10526 */ "Addr56_Y\000"
3175 /* 10535 */ "KC1_166_Y\000"
3176 /* 10545 */ "T66_Y\000"
3177 /* 10551 */ "Addr66_Y\000"
3178 /* 10560 */ "KC1_176_Y\000"
3179 /* 10570 */ "T76_Y\000"
3180 /* 10576 */ "Addr76_Y\000"
3181 /* 10585 */ "KC1_186_Y\000"
3182 /* 10595 */ "T86_Y\000"
3183 /* 10601 */ "Addr86_Y\000"
3184 /* 10610 */ "T96_Y\000"
3185 /* 10616 */ "Addr96_Y\000"
3186 /* 10625 */ "T6_Y\000"
3187 /* 10630 */ "Addr6_Y\000"
3188 /* 10638 */ "T107_Y\000"
3189 /* 10645 */ "Addr107_Y\000"
3190 /* 10655 */ "T117_Y\000"
3191 /* 10662 */ "Addr117_Y\000"
3192 /* 10672 */ "T17_Y\000"
3193 /* 10678 */ "Addr17_Y\000"
3194 /* 10687 */ "T127_Y\000"
3195 /* 10694 */ "Addr127_Y\000"
3196 /* 10704 */ "T27_Y\000"
3197 /* 10710 */ "Addr27_Y\000"
3198 /* 10719 */ "KC0_137_Y\000"
3199 /* 10729 */ "T37_Y\000"
3200 /* 10735 */ "Addr37_Y\000"
3201 /* 10744 */ "KC0_147_Y\000"
3202 /* 10754 */ "T47_Y\000"
3203 /* 10760 */ "Addr47_Y\000"
3204 /* 10769 */ "KC0_157_Y\000"
3205 /* 10779 */ "T57_Y\000"
3206 /* 10785 */ "Addr57_Y\000"
3207 /* 10794 */ "KC1_167_Y\000"
3208 /* 10804 */ "T67_Y\000"
3209 /* 10810 */ "Addr67_Y\000"
3210 /* 10819 */ "KC1_177_Y\000"
3211 /* 10829 */ "T77_Y\000"
3212 /* 10835 */ "Addr77_Y\000"
3213 /* 10844 */ "KC1_187_Y\000"
3214 /* 10854 */ "T87_Y\000"
3215 /* 10860 */ "Addr87_Y\000"
3216 /* 10869 */ "T97_Y\000"
3217 /* 10875 */ "Addr97_Y\000"
3218 /* 10884 */ "T7_Y\000"
3219 /* 10889 */ "Addr7_Y\000"
3220 /* 10897 */ "T108_Y\000"
3221 /* 10904 */ "Addr108_Y\000"
3222 /* 10914 */ "T118_Y\000"
3223 /* 10921 */ "Addr118_Y\000"
3224 /* 10931 */ "T18_Y\000"
3225 /* 10937 */ "Addr18_Y\000"
3226 /* 10946 */ "KC0_128_Y\000"
3227 /* 10956 */ "T28_Y\000"
3228 /* 10962 */ "Addr28_Y\000"
3229 /* 10971 */ "KC0_138_Y\000"
3230 /* 10981 */ "T38_Y\000"
3231 /* 10987 */ "Addr38_Y\000"
3232 /* 10996 */ "KC0_148_Y\000"
3233 /* 11006 */ "T48_Y\000"
3234 /* 11012 */ "Addr48_Y\000"
3235 /* 11021 */ "KC0_158_Y\000"
3236 /* 11031 */ "T58_Y\000"
3237 /* 11037 */ "Addr58_Y\000"
3238 /* 11046 */ "KC1_168_Y\000"
3239 /* 11056 */ "T68_Y\000"
3240 /* 11062 */ "Addr68_Y\000"
3241 /* 11071 */ "KC1_178_Y\000"
3242 /* 11081 */ "T78_Y\000"
3243 /* 11087 */ "Addr78_Y\000"
3244 /* 11096 */ "KC1_188_Y\000"
3245 /* 11106 */ "T88_Y\000"
3246 /* 11112 */ "Addr88_Y\000"
3247 /* 11121 */ "T98_Y\000"
3248 /* 11127 */ "Addr98_Y\000"
3249 /* 11136 */ "T8_Y\000"
3250 /* 11141 */ "Addr8_Y\000"
3251 /* 11149 */ "T109_Y\000"
3252 /* 11156 */ "Addr109_Y\000"
3253 /* 11166 */ "T119_Y\000"
3254 /* 11173 */ "Addr119_Y\000"
3255 /* 11183 */ "T19_Y\000"
3256 /* 11189 */ "Addr19_Y\000"
3257 /* 11198 */ "KC0_129_Y\000"
3258 /* 11208 */ "T29_Y\000"
3259 /* 11214 */ "Addr29_Y\000"
3260 /* 11223 */ "KC0_139_Y\000"
3261 /* 11233 */ "T39_Y\000"
3262 /* 11239 */ "Addr39_Y\000"
3263 /* 11248 */ "KC0_149_Y\000"
3264 /* 11258 */ "T49_Y\000"
3265 /* 11264 */ "Addr49_Y\000"
3266 /* 11273 */ "KC0_159_Y\000"
3267 /* 11283 */ "T59_Y\000"
3268 /* 11289 */ "Addr59_Y\000"
3269 /* 11298 */ "KC1_169_Y\000"
3270 /* 11308 */ "T69_Y\000"
3271 /* 11314 */ "Addr69_Y\000"
3272 /* 11323 */ "KC1_179_Y\000"
3273 /* 11333 */ "T79_Y\000"
3274 /* 11339 */ "Addr79_Y\000"
3275 /* 11348 */ "KC1_189_Y\000"
3276 /* 11358 */ "T89_Y\000"
3277 /* 11364 */ "Addr89_Y\000"
3278 /* 11373 */ "T99_Y\000"
3279 /* 11379 */ "Addr99_Y\000"
3280 /* 11388 */ "T9_Y\000"
3281 /* 11393 */ "Addr9_Y\000"
3282 /* 11401 */ "ALU_LITERAL_Y\000"
3283 /* 11415 */ "PV_Y\000"
3284 /* 11420 */ "T100_Z\000"
3285 /* 11427 */ "Addr100_Z\000"
3286 /* 11437 */ "T110_Z\000"
3287 /* 11444 */ "Addr110_Z\000"
3288 /* 11454 */ "T10_Z\000"
3289 /* 11460 */ "Addr10_Z\000"
3290 /* 11469 */ "T120_Z\000"
3291 /* 11476 */ "Addr120_Z\000"
3292 /* 11486 */ "T20_Z\000"
3293 /* 11492 */ "Addr20_Z\000"
3294 /* 11501 */ "KC0_130_Z\000"
3295 /* 11511 */ "T30_Z\000"
3296 /* 11517 */ "Addr30_Z\000"
3297 /* 11526 */ "KC0_140_Z\000"
3298 /* 11536 */ "T40_Z\000"
3299 /* 11542 */ "Addr40_Z\000"
3300 /* 11551 */ "KC0_150_Z\000"
3301 /* 11561 */ "T50_Z\000"
3302 /* 11567 */ "Addr50_Z\000"
3303 /* 11576 */ "KC1_160_Z\000"
3304 /* 11586 */ "T60_Z\000"
3305 /* 11592 */ "Addr60_Z\000"
3306 /* 11601 */ "KC1_170_Z\000"
3307 /* 11611 */ "T70_Z\000"
3308 /* 11617 */ "Addr70_Z\000"
3309 /* 11626 */ "KC1_180_Z\000"
3310 /* 11636 */ "T80_Z\000"
3311 /* 11642 */ "Addr80_Z\000"
3312 /* 11651 */ "KC1_190_Z\000"
3313 /* 11661 */ "T90_Z\000"
3314 /* 11667 */ "Addr90_Z\000"
3315 /* 11676 */ "T0_Z\000"
3316 /* 11681 */ "Addr0_Z\000"
3317 /* 11689 */ "T101_Z\000"
3318 /* 11696 */ "Addr101_Z\000"
3319 /* 11706 */ "V01_Z\000"
3320 /* 11712 */ "T111_Z\000"
3321 /* 11719 */ "Addr111_Z\000"
3322 /* 11729 */ "T11_Z\000"
3323 /* 11735 */ "Addr11_Z\000"
3324 /* 11744 */ "T121_Z\000"
3325 /* 11751 */ "Addr121_Z\000"
3326 /* 11761 */ "T21_Z\000"
3327 /* 11767 */ "Addr21_Z\000"
3328 /* 11776 */ "KC0_131_Z\000"
3329 /* 11786 */ "T31_Z\000"
3330 /* 11792 */ "Addr31_Z\000"
3331 /* 11801 */ "KC0_141_Z\000"
3332 /* 11811 */ "T41_Z\000"
3333 /* 11817 */ "Addr41_Z\000"
3334 /* 11826 */ "KC0_151_Z\000"
3335 /* 11836 */ "T51_Z\000"
3336 /* 11842 */ "Addr51_Z\000"
3337 /* 11851 */ "KC1_161_Z\000"
3338 /* 11861 */ "T61_Z\000"
3339 /* 11867 */ "Addr61_Z\000"
3340 /* 11876 */ "KC1_171_Z\000"
3341 /* 11886 */ "T71_Z\000"
3342 /* 11892 */ "Addr71_Z\000"
3343 /* 11901 */ "KC1_181_Z\000"
3344 /* 11911 */ "T81_Z\000"
3345 /* 11917 */ "Addr81_Z\000"
3346 /* 11926 */ "KC1_191_Z\000"
3347 /* 11936 */ "T91_Z\000"
3348 /* 11942 */ "Addr91_Z\000"
3349 /* 11951 */ "T1_Z\000"
3350 /* 11956 */ "Addr1_Z\000"
3351 /* 11964 */ "T102_Z\000"
3352 /* 11971 */ "Addr102_Z\000"
3353 /* 11981 */ "T112_Z\000"
3354 /* 11988 */ "Addr112_Z\000"
3355 /* 11998 */ "T12_Z\000"
3356 /* 12004 */ "Addr12_Z\000"
3357 /* 12013 */ "T122_Z\000"
3358 /* 12020 */ "Addr122_Z\000"
3359 /* 12030 */ "T22_Z\000"
3360 /* 12036 */ "Addr22_Z\000"
3361 /* 12045 */ "KC0_132_Z\000"
3362 /* 12055 */ "T32_Z\000"
3363 /* 12061 */ "Addr32_Z\000"
3364 /* 12070 */ "KC0_142_Z\000"
3365 /* 12080 */ "T42_Z\000"
3366 /* 12086 */ "Addr42_Z\000"
3367 /* 12095 */ "KC0_152_Z\000"
3368 /* 12105 */ "T52_Z\000"
3369 /* 12111 */ "Addr52_Z\000"
3370 /* 12120 */ "KC1_162_Z\000"
3371 /* 12130 */ "T62_Z\000"
3372 /* 12136 */ "Addr62_Z\000"
3373 /* 12145 */ "KC1_172_Z\000"
3374 /* 12155 */ "T72_Z\000"
3375 /* 12161 */ "Addr72_Z\000"
3376 /* 12170 */ "KC1_182_Z\000"
3377 /* 12180 */ "T82_Z\000"
3378 /* 12186 */ "Addr82_Z\000"
3379 /* 12195 */ "T92_Z\000"
3380 /* 12201 */ "Addr92_Z\000"
3381 /* 12210 */ "T2_Z\000"
3382 /* 12215 */ "Addr2_Z\000"
3383 /* 12223 */ "T103_Z\000"
3384 /* 12230 */ "Addr103_Z\000"
3385 /* 12240 */ "T113_Z\000"
3386 /* 12247 */ "Addr113_Z\000"
3387 /* 12257 */ "T13_Z\000"
3388 /* 12263 */ "Addr13_Z\000"
3389 /* 12272 */ "V0123_Z\000"
3390 /* 12280 */ "T123_Z\000"
3391 /* 12287 */ "Addr123_Z\000"
3392 /* 12297 */ "T23_Z\000"
3393 /* 12303 */ "V23_Z\000"
3394 /* 12309 */ "Addr23_Z\000"
3395 /* 12318 */ "KC0_133_Z\000"
3396 /* 12328 */ "T33_Z\000"
3397 /* 12334 */ "Addr33_Z\000"
3398 /* 12343 */ "KC0_143_Z\000"
3399 /* 12353 */ "T43_Z\000"
3400 /* 12359 */ "Addr43_Z\000"
3401 /* 12368 */ "KC0_153_Z\000"
3402 /* 12378 */ "T53_Z\000"
3403 /* 12384 */ "Addr53_Z\000"
3404 /* 12393 */ "KC1_163_Z\000"
3405 /* 12403 */ "T63_Z\000"
3406 /* 12409 */ "Addr63_Z\000"
3407 /* 12418 */ "KC1_173_Z\000"
3408 /* 12428 */ "T73_Z\000"
3409 /* 12434 */ "Addr73_Z\000"
3410 /* 12443 */ "KC1_183_Z\000"
3411 /* 12453 */ "T83_Z\000"
3412 /* 12459 */ "Addr83_Z\000"
3413 /* 12468 */ "T93_Z\000"
3414 /* 12474 */ "Addr93_Z\000"
3415 /* 12483 */ "T3_Z\000"
3416 /* 12488 */ "Addr3_Z\000"
3417 /* 12496 */ "T104_Z\000"
3418 /* 12503 */ "Addr104_Z\000"
3419 /* 12513 */ "T114_Z\000"
3420 /* 12520 */ "Addr114_Z\000"
3421 /* 12530 */ "T14_Z\000"
3422 /* 12536 */ "Addr14_Z\000"
3423 /* 12545 */ "T124_Z\000"
3424 /* 12552 */ "Addr124_Z\000"
3425 /* 12562 */ "T24_Z\000"
3426 /* 12568 */ "Addr24_Z\000"
3427 /* 12577 */ "KC0_134_Z\000"
3428 /* 12587 */ "T34_Z\000"
3429 /* 12593 */ "Addr34_Z\000"
3430 /* 12602 */ "KC0_144_Z\000"
3431 /* 12612 */ "T44_Z\000"
3432 /* 12618 */ "Addr44_Z\000"
3433 /* 12627 */ "KC0_154_Z\000"
3434 /* 12637 */ "T54_Z\000"
3435 /* 12643 */ "Addr54_Z\000"
3436 /* 12652 */ "KC1_164_Z\000"
3437 /* 12662 */ "T64_Z\000"
3438 /* 12668 */ "Addr64_Z\000"
3439 /* 12677 */ "KC1_174_Z\000"
3440 /* 12687 */ "T74_Z\000"
3441 /* 12693 */ "Addr74_Z\000"
3442 /* 12702 */ "KC1_184_Z\000"
3443 /* 12712 */ "T84_Z\000"
3444 /* 12718 */ "Addr84_Z\000"
3445 /* 12727 */ "T94_Z\000"
3446 /* 12733 */ "Addr94_Z\000"
3447 /* 12742 */ "T4_Z\000"
3448 /* 12747 */ "Addr4_Z\000"
3449 /* 12755 */ "T105_Z\000"
3450 /* 12762 */ "Addr105_Z\000"
3451 /* 12772 */ "T115_Z\000"
3452 /* 12779 */ "Addr115_Z\000"
3453 /* 12789 */ "T15_Z\000"
3454 /* 12795 */ "Addr15_Z\000"
3455 /* 12804 */ "T125_Z\000"
3456 /* 12811 */ "Addr125_Z\000"
3457 /* 12821 */ "T25_Z\000"
3458 /* 12827 */ "Addr25_Z\000"
3459 /* 12836 */ "KC0_135_Z\000"
3460 /* 12846 */ "T35_Z\000"
3461 /* 12852 */ "Addr35_Z\000"
3462 /* 12861 */ "KC0_145_Z\000"
3463 /* 12871 */ "T45_Z\000"
3464 /* 12877 */ "Addr45_Z\000"
3465 /* 12886 */ "KC0_155_Z\000"
3466 /* 12896 */ "T55_Z\000"
3467 /* 12902 */ "Addr55_Z\000"
3468 /* 12911 */ "KC1_165_Z\000"
3469 /* 12921 */ "T65_Z\000"
3470 /* 12927 */ "Addr65_Z\000"
3471 /* 12936 */ "KC1_175_Z\000"
3472 /* 12946 */ "T75_Z\000"
3473 /* 12952 */ "Addr75_Z\000"
3474 /* 12961 */ "KC1_185_Z\000"
3475 /* 12971 */ "T85_Z\000"
3476 /* 12977 */ "Addr85_Z\000"
3477 /* 12986 */ "T95_Z\000"
3478 /* 12992 */ "Addr95_Z\000"
3479 /* 13001 */ "T5_Z\000"
3480 /* 13006 */ "Addr5_Z\000"
3481 /* 13014 */ "T106_Z\000"
3482 /* 13021 */ "Addr106_Z\000"
3483 /* 13031 */ "T116_Z\000"
3484 /* 13038 */ "Addr116_Z\000"
3485 /* 13048 */ "T16_Z\000"
3486 /* 13054 */ "Addr16_Z\000"
3487 /* 13063 */ "T126_Z\000"
3488 /* 13070 */ "Addr126_Z\000"
3489 /* 13080 */ "T26_Z\000"
3490 /* 13086 */ "Addr26_Z\000"
3491 /* 13095 */ "KC0_136_Z\000"
3492 /* 13105 */ "T36_Z\000"
3493 /* 13111 */ "Addr36_Z\000"
3494 /* 13120 */ "KC0_146_Z\000"
3495 /* 13130 */ "T46_Z\000"
3496 /* 13136 */ "Addr46_Z\000"
3497 /* 13145 */ "KC0_156_Z\000"
3498 /* 13155 */ "T56_Z\000"
3499 /* 13161 */ "Addr56_Z\000"
3500 /* 13170 */ "KC1_166_Z\000"
3501 /* 13180 */ "T66_Z\000"
3502 /* 13186 */ "Addr66_Z\000"
3503 /* 13195 */ "KC1_176_Z\000"
3504 /* 13205 */ "T76_Z\000"
3505 /* 13211 */ "Addr76_Z\000"
3506 /* 13220 */ "KC1_186_Z\000"
3507 /* 13230 */ "T86_Z\000"
3508 /* 13236 */ "Addr86_Z\000"
3509 /* 13245 */ "T96_Z\000"
3510 /* 13251 */ "Addr96_Z\000"
3511 /* 13260 */ "T6_Z\000"
3512 /* 13265 */ "Addr6_Z\000"
3513 /* 13273 */ "T107_Z\000"
3514 /* 13280 */ "Addr107_Z\000"
3515 /* 13290 */ "T117_Z\000"
3516 /* 13297 */ "Addr117_Z\000"
3517 /* 13307 */ "T17_Z\000"
3518 /* 13313 */ "Addr17_Z\000"
3519 /* 13322 */ "T127_Z\000"
3520 /* 13329 */ "Addr127_Z\000"
3521 /* 13339 */ "T27_Z\000"
3522 /* 13345 */ "Addr27_Z\000"
3523 /* 13354 */ "KC0_137_Z\000"
3524 /* 13364 */ "T37_Z\000"
3525 /* 13370 */ "Addr37_Z\000"
3526 /* 13379 */ "KC0_147_Z\000"
3527 /* 13389 */ "T47_Z\000"
3528 /* 13395 */ "Addr47_Z\000"
3529 /* 13404 */ "KC0_157_Z\000"
3530 /* 13414 */ "T57_Z\000"
3531 /* 13420 */ "Addr57_Z\000"
3532 /* 13429 */ "KC1_167_Z\000"
3533 /* 13439 */ "T67_Z\000"
3534 /* 13445 */ "Addr67_Z\000"
3535 /* 13454 */ "KC1_177_Z\000"
3536 /* 13464 */ "T77_Z\000"
3537 /* 13470 */ "Addr77_Z\000"
3538 /* 13479 */ "KC1_187_Z\000"
3539 /* 13489 */ "T87_Z\000"
3540 /* 13495 */ "Addr87_Z\000"
3541 /* 13504 */ "T97_Z\000"
3542 /* 13510 */ "Addr97_Z\000"
3543 /* 13519 */ "T7_Z\000"
3544 /* 13524 */ "Addr7_Z\000"
3545 /* 13532 */ "T108_Z\000"
3546 /* 13539 */ "Addr108_Z\000"
3547 /* 13549 */ "T118_Z\000"
3548 /* 13556 */ "Addr118_Z\000"
3549 /* 13566 */ "T18_Z\000"
3550 /* 13572 */ "Addr18_Z\000"
3551 /* 13581 */ "KC0_128_Z\000"
3552 /* 13591 */ "T28_Z\000"
3553 /* 13597 */ "Addr28_Z\000"
3554 /* 13606 */ "KC0_138_Z\000"
3555 /* 13616 */ "T38_Z\000"
3556 /* 13622 */ "Addr38_Z\000"
3557 /* 13631 */ "KC0_148_Z\000"
3558 /* 13641 */ "T48_Z\000"
3559 /* 13647 */ "Addr48_Z\000"
3560 /* 13656 */ "KC0_158_Z\000"
3561 /* 13666 */ "T58_Z\000"
3562 /* 13672 */ "Addr58_Z\000"
3563 /* 13681 */ "KC1_168_Z\000"
3564 /* 13691 */ "T68_Z\000"
3565 /* 13697 */ "Addr68_Z\000"
3566 /* 13706 */ "KC1_178_Z\000"
3567 /* 13716 */ "T78_Z\000"
3568 /* 13722 */ "Addr78_Z\000"
3569 /* 13731 */ "KC1_188_Z\000"
3570 /* 13741 */ "T88_Z\000"
3571 /* 13747 */ "Addr88_Z\000"
3572 /* 13756 */ "T98_Z\000"
3573 /* 13762 */ "Addr98_Z\000"
3574 /* 13771 */ "T8_Z\000"
3575 /* 13776 */ "Addr8_Z\000"
3576 /* 13784 */ "T109_Z\000"
3577 /* 13791 */ "Addr109_Z\000"
3578 /* 13801 */ "T119_Z\000"
3579 /* 13808 */ "Addr119_Z\000"
3580 /* 13818 */ "T19_Z\000"
3581 /* 13824 */ "Addr19_Z\000"
3582 /* 13833 */ "KC0_129_Z\000"
3583 /* 13843 */ "T29_Z\000"
3584 /* 13849 */ "Addr29_Z\000"
3585 /* 13858 */ "KC0_139_Z\000"
3586 /* 13868 */ "T39_Z\000"
3587 /* 13874 */ "Addr39_Z\000"
3588 /* 13883 */ "KC0_149_Z\000"
3589 /* 13893 */ "T49_Z\000"
3590 /* 13899 */ "Addr49_Z\000"
3591 /* 13908 */ "KC0_159_Z\000"
3592 /* 13918 */ "T59_Z\000"
3593 /* 13924 */ "Addr59_Z\000"
3594 /* 13933 */ "KC1_169_Z\000"
3595 /* 13943 */ "T69_Z\000"
3596 /* 13949 */ "Addr69_Z\000"
3597 /* 13958 */ "KC1_179_Z\000"
3598 /* 13968 */ "T79_Z\000"
3599 /* 13974 */ "Addr79_Z\000"
3600 /* 13983 */ "KC1_189_Z\000"
3601 /* 13993 */ "T89_Z\000"
3602 /* 13999 */ "Addr89_Z\000"
3603 /* 14008 */ "T99_Z\000"
3604 /* 14014 */ "Addr99_Z\000"
3605 /* 14023 */ "T9_Z\000"
3606 /* 14028 */ "Addr9_Z\000"
3607 /* 14036 */ "ALU_LITERAL_Z\000"
3608 /* 14050 */ "PV_Z\000"
3609};
3610#ifdef __GNUC__
3611#pragma GCC diagnostic pop
3612#endif
3613
3614extern const MCRegisterDesc R600RegDesc[] = { // Descriptors
3615 { 12, 0, 0, 0, 0, 0, 0, 0 },
3616 { 584, 4, 4, 2, 16384, 10, 0, 0 },
3617 { 5212, 4, 4, 2, 16385, 10, 0, 0 },
3618 { 7847, 4, 4, 2, 16386, 10, 0, 0 },
3619 { 11401, 4, 4, 2, 16387, 10, 0, 0 },
3620 { 14036, 4, 4, 2, 16388, 10, 0, 0 },
3621 { 506, 4, 4, 2, 16389, 10, 0, 0 },
3622 { 7861, 4, 4, 2, 16390, 10, 0, 0 },
3623 { 501, 4, 4, 2, 16391, 10, 0, 0 },
3624 { 540, 4, 4, 2, 16392, 10, 0, 0 },
3625 { 433, 4, 4, 2, 16393, 10, 0, 0 },
3626 { 450, 4, 4, 2, 16394, 10, 0, 0 },
3627 { 497, 4, 4, 2, 16395, 10, 0, 0 },
3628 { 463, 4, 4, 2, 16396, 10, 0, 0 },
3629 { 467, 4, 4, 2, 16397, 10, 0, 0 },
3630 { 576, 4, 4, 2, 16398, 10, 0, 0 },
3631 { 429, 4, 4, 2, 16399, 10, 0, 0 },
3632 { 530, 4, 4, 2, 16400, 10, 0, 0 },
3633 { 446, 4, 4, 2, 16401, 10, 0, 0 },
3634 { 535, 4, 4, 2, 16402, 10, 0, 0 },
3635 { 562, 4, 4, 2, 16403, 10, 0, 0 },
3636 { 484, 4, 4, 2, 16404, 10, 0, 0 },
3637 { 471, 4, 4, 2, 16405, 10, 0, 0 },
3638 { 516, 4, 4, 2, 16406, 10, 0, 0 },
3639 { 559, 4, 4, 2, 16407, 10, 0, 0 },
3640 { 5226, 4, 4, 2, 16408, 10, 0, 0 },
3641 { 7866, 4, 4, 2, 16409, 10, 0, 0 },
3642 { 11415, 4, 4, 2, 16410, 10, 0, 0 },
3643 { 14050, 4, 4, 2, 16411, 10, 0, 0 },
3644 { 525, 4, 4, 2, 16412, 10, 0, 0 },
3645 { 325, 4, 4, 2, 16413, 10, 0, 0 },
3646 { 377, 4, 4, 2, 16414, 10, 0, 0 },
3647 { 0, 4, 4, 2, 16415, 10, 0, 0 },
3648 { 52, 4, 4, 2, 16416, 10, 0, 0 },
3649 { 91, 4, 4, 2, 16417, 10, 0, 0 },
3650 { 130, 4, 4, 2, 16418, 10, 0, 0 },
3651 { 169, 4, 4, 2, 16419, 10, 0, 0 },
3652 { 208, 4, 4, 2, 16420, 10, 0, 0 },
3653 { 247, 4, 4, 2, 16421, 10, 0, 0 },
3654 { 286, 4, 4, 2, 16422, 10, 0, 0 },
3655 { 338, 4, 4, 2, 16423, 10, 0, 0 },
3656 { 390, 4, 4, 2, 16424, 10, 0, 0 },
3657 { 13, 4, 4, 2, 16425, 10, 0, 0 },
3658 { 65, 4, 4, 2, 16426, 10, 0, 0 },
3659 { 104, 4, 4, 2, 16427, 10, 0, 0 },
3660 { 143, 4, 4, 2, 16428, 10, 0, 0 },
3661 { 182, 4, 4, 2, 16429, 10, 0, 0 },
3662 { 221, 4, 4, 2, 16430, 10, 0, 0 },
3663 { 260, 4, 4, 2, 16431, 10, 0, 0 },
3664 { 299, 4, 4, 2, 16432, 10, 0, 0 },
3665 { 351, 4, 4, 2, 16433, 10, 0, 0 },
3666 { 403, 4, 4, 2, 16434, 10, 0, 0 },
3667 { 26, 4, 4, 2, 16435, 10, 0, 0 },
3668 { 78, 4, 4, 2, 16436, 10, 0, 0 },
3669 { 117, 4, 4, 2, 16437, 10, 0, 0 },
3670 { 156, 4, 4, 2, 16438, 10, 0, 0 },
3671 { 195, 4, 4, 2, 16439, 10, 0, 0 },
3672 { 234, 4, 4, 2, 16440, 10, 0, 0 },
3673 { 273, 4, 4, 2, 16441, 10, 0, 0 },
3674 { 312, 4, 4, 2, 16442, 10, 0, 0 },
3675 { 364, 4, 4, 2, 16443, 10, 0, 0 },
3676 { 416, 4, 4, 2, 16444, 10, 0, 0 },
3677 { 39, 4, 4, 2, 16445, 10, 0, 0 },
3678 { 2857, 4, 4, 2, 16446, 10, 0, 0 },
3679 { 3132, 4, 4, 2, 16447, 10, 0, 0 },
3680 { 3391, 4, 4, 2, 16448, 10, 0, 0 },
3681 { 3664, 4, 4, 2, 16449, 10, 0, 0 },
3682 { 3923, 4, 4, 2, 16450, 10, 0, 0 },
3683 { 4182, 4, 4, 2, 16451, 10, 0, 0 },
3684 { 4441, 4, 4, 2, 16452, 10, 0, 0 },
3685 { 4700, 4, 4, 2, 16453, 10, 0, 0 },
3686 { 4952, 4, 4, 2, 16454, 10, 0, 0 },
3687 { 5204, 4, 4, 2, 16455, 10, 0, 0 },
3688 { 2636, 4, 4, 2, 16456, 10, 0, 0 },
3689 { 2911, 4, 4, 2, 16457, 10, 0, 0 },
3690 { 3180, 4, 4, 2, 16458, 10, 0, 0 },
3691 { 3439, 4, 4, 2, 16459, 10, 0, 0 },
3692 { 3712, 4, 4, 2, 16460, 10, 0, 0 },
3693 { 3971, 4, 4, 2, 16461, 10, 0, 0 },
3694 { 4230, 4, 4, 2, 16462, 10, 0, 0 },
3695 { 4489, 4, 4, 2, 16463, 10, 0, 0 },
3696 { 4748, 4, 4, 2, 16464, 10, 0, 0 },
3697 { 5000, 4, 4, 2, 16465, 10, 0, 0 },
3698 { 2668, 4, 4, 2, 16466, 10, 0, 0 },
3699 { 2943, 4, 4, 2, 16467, 10, 0, 0 },
3700 { 3212, 4, 4, 2, 16468, 10, 0, 0 },
3701 { 3485, 4, 4, 2, 16469, 10, 0, 0 },
3702 { 3744, 4, 4, 2, 16470, 10, 0, 0 },
3703 { 4003, 4, 4, 2, 16471, 10, 0, 0 },
3704 { 4262, 4, 4, 2, 16472, 10, 0, 0 },
3705 { 4521, 4, 4, 2, 16473, 10, 0, 0 },
3706 { 4773, 4, 4, 2, 16474, 10, 0, 0 },
3707 { 5025, 4, 4, 2, 16475, 10, 0, 0 },
3708 { 2693, 4, 4, 2, 16476, 10, 0, 0 },
3709 { 2968, 4, 4, 2, 16477, 10, 0, 0 },
3710 { 3237, 4, 4, 2, 16478, 10, 0, 0 },
3711 { 3510, 4, 4, 2, 16479, 10, 0, 0 },
3712 { 3769, 4, 4, 2, 16480, 10, 0, 0 },
3713 { 4028, 4, 4, 2, 16481, 10, 0, 0 },
3714 { 4287, 4, 4, 2, 16482, 10, 0, 0 },
3715 { 4546, 4, 4, 2, 16483, 10, 0, 0 },
3716 { 4798, 4, 4, 2, 16484, 10, 0, 0 },
3717 { 5050, 4, 4, 2, 16485, 10, 0, 0 },
3718 { 2718, 4, 4, 2, 16486, 10, 0, 0 },
3719 { 2993, 4, 4, 2, 16487, 10, 0, 0 },
3720 { 3262, 4, 4, 2, 16488, 10, 0, 0 },
3721 { 3535, 4, 4, 2, 16489, 10, 0, 0 },
3722 { 3794, 4, 4, 2, 16490, 10, 0, 0 },
3723 { 4053, 4, 4, 2, 16491, 10, 0, 0 },
3724 { 4312, 4, 4, 2, 16492, 10, 0, 0 },
3725 { 4571, 4, 4, 2, 16493, 10, 0, 0 },
3726 { 4823, 4, 4, 2, 16494, 10, 0, 0 },
3727 { 5075, 4, 4, 2, 16495, 10, 0, 0 },
3728 { 2743, 4, 4, 2, 16496, 10, 0, 0 },
3729 { 3018, 4, 4, 2, 16497, 10, 0, 0 },
3730 { 3287, 4, 4, 2, 16498, 10, 0, 0 },
3731 { 3560, 4, 4, 2, 16499, 10, 0, 0 },
3732 { 3819, 4, 4, 2, 16500, 10, 0, 0 },
3733 { 4078, 4, 4, 2, 16501, 10, 0, 0 },
3734 { 4337, 4, 4, 2, 16502, 10, 0, 0 },
3735 { 4596, 4, 4, 2, 16503, 10, 0, 0 },
3736 { 4848, 4, 4, 2, 16504, 10, 0, 0 },
3737 { 5100, 4, 4, 2, 16505, 10, 0, 0 },
3738 { 2768, 4, 4, 2, 16506, 10, 0, 0 },
3739 { 3043, 4, 4, 2, 16507, 10, 0, 0 },
3740 { 3312, 4, 4, 2, 16508, 10, 0, 0 },
3741 { 3585, 4, 4, 2, 16509, 10, 0, 0 },
3742 { 3844, 4, 4, 2, 16510, 10, 0, 0 },
3743 { 4103, 4, 4, 2, 16511, 10, 0, 0 },
3744 { 4362, 4, 4, 2, 16512, 10, 0, 0 },
3745 { 4621, 4, 4, 2, 16513, 10, 0, 0 },
3746 { 4873, 4, 4, 2, 16514, 10, 0, 0 },
3747 { 5125, 4, 4, 2, 16515, 10, 0, 0 },
3748 { 2793, 4, 4, 2, 16516, 10, 0, 0 },
3749 { 3068, 4, 4, 2, 16517, 10, 0, 0 },
3750 { 3337, 4, 4, 2, 16518, 10, 0, 0 },
3751 { 3610, 4, 4, 2, 16519, 10, 0, 0 },
3752 { 3869, 4, 4, 2, 16520, 10, 0, 0 },
3753 { 4128, 4, 4, 2, 16521, 10, 0, 0 },
3754 { 4387, 4, 4, 2, 16522, 10, 0, 0 },
3755 { 4646, 4, 4, 2, 16523, 10, 0, 0 },
3756 { 4898, 4, 4, 2, 16524, 10, 0, 0 },
3757 { 5150, 4, 4, 2, 16525, 10, 0, 0 },
3758 { 2818, 4, 4, 2, 16526, 10, 0, 0 },
3759 { 3093, 4, 4, 2, 16527, 10, 0, 0 },
3760 { 3362, 4, 4, 2, 16528, 10, 0, 0 },
3761 { 3635, 4, 4, 2, 16529, 10, 0, 0 },
3762 { 3894, 4, 4, 2, 16530, 10, 0, 0 },
3763 { 4153, 4, 4, 2, 16531, 10, 0, 0 },
3764 { 4412, 4, 4, 2, 16532, 10, 0, 0 },
3765 { 4671, 4, 4, 2, 16533, 10, 0, 0 },
3766 { 4923, 4, 4, 2, 16534, 10, 0, 0 },
3767 { 5175, 4, 4, 2, 16535, 10, 0, 0 },
3768 { 2843, 4, 4, 2, 16536, 10, 0, 0 },
3769 { 3118, 4, 4, 2, 16537, 10, 0, 0 },
3770 { 3377, 4, 4, 2, 16538, 10, 0, 0 },
3771 { 3650, 4, 4, 2, 16539, 10, 0, 0 },
3772 { 3909, 4, 4, 2, 16540, 10, 0, 0 },
3773 { 4168, 4, 4, 2, 16541, 10, 0, 0 },
3774 { 4427, 4, 4, 2, 16542, 10, 0, 0 },
3775 { 4686, 4, 4, 2, 16543, 10, 0, 0 },
3776 { 4938, 4, 4, 2, 16544, 10, 0, 0 },
3777 { 5190, 4, 4, 2, 16545, 10, 0, 0 },
3778 { 2603, 4, 4, 2, 16546, 10, 0, 0 },
3779 { 2872, 4, 4, 2, 16547, 10, 0, 0 },
3780 { 3147, 4, 4, 2, 16548, 10, 0, 0 },
3781 { 3406, 4, 4, 2, 16549, 10, 0, 0 },
3782 { 3679, 4, 4, 2, 16550, 10, 0, 0 },
3783 { 3938, 4, 4, 2, 16551, 10, 0, 0 },
3784 { 4197, 4, 4, 2, 16552, 10, 0, 0 },
3785 { 4456, 4, 4, 2, 16553, 10, 0, 0 },
3786 { 4715, 4, 4, 2, 16554, 10, 0, 0 },
3787 { 4967, 4, 4, 2, 16555, 10, 0, 0 },
3788 { 2620, 4, 4, 2, 16556, 10, 0, 0 },
3789 { 2895, 4, 4, 2, 16557, 10, 0, 0 },
3790 { 3164, 4, 4, 2, 16558, 10, 0, 0 },
3791 { 3423, 4, 4, 2, 16559, 10, 0, 0 },
3792 { 3696, 4, 4, 2, 16560, 10, 0, 0 },
3793 { 3955, 4, 4, 2, 16561, 10, 0, 0 },
3794 { 4214, 4, 4, 2, 16562, 10, 0, 0 },
3795 { 4473, 4, 4, 2, 16563, 10, 0, 0 },
3796 { 4732, 4, 4, 2, 16564, 10, 0, 0 },
3797 { 4984, 4, 4, 2, 16565, 10, 0, 0 },
3798 { 2652, 4, 4, 2, 16566, 10, 0, 0 },
3799 { 2927, 4, 4, 2, 16567, 10, 0, 0 },
3800 { 3196, 4, 4, 2, 16568, 10, 0, 0 },
3801 { 3463, 4, 4, 2, 16569, 10, 0, 0 },
3802 { 3728, 4, 4, 2, 16570, 10, 0, 0 },
3803 { 3987, 4, 4, 2, 16571, 10, 0, 0 },
3804 { 4246, 4, 4, 2, 16572, 10, 0, 0 },
3805 { 4505, 4, 4, 2, 16573, 10, 0, 0 },
3806 { 5492, 4, 4, 2, 16574, 10, 0, 0 },
3807 { 5767, 4, 4, 2, 16575, 10, 0, 0 },
3808 { 6026, 4, 4, 2, 16576, 10, 0, 0 },
3809 { 6299, 4, 4, 2, 16577, 10, 0, 0 },
3810 { 6558, 4, 4, 2, 16578, 10, 0, 0 },
3811 { 6817, 4, 4, 2, 16579, 10, 0, 0 },
3812 { 7076, 4, 4, 2, 16580, 10, 0, 0 },
3813 { 7335, 4, 4, 2, 16581, 10, 0, 0 },
3814 { 7587, 4, 4, 2, 16582, 10, 0, 0 },
3815 { 7839, 4, 4, 2, 16583, 10, 0, 0 },
3816 { 5271, 4, 4, 2, 16584, 10, 0, 0 },
3817 { 5546, 4, 4, 2, 16585, 10, 0, 0 },
3818 { 5815, 4, 4, 2, 16586, 10, 0, 0 },
3819 { 6074, 4, 4, 2, 16587, 10, 0, 0 },
3820 { 6347, 4, 4, 2, 16588, 10, 0, 0 },
3821 { 6606, 4, 4, 2, 16589, 10, 0, 0 },
3822 { 6865, 4, 4, 2, 16590, 10, 0, 0 },
3823 { 7124, 4, 4, 2, 16591, 10, 0, 0 },
3824 { 7383, 4, 4, 2, 16592, 10, 0, 0 },
3825 { 7635, 4, 4, 2, 16593, 10, 0, 0 },
3826 { 5303, 4, 4, 2, 16594, 10, 0, 0 },
3827 { 5578, 4, 4, 2, 16595, 10, 0, 0 },
3828 { 5847, 4, 4, 2, 16596, 10, 0, 0 },
3829 { 6120, 4, 4, 2, 16597, 10, 0, 0 },
3830 { 6379, 4, 4, 2, 16598, 10, 0, 0 },
3831 { 6638, 4, 4, 2, 16599, 10, 0, 0 },
3832 { 6897, 4, 4, 2, 16600, 10, 0, 0 },
3833 { 7156, 4, 4, 2, 16601, 10, 0, 0 },
3834 { 7408, 4, 4, 2, 16602, 10, 0, 0 },
3835 { 7660, 4, 4, 2, 16603, 10, 0, 0 },
3836 { 5328, 4, 4, 2, 16604, 10, 0, 0 },
3837 { 5603, 4, 4, 2, 16605, 10, 0, 0 },
3838 { 5872, 4, 4, 2, 16606, 10, 0, 0 },
3839 { 6145, 4, 4, 2, 16607, 10, 0, 0 },
3840 { 6404, 4, 4, 2, 16608, 10, 0, 0 },
3841 { 6663, 4, 4, 2, 16609, 10, 0, 0 },
3842 { 6922, 4, 4, 2, 16610, 10, 0, 0 },
3843 { 7181, 4, 4, 2, 16611, 10, 0, 0 },
3844 { 7433, 4, 4, 2, 16612, 10, 0, 0 },
3845 { 7685, 4, 4, 2, 16613, 10, 0, 0 },
3846 { 5353, 4, 4, 2, 16614, 10, 0, 0 },
3847 { 5628, 4, 4, 2, 16615, 10, 0, 0 },
3848 { 5897, 4, 4, 2, 16616, 10, 0, 0 },
3849 { 6170, 4, 4, 2, 16617, 10, 0, 0 },
3850 { 6429, 4, 4, 2, 16618, 10, 0, 0 },
3851 { 6688, 4, 4, 2, 16619, 10, 0, 0 },
3852 { 6947, 4, 4, 2, 16620, 10, 0, 0 },
3853 { 7206, 4, 4, 2, 16621, 10, 0, 0 },
3854 { 7458, 4, 4, 2, 16622, 10, 0, 0 },
3855 { 7710, 4, 4, 2, 16623, 10, 0, 0 },
3856 { 5378, 4, 4, 2, 16624, 10, 0, 0 },
3857 { 5653, 4, 4, 2, 16625, 10, 0, 0 },
3858 { 5922, 4, 4, 2, 16626, 10, 0, 0 },
3859 { 6195, 4, 4, 2, 16627, 10, 0, 0 },
3860 { 6454, 4, 4, 2, 16628, 10, 0, 0 },
3861 { 6713, 4, 4, 2, 16629, 10, 0, 0 },
3862 { 6972, 4, 4, 2, 16630, 10, 0, 0 },
3863 { 7231, 4, 4, 2, 16631, 10, 0, 0 },
3864 { 7483, 4, 4, 2, 16632, 10, 0, 0 },
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5265 { 13429, 4, 10, 2, 17677, 10, 0, 0 },
5266 { 13681, 4, 10, 2, 17679, 10, 0, 0 },
5267 { 13933, 4, 10, 2, 17681, 10, 0, 0 },
5268 { 11601, 4, 10, 2, 17683, 10, 0, 0 },
5269 { 11876, 4, 10, 2, 17685, 10, 0, 0 },
5270 { 12145, 4, 10, 2, 17687, 10, 0, 0 },
5271 { 12418, 4, 10, 2, 17689, 10, 0, 0 },
5272 { 12677, 4, 10, 2, 17691, 10, 0, 0 },
5273 { 12936, 4, 10, 2, 17693, 10, 0, 0 },
5274 { 13195, 4, 10, 2, 17695, 10, 0, 0 },
5275 { 13454, 4, 10, 2, 17697, 10, 0, 0 },
5276 { 13706, 4, 10, 2, 17699, 10, 0, 0 },
5277 { 13958, 4, 10, 2, 17701, 10, 0, 0 },
5278 { 11626, 4, 10, 2, 17703, 10, 0, 0 },
5279 { 11901, 4, 10, 2, 17705, 10, 0, 0 },
5280 { 12170, 4, 10, 2, 17707, 10, 0, 0 },
5281 { 12443, 4, 10, 2, 17709, 10, 0, 0 },
5282 { 12702, 4, 10, 2, 17711, 10, 0, 0 },
5283 { 12961, 4, 10, 2, 17713, 10, 0, 0 },
5284 { 13220, 4, 10, 2, 17715, 10, 0, 0 },
5285 { 13479, 4, 10, 2, 17717, 10, 0, 0 },
5286 { 13731, 4, 10, 2, 17719, 10, 0, 0 },
5287 { 13983, 4, 10, 2, 17721, 10, 0, 0 },
5288 { 11651, 4, 10, 2, 17723, 10, 0, 0 },
5289 { 11926, 4, 10, 2, 17725, 10, 0, 0 },
5290};
5291
5292extern const MCPhysReg R600RegUnitRoots[][2] = {
5293 { R600::ALU_CONST },
5294 { R600::ALU_LITERAL_W },
5295 { R600::ALU_LITERAL_X },
5296 { R600::ALU_LITERAL_Y },
5297 { R600::ALU_LITERAL_Z },
5298 { R600::ALU_PARAM },
5299 { R600::AR_X },
5300 { R600::HALF },
5301 { R600::INDIRECT_BASE_ADDR },
5302 { R600::LDS_DIRECT_A },
5303 { R600::LDS_DIRECT_B },
5304 { R600::NEG_HALF },
5305 { R600::NEG_ONE },
5306 { R600::ONE },
5307 { R600::ONE_INT },
5308 { R600::OQA },
5309 { R600::OQAP },
5310 { R600::OQB },
5311 { R600::OQBP },
5312 { R600::PREDICATE_BIT },
5313 { R600::PRED_SEL_OFF },
5314 { R600::PRED_SEL_ONE },
5315 { R600::PRED_SEL_ZERO },
5316 { R600::PS },
5317 { R600::PV_W },
5318 { R600::PV_X },
5319 { R600::PV_Y },
5320 { R600::PV_Z },
5321 { R600::ZERO },
5322 { R600::ArrayBase448 },
5323 { R600::ArrayBase449 },
5324 { R600::ArrayBase450 },
5325 { R600::ArrayBase451 },
5326 { R600::ArrayBase452 },
5327 { R600::ArrayBase453 },
5328 { R600::ArrayBase454 },
5329 { R600::ArrayBase455 },
5330 { R600::ArrayBase456 },
5331 { R600::ArrayBase457 },
5332 { R600::ArrayBase458 },
5333 { R600::ArrayBase459 },
5334 { R600::ArrayBase460 },
5335 { R600::ArrayBase461 },
5336 { R600::ArrayBase462 },
5337 { R600::ArrayBase463 },
5338 { R600::ArrayBase464 },
5339 { R600::ArrayBase465 },
5340 { R600::ArrayBase466 },
5341 { R600::ArrayBase467 },
5342 { R600::ArrayBase468 },
5343 { R600::ArrayBase469 },
5344 { R600::ArrayBase470 },
5345 { R600::ArrayBase471 },
5346 { R600::ArrayBase472 },
5347 { R600::ArrayBase473 },
5348 { R600::ArrayBase474 },
5349 { R600::ArrayBase475 },
5350 { R600::ArrayBase476 },
5351 { R600::ArrayBase477 },
5352 { R600::ArrayBase478 },
5353 { R600::ArrayBase479 },
5354 { R600::ArrayBase480 },
5355 { R600::Addr0_W },
5356 { R600::Addr1_W },
5357 { R600::Addr2_W },
5358 { R600::Addr3_W },
5359 { R600::Addr4_W },
5360 { R600::Addr5_W },
5361 { R600::Addr6_W },
5362 { R600::Addr7_W },
5363 { R600::Addr8_W },
5364 { R600::Addr9_W },
5365 { R600::Addr10_W },
5366 { R600::Addr11_W },
5367 { R600::Addr12_W },
5368 { R600::Addr13_W },
5369 { R600::Addr14_W },
5370 { R600::Addr15_W },
5371 { R600::Addr16_W },
5372 { R600::Addr17_W },
5373 { R600::Addr18_W },
5374 { R600::Addr19_W },
5375 { R600::Addr20_W },
5376 { R600::Addr21_W },
5377 { R600::Addr22_W },
5378 { R600::Addr23_W },
5379 { R600::Addr24_W },
5380 { R600::Addr25_W },
5381 { R600::Addr26_W },
5382 { R600::Addr27_W },
5383 { R600::Addr28_W },
5384 { R600::Addr29_W },
5385 { R600::Addr30_W },
5386 { R600::Addr31_W },
5387 { R600::Addr32_W },
5388 { R600::Addr33_W },
5389 { R600::Addr34_W },
5390 { R600::Addr35_W },
5391 { R600::Addr36_W },
5392 { R600::Addr37_W },
5393 { R600::Addr38_W },
5394 { R600::Addr39_W },
5395 { R600::Addr40_W },
5396 { R600::Addr41_W },
5397 { R600::Addr42_W },
5398 { R600::Addr43_W },
5399 { R600::Addr44_W },
5400 { R600::Addr45_W },
5401 { R600::Addr46_W },
5402 { R600::Addr47_W },
5403 { R600::Addr48_W },
5404 { R600::Addr49_W },
5405 { R600::Addr50_W },
5406 { R600::Addr51_W },
5407 { R600::Addr52_W },
5408 { R600::Addr53_W },
5409 { R600::Addr54_W },
5410 { R600::Addr55_W },
5411 { R600::Addr56_W },
5412 { R600::Addr57_W },
5413 { R600::Addr58_W },
5414 { R600::Addr59_W },
5415 { R600::Addr60_W },
5416 { R600::Addr61_W },
5417 { R600::Addr62_W },
5418 { R600::Addr63_W },
5419 { R600::Addr64_W },
5420 { R600::Addr65_W },
5421 { R600::Addr66_W },
5422 { R600::Addr67_W },
5423 { R600::Addr68_W },
5424 { R600::Addr69_W },
5425 { R600::Addr70_W },
5426 { R600::Addr71_W },
5427 { R600::Addr72_W },
5428 { R600::Addr73_W },
5429 { R600::Addr74_W },
5430 { R600::Addr75_W },
5431 { R600::Addr76_W },
5432 { R600::Addr77_W },
5433 { R600::Addr78_W },
5434 { R600::Addr79_W },
5435 { R600::Addr80_W },
5436 { R600::Addr81_W },
5437 { R600::Addr82_W },
5438 { R600::Addr83_W },
5439 { R600::Addr84_W },
5440 { R600::Addr85_W },
5441 { R600::Addr86_W },
5442 { R600::Addr87_W },
5443 { R600::Addr88_W },
5444 { R600::Addr89_W },
5445 { R600::Addr90_W },
5446 { R600::Addr91_W },
5447 { R600::Addr92_W },
5448 { R600::Addr93_W },
5449 { R600::Addr94_W },
5450 { R600::Addr95_W },
5451 { R600::Addr96_W },
5452 { R600::Addr97_W },
5453 { R600::Addr98_W },
5454 { R600::Addr99_W },
5455 { R600::Addr100_W },
5456 { R600::Addr101_W },
5457 { R600::Addr102_W },
5458 { R600::Addr103_W },
5459 { R600::Addr104_W },
5460 { R600::Addr105_W },
5461 { R600::Addr106_W },
5462 { R600::Addr107_W },
5463 { R600::Addr108_W },
5464 { R600::Addr109_W },
5465 { R600::Addr110_W },
5466 { R600::Addr111_W },
5467 { R600::Addr112_W },
5468 { R600::Addr113_W },
5469 { R600::Addr114_W },
5470 { R600::Addr115_W },
5471 { R600::Addr116_W },
5472 { R600::Addr117_W },
5473 { R600::Addr118_W },
5474 { R600::Addr119_W },
5475 { R600::Addr120_W },
5476 { R600::Addr121_W },
5477 { R600::Addr122_W },
5478 { R600::Addr123_W },
5479 { R600::Addr124_W },
5480 { R600::Addr125_W },
5481 { R600::Addr126_W },
5482 { R600::Addr127_W },
5483 { R600::Addr0_X },
5484 { R600::Addr1_X },
5485 { R600::Addr2_X },
5486 { R600::Addr3_X },
5487 { R600::Addr4_X },
5488 { R600::Addr5_X },
5489 { R600::Addr6_X },
5490 { R600::Addr7_X },
5491 { R600::Addr8_X },
5492 { R600::Addr9_X },
5493 { R600::Addr10_X },
5494 { R600::Addr11_X },
5495 { R600::Addr12_X },
5496 { R600::Addr13_X },
5497 { R600::Addr14_X },
5498 { R600::Addr15_X },
5499 { R600::Addr16_X },
5500 { R600::Addr17_X },
5501 { R600::Addr18_X },
5502 { R600::Addr19_X },
5503 { R600::Addr20_X },
5504 { R600::Addr21_X },
5505 { R600::Addr22_X },
5506 { R600::Addr23_X },
5507 { R600::Addr24_X },
5508 { R600::Addr25_X },
5509 { R600::Addr26_X },
5510 { R600::Addr27_X },
5511 { R600::Addr28_X },
5512 { R600::Addr29_X },
5513 { R600::Addr30_X },
5514 { R600::Addr31_X },
5515 { R600::Addr32_X },
5516 { R600::Addr33_X },
5517 { R600::Addr34_X },
5518 { R600::Addr35_X },
5519 { R600::Addr36_X },
5520 { R600::Addr37_X },
5521 { R600::Addr38_X },
5522 { R600::Addr39_X },
5523 { R600::Addr40_X },
5524 { R600::Addr41_X },
5525 { R600::Addr42_X },
5526 { R600::Addr43_X },
5527 { R600::Addr44_X },
5528 { R600::Addr45_X },
5529 { R600::Addr46_X },
5530 { R600::Addr47_X },
5531 { R600::Addr48_X },
5532 { R600::Addr49_X },
5533 { R600::Addr50_X },
5534 { R600::Addr51_X },
5535 { R600::Addr52_X },
5536 { R600::Addr53_X },
5537 { R600::Addr54_X },
5538 { R600::Addr55_X },
5539 { R600::Addr56_X },
5540 { R600::Addr57_X },
5541 { R600::Addr58_X },
5542 { R600::Addr59_X },
5543 { R600::Addr60_X },
5544 { R600::Addr61_X },
5545 { R600::Addr62_X },
5546 { R600::Addr63_X },
5547 { R600::Addr64_X },
5548 { R600::Addr65_X },
5549 { R600::Addr66_X },
5550 { R600::Addr67_X },
5551 { R600::Addr68_X },
5552 { R600::Addr69_X },
5553 { R600::Addr70_X },
5554 { R600::Addr71_X },
5555 { R600::Addr72_X },
5556 { R600::Addr73_X },
5557 { R600::Addr74_X },
5558 { R600::Addr75_X },
5559 { R600::Addr76_X },
5560 { R600::Addr77_X },
5561 { R600::Addr78_X },
5562 { R600::Addr79_X },
5563 { R600::Addr80_X },
5564 { R600::Addr81_X },
5565 { R600::Addr82_X },
5566 { R600::Addr83_X },
5567 { R600::Addr84_X },
5568 { R600::Addr85_X },
5569 { R600::Addr86_X },
5570 { R600::Addr87_X },
5571 { R600::Addr88_X },
5572 { R600::Addr89_X },
5573 { R600::Addr90_X },
5574 { R600::Addr91_X },
5575 { R600::Addr92_X },
5576 { R600::Addr93_X },
5577 { R600::Addr94_X },
5578 { R600::Addr95_X },
5579 { R600::Addr96_X },
5580 { R600::Addr97_X },
5581 { R600::Addr98_X },
5582 { R600::Addr99_X },
5583 { R600::Addr100_X },
5584 { R600::Addr101_X },
5585 { R600::Addr102_X },
5586 { R600::Addr103_X },
5587 { R600::Addr104_X },
5588 { R600::Addr105_X },
5589 { R600::Addr106_X },
5590 { R600::Addr107_X },
5591 { R600::Addr108_X },
5592 { R600::Addr109_X },
5593 { R600::Addr110_X },
5594 { R600::Addr111_X },
5595 { R600::Addr112_X },
5596 { R600::Addr113_X },
5597 { R600::Addr114_X },
5598 { R600::Addr115_X },
5599 { R600::Addr116_X },
5600 { R600::Addr117_X },
5601 { R600::Addr118_X },
5602 { R600::Addr119_X },
5603 { R600::Addr120_X },
5604 { R600::Addr121_X },
5605 { R600::Addr122_X },
5606 { R600::Addr123_X },
5607 { R600::Addr124_X },
5608 { R600::Addr125_X },
5609 { R600::Addr126_X },
5610 { R600::Addr127_X },
5611 { R600::Addr0_Y },
5612 { R600::Addr1_Y },
5613 { R600::Addr2_Y },
5614 { R600::Addr3_Y },
5615 { R600::Addr4_Y },
5616 { R600::Addr5_Y },
5617 { R600::Addr6_Y },
5618 { R600::Addr7_Y },
5619 { R600::Addr8_Y },
5620 { R600::Addr9_Y },
5621 { R600::Addr10_Y },
5622 { R600::Addr11_Y },
5623 { R600::Addr12_Y },
5624 { R600::Addr13_Y },
5625 { R600::Addr14_Y },
5626 { R600::Addr15_Y },
5627 { R600::Addr16_Y },
5628 { R600::Addr17_Y },
5629 { R600::Addr18_Y },
5630 { R600::Addr19_Y },
5631 { R600::Addr20_Y },
5632 { R600::Addr21_Y },
5633 { R600::Addr22_Y },
5634 { R600::Addr23_Y },
5635 { R600::Addr24_Y },
5636 { R600::Addr25_Y },
5637 { R600::Addr26_Y },
5638 { R600::Addr27_Y },
5639 { R600::Addr28_Y },
5640 { R600::Addr29_Y },
5641 { R600::Addr30_Y },
5642 { R600::Addr31_Y },
5643 { R600::Addr32_Y },
5644 { R600::Addr33_Y },
5645 { R600::Addr34_Y },
5646 { R600::Addr35_Y },
5647 { R600::Addr36_Y },
5648 { R600::Addr37_Y },
5649 { R600::Addr38_Y },
5650 { R600::Addr39_Y },
5651 { R600::Addr40_Y },
5652 { R600::Addr41_Y },
5653 { R600::Addr42_Y },
5654 { R600::Addr43_Y },
5655 { R600::Addr44_Y },
5656 { R600::Addr45_Y },
5657 { R600::Addr46_Y },
5658 { R600::Addr47_Y },
5659 { R600::Addr48_Y },
5660 { R600::Addr49_Y },
5661 { R600::Addr50_Y },
5662 { R600::Addr51_Y },
5663 { R600::Addr52_Y },
5664 { R600::Addr53_Y },
5665 { R600::Addr54_Y },
5666 { R600::Addr55_Y },
5667 { R600::Addr56_Y },
5668 { R600::Addr57_Y },
5669 { R600::Addr58_Y },
5670 { R600::Addr59_Y },
5671 { R600::Addr60_Y },
5672 { R600::Addr61_Y },
5673 { R600::Addr62_Y },
5674 { R600::Addr63_Y },
5675 { R600::Addr64_Y },
5676 { R600::Addr65_Y },
5677 { R600::Addr66_Y },
5678 { R600::Addr67_Y },
5679 { R600::Addr68_Y },
5680 { R600::Addr69_Y },
5681 { R600::Addr70_Y },
5682 { R600::Addr71_Y },
5683 { R600::Addr72_Y },
5684 { R600::Addr73_Y },
5685 { R600::Addr74_Y },
5686 { R600::Addr75_Y },
5687 { R600::Addr76_Y },
5688 { R600::Addr77_Y },
5689 { R600::Addr78_Y },
5690 { R600::Addr79_Y },
5691 { R600::Addr80_Y },
5692 { R600::Addr81_Y },
5693 { R600::Addr82_Y },
5694 { R600::Addr83_Y },
5695 { R600::Addr84_Y },
5696 { R600::Addr85_Y },
5697 { R600::Addr86_Y },
5698 { R600::Addr87_Y },
5699 { R600::Addr88_Y },
5700 { R600::Addr89_Y },
5701 { R600::Addr90_Y },
5702 { R600::Addr91_Y },
5703 { R600::Addr92_Y },
5704 { R600::Addr93_Y },
5705 { R600::Addr94_Y },
5706 { R600::Addr95_Y },
5707 { R600::Addr96_Y },
5708 { R600::Addr97_Y },
5709 { R600::Addr98_Y },
5710 { R600::Addr99_Y },
5711 { R600::Addr100_Y },
5712 { R600::Addr101_Y },
5713 { R600::Addr102_Y },
5714 { R600::Addr103_Y },
5715 { R600::Addr104_Y },
5716 { R600::Addr105_Y },
5717 { R600::Addr106_Y },
5718 { R600::Addr107_Y },
5719 { R600::Addr108_Y },
5720 { R600::Addr109_Y },
5721 { R600::Addr110_Y },
5722 { R600::Addr111_Y },
5723 { R600::Addr112_Y },
5724 { R600::Addr113_Y },
5725 { R600::Addr114_Y },
5726 { R600::Addr115_Y },
5727 { R600::Addr116_Y },
5728 { R600::Addr117_Y },
5729 { R600::Addr118_Y },
5730 { R600::Addr119_Y },
5731 { R600::Addr120_Y },
5732 { R600::Addr121_Y },
5733 { R600::Addr122_Y },
5734 { R600::Addr123_Y },
5735 { R600::Addr124_Y },
5736 { R600::Addr125_Y },
5737 { R600::Addr126_Y },
5738 { R600::Addr127_Y },
5739 { R600::Addr0_Z },
5740 { R600::Addr1_Z },
5741 { R600::Addr2_Z },
5742 { R600::Addr3_Z },
5743 { R600::Addr4_Z },
5744 { R600::Addr5_Z },
5745 { R600::Addr6_Z },
5746 { R600::Addr7_Z },
5747 { R600::Addr8_Z },
5748 { R600::Addr9_Z },
5749 { R600::Addr10_Z },
5750 { R600::Addr11_Z },
5751 { R600::Addr12_Z },
5752 { R600::Addr13_Z },
5753 { R600::Addr14_Z },
5754 { R600::Addr15_Z },
5755 { R600::Addr16_Z },
5756 { R600::Addr17_Z },
5757 { R600::Addr18_Z },
5758 { R600::Addr19_Z },
5759 { R600::Addr20_Z },
5760 { R600::Addr21_Z },
5761 { R600::Addr22_Z },
5762 { R600::Addr23_Z },
5763 { R600::Addr24_Z },
5764 { R600::Addr25_Z },
5765 { R600::Addr26_Z },
5766 { R600::Addr27_Z },
5767 { R600::Addr28_Z },
5768 { R600::Addr29_Z },
5769 { R600::Addr30_Z },
5770 { R600::Addr31_Z },
5771 { R600::Addr32_Z },
5772 { R600::Addr33_Z },
5773 { R600::Addr34_Z },
5774 { R600::Addr35_Z },
5775 { R600::Addr36_Z },
5776 { R600::Addr37_Z },
5777 { R600::Addr38_Z },
5778 { R600::Addr39_Z },
5779 { R600::Addr40_Z },
5780 { R600::Addr41_Z },
5781 { R600::Addr42_Z },
5782 { R600::Addr43_Z },
5783 { R600::Addr44_Z },
5784 { R600::Addr45_Z },
5785 { R600::Addr46_Z },
5786 { R600::Addr47_Z },
5787 { R600::Addr48_Z },
5788 { R600::Addr49_Z },
5789 { R600::Addr50_Z },
5790 { R600::Addr51_Z },
5791 { R600::Addr52_Z },
5792 { R600::Addr53_Z },
5793 { R600::Addr54_Z },
5794 { R600::Addr55_Z },
5795 { R600::Addr56_Z },
5796 { R600::Addr57_Z },
5797 { R600::Addr58_Z },
5798 { R600::Addr59_Z },
5799 { R600::Addr60_Z },
5800 { R600::Addr61_Z },
5801 { R600::Addr62_Z },
5802 { R600::Addr63_Z },
5803 { R600::Addr64_Z },
5804 { R600::Addr65_Z },
5805 { R600::Addr66_Z },
5806 { R600::Addr67_Z },
5807 { R600::Addr68_Z },
5808 { R600::Addr69_Z },
5809 { R600::Addr70_Z },
5810 { R600::Addr71_Z },
5811 { R600::Addr72_Z },
5812 { R600::Addr73_Z },
5813 { R600::Addr74_Z },
5814 { R600::Addr75_Z },
5815 { R600::Addr76_Z },
5816 { R600::Addr77_Z },
5817 { R600::Addr78_Z },
5818 { R600::Addr79_Z },
5819 { R600::Addr80_Z },
5820 { R600::Addr81_Z },
5821 { R600::Addr82_Z },
5822 { R600::Addr83_Z },
5823 { R600::Addr84_Z },
5824 { R600::Addr85_Z },
5825 { R600::Addr86_Z },
5826 { R600::Addr87_Z },
5827 { R600::Addr88_Z },
5828 { R600::Addr89_Z },
5829 { R600::Addr90_Z },
5830 { R600::Addr91_Z },
5831 { R600::Addr92_Z },
5832 { R600::Addr93_Z },
5833 { R600::Addr94_Z },
5834 { R600::Addr95_Z },
5835 { R600::Addr96_Z },
5836 { R600::Addr97_Z },
5837 { R600::Addr98_Z },
5838 { R600::Addr99_Z },
5839 { R600::Addr100_Z },
5840 { R600::Addr101_Z },
5841 { R600::Addr102_Z },
5842 { R600::Addr103_Z },
5843 { R600::Addr104_Z },
5844 { R600::Addr105_Z },
5845 { R600::Addr106_Z },
5846 { R600::Addr107_Z },
5847 { R600::Addr108_Z },
5848 { R600::Addr109_Z },
5849 { R600::Addr110_Z },
5850 { R600::Addr111_Z },
5851 { R600::Addr112_Z },
5852 { R600::Addr113_Z },
5853 { R600::Addr114_Z },
5854 { R600::Addr115_Z },
5855 { R600::Addr116_Z },
5856 { R600::Addr117_Z },
5857 { R600::Addr118_Z },
5858 { R600::Addr119_Z },
5859 { R600::Addr120_Z },
5860 { R600::Addr121_Z },
5861 { R600::Addr122_Z },
5862 { R600::Addr123_Z },
5863 { R600::Addr124_Z },
5864 { R600::Addr125_Z },
5865 { R600::Addr126_Z },
5866 { R600::Addr127_Z },
5867 { R600::T0_W },
5868 { R600::T1_W },
5869 { R600::T2_W },
5870 { R600::T3_W },
5871 { R600::T4_W },
5872 { R600::T5_W },
5873 { R600::T6_W },
5874 { R600::T7_W },
5875 { R600::T8_W },
5876 { R600::T9_W },
5877 { R600::T10_W },
5878 { R600::T11_W },
5879 { R600::T12_W },
5880 { R600::T13_W },
5881 { R600::T14_W },
5882 { R600::T15_W },
5883 { R600::T16_W },
5884 { R600::T17_W },
5885 { R600::T18_W },
5886 { R600::T19_W },
5887 { R600::T20_W },
5888 { R600::T21_W },
5889 { R600::T22_W },
5890 { R600::T23_W },
5891 { R600::T24_W },
5892 { R600::T25_W },
5893 { R600::T26_W },
5894 { R600::T27_W },
5895 { R600::T28_W },
5896 { R600::T29_W },
5897 { R600::T30_W },
5898 { R600::T31_W },
5899 { R600::T32_W },
5900 { R600::T33_W },
5901 { R600::T34_W },
5902 { R600::T35_W },
5903 { R600::T36_W },
5904 { R600::T37_W },
5905 { R600::T38_W },
5906 { R600::T39_W },
5907 { R600::T40_W },
5908 { R600::T41_W },
5909 { R600::T42_W },
5910 { R600::T43_W },
5911 { R600::T44_W },
5912 { R600::T45_W },
5913 { R600::T46_W },
5914 { R600::T47_W },
5915 { R600::T48_W },
5916 { R600::T49_W },
5917 { R600::T50_W },
5918 { R600::T51_W },
5919 { R600::T52_W },
5920 { R600::T53_W },
5921 { R600::T54_W },
5922 { R600::T55_W },
5923 { R600::T56_W },
5924 { R600::T57_W },
5925 { R600::T58_W },
5926 { R600::T59_W },
5927 { R600::T60_W },
5928 { R600::T61_W },
5929 { R600::T62_W },
5930 { R600::T63_W },
5931 { R600::T64_W },
5932 { R600::T65_W },
5933 { R600::T66_W },
5934 { R600::T67_W },
5935 { R600::T68_W },
5936 { R600::T69_W },
5937 { R600::T70_W },
5938 { R600::T71_W },
5939 { R600::T72_W },
5940 { R600::T73_W },
5941 { R600::T74_W },
5942 { R600::T75_W },
5943 { R600::T76_W },
5944 { R600::T77_W },
5945 { R600::T78_W },
5946 { R600::T79_W },
5947 { R600::T80_W },
5948 { R600::T81_W },
5949 { R600::T82_W },
5950 { R600::T83_W },
5951 { R600::T84_W },
5952 { R600::T85_W },
5953 { R600::T86_W },
5954 { R600::T87_W },
5955 { R600::T88_W },
5956 { R600::T89_W },
5957 { R600::T90_W },
5958 { R600::T91_W },
5959 { R600::T92_W },
5960 { R600::T93_W },
5961 { R600::T94_W },
5962 { R600::T95_W },
5963 { R600::T96_W },
5964 { R600::T97_W },
5965 { R600::T98_W },
5966 { R600::T99_W },
5967 { R600::T100_W },
5968 { R600::T101_W },
5969 { R600::T102_W },
5970 { R600::T103_W },
5971 { R600::T104_W },
5972 { R600::T105_W },
5973 { R600::T106_W },
5974 { R600::T107_W },
5975 { R600::T108_W },
5976 { R600::T109_W },
5977 { R600::T110_W },
5978 { R600::T111_W },
5979 { R600::T112_W },
5980 { R600::T113_W },
5981 { R600::T114_W },
5982 { R600::T115_W },
5983 { R600::T116_W },
5984 { R600::T117_W },
5985 { R600::T118_W },
5986 { R600::T119_W },
5987 { R600::T120_W },
5988 { R600::T121_W },
5989 { R600::T122_W },
5990 { R600::T123_W },
5991 { R600::T124_W },
5992 { R600::T125_W },
5993 { R600::T126_W },
5994 { R600::T127_W },
5995 { R600::T0_X },
5996 { R600::T1_X },
5997 { R600::T2_X },
5998 { R600::T3_X },
5999 { R600::T4_X },
6000 { R600::T5_X },
6001 { R600::T6_X },
6002 { R600::T7_X },
6003 { R600::T8_X },
6004 { R600::T9_X },
6005 { R600::T10_X },
6006 { R600::T11_X },
6007 { R600::T12_X },
6008 { R600::T13_X },
6009 { R600::T14_X },
6010 { R600::T15_X },
6011 { R600::T16_X },
6012 { R600::T17_X },
6013 { R600::T18_X },
6014 { R600::T19_X },
6015 { R600::T20_X },
6016 { R600::T21_X },
6017 { R600::T22_X },
6018 { R600::T23_X },
6019 { R600::T24_X },
6020 { R600::T25_X },
6021 { R600::T26_X },
6022 { R600::T27_X },
6023 { R600::T28_X },
6024 { R600::T29_X },
6025 { R600::T30_X },
6026 { R600::T31_X },
6027 { R600::T32_X },
6028 { R600::T33_X },
6029 { R600::T34_X },
6030 { R600::T35_X },
6031 { R600::T36_X },
6032 { R600::T37_X },
6033 { R600::T38_X },
6034 { R600::T39_X },
6035 { R600::T40_X },
6036 { R600::T41_X },
6037 { R600::T42_X },
6038 { R600::T43_X },
6039 { R600::T44_X },
6040 { R600::T45_X },
6041 { R600::T46_X },
6042 { R600::T47_X },
6043 { R600::T48_X },
6044 { R600::T49_X },
6045 { R600::T50_X },
6046 { R600::T51_X },
6047 { R600::T52_X },
6048 { R600::T53_X },
6049 { R600::T54_X },
6050 { R600::T55_X },
6051 { R600::T56_X },
6052 { R600::T57_X },
6053 { R600::T58_X },
6054 { R600::T59_X },
6055 { R600::T60_X },
6056 { R600::T61_X },
6057 { R600::T62_X },
6058 { R600::T63_X },
6059 { R600::T64_X },
6060 { R600::T65_X },
6061 { R600::T66_X },
6062 { R600::T67_X },
6063 { R600::T68_X },
6064 { R600::T69_X },
6065 { R600::T70_X },
6066 { R600::T71_X },
6067 { R600::T72_X },
6068 { R600::T73_X },
6069 { R600::T74_X },
6070 { R600::T75_X },
6071 { R600::T76_X },
6072 { R600::T77_X },
6073 { R600::T78_X },
6074 { R600::T79_X },
6075 { R600::T80_X },
6076 { R600::T81_X },
6077 { R600::T82_X },
6078 { R600::T83_X },
6079 { R600::T84_X },
6080 { R600::T85_X },
6081 { R600::T86_X },
6082 { R600::T87_X },
6083 { R600::T88_X },
6084 { R600::T89_X },
6085 { R600::T90_X },
6086 { R600::T91_X },
6087 { R600::T92_X },
6088 { R600::T93_X },
6089 { R600::T94_X },
6090 { R600::T95_X },
6091 { R600::T96_X },
6092 { R600::T97_X },
6093 { R600::T98_X },
6094 { R600::T99_X },
6095 { R600::T100_X },
6096 { R600::T101_X },
6097 { R600::T102_X },
6098 { R600::T103_X },
6099 { R600::T104_X },
6100 { R600::T105_X },
6101 { R600::T106_X },
6102 { R600::T107_X },
6103 { R600::T108_X },
6104 { R600::T109_X },
6105 { R600::T110_X },
6106 { R600::T111_X },
6107 { R600::T112_X },
6108 { R600::T113_X },
6109 { R600::T114_X },
6110 { R600::T115_X },
6111 { R600::T116_X },
6112 { R600::T117_X },
6113 { R600::T118_X },
6114 { R600::T119_X },
6115 { R600::T120_X },
6116 { R600::T121_X },
6117 { R600::T122_X },
6118 { R600::T123_X },
6119 { R600::T124_X },
6120 { R600::T125_X },
6121 { R600::T126_X },
6122 { R600::T127_X },
6123 { R600::T0_Y },
6124 { R600::T1_Y },
6125 { R600::T2_Y },
6126 { R600::T3_Y },
6127 { R600::T4_Y },
6128 { R600::T5_Y },
6129 { R600::T6_Y },
6130 { R600::T7_Y },
6131 { R600::T8_Y },
6132 { R600::T9_Y },
6133 { R600::T10_Y },
6134 { R600::T11_Y },
6135 { R600::T12_Y },
6136 { R600::T13_Y },
6137 { R600::T14_Y },
6138 { R600::T15_Y },
6139 { R600::T16_Y },
6140 { R600::T17_Y },
6141 { R600::T18_Y },
6142 { R600::T19_Y },
6143 { R600::T20_Y },
6144 { R600::T21_Y },
6145 { R600::T22_Y },
6146 { R600::T23_Y },
6147 { R600::T24_Y },
6148 { R600::T25_Y },
6149 { R600::T26_Y },
6150 { R600::T27_Y },
6151 { R600::T28_Y },
6152 { R600::T29_Y },
6153 { R600::T30_Y },
6154 { R600::T31_Y },
6155 { R600::T32_Y },
6156 { R600::T33_Y },
6157 { R600::T34_Y },
6158 { R600::T35_Y },
6159 { R600::T36_Y },
6160 { R600::T37_Y },
6161 { R600::T38_Y },
6162 { R600::T39_Y },
6163 { R600::T40_Y },
6164 { R600::T41_Y },
6165 { R600::T42_Y },
6166 { R600::T43_Y },
6167 { R600::T44_Y },
6168 { R600::T45_Y },
6169 { R600::T46_Y },
6170 { R600::T47_Y },
6171 { R600::T48_Y },
6172 { R600::T49_Y },
6173 { R600::T50_Y },
6174 { R600::T51_Y },
6175 { R600::T52_Y },
6176 { R600::T53_Y },
6177 { R600::T54_Y },
6178 { R600::T55_Y },
6179 { R600::T56_Y },
6180 { R600::T57_Y },
6181 { R600::T58_Y },
6182 { R600::T59_Y },
6183 { R600::T60_Y },
6184 { R600::T61_Y },
6185 { R600::T62_Y },
6186 { R600::T63_Y },
6187 { R600::T64_Y },
6188 { R600::T65_Y },
6189 { R600::T66_Y },
6190 { R600::T67_Y },
6191 { R600::T68_Y },
6192 { R600::T69_Y },
6193 { R600::T70_Y },
6194 { R600::T71_Y },
6195 { R600::T72_Y },
6196 { R600::T73_Y },
6197 { R600::T74_Y },
6198 { R600::T75_Y },
6199 { R600::T76_Y },
6200 { R600::T77_Y },
6201 { R600::T78_Y },
6202 { R600::T79_Y },
6203 { R600::T80_Y },
6204 { R600::T81_Y },
6205 { R600::T82_Y },
6206 { R600::T83_Y },
6207 { R600::T84_Y },
6208 { R600::T85_Y },
6209 { R600::T86_Y },
6210 { R600::T87_Y },
6211 { R600::T88_Y },
6212 { R600::T89_Y },
6213 { R600::T90_Y },
6214 { R600::T91_Y },
6215 { R600::T92_Y },
6216 { R600::T93_Y },
6217 { R600::T94_Y },
6218 { R600::T95_Y },
6219 { R600::T96_Y },
6220 { R600::T97_Y },
6221 { R600::T98_Y },
6222 { R600::T99_Y },
6223 { R600::T100_Y },
6224 { R600::T101_Y },
6225 { R600::T102_Y },
6226 { R600::T103_Y },
6227 { R600::T104_Y },
6228 { R600::T105_Y },
6229 { R600::T106_Y },
6230 { R600::T107_Y },
6231 { R600::T108_Y },
6232 { R600::T109_Y },
6233 { R600::T110_Y },
6234 { R600::T111_Y },
6235 { R600::T112_Y },
6236 { R600::T113_Y },
6237 { R600::T114_Y },
6238 { R600::T115_Y },
6239 { R600::T116_Y },
6240 { R600::T117_Y },
6241 { R600::T118_Y },
6242 { R600::T119_Y },
6243 { R600::T120_Y },
6244 { R600::T121_Y },
6245 { R600::T122_Y },
6246 { R600::T123_Y },
6247 { R600::T124_Y },
6248 { R600::T125_Y },
6249 { R600::T126_Y },
6250 { R600::T127_Y },
6251 { R600::T0_Z },
6252 { R600::T1_Z },
6253 { R600::T2_Z },
6254 { R600::T3_Z },
6255 { R600::T4_Z },
6256 { R600::T5_Z },
6257 { R600::T6_Z },
6258 { R600::T7_Z },
6259 { R600::T8_Z },
6260 { R600::T9_Z },
6261 { R600::T10_Z },
6262 { R600::T11_Z },
6263 { R600::T12_Z },
6264 { R600::T13_Z },
6265 { R600::T14_Z },
6266 { R600::T15_Z },
6267 { R600::T16_Z },
6268 { R600::T17_Z },
6269 { R600::T18_Z },
6270 { R600::T19_Z },
6271 { R600::T20_Z },
6272 { R600::T21_Z },
6273 { R600::T22_Z },
6274 { R600::T23_Z },
6275 { R600::T24_Z },
6276 { R600::T25_Z },
6277 { R600::T26_Z },
6278 { R600::T27_Z },
6279 { R600::T28_Z },
6280 { R600::T29_Z },
6281 { R600::T30_Z },
6282 { R600::T31_Z },
6283 { R600::T32_Z },
6284 { R600::T33_Z },
6285 { R600::T34_Z },
6286 { R600::T35_Z },
6287 { R600::T36_Z },
6288 { R600::T37_Z },
6289 { R600::T38_Z },
6290 { R600::T39_Z },
6291 { R600::T40_Z },
6292 { R600::T41_Z },
6293 { R600::T42_Z },
6294 { R600::T43_Z },
6295 { R600::T44_Z },
6296 { R600::T45_Z },
6297 { R600::T46_Z },
6298 { R600::T47_Z },
6299 { R600::T48_Z },
6300 { R600::T49_Z },
6301 { R600::T50_Z },
6302 { R600::T51_Z },
6303 { R600::T52_Z },
6304 { R600::T53_Z },
6305 { R600::T54_Z },
6306 { R600::T55_Z },
6307 { R600::T56_Z },
6308 { R600::T57_Z },
6309 { R600::T58_Z },
6310 { R600::T59_Z },
6311 { R600::T60_Z },
6312 { R600::T61_Z },
6313 { R600::T62_Z },
6314 { R600::T63_Z },
6315 { R600::T64_Z },
6316 { R600::T65_Z },
6317 { R600::T66_Z },
6318 { R600::T67_Z },
6319 { R600::T68_Z },
6320 { R600::T69_Z },
6321 { R600::T70_Z },
6322 { R600::T71_Z },
6323 { R600::T72_Z },
6324 { R600::T73_Z },
6325 { R600::T74_Z },
6326 { R600::T75_Z },
6327 { R600::T76_Z },
6328 { R600::T77_Z },
6329 { R600::T78_Z },
6330 { R600::T79_Z },
6331 { R600::T80_Z },
6332 { R600::T81_Z },
6333 { R600::T82_Z },
6334 { R600::T83_Z },
6335 { R600::T84_Z },
6336 { R600::T85_Z },
6337 { R600::T86_Z },
6338 { R600::T87_Z },
6339 { R600::T88_Z },
6340 { R600::T89_Z },
6341 { R600::T90_Z },
6342 { R600::T91_Z },
6343 { R600::T92_Z },
6344 { R600::T93_Z },
6345 { R600::T94_Z },
6346 { R600::T95_Z },
6347 { R600::T96_Z },
6348 { R600::T97_Z },
6349 { R600::T98_Z },
6350 { R600::T99_Z },
6351 { R600::T100_Z },
6352 { R600::T101_Z },
6353 { R600::T102_Z },
6354 { R600::T103_Z },
6355 { R600::T104_Z },
6356 { R600::T105_Z },
6357 { R600::T106_Z },
6358 { R600::T107_Z },
6359 { R600::T108_Z },
6360 { R600::T109_Z },
6361 { R600::T110_Z },
6362 { R600::T111_Z },
6363 { R600::T112_Z },
6364 { R600::T113_Z },
6365 { R600::T114_Z },
6366 { R600::T115_Z },
6367 { R600::T116_Z },
6368 { R600::T117_Z },
6369 { R600::T118_Z },
6370 { R600::T119_Z },
6371 { R600::T120_Z },
6372 { R600::T121_Z },
6373 { R600::T122_Z },
6374 { R600::T123_Z },
6375 { R600::T124_Z },
6376 { R600::T125_Z },
6377 { R600::T126_Z },
6378 { R600::T127_Z },
6379 { R600::KC0_128_W },
6380 { R600::KC0_129_W },
6381 { R600::KC0_130_W },
6382 { R600::KC0_131_W },
6383 { R600::KC0_132_W },
6384 { R600::KC0_133_W },
6385 { R600::KC0_134_W },
6386 { R600::KC0_135_W },
6387 { R600::KC0_136_W },
6388 { R600::KC0_137_W },
6389 { R600::KC0_138_W },
6390 { R600::KC0_139_W },
6391 { R600::KC0_140_W },
6392 { R600::KC0_141_W },
6393 { R600::KC0_142_W },
6394 { R600::KC0_143_W },
6395 { R600::KC0_144_W },
6396 { R600::KC0_145_W },
6397 { R600::KC0_146_W },
6398 { R600::KC0_147_W },
6399 { R600::KC0_148_W },
6400 { R600::KC0_149_W },
6401 { R600::KC0_150_W },
6402 { R600::KC0_151_W },
6403 { R600::KC0_152_W },
6404 { R600::KC0_153_W },
6405 { R600::KC0_154_W },
6406 { R600::KC0_155_W },
6407 { R600::KC0_156_W },
6408 { R600::KC0_157_W },
6409 { R600::KC0_158_W },
6410 { R600::KC0_159_W },
6411 { R600::KC1_160_W },
6412 { R600::KC1_161_W },
6413 { R600::KC1_162_W },
6414 { R600::KC1_163_W },
6415 { R600::KC1_164_W },
6416 { R600::KC1_165_W },
6417 { R600::KC1_166_W },
6418 { R600::KC1_167_W },
6419 { R600::KC1_168_W },
6420 { R600::KC1_169_W },
6421 { R600::KC1_170_W },
6422 { R600::KC1_171_W },
6423 { R600::KC1_172_W },
6424 { R600::KC1_173_W },
6425 { R600::KC1_174_W },
6426 { R600::KC1_175_W },
6427 { R600::KC1_176_W },
6428 { R600::KC1_177_W },
6429 { R600::KC1_178_W },
6430 { R600::KC1_179_W },
6431 { R600::KC1_180_W },
6432 { R600::KC1_181_W },
6433 { R600::KC1_182_W },
6434 { R600::KC1_183_W },
6435 { R600::KC1_184_W },
6436 { R600::KC1_185_W },
6437 { R600::KC1_186_W },
6438 { R600::KC1_187_W },
6439 { R600::KC1_188_W },
6440 { R600::KC1_189_W },
6441 { R600::KC1_190_W },
6442 { R600::KC1_191_W },
6443 { R600::KC0_128_X },
6444 { R600::KC0_129_X },
6445 { R600::KC0_130_X },
6446 { R600::KC0_131_X },
6447 { R600::KC0_132_X },
6448 { R600::KC0_133_X },
6449 { R600::KC0_134_X },
6450 { R600::KC0_135_X },
6451 { R600::KC0_136_X },
6452 { R600::KC0_137_X },
6453 { R600::KC0_138_X },
6454 { R600::KC0_139_X },
6455 { R600::KC0_140_X },
6456 { R600::KC0_141_X },
6457 { R600::KC0_142_X },
6458 { R600::KC0_143_X },
6459 { R600::KC0_144_X },
6460 { R600::KC0_145_X },
6461 { R600::KC0_146_X },
6462 { R600::KC0_147_X },
6463 { R600::KC0_148_X },
6464 { R600::KC0_149_X },
6465 { R600::KC0_150_X },
6466 { R600::KC0_151_X },
6467 { R600::KC0_152_X },
6468 { R600::KC0_153_X },
6469 { R600::KC0_154_X },
6470 { R600::KC0_155_X },
6471 { R600::KC0_156_X },
6472 { R600::KC0_157_X },
6473 { R600::KC0_158_X },
6474 { R600::KC0_159_X },
6475 { R600::KC1_160_X },
6476 { R600::KC1_161_X },
6477 { R600::KC1_162_X },
6478 { R600::KC1_163_X },
6479 { R600::KC1_164_X },
6480 { R600::KC1_165_X },
6481 { R600::KC1_166_X },
6482 { R600::KC1_167_X },
6483 { R600::KC1_168_X },
6484 { R600::KC1_169_X },
6485 { R600::KC1_170_X },
6486 { R600::KC1_171_X },
6487 { R600::KC1_172_X },
6488 { R600::KC1_173_X },
6489 { R600::KC1_174_X },
6490 { R600::KC1_175_X },
6491 { R600::KC1_176_X },
6492 { R600::KC1_177_X },
6493 { R600::KC1_178_X },
6494 { R600::KC1_179_X },
6495 { R600::KC1_180_X },
6496 { R600::KC1_181_X },
6497 { R600::KC1_182_X },
6498 { R600::KC1_183_X },
6499 { R600::KC1_184_X },
6500 { R600::KC1_185_X },
6501 { R600::KC1_186_X },
6502 { R600::KC1_187_X },
6503 { R600::KC1_188_X },
6504 { R600::KC1_189_X },
6505 { R600::KC1_190_X },
6506 { R600::KC1_191_X },
6507 { R600::KC0_128_Y },
6508 { R600::KC0_128_Z },
6509 { R600::KC0_129_Y },
6510 { R600::KC0_129_Z },
6511 { R600::KC0_130_Y },
6512 { R600::KC0_130_Z },
6513 { R600::KC0_131_Y },
6514 { R600::KC0_131_Z },
6515 { R600::KC0_132_Y },
6516 { R600::KC0_132_Z },
6517 { R600::KC0_133_Y },
6518 { R600::KC0_133_Z },
6519 { R600::KC0_134_Y },
6520 { R600::KC0_134_Z },
6521 { R600::KC0_135_Y },
6522 { R600::KC0_135_Z },
6523 { R600::KC0_136_Y },
6524 { R600::KC0_136_Z },
6525 { R600::KC0_137_Y },
6526 { R600::KC0_137_Z },
6527 { R600::KC0_138_Y },
6528 { R600::KC0_138_Z },
6529 { R600::KC0_139_Y },
6530 { R600::KC0_139_Z },
6531 { R600::KC0_140_Y },
6532 { R600::KC0_140_Z },
6533 { R600::KC0_141_Y },
6534 { R600::KC0_141_Z },
6535 { R600::KC0_142_Y },
6536 { R600::KC0_142_Z },
6537 { R600::KC0_143_Y },
6538 { R600::KC0_143_Z },
6539 { R600::KC0_144_Y },
6540 { R600::KC0_144_Z },
6541 { R600::KC0_145_Y },
6542 { R600::KC0_145_Z },
6543 { R600::KC0_146_Y },
6544 { R600::KC0_146_Z },
6545 { R600::KC0_147_Y },
6546 { R600::KC0_147_Z },
6547 { R600::KC0_148_Y },
6548 { R600::KC0_148_Z },
6549 { R600::KC0_149_Y },
6550 { R600::KC0_149_Z },
6551 { R600::KC0_150_Y },
6552 { R600::KC0_150_Z },
6553 { R600::KC0_151_Y },
6554 { R600::KC0_151_Z },
6555 { R600::KC0_152_Y },
6556 { R600::KC0_152_Z },
6557 { R600::KC0_153_Y },
6558 { R600::KC0_153_Z },
6559 { R600::KC0_154_Y },
6560 { R600::KC0_154_Z },
6561 { R600::KC0_155_Y },
6562 { R600::KC0_155_Z },
6563 { R600::KC0_156_Y },
6564 { R600::KC0_156_Z },
6565 { R600::KC0_157_Y },
6566 { R600::KC0_157_Z },
6567 { R600::KC0_158_Y },
6568 { R600::KC0_158_Z },
6569 { R600::KC0_159_Y },
6570 { R600::KC0_159_Z },
6571 { R600::KC1_160_Y },
6572 { R600::KC1_160_Z },
6573 { R600::KC1_161_Y },
6574 { R600::KC1_161_Z },
6575 { R600::KC1_162_Y },
6576 { R600::KC1_162_Z },
6577 { R600::KC1_163_Y },
6578 { R600::KC1_163_Z },
6579 { R600::KC1_164_Y },
6580 { R600::KC1_164_Z },
6581 { R600::KC1_165_Y },
6582 { R600::KC1_165_Z },
6583 { R600::KC1_166_Y },
6584 { R600::KC1_166_Z },
6585 { R600::KC1_167_Y },
6586 { R600::KC1_167_Z },
6587 { R600::KC1_168_Y },
6588 { R600::KC1_168_Z },
6589 { R600::KC1_169_Y },
6590 { R600::KC1_169_Z },
6591 { R600::KC1_170_Y },
6592 { R600::KC1_170_Z },
6593 { R600::KC1_171_Y },
6594 { R600::KC1_171_Z },
6595 { R600::KC1_172_Y },
6596 { R600::KC1_172_Z },
6597 { R600::KC1_173_Y },
6598 { R600::KC1_173_Z },
6599 { R600::KC1_174_Y },
6600 { R600::KC1_174_Z },
6601 { R600::KC1_175_Y },
6602 { R600::KC1_175_Z },
6603 { R600::KC1_176_Y },
6604 { R600::KC1_176_Z },
6605 { R600::KC1_177_Y },
6606 { R600::KC1_177_Z },
6607 { R600::KC1_178_Y },
6608 { R600::KC1_178_Z },
6609 { R600::KC1_179_Y },
6610 { R600::KC1_179_Z },
6611 { R600::KC1_180_Y },
6612 { R600::KC1_180_Z },
6613 { R600::KC1_181_Y },
6614 { R600::KC1_181_Z },
6615 { R600::KC1_182_Y },
6616 { R600::KC1_182_Z },
6617 { R600::KC1_183_Y },
6618 { R600::KC1_183_Z },
6619 { R600::KC1_184_Y },
6620 { R600::KC1_184_Z },
6621 { R600::KC1_185_Y },
6622 { R600::KC1_185_Z },
6623 { R600::KC1_186_Y },
6624 { R600::KC1_186_Z },
6625 { R600::KC1_187_Y },
6626 { R600::KC1_187_Z },
6627 { R600::KC1_188_Y },
6628 { R600::KC1_188_Z },
6629 { R600::KC1_189_Y },
6630 { R600::KC1_189_Z },
6631 { R600::KC1_190_Y },
6632 { R600::KC1_190_Z },
6633 { R600::KC1_191_Y },
6634 { R600::KC1_191_Z },
6635};
6636
6637namespace { // Register classes...
6638 // R600_Reg32 Register Class...
6639 const MCPhysReg R600_Reg32[] = {
6640 R600::T0_X, R600::T0_Y, R600::T0_Z, R600::T0_W, R600::T1_X, R600::T1_Y, R600::T1_Z, R600::T1_W, R600::T2_X, R600::T2_Y, R600::T2_Z, R600::T2_W, R600::T3_X, R600::T3_Y, R600::T3_Z, R600::T3_W, R600::T4_X, R600::T4_Y, R600::T4_Z, R600::T4_W, R600::T5_X, R600::T5_Y, R600::T5_Z, R600::T5_W, R600::T6_X, R600::T6_Y, R600::T6_Z, R600::T6_W, R600::T7_X, R600::T7_Y, R600::T7_Z, R600::T7_W, R600::T8_X, R600::T8_Y, R600::T8_Z, R600::T8_W, R600::T9_X, R600::T9_Y, R600::T9_Z, R600::T9_W, R600::T10_X, R600::T10_Y, R600::T10_Z, R600::T10_W, R600::T11_X, R600::T11_Y, R600::T11_Z, R600::T11_W, R600::T12_X, R600::T12_Y, R600::T12_Z, R600::T12_W, R600::T13_X, R600::T13_Y, R600::T13_Z, R600::T13_W, R600::T14_X, R600::T14_Y, R600::T14_Z, R600::T14_W, R600::T15_X, R600::T15_Y, R600::T15_Z, R600::T15_W, R600::T16_X, R600::T16_Y, R600::T16_Z, R600::T16_W, R600::T17_X, R600::T17_Y, R600::T17_Z, R600::T17_W, R600::T18_X, R600::T18_Y, R600::T18_Z, R600::T18_W, R600::T19_X, R600::T19_Y, R600::T19_Z, R600::T19_W, R600::T20_X, R600::T20_Y, R600::T20_Z, R600::T20_W, R600::T21_X, R600::T21_Y, R600::T21_Z, R600::T21_W, R600::T22_X, R600::T22_Y, R600::T22_Z, R600::T22_W, R600::T23_X, R600::T23_Y, R600::T23_Z, R600::T23_W, R600::T24_X, R600::T24_Y, R600::T24_Z, R600::T24_W, R600::T25_X, R600::T25_Y, R600::T25_Z, R600::T25_W, R600::T26_X, R600::T26_Y, R600::T26_Z, R600::T26_W, R600::T27_X, R600::T27_Y, R600::T27_Z, R600::T27_W, R600::T28_X, R600::T28_Y, R600::T28_Z, R600::T28_W, R600::T29_X, R600::T29_Y, R600::T29_Z, R600::T29_W, R600::T30_X, R600::T30_Y, R600::T30_Z, R600::T30_W, R600::T31_X, R600::T31_Y, R600::T31_Z, R600::T31_W, R600::T32_X, R600::T32_Y, R600::T32_Z, R600::T32_W, R600::T33_X, R600::T33_Y, R600::T33_Z, R600::T33_W, R600::T34_X, R600::T34_Y, R600::T34_Z, R600::T34_W, R600::T35_X, R600::T35_Y, R600::T35_Z, R600::T35_W, R600::T36_X, R600::T36_Y, R600::T36_Z, R600::T36_W, R600::T37_X, R600::T37_Y, R600::T37_Z, R600::T37_W, R600::T38_X, R600::T38_Y, R600::T38_Z, R600::T38_W, R600::T39_X, R600::T39_Y, R600::T39_Z, R600::T39_W, R600::T40_X, R600::T40_Y, R600::T40_Z, R600::T40_W, R600::T41_X, R600::T41_Y, R600::T41_Z, R600::T41_W, R600::T42_X, R600::T42_Y, R600::T42_Z, R600::T42_W, R600::T43_X, R600::T43_Y, R600::T43_Z, R600::T43_W, R600::T44_X, R600::T44_Y, R600::T44_Z, R600::T44_W, R600::T45_X, R600::T45_Y, R600::T45_Z, R600::T45_W, R600::T46_X, R600::T46_Y, R600::T46_Z, R600::T46_W, R600::T47_X, R600::T47_Y, R600::T47_Z, R600::T47_W, R600::T48_X, R600::T48_Y, R600::T48_Z, R600::T48_W, R600::T49_X, R600::T49_Y, R600::T49_Z, R600::T49_W, R600::T50_X, R600::T50_Y, R600::T50_Z, R600::T50_W, R600::T51_X, R600::T51_Y, R600::T51_Z, R600::T51_W, R600::T52_X, R600::T52_Y, R600::T52_Z, R600::T52_W, R600::T53_X, R600::T53_Y, R600::T53_Z, R600::T53_W, R600::T54_X, R600::T54_Y, R600::T54_Z, R600::T54_W, R600::T55_X, R600::T55_Y, R600::T55_Z, R600::T55_W, R600::T56_X, R600::T56_Y, R600::T56_Z, R600::T56_W, R600::T57_X, R600::T57_Y, R600::T57_Z, R600::T57_W, R600::T58_X, R600::T58_Y, R600::T58_Z, R600::T58_W, R600::T59_X, R600::T59_Y, R600::T59_Z, R600::T59_W, R600::T60_X, R600::T60_Y, R600::T60_Z, R600::T60_W, R600::T61_X, R600::T61_Y, R600::T61_Z, R600::T61_W, R600::T62_X, R600::T62_Y, R600::T62_Z, R600::T62_W, R600::T63_X, R600::T63_Y, R600::T63_Z, R600::T63_W, R600::T64_X, R600::T64_Y, R600::T64_Z, R600::T64_W, R600::T65_X, R600::T65_Y, R600::T65_Z, R600::T65_W, R600::T66_X, R600::T66_Y, R600::T66_Z, R600::T66_W, R600::T67_X, R600::T67_Y, R600::T67_Z, R600::T67_W, R600::T68_X, R600::T68_Y, R600::T68_Z, R600::T68_W, R600::T69_X, R600::T69_Y, R600::T69_Z, R600::T69_W, R600::T70_X, R600::T70_Y, R600::T70_Z, R600::T70_W, R600::T71_X, R600::T71_Y, R600::T71_Z, R600::T71_W, R600::T72_X, R600::T72_Y, R600::T72_Z, R600::T72_W, R600::T73_X, R600::T73_Y, R600::T73_Z, R600::T73_W, R600::T74_X, R600::T74_Y, R600::T74_Z, R600::T74_W, R600::T75_X, R600::T75_Y, R600::T75_Z, R600::T75_W, R600::T76_X, R600::T76_Y, R600::T76_Z, R600::T76_W, R600::T77_X, R600::T77_Y, R600::T77_Z, R600::T77_W, R600::T78_X, R600::T78_Y, R600::T78_Z, R600::T78_W, R600::T79_X, R600::T79_Y, R600::T79_Z, R600::T79_W, R600::T80_X, R600::T80_Y, R600::T80_Z, R600::T80_W, R600::T81_X, R600::T81_Y, R600::T81_Z, R600::T81_W, R600::T82_X, R600::T82_Y, R600::T82_Z, R600::T82_W, R600::T83_X, R600::T83_Y, R600::T83_Z, R600::T83_W, R600::T84_X, R600::T84_Y, R600::T84_Z, R600::T84_W, R600::T85_X, R600::T85_Y, R600::T85_Z, R600::T85_W, R600::T86_X, R600::T86_Y, R600::T86_Z, R600::T86_W, R600::T87_X, R600::T87_Y, R600::T87_Z, R600::T87_W, R600::T88_X, R600::T88_Y, R600::T88_Z, R600::T88_W, R600::T89_X, R600::T89_Y, R600::T89_Z, R600::T89_W, R600::T90_X, R600::T90_Y, R600::T90_Z, R600::T90_W, R600::T91_X, R600::T91_Y, R600::T91_Z, R600::T91_W, R600::T92_X, R600::T92_Y, R600::T92_Z, R600::T92_W, R600::T93_X, R600::T93_Y, R600::T93_Z, R600::T93_W, R600::T94_X, R600::T94_Y, R600::T94_Z, R600::T94_W, R600::T95_X, R600::T95_Y, R600::T95_Z, R600::T95_W, R600::T96_X, R600::T96_Y, R600::T96_Z, R600::T96_W, R600::T97_X, R600::T97_Y, R600::T97_Z, R600::T97_W, R600::T98_X, R600::T98_Y, R600::T98_Z, R600::T98_W, R600::T99_X, R600::T99_Y, R600::T99_Z, R600::T99_W, R600::T100_X, R600::T100_Y, R600::T100_Z, R600::T100_W, R600::T101_X, R600::T101_Y, R600::T101_Z, R600::T101_W, R600::T102_X, R600::T102_Y, R600::T102_Z, R600::T102_W, R600::T103_X, R600::T103_Y, R600::T103_Z, R600::T103_W, R600::T104_X, R600::T104_Y, R600::T104_Z, R600::T104_W, R600::T105_X, R600::T105_Y, R600::T105_Z, R600::T105_W, R600::T106_X, R600::T106_Y, R600::T106_Z, R600::T106_W, R600::T107_X, R600::T107_Y, R600::T107_Z, R600::T107_W, R600::T108_X, R600::T108_Y, R600::T108_Z, R600::T108_W, R600::T109_X, R600::T109_Y, R600::T109_Z, R600::T109_W, R600::T110_X, R600::T110_Y, R600::T110_Z, R600::T110_W, R600::T111_X, R600::T111_Y, R600::T111_Z, R600::T111_W, R600::T112_X, R600::T112_Y, R600::T112_Z, R600::T112_W, R600::T113_X, R600::T113_Y, R600::T113_Z, R600::T113_W, R600::T114_X, R600::T114_Y, R600::T114_Z, R600::T114_W, R600::T115_X, R600::T115_Y, R600::T115_Z, R600::T115_W, R600::T116_X, R600::T116_Y, R600::T116_Z, R600::T116_W, R600::T117_X, R600::T117_Y, R600::T117_Z, R600::T117_W, R600::T118_X, R600::T118_Y, R600::T118_Z, R600::T118_W, R600::T119_X, R600::T119_Y, R600::T119_Z, R600::T119_W, R600::T120_X, R600::T120_Y, R600::T120_Z, R600::T120_W, R600::T121_X, R600::T121_Y, R600::T121_Z, R600::T121_W, R600::T122_X, R600::T122_Y, R600::T122_Z, R600::T122_W, R600::T123_X, R600::T123_Y, R600::T123_Z, R600::T123_W, R600::T124_X, R600::T124_Y, R600::T124_Z, R600::T124_W, R600::T125_X, R600::T125_Y, R600::T125_Z, R600::T125_W, R600::T126_X, R600::T126_Y, R600::T126_Z, R600::T126_W, R600::T127_X, R600::T127_Y, R600::T127_Z, R600::T127_W, R600::AR_X, R600::ArrayBase448, R600::ArrayBase449, R600::ArrayBase450, R600::ArrayBase451, R600::ArrayBase452, R600::ArrayBase453, R600::ArrayBase454, R600::ArrayBase455, R600::ArrayBase456, R600::ArrayBase457, R600::ArrayBase458, R600::ArrayBase459, R600::ArrayBase460, R600::ArrayBase461, R600::ArrayBase462, R600::ArrayBase463, R600::ArrayBase464, R600::ArrayBase465, R600::ArrayBase466, R600::ArrayBase467, R600::ArrayBase468, R600::ArrayBase469, R600::ArrayBase470, R600::ArrayBase471, R600::ArrayBase472, R600::ArrayBase473, R600::ArrayBase474, R600::ArrayBase475, R600::ArrayBase476, R600::ArrayBase477, R600::ArrayBase478, R600::ArrayBase479, R600::ArrayBase480, R600::Addr0_X, R600::Addr1_X, R600::Addr2_X, R600::Addr3_X, R600::Addr4_X, R600::Addr5_X, R600::Addr6_X, R600::Addr7_X, R600::Addr8_X, R600::Addr9_X, R600::Addr10_X, R600::Addr11_X, R600::Addr12_X, R600::Addr13_X, R600::Addr14_X, R600::Addr15_X, R600::Addr16_X, R600::Addr17_X, R600::Addr18_X, R600::Addr19_X, R600::Addr20_X, R600::Addr21_X, R600::Addr22_X, R600::Addr23_X, R600::Addr24_X, R600::Addr25_X, R600::Addr26_X, R600::Addr27_X, R600::Addr28_X, R600::Addr29_X, R600::Addr30_X, R600::Addr31_X, R600::Addr32_X, R600::Addr33_X, R600::Addr34_X, R600::Addr35_X, R600::Addr36_X, R600::Addr37_X, R600::Addr38_X, R600::Addr39_X, R600::Addr40_X, R600::Addr41_X, R600::Addr42_X, R600::Addr43_X, R600::Addr44_X, R600::Addr45_X, R600::Addr46_X, R600::Addr47_X, R600::Addr48_X, R600::Addr49_X, R600::Addr50_X, R600::Addr51_X, R600::Addr52_X, R600::Addr53_X, R600::Addr54_X, R600::Addr55_X, R600::Addr56_X, R600::Addr57_X, R600::Addr58_X, R600::Addr59_X, R600::Addr60_X, R600::Addr61_X, R600::Addr62_X, R600::Addr63_X, R600::Addr64_X, R600::Addr65_X, R600::Addr66_X, R600::Addr67_X, R600::Addr68_X, R600::Addr69_X, R600::Addr70_X, R600::Addr71_X, R600::Addr72_X, R600::Addr73_X, R600::Addr74_X, R600::Addr75_X, R600::Addr76_X, R600::Addr77_X, R600::Addr78_X, R600::Addr79_X, R600::Addr80_X, R600::Addr81_X, R600::Addr82_X, R600::Addr83_X, R600::Addr84_X, R600::Addr85_X, R600::Addr86_X, R600::Addr87_X, R600::Addr88_X, R600::Addr89_X, R600::Addr90_X, R600::Addr91_X, R600::Addr92_X, R600::Addr93_X, R600::Addr94_X, R600::Addr95_X, R600::Addr96_X, R600::Addr97_X, R600::Addr98_X, R600::Addr99_X, R600::Addr100_X, R600::Addr101_X, R600::Addr102_X, R600::Addr103_X, R600::Addr104_X, R600::Addr105_X, R600::Addr106_X, R600::Addr107_X, R600::Addr108_X, R600::Addr109_X, R600::Addr110_X, R600::Addr111_X, R600::Addr112_X, R600::Addr113_X, R600::Addr114_X, R600::Addr115_X, R600::Addr116_X, R600::Addr117_X, R600::Addr118_X, R600::Addr119_X, R600::Addr120_X, R600::Addr121_X, R600::Addr122_X, R600::Addr123_X, R600::Addr124_X, R600::Addr125_X, R600::Addr126_X, R600::Addr127_X, R600::KC0_128_X, R600::KC0_128_Y, R600::KC0_128_Z, R600::KC0_128_W, R600::KC0_129_X, R600::KC0_129_Y, R600::KC0_129_Z, R600::KC0_129_W, R600::KC0_130_X, R600::KC0_130_Y, R600::KC0_130_Z, R600::KC0_130_W, R600::KC0_131_X, R600::KC0_131_Y, R600::KC0_131_Z, R600::KC0_131_W, R600::KC0_132_X, R600::KC0_132_Y, R600::KC0_132_Z, R600::KC0_132_W, R600::KC0_133_X, R600::KC0_133_Y, R600::KC0_133_Z, R600::KC0_133_W, R600::KC0_134_X, R600::KC0_134_Y, R600::KC0_134_Z, R600::KC0_134_W, R600::KC0_135_X, R600::KC0_135_Y, R600::KC0_135_Z, R600::KC0_135_W, R600::KC0_136_X, R600::KC0_136_Y, R600::KC0_136_Z, R600::KC0_136_W, R600::KC0_137_X, R600::KC0_137_Y, R600::KC0_137_Z, R600::KC0_137_W, R600::KC0_138_X, R600::KC0_138_Y, R600::KC0_138_Z, R600::KC0_138_W, R600::KC0_139_X, R600::KC0_139_Y, R600::KC0_139_Z, R600::KC0_139_W, R600::KC0_140_X, R600::KC0_140_Y, R600::KC0_140_Z, R600::KC0_140_W, R600::KC0_141_X, R600::KC0_141_Y, R600::KC0_141_Z, R600::KC0_141_W, R600::KC0_142_X, R600::KC0_142_Y, R600::KC0_142_Z, R600::KC0_142_W, R600::KC0_143_X, R600::KC0_143_Y, R600::KC0_143_Z, R600::KC0_143_W, R600::KC0_144_X, R600::KC0_144_Y, R600::KC0_144_Z, R600::KC0_144_W, R600::KC0_145_X, R600::KC0_145_Y, R600::KC0_145_Z, R600::KC0_145_W, R600::KC0_146_X, R600::KC0_146_Y, R600::KC0_146_Z, R600::KC0_146_W, R600::KC0_147_X, R600::KC0_147_Y, R600::KC0_147_Z, R600::KC0_147_W, R600::KC0_148_X, R600::KC0_148_Y, R600::KC0_148_Z, R600::KC0_148_W, R600::KC0_149_X, R600::KC0_149_Y, R600::KC0_149_Z, R600::KC0_149_W, R600::KC0_150_X, R600::KC0_150_Y, R600::KC0_150_Z, R600::KC0_150_W, R600::KC0_151_X, R600::KC0_151_Y, R600::KC0_151_Z, R600::KC0_151_W, R600::KC0_152_X, R600::KC0_152_Y, R600::KC0_152_Z, R600::KC0_152_W, R600::KC0_153_X, R600::KC0_153_Y, R600::KC0_153_Z, R600::KC0_153_W, R600::KC0_154_X, R600::KC0_154_Y, R600::KC0_154_Z, R600::KC0_154_W, R600::KC0_155_X, R600::KC0_155_Y, R600::KC0_155_Z, R600::KC0_155_W, R600::KC0_156_X, R600::KC0_156_Y, R600::KC0_156_Z, R600::KC0_156_W, R600::KC0_157_X, R600::KC0_157_Y, R600::KC0_157_Z, R600::KC0_157_W, R600::KC0_158_X, R600::KC0_158_Y, R600::KC0_158_Z, R600::KC0_158_W, R600::KC0_159_X, R600::KC0_159_Y, R600::KC0_159_Z, R600::KC0_159_W, R600::KC1_160_X, R600::KC1_160_Y, R600::KC1_160_Z, R600::KC1_160_W, R600::KC1_161_X, R600::KC1_161_Y, R600::KC1_161_Z, R600::KC1_161_W, R600::KC1_162_X, R600::KC1_162_Y, R600::KC1_162_Z, R600::KC1_162_W, R600::KC1_163_X, R600::KC1_163_Y, R600::KC1_163_Z, R600::KC1_163_W, R600::KC1_164_X, R600::KC1_164_Y, R600::KC1_164_Z, R600::KC1_164_W, R600::KC1_165_X, R600::KC1_165_Y, R600::KC1_165_Z, R600::KC1_165_W, R600::KC1_166_X, R600::KC1_166_Y, R600::KC1_166_Z, R600::KC1_166_W, R600::KC1_167_X, R600::KC1_167_Y, R600::KC1_167_Z, R600::KC1_167_W, R600::KC1_168_X, R600::KC1_168_Y, R600::KC1_168_Z, R600::KC1_168_W, R600::KC1_169_X, R600::KC1_169_Y, R600::KC1_169_Z, R600::KC1_169_W, R600::KC1_170_X, R600::KC1_170_Y, R600::KC1_170_Z, R600::KC1_170_W, R600::KC1_171_X, R600::KC1_171_Y, R600::KC1_171_Z, R600::KC1_171_W, R600::KC1_172_X, R600::KC1_172_Y, R600::KC1_172_Z, R600::KC1_172_W, R600::KC1_173_X, R600::KC1_173_Y, R600::KC1_173_Z, R600::KC1_173_W, R600::KC1_174_X, R600::KC1_174_Y, R600::KC1_174_Z, R600::KC1_174_W, R600::KC1_175_X, R600::KC1_175_Y, R600::KC1_175_Z, R600::KC1_175_W, R600::KC1_176_X, R600::KC1_176_Y, R600::KC1_176_Z, R600::KC1_176_W, R600::KC1_177_X, R600::KC1_177_Y, R600::KC1_177_Z, R600::KC1_177_W, R600::KC1_178_X, R600::KC1_178_Y, R600::KC1_178_Z, R600::KC1_178_W, R600::KC1_179_X, R600::KC1_179_Y, R600::KC1_179_Z, R600::KC1_179_W, R600::KC1_180_X, R600::KC1_180_Y, R600::KC1_180_Z, R600::KC1_180_W, R600::KC1_181_X, R600::KC1_181_Y, R600::KC1_181_Z, R600::KC1_181_W, R600::KC1_182_X, R600::KC1_182_Y, R600::KC1_182_Z, R600::KC1_182_W, R600::KC1_183_X, R600::KC1_183_Y, R600::KC1_183_Z, R600::KC1_183_W, R600::KC1_184_X, R600::KC1_184_Y, R600::KC1_184_Z, R600::KC1_184_W, R600::KC1_185_X, R600::KC1_185_Y, R600::KC1_185_Z, R600::KC1_185_W, R600::KC1_186_X, R600::KC1_186_Y, R600::KC1_186_Z, R600::KC1_186_W, R600::KC1_187_X, R600::KC1_187_Y, R600::KC1_187_Z, R600::KC1_187_W, R600::KC1_188_X, R600::KC1_188_Y, R600::KC1_188_Z, R600::KC1_188_W, R600::KC1_189_X, R600::KC1_189_Y, R600::KC1_189_Z, R600::KC1_189_W, R600::KC1_190_X, R600::KC1_190_Y, R600::KC1_190_Z, R600::KC1_190_W, R600::KC1_191_X, R600::KC1_191_Y, R600::KC1_191_Z, R600::KC1_191_W, R600::ZERO, R600::HALF, R600::ONE, R600::ONE_INT, R600::PV_X, R600::ALU_LITERAL_X, R600::NEG_ONE, R600::NEG_HALF, R600::ALU_CONST, R600::ALU_PARAM, R600::OQAP, R600::INDIRECT_BASE_ADDR,
6641 };
6642
6643 // R600_Reg32 Bit set.
6644 const uint8_t R600_Reg32Bits[] = {
6645 0xca, 0xf3, 0x02, 0xe4, 0xff, 0xff, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, 0x00, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x07,
6646 };
6647
6648 // R600_TReg32 Register Class...
6649 const MCPhysReg R600_TReg32[] = {
6650 R600::T0_X, R600::T0_Y, R600::T0_Z, R600::T0_W, R600::T1_X, R600::T1_Y, R600::T1_Z, R600::T1_W, R600::T2_X, R600::T2_Y, R600::T2_Z, R600::T2_W, R600::T3_X, R600::T3_Y, R600::T3_Z, R600::T3_W, R600::T4_X, R600::T4_Y, R600::T4_Z, R600::T4_W, R600::T5_X, R600::T5_Y, R600::T5_Z, R600::T5_W, R600::T6_X, R600::T6_Y, R600::T6_Z, R600::T6_W, R600::T7_X, R600::T7_Y, R600::T7_Z, R600::T7_W, R600::T8_X, R600::T8_Y, R600::T8_Z, R600::T8_W, R600::T9_X, R600::T9_Y, R600::T9_Z, R600::T9_W, R600::T10_X, R600::T10_Y, R600::T10_Z, R600::T10_W, R600::T11_X, R600::T11_Y, R600::T11_Z, R600::T11_W, R600::T12_X, R600::T12_Y, R600::T12_Z, R600::T12_W, R600::T13_X, R600::T13_Y, R600::T13_Z, R600::T13_W, R600::T14_X, R600::T14_Y, R600::T14_Z, R600::T14_W, R600::T15_X, R600::T15_Y, R600::T15_Z, R600::T15_W, R600::T16_X, R600::T16_Y, R600::T16_Z, R600::T16_W, R600::T17_X, R600::T17_Y, R600::T17_Z, R600::T17_W, R600::T18_X, R600::T18_Y, R600::T18_Z, R600::T18_W, R600::T19_X, R600::T19_Y, R600::T19_Z, R600::T19_W, R600::T20_X, R600::T20_Y, R600::T20_Z, R600::T20_W, R600::T21_X, R600::T21_Y, R600::T21_Z, R600::T21_W, R600::T22_X, R600::T22_Y, R600::T22_Z, R600::T22_W, R600::T23_X, R600::T23_Y, R600::T23_Z, R600::T23_W, R600::T24_X, R600::T24_Y, R600::T24_Z, R600::T24_W, R600::T25_X, R600::T25_Y, R600::T25_Z, R600::T25_W, R600::T26_X, R600::T26_Y, R600::T26_Z, R600::T26_W, R600::T27_X, R600::T27_Y, R600::T27_Z, R600::T27_W, R600::T28_X, R600::T28_Y, R600::T28_Z, R600::T28_W, R600::T29_X, R600::T29_Y, R600::T29_Z, R600::T29_W, R600::T30_X, R600::T30_Y, R600::T30_Z, R600::T30_W, R600::T31_X, R600::T31_Y, R600::T31_Z, R600::T31_W, R600::T32_X, R600::T32_Y, R600::T32_Z, R600::T32_W, R600::T33_X, R600::T33_Y, R600::T33_Z, R600::T33_W, R600::T34_X, R600::T34_Y, R600::T34_Z, R600::T34_W, R600::T35_X, R600::T35_Y, R600::T35_Z, R600::T35_W, R600::T36_X, R600::T36_Y, R600::T36_Z, R600::T36_W, R600::T37_X, R600::T37_Y, R600::T37_Z, R600::T37_W, R600::T38_X, R600::T38_Y, R600::T38_Z, R600::T38_W, R600::T39_X, R600::T39_Y, R600::T39_Z, R600::T39_W, R600::T40_X, R600::T40_Y, R600::T40_Z, R600::T40_W, R600::T41_X, R600::T41_Y, R600::T41_Z, R600::T41_W, R600::T42_X, R600::T42_Y, R600::T42_Z, R600::T42_W, R600::T43_X, R600::T43_Y, R600::T43_Z, R600::T43_W, R600::T44_X, R600::T44_Y, R600::T44_Z, R600::T44_W, R600::T45_X, R600::T45_Y, R600::T45_Z, R600::T45_W, R600::T46_X, R600::T46_Y, R600::T46_Z, R600::T46_W, R600::T47_X, R600::T47_Y, R600::T47_Z, R600::T47_W, R600::T48_X, R600::T48_Y, R600::T48_Z, R600::T48_W, R600::T49_X, R600::T49_Y, R600::T49_Z, R600::T49_W, R600::T50_X, R600::T50_Y, R600::T50_Z, R600::T50_W, R600::T51_X, R600::T51_Y, R600::T51_Z, R600::T51_W, R600::T52_X, R600::T52_Y, R600::T52_Z, R600::T52_W, R600::T53_X, R600::T53_Y, R600::T53_Z, R600::T53_W, R600::T54_X, R600::T54_Y, R600::T54_Z, R600::T54_W, R600::T55_X, R600::T55_Y, R600::T55_Z, R600::T55_W, R600::T56_X, R600::T56_Y, R600::T56_Z, R600::T56_W, R600::T57_X, R600::T57_Y, R600::T57_Z, R600::T57_W, R600::T58_X, R600::T58_Y, R600::T58_Z, R600::T58_W, R600::T59_X, R600::T59_Y, R600::T59_Z, R600::T59_W, R600::T60_X, R600::T60_Y, R600::T60_Z, R600::T60_W, R600::T61_X, R600::T61_Y, R600::T61_Z, R600::T61_W, R600::T62_X, R600::T62_Y, R600::T62_Z, R600::T62_W, R600::T63_X, R600::T63_Y, R600::T63_Z, R600::T63_W, R600::T64_X, R600::T64_Y, R600::T64_Z, R600::T64_W, R600::T65_X, R600::T65_Y, R600::T65_Z, R600::T65_W, R600::T66_X, R600::T66_Y, R600::T66_Z, R600::T66_W, R600::T67_X, R600::T67_Y, R600::T67_Z, R600::T67_W, R600::T68_X, R600::T68_Y, R600::T68_Z, R600::T68_W, R600::T69_X, R600::T69_Y, R600::T69_Z, R600::T69_W, R600::T70_X, R600::T70_Y, R600::T70_Z, R600::T70_W, R600::T71_X, R600::T71_Y, R600::T71_Z, R600::T71_W, R600::T72_X, R600::T72_Y, R600::T72_Z, R600::T72_W, R600::T73_X, R600::T73_Y, R600::T73_Z, R600::T73_W, R600::T74_X, R600::T74_Y, R600::T74_Z, R600::T74_W, R600::T75_X, R600::T75_Y, R600::T75_Z, R600::T75_W, R600::T76_X, R600::T76_Y, R600::T76_Z, R600::T76_W, R600::T77_X, R600::T77_Y, R600::T77_Z, R600::T77_W, R600::T78_X, R600::T78_Y, R600::T78_Z, R600::T78_W, R600::T79_X, R600::T79_Y, R600::T79_Z, R600::T79_W, R600::T80_X, R600::T80_Y, R600::T80_Z, R600::T80_W, R600::T81_X, R600::T81_Y, R600::T81_Z, R600::T81_W, R600::T82_X, R600::T82_Y, R600::T82_Z, R600::T82_W, R600::T83_X, R600::T83_Y, R600::T83_Z, R600::T83_W, R600::T84_X, R600::T84_Y, R600::T84_Z, R600::T84_W, R600::T85_X, R600::T85_Y, R600::T85_Z, R600::T85_W, R600::T86_X, R600::T86_Y, R600::T86_Z, R600::T86_W, R600::T87_X, R600::T87_Y, R600::T87_Z, R600::T87_W, R600::T88_X, R600::T88_Y, R600::T88_Z, R600::T88_W, R600::T89_X, R600::T89_Y, R600::T89_Z, R600::T89_W, R600::T90_X, R600::T90_Y, R600::T90_Z, R600::T90_W, R600::T91_X, R600::T91_Y, R600::T91_Z, R600::T91_W, R600::T92_X, R600::T92_Y, R600::T92_Z, R600::T92_W, R600::T93_X, R600::T93_Y, R600::T93_Z, R600::T93_W, R600::T94_X, R600::T94_Y, R600::T94_Z, R600::T94_W, R600::T95_X, R600::T95_Y, R600::T95_Z, R600::T95_W, R600::T96_X, R600::T96_Y, R600::T96_Z, R600::T96_W, R600::T97_X, R600::T97_Y, R600::T97_Z, R600::T97_W, R600::T98_X, R600::T98_Y, R600::T98_Z, R600::T98_W, R600::T99_X, R600::T99_Y, R600::T99_Z, R600::T99_W, R600::T100_X, R600::T100_Y, R600::T100_Z, R600::T100_W, R600::T101_X, R600::T101_Y, R600::T101_Z, R600::T101_W, R600::T102_X, R600::T102_Y, R600::T102_Z, R600::T102_W, R600::T103_X, R600::T103_Y, R600::T103_Z, R600::T103_W, R600::T104_X, R600::T104_Y, R600::T104_Z, R600::T104_W, R600::T105_X, R600::T105_Y, R600::T105_Z, R600::T105_W, R600::T106_X, R600::T106_Y, R600::T106_Z, R600::T106_W, R600::T107_X, R600::T107_Y, R600::T107_Z, R600::T107_W, R600::T108_X, R600::T108_Y, R600::T108_Z, R600::T108_W, R600::T109_X, R600::T109_Y, R600::T109_Z, R600::T109_W, R600::T110_X, R600::T110_Y, R600::T110_Z, R600::T110_W, R600::T111_X, R600::T111_Y, R600::T111_Z, R600::T111_W, R600::T112_X, R600::T112_Y, R600::T112_Z, R600::T112_W, R600::T113_X, R600::T113_Y, R600::T113_Z, R600::T113_W, R600::T114_X, R600::T114_Y, R600::T114_Z, R600::T114_W, R600::T115_X, R600::T115_Y, R600::T115_Z, R600::T115_W, R600::T116_X, R600::T116_Y, R600::T116_Z, R600::T116_W, R600::T117_X, R600::T117_Y, R600::T117_Z, R600::T117_W, R600::T118_X, R600::T118_Y, R600::T118_Z, R600::T118_W, R600::T119_X, R600::T119_Y, R600::T119_Z, R600::T119_W, R600::T120_X, R600::T120_Y, R600::T120_Z, R600::T120_W, R600::T121_X, R600::T121_Y, R600::T121_Z, R600::T121_W, R600::T122_X, R600::T122_Y, R600::T122_Z, R600::T122_W, R600::T123_X, R600::T123_Y, R600::T123_Z, R600::T123_W, R600::T124_X, R600::T124_Y, R600::T124_Z, R600::T124_W, R600::T125_X, R600::T125_Y, R600::T125_Z, R600::T125_W, R600::T126_X, R600::T126_Y, R600::T126_Z, R600::T126_W, R600::T127_X, R600::T127_Y, R600::T127_Z, R600::T127_W, R600::AR_X,
6651 };
6652
6653 // R600_TReg32 Bit set.
6654 const uint8_t R600_TReg32Bits[] = {
6655 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f,
6656 };
6657
6658 // R600_TReg32_X Register Class...
6659 const MCPhysReg R600_TReg32_X[] = {
6660 R600::T0_X, R600::T1_X, R600::T2_X, R600::T3_X, R600::T4_X, R600::T5_X, R600::T6_X, R600::T7_X, R600::T8_X, R600::T9_X, R600::T10_X, R600::T11_X, R600::T12_X, R600::T13_X, R600::T14_X, R600::T15_X, R600::T16_X, R600::T17_X, R600::T18_X, R600::T19_X, R600::T20_X, R600::T21_X, R600::T22_X, R600::T23_X, R600::T24_X, R600::T25_X, R600::T26_X, R600::T27_X, R600::T28_X, R600::T29_X, R600::T30_X, R600::T31_X, R600::T32_X, R600::T33_X, R600::T34_X, R600::T35_X, R600::T36_X, R600::T37_X, R600::T38_X, R600::T39_X, R600::T40_X, R600::T41_X, R600::T42_X, R600::T43_X, R600::T44_X, R600::T45_X, R600::T46_X, R600::T47_X, R600::T48_X, R600::T49_X, R600::T50_X, R600::T51_X, R600::T52_X, R600::T53_X, R600::T54_X, R600::T55_X, R600::T56_X, R600::T57_X, R600::T58_X, R600::T59_X, R600::T60_X, R600::T61_X, R600::T62_X, R600::T63_X, R600::T64_X, R600::T65_X, R600::T66_X, R600::T67_X, R600::T68_X, R600::T69_X, R600::T70_X, R600::T71_X, R600::T72_X, R600::T73_X, R600::T74_X, R600::T75_X, R600::T76_X, R600::T77_X, R600::T78_X, R600::T79_X, R600::T80_X, R600::T81_X, R600::T82_X, R600::T83_X, R600::T84_X, R600::T85_X, R600::T86_X, R600::T87_X, R600::T88_X, R600::T89_X, R600::T90_X, R600::T91_X, R600::T92_X, R600::T93_X, R600::T94_X, R600::T95_X, R600::T96_X, R600::T97_X, R600::T98_X, R600::T99_X, R600::T100_X, R600::T101_X, R600::T102_X, R600::T103_X, R600::T104_X, R600::T105_X, R600::T106_X, R600::T107_X, R600::T108_X, R600::T109_X, R600::T110_X, R600::T111_X, R600::T112_X, R600::T113_X, R600::T114_X, R600::T115_X, R600::T116_X, R600::T117_X, R600::T118_X, R600::T119_X, R600::T120_X, R600::T121_X, R600::T122_X, R600::T123_X, R600::T124_X, R600::T125_X, R600::T126_X, R600::T127_X, R600::AR_X,
6661 };
6662
6663 // R600_TReg32_X Bit set.
6664 const uint8_t R600_TReg32_XBits[] = {
6665 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f,
6666 };
6667
6668 // R600_Addr Register Class...
6669 const MCPhysReg R600_Addr[] = {
6670 R600::Addr0_X, R600::Addr1_X, R600::Addr2_X, R600::Addr3_X, R600::Addr4_X, R600::Addr5_X, R600::Addr6_X, R600::Addr7_X, R600::Addr8_X, R600::Addr9_X, R600::Addr10_X, R600::Addr11_X, R600::Addr12_X, R600::Addr13_X, R600::Addr14_X, R600::Addr15_X, R600::Addr16_X, R600::Addr17_X, R600::Addr18_X, R600::Addr19_X, R600::Addr20_X, R600::Addr21_X, R600::Addr22_X, R600::Addr23_X, R600::Addr24_X, R600::Addr25_X, R600::Addr26_X, R600::Addr27_X, R600::Addr28_X, R600::Addr29_X, R600::Addr30_X, R600::Addr31_X, R600::Addr32_X, R600::Addr33_X, R600::Addr34_X, R600::Addr35_X, R600::Addr36_X, R600::Addr37_X, R600::Addr38_X, R600::Addr39_X, R600::Addr40_X, R600::Addr41_X, R600::Addr42_X, R600::Addr43_X, R600::Addr44_X, R600::Addr45_X, R600::Addr46_X, R600::Addr47_X, R600::Addr48_X, R600::Addr49_X, R600::Addr50_X, R600::Addr51_X, R600::Addr52_X, R600::Addr53_X, R600::Addr54_X, R600::Addr55_X, R600::Addr56_X, R600::Addr57_X, R600::Addr58_X, R600::Addr59_X, R600::Addr60_X, R600::Addr61_X, R600::Addr62_X, R600::Addr63_X, R600::Addr64_X, R600::Addr65_X, R600::Addr66_X, R600::Addr67_X, R600::Addr68_X, R600::Addr69_X, R600::Addr70_X, R600::Addr71_X, R600::Addr72_X, R600::Addr73_X, R600::Addr74_X, R600::Addr75_X, R600::Addr76_X, R600::Addr77_X, R600::Addr78_X, R600::Addr79_X, R600::Addr80_X, R600::Addr81_X, R600::Addr82_X, R600::Addr83_X, R600::Addr84_X, R600::Addr85_X, R600::Addr86_X, R600::Addr87_X, R600::Addr88_X, R600::Addr89_X, R600::Addr90_X, R600::Addr91_X, R600::Addr92_X, R600::Addr93_X, R600::Addr94_X, R600::Addr95_X, R600::Addr96_X, R600::Addr97_X, R600::Addr98_X, R600::Addr99_X, R600::Addr100_X, R600::Addr101_X, R600::Addr102_X, R600::Addr103_X, R600::Addr104_X, R600::Addr105_X, R600::Addr106_X, R600::Addr107_X, R600::Addr108_X, R600::Addr109_X, R600::Addr110_X, R600::Addr111_X, R600::Addr112_X, R600::Addr113_X, R600::Addr114_X, R600::Addr115_X, R600::Addr116_X, R600::Addr117_X, R600::Addr118_X, R600::Addr119_X, R600::Addr120_X, R600::Addr121_X, R600::Addr122_X, R600::Addr123_X, R600::Addr124_X, R600::Addr125_X, R600::Addr126_X, R600::Addr127_X,
6671 };
6672
6673 // R600_Addr Bit set.
6674 const uint8_t R600_AddrBits[] = {
6675 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f,
6676 };
6677
6678 // R600_KC0 Register Class...
6679 const MCPhysReg R600_KC0[] = {
6680 R600::KC0_128_X, R600::KC0_128_Y, R600::KC0_128_Z, R600::KC0_128_W, R600::KC0_129_X, R600::KC0_129_Y, R600::KC0_129_Z, R600::KC0_129_W, R600::KC0_130_X, R600::KC0_130_Y, R600::KC0_130_Z, R600::KC0_130_W, R600::KC0_131_X, R600::KC0_131_Y, R600::KC0_131_Z, R600::KC0_131_W, R600::KC0_132_X, R600::KC0_132_Y, R600::KC0_132_Z, R600::KC0_132_W, R600::KC0_133_X, R600::KC0_133_Y, R600::KC0_133_Z, R600::KC0_133_W, R600::KC0_134_X, R600::KC0_134_Y, R600::KC0_134_Z, R600::KC0_134_W, R600::KC0_135_X, R600::KC0_135_Y, R600::KC0_135_Z, R600::KC0_135_W, R600::KC0_136_X, R600::KC0_136_Y, R600::KC0_136_Z, R600::KC0_136_W, R600::KC0_137_X, R600::KC0_137_Y, R600::KC0_137_Z, R600::KC0_137_W, R600::KC0_138_X, R600::KC0_138_Y, R600::KC0_138_Z, R600::KC0_138_W, R600::KC0_139_X, R600::KC0_139_Y, R600::KC0_139_Z, R600::KC0_139_W, R600::KC0_140_X, R600::KC0_140_Y, R600::KC0_140_Z, R600::KC0_140_W, R600::KC0_141_X, R600::KC0_141_Y, R600::KC0_141_Z, R600::KC0_141_W, R600::KC0_142_X, R600::KC0_142_Y, R600::KC0_142_Z, R600::KC0_142_W, R600::KC0_143_X, R600::KC0_143_Y, R600::KC0_143_Z, R600::KC0_143_W, R600::KC0_144_X, R600::KC0_144_Y, R600::KC0_144_Z, R600::KC0_144_W, R600::KC0_145_X, R600::KC0_145_Y, R600::KC0_145_Z, R600::KC0_145_W, R600::KC0_146_X, R600::KC0_146_Y, R600::KC0_146_Z, R600::KC0_146_W, R600::KC0_147_X, R600::KC0_147_Y, R600::KC0_147_Z, R600::KC0_147_W, R600::KC0_148_X, R600::KC0_148_Y, R600::KC0_148_Z, R600::KC0_148_W, R600::KC0_149_X, R600::KC0_149_Y, R600::KC0_149_Z, R600::KC0_149_W, R600::KC0_150_X, R600::KC0_150_Y, R600::KC0_150_Z, R600::KC0_150_W, R600::KC0_151_X, R600::KC0_151_Y, R600::KC0_151_Z, R600::KC0_151_W, R600::KC0_152_X, R600::KC0_152_Y, R600::KC0_152_Z, R600::KC0_152_W, R600::KC0_153_X, R600::KC0_153_Y, R600::KC0_153_Z, R600::KC0_153_W, R600::KC0_154_X, R600::KC0_154_Y, R600::KC0_154_Z, R600::KC0_154_W, R600::KC0_155_X, R600::KC0_155_Y, R600::KC0_155_Z, R600::KC0_155_W, R600::KC0_156_X, R600::KC0_156_Y, R600::KC0_156_Z, R600::KC0_156_W, R600::KC0_157_X, R600::KC0_157_Y, R600::KC0_157_Z, R600::KC0_157_W, R600::KC0_158_X, R600::KC0_158_Y, R600::KC0_158_Z, R600::KC0_158_W, R600::KC0_159_X, R600::KC0_159_Y, R600::KC0_159_Z, R600::KC0_159_W,
6681 };
6682
6683 // R600_KC0 Bit set.
6684 const uint8_t R600_KC0Bits[] = {
6685 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
6686 };
6687
6688 // R600_KC1 Register Class...
6689 const MCPhysReg R600_KC1[] = {
6690 R600::KC1_160_X, R600::KC1_160_Y, R600::KC1_160_Z, R600::KC1_160_W, R600::KC1_161_X, R600::KC1_161_Y, R600::KC1_161_Z, R600::KC1_161_W, R600::KC1_162_X, R600::KC1_162_Y, R600::KC1_162_Z, R600::KC1_162_W, R600::KC1_163_X, R600::KC1_163_Y, R600::KC1_163_Z, R600::KC1_163_W, R600::KC1_164_X, R600::KC1_164_Y, R600::KC1_164_Z, R600::KC1_164_W, R600::KC1_165_X, R600::KC1_165_Y, R600::KC1_165_Z, R600::KC1_165_W, R600::KC1_166_X, R600::KC1_166_Y, R600::KC1_166_Z, R600::KC1_166_W, R600::KC1_167_X, R600::KC1_167_Y, R600::KC1_167_Z, R600::KC1_167_W, R600::KC1_168_X, R600::KC1_168_Y, R600::KC1_168_Z, R600::KC1_168_W, R600::KC1_169_X, R600::KC1_169_Y, R600::KC1_169_Z, R600::KC1_169_W, R600::KC1_170_X, R600::KC1_170_Y, R600::KC1_170_Z, R600::KC1_170_W, R600::KC1_171_X, R600::KC1_171_Y, R600::KC1_171_Z, R600::KC1_171_W, R600::KC1_172_X, R600::KC1_172_Y, R600::KC1_172_Z, R600::KC1_172_W, R600::KC1_173_X, R600::KC1_173_Y, R600::KC1_173_Z, R600::KC1_173_W, R600::KC1_174_X, R600::KC1_174_Y, R600::KC1_174_Z, R600::KC1_174_W, R600::KC1_175_X, R600::KC1_175_Y, R600::KC1_175_Z, R600::KC1_175_W, R600::KC1_176_X, R600::KC1_176_Y, R600::KC1_176_Z, R600::KC1_176_W, R600::KC1_177_X, R600::KC1_177_Y, R600::KC1_177_Z, R600::KC1_177_W, R600::KC1_178_X, R600::KC1_178_Y, R600::KC1_178_Z, R600::KC1_178_W, R600::KC1_179_X, R600::KC1_179_Y, R600::KC1_179_Z, R600::KC1_179_W, R600::KC1_180_X, R600::KC1_180_Y, R600::KC1_180_Z, R600::KC1_180_W, R600::KC1_181_X, R600::KC1_181_Y, R600::KC1_181_Z, R600::KC1_181_W, R600::KC1_182_X, R600::KC1_182_Y, R600::KC1_182_Z, R600::KC1_182_W, R600::KC1_183_X, R600::KC1_183_Y, R600::KC1_183_Z, R600::KC1_183_W, R600::KC1_184_X, R600::KC1_184_Y, R600::KC1_184_Z, R600::KC1_184_W, R600::KC1_185_X, R600::KC1_185_Y, R600::KC1_185_Z, R600::KC1_185_W, R600::KC1_186_X, R600::KC1_186_Y, R600::KC1_186_Z, R600::KC1_186_W, R600::KC1_187_X, R600::KC1_187_Y, R600::KC1_187_Z, R600::KC1_187_W, R600::KC1_188_X, R600::KC1_188_Y, R600::KC1_188_Z, R600::KC1_188_W, R600::KC1_189_X, R600::KC1_189_Y, R600::KC1_189_Z, R600::KC1_189_W, R600::KC1_190_X, R600::KC1_190_Y, R600::KC1_190_Z, R600::KC1_190_W, R600::KC1_191_X, R600::KC1_191_Y, R600::KC1_191_Z, R600::KC1_191_W,
6691 };
6692
6693 // R600_KC1 Bit set.
6694 const uint8_t R600_KC1Bits[] = {
6695 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
6696 };
6697
6698 // R600_TReg32_W Register Class...
6699 const MCPhysReg R600_TReg32_W[] = {
6700 R600::T0_W, R600::T1_W, R600::T2_W, R600::T3_W, R600::T4_W, R600::T5_W, R600::T6_W, R600::T7_W, R600::T8_W, R600::T9_W, R600::T10_W, R600::T11_W, R600::T12_W, R600::T13_W, R600::T14_W, R600::T15_W, R600::T16_W, R600::T17_W, R600::T18_W, R600::T19_W, R600::T20_W, R600::T21_W, R600::T22_W, R600::T23_W, R600::T24_W, R600::T25_W, R600::T26_W, R600::T27_W, R600::T28_W, R600::T29_W, R600::T30_W, R600::T31_W, R600::T32_W, R600::T33_W, R600::T34_W, R600::T35_W, R600::T36_W, R600::T37_W, R600::T38_W, R600::T39_W, R600::T40_W, R600::T41_W, R600::T42_W, R600::T43_W, R600::T44_W, R600::T45_W, R600::T46_W, R600::T47_W, R600::T48_W, R600::T49_W, R600::T50_W, R600::T51_W, R600::T52_W, R600::T53_W, R600::T54_W, R600::T55_W, R600::T56_W, R600::T57_W, R600::T58_W, R600::T59_W, R600::T60_W, R600::T61_W, R600::T62_W, R600::T63_W, R600::T64_W, R600::T65_W, R600::T66_W, R600::T67_W, R600::T68_W, R600::T69_W, R600::T70_W, R600::T71_W, R600::T72_W, R600::T73_W, R600::T74_W, R600::T75_W, R600::T76_W, R600::T77_W, R600::T78_W, R600::T79_W, R600::T80_W, R600::T81_W, R600::T82_W, R600::T83_W, R600::T84_W, R600::T85_W, R600::T86_W, R600::T87_W, R600::T88_W, R600::T89_W, R600::T90_W, R600::T91_W, R600::T92_W, R600::T93_W, R600::T94_W, R600::T95_W, R600::T96_W, R600::T97_W, R600::T98_W, R600::T99_W, R600::T100_W, R600::T101_W, R600::T102_W, R600::T103_W, R600::T104_W, R600::T105_W, R600::T106_W, R600::T107_W, R600::T108_W, R600::T109_W, R600::T110_W, R600::T111_W, R600::T112_W, R600::T113_W, R600::T114_W, R600::T115_W, R600::T116_W, R600::T117_W, R600::T118_W, R600::T119_W, R600::T120_W, R600::T121_W, R600::T122_W, R600::T123_W, R600::T124_W, R600::T125_W, R600::T126_W, R600::T127_W,
6701 };
6702
6703 // R600_TReg32_W Bit set.
6704 const uint8_t R600_TReg32_WBits[] = {
6705 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f,
6706 };
6707
6708 // R600_TReg32_Y Register Class...
6709 const MCPhysReg R600_TReg32_Y[] = {
6710 R600::T0_Y, R600::T1_Y, R600::T2_Y, R600::T3_Y, R600::T4_Y, R600::T5_Y, R600::T6_Y, R600::T7_Y, R600::T8_Y, R600::T9_Y, R600::T10_Y, R600::T11_Y, R600::T12_Y, R600::T13_Y, R600::T14_Y, R600::T15_Y, R600::T16_Y, R600::T17_Y, R600::T18_Y, R600::T19_Y, R600::T20_Y, R600::T21_Y, R600::T22_Y, R600::T23_Y, R600::T24_Y, R600::T25_Y, R600::T26_Y, R600::T27_Y, R600::T28_Y, R600::T29_Y, R600::T30_Y, R600::T31_Y, R600::T32_Y, R600::T33_Y, R600::T34_Y, R600::T35_Y, R600::T36_Y, R600::T37_Y, R600::T38_Y, R600::T39_Y, R600::T40_Y, R600::T41_Y, R600::T42_Y, R600::T43_Y, R600::T44_Y, R600::T45_Y, R600::T46_Y, R600::T47_Y, R600::T48_Y, R600::T49_Y, R600::T50_Y, R600::T51_Y, R600::T52_Y, R600::T53_Y, R600::T54_Y, R600::T55_Y, R600::T56_Y, R600::T57_Y, R600::T58_Y, R600::T59_Y, R600::T60_Y, R600::T61_Y, R600::T62_Y, R600::T63_Y, R600::T64_Y, R600::T65_Y, R600::T66_Y, R600::T67_Y, R600::T68_Y, R600::T69_Y, R600::T70_Y, R600::T71_Y, R600::T72_Y, R600::T73_Y, R600::T74_Y, R600::T75_Y, R600::T76_Y, R600::T77_Y, R600::T78_Y, R600::T79_Y, R600::T80_Y, R600::T81_Y, R600::T82_Y, R600::T83_Y, R600::T84_Y, R600::T85_Y, R600::T86_Y, R600::T87_Y, R600::T88_Y, R600::T89_Y, R600::T90_Y, R600::T91_Y, R600::T92_Y, R600::T93_Y, R600::T94_Y, R600::T95_Y, R600::T96_Y, R600::T97_Y, R600::T98_Y, R600::T99_Y, R600::T100_Y, R600::T101_Y, R600::T102_Y, R600::T103_Y, R600::T104_Y, R600::T105_Y, R600::T106_Y, R600::T107_Y, R600::T108_Y, R600::T109_Y, R600::T110_Y, R600::T111_Y, R600::T112_Y, R600::T113_Y, R600::T114_Y, R600::T115_Y, R600::T116_Y, R600::T117_Y, R600::T118_Y, R600::T119_Y, R600::T120_Y, R600::T121_Y, R600::T122_Y, R600::T123_Y, R600::T124_Y, R600::T125_Y, R600::T126_Y, R600::T127_Y,
6711 };
6712
6713 // R600_TReg32_Y Bit set.
6714 const uint8_t R600_TReg32_YBits[] = {
6715 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f,
6716 };
6717
6718 // R600_TReg32_Z Register Class...
6719 const MCPhysReg R600_TReg32_Z[] = {
6720 R600::T0_Z, R600::T1_Z, R600::T2_Z, R600::T3_Z, R600::T4_Z, R600::T5_Z, R600::T6_Z, R600::T7_Z, R600::T8_Z, R600::T9_Z, R600::T10_Z, R600::T11_Z, R600::T12_Z, R600::T13_Z, R600::T14_Z, R600::T15_Z, R600::T16_Z, R600::T17_Z, R600::T18_Z, R600::T19_Z, R600::T20_Z, R600::T21_Z, R600::T22_Z, R600::T23_Z, R600::T24_Z, R600::T25_Z, R600::T26_Z, R600::T27_Z, R600::T28_Z, R600::T29_Z, R600::T30_Z, R600::T31_Z, R600::T32_Z, R600::T33_Z, R600::T34_Z, R600::T35_Z, R600::T36_Z, R600::T37_Z, R600::T38_Z, R600::T39_Z, R600::T40_Z, R600::T41_Z, R600::T42_Z, R600::T43_Z, R600::T44_Z, R600::T45_Z, R600::T46_Z, R600::T47_Z, R600::T48_Z, R600::T49_Z, R600::T50_Z, R600::T51_Z, R600::T52_Z, R600::T53_Z, R600::T54_Z, R600::T55_Z, R600::T56_Z, R600::T57_Z, R600::T58_Z, R600::T59_Z, R600::T60_Z, R600::T61_Z, R600::T62_Z, R600::T63_Z, R600::T64_Z, R600::T65_Z, R600::T66_Z, R600::T67_Z, R600::T68_Z, R600::T69_Z, R600::T70_Z, R600::T71_Z, R600::T72_Z, R600::T73_Z, R600::T74_Z, R600::T75_Z, R600::T76_Z, R600::T77_Z, R600::T78_Z, R600::T79_Z, R600::T80_Z, R600::T81_Z, R600::T82_Z, R600::T83_Z, R600::T84_Z, R600::T85_Z, R600::T86_Z, R600::T87_Z, R600::T88_Z, R600::T89_Z, R600::T90_Z, R600::T91_Z, R600::T92_Z, R600::T93_Z, R600::T94_Z, R600::T95_Z, R600::T96_Z, R600::T97_Z, R600::T98_Z, R600::T99_Z, R600::T100_Z, R600::T101_Z, R600::T102_Z, R600::T103_Z, R600::T104_Z, R600::T105_Z, R600::T106_Z, R600::T107_Z, R600::T108_Z, R600::T109_Z, R600::T110_Z, R600::T111_Z, R600::T112_Z, R600::T113_Z, R600::T114_Z, R600::T115_Z, R600::T116_Z, R600::T117_Z, R600::T118_Z, R600::T119_Z, R600::T120_Z, R600::T121_Z, R600::T122_Z, R600::T123_Z, R600::T124_Z, R600::T125_Z, R600::T126_Z, R600::T127_Z,
6721 };
6722
6723 // R600_TReg32_Z Bit set.
6724 const uint8_t R600_TReg32_ZBits[] = {
6725 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f,
6726 };
6727
6728 // R600_ArrayBase Register Class...
6729 const MCPhysReg R600_ArrayBase[] = {
6730 R600::ArrayBase448, R600::ArrayBase449, R600::ArrayBase450, R600::ArrayBase451, R600::ArrayBase452, R600::ArrayBase453, R600::ArrayBase454, R600::ArrayBase455, R600::ArrayBase456, R600::ArrayBase457, R600::ArrayBase458, R600::ArrayBase459, R600::ArrayBase460, R600::ArrayBase461, R600::ArrayBase462, R600::ArrayBase463, R600::ArrayBase464, R600::ArrayBase465, R600::ArrayBase466, R600::ArrayBase467, R600::ArrayBase468, R600::ArrayBase469, R600::ArrayBase470, R600::ArrayBase471, R600::ArrayBase472, R600::ArrayBase473, R600::ArrayBase474, R600::ArrayBase475, R600::ArrayBase476, R600::ArrayBase477, R600::ArrayBase478, R600::ArrayBase479, R600::ArrayBase480,
6731 };
6732
6733 // R600_ArrayBase Bit set.
6734 const uint8_t R600_ArrayBaseBits[] = {
6735 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x7f,
6736 };
6737
6738 // R600_KC0_W Register Class...
6739 const MCPhysReg R600_KC0_W[] = {
6740 R600::KC0_128_W, R600::KC0_129_W, R600::KC0_130_W, R600::KC0_131_W, R600::KC0_132_W, R600::KC0_133_W, R600::KC0_134_W, R600::KC0_135_W, R600::KC0_136_W, R600::KC0_137_W, R600::KC0_138_W, R600::KC0_139_W, R600::KC0_140_W, R600::KC0_141_W, R600::KC0_142_W, R600::KC0_143_W, R600::KC0_144_W, R600::KC0_145_W, R600::KC0_146_W, R600::KC0_147_W, R600::KC0_148_W, R600::KC0_149_W, R600::KC0_150_W, R600::KC0_151_W, R600::KC0_152_W, R600::KC0_153_W, R600::KC0_154_W, R600::KC0_155_W, R600::KC0_156_W, R600::KC0_157_W, R600::KC0_158_W, R600::KC0_159_W,
6741 };
6742
6743 // R600_KC0_W Bit set.
6744 const uint8_t R600_KC0_WBits[] = {
6745 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
6746 };
6747
6748 // R600_KC0_X Register Class...
6749 const MCPhysReg R600_KC0_X[] = {
6750 R600::KC0_128_X, R600::KC0_129_X, R600::KC0_130_X, R600::KC0_131_X, R600::KC0_132_X, R600::KC0_133_X, R600::KC0_134_X, R600::KC0_135_X, R600::KC0_136_X, R600::KC0_137_X, R600::KC0_138_X, R600::KC0_139_X, R600::KC0_140_X, R600::KC0_141_X, R600::KC0_142_X, R600::KC0_143_X, R600::KC0_144_X, R600::KC0_145_X, R600::KC0_146_X, R600::KC0_147_X, R600::KC0_148_X, R600::KC0_149_X, R600::KC0_150_X, R600::KC0_151_X, R600::KC0_152_X, R600::KC0_153_X, R600::KC0_154_X, R600::KC0_155_X, R600::KC0_156_X, R600::KC0_157_X, R600::KC0_158_X, R600::KC0_159_X,
6751 };
6752
6753 // R600_KC0_X Bit set.
6754 const uint8_t R600_KC0_XBits[] = {
6755 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
6756 };
6757
6758 // R600_KC0_Y Register Class...
6759 const MCPhysReg R600_KC0_Y[] = {
6760 R600::KC0_128_Y, R600::KC0_129_Y, R600::KC0_130_Y, R600::KC0_131_Y, R600::KC0_132_Y, R600::KC0_133_Y, R600::KC0_134_Y, R600::KC0_135_Y, R600::KC0_136_Y, R600::KC0_137_Y, R600::KC0_138_Y, R600::KC0_139_Y, R600::KC0_140_Y, R600::KC0_141_Y, R600::KC0_142_Y, R600::KC0_143_Y, R600::KC0_144_Y, R600::KC0_145_Y, R600::KC0_146_Y, R600::KC0_147_Y, R600::KC0_148_Y, R600::KC0_149_Y, R600::KC0_150_Y, R600::KC0_151_Y, R600::KC0_152_Y, R600::KC0_153_Y, R600::KC0_154_Y, R600::KC0_155_Y, R600::KC0_156_Y, R600::KC0_157_Y, R600::KC0_158_Y, R600::KC0_159_Y,
6761 };
6762
6763 // R600_KC0_Y Bit set.
6764 const uint8_t R600_KC0_YBits[] = {
6765 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
6766 };
6767
6768 // R600_KC0_Z Register Class...
6769 const MCPhysReg R600_KC0_Z[] = {
6770 R600::KC0_128_Z, R600::KC0_129_Z, R600::KC0_130_Z, R600::KC0_131_Z, R600::KC0_132_Z, R600::KC0_133_Z, R600::KC0_134_Z, R600::KC0_135_Z, R600::KC0_136_Z, R600::KC0_137_Z, R600::KC0_138_Z, R600::KC0_139_Z, R600::KC0_140_Z, R600::KC0_141_Z, R600::KC0_142_Z, R600::KC0_143_Z, R600::KC0_144_Z, R600::KC0_145_Z, R600::KC0_146_Z, R600::KC0_147_Z, R600::KC0_148_Z, R600::KC0_149_Z, R600::KC0_150_Z, R600::KC0_151_Z, R600::KC0_152_Z, R600::KC0_153_Z, R600::KC0_154_Z, R600::KC0_155_Z, R600::KC0_156_Z, R600::KC0_157_Z, R600::KC0_158_Z, R600::KC0_159_Z,
6771 };
6772
6773 // R600_KC0_Z Bit set.
6774 const uint8_t R600_KC0_ZBits[] = {
6775 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
6776 };
6777
6778 // R600_KC1_W Register Class...
6779 const MCPhysReg R600_KC1_W[] = {
6780 R600::KC1_160_W, R600::KC1_161_W, R600::KC1_162_W, R600::KC1_163_W, R600::KC1_164_W, R600::KC1_165_W, R600::KC1_166_W, R600::KC1_167_W, R600::KC1_168_W, R600::KC1_169_W, R600::KC1_170_W, R600::KC1_171_W, R600::KC1_172_W, R600::KC1_173_W, R600::KC1_174_W, R600::KC1_175_W, R600::KC1_176_W, R600::KC1_177_W, R600::KC1_178_W, R600::KC1_179_W, R600::KC1_180_W, R600::KC1_181_W, R600::KC1_182_W, R600::KC1_183_W, R600::KC1_184_W, R600::KC1_185_W, R600::KC1_186_W, R600::KC1_187_W, R600::KC1_188_W, R600::KC1_189_W, R600::KC1_190_W, R600::KC1_191_W,
6781 };
6782
6783 // R600_KC1_W Bit set.
6784 const uint8_t R600_KC1_WBits[] = {
6785 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
6786 };
6787
6788 // R600_KC1_X Register Class...
6789 const MCPhysReg R600_KC1_X[] = {
6790 R600::KC1_160_X, R600::KC1_161_X, R600::KC1_162_X, R600::KC1_163_X, R600::KC1_164_X, R600::KC1_165_X, R600::KC1_166_X, R600::KC1_167_X, R600::KC1_168_X, R600::KC1_169_X, R600::KC1_170_X, R600::KC1_171_X, R600::KC1_172_X, R600::KC1_173_X, R600::KC1_174_X, R600::KC1_175_X, R600::KC1_176_X, R600::KC1_177_X, R600::KC1_178_X, R600::KC1_179_X, R600::KC1_180_X, R600::KC1_181_X, R600::KC1_182_X, R600::KC1_183_X, R600::KC1_184_X, R600::KC1_185_X, R600::KC1_186_X, R600::KC1_187_X, R600::KC1_188_X, R600::KC1_189_X, R600::KC1_190_X, R600::KC1_191_X,
6791 };
6792
6793 // R600_KC1_X Bit set.
6794 const uint8_t R600_KC1_XBits[] = {
6795 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
6796 };
6797
6798 // R600_KC1_Y Register Class...
6799 const MCPhysReg R600_KC1_Y[] = {
6800 R600::KC1_160_Y, R600::KC1_161_Y, R600::KC1_162_Y, R600::KC1_163_Y, R600::KC1_164_Y, R600::KC1_165_Y, R600::KC1_166_Y, R600::KC1_167_Y, R600::KC1_168_Y, R600::KC1_169_Y, R600::KC1_170_Y, R600::KC1_171_Y, R600::KC1_172_Y, R600::KC1_173_Y, R600::KC1_174_Y, R600::KC1_175_Y, R600::KC1_176_Y, R600::KC1_177_Y, R600::KC1_178_Y, R600::KC1_179_Y, R600::KC1_180_Y, R600::KC1_181_Y, R600::KC1_182_Y, R600::KC1_183_Y, R600::KC1_184_Y, R600::KC1_185_Y, R600::KC1_186_Y, R600::KC1_187_Y, R600::KC1_188_Y, R600::KC1_189_Y, R600::KC1_190_Y, R600::KC1_191_Y,
6801 };
6802
6803 // R600_KC1_Y Bit set.
6804 const uint8_t R600_KC1_YBits[] = {
6805 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
6806 };
6807
6808 // R600_KC1_Z Register Class...
6809 const MCPhysReg R600_KC1_Z[] = {
6810 R600::KC1_160_Z, R600::KC1_161_Z, R600::KC1_162_Z, R600::KC1_163_Z, R600::KC1_164_Z, R600::KC1_165_Z, R600::KC1_166_Z, R600::KC1_167_Z, R600::KC1_168_Z, R600::KC1_169_Z, R600::KC1_170_Z, R600::KC1_171_Z, R600::KC1_172_Z, R600::KC1_173_Z, R600::KC1_174_Z, R600::KC1_175_Z, R600::KC1_176_Z, R600::KC1_177_Z, R600::KC1_178_Z, R600::KC1_179_Z, R600::KC1_180_Z, R600::KC1_181_Z, R600::KC1_182_Z, R600::KC1_183_Z, R600::KC1_184_Z, R600::KC1_185_Z, R600::KC1_186_Z, R600::KC1_187_Z, R600::KC1_188_Z, R600::KC1_189_Z, R600::KC1_190_Z, R600::KC1_191_Z,
6811 };
6812
6813 // R600_KC1_Z Bit set.
6814 const uint8_t R600_KC1_ZBits[] = {
6815 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
6816 };
6817
6818 // R600_LDS_SRC_REG Register Class...
6819 const MCPhysReg R600_LDS_SRC_REG[] = {
6820 R600::OQA, R600::OQB, R600::OQAP, R600::OQBP, R600::LDS_DIRECT_A, R600::LDS_DIRECT_B,
6821 };
6822
6823 // R600_LDS_SRC_REG Bit set.
6824 const uint8_t R600_LDS_SRC_REGBits[] = {
6825 0x00, 0x0c, 0x0f,
6826 };
6827
6828 // R600_Predicate Register Class...
6829 const MCPhysReg R600_Predicate[] = {
6830 R600::PRED_SEL_OFF, R600::PRED_SEL_ZERO, R600::PRED_SEL_ONE,
6831 };
6832
6833 // R600_Predicate Bit set.
6834 const uint8_t R600_PredicateBits[] = {
6835 0x00, 0x00, 0xe0,
6836 };
6837
6838 // R600_Addr_W Register Class...
6839 const MCPhysReg R600_Addr_W[] = {
6840 R600::Addr0_W,
6841 };
6842
6843 // R600_Addr_W Bit set.
6844 const uint8_t R600_Addr_WBits[] = {
6845 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
6846 };
6847
6848 // R600_Addr_Y Register Class...
6849 const MCPhysReg R600_Addr_Y[] = {
6850 R600::Addr0_Y,
6851 };
6852
6853 // R600_Addr_Y Bit set.
6854 const uint8_t R600_Addr_YBits[] = {
6855 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
6856 };
6857
6858 // R600_Addr_Z Register Class...
6859 const MCPhysReg R600_Addr_Z[] = {
6860 R600::Addr0_Z,
6861 };
6862
6863 // R600_Addr_Z Bit set.
6864 const uint8_t R600_Addr_ZBits[] = {
6865 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
6866 };
6867
6868 // R600_LDS_SRC_REG_and_R600_Reg32 Register Class...
6869 const MCPhysReg R600_LDS_SRC_REG_and_R600_Reg32[] = {
6870 R600::OQAP,
6871 };
6872
6873 // R600_LDS_SRC_REG_and_R600_Reg32 Bit set.
6874 const uint8_t R600_LDS_SRC_REG_and_R600_Reg32Bits[] = {
6875 0x00, 0x00, 0x02,
6876 };
6877
6878 // R600_Predicate_Bit Register Class...
6879 const MCPhysReg R600_Predicate_Bit[] = {
6880 R600::PREDICATE_BIT,
6881 };
6882
6883 // R600_Predicate_Bit Bit set.
6884 const uint8_t R600_Predicate_BitBits[] = {
6885 0x00, 0x00, 0x10,
6886 };
6887
6888 // R600_Reg64 Register Class...
6889 const MCPhysReg R600_Reg64[] = {
6890 R600::T0_XY, R600::T1_XY, R600::T2_XY, R600::T3_XY, R600::T4_XY, R600::T5_XY, R600::T6_XY, R600::T7_XY, R600::T8_XY, R600::T9_XY, R600::T10_XY, R600::T11_XY, R600::T12_XY, R600::T13_XY, R600::T14_XY, R600::T15_XY, R600::T16_XY, R600::T17_XY, R600::T18_XY, R600::T19_XY, R600::T20_XY, R600::T21_XY, R600::T22_XY, R600::T23_XY, R600::T24_XY, R600::T25_XY, R600::T26_XY, R600::T27_XY, R600::T28_XY, R600::T29_XY, R600::T30_XY, R600::T31_XY, R600::T32_XY, R600::T33_XY, R600::T34_XY, R600::T35_XY, R600::T36_XY, R600::T37_XY, R600::T38_XY, R600::T39_XY, R600::T40_XY, R600::T41_XY, R600::T42_XY, R600::T43_XY, R600::T44_XY, R600::T45_XY, R600::T46_XY, R600::T47_XY, R600::T48_XY, R600::T49_XY, R600::T50_XY, R600::T51_XY, R600::T52_XY, R600::T53_XY, R600::T54_XY, R600::T55_XY, R600::T56_XY, R600::T57_XY, R600::T58_XY, R600::T59_XY, R600::T60_XY, R600::T61_XY, R600::T62_XY, R600::T63_XY,
6891 };
6892
6893 // R600_Reg64 Bit set.
6894 const uint8_t R600_Reg64Bits[] = {
6895 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f,
6896 };
6897
6898 // R600_Reg64Vertical Register Class...
6899 const MCPhysReg R600_Reg64Vertical[] = {
6900 R600::V01_X, R600::V01_Y, R600::V01_Z, R600::V01_W, R600::V23_X, R600::V23_Y, R600::V23_Z, R600::V23_W,
6901 };
6902
6903 // R600_Reg64Vertical Bit set.
6904 const uint8_t R600_Reg64VerticalBits[] = {
6905 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x6d, 0x03,
6906 };
6907
6908 // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W Register Class...
6909 const MCPhysReg R600_Reg64Vertical_with_sub0_in_R600_TReg32_W[] = {
6910 R600::V01_W, R600::V23_W,
6911 };
6912
6913 // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W Bit set.
6914 const uint8_t R600_Reg64Vertical_with_sub0_in_R600_TReg32_WBits[] = {
6915 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01,
6916 };
6917
6918 // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X Register Class...
6919 const MCPhysReg R600_Reg64Vertical_with_sub0_in_R600_TReg32_X[] = {
6920 R600::V01_X, R600::V23_X,
6921 };
6922
6923 // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X Bit set.
6924 const uint8_t R600_Reg64Vertical_with_sub0_in_R600_TReg32_XBits[] = {
6925 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c,
6926 };
6927
6928 // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y Register Class...
6929 const MCPhysReg R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y[] = {
6930 R600::V01_Y, R600::V23_Y,
6931 };
6932
6933 // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y Bit set.
6934 const uint8_t R600_Reg64Vertical_with_sub0_in_R600_TReg32_YBits[] = {
6935 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60,
6936 };
6937
6938 // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z Register Class...
6939 const MCPhysReg R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z[] = {
6940 R600::V01_Z, R600::V23_Z,
6941 };
6942
6943 // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z Bit set.
6944 const uint8_t R600_Reg64Vertical_with_sub0_in_R600_TReg32_ZBits[] = {
6945 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
6946 };
6947
6948 // R600_Reg128 Register Class...
6949 const MCPhysReg R600_Reg128[] = {
6950 R600::T0_XYZW, R600::T1_XYZW, R600::T2_XYZW, R600::T3_XYZW, R600::T4_XYZW, R600::T5_XYZW, R600::T6_XYZW, R600::T7_XYZW, R600::T8_XYZW, R600::T9_XYZW, R600::T10_XYZW, R600::T11_XYZW, R600::T12_XYZW, R600::T13_XYZW, R600::T14_XYZW, R600::T15_XYZW, R600::T16_XYZW, R600::T17_XYZW, R600::T18_XYZW, R600::T19_XYZW, R600::T20_XYZW, R600::T21_XYZW, R600::T22_XYZW, R600::T23_XYZW, R600::T24_XYZW, R600::T25_XYZW, R600::T26_XYZW, R600::T27_XYZW, R600::T28_XYZW, R600::T29_XYZW, R600::T30_XYZW, R600::T31_XYZW, R600::T32_XYZW, R600::T33_XYZW, R600::T34_XYZW, R600::T35_XYZW, R600::T36_XYZW, R600::T37_XYZW, R600::T38_XYZW, R600::T39_XYZW, R600::T40_XYZW, R600::T41_XYZW, R600::T42_XYZW, R600::T43_XYZW, R600::T44_XYZW, R600::T45_XYZW, R600::T46_XYZW, R600::T47_XYZW, R600::T48_XYZW, R600::T49_XYZW, R600::T50_XYZW, R600::T51_XYZW, R600::T52_XYZW, R600::T53_XYZW, R600::T54_XYZW, R600::T55_XYZW, R600::T56_XYZW, R600::T57_XYZW, R600::T58_XYZW, R600::T59_XYZW, R600::T60_XYZW, R600::T61_XYZW, R600::T62_XYZW, R600::T63_XYZW, R600::T64_XYZW, R600::T65_XYZW, R600::T66_XYZW, R600::T67_XYZW, R600::T68_XYZW, R600::T69_XYZW, R600::T70_XYZW, R600::T71_XYZW, R600::T72_XYZW, R600::T73_XYZW, R600::T74_XYZW, R600::T75_XYZW, R600::T76_XYZW, R600::T77_XYZW, R600::T78_XYZW, R600::T79_XYZW, R600::T80_XYZW, R600::T81_XYZW, R600::T82_XYZW, R600::T83_XYZW, R600::T84_XYZW, R600::T85_XYZW, R600::T86_XYZW, R600::T87_XYZW, R600::T88_XYZW, R600::T89_XYZW, R600::T90_XYZW, R600::T91_XYZW, R600::T92_XYZW, R600::T93_XYZW, R600::T94_XYZW, R600::T95_XYZW, R600::T96_XYZW, R600::T97_XYZW, R600::T98_XYZW, R600::T99_XYZW, R600::T100_XYZW, R600::T101_XYZW, R600::T102_XYZW, R600::T103_XYZW, R600::T104_XYZW, R600::T105_XYZW, R600::T106_XYZW, R600::T107_XYZW, R600::T108_XYZW, R600::T109_XYZW, R600::T110_XYZW, R600::T111_XYZW, R600::T112_XYZW, R600::T113_XYZW, R600::T114_XYZW, R600::T115_XYZW, R600::T116_XYZW, R600::T117_XYZW, R600::T118_XYZW, R600::T119_XYZW, R600::T120_XYZW, R600::T121_XYZW, R600::T122_XYZW, R600::T123_XYZW, R600::T124_XYZW, R600::T125_XYZW, R600::T126_XYZW, R600::T127_XYZW,
6951 };
6952
6953 // R600_Reg128 Bit set.
6954 const uint8_t R600_Reg128Bits[] = {
6955 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f,
6956 };
6957
6958 // R600_Reg128Vertical Register Class...
6959 const MCPhysReg R600_Reg128Vertical[] = {
6960 R600::V0123_W, R600::V0123_Z, R600::V0123_Y, R600::V0123_X,
6961 };
6962
6963 // R600_Reg128Vertical Bit set.
6964 const uint8_t R600_Reg128VerticalBits[] = {
6965 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x92, 0x04,
6966 };
6967
6968 // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W Register Class...
6969 const MCPhysReg R600_Reg128Vertical_with_sub0_in_R600_TReg32_W[] = {
6970 R600::V0123_W,
6971 };
6972
6973 // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W Bit set.
6974 const uint8_t R600_Reg128Vertical_with_sub0_in_R600_TReg32_WBits[] = {
6975 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
6976 };
6977
6978 // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X Register Class...
6979 const MCPhysReg R600_Reg128Vertical_with_sub0_in_R600_TReg32_X[] = {
6980 R600::V0123_X,
6981 };
6982
6983 // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X Bit set.
6984 const uint8_t R600_Reg128Vertical_with_sub0_in_R600_TReg32_XBits[] = {
6985 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
6986 };
6987
6988 // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y Register Class...
6989 const MCPhysReg R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y[] = {
6990 R600::V0123_Y,
6991 };
6992
6993 // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y Bit set.
6994 const uint8_t R600_Reg128Vertical_with_sub0_in_R600_TReg32_YBits[] = {
6995 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
6996 };
6997
6998 // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z Register Class...
6999 const MCPhysReg R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z[] = {
7000 R600::V0123_Z,
7001 };
7002
7003 // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z Bit set.
7004 const uint8_t R600_Reg128Vertical_with_sub0_in_R600_TReg32_ZBits[] = {
7005 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
7006 };
7007
7008} // end anonymous namespace
7009
7010
7011#ifdef __GNUC__
7012#pragma GCC diagnostic push
7013#pragma GCC diagnostic ignored "-Woverlength-strings"
7014#endif
7015extern const char R600RegClassStrings[] = {
7016 /* 0 */ "R600_KC0\000"
7017 /* 9 */ "R600_KC1\000"
7018 /* 18 */ "R600_TReg32\000"
7019 /* 30 */ "R600_LDS_SRC_REG_and_R600_Reg32\000"
7020 /* 62 */ "R600_Reg64\000"
7021 /* 73 */ "R600_Reg128\000"
7022 /* 85 */ "R600_LDS_SRC_REG\000"
7023 /* 102 */ "R600_KC0_W\000"
7024 /* 113 */ "R600_KC1_W\000"
7025 /* 124 */ "R600_Reg64Vertical_with_sub0_in_R600_TReg32_W\000"
7026 /* 170 */ "R600_Reg128Vertical_with_sub0_in_R600_TReg32_W\000"
7027 /* 217 */ "R600_Addr_W\000"
7028 /* 229 */ "R600_KC0_X\000"
7029 /* 240 */ "R600_KC1_X\000"
7030 /* 251 */ "R600_Reg64Vertical_with_sub0_in_R600_TReg32_X\000"
7031 /* 297 */ "R600_Reg128Vertical_with_sub0_in_R600_TReg32_X\000"
7032 /* 344 */ "R600_KC0_Y\000"
7033 /* 355 */ "R600_KC1_Y\000"
7034 /* 366 */ "R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y\000"
7035 /* 412 */ "R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y\000"
7036 /* 459 */ "R600_Addr_Y\000"
7037 /* 471 */ "R600_KC0_Z\000"
7038 /* 482 */ "R600_KC1_Z\000"
7039 /* 493 */ "R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z\000"
7040 /* 539 */ "R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z\000"
7041 /* 586 */ "R600_Addr_Z\000"
7042 /* 598 */ "R600_ArrayBase\000"
7043 /* 613 */ "R600_Predicate\000"
7044 /* 628 */ "R600_Reg64Vertical\000"
7045 /* 647 */ "R600_Reg128Vertical\000"
7046 /* 667 */ "R600_Addr\000"
7047 /* 677 */ "R600_Predicate_Bit\000"
7048};
7049#ifdef __GNUC__
7050#pragma GCC diagnostic pop
7051#endif
7052
7053extern const MCRegisterClass R600MCRegisterClasses[] = {
7054 { R600_Reg32, R600_Reg32Bits, 51, 942, sizeof(R600_Reg32Bits), R600::R600_Reg32RegClassID, 32, 1, true, false },
7055 { R600_TReg32, R600_TReg32Bits, 18, 513, sizeof(R600_TReg32Bits), R600::R600_TReg32RegClassID, 32, 1, true, false },
7056 { R600_TReg32_X, R600_TReg32_XBits, 283, 129, sizeof(R600_TReg32_XBits), R600::R600_TReg32_XRegClassID, 32, 1, true, false },
7057 { R600_Addr, R600_AddrBits, 667, 128, sizeof(R600_AddrBits), R600::R600_AddrRegClassID, 32, 1, false, false },
7058 { R600_KC0, R600_KC0Bits, 0, 128, sizeof(R600_KC0Bits), R600::R600_KC0RegClassID, 32, 1, false, false },
7059 { R600_KC1, R600_KC1Bits, 9, 128, sizeof(R600_KC1Bits), R600::R600_KC1RegClassID, 32, 1, false, false },
7060 { R600_TReg32_W, R600_TReg32_WBits, 156, 128, sizeof(R600_TReg32_WBits), R600::R600_TReg32_WRegClassID, 32, 1, true, false },
7061 { R600_TReg32_Y, R600_TReg32_YBits, 398, 128, sizeof(R600_TReg32_YBits), R600::R600_TReg32_YRegClassID, 32, 1, true, false },
7062 { R600_TReg32_Z, R600_TReg32_ZBits, 525, 128, sizeof(R600_TReg32_ZBits), R600::R600_TReg32_ZRegClassID, 32, 1, true, false },
7063 { R600_ArrayBase, R600_ArrayBaseBits, 598, 33, sizeof(R600_ArrayBaseBits), R600::R600_ArrayBaseRegClassID, 32, 1, true, false },
7064 { R600_KC0_W, R600_KC0_WBits, 102, 32, sizeof(R600_KC0_WBits), R600::R600_KC0_WRegClassID, 32, 1, false, false },
7065 { R600_KC0_X, R600_KC0_XBits, 229, 32, sizeof(R600_KC0_XBits), R600::R600_KC0_XRegClassID, 32, 1, false, false },
7066 { R600_KC0_Y, R600_KC0_YBits, 344, 32, sizeof(R600_KC0_YBits), R600::R600_KC0_YRegClassID, 32, 1, false, false },
7067 { R600_KC0_Z, R600_KC0_ZBits, 471, 32, sizeof(R600_KC0_ZBits), R600::R600_KC0_ZRegClassID, 32, 1, false, false },
7068 { R600_KC1_W, R600_KC1_WBits, 113, 32, sizeof(R600_KC1_WBits), R600::R600_KC1_WRegClassID, 32, 1, false, false },
7069 { R600_KC1_X, R600_KC1_XBits, 240, 32, sizeof(R600_KC1_XBits), R600::R600_KC1_XRegClassID, 32, 1, false, false },
7070 { R600_KC1_Y, R600_KC1_YBits, 355, 32, sizeof(R600_KC1_YBits), R600::R600_KC1_YRegClassID, 32, 1, false, false },
7071 { R600_KC1_Z, R600_KC1_ZBits, 482, 32, sizeof(R600_KC1_ZBits), R600::R600_KC1_ZRegClassID, 32, 1, false, false },
7072 { R600_LDS_SRC_REG, R600_LDS_SRC_REGBits, 85, 6, sizeof(R600_LDS_SRC_REGBits), R600::R600_LDS_SRC_REGRegClassID, 32, 1, false, false },
7073 { R600_Predicate, R600_PredicateBits, 613, 3, sizeof(R600_PredicateBits), R600::R600_PredicateRegClassID, 32, 1, true, false },
7074 { R600_Addr_W, R600_Addr_WBits, 217, 1, sizeof(R600_Addr_WBits), R600::R600_Addr_WRegClassID, 32, 1, false, false },
7075 { R600_Addr_Y, R600_Addr_YBits, 459, 1, sizeof(R600_Addr_YBits), R600::R600_Addr_YRegClassID, 32, 1, false, false },
7076 { R600_Addr_Z, R600_Addr_ZBits, 586, 1, sizeof(R600_Addr_ZBits), R600::R600_Addr_ZRegClassID, 32, 1, false, false },
7077 { R600_LDS_SRC_REG_and_R600_Reg32, R600_LDS_SRC_REG_and_R600_Reg32Bits, 30, 1, sizeof(R600_LDS_SRC_REG_and_R600_Reg32Bits), R600::R600_LDS_SRC_REG_and_R600_Reg32RegClassID, 32, 1, true, false },
7078 { R600_Predicate_Bit, R600_Predicate_BitBits, 677, 1, sizeof(R600_Predicate_BitBits), R600::R600_Predicate_BitRegClassID, 32, 1, true, false },
7079 { R600_Reg64, R600_Reg64Bits, 62, 64, sizeof(R600_Reg64Bits), R600::R600_Reg64RegClassID, 64, 1, true, false },
7080 { R600_Reg64Vertical, R600_Reg64VerticalBits, 628, 8, sizeof(R600_Reg64VerticalBits), R600::R600_Reg64VerticalRegClassID, 64, 1, true, false },
7081 { R600_Reg64Vertical_with_sub0_in_R600_TReg32_W, R600_Reg64Vertical_with_sub0_in_R600_TReg32_WBits, 124, 2, sizeof(R600_Reg64Vertical_with_sub0_in_R600_TReg32_WBits), R600::R600_Reg64Vertical_with_sub0_in_R600_TReg32_WRegClassID, 64, 1, true, false },
7082 { R600_Reg64Vertical_with_sub0_in_R600_TReg32_X, R600_Reg64Vertical_with_sub0_in_R600_TReg32_XBits, 251, 2, sizeof(R600_Reg64Vertical_with_sub0_in_R600_TReg32_XBits), R600::R600_Reg64Vertical_with_sub0_in_R600_TReg32_XRegClassID, 64, 1, true, false },
7083 { R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y, R600_Reg64Vertical_with_sub0_in_R600_TReg32_YBits, 366, 2, sizeof(R600_Reg64Vertical_with_sub0_in_R600_TReg32_YBits), R600::R600_Reg64Vertical_with_sub0_in_R600_TReg32_YRegClassID, 64, 1, true, false },
7084 { R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z, R600_Reg64Vertical_with_sub0_in_R600_TReg32_ZBits, 493, 2, sizeof(R600_Reg64Vertical_with_sub0_in_R600_TReg32_ZBits), R600::R600_Reg64Vertical_with_sub0_in_R600_TReg32_ZRegClassID, 64, 1, true, false },
7085 { R600_Reg128, R600_Reg128Bits, 73, 128, sizeof(R600_Reg128Bits), R600::R600_Reg128RegClassID, 128, -1, true, false },
7086 { R600_Reg128Vertical, R600_Reg128VerticalBits, 647, 4, sizeof(R600_Reg128VerticalBits), R600::R600_Reg128VerticalRegClassID, 128, 1, true, false },
7087 { R600_Reg128Vertical_with_sub0_in_R600_TReg32_W, R600_Reg128Vertical_with_sub0_in_R600_TReg32_WBits, 170, 1, sizeof(R600_Reg128Vertical_with_sub0_in_R600_TReg32_WBits), R600::R600_Reg128Vertical_with_sub0_in_R600_TReg32_WRegClassID, 128, 1, true, false },
7088 { R600_Reg128Vertical_with_sub0_in_R600_TReg32_X, R600_Reg128Vertical_with_sub0_in_R600_TReg32_XBits, 297, 1, sizeof(R600_Reg128Vertical_with_sub0_in_R600_TReg32_XBits), R600::R600_Reg128Vertical_with_sub0_in_R600_TReg32_XRegClassID, 128, 1, true, false },
7089 { R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y, R600_Reg128Vertical_with_sub0_in_R600_TReg32_YBits, 412, 1, sizeof(R600_Reg128Vertical_with_sub0_in_R600_TReg32_YBits), R600::R600_Reg128Vertical_with_sub0_in_R600_TReg32_YRegClassID, 128, 1, true, false },
7090 { R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z, R600_Reg128Vertical_with_sub0_in_R600_TReg32_ZBits, 539, 1, sizeof(R600_Reg128Vertical_with_sub0_in_R600_TReg32_ZBits), R600::R600_Reg128Vertical_with_sub0_in_R600_TReg32_ZRegClassID, 128, 1, true, false },
7091};
7092
7093extern const uint16_t R600RegEncodingTable[] = {
7094 0,
7095 0,
7096 1789,
7097 253,
7098 765,
7099 1277,
7100 0,
7101 0,
7102 252,
7103 0,
7104 223,
7105 224,
7106 252,
7107 249,
7108 249,
7109 250,
7110 219,
7111 221,
7112 220,
7113 222,
7114 0,
7115 0,
7116 3,
7117 2,
7118 255,
7119 1790,
7120 254,
7121 766,
7122 1278,
7123 248,
7124 448,
7125 449,
7126 450,
7127 451,
7128 452,
7129 453,
7130 454,
7131 455,
7132 456,
7133 457,
7134 458,
7135 459,
7136 460,
7137 461,
7138 462,
7139 463,
7140 464,
7141 465,
7142 466,
7143 467,
7144 468,
7145 469,
7146 470,
7147 471,
7148 472,
7149 473,
7150 474,
7151 475,
7152 476,
7153 477,
7154 478,
7155 479,
7156 480,
7157 1536,
7158 1537,
7159 1538,
7160 1539,
7161 1540,
7162 1541,
7163 1542,
7164 1543,
7165 1544,
7166 1545,
7167 1546,
7168 1547,
7169 1548,
7170 1549,
7171 1550,
7172 1551,
7173 1552,
7174 1553,
7175 1554,
7176 1555,
7177 1556,
7178 1557,
7179 1558,
7180 1559,
7181 1560,
7182 1561,
7183 1562,
7184 1563,
7185 1564,
7186 1565,
7187 1566,
7188 1567,
7189 1568,
7190 1569,
7191 1570,
7192 1571,
7193 1572,
7194 1573,
7195 1574,
7196 1575,
7197 1576,
7198 1577,
7199 1578,
7200 1579,
7201 1580,
7202 1581,
7203 1582,
7204 1583,
7205 1584,
7206 1585,
7207 1586,
7208 1587,
7209 1588,
7210 1589,
7211 1590,
7212 1591,
7213 1592,
7214 1593,
7215 1594,
7216 1595,
7217 1596,
7218 1597,
7219 1598,
7220 1599,
7221 1600,
7222 1601,
7223 1602,
7224 1603,
7225 1604,
7226 1605,
7227 1606,
7228 1607,
7229 1608,
7230 1609,
7231 1610,
7232 1611,
7233 1612,
7234 1613,
7235 1614,
7236 1615,
7237 1616,
7238 1617,
7239 1618,
7240 1619,
7241 1620,
7242 1621,
7243 1622,
7244 1623,
7245 1624,
7246 1625,
7247 1626,
7248 1627,
7249 1628,
7250 1629,
7251 1630,
7252 1631,
7253 1632,
7254 1633,
7255 1634,
7256 1635,
7257 1636,
7258 1637,
7259 1638,
7260 1639,
7261 1640,
7262 1641,
7263 1642,
7264 1643,
7265 1644,
7266 1645,
7267 1646,
7268 1647,
7269 1648,
7270 1649,
7271 1650,
7272 1651,
7273 1652,
7274 1653,
7275 1654,
7276 1655,
7277 1656,
7278 1657,
7279 1658,
7280 1659,
7281 1660,
7282 1661,
7283 1662,
7284 1663,
7285 0,
7286 1,
7287 2,
7288 3,
7289 4,
7290 5,
7291 6,
7292 7,
7293 8,
7294 9,
7295 10,
7296 11,
7297 12,
7298 13,
7299 14,
7300 15,
7301 16,
7302 17,
7303 18,
7304 19,
7305 20,
7306 21,
7307 22,
7308 23,
7309 24,
7310 25,
7311 26,
7312 27,
7313 28,
7314 29,
7315 30,
7316 31,
7317 32,
7318 33,
7319 34,
7320 35,
7321 36,
7322 37,
7323 38,
7324 39,
7325 40,
7326 41,
7327 42,
7328 43,
7329 44,
7330 45,
7331 46,
7332 47,
7333 48,
7334 49,
7335 50,
7336 51,
7337 52,
7338 53,
7339 54,
7340 55,
7341 56,
7342 57,
7343 58,
7344 59,
7345 60,
7346 61,
7347 62,
7348 63,
7349 64,
7350 65,
7351 66,
7352 67,
7353 68,
7354 69,
7355 70,
7356 71,
7357 72,
7358 73,
7359 74,
7360 75,
7361 76,
7362 77,
7363 78,
7364 79,
7365 80,
7366 81,
7367 82,
7368 83,
7369 84,
7370 85,
7371 86,
7372 87,
7373 88,
7374 89,
7375 90,
7376 91,
7377 92,
7378 93,
7379 94,
7380 95,
7381 96,
7382 97,
7383 98,
7384 99,
7385 100,
7386 101,
7387 102,
7388 103,
7389 104,
7390 105,
7391 106,
7392 107,
7393 108,
7394 109,
7395 110,
7396 111,
7397 112,
7398 113,
7399 114,
7400 115,
7401 116,
7402 117,
7403 118,
7404 119,
7405 120,
7406 121,
7407 122,
7408 123,
7409 124,
7410 125,
7411 126,
7412 127,
7413 512,
7414 513,
7415 514,
7416 515,
7417 516,
7418 517,
7419 518,
7420 519,
7421 520,
7422 521,
7423 522,
7424 523,
7425 524,
7426 525,
7427 526,
7428 527,
7429 528,
7430 529,
7431 530,
7432 531,
7433 532,
7434 533,
7435 534,
7436 535,
7437 536,
7438 537,
7439 538,
7440 539,
7441 540,
7442 541,
7443 542,
7444 543,
7445 544,
7446 545,
7447 546,
7448 547,
7449 548,
7450 549,
7451 550,
7452 551,
7453 552,
7454 553,
7455 554,
7456 555,
7457 556,
7458 557,
7459 558,
7460 559,
7461 560,
7462 561,
7463 562,
7464 563,
7465 564,
7466 565,
7467 566,
7468 567,
7469 568,
7470 569,
7471 570,
7472 571,
7473 572,
7474 573,
7475 574,
7476 575,
7477 576,
7478 577,
7479 578,
7480 579,
7481 580,
7482 581,
7483 582,
7484 583,
7485 584,
7486 585,
7487 586,
7488 587,
7489 588,
7490 589,
7491 590,
7492 591,
7493 592,
7494 593,
7495 594,
7496 595,
7497 596,
7498 597,
7499 598,
7500 599,
7501 600,
7502 601,
7503 602,
7504 603,
7505 604,
7506 605,
7507 606,
7508 607,
7509 608,
7510 609,
7511 610,
7512 611,
7513 612,
7514 613,
7515 614,
7516 615,
7517 616,
7518 617,
7519 618,
7520 619,
7521 620,
7522 621,
7523 622,
7524 623,
7525 624,
7526 625,
7527 626,
7528 627,
7529 628,
7530 629,
7531 630,
7532 631,
7533 632,
7534 633,
7535 634,
7536 635,
7537 636,
7538 637,
7539 638,
7540 639,
7541 1024,
7542 1025,
7543 1026,
7544 1027,
7545 1028,
7546 1029,
7547 1030,
7548 1031,
7549 1032,
7550 1033,
7551 1034,
7552 1035,
7553 1036,
7554 1037,
7555 1038,
7556 1039,
7557 1040,
7558 1041,
7559 1042,
7560 1043,
7561 1044,
7562 1045,
7563 1046,
7564 1047,
7565 1048,
7566 1049,
7567 1050,
7568 1051,
7569 1052,
7570 1053,
7571 1054,
7572 1055,
7573 1056,
7574 1057,
7575 1058,
7576 1059,
7577 1060,
7578 1061,
7579 1062,
7580 1063,
7581 1064,
7582 1065,
7583 1066,
7584 1067,
7585 1068,
7586 1069,
7587 1070,
7588 1071,
7589 1072,
7590 1073,
7591 1074,
7592 1075,
7593 1076,
7594 1077,
7595 1078,
7596 1079,
7597 1080,
7598 1081,
7599 1082,
7600 1083,
7601 1084,
7602 1085,
7603 1086,
7604 1087,
7605 1088,
7606 1089,
7607 1090,
7608 1091,
7609 1092,
7610 1093,
7611 1094,
7612 1095,
7613 1096,
7614 1097,
7615 1098,
7616 1099,
7617 1100,
7618 1101,
7619 1102,
7620 1103,
7621 1104,
7622 1105,
7623 1106,
7624 1107,
7625 1108,
7626 1109,
7627 1110,
7628 1111,
7629 1112,
7630 1113,
7631 1114,
7632 1115,
7633 1116,
7634 1117,
7635 1118,
7636 1119,
7637 1120,
7638 1121,
7639 1122,
7640 1123,
7641 1124,
7642 1125,
7643 1126,
7644 1127,
7645 1128,
7646 1129,
7647 1130,
7648 1131,
7649 1132,
7650 1133,
7651 1134,
7652 1135,
7653 1136,
7654 1137,
7655 1138,
7656 1139,
7657 1140,
7658 1141,
7659 1142,
7660 1143,
7661 1144,
7662 1145,
7663 1146,
7664 1147,
7665 1148,
7666 1149,
7667 1150,
7668 1151,
7669 1536,
7670 1537,
7671 1538,
7672 1539,
7673 1540,
7674 1541,
7675 1542,
7676 1543,
7677 1544,
7678 1545,
7679 1546,
7680 1547,
7681 1548,
7682 1549,
7683 1550,
7684 1551,
7685 1552,
7686 1553,
7687 1554,
7688 1555,
7689 1556,
7690 1557,
7691 1558,
7692 1559,
7693 1560,
7694 1561,
7695 1562,
7696 1563,
7697 1564,
7698 1565,
7699 1566,
7700 1567,
7701 1568,
7702 1569,
7703 1570,
7704 1571,
7705 1572,
7706 1573,
7707 1574,
7708 1575,
7709 1576,
7710 1577,
7711 1578,
7712 1579,
7713 1580,
7714 1581,
7715 1582,
7716 1583,
7717 1584,
7718 1585,
7719 1586,
7720 1587,
7721 1588,
7722 1589,
7723 1590,
7724 1591,
7725 1592,
7726 1593,
7727 1594,
7728 1595,
7729 1596,
7730 1597,
7731 1598,
7732 1599,
7733 1600,
7734 1601,
7735 1602,
7736 1603,
7737 1604,
7738 1605,
7739 1606,
7740 1607,
7741 1608,
7742 1609,
7743 1610,
7744 1611,
7745 1612,
7746 1613,
7747 1614,
7748 1615,
7749 1616,
7750 1617,
7751 1618,
7752 1619,
7753 1620,
7754 1621,
7755 1622,
7756 1623,
7757 1624,
7758 1625,
7759 1626,
7760 1627,
7761 1628,
7762 1629,
7763 1630,
7764 1631,
7765 1632,
7766 1633,
7767 1634,
7768 1635,
7769 1636,
7770 1637,
7771 1638,
7772 1639,
7773 1640,
7774 1641,
7775 1642,
7776 1643,
7777 1644,
7778 1645,
7779 1646,
7780 1647,
7781 1648,
7782 1649,
7783 1650,
7784 1651,
7785 1652,
7786 1653,
7787 1654,
7788 1655,
7789 1656,
7790 1657,
7791 1658,
7792 1659,
7793 1660,
7794 1661,
7795 1662,
7796 1663,
7797 0,
7798 1,
7799 2,
7800 3,
7801 4,
7802 5,
7803 6,
7804 7,
7805 8,
7806 9,
7807 10,
7808 11,
7809 12,
7810 13,
7811 14,
7812 15,
7813 16,
7814 17,
7815 18,
7816 19,
7817 20,
7818 21,
7819 22,
7820 23,
7821 24,
7822 25,
7823 26,
7824 27,
7825 28,
7826 29,
7827 30,
7828 31,
7829 32,
7830 33,
7831 34,
7832 35,
7833 36,
7834 37,
7835 38,
7836 39,
7837 40,
7838 41,
7839 42,
7840 43,
7841 44,
7842 45,
7843 46,
7844 47,
7845 48,
7846 49,
7847 50,
7848 51,
7849 52,
7850 53,
7851 54,
7852 55,
7853 56,
7854 57,
7855 58,
7856 59,
7857 60,
7858 61,
7859 62,
7860 63,
7861 64,
7862 65,
7863 66,
7864 67,
7865 68,
7866 69,
7867 70,
7868 71,
7869 72,
7870 73,
7871 74,
7872 75,
7873 76,
7874 77,
7875 78,
7876 79,
7877 80,
7878 81,
7879 82,
7880 83,
7881 84,
7882 85,
7883 86,
7884 87,
7885 88,
7886 89,
7887 90,
7888 91,
7889 92,
7890 93,
7891 94,
7892 95,
7893 96,
7894 97,
7895 98,
7896 99,
7897 100,
7898 101,
7899 102,
7900 103,
7901 104,
7902 105,
7903 106,
7904 107,
7905 108,
7906 109,
7907 110,
7908 111,
7909 112,
7910 113,
7911 114,
7912 115,
7913 116,
7914 117,
7915 118,
7916 119,
7917 120,
7918 121,
7919 122,
7920 123,
7921 124,
7922 125,
7923 126,
7924 127,
7925 0,
7926 1,
7927 2,
7928 3,
7929 4,
7930 5,
7931 6,
7932 7,
7933 8,
7934 9,
7935 10,
7936 11,
7937 12,
7938 13,
7939 14,
7940 15,
7941 16,
7942 17,
7943 18,
7944 19,
7945 20,
7946 21,
7947 22,
7948 23,
7949 24,
7950 25,
7951 26,
7952 27,
7953 28,
7954 29,
7955 30,
7956 31,
7957 32,
7958 33,
7959 34,
7960 35,
7961 36,
7962 37,
7963 38,
7964 39,
7965 40,
7966 41,
7967 42,
7968 43,
7969 44,
7970 45,
7971 46,
7972 47,
7973 48,
7974 49,
7975 50,
7976 51,
7977 52,
7978 53,
7979 54,
7980 55,
7981 56,
7982 57,
7983 58,
7984 59,
7985 60,
7986 61,
7987 62,
7988 63,
7989 64,
7990 65,
7991 66,
7992 67,
7993 68,
7994 69,
7995 70,
7996 71,
7997 72,
7998 73,
7999 74,
8000 75,
8001 76,
8002 77,
8003 78,
8004 79,
8005 80,
8006 81,
8007 82,
8008 83,
8009 84,
8010 85,
8011 86,
8012 87,
8013 88,
8014 89,
8015 90,
8016 91,
8017 92,
8018 93,
8019 94,
8020 95,
8021 96,
8022 97,
8023 98,
8024 99,
8025 100,
8026 101,
8027 102,
8028 103,
8029 104,
8030 105,
8031 106,
8032 107,
8033 108,
8034 109,
8035 110,
8036 111,
8037 112,
8038 113,
8039 114,
8040 115,
8041 116,
8042 117,
8043 118,
8044 119,
8045 120,
8046 121,
8047 122,
8048 123,
8049 124,
8050 125,
8051 126,
8052 127,
8053 0,
8054 1,
8055 2,
8056 3,
8057 4,
8058 5,
8059 6,
8060 7,
8061 8,
8062 9,
8063 10,
8064 11,
8065 12,
8066 13,
8067 14,
8068 15,
8069 16,
8070 17,
8071 18,
8072 19,
8073 20,
8074 21,
8075 22,
8076 23,
8077 24,
8078 25,
8079 26,
8080 27,
8081 28,
8082 29,
8083 30,
8084 31,
8085 32,
8086 33,
8087 34,
8088 35,
8089 36,
8090 37,
8091 38,
8092 39,
8093 40,
8094 41,
8095 42,
8096 43,
8097 44,
8098 45,
8099 46,
8100 47,
8101 48,
8102 49,
8103 50,
8104 51,
8105 52,
8106 53,
8107 54,
8108 55,
8109 56,
8110 57,
8111 58,
8112 59,
8113 60,
8114 61,
8115 62,
8116 63,
8117 64,
8118 65,
8119 66,
8120 67,
8121 68,
8122 69,
8123 70,
8124 71,
8125 72,
8126 73,
8127 74,
8128 75,
8129 76,
8130 77,
8131 78,
8132 79,
8133 80,
8134 81,
8135 82,
8136 83,
8137 84,
8138 85,
8139 86,
8140 87,
8141 88,
8142 89,
8143 90,
8144 91,
8145 92,
8146 93,
8147 94,
8148 95,
8149 96,
8150 97,
8151 98,
8152 99,
8153 100,
8154 101,
8155 102,
8156 103,
8157 104,
8158 105,
8159 106,
8160 107,
8161 108,
8162 109,
8163 110,
8164 111,
8165 112,
8166 113,
8167 114,
8168 115,
8169 116,
8170 117,
8171 118,
8172 119,
8173 120,
8174 121,
8175 122,
8176 123,
8177 124,
8178 125,
8179 126,
8180 127,
8181 512,
8182 513,
8183 514,
8184 515,
8185 516,
8186 517,
8187 518,
8188 519,
8189 520,
8190 521,
8191 522,
8192 523,
8193 524,
8194 525,
8195 526,
8196 527,
8197 528,
8198 529,
8199 530,
8200 531,
8201 532,
8202 533,
8203 534,
8204 535,
8205 536,
8206 537,
8207 538,
8208 539,
8209 540,
8210 541,
8211 542,
8212 543,
8213 544,
8214 545,
8215 546,
8216 547,
8217 548,
8218 549,
8219 550,
8220 551,
8221 552,
8222 553,
8223 554,
8224 555,
8225 556,
8226 557,
8227 558,
8228 559,
8229 560,
8230 561,
8231 562,
8232 563,
8233 564,
8234 565,
8235 566,
8236 567,
8237 568,
8238 569,
8239 570,
8240 571,
8241 572,
8242 573,
8243 574,
8244 575,
8245 576,
8246 577,
8247 578,
8248 579,
8249 580,
8250 581,
8251 582,
8252 583,
8253 584,
8254 585,
8255 586,
8256 587,
8257 588,
8258 589,
8259 590,
8260 591,
8261 592,
8262 593,
8263 594,
8264 595,
8265 596,
8266 597,
8267 598,
8268 599,
8269 600,
8270 601,
8271 602,
8272 603,
8273 604,
8274 605,
8275 606,
8276 607,
8277 608,
8278 609,
8279 610,
8280 611,
8281 612,
8282 613,
8283 614,
8284 615,
8285 616,
8286 617,
8287 618,
8288 619,
8289 620,
8290 621,
8291 622,
8292 623,
8293 624,
8294 625,
8295 626,
8296 627,
8297 628,
8298 629,
8299 630,
8300 631,
8301 632,
8302 633,
8303 634,
8304 635,
8305 636,
8306 637,
8307 638,
8308 639,
8309 1024,
8310 1025,
8311 1026,
8312 1027,
8313 1028,
8314 1029,
8315 1030,
8316 1031,
8317 1032,
8318 1033,
8319 1034,
8320 1035,
8321 1036,
8322 1037,
8323 1038,
8324 1039,
8325 1040,
8326 1041,
8327 1042,
8328 1043,
8329 1044,
8330 1045,
8331 1046,
8332 1047,
8333 1048,
8334 1049,
8335 1050,
8336 1051,
8337 1052,
8338 1053,
8339 1054,
8340 1055,
8341 1056,
8342 1057,
8343 1058,
8344 1059,
8345 1060,
8346 1061,
8347 1062,
8348 1063,
8349 1064,
8350 1065,
8351 1066,
8352 1067,
8353 1068,
8354 1069,
8355 1070,
8356 1071,
8357 1072,
8358 1073,
8359 1074,
8360 1075,
8361 1076,
8362 1077,
8363 1078,
8364 1079,
8365 1080,
8366 1081,
8367 1082,
8368 1083,
8369 1084,
8370 1085,
8371 1086,
8372 1087,
8373 1088,
8374 1089,
8375 1090,
8376 1091,
8377 1092,
8378 1093,
8379 1094,
8380 1095,
8381 1096,
8382 1097,
8383 1098,
8384 1099,
8385 1100,
8386 1101,
8387 1102,
8388 1103,
8389 1104,
8390 1105,
8391 1106,
8392 1107,
8393 1108,
8394 1109,
8395 1110,
8396 1111,
8397 1112,
8398 1113,
8399 1114,
8400 1115,
8401 1116,
8402 1117,
8403 1118,
8404 1119,
8405 1120,
8406 1121,
8407 1122,
8408 1123,
8409 1124,
8410 1125,
8411 1126,
8412 1127,
8413 1128,
8414 1129,
8415 1130,
8416 1131,
8417 1132,
8418 1133,
8419 1134,
8420 1135,
8421 1136,
8422 1137,
8423 1138,
8424 1139,
8425 1140,
8426 1141,
8427 1142,
8428 1143,
8429 1144,
8430 1145,
8431 1146,
8432 1147,
8433 1148,
8434 1149,
8435 1150,
8436 1151,
8437 1536,
8438 1538,
8439 1536,
8440 0,
8441 2,
8442 0,
8443 512,
8444 514,
8445 512,
8446 1024,
8447 1026,
8448 1024,
8449 1664,
8450 1665,
8451 1666,
8452 1667,
8453 1668,
8454 1669,
8455 1670,
8456 1671,
8457 1672,
8458 1673,
8459 1674,
8460 1675,
8461 1676,
8462 1677,
8463 1678,
8464 1679,
8465 1680,
8466 1681,
8467 1682,
8468 1683,
8469 1684,
8470 1685,
8471 1686,
8472 1687,
8473 1688,
8474 1689,
8475 1690,
8476 1691,
8477 1692,
8478 1693,
8479 1694,
8480 1695,
8481 1696,
8482 1697,
8483 1698,
8484 1699,
8485 1700,
8486 1701,
8487 1702,
8488 1703,
8489 1704,
8490 1705,
8491 1706,
8492 1707,
8493 1708,
8494 1709,
8495 1710,
8496 1711,
8497 1712,
8498 1713,
8499 1714,
8500 1715,
8501 1716,
8502 1717,
8503 1718,
8504 1719,
8505 1720,
8506 1721,
8507 1722,
8508 1723,
8509 1724,
8510 1725,
8511 1726,
8512 1727,
8513 128,
8514 129,
8515 130,
8516 131,
8517 132,
8518 133,
8519 134,
8520 135,
8521 136,
8522 137,
8523 138,
8524 139,
8525 140,
8526 141,
8527 142,
8528 143,
8529 144,
8530 145,
8531 146,
8532 147,
8533 148,
8534 149,
8535 150,
8536 151,
8537 152,
8538 153,
8539 154,
8540 155,
8541 156,
8542 157,
8543 158,
8544 159,
8545 160,
8546 161,
8547 162,
8548 163,
8549 164,
8550 165,
8551 166,
8552 167,
8553 168,
8554 169,
8555 170,
8556 171,
8557 172,
8558 173,
8559 174,
8560 175,
8561 176,
8562 177,
8563 178,
8564 179,
8565 180,
8566 181,
8567 182,
8568 183,
8569 184,
8570 185,
8571 186,
8572 187,
8573 188,
8574 189,
8575 190,
8576 191,
8577 128,
8578 129,
8579 130,
8580 131,
8581 132,
8582 133,
8583 134,
8584 135,
8585 136,
8586 137,
8587 138,
8588 139,
8589 140,
8590 141,
8591 142,
8592 143,
8593 144,
8594 145,
8595 146,
8596 147,
8597 148,
8598 149,
8599 150,
8600 151,
8601 152,
8602 153,
8603 154,
8604 155,
8605 156,
8606 157,
8607 158,
8608 159,
8609 160,
8610 161,
8611 162,
8612 163,
8613 164,
8614 165,
8615 166,
8616 167,
8617 168,
8618 169,
8619 170,
8620 171,
8621 172,
8622 173,
8623 174,
8624 175,
8625 176,
8626 177,
8627 178,
8628 179,
8629 180,
8630 181,
8631 182,
8632 183,
8633 184,
8634 185,
8635 186,
8636 187,
8637 188,
8638 189,
8639 190,
8640 191,
8641 640,
8642 641,
8643 642,
8644 643,
8645 644,
8646 645,
8647 646,
8648 647,
8649 648,
8650 649,
8651 650,
8652 651,
8653 652,
8654 653,
8655 654,
8656 655,
8657 656,
8658 657,
8659 658,
8660 659,
8661 660,
8662 661,
8663 662,
8664 663,
8665 664,
8666 665,
8667 666,
8668 667,
8669 668,
8670 669,
8671 670,
8672 671,
8673 672,
8674 673,
8675 674,
8676 675,
8677 676,
8678 677,
8679 678,
8680 679,
8681 680,
8682 681,
8683 682,
8684 683,
8685 684,
8686 685,
8687 686,
8688 687,
8689 688,
8690 689,
8691 690,
8692 691,
8693 692,
8694 693,
8695 694,
8696 695,
8697 696,
8698 697,
8699 698,
8700 699,
8701 700,
8702 701,
8703 702,
8704 703,
8705 1152,
8706 1153,
8707 1154,
8708 1155,
8709 1156,
8710 1157,
8711 1158,
8712 1159,
8713 1160,
8714 1161,
8715 1162,
8716 1163,
8717 1164,
8718 1165,
8719 1166,
8720 1167,
8721 1168,
8722 1169,
8723 1170,
8724 1171,
8725 1172,
8726 1173,
8727 1174,
8728 1175,
8729 1176,
8730 1177,
8731 1178,
8732 1179,
8733 1180,
8734 1181,
8735 1182,
8736 1183,
8737 1184,
8738 1185,
8739 1186,
8740 1187,
8741 1188,
8742 1189,
8743 1190,
8744 1191,
8745 1192,
8746 1193,
8747 1194,
8748 1195,
8749 1196,
8750 1197,
8751 1198,
8752 1199,
8753 1200,
8754 1201,
8755 1202,
8756 1203,
8757 1204,
8758 1205,
8759 1206,
8760 1207,
8761 1208,
8762 1209,
8763 1210,
8764 1211,
8765 1212,
8766 1213,
8767 1214,
8768 1215,
8769};
8770static inline void InitR600MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
8771 RI->InitMCRegisterInfo(R600RegDesc, 1675, RA, PC, R600MCRegisterClasses, 37, R600RegUnitRoots, 1342, R600RegDiffLists, R600LaneMaskLists, R600RegStrings, R600RegClassStrings, R600SubRegIdxLists, 17,
8772R600RegEncodingTable);
8773
8774}
8775
8776} // end namespace llvm
8777
8778#endif // GET_REGINFO_MC_DESC
8779
8780/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
8781|* *|
8782|* Register Information Header Fragment *|
8783|* *|
8784|* Automatically generated file, do not edit! *|
8785|* *|
8786\*===----------------------------------------------------------------------===*/
8787
8788
8789#ifdef GET_REGINFO_HEADER
8790#undef GET_REGINFO_HEADER
8791
8792#include "llvm/CodeGen/TargetRegisterInfo.h"
8793
8794namespace llvm {
8795
8796class R600FrameLowering;
8797
8798struct R600GenRegisterInfo : public TargetRegisterInfo {
8799 explicit R600GenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
8800 unsigned PC = 0, unsigned HwMode = 0);
8801 unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
8802 unsigned reverseComposeSubRegIndicesImpl(unsigned, unsigned) const override;
8803 LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
8804 LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
8805 const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass *, unsigned) const override;
8806 const TargetRegisterClass *getSubRegisterClass(const TargetRegisterClass *, unsigned) const override;
8807 const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
8808 unsigned getRegUnitWeight(unsigned RegUnit) const override;
8809 unsigned getNumRegPressureSets() const override;
8810 const char *getRegPressureSetName(unsigned Idx) const override;
8811 unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
8812 const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
8813 const int *getRegUnitPressureSets(unsigned RegUnit) const override;
8814 ArrayRef<const char *> getRegMaskNames() const override;
8815 ArrayRef<const uint32_t *> getRegMasks() const override;
8816 bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override;
8817 bool isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const override;
8818 bool isFixedRegister(const MachineFunction &, MCRegister) const override;
8819 bool isArgumentRegister(const MachineFunction &, MCRegister) const override;
8820 bool isConstantPhysReg(MCRegister PhysReg) const override final;
8821 /// Devirtualized TargetFrameLowering.
8822 static const R600FrameLowering *getFrameLowering(
8823 const MachineFunction &MF);
8824};
8825
8826namespace R600 { // Register classes
8827 extern const TargetRegisterClass R600_Reg32RegClass;
8828 extern const TargetRegisterClass R600_TReg32RegClass;
8829 extern const TargetRegisterClass R600_TReg32_XRegClass;
8830 extern const TargetRegisterClass R600_AddrRegClass;
8831 extern const TargetRegisterClass R600_KC0RegClass;
8832 extern const TargetRegisterClass R600_KC1RegClass;
8833 extern const TargetRegisterClass R600_TReg32_WRegClass;
8834 extern const TargetRegisterClass R600_TReg32_YRegClass;
8835 extern const TargetRegisterClass R600_TReg32_ZRegClass;
8836 extern const TargetRegisterClass R600_ArrayBaseRegClass;
8837 extern const TargetRegisterClass R600_KC0_WRegClass;
8838 extern const TargetRegisterClass R600_KC0_XRegClass;
8839 extern const TargetRegisterClass R600_KC0_YRegClass;
8840 extern const TargetRegisterClass R600_KC0_ZRegClass;
8841 extern const TargetRegisterClass R600_KC1_WRegClass;
8842 extern const TargetRegisterClass R600_KC1_XRegClass;
8843 extern const TargetRegisterClass R600_KC1_YRegClass;
8844 extern const TargetRegisterClass R600_KC1_ZRegClass;
8845 extern const TargetRegisterClass R600_LDS_SRC_REGRegClass;
8846 extern const TargetRegisterClass R600_PredicateRegClass;
8847 extern const TargetRegisterClass R600_Addr_WRegClass;
8848 extern const TargetRegisterClass R600_Addr_YRegClass;
8849 extern const TargetRegisterClass R600_Addr_ZRegClass;
8850 extern const TargetRegisterClass R600_LDS_SRC_REG_and_R600_Reg32RegClass;
8851 extern const TargetRegisterClass R600_Predicate_BitRegClass;
8852 extern const TargetRegisterClass R600_Reg64RegClass;
8853 extern const TargetRegisterClass R600_Reg64VerticalRegClass;
8854 extern const TargetRegisterClass R600_Reg64Vertical_with_sub0_in_R600_TReg32_WRegClass;
8855 extern const TargetRegisterClass R600_Reg64Vertical_with_sub0_in_R600_TReg32_XRegClass;
8856 extern const TargetRegisterClass R600_Reg64Vertical_with_sub0_in_R600_TReg32_YRegClass;
8857 extern const TargetRegisterClass R600_Reg64Vertical_with_sub0_in_R600_TReg32_ZRegClass;
8858 extern const TargetRegisterClass R600_Reg128RegClass;
8859 extern const TargetRegisterClass R600_Reg128VerticalRegClass;
8860 extern const TargetRegisterClass R600_Reg128Vertical_with_sub0_in_R600_TReg32_WRegClass;
8861 extern const TargetRegisterClass R600_Reg128Vertical_with_sub0_in_R600_TReg32_XRegClass;
8862 extern const TargetRegisterClass R600_Reg128Vertical_with_sub0_in_R600_TReg32_YRegClass;
8863 extern const TargetRegisterClass R600_Reg128Vertical_with_sub0_in_R600_TReg32_ZRegClass;
8864} // end namespace R600
8865
8866} // end namespace llvm
8867
8868#endif // GET_REGINFO_HEADER
8869
8870/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
8871|* *|
8872|* Target Register and Register Classes Information *|
8873|* *|
8874|* Automatically generated file, do not edit! *|
8875|* *|
8876\*===----------------------------------------------------------------------===*/
8877
8878
8879#ifdef GET_REGINFO_TARGET_DESC
8880#undef GET_REGINFO_TARGET_DESC
8881
8882namespace llvm {
8883
8884extern const MCRegisterClass R600MCRegisterClasses[];
8885
8886static const MVT::SimpleValueType VTLists[] = {
8887 /* 0 */ MVT::f32, MVT::i32, MVT::Other,
8888 /* 3 */ MVT::v2f32, MVT::v2i32, MVT::i64, MVT::f64, MVT::Other,
8889 /* 8 */ MVT::v2f32, MVT::v2i32, MVT::Other,
8890 /* 11 */ MVT::v4f32, MVT::v4i32, MVT::Other,
8891};
8892
8893static const char *SubRegIndexNameTable[] = { "sub0", "sub1", "sub2", "sub3", "sub4", "sub5", "sub6", "sub7", "sub8", "sub9", "sub10", "sub11", "sub12", "sub13", "sub14", "sub15", "" };
8894
8895static const TargetRegisterInfo::SubRegCoveredBits SubRegIdxRangeTable[] = {
8896 { 65535, 65535 },
8897 { 0, 32 }, // sub0
8898 { 32, 32 }, // sub1
8899 { 64, 32 }, // sub2
8900 { 96, 32 }, // sub3
8901 { 128, 32 }, // sub4
8902 { 160, 32 }, // sub5
8903 { 192, 32 }, // sub6
8904 { 224, 32 }, // sub7
8905 { 256, 32 }, // sub8
8906 { 288, 32 }, // sub9
8907 { 320, 32 }, // sub10
8908 { 352, 32 }, // sub11
8909 { 384, 32 }, // sub12
8910 { 416, 32 }, // sub13
8911 { 448, 32 }, // sub14
8912 { 480, 32 }, // sub15
8913};
8914
8915
8916static const LaneBitmask SubRegIndexLaneMaskTable[] = {
8917 LaneBitmask::getAll(),
8918 LaneBitmask(0x0000000000000001), // sub0
8919 LaneBitmask(0x0000000000000002), // sub1
8920 LaneBitmask(0x0000000000000004), // sub2
8921 LaneBitmask(0x0000000000000008), // sub3
8922 LaneBitmask(0x0000000000000010), // sub4
8923 LaneBitmask(0x0000000000000020), // sub5
8924 LaneBitmask(0x0000000000000040), // sub6
8925 LaneBitmask(0x0000000000000080), // sub7
8926 LaneBitmask(0x0000000000000100), // sub8
8927 LaneBitmask(0x0000000000000200), // sub9
8928 LaneBitmask(0x0000000000000400), // sub10
8929 LaneBitmask(0x0000000000000800), // sub11
8930 LaneBitmask(0x0000000000001000), // sub12
8931 LaneBitmask(0x0000000000002000), // sub13
8932 LaneBitmask(0x0000000000004000), // sub14
8933 LaneBitmask(0x0000000000008000), // sub15
8934 };
8935
8936
8937
8938static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
8939 // Mode = 0 (Default)
8940 { 32, 32, 32, /*VTLists+*/0 }, // R600_Reg32
8941 { 32, 32, 32, /*VTLists+*/0 }, // R600_TReg32
8942 { 32, 32, 32, /*VTLists+*/0 }, // R600_TReg32_X
8943 { 32, 32, 32, /*VTLists+*/1 }, // R600_Addr
8944 { 32, 32, 32, /*VTLists+*/0 }, // R600_KC0
8945 { 32, 32, 32, /*VTLists+*/0 }, // R600_KC1
8946 { 32, 32, 32, /*VTLists+*/0 }, // R600_TReg32_W
8947 { 32, 32, 32, /*VTLists+*/0 }, // R600_TReg32_Y
8948 { 32, 32, 32, /*VTLists+*/0 }, // R600_TReg32_Z
8949 { 32, 32, 32, /*VTLists+*/0 }, // R600_ArrayBase
8950 { 32, 32, 32, /*VTLists+*/0 }, // R600_KC0_W
8951 { 32, 32, 32, /*VTLists+*/0 }, // R600_KC0_X
8952 { 32, 32, 32, /*VTLists+*/0 }, // R600_KC0_Y
8953 { 32, 32, 32, /*VTLists+*/0 }, // R600_KC0_Z
8954 { 32, 32, 32, /*VTLists+*/0 }, // R600_KC1_W
8955 { 32, 32, 32, /*VTLists+*/0 }, // R600_KC1_X
8956 { 32, 32, 32, /*VTLists+*/0 }, // R600_KC1_Y
8957 { 32, 32, 32, /*VTLists+*/0 }, // R600_KC1_Z
8958 { 32, 32, 32, /*VTLists+*/1 }, // R600_LDS_SRC_REG
8959 { 32, 32, 32, /*VTLists+*/1 }, // R600_Predicate
8960 { 32, 32, 32, /*VTLists+*/1 }, // R600_Addr_W
8961 { 32, 32, 32, /*VTLists+*/1 }, // R600_Addr_Y
8962 { 32, 32, 32, /*VTLists+*/1 }, // R600_Addr_Z
8963 { 32, 32, 32, /*VTLists+*/0 }, // R600_LDS_SRC_REG_and_R600_Reg32
8964 { 32, 32, 32, /*VTLists+*/1 }, // R600_Predicate_Bit
8965 { 64, 64, 64, /*VTLists+*/3 }, // R600_Reg64
8966 { 64, 64, 64, /*VTLists+*/8 }, // R600_Reg64Vertical
8967 { 64, 64, 64, /*VTLists+*/8 }, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W
8968 { 64, 64, 64, /*VTLists+*/8 }, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X
8969 { 64, 64, 64, /*VTLists+*/8 }, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y
8970 { 64, 64, 64, /*VTLists+*/8 }, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z
8971 { 128, 128, 128, /*VTLists+*/11 }, // R600_Reg128
8972 { 128, 128, 128, /*VTLists+*/11 }, // R600_Reg128Vertical
8973 { 128, 128, 128, /*VTLists+*/11 }, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W
8974 { 128, 128, 128, /*VTLists+*/11 }, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X
8975 { 128, 128, 128, /*VTLists+*/11 }, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y
8976 { 128, 128, 128, /*VTLists+*/11 }, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z
8977};
8978static const uint32_t R600_Reg32SubClassMask[] = {
8979 0x0083ffff, 0x00000000,
8980 0xfe000000, 0x0000001f, // sub0
8981 0xfe000000, 0x0000001f, // sub1
8982 0x80000000, 0x0000001f, // sub2
8983 0x80000000, 0x0000001f, // sub3
8984};
8985
8986static const uint32_t R600_TReg32SubClassMask[] = {
8987 0x000001c6, 0x00000000,
8988 0xfe000000, 0x0000001f, // sub0
8989 0xfe000000, 0x0000001f, // sub1
8990 0x80000000, 0x0000001f, // sub2
8991 0x80000000, 0x0000001f, // sub3
8992};
8993
8994static const uint32_t R600_TReg32_XSubClassMask[] = {
8995 0x00000004, 0x00000000,
8996 0x92000000, 0x00000004, // sub0
8997 0x10000000, 0x00000004, // sub1
8998 0x00000000, 0x00000004, // sub2
8999 0x00000000, 0x00000004, // sub3
9000};
9001
9002static const uint32_t R600_AddrSubClassMask[] = {
9003 0x00000008, 0x00000000,
9004};
9005
9006static const uint32_t R600_KC0SubClassMask[] = {
9007 0x00003c10, 0x00000000,
9008};
9009
9010static const uint32_t R600_KC1SubClassMask[] = {
9011 0x0003c020, 0x00000000,
9012};
9013
9014static const uint32_t R600_TReg32_WSubClassMask[] = {
9015 0x00000040, 0x00000000,
9016 0x08000000, 0x00000002, // sub0
9017 0x08000000, 0x00000002, // sub1
9018 0x00000000, 0x00000002, // sub2
9019 0x80000000, 0x00000002, // sub3
9020};
9021
9022static const uint32_t R600_TReg32_YSubClassMask[] = {
9023 0x00000080, 0x00000000,
9024 0x20000000, 0x00000008, // sub0
9025 0xa2000000, 0x00000008, // sub1
9026 0x00000000, 0x00000008, // sub2
9027 0x00000000, 0x00000008, // sub3
9028};
9029
9030static const uint32_t R600_TReg32_ZSubClassMask[] = {
9031 0x00000100, 0x00000000,
9032 0x40000000, 0x00000010, // sub0
9033 0x40000000, 0x00000010, // sub1
9034 0x80000000, 0x00000010, // sub2
9035 0x00000000, 0x00000010, // sub3
9036};
9037
9038static const uint32_t R600_ArrayBaseSubClassMask[] = {
9039 0x00000200, 0x00000000,
9040};
9041
9042static const uint32_t R600_KC0_WSubClassMask[] = {
9043 0x00000400, 0x00000000,
9044};
9045
9046static const uint32_t R600_KC0_XSubClassMask[] = {
9047 0x00000800, 0x00000000,
9048};
9049
9050static const uint32_t R600_KC0_YSubClassMask[] = {
9051 0x00001000, 0x00000000,
9052};
9053
9054static const uint32_t R600_KC0_ZSubClassMask[] = {
9055 0x00002000, 0x00000000,
9056};
9057
9058static const uint32_t R600_KC1_WSubClassMask[] = {
9059 0x00004000, 0x00000000,
9060};
9061
9062static const uint32_t R600_KC1_XSubClassMask[] = {
9063 0x00008000, 0x00000000,
9064};
9065
9066static const uint32_t R600_KC1_YSubClassMask[] = {
9067 0x00010000, 0x00000000,
9068};
9069
9070static const uint32_t R600_KC1_ZSubClassMask[] = {
9071 0x00020000, 0x00000000,
9072};
9073
9074static const uint32_t R600_LDS_SRC_REGSubClassMask[] = {
9075 0x00840000, 0x00000000,
9076};
9077
9078static const uint32_t R600_PredicateSubClassMask[] = {
9079 0x00080000, 0x00000000,
9080};
9081
9082static const uint32_t R600_Addr_WSubClassMask[] = {
9083 0x00100000, 0x00000000,
9084};
9085
9086static const uint32_t R600_Addr_YSubClassMask[] = {
9087 0x00200000, 0x00000000,
9088};
9089
9090static const uint32_t R600_Addr_ZSubClassMask[] = {
9091 0x00400000, 0x00000000,
9092};
9093
9094static const uint32_t R600_LDS_SRC_REG_and_R600_Reg32SubClassMask[] = {
9095 0x00800000, 0x00000000,
9096};
9097
9098static const uint32_t R600_Predicate_BitSubClassMask[] = {
9099 0x01000000, 0x00000000,
9100};
9101
9102static const uint32_t R600_Reg64SubClassMask[] = {
9103 0x02000000, 0x00000000,
9104};
9105
9106static const uint32_t R600_Reg64VerticalSubClassMask[] = {
9107 0x7c000000, 0x00000000,
9108};
9109
9110static const uint32_t R600_Reg64Vertical_with_sub0_in_R600_TReg32_WSubClassMask[] = {
9111 0x08000000, 0x00000000,
9112};
9113
9114static const uint32_t R600_Reg64Vertical_with_sub0_in_R600_TReg32_XSubClassMask[] = {
9115 0x10000000, 0x00000000,
9116};
9117
9118static const uint32_t R600_Reg64Vertical_with_sub0_in_R600_TReg32_YSubClassMask[] = {
9119 0x20000000, 0x00000000,
9120};
9121
9122static const uint32_t R600_Reg64Vertical_with_sub0_in_R600_TReg32_ZSubClassMask[] = {
9123 0x40000000, 0x00000000,
9124};
9125
9126static const uint32_t R600_Reg128SubClassMask[] = {
9127 0x80000000, 0x00000000,
9128};
9129
9130static const uint32_t R600_Reg128VerticalSubClassMask[] = {
9131 0x00000000, 0x0000001f,
9132};
9133
9134static const uint32_t R600_Reg128Vertical_with_sub0_in_R600_TReg32_WSubClassMask[] = {
9135 0x00000000, 0x00000002,
9136};
9137
9138static const uint32_t R600_Reg128Vertical_with_sub0_in_R600_TReg32_XSubClassMask[] = {
9139 0x00000000, 0x00000004,
9140};
9141
9142static const uint32_t R600_Reg128Vertical_with_sub0_in_R600_TReg32_YSubClassMask[] = {
9143 0x00000000, 0x00000008,
9144};
9145
9146static const uint32_t R600_Reg128Vertical_with_sub0_in_R600_TReg32_ZSubClassMask[] = {
9147 0x00000000, 0x00000010,
9148};
9149
9150static const uint16_t SuperRegIdxSeqs[] = {
9151 /* 0 */ 1, 2, 3, 4, 0,
9152};
9153
9154static unsigned const R600_TReg32Superclasses[] = {
9155 R600::R600_Reg32RegClassID,
9156};
9157
9158static unsigned const R600_TReg32_XSuperclasses[] = {
9159 R600::R600_Reg32RegClassID,
9160 R600::R600_TReg32RegClassID,
9161};
9162
9163static unsigned const R600_AddrSuperclasses[] = {
9164 R600::R600_Reg32RegClassID,
9165};
9166
9167static unsigned const R600_KC0Superclasses[] = {
9168 R600::R600_Reg32RegClassID,
9169};
9170
9171static unsigned const R600_KC1Superclasses[] = {
9172 R600::R600_Reg32RegClassID,
9173};
9174
9175static unsigned const R600_TReg32_WSuperclasses[] = {
9176 R600::R600_Reg32RegClassID,
9177 R600::R600_TReg32RegClassID,
9178};
9179
9180static unsigned const R600_TReg32_YSuperclasses[] = {
9181 R600::R600_Reg32RegClassID,
9182 R600::R600_TReg32RegClassID,
9183};
9184
9185static unsigned const R600_TReg32_ZSuperclasses[] = {
9186 R600::R600_Reg32RegClassID,
9187 R600::R600_TReg32RegClassID,
9188};
9189
9190static unsigned const R600_ArrayBaseSuperclasses[] = {
9191 R600::R600_Reg32RegClassID,
9192};
9193
9194static unsigned const R600_KC0_WSuperclasses[] = {
9195 R600::R600_Reg32RegClassID,
9196 R600::R600_KC0RegClassID,
9197};
9198
9199static unsigned const R600_KC0_XSuperclasses[] = {
9200 R600::R600_Reg32RegClassID,
9201 R600::R600_KC0RegClassID,
9202};
9203
9204static unsigned const R600_KC0_YSuperclasses[] = {
9205 R600::R600_Reg32RegClassID,
9206 R600::R600_KC0RegClassID,
9207};
9208
9209static unsigned const R600_KC0_ZSuperclasses[] = {
9210 R600::R600_Reg32RegClassID,
9211 R600::R600_KC0RegClassID,
9212};
9213
9214static unsigned const R600_KC1_WSuperclasses[] = {
9215 R600::R600_Reg32RegClassID,
9216 R600::R600_KC1RegClassID,
9217};
9218
9219static unsigned const R600_KC1_XSuperclasses[] = {
9220 R600::R600_Reg32RegClassID,
9221 R600::R600_KC1RegClassID,
9222};
9223
9224static unsigned const R600_KC1_YSuperclasses[] = {
9225 R600::R600_Reg32RegClassID,
9226 R600::R600_KC1RegClassID,
9227};
9228
9229static unsigned const R600_KC1_ZSuperclasses[] = {
9230 R600::R600_Reg32RegClassID,
9231 R600::R600_KC1RegClassID,
9232};
9233
9234static unsigned const R600_LDS_SRC_REG_and_R600_Reg32Superclasses[] = {
9235 R600::R600_Reg32RegClassID,
9236 R600::R600_LDS_SRC_REGRegClassID,
9237};
9238
9239static unsigned const R600_Reg64Vertical_with_sub0_in_R600_TReg32_WSuperclasses[] = {
9240 R600::R600_Reg64VerticalRegClassID,
9241};
9242
9243static unsigned const R600_Reg64Vertical_with_sub0_in_R600_TReg32_XSuperclasses[] = {
9244 R600::R600_Reg64VerticalRegClassID,
9245};
9246
9247static unsigned const R600_Reg64Vertical_with_sub0_in_R600_TReg32_YSuperclasses[] = {
9248 R600::R600_Reg64VerticalRegClassID,
9249};
9250
9251static unsigned const R600_Reg64Vertical_with_sub0_in_R600_TReg32_ZSuperclasses[] = {
9252 R600::R600_Reg64VerticalRegClassID,
9253};
9254
9255static unsigned const R600_Reg128Vertical_with_sub0_in_R600_TReg32_WSuperclasses[] = {
9256 R600::R600_Reg128VerticalRegClassID,
9257};
9258
9259static unsigned const R600_Reg128Vertical_with_sub0_in_R600_TReg32_XSuperclasses[] = {
9260 R600::R600_Reg128VerticalRegClassID,
9261};
9262
9263static unsigned const R600_Reg128Vertical_with_sub0_in_R600_TReg32_YSuperclasses[] = {
9264 R600::R600_Reg128VerticalRegClassID,
9265};
9266
9267static unsigned const R600_Reg128Vertical_with_sub0_in_R600_TReg32_ZSuperclasses[] = {
9268 R600::R600_Reg128VerticalRegClassID,
9269};
9270
9271
9272namespace R600 { // Register class instances
9273 extern const TargetRegisterClass R600_Reg32RegClass = {
9274 &R600MCRegisterClasses[R600_Reg32RegClassID],
9275 R600_Reg32SubClassMask,
9276 SuperRegIdxSeqs + 0,
9277 LaneBitmask(0x0000000000000001),
9278 0,
9279 false,
9280 0x00, /* TSFlags */
9281 false, /* HasDisjunctSubRegs */
9282 false, /* CoveredBySubRegs */
9283 nullptr, 0,
9284 nullptr
9285 };
9286
9287 extern const TargetRegisterClass R600_TReg32RegClass = {
9288 &R600MCRegisterClasses[R600_TReg32RegClassID],
9289 R600_TReg32SubClassMask,
9290 SuperRegIdxSeqs + 0,
9291 LaneBitmask(0x0000000000000001),
9292 0,
9293 false,
9294 0x00, /* TSFlags */
9295 false, /* HasDisjunctSubRegs */
9296 false, /* CoveredBySubRegs */
9297 R600_TReg32Superclasses, 1,
9298 nullptr
9299 };
9300
9301 extern const TargetRegisterClass R600_TReg32_XRegClass = {
9302 &R600MCRegisterClasses[R600_TReg32_XRegClassID],
9303 R600_TReg32_XSubClassMask,
9304 SuperRegIdxSeqs + 0,
9305 LaneBitmask(0x0000000000000001),
9306 0,
9307 false,
9308 0x00, /* TSFlags */
9309 false, /* HasDisjunctSubRegs */
9310 false, /* CoveredBySubRegs */
9311 R600_TReg32_XSuperclasses, 2,
9312 nullptr
9313 };
9314
9315 extern const TargetRegisterClass R600_AddrRegClass = {
9316 &R600MCRegisterClasses[R600_AddrRegClassID],
9317 R600_AddrSubClassMask,
9318 SuperRegIdxSeqs + 4,
9319 LaneBitmask(0x0000000000000001),
9320 0,
9321 false,
9322 0x00, /* TSFlags */
9323 false, /* HasDisjunctSubRegs */
9324 false, /* CoveredBySubRegs */
9325 R600_AddrSuperclasses, 1,
9326 nullptr
9327 };
9328
9329 extern const TargetRegisterClass R600_KC0RegClass = {
9330 &R600MCRegisterClasses[R600_KC0RegClassID],
9331 R600_KC0SubClassMask,
9332 SuperRegIdxSeqs + 4,
9333 LaneBitmask(0x0000000000000001),
9334 0,
9335 false,
9336 0x00, /* TSFlags */
9337 false, /* HasDisjunctSubRegs */
9338 false, /* CoveredBySubRegs */
9339 R600_KC0Superclasses, 1,
9340 nullptr
9341 };
9342
9343 extern const TargetRegisterClass R600_KC1RegClass = {
9344 &R600MCRegisterClasses[R600_KC1RegClassID],
9345 R600_KC1SubClassMask,
9346 SuperRegIdxSeqs + 4,
9347 LaneBitmask(0x0000000000000001),
9348 0,
9349 false,
9350 0x00, /* TSFlags */
9351 false, /* HasDisjunctSubRegs */
9352 false, /* CoveredBySubRegs */
9353 R600_KC1Superclasses, 1,
9354 nullptr
9355 };
9356
9357 extern const TargetRegisterClass R600_TReg32_WRegClass = {
9358 &R600MCRegisterClasses[R600_TReg32_WRegClassID],
9359 R600_TReg32_WSubClassMask,
9360 SuperRegIdxSeqs + 0,
9361 LaneBitmask(0x0000000000000001),
9362 0,
9363 false,
9364 0x00, /* TSFlags */
9365 false, /* HasDisjunctSubRegs */
9366 false, /* CoveredBySubRegs */
9367 R600_TReg32_WSuperclasses, 2,
9368 nullptr
9369 };
9370
9371 extern const TargetRegisterClass R600_TReg32_YRegClass = {
9372 &R600MCRegisterClasses[R600_TReg32_YRegClassID],
9373 R600_TReg32_YSubClassMask,
9374 SuperRegIdxSeqs + 0,
9375 LaneBitmask(0x0000000000000001),
9376 0,
9377 false,
9378 0x00, /* TSFlags */
9379 false, /* HasDisjunctSubRegs */
9380 false, /* CoveredBySubRegs */
9381 R600_TReg32_YSuperclasses, 2,
9382 nullptr
9383 };
9384
9385 extern const TargetRegisterClass R600_TReg32_ZRegClass = {
9386 &R600MCRegisterClasses[R600_TReg32_ZRegClassID],
9387 R600_TReg32_ZSubClassMask,
9388 SuperRegIdxSeqs + 0,
9389 LaneBitmask(0x0000000000000001),
9390 0,
9391 false,
9392 0x00, /* TSFlags */
9393 false, /* HasDisjunctSubRegs */
9394 false, /* CoveredBySubRegs */
9395 R600_TReg32_ZSuperclasses, 2,
9396 nullptr
9397 };
9398
9399 extern const TargetRegisterClass R600_ArrayBaseRegClass = {
9400 &R600MCRegisterClasses[R600_ArrayBaseRegClassID],
9401 R600_ArrayBaseSubClassMask,
9402 SuperRegIdxSeqs + 4,
9403 LaneBitmask(0x0000000000000001),
9404 0,
9405 false,
9406 0x00, /* TSFlags */
9407 false, /* HasDisjunctSubRegs */
9408 false, /* CoveredBySubRegs */
9409 R600_ArrayBaseSuperclasses, 1,
9410 nullptr
9411 };
9412
9413 extern const TargetRegisterClass R600_KC0_WRegClass = {
9414 &R600MCRegisterClasses[R600_KC0_WRegClassID],
9415 R600_KC0_WSubClassMask,
9416 SuperRegIdxSeqs + 4,
9417 LaneBitmask(0x0000000000000001),
9418 0,
9419 false,
9420 0x00, /* TSFlags */
9421 false, /* HasDisjunctSubRegs */
9422 false, /* CoveredBySubRegs */
9423 R600_KC0_WSuperclasses, 2,
9424 nullptr
9425 };
9426
9427 extern const TargetRegisterClass R600_KC0_XRegClass = {
9428 &R600MCRegisterClasses[R600_KC0_XRegClassID],
9429 R600_KC0_XSubClassMask,
9430 SuperRegIdxSeqs + 4,
9431 LaneBitmask(0x0000000000000001),
9432 0,
9433 false,
9434 0x00, /* TSFlags */
9435 false, /* HasDisjunctSubRegs */
9436 false, /* CoveredBySubRegs */
9437 R600_KC0_XSuperclasses, 2,
9438 nullptr
9439 };
9440
9441 extern const TargetRegisterClass R600_KC0_YRegClass = {
9442 &R600MCRegisterClasses[R600_KC0_YRegClassID],
9443 R600_KC0_YSubClassMask,
9444 SuperRegIdxSeqs + 4,
9445 LaneBitmask(0x0000000000000001),
9446 0,
9447 false,
9448 0x00, /* TSFlags */
9449 false, /* HasDisjunctSubRegs */
9450 false, /* CoveredBySubRegs */
9451 R600_KC0_YSuperclasses, 2,
9452 nullptr
9453 };
9454
9455 extern const TargetRegisterClass R600_KC0_ZRegClass = {
9456 &R600MCRegisterClasses[R600_KC0_ZRegClassID],
9457 R600_KC0_ZSubClassMask,
9458 SuperRegIdxSeqs + 4,
9459 LaneBitmask(0x0000000000000001),
9460 0,
9461 false,
9462 0x00, /* TSFlags */
9463 false, /* HasDisjunctSubRegs */
9464 false, /* CoveredBySubRegs */
9465 R600_KC0_ZSuperclasses, 2,
9466 nullptr
9467 };
9468
9469 extern const TargetRegisterClass R600_KC1_WRegClass = {
9470 &R600MCRegisterClasses[R600_KC1_WRegClassID],
9471 R600_KC1_WSubClassMask,
9472 SuperRegIdxSeqs + 4,
9473 LaneBitmask(0x0000000000000001),
9474 0,
9475 false,
9476 0x00, /* TSFlags */
9477 false, /* HasDisjunctSubRegs */
9478 false, /* CoveredBySubRegs */
9479 R600_KC1_WSuperclasses, 2,
9480 nullptr
9481 };
9482
9483 extern const TargetRegisterClass R600_KC1_XRegClass = {
9484 &R600MCRegisterClasses[R600_KC1_XRegClassID],
9485 R600_KC1_XSubClassMask,
9486 SuperRegIdxSeqs + 4,
9487 LaneBitmask(0x0000000000000001),
9488 0,
9489 false,
9490 0x00, /* TSFlags */
9491 false, /* HasDisjunctSubRegs */
9492 false, /* CoveredBySubRegs */
9493 R600_KC1_XSuperclasses, 2,
9494 nullptr
9495 };
9496
9497 extern const TargetRegisterClass R600_KC1_YRegClass = {
9498 &R600MCRegisterClasses[R600_KC1_YRegClassID],
9499 R600_KC1_YSubClassMask,
9500 SuperRegIdxSeqs + 4,
9501 LaneBitmask(0x0000000000000001),
9502 0,
9503 false,
9504 0x00, /* TSFlags */
9505 false, /* HasDisjunctSubRegs */
9506 false, /* CoveredBySubRegs */
9507 R600_KC1_YSuperclasses, 2,
9508 nullptr
9509 };
9510
9511 extern const TargetRegisterClass R600_KC1_ZRegClass = {
9512 &R600MCRegisterClasses[R600_KC1_ZRegClassID],
9513 R600_KC1_ZSubClassMask,
9514 SuperRegIdxSeqs + 4,
9515 LaneBitmask(0x0000000000000001),
9516 0,
9517 false,
9518 0x00, /* TSFlags */
9519 false, /* HasDisjunctSubRegs */
9520 false, /* CoveredBySubRegs */
9521 R600_KC1_ZSuperclasses, 2,
9522 nullptr
9523 };
9524
9525 extern const TargetRegisterClass R600_LDS_SRC_REGRegClass = {
9526 &R600MCRegisterClasses[R600_LDS_SRC_REGRegClassID],
9527 R600_LDS_SRC_REGSubClassMask,
9528 SuperRegIdxSeqs + 4,
9529 LaneBitmask(0x0000000000000001),
9530 0,
9531 false,
9532 0x00, /* TSFlags */
9533 false, /* HasDisjunctSubRegs */
9534 false, /* CoveredBySubRegs */
9535 nullptr, 0,
9536 nullptr
9537 };
9538
9539 extern const TargetRegisterClass R600_PredicateRegClass = {
9540 &R600MCRegisterClasses[R600_PredicateRegClassID],
9541 R600_PredicateSubClassMask,
9542 SuperRegIdxSeqs + 4,
9543 LaneBitmask(0x0000000000000001),
9544 0,
9545 false,
9546 0x00, /* TSFlags */
9547 false, /* HasDisjunctSubRegs */
9548 false, /* CoveredBySubRegs */
9549 nullptr, 0,
9550 nullptr
9551 };
9552
9553 extern const TargetRegisterClass R600_Addr_WRegClass = {
9554 &R600MCRegisterClasses[R600_Addr_WRegClassID],
9555 R600_Addr_WSubClassMask,
9556 SuperRegIdxSeqs + 4,
9557 LaneBitmask(0x0000000000000001),
9558 0,
9559 false,
9560 0x00, /* TSFlags */
9561 false, /* HasDisjunctSubRegs */
9562 false, /* CoveredBySubRegs */
9563 nullptr, 0,
9564 nullptr
9565 };
9566
9567 extern const TargetRegisterClass R600_Addr_YRegClass = {
9568 &R600MCRegisterClasses[R600_Addr_YRegClassID],
9569 R600_Addr_YSubClassMask,
9570 SuperRegIdxSeqs + 4,
9571 LaneBitmask(0x0000000000000001),
9572 0,
9573 false,
9574 0x00, /* TSFlags */
9575 false, /* HasDisjunctSubRegs */
9576 false, /* CoveredBySubRegs */
9577 nullptr, 0,
9578 nullptr
9579 };
9580
9581 extern const TargetRegisterClass R600_Addr_ZRegClass = {
9582 &R600MCRegisterClasses[R600_Addr_ZRegClassID],
9583 R600_Addr_ZSubClassMask,
9584 SuperRegIdxSeqs + 4,
9585 LaneBitmask(0x0000000000000001),
9586 0,
9587 false,
9588 0x00, /* TSFlags */
9589 false, /* HasDisjunctSubRegs */
9590 false, /* CoveredBySubRegs */
9591 nullptr, 0,
9592 nullptr
9593 };
9594
9595 extern const TargetRegisterClass R600_LDS_SRC_REG_and_R600_Reg32RegClass = {
9596 &R600MCRegisterClasses[R600_LDS_SRC_REG_and_R600_Reg32RegClassID],
9597 R600_LDS_SRC_REG_and_R600_Reg32SubClassMask,
9598 SuperRegIdxSeqs + 4,
9599 LaneBitmask(0x0000000000000001),
9600 0,
9601 false,
9602 0x00, /* TSFlags */
9603 false, /* HasDisjunctSubRegs */
9604 false, /* CoveredBySubRegs */
9605 R600_LDS_SRC_REG_and_R600_Reg32Superclasses, 2,
9606 nullptr
9607 };
9608
9609 extern const TargetRegisterClass R600_Predicate_BitRegClass = {
9610 &R600MCRegisterClasses[R600_Predicate_BitRegClassID],
9611 R600_Predicate_BitSubClassMask,
9612 SuperRegIdxSeqs + 4,
9613 LaneBitmask(0x0000000000000001),
9614 0,
9615 false,
9616 0x00, /* TSFlags */
9617 false, /* HasDisjunctSubRegs */
9618 false, /* CoveredBySubRegs */
9619 nullptr, 0,
9620 nullptr
9621 };
9622
9623 extern const TargetRegisterClass R600_Reg64RegClass = {
9624 &R600MCRegisterClasses[R600_Reg64RegClassID],
9625 R600_Reg64SubClassMask,
9626 SuperRegIdxSeqs + 4,
9627 LaneBitmask(0x0000000000000003),
9628 0,
9629 false,
9630 0x00, /* TSFlags */
9631 true, /* HasDisjunctSubRegs */
9632 false, /* CoveredBySubRegs */
9633 nullptr, 0,
9634 nullptr
9635 };
9636
9637 extern const TargetRegisterClass R600_Reg64VerticalRegClass = {
9638 &R600MCRegisterClasses[R600_Reg64VerticalRegClassID],
9639 R600_Reg64VerticalSubClassMask,
9640 SuperRegIdxSeqs + 4,
9641 LaneBitmask(0x0000000000000003),
9642 0,
9643 false,
9644 0x00, /* TSFlags */
9645 true, /* HasDisjunctSubRegs */
9646 false, /* CoveredBySubRegs */
9647 nullptr, 0,
9648 nullptr
9649 };
9650
9651 extern const TargetRegisterClass R600_Reg64Vertical_with_sub0_in_R600_TReg32_WRegClass = {
9652 &R600MCRegisterClasses[R600_Reg64Vertical_with_sub0_in_R600_TReg32_WRegClassID],
9653 R600_Reg64Vertical_with_sub0_in_R600_TReg32_WSubClassMask,
9654 SuperRegIdxSeqs + 4,
9655 LaneBitmask(0x0000000000000003),
9656 0,
9657 false,
9658 0x00, /* TSFlags */
9659 true, /* HasDisjunctSubRegs */
9660 false, /* CoveredBySubRegs */
9661 R600_Reg64Vertical_with_sub0_in_R600_TReg32_WSuperclasses, 1,
9662 nullptr
9663 };
9664
9665 extern const TargetRegisterClass R600_Reg64Vertical_with_sub0_in_R600_TReg32_XRegClass = {
9666 &R600MCRegisterClasses[R600_Reg64Vertical_with_sub0_in_R600_TReg32_XRegClassID],
9667 R600_Reg64Vertical_with_sub0_in_R600_TReg32_XSubClassMask,
9668 SuperRegIdxSeqs + 4,
9669 LaneBitmask(0x0000000000000003),
9670 0,
9671 false,
9672 0x00, /* TSFlags */
9673 true, /* HasDisjunctSubRegs */
9674 false, /* CoveredBySubRegs */
9675 R600_Reg64Vertical_with_sub0_in_R600_TReg32_XSuperclasses, 1,
9676 nullptr
9677 };
9678
9679 extern const TargetRegisterClass R600_Reg64Vertical_with_sub0_in_R600_TReg32_YRegClass = {
9680 &R600MCRegisterClasses[R600_Reg64Vertical_with_sub0_in_R600_TReg32_YRegClassID],
9681 R600_Reg64Vertical_with_sub0_in_R600_TReg32_YSubClassMask,
9682 SuperRegIdxSeqs + 4,
9683 LaneBitmask(0x0000000000000003),
9684 0,
9685 false,
9686 0x00, /* TSFlags */
9687 true, /* HasDisjunctSubRegs */
9688 false, /* CoveredBySubRegs */
9689 R600_Reg64Vertical_with_sub0_in_R600_TReg32_YSuperclasses, 1,
9690 nullptr
9691 };
9692
9693 extern const TargetRegisterClass R600_Reg64Vertical_with_sub0_in_R600_TReg32_ZRegClass = {
9694 &R600MCRegisterClasses[R600_Reg64Vertical_with_sub0_in_R600_TReg32_ZRegClassID],
9695 R600_Reg64Vertical_with_sub0_in_R600_TReg32_ZSubClassMask,
9696 SuperRegIdxSeqs + 4,
9697 LaneBitmask(0x0000000000000003),
9698 0,
9699 false,
9700 0x00, /* TSFlags */
9701 true, /* HasDisjunctSubRegs */
9702 false, /* CoveredBySubRegs */
9703 R600_Reg64Vertical_with_sub0_in_R600_TReg32_ZSuperclasses, 1,
9704 nullptr
9705 };
9706
9707 extern const TargetRegisterClass R600_Reg128RegClass = {
9708 &R600MCRegisterClasses[R600_Reg128RegClassID],
9709 R600_Reg128SubClassMask,
9710 SuperRegIdxSeqs + 4,
9711 LaneBitmask(0x000000000000000F),
9712 0,
9713 false,
9714 0x00, /* TSFlags */
9715 true, /* HasDisjunctSubRegs */
9716 false, /* CoveredBySubRegs */
9717 nullptr, 0,
9718 nullptr
9719 };
9720
9721 extern const TargetRegisterClass R600_Reg128VerticalRegClass = {
9722 &R600MCRegisterClasses[R600_Reg128VerticalRegClassID],
9723 R600_Reg128VerticalSubClassMask,
9724 SuperRegIdxSeqs + 4,
9725 LaneBitmask(0x000000000000000F),
9726 0,
9727 false,
9728 0x00, /* TSFlags */
9729 true, /* HasDisjunctSubRegs */
9730 false, /* CoveredBySubRegs */
9731 nullptr, 0,
9732 nullptr
9733 };
9734
9735 extern const TargetRegisterClass R600_Reg128Vertical_with_sub0_in_R600_TReg32_WRegClass = {
9736 &R600MCRegisterClasses[R600_Reg128Vertical_with_sub0_in_R600_TReg32_WRegClassID],
9737 R600_Reg128Vertical_with_sub0_in_R600_TReg32_WSubClassMask,
9738 SuperRegIdxSeqs + 4,
9739 LaneBitmask(0x000000000000000F),
9740 0,
9741 false,
9742 0x00, /* TSFlags */
9743 true, /* HasDisjunctSubRegs */
9744 false, /* CoveredBySubRegs */
9745 R600_Reg128Vertical_with_sub0_in_R600_TReg32_WSuperclasses, 1,
9746 nullptr
9747 };
9748
9749 extern const TargetRegisterClass R600_Reg128Vertical_with_sub0_in_R600_TReg32_XRegClass = {
9750 &R600MCRegisterClasses[R600_Reg128Vertical_with_sub0_in_R600_TReg32_XRegClassID],
9751 R600_Reg128Vertical_with_sub0_in_R600_TReg32_XSubClassMask,
9752 SuperRegIdxSeqs + 4,
9753 LaneBitmask(0x000000000000000F),
9754 0,
9755 false,
9756 0x00, /* TSFlags */
9757 true, /* HasDisjunctSubRegs */
9758 false, /* CoveredBySubRegs */
9759 R600_Reg128Vertical_with_sub0_in_R600_TReg32_XSuperclasses, 1,
9760 nullptr
9761 };
9762
9763 extern const TargetRegisterClass R600_Reg128Vertical_with_sub0_in_R600_TReg32_YRegClass = {
9764 &R600MCRegisterClasses[R600_Reg128Vertical_with_sub0_in_R600_TReg32_YRegClassID],
9765 R600_Reg128Vertical_with_sub0_in_R600_TReg32_YSubClassMask,
9766 SuperRegIdxSeqs + 4,
9767 LaneBitmask(0x000000000000000F),
9768 0,
9769 false,
9770 0x00, /* TSFlags */
9771 true, /* HasDisjunctSubRegs */
9772 false, /* CoveredBySubRegs */
9773 R600_Reg128Vertical_with_sub0_in_R600_TReg32_YSuperclasses, 1,
9774 nullptr
9775 };
9776
9777 extern const TargetRegisterClass R600_Reg128Vertical_with_sub0_in_R600_TReg32_ZRegClass = {
9778 &R600MCRegisterClasses[R600_Reg128Vertical_with_sub0_in_R600_TReg32_ZRegClassID],
9779 R600_Reg128Vertical_with_sub0_in_R600_TReg32_ZSubClassMask,
9780 SuperRegIdxSeqs + 4,
9781 LaneBitmask(0x000000000000000F),
9782 0,
9783 false,
9784 0x00, /* TSFlags */
9785 true, /* HasDisjunctSubRegs */
9786 false, /* CoveredBySubRegs */
9787 R600_Reg128Vertical_with_sub0_in_R600_TReg32_ZSuperclasses, 1,
9788 nullptr
9789 };
9790
9791} // end namespace R600
9792
9793namespace {
9794 const TargetRegisterClass *const RegisterClasses[] = {
9795 &R600::R600_Reg32RegClass,
9796 &R600::R600_TReg32RegClass,
9797 &R600::R600_TReg32_XRegClass,
9798 &R600::R600_AddrRegClass,
9799 &R600::R600_KC0RegClass,
9800 &R600::R600_KC1RegClass,
9801 &R600::R600_TReg32_WRegClass,
9802 &R600::R600_TReg32_YRegClass,
9803 &R600::R600_TReg32_ZRegClass,
9804 &R600::R600_ArrayBaseRegClass,
9805 &R600::R600_KC0_WRegClass,
9806 &R600::R600_KC0_XRegClass,
9807 &R600::R600_KC0_YRegClass,
9808 &R600::R600_KC0_ZRegClass,
9809 &R600::R600_KC1_WRegClass,
9810 &R600::R600_KC1_XRegClass,
9811 &R600::R600_KC1_YRegClass,
9812 &R600::R600_KC1_ZRegClass,
9813 &R600::R600_LDS_SRC_REGRegClass,
9814 &R600::R600_PredicateRegClass,
9815 &R600::R600_Addr_WRegClass,
9816 &R600::R600_Addr_YRegClass,
9817 &R600::R600_Addr_ZRegClass,
9818 &R600::R600_LDS_SRC_REG_and_R600_Reg32RegClass,
9819 &R600::R600_Predicate_BitRegClass,
9820 &R600::R600_Reg64RegClass,
9821 &R600::R600_Reg64VerticalRegClass,
9822 &R600::R600_Reg64Vertical_with_sub0_in_R600_TReg32_WRegClass,
9823 &R600::R600_Reg64Vertical_with_sub0_in_R600_TReg32_XRegClass,
9824 &R600::R600_Reg64Vertical_with_sub0_in_R600_TReg32_YRegClass,
9825 &R600::R600_Reg64Vertical_with_sub0_in_R600_TReg32_ZRegClass,
9826 &R600::R600_Reg128RegClass,
9827 &R600::R600_Reg128VerticalRegClass,
9828 &R600::R600_Reg128Vertical_with_sub0_in_R600_TReg32_WRegClass,
9829 &R600::R600_Reg128Vertical_with_sub0_in_R600_TReg32_XRegClass,
9830 &R600::R600_Reg128Vertical_with_sub0_in_R600_TReg32_YRegClass,
9831 &R600::R600_Reg128Vertical_with_sub0_in_R600_TReg32_ZRegClass,
9832 };
9833} // end anonymous namespace
9834
9835static const uint8_t CostPerUseTable[] = {
98360, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
9837
9838
9839static const bool InAllocatableClassTable[] = {
9840false, true, false, true, false, false, true, true, true, true, false, false, true, true, true, true, false, true, false, false, true, true, true, true, false, false, true, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
9841
9842
9843static const TargetRegisterInfoDesc R600RegInfoDesc = { // Extra Descriptors
9844CostPerUseTable, 1, InAllocatableClassTable};
9845
9846unsigned R600GenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
9847 static const uint8_t Rows[1][16] = {
9848 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
9849 };
9850
9851 --IdxA; assert(IdxA < 16); (void) IdxA;
9852 --IdxB; assert(IdxB < 16);
9853 return Rows[0][IdxB];
9854}
9855
9856unsigned R600GenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
9857 static const uint8_t Table[16][16] = {
9858 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
9859 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
9860 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
9861 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
9862 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
9863 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
9864 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
9865 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
9866 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
9867 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
9868 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
9869 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
9870 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
9871 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
9872 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
9873 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
9874 };
9875
9876 --IdxA; assert(IdxA < 16);
9877 --IdxB; assert(IdxB < 16);
9878 return Table[IdxA][IdxB];
9879 }
9880
9881 struct MaskRolOp {
9882 LaneBitmask Mask;
9883 uint8_t RotateLeft;
9884 };
9885 static const MaskRolOp LaneMaskComposeSequences[] = {
9886 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 0 }, { LaneBitmask::getNone(), 0 }, // Sequence 0
9887 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 1 }, { LaneBitmask::getNone(), 0 }, // Sequence 2
9888 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 2 }, { LaneBitmask::getNone(), 0 }, // Sequence 4
9889 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 3 }, { LaneBitmask::getNone(), 0 }, // Sequence 6
9890 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 4 }, { LaneBitmask::getNone(), 0 }, // Sequence 8
9891 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 5 }, { LaneBitmask::getNone(), 0 }, // Sequence 10
9892 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 6 }, { LaneBitmask::getNone(), 0 }, // Sequence 12
9893 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 7 }, { LaneBitmask::getNone(), 0 }, // Sequence 14
9894 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 8 }, { LaneBitmask::getNone(), 0 }, // Sequence 16
9895 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 9 }, { LaneBitmask::getNone(), 0 }, // Sequence 18
9896 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 10 }, { LaneBitmask::getNone(), 0 }, // Sequence 20
9897 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 11 }, { LaneBitmask::getNone(), 0 }, // Sequence 22
9898 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 12 }, { LaneBitmask::getNone(), 0 }, // Sequence 24
9899 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 13 }, { LaneBitmask::getNone(), 0 }, // Sequence 26
9900 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 14 }, { LaneBitmask::getNone(), 0 }, // Sequence 28
9901 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 15 }, { LaneBitmask::getNone(), 0 } // Sequence 30
9902 };
9903 static const uint8_t CompositeSequences[] = {
9904 0, // to sub0
9905 2, // to sub1
9906 4, // to sub2
9907 6, // to sub3
9908 8, // to sub4
9909 10, // to sub5
9910 12, // to sub6
9911 14, // to sub7
9912 16, // to sub8
9913 18, // to sub9
9914 20, // to sub10
9915 22, // to sub11
9916 24, // to sub12
9917 26, // to sub13
9918 28, // to sub14
9919 30 // to sub15
9920 };
9921
9922LaneBitmask R600GenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
9923 --IdxA; assert(IdxA < 16 && "Subregister index out of bounds");
9924 LaneBitmask Result;
9925 for (const MaskRolOp *Ops =
9926 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
9927 Ops->Mask.any(); ++Ops) {
9928 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
9929 if (unsigned S = Ops->RotateLeft)
9930 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
9931 else
9932 Result |= LaneBitmask(M);
9933 }
9934 return Result;
9935}
9936
9937LaneBitmask R600GenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
9938 LaneMask &= getSubRegIndexLaneMask(IdxA);
9939 --IdxA; assert(IdxA < 16 && "Subregister index out of bounds");
9940 LaneBitmask Result;
9941 for (const MaskRolOp *Ops =
9942 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
9943 Ops->Mask.any(); ++Ops) {
9944 LaneBitmask::Type M = LaneMask.getAsInteger();
9945 if (unsigned S = Ops->RotateLeft)
9946 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
9947 else
9948 Result |= LaneBitmask(M);
9949 }
9950 return Result;
9951}
9952
9953const TargetRegisterClass *R600GenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
9954 static const uint8_t Table[37][16] = {
9955 { // R600_Reg32
9956 0, // sub0
9957 0, // sub1
9958 0, // sub2
9959 0, // sub3
9960 0, // sub4
9961 0, // sub5
9962 0, // sub6
9963 0, // sub7
9964 0, // sub8
9965 0, // sub9
9966 0, // sub10
9967 0, // sub11
9968 0, // sub12
9969 0, // sub13
9970 0, // sub14
9971 0, // sub15
9972 },
9973 { // R600_TReg32
9974 0, // sub0
9975 0, // sub1
9976 0, // sub2
9977 0, // sub3
9978 0, // sub4
9979 0, // sub5
9980 0, // sub6
9981 0, // sub7
9982 0, // sub8
9983 0, // sub9
9984 0, // sub10
9985 0, // sub11
9986 0, // sub12
9987 0, // sub13
9988 0, // sub14
9989 0, // sub15
9990 },
9991 { // R600_TReg32_X
9992 0, // sub0
9993 0, // sub1
9994 0, // sub2
9995 0, // sub3
9996 0, // sub4
9997 0, // sub5
9998 0, // sub6
9999 0, // sub7
10000 0, // sub8
10001 0, // sub9
10002 0, // sub10
10003 0, // sub11
10004 0, // sub12
10005 0, // sub13
10006 0, // sub14
10007 0, // sub15
10008 },
10009 { // R600_Addr
10010 0, // sub0
10011 0, // sub1
10012 0, // sub2
10013 0, // sub3
10014 0, // sub4
10015 0, // sub5
10016 0, // sub6
10017 0, // sub7
10018 0, // sub8
10019 0, // sub9
10020 0, // sub10
10021 0, // sub11
10022 0, // sub12
10023 0, // sub13
10024 0, // sub14
10025 0, // sub15
10026 },
10027 { // R600_KC0
10028 0, // sub0
10029 0, // sub1
10030 0, // sub2
10031 0, // sub3
10032 0, // sub4
10033 0, // sub5
10034 0, // sub6
10035 0, // sub7
10036 0, // sub8
10037 0, // sub9
10038 0, // sub10
10039 0, // sub11
10040 0, // sub12
10041 0, // sub13
10042 0, // sub14
10043 0, // sub15
10044 },
10045 { // R600_KC1
10046 0, // sub0
10047 0, // sub1
10048 0, // sub2
10049 0, // sub3
10050 0, // sub4
10051 0, // sub5
10052 0, // sub6
10053 0, // sub7
10054 0, // sub8
10055 0, // sub9
10056 0, // sub10
10057 0, // sub11
10058 0, // sub12
10059 0, // sub13
10060 0, // sub14
10061 0, // sub15
10062 },
10063 { // R600_TReg32_W
10064 0, // sub0
10065 0, // sub1
10066 0, // sub2
10067 0, // sub3
10068 0, // sub4
10069 0, // sub5
10070 0, // sub6
10071 0, // sub7
10072 0, // sub8
10073 0, // sub9
10074 0, // sub10
10075 0, // sub11
10076 0, // sub12
10077 0, // sub13
10078 0, // sub14
10079 0, // sub15
10080 },
10081 { // R600_TReg32_Y
10082 0, // sub0
10083 0, // sub1
10084 0, // sub2
10085 0, // sub3
10086 0, // sub4
10087 0, // sub5
10088 0, // sub6
10089 0, // sub7
10090 0, // sub8
10091 0, // sub9
10092 0, // sub10
10093 0, // sub11
10094 0, // sub12
10095 0, // sub13
10096 0, // sub14
10097 0, // sub15
10098 },
10099 { // R600_TReg32_Z
10100 0, // sub0
10101 0, // sub1
10102 0, // sub2
10103 0, // sub3
10104 0, // sub4
10105 0, // sub5
10106 0, // sub6
10107 0, // sub7
10108 0, // sub8
10109 0, // sub9
10110 0, // sub10
10111 0, // sub11
10112 0, // sub12
10113 0, // sub13
10114 0, // sub14
10115 0, // sub15
10116 },
10117 { // R600_ArrayBase
10118 0, // sub0
10119 0, // sub1
10120 0, // sub2
10121 0, // sub3
10122 0, // sub4
10123 0, // sub5
10124 0, // sub6
10125 0, // sub7
10126 0, // sub8
10127 0, // sub9
10128 0, // sub10
10129 0, // sub11
10130 0, // sub12
10131 0, // sub13
10132 0, // sub14
10133 0, // sub15
10134 },
10135 { // R600_KC0_W
10136 0, // sub0
10137 0, // sub1
10138 0, // sub2
10139 0, // sub3
10140 0, // sub4
10141 0, // sub5
10142 0, // sub6
10143 0, // sub7
10144 0, // sub8
10145 0, // sub9
10146 0, // sub10
10147 0, // sub11
10148 0, // sub12
10149 0, // sub13
10150 0, // sub14
10151 0, // sub15
10152 },
10153 { // R600_KC0_X
10154 0, // sub0
10155 0, // sub1
10156 0, // sub2
10157 0, // sub3
10158 0, // sub4
10159 0, // sub5
10160 0, // sub6
10161 0, // sub7
10162 0, // sub8
10163 0, // sub9
10164 0, // sub10
10165 0, // sub11
10166 0, // sub12
10167 0, // sub13
10168 0, // sub14
10169 0, // sub15
10170 },
10171 { // R600_KC0_Y
10172 0, // sub0
10173 0, // sub1
10174 0, // sub2
10175 0, // sub3
10176 0, // sub4
10177 0, // sub5
10178 0, // sub6
10179 0, // sub7
10180 0, // sub8
10181 0, // sub9
10182 0, // sub10
10183 0, // sub11
10184 0, // sub12
10185 0, // sub13
10186 0, // sub14
10187 0, // sub15
10188 },
10189 { // R600_KC0_Z
10190 0, // sub0
10191 0, // sub1
10192 0, // sub2
10193 0, // sub3
10194 0, // sub4
10195 0, // sub5
10196 0, // sub6
10197 0, // sub7
10198 0, // sub8
10199 0, // sub9
10200 0, // sub10
10201 0, // sub11
10202 0, // sub12
10203 0, // sub13
10204 0, // sub14
10205 0, // sub15
10206 },
10207 { // R600_KC1_W
10208 0, // sub0
10209 0, // sub1
10210 0, // sub2
10211 0, // sub3
10212 0, // sub4
10213 0, // sub5
10214 0, // sub6
10215 0, // sub7
10216 0, // sub8
10217 0, // sub9
10218 0, // sub10
10219 0, // sub11
10220 0, // sub12
10221 0, // sub13
10222 0, // sub14
10223 0, // sub15
10224 },
10225 { // R600_KC1_X
10226 0, // sub0
10227 0, // sub1
10228 0, // sub2
10229 0, // sub3
10230 0, // sub4
10231 0, // sub5
10232 0, // sub6
10233 0, // sub7
10234 0, // sub8
10235 0, // sub9
10236 0, // sub10
10237 0, // sub11
10238 0, // sub12
10239 0, // sub13
10240 0, // sub14
10241 0, // sub15
10242 },
10243 { // R600_KC1_Y
10244 0, // sub0
10245 0, // sub1
10246 0, // sub2
10247 0, // sub3
10248 0, // sub4
10249 0, // sub5
10250 0, // sub6
10251 0, // sub7
10252 0, // sub8
10253 0, // sub9
10254 0, // sub10
10255 0, // sub11
10256 0, // sub12
10257 0, // sub13
10258 0, // sub14
10259 0, // sub15
10260 },
10261 { // R600_KC1_Z
10262 0, // sub0
10263 0, // sub1
10264 0, // sub2
10265 0, // sub3
10266 0, // sub4
10267 0, // sub5
10268 0, // sub6
10269 0, // sub7
10270 0, // sub8
10271 0, // sub9
10272 0, // sub10
10273 0, // sub11
10274 0, // sub12
10275 0, // sub13
10276 0, // sub14
10277 0, // sub15
10278 },
10279 { // R600_LDS_SRC_REG
10280 0, // sub0
10281 0, // sub1
10282 0, // sub2
10283 0, // sub3
10284 0, // sub4
10285 0, // sub5
10286 0, // sub6
10287 0, // sub7
10288 0, // sub8
10289 0, // sub9
10290 0, // sub10
10291 0, // sub11
10292 0, // sub12
10293 0, // sub13
10294 0, // sub14
10295 0, // sub15
10296 },
10297 { // R600_Predicate
10298 0, // sub0
10299 0, // sub1
10300 0, // sub2
10301 0, // sub3
10302 0, // sub4
10303 0, // sub5
10304 0, // sub6
10305 0, // sub7
10306 0, // sub8
10307 0, // sub9
10308 0, // sub10
10309 0, // sub11
10310 0, // sub12
10311 0, // sub13
10312 0, // sub14
10313 0, // sub15
10314 },
10315 { // R600_Addr_W
10316 0, // sub0
10317 0, // sub1
10318 0, // sub2
10319 0, // sub3
10320 0, // sub4
10321 0, // sub5
10322 0, // sub6
10323 0, // sub7
10324 0, // sub8
10325 0, // sub9
10326 0, // sub10
10327 0, // sub11
10328 0, // sub12
10329 0, // sub13
10330 0, // sub14
10331 0, // sub15
10332 },
10333 { // R600_Addr_Y
10334 0, // sub0
10335 0, // sub1
10336 0, // sub2
10337 0, // sub3
10338 0, // sub4
10339 0, // sub5
10340 0, // sub6
10341 0, // sub7
10342 0, // sub8
10343 0, // sub9
10344 0, // sub10
10345 0, // sub11
10346 0, // sub12
10347 0, // sub13
10348 0, // sub14
10349 0, // sub15
10350 },
10351 { // R600_Addr_Z
10352 0, // sub0
10353 0, // sub1
10354 0, // sub2
10355 0, // sub3
10356 0, // sub4
10357 0, // sub5
10358 0, // sub6
10359 0, // sub7
10360 0, // sub8
10361 0, // sub9
10362 0, // sub10
10363 0, // sub11
10364 0, // sub12
10365 0, // sub13
10366 0, // sub14
10367 0, // sub15
10368 },
10369 { // R600_LDS_SRC_REG_and_R600_Reg32
10370 0, // sub0
10371 0, // sub1
10372 0, // sub2
10373 0, // sub3
10374 0, // sub4
10375 0, // sub5
10376 0, // sub6
10377 0, // sub7
10378 0, // sub8
10379 0, // sub9
10380 0, // sub10
10381 0, // sub11
10382 0, // sub12
10383 0, // sub13
10384 0, // sub14
10385 0, // sub15
10386 },
10387 { // R600_Predicate_Bit
10388 0, // sub0
10389 0, // sub1
10390 0, // sub2
10391 0, // sub3
10392 0, // sub4
10393 0, // sub5
10394 0, // sub6
10395 0, // sub7
10396 0, // sub8
10397 0, // sub9
10398 0, // sub10
10399 0, // sub11
10400 0, // sub12
10401 0, // sub13
10402 0, // sub14
10403 0, // sub15
10404 },
10405 { // R600_Reg64
10406 26, // sub0 -> R600_Reg64
10407 26, // sub1 -> R600_Reg64
10408 0, // sub2
10409 0, // sub3
10410 0, // sub4
10411 0, // sub5
10412 0, // sub6
10413 0, // sub7
10414 0, // sub8
10415 0, // sub9
10416 0, // sub10
10417 0, // sub11
10418 0, // sub12
10419 0, // sub13
10420 0, // sub14
10421 0, // sub15
10422 },
10423 { // R600_Reg64Vertical
10424 27, // sub0 -> R600_Reg64Vertical
10425 27, // sub1 -> R600_Reg64Vertical
10426 0, // sub2
10427 0, // sub3
10428 0, // sub4
10429 0, // sub5
10430 0, // sub6
10431 0, // sub7
10432 0, // sub8
10433 0, // sub9
10434 0, // sub10
10435 0, // sub11
10436 0, // sub12
10437 0, // sub13
10438 0, // sub14
10439 0, // sub15
10440 },
10441 { // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W
10442 28, // sub0 -> R600_Reg64Vertical_with_sub0_in_R600_TReg32_W
10443 28, // sub1 -> R600_Reg64Vertical_with_sub0_in_R600_TReg32_W
10444 0, // sub2
10445 0, // sub3
10446 0, // sub4
10447 0, // sub5
10448 0, // sub6
10449 0, // sub7
10450 0, // sub8
10451 0, // sub9
10452 0, // sub10
10453 0, // sub11
10454 0, // sub12
10455 0, // sub13
10456 0, // sub14
10457 0, // sub15
10458 },
10459 { // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X
10460 29, // sub0 -> R600_Reg64Vertical_with_sub0_in_R600_TReg32_X
10461 29, // sub1 -> R600_Reg64Vertical_with_sub0_in_R600_TReg32_X
10462 0, // sub2
10463 0, // sub3
10464 0, // sub4
10465 0, // sub5
10466 0, // sub6
10467 0, // sub7
10468 0, // sub8
10469 0, // sub9
10470 0, // sub10
10471 0, // sub11
10472 0, // sub12
10473 0, // sub13
10474 0, // sub14
10475 0, // sub15
10476 },
10477 { // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y
10478 30, // sub0 -> R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y
10479 30, // sub1 -> R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y
10480 0, // sub2
10481 0, // sub3
10482 0, // sub4
10483 0, // sub5
10484 0, // sub6
10485 0, // sub7
10486 0, // sub8
10487 0, // sub9
10488 0, // sub10
10489 0, // sub11
10490 0, // sub12
10491 0, // sub13
10492 0, // sub14
10493 0, // sub15
10494 },
10495 { // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z
10496 31, // sub0 -> R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z
10497 31, // sub1 -> R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z
10498 0, // sub2
10499 0, // sub3
10500 0, // sub4
10501 0, // sub5
10502 0, // sub6
10503 0, // sub7
10504 0, // sub8
10505 0, // sub9
10506 0, // sub10
10507 0, // sub11
10508 0, // sub12
10509 0, // sub13
10510 0, // sub14
10511 0, // sub15
10512 },
10513 { // R600_Reg128
10514 32, // sub0 -> R600_Reg128
10515 32, // sub1 -> R600_Reg128
10516 32, // sub2 -> R600_Reg128
10517 32, // sub3 -> R600_Reg128
10518 0, // sub4
10519 0, // sub5
10520 0, // sub6
10521 0, // sub7
10522 0, // sub8
10523 0, // sub9
10524 0, // sub10
10525 0, // sub11
10526 0, // sub12
10527 0, // sub13
10528 0, // sub14
10529 0, // sub15
10530 },
10531 { // R600_Reg128Vertical
10532 33, // sub0 -> R600_Reg128Vertical
10533 33, // sub1 -> R600_Reg128Vertical
10534 33, // sub2 -> R600_Reg128Vertical
10535 33, // sub3 -> R600_Reg128Vertical
10536 0, // sub4
10537 0, // sub5
10538 0, // sub6
10539 0, // sub7
10540 0, // sub8
10541 0, // sub9
10542 0, // sub10
10543 0, // sub11
10544 0, // sub12
10545 0, // sub13
10546 0, // sub14
10547 0, // sub15
10548 },
10549 { // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W
10550 34, // sub0 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_W
10551 34, // sub1 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_W
10552 34, // sub2 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_W
10553 34, // sub3 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_W
10554 0, // sub4
10555 0, // sub5
10556 0, // sub6
10557 0, // sub7
10558 0, // sub8
10559 0, // sub9
10560 0, // sub10
10561 0, // sub11
10562 0, // sub12
10563 0, // sub13
10564 0, // sub14
10565 0, // sub15
10566 },
10567 { // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X
10568 35, // sub0 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_X
10569 35, // sub1 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_X
10570 35, // sub2 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_X
10571 35, // sub3 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_X
10572 0, // sub4
10573 0, // sub5
10574 0, // sub6
10575 0, // sub7
10576 0, // sub8
10577 0, // sub9
10578 0, // sub10
10579 0, // sub11
10580 0, // sub12
10581 0, // sub13
10582 0, // sub14
10583 0, // sub15
10584 },
10585 { // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y
10586 36, // sub0 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y
10587 36, // sub1 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y
10588 36, // sub2 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y
10589 36, // sub3 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y
10590 0, // sub4
10591 0, // sub5
10592 0, // sub6
10593 0, // sub7
10594 0, // sub8
10595 0, // sub9
10596 0, // sub10
10597 0, // sub11
10598 0, // sub12
10599 0, // sub13
10600 0, // sub14
10601 0, // sub15
10602 },
10603 { // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z
10604 37, // sub0 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z
10605 37, // sub1 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z
10606 37, // sub2 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z
10607 37, // sub3 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z
10608 0, // sub4
10609 0, // sub5
10610 0, // sub6
10611 0, // sub7
10612 0, // sub8
10613 0, // sub9
10614 0, // sub10
10615 0, // sub11
10616 0, // sub12
10617 0, // sub13
10618 0, // sub14
10619 0, // sub15
10620 },
10621 };
10622 assert(RC && "Missing regclass");
10623 if (!Idx) return RC;
10624 --Idx;
10625 assert(Idx < 16 && "Bad subreg");
10626 unsigned TV = Table[RC->getID()][Idx];
10627 return TV ? getRegClass(TV - 1) : nullptr;
10628}
10629
10630const TargetRegisterClass *R600GenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
10631 static const uint8_t Table[37][16] = {
10632 { // R600_Reg32
10633 0, // R600_Reg32:sub0
10634 0, // R600_Reg32:sub1
10635 0, // R600_Reg32:sub2
10636 0, // R600_Reg32:sub3
10637 0, // R600_Reg32:sub4
10638 0, // R600_Reg32:sub5
10639 0, // R600_Reg32:sub6
10640 0, // R600_Reg32:sub7
10641 0, // R600_Reg32:sub8
10642 0, // R600_Reg32:sub9
10643 0, // R600_Reg32:sub10
10644 0, // R600_Reg32:sub11
10645 0, // R600_Reg32:sub12
10646 0, // R600_Reg32:sub13
10647 0, // R600_Reg32:sub14
10648 0, // R600_Reg32:sub15
10649 },
10650 { // R600_TReg32
10651 0, // R600_TReg32:sub0
10652 0, // R600_TReg32:sub1
10653 0, // R600_TReg32:sub2
10654 0, // R600_TReg32:sub3
10655 0, // R600_TReg32:sub4
10656 0, // R600_TReg32:sub5
10657 0, // R600_TReg32:sub6
10658 0, // R600_TReg32:sub7
10659 0, // R600_TReg32:sub8
10660 0, // R600_TReg32:sub9
10661 0, // R600_TReg32:sub10
10662 0, // R600_TReg32:sub11
10663 0, // R600_TReg32:sub12
10664 0, // R600_TReg32:sub13
10665 0, // R600_TReg32:sub14
10666 0, // R600_TReg32:sub15
10667 },
10668 { // R600_TReg32_X
10669 0, // R600_TReg32_X:sub0
10670 0, // R600_TReg32_X:sub1
10671 0, // R600_TReg32_X:sub2
10672 0, // R600_TReg32_X:sub3
10673 0, // R600_TReg32_X:sub4
10674 0, // R600_TReg32_X:sub5
10675 0, // R600_TReg32_X:sub6
10676 0, // R600_TReg32_X:sub7
10677 0, // R600_TReg32_X:sub8
10678 0, // R600_TReg32_X:sub9
10679 0, // R600_TReg32_X:sub10
10680 0, // R600_TReg32_X:sub11
10681 0, // R600_TReg32_X:sub12
10682 0, // R600_TReg32_X:sub13
10683 0, // R600_TReg32_X:sub14
10684 0, // R600_TReg32_X:sub15
10685 },
10686 { // R600_Addr
10687 0, // R600_Addr:sub0
10688 0, // R600_Addr:sub1
10689 0, // R600_Addr:sub2
10690 0, // R600_Addr:sub3
10691 0, // R600_Addr:sub4
10692 0, // R600_Addr:sub5
10693 0, // R600_Addr:sub6
10694 0, // R600_Addr:sub7
10695 0, // R600_Addr:sub8
10696 0, // R600_Addr:sub9
10697 0, // R600_Addr:sub10
10698 0, // R600_Addr:sub11
10699 0, // R600_Addr:sub12
10700 0, // R600_Addr:sub13
10701 0, // R600_Addr:sub14
10702 0, // R600_Addr:sub15
10703 },
10704 { // R600_KC0
10705 0, // R600_KC0:sub0
10706 0, // R600_KC0:sub1
10707 0, // R600_KC0:sub2
10708 0, // R600_KC0:sub3
10709 0, // R600_KC0:sub4
10710 0, // R600_KC0:sub5
10711 0, // R600_KC0:sub6
10712 0, // R600_KC0:sub7
10713 0, // R600_KC0:sub8
10714 0, // R600_KC0:sub9
10715 0, // R600_KC0:sub10
10716 0, // R600_KC0:sub11
10717 0, // R600_KC0:sub12
10718 0, // R600_KC0:sub13
10719 0, // R600_KC0:sub14
10720 0, // R600_KC0:sub15
10721 },
10722 { // R600_KC1
10723 0, // R600_KC1:sub0
10724 0, // R600_KC1:sub1
10725 0, // R600_KC1:sub2
10726 0, // R600_KC1:sub3
10727 0, // R600_KC1:sub4
10728 0, // R600_KC1:sub5
10729 0, // R600_KC1:sub6
10730 0, // R600_KC1:sub7
10731 0, // R600_KC1:sub8
10732 0, // R600_KC1:sub9
10733 0, // R600_KC1:sub10
10734 0, // R600_KC1:sub11
10735 0, // R600_KC1:sub12
10736 0, // R600_KC1:sub13
10737 0, // R600_KC1:sub14
10738 0, // R600_KC1:sub15
10739 },
10740 { // R600_TReg32_W
10741 0, // R600_TReg32_W:sub0
10742 0, // R600_TReg32_W:sub1
10743 0, // R600_TReg32_W:sub2
10744 0, // R600_TReg32_W:sub3
10745 0, // R600_TReg32_W:sub4
10746 0, // R600_TReg32_W:sub5
10747 0, // R600_TReg32_W:sub6
10748 0, // R600_TReg32_W:sub7
10749 0, // R600_TReg32_W:sub8
10750 0, // R600_TReg32_W:sub9
10751 0, // R600_TReg32_W:sub10
10752 0, // R600_TReg32_W:sub11
10753 0, // R600_TReg32_W:sub12
10754 0, // R600_TReg32_W:sub13
10755 0, // R600_TReg32_W:sub14
10756 0, // R600_TReg32_W:sub15
10757 },
10758 { // R600_TReg32_Y
10759 0, // R600_TReg32_Y:sub0
10760 0, // R600_TReg32_Y:sub1
10761 0, // R600_TReg32_Y:sub2
10762 0, // R600_TReg32_Y:sub3
10763 0, // R600_TReg32_Y:sub4
10764 0, // R600_TReg32_Y:sub5
10765 0, // R600_TReg32_Y:sub6
10766 0, // R600_TReg32_Y:sub7
10767 0, // R600_TReg32_Y:sub8
10768 0, // R600_TReg32_Y:sub9
10769 0, // R600_TReg32_Y:sub10
10770 0, // R600_TReg32_Y:sub11
10771 0, // R600_TReg32_Y:sub12
10772 0, // R600_TReg32_Y:sub13
10773 0, // R600_TReg32_Y:sub14
10774 0, // R600_TReg32_Y:sub15
10775 },
10776 { // R600_TReg32_Z
10777 0, // R600_TReg32_Z:sub0
10778 0, // R600_TReg32_Z:sub1
10779 0, // R600_TReg32_Z:sub2
10780 0, // R600_TReg32_Z:sub3
10781 0, // R600_TReg32_Z:sub4
10782 0, // R600_TReg32_Z:sub5
10783 0, // R600_TReg32_Z:sub6
10784 0, // R600_TReg32_Z:sub7
10785 0, // R600_TReg32_Z:sub8
10786 0, // R600_TReg32_Z:sub9
10787 0, // R600_TReg32_Z:sub10
10788 0, // R600_TReg32_Z:sub11
10789 0, // R600_TReg32_Z:sub12
10790 0, // R600_TReg32_Z:sub13
10791 0, // R600_TReg32_Z:sub14
10792 0, // R600_TReg32_Z:sub15
10793 },
10794 { // R600_ArrayBase
10795 0, // R600_ArrayBase:sub0
10796 0, // R600_ArrayBase:sub1
10797 0, // R600_ArrayBase:sub2
10798 0, // R600_ArrayBase:sub3
10799 0, // R600_ArrayBase:sub4
10800 0, // R600_ArrayBase:sub5
10801 0, // R600_ArrayBase:sub6
10802 0, // R600_ArrayBase:sub7
10803 0, // R600_ArrayBase:sub8
10804 0, // R600_ArrayBase:sub9
10805 0, // R600_ArrayBase:sub10
10806 0, // R600_ArrayBase:sub11
10807 0, // R600_ArrayBase:sub12
10808 0, // R600_ArrayBase:sub13
10809 0, // R600_ArrayBase:sub14
10810 0, // R600_ArrayBase:sub15
10811 },
10812 { // R600_KC0_W
10813 0, // R600_KC0_W:sub0
10814 0, // R600_KC0_W:sub1
10815 0, // R600_KC0_W:sub2
10816 0, // R600_KC0_W:sub3
10817 0, // R600_KC0_W:sub4
10818 0, // R600_KC0_W:sub5
10819 0, // R600_KC0_W:sub6
10820 0, // R600_KC0_W:sub7
10821 0, // R600_KC0_W:sub8
10822 0, // R600_KC0_W:sub9
10823 0, // R600_KC0_W:sub10
10824 0, // R600_KC0_W:sub11
10825 0, // R600_KC0_W:sub12
10826 0, // R600_KC0_W:sub13
10827 0, // R600_KC0_W:sub14
10828 0, // R600_KC0_W:sub15
10829 },
10830 { // R600_KC0_X
10831 0, // R600_KC0_X:sub0
10832 0, // R600_KC0_X:sub1
10833 0, // R600_KC0_X:sub2
10834 0, // R600_KC0_X:sub3
10835 0, // R600_KC0_X:sub4
10836 0, // R600_KC0_X:sub5
10837 0, // R600_KC0_X:sub6
10838 0, // R600_KC0_X:sub7
10839 0, // R600_KC0_X:sub8
10840 0, // R600_KC0_X:sub9
10841 0, // R600_KC0_X:sub10
10842 0, // R600_KC0_X:sub11
10843 0, // R600_KC0_X:sub12
10844 0, // R600_KC0_X:sub13
10845 0, // R600_KC0_X:sub14
10846 0, // R600_KC0_X:sub15
10847 },
10848 { // R600_KC0_Y
10849 0, // R600_KC0_Y:sub0
10850 0, // R600_KC0_Y:sub1
10851 0, // R600_KC0_Y:sub2
10852 0, // R600_KC0_Y:sub3
10853 0, // R600_KC0_Y:sub4
10854 0, // R600_KC0_Y:sub5
10855 0, // R600_KC0_Y:sub6
10856 0, // R600_KC0_Y:sub7
10857 0, // R600_KC0_Y:sub8
10858 0, // R600_KC0_Y:sub9
10859 0, // R600_KC0_Y:sub10
10860 0, // R600_KC0_Y:sub11
10861 0, // R600_KC0_Y:sub12
10862 0, // R600_KC0_Y:sub13
10863 0, // R600_KC0_Y:sub14
10864 0, // R600_KC0_Y:sub15
10865 },
10866 { // R600_KC0_Z
10867 0, // R600_KC0_Z:sub0
10868 0, // R600_KC0_Z:sub1
10869 0, // R600_KC0_Z:sub2
10870 0, // R600_KC0_Z:sub3
10871 0, // R600_KC0_Z:sub4
10872 0, // R600_KC0_Z:sub5
10873 0, // R600_KC0_Z:sub6
10874 0, // R600_KC0_Z:sub7
10875 0, // R600_KC0_Z:sub8
10876 0, // R600_KC0_Z:sub9
10877 0, // R600_KC0_Z:sub10
10878 0, // R600_KC0_Z:sub11
10879 0, // R600_KC0_Z:sub12
10880 0, // R600_KC0_Z:sub13
10881 0, // R600_KC0_Z:sub14
10882 0, // R600_KC0_Z:sub15
10883 },
10884 { // R600_KC1_W
10885 0, // R600_KC1_W:sub0
10886 0, // R600_KC1_W:sub1
10887 0, // R600_KC1_W:sub2
10888 0, // R600_KC1_W:sub3
10889 0, // R600_KC1_W:sub4
10890 0, // R600_KC1_W:sub5
10891 0, // R600_KC1_W:sub6
10892 0, // R600_KC1_W:sub7
10893 0, // R600_KC1_W:sub8
10894 0, // R600_KC1_W:sub9
10895 0, // R600_KC1_W:sub10
10896 0, // R600_KC1_W:sub11
10897 0, // R600_KC1_W:sub12
10898 0, // R600_KC1_W:sub13
10899 0, // R600_KC1_W:sub14
10900 0, // R600_KC1_W:sub15
10901 },
10902 { // R600_KC1_X
10903 0, // R600_KC1_X:sub0
10904 0, // R600_KC1_X:sub1
10905 0, // R600_KC1_X:sub2
10906 0, // R600_KC1_X:sub3
10907 0, // R600_KC1_X:sub4
10908 0, // R600_KC1_X:sub5
10909 0, // R600_KC1_X:sub6
10910 0, // R600_KC1_X:sub7
10911 0, // R600_KC1_X:sub8
10912 0, // R600_KC1_X:sub9
10913 0, // R600_KC1_X:sub10
10914 0, // R600_KC1_X:sub11
10915 0, // R600_KC1_X:sub12
10916 0, // R600_KC1_X:sub13
10917 0, // R600_KC1_X:sub14
10918 0, // R600_KC1_X:sub15
10919 },
10920 { // R600_KC1_Y
10921 0, // R600_KC1_Y:sub0
10922 0, // R600_KC1_Y:sub1
10923 0, // R600_KC1_Y:sub2
10924 0, // R600_KC1_Y:sub3
10925 0, // R600_KC1_Y:sub4
10926 0, // R600_KC1_Y:sub5
10927 0, // R600_KC1_Y:sub6
10928 0, // R600_KC1_Y:sub7
10929 0, // R600_KC1_Y:sub8
10930 0, // R600_KC1_Y:sub9
10931 0, // R600_KC1_Y:sub10
10932 0, // R600_KC1_Y:sub11
10933 0, // R600_KC1_Y:sub12
10934 0, // R600_KC1_Y:sub13
10935 0, // R600_KC1_Y:sub14
10936 0, // R600_KC1_Y:sub15
10937 },
10938 { // R600_KC1_Z
10939 0, // R600_KC1_Z:sub0
10940 0, // R600_KC1_Z:sub1
10941 0, // R600_KC1_Z:sub2
10942 0, // R600_KC1_Z:sub3
10943 0, // R600_KC1_Z:sub4
10944 0, // R600_KC1_Z:sub5
10945 0, // R600_KC1_Z:sub6
10946 0, // R600_KC1_Z:sub7
10947 0, // R600_KC1_Z:sub8
10948 0, // R600_KC1_Z:sub9
10949 0, // R600_KC1_Z:sub10
10950 0, // R600_KC1_Z:sub11
10951 0, // R600_KC1_Z:sub12
10952 0, // R600_KC1_Z:sub13
10953 0, // R600_KC1_Z:sub14
10954 0, // R600_KC1_Z:sub15
10955 },
10956 { // R600_LDS_SRC_REG
10957 0, // R600_LDS_SRC_REG:sub0
10958 0, // R600_LDS_SRC_REG:sub1
10959 0, // R600_LDS_SRC_REG:sub2
10960 0, // R600_LDS_SRC_REG:sub3
10961 0, // R600_LDS_SRC_REG:sub4
10962 0, // R600_LDS_SRC_REG:sub5
10963 0, // R600_LDS_SRC_REG:sub6
10964 0, // R600_LDS_SRC_REG:sub7
10965 0, // R600_LDS_SRC_REG:sub8
10966 0, // R600_LDS_SRC_REG:sub9
10967 0, // R600_LDS_SRC_REG:sub10
10968 0, // R600_LDS_SRC_REG:sub11
10969 0, // R600_LDS_SRC_REG:sub12
10970 0, // R600_LDS_SRC_REG:sub13
10971 0, // R600_LDS_SRC_REG:sub14
10972 0, // R600_LDS_SRC_REG:sub15
10973 },
10974 { // R600_Predicate
10975 0, // R600_Predicate:sub0
10976 0, // R600_Predicate:sub1
10977 0, // R600_Predicate:sub2
10978 0, // R600_Predicate:sub3
10979 0, // R600_Predicate:sub4
10980 0, // R600_Predicate:sub5
10981 0, // R600_Predicate:sub6
10982 0, // R600_Predicate:sub7
10983 0, // R600_Predicate:sub8
10984 0, // R600_Predicate:sub9
10985 0, // R600_Predicate:sub10
10986 0, // R600_Predicate:sub11
10987 0, // R600_Predicate:sub12
10988 0, // R600_Predicate:sub13
10989 0, // R600_Predicate:sub14
10990 0, // R600_Predicate:sub15
10991 },
10992 { // R600_Addr_W
10993 0, // R600_Addr_W:sub0
10994 0, // R600_Addr_W:sub1
10995 0, // R600_Addr_W:sub2
10996 0, // R600_Addr_W:sub3
10997 0, // R600_Addr_W:sub4
10998 0, // R600_Addr_W:sub5
10999 0, // R600_Addr_W:sub6
11000 0, // R600_Addr_W:sub7
11001 0, // R600_Addr_W:sub8
11002 0, // R600_Addr_W:sub9
11003 0, // R600_Addr_W:sub10
11004 0, // R600_Addr_W:sub11
11005 0, // R600_Addr_W:sub12
11006 0, // R600_Addr_W:sub13
11007 0, // R600_Addr_W:sub14
11008 0, // R600_Addr_W:sub15
11009 },
11010 { // R600_Addr_Y
11011 0, // R600_Addr_Y:sub0
11012 0, // R600_Addr_Y:sub1
11013 0, // R600_Addr_Y:sub2
11014 0, // R600_Addr_Y:sub3
11015 0, // R600_Addr_Y:sub4
11016 0, // R600_Addr_Y:sub5
11017 0, // R600_Addr_Y:sub6
11018 0, // R600_Addr_Y:sub7
11019 0, // R600_Addr_Y:sub8
11020 0, // R600_Addr_Y:sub9
11021 0, // R600_Addr_Y:sub10
11022 0, // R600_Addr_Y:sub11
11023 0, // R600_Addr_Y:sub12
11024 0, // R600_Addr_Y:sub13
11025 0, // R600_Addr_Y:sub14
11026 0, // R600_Addr_Y:sub15
11027 },
11028 { // R600_Addr_Z
11029 0, // R600_Addr_Z:sub0
11030 0, // R600_Addr_Z:sub1
11031 0, // R600_Addr_Z:sub2
11032 0, // R600_Addr_Z:sub3
11033 0, // R600_Addr_Z:sub4
11034 0, // R600_Addr_Z:sub5
11035 0, // R600_Addr_Z:sub6
11036 0, // R600_Addr_Z:sub7
11037 0, // R600_Addr_Z:sub8
11038 0, // R600_Addr_Z:sub9
11039 0, // R600_Addr_Z:sub10
11040 0, // R600_Addr_Z:sub11
11041 0, // R600_Addr_Z:sub12
11042 0, // R600_Addr_Z:sub13
11043 0, // R600_Addr_Z:sub14
11044 0, // R600_Addr_Z:sub15
11045 },
11046 { // R600_LDS_SRC_REG_and_R600_Reg32
11047 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub0
11048 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub1
11049 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub2
11050 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub3
11051 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub4
11052 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub5
11053 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub6
11054 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub7
11055 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub8
11056 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub9
11057 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub10
11058 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub11
11059 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub12
11060 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub13
11061 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub14
11062 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub15
11063 },
11064 { // R600_Predicate_Bit
11065 0, // R600_Predicate_Bit:sub0
11066 0, // R600_Predicate_Bit:sub1
11067 0, // R600_Predicate_Bit:sub2
11068 0, // R600_Predicate_Bit:sub3
11069 0, // R600_Predicate_Bit:sub4
11070 0, // R600_Predicate_Bit:sub5
11071 0, // R600_Predicate_Bit:sub6
11072 0, // R600_Predicate_Bit:sub7
11073 0, // R600_Predicate_Bit:sub8
11074 0, // R600_Predicate_Bit:sub9
11075 0, // R600_Predicate_Bit:sub10
11076 0, // R600_Predicate_Bit:sub11
11077 0, // R600_Predicate_Bit:sub12
11078 0, // R600_Predicate_Bit:sub13
11079 0, // R600_Predicate_Bit:sub14
11080 0, // R600_Predicate_Bit:sub15
11081 },
11082 { // R600_Reg64
11083 3, // R600_Reg64:sub0 -> R600_TReg32_X
11084 8, // R600_Reg64:sub1 -> R600_TReg32_Y
11085 0, // R600_Reg64:sub2
11086 0, // R600_Reg64:sub3
11087 0, // R600_Reg64:sub4
11088 0, // R600_Reg64:sub5
11089 0, // R600_Reg64:sub6
11090 0, // R600_Reg64:sub7
11091 0, // R600_Reg64:sub8
11092 0, // R600_Reg64:sub9
11093 0, // R600_Reg64:sub10
11094 0, // R600_Reg64:sub11
11095 0, // R600_Reg64:sub12
11096 0, // R600_Reg64:sub13
11097 0, // R600_Reg64:sub14
11098 0, // R600_Reg64:sub15
11099 },
11100 { // R600_Reg64Vertical
11101 2, // R600_Reg64Vertical:sub0 -> R600_TReg32
11102 2, // R600_Reg64Vertical:sub1 -> R600_TReg32
11103 0, // R600_Reg64Vertical:sub2
11104 0, // R600_Reg64Vertical:sub3
11105 0, // R600_Reg64Vertical:sub4
11106 0, // R600_Reg64Vertical:sub5
11107 0, // R600_Reg64Vertical:sub6
11108 0, // R600_Reg64Vertical:sub7
11109 0, // R600_Reg64Vertical:sub8
11110 0, // R600_Reg64Vertical:sub9
11111 0, // R600_Reg64Vertical:sub10
11112 0, // R600_Reg64Vertical:sub11
11113 0, // R600_Reg64Vertical:sub12
11114 0, // R600_Reg64Vertical:sub13
11115 0, // R600_Reg64Vertical:sub14
11116 0, // R600_Reg64Vertical:sub15
11117 },
11118 { // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W
11119 7, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub0 -> R600_TReg32_W
11120 7, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub1 -> R600_TReg32_W
11121 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub2
11122 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub3
11123 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub4
11124 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub5
11125 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub6
11126 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub7
11127 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub8
11128 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub9
11129 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub10
11130 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub11
11131 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub12
11132 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub13
11133 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub14
11134 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub15
11135 },
11136 { // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X
11137 3, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub0 -> R600_TReg32_X
11138 3, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub1 -> R600_TReg32_X
11139 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub2
11140 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub3
11141 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub4
11142 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub5
11143 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub6
11144 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub7
11145 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub8
11146 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub9
11147 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub10
11148 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub11
11149 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub12
11150 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub13
11151 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub14
11152 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub15
11153 },
11154 { // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y
11155 8, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub0 -> R600_TReg32_Y
11156 8, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub1 -> R600_TReg32_Y
11157 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub2
11158 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub3
11159 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub4
11160 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub5
11161 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub6
11162 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub7
11163 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub8
11164 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub9
11165 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub10
11166 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub11
11167 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub12
11168 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub13
11169 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub14
11170 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub15
11171 },
11172 { // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z
11173 9, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub0 -> R600_TReg32_Z
11174 9, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub1 -> R600_TReg32_Z
11175 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub2
11176 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub3
11177 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub4
11178 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub5
11179 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub6
11180 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub7
11181 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub8
11182 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub9
11183 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub10
11184 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub11
11185 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub12
11186 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub13
11187 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub14
11188 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub15
11189 },
11190 { // R600_Reg128
11191 3, // R600_Reg128:sub0 -> R600_TReg32_X
11192 8, // R600_Reg128:sub1 -> R600_TReg32_Y
11193 9, // R600_Reg128:sub2 -> R600_TReg32_Z
11194 7, // R600_Reg128:sub3 -> R600_TReg32_W
11195 0, // R600_Reg128:sub4
11196 0, // R600_Reg128:sub5
11197 0, // R600_Reg128:sub6
11198 0, // R600_Reg128:sub7
11199 0, // R600_Reg128:sub8
11200 0, // R600_Reg128:sub9
11201 0, // R600_Reg128:sub10
11202 0, // R600_Reg128:sub11
11203 0, // R600_Reg128:sub12
11204 0, // R600_Reg128:sub13
11205 0, // R600_Reg128:sub14
11206 0, // R600_Reg128:sub15
11207 },
11208 { // R600_Reg128Vertical
11209 2, // R600_Reg128Vertical:sub0 -> R600_TReg32
11210 2, // R600_Reg128Vertical:sub1 -> R600_TReg32
11211 2, // R600_Reg128Vertical:sub2 -> R600_TReg32
11212 2, // R600_Reg128Vertical:sub3 -> R600_TReg32
11213 0, // R600_Reg128Vertical:sub4
11214 0, // R600_Reg128Vertical:sub5
11215 0, // R600_Reg128Vertical:sub6
11216 0, // R600_Reg128Vertical:sub7
11217 0, // R600_Reg128Vertical:sub8
11218 0, // R600_Reg128Vertical:sub9
11219 0, // R600_Reg128Vertical:sub10
11220 0, // R600_Reg128Vertical:sub11
11221 0, // R600_Reg128Vertical:sub12
11222 0, // R600_Reg128Vertical:sub13
11223 0, // R600_Reg128Vertical:sub14
11224 0, // R600_Reg128Vertical:sub15
11225 },
11226 { // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W
11227 7, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub0 -> R600_TReg32_W
11228 7, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub1 -> R600_TReg32_W
11229 7, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub2 -> R600_TReg32_W
11230 7, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub3 -> R600_TReg32_W
11231 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub4
11232 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub5
11233 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub6
11234 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub7
11235 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub8
11236 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub9
11237 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub10
11238 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub11
11239 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub12
11240 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub13
11241 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub14
11242 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub15
11243 },
11244 { // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X
11245 3, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub0 -> R600_TReg32_X
11246 3, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub1 -> R600_TReg32_X
11247 3, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub2 -> R600_TReg32_X
11248 3, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub3 -> R600_TReg32_X
11249 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub4
11250 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub5
11251 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub6
11252 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub7
11253 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub8
11254 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub9
11255 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub10
11256 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub11
11257 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub12
11258 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub13
11259 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub14
11260 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub15
11261 },
11262 { // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y
11263 8, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub0 -> R600_TReg32_Y
11264 8, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub1 -> R600_TReg32_Y
11265 8, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub2 -> R600_TReg32_Y
11266 8, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub3 -> R600_TReg32_Y
11267 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub4
11268 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub5
11269 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub6
11270 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub7
11271 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub8
11272 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub9
11273 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub10
11274 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub11
11275 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub12
11276 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub13
11277 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub14
11278 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub15
11279 },
11280 { // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z
11281 9, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub0 -> R600_TReg32_Z
11282 9, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub1 -> R600_TReg32_Z
11283 9, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub2 -> R600_TReg32_Z
11284 9, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub3 -> R600_TReg32_Z
11285 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub4
11286 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub5
11287 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub6
11288 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub7
11289 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub8
11290 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub9
11291 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub10
11292 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub11
11293 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub12
11294 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub13
11295 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub14
11296 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub15
11297 },
11298 };
11299 assert(RC && "Missing regclass");
11300 if (!Idx) return RC;
11301 --Idx;
11302 assert(Idx < 16 && "Bad subreg");
11303 unsigned TV = Table[RC->getID()][Idx];
11304 return TV ? getRegClass(TV - 1) : nullptr;
11305}
11306
11307/// Get the weight in units of pressure for this register class.
11308const RegClassWeight &R600GenRegisterInfo::
11309getRegClassWeight(const TargetRegisterClass *RC) const {
11310 static const RegClassWeight RCWeightTable[] = {
11311 {0, 942}, // R600_Reg32
11312 {0, 513}, // R600_TReg32
11313 {0, 129}, // R600_TReg32_X
11314 {0, 128}, // R600_Addr
11315 {0, 128}, // R600_KC0
11316 {0, 128}, // R600_KC1
11317 {0, 128}, // R600_TReg32_W
11318 {0, 128}, // R600_TReg32_Y
11319 {0, 128}, // R600_TReg32_Z
11320 {0, 33}, // R600_ArrayBase
11321 {0, 32}, // R600_KC0_W
11322 {0, 32}, // R600_KC0_X
11323 {0, 32}, // R600_KC0_Y
11324 {0, 32}, // R600_KC0_Z
11325 {0, 32}, // R600_KC1_W
11326 {0, 32}, // R600_KC1_X
11327 {0, 32}, // R600_KC1_Y
11328 {0, 32}, // R600_KC1_Z
11329 {0, 1}, // R600_LDS_SRC_REG
11330 {0, 3}, // R600_Predicate
11331 {0, 0}, // R600_Addr_W
11332 {0, 0}, // R600_Addr_Y
11333 {0, 0}, // R600_Addr_Z
11334 {1, 1}, // R600_LDS_SRC_REG_and_R600_Reg32
11335 {0, 1}, // R600_Predicate_Bit
11336 {0, 128}, // R600_Reg64
11337 {0, 16}, // R600_Reg64Vertical
11338 {2, 4}, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W
11339 {2, 4}, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X
11340 {2, 4}, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y
11341 {2, 4}, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z
11342 {0, 512}, // R600_Reg128
11343 {0, 16}, // R600_Reg128Vertical
11344 {4, 4}, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W
11345 {4, 4}, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X
11346 {4, 4}, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y
11347 {4, 4}, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z
11348 };
11349 return RCWeightTable[RC->getID()];
11350}
11351
11352/// Get the weight in units of pressure for this register unit.
11353unsigned R600GenRegisterInfo::
11354getRegUnitWeight(unsigned RegUnit) const {
11355 assert(RegUnit < 1342 && "invalid register unit");
11356 // All register units have unit weight.
11357 return 1;
11358}
11359
11360
11361// Get the number of dimensions of register pressure.
11362unsigned R600GenRegisterInfo::getNumRegPressureSets() const {
11363 return 23;
11364}
11365
11366// Get the name of this register unit pressure set.
11367const char *R600GenRegisterInfo::
11368getRegPressureSetName(unsigned Idx) const {
11369 static const char *PressureNameTable[] = {
11370 "R600_LDS_SRC_REG_and_R600_Reg32",
11371 "R600_Predicate_Bit",
11372 "R600_Predicate",
11373 "R600_Reg64Vertical_with_sub0_in_R600_TReg32_W",
11374 "R600_Reg64Vertical_with_sub0_in_R600_TReg32_X",
11375 "R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y",
11376 "R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z",
11377 "R600_Reg64Vertical",
11378 "R600_ArrayBase",
11379 "R600_TReg32_W",
11380 "R600_TReg32_Y",
11381 "R600_TReg32_Z",
11382 "R600_Reg64",
11383 "R600_TReg32_X",
11384 "R600_Reg64_with_R600_Reg64Vertical",
11385 "R600_TReg32_W_with_R600_Reg64Vertical",
11386 "R600_TReg32_Y_with_R600_Reg64Vertical",
11387 "R600_TReg32_Z_with_R600_Reg64Vertical",
11388 "R600_TReg32_X_with_R600_Reg64Vertical",
11389 "R600_TReg32_Y_with_R600_Reg64",
11390 "R600_TReg32_X_with_R600_Reg64",
11391 "R600_TReg32",
11392 "R600_Reg32",
11393 };
11394 return PressureNameTable[Idx];
11395}
11396
11397// Get the register unit pressure limit for this dimension.
11398// This limit must be adjusted dynamically for reserved registers.
11399unsigned R600GenRegisterInfo::
11400getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
11401 static const uint16_t PressureLimitTable[] = {
11402 1, // 0: R600_LDS_SRC_REG_and_R600_Reg32
11403 1, // 1: R600_Predicate_Bit
11404 3, // 2: R600_Predicate
11405 4, // 3: R600_Reg64Vertical_with_sub0_in_R600_TReg32_W
11406 4, // 4: R600_Reg64Vertical_with_sub0_in_R600_TReg32_X
11407 4, // 5: R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y
11408 4, // 6: R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z
11409 16, // 7: R600_Reg64Vertical
11410 33, // 8: R600_ArrayBase
11411 128, // 9: R600_TReg32_W
11412 128, // 10: R600_TReg32_Y
11413 128, // 11: R600_TReg32_Z
11414 128, // 12: R600_Reg64
11415 129, // 13: R600_TReg32_X
11416 136, // 14: R600_Reg64_with_R600_Reg64Vertical
11417 140, // 15: R600_TReg32_W_with_R600_Reg64Vertical
11418 140, // 16: R600_TReg32_Y_with_R600_Reg64Vertical
11419 140, // 17: R600_TReg32_Z_with_R600_Reg64Vertical
11420 141, // 18: R600_TReg32_X_with_R600_Reg64Vertical
11421 192, // 19: R600_TReg32_Y_with_R600_Reg64
11422 193, // 20: R600_TReg32_X_with_R600_Reg64
11423 513, // 21: R600_TReg32
11424 942, // 22: R600_Reg32
11425 };
11426 return PressureLimitTable[Idx];
11427}
11428
11429/// Table of pressure sets per register class or unit.
11430static const int RCSetsTable[] = {
11431 /* 0 */ 1, -1,
11432 /* 2 */ 2, -1,
11433 /* 4 */ 0, 22, -1,
11434 /* 7 */ 8, 22, -1,
11435 /* 10 */ 9, 15, 21, 22, -1,
11436 /* 15 */ 11, 17, 21, 22, -1,
11437 /* 20 */ 7, 14, 15, 16, 17, 18, 21, 22, -1,
11438 /* 29 */ 3, 7, 9, 14, 15, 16, 17, 18, 21, 22, -1,
11439 /* 40 */ 6, 7, 11, 14, 15, 16, 17, 18, 21, 22, -1,
11440 /* 51 */ 10, 16, 19, 21, 22, -1,
11441 /* 57 */ 13, 18, 20, 21, 22, -1,
11442 /* 63 */ 12, 14, 19, 20, 21, 22, -1,
11443 /* 70 */ 10, 12, 14, 16, 19, 20, 21, 22, -1,
11444 /* 79 */ 12, 13, 14, 18, 19, 20, 21, 22, -1,
11445 /* 88 */ 5, 7, 10, 12, 14, 15, 16, 17, 18, 19, 20, 21, 22, -1,
11446 /* 102 */ 4, 7, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, -1,
11447};
11448
11449/// Get the dimensions of register pressure impacted by this register class.
11450/// Returns a -1 terminated array of pressure set IDs
11451const int *R600GenRegisterInfo::
11452getRegClassPressureSets(const TargetRegisterClass *RC) const {
11453 static const uint8_t RCSetStartTable[] = {
11454 5,12,57,1,1,1,10,51,15,7,1,1,1,1,1,1,1,1,1,2,1,1,1,4,0,63,20,29,102,88,40,12,20,29,102,88,40,};
11455 return &RCSetsTable[RCSetStartTable[RC->getID()]];
11456}
11457
11458/// Get the dimensions of register pressure impacted by this register unit.
11459/// Returns a -1 terminated array of pressure set IDs
11460const int *R600GenRegisterInfo::
11461getRegUnitPressureSets(unsigned RegUnit) const {
11462 assert(RegUnit < 1342 && "invalid register unit");
11463 static const uint8_t RUSetStartTable[] = {
11464 5,1,5,1,1,5,57,5,5,1,1,5,5,5,5,1,4,1,1,0,2,2,2,1,1,5,1,1,5,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,29,29,29,29,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,102,102,102,102,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,88,88,88,88,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,40,40,40,40,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,};
11465 return &RCSetsTable[RUSetStartTable[RegUnit]];
11466}
11467
11468extern const MCRegisterDesc R600RegDesc[];
11469extern const int16_t R600RegDiffLists[];
11470extern const LaneBitmask R600LaneMaskLists[];
11471extern const char R600RegStrings[];
11472extern const char R600RegClassStrings[];
11473extern const MCPhysReg R600RegUnitRoots[][2];
11474extern const uint16_t R600SubRegIdxLists[];
11475extern const uint16_t R600RegEncodingTable[];
11476R600GenRegisterInfo::
11477R600GenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
11478 unsigned PC, unsigned HwMode)
11479 : TargetRegisterInfo(&R600RegInfoDesc, RegisterClasses, RegisterClasses+37,
11480 SubRegIndexNameTable, SubRegIdxRangeTable, SubRegIndexLaneMaskTable,
11481 LaneBitmask(0xFFFFFFFFFFFFFFF0), RegClassInfos, VTLists, HwMode) {
11482 InitMCRegisterInfo(R600RegDesc, 1675, RA, PC,
11483 R600MCRegisterClasses, 37,
11484 R600RegUnitRoots,
11485 1342,
11486 R600RegDiffLists,
11487 R600LaneMaskLists,
11488 R600RegStrings,
11489 R600RegClassStrings,
11490 R600SubRegIdxLists,
11491 17,
11492 R600RegEncodingTable);
11493
11494}
11495
11496
11497
11498ArrayRef<const uint32_t *> R600GenRegisterInfo::getRegMasks() const {
11499 return {};
11500}
11501
11502bool R600GenRegisterInfo::
11503isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
11504 return
11505 false;
11506}
11507
11508bool R600GenRegisterInfo::
11509isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
11510 return
11511 false;
11512}
11513
11514bool R600GenRegisterInfo::
11515isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
11516 return
11517 false;
11518}
11519
11520bool R600GenRegisterInfo::
11521isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
11522 return
11523 false;
11524}
11525
11526bool R600GenRegisterInfo::
11527isConstantPhysReg(MCRegister PhysReg) const {
11528 return
11529 false;
11530}
11531
11532ArrayRef<const char *> R600GenRegisterInfo::getRegMaskNames() const {
11533 return {};
11534}
11535
11536const R600FrameLowering *
11537R600GenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
11538 return static_cast<const R600FrameLowering *>(
11539 MF.getSubtarget().getFrameLowering());
11540}
11541
11542} // end namespace llvm
11543
11544#endif // GET_REGINFO_TARGET_DESC
11545
11546