1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Subtarget Enumeration Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_SUBTARGETINFO_ENUM
11#undef GET_SUBTARGETINFO_ENUM
12
13namespace llvm {
14namespace R600 {
15enum {
16 FeatureAddressableLocalMemorySize32768 = 0,
17 FeatureAddressableLocalMemorySize65536 = 1,
18 FeatureAddressableLocalMemorySize163840 = 2,
19 FeatureCFALUBug = 3,
20 FeatureCaymanISA = 4,
21 FeatureEvergreen = 5,
22 FeatureFMA = 6,
23 FeatureFP64 = 7,
24 FeatureFetchLimit8 = 8,
25 FeatureFetchLimit16 = 9,
26 FeatureNorthernIslands = 10,
27 FeaturePromoteAlloca = 11,
28 FeatureR600 = 12,
29 FeatureR600ALUInst = 13,
30 FeatureR700 = 14,
31 FeatureVertexCache = 15,
32 FeatureWavefrontSize16 = 16,
33 FeatureWavefrontSize32 = 17,
34 FeatureWavefrontSize64 = 18,
35 NumSubtargetFeatures = 19
36};
37} // end namespace R600
38} // end namespace llvm
39
40#endif // GET_SUBTARGETINFO_ENUM
41
42
43#ifdef GET_SUBTARGETINFO_MACRO
44GET_SUBTARGETINFO_MACRO(CFALUBug, false, cFALUBug)
45GET_SUBTARGETINFO_MACRO(CaymanISA, false, caymanISA)
46GET_SUBTARGETINFO_MACRO(EnablePromoteAlloca, false, enablePromoteAlloca)
47GET_SUBTARGETINFO_MACRO(FMA, false, fMA)
48GET_SUBTARGETINFO_MACRO(FP64, false, fP64)
49GET_SUBTARGETINFO_MACRO(HasVertexCache, false, hasVertexCache)
50GET_SUBTARGETINFO_MACRO(R600ALUInst, true, r600ALUInst)
51#undef GET_SUBTARGETINFO_MACRO
52#endif // GET_SUBTARGETINFO_MACRO
53
54
55#ifdef GET_SUBTARGETINFO_MC_DESC
56#undef GET_SUBTARGETINFO_MC_DESC
57
58namespace llvm {
59// Sorted (by key) array of values for CPU features.
60extern const llvm::SubtargetFeatureKV R600FeatureKV[] = {
61 { "HasVertexCache", "Specify use of dedicated vertex cache", R600::FeatureVertexCache, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
62 { "R600ALUInst", "Older version of ALU instructions encoding", R600::FeatureR600ALUInst, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
63 { "addressablelocalmemorysize163840", "The size of local memory in bytes", R600::FeatureAddressableLocalMemorySize163840, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
64 { "addressablelocalmemorysize32768", "The size of local memory in bytes", R600::FeatureAddressableLocalMemorySize32768, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
65 { "addressablelocalmemorysize65536", "The size of local memory in bytes", R600::FeatureAddressableLocalMemorySize65536, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
66 { "caymanISA", "Use Cayman ISA", R600::FeatureCaymanISA, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
67 { "cfalubug", "GPU has CF_ALU bug", R600::FeatureCFALUBug, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
68 { "evergreen", "EVERGREEN GPU generation", R600::FeatureEvergreen, { { { 0x201ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
69 { "fetch16", "Limit the maximum number of fetches in a clause to 16", R600::FeatureFetchLimit16, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
70 { "fetch8", "Limit the maximum number of fetches in a clause to 8", R600::FeatureFetchLimit8, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
71 { "fmaf", "Enable single precision FMA (not as fast as mul+add, but fused)", R600::FeatureFMA, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
72 { "fp64", "Enable double precision operations", R600::FeatureFP64, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
73 { "northern-islands", "NORTHERN_ISLANDS GPU generation", R600::FeatureNorthernIslands, { { { 0x40201ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
74 { "promote-alloca", "Enable promote alloca pass", R600::FeaturePromoteAlloca, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
75 { "r600", "R600 GPU generation", R600::FeatureR600, { { { 0x2100ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
76 { "r700", "R700 GPU generation", R600::FeatureR700, { { { 0x200ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
77 { "wavefrontsize16", "The number of threads per wavefront", R600::FeatureWavefrontSize16, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
78 { "wavefrontsize32", "The number of threads per wavefront", R600::FeatureWavefrontSize32, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
79 { "wavefrontsize64", "The number of threads per wavefront", R600::FeatureWavefrontSize64, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
80};
81
82#ifdef DBGFIELD
83#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
84#endif
85#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
86#define DBGFIELD(x) x,
87#define DBGVAL_OR_NULLPTR(x) x
88#else
89#define DBGFIELD(x)
90#define DBGVAL_OR_NULLPTR(x) nullptr
91#endif
92
93// Functional units for "R600_VLIW5_Itin"
94namespace R600_VLIW5_ItinFU {
95 const InstrStage::FuncUnits ALU_X = 1ULL << 0;
96 const InstrStage::FuncUnits ALU_Y = 1ULL << 1;
97 const InstrStage::FuncUnits ALU_Z = 1ULL << 2;
98 const InstrStage::FuncUnits ALU_W = 1ULL << 3;
99 const InstrStage::FuncUnits TRANS = 1ULL << 4;
100 const InstrStage::FuncUnits ALU_NULL = 1ULL << 5;
101} // end namespace R600_VLIW5_ItinFU
102
103// Functional units for "R600_VLIW4_Itin"
104namespace R600_VLIW4_ItinFU {
105 const InstrStage::FuncUnits ALU_X = 1ULL << 0;
106 const InstrStage::FuncUnits ALU_Y = 1ULL << 1;
107 const InstrStage::FuncUnits ALU_Z = 1ULL << 2;
108 const InstrStage::FuncUnits ALU_W = 1ULL << 3;
109 const InstrStage::FuncUnits ALU_NULL = 1ULL << 4;
110} // end namespace R600_VLIW4_ItinFU
111
112extern const llvm::InstrStage R600Stages[] = {
113 { 0, 0, 0, llvm::InstrStage::Required }, // No itinerary
114 { 1, R600_VLIW5_ItinFU::ALU_NULL, -1, (llvm::InstrStage::ReservationKinds)0 }, // 1
115 { 1, R600_VLIW5_ItinFU::ALU_X | R600_VLIW5_ItinFU::ALU_Y | R600_VLIW5_ItinFU::ALU_Z | R600_VLIW5_ItinFU::ALU_W, -1, (llvm::InstrStage::ReservationKinds)0 }, // 2
116 { 1, R600_VLIW5_ItinFU::ALU_X | R600_VLIW5_ItinFU::ALU_Y | R600_VLIW5_ItinFU::ALU_Z | R600_VLIW5_ItinFU::ALU_W | R600_VLIW5_ItinFU::TRANS, -1, (llvm::InstrStage::ReservationKinds)0 }, // 3
117 { 1, R600_VLIW5_ItinFU::TRANS, -1, (llvm::InstrStage::ReservationKinds)0 }, // 4
118 { 1, R600_VLIW5_ItinFU::ALU_X, -1, (llvm::InstrStage::ReservationKinds)0 }, // 5
119 { 1, R600_VLIW4_ItinFU::ALU_NULL, -1, (llvm::InstrStage::ReservationKinds)0 }, // 6
120 { 1, R600_VLIW4_ItinFU::ALU_X | R600_VLIW4_ItinFU::ALU_Y | R600_VLIW4_ItinFU::ALU_Z | R600_VLIW4_ItinFU::ALU_W, -1, (llvm::InstrStage::ReservationKinds)0 }, // 7
121 { 0, 0, 0, llvm::InstrStage::Required } // End stages
122};
123extern const unsigned R600OperandCycles[] = {
124 0, // No itinerary
125 0 // End operand cycles
126};
127extern const unsigned R600ForwardingPaths[] = {
128 0, // No itinerary
129 0 // End bypass tables
130};
131
132static constexpr llvm::InstrItinerary R600_VLIW5_Itin[] = {
133 { 0, 0, 0, 0, 0 }, // 0 NoInstrModel
134 { 1, 1, 2, 0, 0 }, // 1 NullALU
135 { 1, 2, 3, 0, 0 }, // 2 VecALU
136 { 1, 3, 4, 0, 0 }, // 3 AnyALU
137 { 1, 4, 5, 0, 0 }, // 4 TransALU
138 { 1, 5, 6, 0, 0 }, // 5 XALU
139 { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }// end marker
140};
141
142static constexpr llvm::InstrItinerary R600_VLIW4_Itin[] = {
143 { 0, 0, 0, 0, 0 }, // 0 NoInstrModel
144 { 1, 6, 7, 0, 0 }, // 1 NullALU
145 { 1, 7, 8, 0, 0 }, // 2 VecALU
146 { 1, 7, 8, 0, 0 }, // 3 AnyALU
147 { 1, 6, 7, 0, 0 }, // 4 TransALU
148 { 0, 0, 0, 0, 0 }, // 5 XALU
149 { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }// end marker
150};
151
152// ===============================================================
153// Data tables for the new per-operand machine model.
154
155// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}
156extern const llvm::MCWriteProcResEntry R600WriteProcResTable[] = {
157 { 0, 0, 0 }, // Invalid
158}; // R600WriteProcResTable
159
160// {Cycles, WriteResourceID}
161extern const llvm::MCWriteLatencyEntry R600WriteLatencyTable[] = {
162 { 0, 0}, // Invalid
163}; // R600WriteLatencyTable
164
165// {UseIdx, WriteResourceID, Cycles}
166extern const llvm::MCReadAdvanceEntry R600ReadAdvanceTable[] = {
167 {0, 0, 0}, // Invalid
168}; // R600ReadAdvanceTable
169
170#ifdef __GNUC__
171#pragma GCC diagnostic push
172#pragma GCC diagnostic ignored "-Woverlength-strings"
173#endif
174static constexpr char R600SchedClassNamesStorage[] =
175 "\0"
176 "InvalidSchedClass\0"
177 ;
178#ifdef __GNUC__
179#pragma GCC diagnostic pop
180#endif
181
182static constexpr llvm::StringTable R600SchedClassNames =
183 R600SchedClassNamesStorage;
184
185static const llvm::MCSchedModel NoSchedModel = {
186 MCSchedModel::DefaultIssueWidth,
187 MCSchedModel::DefaultMicroOpBufferSize,
188 MCSchedModel::DefaultLoopMicroOpBufferSize,
189 MCSchedModel::DefaultLoadLatency,
190 MCSchedModel::DefaultHighLatency,
191 MCSchedModel::DefaultMispredictPenalty,
192 false, // PostRAScheduler
193 false, // CompleteModel
194 false, // EnableIntervals
195 0, // Processor ID
196 nullptr, nullptr, 0, 0, // No instruction-level machine model.
197 DBGVAL_OR_NULLPTR(&R600SchedClassNames), // SchedClassNames
198 nullptr, // No Itinerary
199 nullptr // No extra processor descriptor
200};
201
202static const llvm::MCSchedModel R600_VLIW5_ItinModel = {
203 MCSchedModel::DefaultIssueWidth,
204 MCSchedModel::DefaultMicroOpBufferSize,
205 MCSchedModel::DefaultLoopMicroOpBufferSize,
206 MCSchedModel::DefaultLoadLatency,
207 MCSchedModel::DefaultHighLatency,
208 MCSchedModel::DefaultMispredictPenalty,
209 false, // PostRAScheduler
210 false, // CompleteModel
211 false, // EnableIntervals
212 1, // Processor ID
213 nullptr, nullptr, 0, 0, // No instruction-level machine model.
214 DBGVAL_OR_NULLPTR(&R600SchedClassNames), // SchedClassNames
215 R600_VLIW5_Itin,
216 nullptr // No extra processor descriptor
217};
218
219static const llvm::MCSchedModel R600_VLIW4_ItinModel = {
220 MCSchedModel::DefaultIssueWidth,
221 MCSchedModel::DefaultMicroOpBufferSize,
222 MCSchedModel::DefaultLoopMicroOpBufferSize,
223 MCSchedModel::DefaultLoadLatency,
224 MCSchedModel::DefaultHighLatency,
225 MCSchedModel::DefaultMispredictPenalty,
226 false, // PostRAScheduler
227 false, // CompleteModel
228 false, // EnableIntervals
229 2, // Processor ID
230 nullptr, nullptr, 0, 0, // No instruction-level machine model.
231 DBGVAL_OR_NULLPTR(&R600SchedClassNames), // SchedClassNames
232 R600_VLIW4_Itin,
233 nullptr // No extra processor descriptor
234};
235
236#undef DBGFIELD
237
238#undef DBGVAL_OR_NULLPTR
239
240// Sorted (by key) array of values for CPU subtype.
241extern const llvm::SubtargetSubTypeKV R600SubTypeKV[] = {
242 { "barts", { { { 0x8408ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
243 { "caicos", { { { 0x408ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
244 { "cayman", { { { 0x450ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW4_ItinModel },
245 { "cedar", { { { 0x28028ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
246 { "cypress", { { { 0x48060ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
247 { "juniper", { { { 0x48020ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
248 { "r600", { { { 0x49000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
249 { "r630", { { { 0x29000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
250 { "redwood", { { { 0x48028ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
251 { "rs880", { { { 0x11000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
252 { "rv670", { { { 0x49000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
253 { "rv710", { { { 0x2c000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
254 { "rv730", { { { 0x2c000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
255 { "rv770", { { { 0x4c000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
256 { "sumo", { { { 0x40028ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
257 { "turks", { { { 0x8408ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
258};
259
260// Sorted array of names of CPU subtypes, including aliases.
261extern const llvm::StringRef R600Names[] = {
262"barts",
263"caicos",
264"cayman",
265"cedar",
266"cypress",
267"juniper",
268"r600",
269"r630",
270"redwood",
271"rs880",
272"rv670",
273"rv710",
274"rv730",
275"rv770",
276"sumo",
277"turks"};
278
279namespace R600_MC {
280unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
281 const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) {
282 // Don't know how to resolve this scheduling class.
283 return 0;
284}
285} // end namespace R600_MC
286
287struct R600GenMCSubtargetInfo : public MCSubtargetInfo {
288 R600GenMCSubtargetInfo(const Triple &TT,
289 StringRef CPU, StringRef TuneCPU, StringRef FS,
290 ArrayRef<StringRef> PN,
291 ArrayRef<SubtargetFeatureKV> PF,
292 ArrayRef<SubtargetSubTypeKV> PD,
293 const MCWriteProcResEntry *WPR,
294 const MCWriteLatencyEntry *WL,
295 const MCReadAdvanceEntry *RA, const InstrStage *IS,
296 const unsigned *OC, const unsigned *FP) :
297 MCSubtargetInfo(TT, CPU, TuneCPU, FS, PN, PF, PD,
298 WPR, WL, RA, IS, OC, FP) { }
299
300 unsigned resolveVariantSchedClass(unsigned SchedClass,
301 const MCInst *MI, const MCInstrInfo *MCII,
302 unsigned CPUID) const override {
303 return R600_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);
304 }
305};
306
307static inline MCSubtargetInfo *createR600MCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
308 return new R600GenMCSubtargetInfo(TT, CPU, TuneCPU, FS, R600Names, R600FeatureKV, R600SubTypeKV,
309 R600WriteProcResTable, R600WriteLatencyTable, R600ReadAdvanceTable,
310 R600Stages, R600OperandCycles, R600ForwardingPaths);
311}
312
313} // end namespace llvm
314
315#endif // GET_SUBTARGETINFO_MC_DESC
316
317
318#ifdef GET_SUBTARGETINFO_TARGET_DESC
319#undef GET_SUBTARGETINFO_TARGET_DESC
320
321#include "llvm/ADT/BitmaskEnum.h"
322#include "llvm/Support/Debug.h"
323#include "llvm/Support/raw_ostream.h"
324
325// ParseSubtargetFeatures - Parses features string setting specified
326// subtarget options.
327void llvm::R600Subtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
328 LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
329 LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
330 LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
331 InitMCProcessorInfo(CPU, TuneCPU, FS);
332 const FeatureBitset &Bits = getFeatureBits();
333 if (Bits[R600::FeatureAddressableLocalMemorySize32768] && AddressableLocalMemorySize < 32768) AddressableLocalMemorySize = 32768;
334 if (Bits[R600::FeatureAddressableLocalMemorySize65536] && AddressableLocalMemorySize < 65536) AddressableLocalMemorySize = 65536;
335 if (Bits[R600::FeatureAddressableLocalMemorySize163840] && AddressableLocalMemorySize < 163840) AddressableLocalMemorySize = 163840;
336 if (Bits[R600::FeatureCFALUBug]) CFALUBug = true;
337 if (Bits[R600::FeatureCaymanISA]) CaymanISA = true;
338 if (Bits[R600::FeatureEvergreen] && Gen < R600Subtarget::EVERGREEN) Gen = R600Subtarget::EVERGREEN;
339 if (Bits[R600::FeatureFMA]) FMA = true;
340 if (Bits[R600::FeatureFP64]) FP64 = true;
341 if (Bits[R600::FeatureFetchLimit8] && TexVTXClauseSize < 8) TexVTXClauseSize = 8;
342 if (Bits[R600::FeatureFetchLimit16] && TexVTXClauseSize < 16) TexVTXClauseSize = 16;
343 if (Bits[R600::FeatureNorthernIslands] && Gen < R600Subtarget::NORTHERN_ISLANDS) Gen = R600Subtarget::NORTHERN_ISLANDS;
344 if (Bits[R600::FeaturePromoteAlloca]) EnablePromoteAlloca = true;
345 if (Bits[R600::FeatureR600] && Gen < R600Subtarget::R600) Gen = R600Subtarget::R600;
346 if (Bits[R600::FeatureR600ALUInst]) R600ALUInst = false;
347 if (Bits[R600::FeatureR700] && Gen < R600Subtarget::R700) Gen = R600Subtarget::R700;
348 if (Bits[R600::FeatureVertexCache]) HasVertexCache = true;
349 if (Bits[R600::FeatureWavefrontSize16] && WavefrontSizeLog2 < 4) WavefrontSizeLog2 = 4;
350 if (Bits[R600::FeatureWavefrontSize32] && WavefrontSizeLog2 < 5) WavefrontSizeLog2 = 5;
351 if (Bits[R600::FeatureWavefrontSize64] && WavefrontSizeLog2 < 6) WavefrontSizeLog2 = 6;
352}
353#endif // GET_SUBTARGETINFO_TARGET_DESC
354
355
356#ifdef GET_SUBTARGETINFO_HEADER
357#undef GET_SUBTARGETINFO_HEADER
358
359namespace llvm {
360class DFAPacketizer;
361namespace R600_MC {
362unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID);
363} // end namespace R600_MC
364
365struct R600GenSubtargetInfo : public TargetSubtargetInfo {
366 explicit R600GenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
367public:
368 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
369 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const override;
370 DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
371};
372} // end namespace llvm
373
374#endif // GET_SUBTARGETINFO_HEADER
375
376
377#ifdef GET_SUBTARGETINFO_CTOR
378#undef GET_SUBTARGETINFO_CTOR
379
380#include "llvm/CodeGen/TargetSchedule.h"
381
382namespace llvm {
383extern const llvm::StringRef R600Names[];
384extern const llvm::SubtargetFeatureKV R600FeatureKV[];
385extern const llvm::SubtargetSubTypeKV R600SubTypeKV[];
386extern const llvm::MCWriteProcResEntry R600WriteProcResTable[];
387extern const llvm::MCWriteLatencyEntry R600WriteLatencyTable[];
388extern const llvm::MCReadAdvanceEntry R600ReadAdvanceTable[];
389extern const llvm::InstrStage R600Stages[];
390extern const unsigned R600OperandCycles[];
391extern const unsigned R600ForwardingPaths[];
392R600GenSubtargetInfo::R600GenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
393 : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, ArrayRef(R600Names, 16), ArrayRef(R600FeatureKV, 19), ArrayRef(R600SubTypeKV, 16),
394 R600WriteProcResTable, R600WriteLatencyTable, R600ReadAdvanceTable,
395 R600Stages, R600OperandCycles, R600ForwardingPaths) {}
396
397unsigned R600GenSubtargetInfo
398::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
399 report_fatal_error("Expected a variant SchedClass");
400} // R600GenSubtargetInfo::resolveSchedClass
401
402unsigned R600GenSubtargetInfo
403::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {
404 return R600_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);
405} // R600GenSubtargetInfo::resolveVariantSchedClass
406
407} // end namespace llvm
408
409#endif // GET_SUBTARGETINFO_CTOR
410
411
412#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
413#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
414
415#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
416
417
418#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
419#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
420
421#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
422
423