1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11namespace llvm::AVR {
12 enum {
13 PHI = 0,
14 INLINEASM = 1,
15 INLINEASM_BR = 2,
16 CFI_INSTRUCTION = 3,
17 EH_LABEL = 4,
18 GC_LABEL = 5,
19 ANNOTATION_LABEL = 6,
20 KILL = 7,
21 EXTRACT_SUBREG = 8,
22 INSERT_SUBREG = 9,
23 IMPLICIT_DEF = 10,
24 INIT_UNDEF = 11,
25 SUBREG_TO_REG = 12,
26 COPY_TO_REGCLASS = 13,
27 DBG_VALUE = 14,
28 DBG_VALUE_LIST = 15,
29 DBG_INSTR_REF = 16,
30 DBG_PHI = 17,
31 DBG_LABEL = 18,
32 REG_SEQUENCE = 19,
33 COPY = 20,
34 BUNDLE = 21,
35 LIFETIME_START = 22,
36 LIFETIME_END = 23,
37 PSEUDO_PROBE = 24,
38 ARITH_FENCE = 25,
39 STACKMAP = 26,
40 FENTRY_CALL = 27,
41 PATCHPOINT = 28,
42 LOAD_STACK_GUARD = 29,
43 PREALLOCATED_SETUP = 30,
44 PREALLOCATED_ARG = 31,
45 STATEPOINT = 32,
46 LOCAL_ESCAPE = 33,
47 FAULTING_OP = 34,
48 PATCHABLE_OP = 35,
49 PATCHABLE_FUNCTION_ENTER = 36,
50 PATCHABLE_RET = 37,
51 PATCHABLE_FUNCTION_EXIT = 38,
52 PATCHABLE_TAIL_CALL = 39,
53 PATCHABLE_EVENT_CALL = 40,
54 PATCHABLE_TYPED_EVENT_CALL = 41,
55 ICALL_BRANCH_FUNNEL = 42,
56 FAKE_USE = 43,
57 MEMBARRIER = 44,
58 JUMP_TABLE_DEBUG_INFO = 45,
59 CONVERGENCECTRL_ENTRY = 46,
60 CONVERGENCECTRL_ANCHOR = 47,
61 CONVERGENCECTRL_LOOP = 48,
62 CONVERGENCECTRL_GLUE = 49,
63 G_ASSERT_SEXT = 50,
64 G_ASSERT_ZEXT = 51,
65 G_ASSERT_ALIGN = 52,
66 G_ADD = 53,
67 G_SUB = 54,
68 G_MUL = 55,
69 G_SDIV = 56,
70 G_UDIV = 57,
71 G_SREM = 58,
72 G_UREM = 59,
73 G_SDIVREM = 60,
74 G_UDIVREM = 61,
75 G_AND = 62,
76 G_OR = 63,
77 G_XOR = 64,
78 G_ABDS = 65,
79 G_ABDU = 66,
80 G_IMPLICIT_DEF = 67,
81 G_PHI = 68,
82 G_FRAME_INDEX = 69,
83 G_GLOBAL_VALUE = 70,
84 G_PTRAUTH_GLOBAL_VALUE = 71,
85 G_CONSTANT_POOL = 72,
86 G_EXTRACT = 73,
87 G_UNMERGE_VALUES = 74,
88 G_INSERT = 75,
89 G_MERGE_VALUES = 76,
90 G_BUILD_VECTOR = 77,
91 G_BUILD_VECTOR_TRUNC = 78,
92 G_CONCAT_VECTORS = 79,
93 G_PTRTOINT = 80,
94 G_INTTOPTR = 81,
95 G_BITCAST = 82,
96 G_FREEZE = 83,
97 G_CONSTANT_FOLD_BARRIER = 84,
98 G_INTRINSIC_FPTRUNC_ROUND = 85,
99 G_INTRINSIC_TRUNC = 86,
100 G_INTRINSIC_ROUND = 87,
101 G_INTRINSIC_LRINT = 88,
102 G_INTRINSIC_LLRINT = 89,
103 G_INTRINSIC_ROUNDEVEN = 90,
104 G_READCYCLECOUNTER = 91,
105 G_READSTEADYCOUNTER = 92,
106 G_LOAD = 93,
107 G_SEXTLOAD = 94,
108 G_ZEXTLOAD = 95,
109 G_INDEXED_LOAD = 96,
110 G_INDEXED_SEXTLOAD = 97,
111 G_INDEXED_ZEXTLOAD = 98,
112 G_STORE = 99,
113 G_INDEXED_STORE = 100,
114 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 101,
115 G_ATOMIC_CMPXCHG = 102,
116 G_ATOMICRMW_XCHG = 103,
117 G_ATOMICRMW_ADD = 104,
118 G_ATOMICRMW_SUB = 105,
119 G_ATOMICRMW_AND = 106,
120 G_ATOMICRMW_NAND = 107,
121 G_ATOMICRMW_OR = 108,
122 G_ATOMICRMW_XOR = 109,
123 G_ATOMICRMW_MAX = 110,
124 G_ATOMICRMW_MIN = 111,
125 G_ATOMICRMW_UMAX = 112,
126 G_ATOMICRMW_UMIN = 113,
127 G_ATOMICRMW_FADD = 114,
128 G_ATOMICRMW_FSUB = 115,
129 G_ATOMICRMW_FMAX = 116,
130 G_ATOMICRMW_FMIN = 117,
131 G_ATOMICRMW_FMAXIMUM = 118,
132 G_ATOMICRMW_FMINIMUM = 119,
133 G_ATOMICRMW_UINC_WRAP = 120,
134 G_ATOMICRMW_UDEC_WRAP = 121,
135 G_ATOMICRMW_USUB_COND = 122,
136 G_ATOMICRMW_USUB_SAT = 123,
137 G_FENCE = 124,
138 G_PREFETCH = 125,
139 G_BRCOND = 126,
140 G_BRINDIRECT = 127,
141 G_INVOKE_REGION_START = 128,
142 G_INTRINSIC = 129,
143 G_INTRINSIC_W_SIDE_EFFECTS = 130,
144 G_INTRINSIC_CONVERGENT = 131,
145 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 132,
146 G_ANYEXT = 133,
147 G_TRUNC = 134,
148 G_CONSTANT = 135,
149 G_FCONSTANT = 136,
150 G_VASTART = 137,
151 G_VAARG = 138,
152 G_SEXT = 139,
153 G_SEXT_INREG = 140,
154 G_ZEXT = 141,
155 G_SHL = 142,
156 G_LSHR = 143,
157 G_ASHR = 144,
158 G_FSHL = 145,
159 G_FSHR = 146,
160 G_ROTR = 147,
161 G_ROTL = 148,
162 G_ICMP = 149,
163 G_FCMP = 150,
164 G_SCMP = 151,
165 G_UCMP = 152,
166 G_SELECT = 153,
167 G_UADDO = 154,
168 G_UADDE = 155,
169 G_USUBO = 156,
170 G_USUBE = 157,
171 G_SADDO = 158,
172 G_SADDE = 159,
173 G_SSUBO = 160,
174 G_SSUBE = 161,
175 G_UMULO = 162,
176 G_SMULO = 163,
177 G_UMULH = 164,
178 G_SMULH = 165,
179 G_UADDSAT = 166,
180 G_SADDSAT = 167,
181 G_USUBSAT = 168,
182 G_SSUBSAT = 169,
183 G_USHLSAT = 170,
184 G_SSHLSAT = 171,
185 G_SMULFIX = 172,
186 G_UMULFIX = 173,
187 G_SMULFIXSAT = 174,
188 G_UMULFIXSAT = 175,
189 G_SDIVFIX = 176,
190 G_UDIVFIX = 177,
191 G_SDIVFIXSAT = 178,
192 G_UDIVFIXSAT = 179,
193 G_FADD = 180,
194 G_FSUB = 181,
195 G_FMUL = 182,
196 G_FMA = 183,
197 G_FMAD = 184,
198 G_FDIV = 185,
199 G_FREM = 186,
200 G_FPOW = 187,
201 G_FPOWI = 188,
202 G_FEXP = 189,
203 G_FEXP2 = 190,
204 G_FEXP10 = 191,
205 G_FLOG = 192,
206 G_FLOG2 = 193,
207 G_FLOG10 = 194,
208 G_FLDEXP = 195,
209 G_FFREXP = 196,
210 G_FNEG = 197,
211 G_FPEXT = 198,
212 G_FPTRUNC = 199,
213 G_FPTOSI = 200,
214 G_FPTOUI = 201,
215 G_SITOFP = 202,
216 G_UITOFP = 203,
217 G_FPTOSI_SAT = 204,
218 G_FPTOUI_SAT = 205,
219 G_FABS = 206,
220 G_FCOPYSIGN = 207,
221 G_IS_FPCLASS = 208,
222 G_FCANONICALIZE = 209,
223 G_FMINNUM = 210,
224 G_FMAXNUM = 211,
225 G_FMINNUM_IEEE = 212,
226 G_FMAXNUM_IEEE = 213,
227 G_FMINIMUM = 214,
228 G_FMAXIMUM = 215,
229 G_FMINIMUMNUM = 216,
230 G_FMAXIMUMNUM = 217,
231 G_GET_FPENV = 218,
232 G_SET_FPENV = 219,
233 G_RESET_FPENV = 220,
234 G_GET_FPMODE = 221,
235 G_SET_FPMODE = 222,
236 G_RESET_FPMODE = 223,
237 G_PTR_ADD = 224,
238 G_PTRMASK = 225,
239 G_SMIN = 226,
240 G_SMAX = 227,
241 G_UMIN = 228,
242 G_UMAX = 229,
243 G_ABS = 230,
244 G_LROUND = 231,
245 G_LLROUND = 232,
246 G_BR = 233,
247 G_BRJT = 234,
248 G_VSCALE = 235,
249 G_INSERT_SUBVECTOR = 236,
250 G_EXTRACT_SUBVECTOR = 237,
251 G_INSERT_VECTOR_ELT = 238,
252 G_EXTRACT_VECTOR_ELT = 239,
253 G_SHUFFLE_VECTOR = 240,
254 G_SPLAT_VECTOR = 241,
255 G_STEP_VECTOR = 242,
256 G_VECTOR_COMPRESS = 243,
257 G_CTTZ = 244,
258 G_CTTZ_ZERO_UNDEF = 245,
259 G_CTLZ = 246,
260 G_CTLZ_ZERO_UNDEF = 247,
261 G_CTPOP = 248,
262 G_BSWAP = 249,
263 G_BITREVERSE = 250,
264 G_FCEIL = 251,
265 G_FCOS = 252,
266 G_FSIN = 253,
267 G_FSINCOS = 254,
268 G_FTAN = 255,
269 G_FACOS = 256,
270 G_FASIN = 257,
271 G_FATAN = 258,
272 G_FATAN2 = 259,
273 G_FCOSH = 260,
274 G_FSINH = 261,
275 G_FTANH = 262,
276 G_FSQRT = 263,
277 G_FFLOOR = 264,
278 G_FRINT = 265,
279 G_FNEARBYINT = 266,
280 G_ADDRSPACE_CAST = 267,
281 G_BLOCK_ADDR = 268,
282 G_JUMP_TABLE = 269,
283 G_DYN_STACKALLOC = 270,
284 G_STACKSAVE = 271,
285 G_STACKRESTORE = 272,
286 G_STRICT_FADD = 273,
287 G_STRICT_FSUB = 274,
288 G_STRICT_FMUL = 275,
289 G_STRICT_FDIV = 276,
290 G_STRICT_FREM = 277,
291 G_STRICT_FMA = 278,
292 G_STRICT_FSQRT = 279,
293 G_STRICT_FLDEXP = 280,
294 G_READ_REGISTER = 281,
295 G_WRITE_REGISTER = 282,
296 G_MEMCPY = 283,
297 G_MEMCPY_INLINE = 284,
298 G_MEMMOVE = 285,
299 G_MEMSET = 286,
300 G_BZERO = 287,
301 G_TRAP = 288,
302 G_DEBUGTRAP = 289,
303 G_UBSANTRAP = 290,
304 G_VECREDUCE_SEQ_FADD = 291,
305 G_VECREDUCE_SEQ_FMUL = 292,
306 G_VECREDUCE_FADD = 293,
307 G_VECREDUCE_FMUL = 294,
308 G_VECREDUCE_FMAX = 295,
309 G_VECREDUCE_FMIN = 296,
310 G_VECREDUCE_FMAXIMUM = 297,
311 G_VECREDUCE_FMINIMUM = 298,
312 G_VECREDUCE_ADD = 299,
313 G_VECREDUCE_MUL = 300,
314 G_VECREDUCE_AND = 301,
315 G_VECREDUCE_OR = 302,
316 G_VECREDUCE_XOR = 303,
317 G_VECREDUCE_SMAX = 304,
318 G_VECREDUCE_SMIN = 305,
319 G_VECREDUCE_UMAX = 306,
320 G_VECREDUCE_UMIN = 307,
321 G_SBFX = 308,
322 G_UBFX = 309,
323 ADCWRdRr = 310,
324 ADDWRdRr = 311,
325 ADJCALLSTACKDOWN = 312,
326 ADJCALLSTACKUP = 313,
327 ANDIWRdK = 314,
328 ANDWRdRr = 315,
329 ASRBNRd = 316,
330 ASRWLoRd = 317,
331 ASRWNRd = 318,
332 ASRWRd = 319,
333 Asr16 = 320,
334 Asr32 = 321,
335 Asr8 = 322,
336 AtomicFence = 323,
337 AtomicLoad16 = 324,
338 AtomicLoad8 = 325,
339 AtomicLoadAdd16 = 326,
340 AtomicLoadAdd8 = 327,
341 AtomicLoadAnd16 = 328,
342 AtomicLoadAnd8 = 329,
343 AtomicLoadOr16 = 330,
344 AtomicLoadOr8 = 331,
345 AtomicLoadSub16 = 332,
346 AtomicLoadSub8 = 333,
347 AtomicLoadXor16 = 334,
348 AtomicLoadXor8 = 335,
349 AtomicStore16 = 336,
350 AtomicStore8 = 337,
351 COMWRd = 338,
352 CPCWRdRr = 339,
353 CPWRdRr = 340,
354 CopyZero = 341,
355 ELPMBRdZ = 342,
356 ELPMBRdZPi = 343,
357 ELPMWRdZ = 344,
358 ELPMWRdZPi = 345,
359 EORWRdRr = 346,
360 FRMIDX = 347,
361 INWRdA = 348,
362 LDDWRdPtrQ = 349,
363 LDDWRdYQ = 350,
364 LDIWRdK = 351,
365 LDSWRdK = 352,
366 LDWRdPtr = 353,
367 LDWRdPtrPd = 354,
368 LDWRdPtrPi = 355,
369 LPMBRdZ = 356,
370 LPMWRdZ = 357,
371 LPMWRdZPi = 358,
372 LSLBNRd = 359,
373 LSLWHiRd = 360,
374 LSLWNRd = 361,
375 LSLWRd = 362,
376 LSRBNRd = 363,
377 LSRWLoRd = 364,
378 LSRWNRd = 365,
379 LSRWRd = 366,
380 Lsl16 = 367,
381 Lsl32 = 368,
382 Lsl8 = 369,
383 Lsr16 = 370,
384 Lsr32 = 371,
385 Lsr8 = 372,
386 NEGWRd = 373,
387 ORIWRdK = 374,
388 ORWRdRr = 375,
389 OUTWARr = 376,
390 POPWRd = 377,
391 PUSHWRr = 378,
392 ROLBRdR1 = 379,
393 ROLBRdR17 = 380,
394 ROLWRd = 381,
395 RORBRd = 382,
396 RORWRd = 383,
397 Rol16 = 384,
398 Rol8 = 385,
399 Ror16 = 386,
400 Ror8 = 387,
401 SBCIWRdK = 388,
402 SBCWRdRr = 389,
403 SEXT = 390,
404 SPREAD = 391,
405 SPWRITE = 392,
406 STDSPQRr = 393,
407 STDWPtrQRr = 394,
408 STDWSPQRr = 395,
409 STSWKRr = 396,
410 STWPtrPdRr = 397,
411 STWPtrPiRr = 398,
412 STWPtrRr = 399,
413 SUBIWRdK = 400,
414 SUBWRdRr = 401,
415 Select16 = 402,
416 Select8 = 403,
417 ZEXT = 404,
418 ADCRdRr = 405,
419 ADDRdRr = 406,
420 ADIWRdK = 407,
421 ANDIRdK = 408,
422 ANDRdRr = 409,
423 ASRRd = 410,
424 BCLRs = 411,
425 BLD = 412,
426 BRBCsk = 413,
427 BRBSsk = 414,
428 BREAK = 415,
429 BREQk = 416,
430 BRGEk = 417,
431 BRLOk = 418,
432 BRLTk = 419,
433 BRMIk = 420,
434 BRNEk = 421,
435 BRPLk = 422,
436 BRSHk = 423,
437 BSETs = 424,
438 BST = 425,
439 CALLk = 426,
440 CBIAb = 427,
441 COMRd = 428,
442 CPCRdRr = 429,
443 CPIRdK = 430,
444 CPRdRr = 431,
445 CPSE = 432,
446 DECRd = 433,
447 DESK = 434,
448 EICALL = 435,
449 EIJMP = 436,
450 ELPM = 437,
451 ELPMRdZ = 438,
452 ELPMRdZPi = 439,
453 EORRdRr = 440,
454 FMUL = 441,
455 FMULS = 442,
456 FMULSU = 443,
457 ICALL = 444,
458 IJMP = 445,
459 INCRd = 446,
460 INRdA = 447,
461 JMPk = 448,
462 LACZRd = 449,
463 LASZRd = 450,
464 LATZRd = 451,
465 LDDRdPtrQ = 452,
466 LDIRdK = 453,
467 LDRdPtr = 454,
468 LDRdPtrPd = 455,
469 LDRdPtrPi = 456,
470 LDSRdK = 457,
471 LDSRdKTiny = 458,
472 LPM = 459,
473 LPMRdZ = 460,
474 LPMRdZPi = 461,
475 LSRRd = 462,
476 MOVRdRr = 463,
477 MOVWRdRr = 464,
478 MULRdRr = 465,
479 MULSRdRr = 466,
480 MULSURdRr = 467,
481 NEGRd = 468,
482 NOP = 469,
483 ORIRdK = 470,
484 ORRdRr = 471,
485 OUTARr = 472,
486 POPRd = 473,
487 PUSHRr = 474,
488 RCALLk = 475,
489 RET = 476,
490 RETI = 477,
491 RJMPk = 478,
492 RORRd = 479,
493 SBCIRdK = 480,
494 SBCRdRr = 481,
495 SBIAb = 482,
496 SBICAb = 483,
497 SBISAb = 484,
498 SBIWRdK = 485,
499 SBRCRrB = 486,
500 SBRSRrB = 487,
501 SLEEP = 488,
502 SPM = 489,
503 SPMZPi = 490,
504 STDPtrQRr = 491,
505 STPtrPdRr = 492,
506 STPtrPiRr = 493,
507 STPtrRr = 494,
508 STSKRr = 495,
509 STSKRrTiny = 496,
510 SUBIRdK = 497,
511 SUBRdRr = 498,
512 SWAPRd = 499,
513 WDR = 500,
514 XCHZRd = 501,
515 INSTRUCTION_LIST_END = 502
516 };
517
518} // end namespace llvm::AVR
519#endif // GET_INSTRINFO_ENUM
520
521#ifdef GET_INSTRINFO_SCHED_ENUM
522#undef GET_INSTRINFO_SCHED_ENUM
523namespace llvm::AVR::Sched {
524
525 enum {
526 NoInstrModel = 0,
527 SCHED_LIST_END = 1
528 };
529} // end namespace llvm::AVR::Sched
530#endif // GET_INSTRINFO_SCHED_ENUM
531
532#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
533namespace llvm {
534
535struct AVRInstrTable {
536 MCInstrDesc Insts[502];
537 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
538 MCOperandInfo OperandInfo[315];
539 static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps");
540 MCPhysReg ImplicitOps[44];
541};
542
543} // end namespace llvm
544#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
545
546#ifdef GET_INSTRINFO_MC_DESC
547#undef GET_INSTRINFO_MC_DESC
548namespace llvm {
549
550static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0);
551static constexpr unsigned AVRImpOpBase = sizeof AVRInstrTable::OperandInfo / (sizeof(MCPhysReg));
552
553extern const AVRInstrTable AVRDescs = {
554 {
555 { 501, 2, 1, 2, 0, 0, 0, 223, AVRImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #501 = XCHZRd
556 { 500, 0, 0, 2, 0, 0, 0, 1, AVRImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #500 = WDR
557 { 499, 2, 1, 2, 0, 0, 0, 238, AVRImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #499 = SWAPRd
558 { 498, 3, 1, 2, 0, 0, 1, 269, AVRImpOpBase + 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #498 = SUBRdRr
559 { 497, 3, 1, 2, 0, 0, 1, 275, AVRImpOpBase + 2, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #497 = SUBIRdK
560 { 496, 2, 0, 2, 0, 0, 0, 313, AVRImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #496 = STSKRrTiny
561 { 495, 2, 0, 4, 0, 0, 0, 303, AVRImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #495 = STSKRr
562 { 494, 2, 0, 2, 0, 0, 0, 189, AVRImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #494 = STPtrRr
563 { 493, 4, 1, 2, 0, 0, 0, 309, AVRImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #493 = STPtrPiRr
564 { 492, 4, 1, 2, 0, 0, 0, 309, AVRImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #492 = STPtrPdRr
565 { 491, 3, 0, 2, 0, 0, 0, 306, AVRImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #491 = STDPtrQRr
566 { 490, 1, 0, 2, 0, 2, 1, 305, AVRImpOpBase + 41, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #490 = SPMZPi
567 { 489, 0, 0, 2, 0, 3, 0, 1, AVRImpOpBase + 38, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #489 = SPM
568 { 488, 0, 0, 2, 0, 0, 0, 1, AVRImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #488 = SLEEP
569 { 487, 2, 0, 2, 0, 0, 0, 283, AVRImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #487 = SBRSRrB
570 { 486, 2, 0, 2, 0, 0, 0, 283, AVRImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #486 = SBRCRrB
571 { 485, 3, 1, 2, 0, 0, 1, 272, AVRImpOpBase + 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #485 = SBIWRdK
572 { 484, 2, 0, 2, 0, 0, 0, 285, AVRImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #484 = SBISAb
573 { 483, 2, 0, 2, 0, 0, 0, 285, AVRImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #483 = SBICAb
574 { 482, 2, 0, 2, 0, 0, 0, 285, AVRImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #482 = SBIAb
575 { 481, 3, 1, 2, 0, 1, 1, 269, AVRImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #481 = SBCRdRr
576 { 480, 3, 1, 2, 0, 1, 1, 275, AVRImpOpBase + 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #480 = SBCIRdK
577 { 479, 2, 1, 2, 0, 1, 1, 238, AVRImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #479 = RORRd
578 { 478, 1, 0, 2, 0, 0, 0, 0, AVRImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #478 = RJMPk
579 { 477, 0, 0, 2, 0, 0, 0, 1, AVRImpOpBase + 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #477 = RETI
580 { 476, 0, 0, 2, 0, 0, 0, 1, AVRImpOpBase + 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #476 = RET
581 { 475, 1, 0, 2, 0, 1, 0, 0, AVRImpOpBase + 16, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #475 = RCALLk
582 { 474, 1, 0, 2, 0, 1, 1, 193, AVRImpOpBase + 10, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #474 = PUSHRr
583 { 473, 1, 1, 2, 0, 1, 1, 193, AVRImpOpBase + 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #473 = POPRd
584 { 472, 2, 0, 2, 0, 0, 0, 303, AVRImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #472 = OUTARr
585 { 471, 3, 1, 2, 0, 0, 1, 269, AVRImpOpBase + 2, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #471 = ORRdRr
586 { 470, 3, 1, 2, 0, 0, 1, 275, AVRImpOpBase + 2, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #470 = ORIRdK
587 { 469, 0, 0, 2, 0, 0, 0, 1, AVRImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #469 = NOP
588 { 468, 2, 1, 2, 0, 0, 1, 238, AVRImpOpBase + 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #468 = NEGRd
589 { 467, 2, 0, 2, 0, 0, 3, 291, AVRImpOpBase + 35, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #467 = MULSURdRr
590 { 466, 2, 0, 2, 0, 0, 3, 301, AVRImpOpBase + 35, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #466 = MULSRdRr
591 { 465, 2, 0, 2, 0, 0, 3, 287, AVRImpOpBase + 35, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #465 = MULRdRr
592 { 464, 2, 1, 2, 0, 0, 0, 191, AVRImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #464 = MOVWRdRr
593 { 463, 2, 1, 2, 0, 0, 0, 287, AVRImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #463 = MOVRdRr
594 { 462, 2, 1, 2, 0, 0, 1, 238, AVRImpOpBase + 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #462 = LSRRd
595 { 461, 2, 1, 2, 0, 0, 1, 223, AVRImpOpBase + 9, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #461 = LPMRdZPi
596 { 460, 2, 1, 2, 0, 0, 0, 223, AVRImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #460 = LPMRdZ
597 { 459, 0, 0, 2, 0, 1, 1, 1, AVRImpOpBase + 33, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #459 = LPM
598 { 458, 2, 1, 2, 0, 0, 0, 289, AVRImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #458 = LDSRdKTiny
599 { 457, 2, 1, 4, 0, 0, 0, 293, AVRImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #457 = LDSRdK
600 { 456, 3, 2, 2, 0, 0, 0, 298, AVRImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #456 = LDRdPtrPi
601 { 455, 3, 2, 2, 0, 0, 0, 298, AVRImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #455 = LDRdPtrPd
602 { 454, 2, 1, 2, 0, 0, 0, 179, AVRImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #454 = LDRdPtr
603 { 453, 2, 1, 2, 0, 0, 0, 289, AVRImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #453 = LDIRdK
604 { 452, 3, 1, 2, 0, 0, 0, 295, AVRImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #452 = LDDRdPtrQ
605 { 451, 2, 1, 2, 0, 0, 0, 223, AVRImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #451 = LATZRd
606 { 450, 2, 1, 2, 0, 0, 0, 223, AVRImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #450 = LASZRd
607 { 449, 2, 1, 2, 0, 0, 0, 223, AVRImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #449 = LACZRd
608 { 448, 1, 0, 4, 0, 0, 0, 0, AVRImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #448 = JMPk
609 { 447, 2, 1, 2, 0, 0, 0, 293, AVRImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #447 = INRdA
610 { 446, 2, 1, 2, 0, 0, 1, 238, AVRImpOpBase + 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #446 = INCRd
611 { 445, 0, 0, 2, 0, 1, 0, 1, AVRImpOpBase + 9, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #445 = IJMP
612 { 444, 0, 0, 2, 0, 2, 0, 1, AVRImpOpBase + 6, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #444 = ICALL
613 { 443, 2, 0, 2, 0, 0, 3, 291, AVRImpOpBase + 35, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #443 = FMULSU
614 { 442, 2, 0, 2, 0, 0, 3, 291, AVRImpOpBase + 35, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #442 = FMULS
615 { 441, 2, 0, 2, 0, 0, 3, 291, AVRImpOpBase + 35, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #441 = FMUL
616 { 440, 3, 1, 2, 0, 0, 1, 269, AVRImpOpBase + 2, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #440 = EORRdRr
617 { 439, 2, 1, 2, 0, 0, 1, 223, AVRImpOpBase + 9, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #439 = ELPMRdZPi
618 { 438, 2, 1, 2, 0, 0, 0, 223, AVRImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #438 = ELPMRdZ
619 { 437, 0, 0, 2, 0, 1, 1, 1, AVRImpOpBase + 33, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #437 = ELPM
620 { 436, 0, 0, 2, 0, 1, 0, 1, AVRImpOpBase + 9, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #436 = EIJMP
621 { 435, 0, 0, 2, 0, 2, 0, 1, AVRImpOpBase + 6, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #435 = EICALL
622 { 434, 1, 0, 2, 0, 0, 16, 1, AVRImpOpBase + 17, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #434 = DESK
623 { 433, 2, 1, 2, 0, 0, 1, 238, AVRImpOpBase + 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #433 = DECRd
624 { 432, 2, 0, 2, 0, 0, 1, 287, AVRImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #432 = CPSE
625 { 431, 2, 0, 2, 0, 0, 1, 287, AVRImpOpBase + 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #431 = CPRdRr
626 { 430, 2, 0, 2, 0, 0, 1, 289, AVRImpOpBase + 2, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #430 = CPIRdK
627 { 429, 2, 0, 2, 0, 1, 1, 287, AVRImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #429 = CPCRdRr
628 { 428, 2, 1, 2, 0, 0, 1, 238, AVRImpOpBase + 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #428 = COMRd
629 { 427, 2, 0, 2, 0, 0, 0, 285, AVRImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #427 = CBIAb
630 { 426, 1, 0, 4, 0, 1, 0, 0, AVRImpOpBase + 16, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #426 = CALLk
631 { 425, 2, 0, 2, 0, 0, 1, 283, AVRImpOpBase + 2, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #425 = BST
632 { 424, 1, 0, 2, 0, 0, 1, 1, AVRImpOpBase + 2, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #424 = BSETs
633 { 423, 1, 0, 2, 0, 1, 0, 0, AVRImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #423 = BRSHk
634 { 422, 1, 0, 2, 0, 1, 0, 0, AVRImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #422 = BRPLk
635 { 421, 1, 0, 2, 0, 1, 0, 0, AVRImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #421 = BRNEk
636 { 420, 1, 0, 2, 0, 1, 0, 0, AVRImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #420 = BRMIk
637 { 419, 1, 0, 2, 0, 1, 0, 0, AVRImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #419 = BRLTk
638 { 418, 1, 0, 2, 0, 1, 0, 0, AVRImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #418 = BRLOk
639 { 417, 1, 0, 2, 0, 1, 0, 0, AVRImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #417 = BRGEk
640 { 416, 1, 0, 2, 0, 1, 0, 0, AVRImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #416 = BREQk
641 { 415, 0, 0, 2, 0, 0, 0, 1, AVRImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #415 = BREAK
642 { 414, 2, 0, 2, 0, 1, 0, 281, AVRImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #414 = BRBSsk
643 { 413, 2, 0, 2, 0, 1, 0, 281, AVRImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #413 = BRBCsk
644 { 412, 3, 1, 2, 0, 1, 0, 278, AVRImpOpBase + 2, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #412 = BLD
645 { 411, 1, 0, 2, 0, 0, 1, 1, AVRImpOpBase + 2, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #411 = BCLRs
646 { 410, 2, 1, 2, 0, 0, 1, 238, AVRImpOpBase + 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #410 = ASRRd
647 { 409, 3, 1, 2, 0, 0, 1, 269, AVRImpOpBase + 2, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #409 = ANDRdRr
648 { 408, 3, 1, 2, 0, 0, 1, 275, AVRImpOpBase + 2, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #408 = ANDIRdK
649 { 407, 3, 1, 2, 0, 0, 1, 272, AVRImpOpBase + 2, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #407 = ADIWRdK
650 { 406, 3, 1, 2, 0, 0, 1, 269, AVRImpOpBase + 2, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #406 = ADDRdRr
651 { 405, 3, 1, 2, 0, 1, 1, 269, AVRImpOpBase + 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #405 = ADCRdRr
652 { 404, 2, 1, 2, 0, 0, 1, 240, AVRImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #404 = ZEXT
653 { 403, 4, 1, 2, 0, 1, 0, 265, AVRImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #403 = Select8
654 { 402, 4, 1, 2, 0, 1, 0, 261, AVRImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #402 = Select16
655 { 401, 3, 1, 2, 0, 0, 1, 152, AVRImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #401 = SUBWRdRr
656 { 400, 3, 1, 2, 0, 0, 1, 155, AVRImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #400 = SUBIWRdK
657 { 399, 2, 0, 2, 0, 0, 0, 187, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #399 = STWPtrRr
658 { 398, 4, 1, 2, 0, 0, 0, 257, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #398 = STWPtrPiRr
659 { 397, 4, 1, 2, 0, 0, 0, 257, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #397 = STWPtrPdRr
660 { 396, 2, 0, 2, 0, 0, 0, 255, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #396 = STSWKRr
661 { 395, 3, 0, 2, 0, 0, 1, 252, AVRImpOpBase + 16, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #395 = STDWSPQRr
662 { 394, 3, 0, 2, 0, 0, 0, 249, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #394 = STDWPtrQRr
663 { 393, 3, 0, 2, 0, 0, 1, 246, AVRImpOpBase + 16, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #393 = STDSPQRr
664 { 392, 2, 1, 2, 0, 0, 1, 244, AVRImpOpBase + 16, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #392 = SPWRITE
665 { 391, 2, 1, 2, 0, 1, 0, 242, AVRImpOpBase + 16, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #391 = SPREAD
666 { 390, 2, 1, 2, 0, 0, 1, 240, AVRImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #390 = SEXT
667 { 389, 3, 1, 2, 0, 1, 1, 152, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #389 = SBCWRdRr
668 { 388, 3, 1, 2, 0, 1, 1, 155, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #388 = SBCIWRdK
669 { 387, 3, 1, 2, 0, 0, 1, 174, AVRImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #387 = Ror8
670 { 386, 3, 1, 2, 0, 0, 1, 166, AVRImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #386 = Ror16
671 { 385, 3, 1, 2, 0, 0, 1, 174, AVRImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #385 = Rol8
672 { 384, 3, 1, 2, 0, 0, 1, 166, AVRImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #384 = Rol16
673 { 383, 2, 1, 2, 0, 1, 1, 161, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #383 = RORWRd
674 { 382, 2, 1, 2, 0, 0, 1, 238, AVRImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #382 = RORBRd
675 { 381, 2, 1, 2, 0, 1, 1, 161, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #381 = ROLWRd
676 { 380, 2, 1, 2, 0, 1, 1, 238, AVRImpOpBase + 14, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #380 = ROLBRdR17
677 { 379, 2, 1, 2, 0, 1, 1, 238, AVRImpOpBase + 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #379 = ROLBRdR1
678 { 378, 1, 0, 2, 0, 1, 1, 237, AVRImpOpBase + 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #378 = PUSHWRr
679 { 377, 1, 1, 2, 0, 1, 1, 237, AVRImpOpBase + 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #377 = POPWRd
680 { 376, 2, 0, 2, 0, 0, 0, 235, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #376 = OUTWARr
681 { 375, 3, 1, 2, 0, 0, 1, 152, AVRImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #375 = ORWRdRr
682 { 374, 3, 1, 2, 0, 0, 1, 155, AVRImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #374 = ORIWRdK
683 { 373, 3, 1, 2, 0, 0, 1, 232, AVRImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #373 = NEGWRd
684 { 372, 3, 1, 2, 0, 0, 1, 174, AVRImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #372 = Lsr8
685 { 371, 5, 2, 2, 0, 0, 1, 169, AVRImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #371 = Lsr32
686 { 370, 3, 1, 2, 0, 0, 1, 166, AVRImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #370 = Lsr16
687 { 369, 3, 1, 2, 0, 0, 1, 174, AVRImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #369 = Lsl8
688 { 368, 5, 2, 2, 0, 0, 1, 169, AVRImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #368 = Lsl32
689 { 367, 3, 1, 2, 0, 0, 1, 166, AVRImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #367 = Lsl16
690 { 366, 2, 1, 2, 0, 0, 1, 161, AVRImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #366 = LSRWRd
691 { 365, 3, 1, 2, 0, 0, 1, 229, AVRImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #365 = LSRWNRd
692 { 364, 2, 1, 2, 0, 0, 1, 161, AVRImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #364 = LSRWLoRd
693 { 363, 3, 1, 2, 0, 0, 1, 158, AVRImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #363 = LSRBNRd
694 { 362, 2, 1, 2, 0, 0, 1, 161, AVRImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #362 = LSLWRd
695 { 361, 3, 1, 2, 0, 0, 1, 229, AVRImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #361 = LSLWNRd
696 { 360, 2, 1, 2, 0, 0, 1, 161, AVRImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #360 = LSLWHiRd
697 { 359, 3, 1, 2, 0, 0, 1, 158, AVRImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #359 = LSLBNRd
698 { 358, 2, 1, 2, 0, 0, 1, 227, AVRImpOpBase + 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #358 = LPMWRdZPi
699 { 357, 2, 1, 2, 0, 0, 1, 225, AVRImpOpBase + 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #357 = LPMWRdZ
700 { 356, 2, 1, 2, 0, 0, 1, 223, AVRImpOpBase + 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #356 = LPMBRdZ
701 { 355, 3, 2, 2, 0, 0, 0, 220, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #355 = LDWRdPtrPi
702 { 354, 3, 2, 2, 0, 0, 0, 220, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #354 = LDWRdPtrPd
703 { 353, 2, 1, 2, 0, 0, 0, 218, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #353 = LDWRdPtr
704 { 352, 2, 1, 2, 0, 0, 0, 216, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #352 = LDSWRdK
705 { 351, 2, 1, 2, 0, 0, 0, 214, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #351 = LDIWRdK
706 { 350, 3, 1, 2, 0, 0, 0, 211, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #350 = LDDWRdYQ
707 { 349, 3, 1, 2, 0, 0, 0, 208, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #349 = LDDWRdPtrQ
708 { 348, 2, 1, 2, 0, 0, 0, 206, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #348 = INWRdA
709 { 347, 3, 1, 2, 0, 0, 1, 203, AVRImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #347 = FRMIDX
710 { 346, 3, 1, 2, 0, 0, 1, 152, AVRImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #346 = EORWRdRr
711 { 345, 3, 1, 2, 0, 0, 1, 200, AVRImpOpBase + 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #345 = ELPMWRdZPi
712 { 344, 3, 1, 2, 0, 0, 1, 197, AVRImpOpBase + 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #344 = ELPMWRdZ
713 { 343, 3, 1, 2, 0, 0, 1, 194, AVRImpOpBase + 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #343 = ELPMBRdZPi
714 { 342, 3, 1, 2, 0, 0, 1, 194, AVRImpOpBase + 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #342 = ELPMBRdZ
715 { 341, 1, 1, 2, 0, 0, 0, 193, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #341 = CopyZero
716 { 340, 2, 0, 2, 0, 0, 1, 191, AVRImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #340 = CPWRdRr
717 { 339, 2, 0, 2, 0, 1, 1, 191, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #339 = CPCWRdRr
718 { 338, 2, 1, 2, 0, 0, 1, 161, AVRImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #338 = COMWRd
719 { 337, 2, 0, 2, 0, 0, 0, 189, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #337 = AtomicStore8
720 { 336, 2, 0, 2, 0, 0, 0, 187, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #336 = AtomicStore16
721 { 335, 3, 1, 2, 0, 0, 0, 184, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #335 = AtomicLoadXor8
722 { 334, 3, 1, 2, 0, 0, 0, 181, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #334 = AtomicLoadXor16
723 { 333, 3, 1, 2, 0, 0, 0, 184, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #333 = AtomicLoadSub8
724 { 332, 3, 1, 2, 0, 0, 0, 181, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #332 = AtomicLoadSub16
725 { 331, 3, 1, 2, 0, 0, 0, 184, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #331 = AtomicLoadOr8
726 { 330, 3, 1, 2, 0, 0, 0, 181, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #330 = AtomicLoadOr16
727 { 329, 3, 1, 2, 0, 0, 0, 184, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #329 = AtomicLoadAnd8
728 { 328, 3, 1, 2, 0, 0, 0, 181, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #328 = AtomicLoadAnd16
729 { 327, 3, 1, 2, 0, 0, 0, 184, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #327 = AtomicLoadAdd8
730 { 326, 3, 1, 2, 0, 0, 0, 181, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #326 = AtomicLoadAdd16
731 { 325, 2, 1, 2, 0, 0, 0, 179, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #325 = AtomicLoad8
732 { 324, 2, 1, 2, 0, 0, 0, 177, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #324 = AtomicLoad16
733 { 323, 0, 0, 2, 0, 0, 0, 1, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #323 = AtomicFence
734 { 322, 3, 1, 2, 0, 0, 1, 174, AVRImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #322 = Asr8
735 { 321, 5, 2, 2, 0, 0, 1, 169, AVRImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #321 = Asr32
736 { 320, 3, 1, 2, 0, 0, 1, 166, AVRImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #320 = Asr16
737 { 319, 2, 1, 2, 0, 0, 1, 161, AVRImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #319 = ASRWRd
738 { 318, 3, 1, 2, 0, 0, 1, 163, AVRImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #318 = ASRWNRd
739 { 317, 2, 1, 2, 0, 0, 1, 161, AVRImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #317 = ASRWLoRd
740 { 316, 3, 1, 2, 0, 0, 1, 158, AVRImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #316 = ASRBNRd
741 { 315, 3, 1, 2, 0, 0, 1, 152, AVRImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #315 = ANDWRdRr
742 { 314, 3, 1, 2, 0, 0, 1, 155, AVRImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #314 = ANDIWRdK
743 { 313, 2, 0, 2, 0, 1, 1, 21, AVRImpOpBase + 6, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #313 = ADJCALLSTACKUP
744 { 312, 2, 0, 2, 0, 1, 2, 21, AVRImpOpBase + 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #312 = ADJCALLSTACKDOWN
745 { 311, 3, 1, 2, 0, 0, 1, 152, AVRImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #311 = ADDWRdRr
746 { 310, 3, 1, 2, 0, 1, 1, 152, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #310 = ADCWRdRr
747 { 309, 4, 1, 0, 0, 0, 0, 148, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #309 = G_UBFX
748 { 308, 4, 1, 0, 0, 0, 0, 148, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #308 = G_SBFX
749 { 307, 2, 1, 0, 0, 0, 0, 61, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #307 = G_VECREDUCE_UMIN
750 { 306, 2, 1, 0, 0, 0, 0, 61, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #306 = G_VECREDUCE_UMAX
751 { 305, 2, 1, 0, 0, 0, 0, 61, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #305 = G_VECREDUCE_SMIN
752 { 304, 2, 1, 0, 0, 0, 0, 61, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #304 = G_VECREDUCE_SMAX
753 { 303, 2, 1, 0, 0, 0, 0, 61, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #303 = G_VECREDUCE_XOR
754 { 302, 2, 1, 0, 0, 0, 0, 61, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #302 = G_VECREDUCE_OR
755 { 301, 2, 1, 0, 0, 0, 0, 61, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #301 = G_VECREDUCE_AND
756 { 300, 2, 1, 0, 0, 0, 0, 61, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #300 = G_VECREDUCE_MUL
757 { 299, 2, 1, 0, 0, 0, 0, 61, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #299 = G_VECREDUCE_ADD
758 { 298, 2, 1, 0, 0, 0, 0, 61, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #298 = G_VECREDUCE_FMINIMUM
759 { 297, 2, 1, 0, 0, 0, 0, 61, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #297 = G_VECREDUCE_FMAXIMUM
760 { 296, 2, 1, 0, 0, 0, 0, 61, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #296 = G_VECREDUCE_FMIN
761 { 295, 2, 1, 0, 0, 0, 0, 61, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #295 = G_VECREDUCE_FMAX
762 { 294, 2, 1, 0, 0, 0, 0, 61, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #294 = G_VECREDUCE_FMUL
763 { 293, 2, 1, 0, 0, 0, 0, 61, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #293 = G_VECREDUCE_FADD
764 { 292, 3, 1, 0, 0, 0, 0, 131, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #292 = G_VECREDUCE_SEQ_FMUL
765 { 291, 3, 1, 0, 0, 0, 0, 131, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #291 = G_VECREDUCE_SEQ_FADD
766 { 290, 1, 0, 0, 0, 0, 0, 1, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #290 = G_UBSANTRAP
767 { 289, 0, 0, 0, 0, 0, 0, 1, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #289 = G_DEBUGTRAP
768 { 288, 0, 0, 0, 0, 0, 0, 1, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #288 = G_TRAP
769 { 287, 3, 0, 0, 0, 0, 0, 58, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #287 = G_BZERO
770 { 286, 4, 0, 0, 0, 0, 0, 144, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #286 = G_MEMSET
771 { 285, 4, 0, 0, 0, 0, 0, 144, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #285 = G_MEMMOVE
772 { 284, 3, 0, 0, 0, 0, 0, 131, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #284 = G_MEMCPY_INLINE
773 { 283, 4, 0, 0, 0, 0, 0, 144, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #283 = G_MEMCPY
774 { 282, 2, 0, 0, 0, 0, 0, 142, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #282 = G_WRITE_REGISTER
775 { 281, 2, 1, 0, 0, 0, 0, 51, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #281 = G_READ_REGISTER
776 { 280, 3, 1, 0, 0, 0, 0, 101, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #280 = G_STRICT_FLDEXP
777 { 279, 2, 1, 0, 0, 0, 0, 67, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #279 = G_STRICT_FSQRT
778 { 278, 4, 1, 0, 0, 0, 0, 46, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #278 = G_STRICT_FMA
779 { 277, 3, 1, 0, 0, 0, 0, 43, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #277 = G_STRICT_FREM
780 { 276, 3, 1, 0, 0, 0, 0, 43, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #276 = G_STRICT_FDIV
781 { 275, 3, 1, 0, 0, 0, 0, 43, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #275 = G_STRICT_FMUL
782 { 274, 3, 1, 0, 0, 0, 0, 43, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #274 = G_STRICT_FSUB
783 { 273, 3, 1, 0, 0, 0, 0, 43, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #273 = G_STRICT_FADD
784 { 272, 1, 0, 0, 0, 0, 0, 50, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #272 = G_STACKRESTORE
785 { 271, 1, 1, 0, 0, 0, 0, 50, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #271 = G_STACKSAVE
786 { 270, 3, 1, 0, 0, 0, 0, 69, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #270 = G_DYN_STACKALLOC
787 { 269, 2, 1, 0, 0, 0, 0, 51, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #269 = G_JUMP_TABLE
788 { 268, 2, 1, 0, 0, 0, 0, 51, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #268 = G_BLOCK_ADDR
789 { 267, 2, 1, 0, 0, 0, 0, 61, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #267 = G_ADDRSPACE_CAST
790 { 266, 2, 1, 0, 0, 0, 0, 67, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #266 = G_FNEARBYINT
791 { 265, 2, 1, 0, 0, 0, 0, 67, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #265 = G_FRINT
792 { 264, 2, 1, 0, 0, 0, 0, 67, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #264 = G_FFLOOR
793 { 263, 2, 1, 0, 0, 0, 0, 67, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #263 = G_FSQRT
794 { 262, 2, 1, 0, 0, 0, 0, 67, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #262 = G_FTANH
795 { 261, 2, 1, 0, 0, 0, 0, 67, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #261 = G_FSINH
796 { 260, 2, 1, 0, 0, 0, 0, 67, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #260 = G_FCOSH
797 { 259, 3, 1, 0, 0, 0, 0, 43, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #259 = G_FATAN2
798 { 258, 2, 1, 0, 0, 0, 0, 67, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #258 = G_FATAN
799 { 257, 2, 1, 0, 0, 0, 0, 67, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #257 = G_FASIN
800 { 256, 2, 1, 0, 0, 0, 0, 67, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #256 = G_FACOS
801 { 255, 2, 1, 0, 0, 0, 0, 67, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #255 = G_FTAN
802 { 254, 3, 2, 0, 0, 0, 0, 43, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #254 = G_FSINCOS
803 { 253, 2, 1, 0, 0, 0, 0, 67, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #253 = G_FSIN
804 { 252, 2, 1, 0, 0, 0, 0, 67, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #252 = G_FCOS
805 { 251, 2, 1, 0, 0, 0, 0, 67, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #251 = G_FCEIL
806 { 250, 2, 1, 0, 0, 0, 0, 67, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #250 = G_BITREVERSE
807 { 249, 2, 1, 0, 0, 0, 0, 67, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #249 = G_BSWAP
808 { 248, 2, 1, 0, 0, 0, 0, 61, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #248 = G_CTPOP
809 { 247, 2, 1, 0, 0, 0, 0, 61, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #247 = G_CTLZ_ZERO_UNDEF
810 { 246, 2, 1, 0, 0, 0, 0, 61, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #246 = G_CTLZ
811 { 245, 2, 1, 0, 0, 0, 0, 61, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #245 = G_CTTZ_ZERO_UNDEF
812 { 244, 2, 1, 0, 0, 0, 0, 61, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #244 = G_CTTZ
813 { 243, 4, 1, 0, 0, 0, 0, 138, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #243 = G_VECTOR_COMPRESS
814 { 242, 2, 1, 0, 0, 0, 0, 51, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #242 = G_STEP_VECTOR
815 { 241, 2, 1, 0, 0, 0, 0, 61, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #241 = G_SPLAT_VECTOR
816 { 240, 4, 1, 0, 0, 0, 0, 134, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #240 = G_SHUFFLE_VECTOR
817 { 239, 3, 1, 0, 0, 0, 0, 131, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #239 = G_EXTRACT_VECTOR_ELT
818 { 238, 4, 1, 0, 0, 0, 0, 127, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #238 = G_INSERT_VECTOR_ELT
819 { 237, 3, 1, 0, 0, 0, 0, 58, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #237 = G_EXTRACT_SUBVECTOR
820 { 236, 4, 1, 0, 0, 0, 0, 63, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #236 = G_INSERT_SUBVECTOR
821 { 235, 2, 1, 0, 0, 0, 0, 51, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #235 = G_VSCALE
822 { 234, 3, 0, 0, 0, 0, 0, 124, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #234 = G_BRJT
823 { 233, 1, 0, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #233 = G_BR
824 { 232, 2, 1, 0, 0, 0, 0, 61, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #232 = G_LLROUND
825 { 231, 2, 1, 0, 0, 0, 0, 61, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #231 = G_LROUND
826 { 230, 2, 1, 0, 0, 0, 0, 67, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #230 = G_ABS
827 { 229, 3, 1, 0, 0, 0, 0, 43, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #229 = G_UMAX
828 { 228, 3, 1, 0, 0, 0, 0, 43, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #228 = G_UMIN
829 { 227, 3, 1, 0, 0, 0, 0, 43, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #227 = G_SMAX
830 { 226, 3, 1, 0, 0, 0, 0, 43, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #226 = G_SMIN
831 { 225, 3, 1, 0, 0, 0, 0, 101, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #225 = G_PTRMASK
832 { 224, 3, 1, 0, 0, 0, 0, 101, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #224 = G_PTR_ADD
833 { 223, 0, 0, 0, 0, 0, 0, 1, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #223 = G_RESET_FPMODE
834 { 222, 1, 0, 0, 0, 0, 0, 50, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #222 = G_SET_FPMODE
835 { 221, 1, 1, 0, 0, 0, 0, 50, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #221 = G_GET_FPMODE
836 { 220, 0, 0, 0, 0, 0, 0, 1, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #220 = G_RESET_FPENV
837 { 219, 1, 0, 0, 0, 0, 0, 50, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #219 = G_SET_FPENV
838 { 218, 1, 1, 0, 0, 0, 0, 50, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #218 = G_GET_FPENV
839 { 217, 3, 1, 0, 0, 0, 0, 43, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #217 = G_FMAXIMUMNUM
840 { 216, 3, 1, 0, 0, 0, 0, 43, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #216 = G_FMINIMUMNUM
841 { 215, 3, 1, 0, 0, 0, 0, 43, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #215 = G_FMAXIMUM
842 { 214, 3, 1, 0, 0, 0, 0, 43, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #214 = G_FMINIMUM
843 { 213, 3, 1, 0, 0, 0, 0, 43, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #213 = G_FMAXNUM_IEEE
844 { 212, 3, 1, 0, 0, 0, 0, 43, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #212 = G_FMINNUM_IEEE
845 { 211, 3, 1, 0, 0, 0, 0, 43, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #211 = G_FMAXNUM
846 { 210, 3, 1, 0, 0, 0, 0, 43, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #210 = G_FMINNUM
847 { 209, 2, 1, 0, 0, 0, 0, 67, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #209 = G_FCANONICALIZE
848 { 208, 3, 1, 0, 0, 0, 0, 98, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #208 = G_IS_FPCLASS
849 { 207, 3, 1, 0, 0, 0, 0, 101, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #207 = G_FCOPYSIGN
850 { 206, 2, 1, 0, 0, 0, 0, 67, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #206 = G_FABS
851 { 205, 2, 1, 0, 0, 0, 0, 61, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #205 = G_FPTOUI_SAT
852 { 204, 2, 1, 0, 0, 0, 0, 61, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #204 = G_FPTOSI_SAT
853 { 203, 2, 1, 0, 0, 0, 0, 61, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #203 = G_UITOFP
854 { 202, 2, 1, 0, 0, 0, 0, 61, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #202 = G_SITOFP
855 { 201, 2, 1, 0, 0, 0, 0, 61, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #201 = G_FPTOUI
856 { 200, 2, 1, 0, 0, 0, 0, 61, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #200 = G_FPTOSI
857 { 199, 2, 1, 0, 0, 0, 0, 61, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #199 = G_FPTRUNC
858 { 198, 2, 1, 0, 0, 0, 0, 61, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #198 = G_FPEXT
859 { 197, 2, 1, 0, 0, 0, 0, 67, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #197 = G_FNEG
860 { 196, 3, 2, 0, 0, 0, 0, 91, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #196 = G_FFREXP
861 { 195, 3, 1, 0, 0, 0, 0, 101, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #195 = G_FLDEXP
862 { 194, 2, 1, 0, 0, 0, 0, 67, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #194 = G_FLOG10
863 { 193, 2, 1, 0, 0, 0, 0, 67, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #193 = G_FLOG2
864 { 192, 2, 1, 0, 0, 0, 0, 67, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #192 = G_FLOG
865 { 191, 2, 1, 0, 0, 0, 0, 67, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #191 = G_FEXP10
866 { 190, 2, 1, 0, 0, 0, 0, 67, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #190 = G_FEXP2
867 { 189, 2, 1, 0, 0, 0, 0, 67, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #189 = G_FEXP
868 { 188, 3, 1, 0, 0, 0, 0, 101, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #188 = G_FPOWI
869 { 187, 3, 1, 0, 0, 0, 0, 43, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #187 = G_FPOW
870 { 186, 3, 1, 0, 0, 0, 0, 43, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #186 = G_FREM
871 { 185, 3, 1, 0, 0, 0, 0, 43, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #185 = G_FDIV
872 { 184, 4, 1, 0, 0, 0, 0, 46, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #184 = G_FMAD
873 { 183, 4, 1, 0, 0, 0, 0, 46, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #183 = G_FMA
874 { 182, 3, 1, 0, 0, 0, 0, 43, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #182 = G_FMUL
875 { 181, 3, 1, 0, 0, 0, 0, 43, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #181 = G_FSUB
876 { 180, 3, 1, 0, 0, 0, 0, 43, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #180 = G_FADD
877 { 179, 4, 1, 0, 0, 0, 0, 120, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #179 = G_UDIVFIXSAT
878 { 178, 4, 1, 0, 0, 0, 0, 120, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #178 = G_SDIVFIXSAT
879 { 177, 4, 1, 0, 0, 0, 0, 120, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #177 = G_UDIVFIX
880 { 176, 4, 1, 0, 0, 0, 0, 120, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #176 = G_SDIVFIX
881 { 175, 4, 1, 0, 0, 0, 0, 120, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #175 = G_UMULFIXSAT
882 { 174, 4, 1, 0, 0, 0, 0, 120, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #174 = G_SMULFIXSAT
883 { 173, 4, 1, 0, 0, 0, 0, 120, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #173 = G_UMULFIX
884 { 172, 4, 1, 0, 0, 0, 0, 120, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #172 = G_SMULFIX
885 { 171, 3, 1, 0, 0, 0, 0, 101, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #171 = G_SSHLSAT
886 { 170, 3, 1, 0, 0, 0, 0, 101, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #170 = G_USHLSAT
887 { 169, 3, 1, 0, 0, 0, 0, 43, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #169 = G_SSUBSAT
888 { 168, 3, 1, 0, 0, 0, 0, 43, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #168 = G_USUBSAT
889 { 167, 3, 1, 0, 0, 0, 0, 43, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #167 = G_SADDSAT
890 { 166, 3, 1, 0, 0, 0, 0, 43, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #166 = G_UADDSAT
891 { 165, 3, 1, 0, 0, 0, 0, 43, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #165 = G_SMULH
892 { 164, 3, 1, 0, 0, 0, 0, 43, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #164 = G_UMULH
893 { 163, 4, 2, 0, 0, 0, 0, 87, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #163 = G_SMULO
894 { 162, 4, 2, 0, 0, 0, 0, 87, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #162 = G_UMULO
895 { 161, 5, 2, 0, 0, 0, 0, 115, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #161 = G_SSUBE
896 { 160, 4, 2, 0, 0, 0, 0, 87, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #160 = G_SSUBO
897 { 159, 5, 2, 0, 0, 0, 0, 115, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #159 = G_SADDE
898 { 158, 4, 2, 0, 0, 0, 0, 87, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #158 = G_SADDO
899 { 157, 5, 2, 0, 0, 0, 0, 115, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #157 = G_USUBE
900 { 156, 4, 2, 0, 0, 0, 0, 87, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #156 = G_USUBO
901 { 155, 5, 2, 0, 0, 0, 0, 115, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #155 = G_UADDE
902 { 154, 4, 2, 0, 0, 0, 0, 87, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #154 = G_UADDO
903 { 153, 4, 1, 0, 0, 0, 0, 87, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #153 = G_SELECT
904 { 152, 3, 1, 0, 0, 0, 0, 112, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #152 = G_UCMP
905 { 151, 3, 1, 0, 0, 0, 0, 112, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #151 = G_SCMP
906 { 150, 4, 1, 0, 0, 0, 0, 108, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #150 = G_FCMP
907 { 149, 4, 1, 0, 0, 0, 0, 108, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #149 = G_ICMP
908 { 148, 3, 1, 0, 0, 0, 0, 101, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #148 = G_ROTL
909 { 147, 3, 1, 0, 0, 0, 0, 101, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #147 = G_ROTR
910 { 146, 4, 1, 0, 0, 0, 0, 104, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #146 = G_FSHR
911 { 145, 4, 1, 0, 0, 0, 0, 104, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #145 = G_FSHL
912 { 144, 3, 1, 0, 0, 0, 0, 101, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #144 = G_ASHR
913 { 143, 3, 1, 0, 0, 0, 0, 101, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #143 = G_LSHR
914 { 142, 3, 1, 0, 0, 0, 0, 101, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #142 = G_SHL
915 { 141, 2, 1, 0, 0, 0, 0, 61, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #141 = G_ZEXT
916 { 140, 3, 1, 0, 0, 0, 0, 40, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #140 = G_SEXT_INREG
917 { 139, 2, 1, 0, 0, 0, 0, 61, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #139 = G_SEXT
918 { 138, 3, 1, 0, 0, 0, 0, 98, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #138 = G_VAARG
919 { 137, 1, 0, 0, 0, 0, 0, 50, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #137 = G_VASTART
920 { 136, 2, 1, 0, 0, 0, 0, 51, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #136 = G_FCONSTANT
921 { 135, 2, 1, 0, 0, 0, 0, 51, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #135 = G_CONSTANT
922 { 134, 2, 1, 0, 0, 0, 0, 61, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #134 = G_TRUNC
923 { 133, 2, 1, 0, 0, 0, 0, 61, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #133 = G_ANYEXT
924 { 132, 1, 0, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #132 = G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
925 { 131, 1, 0, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #131 = G_INTRINSIC_CONVERGENT
926 { 130, 1, 0, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #130 = G_INTRINSIC_W_SIDE_EFFECTS
927 { 129, 1, 0, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #129 = G_INTRINSIC
928 { 128, 0, 0, 0, 0, 0, 0, 1, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #128 = G_INVOKE_REGION_START
929 { 127, 1, 0, 0, 0, 0, 0, 50, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #127 = G_BRINDIRECT
930 { 126, 2, 0, 0, 0, 0, 0, 51, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #126 = G_BRCOND
931 { 125, 4, 0, 0, 0, 0, 0, 94, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #125 = G_PREFETCH
932 { 124, 2, 0, 0, 0, 0, 0, 21, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #124 = G_FENCE
933 { 123, 3, 1, 0, 0, 0, 0, 91, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #123 = G_ATOMICRMW_USUB_SAT
934 { 122, 3, 1, 0, 0, 0, 0, 91, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #122 = G_ATOMICRMW_USUB_COND
935 { 121, 3, 1, 0, 0, 0, 0, 91, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #121 = G_ATOMICRMW_UDEC_WRAP
936 { 120, 3, 1, 0, 0, 0, 0, 91, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #120 = G_ATOMICRMW_UINC_WRAP
937 { 119, 3, 1, 0, 0, 0, 0, 91, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #119 = G_ATOMICRMW_FMINIMUM
938 { 118, 3, 1, 0, 0, 0, 0, 91, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #118 = G_ATOMICRMW_FMAXIMUM
939 { 117, 3, 1, 0, 0, 0, 0, 91, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #117 = G_ATOMICRMW_FMIN
940 { 116, 3, 1, 0, 0, 0, 0, 91, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #116 = G_ATOMICRMW_FMAX
941 { 115, 3, 1, 0, 0, 0, 0, 91, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #115 = G_ATOMICRMW_FSUB
942 { 114, 3, 1, 0, 0, 0, 0, 91, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #114 = G_ATOMICRMW_FADD
943 { 113, 3, 1, 0, 0, 0, 0, 91, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #113 = G_ATOMICRMW_UMIN
944 { 112, 3, 1, 0, 0, 0, 0, 91, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #112 = G_ATOMICRMW_UMAX
945 { 111, 3, 1, 0, 0, 0, 0, 91, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #111 = G_ATOMICRMW_MIN
946 { 110, 3, 1, 0, 0, 0, 0, 91, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #110 = G_ATOMICRMW_MAX
947 { 109, 3, 1, 0, 0, 0, 0, 91, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #109 = G_ATOMICRMW_XOR
948 { 108, 3, 1, 0, 0, 0, 0, 91, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #108 = G_ATOMICRMW_OR
949 { 107, 3, 1, 0, 0, 0, 0, 91, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #107 = G_ATOMICRMW_NAND
950 { 106, 3, 1, 0, 0, 0, 0, 91, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #106 = G_ATOMICRMW_AND
951 { 105, 3, 1, 0, 0, 0, 0, 91, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #105 = G_ATOMICRMW_SUB
952 { 104, 3, 1, 0, 0, 0, 0, 91, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #104 = G_ATOMICRMW_ADD
953 { 103, 3, 1, 0, 0, 0, 0, 91, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #103 = G_ATOMICRMW_XCHG
954 { 102, 4, 1, 0, 0, 0, 0, 87, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #102 = G_ATOMIC_CMPXCHG
955 { 101, 5, 2, 0, 0, 0, 0, 82, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #101 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
956 { 100, 5, 1, 0, 0, 0, 0, 77, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #100 = G_INDEXED_STORE
957 { 99, 2, 0, 0, 0, 0, 0, 61, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #99 = G_STORE
958 { 98, 5, 2, 0, 0, 0, 0, 72, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #98 = G_INDEXED_ZEXTLOAD
959 { 97, 5, 2, 0, 0, 0, 0, 72, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #97 = G_INDEXED_SEXTLOAD
960 { 96, 5, 2, 0, 0, 0, 0, 72, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #96 = G_INDEXED_LOAD
961 { 95, 2, 1, 0, 0, 0, 0, 61, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #95 = G_ZEXTLOAD
962 { 94, 2, 1, 0, 0, 0, 0, 61, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #94 = G_SEXTLOAD
963 { 93, 2, 1, 0, 0, 0, 0, 61, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #93 = G_LOAD
964 { 92, 1, 1, 0, 0, 0, 0, 50, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #92 = G_READSTEADYCOUNTER
965 { 91, 1, 1, 0, 0, 0, 0, 50, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #91 = G_READCYCLECOUNTER
966 { 90, 2, 1, 0, 0, 0, 0, 67, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #90 = G_INTRINSIC_ROUNDEVEN
967 { 89, 2, 1, 0, 0, 0, 0, 61, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #89 = G_INTRINSIC_LLRINT
968 { 88, 2, 1, 0, 0, 0, 0, 61, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #88 = G_INTRINSIC_LRINT
969 { 87, 2, 1, 0, 0, 0, 0, 67, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #87 = G_INTRINSIC_ROUND
970 { 86, 2, 1, 0, 0, 0, 0, 67, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #86 = G_INTRINSIC_TRUNC
971 { 85, 3, 1, 0, 0, 0, 0, 69, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #85 = G_INTRINSIC_FPTRUNC_ROUND
972 { 84, 2, 1, 0, 0, 0, 0, 67, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #84 = G_CONSTANT_FOLD_BARRIER
973 { 83, 2, 1, 0, 0, 0, 0, 67, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #83 = G_FREEZE
974 { 82, 2, 1, 0, 0, 0, 0, 61, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #82 = G_BITCAST
975 { 81, 2, 1, 0, 0, 0, 0, 61, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #81 = G_INTTOPTR
976 { 80, 2, 1, 0, 0, 0, 0, 61, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #80 = G_PTRTOINT
977 { 79, 2, 1, 0, 0, 0, 0, 61, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #79 = G_CONCAT_VECTORS
978 { 78, 2, 1, 0, 0, 0, 0, 61, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #78 = G_BUILD_VECTOR_TRUNC
979 { 77, 2, 1, 0, 0, 0, 0, 61, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #77 = G_BUILD_VECTOR
980 { 76, 2, 1, 0, 0, 0, 0, 61, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #76 = G_MERGE_VALUES
981 { 75, 4, 1, 0, 0, 0, 0, 63, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #75 = G_INSERT
982 { 74, 2, 1, 0, 0, 0, 0, 61, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #74 = G_UNMERGE_VALUES
983 { 73, 3, 1, 0, 0, 0, 0, 58, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #73 = G_EXTRACT
984 { 72, 2, 1, 0, 0, 0, 0, 51, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #72 = G_CONSTANT_POOL
985 { 71, 5, 1, 0, 0, 0, 0, 53, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #71 = G_PTRAUTH_GLOBAL_VALUE
986 { 70, 2, 1, 0, 0, 0, 0, 51, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #70 = G_GLOBAL_VALUE
987 { 69, 2, 1, 0, 0, 0, 0, 51, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #69 = G_FRAME_INDEX
988 { 68, 1, 1, 0, 0, 0, 0, 50, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #68 = G_PHI
989 { 67, 1, 1, 0, 0, 0, 0, 50, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #67 = G_IMPLICIT_DEF
990 { 66, 3, 1, 0, 0, 0, 0, 43, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #66 = G_ABDU
991 { 65, 3, 1, 0, 0, 0, 0, 43, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #65 = G_ABDS
992 { 64, 3, 1, 0, 0, 0, 0, 43, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #64 = G_XOR
993 { 63, 3, 1, 0, 0, 0, 0, 43, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #63 = G_OR
994 { 62, 3, 1, 0, 0, 0, 0, 43, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #62 = G_AND
995 { 61, 4, 2, 0, 0, 0, 0, 46, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #61 = G_UDIVREM
996 { 60, 4, 2, 0, 0, 0, 0, 46, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #60 = G_SDIVREM
997 { 59, 3, 1, 0, 0, 0, 0, 43, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #59 = G_UREM
998 { 58, 3, 1, 0, 0, 0, 0, 43, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #58 = G_SREM
999 { 57, 3, 1, 0, 0, 0, 0, 43, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #57 = G_UDIV
1000 { 56, 3, 1, 0, 0, 0, 0, 43, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #56 = G_SDIV
1001 { 55, 3, 1, 0, 0, 0, 0, 43, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #55 = G_MUL
1002 { 54, 3, 1, 0, 0, 0, 0, 43, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #54 = G_SUB
1003 { 53, 3, 1, 0, 0, 0, 0, 43, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #53 = G_ADD
1004 { 52, 3, 1, 0, 0, 0, 0, 40, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #52 = G_ASSERT_ALIGN
1005 { 51, 3, 1, 0, 0, 0, 0, 40, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #51 = G_ASSERT_ZEXT
1006 { 50, 3, 1, 0, 0, 0, 0, 40, AVRImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #50 = G_ASSERT_SEXT
1007 { 49, 1, 0, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #49 = CONVERGENCECTRL_GLUE
1008 { 48, 2, 1, 0, 0, 0, 0, 13, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #48 = CONVERGENCECTRL_LOOP
1009 { 47, 1, 1, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #47 = CONVERGENCECTRL_ANCHOR
1010 { 46, 1, 1, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #46 = CONVERGENCECTRL_ENTRY
1011 { 45, 1, 0, 0, 0, 0, 0, 1, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #45 = JUMP_TABLE_DEBUG_INFO
1012 { 44, 0, 0, 0, 0, 0, 0, 1, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #44 = MEMBARRIER
1013 { 43, 0, 0, 0, 0, 0, 0, 1, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #43 = FAKE_USE
1014 { 42, 0, 0, 0, 0, 0, 0, 1, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #42 = ICALL_BRANCH_FUNNEL
1015 { 41, 3, 0, 0, 0, 0, 0, 37, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #41 = PATCHABLE_TYPED_EVENT_CALL
1016 { 40, 2, 0, 0, 0, 0, 0, 35, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #40 = PATCHABLE_EVENT_CALL
1017 { 39, 0, 0, 0, 0, 0, 0, 1, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #39 = PATCHABLE_TAIL_CALL
1018 { 38, 0, 0, 0, 0, 0, 0, 1, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #38 = PATCHABLE_FUNCTION_EXIT
1019 { 37, 0, 0, 0, 0, 0, 0, 1, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #37 = PATCHABLE_RET
1020 { 36, 0, 0, 0, 0, 0, 0, 1, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #36 = PATCHABLE_FUNCTION_ENTER
1021 { 35, 0, 0, 0, 0, 0, 0, 1, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #35 = PATCHABLE_OP
1022 { 34, 1, 1, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #34 = FAULTING_OP
1023 { 33, 2, 0, 0, 0, 0, 0, 33, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #33 = LOCAL_ESCAPE
1024 { 32, 0, 0, 0, 0, 0, 0, 1, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #32 = STATEPOINT
1025 { 31, 3, 1, 0, 0, 0, 0, 30, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #31 = PREALLOCATED_ARG
1026 { 30, 1, 0, 0, 0, 0, 0, 1, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #30 = PREALLOCATED_SETUP
1027 { 29, 1, 1, 0, 0, 0, 0, 29, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #29 = LOAD_STACK_GUARD
1028 { 28, 6, 1, 0, 0, 0, 0, 23, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #28 = PATCHPOINT
1029 { 27, 0, 0, 0, 0, 0, 0, 1, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #27 = FENTRY_CALL
1030 { 26, 2, 0, 0, 0, 0, 0, 21, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #26 = STACKMAP
1031 { 25, 2, 1, 0, 0, 0, 0, 19, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #25 = ARITH_FENCE
1032 { 24, 4, 0, 0, 0, 0, 0, 15, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #24 = PSEUDO_PROBE
1033 { 23, 1, 0, 0, 0, 0, 0, 1, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #23 = LIFETIME_END
1034 { 22, 1, 0, 0, 0, 0, 0, 1, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #22 = LIFETIME_START
1035 { 21, 0, 0, 0, 0, 0, 0, 1, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #21 = BUNDLE
1036 { 20, 2, 1, 0, 0, 0, 0, 13, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #20 = COPY
1037 { 19, 2, 1, 0, 0, 0, 0, 13, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #19 = REG_SEQUENCE
1038 { 18, 1, 0, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #18 = DBG_LABEL
1039 { 17, 0, 0, 0, 0, 0, 0, 1, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #17 = DBG_PHI
1040 { 16, 0, 0, 0, 0, 0, 0, 1, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #16 = DBG_INSTR_REF
1041 { 15, 0, 0, 0, 0, 0, 0, 1, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #15 = DBG_VALUE_LIST
1042 { 14, 0, 0, 0, 0, 0, 0, 1, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #14 = DBG_VALUE
1043 { 13, 3, 1, 0, 0, 0, 0, 2, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #13 = COPY_TO_REGCLASS
1044 { 12, 4, 1, 0, 0, 0, 0, 9, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #12 = SUBREG_TO_REG
1045 { 11, 1, 1, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #11 = INIT_UNDEF
1046 { 10, 1, 1, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #10 = IMPLICIT_DEF
1047 { 9, 4, 1, 0, 0, 0, 0, 5, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #9 = INSERT_SUBREG
1048 { 8, 3, 1, 0, 0, 0, 0, 2, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #8 = EXTRACT_SUBREG
1049 { 7, 0, 0, 0, 0, 0, 0, 1, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #7 = KILL
1050 { 6, 1, 0, 0, 0, 0, 0, 1, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #6 = ANNOTATION_LABEL
1051 { 5, 1, 0, 0, 0, 0, 0, 1, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #5 = GC_LABEL
1052 { 4, 1, 0, 0, 0, 0, 0, 1, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #4 = EH_LABEL
1053 { 3, 1, 0, 0, 0, 0, 0, 1, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #3 = CFI_INSTRUCTION
1054 { 2, 0, 0, 0, 0, 0, 0, 1, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #2 = INLINEASM_BR
1055 { 1, 0, 0, 0, 0, 0, 0, 1, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1 = INLINEASM
1056 { 0, 1, 1, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #0 = PHI
1057 }, {
1058 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1059 /* 1 */
1060 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1061 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1062 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1063 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1064 /* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1065 /* 15 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1066 /* 19 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
1067 /* 21 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1068 /* 23 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1069 /* 29 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
1070 /* 30 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1071 /* 33 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1072 /* 35 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1073 /* 37 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1074 /* 40 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1075 /* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1076 /* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1077 /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1078 /* 51 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1079 /* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1080 /* 58 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1081 /* 61 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1082 /* 63 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1083 /* 67 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1084 /* 69 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1085 /* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1086 /* 77 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1087 /* 82 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1088 /* 87 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1089 /* 91 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1090 /* 94 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1091 /* 98 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1092 /* 101 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1093 /* 104 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1094 /* 108 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1095 /* 112 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1096 /* 115 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1097 /* 120 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1098 /* 124 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1099 /* 127 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1100 /* 131 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1101 /* 134 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1102 /* 138 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1103 /* 142 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1104 /* 144 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1105 /* 148 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1106 /* 152 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1107 /* 155 */ { AVR::DLDREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DLDREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1108 /* 158 */ { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1109 /* 161 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1110 /* 163 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1111 /* 166 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1112 /* 169 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1113 /* 174 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1114 /* 177 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1115 /* 179 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1116 /* 181 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1117 /* 184 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1118 /* 187 */ { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1119 /* 189 */ { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1120 /* 191 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1121 /* 193 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1122 /* 194 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::ZREGRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1123 /* 197 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { AVR::ZREGRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1124 /* 200 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::ZREGRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1125 /* 203 */ { AVR::DLDREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DLDREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1126 /* 206 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1127 /* 208 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1128 /* 211 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1129 /* 214 */ { AVR::DLDREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1130 /* 216 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1131 /* 218 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1132 /* 220 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) },
1133 /* 223 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::ZREGRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1134 /* 225 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { AVR::ZREGRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1135 /* 227 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::ZREGRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1136 /* 229 */ { AVR::DLDREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1137 /* 232 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1138 /* 235 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1139 /* 237 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1140 /* 238 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1141 /* 240 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1142 /* 242 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPRSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1143 /* 244 */ { AVR::GPRSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1144 /* 246 */ { AVR::GPRSPRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1145 /* 249 */ { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1146 /* 252 */ { AVR::GPRSPRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1147 /* 255 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1148 /* 257 */ { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1149 /* 261 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1150 /* 265 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1151 /* 269 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1152 /* 272 */ { AVR::IWREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::IWREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1153 /* 275 */ { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1154 /* 278 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1155 /* 281 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1156 /* 283 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1157 /* 285 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1158 /* 287 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1159 /* 289 */ { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1160 /* 291 */ { AVR::LD8loRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::LD8loRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1161 /* 293 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1162 /* 295 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1163 /* 298 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) },
1164 /* 301 */ { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1165 /* 303 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1166 /* 305 */ { AVR::ZREGRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1167 /* 306 */ { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1168 /* 309 */ { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1169 /* 313 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1170 }, {
1171 /* 0 */
1172 /* 0 */ AVR::SREG, AVR::SREG,
1173 /* 2 */ AVR::SREG,
1174 /* 3 */ AVR::SP, AVR::SP, AVR::SREG,
1175 /* 6 */ AVR::SP, AVR::R31R30,
1176 /* 8 */ AVR::R0,
1177 /* 9 */ AVR::R31R30,
1178 /* 10 */ AVR::SP, AVR::SP,
1179 /* 12 */ AVR::R1, AVR::SREG,
1180 /* 14 */ AVR::R17, AVR::SREG,
1181 /* 16 */ AVR::SP,
1182 /* 17 */ AVR::R15, AVR::R14, AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8, AVR::R7, AVR::R6, AVR::R5, AVR::R4, AVR::R3, AVR::R2, AVR::R1, AVR::R0,
1183 /* 33 */ AVR::R31R30, AVR::R0,
1184 /* 35 */ AVR::R1, AVR::R0, AVR::SREG,
1185 /* 38 */ AVR::R31R30, AVR::R1, AVR::R0,
1186 /* 41 */ AVR::R1, AVR::R0, AVR::R31R30,
1187 }
1188};
1189
1190
1191#ifdef __GNUC__
1192#pragma GCC diagnostic push
1193#pragma GCC diagnostic ignored "-Woverlength-strings"
1194#endif
1195extern const char AVRInstrNameData[] = {
1196 /* 0 */ "G_FLOG10\000"
1197 /* 9 */ "G_FEXP10\000"
1198 /* 18 */ "ROLBRdR1\000"
1199 /* 27 */ "Lsl32\000"
1200 /* 33 */ "Asr32\000"
1201 /* 39 */ "Lsr32\000"
1202 /* 45 */ "G_FLOG2\000"
1203 /* 53 */ "G_FATAN2\000"
1204 /* 62 */ "G_FEXP2\000"
1205 /* 70 */ "AtomicLoadSub16\000"
1206 /* 86 */ "AtomicLoad16\000"
1207 /* 99 */ "AtomicLoadAdd16\000"
1208 /* 115 */ "AtomicLoadAnd16\000"
1209 /* 131 */ "AtomicStore16\000"
1210 /* 145 */ "Rol16\000"
1211 /* 151 */ "Lsl16\000"
1212 /* 157 */ "AtomicLoadOr16\000"
1213 /* 172 */ "Ror16\000"
1214 /* 178 */ "AtomicLoadXor16\000"
1215 /* 194 */ "Asr16\000"
1216 /* 200 */ "Lsr16\000"
1217 /* 206 */ "Select16\000"
1218 /* 215 */ "ROLBRdR17\000"
1219 /* 225 */ "AtomicLoadSub8\000"
1220 /* 240 */ "AtomicLoad8\000"
1221 /* 252 */ "AtomicLoadAdd8\000"
1222 /* 267 */ "AtomicLoadAnd8\000"
1223 /* 282 */ "AtomicStore8\000"
1224 /* 295 */ "Rol8\000"
1225 /* 300 */ "Lsl8\000"
1226 /* 305 */ "AtomicLoadOr8\000"
1227 /* 319 */ "Ror8\000"
1228 /* 324 */ "AtomicLoadXor8\000"
1229 /* 339 */ "Asr8\000"
1230 /* 344 */ "Lsr8\000"
1231 /* 349 */ "Select8\000"
1232 /* 357 */ "G_FMA\000"
1233 /* 363 */ "G_STRICT_FMA\000"
1234 /* 376 */ "INRdA\000"
1235 /* 382 */ "INWRdA\000"
1236 /* 389 */ "G_FSUB\000"
1237 /* 396 */ "G_STRICT_FSUB\000"
1238 /* 410 */ "G_ATOMICRMW_FSUB\000"
1239 /* 427 */ "G_SUB\000"
1240 /* 433 */ "G_ATOMICRMW_SUB\000"
1241 /* 449 */ "SBRCRrB\000"
1242 /* 457 */ "SBRSRrB\000"
1243 /* 465 */ "G_INTRINSIC\000"
1244 /* 477 */ "G_FPTRUNC\000"
1245 /* 487 */ "G_INTRINSIC_TRUNC\000"
1246 /* 505 */ "G_TRUNC\000"
1247 /* 513 */ "G_BUILD_VECTOR_TRUNC\000"
1248 /* 534 */ "G_DYN_STACKALLOC\000"
1249 /* 551 */ "SPREAD\000"
1250 /* 558 */ "G_FMAD\000"
1251 /* 565 */ "G_INDEXED_SEXTLOAD\000"
1252 /* 584 */ "G_SEXTLOAD\000"
1253 /* 595 */ "G_INDEXED_ZEXTLOAD\000"
1254 /* 614 */ "G_ZEXTLOAD\000"
1255 /* 625 */ "G_INDEXED_LOAD\000"
1256 /* 640 */ "G_LOAD\000"
1257 /* 647 */ "G_VECREDUCE_FADD\000"
1258 /* 664 */ "G_FADD\000"
1259 /* 671 */ "G_VECREDUCE_SEQ_FADD\000"
1260 /* 692 */ "G_STRICT_FADD\000"
1261 /* 706 */ "G_ATOMICRMW_FADD\000"
1262 /* 723 */ "G_VECREDUCE_ADD\000"
1263 /* 739 */ "G_ADD\000"
1264 /* 745 */ "G_PTR_ADD\000"
1265 /* 755 */ "G_ATOMICRMW_ADD\000"
1266 /* 771 */ "BLD\000"
1267 /* 775 */ "G_ATOMICRMW_NAND\000"
1268 /* 792 */ "G_VECREDUCE_AND\000"
1269 /* 808 */ "G_AND\000"
1270 /* 814 */ "G_ATOMICRMW_AND\000"
1271 /* 830 */ "LIFETIME_END\000"
1272 /* 843 */ "G_BRCOND\000"
1273 /* 852 */ "G_ATOMICRMW_USUB_COND\000"
1274 /* 874 */ "G_LLROUND\000"
1275 /* 884 */ "G_LROUND\000"
1276 /* 893 */ "G_INTRINSIC_ROUND\000"
1277 /* 911 */ "G_INTRINSIC_FPTRUNC_ROUND\000"
1278 /* 937 */ "LOAD_STACK_GUARD\000"
1279 /* 954 */ "PSEUDO_PROBE\000"
1280 /* 967 */ "G_SSUBE\000"
1281 /* 975 */ "G_USUBE\000"
1282 /* 983 */ "G_FENCE\000"
1283 /* 991 */ "ARITH_FENCE\000"
1284 /* 1003 */ "REG_SEQUENCE\000"
1285 /* 1016 */ "G_SADDE\000"
1286 /* 1024 */ "G_UADDE\000"
1287 /* 1032 */ "G_GET_FPMODE\000"
1288 /* 1045 */ "G_RESET_FPMODE\000"
1289 /* 1060 */ "G_SET_FPMODE\000"
1290 /* 1073 */ "G_FMINNUM_IEEE\000"
1291 /* 1088 */ "G_FMAXNUM_IEEE\000"
1292 /* 1103 */ "G_VSCALE\000"
1293 /* 1112 */ "G_JUMP_TABLE\000"
1294 /* 1125 */ "BUNDLE\000"
1295 /* 1132 */ "G_MEMCPY_INLINE\000"
1296 /* 1148 */ "LOCAL_ESCAPE\000"
1297 /* 1161 */ "G_STACKRESTORE\000"
1298 /* 1176 */ "G_INDEXED_STORE\000"
1299 /* 1192 */ "G_STORE\000"
1300 /* 1200 */ "CPSE\000"
1301 /* 1205 */ "G_BITREVERSE\000"
1302 /* 1218 */ "FAKE_USE\000"
1303 /* 1227 */ "SPWRITE\000"
1304 /* 1235 */ "DBG_VALUE\000"
1305 /* 1245 */ "G_GLOBAL_VALUE\000"
1306 /* 1260 */ "G_PTRAUTH_GLOBAL_VALUE\000"
1307 /* 1283 */ "CONVERGENCECTRL_GLUE\000"
1308 /* 1304 */ "G_STACKSAVE\000"
1309 /* 1316 */ "G_MEMMOVE\000"
1310 /* 1326 */ "G_FREEZE\000"
1311 /* 1335 */ "G_FCANONICALIZE\000"
1312 /* 1351 */ "G_CTLZ_ZERO_UNDEF\000"
1313 /* 1369 */ "G_CTTZ_ZERO_UNDEF\000"
1314 /* 1387 */ "INIT_UNDEF\000"
1315 /* 1398 */ "G_IMPLICIT_DEF\000"
1316 /* 1413 */ "DBG_INSTR_REF\000"
1317 /* 1427 */ "G_FNEG\000"
1318 /* 1434 */ "EXTRACT_SUBREG\000"
1319 /* 1449 */ "INSERT_SUBREG\000"
1320 /* 1463 */ "G_SEXT_INREG\000"
1321 /* 1476 */ "SUBREG_TO_REG\000"
1322 /* 1490 */ "G_ATOMIC_CMPXCHG\000"
1323 /* 1507 */ "G_ATOMICRMW_XCHG\000"
1324 /* 1524 */ "G_FLOG\000"
1325 /* 1531 */ "G_VAARG\000"
1326 /* 1539 */ "PREALLOCATED_ARG\000"
1327 /* 1556 */ "G_PREFETCH\000"
1328 /* 1567 */ "G_SMULH\000"
1329 /* 1575 */ "G_UMULH\000"
1330 /* 1583 */ "G_FTANH\000"
1331 /* 1591 */ "G_FSINH\000"
1332 /* 1599 */ "G_FCOSH\000"
1333 /* 1607 */ "DBG_PHI\000"
1334 /* 1615 */ "G_FPTOSI\000"
1335 /* 1624 */ "RETI\000"
1336 /* 1629 */ "G_FPTOUI\000"
1337 /* 1638 */ "G_FPOWI\000"
1338 /* 1646 */ "BREAK\000"
1339 /* 1652 */ "G_PTRMASK\000"
1340 /* 1662 */ "DESK\000"
1341 /* 1667 */ "SUBIRdK\000"
1342 /* 1675 */ "SBCIRdK\000"
1343 /* 1683 */ "LDIRdK\000"
1344 /* 1690 */ "ANDIRdK\000"
1345 /* 1698 */ "CPIRdK\000"
1346 /* 1705 */ "ORIRdK\000"
1347 /* 1712 */ "LDSRdK\000"
1348 /* 1719 */ "SBIWRdK\000"
1349 /* 1727 */ "SUBIWRdK\000"
1350 /* 1736 */ "SBCIWRdK\000"
1351 /* 1745 */ "ADIWRdK\000"
1352 /* 1753 */ "LDIWRdK\000"
1353 /* 1761 */ "ANDIWRdK\000"
1354 /* 1770 */ "ORIWRdK\000"
1355 /* 1778 */ "LDSWRdK\000"
1356 /* 1786 */ "GC_LABEL\000"
1357 /* 1795 */ "DBG_LABEL\000"
1358 /* 1805 */ "EH_LABEL\000"
1359 /* 1814 */ "ANNOTATION_LABEL\000"
1360 /* 1831 */ "ICALL_BRANCH_FUNNEL\000"
1361 /* 1851 */ "G_FSHL\000"
1362 /* 1858 */ "G_SHL\000"
1363 /* 1864 */ "G_FCEIL\000"
1364 /* 1872 */ "EICALL\000"
1365 /* 1879 */ "PATCHABLE_TAIL_CALL\000"
1366 /* 1899 */ "PATCHABLE_TYPED_EVENT_CALL\000"
1367 /* 1926 */ "PATCHABLE_EVENT_CALL\000"
1368 /* 1947 */ "FENTRY_CALL\000"
1369 /* 1959 */ "KILL\000"
1370 /* 1964 */ "G_CONSTANT_POOL\000"
1371 /* 1980 */ "G_ROTL\000"
1372 /* 1987 */ "G_VECREDUCE_FMUL\000"
1373 /* 2004 */ "G_FMUL\000"
1374 /* 2011 */ "G_VECREDUCE_SEQ_FMUL\000"
1375 /* 2032 */ "G_STRICT_FMUL\000"
1376 /* 2046 */ "G_VECREDUCE_MUL\000"
1377 /* 2062 */ "G_MUL\000"
1378 /* 2068 */ "G_FREM\000"
1379 /* 2075 */ "G_STRICT_FREM\000"
1380 /* 2089 */ "G_SREM\000"
1381 /* 2096 */ "G_UREM\000"
1382 /* 2103 */ "G_SDIVREM\000"
1383 /* 2113 */ "G_UDIVREM\000"
1384 /* 2123 */ "ELPM\000"
1385 /* 2128 */ "SPM\000"
1386 /* 2132 */ "INLINEASM\000"
1387 /* 2142 */ "G_VECREDUCE_FMINIMUM\000"
1388 /* 2163 */ "G_FMINIMUM\000"
1389 /* 2174 */ "G_ATOMICRMW_FMINIMUM\000"
1390 /* 2195 */ "G_VECREDUCE_FMAXIMUM\000"
1391 /* 2216 */ "G_FMAXIMUM\000"
1392 /* 2227 */ "G_ATOMICRMW_FMAXIMUM\000"
1393 /* 2248 */ "G_FMINIMUMNUM\000"
1394 /* 2262 */ "G_FMAXIMUMNUM\000"
1395 /* 2276 */ "G_FMINNUM\000"
1396 /* 2286 */ "G_FMAXNUM\000"
1397 /* 2296 */ "G_FATAN\000"
1398 /* 2304 */ "G_FTAN\000"
1399 /* 2311 */ "G_INTRINSIC_ROUNDEVEN\000"
1400 /* 2333 */ "G_ASSERT_ALIGN\000"
1401 /* 2348 */ "G_FCOPYSIGN\000"
1402 /* 2360 */ "G_VECREDUCE_FMIN\000"
1403 /* 2377 */ "G_ATOMICRMW_FMIN\000"
1404 /* 2394 */ "G_VECREDUCE_SMIN\000"
1405 /* 2411 */ "G_SMIN\000"
1406 /* 2418 */ "G_VECREDUCE_UMIN\000"
1407 /* 2435 */ "G_UMIN\000"
1408 /* 2442 */ "G_ATOMICRMW_UMIN\000"
1409 /* 2459 */ "G_ATOMICRMW_MIN\000"
1410 /* 2475 */ "G_FASIN\000"
1411 /* 2483 */ "G_FSIN\000"
1412 /* 2490 */ "CFI_INSTRUCTION\000"
1413 /* 2506 */ "ADJCALLSTACKDOWN\000"
1414 /* 2523 */ "G_SSUBO\000"
1415 /* 2531 */ "G_USUBO\000"
1416 /* 2539 */ "G_SADDO\000"
1417 /* 2547 */ "G_UADDO\000"
1418 /* 2555 */ "JUMP_TABLE_DEBUG_INFO\000"
1419 /* 2577 */ "G_SMULO\000"
1420 /* 2585 */ "G_UMULO\000"
1421 /* 2593 */ "G_BZERO\000"
1422 /* 2601 */ "STACKMAP\000"
1423 /* 2610 */ "G_DEBUGTRAP\000"
1424 /* 2622 */ "G_UBSANTRAP\000"
1425 /* 2634 */ "G_TRAP\000"
1426 /* 2641 */ "G_ATOMICRMW_UDEC_WRAP\000"
1427 /* 2663 */ "G_ATOMICRMW_UINC_WRAP\000"
1428 /* 2685 */ "G_BSWAP\000"
1429 /* 2693 */ "SLEEP\000"
1430 /* 2699 */ "G_SITOFP\000"
1431 /* 2708 */ "G_UITOFP\000"
1432 /* 2717 */ "G_FCMP\000"
1433 /* 2724 */ "G_ICMP\000"
1434 /* 2731 */ "G_SCMP\000"
1435 /* 2738 */ "G_UCMP\000"
1436 /* 2745 */ "EIJMP\000"
1437 /* 2751 */ "NOP\000"
1438 /* 2755 */ "CONVERGENCECTRL_LOOP\000"
1439 /* 2776 */ "G_CTPOP\000"
1440 /* 2784 */ "PATCHABLE_OP\000"
1441 /* 2797 */ "FAULTING_OP\000"
1442 /* 2809 */ "ADJCALLSTACKUP\000"
1443 /* 2824 */ "PREALLOCATED_SETUP\000"
1444 /* 2843 */ "G_FLDEXP\000"
1445 /* 2852 */ "G_STRICT_FLDEXP\000"
1446 /* 2868 */ "G_FEXP\000"
1447 /* 2875 */ "G_FFREXP\000"
1448 /* 2884 */ "LDDWRdYQ\000"
1449 /* 2893 */ "LDDRdPtrQ\000"
1450 /* 2903 */ "LDDWRdPtrQ\000"
1451 /* 2914 */ "G_BR\000"
1452 /* 2919 */ "INLINEASM_BR\000"
1453 /* 2932 */ "G_BLOCK_ADDR\000"
1454 /* 2945 */ "WDR\000"
1455 /* 2949 */ "MEMBARRIER\000"
1456 /* 2960 */ "G_CONSTANT_FOLD_BARRIER\000"
1457 /* 2984 */ "PATCHABLE_FUNCTION_ENTER\000"
1458 /* 3009 */ "G_READCYCLECOUNTER\000"
1459 /* 3028 */ "G_READSTEADYCOUNTER\000"
1460 /* 3048 */ "G_READ_REGISTER\000"
1461 /* 3064 */ "G_WRITE_REGISTER\000"
1462 /* 3081 */ "G_ASHR\000"
1463 /* 3088 */ "G_FSHR\000"
1464 /* 3095 */ "G_LSHR\000"
1465 /* 3102 */ "CONVERGENCECTRL_ANCHOR\000"
1466 /* 3125 */ "G_FFLOOR\000"
1467 /* 3134 */ "G_EXTRACT_SUBVECTOR\000"
1468 /* 3154 */ "G_INSERT_SUBVECTOR\000"
1469 /* 3173 */ "G_BUILD_VECTOR\000"
1470 /* 3188 */ "G_SHUFFLE_VECTOR\000"
1471 /* 3205 */ "G_STEP_VECTOR\000"
1472 /* 3219 */ "G_SPLAT_VECTOR\000"
1473 /* 3234 */ "G_VECREDUCE_XOR\000"
1474 /* 3250 */ "G_XOR\000"
1475 /* 3256 */ "G_ATOMICRMW_XOR\000"
1476 /* 3272 */ "G_VECREDUCE_OR\000"
1477 /* 3287 */ "G_OR\000"
1478 /* 3292 */ "G_ATOMICRMW_OR\000"
1479 /* 3307 */ "G_ROTR\000"
1480 /* 3314 */ "G_INTTOPTR\000"
1481 /* 3325 */ "G_FABS\000"
1482 /* 3332 */ "G_ABS\000"
1483 /* 3338 */ "G_ABDS\000"
1484 /* 3345 */ "G_UNMERGE_VALUES\000"
1485 /* 3362 */ "G_MERGE_VALUES\000"
1486 /* 3377 */ "FMULS\000"
1487 /* 3383 */ "G_FACOS\000"
1488 /* 3391 */ "G_FCOS\000"
1489 /* 3398 */ "G_FSINCOS\000"
1490 /* 3408 */ "G_CONCAT_VECTORS\000"
1491 /* 3425 */ "COPY_TO_REGCLASS\000"
1492 /* 3442 */ "G_IS_FPCLASS\000"
1493 /* 3455 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000"
1494 /* 3485 */ "G_VECTOR_COMPRESS\000"
1495 /* 3503 */ "G_INTRINSIC_W_SIDE_EFFECTS\000"
1496 /* 3530 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000"
1497 /* 3568 */ "G_SSUBSAT\000"
1498 /* 3578 */ "G_USUBSAT\000"
1499 /* 3588 */ "G_SADDSAT\000"
1500 /* 3598 */ "G_UADDSAT\000"
1501 /* 3608 */ "G_SSHLSAT\000"
1502 /* 3618 */ "G_USHLSAT\000"
1503 /* 3628 */ "G_SMULFIXSAT\000"
1504 /* 3641 */ "G_UMULFIXSAT\000"
1505 /* 3654 */ "G_SDIVFIXSAT\000"
1506 /* 3667 */ "G_UDIVFIXSAT\000"
1507 /* 3680 */ "G_ATOMICRMW_USUB_SAT\000"
1508 /* 3701 */ "G_FPTOSI_SAT\000"
1509 /* 3714 */ "G_FPTOUI_SAT\000"
1510 /* 3727 */ "G_EXTRACT\000"
1511 /* 3737 */ "G_SELECT\000"
1512 /* 3746 */ "G_BRINDIRECT\000"
1513 /* 3759 */ "PATCHABLE_RET\000"
1514 /* 3773 */ "G_MEMSET\000"
1515 /* 3782 */ "PATCHABLE_FUNCTION_EXIT\000"
1516 /* 3806 */ "G_BRJT\000"
1517 /* 3813 */ "G_EXTRACT_VECTOR_ELT\000"
1518 /* 3834 */ "G_INSERT_VECTOR_ELT\000"
1519 /* 3854 */ "G_FCONSTANT\000"
1520 /* 3866 */ "G_CONSTANT\000"
1521 /* 3877 */ "G_INTRINSIC_CONVERGENT\000"
1522 /* 3900 */ "STATEPOINT\000"
1523 /* 3911 */ "PATCHPOINT\000"
1524 /* 3922 */ "G_PTRTOINT\000"
1525 /* 3933 */ "G_FRINT\000"
1526 /* 3941 */ "G_INTRINSIC_LLRINT\000"
1527 /* 3960 */ "G_INTRINSIC_LRINT\000"
1528 /* 3978 */ "G_FNEARBYINT\000"
1529 /* 3991 */ "G_VASTART\000"
1530 /* 4001 */ "LIFETIME_START\000"
1531 /* 4016 */ "G_INVOKE_REGION_START\000"
1532 /* 4038 */ "G_INSERT\000"
1533 /* 4047 */ "G_FSQRT\000"
1534 /* 4055 */ "G_STRICT_FSQRT\000"
1535 /* 4070 */ "G_BITCAST\000"
1536 /* 4080 */ "G_ADDRSPACE_CAST\000"
1537 /* 4097 */ "BST\000"
1538 /* 4101 */ "DBG_VALUE_LIST\000"
1539 /* 4116 */ "G_FPEXT\000"
1540 /* 4124 */ "G_SEXT\000"
1541 /* 4131 */ "G_ASSERT_SEXT\000"
1542 /* 4145 */ "G_ANYEXT\000"
1543 /* 4154 */ "G_ZEXT\000"
1544 /* 4161 */ "G_ASSERT_ZEXT\000"
1545 /* 4175 */ "G_ABDU\000"
1546 /* 4182 */ "FMULSU\000"
1547 /* 4189 */ "G_FDIV\000"
1548 /* 4196 */ "G_STRICT_FDIV\000"
1549 /* 4210 */ "G_SDIV\000"
1550 /* 4217 */ "G_UDIV\000"
1551 /* 4224 */ "G_GET_FPENV\000"
1552 /* 4236 */ "G_RESET_FPENV\000"
1553 /* 4250 */ "G_SET_FPENV\000"
1554 /* 4262 */ "G_FPOW\000"
1555 /* 4269 */ "G_VECREDUCE_FMAX\000"
1556 /* 4286 */ "G_ATOMICRMW_FMAX\000"
1557 /* 4303 */ "G_VECREDUCE_SMAX\000"
1558 /* 4320 */ "G_SMAX\000"
1559 /* 4327 */ "G_VECREDUCE_UMAX\000"
1560 /* 4344 */ "G_UMAX\000"
1561 /* 4351 */ "G_ATOMICRMW_UMAX\000"
1562 /* 4368 */ "G_ATOMICRMW_MAX\000"
1563 /* 4384 */ "FRMIDX\000"
1564 /* 4391 */ "G_FRAME_INDEX\000"
1565 /* 4405 */ "G_SBFX\000"
1566 /* 4412 */ "G_UBFX\000"
1567 /* 4419 */ "G_SMULFIX\000"
1568 /* 4429 */ "G_UMULFIX\000"
1569 /* 4439 */ "G_SDIVFIX\000"
1570 /* 4449 */ "G_UDIVFIX\000"
1571 /* 4459 */ "G_MEMCPY\000"
1572 /* 4468 */ "COPY\000"
1573 /* 4473 */ "CONVERGENCECTRL_ENTRY\000"
1574 /* 4495 */ "G_CTLZ\000"
1575 /* 4502 */ "G_CTTZ\000"
1576 /* 4509 */ "ELPMBRdZ\000"
1577 /* 4518 */ "ELPMRdZ\000"
1578 /* 4526 */ "ELPMWRdZ\000"
1579 /* 4535 */ "SBICAb\000"
1580 /* 4542 */ "CBIAb\000"
1581 /* 4548 */ "SBIAb\000"
1582 /* 4554 */ "SBISAb\000"
1583 /* 4561 */ "LDRdPtrPd\000"
1584 /* 4571 */ "LDWRdPtrPd\000"
1585 /* 4582 */ "RORBRd\000"
1586 /* 4589 */ "DECRd\000"
1587 /* 4595 */ "INCRd\000"
1588 /* 4601 */ "NEGRd\000"
1589 /* 4607 */ "COMRd\000"
1590 /* 4613 */ "LSLBNRd\000"
1591 /* 4621 */ "ASRBNRd\000"
1592 /* 4629 */ "LSRBNRd\000"
1593 /* 4637 */ "LSLWNRd\000"
1594 /* 4645 */ "ASRWNRd\000"
1595 /* 4653 */ "LSRWNRd\000"
1596 /* 4661 */ "SWAPRd\000"
1597 /* 4668 */ "POPRd\000"
1598 /* 4674 */ "RORRd\000"
1599 /* 4680 */ "ASRRd\000"
1600 /* 4686 */ "LSRRd\000"
1601 /* 4692 */ "NEGWRd\000"
1602 /* 4699 */ "ROLWRd\000"
1603 /* 4706 */ "LSLWRd\000"
1604 /* 4713 */ "COMWRd\000"
1605 /* 4720 */ "POPWRd\000"
1606 /* 4727 */ "RORWRd\000"
1607 /* 4734 */ "ASRWRd\000"
1608 /* 4741 */ "LSRWRd\000"
1609 /* 4748 */ "LACZRd\000"
1610 /* 4755 */ "XCHZRd\000"
1611 /* 4762 */ "LASZRd\000"
1612 /* 4769 */ "LATZRd\000"
1613 /* 4776 */ "LSLWHiRd\000"
1614 /* 4785 */ "ASRWLoRd\000"
1615 /* 4794 */ "LSRWLoRd\000"
1616 /* 4803 */ "AtomicFence\000"
1617 /* 4815 */ "SPMZPi\000"
1618 /* 4822 */ "ELPMBRdZPi\000"
1619 /* 4833 */ "ELPMRdZPi\000"
1620 /* 4843 */ "ELPMWRdZPi\000"
1621 /* 4854 */ "LDRdPtrPi\000"
1622 /* 4864 */ "LDWRdPtrPi\000"
1623 /* 4875 */ "BRGEk\000"
1624 /* 4881 */ "BRNEk\000"
1625 /* 4887 */ "BRSHk\000"
1626 /* 4893 */ "BRMIk\000"
1627 /* 4899 */ "RCALLk\000"
1628 /* 4906 */ "BRPLk\000"
1629 /* 4912 */ "BRLOk\000"
1630 /* 4918 */ "RJMPk\000"
1631 /* 4924 */ "BREQk\000"
1632 /* 4930 */ "BRLTk\000"
1633 /* 4936 */ "BRBCsk\000"
1634 /* 4943 */ "BRBSsk\000"
1635 /* 4950 */ "CopyZero\000"
1636 /* 4959 */ "OUTARr\000"
1637 /* 4966 */ "OUTWARr\000"
1638 /* 4974 */ "PUSHRr\000"
1639 /* 4981 */ "STSKRr\000"
1640 /* 4988 */ "STSWKRr\000"
1641 /* 4996 */ "STDSPQRr\000"
1642 /* 5005 */ "STDWSPQRr\000"
1643 /* 5015 */ "STDPtrQRr\000"
1644 /* 5025 */ "STDWPtrQRr\000"
1645 /* 5036 */ "PUSHWRr\000"
1646 /* 5044 */ "STPtrPdRr\000"
1647 /* 5054 */ "STWPtrPdRr\000"
1648 /* 5065 */ "SUBRdRr\000"
1649 /* 5073 */ "SBCRdRr\000"
1650 /* 5081 */ "ADCRdRr\000"
1651 /* 5089 */ "CPCRdRr\000"
1652 /* 5097 */ "ADDRdRr\000"
1653 /* 5105 */ "ANDRdRr\000"
1654 /* 5113 */ "MULRdRr\000"
1655 /* 5121 */ "CPRdRr\000"
1656 /* 5128 */ "EORRdRr\000"
1657 /* 5136 */ "MULSRdRr\000"
1658 /* 5145 */ "MULSURdRr\000"
1659 /* 5155 */ "MOVRdRr\000"
1660 /* 5163 */ "SUBWRdRr\000"
1661 /* 5172 */ "SBCWRdRr\000"
1662 /* 5181 */ "ADCWRdRr\000"
1663 /* 5190 */ "CPCWRdRr\000"
1664 /* 5199 */ "ADDWRdRr\000"
1665 /* 5208 */ "ANDWRdRr\000"
1666 /* 5217 */ "CPWRdRr\000"
1667 /* 5225 */ "EORWRdRr\000"
1668 /* 5234 */ "MOVWRdRr\000"
1669 /* 5243 */ "STPtrPiRr\000"
1670 /* 5253 */ "STWPtrPiRr\000"
1671 /* 5264 */ "STPtrRr\000"
1672 /* 5272 */ "STWPtrRr\000"
1673 /* 5281 */ "LDRdPtr\000"
1674 /* 5289 */ "LDWRdPtr\000"
1675 /* 5298 */ "BCLRs\000"
1676 /* 5304 */ "BSETs\000"
1677 /* 5310 */ "LDSRdKTiny\000"
1678 /* 5321 */ "STSKRrTiny\000"
1679};
1680#ifdef __GNUC__
1681#pragma GCC diagnostic pop
1682#endif
1683
1684extern const unsigned AVRInstrNameIndices[] = {
1685 1611U, 2132U, 2919U, 2490U, 1805U, 1786U, 1814U, 1959U,
1686 1434U, 1449U, 1400U, 1387U, 1476U, 3425U, 1235U, 4101U,
1687 1413U, 1607U, 1795U, 1003U, 4468U, 1125U, 4001U, 830U,
1688 954U, 991U, 2601U, 1947U, 3911U, 937U, 2824U, 1539U,
1689 3900U, 1148U, 2797U, 2784U, 2984U, 3759U, 3782U, 1879U,
1690 1926U, 1899U, 1831U, 1218U, 2949U, 2555U, 4473U, 3102U,
1691 2755U, 1283U, 4131U, 4161U, 2333U, 739U, 427U, 2062U,
1692 4210U, 4217U, 2089U, 2096U, 2103U, 2113U, 808U, 3287U,
1693 3250U, 3338U, 4175U, 1398U, 1609U, 4391U, 1245U, 1260U,
1694 1964U, 3727U, 3345U, 4038U, 3362U, 3173U, 513U, 3408U,
1695 3922U, 3314U, 4070U, 1326U, 2960U, 911U, 487U, 893U,
1696 3960U, 3941U, 2311U, 3009U, 3028U, 640U, 584U, 614U,
1697 625U, 565U, 595U, 1192U, 1176U, 3455U, 1490U, 1507U,
1698 755U, 433U, 814U, 775U, 3292U, 3256U, 4368U, 2459U,
1699 4351U, 2442U, 706U, 410U, 4286U, 2377U, 2227U, 2174U,
1700 2663U, 2641U, 852U, 3680U, 983U, 1556U, 843U, 3746U,
1701 4016U, 465U, 3503U, 3877U, 3530U, 4145U, 505U, 3866U,
1702 3854U, 3991U, 1531U, 4124U, 1463U, 4154U, 1858U, 3095U,
1703 3081U, 1851U, 3088U, 3307U, 1980U, 2724U, 2717U, 2731U,
1704 2738U, 3737U, 2547U, 1024U, 2531U, 975U, 2539U, 1016U,
1705 2523U, 967U, 2585U, 2577U, 1575U, 1567U, 3598U, 3588U,
1706 3578U, 3568U, 3618U, 3608U, 4419U, 4429U, 3628U, 3641U,
1707 4439U, 4449U, 3654U, 3667U, 664U, 389U, 2004U, 357U,
1708 558U, 4189U, 2068U, 4262U, 1638U, 2868U, 62U, 9U,
1709 1524U, 45U, 0U, 2843U, 2875U, 1427U, 4116U, 477U,
1710 1615U, 1629U, 2699U, 2708U, 3701U, 3714U, 3325U, 2348U,
1711 3442U, 1335U, 2276U, 2286U, 1073U, 1088U, 2163U, 2216U,
1712 2248U, 2262U, 4224U, 4250U, 4236U, 1032U, 1060U, 1045U,
1713 745U, 1652U, 2411U, 4320U, 2435U, 4344U, 3332U, 884U,
1714 874U, 2914U, 3806U, 1103U, 3154U, 3134U, 3834U, 3813U,
1715 3188U, 3219U, 3205U, 3485U, 4502U, 1369U, 4495U, 1351U,
1716 2776U, 2685U, 1205U, 1864U, 3391U, 2483U, 3398U, 2304U,
1717 3383U, 2475U, 2296U, 53U, 1599U, 1591U, 1583U, 4047U,
1718 3125U, 3933U, 3978U, 4080U, 2932U, 1112U, 534U, 1304U,
1719 1161U, 692U, 396U, 2032U, 4196U, 2075U, 363U, 4055U,
1720 2852U, 3048U, 3064U, 4459U, 1132U, 1316U, 3773U, 2593U,
1721 2634U, 2610U, 2622U, 671U, 2011U, 647U, 1987U, 4269U,
1722 2360U, 2195U, 2142U, 723U, 2046U, 792U, 3272U, 3234U,
1723 4303U, 2394U, 4327U, 2418U, 4405U, 4412U, 5181U, 5199U,
1724 2506U, 2809U, 1761U, 5208U, 4621U, 4785U, 4645U, 4734U,
1725 194U, 33U, 339U, 4803U, 86U, 240U, 99U, 252U,
1726 115U, 267U, 157U, 305U, 70U, 225U, 178U, 324U,
1727 131U, 282U, 4713U, 5190U, 5217U, 4950U, 4509U, 4822U,
1728 4526U, 4843U, 5225U, 4384U, 382U, 2903U, 2884U, 1753U,
1729 1778U, 5289U, 4571U, 4864U, 4510U, 4527U, 4844U, 4613U,
1730 4776U, 4637U, 4706U, 4629U, 4794U, 4653U, 4741U, 151U,
1731 27U, 300U, 200U, 39U, 344U, 4692U, 1770U, 5226U,
1732 4966U, 4720U, 5036U, 18U, 215U, 4699U, 4582U, 4727U,
1733 145U, 295U, 172U, 319U, 1736U, 5172U, 4126U, 551U,
1734 1227U, 4996U, 5025U, 5005U, 4988U, 5054U, 5253U, 5272U,
1735 1727U, 5163U, 206U, 349U, 4156U, 5081U, 5097U, 1745U,
1736 1690U, 5105U, 4680U, 5298U, 771U, 4936U, 4943U, 1646U,
1737 4924U, 4875U, 4912U, 4930U, 4893U, 4881U, 4906U, 4887U,
1738 5304U, 4097U, 4900U, 4542U, 4607U, 5089U, 1698U, 5121U,
1739 1200U, 4589U, 1662U, 1872U, 2745U, 2123U, 4518U, 4833U,
1740 5128U, 1999U, 3377U, 4182U, 1873U, 2746U, 4595U, 376U,
1741 4919U, 4748U, 4762U, 4769U, 2893U, 1683U, 5281U, 4561U,
1742 4854U, 1712U, 5310U, 2124U, 4519U, 4834U, 4686U, 5155U,
1743 5234U, 5113U, 5136U, 5145U, 4601U, 2751U, 1705U, 5129U,
1744 4959U, 4668U, 4974U, 4899U, 3769U, 1624U, 4918U, 4674U,
1745 1675U, 5073U, 4548U, 4535U, 4554U, 1719U, 449U, 457U,
1746 2693U, 2128U, 4815U, 5015U, 5044U, 5243U, 5264U, 4981U,
1747 5321U, 1667U, 5065U, 4661U, 2945U, 4755U,
1748};
1749
1750static inline void InitAVRMCInstrInfo(MCInstrInfo *II) {
1751 II->InitMCInstrInfo(AVRDescs.Insts, AVRInstrNameIndices, AVRInstrNameData, nullptr, nullptr, 502);
1752}
1753
1754} // end namespace llvm
1755#endif // GET_INSTRINFO_MC_DESC
1756
1757#ifdef GET_INSTRINFO_HEADER
1758#undef GET_INSTRINFO_HEADER
1759namespace llvm {
1760struct AVRGenInstrInfo : public TargetInstrInfo {
1761 explicit AVRGenInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
1762 ~AVRGenInstrInfo() override = default;
1763
1764};
1765} // end namespace llvm
1766#endif // GET_INSTRINFO_HEADER
1767
1768#ifdef GET_INSTRINFO_HELPER_DECLS
1769#undef GET_INSTRINFO_HELPER_DECLS
1770
1771
1772#endif // GET_INSTRINFO_HELPER_DECLS
1773
1774#ifdef GET_INSTRINFO_HELPERS
1775#undef GET_INSTRINFO_HELPERS
1776
1777#endif // GET_INSTRINFO_HELPERS
1778
1779#ifdef GET_INSTRINFO_CTOR_DTOR
1780#undef GET_INSTRINFO_CTOR_DTOR
1781namespace llvm {
1782extern const AVRInstrTable AVRDescs;
1783extern const unsigned AVRInstrNameIndices[];
1784extern const char AVRInstrNameData[];
1785AVRGenInstrInfo::AVRGenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
1786 : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
1787 InitMCInstrInfo(AVRDescs.Insts, AVRInstrNameIndices, AVRInstrNameData, nullptr, nullptr, 502);
1788}
1789} // end namespace llvm
1790#endif // GET_INSTRINFO_CTOR_DTOR
1791
1792#ifdef GET_INSTRINFO_MC_HELPER_DECLS
1793#undef GET_INSTRINFO_MC_HELPER_DECLS
1794
1795namespace llvm {
1796class MCInst;
1797class FeatureBitset;
1798
1799namespace AVR_MC {
1800
1801void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
1802
1803} // end namespace AVR_MC
1804} // end namespace llvm
1805
1806#endif // GET_INSTRINFO_MC_HELPER_DECLS
1807
1808#ifdef GET_INSTRINFO_MC_HELPERS
1809#undef GET_INSTRINFO_MC_HELPERS
1810
1811namespace llvm::AVR_MC {
1812} // end namespace llvm::AVR_MC
1813#endif // GET_GENISTRINFO_MC_HELPERS
1814
1815#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
1816 defined(GET_AVAILABLE_OPCODE_CHECKER)
1817#define GET_COMPUTE_FEATURES
1818#endif
1819#ifdef GET_COMPUTE_FEATURES
1820#undef GET_COMPUTE_FEATURES
1821namespace llvm::AVR_MC {
1822// Bits for subtarget features that participate in instruction matching.
1823enum SubtargetFeatureBits : uint8_t {
1824 Feature_HasSRAMBit = 14,
1825 Feature_HasJMPCALLBit = 7,
1826 Feature_HasIJMPCALLBit = 6,
1827 Feature_HasEIJMPCALLBit = 3,
1828 Feature_HasADDSUBIWBit = 0,
1829 Feature_HasSmallStackBit = 15,
1830 Feature_HasMOVWBit = 10,
1831 Feature_HasLPMBit = 8,
1832 Feature_HasLPMXBit = 9,
1833 Feature_HasELPMBit = 4,
1834 Feature_HasELPMXBit = 5,
1835 Feature_HasSPMBit = 12,
1836 Feature_HasSPMXBit = 13,
1837 Feature_HasDESBit = 2,
1838 Feature_SupportsRMWBit = 18,
1839 Feature_SupportsMultiplicationBit = 17,
1840 Feature_HasBREAKBit = 1,
1841 Feature_HasTinyEncodingBit = 16,
1842 Feature_HasNonTinyEncodingBit = 11,
1843};
1844
1845inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
1846 FeatureBitset Features;
1847 if (FB[AVR::FeatureSRAM])
1848 Features.set(Feature_HasSRAMBit);
1849 if (FB[AVR::FeatureJMPCALL])
1850 Features.set(Feature_HasJMPCALLBit);
1851 if (FB[AVR::FeatureIJMPCALL])
1852 Features.set(Feature_HasIJMPCALLBit);
1853 if (FB[AVR::FeatureEIJMPCALL])
1854 Features.set(Feature_HasEIJMPCALLBit);
1855 if (FB[AVR::FeatureADDSUBIW])
1856 Features.set(Feature_HasADDSUBIWBit);
1857 if (FB[AVR::FeatureSmallStack])
1858 Features.set(Feature_HasSmallStackBit);
1859 if (FB[AVR::FeatureMOVW])
1860 Features.set(Feature_HasMOVWBit);
1861 if (FB[AVR::FeatureLPM])
1862 Features.set(Feature_HasLPMBit);
1863 if (FB[AVR::FeatureLPMX])
1864 Features.set(Feature_HasLPMXBit);
1865 if (FB[AVR::FeatureELPM])
1866 Features.set(Feature_HasELPMBit);
1867 if (FB[AVR::FeatureELPMX])
1868 Features.set(Feature_HasELPMXBit);
1869 if (FB[AVR::FeatureSPM])
1870 Features.set(Feature_HasSPMBit);
1871 if (FB[AVR::FeatureSPMX])
1872 Features.set(Feature_HasSPMXBit);
1873 if (FB[AVR::FeatureDES])
1874 Features.set(Feature_HasDESBit);
1875 if (FB[AVR::FeatureRMW])
1876 Features.set(Feature_SupportsRMWBit);
1877 if (FB[AVR::FeatureMultiplication])
1878 Features.set(Feature_SupportsMultiplicationBit);
1879 if (FB[AVR::FeatureBREAK])
1880 Features.set(Feature_HasBREAKBit);
1881 if (FB[AVR::FeatureTinyEncoding])
1882 Features.set(Feature_HasTinyEncodingBit);
1883 if (!FB[AVR::FeatureTinyEncoding])
1884 Features.set(Feature_HasNonTinyEncodingBit);
1885 return Features;
1886}
1887
1888inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
1889 enum : uint8_t {
1890 CEFBS_None,
1891 CEFBS_HasADDSUBIW,
1892 CEFBS_HasBREAK,
1893 CEFBS_HasDES,
1894 CEFBS_HasEIJMPCALL,
1895 CEFBS_HasELPM,
1896 CEFBS_HasELPMX,
1897 CEFBS_HasIJMPCALL,
1898 CEFBS_HasJMPCALL,
1899 CEFBS_HasLPM,
1900 CEFBS_HasLPMX,
1901 CEFBS_HasMOVW,
1902 CEFBS_HasNonTinyEncoding,
1903 CEFBS_HasSPM,
1904 CEFBS_HasSPMX,
1905 CEFBS_HasSRAM,
1906 CEFBS_HasTinyEncoding,
1907 CEFBS_SupportsMultiplication,
1908 CEFBS_SupportsRMW,
1909 CEFBS_HasSRAM_HasNonTinyEncoding,
1910 CEFBS_HasSRAM_HasTinyEncoding,
1911 };
1912
1913 static constexpr FeatureBitset FeatureBitsets[] = {
1914 {}, // CEFBS_None
1915 {Feature_HasADDSUBIWBit, },
1916 {Feature_HasBREAKBit, },
1917 {Feature_HasDESBit, },
1918 {Feature_HasEIJMPCALLBit, },
1919 {Feature_HasELPMBit, },
1920 {Feature_HasELPMXBit, },
1921 {Feature_HasIJMPCALLBit, },
1922 {Feature_HasJMPCALLBit, },
1923 {Feature_HasLPMBit, },
1924 {Feature_HasLPMXBit, },
1925 {Feature_HasMOVWBit, },
1926 {Feature_HasNonTinyEncodingBit, },
1927 {Feature_HasSPMBit, },
1928 {Feature_HasSPMXBit, },
1929 {Feature_HasSRAMBit, },
1930 {Feature_HasTinyEncodingBit, },
1931 {Feature_SupportsMultiplicationBit, },
1932 {Feature_SupportsRMWBit, },
1933 {Feature_HasSRAMBit, Feature_HasNonTinyEncodingBit, },
1934 {Feature_HasSRAMBit, Feature_HasTinyEncodingBit, },
1935 };
1936 static constexpr uint8_t RequiredFeaturesRefs[] = {
1937 CEFBS_None, // PHI = 0
1938 CEFBS_None, // INLINEASM = 1
1939 CEFBS_None, // INLINEASM_BR = 2
1940 CEFBS_None, // CFI_INSTRUCTION = 3
1941 CEFBS_None, // EH_LABEL = 4
1942 CEFBS_None, // GC_LABEL = 5
1943 CEFBS_None, // ANNOTATION_LABEL = 6
1944 CEFBS_None, // KILL = 7
1945 CEFBS_None, // EXTRACT_SUBREG = 8
1946 CEFBS_None, // INSERT_SUBREG = 9
1947 CEFBS_None, // IMPLICIT_DEF = 10
1948 CEFBS_None, // INIT_UNDEF = 11
1949 CEFBS_None, // SUBREG_TO_REG = 12
1950 CEFBS_None, // COPY_TO_REGCLASS = 13
1951 CEFBS_None, // DBG_VALUE = 14
1952 CEFBS_None, // DBG_VALUE_LIST = 15
1953 CEFBS_None, // DBG_INSTR_REF = 16
1954 CEFBS_None, // DBG_PHI = 17
1955 CEFBS_None, // DBG_LABEL = 18
1956 CEFBS_None, // REG_SEQUENCE = 19
1957 CEFBS_None, // COPY = 20
1958 CEFBS_None, // BUNDLE = 21
1959 CEFBS_None, // LIFETIME_START = 22
1960 CEFBS_None, // LIFETIME_END = 23
1961 CEFBS_None, // PSEUDO_PROBE = 24
1962 CEFBS_None, // ARITH_FENCE = 25
1963 CEFBS_None, // STACKMAP = 26
1964 CEFBS_None, // FENTRY_CALL = 27
1965 CEFBS_None, // PATCHPOINT = 28
1966 CEFBS_None, // LOAD_STACK_GUARD = 29
1967 CEFBS_None, // PREALLOCATED_SETUP = 30
1968 CEFBS_None, // PREALLOCATED_ARG = 31
1969 CEFBS_None, // STATEPOINT = 32
1970 CEFBS_None, // LOCAL_ESCAPE = 33
1971 CEFBS_None, // FAULTING_OP = 34
1972 CEFBS_None, // PATCHABLE_OP = 35
1973 CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 36
1974 CEFBS_None, // PATCHABLE_RET = 37
1975 CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 38
1976 CEFBS_None, // PATCHABLE_TAIL_CALL = 39
1977 CEFBS_None, // PATCHABLE_EVENT_CALL = 40
1978 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 41
1979 CEFBS_None, // ICALL_BRANCH_FUNNEL = 42
1980 CEFBS_None, // FAKE_USE = 43
1981 CEFBS_None, // MEMBARRIER = 44
1982 CEFBS_None, // JUMP_TABLE_DEBUG_INFO = 45
1983 CEFBS_None, // CONVERGENCECTRL_ENTRY = 46
1984 CEFBS_None, // CONVERGENCECTRL_ANCHOR = 47
1985 CEFBS_None, // CONVERGENCECTRL_LOOP = 48
1986 CEFBS_None, // CONVERGENCECTRL_GLUE = 49
1987 CEFBS_None, // G_ASSERT_SEXT = 50
1988 CEFBS_None, // G_ASSERT_ZEXT = 51
1989 CEFBS_None, // G_ASSERT_ALIGN = 52
1990 CEFBS_None, // G_ADD = 53
1991 CEFBS_None, // G_SUB = 54
1992 CEFBS_None, // G_MUL = 55
1993 CEFBS_None, // G_SDIV = 56
1994 CEFBS_None, // G_UDIV = 57
1995 CEFBS_None, // G_SREM = 58
1996 CEFBS_None, // G_UREM = 59
1997 CEFBS_None, // G_SDIVREM = 60
1998 CEFBS_None, // G_UDIVREM = 61
1999 CEFBS_None, // G_AND = 62
2000 CEFBS_None, // G_OR = 63
2001 CEFBS_None, // G_XOR = 64
2002 CEFBS_None, // G_ABDS = 65
2003 CEFBS_None, // G_ABDU = 66
2004 CEFBS_None, // G_IMPLICIT_DEF = 67
2005 CEFBS_None, // G_PHI = 68
2006 CEFBS_None, // G_FRAME_INDEX = 69
2007 CEFBS_None, // G_GLOBAL_VALUE = 70
2008 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE = 71
2009 CEFBS_None, // G_CONSTANT_POOL = 72
2010 CEFBS_None, // G_EXTRACT = 73
2011 CEFBS_None, // G_UNMERGE_VALUES = 74
2012 CEFBS_None, // G_INSERT = 75
2013 CEFBS_None, // G_MERGE_VALUES = 76
2014 CEFBS_None, // G_BUILD_VECTOR = 77
2015 CEFBS_None, // G_BUILD_VECTOR_TRUNC = 78
2016 CEFBS_None, // G_CONCAT_VECTORS = 79
2017 CEFBS_None, // G_PTRTOINT = 80
2018 CEFBS_None, // G_INTTOPTR = 81
2019 CEFBS_None, // G_BITCAST = 82
2020 CEFBS_None, // G_FREEZE = 83
2021 CEFBS_None, // G_CONSTANT_FOLD_BARRIER = 84
2022 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND = 85
2023 CEFBS_None, // G_INTRINSIC_TRUNC = 86
2024 CEFBS_None, // G_INTRINSIC_ROUND = 87
2025 CEFBS_None, // G_INTRINSIC_LRINT = 88
2026 CEFBS_None, // G_INTRINSIC_LLRINT = 89
2027 CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 90
2028 CEFBS_None, // G_READCYCLECOUNTER = 91
2029 CEFBS_None, // G_READSTEADYCOUNTER = 92
2030 CEFBS_None, // G_LOAD = 93
2031 CEFBS_None, // G_SEXTLOAD = 94
2032 CEFBS_None, // G_ZEXTLOAD = 95
2033 CEFBS_None, // G_INDEXED_LOAD = 96
2034 CEFBS_None, // G_INDEXED_SEXTLOAD = 97
2035 CEFBS_None, // G_INDEXED_ZEXTLOAD = 98
2036 CEFBS_None, // G_STORE = 99
2037 CEFBS_None, // G_INDEXED_STORE = 100
2038 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 101
2039 CEFBS_None, // G_ATOMIC_CMPXCHG = 102
2040 CEFBS_None, // G_ATOMICRMW_XCHG = 103
2041 CEFBS_None, // G_ATOMICRMW_ADD = 104
2042 CEFBS_None, // G_ATOMICRMW_SUB = 105
2043 CEFBS_None, // G_ATOMICRMW_AND = 106
2044 CEFBS_None, // G_ATOMICRMW_NAND = 107
2045 CEFBS_None, // G_ATOMICRMW_OR = 108
2046 CEFBS_None, // G_ATOMICRMW_XOR = 109
2047 CEFBS_None, // G_ATOMICRMW_MAX = 110
2048 CEFBS_None, // G_ATOMICRMW_MIN = 111
2049 CEFBS_None, // G_ATOMICRMW_UMAX = 112
2050 CEFBS_None, // G_ATOMICRMW_UMIN = 113
2051 CEFBS_None, // G_ATOMICRMW_FADD = 114
2052 CEFBS_None, // G_ATOMICRMW_FSUB = 115
2053 CEFBS_None, // G_ATOMICRMW_FMAX = 116
2054 CEFBS_None, // G_ATOMICRMW_FMIN = 117
2055 CEFBS_None, // G_ATOMICRMW_FMAXIMUM = 118
2056 CEFBS_None, // G_ATOMICRMW_FMINIMUM = 119
2057 CEFBS_None, // G_ATOMICRMW_UINC_WRAP = 120
2058 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP = 121
2059 CEFBS_None, // G_ATOMICRMW_USUB_COND = 122
2060 CEFBS_None, // G_ATOMICRMW_USUB_SAT = 123
2061 CEFBS_None, // G_FENCE = 124
2062 CEFBS_None, // G_PREFETCH = 125
2063 CEFBS_None, // G_BRCOND = 126
2064 CEFBS_None, // G_BRINDIRECT = 127
2065 CEFBS_None, // G_INVOKE_REGION_START = 128
2066 CEFBS_None, // G_INTRINSIC = 129
2067 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 130
2068 CEFBS_None, // G_INTRINSIC_CONVERGENT = 131
2069 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 132
2070 CEFBS_None, // G_ANYEXT = 133
2071 CEFBS_None, // G_TRUNC = 134
2072 CEFBS_None, // G_CONSTANT = 135
2073 CEFBS_None, // G_FCONSTANT = 136
2074 CEFBS_None, // G_VASTART = 137
2075 CEFBS_None, // G_VAARG = 138
2076 CEFBS_None, // G_SEXT = 139
2077 CEFBS_None, // G_SEXT_INREG = 140
2078 CEFBS_None, // G_ZEXT = 141
2079 CEFBS_None, // G_SHL = 142
2080 CEFBS_None, // G_LSHR = 143
2081 CEFBS_None, // G_ASHR = 144
2082 CEFBS_None, // G_FSHL = 145
2083 CEFBS_None, // G_FSHR = 146
2084 CEFBS_None, // G_ROTR = 147
2085 CEFBS_None, // G_ROTL = 148
2086 CEFBS_None, // G_ICMP = 149
2087 CEFBS_None, // G_FCMP = 150
2088 CEFBS_None, // G_SCMP = 151
2089 CEFBS_None, // G_UCMP = 152
2090 CEFBS_None, // G_SELECT = 153
2091 CEFBS_None, // G_UADDO = 154
2092 CEFBS_None, // G_UADDE = 155
2093 CEFBS_None, // G_USUBO = 156
2094 CEFBS_None, // G_USUBE = 157
2095 CEFBS_None, // G_SADDO = 158
2096 CEFBS_None, // G_SADDE = 159
2097 CEFBS_None, // G_SSUBO = 160
2098 CEFBS_None, // G_SSUBE = 161
2099 CEFBS_None, // G_UMULO = 162
2100 CEFBS_None, // G_SMULO = 163
2101 CEFBS_None, // G_UMULH = 164
2102 CEFBS_None, // G_SMULH = 165
2103 CEFBS_None, // G_UADDSAT = 166
2104 CEFBS_None, // G_SADDSAT = 167
2105 CEFBS_None, // G_USUBSAT = 168
2106 CEFBS_None, // G_SSUBSAT = 169
2107 CEFBS_None, // G_USHLSAT = 170
2108 CEFBS_None, // G_SSHLSAT = 171
2109 CEFBS_None, // G_SMULFIX = 172
2110 CEFBS_None, // G_UMULFIX = 173
2111 CEFBS_None, // G_SMULFIXSAT = 174
2112 CEFBS_None, // G_UMULFIXSAT = 175
2113 CEFBS_None, // G_SDIVFIX = 176
2114 CEFBS_None, // G_UDIVFIX = 177
2115 CEFBS_None, // G_SDIVFIXSAT = 178
2116 CEFBS_None, // G_UDIVFIXSAT = 179
2117 CEFBS_None, // G_FADD = 180
2118 CEFBS_None, // G_FSUB = 181
2119 CEFBS_None, // G_FMUL = 182
2120 CEFBS_None, // G_FMA = 183
2121 CEFBS_None, // G_FMAD = 184
2122 CEFBS_None, // G_FDIV = 185
2123 CEFBS_None, // G_FREM = 186
2124 CEFBS_None, // G_FPOW = 187
2125 CEFBS_None, // G_FPOWI = 188
2126 CEFBS_None, // G_FEXP = 189
2127 CEFBS_None, // G_FEXP2 = 190
2128 CEFBS_None, // G_FEXP10 = 191
2129 CEFBS_None, // G_FLOG = 192
2130 CEFBS_None, // G_FLOG2 = 193
2131 CEFBS_None, // G_FLOG10 = 194
2132 CEFBS_None, // G_FLDEXP = 195
2133 CEFBS_None, // G_FFREXP = 196
2134 CEFBS_None, // G_FNEG = 197
2135 CEFBS_None, // G_FPEXT = 198
2136 CEFBS_None, // G_FPTRUNC = 199
2137 CEFBS_None, // G_FPTOSI = 200
2138 CEFBS_None, // G_FPTOUI = 201
2139 CEFBS_None, // G_SITOFP = 202
2140 CEFBS_None, // G_UITOFP = 203
2141 CEFBS_None, // G_FPTOSI_SAT = 204
2142 CEFBS_None, // G_FPTOUI_SAT = 205
2143 CEFBS_None, // G_FABS = 206
2144 CEFBS_None, // G_FCOPYSIGN = 207
2145 CEFBS_None, // G_IS_FPCLASS = 208
2146 CEFBS_None, // G_FCANONICALIZE = 209
2147 CEFBS_None, // G_FMINNUM = 210
2148 CEFBS_None, // G_FMAXNUM = 211
2149 CEFBS_None, // G_FMINNUM_IEEE = 212
2150 CEFBS_None, // G_FMAXNUM_IEEE = 213
2151 CEFBS_None, // G_FMINIMUM = 214
2152 CEFBS_None, // G_FMAXIMUM = 215
2153 CEFBS_None, // G_FMINIMUMNUM = 216
2154 CEFBS_None, // G_FMAXIMUMNUM = 217
2155 CEFBS_None, // G_GET_FPENV = 218
2156 CEFBS_None, // G_SET_FPENV = 219
2157 CEFBS_None, // G_RESET_FPENV = 220
2158 CEFBS_None, // G_GET_FPMODE = 221
2159 CEFBS_None, // G_SET_FPMODE = 222
2160 CEFBS_None, // G_RESET_FPMODE = 223
2161 CEFBS_None, // G_PTR_ADD = 224
2162 CEFBS_None, // G_PTRMASK = 225
2163 CEFBS_None, // G_SMIN = 226
2164 CEFBS_None, // G_SMAX = 227
2165 CEFBS_None, // G_UMIN = 228
2166 CEFBS_None, // G_UMAX = 229
2167 CEFBS_None, // G_ABS = 230
2168 CEFBS_None, // G_LROUND = 231
2169 CEFBS_None, // G_LLROUND = 232
2170 CEFBS_None, // G_BR = 233
2171 CEFBS_None, // G_BRJT = 234
2172 CEFBS_None, // G_VSCALE = 235
2173 CEFBS_None, // G_INSERT_SUBVECTOR = 236
2174 CEFBS_None, // G_EXTRACT_SUBVECTOR = 237
2175 CEFBS_None, // G_INSERT_VECTOR_ELT = 238
2176 CEFBS_None, // G_EXTRACT_VECTOR_ELT = 239
2177 CEFBS_None, // G_SHUFFLE_VECTOR = 240
2178 CEFBS_None, // G_SPLAT_VECTOR = 241
2179 CEFBS_None, // G_STEP_VECTOR = 242
2180 CEFBS_None, // G_VECTOR_COMPRESS = 243
2181 CEFBS_None, // G_CTTZ = 244
2182 CEFBS_None, // G_CTTZ_ZERO_UNDEF = 245
2183 CEFBS_None, // G_CTLZ = 246
2184 CEFBS_None, // G_CTLZ_ZERO_UNDEF = 247
2185 CEFBS_None, // G_CTPOP = 248
2186 CEFBS_None, // G_BSWAP = 249
2187 CEFBS_None, // G_BITREVERSE = 250
2188 CEFBS_None, // G_FCEIL = 251
2189 CEFBS_None, // G_FCOS = 252
2190 CEFBS_None, // G_FSIN = 253
2191 CEFBS_None, // G_FSINCOS = 254
2192 CEFBS_None, // G_FTAN = 255
2193 CEFBS_None, // G_FACOS = 256
2194 CEFBS_None, // G_FASIN = 257
2195 CEFBS_None, // G_FATAN = 258
2196 CEFBS_None, // G_FATAN2 = 259
2197 CEFBS_None, // G_FCOSH = 260
2198 CEFBS_None, // G_FSINH = 261
2199 CEFBS_None, // G_FTANH = 262
2200 CEFBS_None, // G_FSQRT = 263
2201 CEFBS_None, // G_FFLOOR = 264
2202 CEFBS_None, // G_FRINT = 265
2203 CEFBS_None, // G_FNEARBYINT = 266
2204 CEFBS_None, // G_ADDRSPACE_CAST = 267
2205 CEFBS_None, // G_BLOCK_ADDR = 268
2206 CEFBS_None, // G_JUMP_TABLE = 269
2207 CEFBS_None, // G_DYN_STACKALLOC = 270
2208 CEFBS_None, // G_STACKSAVE = 271
2209 CEFBS_None, // G_STACKRESTORE = 272
2210 CEFBS_None, // G_STRICT_FADD = 273
2211 CEFBS_None, // G_STRICT_FSUB = 274
2212 CEFBS_None, // G_STRICT_FMUL = 275
2213 CEFBS_None, // G_STRICT_FDIV = 276
2214 CEFBS_None, // G_STRICT_FREM = 277
2215 CEFBS_None, // G_STRICT_FMA = 278
2216 CEFBS_None, // G_STRICT_FSQRT = 279
2217 CEFBS_None, // G_STRICT_FLDEXP = 280
2218 CEFBS_None, // G_READ_REGISTER = 281
2219 CEFBS_None, // G_WRITE_REGISTER = 282
2220 CEFBS_None, // G_MEMCPY = 283
2221 CEFBS_None, // G_MEMCPY_INLINE = 284
2222 CEFBS_None, // G_MEMMOVE = 285
2223 CEFBS_None, // G_MEMSET = 286
2224 CEFBS_None, // G_BZERO = 287
2225 CEFBS_None, // G_TRAP = 288
2226 CEFBS_None, // G_DEBUGTRAP = 289
2227 CEFBS_None, // G_UBSANTRAP = 290
2228 CEFBS_None, // G_VECREDUCE_SEQ_FADD = 291
2229 CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 292
2230 CEFBS_None, // G_VECREDUCE_FADD = 293
2231 CEFBS_None, // G_VECREDUCE_FMUL = 294
2232 CEFBS_None, // G_VECREDUCE_FMAX = 295
2233 CEFBS_None, // G_VECREDUCE_FMIN = 296
2234 CEFBS_None, // G_VECREDUCE_FMAXIMUM = 297
2235 CEFBS_None, // G_VECREDUCE_FMINIMUM = 298
2236 CEFBS_None, // G_VECREDUCE_ADD = 299
2237 CEFBS_None, // G_VECREDUCE_MUL = 300
2238 CEFBS_None, // G_VECREDUCE_AND = 301
2239 CEFBS_None, // G_VECREDUCE_OR = 302
2240 CEFBS_None, // G_VECREDUCE_XOR = 303
2241 CEFBS_None, // G_VECREDUCE_SMAX = 304
2242 CEFBS_None, // G_VECREDUCE_SMIN = 305
2243 CEFBS_None, // G_VECREDUCE_UMAX = 306
2244 CEFBS_None, // G_VECREDUCE_UMIN = 307
2245 CEFBS_None, // G_SBFX = 308
2246 CEFBS_None, // G_UBFX = 309
2247 CEFBS_None, // ADCWRdRr = 310
2248 CEFBS_None, // ADDWRdRr = 311
2249 CEFBS_None, // ADJCALLSTACKDOWN = 312
2250 CEFBS_None, // ADJCALLSTACKUP = 313
2251 CEFBS_None, // ANDIWRdK = 314
2252 CEFBS_None, // ANDWRdRr = 315
2253 CEFBS_None, // ASRBNRd = 316
2254 CEFBS_None, // ASRWLoRd = 317
2255 CEFBS_None, // ASRWNRd = 318
2256 CEFBS_None, // ASRWRd = 319
2257 CEFBS_None, // Asr16 = 320
2258 CEFBS_None, // Asr32 = 321
2259 CEFBS_None, // Asr8 = 322
2260 CEFBS_None, // AtomicFence = 323
2261 CEFBS_None, // AtomicLoad16 = 324
2262 CEFBS_None, // AtomicLoad8 = 325
2263 CEFBS_None, // AtomicLoadAdd16 = 326
2264 CEFBS_None, // AtomicLoadAdd8 = 327
2265 CEFBS_None, // AtomicLoadAnd16 = 328
2266 CEFBS_None, // AtomicLoadAnd8 = 329
2267 CEFBS_None, // AtomicLoadOr16 = 330
2268 CEFBS_None, // AtomicLoadOr8 = 331
2269 CEFBS_None, // AtomicLoadSub16 = 332
2270 CEFBS_None, // AtomicLoadSub8 = 333
2271 CEFBS_None, // AtomicLoadXor16 = 334
2272 CEFBS_None, // AtomicLoadXor8 = 335
2273 CEFBS_None, // AtomicStore16 = 336
2274 CEFBS_None, // AtomicStore8 = 337
2275 CEFBS_None, // COMWRd = 338
2276 CEFBS_None, // CPCWRdRr = 339
2277 CEFBS_None, // CPWRdRr = 340
2278 CEFBS_None, // CopyZero = 341
2279 CEFBS_HasELPM, // ELPMBRdZ = 342
2280 CEFBS_HasELPMX, // ELPMBRdZPi = 343
2281 CEFBS_HasELPM, // ELPMWRdZ = 344
2282 CEFBS_HasELPMX, // ELPMWRdZPi = 345
2283 CEFBS_None, // EORWRdRr = 346
2284 CEFBS_None, // FRMIDX = 347
2285 CEFBS_None, // INWRdA = 348
2286 CEFBS_HasSRAM, // LDDWRdPtrQ = 349
2287 CEFBS_HasSRAM, // LDDWRdYQ = 350
2288 CEFBS_None, // LDIWRdK = 351
2289 CEFBS_HasSRAM_HasNonTinyEncoding, // LDSWRdK = 352
2290 CEFBS_HasSRAM, // LDWRdPtr = 353
2291 CEFBS_HasSRAM, // LDWRdPtrPd = 354
2292 CEFBS_HasSRAM, // LDWRdPtrPi = 355
2293 CEFBS_HasLPM, // LPMBRdZ = 356
2294 CEFBS_HasLPM, // LPMWRdZ = 357
2295 CEFBS_HasLPMX, // LPMWRdZPi = 358
2296 CEFBS_None, // LSLBNRd = 359
2297 CEFBS_None, // LSLWHiRd = 360
2298 CEFBS_None, // LSLWNRd = 361
2299 CEFBS_None, // LSLWRd = 362
2300 CEFBS_None, // LSRBNRd = 363
2301 CEFBS_None, // LSRWLoRd = 364
2302 CEFBS_None, // LSRWNRd = 365
2303 CEFBS_None, // LSRWRd = 366
2304 CEFBS_None, // Lsl16 = 367
2305 CEFBS_None, // Lsl32 = 368
2306 CEFBS_None, // Lsl8 = 369
2307 CEFBS_None, // Lsr16 = 370
2308 CEFBS_None, // Lsr32 = 371
2309 CEFBS_None, // Lsr8 = 372
2310 CEFBS_None, // NEGWRd = 373
2311 CEFBS_None, // ORIWRdK = 374
2312 CEFBS_None, // ORWRdRr = 375
2313 CEFBS_None, // OUTWARr = 376
2314 CEFBS_HasSRAM, // POPWRd = 377
2315 CEFBS_HasSRAM, // PUSHWRr = 378
2316 CEFBS_HasNonTinyEncoding, // ROLBRdR1 = 379
2317 CEFBS_HasTinyEncoding, // ROLBRdR17 = 380
2318 CEFBS_None, // ROLWRd = 381
2319 CEFBS_None, // RORBRd = 382
2320 CEFBS_None, // RORWRd = 383
2321 CEFBS_None, // Rol16 = 384
2322 CEFBS_None, // Rol8 = 385
2323 CEFBS_None, // Ror16 = 386
2324 CEFBS_None, // Ror8 = 387
2325 CEFBS_None, // SBCIWRdK = 388
2326 CEFBS_None, // SBCWRdRr = 389
2327 CEFBS_None, // SEXT = 390
2328 CEFBS_None, // SPREAD = 391
2329 CEFBS_None, // SPWRITE = 392
2330 CEFBS_None, // STDSPQRr = 393
2331 CEFBS_HasSRAM, // STDWPtrQRr = 394
2332 CEFBS_None, // STDWSPQRr = 395
2333 CEFBS_HasSRAM_HasNonTinyEncoding, // STSWKRr = 396
2334 CEFBS_HasSRAM, // STWPtrPdRr = 397
2335 CEFBS_HasSRAM, // STWPtrPiRr = 398
2336 CEFBS_HasSRAM, // STWPtrRr = 399
2337 CEFBS_None, // SUBIWRdK = 400
2338 CEFBS_None, // SUBWRdRr = 401
2339 CEFBS_None, // Select16 = 402
2340 CEFBS_None, // Select8 = 403
2341 CEFBS_None, // ZEXT = 404
2342 CEFBS_None, // ADCRdRr = 405
2343 CEFBS_None, // ADDRdRr = 406
2344 CEFBS_HasADDSUBIW, // ADIWRdK = 407
2345 CEFBS_None, // ANDIRdK = 408
2346 CEFBS_None, // ANDRdRr = 409
2347 CEFBS_None, // ASRRd = 410
2348 CEFBS_None, // BCLRs = 411
2349 CEFBS_None, // BLD = 412
2350 CEFBS_None, // BRBCsk = 413
2351 CEFBS_None, // BRBSsk = 414
2352 CEFBS_HasBREAK, // BREAK = 415
2353 CEFBS_None, // BREQk = 416
2354 CEFBS_None, // BRGEk = 417
2355 CEFBS_None, // BRLOk = 418
2356 CEFBS_None, // BRLTk = 419
2357 CEFBS_None, // BRMIk = 420
2358 CEFBS_None, // BRNEk = 421
2359 CEFBS_None, // BRPLk = 422
2360 CEFBS_None, // BRSHk = 423
2361 CEFBS_None, // BSETs = 424
2362 CEFBS_None, // BST = 425
2363 CEFBS_HasJMPCALL, // CALLk = 426
2364 CEFBS_None, // CBIAb = 427
2365 CEFBS_None, // COMRd = 428
2366 CEFBS_None, // CPCRdRr = 429
2367 CEFBS_None, // CPIRdK = 430
2368 CEFBS_None, // CPRdRr = 431
2369 CEFBS_None, // CPSE = 432
2370 CEFBS_None, // DECRd = 433
2371 CEFBS_HasDES, // DESK = 434
2372 CEFBS_HasEIJMPCALL, // EICALL = 435
2373 CEFBS_HasEIJMPCALL, // EIJMP = 436
2374 CEFBS_HasELPM, // ELPM = 437
2375 CEFBS_HasELPMX, // ELPMRdZ = 438
2376 CEFBS_HasELPMX, // ELPMRdZPi = 439
2377 CEFBS_None, // EORRdRr = 440
2378 CEFBS_SupportsMultiplication, // FMUL = 441
2379 CEFBS_SupportsMultiplication, // FMULS = 442
2380 CEFBS_SupportsMultiplication, // FMULSU = 443
2381 CEFBS_HasIJMPCALL, // ICALL = 444
2382 CEFBS_HasIJMPCALL, // IJMP = 445
2383 CEFBS_None, // INCRd = 446
2384 CEFBS_None, // INRdA = 447
2385 CEFBS_HasJMPCALL, // JMPk = 448
2386 CEFBS_SupportsRMW, // LACZRd = 449
2387 CEFBS_SupportsRMW, // LASZRd = 450
2388 CEFBS_SupportsRMW, // LATZRd = 451
2389 CEFBS_HasSRAM_HasNonTinyEncoding, // LDDRdPtrQ = 452
2390 CEFBS_None, // LDIRdK = 453
2391 CEFBS_HasSRAM, // LDRdPtr = 454
2392 CEFBS_HasSRAM, // LDRdPtrPd = 455
2393 CEFBS_HasSRAM, // LDRdPtrPi = 456
2394 CEFBS_HasSRAM_HasNonTinyEncoding, // LDSRdK = 457
2395 CEFBS_HasSRAM_HasTinyEncoding, // LDSRdKTiny = 458
2396 CEFBS_HasLPM, // LPM = 459
2397 CEFBS_HasLPMX, // LPMRdZ = 460
2398 CEFBS_HasLPMX, // LPMRdZPi = 461
2399 CEFBS_None, // LSRRd = 462
2400 CEFBS_None, // MOVRdRr = 463
2401 CEFBS_HasMOVW, // MOVWRdRr = 464
2402 CEFBS_SupportsMultiplication, // MULRdRr = 465
2403 CEFBS_SupportsMultiplication, // MULSRdRr = 466
2404 CEFBS_SupportsMultiplication, // MULSURdRr = 467
2405 CEFBS_None, // NEGRd = 468
2406 CEFBS_None, // NOP = 469
2407 CEFBS_None, // ORIRdK = 470
2408 CEFBS_None, // ORRdRr = 471
2409 CEFBS_None, // OUTARr = 472
2410 CEFBS_HasSRAM, // POPRd = 473
2411 CEFBS_HasSRAM, // PUSHRr = 474
2412 CEFBS_None, // RCALLk = 475
2413 CEFBS_None, // RET = 476
2414 CEFBS_None, // RETI = 477
2415 CEFBS_None, // RJMPk = 478
2416 CEFBS_None, // RORRd = 479
2417 CEFBS_None, // SBCIRdK = 480
2418 CEFBS_None, // SBCRdRr = 481
2419 CEFBS_None, // SBIAb = 482
2420 CEFBS_None, // SBICAb = 483
2421 CEFBS_None, // SBISAb = 484
2422 CEFBS_HasADDSUBIW, // SBIWRdK = 485
2423 CEFBS_None, // SBRCRrB = 486
2424 CEFBS_None, // SBRSRrB = 487
2425 CEFBS_None, // SLEEP = 488
2426 CEFBS_HasSPM, // SPM = 489
2427 CEFBS_HasSPMX, // SPMZPi = 490
2428 CEFBS_HasSRAM_HasNonTinyEncoding, // STDPtrQRr = 491
2429 CEFBS_HasSRAM, // STPtrPdRr = 492
2430 CEFBS_HasSRAM, // STPtrPiRr = 493
2431 CEFBS_HasSRAM, // STPtrRr = 494
2432 CEFBS_HasSRAM_HasNonTinyEncoding, // STSKRr = 495
2433 CEFBS_HasSRAM_HasTinyEncoding, // STSKRrTiny = 496
2434 CEFBS_None, // SUBIRdK = 497
2435 CEFBS_None, // SUBRdRr = 498
2436 CEFBS_None, // SWAPRd = 499
2437 CEFBS_None, // WDR = 500
2438 CEFBS_SupportsRMW, // XCHZRd = 501
2439 };
2440
2441 assert(Opcode < 502);
2442 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
2443}
2444
2445} // end namespace llvm::AVR_MC
2446#endif // GET_COMPUTE_FEATURES
2447
2448#ifdef GET_AVAILABLE_OPCODE_CHECKER
2449#undef GET_AVAILABLE_OPCODE_CHECKER
2450namespace llvm::AVR_MC {
2451bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
2452 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
2453 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
2454 FeatureBitset MissingFeatures =
2455 (AvailableFeatures & RequiredFeatures) ^
2456 RequiredFeatures;
2457 return !MissingFeatures.any();
2458}
2459} // end namespace llvm::AVR_MC
2460#endif // GET_AVAILABLE_OPCODE_CHECKER
2461
2462#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
2463#undef ENABLE_INSTR_PREDICATE_VERIFIER
2464#include <sstream>
2465
2466namespace llvm::AVR_MC {
2467#ifndef NDEBUG
2468static const char *SubtargetFeatureNames[] = {
2469 "Feature_HasADDSUBIW",
2470 "Feature_HasBREAK",
2471 "Feature_HasDES",
2472 "Feature_HasEIJMPCALL",
2473 "Feature_HasELPM",
2474 "Feature_HasELPMX",
2475 "Feature_HasIJMPCALL",
2476 "Feature_HasJMPCALL",
2477 "Feature_HasLPM",
2478 "Feature_HasLPMX",
2479 "Feature_HasMOVW",
2480 "Feature_HasNonTinyEncoding",
2481 "Feature_HasSPM",
2482 "Feature_HasSPMX",
2483 "Feature_HasSRAM",
2484 "Feature_HasSmallStack",
2485 "Feature_HasTinyEncoding",
2486 "Feature_SupportsMultiplication",
2487 "Feature_SupportsRMW",
2488 nullptr
2489};
2490
2491#endif // NDEBUG
2492
2493void verifyInstructionPredicates(
2494 unsigned Opcode, const FeatureBitset &Features) {
2495#ifndef NDEBUG
2496 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
2497 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
2498 FeatureBitset MissingFeatures =
2499 (AvailableFeatures & RequiredFeatures) ^
2500 RequiredFeatures;
2501 if (MissingFeatures.any()) {
2502 std::ostringstream Msg;
2503 Msg << "Attempting to emit " << &AVRInstrNameData[AVRInstrNameIndices[Opcode]]
2504 << " instruction but the ";
2505 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
2506 if (MissingFeatures.test(i))
2507 Msg << SubtargetFeatureNames[i] << " ";
2508 Msg << "predicate(s) are not met";
2509 report_fatal_error(Msg.str().c_str());
2510 }
2511#endif // NDEBUG
2512}
2513} // end namespace llvm::AVR_MC
2514#endif // ENABLE_INSTR_PREDICATE_VERIFIER
2515
2516