1//===-- AVRInstrInfo.h - AVR Instruction Information ------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the AVR implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_AVR_INSTR_INFO_H
14#define LLVM_AVR_INSTR_INFO_H
15
16#include "llvm/CodeGen/TargetInstrInfo.h"
17
18#include "AVRRegisterInfo.h"
19
20#define GET_INSTRINFO_HEADER
21#include "AVRGenInstrInfo.inc"
22#undef GET_INSTRINFO_HEADER
23
24namespace llvm {
25
26class AVRSubtarget;
27
28namespace AVRCC {
29
30/// AVR specific condition codes.
31/// These correspond to `AVR_*_COND` in `AVRInstrInfo.td`.
32/// They must be kept in synch.
33enum CondCodes {
34 COND_EQ, //!< Equal
35 COND_NE, //!< Not equal
36 COND_GE, //!< Greater than or equal
37 COND_LT, //!< Less than
38 COND_SH, //!< Unsigned same or higher
39 COND_LO, //!< Unsigned lower
40 COND_MI, //!< Minus
41 COND_PL, //!< Plus
42 COND_INVALID
43};
44
45} // end of namespace AVRCC
46
47namespace AVRII {
48
49/// Specifies a target operand flag.
50enum TOF {
51 MO_NO_FLAG,
52
53 /// On a symbol operand, this represents the lo part.
54 MO_LO = (1 << 1),
55
56 /// On a symbol operand, this represents the hi part.
57 MO_HI = (1 << 2),
58
59 /// On a symbol operand, this represents it has to be negated.
60 MO_NEG = (1 << 3)
61};
62
63} // end of namespace AVRII
64
65/// Utilities related to the AVR instruction set.
66class AVRInstrInfo : public AVRGenInstrInfo {
67public:
68 explicit AVRInstrInfo(AVRSubtarget &STI);
69
70 const AVRRegisterInfo &getRegisterInfo() const { return RI; }
71 const MCInstrDesc &getBrCond(AVRCC::CondCodes CC) const;
72 AVRCC::CondCodes getCondFromBranchOpc(unsigned Opc) const;
73 AVRCC::CondCodes getOppositeCondition(AVRCC::CondCodes CC) const;
74 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
75
76 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
77 const DebugLoc &DL, Register DestReg, Register SrcReg,
78 bool KillSrc, bool RenamableDest = false,
79 bool RenamableSrc = false) const override;
80 void storeRegToStackSlot(
81 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg,
82 bool isKill, int FrameIndex, const TargetRegisterClass *RC,
83 const TargetRegisterInfo *TRI, Register VReg,
84 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
85 void loadRegFromStackSlot(
86 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg,
87 int FrameIndex, const TargetRegisterClass *RC,
88 const TargetRegisterInfo *TRI, Register VReg,
89 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
90 Register isLoadFromStackSlot(const MachineInstr &MI,
91 int &FrameIndex) const override;
92 Register isStoreToStackSlot(const MachineInstr &MI,
93 int &FrameIndex) const override;
94
95 // Branch analysis.
96 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
97 MachineBasicBlock *&FBB,
98 SmallVectorImpl<MachineOperand> &Cond,
99 bool AllowModify = false) const override;
100 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
101 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
102 const DebugLoc &DL,
103 int *BytesAdded = nullptr) const override;
104 unsigned removeBranch(MachineBasicBlock &MBB,
105 int *BytesRemoved = nullptr) const override;
106 bool
107 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
108
109 MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
110
111 bool isBranchOffsetInRange(unsigned BranchOpc,
112 int64_t BrOffset) const override;
113
114 void insertIndirectBranch(MachineBasicBlock &MBB,
115 MachineBasicBlock &NewDestBB,
116 MachineBasicBlock &RestoreBB, const DebugLoc &DL,
117 int64_t BrOffset, RegScavenger *RS) const override;
118
119private:
120 const AVRRegisterInfo RI;
121
122protected:
123 const AVRSubtarget &STI;
124};
125
126} // end namespace llvm
127
128#endif // LLVM_AVR_INSTR_INFO_H
129