1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register Enum Values *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_REGINFO_ENUM
11#undef GET_REGINFO_ENUM
12
13namespace llvm {
14
15class MCRegisterClass;
16extern const MCRegisterClass AVRMCRegisterClasses[];
17
18namespace AVR {
19enum : unsigned {
20 NoRegister,
21 SP = 1,
22 SPH = 2,
23 SPL = 3,
24 SREG = 4,
25 R0 = 5,
26 R1 = 6,
27 R2 = 7,
28 R3 = 8,
29 R4 = 9,
30 R5 = 10,
31 R6 = 11,
32 R7 = 12,
33 R8 = 13,
34 R9 = 14,
35 R10 = 15,
36 R11 = 16,
37 R12 = 17,
38 R13 = 18,
39 R14 = 19,
40 R15 = 20,
41 R16 = 21,
42 R17 = 22,
43 R18 = 23,
44 R19 = 24,
45 R20 = 25,
46 R21 = 26,
47 R22 = 27,
48 R23 = 28,
49 R24 = 29,
50 R25 = 30,
51 R26 = 31,
52 R27 = 32,
53 R28 = 33,
54 R29 = 34,
55 R30 = 35,
56 R31 = 36,
57 R1R0 = 37,
58 R3R2 = 38,
59 R5R4 = 39,
60 R7R6 = 40,
61 R9R8 = 41,
62 R10R9 = 42,
63 R11R10 = 43,
64 R12R11 = 44,
65 R13R12 = 45,
66 R14R13 = 46,
67 R15R14 = 47,
68 R16R15 = 48,
69 R17R16 = 49,
70 R18R17 = 50,
71 R19R18 = 51,
72 R20R19 = 52,
73 R21R20 = 53,
74 R22R21 = 54,
75 R23R22 = 55,
76 R24R23 = 56,
77 R25R24 = 57,
78 R26R25 = 58,
79 R27R26 = 59,
80 R29R28 = 60,
81 R31R30 = 61,
82 NUM_TARGET_REGS // 62
83};
84} // end namespace AVR
85
86// Register classes
87
88namespace AVR {
89enum {
90 GPR8RegClassID = 0,
91 GPR8loRegClassID = 1,
92 LD8RegClassID = 2,
93 LD8loRegClassID = 3,
94 CCRRegClassID = 4,
95 DREGSRegClassID = 5,
96 DREGSMOVWRegClassID = 6,
97 DREGS_with_sub_hi_in_LD8RegClassID = 7,
98 DREGS_with_sub_lo_in_LD8RegClassID = 8,
99 DREGS_with_sub_lo_in_GPR8loRegClassID = 9,
100 DREGS_with_sub_hi_in_GPR8loRegClassID = 10,
101 DLDREGSRegClassID = 11,
102 DREGS_with_sub_hi_in_LD8loRegClassID = 12,
103 DREGS_with_sub_lo_in_LD8loRegClassID = 13,
104 DREGSloRegClassID = 14,
105 DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8RegClassID = 15,
106 DREGSLD8loRegClassID = 16,
107 IWREGSRegClassID = 17,
108 PTRREGSRegClassID = 18,
109 PTRDISPREGSRegClassID = 19,
110 DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loRegClassID = 20,
111 GPRSPRegClassID = 21,
112 ZREGRegClassID = 22,
113
114};
115} // end namespace AVR
116
117
118// Register alternate name indices
119
120namespace AVR {
121enum {
122 NoRegAltName, // 0
123 ptr, // 1
124 NUM_TARGET_REG_ALT_NAMES = 2
125};
126} // end namespace AVR
127
128
129// Subregister indices
130
131namespace AVR {
132enum : uint16_t {
133 NoSubRegister,
134 sub_hi, // 1
135 sub_lo, // 2
136 NUM_TARGET_SUBREGS
137};
138} // end namespace AVR
139
140// Register pressure sets enum.
141namespace AVR {
142enum RegisterPressureSets {
143 CCR = 0,
144 DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo = 1,
145 GPRSP = 2,
146 IWREGS = 3,
147 LD8lo = 4,
148 LD8 = 5,
149 GPR8lo = 6,
150 GPR8lo_with_LD8lo = 7,
151 GPR8 = 8,
152};
153} // end namespace AVR
154
155} // end namespace llvm
156
157#endif // GET_REGINFO_ENUM
158
159/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
160|* *|
161|* MC Register Information *|
162|* *|
163|* Automatically generated file, do not edit! *|
164|* *|
165\*===----------------------------------------------------------------------===*/
166
167
168#ifdef GET_REGINFO_MC_DESC
169#undef GET_REGINFO_MC_DESC
170
171namespace llvm {
172
173extern const int16_t AVRRegDiffLists[] = {
174 /* 0 */ -2, 0,
175 /* 2 */ 2, -1, 0,
176 /* 5 */ -32, 1, 0,
177 /* 8 */ -31, 1, 0,
178 /* 11 */ -30, 1, 0,
179 /* 14 */ -29, 1, 0,
180 /* 17 */ -28, 1, 0,
181 /* 20 */ -27, 1, 0,
182 /* 23 */ -26, 1, 0,
183 /* 26 */ 27, 1, 0,
184 /* 29 */ 25, 0,
185 /* 31 */ 26, 0,
186 /* 33 */ 27, 0,
187 /* 35 */ 28, 0,
188 /* 37 */ 29, 0,
189 /* 39 */ 30, 0,
190 /* 41 */ 31, 0,
191 /* 43 */ 32, 0,
192};
193
194extern const LaneBitmask AVRLaneMaskLists[] = {
195 /* 0 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000001),
196 /* 2 */ LaneBitmask(0xFFFFFFFFFFFFFFFF),
197};
198
199extern const uint16_t AVRSubRegIdxLists[] = {
200 /* 0 */ 2, 1,
201};
202
203
204#ifdef __GNUC__
205#pragma GCC diagnostic push
206#pragma GCC diagnostic ignored "-Woverlength-strings"
207#endif
208extern const char AVRRegStrings[] = {
209 /* 0 */ "R11R10\000"
210 /* 7 */ "R21R20\000"
211 /* 14 */ "R31R30\000"
212 /* 21 */ "R1R0\000"
213 /* 26 */ "R12R11\000"
214 /* 33 */ "R22R21\000"
215 /* 40 */ "R31\000"
216 /* 44 */ "R1\000"
217 /* 47 */ "R13R12\000"
218 /* 54 */ "R23R22\000"
219 /* 61 */ "R3R2\000"
220 /* 66 */ "R14R13\000"
221 /* 73 */ "R24R23\000"
222 /* 80 */ "R3\000"
223 /* 83 */ "R15R14\000"
224 /* 90 */ "R25R24\000"
225 /* 97 */ "R5R4\000"
226 /* 102 */ "R16R15\000"
227 /* 109 */ "R26R25\000"
228 /* 116 */ "R5\000"
229 /* 119 */ "R17R16\000"
230 /* 126 */ "R27R26\000"
231 /* 133 */ "R7R6\000"
232 /* 138 */ "R18R17\000"
233 /* 145 */ "R27\000"
234 /* 149 */ "R7\000"
235 /* 152 */ "R19R18\000"
236 /* 159 */ "R29R28\000"
237 /* 166 */ "R9R8\000"
238 /* 171 */ "R20R19\000"
239 /* 178 */ "R29\000"
240 /* 182 */ "R10R9\000"
241 /* 188 */ "SREG\000"
242 /* 193 */ "SPH\000"
243 /* 197 */ "SPL\000"
244 /* 201 */ "SP\000"
245};
246#ifdef __GNUC__
247#pragma GCC diagnostic pop
248#endif
249
250extern const MCRegisterDesc AVRRegDesc[] = { // Descriptors
251 { 6, 0, 0, 0, 0, 0, 0, 0 },
252 { 201, 2, 1, 0, 24576, 0, 0, 0 },
253 { 193, 1, 3, 2, 4097, 2, 0, 0 },
254 { 197, 1, 0, 2, 4096, 2, 0, 0 },
255 { 188, 1, 1, 2, 4098, 2, 0, 0 },
256 { 23, 1, 43, 2, 4099, 2, 0, 0 },
257 { 44, 1, 41, 2, 4100, 2, 0, 0 },
258 { 63, 1, 41, 2, 4101, 2, 0, 0 },
259 { 80, 1, 39, 2, 4102, 2, 0, 0 },
260 { 99, 1, 39, 2, 4103, 2, 0, 0 },
261 { 116, 1, 37, 2, 4104, 2, 0, 0 },
262 { 135, 1, 37, 2, 4105, 2, 0, 0 },
263 { 149, 1, 35, 2, 4106, 2, 0, 0 },
264 { 168, 1, 35, 2, 4107, 2, 0, 0 },
265 { 185, 1, 26, 2, 4108, 2, 0, 0 },
266 { 3, 1, 26, 2, 4109, 2, 0, 0 },
267 { 29, 1, 26, 2, 4110, 2, 0, 0 },
268 { 50, 1, 26, 2, 4111, 2, 0, 0 },
269 { 69, 1, 26, 2, 4112, 2, 0, 0 },
270 { 86, 1, 26, 2, 4113, 2, 0, 0 },
271 { 105, 1, 26, 2, 4114, 2, 0, 0 },
272 { 122, 1, 26, 2, 4115, 2, 0, 0 },
273 { 141, 1, 26, 2, 4116, 2, 0, 0 },
274 { 155, 1, 26, 2, 4117, 2, 0, 0 },
275 { 174, 1, 26, 2, 4118, 2, 0, 0 },
276 { 10, 1, 26, 2, 4119, 2, 0, 0 },
277 { 36, 1, 26, 2, 4120, 2, 0, 0 },
278 { 57, 1, 26, 2, 4121, 2, 0, 0 },
279 { 76, 1, 26, 2, 4122, 2, 0, 0 },
280 { 93, 1, 26, 2, 4123, 2, 0, 0 },
281 { 112, 1, 26, 2, 4124, 2, 0, 0 },
282 { 129, 1, 26, 2, 4125, 2, 0, 0 },
283 { 145, 1, 33, 2, 4126, 2, 0, 0 },
284 { 162, 1, 33, 2, 4127, 2, 0, 0 },
285 { 178, 1, 31, 2, 4128, 2, 0, 0 },
286 { 17, 1, 31, 2, 4129, 2, 0, 0 },
287 { 40, 1, 29, 2, 4130, 2, 0, 0 },
288 { 21, 5, 1, 0, 24579, 0, 0, 0 },
289 { 61, 8, 1, 0, 24581, 0, 0, 0 },
290 { 97, 11, 1, 0, 24583, 0, 0, 0 },
291 { 133, 14, 1, 0, 24585, 0, 0, 0 },
292 { 166, 17, 1, 0, 24587, 0, 0, 0 },
293 { 182, 17, 1, 0, 24588, 0, 0, 0 },
294 { 0, 17, 1, 0, 24589, 0, 0, 0 },
295 { 26, 17, 1, 0, 24590, 0, 0, 0 },
296 { 47, 17, 1, 0, 24591, 0, 0, 0 },
297 { 66, 17, 1, 0, 24592, 0, 0, 0 },
298 { 83, 17, 1, 0, 24593, 0, 0, 0 },
299 { 102, 17, 1, 0, 24594, 0, 0, 0 },
300 { 119, 17, 1, 0, 24595, 0, 0, 0 },
301 { 138, 17, 1, 0, 24596, 0, 0, 0 },
302 { 152, 17, 1, 0, 24597, 0, 0, 0 },
303 { 171, 17, 1, 0, 24598, 0, 0, 0 },
304 { 7, 17, 1, 0, 24599, 0, 0, 0 },
305 { 33, 17, 1, 0, 24600, 0, 0, 0 },
306 { 54, 17, 1, 0, 24601, 0, 0, 0 },
307 { 73, 17, 1, 0, 24602, 0, 0, 0 },
308 { 90, 17, 1, 0, 24603, 0, 0, 0 },
309 { 109, 17, 1, 0, 24604, 0, 0, 0 },
310 { 126, 17, 1, 0, 24605, 0, 0, 0 },
311 { 159, 20, 1, 0, 24607, 0, 0, 0 },
312 { 14, 23, 1, 0, 24609, 0, 0, 0 },
313};
314
315extern const MCPhysReg AVRRegUnitRoots[][2] = {
316 { AVR::SPL },
317 { AVR::SPH },
318 { AVR::SREG },
319 { AVR::R0 },
320 { AVR::R1 },
321 { AVR::R2 },
322 { AVR::R3 },
323 { AVR::R4 },
324 { AVR::R5 },
325 { AVR::R6 },
326 { AVR::R7 },
327 { AVR::R8 },
328 { AVR::R9 },
329 { AVR::R10 },
330 { AVR::R11 },
331 { AVR::R12 },
332 { AVR::R13 },
333 { AVR::R14 },
334 { AVR::R15 },
335 { AVR::R16 },
336 { AVR::R17 },
337 { AVR::R18 },
338 { AVR::R19 },
339 { AVR::R20 },
340 { AVR::R21 },
341 { AVR::R22 },
342 { AVR::R23 },
343 { AVR::R24 },
344 { AVR::R25 },
345 { AVR::R26 },
346 { AVR::R27 },
347 { AVR::R28 },
348 { AVR::R29 },
349 { AVR::R30 },
350 { AVR::R31 },
351};
352
353namespace { // Register classes...
354 // GPR8 Register Class...
355 const MCPhysReg GPR8[] = {
356 AVR::R24, AVR::R25, AVR::R18, AVR::R19, AVR::R20, AVR::R21, AVR::R22, AVR::R23, AVR::R30, AVR::R31, AVR::R26, AVR::R27, AVR::R28, AVR::R29, AVR::R17, AVR::R16, AVR::R15, AVR::R14, AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8, AVR::R7, AVR::R6, AVR::R5, AVR::R4, AVR::R3, AVR::R2, AVR::R0, AVR::R1,
357 };
358
359 // GPR8 Bit set.
360 const uint8_t GPR8Bits[] = {
361 0xe0, 0xff, 0xff, 0xff, 0x1f,
362 };
363
364 // GPR8lo Register Class...
365 const MCPhysReg GPR8lo[] = {
366 AVR::R15, AVR::R14, AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8, AVR::R7, AVR::R6, AVR::R5, AVR::R4, AVR::R3, AVR::R2, AVR::R0, AVR::R1,
367 };
368
369 // GPR8lo Bit set.
370 const uint8_t GPR8loBits[] = {
371 0xe0, 0xff, 0x1f,
372 };
373
374 // LD8 Register Class...
375 const MCPhysReg LD8[] = {
376 AVR::R24, AVR::R25, AVR::R18, AVR::R19, AVR::R20, AVR::R21, AVR::R22, AVR::R23, AVR::R30, AVR::R31, AVR::R26, AVR::R27, AVR::R28, AVR::R29, AVR::R17, AVR::R16,
377 };
378
379 // LD8 Bit set.
380 const uint8_t LD8Bits[] = {
381 0x00, 0x00, 0xe0, 0xff, 0x1f,
382 };
383
384 // LD8lo Register Class...
385 const MCPhysReg LD8lo[] = {
386 AVR::R23, AVR::R22, AVR::R21, AVR::R20, AVR::R19, AVR::R18, AVR::R17, AVR::R16,
387 };
388
389 // LD8lo Bit set.
390 const uint8_t LD8loBits[] = {
391 0x00, 0x00, 0xe0, 0x1f,
392 };
393
394 // CCR Register Class...
395 const MCPhysReg CCR[] = {
396 AVR::SREG,
397 };
398
399 // CCR Bit set.
400 const uint8_t CCRBits[] = {
401 0x10,
402 };
403
404 // DREGS Register Class...
405 const MCPhysReg DREGS[] = {
406 AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R31R30, AVR::R27R26, AVR::R29R28, AVR::R17R16, AVR::R15R14, AVR::R13R12, AVR::R11R10, AVR::R9R8, AVR::R7R6, AVR::R5R4, AVR::R3R2, AVR::R1R0, AVR::R26R25, AVR::R24R23, AVR::R22R21, AVR::R20R19, AVR::R18R17, AVR::R16R15, AVR::R14R13, AVR::R12R11, AVR::R10R9,
407 };
408
409 // DREGS Bit set.
410 const uint8_t DREGSBits[] = {
411 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0x3f,
412 };
413
414 // DREGSMOVW Register Class...
415 const MCPhysReg DREGSMOVW[] = {
416 AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R31R30, AVR::R27R26, AVR::R29R28, AVR::R17R16, AVR::R15R14, AVR::R13R12, AVR::R11R10, AVR::R9R8, AVR::R7R6, AVR::R5R4, AVR::R3R2, AVR::R1R0,
417 };
418
419 // DREGSMOVW Bit set.
420 const uint8_t DREGSMOVWBits[] = {
421 0x00, 0x00, 0x00, 0x00, 0xe0, 0xab, 0xaa, 0x3a,
422 };
423
424 // DREGS_with_sub_hi_in_LD8 Register Class...
425 const MCPhysReg DREGS_with_sub_hi_in_LD8[] = {
426 AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R31R30, AVR::R27R26, AVR::R29R28, AVR::R17R16, AVR::R26R25, AVR::R24R23, AVR::R22R21, AVR::R20R19, AVR::R18R17, AVR::R16R15,
427 };
428
429 // DREGS_with_sub_hi_in_LD8 Bit set.
430 const uint8_t DREGS_with_sub_hi_in_LD8Bits[] = {
431 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x3f,
432 };
433
434 // DREGS_with_sub_lo_in_LD8 Register Class...
435 const MCPhysReg DREGS_with_sub_lo_in_LD8[] = {
436 AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R31R30, AVR::R27R26, AVR::R29R28, AVR::R17R16, AVR::R26R25, AVR::R24R23, AVR::R22R21, AVR::R20R19, AVR::R18R17,
437 };
438
439 // DREGS_with_sub_lo_in_LD8 Bit set.
440 const uint8_t DREGS_with_sub_lo_in_LD8Bits[] = {
441 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x3f,
442 };
443
444 // DREGS_with_sub_lo_in_GPR8lo Register Class...
445 const MCPhysReg DREGS_with_sub_lo_in_GPR8lo[] = {
446 AVR::R15R14, AVR::R13R12, AVR::R11R10, AVR::R9R8, AVR::R7R6, AVR::R5R4, AVR::R3R2, AVR::R1R0, AVR::R16R15, AVR::R14R13, AVR::R12R11, AVR::R10R9,
447 };
448
449 // DREGS_with_sub_lo_in_GPR8lo Bit set.
450 const uint8_t DREGS_with_sub_lo_in_GPR8loBits[] = {
451 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x01,
452 };
453
454 // DREGS_with_sub_hi_in_GPR8lo Register Class...
455 const MCPhysReg DREGS_with_sub_hi_in_GPR8lo[] = {
456 AVR::R15R14, AVR::R13R12, AVR::R11R10, AVR::R9R8, AVR::R7R6, AVR::R5R4, AVR::R3R2, AVR::R1R0, AVR::R14R13, AVR::R12R11, AVR::R10R9,
457 };
458
459 // DREGS_with_sub_hi_in_GPR8lo Bit set.
460 const uint8_t DREGS_with_sub_hi_in_GPR8loBits[] = {
461 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff,
462 };
463
464 // DLDREGS Register Class...
465 const MCPhysReg DLDREGS[] = {
466 AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R31R30, AVR::R27R26, AVR::R29R28, AVR::R17R16,
467 };
468
469 // DLDREGS Bit set.
470 const uint8_t DLDREGSBits[] = {
471 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0x3a,
472 };
473
474 // DREGS_with_sub_hi_in_LD8lo Register Class...
475 const MCPhysReg DREGS_with_sub_hi_in_LD8lo[] = {
476 AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R17R16, AVR::R22R21, AVR::R20R19, AVR::R18R17, AVR::R16R15,
477 };
478
479 // DREGS_with_sub_hi_in_LD8lo Bit set.
480 const uint8_t DREGS_with_sub_hi_in_LD8loBits[] = {
481 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
482 };
483
484 // DREGS_with_sub_lo_in_LD8lo Register Class...
485 const MCPhysReg DREGS_with_sub_lo_in_LD8lo[] = {
486 AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R17R16, AVR::R24R23, AVR::R22R21, AVR::R20R19, AVR::R18R17,
487 };
488
489 // DREGS_with_sub_lo_in_LD8lo Bit set.
490 const uint8_t DREGS_with_sub_lo_in_LD8loBits[] = {
491 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01,
492 };
493
494 // DREGSlo Register Class...
495 const MCPhysReg DREGSlo[] = {
496 AVR::R15R14, AVR::R13R12, AVR::R11R10, AVR::R9R8, AVR::R7R6, AVR::R5R4, AVR::R3R2, AVR::R1R0,
497 };
498
499 // DREGSlo Bit set.
500 const uint8_t DREGSloBits[] = {
501 0x00, 0x00, 0x00, 0x00, 0xe0, 0xab,
502 };
503
504 // DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8 Register Class...
505 const MCPhysReg DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8[] = {
506 AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R17R16, AVR::R22R21, AVR::R20R19, AVR::R18R17,
507 };
508
509 // DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8 Bit set.
510 const uint8_t DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8Bits[] = {
511 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe,
512 };
513
514 // DREGSLD8lo Register Class...
515 const MCPhysReg DREGSLD8lo[] = {
516 AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R17R16,
517 };
518
519 // DREGSLD8lo Bit set.
520 const uint8_t DREGSLD8loBits[] = {
521 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa,
522 };
523
524 // IWREGS Register Class...
525 const MCPhysReg IWREGS[] = {
526 AVR::R25R24, AVR::R31R30, AVR::R27R26, AVR::R29R28,
527 };
528
529 // IWREGS Bit set.
530 const uint8_t IWREGSBits[] = {
531 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3a,
532 };
533
534 // PTRREGS Register Class...
535 const MCPhysReg PTRREGS[] = {
536 AVR::R27R26, AVR::R29R28, AVR::R31R30,
537 };
538
539 // PTRREGS Bit set.
540 const uint8_t PTRREGSBits[] = {
541 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38,
542 };
543
544 // PTRDISPREGS Register Class...
545 const MCPhysReg PTRDISPREGS[] = {
546 AVR::R31R30, AVR::R29R28,
547 };
548
549 // PTRDISPREGS Bit set.
550 const uint8_t PTRDISPREGSBits[] = {
551 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30,
552 };
553
554 // DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo Register Class...
555 const MCPhysReg DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo[] = {
556 AVR::R16R15,
557 };
558
559 // DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo Bit set.
560 const uint8_t DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loBits[] = {
561 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
562 };
563
564 // GPRSP Register Class...
565 const MCPhysReg GPRSP[] = {
566 AVR::SP,
567 };
568
569 // GPRSP Bit set.
570 const uint8_t GPRSPBits[] = {
571 0x02,
572 };
573
574 // ZREG Register Class...
575 const MCPhysReg ZREG[] = {
576 AVR::R31R30,
577 };
578
579 // ZREG Bit set.
580 const uint8_t ZREGBits[] = {
581 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
582 };
583
584} // end anonymous namespace
585
586
587#ifdef __GNUC__
588#pragma GCC diagnostic push
589#pragma GCC diagnostic ignored "-Woverlength-strings"
590#endif
591extern const char AVRRegClassStrings[] = {
592 /* 0 */ "DREGS_with_sub_hi_in_LD8\000"
593 /* 25 */ "DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8\000"
594 /* 81 */ "GPR8\000"
595 /* 86 */ "ZREG\000"
596 /* 91 */ "GPRSP\000"
597 /* 97 */ "CCR\000"
598 /* 101 */ "DLDREGS\000"
599 /* 109 */ "PTRDISPREGS\000"
600 /* 121 */ "PTRREGS\000"
601 /* 129 */ "IWREGS\000"
602 /* 136 */ "DREGSMOVW\000"
603 /* 146 */ "DREGSLD8lo\000"
604 /* 157 */ "DREGS_with_sub_hi_in_LD8lo\000"
605 /* 184 */ "DREGS_with_sub_lo_in_LD8lo\000"
606 /* 211 */ "DREGS_with_sub_hi_in_GPR8lo\000"
607 /* 239 */ "DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo\000"
608 /* 296 */ "DREGSlo\000"
609};
610#ifdef __GNUC__
611#pragma GCC diagnostic pop
612#endif
613
614extern const MCRegisterClass AVRMCRegisterClasses[] = {
615 { GPR8, GPR8Bits, 81, 32, sizeof(GPR8Bits), AVR::GPR8RegClassID, 8, 1, true, false },
616 { GPR8lo, GPR8loBits, 232, 16, sizeof(GPR8loBits), AVR::GPR8loRegClassID, 8, 1, true, false },
617 { LD8, LD8Bits, 21, 16, sizeof(LD8Bits), AVR::LD8RegClassID, 8, 1, true, false },
618 { LD8lo, LD8loBits, 151, 8, sizeof(LD8loBits), AVR::LD8loRegClassID, 8, 1, true, false },
619 { CCR, CCRBits, 97, 1, sizeof(CCRBits), AVR::CCRRegClassID, 8, -1, true, false },
620 { DREGS, DREGSBits, 103, 25, sizeof(DREGSBits), AVR::DREGSRegClassID, 16, 1, true, false },
621 { DREGSMOVW, DREGSMOVWBits, 136, 16, sizeof(DREGSMOVWBits), AVR::DREGSMOVWRegClassID, 16, 1, true, false },
622 { DREGS_with_sub_hi_in_LD8, DREGS_with_sub_hi_in_LD8Bits, 0, 14, sizeof(DREGS_with_sub_hi_in_LD8Bits), AVR::DREGS_with_sub_hi_in_LD8RegClassID, 16, 1, true, false },
623 { DREGS_with_sub_lo_in_LD8, DREGS_with_sub_lo_in_LD8Bits, 56, 13, sizeof(DREGS_with_sub_lo_in_LD8Bits), AVR::DREGS_with_sub_lo_in_LD8RegClassID, 16, 1, true, false },
624 { DREGS_with_sub_lo_in_GPR8lo, DREGS_with_sub_lo_in_GPR8loBits, 268, 12, sizeof(DREGS_with_sub_lo_in_GPR8loBits), AVR::DREGS_with_sub_lo_in_GPR8loRegClassID, 16, 1, true, false },
625 { DREGS_with_sub_hi_in_GPR8lo, DREGS_with_sub_hi_in_GPR8loBits, 211, 11, sizeof(DREGS_with_sub_hi_in_GPR8loBits), AVR::DREGS_with_sub_hi_in_GPR8loRegClassID, 16, 1, true, false },
626 { DLDREGS, DLDREGSBits, 101, 8, sizeof(DLDREGSBits), AVR::DLDREGSRegClassID, 16, 1, true, false },
627 { DREGS_with_sub_hi_in_LD8lo, DREGS_with_sub_hi_in_LD8loBits, 157, 8, sizeof(DREGS_with_sub_hi_in_LD8loBits), AVR::DREGS_with_sub_hi_in_LD8loRegClassID, 16, 1, true, false },
628 { DREGS_with_sub_lo_in_LD8lo, DREGS_with_sub_lo_in_LD8loBits, 184, 8, sizeof(DREGS_with_sub_lo_in_LD8loBits), AVR::DREGS_with_sub_lo_in_LD8loRegClassID, 16, 1, true, false },
629 { DREGSlo, DREGSloBits, 296, 8, sizeof(DREGSloBits), AVR::DREGSloRegClassID, 16, 1, true, false },
630 { DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8, DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8Bits, 25, 7, sizeof(DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8Bits), AVR::DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8RegClassID, 16, 1, true, false },
631 { DREGSLD8lo, DREGSLD8loBits, 146, 4, sizeof(DREGSLD8loBits), AVR::DREGSLD8loRegClassID, 16, 1, true, false },
632 { IWREGS, IWREGSBits, 129, 4, sizeof(IWREGSBits), AVR::IWREGSRegClassID, 16, 1, true, false },
633 { PTRREGS, PTRREGSBits, 121, 3, sizeof(PTRREGSBits), AVR::PTRREGSRegClassID, 16, 1, true, false },
634 { PTRDISPREGS, PTRDISPREGSBits, 109, 2, sizeof(PTRDISPREGSBits), AVR::PTRDISPREGSRegClassID, 16, 1, true, false },
635 { DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo, DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loBits, 239, 1, sizeof(DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loBits), AVR::DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loRegClassID, 16, 1, true, false },
636 { GPRSP, GPRSPBits, 91, 1, sizeof(GPRSPBits), AVR::GPRSPRegClassID, 16, 1, true, false },
637 { ZREG, ZREGBits, 86, 1, sizeof(ZREGBits), AVR::ZREGRegClassID, 16, 1, true, false },
638};
639
640// AVR Dwarf<->LLVM register mappings.
641extern const MCRegisterInfo::DwarfLLVMRegPair AVRDwarfFlavour0Dwarf2L[] = {
642 { 0U, AVR::R1R0 },
643 { 1U, AVR::R1 },
644 { 2U, AVR::R3R2 },
645 { 3U, AVR::R3 },
646 { 4U, AVR::R5R4 },
647 { 5U, AVR::R5 },
648 { 6U, AVR::R7R6 },
649 { 7U, AVR::R7 },
650 { 8U, AVR::R9R8 },
651 { 9U, AVR::R10R9 },
652 { 10U, AVR::R11R10 },
653 { 11U, AVR::R12R11 },
654 { 12U, AVR::R13R12 },
655 { 13U, AVR::R14R13 },
656 { 14U, AVR::R15R14 },
657 { 15U, AVR::R16R15 },
658 { 16U, AVR::R17R16 },
659 { 17U, AVR::R18R17 },
660 { 18U, AVR::R19R18 },
661 { 19U, AVR::R20R19 },
662 { 20U, AVR::R21R20 },
663 { 21U, AVR::R22R21 },
664 { 22U, AVR::R23R22 },
665 { 23U, AVR::R24R23 },
666 { 24U, AVR::R25R24 },
667 { 25U, AVR::R26R25 },
668 { 26U, AVR::R27R26 },
669 { 27U, AVR::R27 },
670 { 28U, AVR::R29R28 },
671 { 29U, AVR::R29 },
672 { 30U, AVR::R31R30 },
673 { 31U, AVR::R31 },
674 { 32U, AVR::SPL },
675 { 33U, AVR::SPH },
676 { 88U, AVR::SREG },
677};
678extern const unsigned AVRDwarfFlavour0Dwarf2LSize = std::size(AVRDwarfFlavour0Dwarf2L);
679
680extern const MCRegisterInfo::DwarfLLVMRegPair AVREHFlavour0Dwarf2L[] = {
681 { 0U, AVR::R1R0 },
682 { 1U, AVR::R1 },
683 { 2U, AVR::R3R2 },
684 { 3U, AVR::R3 },
685 { 4U, AVR::R5R4 },
686 { 5U, AVR::R5 },
687 { 6U, AVR::R7R6 },
688 { 7U, AVR::R7 },
689 { 8U, AVR::R9R8 },
690 { 9U, AVR::R10R9 },
691 { 10U, AVR::R11R10 },
692 { 11U, AVR::R12R11 },
693 { 12U, AVR::R13R12 },
694 { 13U, AVR::R14R13 },
695 { 14U, AVR::R15R14 },
696 { 15U, AVR::R16R15 },
697 { 16U, AVR::R17R16 },
698 { 17U, AVR::R18R17 },
699 { 18U, AVR::R19R18 },
700 { 19U, AVR::R20R19 },
701 { 20U, AVR::R21R20 },
702 { 21U, AVR::R22R21 },
703 { 22U, AVR::R23R22 },
704 { 23U, AVR::R24R23 },
705 { 24U, AVR::R25R24 },
706 { 25U, AVR::R26R25 },
707 { 26U, AVR::R27R26 },
708 { 27U, AVR::R27 },
709 { 28U, AVR::R29R28 },
710 { 29U, AVR::R29 },
711 { 30U, AVR::R31R30 },
712 { 31U, AVR::R31 },
713 { 32U, AVR::SPL },
714 { 33U, AVR::SPH },
715 { 88U, AVR::SREG },
716};
717extern const unsigned AVREHFlavour0Dwarf2LSize = std::size(AVREHFlavour0Dwarf2L);
718
719extern const MCRegisterInfo::DwarfLLVMRegPair AVRDwarfFlavour0L2Dwarf[] = {
720 { AVR::SP, 32U },
721 { AVR::SPH, 33U },
722 { AVR::SPL, 32U },
723 { AVR::SREG, 88U },
724 { AVR::R0, 0U },
725 { AVR::R1, 1U },
726 { AVR::R2, 2U },
727 { AVR::R3, 3U },
728 { AVR::R4, 4U },
729 { AVR::R5, 5U },
730 { AVR::R6, 6U },
731 { AVR::R7, 7U },
732 { AVR::R8, 8U },
733 { AVR::R9, 9U },
734 { AVR::R10, 10U },
735 { AVR::R11, 11U },
736 { AVR::R12, 12U },
737 { AVR::R13, 13U },
738 { AVR::R14, 14U },
739 { AVR::R15, 15U },
740 { AVR::R16, 16U },
741 { AVR::R17, 17U },
742 { AVR::R18, 18U },
743 { AVR::R19, 19U },
744 { AVR::R20, 20U },
745 { AVR::R21, 21U },
746 { AVR::R22, 22U },
747 { AVR::R23, 23U },
748 { AVR::R24, 24U },
749 { AVR::R25, 25U },
750 { AVR::R26, 26U },
751 { AVR::R27, 27U },
752 { AVR::R28, 28U },
753 { AVR::R29, 29U },
754 { AVR::R30, 30U },
755 { AVR::R31, 31U },
756 { AVR::R1R0, 0U },
757 { AVR::R3R2, 2U },
758 { AVR::R5R4, 4U },
759 { AVR::R7R6, 6U },
760 { AVR::R9R8, 8U },
761 { AVR::R10R9, 9U },
762 { AVR::R11R10, 10U },
763 { AVR::R12R11, 11U },
764 { AVR::R13R12, 12U },
765 { AVR::R14R13, 13U },
766 { AVR::R15R14, 14U },
767 { AVR::R16R15, 15U },
768 { AVR::R17R16, 16U },
769 { AVR::R18R17, 17U },
770 { AVR::R19R18, 18U },
771 { AVR::R20R19, 19U },
772 { AVR::R21R20, 20U },
773 { AVR::R22R21, 21U },
774 { AVR::R23R22, 22U },
775 { AVR::R24R23, 23U },
776 { AVR::R25R24, 24U },
777 { AVR::R26R25, 25U },
778 { AVR::R27R26, 26U },
779 { AVR::R29R28, 28U },
780 { AVR::R31R30, 30U },
781};
782extern const unsigned AVRDwarfFlavour0L2DwarfSize = std::size(AVRDwarfFlavour0L2Dwarf);
783
784extern const MCRegisterInfo::DwarfLLVMRegPair AVREHFlavour0L2Dwarf[] = {
785 { AVR::SP, 32U },
786 { AVR::SPH, 33U },
787 { AVR::SPL, 32U },
788 { AVR::SREG, 88U },
789 { AVR::R0, 0U },
790 { AVR::R1, 1U },
791 { AVR::R2, 2U },
792 { AVR::R3, 3U },
793 { AVR::R4, 4U },
794 { AVR::R5, 5U },
795 { AVR::R6, 6U },
796 { AVR::R7, 7U },
797 { AVR::R8, 8U },
798 { AVR::R9, 9U },
799 { AVR::R10, 10U },
800 { AVR::R11, 11U },
801 { AVR::R12, 12U },
802 { AVR::R13, 13U },
803 { AVR::R14, 14U },
804 { AVR::R15, 15U },
805 { AVR::R16, 16U },
806 { AVR::R17, 17U },
807 { AVR::R18, 18U },
808 { AVR::R19, 19U },
809 { AVR::R20, 20U },
810 { AVR::R21, 21U },
811 { AVR::R22, 22U },
812 { AVR::R23, 23U },
813 { AVR::R24, 24U },
814 { AVR::R25, 25U },
815 { AVR::R26, 26U },
816 { AVR::R27, 27U },
817 { AVR::R28, 28U },
818 { AVR::R29, 29U },
819 { AVR::R30, 30U },
820 { AVR::R31, 31U },
821 { AVR::R1R0, 0U },
822 { AVR::R3R2, 2U },
823 { AVR::R5R4, 4U },
824 { AVR::R7R6, 6U },
825 { AVR::R9R8, 8U },
826 { AVR::R10R9, 9U },
827 { AVR::R11R10, 10U },
828 { AVR::R12R11, 11U },
829 { AVR::R13R12, 12U },
830 { AVR::R14R13, 13U },
831 { AVR::R15R14, 14U },
832 { AVR::R16R15, 15U },
833 { AVR::R17R16, 16U },
834 { AVR::R18R17, 17U },
835 { AVR::R19R18, 18U },
836 { AVR::R20R19, 19U },
837 { AVR::R21R20, 20U },
838 { AVR::R22R21, 21U },
839 { AVR::R23R22, 22U },
840 { AVR::R24R23, 23U },
841 { AVR::R25R24, 24U },
842 { AVR::R26R25, 25U },
843 { AVR::R27R26, 26U },
844 { AVR::R29R28, 28U },
845 { AVR::R31R30, 30U },
846};
847extern const unsigned AVREHFlavour0L2DwarfSize = std::size(AVREHFlavour0L2Dwarf);
848
849extern const uint16_t AVRRegEncodingTable[] = {
850 0,
851 32,
852 33,
853 32,
854 14,
855 0,
856 1,
857 2,
858 3,
859 4,
860 5,
861 6,
862 7,
863 8,
864 9,
865 10,
866 11,
867 12,
868 13,
869 14,
870 15,
871 16,
872 17,
873 18,
874 19,
875 20,
876 21,
877 22,
878 23,
879 24,
880 25,
881 26,
882 27,
883 28,
884 29,
885 30,
886 31,
887 0,
888 2,
889 4,
890 6,
891 8,
892 9,
893 10,
894 11,
895 12,
896 13,
897 14,
898 15,
899 16,
900 17,
901 18,
902 19,
903 20,
904 21,
905 22,
906 23,
907 24,
908 25,
909 26,
910 28,
911 30,
912};
913static inline void InitAVRMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
914 RI->InitMCRegisterInfo(AVRRegDesc, 62, RA, PC, AVRMCRegisterClasses, 23, AVRRegUnitRoots, 35, AVRRegDiffLists, AVRLaneMaskLists, AVRRegStrings, AVRRegClassStrings, AVRSubRegIdxLists, 3,
915AVRRegEncodingTable);
916
917 switch (DwarfFlavour) {
918 default:
919 llvm_unreachable("Unknown DWARF flavour");
920 case 0:
921 RI->mapDwarfRegsToLLVMRegs(AVRDwarfFlavour0Dwarf2L, AVRDwarfFlavour0Dwarf2LSize, false);
922 break;
923 }
924 switch (EHFlavour) {
925 default:
926 llvm_unreachable("Unknown DWARF flavour");
927 case 0:
928 RI->mapDwarfRegsToLLVMRegs(AVREHFlavour0Dwarf2L, AVREHFlavour0Dwarf2LSize, true);
929 break;
930 }
931 switch (DwarfFlavour) {
932 default:
933 llvm_unreachable("Unknown DWARF flavour");
934 case 0:
935 RI->mapLLVMRegsToDwarfRegs(AVRDwarfFlavour0L2Dwarf, AVRDwarfFlavour0L2DwarfSize, false);
936 break;
937 }
938 switch (EHFlavour) {
939 default:
940 llvm_unreachable("Unknown DWARF flavour");
941 case 0:
942 RI->mapLLVMRegsToDwarfRegs(AVREHFlavour0L2Dwarf, AVREHFlavour0L2DwarfSize, true);
943 break;
944 }
945}
946
947} // end namespace llvm
948
949#endif // GET_REGINFO_MC_DESC
950
951/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
952|* *|
953|* Register Information Header Fragment *|
954|* *|
955|* Automatically generated file, do not edit! *|
956|* *|
957\*===----------------------------------------------------------------------===*/
958
959
960#ifdef GET_REGINFO_HEADER
961#undef GET_REGINFO_HEADER
962
963#include "llvm/CodeGen/TargetRegisterInfo.h"
964
965namespace llvm {
966
967class AVRFrameLowering;
968
969struct AVRGenRegisterInfo : public TargetRegisterInfo {
970 explicit AVRGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
971 unsigned PC = 0, unsigned HwMode = 0);
972 unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
973 unsigned reverseComposeSubRegIndicesImpl(unsigned, unsigned) const override;
974 LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
975 LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
976 const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass *, unsigned) const override;
977 const TargetRegisterClass *getSubRegisterClass(const TargetRegisterClass *, unsigned) const override;
978 const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
979 unsigned getRegUnitWeight(unsigned RegUnit) const override;
980 unsigned getNumRegPressureSets() const override;
981 const char *getRegPressureSetName(unsigned Idx) const override;
982 unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
983 const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
984 const int *getRegUnitPressureSets(unsigned RegUnit) const override;
985 ArrayRef<const char *> getRegMaskNames() const override;
986 ArrayRef<const uint32_t *> getRegMasks() const override;
987 bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override;
988 bool isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const override;
989 bool isFixedRegister(const MachineFunction &, MCRegister) const override;
990 bool isArgumentRegister(const MachineFunction &, MCRegister) const override;
991 bool isConstantPhysReg(MCRegister PhysReg) const override final;
992 /// Devirtualized TargetFrameLowering.
993 static const AVRFrameLowering *getFrameLowering(
994 const MachineFunction &MF);
995};
996
997namespace AVR { // Register classes
998 extern const TargetRegisterClass GPR8RegClass;
999 extern const TargetRegisterClass GPR8loRegClass;
1000 extern const TargetRegisterClass LD8RegClass;
1001 extern const TargetRegisterClass LD8loRegClass;
1002 extern const TargetRegisterClass CCRRegClass;
1003 extern const TargetRegisterClass DREGSRegClass;
1004 extern const TargetRegisterClass DREGSMOVWRegClass;
1005 extern const TargetRegisterClass DREGS_with_sub_hi_in_LD8RegClass;
1006 extern const TargetRegisterClass DREGS_with_sub_lo_in_LD8RegClass;
1007 extern const TargetRegisterClass DREGS_with_sub_lo_in_GPR8loRegClass;
1008 extern const TargetRegisterClass DREGS_with_sub_hi_in_GPR8loRegClass;
1009 extern const TargetRegisterClass DLDREGSRegClass;
1010 extern const TargetRegisterClass DREGS_with_sub_hi_in_LD8loRegClass;
1011 extern const TargetRegisterClass DREGS_with_sub_lo_in_LD8loRegClass;
1012 extern const TargetRegisterClass DREGSloRegClass;
1013 extern const TargetRegisterClass DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8RegClass;
1014 extern const TargetRegisterClass DREGSLD8loRegClass;
1015 extern const TargetRegisterClass IWREGSRegClass;
1016 extern const TargetRegisterClass PTRREGSRegClass;
1017 extern const TargetRegisterClass PTRDISPREGSRegClass;
1018 extern const TargetRegisterClass DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loRegClass;
1019 extern const TargetRegisterClass GPRSPRegClass;
1020 extern const TargetRegisterClass ZREGRegClass;
1021} // end namespace AVR
1022
1023} // end namespace llvm
1024
1025#endif // GET_REGINFO_HEADER
1026
1027/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
1028|* *|
1029|* Target Register and Register Classes Information *|
1030|* *|
1031|* Automatically generated file, do not edit! *|
1032|* *|
1033\*===----------------------------------------------------------------------===*/
1034
1035
1036#ifdef GET_REGINFO_TARGET_DESC
1037#undef GET_REGINFO_TARGET_DESC
1038
1039namespace llvm {
1040
1041extern const MCRegisterClass AVRMCRegisterClasses[];
1042
1043static const MVT::SimpleValueType VTLists[] = {
1044 /* 0 */ MVT::i8, MVT::Other,
1045 /* 2 */ MVT::i16, MVT::Other,
1046};
1047
1048static const char *SubRegIndexNameTable[] = { "sub_hi", "sub_lo", "" };
1049
1050static const TargetRegisterInfo::SubRegCoveredBits SubRegIdxRangeTable[] = {
1051 { 65535, 65535 },
1052 { 8, 8 }, // sub_hi
1053 { 0, 8 }, // sub_lo
1054};
1055
1056
1057static const LaneBitmask SubRegIndexLaneMaskTable[] = {
1058 LaneBitmask::getAll(),
1059 LaneBitmask(0x0000000000000001), // sub_hi
1060 LaneBitmask(0x0000000000000002), // sub_lo
1061 };
1062
1063
1064
1065static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
1066 // Mode = 0 (Default)
1067 { 8, 8, 8, /*VTLists+*/0 }, // GPR8
1068 { 8, 8, 8, /*VTLists+*/0 }, // GPR8lo
1069 { 8, 8, 8, /*VTLists+*/0 }, // LD8
1070 { 8, 8, 8, /*VTLists+*/0 }, // LD8lo
1071 { 8, 8, 8, /*VTLists+*/0 }, // CCR
1072 { 16, 16, 8, /*VTLists+*/2 }, // DREGS
1073 { 16, 16, 8, /*VTLists+*/2 }, // DREGSMOVW
1074 { 16, 16, 8, /*VTLists+*/2 }, // DREGS_with_sub_hi_in_LD8
1075 { 16, 16, 8, /*VTLists+*/2 }, // DREGS_with_sub_lo_in_LD8
1076 { 16, 16, 8, /*VTLists+*/2 }, // DREGS_with_sub_lo_in_GPR8lo
1077 { 16, 16, 8, /*VTLists+*/2 }, // DREGS_with_sub_hi_in_GPR8lo
1078 { 16, 16, 8, /*VTLists+*/2 }, // DLDREGS
1079 { 16, 16, 8, /*VTLists+*/2 }, // DREGS_with_sub_hi_in_LD8lo
1080 { 16, 16, 8, /*VTLists+*/2 }, // DREGS_with_sub_lo_in_LD8lo
1081 { 16, 16, 8, /*VTLists+*/2 }, // DREGSlo
1082 { 16, 16, 8, /*VTLists+*/2 }, // DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8
1083 { 16, 16, 8, /*VTLists+*/2 }, // DREGSLD8lo
1084 { 16, 16, 8, /*VTLists+*/2 }, // IWREGS
1085 { 16, 16, 8, /*VTLists+*/2 }, // PTRREGS
1086 { 16, 16, 8, /*VTLists+*/2 }, // PTRDISPREGS
1087 { 16, 16, 8, /*VTLists+*/2 }, // DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo
1088 { 16, 16, 8, /*VTLists+*/2 }, // GPRSP
1089 { 16, 16, 8, /*VTLists+*/2 }, // ZREG
1090};
1091static const uint32_t GPR8SubClassMask[] = {
1092 0x0000000f,
1093 0x005fffe0, // sub_hi
1094 0x005fffe0, // sub_lo
1095};
1096
1097static const uint32_t GPR8loSubClassMask[] = {
1098 0x00000002,
1099 0x00004400, // sub_hi
1100 0x00104600, // sub_lo
1101};
1102
1103static const uint32_t LD8SubClassMask[] = {
1104 0x0000000c,
1105 0x005fb980, // sub_hi
1106 0x004fa900, // sub_lo
1107};
1108
1109static const uint32_t LD8loSubClassMask[] = {
1110 0x00000008,
1111 0x00119000, // sub_hi
1112 0x0001a000, // sub_lo
1113};
1114
1115static const uint32_t CCRSubClassMask[] = {
1116 0x00000010,
1117};
1118
1119static const uint32_t DREGSSubClassMask[] = {
1120 0x005fffe0,
1121};
1122
1123static const uint32_t DREGSMOVWSubClassMask[] = {
1124 0x004f4840,
1125};
1126
1127static const uint32_t DREGS_with_sub_hi_in_LD8SubClassMask[] = {
1128 0x005fb980,
1129};
1130
1131static const uint32_t DREGS_with_sub_lo_in_LD8SubClassMask[] = {
1132 0x004fa900,
1133};
1134
1135static const uint32_t DREGS_with_sub_lo_in_GPR8loSubClassMask[] = {
1136 0x00104600,
1137};
1138
1139static const uint32_t DREGS_with_sub_hi_in_GPR8loSubClassMask[] = {
1140 0x00004400,
1141};
1142
1143static const uint32_t DLDREGSSubClassMask[] = {
1144 0x004f0800,
1145};
1146
1147static const uint32_t DREGS_with_sub_hi_in_LD8loSubClassMask[] = {
1148 0x00119000,
1149};
1150
1151static const uint32_t DREGS_with_sub_lo_in_LD8loSubClassMask[] = {
1152 0x0001a000,
1153};
1154
1155static const uint32_t DREGSloSubClassMask[] = {
1156 0x00004000,
1157};
1158
1159static const uint32_t DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8SubClassMask[] = {
1160 0x00018000,
1161};
1162
1163static const uint32_t DREGSLD8loSubClassMask[] = {
1164 0x00010000,
1165};
1166
1167static const uint32_t IWREGSSubClassMask[] = {
1168 0x004e0000,
1169};
1170
1171static const uint32_t PTRREGSSubClassMask[] = {
1172 0x004c0000,
1173};
1174
1175static const uint32_t PTRDISPREGSSubClassMask[] = {
1176 0x00480000,
1177};
1178
1179static const uint32_t DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loSubClassMask[] = {
1180 0x00100000,
1181};
1182
1183static const uint32_t GPRSPSubClassMask[] = {
1184 0x00200000,
1185};
1186
1187static const uint32_t ZREGSubClassMask[] = {
1188 0x00400000,
1189};
1190
1191static const uint16_t SuperRegIdxSeqs[] = {
1192 /* 0 */ 1, 2, 0,
1193};
1194
1195static unsigned const GPR8loSuperclasses[] = {
1196 AVR::GPR8RegClassID,
1197};
1198
1199static unsigned const LD8Superclasses[] = {
1200 AVR::GPR8RegClassID,
1201};
1202
1203static unsigned const LD8loSuperclasses[] = {
1204 AVR::GPR8RegClassID,
1205 AVR::LD8RegClassID,
1206};
1207
1208static unsigned const DREGSMOVWSuperclasses[] = {
1209 AVR::DREGSRegClassID,
1210};
1211
1212static unsigned const DREGS_with_sub_hi_in_LD8Superclasses[] = {
1213 AVR::DREGSRegClassID,
1214};
1215
1216static unsigned const DREGS_with_sub_lo_in_LD8Superclasses[] = {
1217 AVR::DREGSRegClassID,
1218 AVR::DREGS_with_sub_hi_in_LD8RegClassID,
1219};
1220
1221static unsigned const DREGS_with_sub_lo_in_GPR8loSuperclasses[] = {
1222 AVR::DREGSRegClassID,
1223};
1224
1225static unsigned const DREGS_with_sub_hi_in_GPR8loSuperclasses[] = {
1226 AVR::DREGSRegClassID,
1227 AVR::DREGS_with_sub_lo_in_GPR8loRegClassID,
1228};
1229
1230static unsigned const DLDREGSSuperclasses[] = {
1231 AVR::DREGSRegClassID,
1232 AVR::DREGSMOVWRegClassID,
1233 AVR::DREGS_with_sub_hi_in_LD8RegClassID,
1234 AVR::DREGS_with_sub_lo_in_LD8RegClassID,
1235};
1236
1237static unsigned const DREGS_with_sub_hi_in_LD8loSuperclasses[] = {
1238 AVR::DREGSRegClassID,
1239 AVR::DREGS_with_sub_hi_in_LD8RegClassID,
1240};
1241
1242static unsigned const DREGS_with_sub_lo_in_LD8loSuperclasses[] = {
1243 AVR::DREGSRegClassID,
1244 AVR::DREGS_with_sub_hi_in_LD8RegClassID,
1245 AVR::DREGS_with_sub_lo_in_LD8RegClassID,
1246};
1247
1248static unsigned const DREGSloSuperclasses[] = {
1249 AVR::DREGSRegClassID,
1250 AVR::DREGSMOVWRegClassID,
1251 AVR::DREGS_with_sub_lo_in_GPR8loRegClassID,
1252 AVR::DREGS_with_sub_hi_in_GPR8loRegClassID,
1253};
1254
1255static unsigned const DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8Superclasses[] = {
1256 AVR::DREGSRegClassID,
1257 AVR::DREGS_with_sub_hi_in_LD8RegClassID,
1258 AVR::DREGS_with_sub_lo_in_LD8RegClassID,
1259 AVR::DREGS_with_sub_hi_in_LD8loRegClassID,
1260 AVR::DREGS_with_sub_lo_in_LD8loRegClassID,
1261};
1262
1263static unsigned const DREGSLD8loSuperclasses[] = {
1264 AVR::DREGSRegClassID,
1265 AVR::DREGSMOVWRegClassID,
1266 AVR::DREGS_with_sub_hi_in_LD8RegClassID,
1267 AVR::DREGS_with_sub_lo_in_LD8RegClassID,
1268 AVR::DLDREGSRegClassID,
1269 AVR::DREGS_with_sub_hi_in_LD8loRegClassID,
1270 AVR::DREGS_with_sub_lo_in_LD8loRegClassID,
1271 AVR::DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8RegClassID,
1272};
1273
1274static unsigned const IWREGSSuperclasses[] = {
1275 AVR::DREGSRegClassID,
1276 AVR::DREGSMOVWRegClassID,
1277 AVR::DREGS_with_sub_hi_in_LD8RegClassID,
1278 AVR::DREGS_with_sub_lo_in_LD8RegClassID,
1279 AVR::DLDREGSRegClassID,
1280};
1281
1282static unsigned const PTRREGSSuperclasses[] = {
1283 AVR::DREGSRegClassID,
1284 AVR::DREGSMOVWRegClassID,
1285 AVR::DREGS_with_sub_hi_in_LD8RegClassID,
1286 AVR::DREGS_with_sub_lo_in_LD8RegClassID,
1287 AVR::DLDREGSRegClassID,
1288 AVR::IWREGSRegClassID,
1289};
1290
1291static unsigned const PTRDISPREGSSuperclasses[] = {
1292 AVR::DREGSRegClassID,
1293 AVR::DREGSMOVWRegClassID,
1294 AVR::DREGS_with_sub_hi_in_LD8RegClassID,
1295 AVR::DREGS_with_sub_lo_in_LD8RegClassID,
1296 AVR::DLDREGSRegClassID,
1297 AVR::IWREGSRegClassID,
1298 AVR::PTRREGSRegClassID,
1299};
1300
1301static unsigned const DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loSuperclasses[] = {
1302 AVR::DREGSRegClassID,
1303 AVR::DREGS_with_sub_hi_in_LD8RegClassID,
1304 AVR::DREGS_with_sub_lo_in_GPR8loRegClassID,
1305 AVR::DREGS_with_sub_hi_in_LD8loRegClassID,
1306};
1307
1308static unsigned const ZREGSuperclasses[] = {
1309 AVR::DREGSRegClassID,
1310 AVR::DREGSMOVWRegClassID,
1311 AVR::DREGS_with_sub_hi_in_LD8RegClassID,
1312 AVR::DREGS_with_sub_lo_in_LD8RegClassID,
1313 AVR::DLDREGSRegClassID,
1314 AVR::IWREGSRegClassID,
1315 AVR::PTRREGSRegClassID,
1316 AVR::PTRDISPREGSRegClassID,
1317};
1318
1319
1320namespace AVR { // Register class instances
1321 extern const TargetRegisterClass GPR8RegClass = {
1322 &AVRMCRegisterClasses[GPR8RegClassID],
1323 GPR8SubClassMask,
1324 SuperRegIdxSeqs + 0,
1325 LaneBitmask(0x0000000000000001),
1326 0,
1327 false,
1328 0x00, /* TSFlags */
1329 false, /* HasDisjunctSubRegs */
1330 false, /* CoveredBySubRegs */
1331 nullptr, 0,
1332 nullptr
1333 };
1334
1335 extern const TargetRegisterClass GPR8loRegClass = {
1336 &AVRMCRegisterClasses[GPR8loRegClassID],
1337 GPR8loSubClassMask,
1338 SuperRegIdxSeqs + 0,
1339 LaneBitmask(0x0000000000000001),
1340 0,
1341 false,
1342 0x00, /* TSFlags */
1343 false, /* HasDisjunctSubRegs */
1344 false, /* CoveredBySubRegs */
1345 GPR8loSuperclasses, 1,
1346 nullptr
1347 };
1348
1349 extern const TargetRegisterClass LD8RegClass = {
1350 &AVRMCRegisterClasses[LD8RegClassID],
1351 LD8SubClassMask,
1352 SuperRegIdxSeqs + 0,
1353 LaneBitmask(0x0000000000000001),
1354 0,
1355 false,
1356 0x00, /* TSFlags */
1357 false, /* HasDisjunctSubRegs */
1358 false, /* CoveredBySubRegs */
1359 LD8Superclasses, 1,
1360 nullptr
1361 };
1362
1363 extern const TargetRegisterClass LD8loRegClass = {
1364 &AVRMCRegisterClasses[LD8loRegClassID],
1365 LD8loSubClassMask,
1366 SuperRegIdxSeqs + 0,
1367 LaneBitmask(0x0000000000000001),
1368 0,
1369 false,
1370 0x00, /* TSFlags */
1371 false, /* HasDisjunctSubRegs */
1372 false, /* CoveredBySubRegs */
1373 LD8loSuperclasses, 2,
1374 nullptr
1375 };
1376
1377 extern const TargetRegisterClass CCRRegClass = {
1378 &AVRMCRegisterClasses[CCRRegClassID],
1379 CCRSubClassMask,
1380 SuperRegIdxSeqs + 2,
1381 LaneBitmask(0x0000000000000001),
1382 0,
1383 false,
1384 0x00, /* TSFlags */
1385 false, /* HasDisjunctSubRegs */
1386 false, /* CoveredBySubRegs */
1387 nullptr, 0,
1388 nullptr
1389 };
1390
1391 extern const TargetRegisterClass DREGSRegClass = {
1392 &AVRMCRegisterClasses[DREGSRegClassID],
1393 DREGSSubClassMask,
1394 SuperRegIdxSeqs + 2,
1395 LaneBitmask(0x0000000000000003),
1396 0,
1397 false,
1398 0x00, /* TSFlags */
1399 true, /* HasDisjunctSubRegs */
1400 true, /* CoveredBySubRegs */
1401 nullptr, 0,
1402 nullptr
1403 };
1404
1405 extern const TargetRegisterClass DREGSMOVWRegClass = {
1406 &AVRMCRegisterClasses[DREGSMOVWRegClassID],
1407 DREGSMOVWSubClassMask,
1408 SuperRegIdxSeqs + 2,
1409 LaneBitmask(0x0000000000000003),
1410 0,
1411 false,
1412 0x00, /* TSFlags */
1413 true, /* HasDisjunctSubRegs */
1414 true, /* CoveredBySubRegs */
1415 DREGSMOVWSuperclasses, 1,
1416 nullptr
1417 };
1418
1419 extern const TargetRegisterClass DREGS_with_sub_hi_in_LD8RegClass = {
1420 &AVRMCRegisterClasses[DREGS_with_sub_hi_in_LD8RegClassID],
1421 DREGS_with_sub_hi_in_LD8SubClassMask,
1422 SuperRegIdxSeqs + 2,
1423 LaneBitmask(0x0000000000000003),
1424 0,
1425 false,
1426 0x00, /* TSFlags */
1427 true, /* HasDisjunctSubRegs */
1428 true, /* CoveredBySubRegs */
1429 DREGS_with_sub_hi_in_LD8Superclasses, 1,
1430 nullptr
1431 };
1432
1433 extern const TargetRegisterClass DREGS_with_sub_lo_in_LD8RegClass = {
1434 &AVRMCRegisterClasses[DREGS_with_sub_lo_in_LD8RegClassID],
1435 DREGS_with_sub_lo_in_LD8SubClassMask,
1436 SuperRegIdxSeqs + 2,
1437 LaneBitmask(0x0000000000000003),
1438 0,
1439 false,
1440 0x00, /* TSFlags */
1441 true, /* HasDisjunctSubRegs */
1442 true, /* CoveredBySubRegs */
1443 DREGS_with_sub_lo_in_LD8Superclasses, 2,
1444 nullptr
1445 };
1446
1447 extern const TargetRegisterClass DREGS_with_sub_lo_in_GPR8loRegClass = {
1448 &AVRMCRegisterClasses[DREGS_with_sub_lo_in_GPR8loRegClassID],
1449 DREGS_with_sub_lo_in_GPR8loSubClassMask,
1450 SuperRegIdxSeqs + 2,
1451 LaneBitmask(0x0000000000000003),
1452 0,
1453 false,
1454 0x00, /* TSFlags */
1455 true, /* HasDisjunctSubRegs */
1456 true, /* CoveredBySubRegs */
1457 DREGS_with_sub_lo_in_GPR8loSuperclasses, 1,
1458 nullptr
1459 };
1460
1461 extern const TargetRegisterClass DREGS_with_sub_hi_in_GPR8loRegClass = {
1462 &AVRMCRegisterClasses[DREGS_with_sub_hi_in_GPR8loRegClassID],
1463 DREGS_with_sub_hi_in_GPR8loSubClassMask,
1464 SuperRegIdxSeqs + 2,
1465 LaneBitmask(0x0000000000000003),
1466 0,
1467 false,
1468 0x00, /* TSFlags */
1469 true, /* HasDisjunctSubRegs */
1470 true, /* CoveredBySubRegs */
1471 DREGS_with_sub_hi_in_GPR8loSuperclasses, 2,
1472 nullptr
1473 };
1474
1475 extern const TargetRegisterClass DLDREGSRegClass = {
1476 &AVRMCRegisterClasses[DLDREGSRegClassID],
1477 DLDREGSSubClassMask,
1478 SuperRegIdxSeqs + 2,
1479 LaneBitmask(0x0000000000000003),
1480 0,
1481 false,
1482 0x00, /* TSFlags */
1483 true, /* HasDisjunctSubRegs */
1484 true, /* CoveredBySubRegs */
1485 DLDREGSSuperclasses, 4,
1486 nullptr
1487 };
1488
1489 extern const TargetRegisterClass DREGS_with_sub_hi_in_LD8loRegClass = {
1490 &AVRMCRegisterClasses[DREGS_with_sub_hi_in_LD8loRegClassID],
1491 DREGS_with_sub_hi_in_LD8loSubClassMask,
1492 SuperRegIdxSeqs + 2,
1493 LaneBitmask(0x0000000000000003),
1494 0,
1495 false,
1496 0x00, /* TSFlags */
1497 true, /* HasDisjunctSubRegs */
1498 true, /* CoveredBySubRegs */
1499 DREGS_with_sub_hi_in_LD8loSuperclasses, 2,
1500 nullptr
1501 };
1502
1503 extern const TargetRegisterClass DREGS_with_sub_lo_in_LD8loRegClass = {
1504 &AVRMCRegisterClasses[DREGS_with_sub_lo_in_LD8loRegClassID],
1505 DREGS_with_sub_lo_in_LD8loSubClassMask,
1506 SuperRegIdxSeqs + 2,
1507 LaneBitmask(0x0000000000000003),
1508 0,
1509 false,
1510 0x00, /* TSFlags */
1511 true, /* HasDisjunctSubRegs */
1512 true, /* CoveredBySubRegs */
1513 DREGS_with_sub_lo_in_LD8loSuperclasses, 3,
1514 nullptr
1515 };
1516
1517 extern const TargetRegisterClass DREGSloRegClass = {
1518 &AVRMCRegisterClasses[DREGSloRegClassID],
1519 DREGSloSubClassMask,
1520 SuperRegIdxSeqs + 2,
1521 LaneBitmask(0x0000000000000003),
1522 0,
1523 false,
1524 0x00, /* TSFlags */
1525 true, /* HasDisjunctSubRegs */
1526 true, /* CoveredBySubRegs */
1527 DREGSloSuperclasses, 4,
1528 nullptr
1529 };
1530
1531 extern const TargetRegisterClass DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8RegClass = {
1532 &AVRMCRegisterClasses[DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8RegClassID],
1533 DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8SubClassMask,
1534 SuperRegIdxSeqs + 2,
1535 LaneBitmask(0x0000000000000003),
1536 0,
1537 false,
1538 0x00, /* TSFlags */
1539 true, /* HasDisjunctSubRegs */
1540 true, /* CoveredBySubRegs */
1541 DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8Superclasses, 5,
1542 nullptr
1543 };
1544
1545 extern const TargetRegisterClass DREGSLD8loRegClass = {
1546 &AVRMCRegisterClasses[DREGSLD8loRegClassID],
1547 DREGSLD8loSubClassMask,
1548 SuperRegIdxSeqs + 2,
1549 LaneBitmask(0x0000000000000003),
1550 0,
1551 false,
1552 0x00, /* TSFlags */
1553 true, /* HasDisjunctSubRegs */
1554 true, /* CoveredBySubRegs */
1555 DREGSLD8loSuperclasses, 8,
1556 nullptr
1557 };
1558
1559 extern const TargetRegisterClass IWREGSRegClass = {
1560 &AVRMCRegisterClasses[IWREGSRegClassID],
1561 IWREGSSubClassMask,
1562 SuperRegIdxSeqs + 2,
1563 LaneBitmask(0x0000000000000003),
1564 0,
1565 false,
1566 0x00, /* TSFlags */
1567 true, /* HasDisjunctSubRegs */
1568 true, /* CoveredBySubRegs */
1569 IWREGSSuperclasses, 5,
1570 nullptr
1571 };
1572
1573 extern const TargetRegisterClass PTRREGSRegClass = {
1574 &AVRMCRegisterClasses[PTRREGSRegClassID],
1575 PTRREGSSubClassMask,
1576 SuperRegIdxSeqs + 2,
1577 LaneBitmask(0x0000000000000003),
1578 0,
1579 false,
1580 0x00, /* TSFlags */
1581 true, /* HasDisjunctSubRegs */
1582 true, /* CoveredBySubRegs */
1583 PTRREGSSuperclasses, 6,
1584 nullptr
1585 };
1586
1587 extern const TargetRegisterClass PTRDISPREGSRegClass = {
1588 &AVRMCRegisterClasses[PTRDISPREGSRegClassID],
1589 PTRDISPREGSSubClassMask,
1590 SuperRegIdxSeqs + 2,
1591 LaneBitmask(0x0000000000000003),
1592 0,
1593 false,
1594 0x00, /* TSFlags */
1595 true, /* HasDisjunctSubRegs */
1596 true, /* CoveredBySubRegs */
1597 PTRDISPREGSSuperclasses, 7,
1598 nullptr
1599 };
1600
1601 extern const TargetRegisterClass DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loRegClass = {
1602 &AVRMCRegisterClasses[DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loRegClassID],
1603 DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loSubClassMask,
1604 SuperRegIdxSeqs + 2,
1605 LaneBitmask(0x0000000000000003),
1606 0,
1607 false,
1608 0x00, /* TSFlags */
1609 true, /* HasDisjunctSubRegs */
1610 true, /* CoveredBySubRegs */
1611 DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loSuperclasses, 4,
1612 nullptr
1613 };
1614
1615 extern const TargetRegisterClass GPRSPRegClass = {
1616 &AVRMCRegisterClasses[GPRSPRegClassID],
1617 GPRSPSubClassMask,
1618 SuperRegIdxSeqs + 2,
1619 LaneBitmask(0x0000000000000003),
1620 0,
1621 false,
1622 0x00, /* TSFlags */
1623 true, /* HasDisjunctSubRegs */
1624 true, /* CoveredBySubRegs */
1625 nullptr, 0,
1626 nullptr
1627 };
1628
1629 extern const TargetRegisterClass ZREGRegClass = {
1630 &AVRMCRegisterClasses[ZREGRegClassID],
1631 ZREGSubClassMask,
1632 SuperRegIdxSeqs + 2,
1633 LaneBitmask(0x0000000000000003),
1634 0,
1635 false,
1636 0x00, /* TSFlags */
1637 true, /* HasDisjunctSubRegs */
1638 true, /* CoveredBySubRegs */
1639 ZREGSuperclasses, 8,
1640 nullptr
1641 };
1642
1643} // end namespace AVR
1644
1645namespace {
1646 const TargetRegisterClass *const RegisterClasses[] = {
1647 &AVR::GPR8RegClass,
1648 &AVR::GPR8loRegClass,
1649 &AVR::LD8RegClass,
1650 &AVR::LD8loRegClass,
1651 &AVR::CCRRegClass,
1652 &AVR::DREGSRegClass,
1653 &AVR::DREGSMOVWRegClass,
1654 &AVR::DREGS_with_sub_hi_in_LD8RegClass,
1655 &AVR::DREGS_with_sub_lo_in_LD8RegClass,
1656 &AVR::DREGS_with_sub_lo_in_GPR8loRegClass,
1657 &AVR::DREGS_with_sub_hi_in_GPR8loRegClass,
1658 &AVR::DLDREGSRegClass,
1659 &AVR::DREGS_with_sub_hi_in_LD8loRegClass,
1660 &AVR::DREGS_with_sub_lo_in_LD8loRegClass,
1661 &AVR::DREGSloRegClass,
1662 &AVR::DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8RegClass,
1663 &AVR::DREGSLD8loRegClass,
1664 &AVR::IWREGSRegClass,
1665 &AVR::PTRREGSRegClass,
1666 &AVR::PTRDISPREGSRegClass,
1667 &AVR::DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loRegClass,
1668 &AVR::GPRSPRegClass,
1669 &AVR::ZREGRegClass,
1670 };
1671} // end anonymous namespace
1672
1673static const uint8_t CostPerUseTable[] = {
16740, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
1675
1676
1677static const bool InAllocatableClassTable[] = {
1678false, true, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
1679
1680
1681static const TargetRegisterInfoDesc AVRRegInfoDesc = { // Extra Descriptors
1682CostPerUseTable, 1, InAllocatableClassTable};
1683
1684unsigned AVRGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
1685 static const uint8_t Rows[1][2] = {
1686 { 0, 0, },
1687 };
1688
1689 --IdxA; assert(IdxA < 2); (void) IdxA;
1690 --IdxB; assert(IdxB < 2);
1691 return Rows[0][IdxB];
1692}
1693
1694unsigned AVRGenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
1695 static const uint8_t Table[2][2] = {
1696 { 0, 0, },
1697 { 0, 0, },
1698 };
1699
1700 --IdxA; assert(IdxA < 2);
1701 --IdxB; assert(IdxB < 2);
1702 return Table[IdxA][IdxB];
1703 }
1704
1705 struct MaskRolOp {
1706 LaneBitmask Mask;
1707 uint8_t RotateLeft;
1708 };
1709 static const MaskRolOp LaneMaskComposeSequences[] = {
1710 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 0 }, { LaneBitmask::getNone(), 0 }, // Sequence 0
1711 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 1 }, { LaneBitmask::getNone(), 0 } // Sequence 2
1712 };
1713 static const uint8_t CompositeSequences[] = {
1714 0, // to sub_hi
1715 2 // to sub_lo
1716 };
1717
1718LaneBitmask AVRGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
1719 --IdxA; assert(IdxA < 2 && "Subregister index out of bounds");
1720 LaneBitmask Result;
1721 for (const MaskRolOp *Ops =
1722 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
1723 Ops->Mask.any(); ++Ops) {
1724 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
1725 if (unsigned S = Ops->RotateLeft)
1726 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
1727 else
1728 Result |= LaneBitmask(M);
1729 }
1730 return Result;
1731}
1732
1733LaneBitmask AVRGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
1734 LaneMask &= getSubRegIndexLaneMask(IdxA);
1735 --IdxA; assert(IdxA < 2 && "Subregister index out of bounds");
1736 LaneBitmask Result;
1737 for (const MaskRolOp *Ops =
1738 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
1739 Ops->Mask.any(); ++Ops) {
1740 LaneBitmask::Type M = LaneMask.getAsInteger();
1741 if (unsigned S = Ops->RotateLeft)
1742 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
1743 else
1744 Result |= LaneBitmask(M);
1745 }
1746 return Result;
1747}
1748
1749const TargetRegisterClass *AVRGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
1750 static const uint8_t Table[23][2] = {
1751 { // GPR8
1752 0, // sub_hi
1753 0, // sub_lo
1754 },
1755 { // GPR8lo
1756 0, // sub_hi
1757 0, // sub_lo
1758 },
1759 { // LD8
1760 0, // sub_hi
1761 0, // sub_lo
1762 },
1763 { // LD8lo
1764 0, // sub_hi
1765 0, // sub_lo
1766 },
1767 { // CCR
1768 0, // sub_hi
1769 0, // sub_lo
1770 },
1771 { // DREGS
1772 6, // sub_hi -> DREGS
1773 6, // sub_lo -> DREGS
1774 },
1775 { // DREGSMOVW
1776 7, // sub_hi -> DREGSMOVW
1777 7, // sub_lo -> DREGSMOVW
1778 },
1779 { // DREGS_with_sub_hi_in_LD8
1780 8, // sub_hi -> DREGS_with_sub_hi_in_LD8
1781 8, // sub_lo -> DREGS_with_sub_hi_in_LD8
1782 },
1783 { // DREGS_with_sub_lo_in_LD8
1784 9, // sub_hi -> DREGS_with_sub_lo_in_LD8
1785 9, // sub_lo -> DREGS_with_sub_lo_in_LD8
1786 },
1787 { // DREGS_with_sub_lo_in_GPR8lo
1788 10, // sub_hi -> DREGS_with_sub_lo_in_GPR8lo
1789 10, // sub_lo -> DREGS_with_sub_lo_in_GPR8lo
1790 },
1791 { // DREGS_with_sub_hi_in_GPR8lo
1792 11, // sub_hi -> DREGS_with_sub_hi_in_GPR8lo
1793 11, // sub_lo -> DREGS_with_sub_hi_in_GPR8lo
1794 },
1795 { // DLDREGS
1796 12, // sub_hi -> DLDREGS
1797 12, // sub_lo -> DLDREGS
1798 },
1799 { // DREGS_with_sub_hi_in_LD8lo
1800 13, // sub_hi -> DREGS_with_sub_hi_in_LD8lo
1801 13, // sub_lo -> DREGS_with_sub_hi_in_LD8lo
1802 },
1803 { // DREGS_with_sub_lo_in_LD8lo
1804 14, // sub_hi -> DREGS_with_sub_lo_in_LD8lo
1805 14, // sub_lo -> DREGS_with_sub_lo_in_LD8lo
1806 },
1807 { // DREGSlo
1808 15, // sub_hi -> DREGSlo
1809 15, // sub_lo -> DREGSlo
1810 },
1811 { // DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8
1812 16, // sub_hi -> DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8
1813 16, // sub_lo -> DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8
1814 },
1815 { // DREGSLD8lo
1816 17, // sub_hi -> DREGSLD8lo
1817 17, // sub_lo -> DREGSLD8lo
1818 },
1819 { // IWREGS
1820 18, // sub_hi -> IWREGS
1821 18, // sub_lo -> IWREGS
1822 },
1823 { // PTRREGS
1824 19, // sub_hi -> PTRREGS
1825 19, // sub_lo -> PTRREGS
1826 },
1827 { // PTRDISPREGS
1828 20, // sub_hi -> PTRDISPREGS
1829 20, // sub_lo -> PTRDISPREGS
1830 },
1831 { // DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo
1832 21, // sub_hi -> DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo
1833 21, // sub_lo -> DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo
1834 },
1835 { // GPRSP
1836 22, // sub_hi -> GPRSP
1837 22, // sub_lo -> GPRSP
1838 },
1839 { // ZREG
1840 23, // sub_hi -> ZREG
1841 23, // sub_lo -> ZREG
1842 },
1843 };
1844 assert(RC && "Missing regclass");
1845 if (!Idx) return RC;
1846 --Idx;
1847 assert(Idx < 2 && "Bad subreg");
1848 unsigned TV = Table[RC->getID()][Idx];
1849 return TV ? getRegClass(TV - 1) : nullptr;
1850}
1851
1852const TargetRegisterClass *AVRGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
1853 static const uint8_t Table[23][2] = {
1854 { // GPR8
1855 0, // GPR8:sub_hi
1856 0, // GPR8:sub_lo
1857 },
1858 { // GPR8lo
1859 0, // GPR8lo:sub_hi
1860 0, // GPR8lo:sub_lo
1861 },
1862 { // LD8
1863 0, // LD8:sub_hi
1864 0, // LD8:sub_lo
1865 },
1866 { // LD8lo
1867 0, // LD8lo:sub_hi
1868 0, // LD8lo:sub_lo
1869 },
1870 { // CCR
1871 0, // CCR:sub_hi
1872 0, // CCR:sub_lo
1873 },
1874 { // DREGS
1875 1, // DREGS:sub_hi -> GPR8
1876 1, // DREGS:sub_lo -> GPR8
1877 },
1878 { // DREGSMOVW
1879 1, // DREGSMOVW:sub_hi -> GPR8
1880 1, // DREGSMOVW:sub_lo -> GPR8
1881 },
1882 { // DREGS_with_sub_hi_in_LD8
1883 3, // DREGS_with_sub_hi_in_LD8:sub_hi -> LD8
1884 1, // DREGS_with_sub_hi_in_LD8:sub_lo -> GPR8
1885 },
1886 { // DREGS_with_sub_lo_in_LD8
1887 3, // DREGS_with_sub_lo_in_LD8:sub_hi -> LD8
1888 3, // DREGS_with_sub_lo_in_LD8:sub_lo -> LD8
1889 },
1890 { // DREGS_with_sub_lo_in_GPR8lo
1891 1, // DREGS_with_sub_lo_in_GPR8lo:sub_hi -> GPR8
1892 2, // DREGS_with_sub_lo_in_GPR8lo:sub_lo -> GPR8lo
1893 },
1894 { // DREGS_with_sub_hi_in_GPR8lo
1895 2, // DREGS_with_sub_hi_in_GPR8lo:sub_hi -> GPR8lo
1896 2, // DREGS_with_sub_hi_in_GPR8lo:sub_lo -> GPR8lo
1897 },
1898 { // DLDREGS
1899 3, // DLDREGS:sub_hi -> LD8
1900 3, // DLDREGS:sub_lo -> LD8
1901 },
1902 { // DREGS_with_sub_hi_in_LD8lo
1903 4, // DREGS_with_sub_hi_in_LD8lo:sub_hi -> LD8lo
1904 1, // DREGS_with_sub_hi_in_LD8lo:sub_lo -> GPR8
1905 },
1906 { // DREGS_with_sub_lo_in_LD8lo
1907 3, // DREGS_with_sub_lo_in_LD8lo:sub_hi -> LD8
1908 4, // DREGS_with_sub_lo_in_LD8lo:sub_lo -> LD8lo
1909 },
1910 { // DREGSlo
1911 2, // DREGSlo:sub_hi -> GPR8lo
1912 2, // DREGSlo:sub_lo -> GPR8lo
1913 },
1914 { // DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8
1915 4, // DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8:sub_hi -> LD8lo
1916 4, // DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8:sub_lo -> LD8lo
1917 },
1918 { // DREGSLD8lo
1919 4, // DREGSLD8lo:sub_hi -> LD8lo
1920 4, // DREGSLD8lo:sub_lo -> LD8lo
1921 },
1922 { // IWREGS
1923 3, // IWREGS:sub_hi -> LD8
1924 3, // IWREGS:sub_lo -> LD8
1925 },
1926 { // PTRREGS
1927 3, // PTRREGS:sub_hi -> LD8
1928 3, // PTRREGS:sub_lo -> LD8
1929 },
1930 { // PTRDISPREGS
1931 3, // PTRDISPREGS:sub_hi -> LD8
1932 3, // PTRDISPREGS:sub_lo -> LD8
1933 },
1934 { // DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo
1935 4, // DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo:sub_hi -> LD8lo
1936 2, // DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo:sub_lo -> GPR8lo
1937 },
1938 { // GPRSP
1939 0, // GPRSP:sub_hi
1940 0, // GPRSP:sub_lo
1941 },
1942 { // ZREG
1943 3, // ZREG:sub_hi -> LD8
1944 3, // ZREG:sub_lo -> LD8
1945 },
1946 };
1947 assert(RC && "Missing regclass");
1948 if (!Idx) return RC;
1949 --Idx;
1950 assert(Idx < 2 && "Bad subreg");
1951 unsigned TV = Table[RC->getID()][Idx];
1952 return TV ? getRegClass(TV - 1) : nullptr;
1953}
1954
1955/// Get the weight in units of pressure for this register class.
1956const RegClassWeight &AVRGenRegisterInfo::
1957getRegClassWeight(const TargetRegisterClass *RC) const {
1958 static const RegClassWeight RCWeightTable[] = {
1959 {1, 32}, // GPR8
1960 {1, 16}, // GPR8lo
1961 {1, 16}, // LD8
1962 {1, 8}, // LD8lo
1963 {1, 1}, // CCR
1964 {2, 32}, // DREGS
1965 {2, 32}, // DREGSMOVW
1966 {2, 17}, // DREGS_with_sub_hi_in_LD8
1967 {2, 16}, // DREGS_with_sub_lo_in_LD8
1968 {2, 17}, // DREGS_with_sub_lo_in_GPR8lo
1969 {2, 16}, // DREGS_with_sub_hi_in_GPR8lo
1970 {2, 16}, // DLDREGS
1971 {2, 9}, // DREGS_with_sub_hi_in_LD8lo
1972 {2, 9}, // DREGS_with_sub_lo_in_LD8lo
1973 {2, 16}, // DREGSlo
1974 {2, 8}, // DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8
1975 {2, 8}, // DREGSLD8lo
1976 {2, 8}, // IWREGS
1977 {2, 6}, // PTRREGS
1978 {2, 4}, // PTRDISPREGS
1979 {2, 2}, // DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo
1980 {2, 2}, // GPRSP
1981 {2, 2}, // ZREG
1982 };
1983 return RCWeightTable[RC->getID()];
1984}
1985
1986/// Get the weight in units of pressure for this register unit.
1987unsigned AVRGenRegisterInfo::
1988getRegUnitWeight(unsigned RegUnit) const {
1989 assert(RegUnit < 35 && "invalid register unit");
1990 // All register units have unit weight.
1991 return 1;
1992}
1993
1994
1995// Get the number of dimensions of register pressure.
1996unsigned AVRGenRegisterInfo::getNumRegPressureSets() const {
1997 return 9;
1998}
1999
2000// Get the name of this register unit pressure set.
2001const char *AVRGenRegisterInfo::
2002getRegPressureSetName(unsigned Idx) const {
2003 static const char *PressureNameTable[] = {
2004 "CCR",
2005 "DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo",
2006 "GPRSP",
2007 "IWREGS",
2008 "LD8lo",
2009 "LD8",
2010 "GPR8lo",
2011 "GPR8lo_with_LD8lo",
2012 "GPR8",
2013 };
2014 return PressureNameTable[Idx];
2015}
2016
2017// Get the register unit pressure limit for this dimension.
2018// This limit must be adjusted dynamically for reserved registers.
2019unsigned AVRGenRegisterInfo::
2020getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
2021 static const uint8_t PressureLimitTable[] = {
2022 1, // 0: CCR
2023 2, // 1: DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo
2024 2, // 2: GPRSP
2025 8, // 3: IWREGS
2026 10, // 4: LD8lo
2027 17, // 5: LD8
2028 17, // 6: GPR8lo
2029 25, // 7: GPR8lo_with_LD8lo
2030 32, // 8: GPR8
2031 };
2032 return PressureLimitTable[Idx];
2033}
2034
2035/// Table of pressure sets per register class or unit.
2036static const int RCSetsTable[] = {
2037 /* 0 */ 0, -1,
2038 /* 2 */ 2, -1,
2039 /* 4 */ 3, 5, 8, -1,
2040 /* 8 */ 3, 4, 5, 7, 8, -1,
2041 /* 14 */ 1, 4, 5, 6, 7, 8, -1,
2042};
2043
2044/// Get the dimensions of register pressure impacted by this register class.
2045/// Returns a -1 terminated array of pressure set IDs
2046const int *AVRGenRegisterInfo::
2047getRegClassPressureSets(const TargetRegisterClass *RC) const {
2048 static const uint8_t RCSetStartTable[] = {
2049 6,17,5,9,0,6,6,5,5,17,17,5,9,9,17,9,9,4,4,4,14,2,4,};
2050 return &RCSetsTable[RCSetStartTable[RC->getID()]];
2051}
2052
2053/// Get the dimensions of register pressure impacted by this register unit.
2054/// Returns a -1 terminated array of pressure set IDs
2055const int *AVRGenRegisterInfo::
2056getRegUnitPressureSets(unsigned RegUnit) const {
2057 assert(RegUnit < 35 && "invalid register unit");
2058 static const uint8_t RUSetStartTable[] = {
2059 2,2,0,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,14,14,9,9,9,9,9,9,9,8,4,4,4,4,4,4,4,};
2060 return &RCSetsTable[RUSetStartTable[RegUnit]];
2061}
2062
2063extern const MCRegisterDesc AVRRegDesc[];
2064extern const int16_t AVRRegDiffLists[];
2065extern const LaneBitmask AVRLaneMaskLists[];
2066extern const char AVRRegStrings[];
2067extern const char AVRRegClassStrings[];
2068extern const MCPhysReg AVRRegUnitRoots[][2];
2069extern const uint16_t AVRSubRegIdxLists[];
2070extern const uint16_t AVRRegEncodingTable[];
2071// AVR Dwarf<->LLVM register mappings.
2072extern const MCRegisterInfo::DwarfLLVMRegPair AVRDwarfFlavour0Dwarf2L[];
2073extern const unsigned AVRDwarfFlavour0Dwarf2LSize;
2074
2075extern const MCRegisterInfo::DwarfLLVMRegPair AVREHFlavour0Dwarf2L[];
2076extern const unsigned AVREHFlavour0Dwarf2LSize;
2077
2078extern const MCRegisterInfo::DwarfLLVMRegPair AVRDwarfFlavour0L2Dwarf[];
2079extern const unsigned AVRDwarfFlavour0L2DwarfSize;
2080
2081extern const MCRegisterInfo::DwarfLLVMRegPair AVREHFlavour0L2Dwarf[];
2082extern const unsigned AVREHFlavour0L2DwarfSize;
2083
2084AVRGenRegisterInfo::
2085AVRGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
2086 unsigned PC, unsigned HwMode)
2087 : TargetRegisterInfo(&AVRRegInfoDesc, RegisterClasses, RegisterClasses+23,
2088 SubRegIndexNameTable, SubRegIdxRangeTable, SubRegIndexLaneMaskTable,
2089 LaneBitmask(0xFFFFFFFFFFFFFFFF), RegClassInfos, VTLists, HwMode) {
2090 InitMCRegisterInfo(AVRRegDesc, 62, RA, PC,
2091 AVRMCRegisterClasses, 23,
2092 AVRRegUnitRoots,
2093 35,
2094 AVRRegDiffLists,
2095 AVRLaneMaskLists,
2096 AVRRegStrings,
2097 AVRRegClassStrings,
2098 AVRSubRegIdxLists,
2099 3,
2100 AVRRegEncodingTable);
2101
2102 switch (DwarfFlavour) {
2103 default:
2104 llvm_unreachable("Unknown DWARF flavour");
2105 case 0:
2106 mapDwarfRegsToLLVMRegs(AVRDwarfFlavour0Dwarf2L, AVRDwarfFlavour0Dwarf2LSize, false);
2107 break;
2108 }
2109 switch (EHFlavour) {
2110 default:
2111 llvm_unreachable("Unknown DWARF flavour");
2112 case 0:
2113 mapDwarfRegsToLLVMRegs(AVREHFlavour0Dwarf2L, AVREHFlavour0Dwarf2LSize, true);
2114 break;
2115 }
2116 switch (DwarfFlavour) {
2117 default:
2118 llvm_unreachable("Unknown DWARF flavour");
2119 case 0:
2120 mapLLVMRegsToDwarfRegs(AVRDwarfFlavour0L2Dwarf, AVRDwarfFlavour0L2DwarfSize, false);
2121 break;
2122 }
2123 switch (EHFlavour) {
2124 default:
2125 llvm_unreachable("Unknown DWARF flavour");
2126 case 0:
2127 mapLLVMRegsToDwarfRegs(AVREHFlavour0L2Dwarf, AVREHFlavour0L2DwarfSize, true);
2128 break;
2129 }
2130}
2131
2132static const MCPhysReg CSR_Interrupts_SaveList[] = { AVR::R31, AVR::R30, AVR::R29, AVR::R28, AVR::R27, AVR::R26, AVR::R25, AVR::R24, AVR::R23, AVR::R22, AVR::R21, AVR::R20, AVR::R19, AVR::R18, AVR::R17, AVR::R16, AVR::R15, AVR::R14, AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8, AVR::R7, AVR::R6, AVR::R5, AVR::R4, AVR::R3, AVR::R2, 0 };
2133static const uint32_t CSR_Interrupts_RegMask[] = { 0xffffff80, 0x3fffffdf, };
2134static const MCPhysReg CSR_InterruptsTiny_SaveList[] = { AVR::R31, AVR::R30, AVR::R29, AVR::R28, AVR::R27, AVR::R26, AVR::R25, AVR::R24, AVR::R23, AVR::R22, AVR::R21, AVR::R20, AVR::R19, AVR::R18, 0 };
2135static const uint32_t CSR_InterruptsTiny_RegMask[] = { 0xff800000, 0x3ff8001f, };
2136static const MCPhysReg CSR_Normal_SaveList[] = { AVR::R29, AVR::R28, AVR::R17, AVR::R16, AVR::R15, AVR::R14, AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8, AVR::R7, AVR::R6, AVR::R5, AVR::R4, AVR::R3, AVR::R2, 0 };
2137static const uint32_t CSR_Normal_RegMask[] = { 0x007fff80, 0x1003ffc6, };
2138static const MCPhysReg CSR_NormalTiny_SaveList[] = { AVR::R29, AVR::R28, AVR::R19, AVR::R18, 0 };
2139static const uint32_t CSR_NormalTiny_RegMask[] = { 0x01800000, 0x10080006, };
2140
2141
2142ArrayRef<const uint32_t *> AVRGenRegisterInfo::getRegMasks() const {
2143 static const uint32_t *const Masks[] = {
2144 CSR_Interrupts_RegMask,
2145 CSR_InterruptsTiny_RegMask,
2146 CSR_Normal_RegMask,
2147 CSR_NormalTiny_RegMask,
2148 };
2149 return ArrayRef(Masks);
2150}
2151
2152bool AVRGenRegisterInfo::
2153isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
2154 return
2155 false;
2156}
2157
2158bool AVRGenRegisterInfo::
2159isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
2160 return
2161 false;
2162}
2163
2164bool AVRGenRegisterInfo::
2165isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
2166 return
2167 false;
2168}
2169
2170bool AVRGenRegisterInfo::
2171isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
2172 return
2173 false;
2174}
2175
2176bool AVRGenRegisterInfo::
2177isConstantPhysReg(MCRegister PhysReg) const {
2178 return
2179 false;
2180}
2181
2182ArrayRef<const char *> AVRGenRegisterInfo::getRegMaskNames() const {
2183 static const char *Names[] = {
2184 "CSR_Interrupts",
2185 "CSR_InterruptsTiny",
2186 "CSR_Normal",
2187 "CSR_NormalTiny",
2188 };
2189 return ArrayRef(Names);
2190}
2191
2192const AVRFrameLowering *
2193AVRGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
2194 return static_cast<const AVRFrameLowering *>(
2195 MF.getSubtarget().getFrameLowering());
2196}
2197
2198} // end namespace llvm
2199
2200#endif // GET_REGINFO_TARGET_DESC
2201
2202