1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register Enum Values *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_REGINFO_ENUM
11#undef GET_REGINFO_ENUM
12
13namespace llvm {
14
15class MCRegisterClass;
16extern const MCRegisterClass LanaiMCRegisterClasses[];
17
18namespace Lanai {
19enum : unsigned {
20 NoRegister,
21 FP = 1,
22 PC = 2,
23 RCA = 3,
24 RV = 4,
25 SP = 5,
26 SR = 6,
27 R0 = 7,
28 R1 = 8,
29 R2 = 9,
30 R3 = 10,
31 R4 = 11,
32 R5 = 12,
33 R6 = 13,
34 R7 = 14,
35 R8 = 15,
36 R9 = 16,
37 R10 = 17,
38 R11 = 18,
39 R12 = 19,
40 R13 = 20,
41 R14 = 21,
42 R15 = 22,
43 R16 = 23,
44 R17 = 24,
45 R18 = 25,
46 R19 = 26,
47 R20 = 27,
48 R21 = 28,
49 R22 = 29,
50 R23 = 30,
51 R24 = 31,
52 R25 = 32,
53 R26 = 33,
54 R27 = 34,
55 R28 = 35,
56 R29 = 36,
57 R30 = 37,
58 R31 = 38,
59 RR1 = 39,
60 RR2 = 40,
61 NUM_TARGET_REGS // 41
62};
63} // end namespace Lanai
64
65// Register classes
66
67namespace Lanai {
68enum {
69 GPRRegClassID = 0,
70 GPR_with_sub_32RegClassID = 1,
71 CCRRegClassID = 2,
72
73};
74} // end namespace Lanai
75
76
77// Subregister indices
78
79namespace Lanai {
80enum : uint16_t {
81 NoSubRegister,
82 sub_32, // 1
83 NUM_TARGET_SUBREGS
84};
85} // end namespace Lanai
86
87// Register pressure sets enum.
88namespace Lanai {
89enum RegisterPressureSets {
90 GPR_with_sub_32 = 0,
91 GPR = 1,
92};
93} // end namespace Lanai
94
95} // end namespace llvm
96
97#endif // GET_REGINFO_ENUM
98
99/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
100|* *|
101|* MC Register Information *|
102|* *|
103|* Automatically generated file, do not edit! *|
104|* *|
105\*===----------------------------------------------------------------------===*/
106
107
108#ifdef GET_REGINFO_MC_DESC
109#undef GET_REGINFO_MC_DESC
110
111namespace llvm {
112
113extern const int16_t LanaiRegDiffLists[] = {
114 /* 0 */ -22, 0,
115 /* 2 */ -19, 0,
116 /* 4 */ -11, 0,
117 /* 6 */ -7, 0,
118 /* 8 */ -6, 0,
119 /* 10 */ 6, 0,
120 /* 12 */ 7, 0,
121 /* 14 */ 11, 0,
122 /* 16 */ 19, 0,
123 /* 18 */ 22, 0,
124};
125
126extern const LaneBitmask LanaiLaneMaskLists[] = {
127 /* 0 */ LaneBitmask(0x0000000000000001),
128 /* 1 */ LaneBitmask(0xFFFFFFFFFFFFFFFF),
129};
130
131extern const uint16_t LanaiSubRegIdxLists[] = {
132 /* 0 */ 1,
133};
134
135
136#ifdef __GNUC__
137#pragma GCC diagnostic push
138#pragma GCC diagnostic ignored "-Woverlength-strings"
139#endif
140extern const char LanaiRegStrings[] = {
141 /* 0 */ "R10\000"
142 /* 4 */ "R20\000"
143 /* 8 */ "R30\000"
144 /* 12 */ "R0\000"
145 /* 15 */ "R11\000"
146 /* 19 */ "R21\000"
147 /* 23 */ "R31\000"
148 /* 27 */ "RR1\000"
149 /* 31 */ "R12\000"
150 /* 35 */ "R22\000"
151 /* 39 */ "RR2\000"
152 /* 43 */ "R13\000"
153 /* 47 */ "R23\000"
154 /* 51 */ "R3\000"
155 /* 54 */ "R14\000"
156 /* 58 */ "R24\000"
157 /* 62 */ "R4\000"
158 /* 65 */ "R15\000"
159 /* 69 */ "R25\000"
160 /* 73 */ "R5\000"
161 /* 76 */ "R16\000"
162 /* 80 */ "R26\000"
163 /* 84 */ "R6\000"
164 /* 87 */ "R17\000"
165 /* 91 */ "R27\000"
166 /* 95 */ "R7\000"
167 /* 98 */ "R18\000"
168 /* 102 */ "R28\000"
169 /* 106 */ "R8\000"
170 /* 109 */ "R19\000"
171 /* 113 */ "R29\000"
172 /* 117 */ "R9\000"
173 /* 120 */ "RCA\000"
174 /* 124 */ "PC\000"
175 /* 127 */ "FP\000"
176 /* 130 */ "SP\000"
177 /* 133 */ "SR\000"
178 /* 136 */ "RV\000"
179};
180#ifdef __GNUC__
181#pragma GCC diagnostic pop
182#endif
183
184extern const MCRegisterDesc LanaiRegDesc[] = { // Descriptors
185 { 3, 0, 0, 0, 0, 0, 0, 0 },
186 { 127, 14, 1, 0, 4096, 0, 0, 0 },
187 { 124, 12, 1, 0, 4097, 0, 0, 0 },
188 { 120, 16, 1, 0, 4098, 0, 0, 0 },
189 { 136, 14, 1, 0, 4099, 0, 0, 0 },
190 { 130, 10, 1, 0, 4100, 0, 0, 0 },
191 { 133, 1, 1, 1, 4101, 1, 0, 0 },
192 { 12, 1, 1, 1, 4102, 1, 0, 0 },
193 { 28, 1, 1, 1, 4103, 1, 0, 0 },
194 { 40, 1, 6, 1, 4097, 1, 0, 0 },
195 { 51, 1, 1, 1, 4104, 1, 0, 0 },
196 { 62, 1, 8, 1, 4100, 1, 0, 0 },
197 { 73, 1, 4, 1, 4096, 1, 0, 0 },
198 { 84, 1, 1, 1, 4105, 1, 0, 0 },
199 { 95, 1, 1, 1, 4106, 1, 0, 0 },
200 { 106, 1, 4, 1, 4099, 1, 0, 0 },
201 { 117, 1, 1, 1, 4107, 1, 0, 0 },
202 { 0, 1, 18, 1, 4108, 1, 0, 0 },
203 { 15, 1, 18, 1, 4109, 1, 0, 0 },
204 { 31, 1, 1, 1, 4110, 1, 0, 0 },
205 { 43, 1, 1, 1, 4111, 1, 0, 0 },
206 { 54, 1, 1, 1, 4112, 1, 0, 0 },
207 { 65, 1, 2, 1, 4098, 1, 0, 0 },
208 { 76, 1, 1, 1, 4113, 1, 0, 0 },
209 { 87, 1, 1, 1, 4114, 1, 0, 0 },
210 { 98, 1, 1, 1, 4115, 1, 0, 0 },
211 { 109, 1, 1, 1, 4116, 1, 0, 0 },
212 { 4, 1, 1, 1, 4117, 1, 0, 0 },
213 { 19, 1, 1, 1, 4118, 1, 0, 0 },
214 { 35, 1, 1, 1, 4119, 1, 0, 0 },
215 { 47, 1, 1, 1, 4120, 1, 0, 0 },
216 { 58, 1, 1, 1, 4121, 1, 0, 0 },
217 { 69, 1, 1, 1, 4122, 1, 0, 0 },
218 { 80, 1, 1, 1, 4123, 1, 0, 0 },
219 { 91, 1, 1, 1, 4124, 1, 0, 0 },
220 { 102, 1, 1, 1, 4125, 1, 0, 0 },
221 { 113, 1, 1, 1, 4126, 1, 0, 0 },
222 { 8, 1, 1, 1, 4127, 1, 0, 0 },
223 { 23, 1, 1, 1, 4128, 1, 0, 0 },
224 { 27, 0, 1, 0, 4108, 0, 0, 0 },
225 { 39, 0, 1, 0, 4109, 0, 0, 0 },
226};
227
228extern const MCPhysReg LanaiRegUnitRoots[][2] = {
229 { Lanai::R5 },
230 { Lanai::R2 },
231 { Lanai::R15 },
232 { Lanai::R8 },
233 { Lanai::R4 },
234 { Lanai::SR },
235 { Lanai::R0 },
236 { Lanai::R1 },
237 { Lanai::R3 },
238 { Lanai::R6 },
239 { Lanai::R7 },
240 { Lanai::R9 },
241 { Lanai::R10 },
242 { Lanai::R11 },
243 { Lanai::R12 },
244 { Lanai::R13 },
245 { Lanai::R14 },
246 { Lanai::R16 },
247 { Lanai::R17 },
248 { Lanai::R18 },
249 { Lanai::R19 },
250 { Lanai::R20 },
251 { Lanai::R21 },
252 { Lanai::R22 },
253 { Lanai::R23 },
254 { Lanai::R24 },
255 { Lanai::R25 },
256 { Lanai::R26 },
257 { Lanai::R27 },
258 { Lanai::R28 },
259 { Lanai::R29 },
260 { Lanai::R30 },
261 { Lanai::R31 },
262};
263
264namespace { // Register classes...
265 // GPR Register Class...
266 const MCPhysReg GPR[] = {
267 Lanai::R3, Lanai::R9, Lanai::R12, Lanai::R13, Lanai::R14, Lanai::R16, Lanai::R17, Lanai::R20, Lanai::R21, Lanai::R22, Lanai::R23, Lanai::R24, Lanai::R25, Lanai::R26, Lanai::R27, Lanai::R28, Lanai::R29, Lanai::R30, Lanai::R31, Lanai::R6, Lanai::R7, Lanai::R18, Lanai::R19, Lanai::R15, Lanai::RCA, Lanai::R10, Lanai::RR1, Lanai::R11, Lanai::RR2, Lanai::R8, Lanai::RV, Lanai::R5, Lanai::FP, Lanai::R4, Lanai::SP, Lanai::R2, Lanai::PC, Lanai::R1, Lanai::R0,
268 };
269
270 // GPR Bit set.
271 const uint8_t GPRBits[] = {
272 0xbe, 0xff, 0xff, 0xff, 0xff, 0x01,
273 };
274
275 // GPR_with_sub_32 Register Class...
276 const MCPhysReg GPR_with_sub_32[] = {
277 Lanai::RCA, Lanai::RR1, Lanai::RR2, Lanai::RV, Lanai::FP, Lanai::SP, Lanai::PC,
278 };
279
280 // GPR_with_sub_32 Bit set.
281 const uint8_t GPR_with_sub_32Bits[] = {
282 0x3e, 0x00, 0x00, 0x00, 0x80, 0x01,
283 };
284
285 // CCR Register Class...
286 const MCPhysReg CCR[] = {
287 Lanai::SR,
288 };
289
290 // CCR Bit set.
291 const uint8_t CCRBits[] = {
292 0x40,
293 };
294
295} // end anonymous namespace
296
297
298#ifdef __GNUC__
299#pragma GCC diagnostic push
300#pragma GCC diagnostic ignored "-Woverlength-strings"
301#endif
302extern const char LanaiRegClassStrings[] = {
303 /* 0 */ "GPR_with_sub_32\000"
304 /* 16 */ "CCR\000"
305 /* 20 */ "GPR\000"
306};
307#ifdef __GNUC__
308#pragma GCC diagnostic pop
309#endif
310
311extern const MCRegisterClass LanaiMCRegisterClasses[] = {
312 { GPR, GPRBits, 20, 39, sizeof(GPRBits), Lanai::GPRRegClassID, 32, 1, true, false },
313 { GPR_with_sub_32, GPR_with_sub_32Bits, 0, 7, sizeof(GPR_with_sub_32Bits), Lanai::GPR_with_sub_32RegClassID, 32, 1, true, false },
314 { CCR, CCRBits, 16, 1, sizeof(CCRBits), Lanai::CCRRegClassID, 32, -1, false, false },
315};
316
317// Lanai Dwarf<->LLVM register mappings.
318extern const MCRegisterInfo::DwarfLLVMRegPair LanaiDwarfFlavour0Dwarf2L[] = {
319 { 0U, Lanai::R0 },
320 { 1U, Lanai::R1 },
321 { 2U, Lanai::R2 },
322 { 3U, Lanai::R3 },
323 { 4U, Lanai::R4 },
324 { 5U, Lanai::R5 },
325 { 6U, Lanai::R6 },
326 { 7U, Lanai::R7 },
327 { 8U, Lanai::R8 },
328 { 9U, Lanai::R9 },
329 { 10U, Lanai::R10 },
330 { 11U, Lanai::R11 },
331 { 12U, Lanai::R12 },
332 { 13U, Lanai::R13 },
333 { 14U, Lanai::R14 },
334 { 15U, Lanai::R15 },
335 { 16U, Lanai::R16 },
336 { 17U, Lanai::R17 },
337 { 18U, Lanai::R18 },
338 { 19U, Lanai::R19 },
339 { 20U, Lanai::R20 },
340 { 21U, Lanai::R21 },
341 { 22U, Lanai::R22 },
342 { 23U, Lanai::R23 },
343 { 24U, Lanai::R24 },
344 { 25U, Lanai::R25 },
345 { 26U, Lanai::R26 },
346 { 27U, Lanai::R27 },
347 { 28U, Lanai::R28 },
348 { 29U, Lanai::R29 },
349 { 30U, Lanai::R30 },
350 { 31U, Lanai::R31 },
351};
352extern const unsigned LanaiDwarfFlavour0Dwarf2LSize = std::size(LanaiDwarfFlavour0Dwarf2L);
353
354extern const MCRegisterInfo::DwarfLLVMRegPair LanaiEHFlavour0Dwarf2L[] = {
355 { 0U, Lanai::R0 },
356 { 1U, Lanai::R1 },
357 { 2U, Lanai::R2 },
358 { 3U, Lanai::R3 },
359 { 4U, Lanai::R4 },
360 { 5U, Lanai::R5 },
361 { 6U, Lanai::R6 },
362 { 7U, Lanai::R7 },
363 { 8U, Lanai::R8 },
364 { 9U, Lanai::R9 },
365 { 10U, Lanai::R10 },
366 { 11U, Lanai::R11 },
367 { 12U, Lanai::R12 },
368 { 13U, Lanai::R13 },
369 { 14U, Lanai::R14 },
370 { 15U, Lanai::R15 },
371 { 16U, Lanai::R16 },
372 { 17U, Lanai::R17 },
373 { 18U, Lanai::R18 },
374 { 19U, Lanai::R19 },
375 { 20U, Lanai::R20 },
376 { 21U, Lanai::R21 },
377 { 22U, Lanai::R22 },
378 { 23U, Lanai::R23 },
379 { 24U, Lanai::R24 },
380 { 25U, Lanai::R25 },
381 { 26U, Lanai::R26 },
382 { 27U, Lanai::R27 },
383 { 28U, Lanai::R28 },
384 { 29U, Lanai::R29 },
385 { 30U, Lanai::R30 },
386 { 31U, Lanai::R31 },
387};
388extern const unsigned LanaiEHFlavour0Dwarf2LSize = std::size(LanaiEHFlavour0Dwarf2L);
389
390extern const MCRegisterInfo::DwarfLLVMRegPair LanaiDwarfFlavour0L2Dwarf[] = {
391 { Lanai::FP, 5U },
392 { Lanai::PC, 2U },
393 { Lanai::RCA, 15U },
394 { Lanai::RV, 8U },
395 { Lanai::SP, 4U },
396 { Lanai::R0, 0U },
397 { Lanai::R1, 1U },
398 { Lanai::R2, 2U },
399 { Lanai::R3, 3U },
400 { Lanai::R4, 4U },
401 { Lanai::R5, 5U },
402 { Lanai::R6, 6U },
403 { Lanai::R7, 7U },
404 { Lanai::R8, 8U },
405 { Lanai::R9, 9U },
406 { Lanai::R10, 10U },
407 { Lanai::R11, 11U },
408 { Lanai::R12, 12U },
409 { Lanai::R13, 13U },
410 { Lanai::R14, 14U },
411 { Lanai::R15, 15U },
412 { Lanai::R16, 16U },
413 { Lanai::R17, 17U },
414 { Lanai::R18, 18U },
415 { Lanai::R19, 19U },
416 { Lanai::R20, 20U },
417 { Lanai::R21, 21U },
418 { Lanai::R22, 22U },
419 { Lanai::R23, 23U },
420 { Lanai::R24, 24U },
421 { Lanai::R25, 25U },
422 { Lanai::R26, 26U },
423 { Lanai::R27, 27U },
424 { Lanai::R28, 28U },
425 { Lanai::R29, 29U },
426 { Lanai::R30, 30U },
427 { Lanai::R31, 31U },
428 { Lanai::RR1, 10U },
429 { Lanai::RR2, 11U },
430};
431extern const unsigned LanaiDwarfFlavour0L2DwarfSize = std::size(LanaiDwarfFlavour0L2Dwarf);
432
433extern const MCRegisterInfo::DwarfLLVMRegPair LanaiEHFlavour0L2Dwarf[] = {
434 { Lanai::FP, 5U },
435 { Lanai::PC, 2U },
436 { Lanai::RCA, 15U },
437 { Lanai::RV, 8U },
438 { Lanai::SP, 4U },
439 { Lanai::R0, 0U },
440 { Lanai::R1, 1U },
441 { Lanai::R2, 2U },
442 { Lanai::R3, 3U },
443 { Lanai::R4, 4U },
444 { Lanai::R5, 5U },
445 { Lanai::R6, 6U },
446 { Lanai::R7, 7U },
447 { Lanai::R8, 8U },
448 { Lanai::R9, 9U },
449 { Lanai::R10, 10U },
450 { Lanai::R11, 11U },
451 { Lanai::R12, 12U },
452 { Lanai::R13, 13U },
453 { Lanai::R14, 14U },
454 { Lanai::R15, 15U },
455 { Lanai::R16, 16U },
456 { Lanai::R17, 17U },
457 { Lanai::R18, 18U },
458 { Lanai::R19, 19U },
459 { Lanai::R20, 20U },
460 { Lanai::R21, 21U },
461 { Lanai::R22, 22U },
462 { Lanai::R23, 23U },
463 { Lanai::R24, 24U },
464 { Lanai::R25, 25U },
465 { Lanai::R26, 26U },
466 { Lanai::R27, 27U },
467 { Lanai::R28, 28U },
468 { Lanai::R29, 29U },
469 { Lanai::R30, 30U },
470 { Lanai::R31, 31U },
471 { Lanai::RR1, 10U },
472 { Lanai::RR2, 11U },
473};
474extern const unsigned LanaiEHFlavour0L2DwarfSize = std::size(LanaiEHFlavour0L2Dwarf);
475
476extern const uint16_t LanaiRegEncodingTable[] = {
477 0,
478 0,
479 0,
480 0,
481 0,
482 0,
483 0,
484 0,
485 0,
486 0,
487 0,
488 0,
489 0,
490 0,
491 0,
492 0,
493 0,
494 0,
495 0,
496 0,
497 0,
498 0,
499 0,
500 0,
501 0,
502 0,
503 0,
504 0,
505 0,
506 0,
507 0,
508 0,
509 0,
510 0,
511 0,
512 0,
513 0,
514 0,
515 0,
516 0,
517 0,
518};
519static inline void InitLanaiMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
520 RI->InitMCRegisterInfo(LanaiRegDesc, 41, RA, PC, LanaiMCRegisterClasses, 3, LanaiRegUnitRoots, 33, LanaiRegDiffLists, LanaiLaneMaskLists, LanaiRegStrings, LanaiRegClassStrings, LanaiSubRegIdxLists, 2,
521LanaiRegEncodingTable);
522
523 switch (DwarfFlavour) {
524 default:
525 llvm_unreachable("Unknown DWARF flavour");
526 case 0:
527 RI->mapDwarfRegsToLLVMRegs(LanaiDwarfFlavour0Dwarf2L, LanaiDwarfFlavour0Dwarf2LSize, false);
528 break;
529 }
530 switch (EHFlavour) {
531 default:
532 llvm_unreachable("Unknown DWARF flavour");
533 case 0:
534 RI->mapDwarfRegsToLLVMRegs(LanaiEHFlavour0Dwarf2L, LanaiEHFlavour0Dwarf2LSize, true);
535 break;
536 }
537 switch (DwarfFlavour) {
538 default:
539 llvm_unreachable("Unknown DWARF flavour");
540 case 0:
541 RI->mapLLVMRegsToDwarfRegs(LanaiDwarfFlavour0L2Dwarf, LanaiDwarfFlavour0L2DwarfSize, false);
542 break;
543 }
544 switch (EHFlavour) {
545 default:
546 llvm_unreachable("Unknown DWARF flavour");
547 case 0:
548 RI->mapLLVMRegsToDwarfRegs(LanaiEHFlavour0L2Dwarf, LanaiEHFlavour0L2DwarfSize, true);
549 break;
550 }
551}
552
553} // end namespace llvm
554
555#endif // GET_REGINFO_MC_DESC
556
557/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
558|* *|
559|* Register Information Header Fragment *|
560|* *|
561|* Automatically generated file, do not edit! *|
562|* *|
563\*===----------------------------------------------------------------------===*/
564
565
566#ifdef GET_REGINFO_HEADER
567#undef GET_REGINFO_HEADER
568
569#include "llvm/CodeGen/TargetRegisterInfo.h"
570
571namespace llvm {
572
573class LanaiFrameLowering;
574
575struct LanaiGenRegisterInfo : public TargetRegisterInfo {
576 explicit LanaiGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
577 unsigned PC = 0, unsigned HwMode = 0);
578 unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
579 unsigned reverseComposeSubRegIndicesImpl(unsigned, unsigned) const override;
580 LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
581 LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
582 const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass *, unsigned) const override;
583 const TargetRegisterClass *getSubRegisterClass(const TargetRegisterClass *, unsigned) const override;
584 const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
585 unsigned getRegUnitWeight(unsigned RegUnit) const override;
586 unsigned getNumRegPressureSets() const override;
587 const char *getRegPressureSetName(unsigned Idx) const override;
588 unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
589 const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
590 const int *getRegUnitPressureSets(unsigned RegUnit) const override;
591 ArrayRef<const char *> getRegMaskNames() const override;
592 ArrayRef<const uint32_t *> getRegMasks() const override;
593 bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override;
594 bool isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const override;
595 bool isFixedRegister(const MachineFunction &, MCRegister) const override;
596 bool isArgumentRegister(const MachineFunction &, MCRegister) const override;
597 bool isConstantPhysReg(MCRegister PhysReg) const override final;
598 /// Devirtualized TargetFrameLowering.
599 static const LanaiFrameLowering *getFrameLowering(
600 const MachineFunction &MF);
601};
602
603namespace Lanai { // Register classes
604 extern const TargetRegisterClass GPRRegClass;
605 extern const TargetRegisterClass GPR_with_sub_32RegClass;
606 extern const TargetRegisterClass CCRRegClass;
607} // end namespace Lanai
608
609} // end namespace llvm
610
611#endif // GET_REGINFO_HEADER
612
613/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
614|* *|
615|* Target Register and Register Classes Information *|
616|* *|
617|* Automatically generated file, do not edit! *|
618|* *|
619\*===----------------------------------------------------------------------===*/
620
621
622#ifdef GET_REGINFO_TARGET_DESC
623#undef GET_REGINFO_TARGET_DESC
624
625namespace llvm {
626
627extern const MCRegisterClass LanaiMCRegisterClasses[];
628
629static const MVT::SimpleValueType VTLists[] = {
630 /* 0 */ MVT::i32, MVT::Other,
631};
632
633static const char *SubRegIndexNameTable[] = { "sub_32", "" };
634
635static const TargetRegisterInfo::SubRegCoveredBits SubRegIdxRangeTable[] = {
636 { 65535, 65535 },
637 { 0, 32 }, // sub_32
638};
639
640
641static const LaneBitmask SubRegIndexLaneMaskTable[] = {
642 LaneBitmask::getAll(),
643 LaneBitmask(0x0000000000000001), // sub_32
644 };
645
646
647
648static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
649 // Mode = 0 (Default)
650 { 32, 32, 32, /*VTLists+*/0 }, // GPR
651 { 32, 32, 32, /*VTLists+*/0 }, // GPR_with_sub_32
652 { 32, 32, 32, /*VTLists+*/0 }, // CCR
653};
654static const uint32_t GPRSubClassMask[] = {
655 0x00000003,
656 0x00000002, // sub_32
657};
658
659static const uint32_t GPR_with_sub_32SubClassMask[] = {
660 0x00000002,
661};
662
663static const uint32_t CCRSubClassMask[] = {
664 0x00000004,
665};
666
667static const uint16_t SuperRegIdxSeqs[] = {
668 /* 0 */ 1, 0,
669};
670
671static unsigned const GPR_with_sub_32Superclasses[] = {
672 Lanai::GPRRegClassID,
673};
674
675
676namespace Lanai { // Register class instances
677 extern const TargetRegisterClass GPRRegClass = {
678 &LanaiMCRegisterClasses[GPRRegClassID],
679 GPRSubClassMask,
680 SuperRegIdxSeqs + 0,
681 LaneBitmask(0x0000000000000001),
682 0,
683 false,
684 0x00, /* TSFlags */
685 false, /* HasDisjunctSubRegs */
686 false, /* CoveredBySubRegs */
687 nullptr, 0,
688 nullptr
689 };
690
691 extern const TargetRegisterClass GPR_with_sub_32RegClass = {
692 &LanaiMCRegisterClasses[GPR_with_sub_32RegClassID],
693 GPR_with_sub_32SubClassMask,
694 SuperRegIdxSeqs + 1,
695 LaneBitmask(0x0000000000000001),
696 0,
697 false,
698 0x00, /* TSFlags */
699 false, /* HasDisjunctSubRegs */
700 false, /* CoveredBySubRegs */
701 GPR_with_sub_32Superclasses, 1,
702 nullptr
703 };
704
705 extern const TargetRegisterClass CCRRegClass = {
706 &LanaiMCRegisterClasses[CCRRegClassID],
707 CCRSubClassMask,
708 SuperRegIdxSeqs + 1,
709 LaneBitmask(0x0000000000000001),
710 0,
711 false,
712 0x00, /* TSFlags */
713 false, /* HasDisjunctSubRegs */
714 false, /* CoveredBySubRegs */
715 nullptr, 0,
716 nullptr
717 };
718
719} // end namespace Lanai
720
721namespace {
722 const TargetRegisterClass *const RegisterClasses[] = {
723 &Lanai::GPRRegClass,
724 &Lanai::GPR_with_sub_32RegClass,
725 &Lanai::CCRRegClass,
726 };
727} // end anonymous namespace
728
729static const uint8_t CostPerUseTable[] = {
7300, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
731
732
733static const bool InAllocatableClassTable[] = {
734false, true, true, true, true, true, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
735
736
737static const TargetRegisterInfoDesc LanaiRegInfoDesc = { // Extra Descriptors
738CostPerUseTable, 1, InAllocatableClassTable};
739
740unsigned LanaiGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
741 static const uint8_t Rows[1][1] = {
742 { 0, },
743 };
744
745 --IdxA; assert(IdxA < 1); (void) IdxA;
746 --IdxB; assert(IdxB < 1);
747 return Rows[0][IdxB];
748}
749
750unsigned LanaiGenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
751 static const uint8_t Table[1][1] = {
752 { 0, },
753 };
754
755 --IdxA; assert(IdxA < 1);
756 --IdxB; assert(IdxB < 1);
757 return Table[IdxA][IdxB];
758 }
759
760 struct MaskRolOp {
761 LaneBitmask Mask;
762 uint8_t RotateLeft;
763 };
764 static const MaskRolOp LaneMaskComposeSequences[] = {
765 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 0 }, { LaneBitmask::getNone(), 0 } // Sequence 0
766 };
767 static const uint8_t CompositeSequences[] = {
768 0 // to sub_32
769 };
770
771LaneBitmask LanaiGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
772 --IdxA; assert(IdxA < 1 && "Subregister index out of bounds");
773 LaneBitmask Result;
774 for (const MaskRolOp *Ops =
775 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
776 Ops->Mask.any(); ++Ops) {
777 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
778 if (unsigned S = Ops->RotateLeft)
779 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
780 else
781 Result |= LaneBitmask(M);
782 }
783 return Result;
784}
785
786LaneBitmask LanaiGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
787 LaneMask &= getSubRegIndexLaneMask(IdxA);
788 --IdxA; assert(IdxA < 1 && "Subregister index out of bounds");
789 LaneBitmask Result;
790 for (const MaskRolOp *Ops =
791 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
792 Ops->Mask.any(); ++Ops) {
793 LaneBitmask::Type M = LaneMask.getAsInteger();
794 if (unsigned S = Ops->RotateLeft)
795 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
796 else
797 Result |= LaneBitmask(M);
798 }
799 return Result;
800}
801
802const TargetRegisterClass *LanaiGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
803 static const uint8_t Table[3][1] = {
804 { // GPR
805 2, // sub_32 -> GPR_with_sub_32
806 },
807 { // GPR_with_sub_32
808 2, // sub_32 -> GPR_with_sub_32
809 },
810 { // CCR
811 0, // sub_32
812 },
813 };
814 assert(RC && "Missing regclass");
815 if (!Idx) return RC;
816 --Idx;
817 assert(Idx < 1 && "Bad subreg");
818 unsigned TV = Table[RC->getID()][Idx];
819 return TV ? getRegClass(TV - 1) : nullptr;
820}
821
822const TargetRegisterClass *LanaiGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
823 static const uint8_t Table[3][1] = {
824 { // GPR
825 1, // GPR:sub_32 -> GPR
826 },
827 { // GPR_with_sub_32
828 1, // GPR_with_sub_32:sub_32 -> GPR
829 },
830 { // CCR
831 0, // CCR:sub_32
832 },
833 };
834 assert(RC && "Missing regclass");
835 if (!Idx) return RC;
836 --Idx;
837 assert(Idx < 1 && "Bad subreg");
838 unsigned TV = Table[RC->getID()][Idx];
839 return TV ? getRegClass(TV - 1) : nullptr;
840}
841
842/// Get the weight in units of pressure for this register class.
843const RegClassWeight &LanaiGenRegisterInfo::
844getRegClassWeight(const TargetRegisterClass *RC) const {
845 static const RegClassWeight RCWeightTable[] = {
846 {1, 32}, // GPR
847 {1, 7}, // GPR_with_sub_32
848 {0, 0}, // CCR
849 };
850 return RCWeightTable[RC->getID()];
851}
852
853/// Get the weight in units of pressure for this register unit.
854unsigned LanaiGenRegisterInfo::
855getRegUnitWeight(unsigned RegUnit) const {
856 assert(RegUnit < 33 && "invalid register unit");
857 // All register units have unit weight.
858 return 1;
859}
860
861
862// Get the number of dimensions of register pressure.
863unsigned LanaiGenRegisterInfo::getNumRegPressureSets() const {
864 return 2;
865}
866
867// Get the name of this register unit pressure set.
868const char *LanaiGenRegisterInfo::
869getRegPressureSetName(unsigned Idx) const {
870 static const char *PressureNameTable[] = {
871 "GPR_with_sub_32",
872 "GPR",
873 };
874 return PressureNameTable[Idx];
875}
876
877// Get the register unit pressure limit for this dimension.
878// This limit must be adjusted dynamically for reserved registers.
879unsigned LanaiGenRegisterInfo::
880getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
881 static const uint8_t PressureLimitTable[] = {
882 7, // 0: GPR_with_sub_32
883 32, // 1: GPR
884 };
885 return PressureLimitTable[Idx];
886}
887
888/// Table of pressure sets per register class or unit.
889static const int RCSetsTable[] = {
890 /* 0 */ 0, 1, -1,
891};
892
893/// Get the dimensions of register pressure impacted by this register class.
894/// Returns a -1 terminated array of pressure set IDs
895const int *LanaiGenRegisterInfo::
896getRegClassPressureSets(const TargetRegisterClass *RC) const {
897 static const uint8_t RCSetStartTable[] = {
898 1,0,2,};
899 return &RCSetsTable[RCSetStartTable[RC->getID()]];
900}
901
902/// Get the dimensions of register pressure impacted by this register unit.
903/// Returns a -1 terminated array of pressure set IDs
904const int *LanaiGenRegisterInfo::
905getRegUnitPressureSets(unsigned RegUnit) const {
906 assert(RegUnit < 33 && "invalid register unit");
907 static const uint8_t RUSetStartTable[] = {
908 0,0,0,0,0,2,1,1,1,1,1,1,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,};
909 return &RCSetsTable[RUSetStartTable[RegUnit]];
910}
911
912extern const MCRegisterDesc LanaiRegDesc[];
913extern const int16_t LanaiRegDiffLists[];
914extern const LaneBitmask LanaiLaneMaskLists[];
915extern const char LanaiRegStrings[];
916extern const char LanaiRegClassStrings[];
917extern const MCPhysReg LanaiRegUnitRoots[][2];
918extern const uint16_t LanaiSubRegIdxLists[];
919extern const uint16_t LanaiRegEncodingTable[];
920// Lanai Dwarf<->LLVM register mappings.
921extern const MCRegisterInfo::DwarfLLVMRegPair LanaiDwarfFlavour0Dwarf2L[];
922extern const unsigned LanaiDwarfFlavour0Dwarf2LSize;
923
924extern const MCRegisterInfo::DwarfLLVMRegPair LanaiEHFlavour0Dwarf2L[];
925extern const unsigned LanaiEHFlavour0Dwarf2LSize;
926
927extern const MCRegisterInfo::DwarfLLVMRegPair LanaiDwarfFlavour0L2Dwarf[];
928extern const unsigned LanaiDwarfFlavour0L2DwarfSize;
929
930extern const MCRegisterInfo::DwarfLLVMRegPair LanaiEHFlavour0L2Dwarf[];
931extern const unsigned LanaiEHFlavour0L2DwarfSize;
932
933LanaiGenRegisterInfo::
934LanaiGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
935 unsigned PC, unsigned HwMode)
936 : TargetRegisterInfo(&LanaiRegInfoDesc, RegisterClasses, RegisterClasses+3,
937 SubRegIndexNameTable, SubRegIdxRangeTable, SubRegIndexLaneMaskTable,
938 LaneBitmask(0xFFFFFFFFFFFFFFFE), RegClassInfos, VTLists, HwMode) {
939 InitMCRegisterInfo(LanaiRegDesc, 41, RA, PC,
940 LanaiMCRegisterClasses, 3,
941 LanaiRegUnitRoots,
942 33,
943 LanaiRegDiffLists,
944 LanaiLaneMaskLists,
945 LanaiRegStrings,
946 LanaiRegClassStrings,
947 LanaiSubRegIdxLists,
948 2,
949 LanaiRegEncodingTable);
950
951 switch (DwarfFlavour) {
952 default:
953 llvm_unreachable("Unknown DWARF flavour");
954 case 0:
955 mapDwarfRegsToLLVMRegs(LanaiDwarfFlavour0Dwarf2L, LanaiDwarfFlavour0Dwarf2LSize, false);
956 break;
957 }
958 switch (EHFlavour) {
959 default:
960 llvm_unreachable("Unknown DWARF flavour");
961 case 0:
962 mapDwarfRegsToLLVMRegs(LanaiEHFlavour0Dwarf2L, LanaiEHFlavour0Dwarf2LSize, true);
963 break;
964 }
965 switch (DwarfFlavour) {
966 default:
967 llvm_unreachable("Unknown DWARF flavour");
968 case 0:
969 mapLLVMRegsToDwarfRegs(LanaiDwarfFlavour0L2Dwarf, LanaiDwarfFlavour0L2DwarfSize, false);
970 break;
971 }
972 switch (EHFlavour) {
973 default:
974 llvm_unreachable("Unknown DWARF flavour");
975 case 0:
976 mapLLVMRegsToDwarfRegs(LanaiEHFlavour0L2Dwarf, LanaiEHFlavour0L2DwarfSize, true);
977 break;
978 }
979}
980
981static const MCPhysReg CSR_SaveList[] = { 0 };
982static const uint32_t CSR_RegMask[] = { 0x00000000, 0x00000000, };
983
984
985ArrayRef<const uint32_t *> LanaiGenRegisterInfo::getRegMasks() const {
986 static const uint32_t *const Masks[] = {
987 CSR_RegMask,
988 };
989 return ArrayRef(Masks);
990}
991
992bool LanaiGenRegisterInfo::
993isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
994 return
995 false;
996}
997
998bool LanaiGenRegisterInfo::
999isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
1000 return
1001 false;
1002}
1003
1004bool LanaiGenRegisterInfo::
1005isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
1006 return
1007 false;
1008}
1009
1010bool LanaiGenRegisterInfo::
1011isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
1012 return
1013 false;
1014}
1015
1016bool LanaiGenRegisterInfo::
1017isConstantPhysReg(MCRegister PhysReg) const {
1018 return
1019 false;
1020}
1021
1022ArrayRef<const char *> LanaiGenRegisterInfo::getRegMaskNames() const {
1023 static const char *Names[] = {
1024 "CSR",
1025 };
1026 return ArrayRef(Names);
1027}
1028
1029const LanaiFrameLowering *
1030LanaiGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
1031 return static_cast<const LanaiFrameLowering *>(
1032 MF.getSubtarget().getFrameLowering());
1033}
1034
1035} // end namespace llvm
1036
1037#endif // GET_REGINFO_TARGET_DESC
1038
1039