1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Machine Code Emitter *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9uint64_t LoongArchMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
10 SmallVectorImpl<MCFixup> &Fixups,
11 const MCSubtargetInfo &STI) const {
12 static const uint64_t InstBits[] = {
13 UINT64_C(0),
14 UINT64_C(0),
15 UINT64_C(0),
16 UINT64_C(0),
17 UINT64_C(0),
18 UINT64_C(0),
19 UINT64_C(0),
20 UINT64_C(0),
21 UINT64_C(0),
22 UINT64_C(0),
23 UINT64_C(0),
24 UINT64_C(0),
25 UINT64_C(0),
26 UINT64_C(0),
27 UINT64_C(0),
28 UINT64_C(0),
29 UINT64_C(0),
30 UINT64_C(0),
31 UINT64_C(0),
32 UINT64_C(0),
33 UINT64_C(0),
34 UINT64_C(0),
35 UINT64_C(0),
36 UINT64_C(0),
37 UINT64_C(0),
38 UINT64_C(0),
39 UINT64_C(0),
40 UINT64_C(0),
41 UINT64_C(0),
42 UINT64_C(0),
43 UINT64_C(0),
44 UINT64_C(0),
45 UINT64_C(0),
46 UINT64_C(0),
47 UINT64_C(0),
48 UINT64_C(0),
49 UINT64_C(0),
50 UINT64_C(0),
51 UINT64_C(0),
52 UINT64_C(0),
53 UINT64_C(0),
54 UINT64_C(0),
55 UINT64_C(0),
56 UINT64_C(0),
57 UINT64_C(0),
58 UINT64_C(0),
59 UINT64_C(0),
60 UINT64_C(0),
61 UINT64_C(0),
62 UINT64_C(0),
63 UINT64_C(0),
64 UINT64_C(0),
65 UINT64_C(0),
66 UINT64_C(0),
67 UINT64_C(0),
68 UINT64_C(0),
69 UINT64_C(0),
70 UINT64_C(0),
71 UINT64_C(0),
72 UINT64_C(0),
73 UINT64_C(0),
74 UINT64_C(0),
75 UINT64_C(0),
76 UINT64_C(0),
77 UINT64_C(0),
78 UINT64_C(0),
79 UINT64_C(0),
80 UINT64_C(0),
81 UINT64_C(0),
82 UINT64_C(0),
83 UINT64_C(0),
84 UINT64_C(0),
85 UINT64_C(0),
86 UINT64_C(0),
87 UINT64_C(0),
88 UINT64_C(0),
89 UINT64_C(0),
90 UINT64_C(0),
91 UINT64_C(0),
92 UINT64_C(0),
93 UINT64_C(0),
94 UINT64_C(0),
95 UINT64_C(0),
96 UINT64_C(0),
97 UINT64_C(0),
98 UINT64_C(0),
99 UINT64_C(0),
100 UINT64_C(0),
101 UINT64_C(0),
102 UINT64_C(0),
103 UINT64_C(0),
104 UINT64_C(0),
105 UINT64_C(0),
106 UINT64_C(0),
107 UINT64_C(0),
108 UINT64_C(0),
109 UINT64_C(0),
110 UINT64_C(0),
111 UINT64_C(0),
112 UINT64_C(0),
113 UINT64_C(0),
114 UINT64_C(0),
115 UINT64_C(0),
116 UINT64_C(0),
117 UINT64_C(0),
118 UINT64_C(0),
119 UINT64_C(0),
120 UINT64_C(0),
121 UINT64_C(0),
122 UINT64_C(0),
123 UINT64_C(0),
124 UINT64_C(0),
125 UINT64_C(0),
126 UINT64_C(0),
127 UINT64_C(0),
128 UINT64_C(0),
129 UINT64_C(0),
130 UINT64_C(0),
131 UINT64_C(0),
132 UINT64_C(0),
133 UINT64_C(0),
134 UINT64_C(0),
135 UINT64_C(0),
136 UINT64_C(0),
137 UINT64_C(0),
138 UINT64_C(0),
139 UINT64_C(0),
140 UINT64_C(0),
141 UINT64_C(0),
142 UINT64_C(0),
143 UINT64_C(0),
144 UINT64_C(0),
145 UINT64_C(0),
146 UINT64_C(0),
147 UINT64_C(0),
148 UINT64_C(0),
149 UINT64_C(0),
150 UINT64_C(0),
151 UINT64_C(0),
152 UINT64_C(0),
153 UINT64_C(0),
154 UINT64_C(0),
155 UINT64_C(0),
156 UINT64_C(0),
157 UINT64_C(0),
158 UINT64_C(0),
159 UINT64_C(0),
160 UINT64_C(0),
161 UINT64_C(0),
162 UINT64_C(0),
163 UINT64_C(0),
164 UINT64_C(0),
165 UINT64_C(0),
166 UINT64_C(0),
167 UINT64_C(0),
168 UINT64_C(0),
169 UINT64_C(0),
170 UINT64_C(0),
171 UINT64_C(0),
172 UINT64_C(0),
173 UINT64_C(0),
174 UINT64_C(0),
175 UINT64_C(0),
176 UINT64_C(0),
177 UINT64_C(0),
178 UINT64_C(0),
179 UINT64_C(0),
180 UINT64_C(0),
181 UINT64_C(0),
182 UINT64_C(0),
183 UINT64_C(0),
184 UINT64_C(0),
185 UINT64_C(0),
186 UINT64_C(0),
187 UINT64_C(0),
188 UINT64_C(0),
189 UINT64_C(0),
190 UINT64_C(0),
191 UINT64_C(0),
192 UINT64_C(0),
193 UINT64_C(0),
194 UINT64_C(0),
195 UINT64_C(0),
196 UINT64_C(0),
197 UINT64_C(0),
198 UINT64_C(0),
199 UINT64_C(0),
200 UINT64_C(0),
201 UINT64_C(0),
202 UINT64_C(0),
203 UINT64_C(0),
204 UINT64_C(0),
205 UINT64_C(0),
206 UINT64_C(0),
207 UINT64_C(0),
208 UINT64_C(0),
209 UINT64_C(0),
210 UINT64_C(0),
211 UINT64_C(0),
212 UINT64_C(0),
213 UINT64_C(0),
214 UINT64_C(0),
215 UINT64_C(0),
216 UINT64_C(0),
217 UINT64_C(0),
218 UINT64_C(0),
219 UINT64_C(0),
220 UINT64_C(0),
221 UINT64_C(0),
222 UINT64_C(0),
223 UINT64_C(0),
224 UINT64_C(0),
225 UINT64_C(0),
226 UINT64_C(0),
227 UINT64_C(0),
228 UINT64_C(0),
229 UINT64_C(0),
230 UINT64_C(0),
231 UINT64_C(0),
232 UINT64_C(0),
233 UINT64_C(0),
234 UINT64_C(0),
235 UINT64_C(0),
236 UINT64_C(0),
237 UINT64_C(0),
238 UINT64_C(0),
239 UINT64_C(0),
240 UINT64_C(0),
241 UINT64_C(0),
242 UINT64_C(0),
243 UINT64_C(0),
244 UINT64_C(0),
245 UINT64_C(0),
246 UINT64_C(0),
247 UINT64_C(0),
248 UINT64_C(0),
249 UINT64_C(0),
250 UINT64_C(0),
251 UINT64_C(0),
252 UINT64_C(0),
253 UINT64_C(0),
254 UINT64_C(0),
255 UINT64_C(0),
256 UINT64_C(0),
257 UINT64_C(0),
258 UINT64_C(0),
259 UINT64_C(0),
260 UINT64_C(0),
261 UINT64_C(0),
262 UINT64_C(0),
263 UINT64_C(0),
264 UINT64_C(0),
265 UINT64_C(0),
266 UINT64_C(0),
267 UINT64_C(0),
268 UINT64_C(0),
269 UINT64_C(0),
270 UINT64_C(0),
271 UINT64_C(0),
272 UINT64_C(0),
273 UINT64_C(0),
274 UINT64_C(0),
275 UINT64_C(0),
276 UINT64_C(0),
277 UINT64_C(0),
278 UINT64_C(0),
279 UINT64_C(0),
280 UINT64_C(0),
281 UINT64_C(0),
282 UINT64_C(0),
283 UINT64_C(0),
284 UINT64_C(0),
285 UINT64_C(0),
286 UINT64_C(0),
287 UINT64_C(0),
288 UINT64_C(0),
289 UINT64_C(0),
290 UINT64_C(0),
291 UINT64_C(0),
292 UINT64_C(0),
293 UINT64_C(0),
294 UINT64_C(0),
295 UINT64_C(0),
296 UINT64_C(0),
297 UINT64_C(0),
298 UINT64_C(0),
299 UINT64_C(0),
300 UINT64_C(0),
301 UINT64_C(0),
302 UINT64_C(0),
303 UINT64_C(0),
304 UINT64_C(0),
305 UINT64_C(0),
306 UINT64_C(0),
307 UINT64_C(0),
308 UINT64_C(0),
309 UINT64_C(0),
310 UINT64_C(0),
311 UINT64_C(0),
312 UINT64_C(0),
313 UINT64_C(0),
314 UINT64_C(0),
315 UINT64_C(0),
316 UINT64_C(0),
317 UINT64_C(0),
318 UINT64_C(0),
319 UINT64_C(0),
320 UINT64_C(0),
321 UINT64_C(0),
322 UINT64_C(0),
323 UINT64_C(0),
324 UINT64_C(0),
325 UINT64_C(0),
326 UINT64_C(0),
327 UINT64_C(0),
328 UINT64_C(0),
329 UINT64_C(0),
330 UINT64_C(0),
331 UINT64_C(0),
332 UINT64_C(0),
333 UINT64_C(0),
334 UINT64_C(0),
335 UINT64_C(0),
336 UINT64_C(0),
337 UINT64_C(0),
338 UINT64_C(0),
339 UINT64_C(0),
340 UINT64_C(0),
341 UINT64_C(0),
342 UINT64_C(0),
343 UINT64_C(0),
344 UINT64_C(0),
345 UINT64_C(0),
346 UINT64_C(0),
347 UINT64_C(0),
348 UINT64_C(0),
349 UINT64_C(0),
350 UINT64_C(0),
351 UINT64_C(0),
352 UINT64_C(0),
353 UINT64_C(0),
354 UINT64_C(0),
355 UINT64_C(0),
356 UINT64_C(0),
357 UINT64_C(0),
358 UINT64_C(0),
359 UINT64_C(0),
360 UINT64_C(0),
361 UINT64_C(0),
362 UINT64_C(0),
363 UINT64_C(0),
364 UINT64_C(0),
365 UINT64_C(0),
366 UINT64_C(0),
367 UINT64_C(0),
368 UINT64_C(0),
369 UINT64_C(0),
370 UINT64_C(0),
371 UINT64_C(0),
372 UINT64_C(0),
373 UINT64_C(0),
374 UINT64_C(0),
375 UINT64_C(0),
376 UINT64_C(0),
377 UINT64_C(0),
378 UINT64_C(0),
379 UINT64_C(0),
380 UINT64_C(0),
381 UINT64_C(0),
382 UINT64_C(0),
383 UINT64_C(0),
384 UINT64_C(0),
385 UINT64_C(0),
386 UINT64_C(0),
387 UINT64_C(0),
388 UINT64_C(0),
389 UINT64_C(0),
390 UINT64_C(0),
391 UINT64_C(0),
392 UINT64_C(0),
393 UINT64_C(0),
394 UINT64_C(0),
395 UINT64_C(0),
396 UINT64_C(0),
397 UINT64_C(0),
398 UINT64_C(0),
399 UINT64_C(0),
400 UINT64_C(0),
401 UINT64_C(0),
402 UINT64_C(0),
403 UINT64_C(0),
404 UINT64_C(0),
405 UINT64_C(0),
406 UINT64_C(0),
407 UINT64_C(0),
408 UINT64_C(0),
409 UINT64_C(0),
410 UINT64_C(0),
411 UINT64_C(0),
412 UINT64_C(0),
413 UINT64_C(0),
414 UINT64_C(0),
415 UINT64_C(0),
416 UINT64_C(0),
417 UINT64_C(0),
418 UINT64_C(0),
419 UINT64_C(0),
420 UINT64_C(0),
421 UINT64_C(0),
422 UINT64_C(0),
423 UINT64_C(0),
424 UINT64_C(0),
425 UINT64_C(0),
426 UINT64_C(0),
427 UINT64_C(0),
428 UINT64_C(0),
429 UINT64_C(0),
430 UINT64_C(0),
431 UINT64_C(0),
432 UINT64_C(0),
433 UINT64_C(0),
434 UINT64_C(0),
435 UINT64_C(0),
436 UINT64_C(0),
437 UINT64_C(0),
438 UINT64_C(0),
439 UINT64_C(0),
440 UINT64_C(0),
441 UINT64_C(0),
442 UINT64_C(3145728), // ADC_B
443 UINT64_C(3244032), // ADC_D
444 UINT64_C(3178496), // ADC_H
445 UINT64_C(3211264), // ADC_W
446 UINT64_C(46137344), // ADDI_D
447 UINT64_C(41943040), // ADDI_W
448 UINT64_C(2719744), // ADDU12I_D
449 UINT64_C(2686976), // ADDU12I_W
450 UINT64_C(268435456), // ADDU16I_D
451 UINT64_C(1081344), // ADD_D
452 UINT64_C(1048576), // ADD_W
453 UINT64_C(2883584), // ALSL_D
454 UINT64_C(262144), // ALSL_W
455 UINT64_C(393216), // ALSL_WU
456 UINT64_C(945618944), // AMADD_B
457 UINT64_C(945913856), // AMADD_D
458 UINT64_C(945651712), // AMADD_H
459 UINT64_C(945881088), // AMADD_W
460 UINT64_C(945750016), // AMADD__DB_B
461 UINT64_C(946503680), // AMADD__DB_D
462 UINT64_C(945782784), // AMADD__DB_H
463 UINT64_C(946470912), // AMADD__DB_W
464 UINT64_C(945979392), // AMAND_D
465 UINT64_C(945946624), // AMAND_W
466 UINT64_C(946569216), // AMAND__DB_D
467 UINT64_C(946536448), // AMAND__DB_W
468 UINT64_C(945291264), // AMCAS_B
469 UINT64_C(945389568), // AMCAS_D
470 UINT64_C(945324032), // AMCAS_H
471 UINT64_C(945356800), // AMCAS_W
472 UINT64_C(945422336), // AMCAS__DB_B
473 UINT64_C(945520640), // AMCAS__DB_D
474 UINT64_C(945455104), // AMCAS__DB_H
475 UINT64_C(945487872), // AMCAS__DB_W
476 UINT64_C(946176000), // AMMAX_D
477 UINT64_C(946307072), // AMMAX_DU
478 UINT64_C(946143232), // AMMAX_W
479 UINT64_C(946274304), // AMMAX_WU
480 UINT64_C(946765824), // AMMAX__DB_D
481 UINT64_C(946896896), // AMMAX__DB_DU
482 UINT64_C(946733056), // AMMAX__DB_W
483 UINT64_C(946864128), // AMMAX__DB_WU
484 UINT64_C(946241536), // AMMIN_D
485 UINT64_C(946372608), // AMMIN_DU
486 UINT64_C(946208768), // AMMIN_W
487 UINT64_C(946339840), // AMMIN_WU
488 UINT64_C(946831360), // AMMIN__DB_D
489 UINT64_C(946962432), // AMMIN__DB_DU
490 UINT64_C(946798592), // AMMIN__DB_W
491 UINT64_C(946929664), // AMMIN__DB_WU
492 UINT64_C(946044928), // AMOR_D
493 UINT64_C(946012160), // AMOR_W
494 UINT64_C(946634752), // AMOR__DB_D
495 UINT64_C(946601984), // AMOR__DB_W
496 UINT64_C(945553408), // AMSWAP_B
497 UINT64_C(945848320), // AMSWAP_D
498 UINT64_C(945586176), // AMSWAP_H
499 UINT64_C(945815552), // AMSWAP_W
500 UINT64_C(945684480), // AMSWAP__DB_B
501 UINT64_C(946438144), // AMSWAP__DB_D
502 UINT64_C(945717248), // AMSWAP__DB_H
503 UINT64_C(946405376), // AMSWAP__DB_W
504 UINT64_C(946110464), // AMXOR_D
505 UINT64_C(946077696), // AMXOR_W
506 UINT64_C(946700288), // AMXOR__DB_D
507 UINT64_C(946667520), // AMXOR__DB_W
508 UINT64_C(1343488), // AND
509 UINT64_C(54525952), // ANDI
510 UINT64_C(1474560), // ANDN
511 UINT64_C(3670032), // ARMADC_W
512 UINT64_C(3604496), // ARMADD_W
513 UINT64_C(3735568), // ARMAND_W
514 UINT64_C(6029376), // ARMMFFLAG
515 UINT64_C(3555328), // ARMMOVE
516 UINT64_C(4177950), // ARMMOV_D
517 UINT64_C(4177949), // ARMMOV_W
518 UINT64_C(6029408), // ARMMTFLAG
519 UINT64_C(4177948), // ARMNOT_W
520 UINT64_C(3768336), // ARMOR_W
521 UINT64_C(4063248), // ARMROTRI_W
522 UINT64_C(3932176), // ARMROTR_W
523 UINT64_C(4177951), // ARMRRX_W
524 UINT64_C(3702800), // ARMSBC_W
525 UINT64_C(3964944), // ARMSLLI_W
526 UINT64_C(3833872), // ARMSLL_W
527 UINT64_C(4030480), // ARMSRAI_W
528 UINT64_C(3899408), // ARMSRA_W
529 UINT64_C(3997712), // ARMSRLI_W
530 UINT64_C(3866640), // ARMSRL_W
531 UINT64_C(3637264), // ARMSUB_W
532 UINT64_C(3801104), // ARMXOR_W
533 UINT64_C(98304), // ASRTGT_D
534 UINT64_C(65536), // ASRTLE_D
535 UINT64_C(1342177280), // B
536 UINT64_C(1207959552), // BCEQZ
537 UINT64_C(1207959808), // BCNEZ
538 UINT64_C(1476395008), // BEQ
539 UINT64_C(1073741824), // BEQZ
540 UINT64_C(1677721600), // BGE
541 UINT64_C(1811939328), // BGEU
542 UINT64_C(18432), // BITREV_4B
543 UINT64_C(19456), // BITREV_8B
544 UINT64_C(21504), // BITREV_D
545 UINT64_C(20480), // BITREV_W
546 UINT64_C(1409286144), // BL
547 UINT64_C(1610612736), // BLT
548 UINT64_C(1744830464), // BLTU
549 UINT64_C(1543503872), // BNE
550 UINT64_C(1140850688), // BNEZ
551 UINT64_C(2752512), // BREAK
552 UINT64_C(8388608), // BSTRINS_D
553 UINT64_C(6291456), // BSTRINS_W
554 UINT64_C(12582912), // BSTRPICK_D
555 UINT64_C(6324224), // BSTRPICK_W
556 UINT64_C(786432), // BYTEPICK_D
557 UINT64_C(524288), // BYTEPICK_W
558 UINT64_C(100663296), // CACOP
559 UINT64_C(8192), // CLO_D
560 UINT64_C(4096), // CLO_W
561 UINT64_C(9216), // CLZ_D
562 UINT64_C(5120), // CLZ_W
563 UINT64_C(27648), // CPUCFG
564 UINT64_C(2490368), // CRCC_W_B_W
565 UINT64_C(2588672), // CRCC_W_D_W
566 UINT64_C(2523136), // CRCC_W_H_W
567 UINT64_C(2555904), // CRCC_W_W_W
568 UINT64_C(2359296), // CRC_W_B_W
569 UINT64_C(2457600), // CRC_W_D_W
570 UINT64_C(2392064), // CRC_W_H_W
571 UINT64_C(2424832), // CRC_W_W_W
572 UINT64_C(67108864), // CSRRD
573 UINT64_C(67108896), // CSRWR
574 UINT64_C(67108864), // CSRXCHG
575 UINT64_C(10240), // CTO_D
576 UINT64_C(6144), // CTO_W
577 UINT64_C(11264), // CTZ_D
578 UINT64_C(7168), // CTZ_W
579 UINT64_C(946995200), // DBAR
580 UINT64_C(2785280), // DBCL
581 UINT64_C(2228224), // DIV_D
582 UINT64_C(2293760), // DIV_DU
583 UINT64_C(2097152), // DIV_W
584 UINT64_C(2162688), // DIV_WU
585 UINT64_C(105396224), // ERTN
586 UINT64_C(23552), // EXT_W_B
587 UINT64_C(22528), // EXT_W_H
588 UINT64_C(18089984), // FABS_D
589 UINT64_C(18088960), // FABS_S
590 UINT64_C(16842752), // FADD_D
591 UINT64_C(16809984), // FADD_S
592 UINT64_C(18102272), // FCLASS_D
593 UINT64_C(18101248), // FCLASS_S
594 UINT64_C(203423744), // FCMP_CAF_D
595 UINT64_C(202375168), // FCMP_CAF_S
596 UINT64_C(203554816), // FCMP_CEQ_D
597 UINT64_C(202506240), // FCMP_CEQ_S
598 UINT64_C(203620352), // FCMP_CLE_D
599 UINT64_C(202571776), // FCMP_CLE_S
600 UINT64_C(203489280), // FCMP_CLT_D
601 UINT64_C(202440704), // FCMP_CLT_S
602 UINT64_C(203948032), // FCMP_CNE_D
603 UINT64_C(202899456), // FCMP_CNE_S
604 UINT64_C(204079104), // FCMP_COR_D
605 UINT64_C(203030528), // FCMP_COR_S
606 UINT64_C(203816960), // FCMP_CUEQ_D
607 UINT64_C(202768384), // FCMP_CUEQ_S
608 UINT64_C(203882496), // FCMP_CULE_D
609 UINT64_C(202833920), // FCMP_CULE_S
610 UINT64_C(203751424), // FCMP_CULT_D
611 UINT64_C(202702848), // FCMP_CULT_S
612 UINT64_C(204210176), // FCMP_CUNE_D
613 UINT64_C(203161600), // FCMP_CUNE_S
614 UINT64_C(203685888), // FCMP_CUN_D
615 UINT64_C(202637312), // FCMP_CUN_S
616 UINT64_C(203456512), // FCMP_SAF_D
617 UINT64_C(202407936), // FCMP_SAF_S
618 UINT64_C(203587584), // FCMP_SEQ_D
619 UINT64_C(202539008), // FCMP_SEQ_S
620 UINT64_C(203653120), // FCMP_SLE_D
621 UINT64_C(202604544), // FCMP_SLE_S
622 UINT64_C(203522048), // FCMP_SLT_D
623 UINT64_C(202473472), // FCMP_SLT_S
624 UINT64_C(203980800), // FCMP_SNE_D
625 UINT64_C(202932224), // FCMP_SNE_S
626 UINT64_C(204111872), // FCMP_SOR_D
627 UINT64_C(203063296), // FCMP_SOR_S
628 UINT64_C(203849728), // FCMP_SUEQ_D
629 UINT64_C(202801152), // FCMP_SUEQ_S
630 UINT64_C(203915264), // FCMP_SULE_D
631 UINT64_C(202866688), // FCMP_SULE_S
632 UINT64_C(203784192), // FCMP_SULT_D
633 UINT64_C(202735616), // FCMP_SULT_S
634 UINT64_C(204242944), // FCMP_SUNE_D
635 UINT64_C(203194368), // FCMP_SUNE_S
636 UINT64_C(203718656), // FCMP_SUN_D
637 UINT64_C(202670080), // FCMP_SUN_S
638 UINT64_C(18022400), // FCOPYSIGN_D
639 UINT64_C(17989632), // FCOPYSIGN_S
640 UINT64_C(18153472), // FCVT_D_LD
641 UINT64_C(18424832), // FCVT_D_S
642 UINT64_C(18145280), // FCVT_LD_D
643 UINT64_C(18421760), // FCVT_S_D
644 UINT64_C(18146304), // FCVT_UD_D
645 UINT64_C(17235968), // FDIV_D
646 UINT64_C(17203200), // FDIV_S
647 UINT64_C(18688000), // FFINT_D_L
648 UINT64_C(18685952), // FFINT_D_W
649 UINT64_C(18683904), // FFINT_S_L
650 UINT64_C(18681856), // FFINT_S_W
651 UINT64_C(947159040), // FLDGT_D
652 UINT64_C(947126272), // FLDGT_S
653 UINT64_C(947224576), // FLDLE_D
654 UINT64_C(947191808), // FLDLE_S
655 UINT64_C(942931968), // FLDX_D
656 UINT64_C(942669824), // FLDX_S
657 UINT64_C(729808896), // FLD_D
658 UINT64_C(721420288), // FLD_S
659 UINT64_C(18098176), // FLOGB_D
660 UINT64_C(18097152), // FLOGB_S
661 UINT64_C(136314880), // FMADD_D
662 UINT64_C(135266304), // FMADD_S
663 UINT64_C(17629184), // FMAXA_D
664 UINT64_C(17596416), // FMAXA_S
665 UINT64_C(17367040), // FMAX_D
666 UINT64_C(17334272), // FMAX_S
667 UINT64_C(17760256), // FMINA_D
668 UINT64_C(17727488), // FMINA_S
669 UINT64_C(17498112), // FMIN_D
670 UINT64_C(17465344), // FMIN_S
671 UINT64_C(18126848), // FMOV_D
672 UINT64_C(18125824), // FMOV_S
673 UINT64_C(140509184), // FMSUB_D
674 UINT64_C(139460608), // FMSUB_S
675 UINT64_C(17104896), // FMUL_D
676 UINT64_C(17072128), // FMUL_S
677 UINT64_C(18094080), // FNEG_D
678 UINT64_C(18093056), // FNEG_S
679 UINT64_C(144703488), // FNMADD_D
680 UINT64_C(143654912), // FNMADD_S
681 UINT64_C(148897792), // FNMSUB_D
682 UINT64_C(147849216), // FNMSUB_S
683 UINT64_C(18118656), // FRECIPE_D
684 UINT64_C(18117632), // FRECIPE_S
685 UINT64_C(18110464), // FRECIP_D
686 UINT64_C(18109440), // FRECIP_S
687 UINT64_C(18761728), // FRINT_D
688 UINT64_C(18760704), // FRINT_S
689 UINT64_C(18122752), // FRSQRTE_D
690 UINT64_C(18121728), // FRSQRTE_S
691 UINT64_C(18114560), // FRSQRT_D
692 UINT64_C(18113536), // FRSQRT_S
693 UINT64_C(17891328), // FSCALEB_D
694 UINT64_C(17858560), // FSCALEB_S
695 UINT64_C(218103808), // FSEL_xD
696 UINT64_C(218103808), // FSEL_xS
697 UINT64_C(18106368), // FSQRT_D
698 UINT64_C(18105344), // FSQRT_S
699 UINT64_C(947290112), // FSTGT_D
700 UINT64_C(947257344), // FSTGT_S
701 UINT64_C(947355648), // FSTLE_D
702 UINT64_C(947322880), // FSTLE_S
703 UINT64_C(943456256), // FSTX_D
704 UINT64_C(943194112), // FSTX_S
705 UINT64_C(734003200), // FST_D
706 UINT64_C(725614592), // FST_S
707 UINT64_C(16973824), // FSUB_D
708 UINT64_C(16941056), // FSUB_S
709 UINT64_C(18491392), // FTINTRM_L_D
710 UINT64_C(18490368), // FTINTRM_L_S
711 UINT64_C(18483200), // FTINTRM_W_D
712 UINT64_C(18482176), // FTINTRM_W_S
713 UINT64_C(18540544), // FTINTRNE_L_D
714 UINT64_C(18539520), // FTINTRNE_L_S
715 UINT64_C(18532352), // FTINTRNE_W_D
716 UINT64_C(18531328), // FTINTRNE_W_S
717 UINT64_C(18507776), // FTINTRP_L_D
718 UINT64_C(18506752), // FTINTRP_L_S
719 UINT64_C(18499584), // FTINTRP_W_D
720 UINT64_C(18498560), // FTINTRP_W_S
721 UINT64_C(18524160), // FTINTRZ_L_D
722 UINT64_C(18523136), // FTINTRZ_L_S
723 UINT64_C(18515968), // FTINTRZ_W_D
724 UINT64_C(18514944), // FTINTRZ_W_S
725 UINT64_C(18556928), // FTINT_L_D
726 UINT64_C(18555904), // FTINT_L_S
727 UINT64_C(18548736), // FTINT_W_D
728 UINT64_C(18547712), // FTINT_W_S
729 UINT64_C(83886080), // GCSRRD
730 UINT64_C(83886112), // GCSRWR
731 UINT64_C(83886080), // GCSRXCHG
732 UINT64_C(105391105), // GTLBFLUSH
733 UINT64_C(2850816), // HVCL
734 UINT64_C(947027968), // IBAR
735 UINT64_C(105414656), // IDLE
736 UINT64_C(105480192), // INVTLB
737 UINT64_C(105381888), // IOCSRRD_B
738 UINT64_C(105384960), // IOCSRRD_D
739 UINT64_C(105382912), // IOCSRRD_H
740 UINT64_C(105383936), // IOCSRRD_W
741 UINT64_C(105385984), // IOCSRWR_B
742 UINT64_C(105389056), // IOCSRWR_D
743 UINT64_C(105387008), // IOCSRWR_H
744 UINT64_C(105388032), // IOCSRWR_W
745 UINT64_C(1275068416), // JIRL
746 UINT64_C(1207960064), // JISCR0
747 UINT64_C(1207960320), // JISCR1
748 UINT64_C(104857600), // LDDIR
749 UINT64_C(947388416), // LDGT_B
750 UINT64_C(947486720), // LDGT_D
751 UINT64_C(947421184), // LDGT_H
752 UINT64_C(947453952), // LDGT_W
753 UINT64_C(947519488), // LDLE_B
754 UINT64_C(947617792), // LDLE_D
755 UINT64_C(947552256), // LDLE_H
756 UINT64_C(947585024), // LDLE_W
757 UINT64_C(780140544), // LDL_D
758 UINT64_C(771751936), // LDL_W
759 UINT64_C(105119744), // LDPTE
760 UINT64_C(637534208), // LDPTR_D
761 UINT64_C(603979776), // LDPTR_W
762 UINT64_C(784334848), // LDR_D
763 UINT64_C(775946240), // LDR_W
764 UINT64_C(939524096), // LDX_B
765 UINT64_C(941621248), // LDX_BU
766 UINT64_C(940310528), // LDX_D
767 UINT64_C(939786240), // LDX_H
768 UINT64_C(941883392), // LDX_HU
769 UINT64_C(940048384), // LDX_W
770 UINT64_C(942145536), // LDX_WU
771 UINT64_C(671088640), // LD_B
772 UINT64_C(704643072), // LD_BU
773 UINT64_C(683671552), // LD_D
774 UINT64_C(675282944), // LD_H
775 UINT64_C(708837376), // LD_HU
776 UINT64_C(679477248), // LD_W
777 UINT64_C(713031680), // LD_WU
778 UINT64_C(945260544), // LLACQ_D
779 UINT64_C(945258496), // LLACQ_W
780 UINT64_C(570425344), // LL_D
781 UINT64_C(536870912), // LL_W
782 UINT64_C(335544320), // LU12I_W
783 UINT64_C(369098752), // LU32I_D
784 UINT64_C(50331648), // LU52I_D
785 UINT64_C(1245184), // MASKEQZ
786 UINT64_C(1277952), // MASKNEZ
787 UINT64_C(2260992), // MOD_D
788 UINT64_C(2326528), // MOD_DU
789 UINT64_C(2129920), // MOD_W
790 UINT64_C(2195456), // MOD_WU
791 UINT64_C(18142208), // MOVCF2FR_xS
792 UINT64_C(18144256), // MOVCF2GR
793 UINT64_C(18139136), // MOVFCSR2GR
794 UINT64_C(18141184), // MOVFR2CF_xS
795 UINT64_C(18135040), // MOVFR2GR_D
796 UINT64_C(18134016), // MOVFR2GR_S
797 UINT64_C(18134016), // MOVFR2GR_S_64
798 UINT64_C(18136064), // MOVFRH2GR_S
799 UINT64_C(18143232), // MOVGR2CF
800 UINT64_C(18137088), // MOVGR2FCSR
801 UINT64_C(18131968), // MOVGR2FRH_W
802 UINT64_C(18130944), // MOVGR2FR_D
803 UINT64_C(18129920), // MOVGR2FR_W
804 UINT64_C(18129920), // MOVGR2FR_W_64
805 UINT64_C(2048), // MOVGR2SCR
806 UINT64_C(3072), // MOVSCR2GR
807 UINT64_C(1966080), // MULH_D
808 UINT64_C(1998848), // MULH_DU
809 UINT64_C(1867776), // MULH_W
810 UINT64_C(1900544), // MULH_WU
811 UINT64_C(2031616), // MULW_D_W
812 UINT64_C(2064384), // MULW_D_WU
813 UINT64_C(1933312), // MUL_D
814 UINT64_C(1835008), // MUL_W
815 UINT64_C(1310720), // NOR
816 UINT64_C(1376256), // OR
817 UINT64_C(58720256), // ORI
818 UINT64_C(1441792), // ORN
819 UINT64_C(402653184), // PCADDI
820 UINT64_C(469762048), // PCADDU12I
821 UINT64_C(503316480), // PCADDU18I
822 UINT64_C(436207616), // PCALAU12I
823 UINT64_C(717225984), // PRELD
824 UINT64_C(942407680), // PRELDX
825 UINT64_C(5251072), // RCRI_B
826 UINT64_C(5308416), // RCRI_D
827 UINT64_C(5259264), // RCRI_H
828 UINT64_C(5275648), // RCRI_W
829 UINT64_C(3407872), // RCR_B
830 UINT64_C(3506176), // RCR_D
831 UINT64_C(3440640), // RCR_H
832 UINT64_C(3473408), // RCR_W
833 UINT64_C(25600), // RDTIMEH_W
834 UINT64_C(24576), // RDTIMEL_W
835 UINT64_C(26624), // RDTIME_D
836 UINT64_C(12288), // REVB_2H
837 UINT64_C(14336), // REVB_2W
838 UINT64_C(13312), // REVB_4H
839 UINT64_C(15360), // REVB_D
840 UINT64_C(16384), // REVH_2W
841 UINT64_C(17408), // REVH_D
842 UINT64_C(4988928), // ROTRI_B
843 UINT64_C(5046272), // ROTRI_D
844 UINT64_C(4997120), // ROTRI_H
845 UINT64_C(5013504), // ROTRI_W
846 UINT64_C(1703936), // ROTR_B
847 UINT64_C(1802240), // ROTR_D
848 UINT64_C(1736704), // ROTR_H
849 UINT64_C(1769472), // ROTR_W
850 UINT64_C(3276800), // SBC_B
851 UINT64_C(3375104), // SBC_D
852 UINT64_C(3309568), // SBC_H
853 UINT64_C(3342336), // SBC_W
854 UINT64_C(945261568), // SCREL_D
855 UINT64_C(945259520), // SCREL_W
856 UINT64_C(587202560), // SC_D
857 UINT64_C(945225728), // SC_Q
858 UINT64_C(553648128), // SC_W
859 UINT64_C(3588096), // SETARMJ
860 UINT64_C(3571712), // SETX86J
861 UINT64_C(30720), // SETX86LOOPE
862 UINT64_C(31744), // SETX86LOOPNE
863 UINT64_C(202375168), // SET_CFR_FALSE
864 UINT64_C(202768384), // SET_CFR_TRUE
865 UINT64_C(4259840), // SLLI_D
866 UINT64_C(4227072), // SLLI_W
867 UINT64_C(1605632), // SLL_D
868 UINT64_C(1507328), // SLL_W
869 UINT64_C(1179648), // SLT
870 UINT64_C(33554432), // SLTI
871 UINT64_C(1212416), // SLTU
872 UINT64_C(37748736), // SLTUI
873 UINT64_C(4784128), // SRAI_D
874 UINT64_C(4751360), // SRAI_W
875 UINT64_C(1671168), // SRA_D
876 UINT64_C(1572864), // SRA_W
877 UINT64_C(4521984), // SRLI_D
878 UINT64_C(4489216), // SRLI_W
879 UINT64_C(1638400), // SRL_D
880 UINT64_C(1540096), // SRL_W
881 UINT64_C(947650560), // STGT_B
882 UINT64_C(947748864), // STGT_D
883 UINT64_C(947683328), // STGT_H
884 UINT64_C(947716096), // STGT_W
885 UINT64_C(947781632), // STLE_B
886 UINT64_C(947879936), // STLE_D
887 UINT64_C(947814400), // STLE_H
888 UINT64_C(947847168), // STLE_W
889 UINT64_C(796917760), // STL_D
890 UINT64_C(788529152), // STL_W
891 UINT64_C(654311424), // STPTR_D
892 UINT64_C(620756992), // STPTR_W
893 UINT64_C(801112064), // STR_D
894 UINT64_C(792723456), // STR_W
895 UINT64_C(940572672), // STX_B
896 UINT64_C(941359104), // STX_D
897 UINT64_C(940834816), // STX_H
898 UINT64_C(941096960), // STX_W
899 UINT64_C(687865856), // ST_B
900 UINT64_C(700448768), // ST_D
901 UINT64_C(692060160), // ST_H
902 UINT64_C(696254464), // ST_W
903 UINT64_C(1146880), // SUB_D
904 UINT64_C(1114112), // SUB_W
905 UINT64_C(2818048), // SYSCALL
906 UINT64_C(105390080), // TLBCLR
907 UINT64_C(105395200), // TLBFILL
908 UINT64_C(105391104), // TLBFLUSH
909 UINT64_C(105393152), // TLBRD
910 UINT64_C(105392128), // TLBSRCH
911 UINT64_C(105394176), // TLBWR
912 UINT64_C(1885339648), // VABSD_B
913 UINT64_C(1885470720), // VABSD_BU
914 UINT64_C(1885437952), // VABSD_D
915 UINT64_C(1885569024), // VABSD_DU
916 UINT64_C(1885372416), // VABSD_H
917 UINT64_C(1885503488), // VABSD_HU
918 UINT64_C(1885405184), // VABSD_W
919 UINT64_C(1885536256), // VABSD_WU
920 UINT64_C(1885077504), // VADDA_B
921 UINT64_C(1885175808), // VADDA_D
922 UINT64_C(1885110272), // VADDA_H
923 UINT64_C(1885143040), // VADDA_W
924 UINT64_C(1921646592), // VADDI_BU
925 UINT64_C(1921744896), // VADDI_DU
926 UINT64_C(1921679360), // VADDI_HU
927 UINT64_C(1921712128), // VADDI_WU
928 UINT64_C(1881079808), // VADDWEV_D_W
929 UINT64_C(1882128384), // VADDWEV_D_WU
930 UINT64_C(1883176960), // VADDWEV_D_WU_W
931 UINT64_C(1881014272), // VADDWEV_H_B
932 UINT64_C(1882062848), // VADDWEV_H_BU
933 UINT64_C(1883111424), // VADDWEV_H_BU_B
934 UINT64_C(1881112576), // VADDWEV_Q_D
935 UINT64_C(1882161152), // VADDWEV_Q_DU
936 UINT64_C(1883209728), // VADDWEV_Q_DU_D
937 UINT64_C(1881047040), // VADDWEV_W_H
938 UINT64_C(1882095616), // VADDWEV_W_HU
939 UINT64_C(1883144192), // VADDWEV_W_HU_H
940 UINT64_C(1881341952), // VADDWOD_D_W
941 UINT64_C(1882390528), // VADDWOD_D_WU
942 UINT64_C(1883308032), // VADDWOD_D_WU_W
943 UINT64_C(1881276416), // VADDWOD_H_B
944 UINT64_C(1882324992), // VADDWOD_H_BU
945 UINT64_C(1883242496), // VADDWOD_H_BU_B
946 UINT64_C(1881374720), // VADDWOD_Q_D
947 UINT64_C(1882423296), // VADDWOD_Q_DU
948 UINT64_C(1883340800), // VADDWOD_Q_DU_D
949 UINT64_C(1881309184), // VADDWOD_W_H
950 UINT64_C(1882357760), // VADDWOD_W_HU
951 UINT64_C(1883275264), // VADDWOD_W_HU_H
952 UINT64_C(1879703552), // VADD_B
953 UINT64_C(1879801856), // VADD_D
954 UINT64_C(1879736320), // VADD_H
955 UINT64_C(1898774528), // VADD_Q
956 UINT64_C(1879769088), // VADD_W
957 UINT64_C(1943011328), // VANDI_B
958 UINT64_C(1898446848), // VANDN_V
959 UINT64_C(1898315776), // VAND_V
960 UINT64_C(1885863936), // VAVGR_B
961 UINT64_C(1885995008), // VAVGR_BU
962 UINT64_C(1885962240), // VAVGR_D
963 UINT64_C(1886093312), // VAVGR_DU
964 UINT64_C(1885896704), // VAVGR_H
965 UINT64_C(1886027776), // VAVGR_HU
966 UINT64_C(1885929472), // VAVGR_W
967 UINT64_C(1886060544), // VAVGR_WU
968 UINT64_C(1885601792), // VAVG_B
969 UINT64_C(1885732864), // VAVG_BU
970 UINT64_C(1885700096), // VAVG_D
971 UINT64_C(1885831168), // VAVG_DU
972 UINT64_C(1885634560), // VAVG_H
973 UINT64_C(1885765632), // VAVG_HU
974 UINT64_C(1885667328), // VAVG_W
975 UINT64_C(1885798400), // VAVG_WU
976 UINT64_C(1930436608), // VBITCLRI_B
977 UINT64_C(1930493952), // VBITCLRI_D
978 UINT64_C(1930444800), // VBITCLRI_H
979 UINT64_C(1930461184), // VBITCLRI_W
980 UINT64_C(1896611840), // VBITCLR_B
981 UINT64_C(1896710144), // VBITCLR_D
982 UINT64_C(1896644608), // VBITCLR_H
983 UINT64_C(1896677376), // VBITCLR_W
984 UINT64_C(1930960896), // VBITREVI_B
985 UINT64_C(1931018240), // VBITREVI_D
986 UINT64_C(1930969088), // VBITREVI_H
987 UINT64_C(1930985472), // VBITREVI_W
988 UINT64_C(1896873984), // VBITREV_B
989 UINT64_C(1896972288), // VBITREV_D
990 UINT64_C(1896906752), // VBITREV_H
991 UINT64_C(1896939520), // VBITREV_W
992 UINT64_C(1942224896), // VBITSELI_B
993 UINT64_C(219152384), // VBITSEL_V
994 UINT64_C(1930698752), // VBITSETI_B
995 UINT64_C(1930756096), // VBITSETI_D
996 UINT64_C(1930706944), // VBITSETI_H
997 UINT64_C(1930723328), // VBITSETI_W
998 UINT64_C(1896742912), // VBITSET_B
999 UINT64_C(1896841216), // VBITSET_D
1000 UINT64_C(1896775680), // VBITSET_H
1001 UINT64_C(1896808448), // VBITSET_W
1002 UINT64_C(1921908736), // VBSLL_V
1003 UINT64_C(1921941504), // VBSRL_V
1004 UINT64_C(1922826240), // VCLO_B
1005 UINT64_C(1922829312), // VCLO_D
1006 UINT64_C(1922827264), // VCLO_H
1007 UINT64_C(1922828288), // VCLO_W
1008 UINT64_C(1922830336), // VCLZ_B
1009 UINT64_C(1922833408), // VCLZ_D
1010 UINT64_C(1922831360), // VCLZ_H
1011 UINT64_C(1922832384), // VCLZ_W
1012 UINT64_C(1893728256), // VDIV_B
1013 UINT64_C(1893990400), // VDIV_BU
1014 UINT64_C(1893826560), // VDIV_D
1015 UINT64_C(1894088704), // VDIV_DU
1016 UINT64_C(1893761024), // VDIV_H
1017 UINT64_C(1894023168), // VDIV_HU
1018 UINT64_C(1893793792), // VDIV_W
1019 UINT64_C(1894055936), // VDIV_WU
1020 UINT64_C(1990144000), // VEXT2XV_DU_BU
1021 UINT64_C(1990146048), // VEXT2XV_DU_HU
1022 UINT64_C(1990147072), // VEXT2XV_DU_WU
1023 UINT64_C(1990137856), // VEXT2XV_D_B
1024 UINT64_C(1990139904), // VEXT2XV_D_H
1025 UINT64_C(1990140928), // VEXT2XV_D_W
1026 UINT64_C(1990141952), // VEXT2XV_HU_BU
1027 UINT64_C(1990135808), // VEXT2XV_H_B
1028 UINT64_C(1990142976), // VEXT2XV_WU_BU
1029 UINT64_C(1990145024), // VEXT2XV_WU_HU
1030 UINT64_C(1990136832), // VEXT2XV_W_B
1031 UINT64_C(1990138880), // VEXT2XV_W_H
1032 UINT64_C(1923020800), // VEXTH_DU_WU
1033 UINT64_C(1923016704), // VEXTH_D_W
1034 UINT64_C(1923018752), // VEXTH_HU_BU
1035 UINT64_C(1923014656), // VEXTH_H_B
1036 UINT64_C(1923021824), // VEXTH_QU_DU
1037 UINT64_C(1923017728), // VEXTH_Q_D
1038 UINT64_C(1923019776), // VEXTH_WU_HU
1039 UINT64_C(1923015680), // VEXTH_W_H
1040 UINT64_C(1930231808), // VEXTL_QU_DU
1041 UINT64_C(1929969664), // VEXTL_Q_D
1042 UINT64_C(1938554880), // VEXTRINS_B
1043 UINT64_C(1937768448), // VEXTRINS_D
1044 UINT64_C(1938292736), // VEXTRINS_H
1045 UINT64_C(1938030592), // VEXTRINS_W
1046 UINT64_C(1899036672), // VFADD_D
1047 UINT64_C(1899003904), // VFADD_S
1048 UINT64_C(1922881536), // VFCLASS_D
1049 UINT64_C(1922880512), // VFCLASS_S
1050 UINT64_C(207618048), // VFCMP_CAF_D
1051 UINT64_C(206569472), // VFCMP_CAF_S
1052 UINT64_C(207749120), // VFCMP_CEQ_D
1053 UINT64_C(206700544), // VFCMP_CEQ_S
1054 UINT64_C(207814656), // VFCMP_CLE_D
1055 UINT64_C(206766080), // VFCMP_CLE_S
1056 UINT64_C(207683584), // VFCMP_CLT_D
1057 UINT64_C(206635008), // VFCMP_CLT_S
1058 UINT64_C(208142336), // VFCMP_CNE_D
1059 UINT64_C(207093760), // VFCMP_CNE_S
1060 UINT64_C(208273408), // VFCMP_COR_D
1061 UINT64_C(207224832), // VFCMP_COR_S
1062 UINT64_C(208011264), // VFCMP_CUEQ_D
1063 UINT64_C(206962688), // VFCMP_CUEQ_S
1064 UINT64_C(208076800), // VFCMP_CULE_D
1065 UINT64_C(207028224), // VFCMP_CULE_S
1066 UINT64_C(207945728), // VFCMP_CULT_D
1067 UINT64_C(206897152), // VFCMP_CULT_S
1068 UINT64_C(208404480), // VFCMP_CUNE_D
1069 UINT64_C(207355904), // VFCMP_CUNE_S
1070 UINT64_C(207880192), // VFCMP_CUN_D
1071 UINT64_C(206831616), // VFCMP_CUN_S
1072 UINT64_C(207650816), // VFCMP_SAF_D
1073 UINT64_C(206602240), // VFCMP_SAF_S
1074 UINT64_C(207781888), // VFCMP_SEQ_D
1075 UINT64_C(206733312), // VFCMP_SEQ_S
1076 UINT64_C(207847424), // VFCMP_SLE_D
1077 UINT64_C(206798848), // VFCMP_SLE_S
1078 UINT64_C(207716352), // VFCMP_SLT_D
1079 UINT64_C(206667776), // VFCMP_SLT_S
1080 UINT64_C(208175104), // VFCMP_SNE_D
1081 UINT64_C(207126528), // VFCMP_SNE_S
1082 UINT64_C(208306176), // VFCMP_SOR_D
1083 UINT64_C(207257600), // VFCMP_SOR_S
1084 UINT64_C(208044032), // VFCMP_SUEQ_D
1085 UINT64_C(206995456), // VFCMP_SUEQ_S
1086 UINT64_C(208109568), // VFCMP_SULE_D
1087 UINT64_C(207060992), // VFCMP_SULE_S
1088 UINT64_C(207978496), // VFCMP_SULT_D
1089 UINT64_C(206929920), // VFCMP_SULT_S
1090 UINT64_C(208437248), // VFCMP_SUNE_D
1091 UINT64_C(207388672), // VFCMP_SUNE_S
1092 UINT64_C(207912960), // VFCMP_SUN_D
1093 UINT64_C(206864384), // VFCMP_SUN_S
1094 UINT64_C(1922954240), // VFCVTH_D_S
1095 UINT64_C(1922952192), // VFCVTH_S_H
1096 UINT64_C(1922953216), // VFCVTL_D_S
1097 UINT64_C(1922951168), // VFCVTL_S_H
1098 UINT64_C(1900412928), // VFCVT_H_S
1099 UINT64_C(1900445696), // VFCVT_S_D
1100 UINT64_C(1899692032), // VFDIV_D
1101 UINT64_C(1899659264), // VFDIV_S
1102 UINT64_C(1922962432), // VFFINTH_D_W
1103 UINT64_C(1922961408), // VFFINTL_D_W
1104 UINT64_C(1922959360), // VFFINT_D_L
1105 UINT64_C(1922960384), // VFFINT_D_LU
1106 UINT64_C(1900544000), // VFFINT_S_L
1107 UINT64_C(1922957312), // VFFINT_S_W
1108 UINT64_C(1922958336), // VFFINT_S_WU
1109 UINT64_C(1922877440), // VFLOGB_D
1110 UINT64_C(1922876416), // VFLOGB_S
1111 UINT64_C(153092096), // VFMADD_D
1112 UINT64_C(152043520), // VFMADD_S
1113 UINT64_C(1900085248), // VFMAXA_D
1114 UINT64_C(1900052480), // VFMAXA_S
1115 UINT64_C(1899823104), // VFMAX_D
1116 UINT64_C(1899790336), // VFMAX_S
1117 UINT64_C(1900216320), // VFMINA_D
1118 UINT64_C(1900183552), // VFMINA_S
1119 UINT64_C(1899954176), // VFMIN_D
1120 UINT64_C(1899921408), // VFMIN_S
1121 UINT64_C(157286400), // VFMSUB_D
1122 UINT64_C(156237824), // VFMSUB_S
1123 UINT64_C(1899560960), // VFMUL_D
1124 UINT64_C(1899528192), // VFMUL_S
1125 UINT64_C(161480704), // VFNMADD_D
1126 UINT64_C(160432128), // VFNMADD_S
1127 UINT64_C(165675008), // VFNMSUB_D
1128 UINT64_C(164626432), // VFNMSUB_S
1129 UINT64_C(1922897920), // VFRECIPE_D
1130 UINT64_C(1922896896), // VFRECIPE_S
1131 UINT64_C(1922889728), // VFRECIP_D
1132 UINT64_C(1922888704), // VFRECIP_S
1133 UINT64_C(1922910208), // VFRINTRM_D
1134 UINT64_C(1922909184), // VFRINTRM_S
1135 UINT64_C(1922922496), // VFRINTRNE_D
1136 UINT64_C(1922921472), // VFRINTRNE_S
1137 UINT64_C(1922914304), // VFRINTRP_D
1138 UINT64_C(1922913280), // VFRINTRP_S
1139 UINT64_C(1922918400), // VFRINTRZ_D
1140 UINT64_C(1922917376), // VFRINTRZ_S
1141 UINT64_C(1922906112), // VFRINT_D
1142 UINT64_C(1922905088), // VFRINT_S
1143 UINT64_C(1922902016), // VFRSQRTE_D
1144 UINT64_C(1922900992), // VFRSQRTE_S
1145 UINT64_C(1922893824), // VFRSQRT_D
1146 UINT64_C(1922892800), // VFRSQRT_S
1147 UINT64_C(1922695168), // VFRSTPI_B
1148 UINT64_C(1922727936), // VFRSTPI_H
1149 UINT64_C(1898643456), // VFRSTP_B
1150 UINT64_C(1898676224), // VFRSTP_H
1151 UINT64_C(1922885632), // VFSQRT_D
1152 UINT64_C(1922884608), // VFSQRT_S
1153 UINT64_C(1899167744), // VFSUB_D
1154 UINT64_C(1899134976), // VFSUB_S
1155 UINT64_C(1922991104), // VFTINTH_L_S
1156 UINT64_C(1922990080), // VFTINTL_L_S
1157 UINT64_C(1922993152), // VFTINTRMH_L_S
1158 UINT64_C(1922992128), // VFTINTRML_L_S
1159 UINT64_C(1922972672), // VFTINTRM_L_D
1160 UINT64_C(1900675072), // VFTINTRM_W_D
1161 UINT64_C(1922971648), // VFTINTRM_W_S
1162 UINT64_C(1922999296), // VFTINTRNEH_L_S
1163 UINT64_C(1922998272), // VFTINTRNEL_L_S
1164 UINT64_C(1922978816), // VFTINTRNE_L_D
1165 UINT64_C(1900773376), // VFTINTRNE_W_D
1166 UINT64_C(1922977792), // VFTINTRNE_W_S
1167 UINT64_C(1922995200), // VFTINTRPH_L_S
1168 UINT64_C(1922994176), // VFTINTRPL_L_S
1169 UINT64_C(1922974720), // VFTINTRP_L_D
1170 UINT64_C(1900707840), // VFTINTRP_W_D
1171 UINT64_C(1922973696), // VFTINTRP_W_S
1172 UINT64_C(1922997248), // VFTINTRZH_L_S
1173 UINT64_C(1922996224), // VFTINTRZL_L_S
1174 UINT64_C(1922987008), // VFTINTRZ_LU_D
1175 UINT64_C(1922976768), // VFTINTRZ_L_D
1176 UINT64_C(1922985984), // VFTINTRZ_WU_S
1177 UINT64_C(1900740608), // VFTINTRZ_W_D
1178 UINT64_C(1922975744), // VFTINTRZ_W_S
1179 UINT64_C(1922980864), // VFTINT_LU_D
1180 UINT64_C(1922970624), // VFTINT_L_D
1181 UINT64_C(1922979840), // VFTINT_WU_S
1182 UINT64_C(1900642304), // VFTINT_W_D
1183 UINT64_C(1922969600), // VFTINT_W_S
1184 UINT64_C(1884880896), // VHADDW_DU_WU
1185 UINT64_C(1884618752), // VHADDW_D_W
1186 UINT64_C(1884815360), // VHADDW_HU_BU
1187 UINT64_C(1884553216), // VHADDW_H_B
1188 UINT64_C(1884913664), // VHADDW_QU_DU
1189 UINT64_C(1884651520), // VHADDW_Q_D
1190 UINT64_C(1884848128), // VHADDW_WU_HU
1191 UINT64_C(1884585984), // VHADDW_W_H
1192 UINT64_C(1885011968), // VHSUBW_DU_WU
1193 UINT64_C(1884749824), // VHSUBW_D_W
1194 UINT64_C(1884946432), // VHSUBW_HU_BU
1195 UINT64_C(1884684288), // VHSUBW_H_B
1196 UINT64_C(1885044736), // VHSUBW_QU_DU
1197 UINT64_C(1884782592), // VHSUBW_Q_D
1198 UINT64_C(1884979200), // VHSUBW_WU_HU
1199 UINT64_C(1884717056), // VHSUBW_W_H
1200 UINT64_C(1897660416), // VILVH_B
1201 UINT64_C(1897758720), // VILVH_D
1202 UINT64_C(1897693184), // VILVH_H
1203 UINT64_C(1897725952), // VILVH_W
1204 UINT64_C(1897529344), // VILVL_B
1205 UINT64_C(1897627648), // VILVL_D
1206 UINT64_C(1897562112), // VILVL_H
1207 UINT64_C(1897594880), // VILVL_W
1208 UINT64_C(1928036352), // VINSGR2VR_B
1209 UINT64_C(1928065024), // VINSGR2VR_D
1210 UINT64_C(1928052736), // VINSGR2VR_H
1211 UINT64_C(1928060928), // VINSGR2VR_W
1212 UINT64_C(738197504), // VLD
1213 UINT64_C(1944059904), // VLDI
1214 UINT64_C(813694976), // VLDREPL_B
1215 UINT64_C(806354944), // VLDREPL_D
1216 UINT64_C(809500672), // VLDREPL_H
1217 UINT64_C(807403520), // VLDREPL_W
1218 UINT64_C(943718400), // VLDX
1219 UINT64_C(1890385920), // VMADDWEV_D_W
1220 UINT64_C(1890910208), // VMADDWEV_D_WU
1221 UINT64_C(1891434496), // VMADDWEV_D_WU_W
1222 UINT64_C(1890320384), // VMADDWEV_H_B
1223 UINT64_C(1890844672), // VMADDWEV_H_BU
1224 UINT64_C(1891368960), // VMADDWEV_H_BU_B
1225 UINT64_C(1890418688), // VMADDWEV_Q_D
1226 UINT64_C(1890942976), // VMADDWEV_Q_DU
1227 UINT64_C(1891467264), // VMADDWEV_Q_DU_D
1228 UINT64_C(1890353152), // VMADDWEV_W_H
1229 UINT64_C(1890877440), // VMADDWEV_W_HU
1230 UINT64_C(1891401728), // VMADDWEV_W_HU_H
1231 UINT64_C(1890516992), // VMADDWOD_D_W
1232 UINT64_C(1891041280), // VMADDWOD_D_WU
1233 UINT64_C(1891565568), // VMADDWOD_D_WU_W
1234 UINT64_C(1890451456), // VMADDWOD_H_B
1235 UINT64_C(1890975744), // VMADDWOD_H_BU
1236 UINT64_C(1891500032), // VMADDWOD_H_BU_B
1237 UINT64_C(1890549760), // VMADDWOD_Q_D
1238 UINT64_C(1891074048), // VMADDWOD_Q_DU
1239 UINT64_C(1891598336), // VMADDWOD_Q_DU_D
1240 UINT64_C(1890484224), // VMADDWOD_W_H
1241 UINT64_C(1891008512), // VMADDWOD_W_HU
1242 UINT64_C(1891532800), // VMADDWOD_W_HU_H
1243 UINT64_C(1890058240), // VMADD_B
1244 UINT64_C(1890156544), // VMADD_D
1245 UINT64_C(1890091008), // VMADD_H
1246 UINT64_C(1890123776), // VMADD_W
1247 UINT64_C(1922039808), // VMAXI_B
1248 UINT64_C(1922301952), // VMAXI_BU
1249 UINT64_C(1922138112), // VMAXI_D
1250 UINT64_C(1922400256), // VMAXI_DU
1251 UINT64_C(1922072576), // VMAXI_H
1252 UINT64_C(1922334720), // VMAXI_HU
1253 UINT64_C(1922105344), // VMAXI_W
1254 UINT64_C(1922367488), // VMAXI_WU
1255 UINT64_C(1886388224), // VMAX_B
1256 UINT64_C(1886650368), // VMAX_BU
1257 UINT64_C(1886486528), // VMAX_D
1258 UINT64_C(1886748672), // VMAX_DU
1259 UINT64_C(1886420992), // VMAX_H
1260 UINT64_C(1886683136), // VMAX_HU
1261 UINT64_C(1886453760), // VMAX_W
1262 UINT64_C(1886715904), // VMAX_WU
1263 UINT64_C(1922170880), // VMINI_B
1264 UINT64_C(1922433024), // VMINI_BU
1265 UINT64_C(1922269184), // VMINI_D
1266 UINT64_C(1922531328), // VMINI_DU
1267 UINT64_C(1922203648), // VMINI_H
1268 UINT64_C(1922465792), // VMINI_HU
1269 UINT64_C(1922236416), // VMINI_W
1270 UINT64_C(1922498560), // VMINI_WU
1271 UINT64_C(1886519296), // VMIN_B
1272 UINT64_C(1886781440), // VMIN_BU
1273 UINT64_C(1886617600), // VMIN_D
1274 UINT64_C(1886879744), // VMIN_DU
1275 UINT64_C(1886552064), // VMIN_H
1276 UINT64_C(1886814208), // VMIN_HU
1277 UINT64_C(1886584832), // VMIN_W
1278 UINT64_C(1886846976), // VMIN_WU
1279 UINT64_C(1893859328), // VMOD_B
1280 UINT64_C(1894121472), // VMOD_BU
1281 UINT64_C(1893957632), // VMOD_D
1282 UINT64_C(1894219776), // VMOD_DU
1283 UINT64_C(1893892096), // VMOD_H
1284 UINT64_C(1894154240), // VMOD_HU
1285 UINT64_C(1893924864), // VMOD_W
1286 UINT64_C(1894187008), // VMOD_WU
1287 UINT64_C(1922846720), // VMSKGEZ_B
1288 UINT64_C(1922842624), // VMSKLTZ_B
1289 UINT64_C(1922845696), // VMSKLTZ_D
1290 UINT64_C(1922843648), // VMSKLTZ_H
1291 UINT64_C(1922844672), // VMSKLTZ_W
1292 UINT64_C(1922850816), // VMSKNZ_B
1293 UINT64_C(1890189312), // VMSUB_B
1294 UINT64_C(1890287616), // VMSUB_D
1295 UINT64_C(1890222080), // VMSUB_H
1296 UINT64_C(1890254848), // VMSUB_W
1297 UINT64_C(1887830016), // VMUH_B
1298 UINT64_C(1887961088), // VMUH_BU
1299 UINT64_C(1887928320), // VMUH_D
1300 UINT64_C(1888059392), // VMUH_DU
1301 UINT64_C(1887862784), // VMUH_H
1302 UINT64_C(1887993856), // VMUH_HU
1303 UINT64_C(1887895552), // VMUH_W
1304 UINT64_C(1888026624), // VMUH_WU
1305 UINT64_C(1888550912), // VMULWEV_D_W
1306 UINT64_C(1889075200), // VMULWEV_D_WU
1307 UINT64_C(1889599488), // VMULWEV_D_WU_W
1308 UINT64_C(1888485376), // VMULWEV_H_B
1309 UINT64_C(1889009664), // VMULWEV_H_BU
1310 UINT64_C(1889533952), // VMULWEV_H_BU_B
1311 UINT64_C(1888583680), // VMULWEV_Q_D
1312 UINT64_C(1889107968), // VMULWEV_Q_DU
1313 UINT64_C(1889632256), // VMULWEV_Q_DU_D
1314 UINT64_C(1888518144), // VMULWEV_W_H
1315 UINT64_C(1889042432), // VMULWEV_W_HU
1316 UINT64_C(1889566720), // VMULWEV_W_HU_H
1317 UINT64_C(1888681984), // VMULWOD_D_W
1318 UINT64_C(1889206272), // VMULWOD_D_WU
1319 UINT64_C(1889730560), // VMULWOD_D_WU_W
1320 UINT64_C(1888616448), // VMULWOD_H_B
1321 UINT64_C(1889140736), // VMULWOD_H_BU
1322 UINT64_C(1889665024), // VMULWOD_H_BU_B
1323 UINT64_C(1888714752), // VMULWOD_Q_D
1324 UINT64_C(1889239040), // VMULWOD_Q_DU
1325 UINT64_C(1889763328), // VMULWOD_Q_DU_D
1326 UINT64_C(1888649216), // VMULWOD_W_H
1327 UINT64_C(1889173504), // VMULWOD_W_HU
1328 UINT64_C(1889697792), // VMULWOD_W_HU_H
1329 UINT64_C(1887698944), // VMUL_B
1330 UINT64_C(1887797248), // VMUL_D
1331 UINT64_C(1887731712), // VMUL_H
1332 UINT64_C(1887764480), // VMUL_W
1333 UINT64_C(1922838528), // VNEG_B
1334 UINT64_C(1922841600), // VNEG_D
1335 UINT64_C(1922839552), // VNEG_H
1336 UINT64_C(1922840576), // VNEG_W
1337 UINT64_C(1943797760), // VNORI_B
1338 UINT64_C(1898414080), // VNOR_V
1339 UINT64_C(1943273472), // VORI_B
1340 UINT64_C(1898479616), // VORN_V
1341 UINT64_C(1898348544), // VOR_V
1342 UINT64_C(1897267200), // VPACKEV_B
1343 UINT64_C(1897365504), // VPACKEV_D
1344 UINT64_C(1897299968), // VPACKEV_H
1345 UINT64_C(1897332736), // VPACKEV_W
1346 UINT64_C(1897398272), // VPACKOD_B
1347 UINT64_C(1897496576), // VPACKOD_D
1348 UINT64_C(1897431040), // VPACKOD_H
1349 UINT64_C(1897463808), // VPACKOD_W
1350 UINT64_C(1922834432), // VPCNT_B
1351 UINT64_C(1922837504), // VPCNT_D
1352 UINT64_C(1922835456), // VPCNT_H
1353 UINT64_C(1922836480), // VPCNT_W
1354 UINT64_C(1944322048), // VPERMI_W
1355 UINT64_C(1897791488), // VPICKEV_B
1356 UINT64_C(1897889792), // VPICKEV_D
1357 UINT64_C(1897824256), // VPICKEV_H
1358 UINT64_C(1897857024), // VPICKEV_W
1359 UINT64_C(1897922560), // VPICKOD_B
1360 UINT64_C(1898020864), // VPICKOD_D
1361 UINT64_C(1897955328), // VPICKOD_H
1362 UINT64_C(1897988096), // VPICKOD_W
1363 UINT64_C(1928298496), // VPICKVE2GR_B
1364 UINT64_C(1928560640), // VPICKVE2GR_BU
1365 UINT64_C(1928327168), // VPICKVE2GR_D
1366 UINT64_C(1928589312), // VPICKVE2GR_DU
1367 UINT64_C(1928314880), // VPICKVE2GR_H
1368 UINT64_C(1928577024), // VPICKVE2GR_HU
1369 UINT64_C(1928323072), // VPICKVE2GR_W
1370 UINT64_C(1928585216), // VPICKVE2GR_WU
1371 UINT64_C(1923022848), // VREPLGR2VR_B
1372 UINT64_C(1923025920), // VREPLGR2VR_D
1373 UINT64_C(1923023872), // VREPLGR2VR_H
1374 UINT64_C(1923024896), // VREPLGR2VR_W
1375 UINT64_C(1928822784), // VREPLVEI_B
1376 UINT64_C(1928851456), // VREPLVEI_D
1377 UINT64_C(1928839168), // VREPLVEI_H
1378 UINT64_C(1928847360), // VREPLVEI_W
1379 UINT64_C(1898053632), // VREPLVE_B
1380 UINT64_C(1898151936), // VREPLVE_D
1381 UINT64_C(1898086400), // VREPLVE_H
1382 UINT64_C(1898119168), // VREPLVE_W
1383 UINT64_C(1923096576), // VROTRI_B
1384 UINT64_C(1923153920), // VROTRI_D
1385 UINT64_C(1923104768), // VROTRI_H
1386 UINT64_C(1923121152), // VROTRI_W
1387 UINT64_C(1894645760), // VROTR_B
1388 UINT64_C(1894744064), // VROTR_D
1389 UINT64_C(1894678528), // VROTR_H
1390 UINT64_C(1894711296), // VROTR_W
1391 UINT64_C(1883635712), // VSADD_B
1392 UINT64_C(1883897856), // VSADD_BU
1393 UINT64_C(1883734016), // VSADD_D
1394 UINT64_C(1883996160), // VSADD_DU
1395 UINT64_C(1883668480), // VSADD_H
1396 UINT64_C(1883930624), // VSADD_HU
1397 UINT64_C(1883701248), // VSADD_W
1398 UINT64_C(1883963392), // VSADD_WU
1399 UINT64_C(1931747328), // VSAT_B
1400 UINT64_C(1932009472), // VSAT_BU
1401 UINT64_C(1931804672), // VSAT_D
1402 UINT64_C(1932066816), // VSAT_DU
1403 UINT64_C(1931755520), // VSAT_H
1404 UINT64_C(1932017664), // VSAT_HU
1405 UINT64_C(1931771904), // VSAT_W
1406 UINT64_C(1932034048), // VSAT_WU
1407 UINT64_C(1920991232), // VSEQI_B
1408 UINT64_C(1921089536), // VSEQI_D
1409 UINT64_C(1921024000), // VSEQI_H
1410 UINT64_C(1921056768), // VSEQI_W
1411 UINT64_C(1879048192), // VSEQ_B
1412 UINT64_C(1879146496), // VSEQ_D
1413 UINT64_C(1879080960), // VSEQ_H
1414 UINT64_C(1879113728), // VSEQ_W
1415 UINT64_C(1922871296), // VSETALLNEZ_B
1416 UINT64_C(1922874368), // VSETALLNEZ_D
1417 UINT64_C(1922872320), // VSETALLNEZ_H
1418 UINT64_C(1922873344), // VSETALLNEZ_W
1419 UINT64_C(1922867200), // VSETANYEQZ_B
1420 UINT64_C(1922870272), // VSETANYEQZ_D
1421 UINT64_C(1922868224), // VSETANYEQZ_H
1422 UINT64_C(1922869248), // VSETANYEQZ_W
1423 UINT64_C(1922865152), // VSETEQZ_V
1424 UINT64_C(1922866176), // VSETNEZ_V
1425 UINT64_C(1938817024), // VSHUF4I_B
1426 UINT64_C(1939603456), // VSHUF4I_D
1427 UINT64_C(1939079168), // VSHUF4I_H
1428 UINT64_C(1939341312), // VSHUF4I_W
1429 UINT64_C(223346688), // VSHUF_B
1430 UINT64_C(1903919104), // VSHUF_D
1431 UINT64_C(1903853568), // VSHUF_H
1432 UINT64_C(1903886336), // VSHUF_W
1433 UINT64_C(1898840064), // VSIGNCOV_B
1434 UINT64_C(1898938368), // VSIGNCOV_D
1435 UINT64_C(1898872832), // VSIGNCOV_H
1436 UINT64_C(1898905600), // VSIGNCOV_W
1437 UINT64_C(1921122304), // VSLEI_B
1438 UINT64_C(1921253376), // VSLEI_BU
1439 UINT64_C(1921220608), // VSLEI_D
1440 UINT64_C(1921351680), // VSLEI_DU
1441 UINT64_C(1921155072), // VSLEI_H
1442 UINT64_C(1921286144), // VSLEI_HU
1443 UINT64_C(1921187840), // VSLEI_W
1444 UINT64_C(1921318912), // VSLEI_WU
1445 UINT64_C(1879179264), // VSLE_B
1446 UINT64_C(1879310336), // VSLE_BU
1447 UINT64_C(1879277568), // VSLE_D
1448 UINT64_C(1879408640), // VSLE_DU
1449 UINT64_C(1879212032), // VSLE_H
1450 UINT64_C(1879343104), // VSLE_HU
1451 UINT64_C(1879244800), // VSLE_W
1452 UINT64_C(1879375872), // VSLE_WU
1453 UINT64_C(1932271616), // VSLLI_B
1454 UINT64_C(1932328960), // VSLLI_D
1455 UINT64_C(1932279808), // VSLLI_H
1456 UINT64_C(1932296192), // VSLLI_W
1457 UINT64_C(1930199040), // VSLLWIL_DU_WU
1458 UINT64_C(1929936896), // VSLLWIL_D_W
1459 UINT64_C(1930174464), // VSLLWIL_HU_BU
1460 UINT64_C(1929912320), // VSLLWIL_H_B
1461 UINT64_C(1930182656), // VSLLWIL_WU_HU
1462 UINT64_C(1929920512), // VSLLWIL_W_H
1463 UINT64_C(1894252544), // VSLL_B
1464 UINT64_C(1894350848), // VSLL_D
1465 UINT64_C(1894285312), // VSLL_H
1466 UINT64_C(1894318080), // VSLL_W
1467 UINT64_C(1921384448), // VSLTI_B
1468 UINT64_C(1921515520), // VSLTI_BU
1469 UINT64_C(1921482752), // VSLTI_D
1470 UINT64_C(1921613824), // VSLTI_DU
1471 UINT64_C(1921417216), // VSLTI_H
1472 UINT64_C(1921548288), // VSLTI_HU
1473 UINT64_C(1921449984), // VSLTI_W
1474 UINT64_C(1921581056), // VSLTI_WU
1475 UINT64_C(1879441408), // VSLT_B
1476 UINT64_C(1879572480), // VSLT_BU
1477 UINT64_C(1879539712), // VSLT_D
1478 UINT64_C(1879670784), // VSLT_DU
1479 UINT64_C(1879474176), // VSLT_H
1480 UINT64_C(1879605248), // VSLT_HU
1481 UINT64_C(1879506944), // VSLT_W
1482 UINT64_C(1879638016), // VSLT_WU
1483 UINT64_C(1932795904), // VSRAI_B
1484 UINT64_C(1932853248), // VSRAI_D
1485 UINT64_C(1932804096), // VSRAI_H
1486 UINT64_C(1932820480), // VSRAI_W
1487 UINT64_C(1935163392), // VSRANI_B_H
1488 UINT64_C(1935278080), // VSRANI_D_Q
1489 UINT64_C(1935179776), // VSRANI_H_W
1490 UINT64_C(1935212544), // VSRANI_W_D
1491 UINT64_C(1895202816), // VSRAN_B_H
1492 UINT64_C(1895235584), // VSRAN_H_W
1493 UINT64_C(1895268352), // VSRAN_W_D
1494 UINT64_C(1923620864), // VSRARI_B
1495 UINT64_C(1923678208), // VSRARI_D
1496 UINT64_C(1923629056), // VSRARI_H
1497 UINT64_C(1923645440), // VSRARI_W
1498 UINT64_C(1935425536), // VSRARNI_B_H
1499 UINT64_C(1935540224), // VSRARNI_D_Q
1500 UINT64_C(1935441920), // VSRARNI_H_W
1501 UINT64_C(1935474688), // VSRARNI_W_D
1502 UINT64_C(1895464960), // VSRARN_B_H
1503 UINT64_C(1895497728), // VSRARN_H_W
1504 UINT64_C(1895530496), // VSRARN_W_D
1505 UINT64_C(1894907904), // VSRAR_B
1506 UINT64_C(1895006208), // VSRAR_D
1507 UINT64_C(1894940672), // VSRAR_H
1508 UINT64_C(1894973440), // VSRAR_W
1509 UINT64_C(1894514688), // VSRA_B
1510 UINT64_C(1894612992), // VSRA_D
1511 UINT64_C(1894547456), // VSRA_H
1512 UINT64_C(1894580224), // VSRA_W
1513 UINT64_C(1932533760), // VSRLI_B
1514 UINT64_C(1932591104), // VSRLI_D
1515 UINT64_C(1932541952), // VSRLI_H
1516 UINT64_C(1932558336), // VSRLI_W
1517 UINT64_C(1933590528), // VSRLNI_B_H
1518 UINT64_C(1933705216), // VSRLNI_D_Q
1519 UINT64_C(1933606912), // VSRLNI_H_W
1520 UINT64_C(1933639680), // VSRLNI_W_D
1521 UINT64_C(1895071744), // VSRLN_B_H
1522 UINT64_C(1895104512), // VSRLN_H_W
1523 UINT64_C(1895137280), // VSRLN_W_D
1524 UINT64_C(1923358720), // VSRLRI_B
1525 UINT64_C(1923416064), // VSRLRI_D
1526 UINT64_C(1923366912), // VSRLRI_H
1527 UINT64_C(1923383296), // VSRLRI_W
1528 UINT64_C(1933852672), // VSRLRNI_B_H
1529 UINT64_C(1933967360), // VSRLRNI_D_Q
1530 UINT64_C(1933869056), // VSRLRNI_H_W
1531 UINT64_C(1933901824), // VSRLRNI_W_D
1532 UINT64_C(1895333888), // VSRLRN_B_H
1533 UINT64_C(1895366656), // VSRLRN_H_W
1534 UINT64_C(1895399424), // VSRLRN_W_D
1535 UINT64_C(1894776832), // VSRLR_B
1536 UINT64_C(1894875136), // VSRLR_D
1537 UINT64_C(1894809600), // VSRLR_H
1538 UINT64_C(1894842368), // VSRLR_W
1539 UINT64_C(1894383616), // VSRL_B
1540 UINT64_C(1894481920), // VSRL_D
1541 UINT64_C(1894416384), // VSRL_H
1542 UINT64_C(1894449152), // VSRL_W
1543 UINT64_C(1935949824), // VSSRANI_BU_H
1544 UINT64_C(1935687680), // VSSRANI_B_H
1545 UINT64_C(1936064512), // VSSRANI_DU_Q
1546 UINT64_C(1935802368), // VSSRANI_D_Q
1547 UINT64_C(1935966208), // VSSRANI_HU_W
1548 UINT64_C(1935704064), // VSSRANI_H_W
1549 UINT64_C(1935998976), // VSSRANI_WU_D
1550 UINT64_C(1935736832), // VSSRANI_W_D
1551 UINT64_C(1896251392), // VSSRAN_BU_H
1552 UINT64_C(1895727104), // VSSRAN_B_H
1553 UINT64_C(1896284160), // VSSRAN_HU_W
1554 UINT64_C(1895759872), // VSSRAN_H_W
1555 UINT64_C(1896316928), // VSSRAN_WU_D
1556 UINT64_C(1895792640), // VSSRAN_W_D
1557 UINT64_C(1936474112), // VSSRARNI_BU_H
1558 UINT64_C(1936211968), // VSSRARNI_B_H
1559 UINT64_C(1936588800), // VSSRARNI_DU_Q
1560 UINT64_C(1936326656), // VSSRARNI_D_Q
1561 UINT64_C(1936490496), // VSSRARNI_HU_W
1562 UINT64_C(1936228352), // VSSRARNI_H_W
1563 UINT64_C(1936523264), // VSSRARNI_WU_D
1564 UINT64_C(1936261120), // VSSRARNI_W_D
1565 UINT64_C(1896513536), // VSSRARN_BU_H
1566 UINT64_C(1895989248), // VSSRARN_B_H
1567 UINT64_C(1896546304), // VSSRARN_HU_W
1568 UINT64_C(1896022016), // VSSRARN_H_W
1569 UINT64_C(1896579072), // VSSRARN_WU_D
1570 UINT64_C(1896054784), // VSSRARN_W_D
1571 UINT64_C(1934376960), // VSSRLNI_BU_H
1572 UINT64_C(1934114816), // VSSRLNI_B_H
1573 UINT64_C(1934491648), // VSSRLNI_DU_Q
1574 UINT64_C(1934229504), // VSSRLNI_D_Q
1575 UINT64_C(1934393344), // VSSRLNI_HU_W
1576 UINT64_C(1934131200), // VSSRLNI_H_W
1577 UINT64_C(1934426112), // VSSRLNI_WU_D
1578 UINT64_C(1934163968), // VSSRLNI_W_D
1579 UINT64_C(1896120320), // VSSRLN_BU_H
1580 UINT64_C(1895596032), // VSSRLN_B_H
1581 UINT64_C(1896153088), // VSSRLN_HU_W
1582 UINT64_C(1895628800), // VSSRLN_H_W
1583 UINT64_C(1896185856), // VSSRLN_WU_D
1584 UINT64_C(1895661568), // VSSRLN_W_D
1585 UINT64_C(1934901248), // VSSRLRNI_BU_H
1586 UINT64_C(1934639104), // VSSRLRNI_B_H
1587 UINT64_C(1935015936), // VSSRLRNI_DU_Q
1588 UINT64_C(1934753792), // VSSRLRNI_D_Q
1589 UINT64_C(1934917632), // VSSRLRNI_HU_W
1590 UINT64_C(1934655488), // VSSRLRNI_H_W
1591 UINT64_C(1934950400), // VSSRLRNI_WU_D
1592 UINT64_C(1934688256), // VSSRLRNI_W_D
1593 UINT64_C(1896382464), // VSSRLRN_BU_H
1594 UINT64_C(1895858176), // VSSRLRN_B_H
1595 UINT64_C(1896415232), // VSSRLRN_HU_W
1596 UINT64_C(1895890944), // VSSRLRN_H_W
1597 UINT64_C(1896448000), // VSSRLRN_WU_D
1598 UINT64_C(1895923712), // VSSRLRN_W_D
1599 UINT64_C(1883766784), // VSSUB_B
1600 UINT64_C(1884028928), // VSSUB_BU
1601 UINT64_C(1883865088), // VSSUB_D
1602 UINT64_C(1884127232), // VSSUB_DU
1603 UINT64_C(1883799552), // VSSUB_H
1604 UINT64_C(1884061696), // VSSUB_HU
1605 UINT64_C(1883832320), // VSSUB_W
1606 UINT64_C(1884094464), // VSSUB_WU
1607 UINT64_C(742391808), // VST
1608 UINT64_C(830472192), // VSTELM_B
1609 UINT64_C(823132160), // VSTELM_D
1610 UINT64_C(826277888), // VSTELM_H
1611 UINT64_C(824180736), // VSTELM_W
1612 UINT64_C(943980544), // VSTX
1613 UINT64_C(1921777664), // VSUBI_BU
1614 UINT64_C(1921875968), // VSUBI_DU
1615 UINT64_C(1921810432), // VSUBI_HU
1616 UINT64_C(1921843200), // VSUBI_WU
1617 UINT64_C(1881210880), // VSUBWEV_D_W
1618 UINT64_C(1882259456), // VSUBWEV_D_WU
1619 UINT64_C(1881145344), // VSUBWEV_H_B
1620 UINT64_C(1882193920), // VSUBWEV_H_BU
1621 UINT64_C(1881243648), // VSUBWEV_Q_D
1622 UINT64_C(1882292224), // VSUBWEV_Q_DU
1623 UINT64_C(1881178112), // VSUBWEV_W_H
1624 UINT64_C(1882226688), // VSUBWEV_W_HU
1625 UINT64_C(1881473024), // VSUBWOD_D_W
1626 UINT64_C(1882521600), // VSUBWOD_D_WU
1627 UINT64_C(1881407488), // VSUBWOD_H_B
1628 UINT64_C(1882456064), // VSUBWOD_H_BU
1629 UINT64_C(1881505792), // VSUBWOD_Q_D
1630 UINT64_C(1882554368), // VSUBWOD_Q_DU
1631 UINT64_C(1881440256), // VSUBWOD_W_H
1632 UINT64_C(1882488832), // VSUBWOD_W_HU
1633 UINT64_C(1879834624), // VSUB_B
1634 UINT64_C(1879932928), // VSUB_D
1635 UINT64_C(1879867392), // VSUB_H
1636 UINT64_C(1898807296), // VSUB_Q
1637 UINT64_C(1879900160), // VSUB_W
1638 UINT64_C(1943535616), // VXORI_B
1639 UINT64_C(1898381312), // VXOR_V
1640 UINT64_C(4128780), // X86ADC_B
1641 UINT64_C(4128783), // X86ADC_D
1642 UINT64_C(4128781), // X86ADC_H
1643 UINT64_C(4128782), // X86ADC_W
1644 UINT64_C(4128772), // X86ADD_B
1645 UINT64_C(4128775), // X86ADD_D
1646 UINT64_C(4128769), // X86ADD_DU
1647 UINT64_C(4128773), // X86ADD_H
1648 UINT64_C(4128774), // X86ADD_W
1649 UINT64_C(4128768), // X86ADD_WU
1650 UINT64_C(4161552), // X86AND_B
1651 UINT64_C(4161555), // X86AND_D
1652 UINT64_C(4161553), // X86AND_H
1653 UINT64_C(4161554), // X86AND_W
1654 UINT64_C(32808), // X86CLRTM
1655 UINT64_C(32809), // X86DECTOP
1656 UINT64_C(32772), // X86DEC_B
1657 UINT64_C(32775), // X86DEC_D
1658 UINT64_C(32773), // X86DEC_H
1659 UINT64_C(32774), // X86DEC_W
1660 UINT64_C(32777), // X86INCTOP
1661 UINT64_C(32768), // X86INC_B
1662 UINT64_C(32771), // X86INC_D
1663 UINT64_C(32769), // X86INC_H
1664 UINT64_C(32770), // X86INC_W
1665 UINT64_C(6029312), // X86MFFLAG
1666 UINT64_C(29696), // X86MFTOP
1667 UINT64_C(6029344), // X86MTFLAG
1668 UINT64_C(28672), // X86MTTOP
1669 UINT64_C(4096000), // X86MUL_B
1670 UINT64_C(4096004), // X86MUL_BU
1671 UINT64_C(4096003), // X86MUL_D
1672 UINT64_C(4096007), // X86MUL_DU
1673 UINT64_C(4096001), // X86MUL_H
1674 UINT64_C(4096005), // X86MUL_HU
1675 UINT64_C(4096002), // X86MUL_W
1676 UINT64_C(4096006), // X86MUL_WU
1677 UINT64_C(4161556), // X86OR_B
1678 UINT64_C(4161559), // X86OR_D
1679 UINT64_C(4161557), // X86OR_H
1680 UINT64_C(4161558), // X86OR_W
1681 UINT64_C(5513240), // X86RCLI_B
1682 UINT64_C(5570587), // X86RCLI_D
1683 UINT64_C(5521433), // X86RCLI_H
1684 UINT64_C(5537818), // X86RCLI_W
1685 UINT64_C(4161548), // X86RCL_B
1686 UINT64_C(4161551), // X86RCL_D
1687 UINT64_C(4161549), // X86RCL_H
1688 UINT64_C(4161550), // X86RCL_W
1689 UINT64_C(5513232), // X86RCRI_B
1690 UINT64_C(5570579), // X86RCRI_D
1691 UINT64_C(5521425), // X86RCRI_H
1692 UINT64_C(5537810), // X86RCRI_W
1693 UINT64_C(4161544), // X86RCR_B
1694 UINT64_C(4161547), // X86RCR_D
1695 UINT64_C(4161545), // X86RCR_H
1696 UINT64_C(4161546), // X86RCR_W
1697 UINT64_C(5513236), // X86ROTLI_B
1698 UINT64_C(5570583), // X86ROTLI_D
1699 UINT64_C(5521429), // X86ROTLI_H
1700 UINT64_C(5537814), // X86ROTLI_W
1701 UINT64_C(4161540), // X86ROTL_B
1702 UINT64_C(4161543), // X86ROTL_D
1703 UINT64_C(4161541), // X86ROTL_H
1704 UINT64_C(4161542), // X86ROTL_W
1705 UINT64_C(5513228), // X86ROTRI_B
1706 UINT64_C(5570575), // X86ROTRI_D
1707 UINT64_C(5521421), // X86ROTRI_H
1708 UINT64_C(5537806), // X86ROTRI_W
1709 UINT64_C(4161536), // X86ROTR_B
1710 UINT64_C(4161538), // X86ROTR_D
1711 UINT64_C(4161537), // X86ROTR_H
1712 UINT64_C(4161539), // X86ROTR_W
1713 UINT64_C(4128784), // X86SBC_B
1714 UINT64_C(4128787), // X86SBC_D
1715 UINT64_C(4128785), // X86SBC_H
1716 UINT64_C(4128786), // X86SBC_W
1717 UINT64_C(5767168), // X86SETTAG
1718 UINT64_C(32776), // X86SETTM
1719 UINT64_C(5513216), // X86SLLI_B
1720 UINT64_C(5570563), // X86SLLI_D
1721 UINT64_C(5521409), // X86SLLI_H
1722 UINT64_C(5537794), // X86SLLI_W
1723 UINT64_C(4128788), // X86SLL_B
1724 UINT64_C(4128791), // X86SLL_D
1725 UINT64_C(4128789), // X86SLL_H
1726 UINT64_C(4128790), // X86SLL_W
1727 UINT64_C(5513224), // X86SRAI_B
1728 UINT64_C(5570571), // X86SRAI_D
1729 UINT64_C(5521417), // X86SRAI_H
1730 UINT64_C(5537802), // X86SRAI_W
1731 UINT64_C(4128796), // X86SRA_B
1732 UINT64_C(4128799), // X86SRA_D
1733 UINT64_C(4128797), // X86SRA_H
1734 UINT64_C(4128798), // X86SRA_W
1735 UINT64_C(5513220), // X86SRLI_B
1736 UINT64_C(5570567), // X86SRLI_D
1737 UINT64_C(5521413), // X86SRLI_H
1738 UINT64_C(5537798), // X86SRLI_W
1739 UINT64_C(4128792), // X86SRL_B
1740 UINT64_C(4128795), // X86SRL_D
1741 UINT64_C(4128793), // X86SRL_H
1742 UINT64_C(4128794), // X86SRL_W
1743 UINT64_C(4128776), // X86SUB_B
1744 UINT64_C(4128779), // X86SUB_D
1745 UINT64_C(4128771), // X86SUB_DU
1746 UINT64_C(4128777), // X86SUB_H
1747 UINT64_C(4128778), // X86SUB_W
1748 UINT64_C(4128770), // X86SUB_WU
1749 UINT64_C(4161560), // X86XOR_B
1750 UINT64_C(4161563), // X86XOR_D
1751 UINT64_C(4161561), // X86XOR_H
1752 UINT64_C(4161562), // X86XOR_W
1753 UINT64_C(1409024), // XOR
1754 UINT64_C(62914560), // XORI
1755 UINT64_C(1952448512), // XVABSD_B
1756 UINT64_C(1952579584), // XVABSD_BU
1757 UINT64_C(1952546816), // XVABSD_D
1758 UINT64_C(1952677888), // XVABSD_DU
1759 UINT64_C(1952481280), // XVABSD_H
1760 UINT64_C(1952612352), // XVABSD_HU
1761 UINT64_C(1952514048), // XVABSD_W
1762 UINT64_C(1952645120), // XVABSD_WU
1763 UINT64_C(1952186368), // XVADDA_B
1764 UINT64_C(1952284672), // XVADDA_D
1765 UINT64_C(1952219136), // XVADDA_H
1766 UINT64_C(1952251904), // XVADDA_W
1767 UINT64_C(1988755456), // XVADDI_BU
1768 UINT64_C(1988853760), // XVADDI_DU
1769 UINT64_C(1988788224), // XVADDI_HU
1770 UINT64_C(1988820992), // XVADDI_WU
1771 UINT64_C(1948188672), // XVADDWEV_D_W
1772 UINT64_C(1949237248), // XVADDWEV_D_WU
1773 UINT64_C(1950285824), // XVADDWEV_D_WU_W
1774 UINT64_C(1948123136), // XVADDWEV_H_B
1775 UINT64_C(1949171712), // XVADDWEV_H_BU
1776 UINT64_C(1950220288), // XVADDWEV_H_BU_B
1777 UINT64_C(1948221440), // XVADDWEV_Q_D
1778 UINT64_C(1949270016), // XVADDWEV_Q_DU
1779 UINT64_C(1950318592), // XVADDWEV_Q_DU_D
1780 UINT64_C(1948155904), // XVADDWEV_W_H
1781 UINT64_C(1949204480), // XVADDWEV_W_HU
1782 UINT64_C(1950253056), // XVADDWEV_W_HU_H
1783 UINT64_C(1948450816), // XVADDWOD_D_W
1784 UINT64_C(1949499392), // XVADDWOD_D_WU
1785 UINT64_C(1950416896), // XVADDWOD_D_WU_W
1786 UINT64_C(1948385280), // XVADDWOD_H_B
1787 UINT64_C(1949433856), // XVADDWOD_H_BU
1788 UINT64_C(1950351360), // XVADDWOD_H_BU_B
1789 UINT64_C(1948483584), // XVADDWOD_Q_D
1790 UINT64_C(1949532160), // XVADDWOD_Q_DU
1791 UINT64_C(1950449664), // XVADDWOD_Q_DU_D
1792 UINT64_C(1948418048), // XVADDWOD_W_H
1793 UINT64_C(1949466624), // XVADDWOD_W_HU
1794 UINT64_C(1950384128), // XVADDWOD_W_HU_H
1795 UINT64_C(1946812416), // XVADD_B
1796 UINT64_C(1946910720), // XVADD_D
1797 UINT64_C(1946845184), // XVADD_H
1798 UINT64_C(1965883392), // XVADD_Q
1799 UINT64_C(1946877952), // XVADD_W
1800 UINT64_C(2010120192), // XVANDI_B
1801 UINT64_C(1965555712), // XVANDN_V
1802 UINT64_C(1965424640), // XVAND_V
1803 UINT64_C(1952972800), // XVAVGR_B
1804 UINT64_C(1953103872), // XVAVGR_BU
1805 UINT64_C(1953071104), // XVAVGR_D
1806 UINT64_C(1953202176), // XVAVGR_DU
1807 UINT64_C(1953005568), // XVAVGR_H
1808 UINT64_C(1953136640), // XVAVGR_HU
1809 UINT64_C(1953038336), // XVAVGR_W
1810 UINT64_C(1953169408), // XVAVGR_WU
1811 UINT64_C(1952710656), // XVAVG_B
1812 UINT64_C(1952841728), // XVAVG_BU
1813 UINT64_C(1952808960), // XVAVG_D
1814 UINT64_C(1952940032), // XVAVG_DU
1815 UINT64_C(1952743424), // XVAVG_H
1816 UINT64_C(1952874496), // XVAVG_HU
1817 UINT64_C(1952776192), // XVAVG_W
1818 UINT64_C(1952907264), // XVAVG_WU
1819 UINT64_C(1997545472), // XVBITCLRI_B
1820 UINT64_C(1997602816), // XVBITCLRI_D
1821 UINT64_C(1997553664), // XVBITCLRI_H
1822 UINT64_C(1997570048), // XVBITCLRI_W
1823 UINT64_C(1963720704), // XVBITCLR_B
1824 UINT64_C(1963819008), // XVBITCLR_D
1825 UINT64_C(1963753472), // XVBITCLR_H
1826 UINT64_C(1963786240), // XVBITCLR_W
1827 UINT64_C(1998069760), // XVBITREVI_B
1828 UINT64_C(1998127104), // XVBITREVI_D
1829 UINT64_C(1998077952), // XVBITREVI_H
1830 UINT64_C(1998094336), // XVBITREVI_W
1831 UINT64_C(1963982848), // XVBITREV_B
1832 UINT64_C(1964081152), // XVBITREV_D
1833 UINT64_C(1964015616), // XVBITREV_H
1834 UINT64_C(1964048384), // XVBITREV_W
1835 UINT64_C(2009333760), // XVBITSELI_B
1836 UINT64_C(220200960), // XVBITSEL_V
1837 UINT64_C(1997807616), // XVBITSETI_B
1838 UINT64_C(1997864960), // XVBITSETI_D
1839 UINT64_C(1997815808), // XVBITSETI_H
1840 UINT64_C(1997832192), // XVBITSETI_W
1841 UINT64_C(1963851776), // XVBITSET_B
1842 UINT64_C(1963950080), // XVBITSET_D
1843 UINT64_C(1963884544), // XVBITSET_H
1844 UINT64_C(1963917312), // XVBITSET_W
1845 UINT64_C(1989017600), // XVBSLL_V
1846 UINT64_C(1989050368), // XVBSRL_V
1847 UINT64_C(1989935104), // XVCLO_B
1848 UINT64_C(1989938176), // XVCLO_D
1849 UINT64_C(1989936128), // XVCLO_H
1850 UINT64_C(1989937152), // XVCLO_W
1851 UINT64_C(1989939200), // XVCLZ_B
1852 UINT64_C(1989942272), // XVCLZ_D
1853 UINT64_C(1989940224), // XVCLZ_H
1854 UINT64_C(1989941248), // XVCLZ_W
1855 UINT64_C(1960837120), // XVDIV_B
1856 UINT64_C(1961099264), // XVDIV_BU
1857 UINT64_C(1960935424), // XVDIV_D
1858 UINT64_C(1961197568), // XVDIV_DU
1859 UINT64_C(1960869888), // XVDIV_H
1860 UINT64_C(1961132032), // XVDIV_HU
1861 UINT64_C(1960902656), // XVDIV_W
1862 UINT64_C(1961164800), // XVDIV_WU
1863 UINT64_C(1990129664), // XVEXTH_DU_WU
1864 UINT64_C(1990125568), // XVEXTH_D_W
1865 UINT64_C(1990127616), // XVEXTH_HU_BU
1866 UINT64_C(1990123520), // XVEXTH_H_B
1867 UINT64_C(1990130688), // XVEXTH_QU_DU
1868 UINT64_C(1990126592), // XVEXTH_Q_D
1869 UINT64_C(1990128640), // XVEXTH_WU_HU
1870 UINT64_C(1990124544), // XVEXTH_W_H
1871 UINT64_C(1997340672), // XVEXTL_QU_DU
1872 UINT64_C(1997078528), // XVEXTL_Q_D
1873 UINT64_C(2005663744), // XVEXTRINS_B
1874 UINT64_C(2004877312), // XVEXTRINS_D
1875 UINT64_C(2005401600), // XVEXTRINS_H
1876 UINT64_C(2005139456), // XVEXTRINS_W
1877 UINT64_C(1966145536), // XVFADD_D
1878 UINT64_C(1966112768), // XVFADD_S
1879 UINT64_C(1989990400), // XVFCLASS_D
1880 UINT64_C(1989989376), // XVFCLASS_S
1881 UINT64_C(211812352), // XVFCMP_CAF_D
1882 UINT64_C(210763776), // XVFCMP_CAF_S
1883 UINT64_C(211943424), // XVFCMP_CEQ_D
1884 UINT64_C(210894848), // XVFCMP_CEQ_S
1885 UINT64_C(212008960), // XVFCMP_CLE_D
1886 UINT64_C(210960384), // XVFCMP_CLE_S
1887 UINT64_C(211877888), // XVFCMP_CLT_D
1888 UINT64_C(210829312), // XVFCMP_CLT_S
1889 UINT64_C(212336640), // XVFCMP_CNE_D
1890 UINT64_C(211288064), // XVFCMP_CNE_S
1891 UINT64_C(212467712), // XVFCMP_COR_D
1892 UINT64_C(211419136), // XVFCMP_COR_S
1893 UINT64_C(212205568), // XVFCMP_CUEQ_D
1894 UINT64_C(211156992), // XVFCMP_CUEQ_S
1895 UINT64_C(212271104), // XVFCMP_CULE_D
1896 UINT64_C(211222528), // XVFCMP_CULE_S
1897 UINT64_C(212140032), // XVFCMP_CULT_D
1898 UINT64_C(211091456), // XVFCMP_CULT_S
1899 UINT64_C(212598784), // XVFCMP_CUNE_D
1900 UINT64_C(211550208), // XVFCMP_CUNE_S
1901 UINT64_C(212074496), // XVFCMP_CUN_D
1902 UINT64_C(211025920), // XVFCMP_CUN_S
1903 UINT64_C(211845120), // XVFCMP_SAF_D
1904 UINT64_C(210796544), // XVFCMP_SAF_S
1905 UINT64_C(211976192), // XVFCMP_SEQ_D
1906 UINT64_C(210927616), // XVFCMP_SEQ_S
1907 UINT64_C(212041728), // XVFCMP_SLE_D
1908 UINT64_C(210993152), // XVFCMP_SLE_S
1909 UINT64_C(211910656), // XVFCMP_SLT_D
1910 UINT64_C(210862080), // XVFCMP_SLT_S
1911 UINT64_C(212369408), // XVFCMP_SNE_D
1912 UINT64_C(211320832), // XVFCMP_SNE_S
1913 UINT64_C(212500480), // XVFCMP_SOR_D
1914 UINT64_C(211451904), // XVFCMP_SOR_S
1915 UINT64_C(212238336), // XVFCMP_SUEQ_D
1916 UINT64_C(211189760), // XVFCMP_SUEQ_S
1917 UINT64_C(212303872), // XVFCMP_SULE_D
1918 UINT64_C(211255296), // XVFCMP_SULE_S
1919 UINT64_C(212172800), // XVFCMP_SULT_D
1920 UINT64_C(211124224), // XVFCMP_SULT_S
1921 UINT64_C(212631552), // XVFCMP_SUNE_D
1922 UINT64_C(211582976), // XVFCMP_SUNE_S
1923 UINT64_C(212107264), // XVFCMP_SUN_D
1924 UINT64_C(211058688), // XVFCMP_SUN_S
1925 UINT64_C(1990063104), // XVFCVTH_D_S
1926 UINT64_C(1990061056), // XVFCVTH_S_H
1927 UINT64_C(1990062080), // XVFCVTL_D_S
1928 UINT64_C(1990060032), // XVFCVTL_S_H
1929 UINT64_C(1967521792), // XVFCVT_H_S
1930 UINT64_C(1967554560), // XVFCVT_S_D
1931 UINT64_C(1966800896), // XVFDIV_D
1932 UINT64_C(1966768128), // XVFDIV_S
1933 UINT64_C(1990071296), // XVFFINTH_D_W
1934 UINT64_C(1990070272), // XVFFINTL_D_W
1935 UINT64_C(1990068224), // XVFFINT_D_L
1936 UINT64_C(1990069248), // XVFFINT_D_LU
1937 UINT64_C(1967652864), // XVFFINT_S_L
1938 UINT64_C(1990066176), // XVFFINT_S_W
1939 UINT64_C(1990067200), // XVFFINT_S_WU
1940 UINT64_C(1989986304), // XVFLOGB_D
1941 UINT64_C(1989985280), // XVFLOGB_S
1942 UINT64_C(169869312), // XVFMADD_D
1943 UINT64_C(168820736), // XVFMADD_S
1944 UINT64_C(1967194112), // XVFMAXA_D
1945 UINT64_C(1967161344), // XVFMAXA_S
1946 UINT64_C(1966931968), // XVFMAX_D
1947 UINT64_C(1966899200), // XVFMAX_S
1948 UINT64_C(1967325184), // XVFMINA_D
1949 UINT64_C(1967292416), // XVFMINA_S
1950 UINT64_C(1967063040), // XVFMIN_D
1951 UINT64_C(1967030272), // XVFMIN_S
1952 UINT64_C(174063616), // XVFMSUB_D
1953 UINT64_C(173015040), // XVFMSUB_S
1954 UINT64_C(1966669824), // XVFMUL_D
1955 UINT64_C(1966637056), // XVFMUL_S
1956 UINT64_C(178257920), // XVFNMADD_D
1957 UINT64_C(177209344), // XVFNMADD_S
1958 UINT64_C(182452224), // XVFNMSUB_D
1959 UINT64_C(181403648), // XVFNMSUB_S
1960 UINT64_C(1990006784), // XVFRECIPE_D
1961 UINT64_C(1990005760), // XVFRECIPE_S
1962 UINT64_C(1989998592), // XVFRECIP_D
1963 UINT64_C(1989997568), // XVFRECIP_S
1964 UINT64_C(1990019072), // XVFRINTRM_D
1965 UINT64_C(1990018048), // XVFRINTRM_S
1966 UINT64_C(1990031360), // XVFRINTRNE_D
1967 UINT64_C(1990030336), // XVFRINTRNE_S
1968 UINT64_C(1990023168), // XVFRINTRP_D
1969 UINT64_C(1990022144), // XVFRINTRP_S
1970 UINT64_C(1990027264), // XVFRINTRZ_D
1971 UINT64_C(1990026240), // XVFRINTRZ_S
1972 UINT64_C(1990014976), // XVFRINT_D
1973 UINT64_C(1990013952), // XVFRINT_S
1974 UINT64_C(1990010880), // XVFRSQRTE_D
1975 UINT64_C(1990009856), // XVFRSQRTE_S
1976 UINT64_C(1990002688), // XVFRSQRT_D
1977 UINT64_C(1990001664), // XVFRSQRT_S
1978 UINT64_C(1989804032), // XVFRSTPI_B
1979 UINT64_C(1989836800), // XVFRSTPI_H
1980 UINT64_C(1965752320), // XVFRSTP_B
1981 UINT64_C(1965785088), // XVFRSTP_H
1982 UINT64_C(1989994496), // XVFSQRT_D
1983 UINT64_C(1989993472), // XVFSQRT_S
1984 UINT64_C(1966276608), // XVFSUB_D
1985 UINT64_C(1966243840), // XVFSUB_S
1986 UINT64_C(1990099968), // XVFTINTH_L_S
1987 UINT64_C(1990098944), // XVFTINTL_L_S
1988 UINT64_C(1990102016), // XVFTINTRMH_L_S
1989 UINT64_C(1990100992), // XVFTINTRML_L_S
1990 UINT64_C(1990081536), // XVFTINTRM_L_D
1991 UINT64_C(1967783936), // XVFTINTRM_W_D
1992 UINT64_C(1990080512), // XVFTINTRM_W_S
1993 UINT64_C(1990108160), // XVFTINTRNEH_L_S
1994 UINT64_C(1990107136), // XVFTINTRNEL_L_S
1995 UINT64_C(1990087680), // XVFTINTRNE_L_D
1996 UINT64_C(1967882240), // XVFTINTRNE_W_D
1997 UINT64_C(1990086656), // XVFTINTRNE_W_S
1998 UINT64_C(1990104064), // XVFTINTRPH_L_S
1999 UINT64_C(1990103040), // XVFTINTRPL_L_S
2000 UINT64_C(1990083584), // XVFTINTRP_L_D
2001 UINT64_C(1967816704), // XVFTINTRP_W_D
2002 UINT64_C(1990082560), // XVFTINTRP_W_S
2003 UINT64_C(1990106112), // XVFTINTRZH_L_S
2004 UINT64_C(1990105088), // XVFTINTRZL_L_S
2005 UINT64_C(1990095872), // XVFTINTRZ_LU_D
2006 UINT64_C(1990085632), // XVFTINTRZ_L_D
2007 UINT64_C(1990094848), // XVFTINTRZ_WU_S
2008 UINT64_C(1967849472), // XVFTINTRZ_W_D
2009 UINT64_C(1990084608), // XVFTINTRZ_W_S
2010 UINT64_C(1990089728), // XVFTINT_LU_D
2011 UINT64_C(1990079488), // XVFTINT_L_D
2012 UINT64_C(1990088704), // XVFTINT_WU_S
2013 UINT64_C(1967751168), // XVFTINT_W_D
2014 UINT64_C(1990078464), // XVFTINT_W_S
2015 UINT64_C(1951989760), // XVHADDW_DU_WU
2016 UINT64_C(1951727616), // XVHADDW_D_W
2017 UINT64_C(1951924224), // XVHADDW_HU_BU
2018 UINT64_C(1951662080), // XVHADDW_H_B
2019 UINT64_C(1952022528), // XVHADDW_QU_DU
2020 UINT64_C(1951760384), // XVHADDW_Q_D
2021 UINT64_C(1951956992), // XVHADDW_WU_HU
2022 UINT64_C(1951694848), // XVHADDW_W_H
2023 UINT64_C(1990164480), // XVHSELI_D
2024 UINT64_C(1952120832), // XVHSUBW_DU_WU
2025 UINT64_C(1951858688), // XVHSUBW_D_W
2026 UINT64_C(1952055296), // XVHSUBW_HU_BU
2027 UINT64_C(1951793152), // XVHSUBW_H_B
2028 UINT64_C(1952153600), // XVHSUBW_QU_DU
2029 UINT64_C(1951891456), // XVHSUBW_Q_D
2030 UINT64_C(1952088064), // XVHSUBW_WU_HU
2031 UINT64_C(1951825920), // XVHSUBW_W_H
2032 UINT64_C(1964769280), // XVILVH_B
2033 UINT64_C(1964867584), // XVILVH_D
2034 UINT64_C(1964802048), // XVILVH_H
2035 UINT64_C(1964834816), // XVILVH_W
2036 UINT64_C(1964638208), // XVILVL_B
2037 UINT64_C(1964736512), // XVILVL_D
2038 UINT64_C(1964670976), // XVILVL_H
2039 UINT64_C(1964703744), // XVILVL_W
2040 UINT64_C(1995169792), // XVINSGR2VR_D
2041 UINT64_C(1995161600), // XVINSGR2VR_W
2042 UINT64_C(1996480512), // XVINSVE0_D
2043 UINT64_C(1996472320), // XVINSVE0_W
2044 UINT64_C(746586112), // XVLD
2045 UINT64_C(2011168768), // XVLDI
2046 UINT64_C(847249408), // XVLDREPL_B
2047 UINT64_C(839909376), // XVLDREPL_D
2048 UINT64_C(843055104), // XVLDREPL_H
2049 UINT64_C(840957952), // XVLDREPL_W
2050 UINT64_C(944242688), // XVLDX
2051 UINT64_C(1957494784), // XVMADDWEV_D_W
2052 UINT64_C(1958019072), // XVMADDWEV_D_WU
2053 UINT64_C(1958543360), // XVMADDWEV_D_WU_W
2054 UINT64_C(1957429248), // XVMADDWEV_H_B
2055 UINT64_C(1957953536), // XVMADDWEV_H_BU
2056 UINT64_C(1958477824), // XVMADDWEV_H_BU_B
2057 UINT64_C(1957527552), // XVMADDWEV_Q_D
2058 UINT64_C(1958051840), // XVMADDWEV_Q_DU
2059 UINT64_C(1958576128), // XVMADDWEV_Q_DU_D
2060 UINT64_C(1957462016), // XVMADDWEV_W_H
2061 UINT64_C(1957986304), // XVMADDWEV_W_HU
2062 UINT64_C(1958510592), // XVMADDWEV_W_HU_H
2063 UINT64_C(1957625856), // XVMADDWOD_D_W
2064 UINT64_C(1958150144), // XVMADDWOD_D_WU
2065 UINT64_C(1958674432), // XVMADDWOD_D_WU_W
2066 UINT64_C(1957560320), // XVMADDWOD_H_B
2067 UINT64_C(1958084608), // XVMADDWOD_H_BU
2068 UINT64_C(1958608896), // XVMADDWOD_H_BU_B
2069 UINT64_C(1957658624), // XVMADDWOD_Q_D
2070 UINT64_C(1958182912), // XVMADDWOD_Q_DU
2071 UINT64_C(1958707200), // XVMADDWOD_Q_DU_D
2072 UINT64_C(1957593088), // XVMADDWOD_W_H
2073 UINT64_C(1958117376), // XVMADDWOD_W_HU
2074 UINT64_C(1958641664), // XVMADDWOD_W_HU_H
2075 UINT64_C(1957167104), // XVMADD_B
2076 UINT64_C(1957265408), // XVMADD_D
2077 UINT64_C(1957199872), // XVMADD_H
2078 UINT64_C(1957232640), // XVMADD_W
2079 UINT64_C(1989148672), // XVMAXI_B
2080 UINT64_C(1989410816), // XVMAXI_BU
2081 UINT64_C(1989246976), // XVMAXI_D
2082 UINT64_C(1989509120), // XVMAXI_DU
2083 UINT64_C(1989181440), // XVMAXI_H
2084 UINT64_C(1989443584), // XVMAXI_HU
2085 UINT64_C(1989214208), // XVMAXI_W
2086 UINT64_C(1989476352), // XVMAXI_WU
2087 UINT64_C(1953497088), // XVMAX_B
2088 UINT64_C(1953759232), // XVMAX_BU
2089 UINT64_C(1953595392), // XVMAX_D
2090 UINT64_C(1953857536), // XVMAX_DU
2091 UINT64_C(1953529856), // XVMAX_H
2092 UINT64_C(1953792000), // XVMAX_HU
2093 UINT64_C(1953562624), // XVMAX_W
2094 UINT64_C(1953824768), // XVMAX_WU
2095 UINT64_C(1989279744), // XVMINI_B
2096 UINT64_C(1989541888), // XVMINI_BU
2097 UINT64_C(1989378048), // XVMINI_D
2098 UINT64_C(1989640192), // XVMINI_DU
2099 UINT64_C(1989312512), // XVMINI_H
2100 UINT64_C(1989574656), // XVMINI_HU
2101 UINT64_C(1989345280), // XVMINI_W
2102 UINT64_C(1989607424), // XVMINI_WU
2103 UINT64_C(1953628160), // XVMIN_B
2104 UINT64_C(1953890304), // XVMIN_BU
2105 UINT64_C(1953726464), // XVMIN_D
2106 UINT64_C(1953988608), // XVMIN_DU
2107 UINT64_C(1953660928), // XVMIN_H
2108 UINT64_C(1953923072), // XVMIN_HU
2109 UINT64_C(1953693696), // XVMIN_W
2110 UINT64_C(1953955840), // XVMIN_WU
2111 UINT64_C(1960968192), // XVMOD_B
2112 UINT64_C(1961230336), // XVMOD_BU
2113 UINT64_C(1961066496), // XVMOD_D
2114 UINT64_C(1961328640), // XVMOD_DU
2115 UINT64_C(1961000960), // XVMOD_H
2116 UINT64_C(1961263104), // XVMOD_HU
2117 UINT64_C(1961033728), // XVMOD_W
2118 UINT64_C(1961295872), // XVMOD_WU
2119 UINT64_C(1989955584), // XVMSKGEZ_B
2120 UINT64_C(1989951488), // XVMSKLTZ_B
2121 UINT64_C(1989954560), // XVMSKLTZ_D
2122 UINT64_C(1989952512), // XVMSKLTZ_H
2123 UINT64_C(1989953536), // XVMSKLTZ_W
2124 UINT64_C(1989959680), // XVMSKNZ_B
2125 UINT64_C(1957298176), // XVMSUB_B
2126 UINT64_C(1957396480), // XVMSUB_D
2127 UINT64_C(1957330944), // XVMSUB_H
2128 UINT64_C(1957363712), // XVMSUB_W
2129 UINT64_C(1954938880), // XVMUH_B
2130 UINT64_C(1955069952), // XVMUH_BU
2131 UINT64_C(1955037184), // XVMUH_D
2132 UINT64_C(1955168256), // XVMUH_DU
2133 UINT64_C(1954971648), // XVMUH_H
2134 UINT64_C(1955102720), // XVMUH_HU
2135 UINT64_C(1955004416), // XVMUH_W
2136 UINT64_C(1955135488), // XVMUH_WU
2137 UINT64_C(1955659776), // XVMULWEV_D_W
2138 UINT64_C(1956184064), // XVMULWEV_D_WU
2139 UINT64_C(1956708352), // XVMULWEV_D_WU_W
2140 UINT64_C(1955594240), // XVMULWEV_H_B
2141 UINT64_C(1956118528), // XVMULWEV_H_BU
2142 UINT64_C(1956642816), // XVMULWEV_H_BU_B
2143 UINT64_C(1955692544), // XVMULWEV_Q_D
2144 UINT64_C(1956216832), // XVMULWEV_Q_DU
2145 UINT64_C(1956741120), // XVMULWEV_Q_DU_D
2146 UINT64_C(1955627008), // XVMULWEV_W_H
2147 UINT64_C(1956151296), // XVMULWEV_W_HU
2148 UINT64_C(1956675584), // XVMULWEV_W_HU_H
2149 UINT64_C(1955790848), // XVMULWOD_D_W
2150 UINT64_C(1956315136), // XVMULWOD_D_WU
2151 UINT64_C(1956839424), // XVMULWOD_D_WU_W
2152 UINT64_C(1955725312), // XVMULWOD_H_B
2153 UINT64_C(1956249600), // XVMULWOD_H_BU
2154 UINT64_C(1956773888), // XVMULWOD_H_BU_B
2155 UINT64_C(1955823616), // XVMULWOD_Q_D
2156 UINT64_C(1956347904), // XVMULWOD_Q_DU
2157 UINT64_C(1956872192), // XVMULWOD_Q_DU_D
2158 UINT64_C(1955758080), // XVMULWOD_W_H
2159 UINT64_C(1956282368), // XVMULWOD_W_HU
2160 UINT64_C(1956806656), // XVMULWOD_W_HU_H
2161 UINT64_C(1954807808), // XVMUL_B
2162 UINT64_C(1954906112), // XVMUL_D
2163 UINT64_C(1954840576), // XVMUL_H
2164 UINT64_C(1954873344), // XVMUL_W
2165 UINT64_C(1989947392), // XVNEG_B
2166 UINT64_C(1989950464), // XVNEG_D
2167 UINT64_C(1989948416), // XVNEG_H
2168 UINT64_C(1989949440), // XVNEG_W
2169 UINT64_C(2010906624), // XVNORI_B
2170 UINT64_C(1965522944), // XVNOR_V
2171 UINT64_C(2010382336), // XVORI_B
2172 UINT64_C(1965588480), // XVORN_V
2173 UINT64_C(1965457408), // XVOR_V
2174 UINT64_C(1964376064), // XVPACKEV_B
2175 UINT64_C(1964474368), // XVPACKEV_D
2176 UINT64_C(1964408832), // XVPACKEV_H
2177 UINT64_C(1964441600), // XVPACKEV_W
2178 UINT64_C(1964507136), // XVPACKOD_B
2179 UINT64_C(1964605440), // XVPACKOD_D
2180 UINT64_C(1964539904), // XVPACKOD_H
2181 UINT64_C(1964572672), // XVPACKOD_W
2182 UINT64_C(1989943296), // XVPCNT_B
2183 UINT64_C(1989946368), // XVPCNT_D
2184 UINT64_C(1989944320), // XVPCNT_H
2185 UINT64_C(1989945344), // XVPCNT_W
2186 UINT64_C(2011693056), // XVPERMI_D
2187 UINT64_C(2011955200), // XVPERMI_Q
2188 UINT64_C(2011430912), // XVPERMI_W
2189 UINT64_C(1971126272), // XVPERM_W
2190 UINT64_C(1964900352), // XVPICKEV_B
2191 UINT64_C(1964998656), // XVPICKEV_D
2192 UINT64_C(1964933120), // XVPICKEV_H
2193 UINT64_C(1964965888), // XVPICKEV_W
2194 UINT64_C(1965031424), // XVPICKOD_B
2195 UINT64_C(1965129728), // XVPICKOD_D
2196 UINT64_C(1965064192), // XVPICKOD_H
2197 UINT64_C(1965096960), // XVPICKOD_W
2198 UINT64_C(1995431936), // XVPICKVE2GR_D
2199 UINT64_C(1995694080), // XVPICKVE2GR_DU
2200 UINT64_C(1995423744), // XVPICKVE2GR_W
2201 UINT64_C(1995685888), // XVPICKVE2GR_WU
2202 UINT64_C(1996742656), // XVPICKVE_D
2203 UINT64_C(1996734464), // XVPICKVE_W
2204 UINT64_C(1995931648), // XVREPL128VEI_B
2205 UINT64_C(1995960320), // XVREPL128VEI_D
2206 UINT64_C(1995948032), // XVREPL128VEI_H
2207 UINT64_C(1995956224), // XVREPL128VEI_W
2208 UINT64_C(1990131712), // XVREPLGR2VR_B
2209 UINT64_C(1990134784), // XVREPLGR2VR_D
2210 UINT64_C(1990132736), // XVREPLGR2VR_H
2211 UINT64_C(1990133760), // XVREPLGR2VR_W
2212 UINT64_C(1996947456), // XVREPLVE0_B
2213 UINT64_C(1997004800), // XVREPLVE0_D
2214 UINT64_C(1996980224), // XVREPLVE0_H
2215 UINT64_C(1997008896), // XVREPLVE0_Q
2216 UINT64_C(1996996608), // XVREPLVE0_W
2217 UINT64_C(1965162496), // XVREPLVE_B
2218 UINT64_C(1965260800), // XVREPLVE_D
2219 UINT64_C(1965195264), // XVREPLVE_H
2220 UINT64_C(1965228032), // XVREPLVE_W
2221 UINT64_C(1990205440), // XVROTRI_B
2222 UINT64_C(1990262784), // XVROTRI_D
2223 UINT64_C(1990213632), // XVROTRI_H
2224 UINT64_C(1990230016), // XVROTRI_W
2225 UINT64_C(1961754624), // XVROTR_B
2226 UINT64_C(1961852928), // XVROTR_D
2227 UINT64_C(1961787392), // XVROTR_H
2228 UINT64_C(1961820160), // XVROTR_W
2229 UINT64_C(1950744576), // XVSADD_B
2230 UINT64_C(1951006720), // XVSADD_BU
2231 UINT64_C(1950842880), // XVSADD_D
2232 UINT64_C(1951105024), // XVSADD_DU
2233 UINT64_C(1950777344), // XVSADD_H
2234 UINT64_C(1951039488), // XVSADD_HU
2235 UINT64_C(1950810112), // XVSADD_W
2236 UINT64_C(1951072256), // XVSADD_WU
2237 UINT64_C(1998856192), // XVSAT_B
2238 UINT64_C(1999118336), // XVSAT_BU
2239 UINT64_C(1998913536), // XVSAT_D
2240 UINT64_C(1999175680), // XVSAT_DU
2241 UINT64_C(1998864384), // XVSAT_H
2242 UINT64_C(1999126528), // XVSAT_HU
2243 UINT64_C(1998880768), // XVSAT_W
2244 UINT64_C(1999142912), // XVSAT_WU
2245 UINT64_C(1988100096), // XVSEQI_B
2246 UINT64_C(1988198400), // XVSEQI_D
2247 UINT64_C(1988132864), // XVSEQI_H
2248 UINT64_C(1988165632), // XVSEQI_W
2249 UINT64_C(1946157056), // XVSEQ_B
2250 UINT64_C(1946255360), // XVSEQ_D
2251 UINT64_C(1946189824), // XVSEQ_H
2252 UINT64_C(1946222592), // XVSEQ_W
2253 UINT64_C(1989980160), // XVSETALLNEZ_B
2254 UINT64_C(1989983232), // XVSETALLNEZ_D
2255 UINT64_C(1989981184), // XVSETALLNEZ_H
2256 UINT64_C(1989982208), // XVSETALLNEZ_W
2257 UINT64_C(1989976064), // XVSETANYEQZ_B
2258 UINT64_C(1989979136), // XVSETANYEQZ_D
2259 UINT64_C(1989977088), // XVSETANYEQZ_H
2260 UINT64_C(1989978112), // XVSETANYEQZ_W
2261 UINT64_C(1989974016), // XVSETEQZ_V
2262 UINT64_C(1989975040), // XVSETNEZ_V
2263 UINT64_C(2005925888), // XVSHUF4I_B
2264 UINT64_C(2006712320), // XVSHUF4I_D
2265 UINT64_C(2006188032), // XVSHUF4I_H
2266 UINT64_C(2006450176), // XVSHUF4I_W
2267 UINT64_C(224395264), // XVSHUF_B
2268 UINT64_C(1971027968), // XVSHUF_D
2269 UINT64_C(1970962432), // XVSHUF_H
2270 UINT64_C(1970995200), // XVSHUF_W
2271 UINT64_C(1965948928), // XVSIGNCOV_B
2272 UINT64_C(1966047232), // XVSIGNCOV_D
2273 UINT64_C(1965981696), // XVSIGNCOV_H
2274 UINT64_C(1966014464), // XVSIGNCOV_W
2275 UINT64_C(1988231168), // XVSLEI_B
2276 UINT64_C(1988362240), // XVSLEI_BU
2277 UINT64_C(1988329472), // XVSLEI_D
2278 UINT64_C(1988460544), // XVSLEI_DU
2279 UINT64_C(1988263936), // XVSLEI_H
2280 UINT64_C(1988395008), // XVSLEI_HU
2281 UINT64_C(1988296704), // XVSLEI_W
2282 UINT64_C(1988427776), // XVSLEI_WU
2283 UINT64_C(1946288128), // XVSLE_B
2284 UINT64_C(1946419200), // XVSLE_BU
2285 UINT64_C(1946386432), // XVSLE_D
2286 UINT64_C(1946517504), // XVSLE_DU
2287 UINT64_C(1946320896), // XVSLE_H
2288 UINT64_C(1946451968), // XVSLE_HU
2289 UINT64_C(1946353664), // XVSLE_W
2290 UINT64_C(1946484736), // XVSLE_WU
2291 UINT64_C(1999380480), // XVSLLI_B
2292 UINT64_C(1999437824), // XVSLLI_D
2293 UINT64_C(1999388672), // XVSLLI_H
2294 UINT64_C(1999405056), // XVSLLI_W
2295 UINT64_C(1997307904), // XVSLLWIL_DU_WU
2296 UINT64_C(1997045760), // XVSLLWIL_D_W
2297 UINT64_C(1997283328), // XVSLLWIL_HU_BU
2298 UINT64_C(1997021184), // XVSLLWIL_H_B
2299 UINT64_C(1997291520), // XVSLLWIL_WU_HU
2300 UINT64_C(1997029376), // XVSLLWIL_W_H
2301 UINT64_C(1961361408), // XVSLL_B
2302 UINT64_C(1961459712), // XVSLL_D
2303 UINT64_C(1961394176), // XVSLL_H
2304 UINT64_C(1961426944), // XVSLL_W
2305 UINT64_C(1988493312), // XVSLTI_B
2306 UINT64_C(1988624384), // XVSLTI_BU
2307 UINT64_C(1988591616), // XVSLTI_D
2308 UINT64_C(1988722688), // XVSLTI_DU
2309 UINT64_C(1988526080), // XVSLTI_H
2310 UINT64_C(1988657152), // XVSLTI_HU
2311 UINT64_C(1988558848), // XVSLTI_W
2312 UINT64_C(1988689920), // XVSLTI_WU
2313 UINT64_C(1946550272), // XVSLT_B
2314 UINT64_C(1946681344), // XVSLT_BU
2315 UINT64_C(1946648576), // XVSLT_D
2316 UINT64_C(1946779648), // XVSLT_DU
2317 UINT64_C(1946583040), // XVSLT_H
2318 UINT64_C(1946714112), // XVSLT_HU
2319 UINT64_C(1946615808), // XVSLT_W
2320 UINT64_C(1946746880), // XVSLT_WU
2321 UINT64_C(1999904768), // XVSRAI_B
2322 UINT64_C(1999962112), // XVSRAI_D
2323 UINT64_C(1999912960), // XVSRAI_H
2324 UINT64_C(1999929344), // XVSRAI_W
2325 UINT64_C(2002272256), // XVSRANI_B_H
2326 UINT64_C(2002386944), // XVSRANI_D_Q
2327 UINT64_C(2002288640), // XVSRANI_H_W
2328 UINT64_C(2002321408), // XVSRANI_W_D
2329 UINT64_C(1962311680), // XVSRAN_B_H
2330 UINT64_C(1962344448), // XVSRAN_H_W
2331 UINT64_C(1962377216), // XVSRAN_W_D
2332 UINT64_C(1990729728), // XVSRARI_B
2333 UINT64_C(1990787072), // XVSRARI_D
2334 UINT64_C(1990737920), // XVSRARI_H
2335 UINT64_C(1990754304), // XVSRARI_W
2336 UINT64_C(2002534400), // XVSRARNI_B_H
2337 UINT64_C(2002649088), // XVSRARNI_D_Q
2338 UINT64_C(2002550784), // XVSRARNI_H_W
2339 UINT64_C(2002583552), // XVSRARNI_W_D
2340 UINT64_C(1962573824), // XVSRARN_B_H
2341 UINT64_C(1962606592), // XVSRARN_H_W
2342 UINT64_C(1962639360), // XVSRARN_W_D
2343 UINT64_C(1962016768), // XVSRAR_B
2344 UINT64_C(1962115072), // XVSRAR_D
2345 UINT64_C(1962049536), // XVSRAR_H
2346 UINT64_C(1962082304), // XVSRAR_W
2347 UINT64_C(1961623552), // XVSRA_B
2348 UINT64_C(1961721856), // XVSRA_D
2349 UINT64_C(1961656320), // XVSRA_H
2350 UINT64_C(1961689088), // XVSRA_W
2351 UINT64_C(1999642624), // XVSRLI_B
2352 UINT64_C(1999699968), // XVSRLI_D
2353 UINT64_C(1999650816), // XVSRLI_H
2354 UINT64_C(1999667200), // XVSRLI_W
2355 UINT64_C(2000699392), // XVSRLNI_B_H
2356 UINT64_C(2000814080), // XVSRLNI_D_Q
2357 UINT64_C(2000715776), // XVSRLNI_H_W
2358 UINT64_C(2000748544), // XVSRLNI_W_D
2359 UINT64_C(1962180608), // XVSRLN_B_H
2360 UINT64_C(1962213376), // XVSRLN_H_W
2361 UINT64_C(1962246144), // XVSRLN_W_D
2362 UINT64_C(1990467584), // XVSRLRI_B
2363 UINT64_C(1990524928), // XVSRLRI_D
2364 UINT64_C(1990475776), // XVSRLRI_H
2365 UINT64_C(1990492160), // XVSRLRI_W
2366 UINT64_C(2000961536), // XVSRLRNI_B_H
2367 UINT64_C(2001076224), // XVSRLRNI_D_Q
2368 UINT64_C(2000977920), // XVSRLRNI_H_W
2369 UINT64_C(2001010688), // XVSRLRNI_W_D
2370 UINT64_C(1962442752), // XVSRLRN_B_H
2371 UINT64_C(1962475520), // XVSRLRN_H_W
2372 UINT64_C(1962508288), // XVSRLRN_W_D
2373 UINT64_C(1961885696), // XVSRLR_B
2374 UINT64_C(1961984000), // XVSRLR_D
2375 UINT64_C(1961918464), // XVSRLR_H
2376 UINT64_C(1961951232), // XVSRLR_W
2377 UINT64_C(1961492480), // XVSRL_B
2378 UINT64_C(1961590784), // XVSRL_D
2379 UINT64_C(1961525248), // XVSRL_H
2380 UINT64_C(1961558016), // XVSRL_W
2381 UINT64_C(2003058688), // XVSSRANI_BU_H
2382 UINT64_C(2002796544), // XVSSRANI_B_H
2383 UINT64_C(2003173376), // XVSSRANI_DU_Q
2384 UINT64_C(2002911232), // XVSSRANI_D_Q
2385 UINT64_C(2003075072), // XVSSRANI_HU_W
2386 UINT64_C(2002812928), // XVSSRANI_H_W
2387 UINT64_C(2003107840), // XVSSRANI_WU_D
2388 UINT64_C(2002845696), // XVSSRANI_W_D
2389 UINT64_C(1963360256), // XVSSRAN_BU_H
2390 UINT64_C(1962835968), // XVSSRAN_B_H
2391 UINT64_C(1963393024), // XVSSRAN_HU_W
2392 UINT64_C(1962868736), // XVSSRAN_H_W
2393 UINT64_C(1963425792), // XVSSRAN_WU_D
2394 UINT64_C(1962901504), // XVSSRAN_W_D
2395 UINT64_C(2003582976), // XVSSRARNI_BU_H
2396 UINT64_C(2003320832), // XVSSRARNI_B_H
2397 UINT64_C(2003697664), // XVSSRARNI_DU_Q
2398 UINT64_C(2003435520), // XVSSRARNI_D_Q
2399 UINT64_C(2003599360), // XVSSRARNI_HU_W
2400 UINT64_C(2003337216), // XVSSRARNI_H_W
2401 UINT64_C(2003632128), // XVSSRARNI_WU_D
2402 UINT64_C(2003369984), // XVSSRARNI_W_D
2403 UINT64_C(1963622400), // XVSSRARN_BU_H
2404 UINT64_C(1963098112), // XVSSRARN_B_H
2405 UINT64_C(1963655168), // XVSSRARN_HU_W
2406 UINT64_C(1963130880), // XVSSRARN_H_W
2407 UINT64_C(1963687936), // XVSSRARN_WU_D
2408 UINT64_C(1963163648), // XVSSRARN_W_D
2409 UINT64_C(2001485824), // XVSSRLNI_BU_H
2410 UINT64_C(2001223680), // XVSSRLNI_B_H
2411 UINT64_C(2001600512), // XVSSRLNI_DU_Q
2412 UINT64_C(2001338368), // XVSSRLNI_D_Q
2413 UINT64_C(2001502208), // XVSSRLNI_HU_W
2414 UINT64_C(2001240064), // XVSSRLNI_H_W
2415 UINT64_C(2001534976), // XVSSRLNI_WU_D
2416 UINT64_C(2001272832), // XVSSRLNI_W_D
2417 UINT64_C(1963229184), // XVSSRLN_BU_H
2418 UINT64_C(1962704896), // XVSSRLN_B_H
2419 UINT64_C(1963261952), // XVSSRLN_HU_W
2420 UINT64_C(1962737664), // XVSSRLN_H_W
2421 UINT64_C(1963294720), // XVSSRLN_WU_D
2422 UINT64_C(1962770432), // XVSSRLN_W_D
2423 UINT64_C(2002010112), // XVSSRLRNI_BU_H
2424 UINT64_C(2001747968), // XVSSRLRNI_B_H
2425 UINT64_C(2002124800), // XVSSRLRNI_DU_Q
2426 UINT64_C(2001862656), // XVSSRLRNI_D_Q
2427 UINT64_C(2002026496), // XVSSRLRNI_HU_W
2428 UINT64_C(2001764352), // XVSSRLRNI_H_W
2429 UINT64_C(2002059264), // XVSSRLRNI_WU_D
2430 UINT64_C(2001797120), // XVSSRLRNI_W_D
2431 UINT64_C(1963491328), // XVSSRLRN_BU_H
2432 UINT64_C(1962967040), // XVSSRLRN_B_H
2433 UINT64_C(1963524096), // XVSSRLRN_HU_W
2434 UINT64_C(1962999808), // XVSSRLRN_H_W
2435 UINT64_C(1963556864), // XVSSRLRN_WU_D
2436 UINT64_C(1963032576), // XVSSRLRN_W_D
2437 UINT64_C(1950875648), // XVSSUB_B
2438 UINT64_C(1951137792), // XVSSUB_BU
2439 UINT64_C(1950973952), // XVSSUB_D
2440 UINT64_C(1951236096), // XVSSUB_DU
2441 UINT64_C(1950908416), // XVSSUB_H
2442 UINT64_C(1951170560), // XVSSUB_HU
2443 UINT64_C(1950941184), // XVSSUB_W
2444 UINT64_C(1951203328), // XVSSUB_WU
2445 UINT64_C(750780416), // XVST
2446 UINT64_C(864026624), // XVSTELM_B
2447 UINT64_C(856686592), // XVSTELM_D
2448 UINT64_C(859832320), // XVSTELM_H
2449 UINT64_C(857735168), // XVSTELM_W
2450 UINT64_C(944504832), // XVSTX
2451 UINT64_C(1988886528), // XVSUBI_BU
2452 UINT64_C(1988984832), // XVSUBI_DU
2453 UINT64_C(1988919296), // XVSUBI_HU
2454 UINT64_C(1988952064), // XVSUBI_WU
2455 UINT64_C(1948319744), // XVSUBWEV_D_W
2456 UINT64_C(1949368320), // XVSUBWEV_D_WU
2457 UINT64_C(1948254208), // XVSUBWEV_H_B
2458 UINT64_C(1949302784), // XVSUBWEV_H_BU
2459 UINT64_C(1948352512), // XVSUBWEV_Q_D
2460 UINT64_C(1949401088), // XVSUBWEV_Q_DU
2461 UINT64_C(1948286976), // XVSUBWEV_W_H
2462 UINT64_C(1949335552), // XVSUBWEV_W_HU
2463 UINT64_C(1948581888), // XVSUBWOD_D_W
2464 UINT64_C(1949630464), // XVSUBWOD_D_WU
2465 UINT64_C(1948516352), // XVSUBWOD_H_B
2466 UINT64_C(1949564928), // XVSUBWOD_H_BU
2467 UINT64_C(1948614656), // XVSUBWOD_Q_D
2468 UINT64_C(1949663232), // XVSUBWOD_Q_DU
2469 UINT64_C(1948549120), // XVSUBWOD_W_H
2470 UINT64_C(1949597696), // XVSUBWOD_W_HU
2471 UINT64_C(1946943488), // XVSUB_B
2472 UINT64_C(1947041792), // XVSUB_D
2473 UINT64_C(1946976256), // XVSUB_H
2474 UINT64_C(1965916160), // XVSUB_Q
2475 UINT64_C(1947009024), // XVSUB_W
2476 UINT64_C(2010644480), // XVXORI_B
2477 UINT64_C(1965490176), // XVXOR_V
2478 UINT64_C(0)
2479 };
2480 const unsigned opcode = MI.getOpcode();
2481 uint64_t Value = InstBits[opcode];
2482 uint64_t op = 0;
2483 (void)op; // suppress warning
2484 switch (opcode) {
2485 case LoongArch::ERTN:
2486 case LoongArch::GTLBFLUSH:
2487 case LoongArch::TLBCLR:
2488 case LoongArch::TLBFILL:
2489 case LoongArch::TLBFLUSH:
2490 case LoongArch::TLBRD:
2491 case LoongArch::TLBSRCH:
2492 case LoongArch::TLBWR:
2493 case LoongArch::X86CLRTM:
2494 case LoongArch::X86DECTOP:
2495 case LoongArch::X86INCTOP:
2496 case LoongArch::X86SETTM: {
2497 break;
2498 }
2499 case LoongArch::FSEL_xD:
2500 case LoongArch::FSEL_xS: {
2501 // op: ca
2502 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
2503 op &= UINT64_C(7);
2504 op <<= 15;
2505 Value |= op;
2506 // op: fk
2507 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
2508 op &= UINT64_C(31);
2509 op <<= 10;
2510 Value |= op;
2511 // op: fj
2512 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2513 op &= UINT64_C(31);
2514 op <<= 5;
2515 Value |= op;
2516 // op: fd
2517 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2518 op &= UINT64_C(31);
2519 Value |= op;
2520 break;
2521 }
2522 case LoongArch::SET_CFR_FALSE:
2523 case LoongArch::SET_CFR_TRUE: {
2524 // op: cd
2525 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2526 op &= UINT64_C(7);
2527 Value |= op;
2528 break;
2529 }
2530 case LoongArch::CSRRD:
2531 case LoongArch::GCSRRD: {
2532 // op: csr_num
2533 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2534 op &= UINT64_C(16383);
2535 op <<= 10;
2536 Value |= op;
2537 // op: rd
2538 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2539 op &= UINT64_C(31);
2540 Value |= op;
2541 break;
2542 }
2543 case LoongArch::CSRWR:
2544 case LoongArch::GCSRWR: {
2545 // op: csr_num
2546 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
2547 op &= UINT64_C(16383);
2548 op <<= 10;
2549 Value |= op;
2550 // op: rd
2551 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2552 op &= UINT64_C(31);
2553 Value |= op;
2554 break;
2555 }
2556 case LoongArch::CSRXCHG:
2557 case LoongArch::GCSRXCHG: {
2558 // op: csr_num
2559 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
2560 op &= UINT64_C(16383);
2561 op <<= 10;
2562 Value |= op;
2563 // op: rj
2564 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
2565 op &= UINT64_C(31);
2566 op <<= 5;
2567 Value |= op;
2568 // op: rd
2569 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2570 op &= UINT64_C(31);
2571 Value |= op;
2572 break;
2573 }
2574 case LoongArch::FMADD_D:
2575 case LoongArch::FMADD_S:
2576 case LoongArch::FMSUB_D:
2577 case LoongArch::FMSUB_S:
2578 case LoongArch::FNMADD_D:
2579 case LoongArch::FNMADD_S:
2580 case LoongArch::FNMSUB_D:
2581 case LoongArch::FNMSUB_S: {
2582 // op: fa
2583 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
2584 op &= UINT64_C(31);
2585 op <<= 15;
2586 Value |= op;
2587 // op: fk
2588 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
2589 op &= UINT64_C(31);
2590 op <<= 10;
2591 Value |= op;
2592 // op: fj
2593 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2594 op &= UINT64_C(31);
2595 op <<= 5;
2596 Value |= op;
2597 // op: fd
2598 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2599 op &= UINT64_C(31);
2600 Value |= op;
2601 break;
2602 }
2603 case LoongArch::FABS_D:
2604 case LoongArch::FABS_S:
2605 case LoongArch::FCLASS_D:
2606 case LoongArch::FCLASS_S:
2607 case LoongArch::FCVT_D_S:
2608 case LoongArch::FCVT_LD_D:
2609 case LoongArch::FCVT_S_D:
2610 case LoongArch::FCVT_UD_D:
2611 case LoongArch::FFINT_D_L:
2612 case LoongArch::FFINT_D_W:
2613 case LoongArch::FFINT_S_L:
2614 case LoongArch::FFINT_S_W:
2615 case LoongArch::FLOGB_D:
2616 case LoongArch::FLOGB_S:
2617 case LoongArch::FNEG_D:
2618 case LoongArch::FNEG_S:
2619 case LoongArch::FRECIPE_D:
2620 case LoongArch::FRECIPE_S:
2621 case LoongArch::FRECIP_D:
2622 case LoongArch::FRECIP_S:
2623 case LoongArch::FRINT_D:
2624 case LoongArch::FRINT_S:
2625 case LoongArch::FRSQRTE_D:
2626 case LoongArch::FRSQRTE_S:
2627 case LoongArch::FRSQRT_D:
2628 case LoongArch::FRSQRT_S:
2629 case LoongArch::FSQRT_D:
2630 case LoongArch::FSQRT_S:
2631 case LoongArch::FTINTRM_L_D:
2632 case LoongArch::FTINTRM_L_S:
2633 case LoongArch::FTINTRM_W_D:
2634 case LoongArch::FTINTRM_W_S:
2635 case LoongArch::FTINTRNE_L_D:
2636 case LoongArch::FTINTRNE_L_S:
2637 case LoongArch::FTINTRNE_W_D:
2638 case LoongArch::FTINTRNE_W_S:
2639 case LoongArch::FTINTRP_L_D:
2640 case LoongArch::FTINTRP_L_S:
2641 case LoongArch::FTINTRP_W_D:
2642 case LoongArch::FTINTRP_W_S:
2643 case LoongArch::FTINTRZ_L_D:
2644 case LoongArch::FTINTRZ_L_S:
2645 case LoongArch::FTINTRZ_W_D:
2646 case LoongArch::FTINTRZ_W_S:
2647 case LoongArch::FTINT_L_D:
2648 case LoongArch::FTINT_L_S:
2649 case LoongArch::FTINT_W_D:
2650 case LoongArch::FTINT_W_S: {
2651 // op: fj
2652 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2653 op &= UINT64_C(31);
2654 op <<= 5;
2655 Value |= op;
2656 // op: fd
2657 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2658 op &= UINT64_C(31);
2659 Value |= op;
2660 break;
2661 }
2662 case LoongArch::FCMP_CAF_D:
2663 case LoongArch::FCMP_CAF_S:
2664 case LoongArch::FCMP_CEQ_D:
2665 case LoongArch::FCMP_CEQ_S:
2666 case LoongArch::FCMP_CLE_D:
2667 case LoongArch::FCMP_CLE_S:
2668 case LoongArch::FCMP_CLT_D:
2669 case LoongArch::FCMP_CLT_S:
2670 case LoongArch::FCMP_CNE_D:
2671 case LoongArch::FCMP_CNE_S:
2672 case LoongArch::FCMP_COR_D:
2673 case LoongArch::FCMP_COR_S:
2674 case LoongArch::FCMP_CUEQ_D:
2675 case LoongArch::FCMP_CUEQ_S:
2676 case LoongArch::FCMP_CULE_D:
2677 case LoongArch::FCMP_CULE_S:
2678 case LoongArch::FCMP_CULT_D:
2679 case LoongArch::FCMP_CULT_S:
2680 case LoongArch::FCMP_CUNE_D:
2681 case LoongArch::FCMP_CUNE_S:
2682 case LoongArch::FCMP_CUN_D:
2683 case LoongArch::FCMP_CUN_S:
2684 case LoongArch::FCMP_SAF_D:
2685 case LoongArch::FCMP_SAF_S:
2686 case LoongArch::FCMP_SEQ_D:
2687 case LoongArch::FCMP_SEQ_S:
2688 case LoongArch::FCMP_SLE_D:
2689 case LoongArch::FCMP_SLE_S:
2690 case LoongArch::FCMP_SLT_D:
2691 case LoongArch::FCMP_SLT_S:
2692 case LoongArch::FCMP_SNE_D:
2693 case LoongArch::FCMP_SNE_S:
2694 case LoongArch::FCMP_SOR_D:
2695 case LoongArch::FCMP_SOR_S:
2696 case LoongArch::FCMP_SUEQ_D:
2697 case LoongArch::FCMP_SUEQ_S:
2698 case LoongArch::FCMP_SULE_D:
2699 case LoongArch::FCMP_SULE_S:
2700 case LoongArch::FCMP_SULT_D:
2701 case LoongArch::FCMP_SULT_S:
2702 case LoongArch::FCMP_SUNE_D:
2703 case LoongArch::FCMP_SUNE_S:
2704 case LoongArch::FCMP_SUN_D:
2705 case LoongArch::FCMP_SUN_S: {
2706 // op: fk
2707 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
2708 op &= UINT64_C(31);
2709 op <<= 10;
2710 Value |= op;
2711 // op: fj
2712 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2713 op &= UINT64_C(31);
2714 op <<= 5;
2715 Value |= op;
2716 // op: cd
2717 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2718 op &= UINT64_C(7);
2719 Value |= op;
2720 break;
2721 }
2722 case LoongArch::FADD_D:
2723 case LoongArch::FADD_S:
2724 case LoongArch::FCOPYSIGN_D:
2725 case LoongArch::FCOPYSIGN_S:
2726 case LoongArch::FCVT_D_LD:
2727 case LoongArch::FDIV_D:
2728 case LoongArch::FDIV_S:
2729 case LoongArch::FMAXA_D:
2730 case LoongArch::FMAXA_S:
2731 case LoongArch::FMAX_D:
2732 case LoongArch::FMAX_S:
2733 case LoongArch::FMINA_D:
2734 case LoongArch::FMINA_S:
2735 case LoongArch::FMIN_D:
2736 case LoongArch::FMIN_S:
2737 case LoongArch::FMUL_D:
2738 case LoongArch::FMUL_S:
2739 case LoongArch::FSCALEB_D:
2740 case LoongArch::FSCALEB_S:
2741 case LoongArch::FSUB_D:
2742 case LoongArch::FSUB_S: {
2743 // op: fk
2744 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
2745 op &= UINT64_C(31);
2746 op <<= 10;
2747 Value |= op;
2748 // op: fj
2749 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2750 op &= UINT64_C(31);
2751 op <<= 5;
2752 Value |= op;
2753 // op: fd
2754 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2755 op &= UINT64_C(31);
2756 Value |= op;
2757 break;
2758 }
2759 case LoongArch::VPICKVE2GR_D:
2760 case LoongArch::VPICKVE2GR_DU: {
2761 // op: imm1
2762 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
2763 op &= UINT64_C(1);
2764 op <<= 10;
2765 Value |= op;
2766 // op: vj
2767 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2768 op &= UINT64_C(31);
2769 op <<= 5;
2770 Value |= op;
2771 // op: rd
2772 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2773 op &= UINT64_C(31);
2774 Value |= op;
2775 break;
2776 }
2777 case LoongArch::VREPLVEI_D: {
2778 // op: imm1
2779 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
2780 op &= UINT64_C(1);
2781 op <<= 10;
2782 Value |= op;
2783 // op: vj
2784 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2785 op &= UINT64_C(31);
2786 op <<= 5;
2787 Value |= op;
2788 // op: vd
2789 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2790 op &= UINT64_C(31);
2791 Value |= op;
2792 break;
2793 }
2794 case LoongArch::XVREPL128VEI_D: {
2795 // op: imm1
2796 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
2797 op &= UINT64_C(1);
2798 op <<= 10;
2799 Value |= op;
2800 // op: xj
2801 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2802 op &= UINT64_C(31);
2803 op <<= 5;
2804 Value |= op;
2805 // op: xd
2806 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2807 op &= UINT64_C(31);
2808 Value |= op;
2809 break;
2810 }
2811 case LoongArch::VINSGR2VR_D: {
2812 // op: imm1
2813 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
2814 op &= UINT64_C(1);
2815 op <<= 10;
2816 Value |= op;
2817 // op: rj
2818 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
2819 op &= UINT64_C(31);
2820 op <<= 5;
2821 Value |= op;
2822 // op: vd
2823 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2824 op &= UINT64_C(31);
2825 Value |= op;
2826 break;
2827 }
2828 case LoongArch::VSTELM_D: {
2829 // op: imm1
2830 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
2831 op &= UINT64_C(1);
2832 op <<= 18;
2833 Value |= op;
2834 // op: imm8
2835 op = getImmOpValueAsr<3>(MI, OpNo: 2, Fixups, STI);
2836 op &= UINT64_C(255);
2837 op <<= 10;
2838 Value |= op;
2839 // op: rj
2840 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2841 op &= UINT64_C(31);
2842 op <<= 5;
2843 Value |= op;
2844 // op: vd
2845 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2846 op &= UINT64_C(31);
2847 Value |= op;
2848 break;
2849 }
2850 case LoongArch::VLDREPL_W: {
2851 // op: imm10
2852 op = getImmOpValueAsr<2>(MI, OpNo: 2, Fixups, STI);
2853 op &= UINT64_C(1023);
2854 op <<= 10;
2855 Value |= op;
2856 // op: rj
2857 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2858 op &= UINT64_C(31);
2859 op <<= 5;
2860 Value |= op;
2861 // op: vd
2862 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2863 op &= UINT64_C(31);
2864 Value |= op;
2865 break;
2866 }
2867 case LoongArch::XVLDREPL_W: {
2868 // op: imm10
2869 op = getImmOpValueAsr<2>(MI, OpNo: 2, Fixups, STI);
2870 op &= UINT64_C(1023);
2871 op <<= 10;
2872 Value |= op;
2873 // op: rj
2874 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2875 op &= UINT64_C(31);
2876 op <<= 5;
2877 Value |= op;
2878 // op: xd
2879 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2880 op &= UINT64_C(31);
2881 Value |= op;
2882 break;
2883 }
2884 case LoongArch::VLDREPL_H: {
2885 // op: imm11
2886 op = getImmOpValueAsr<1>(MI, OpNo: 2, Fixups, STI);
2887 op &= UINT64_C(2047);
2888 op <<= 10;
2889 Value |= op;
2890 // op: rj
2891 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2892 op &= UINT64_C(31);
2893 op <<= 5;
2894 Value |= op;
2895 // op: vd
2896 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2897 op &= UINT64_C(31);
2898 Value |= op;
2899 break;
2900 }
2901 case LoongArch::XVLDREPL_H: {
2902 // op: imm11
2903 op = getImmOpValueAsr<1>(MI, OpNo: 2, Fixups, STI);
2904 op &= UINT64_C(2047);
2905 op <<= 10;
2906 Value |= op;
2907 // op: rj
2908 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2909 op &= UINT64_C(31);
2910 op <<= 5;
2911 Value |= op;
2912 // op: xd
2913 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2914 op &= UINT64_C(31);
2915 Value |= op;
2916 break;
2917 }
2918 case LoongArch::FLD_D:
2919 case LoongArch::FLD_S:
2920 case LoongArch::FST_D:
2921 case LoongArch::FST_S: {
2922 // op: imm12
2923 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
2924 op &= UINT64_C(4095);
2925 op <<= 10;
2926 Value |= op;
2927 // op: rj
2928 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2929 op &= UINT64_C(31);
2930 op <<= 5;
2931 Value |= op;
2932 // op: fd
2933 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2934 op &= UINT64_C(31);
2935 Value |= op;
2936 break;
2937 }
2938 case LoongArch::PRELD: {
2939 // op: imm12
2940 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
2941 op &= UINT64_C(4095);
2942 op <<= 10;
2943 Value |= op;
2944 // op: rj
2945 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2946 op &= UINT64_C(31);
2947 op <<= 5;
2948 Value |= op;
2949 // op: imm5
2950 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2951 op &= UINT64_C(31);
2952 Value |= op;
2953 break;
2954 }
2955 case LoongArch::CACOP: {
2956 // op: imm12
2957 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
2958 op &= UINT64_C(4095);
2959 op <<= 10;
2960 Value |= op;
2961 // op: rj
2962 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2963 op &= UINT64_C(31);
2964 op <<= 5;
2965 Value |= op;
2966 // op: op
2967 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2968 op &= UINT64_C(31);
2969 Value |= op;
2970 break;
2971 }
2972 case LoongArch::ADDI_D:
2973 case LoongArch::ADDI_W:
2974 case LoongArch::ANDI:
2975 case LoongArch::LDL_D:
2976 case LoongArch::LDL_W:
2977 case LoongArch::LDR_D:
2978 case LoongArch::LDR_W:
2979 case LoongArch::LD_B:
2980 case LoongArch::LD_BU:
2981 case LoongArch::LD_D:
2982 case LoongArch::LD_H:
2983 case LoongArch::LD_HU:
2984 case LoongArch::LD_W:
2985 case LoongArch::LD_WU:
2986 case LoongArch::LU52I_D:
2987 case LoongArch::ORI:
2988 case LoongArch::SLTI:
2989 case LoongArch::SLTUI:
2990 case LoongArch::STL_D:
2991 case LoongArch::STL_W:
2992 case LoongArch::STR_D:
2993 case LoongArch::STR_W:
2994 case LoongArch::ST_B:
2995 case LoongArch::ST_D:
2996 case LoongArch::ST_H:
2997 case LoongArch::ST_W:
2998 case LoongArch::XORI: {
2999 // op: imm12
3000 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3001 op &= UINT64_C(4095);
3002 op <<= 10;
3003 Value |= op;
3004 // op: rj
3005 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3006 op &= UINT64_C(31);
3007 op <<= 5;
3008 Value |= op;
3009 // op: rd
3010 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3011 op &= UINT64_C(31);
3012 Value |= op;
3013 break;
3014 }
3015 case LoongArch::VLD:
3016 case LoongArch::VLDREPL_B:
3017 case LoongArch::VST: {
3018 // op: imm12
3019 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3020 op &= UINT64_C(4095);
3021 op <<= 10;
3022 Value |= op;
3023 // op: rj
3024 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3025 op &= UINT64_C(31);
3026 op <<= 5;
3027 Value |= op;
3028 // op: vd
3029 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3030 op &= UINT64_C(31);
3031 Value |= op;
3032 break;
3033 }
3034 case LoongArch::XVLD:
3035 case LoongArch::XVLDREPL_B:
3036 case LoongArch::XVST: {
3037 // op: imm12
3038 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3039 op &= UINT64_C(4095);
3040 op <<= 10;
3041 Value |= op;
3042 // op: rj
3043 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3044 op &= UINT64_C(31);
3045 op <<= 5;
3046 Value |= op;
3047 // op: xd
3048 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3049 op &= UINT64_C(31);
3050 Value |= op;
3051 break;
3052 }
3053 case LoongArch::VLDI: {
3054 // op: imm13
3055 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3056 op &= UINT64_C(8191);
3057 op <<= 5;
3058 Value |= op;
3059 // op: vd
3060 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3061 op &= UINT64_C(31);
3062 Value |= op;
3063 break;
3064 }
3065 case LoongArch::XVLDI: {
3066 // op: imm13
3067 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3068 op &= UINT64_C(8191);
3069 op <<= 5;
3070 Value |= op;
3071 // op: xd
3072 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3073 op &= UINT64_C(31);
3074 Value |= op;
3075 break;
3076 }
3077 case LoongArch::LDPTR_D:
3078 case LoongArch::LDPTR_W:
3079 case LoongArch::LL_D:
3080 case LoongArch::LL_W:
3081 case LoongArch::STPTR_D:
3082 case LoongArch::STPTR_W: {
3083 // op: imm14
3084 op = getImmOpValueAsr<2>(MI, OpNo: 2, Fixups, STI);
3085 op &= UINT64_C(16383);
3086 op <<= 10;
3087 Value |= op;
3088 // op: rj
3089 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3090 op &= UINT64_C(31);
3091 op <<= 5;
3092 Value |= op;
3093 // op: rd
3094 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3095 op &= UINT64_C(31);
3096 Value |= op;
3097 break;
3098 }
3099 case LoongArch::SC_D:
3100 case LoongArch::SC_W: {
3101 // op: imm14
3102 op = getImmOpValueAsr<2>(MI, OpNo: 3, Fixups, STI);
3103 op &= UINT64_C(16383);
3104 op <<= 10;
3105 Value |= op;
3106 // op: rj
3107 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3108 op &= UINT64_C(31);
3109 op <<= 5;
3110 Value |= op;
3111 // op: rd
3112 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3113 op &= UINT64_C(31);
3114 Value |= op;
3115 break;
3116 }
3117 case LoongArch::BREAK:
3118 case LoongArch::DBAR:
3119 case LoongArch::DBCL:
3120 case LoongArch::HVCL:
3121 case LoongArch::IBAR:
3122 case LoongArch::IDLE:
3123 case LoongArch::SYSCALL: {
3124 // op: imm15
3125 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3126 op &= UINT64_C(32767);
3127 Value |= op;
3128 break;
3129 }
3130 case LoongArch::BEQ:
3131 case LoongArch::BGE:
3132 case LoongArch::BGEU:
3133 case LoongArch::BLT:
3134 case LoongArch::BLTU:
3135 case LoongArch::BNE: {
3136 // op: imm16
3137 op = getImmOpValueAsr<2>(MI, OpNo: 2, Fixups, STI);
3138 op &= UINT64_C(65535);
3139 op <<= 10;
3140 Value |= op;
3141 // op: rj
3142 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3143 op &= UINT64_C(31);
3144 op <<= 5;
3145 Value |= op;
3146 // op: rd
3147 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3148 op &= UINT64_C(31);
3149 Value |= op;
3150 break;
3151 }
3152 case LoongArch::JIRL: {
3153 // op: imm16
3154 op = getImmOpValueAsr<2>(MI, OpNo: 2, Fixups, STI);
3155 op &= UINT64_C(65535);
3156 op <<= 10;
3157 Value |= op;
3158 // op: rj
3159 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3160 op &= UINT64_C(31);
3161 op <<= 5;
3162 Value |= op;
3163 // op: rd
3164 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3165 op &= UINT64_C(31);
3166 Value |= op;
3167 break;
3168 }
3169 case LoongArch::ADDU16I_D: {
3170 // op: imm16
3171 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3172 op &= UINT64_C(65535);
3173 op <<= 10;
3174 Value |= op;
3175 // op: rj
3176 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3177 op &= UINT64_C(31);
3178 op <<= 5;
3179 Value |= op;
3180 // op: rd
3181 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3182 op &= UINT64_C(31);
3183 Value |= op;
3184 break;
3185 }
3186 case LoongArch::ALSL_D:
3187 case LoongArch::ALSL_W:
3188 case LoongArch::ALSL_WU: {
3189 // op: imm2
3190 op = getImmOpValueSub1(MI, OpNo: 3, Fixups, STI);
3191 op &= UINT64_C(3);
3192 op <<= 15;
3193 Value |= op;
3194 // op: rk
3195 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3196 op &= UINT64_C(31);
3197 op <<= 10;
3198 Value |= op;
3199 // op: rj
3200 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3201 op &= UINT64_C(31);
3202 op <<= 5;
3203 Value |= op;
3204 // op: rd
3205 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3206 op &= UINT64_C(31);
3207 Value |= op;
3208 break;
3209 }
3210 case LoongArch::VPICKVE2GR_W:
3211 case LoongArch::VPICKVE2GR_WU: {
3212 // op: imm2
3213 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3214 op &= UINT64_C(3);
3215 op <<= 10;
3216 Value |= op;
3217 // op: vj
3218 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3219 op &= UINT64_C(31);
3220 op <<= 5;
3221 Value |= op;
3222 // op: rd
3223 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3224 op &= UINT64_C(31);
3225 Value |= op;
3226 break;
3227 }
3228 case LoongArch::VREPLVEI_W: {
3229 // op: imm2
3230 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3231 op &= UINT64_C(3);
3232 op <<= 10;
3233 Value |= op;
3234 // op: vj
3235 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3236 op &= UINT64_C(31);
3237 op <<= 5;
3238 Value |= op;
3239 // op: vd
3240 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3241 op &= UINT64_C(31);
3242 Value |= op;
3243 break;
3244 }
3245 case LoongArch::XVPICKVE2GR_D:
3246 case LoongArch::XVPICKVE2GR_DU: {
3247 // op: imm2
3248 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3249 op &= UINT64_C(3);
3250 op <<= 10;
3251 Value |= op;
3252 // op: xj
3253 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3254 op &= UINT64_C(31);
3255 op <<= 5;
3256 Value |= op;
3257 // op: rd
3258 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3259 op &= UINT64_C(31);
3260 Value |= op;
3261 break;
3262 }
3263 case LoongArch::XVPICKVE_D:
3264 case LoongArch::XVREPL128VEI_W: {
3265 // op: imm2
3266 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3267 op &= UINT64_C(3);
3268 op <<= 10;
3269 Value |= op;
3270 // op: xj
3271 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3272 op &= UINT64_C(31);
3273 op <<= 5;
3274 Value |= op;
3275 // op: xd
3276 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3277 op &= UINT64_C(31);
3278 Value |= op;
3279 break;
3280 }
3281 case LoongArch::VINSGR2VR_W: {
3282 // op: imm2
3283 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
3284 op &= UINT64_C(3);
3285 op <<= 10;
3286 Value |= op;
3287 // op: rj
3288 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3289 op &= UINT64_C(31);
3290 op <<= 5;
3291 Value |= op;
3292 // op: vd
3293 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3294 op &= UINT64_C(31);
3295 Value |= op;
3296 break;
3297 }
3298 case LoongArch::XVINSGR2VR_D: {
3299 // op: imm2
3300 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
3301 op &= UINT64_C(3);
3302 op <<= 10;
3303 Value |= op;
3304 // op: rj
3305 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3306 op &= UINT64_C(31);
3307 op <<= 5;
3308 Value |= op;
3309 // op: xd
3310 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3311 op &= UINT64_C(31);
3312 Value |= op;
3313 break;
3314 }
3315 case LoongArch::XVINSVE0_D: {
3316 // op: imm2
3317 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
3318 op &= UINT64_C(3);
3319 op <<= 10;
3320 Value |= op;
3321 // op: xj
3322 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3323 op &= UINT64_C(31);
3324 op <<= 5;
3325 Value |= op;
3326 // op: xd
3327 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3328 op &= UINT64_C(31);
3329 Value |= op;
3330 break;
3331 }
3332 case LoongArch::BYTEPICK_W: {
3333 // op: imm2
3334 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
3335 op &= UINT64_C(3);
3336 op <<= 15;
3337 Value |= op;
3338 // op: rk
3339 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3340 op &= UINT64_C(31);
3341 op <<= 10;
3342 Value |= op;
3343 // op: rj
3344 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3345 op &= UINT64_C(31);
3346 op <<= 5;
3347 Value |= op;
3348 // op: rd
3349 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3350 op &= UINT64_C(31);
3351 Value |= op;
3352 break;
3353 }
3354 case LoongArch::VSTELM_W: {
3355 // op: imm2
3356 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
3357 op &= UINT64_C(3);
3358 op <<= 18;
3359 Value |= op;
3360 // op: imm8
3361 op = getImmOpValueAsr<2>(MI, OpNo: 2, Fixups, STI);
3362 op &= UINT64_C(255);
3363 op <<= 10;
3364 Value |= op;
3365 // op: rj
3366 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3367 op &= UINT64_C(31);
3368 op <<= 5;
3369 Value |= op;
3370 // op: vd
3371 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3372 op &= UINT64_C(31);
3373 Value |= op;
3374 break;
3375 }
3376 case LoongArch::XVSTELM_D: {
3377 // op: imm2
3378 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
3379 op &= UINT64_C(3);
3380 op <<= 18;
3381 Value |= op;
3382 // op: imm8
3383 op = getImmOpValueAsr<3>(MI, OpNo: 2, Fixups, STI);
3384 op &= UINT64_C(255);
3385 op <<= 10;
3386 Value |= op;
3387 // op: rj
3388 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3389 op &= UINT64_C(31);
3390 op <<= 5;
3391 Value |= op;
3392 // op: xd
3393 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3394 op &= UINT64_C(31);
3395 Value |= op;
3396 break;
3397 }
3398 case LoongArch::LU12I_W:
3399 case LoongArch::PCADDI:
3400 case LoongArch::PCADDU12I:
3401 case LoongArch::PCADDU18I:
3402 case LoongArch::PCALAU12I: {
3403 // op: imm20
3404 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3405 op &= UINT64_C(1048575);
3406 op <<= 5;
3407 Value |= op;
3408 // op: rd
3409 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3410 op &= UINT64_C(31);
3411 Value |= op;
3412 break;
3413 }
3414 case LoongArch::LU32I_D: {
3415 // op: imm20
3416 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3417 op &= UINT64_C(1048575);
3418 op <<= 5;
3419 Value |= op;
3420 // op: rd
3421 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3422 op &= UINT64_C(31);
3423 Value |= op;
3424 break;
3425 }
3426 case LoongArch::JISCR0:
3427 case LoongArch::JISCR1: {
3428 // op: imm21
3429 op = getImmOpValueAsr<2>(MI, OpNo: 0, Fixups, STI);
3430 Value |= (op & UINT64_C(65535)) << 10;
3431 Value |= (op & UINT64_C(2031616)) >> 16;
3432 break;
3433 }
3434 case LoongArch::BCEQZ:
3435 case LoongArch::BCNEZ: {
3436 // op: imm21
3437 op = getImmOpValueAsr<2>(MI, OpNo: 1, Fixups, STI);
3438 Value |= (op & UINT64_C(65535)) << 10;
3439 Value |= (op & UINT64_C(2031616)) >> 16;
3440 // op: cj
3441 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3442 op &= UINT64_C(7);
3443 op <<= 5;
3444 Value |= op;
3445 break;
3446 }
3447 case LoongArch::BEQZ:
3448 case LoongArch::BNEZ: {
3449 // op: imm21
3450 op = getImmOpValueAsr<2>(MI, OpNo: 1, Fixups, STI);
3451 Value |= (op & UINT64_C(65535)) << 10;
3452 Value |= (op & UINT64_C(2031616)) >> 16;
3453 // op: rj
3454 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3455 op &= UINT64_C(31);
3456 op <<= 5;
3457 Value |= op;
3458 break;
3459 }
3460 case LoongArch::B:
3461 case LoongArch::BL: {
3462 // op: imm26
3463 op = getImmOpValueAsr<2>(MI, OpNo: 0, Fixups, STI);
3464 Value |= (op & UINT64_C(65535)) << 10;
3465 Value |= (op & UINT64_C(67043328)) >> 16;
3466 break;
3467 }
3468 case LoongArch::X86RCLI_B:
3469 case LoongArch::X86RCRI_B:
3470 case LoongArch::X86ROTLI_B:
3471 case LoongArch::X86ROTRI_B:
3472 case LoongArch::X86SLLI_B:
3473 case LoongArch::X86SRAI_B:
3474 case LoongArch::X86SRLI_B: {
3475 // op: imm3
3476 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3477 op &= UINT64_C(7);
3478 op <<= 10;
3479 Value |= op;
3480 // op: rj
3481 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3482 op &= UINT64_C(31);
3483 op <<= 5;
3484 Value |= op;
3485 break;
3486 }
3487 case LoongArch::RCRI_B:
3488 case LoongArch::ROTRI_B: {
3489 // op: imm3
3490 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3491 op &= UINT64_C(7);
3492 op <<= 10;
3493 Value |= op;
3494 // op: rj
3495 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3496 op &= UINT64_C(31);
3497 op <<= 5;
3498 Value |= op;
3499 // op: rd
3500 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3501 op &= UINT64_C(31);
3502 Value |= op;
3503 break;
3504 }
3505 case LoongArch::VPICKVE2GR_H:
3506 case LoongArch::VPICKVE2GR_HU: {
3507 // op: imm3
3508 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3509 op &= UINT64_C(7);
3510 op <<= 10;
3511 Value |= op;
3512 // op: vj
3513 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3514 op &= UINT64_C(31);
3515 op <<= 5;
3516 Value |= op;
3517 // op: rd
3518 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3519 op &= UINT64_C(31);
3520 Value |= op;
3521 break;
3522 }
3523 case LoongArch::VBITCLRI_B:
3524 case LoongArch::VBITREVI_B:
3525 case LoongArch::VBITSETI_B:
3526 case LoongArch::VREPLVEI_H:
3527 case LoongArch::VROTRI_B:
3528 case LoongArch::VSAT_B:
3529 case LoongArch::VSAT_BU:
3530 case LoongArch::VSLLI_B:
3531 case LoongArch::VSLLWIL_HU_BU:
3532 case LoongArch::VSLLWIL_H_B:
3533 case LoongArch::VSRAI_B:
3534 case LoongArch::VSRARI_B:
3535 case LoongArch::VSRLI_B:
3536 case LoongArch::VSRLRI_B: {
3537 // op: imm3
3538 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3539 op &= UINT64_C(7);
3540 op <<= 10;
3541 Value |= op;
3542 // op: vj
3543 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3544 op &= UINT64_C(31);
3545 op <<= 5;
3546 Value |= op;
3547 // op: vd
3548 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3549 op &= UINT64_C(31);
3550 Value |= op;
3551 break;
3552 }
3553 case LoongArch::XVPICKVE2GR_W:
3554 case LoongArch::XVPICKVE2GR_WU: {
3555 // op: imm3
3556 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3557 op &= UINT64_C(7);
3558 op <<= 10;
3559 Value |= op;
3560 // op: xj
3561 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3562 op &= UINT64_C(31);
3563 op <<= 5;
3564 Value |= op;
3565 // op: rd
3566 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3567 op &= UINT64_C(31);
3568 Value |= op;
3569 break;
3570 }
3571 case LoongArch::XVBITCLRI_B:
3572 case LoongArch::XVBITREVI_B:
3573 case LoongArch::XVBITSETI_B:
3574 case LoongArch::XVPICKVE_W:
3575 case LoongArch::XVREPL128VEI_H:
3576 case LoongArch::XVROTRI_B:
3577 case LoongArch::XVSAT_B:
3578 case LoongArch::XVSAT_BU:
3579 case LoongArch::XVSLLI_B:
3580 case LoongArch::XVSLLWIL_HU_BU:
3581 case LoongArch::XVSLLWIL_H_B:
3582 case LoongArch::XVSRAI_B:
3583 case LoongArch::XVSRARI_B:
3584 case LoongArch::XVSRLI_B:
3585 case LoongArch::XVSRLRI_B: {
3586 // op: imm3
3587 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3588 op &= UINT64_C(7);
3589 op <<= 10;
3590 Value |= op;
3591 // op: xj
3592 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3593 op &= UINT64_C(31);
3594 op <<= 5;
3595 Value |= op;
3596 // op: xd
3597 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3598 op &= UINT64_C(31);
3599 Value |= op;
3600 break;
3601 }
3602 case LoongArch::VINSGR2VR_H: {
3603 // op: imm3
3604 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
3605 op &= UINT64_C(7);
3606 op <<= 10;
3607 Value |= op;
3608 // op: rj
3609 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3610 op &= UINT64_C(31);
3611 op <<= 5;
3612 Value |= op;
3613 // op: vd
3614 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3615 op &= UINT64_C(31);
3616 Value |= op;
3617 break;
3618 }
3619 case LoongArch::XVINSGR2VR_W: {
3620 // op: imm3
3621 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
3622 op &= UINT64_C(7);
3623 op <<= 10;
3624 Value |= op;
3625 // op: rj
3626 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3627 op &= UINT64_C(31);
3628 op <<= 5;
3629 Value |= op;
3630 // op: xd
3631 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3632 op &= UINT64_C(31);
3633 Value |= op;
3634 break;
3635 }
3636 case LoongArch::XVINSVE0_W: {
3637 // op: imm3
3638 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
3639 op &= UINT64_C(7);
3640 op <<= 10;
3641 Value |= op;
3642 // op: xj
3643 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3644 op &= UINT64_C(31);
3645 op <<= 5;
3646 Value |= op;
3647 // op: xd
3648 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3649 op &= UINT64_C(31);
3650 Value |= op;
3651 break;
3652 }
3653 case LoongArch::BYTEPICK_D: {
3654 // op: imm3
3655 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
3656 op &= UINT64_C(7);
3657 op <<= 15;
3658 Value |= op;
3659 // op: rk
3660 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3661 op &= UINT64_C(31);
3662 op <<= 10;
3663 Value |= op;
3664 // op: rj
3665 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3666 op &= UINT64_C(31);
3667 op <<= 5;
3668 Value |= op;
3669 // op: rd
3670 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3671 op &= UINT64_C(31);
3672 Value |= op;
3673 break;
3674 }
3675 case LoongArch::VSTELM_H: {
3676 // op: imm3
3677 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
3678 op &= UINT64_C(7);
3679 op <<= 18;
3680 Value |= op;
3681 // op: imm8
3682 op = getImmOpValueAsr<1>(MI, OpNo: 2, Fixups, STI);
3683 op &= UINT64_C(255);
3684 op <<= 10;
3685 Value |= op;
3686 // op: rj
3687 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3688 op &= UINT64_C(31);
3689 op <<= 5;
3690 Value |= op;
3691 // op: vd
3692 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3693 op &= UINT64_C(31);
3694 Value |= op;
3695 break;
3696 }
3697 case LoongArch::XVSTELM_W: {
3698 // op: imm3
3699 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
3700 op &= UINT64_C(7);
3701 op <<= 18;
3702 Value |= op;
3703 // op: imm8
3704 op = getImmOpValueAsr<2>(MI, OpNo: 2, Fixups, STI);
3705 op &= UINT64_C(255);
3706 op <<= 10;
3707 Value |= op;
3708 // op: rj
3709 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3710 op &= UINT64_C(31);
3711 op <<= 5;
3712 Value |= op;
3713 // op: xd
3714 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3715 op &= UINT64_C(31);
3716 Value |= op;
3717 break;
3718 }
3719 case LoongArch::SETARMJ:
3720 case LoongArch::SETX86J: {
3721 // op: imm4
3722 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3723 op &= UINT64_C(15);
3724 op <<= 10;
3725 Value |= op;
3726 // op: rd
3727 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3728 op &= UINT64_C(31);
3729 Value |= op;
3730 break;
3731 }
3732 case LoongArch::ARMMOV_D:
3733 case LoongArch::ARMMOV_W:
3734 case LoongArch::ARMNOT_W:
3735 case LoongArch::ARMRRX_W:
3736 case LoongArch::X86RCLI_H:
3737 case LoongArch::X86RCRI_H:
3738 case LoongArch::X86ROTLI_H:
3739 case LoongArch::X86ROTRI_H:
3740 case LoongArch::X86SLLI_H:
3741 case LoongArch::X86SRAI_H:
3742 case LoongArch::X86SRLI_H: {
3743 // op: imm4
3744 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3745 op &= UINT64_C(15);
3746 op <<= 10;
3747 Value |= op;
3748 // op: rj
3749 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3750 op &= UINT64_C(31);
3751 op <<= 5;
3752 Value |= op;
3753 break;
3754 }
3755 case LoongArch::ARMADC_W:
3756 case LoongArch::ARMADD_W:
3757 case LoongArch::ARMAND_W:
3758 case LoongArch::ARMOR_W:
3759 case LoongArch::ARMROTR_W:
3760 case LoongArch::ARMSBC_W:
3761 case LoongArch::ARMSLL_W:
3762 case LoongArch::ARMSRA_W:
3763 case LoongArch::ARMSRL_W:
3764 case LoongArch::ARMSUB_W:
3765 case LoongArch::ARMXOR_W: {
3766 // op: imm4
3767 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3768 op &= UINT64_C(15);
3769 Value |= op;
3770 // op: rk
3771 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3772 op &= UINT64_C(31);
3773 op <<= 10;
3774 Value |= op;
3775 // op: rj
3776 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3777 op &= UINT64_C(31);
3778 op <<= 5;
3779 Value |= op;
3780 break;
3781 }
3782 case LoongArch::ARMMOVE:
3783 case LoongArch::RCRI_H:
3784 case LoongArch::ROTRI_H: {
3785 // op: imm4
3786 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3787 op &= UINT64_C(15);
3788 op <<= 10;
3789 Value |= op;
3790 // op: rj
3791 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3792 op &= UINT64_C(31);
3793 op <<= 5;
3794 Value |= op;
3795 // op: rd
3796 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3797 op &= UINT64_C(31);
3798 Value |= op;
3799 break;
3800 }
3801 case LoongArch::VPICKVE2GR_B:
3802 case LoongArch::VPICKVE2GR_BU: {
3803 // op: imm4
3804 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3805 op &= UINT64_C(15);
3806 op <<= 10;
3807 Value |= op;
3808 // op: vj
3809 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3810 op &= UINT64_C(31);
3811 op <<= 5;
3812 Value |= op;
3813 // op: rd
3814 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3815 op &= UINT64_C(31);
3816 Value |= op;
3817 break;
3818 }
3819 case LoongArch::VBITCLRI_H:
3820 case LoongArch::VBITREVI_H:
3821 case LoongArch::VBITSETI_H:
3822 case LoongArch::VREPLVEI_B:
3823 case LoongArch::VROTRI_H:
3824 case LoongArch::VSAT_H:
3825 case LoongArch::VSAT_HU:
3826 case LoongArch::VSLLI_H:
3827 case LoongArch::VSLLWIL_WU_HU:
3828 case LoongArch::VSLLWIL_W_H:
3829 case LoongArch::VSRAI_H:
3830 case LoongArch::VSRARI_H:
3831 case LoongArch::VSRLI_H:
3832 case LoongArch::VSRLRI_H: {
3833 // op: imm4
3834 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3835 op &= UINT64_C(15);
3836 op <<= 10;
3837 Value |= op;
3838 // op: vj
3839 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3840 op &= UINT64_C(31);
3841 op <<= 5;
3842 Value |= op;
3843 // op: vd
3844 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3845 op &= UINT64_C(31);
3846 Value |= op;
3847 break;
3848 }
3849 case LoongArch::XVBITCLRI_H:
3850 case LoongArch::XVBITREVI_H:
3851 case LoongArch::XVBITSETI_H:
3852 case LoongArch::XVREPL128VEI_B:
3853 case LoongArch::XVROTRI_H:
3854 case LoongArch::XVSAT_H:
3855 case LoongArch::XVSAT_HU:
3856 case LoongArch::XVSLLI_H:
3857 case LoongArch::XVSLLWIL_WU_HU:
3858 case LoongArch::XVSLLWIL_W_H:
3859 case LoongArch::XVSRAI_H:
3860 case LoongArch::XVSRARI_H:
3861 case LoongArch::XVSRLI_H:
3862 case LoongArch::XVSRLRI_H: {
3863 // op: imm4
3864 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3865 op &= UINT64_C(15);
3866 op <<= 10;
3867 Value |= op;
3868 // op: xj
3869 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3870 op &= UINT64_C(31);
3871 op <<= 5;
3872 Value |= op;
3873 // op: xd
3874 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3875 op &= UINT64_C(31);
3876 Value |= op;
3877 break;
3878 }
3879 case LoongArch::VINSGR2VR_B: {
3880 // op: imm4
3881 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
3882 op &= UINT64_C(15);
3883 op <<= 10;
3884 Value |= op;
3885 // op: rj
3886 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3887 op &= UINT64_C(31);
3888 op <<= 5;
3889 Value |= op;
3890 // op: vd
3891 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3892 op &= UINT64_C(31);
3893 Value |= op;
3894 break;
3895 }
3896 case LoongArch::VSRANI_B_H:
3897 case LoongArch::VSRARNI_B_H:
3898 case LoongArch::VSRLNI_B_H:
3899 case LoongArch::VSRLRNI_B_H:
3900 case LoongArch::VSSRANI_BU_H:
3901 case LoongArch::VSSRANI_B_H:
3902 case LoongArch::VSSRARNI_BU_H:
3903 case LoongArch::VSSRARNI_B_H:
3904 case LoongArch::VSSRLNI_BU_H:
3905 case LoongArch::VSSRLNI_B_H:
3906 case LoongArch::VSSRLRNI_BU_H:
3907 case LoongArch::VSSRLRNI_B_H: {
3908 // op: imm4
3909 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
3910 op &= UINT64_C(15);
3911 op <<= 10;
3912 Value |= op;
3913 // op: vj
3914 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3915 op &= UINT64_C(31);
3916 op <<= 5;
3917 Value |= op;
3918 // op: vd
3919 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3920 op &= UINT64_C(31);
3921 Value |= op;
3922 break;
3923 }
3924 case LoongArch::XVSRANI_B_H:
3925 case LoongArch::XVSRARNI_B_H:
3926 case LoongArch::XVSRLNI_B_H:
3927 case LoongArch::XVSRLRNI_B_H:
3928 case LoongArch::XVSSRANI_BU_H:
3929 case LoongArch::XVSSRANI_B_H:
3930 case LoongArch::XVSSRARNI_BU_H:
3931 case LoongArch::XVSSRARNI_B_H:
3932 case LoongArch::XVSSRLNI_BU_H:
3933 case LoongArch::XVSSRLNI_B_H:
3934 case LoongArch::XVSSRLRNI_BU_H:
3935 case LoongArch::XVSSRLRNI_B_H: {
3936 // op: imm4
3937 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
3938 op &= UINT64_C(15);
3939 op <<= 10;
3940 Value |= op;
3941 // op: xj
3942 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3943 op &= UINT64_C(31);
3944 op <<= 5;
3945 Value |= op;
3946 // op: xd
3947 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3948 op &= UINT64_C(31);
3949 Value |= op;
3950 break;
3951 }
3952 case LoongArch::XVSTELM_H: {
3953 // op: imm4
3954 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
3955 op &= UINT64_C(15);
3956 op <<= 18;
3957 Value |= op;
3958 // op: imm8
3959 op = getImmOpValueAsr<1>(MI, OpNo: 2, Fixups, STI);
3960 op &= UINT64_C(255);
3961 op <<= 10;
3962 Value |= op;
3963 // op: rj
3964 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3965 op &= UINT64_C(31);
3966 op <<= 5;
3967 Value |= op;
3968 // op: xd
3969 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3970 op &= UINT64_C(31);
3971 Value |= op;
3972 break;
3973 }
3974 case LoongArch::VSTELM_B: {
3975 // op: imm4
3976 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
3977 op &= UINT64_C(15);
3978 op <<= 18;
3979 Value |= op;
3980 // op: imm8
3981 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3982 op &= UINT64_C(255);
3983 op <<= 10;
3984 Value |= op;
3985 // op: rj
3986 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3987 op &= UINT64_C(31);
3988 op <<= 5;
3989 Value |= op;
3990 // op: vd
3991 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3992 op &= UINT64_C(31);
3993 Value |= op;
3994 break;
3995 }
3996 case LoongArch::X86RCLI_W:
3997 case LoongArch::X86RCRI_W:
3998 case LoongArch::X86ROTLI_W:
3999 case LoongArch::X86ROTRI_W:
4000 case LoongArch::X86SLLI_W:
4001 case LoongArch::X86SRAI_W:
4002 case LoongArch::X86SRLI_W: {
4003 // op: imm5
4004 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4005 op &= UINT64_C(31);
4006 op <<= 10;
4007 Value |= op;
4008 // op: rj
4009 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4010 op &= UINT64_C(31);
4011 op <<= 5;
4012 Value |= op;
4013 break;
4014 }
4015 case LoongArch::ARMROTRI_W:
4016 case LoongArch::ARMSLLI_W:
4017 case LoongArch::ARMSRAI_W:
4018 case LoongArch::ARMSRLI_W: {
4019 // op: imm5
4020 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4021 op &= UINT64_C(31);
4022 op <<= 10;
4023 Value |= op;
4024 // op: rj
4025 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4026 op &= UINT64_C(31);
4027 op <<= 5;
4028 Value |= op;
4029 // op: imm4
4030 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4031 op &= UINT64_C(15);
4032 Value |= op;
4033 break;
4034 }
4035 case LoongArch::ADDU12I_D:
4036 case LoongArch::ADDU12I_W:
4037 case LoongArch::RCRI_W:
4038 case LoongArch::ROTRI_W:
4039 case LoongArch::SLLI_W:
4040 case LoongArch::SRAI_W:
4041 case LoongArch::SRLI_W: {
4042 // op: imm5
4043 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4044 op &= UINT64_C(31);
4045 op <<= 10;
4046 Value |= op;
4047 // op: rj
4048 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4049 op &= UINT64_C(31);
4050 op <<= 5;
4051 Value |= op;
4052 // op: rd
4053 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4054 op &= UINT64_C(31);
4055 Value |= op;
4056 break;
4057 }
4058 case LoongArch::VADDI_BU:
4059 case LoongArch::VADDI_DU:
4060 case LoongArch::VADDI_HU:
4061 case LoongArch::VADDI_WU:
4062 case LoongArch::VBITCLRI_W:
4063 case LoongArch::VBITREVI_W:
4064 case LoongArch::VBITSETI_W:
4065 case LoongArch::VBSLL_V:
4066 case LoongArch::VBSRL_V:
4067 case LoongArch::VMAXI_B:
4068 case LoongArch::VMAXI_BU:
4069 case LoongArch::VMAXI_D:
4070 case LoongArch::VMAXI_DU:
4071 case LoongArch::VMAXI_H:
4072 case LoongArch::VMAXI_HU:
4073 case LoongArch::VMAXI_W:
4074 case LoongArch::VMAXI_WU:
4075 case LoongArch::VMINI_B:
4076 case LoongArch::VMINI_BU:
4077 case LoongArch::VMINI_D:
4078 case LoongArch::VMINI_DU:
4079 case LoongArch::VMINI_H:
4080 case LoongArch::VMINI_HU:
4081 case LoongArch::VMINI_W:
4082 case LoongArch::VMINI_WU:
4083 case LoongArch::VROTRI_W:
4084 case LoongArch::VSAT_W:
4085 case LoongArch::VSAT_WU:
4086 case LoongArch::VSEQI_B:
4087 case LoongArch::VSEQI_D:
4088 case LoongArch::VSEQI_H:
4089 case LoongArch::VSEQI_W:
4090 case LoongArch::VSLEI_B:
4091 case LoongArch::VSLEI_BU:
4092 case LoongArch::VSLEI_D:
4093 case LoongArch::VSLEI_DU:
4094 case LoongArch::VSLEI_H:
4095 case LoongArch::VSLEI_HU:
4096 case LoongArch::VSLEI_W:
4097 case LoongArch::VSLEI_WU:
4098 case LoongArch::VSLLI_W:
4099 case LoongArch::VSLLWIL_DU_WU:
4100 case LoongArch::VSLLWIL_D_W:
4101 case LoongArch::VSLTI_B:
4102 case LoongArch::VSLTI_BU:
4103 case LoongArch::VSLTI_D:
4104 case LoongArch::VSLTI_DU:
4105 case LoongArch::VSLTI_H:
4106 case LoongArch::VSLTI_HU:
4107 case LoongArch::VSLTI_W:
4108 case LoongArch::VSLTI_WU:
4109 case LoongArch::VSRAI_W:
4110 case LoongArch::VSRARI_W:
4111 case LoongArch::VSRLI_W:
4112 case LoongArch::VSRLRI_W:
4113 case LoongArch::VSUBI_BU:
4114 case LoongArch::VSUBI_DU:
4115 case LoongArch::VSUBI_HU:
4116 case LoongArch::VSUBI_WU: {
4117 // op: imm5
4118 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4119 op &= UINT64_C(31);
4120 op <<= 10;
4121 Value |= op;
4122 // op: vj
4123 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4124 op &= UINT64_C(31);
4125 op <<= 5;
4126 Value |= op;
4127 // op: vd
4128 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4129 op &= UINT64_C(31);
4130 Value |= op;
4131 break;
4132 }
4133 case LoongArch::XVADDI_BU:
4134 case LoongArch::XVADDI_DU:
4135 case LoongArch::XVADDI_HU:
4136 case LoongArch::XVADDI_WU:
4137 case LoongArch::XVBITCLRI_W:
4138 case LoongArch::XVBITREVI_W:
4139 case LoongArch::XVBITSETI_W:
4140 case LoongArch::XVBSLL_V:
4141 case LoongArch::XVBSRL_V:
4142 case LoongArch::XVHSELI_D:
4143 case LoongArch::XVMAXI_B:
4144 case LoongArch::XVMAXI_BU:
4145 case LoongArch::XVMAXI_D:
4146 case LoongArch::XVMAXI_DU:
4147 case LoongArch::XVMAXI_H:
4148 case LoongArch::XVMAXI_HU:
4149 case LoongArch::XVMAXI_W:
4150 case LoongArch::XVMAXI_WU:
4151 case LoongArch::XVMINI_B:
4152 case LoongArch::XVMINI_BU:
4153 case LoongArch::XVMINI_D:
4154 case LoongArch::XVMINI_DU:
4155 case LoongArch::XVMINI_H:
4156 case LoongArch::XVMINI_HU:
4157 case LoongArch::XVMINI_W:
4158 case LoongArch::XVMINI_WU:
4159 case LoongArch::XVROTRI_W:
4160 case LoongArch::XVSAT_W:
4161 case LoongArch::XVSAT_WU:
4162 case LoongArch::XVSEQI_B:
4163 case LoongArch::XVSEQI_D:
4164 case LoongArch::XVSEQI_H:
4165 case LoongArch::XVSEQI_W:
4166 case LoongArch::XVSLEI_B:
4167 case LoongArch::XVSLEI_BU:
4168 case LoongArch::XVSLEI_D:
4169 case LoongArch::XVSLEI_DU:
4170 case LoongArch::XVSLEI_H:
4171 case LoongArch::XVSLEI_HU:
4172 case LoongArch::XVSLEI_W:
4173 case LoongArch::XVSLEI_WU:
4174 case LoongArch::XVSLLI_W:
4175 case LoongArch::XVSLLWIL_DU_WU:
4176 case LoongArch::XVSLLWIL_D_W:
4177 case LoongArch::XVSLTI_B:
4178 case LoongArch::XVSLTI_BU:
4179 case LoongArch::XVSLTI_D:
4180 case LoongArch::XVSLTI_DU:
4181 case LoongArch::XVSLTI_H:
4182 case LoongArch::XVSLTI_HU:
4183 case LoongArch::XVSLTI_W:
4184 case LoongArch::XVSLTI_WU:
4185 case LoongArch::XVSRAI_W:
4186 case LoongArch::XVSRARI_W:
4187 case LoongArch::XVSRLI_W:
4188 case LoongArch::XVSRLRI_W:
4189 case LoongArch::XVSUBI_BU:
4190 case LoongArch::XVSUBI_DU:
4191 case LoongArch::XVSUBI_HU:
4192 case LoongArch::XVSUBI_WU: {
4193 // op: imm5
4194 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4195 op &= UINT64_C(31);
4196 op <<= 10;
4197 Value |= op;
4198 // op: xj
4199 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4200 op &= UINT64_C(31);
4201 op <<= 5;
4202 Value |= op;
4203 // op: xd
4204 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4205 op &= UINT64_C(31);
4206 Value |= op;
4207 break;
4208 }
4209 case LoongArch::VFRSTPI_B:
4210 case LoongArch::VFRSTPI_H:
4211 case LoongArch::VSRANI_H_W:
4212 case LoongArch::VSRARNI_H_W:
4213 case LoongArch::VSRLNI_H_W:
4214 case LoongArch::VSRLRNI_H_W:
4215 case LoongArch::VSSRANI_HU_W:
4216 case LoongArch::VSSRANI_H_W:
4217 case LoongArch::VSSRARNI_HU_W:
4218 case LoongArch::VSSRARNI_H_W:
4219 case LoongArch::VSSRLNI_HU_W:
4220 case LoongArch::VSSRLNI_H_W:
4221 case LoongArch::VSSRLRNI_HU_W:
4222 case LoongArch::VSSRLRNI_H_W: {
4223 // op: imm5
4224 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4225 op &= UINT64_C(31);
4226 op <<= 10;
4227 Value |= op;
4228 // op: vj
4229 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4230 op &= UINT64_C(31);
4231 op <<= 5;
4232 Value |= op;
4233 // op: vd
4234 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4235 op &= UINT64_C(31);
4236 Value |= op;
4237 break;
4238 }
4239 case LoongArch::XVFRSTPI_B:
4240 case LoongArch::XVFRSTPI_H:
4241 case LoongArch::XVSRANI_H_W:
4242 case LoongArch::XVSRARNI_H_W:
4243 case LoongArch::XVSRLNI_H_W:
4244 case LoongArch::XVSRLRNI_H_W:
4245 case LoongArch::XVSSRANI_HU_W:
4246 case LoongArch::XVSSRANI_H_W:
4247 case LoongArch::XVSSRARNI_HU_W:
4248 case LoongArch::XVSSRARNI_H_W:
4249 case LoongArch::XVSSRLNI_HU_W:
4250 case LoongArch::XVSSRLNI_H_W:
4251 case LoongArch::XVSSRLRNI_HU_W:
4252 case LoongArch::XVSSRLRNI_H_W: {
4253 // op: imm5
4254 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4255 op &= UINT64_C(31);
4256 op <<= 10;
4257 Value |= op;
4258 // op: xj
4259 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4260 op &= UINT64_C(31);
4261 op <<= 5;
4262 Value |= op;
4263 // op: xd
4264 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4265 op &= UINT64_C(31);
4266 Value |= op;
4267 break;
4268 }
4269 case LoongArch::XVSTELM_B: {
4270 // op: imm5
4271 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4272 op &= UINT64_C(31);
4273 op <<= 18;
4274 Value |= op;
4275 // op: imm8
4276 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4277 op &= UINT64_C(255);
4278 op <<= 10;
4279 Value |= op;
4280 // op: rj
4281 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4282 op &= UINT64_C(31);
4283 op <<= 5;
4284 Value |= op;
4285 // op: xd
4286 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4287 op &= UINT64_C(31);
4288 Value |= op;
4289 break;
4290 }
4291 case LoongArch::X86RCLI_D:
4292 case LoongArch::X86RCRI_D:
4293 case LoongArch::X86ROTLI_D:
4294 case LoongArch::X86ROTRI_D:
4295 case LoongArch::X86SLLI_D:
4296 case LoongArch::X86SRAI_D:
4297 case LoongArch::X86SRLI_D: {
4298 // op: imm6
4299 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4300 op &= UINT64_C(63);
4301 op <<= 10;
4302 Value |= op;
4303 // op: rj
4304 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4305 op &= UINT64_C(31);
4306 op <<= 5;
4307 Value |= op;
4308 break;
4309 }
4310 case LoongArch::RCRI_D:
4311 case LoongArch::ROTRI_D:
4312 case LoongArch::SLLI_D:
4313 case LoongArch::SRAI_D:
4314 case LoongArch::SRLI_D: {
4315 // op: imm6
4316 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4317 op &= UINT64_C(63);
4318 op <<= 10;
4319 Value |= op;
4320 // op: rj
4321 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4322 op &= UINT64_C(31);
4323 op <<= 5;
4324 Value |= op;
4325 // op: rd
4326 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4327 op &= UINT64_C(31);
4328 Value |= op;
4329 break;
4330 }
4331 case LoongArch::VBITCLRI_D:
4332 case LoongArch::VBITREVI_D:
4333 case LoongArch::VBITSETI_D:
4334 case LoongArch::VROTRI_D:
4335 case LoongArch::VSAT_D:
4336 case LoongArch::VSAT_DU:
4337 case LoongArch::VSLLI_D:
4338 case LoongArch::VSRAI_D:
4339 case LoongArch::VSRARI_D:
4340 case LoongArch::VSRLI_D:
4341 case LoongArch::VSRLRI_D: {
4342 // op: imm6
4343 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4344 op &= UINT64_C(63);
4345 op <<= 10;
4346 Value |= op;
4347 // op: vj
4348 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4349 op &= UINT64_C(31);
4350 op <<= 5;
4351 Value |= op;
4352 // op: vd
4353 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4354 op &= UINT64_C(31);
4355 Value |= op;
4356 break;
4357 }
4358 case LoongArch::XVBITCLRI_D:
4359 case LoongArch::XVBITREVI_D:
4360 case LoongArch::XVBITSETI_D:
4361 case LoongArch::XVROTRI_D:
4362 case LoongArch::XVSAT_D:
4363 case LoongArch::XVSAT_DU:
4364 case LoongArch::XVSLLI_D:
4365 case LoongArch::XVSRAI_D:
4366 case LoongArch::XVSRARI_D:
4367 case LoongArch::XVSRLI_D:
4368 case LoongArch::XVSRLRI_D: {
4369 // op: imm6
4370 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4371 op &= UINT64_C(63);
4372 op <<= 10;
4373 Value |= op;
4374 // op: xj
4375 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4376 op &= UINT64_C(31);
4377 op <<= 5;
4378 Value |= op;
4379 // op: xd
4380 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4381 op &= UINT64_C(31);
4382 Value |= op;
4383 break;
4384 }
4385 case LoongArch::VSRANI_W_D:
4386 case LoongArch::VSRARNI_W_D:
4387 case LoongArch::VSRLNI_W_D:
4388 case LoongArch::VSRLRNI_W_D:
4389 case LoongArch::VSSRANI_WU_D:
4390 case LoongArch::VSSRANI_W_D:
4391 case LoongArch::VSSRARNI_WU_D:
4392 case LoongArch::VSSRARNI_W_D:
4393 case LoongArch::VSSRLNI_WU_D:
4394 case LoongArch::VSSRLNI_W_D:
4395 case LoongArch::VSSRLRNI_WU_D:
4396 case LoongArch::VSSRLRNI_W_D: {
4397 // op: imm6
4398 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4399 op &= UINT64_C(63);
4400 op <<= 10;
4401 Value |= op;
4402 // op: vj
4403 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4404 op &= UINT64_C(31);
4405 op <<= 5;
4406 Value |= op;
4407 // op: vd
4408 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4409 op &= UINT64_C(31);
4410 Value |= op;
4411 break;
4412 }
4413 case LoongArch::XVSRANI_W_D:
4414 case LoongArch::XVSRARNI_W_D:
4415 case LoongArch::XVSRLNI_W_D:
4416 case LoongArch::XVSRLRNI_W_D:
4417 case LoongArch::XVSSRANI_WU_D:
4418 case LoongArch::XVSSRANI_W_D:
4419 case LoongArch::XVSSRARNI_WU_D:
4420 case LoongArch::XVSSRARNI_W_D:
4421 case LoongArch::XVSSRLNI_WU_D:
4422 case LoongArch::XVSSRLNI_W_D:
4423 case LoongArch::XVSSRLRNI_WU_D:
4424 case LoongArch::XVSSRLRNI_W_D: {
4425 // op: imm6
4426 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4427 op &= UINT64_C(63);
4428 op <<= 10;
4429 Value |= op;
4430 // op: xj
4431 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4432 op &= UINT64_C(31);
4433 op <<= 5;
4434 Value |= op;
4435 // op: xd
4436 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4437 op &= UINT64_C(31);
4438 Value |= op;
4439 break;
4440 }
4441 case LoongArch::VSRANI_D_Q:
4442 case LoongArch::VSRARNI_D_Q:
4443 case LoongArch::VSRLNI_D_Q:
4444 case LoongArch::VSRLRNI_D_Q:
4445 case LoongArch::VSSRANI_DU_Q:
4446 case LoongArch::VSSRANI_D_Q:
4447 case LoongArch::VSSRARNI_DU_Q:
4448 case LoongArch::VSSRARNI_D_Q:
4449 case LoongArch::VSSRLNI_DU_Q:
4450 case LoongArch::VSSRLNI_D_Q:
4451 case LoongArch::VSSRLRNI_DU_Q:
4452 case LoongArch::VSSRLRNI_D_Q: {
4453 // op: imm7
4454 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4455 op &= UINT64_C(127);
4456 op <<= 10;
4457 Value |= op;
4458 // op: vj
4459 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4460 op &= UINT64_C(31);
4461 op <<= 5;
4462 Value |= op;
4463 // op: vd
4464 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4465 op &= UINT64_C(31);
4466 Value |= op;
4467 break;
4468 }
4469 case LoongArch::XVSRANI_D_Q:
4470 case LoongArch::XVSRARNI_D_Q:
4471 case LoongArch::XVSRLNI_D_Q:
4472 case LoongArch::XVSRLRNI_D_Q:
4473 case LoongArch::XVSSRANI_DU_Q:
4474 case LoongArch::XVSSRANI_D_Q:
4475 case LoongArch::XVSSRARNI_DU_Q:
4476 case LoongArch::XVSSRARNI_D_Q:
4477 case LoongArch::XVSSRLNI_DU_Q:
4478 case LoongArch::XVSSRLNI_D_Q:
4479 case LoongArch::XVSSRLRNI_DU_Q:
4480 case LoongArch::XVSSRLRNI_D_Q: {
4481 // op: imm7
4482 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4483 op &= UINT64_C(127);
4484 op <<= 10;
4485 Value |= op;
4486 // op: xj
4487 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4488 op &= UINT64_C(31);
4489 op <<= 5;
4490 Value |= op;
4491 // op: xd
4492 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4493 op &= UINT64_C(31);
4494 Value |= op;
4495 break;
4496 }
4497 case LoongArch::ARMMFFLAG:
4498 case LoongArch::ARMMTFLAG:
4499 case LoongArch::X86MFFLAG:
4500 case LoongArch::X86MTFLAG: {
4501 // op: imm8
4502 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4503 op &= UINT64_C(255);
4504 op <<= 10;
4505 Value |= op;
4506 // op: rd
4507 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4508 op &= UINT64_C(31);
4509 Value |= op;
4510 break;
4511 }
4512 case LoongArch::X86SETTAG: {
4513 // op: imm8
4514 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4515 op &= UINT64_C(255);
4516 op <<= 10;
4517 Value |= op;
4518 // op: imm5
4519 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4520 op &= UINT64_C(31);
4521 op <<= 5;
4522 Value |= op;
4523 // op: rd
4524 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4525 op &= UINT64_C(31);
4526 Value |= op;
4527 break;
4528 }
4529 case LoongArch::LDDIR: {
4530 // op: imm8
4531 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4532 op &= UINT64_C(255);
4533 op <<= 10;
4534 Value |= op;
4535 // op: rj
4536 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4537 op &= UINT64_C(31);
4538 op <<= 5;
4539 Value |= op;
4540 // op: rd
4541 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4542 op &= UINT64_C(31);
4543 Value |= op;
4544 break;
4545 }
4546 case LoongArch::VANDI_B:
4547 case LoongArch::VNORI_B:
4548 case LoongArch::VORI_B:
4549 case LoongArch::VSHUF4I_B:
4550 case LoongArch::VSHUF4I_H:
4551 case LoongArch::VSHUF4I_W:
4552 case LoongArch::VXORI_B: {
4553 // op: imm8
4554 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4555 op &= UINT64_C(255);
4556 op <<= 10;
4557 Value |= op;
4558 // op: vj
4559 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4560 op &= UINT64_C(31);
4561 op <<= 5;
4562 Value |= op;
4563 // op: vd
4564 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4565 op &= UINT64_C(31);
4566 Value |= op;
4567 break;
4568 }
4569 case LoongArch::XVANDI_B:
4570 case LoongArch::XVNORI_B:
4571 case LoongArch::XVORI_B:
4572 case LoongArch::XVPERMI_D:
4573 case LoongArch::XVSHUF4I_B:
4574 case LoongArch::XVSHUF4I_H:
4575 case LoongArch::XVSHUF4I_W:
4576 case LoongArch::XVXORI_B: {
4577 // op: imm8
4578 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4579 op &= UINT64_C(255);
4580 op <<= 10;
4581 Value |= op;
4582 // op: xj
4583 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4584 op &= UINT64_C(31);
4585 op <<= 5;
4586 Value |= op;
4587 // op: xd
4588 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4589 op &= UINT64_C(31);
4590 Value |= op;
4591 break;
4592 }
4593 case LoongArch::VBITSELI_B:
4594 case LoongArch::VEXTRINS_B:
4595 case LoongArch::VEXTRINS_D:
4596 case LoongArch::VEXTRINS_H:
4597 case LoongArch::VEXTRINS_W:
4598 case LoongArch::VPERMI_W:
4599 case LoongArch::VSHUF4I_D: {
4600 // op: imm8
4601 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4602 op &= UINT64_C(255);
4603 op <<= 10;
4604 Value |= op;
4605 // op: vj
4606 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4607 op &= UINT64_C(31);
4608 op <<= 5;
4609 Value |= op;
4610 // op: vd
4611 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4612 op &= UINT64_C(31);
4613 Value |= op;
4614 break;
4615 }
4616 case LoongArch::XVBITSELI_B:
4617 case LoongArch::XVEXTRINS_B:
4618 case LoongArch::XVEXTRINS_D:
4619 case LoongArch::XVEXTRINS_H:
4620 case LoongArch::XVEXTRINS_W:
4621 case LoongArch::XVPERMI_Q:
4622 case LoongArch::XVPERMI_W:
4623 case LoongArch::XVSHUF4I_D: {
4624 // op: imm8
4625 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4626 op &= UINT64_C(255);
4627 op <<= 10;
4628 Value |= op;
4629 // op: xj
4630 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4631 op &= UINT64_C(31);
4632 op <<= 5;
4633 Value |= op;
4634 // op: xd
4635 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4636 op &= UINT64_C(31);
4637 Value |= op;
4638 break;
4639 }
4640 case LoongArch::VLDREPL_D: {
4641 // op: imm9
4642 op = getImmOpValueAsr<3>(MI, OpNo: 2, Fixups, STI);
4643 op &= UINT64_C(511);
4644 op <<= 10;
4645 Value |= op;
4646 // op: rj
4647 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4648 op &= UINT64_C(31);
4649 op <<= 5;
4650 Value |= op;
4651 // op: vd
4652 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4653 op &= UINT64_C(31);
4654 Value |= op;
4655 break;
4656 }
4657 case LoongArch::XVLDREPL_D: {
4658 // op: imm9
4659 op = getImmOpValueAsr<3>(MI, OpNo: 2, Fixups, STI);
4660 op &= UINT64_C(511);
4661 op <<= 10;
4662 Value |= op;
4663 // op: rj
4664 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4665 op &= UINT64_C(31);
4666 op <<= 5;
4667 Value |= op;
4668 // op: xd
4669 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4670 op &= UINT64_C(31);
4671 Value |= op;
4672 break;
4673 }
4674 case LoongArch::BSTRPICK_D: {
4675 // op: msbd
4676 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4677 op &= UINT64_C(63);
4678 op <<= 16;
4679 Value |= op;
4680 // op: lsbd
4681 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4682 op &= UINT64_C(63);
4683 op <<= 10;
4684 Value |= op;
4685 // op: rj
4686 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4687 op &= UINT64_C(31);
4688 op <<= 5;
4689 Value |= op;
4690 // op: rd
4691 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4692 op &= UINT64_C(31);
4693 Value |= op;
4694 break;
4695 }
4696 case LoongArch::BSTRINS_D: {
4697 // op: msbd
4698 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4699 op &= UINT64_C(63);
4700 op <<= 16;
4701 Value |= op;
4702 // op: lsbd
4703 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
4704 op &= UINT64_C(63);
4705 op <<= 10;
4706 Value |= op;
4707 // op: rj
4708 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4709 op &= UINT64_C(31);
4710 op <<= 5;
4711 Value |= op;
4712 // op: rd
4713 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4714 op &= UINT64_C(31);
4715 Value |= op;
4716 break;
4717 }
4718 case LoongArch::BSTRPICK_W: {
4719 // op: msbw
4720 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4721 op &= UINT64_C(31);
4722 op <<= 16;
4723 Value |= op;
4724 // op: lsbw
4725 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4726 op &= UINT64_C(31);
4727 op <<= 10;
4728 Value |= op;
4729 // op: rj
4730 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4731 op &= UINT64_C(31);
4732 op <<= 5;
4733 Value |= op;
4734 // op: rd
4735 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4736 op &= UINT64_C(31);
4737 Value |= op;
4738 break;
4739 }
4740 case LoongArch::BSTRINS_W: {
4741 // op: msbw
4742 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4743 op &= UINT64_C(31);
4744 op <<= 16;
4745 Value |= op;
4746 // op: lsbw
4747 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
4748 op &= UINT64_C(31);
4749 op <<= 10;
4750 Value |= op;
4751 // op: rj
4752 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4753 op &= UINT64_C(31);
4754 op <<= 5;
4755 Value |= op;
4756 // op: rd
4757 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4758 op &= UINT64_C(31);
4759 Value |= op;
4760 break;
4761 }
4762 case LoongArch::X86MTTOP: {
4763 // op: ptr
4764 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4765 op &= UINT64_C(7);
4766 op <<= 5;
4767 Value |= op;
4768 break;
4769 }
4770 case LoongArch::X86MFTOP: {
4771 // op: rd
4772 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4773 op &= UINT64_C(31);
4774 Value |= op;
4775 break;
4776 }
4777 case LoongArch::X86DEC_B:
4778 case LoongArch::X86DEC_D:
4779 case LoongArch::X86DEC_H:
4780 case LoongArch::X86DEC_W:
4781 case LoongArch::X86INC_B:
4782 case LoongArch::X86INC_D:
4783 case LoongArch::X86INC_H:
4784 case LoongArch::X86INC_W: {
4785 // op: rj
4786 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4787 op &= UINT64_C(31);
4788 op <<= 5;
4789 Value |= op;
4790 break;
4791 }
4792 case LoongArch::BITREV_4B:
4793 case LoongArch::BITREV_8B:
4794 case LoongArch::BITREV_D:
4795 case LoongArch::BITREV_W:
4796 case LoongArch::CLO_D:
4797 case LoongArch::CLO_W:
4798 case LoongArch::CLZ_D:
4799 case LoongArch::CLZ_W:
4800 case LoongArch::CPUCFG:
4801 case LoongArch::CTO_D:
4802 case LoongArch::CTO_W:
4803 case LoongArch::CTZ_D:
4804 case LoongArch::CTZ_W:
4805 case LoongArch::EXT_W_B:
4806 case LoongArch::EXT_W_H:
4807 case LoongArch::IOCSRRD_B:
4808 case LoongArch::IOCSRRD_D:
4809 case LoongArch::IOCSRRD_H:
4810 case LoongArch::IOCSRRD_W:
4811 case LoongArch::IOCSRWR_B:
4812 case LoongArch::IOCSRWR_D:
4813 case LoongArch::IOCSRWR_H:
4814 case LoongArch::IOCSRWR_W:
4815 case LoongArch::LLACQ_D:
4816 case LoongArch::LLACQ_W:
4817 case LoongArch::RDTIMEH_W:
4818 case LoongArch::RDTIMEL_W:
4819 case LoongArch::RDTIME_D:
4820 case LoongArch::REVB_2H:
4821 case LoongArch::REVB_2W:
4822 case LoongArch::REVB_4H:
4823 case LoongArch::REVB_D:
4824 case LoongArch::REVH_2W:
4825 case LoongArch::REVH_D:
4826 case LoongArch::SETX86LOOPE:
4827 case LoongArch::SETX86LOOPNE: {
4828 // op: rj
4829 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4830 op &= UINT64_C(31);
4831 op <<= 5;
4832 Value |= op;
4833 // op: rd
4834 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4835 op &= UINT64_C(31);
4836 Value |= op;
4837 break;
4838 }
4839 case LoongArch::MOVGR2SCR: {
4840 // op: rj
4841 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4842 op &= UINT64_C(31);
4843 op <<= 5;
4844 Value |= op;
4845 // op: sd
4846 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4847 op &= UINT64_C(3);
4848 Value |= op;
4849 break;
4850 }
4851 case LoongArch::VREPLGR2VR_B:
4852 case LoongArch::VREPLGR2VR_D:
4853 case LoongArch::VREPLGR2VR_H:
4854 case LoongArch::VREPLGR2VR_W: {
4855 // op: rj
4856 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4857 op &= UINT64_C(31);
4858 op <<= 5;
4859 Value |= op;
4860 // op: vd
4861 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4862 op &= UINT64_C(31);
4863 Value |= op;
4864 break;
4865 }
4866 case LoongArch::XVREPLGR2VR_B:
4867 case LoongArch::XVREPLGR2VR_D:
4868 case LoongArch::XVREPLGR2VR_H:
4869 case LoongArch::XVREPLGR2VR_W: {
4870 // op: rj
4871 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4872 op &= UINT64_C(31);
4873 op <<= 5;
4874 Value |= op;
4875 // op: xd
4876 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4877 op &= UINT64_C(31);
4878 Value |= op;
4879 break;
4880 }
4881 case LoongArch::SCREL_D:
4882 case LoongArch::SCREL_W: {
4883 // op: rj
4884 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4885 op &= UINT64_C(31);
4886 op <<= 5;
4887 Value |= op;
4888 // op: rd
4889 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4890 op &= UINT64_C(31);
4891 Value |= op;
4892 break;
4893 }
4894 case LoongArch::INVTLB: {
4895 // op: rk
4896 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4897 op &= UINT64_C(31);
4898 op <<= 10;
4899 Value |= op;
4900 // op: rj
4901 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4902 op &= UINT64_C(31);
4903 op <<= 5;
4904 Value |= op;
4905 // op: op
4906 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4907 op &= UINT64_C(31);
4908 Value |= op;
4909 break;
4910 }
4911 case LoongArch::ASRTGT_D:
4912 case LoongArch::ASRTLE_D:
4913 case LoongArch::X86ADC_B:
4914 case LoongArch::X86ADC_D:
4915 case LoongArch::X86ADC_H:
4916 case LoongArch::X86ADC_W:
4917 case LoongArch::X86ADD_B:
4918 case LoongArch::X86ADD_D:
4919 case LoongArch::X86ADD_DU:
4920 case LoongArch::X86ADD_H:
4921 case LoongArch::X86ADD_W:
4922 case LoongArch::X86ADD_WU:
4923 case LoongArch::X86AND_B:
4924 case LoongArch::X86AND_D:
4925 case LoongArch::X86AND_H:
4926 case LoongArch::X86AND_W:
4927 case LoongArch::X86MUL_B:
4928 case LoongArch::X86MUL_BU:
4929 case LoongArch::X86MUL_D:
4930 case LoongArch::X86MUL_DU:
4931 case LoongArch::X86MUL_H:
4932 case LoongArch::X86MUL_HU:
4933 case LoongArch::X86MUL_W:
4934 case LoongArch::X86MUL_WU:
4935 case LoongArch::X86OR_B:
4936 case LoongArch::X86OR_D:
4937 case LoongArch::X86OR_H:
4938 case LoongArch::X86OR_W:
4939 case LoongArch::X86RCL_B:
4940 case LoongArch::X86RCL_D:
4941 case LoongArch::X86RCL_H:
4942 case LoongArch::X86RCL_W:
4943 case LoongArch::X86RCR_B:
4944 case LoongArch::X86RCR_D:
4945 case LoongArch::X86RCR_H:
4946 case LoongArch::X86RCR_W:
4947 case LoongArch::X86ROTL_B:
4948 case LoongArch::X86ROTL_D:
4949 case LoongArch::X86ROTL_H:
4950 case LoongArch::X86ROTL_W:
4951 case LoongArch::X86ROTR_B:
4952 case LoongArch::X86ROTR_D:
4953 case LoongArch::X86ROTR_H:
4954 case LoongArch::X86ROTR_W:
4955 case LoongArch::X86SBC_B:
4956 case LoongArch::X86SBC_D:
4957 case LoongArch::X86SBC_H:
4958 case LoongArch::X86SBC_W:
4959 case LoongArch::X86SLL_B:
4960 case LoongArch::X86SLL_D:
4961 case LoongArch::X86SLL_H:
4962 case LoongArch::X86SLL_W:
4963 case LoongArch::X86SRA_B:
4964 case LoongArch::X86SRA_D:
4965 case LoongArch::X86SRA_H:
4966 case LoongArch::X86SRA_W:
4967 case LoongArch::X86SRL_B:
4968 case LoongArch::X86SRL_D:
4969 case LoongArch::X86SRL_H:
4970 case LoongArch::X86SRL_W:
4971 case LoongArch::X86SUB_B:
4972 case LoongArch::X86SUB_D:
4973 case LoongArch::X86SUB_DU:
4974 case LoongArch::X86SUB_H:
4975 case LoongArch::X86SUB_W:
4976 case LoongArch::X86SUB_WU:
4977 case LoongArch::X86XOR_B:
4978 case LoongArch::X86XOR_D:
4979 case LoongArch::X86XOR_H:
4980 case LoongArch::X86XOR_W: {
4981 // op: rk
4982 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4983 op &= UINT64_C(31);
4984 op <<= 10;
4985 Value |= op;
4986 // op: rj
4987 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4988 op &= UINT64_C(31);
4989 op <<= 5;
4990 Value |= op;
4991 break;
4992 }
4993 case LoongArch::AMADD_B:
4994 case LoongArch::AMADD_D:
4995 case LoongArch::AMADD_H:
4996 case LoongArch::AMADD_W:
4997 case LoongArch::AMADD__DB_B:
4998 case LoongArch::AMADD__DB_D:
4999 case LoongArch::AMADD__DB_H:
5000 case LoongArch::AMADD__DB_W:
5001 case LoongArch::AMAND_D:
5002 case LoongArch::AMAND_W:
5003 case LoongArch::AMAND__DB_D:
5004 case LoongArch::AMAND__DB_W:
5005 case LoongArch::AMMAX_D:
5006 case LoongArch::AMMAX_DU:
5007 case LoongArch::AMMAX_W:
5008 case LoongArch::AMMAX_WU:
5009 case LoongArch::AMMAX__DB_D:
5010 case LoongArch::AMMAX__DB_DU:
5011 case LoongArch::AMMAX__DB_W:
5012 case LoongArch::AMMAX__DB_WU:
5013 case LoongArch::AMMIN_D:
5014 case LoongArch::AMMIN_DU:
5015 case LoongArch::AMMIN_W:
5016 case LoongArch::AMMIN_WU:
5017 case LoongArch::AMMIN__DB_D:
5018 case LoongArch::AMMIN__DB_DU:
5019 case LoongArch::AMMIN__DB_W:
5020 case LoongArch::AMMIN__DB_WU:
5021 case LoongArch::AMOR_D:
5022 case LoongArch::AMOR_W:
5023 case LoongArch::AMOR__DB_D:
5024 case LoongArch::AMOR__DB_W:
5025 case LoongArch::AMSWAP_B:
5026 case LoongArch::AMSWAP_D:
5027 case LoongArch::AMSWAP_H:
5028 case LoongArch::AMSWAP_W:
5029 case LoongArch::AMSWAP__DB_B:
5030 case LoongArch::AMSWAP__DB_D:
5031 case LoongArch::AMSWAP__DB_H:
5032 case LoongArch::AMSWAP__DB_W:
5033 case LoongArch::AMXOR_D:
5034 case LoongArch::AMXOR_W:
5035 case LoongArch::AMXOR__DB_D:
5036 case LoongArch::AMXOR__DB_W: {
5037 // op: rk
5038 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5039 op &= UINT64_C(31);
5040 op <<= 10;
5041 Value |= op;
5042 // op: rj
5043 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5044 op &= UINT64_C(31);
5045 op <<= 5;
5046 Value |= op;
5047 // op: rd
5048 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5049 op &= UINT64_C(31);
5050 Value |= op;
5051 break;
5052 }
5053 case LoongArch::FLDGT_D:
5054 case LoongArch::FLDGT_S:
5055 case LoongArch::FLDLE_D:
5056 case LoongArch::FLDLE_S:
5057 case LoongArch::FLDX_D:
5058 case LoongArch::FLDX_S:
5059 case LoongArch::FSTGT_D:
5060 case LoongArch::FSTGT_S:
5061 case LoongArch::FSTLE_D:
5062 case LoongArch::FSTLE_S:
5063 case LoongArch::FSTX_D:
5064 case LoongArch::FSTX_S: {
5065 // op: rk
5066 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5067 op &= UINT64_C(31);
5068 op <<= 10;
5069 Value |= op;
5070 // op: rj
5071 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5072 op &= UINT64_C(31);
5073 op <<= 5;
5074 Value |= op;
5075 // op: fd
5076 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5077 op &= UINT64_C(31);
5078 Value |= op;
5079 break;
5080 }
5081 case LoongArch::PRELDX: {
5082 // op: rk
5083 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5084 op &= UINT64_C(31);
5085 op <<= 10;
5086 Value |= op;
5087 // op: rj
5088 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5089 op &= UINT64_C(31);
5090 op <<= 5;
5091 Value |= op;
5092 // op: imm5
5093 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5094 op &= UINT64_C(31);
5095 Value |= op;
5096 break;
5097 }
5098 case LoongArch::ADC_B:
5099 case LoongArch::ADC_D:
5100 case LoongArch::ADC_H:
5101 case LoongArch::ADC_W:
5102 case LoongArch::ADD_D:
5103 case LoongArch::ADD_W:
5104 case LoongArch::AND:
5105 case LoongArch::ANDN:
5106 case LoongArch::CRCC_W_B_W:
5107 case LoongArch::CRCC_W_D_W:
5108 case LoongArch::CRCC_W_H_W:
5109 case LoongArch::CRCC_W_W_W:
5110 case LoongArch::CRC_W_B_W:
5111 case LoongArch::CRC_W_D_W:
5112 case LoongArch::CRC_W_H_W:
5113 case LoongArch::CRC_W_W_W:
5114 case LoongArch::DIV_D:
5115 case LoongArch::DIV_DU:
5116 case LoongArch::DIV_W:
5117 case LoongArch::DIV_WU:
5118 case LoongArch::LDGT_B:
5119 case LoongArch::LDGT_D:
5120 case LoongArch::LDGT_H:
5121 case LoongArch::LDGT_W:
5122 case LoongArch::LDLE_B:
5123 case LoongArch::LDLE_D:
5124 case LoongArch::LDLE_H:
5125 case LoongArch::LDLE_W:
5126 case LoongArch::LDX_B:
5127 case LoongArch::LDX_BU:
5128 case LoongArch::LDX_D:
5129 case LoongArch::LDX_H:
5130 case LoongArch::LDX_HU:
5131 case LoongArch::LDX_W:
5132 case LoongArch::LDX_WU:
5133 case LoongArch::MASKEQZ:
5134 case LoongArch::MASKNEZ:
5135 case LoongArch::MOD_D:
5136 case LoongArch::MOD_DU:
5137 case LoongArch::MOD_W:
5138 case LoongArch::MOD_WU:
5139 case LoongArch::MULH_D:
5140 case LoongArch::MULH_DU:
5141 case LoongArch::MULH_W:
5142 case LoongArch::MULH_WU:
5143 case LoongArch::MULW_D_W:
5144 case LoongArch::MULW_D_WU:
5145 case LoongArch::MUL_D:
5146 case LoongArch::MUL_W:
5147 case LoongArch::NOR:
5148 case LoongArch::OR:
5149 case LoongArch::ORN:
5150 case LoongArch::RCR_B:
5151 case LoongArch::RCR_D:
5152 case LoongArch::RCR_H:
5153 case LoongArch::RCR_W:
5154 case LoongArch::ROTR_B:
5155 case LoongArch::ROTR_D:
5156 case LoongArch::ROTR_H:
5157 case LoongArch::ROTR_W:
5158 case LoongArch::SBC_B:
5159 case LoongArch::SBC_D:
5160 case LoongArch::SBC_H:
5161 case LoongArch::SBC_W:
5162 case LoongArch::SLL_D:
5163 case LoongArch::SLL_W:
5164 case LoongArch::SLT:
5165 case LoongArch::SLTU:
5166 case LoongArch::SRA_D:
5167 case LoongArch::SRA_W:
5168 case LoongArch::SRL_D:
5169 case LoongArch::SRL_W:
5170 case LoongArch::STGT_B:
5171 case LoongArch::STGT_D:
5172 case LoongArch::STGT_H:
5173 case LoongArch::STGT_W:
5174 case LoongArch::STLE_B:
5175 case LoongArch::STLE_D:
5176 case LoongArch::STLE_H:
5177 case LoongArch::STLE_W:
5178 case LoongArch::STX_B:
5179 case LoongArch::STX_D:
5180 case LoongArch::STX_H:
5181 case LoongArch::STX_W:
5182 case LoongArch::SUB_D:
5183 case LoongArch::SUB_W:
5184 case LoongArch::XOR: {
5185 // op: rk
5186 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5187 op &= UINT64_C(31);
5188 op <<= 10;
5189 Value |= op;
5190 // op: rj
5191 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5192 op &= UINT64_C(31);
5193 op <<= 5;
5194 Value |= op;
5195 // op: rd
5196 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5197 op &= UINT64_C(31);
5198 Value |= op;
5199 break;
5200 }
5201 case LoongArch::VLDX:
5202 case LoongArch::VSTX: {
5203 // op: rk
5204 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5205 op &= UINT64_C(31);
5206 op <<= 10;
5207 Value |= op;
5208 // op: rj
5209 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5210 op &= UINT64_C(31);
5211 op <<= 5;
5212 Value |= op;
5213 // op: vd
5214 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5215 op &= UINT64_C(31);
5216 Value |= op;
5217 break;
5218 }
5219 case LoongArch::XVLDX:
5220 case LoongArch::XVSTX: {
5221 // op: rk
5222 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5223 op &= UINT64_C(31);
5224 op <<= 10;
5225 Value |= op;
5226 // op: rj
5227 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5228 op &= UINT64_C(31);
5229 op <<= 5;
5230 Value |= op;
5231 // op: xd
5232 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5233 op &= UINT64_C(31);
5234 Value |= op;
5235 break;
5236 }
5237 case LoongArch::AMCAS_B:
5238 case LoongArch::AMCAS_D:
5239 case LoongArch::AMCAS_H:
5240 case LoongArch::AMCAS_W:
5241 case LoongArch::AMCAS__DB_B:
5242 case LoongArch::AMCAS__DB_D:
5243 case LoongArch::AMCAS__DB_H:
5244 case LoongArch::AMCAS__DB_W:
5245 case LoongArch::SC_Q: {
5246 // op: rk
5247 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5248 op &= UINT64_C(31);
5249 op <<= 10;
5250 Value |= op;
5251 // op: rj
5252 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
5253 op &= UINT64_C(31);
5254 op <<= 5;
5255 Value |= op;
5256 // op: rd
5257 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5258 op &= UINT64_C(31);
5259 Value |= op;
5260 break;
5261 }
5262 case LoongArch::VREPLVE_B:
5263 case LoongArch::VREPLVE_D:
5264 case LoongArch::VREPLVE_H:
5265 case LoongArch::VREPLVE_W: {
5266 // op: rk
5267 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5268 op &= UINT64_C(31);
5269 op <<= 10;
5270 Value |= op;
5271 // op: vj
5272 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5273 op &= UINT64_C(31);
5274 op <<= 5;
5275 Value |= op;
5276 // op: vd
5277 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5278 op &= UINT64_C(31);
5279 Value |= op;
5280 break;
5281 }
5282 case LoongArch::XVREPLVE_B:
5283 case LoongArch::XVREPLVE_D:
5284 case LoongArch::XVREPLVE_H:
5285 case LoongArch::XVREPLVE_W: {
5286 // op: rk
5287 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5288 op &= UINT64_C(31);
5289 op <<= 10;
5290 Value |= op;
5291 // op: xj
5292 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5293 op &= UINT64_C(31);
5294 op <<= 5;
5295 Value |= op;
5296 // op: xd
5297 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5298 op &= UINT64_C(31);
5299 Value |= op;
5300 break;
5301 }
5302 case LoongArch::LDPTE: {
5303 // op: seq
5304 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5305 op &= UINT64_C(255);
5306 op <<= 10;
5307 Value |= op;
5308 // op: rj
5309 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5310 op &= UINT64_C(31);
5311 op <<= 5;
5312 Value |= op;
5313 break;
5314 }
5315 case LoongArch::MOVSCR2GR: {
5316 // op: sj
5317 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5318 op &= UINT64_C(3);
5319 op <<= 5;
5320 Value |= op;
5321 // op: rd
5322 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5323 op &= UINT64_C(31);
5324 Value |= op;
5325 break;
5326 }
5327 case LoongArch::FMOV_D:
5328 case LoongArch::FMOV_S:
5329 case LoongArch::MOVCF2FR_xS:
5330 case LoongArch::MOVCF2GR:
5331 case LoongArch::MOVFCSR2GR:
5332 case LoongArch::MOVFR2CF_xS:
5333 case LoongArch::MOVFR2GR_D:
5334 case LoongArch::MOVFR2GR_S:
5335 case LoongArch::MOVFR2GR_S_64:
5336 case LoongArch::MOVFRH2GR_S:
5337 case LoongArch::MOVGR2CF:
5338 case LoongArch::MOVGR2FCSR:
5339 case LoongArch::MOVGR2FR_D:
5340 case LoongArch::MOVGR2FR_W:
5341 case LoongArch::MOVGR2FR_W_64: {
5342 // op: src
5343 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5344 op &= UINT64_C(31);
5345 op <<= 5;
5346 Value |= op;
5347 // op: dst
5348 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5349 op &= UINT64_C(31);
5350 Value |= op;
5351 break;
5352 }
5353 case LoongArch::MOVGR2FRH_W: {
5354 // op: src
5355 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5356 op &= UINT64_C(31);
5357 op <<= 5;
5358 Value |= op;
5359 // op: dst
5360 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5361 op &= UINT64_C(31);
5362 Value |= op;
5363 break;
5364 }
5365 case LoongArch::VBITSEL_V:
5366 case LoongArch::VFMADD_D:
5367 case LoongArch::VFMADD_S:
5368 case LoongArch::VFMSUB_D:
5369 case LoongArch::VFMSUB_S:
5370 case LoongArch::VFNMADD_D:
5371 case LoongArch::VFNMADD_S:
5372 case LoongArch::VFNMSUB_D:
5373 case LoongArch::VFNMSUB_S:
5374 case LoongArch::VSHUF_B: {
5375 // op: va
5376 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
5377 op &= UINT64_C(31);
5378 op <<= 15;
5379 Value |= op;
5380 // op: vk
5381 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5382 op &= UINT64_C(31);
5383 op <<= 10;
5384 Value |= op;
5385 // op: vj
5386 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5387 op &= UINT64_C(31);
5388 op <<= 5;
5389 Value |= op;
5390 // op: vd
5391 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5392 op &= UINT64_C(31);
5393 Value |= op;
5394 break;
5395 }
5396 case LoongArch::VSETALLNEZ_B:
5397 case LoongArch::VSETALLNEZ_D:
5398 case LoongArch::VSETALLNEZ_H:
5399 case LoongArch::VSETALLNEZ_W:
5400 case LoongArch::VSETANYEQZ_B:
5401 case LoongArch::VSETANYEQZ_D:
5402 case LoongArch::VSETANYEQZ_H:
5403 case LoongArch::VSETANYEQZ_W:
5404 case LoongArch::VSETEQZ_V:
5405 case LoongArch::VSETNEZ_V: {
5406 // op: vj
5407 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5408 op &= UINT64_C(31);
5409 op <<= 5;
5410 Value |= op;
5411 // op: cd
5412 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5413 op &= UINT64_C(7);
5414 Value |= op;
5415 break;
5416 }
5417 case LoongArch::VCLO_B:
5418 case LoongArch::VCLO_D:
5419 case LoongArch::VCLO_H:
5420 case LoongArch::VCLO_W:
5421 case LoongArch::VCLZ_B:
5422 case LoongArch::VCLZ_D:
5423 case LoongArch::VCLZ_H:
5424 case LoongArch::VCLZ_W:
5425 case LoongArch::VEXTH_DU_WU:
5426 case LoongArch::VEXTH_D_W:
5427 case LoongArch::VEXTH_HU_BU:
5428 case LoongArch::VEXTH_H_B:
5429 case LoongArch::VEXTH_QU_DU:
5430 case LoongArch::VEXTH_Q_D:
5431 case LoongArch::VEXTH_WU_HU:
5432 case LoongArch::VEXTH_W_H:
5433 case LoongArch::VEXTL_QU_DU:
5434 case LoongArch::VEXTL_Q_D:
5435 case LoongArch::VFCLASS_D:
5436 case LoongArch::VFCLASS_S:
5437 case LoongArch::VFCVTH_D_S:
5438 case LoongArch::VFCVTH_S_H:
5439 case LoongArch::VFCVTL_D_S:
5440 case LoongArch::VFCVTL_S_H:
5441 case LoongArch::VFFINTH_D_W:
5442 case LoongArch::VFFINTL_D_W:
5443 case LoongArch::VFFINT_D_L:
5444 case LoongArch::VFFINT_D_LU:
5445 case LoongArch::VFFINT_S_W:
5446 case LoongArch::VFFINT_S_WU:
5447 case LoongArch::VFLOGB_D:
5448 case LoongArch::VFLOGB_S:
5449 case LoongArch::VFRECIPE_D:
5450 case LoongArch::VFRECIPE_S:
5451 case LoongArch::VFRECIP_D:
5452 case LoongArch::VFRECIP_S:
5453 case LoongArch::VFRINTRM_D:
5454 case LoongArch::VFRINTRM_S:
5455 case LoongArch::VFRINTRNE_D:
5456 case LoongArch::VFRINTRNE_S:
5457 case LoongArch::VFRINTRP_D:
5458 case LoongArch::VFRINTRP_S:
5459 case LoongArch::VFRINTRZ_D:
5460 case LoongArch::VFRINTRZ_S:
5461 case LoongArch::VFRINT_D:
5462 case LoongArch::VFRINT_S:
5463 case LoongArch::VFRSQRTE_D:
5464 case LoongArch::VFRSQRTE_S:
5465 case LoongArch::VFRSQRT_D:
5466 case LoongArch::VFRSQRT_S:
5467 case LoongArch::VFSQRT_D:
5468 case LoongArch::VFSQRT_S:
5469 case LoongArch::VFTINTH_L_S:
5470 case LoongArch::VFTINTL_L_S:
5471 case LoongArch::VFTINTRMH_L_S:
5472 case LoongArch::VFTINTRML_L_S:
5473 case LoongArch::VFTINTRM_L_D:
5474 case LoongArch::VFTINTRM_W_S:
5475 case LoongArch::VFTINTRNEH_L_S:
5476 case LoongArch::VFTINTRNEL_L_S:
5477 case LoongArch::VFTINTRNE_L_D:
5478 case LoongArch::VFTINTRNE_W_S:
5479 case LoongArch::VFTINTRPH_L_S:
5480 case LoongArch::VFTINTRPL_L_S:
5481 case LoongArch::VFTINTRP_L_D:
5482 case LoongArch::VFTINTRP_W_S:
5483 case LoongArch::VFTINTRZH_L_S:
5484 case LoongArch::VFTINTRZL_L_S:
5485 case LoongArch::VFTINTRZ_LU_D:
5486 case LoongArch::VFTINTRZ_L_D:
5487 case LoongArch::VFTINTRZ_WU_S:
5488 case LoongArch::VFTINTRZ_W_S:
5489 case LoongArch::VFTINT_LU_D:
5490 case LoongArch::VFTINT_L_D:
5491 case LoongArch::VFTINT_WU_S:
5492 case LoongArch::VFTINT_W_S:
5493 case LoongArch::VMSKGEZ_B:
5494 case LoongArch::VMSKLTZ_B:
5495 case LoongArch::VMSKLTZ_D:
5496 case LoongArch::VMSKLTZ_H:
5497 case LoongArch::VMSKLTZ_W:
5498 case LoongArch::VMSKNZ_B:
5499 case LoongArch::VNEG_B:
5500 case LoongArch::VNEG_D:
5501 case LoongArch::VNEG_H:
5502 case LoongArch::VNEG_W:
5503 case LoongArch::VPCNT_B:
5504 case LoongArch::VPCNT_D:
5505 case LoongArch::VPCNT_H:
5506 case LoongArch::VPCNT_W: {
5507 // op: vj
5508 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5509 op &= UINT64_C(31);
5510 op <<= 5;
5511 Value |= op;
5512 // op: vd
5513 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5514 op &= UINT64_C(31);
5515 Value |= op;
5516 break;
5517 }
5518 case LoongArch::VABSD_B:
5519 case LoongArch::VABSD_BU:
5520 case LoongArch::VABSD_D:
5521 case LoongArch::VABSD_DU:
5522 case LoongArch::VABSD_H:
5523 case LoongArch::VABSD_HU:
5524 case LoongArch::VABSD_W:
5525 case LoongArch::VABSD_WU:
5526 case LoongArch::VADDA_B:
5527 case LoongArch::VADDA_D:
5528 case LoongArch::VADDA_H:
5529 case LoongArch::VADDA_W:
5530 case LoongArch::VADDWEV_D_W:
5531 case LoongArch::VADDWEV_D_WU:
5532 case LoongArch::VADDWEV_D_WU_W:
5533 case LoongArch::VADDWEV_H_B:
5534 case LoongArch::VADDWEV_H_BU:
5535 case LoongArch::VADDWEV_H_BU_B:
5536 case LoongArch::VADDWEV_Q_D:
5537 case LoongArch::VADDWEV_Q_DU:
5538 case LoongArch::VADDWEV_Q_DU_D:
5539 case LoongArch::VADDWEV_W_H:
5540 case LoongArch::VADDWEV_W_HU:
5541 case LoongArch::VADDWEV_W_HU_H:
5542 case LoongArch::VADDWOD_D_W:
5543 case LoongArch::VADDWOD_D_WU:
5544 case LoongArch::VADDWOD_D_WU_W:
5545 case LoongArch::VADDWOD_H_B:
5546 case LoongArch::VADDWOD_H_BU:
5547 case LoongArch::VADDWOD_H_BU_B:
5548 case LoongArch::VADDWOD_Q_D:
5549 case LoongArch::VADDWOD_Q_DU:
5550 case LoongArch::VADDWOD_Q_DU_D:
5551 case LoongArch::VADDWOD_W_H:
5552 case LoongArch::VADDWOD_W_HU:
5553 case LoongArch::VADDWOD_W_HU_H:
5554 case LoongArch::VADD_B:
5555 case LoongArch::VADD_D:
5556 case LoongArch::VADD_H:
5557 case LoongArch::VADD_Q:
5558 case LoongArch::VADD_W:
5559 case LoongArch::VANDN_V:
5560 case LoongArch::VAND_V:
5561 case LoongArch::VAVGR_B:
5562 case LoongArch::VAVGR_BU:
5563 case LoongArch::VAVGR_D:
5564 case LoongArch::VAVGR_DU:
5565 case LoongArch::VAVGR_H:
5566 case LoongArch::VAVGR_HU:
5567 case LoongArch::VAVGR_W:
5568 case LoongArch::VAVGR_WU:
5569 case LoongArch::VAVG_B:
5570 case LoongArch::VAVG_BU:
5571 case LoongArch::VAVG_D:
5572 case LoongArch::VAVG_DU:
5573 case LoongArch::VAVG_H:
5574 case LoongArch::VAVG_HU:
5575 case LoongArch::VAVG_W:
5576 case LoongArch::VAVG_WU:
5577 case LoongArch::VBITCLR_B:
5578 case LoongArch::VBITCLR_D:
5579 case LoongArch::VBITCLR_H:
5580 case LoongArch::VBITCLR_W:
5581 case LoongArch::VBITREV_B:
5582 case LoongArch::VBITREV_D:
5583 case LoongArch::VBITREV_H:
5584 case LoongArch::VBITREV_W:
5585 case LoongArch::VBITSET_B:
5586 case LoongArch::VBITSET_D:
5587 case LoongArch::VBITSET_H:
5588 case LoongArch::VBITSET_W:
5589 case LoongArch::VDIV_B:
5590 case LoongArch::VDIV_BU:
5591 case LoongArch::VDIV_D:
5592 case LoongArch::VDIV_DU:
5593 case LoongArch::VDIV_H:
5594 case LoongArch::VDIV_HU:
5595 case LoongArch::VDIV_W:
5596 case LoongArch::VDIV_WU:
5597 case LoongArch::VFADD_D:
5598 case LoongArch::VFADD_S:
5599 case LoongArch::VFCMP_CAF_D:
5600 case LoongArch::VFCMP_CAF_S:
5601 case LoongArch::VFCMP_CEQ_D:
5602 case LoongArch::VFCMP_CEQ_S:
5603 case LoongArch::VFCMP_CLE_D:
5604 case LoongArch::VFCMP_CLE_S:
5605 case LoongArch::VFCMP_CLT_D:
5606 case LoongArch::VFCMP_CLT_S:
5607 case LoongArch::VFCMP_CNE_D:
5608 case LoongArch::VFCMP_CNE_S:
5609 case LoongArch::VFCMP_COR_D:
5610 case LoongArch::VFCMP_COR_S:
5611 case LoongArch::VFCMP_CUEQ_D:
5612 case LoongArch::VFCMP_CUEQ_S:
5613 case LoongArch::VFCMP_CULE_D:
5614 case LoongArch::VFCMP_CULE_S:
5615 case LoongArch::VFCMP_CULT_D:
5616 case LoongArch::VFCMP_CULT_S:
5617 case LoongArch::VFCMP_CUNE_D:
5618 case LoongArch::VFCMP_CUNE_S:
5619 case LoongArch::VFCMP_CUN_D:
5620 case LoongArch::VFCMP_CUN_S:
5621 case LoongArch::VFCMP_SAF_D:
5622 case LoongArch::VFCMP_SAF_S:
5623 case LoongArch::VFCMP_SEQ_D:
5624 case LoongArch::VFCMP_SEQ_S:
5625 case LoongArch::VFCMP_SLE_D:
5626 case LoongArch::VFCMP_SLE_S:
5627 case LoongArch::VFCMP_SLT_D:
5628 case LoongArch::VFCMP_SLT_S:
5629 case LoongArch::VFCMP_SNE_D:
5630 case LoongArch::VFCMP_SNE_S:
5631 case LoongArch::VFCMP_SOR_D:
5632 case LoongArch::VFCMP_SOR_S:
5633 case LoongArch::VFCMP_SUEQ_D:
5634 case LoongArch::VFCMP_SUEQ_S:
5635 case LoongArch::VFCMP_SULE_D:
5636 case LoongArch::VFCMP_SULE_S:
5637 case LoongArch::VFCMP_SULT_D:
5638 case LoongArch::VFCMP_SULT_S:
5639 case LoongArch::VFCMP_SUNE_D:
5640 case LoongArch::VFCMP_SUNE_S:
5641 case LoongArch::VFCMP_SUN_D:
5642 case LoongArch::VFCMP_SUN_S:
5643 case LoongArch::VFCVT_H_S:
5644 case LoongArch::VFCVT_S_D:
5645 case LoongArch::VFDIV_D:
5646 case LoongArch::VFDIV_S:
5647 case LoongArch::VFFINT_S_L:
5648 case LoongArch::VFMAXA_D:
5649 case LoongArch::VFMAXA_S:
5650 case LoongArch::VFMAX_D:
5651 case LoongArch::VFMAX_S:
5652 case LoongArch::VFMINA_D:
5653 case LoongArch::VFMINA_S:
5654 case LoongArch::VFMIN_D:
5655 case LoongArch::VFMIN_S:
5656 case LoongArch::VFMUL_D:
5657 case LoongArch::VFMUL_S:
5658 case LoongArch::VFSUB_D:
5659 case LoongArch::VFSUB_S:
5660 case LoongArch::VFTINTRM_W_D:
5661 case LoongArch::VFTINTRNE_W_D:
5662 case LoongArch::VFTINTRP_W_D:
5663 case LoongArch::VFTINTRZ_W_D:
5664 case LoongArch::VFTINT_W_D:
5665 case LoongArch::VHADDW_DU_WU:
5666 case LoongArch::VHADDW_D_W:
5667 case LoongArch::VHADDW_HU_BU:
5668 case LoongArch::VHADDW_H_B:
5669 case LoongArch::VHADDW_QU_DU:
5670 case LoongArch::VHADDW_Q_D:
5671 case LoongArch::VHADDW_WU_HU:
5672 case LoongArch::VHADDW_W_H:
5673 case LoongArch::VHSUBW_DU_WU:
5674 case LoongArch::VHSUBW_D_W:
5675 case LoongArch::VHSUBW_HU_BU:
5676 case LoongArch::VHSUBW_H_B:
5677 case LoongArch::VHSUBW_QU_DU:
5678 case LoongArch::VHSUBW_Q_D:
5679 case LoongArch::VHSUBW_WU_HU:
5680 case LoongArch::VHSUBW_W_H:
5681 case LoongArch::VILVH_B:
5682 case LoongArch::VILVH_D:
5683 case LoongArch::VILVH_H:
5684 case LoongArch::VILVH_W:
5685 case LoongArch::VILVL_B:
5686 case LoongArch::VILVL_D:
5687 case LoongArch::VILVL_H:
5688 case LoongArch::VILVL_W:
5689 case LoongArch::VMAX_B:
5690 case LoongArch::VMAX_BU:
5691 case LoongArch::VMAX_D:
5692 case LoongArch::VMAX_DU:
5693 case LoongArch::VMAX_H:
5694 case LoongArch::VMAX_HU:
5695 case LoongArch::VMAX_W:
5696 case LoongArch::VMAX_WU:
5697 case LoongArch::VMIN_B:
5698 case LoongArch::VMIN_BU:
5699 case LoongArch::VMIN_D:
5700 case LoongArch::VMIN_DU:
5701 case LoongArch::VMIN_H:
5702 case LoongArch::VMIN_HU:
5703 case LoongArch::VMIN_W:
5704 case LoongArch::VMIN_WU:
5705 case LoongArch::VMOD_B:
5706 case LoongArch::VMOD_BU:
5707 case LoongArch::VMOD_D:
5708 case LoongArch::VMOD_DU:
5709 case LoongArch::VMOD_H:
5710 case LoongArch::VMOD_HU:
5711 case LoongArch::VMOD_W:
5712 case LoongArch::VMOD_WU:
5713 case LoongArch::VMUH_B:
5714 case LoongArch::VMUH_BU:
5715 case LoongArch::VMUH_D:
5716 case LoongArch::VMUH_DU:
5717 case LoongArch::VMUH_H:
5718 case LoongArch::VMUH_HU:
5719 case LoongArch::VMUH_W:
5720 case LoongArch::VMUH_WU:
5721 case LoongArch::VMULWEV_D_W:
5722 case LoongArch::VMULWEV_D_WU:
5723 case LoongArch::VMULWEV_D_WU_W:
5724 case LoongArch::VMULWEV_H_B:
5725 case LoongArch::VMULWEV_H_BU:
5726 case LoongArch::VMULWEV_H_BU_B:
5727 case LoongArch::VMULWEV_Q_D:
5728 case LoongArch::VMULWEV_Q_DU:
5729 case LoongArch::VMULWEV_Q_DU_D:
5730 case LoongArch::VMULWEV_W_H:
5731 case LoongArch::VMULWEV_W_HU:
5732 case LoongArch::VMULWEV_W_HU_H:
5733 case LoongArch::VMULWOD_D_W:
5734 case LoongArch::VMULWOD_D_WU:
5735 case LoongArch::VMULWOD_D_WU_W:
5736 case LoongArch::VMULWOD_H_B:
5737 case LoongArch::VMULWOD_H_BU:
5738 case LoongArch::VMULWOD_H_BU_B:
5739 case LoongArch::VMULWOD_Q_D:
5740 case LoongArch::VMULWOD_Q_DU:
5741 case LoongArch::VMULWOD_Q_DU_D:
5742 case LoongArch::VMULWOD_W_H:
5743 case LoongArch::VMULWOD_W_HU:
5744 case LoongArch::VMULWOD_W_HU_H:
5745 case LoongArch::VMUL_B:
5746 case LoongArch::VMUL_D:
5747 case LoongArch::VMUL_H:
5748 case LoongArch::VMUL_W:
5749 case LoongArch::VNOR_V:
5750 case LoongArch::VORN_V:
5751 case LoongArch::VOR_V:
5752 case LoongArch::VPACKEV_B:
5753 case LoongArch::VPACKEV_D:
5754 case LoongArch::VPACKEV_H:
5755 case LoongArch::VPACKEV_W:
5756 case LoongArch::VPACKOD_B:
5757 case LoongArch::VPACKOD_D:
5758 case LoongArch::VPACKOD_H:
5759 case LoongArch::VPACKOD_W:
5760 case LoongArch::VPICKEV_B:
5761 case LoongArch::VPICKEV_D:
5762 case LoongArch::VPICKEV_H:
5763 case LoongArch::VPICKEV_W:
5764 case LoongArch::VPICKOD_B:
5765 case LoongArch::VPICKOD_D:
5766 case LoongArch::VPICKOD_H:
5767 case LoongArch::VPICKOD_W:
5768 case LoongArch::VROTR_B:
5769 case LoongArch::VROTR_D:
5770 case LoongArch::VROTR_H:
5771 case LoongArch::VROTR_W:
5772 case LoongArch::VSADD_B:
5773 case LoongArch::VSADD_BU:
5774 case LoongArch::VSADD_D:
5775 case LoongArch::VSADD_DU:
5776 case LoongArch::VSADD_H:
5777 case LoongArch::VSADD_HU:
5778 case LoongArch::VSADD_W:
5779 case LoongArch::VSADD_WU:
5780 case LoongArch::VSEQ_B:
5781 case LoongArch::VSEQ_D:
5782 case LoongArch::VSEQ_H:
5783 case LoongArch::VSEQ_W:
5784 case LoongArch::VSIGNCOV_B:
5785 case LoongArch::VSIGNCOV_D:
5786 case LoongArch::VSIGNCOV_H:
5787 case LoongArch::VSIGNCOV_W:
5788 case LoongArch::VSLE_B:
5789 case LoongArch::VSLE_BU:
5790 case LoongArch::VSLE_D:
5791 case LoongArch::VSLE_DU:
5792 case LoongArch::VSLE_H:
5793 case LoongArch::VSLE_HU:
5794 case LoongArch::VSLE_W:
5795 case LoongArch::VSLE_WU:
5796 case LoongArch::VSLL_B:
5797 case LoongArch::VSLL_D:
5798 case LoongArch::VSLL_H:
5799 case LoongArch::VSLL_W:
5800 case LoongArch::VSLT_B:
5801 case LoongArch::VSLT_BU:
5802 case LoongArch::VSLT_D:
5803 case LoongArch::VSLT_DU:
5804 case LoongArch::VSLT_H:
5805 case LoongArch::VSLT_HU:
5806 case LoongArch::VSLT_W:
5807 case LoongArch::VSLT_WU:
5808 case LoongArch::VSRAN_B_H:
5809 case LoongArch::VSRAN_H_W:
5810 case LoongArch::VSRAN_W_D:
5811 case LoongArch::VSRARN_B_H:
5812 case LoongArch::VSRARN_H_W:
5813 case LoongArch::VSRARN_W_D:
5814 case LoongArch::VSRAR_B:
5815 case LoongArch::VSRAR_D:
5816 case LoongArch::VSRAR_H:
5817 case LoongArch::VSRAR_W:
5818 case LoongArch::VSRA_B:
5819 case LoongArch::VSRA_D:
5820 case LoongArch::VSRA_H:
5821 case LoongArch::VSRA_W:
5822 case LoongArch::VSRLN_B_H:
5823 case LoongArch::VSRLN_H_W:
5824 case LoongArch::VSRLN_W_D:
5825 case LoongArch::VSRLRN_B_H:
5826 case LoongArch::VSRLRN_H_W:
5827 case LoongArch::VSRLRN_W_D:
5828 case LoongArch::VSRLR_B:
5829 case LoongArch::VSRLR_D:
5830 case LoongArch::VSRLR_H:
5831 case LoongArch::VSRLR_W:
5832 case LoongArch::VSRL_B:
5833 case LoongArch::VSRL_D:
5834 case LoongArch::VSRL_H:
5835 case LoongArch::VSRL_W:
5836 case LoongArch::VSSRAN_BU_H:
5837 case LoongArch::VSSRAN_B_H:
5838 case LoongArch::VSSRAN_HU_W:
5839 case LoongArch::VSSRAN_H_W:
5840 case LoongArch::VSSRAN_WU_D:
5841 case LoongArch::VSSRAN_W_D:
5842 case LoongArch::VSSRARN_BU_H:
5843 case LoongArch::VSSRARN_B_H:
5844 case LoongArch::VSSRARN_HU_W:
5845 case LoongArch::VSSRARN_H_W:
5846 case LoongArch::VSSRARN_WU_D:
5847 case LoongArch::VSSRARN_W_D:
5848 case LoongArch::VSSRLN_BU_H:
5849 case LoongArch::VSSRLN_B_H:
5850 case LoongArch::VSSRLN_HU_W:
5851 case LoongArch::VSSRLN_H_W:
5852 case LoongArch::VSSRLN_WU_D:
5853 case LoongArch::VSSRLN_W_D:
5854 case LoongArch::VSSRLRN_BU_H:
5855 case LoongArch::VSSRLRN_B_H:
5856 case LoongArch::VSSRLRN_HU_W:
5857 case LoongArch::VSSRLRN_H_W:
5858 case LoongArch::VSSRLRN_WU_D:
5859 case LoongArch::VSSRLRN_W_D:
5860 case LoongArch::VSSUB_B:
5861 case LoongArch::VSSUB_BU:
5862 case LoongArch::VSSUB_D:
5863 case LoongArch::VSSUB_DU:
5864 case LoongArch::VSSUB_H:
5865 case LoongArch::VSSUB_HU:
5866 case LoongArch::VSSUB_W:
5867 case LoongArch::VSSUB_WU:
5868 case LoongArch::VSUBWEV_D_W:
5869 case LoongArch::VSUBWEV_D_WU:
5870 case LoongArch::VSUBWEV_H_B:
5871 case LoongArch::VSUBWEV_H_BU:
5872 case LoongArch::VSUBWEV_Q_D:
5873 case LoongArch::VSUBWEV_Q_DU:
5874 case LoongArch::VSUBWEV_W_H:
5875 case LoongArch::VSUBWEV_W_HU:
5876 case LoongArch::VSUBWOD_D_W:
5877 case LoongArch::VSUBWOD_D_WU:
5878 case LoongArch::VSUBWOD_H_B:
5879 case LoongArch::VSUBWOD_H_BU:
5880 case LoongArch::VSUBWOD_Q_D:
5881 case LoongArch::VSUBWOD_Q_DU:
5882 case LoongArch::VSUBWOD_W_H:
5883 case LoongArch::VSUBWOD_W_HU:
5884 case LoongArch::VSUB_B:
5885 case LoongArch::VSUB_D:
5886 case LoongArch::VSUB_H:
5887 case LoongArch::VSUB_Q:
5888 case LoongArch::VSUB_W:
5889 case LoongArch::VXOR_V: {
5890 // op: vk
5891 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5892 op &= UINT64_C(31);
5893 op <<= 10;
5894 Value |= op;
5895 // op: vj
5896 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5897 op &= UINT64_C(31);
5898 op <<= 5;
5899 Value |= op;
5900 // op: vd
5901 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5902 op &= UINT64_C(31);
5903 Value |= op;
5904 break;
5905 }
5906 case LoongArch::VFRSTP_B:
5907 case LoongArch::VFRSTP_H:
5908 case LoongArch::VMADDWEV_D_W:
5909 case LoongArch::VMADDWEV_D_WU:
5910 case LoongArch::VMADDWEV_D_WU_W:
5911 case LoongArch::VMADDWEV_H_B:
5912 case LoongArch::VMADDWEV_H_BU:
5913 case LoongArch::VMADDWEV_H_BU_B:
5914 case LoongArch::VMADDWEV_Q_D:
5915 case LoongArch::VMADDWEV_Q_DU:
5916 case LoongArch::VMADDWEV_Q_DU_D:
5917 case LoongArch::VMADDWEV_W_H:
5918 case LoongArch::VMADDWEV_W_HU:
5919 case LoongArch::VMADDWEV_W_HU_H:
5920 case LoongArch::VMADDWOD_D_W:
5921 case LoongArch::VMADDWOD_D_WU:
5922 case LoongArch::VMADDWOD_D_WU_W:
5923 case LoongArch::VMADDWOD_H_B:
5924 case LoongArch::VMADDWOD_H_BU:
5925 case LoongArch::VMADDWOD_H_BU_B:
5926 case LoongArch::VMADDWOD_Q_D:
5927 case LoongArch::VMADDWOD_Q_DU:
5928 case LoongArch::VMADDWOD_Q_DU_D:
5929 case LoongArch::VMADDWOD_W_H:
5930 case LoongArch::VMADDWOD_W_HU:
5931 case LoongArch::VMADDWOD_W_HU_H:
5932 case LoongArch::VMADD_B:
5933 case LoongArch::VMADD_D:
5934 case LoongArch::VMADD_H:
5935 case LoongArch::VMADD_W:
5936 case LoongArch::VMSUB_B:
5937 case LoongArch::VMSUB_D:
5938 case LoongArch::VMSUB_H:
5939 case LoongArch::VMSUB_W:
5940 case LoongArch::VSHUF_D:
5941 case LoongArch::VSHUF_H:
5942 case LoongArch::VSHUF_W: {
5943 // op: vk
5944 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
5945 op &= UINT64_C(31);
5946 op <<= 10;
5947 Value |= op;
5948 // op: vj
5949 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5950 op &= UINT64_C(31);
5951 op <<= 5;
5952 Value |= op;
5953 // op: vd
5954 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5955 op &= UINT64_C(31);
5956 Value |= op;
5957 break;
5958 }
5959 case LoongArch::XVBITSEL_V:
5960 case LoongArch::XVFMADD_D:
5961 case LoongArch::XVFMADD_S:
5962 case LoongArch::XVFMSUB_D:
5963 case LoongArch::XVFMSUB_S:
5964 case LoongArch::XVFNMADD_D:
5965 case LoongArch::XVFNMADD_S:
5966 case LoongArch::XVFNMSUB_D:
5967 case LoongArch::XVFNMSUB_S:
5968 case LoongArch::XVSHUF_B: {
5969 // op: xa
5970 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
5971 op &= UINT64_C(31);
5972 op <<= 15;
5973 Value |= op;
5974 // op: xk
5975 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5976 op &= UINT64_C(31);
5977 op <<= 10;
5978 Value |= op;
5979 // op: xj
5980 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5981 op &= UINT64_C(31);
5982 op <<= 5;
5983 Value |= op;
5984 // op: xd
5985 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5986 op &= UINT64_C(31);
5987 Value |= op;
5988 break;
5989 }
5990 case LoongArch::XVSETALLNEZ_B:
5991 case LoongArch::XVSETALLNEZ_D:
5992 case LoongArch::XVSETALLNEZ_H:
5993 case LoongArch::XVSETALLNEZ_W:
5994 case LoongArch::XVSETANYEQZ_B:
5995 case LoongArch::XVSETANYEQZ_D:
5996 case LoongArch::XVSETANYEQZ_H:
5997 case LoongArch::XVSETANYEQZ_W:
5998 case LoongArch::XVSETEQZ_V:
5999 case LoongArch::XVSETNEZ_V: {
6000 // op: xj
6001 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6002 op &= UINT64_C(31);
6003 op <<= 5;
6004 Value |= op;
6005 // op: cd
6006 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6007 op &= UINT64_C(7);
6008 Value |= op;
6009 break;
6010 }
6011 case LoongArch::VEXT2XV_DU_BU:
6012 case LoongArch::VEXT2XV_DU_HU:
6013 case LoongArch::VEXT2XV_DU_WU:
6014 case LoongArch::VEXT2XV_D_B:
6015 case LoongArch::VEXT2XV_D_H:
6016 case LoongArch::VEXT2XV_D_W:
6017 case LoongArch::VEXT2XV_HU_BU:
6018 case LoongArch::VEXT2XV_H_B:
6019 case LoongArch::VEXT2XV_WU_BU:
6020 case LoongArch::VEXT2XV_WU_HU:
6021 case LoongArch::VEXT2XV_W_B:
6022 case LoongArch::VEXT2XV_W_H:
6023 case LoongArch::XVCLO_B:
6024 case LoongArch::XVCLO_D:
6025 case LoongArch::XVCLO_H:
6026 case LoongArch::XVCLO_W:
6027 case LoongArch::XVCLZ_B:
6028 case LoongArch::XVCLZ_D:
6029 case LoongArch::XVCLZ_H:
6030 case LoongArch::XVCLZ_W:
6031 case LoongArch::XVEXTH_DU_WU:
6032 case LoongArch::XVEXTH_D_W:
6033 case LoongArch::XVEXTH_HU_BU:
6034 case LoongArch::XVEXTH_H_B:
6035 case LoongArch::XVEXTH_QU_DU:
6036 case LoongArch::XVEXTH_Q_D:
6037 case LoongArch::XVEXTH_WU_HU:
6038 case LoongArch::XVEXTH_W_H:
6039 case LoongArch::XVEXTL_QU_DU:
6040 case LoongArch::XVEXTL_Q_D:
6041 case LoongArch::XVFCLASS_D:
6042 case LoongArch::XVFCLASS_S:
6043 case LoongArch::XVFCVTH_D_S:
6044 case LoongArch::XVFCVTH_S_H:
6045 case LoongArch::XVFCVTL_D_S:
6046 case LoongArch::XVFCVTL_S_H:
6047 case LoongArch::XVFFINTH_D_W:
6048 case LoongArch::XVFFINTL_D_W:
6049 case LoongArch::XVFFINT_D_L:
6050 case LoongArch::XVFFINT_D_LU:
6051 case LoongArch::XVFFINT_S_W:
6052 case LoongArch::XVFFINT_S_WU:
6053 case LoongArch::XVFLOGB_D:
6054 case LoongArch::XVFLOGB_S:
6055 case LoongArch::XVFRECIPE_D:
6056 case LoongArch::XVFRECIPE_S:
6057 case LoongArch::XVFRECIP_D:
6058 case LoongArch::XVFRECIP_S:
6059 case LoongArch::XVFRINTRM_D:
6060 case LoongArch::XVFRINTRM_S:
6061 case LoongArch::XVFRINTRNE_D:
6062 case LoongArch::XVFRINTRNE_S:
6063 case LoongArch::XVFRINTRP_D:
6064 case LoongArch::XVFRINTRP_S:
6065 case LoongArch::XVFRINTRZ_D:
6066 case LoongArch::XVFRINTRZ_S:
6067 case LoongArch::XVFRINT_D:
6068 case LoongArch::XVFRINT_S:
6069 case LoongArch::XVFRSQRTE_D:
6070 case LoongArch::XVFRSQRTE_S:
6071 case LoongArch::XVFRSQRT_D:
6072 case LoongArch::XVFRSQRT_S:
6073 case LoongArch::XVFSQRT_D:
6074 case LoongArch::XVFSQRT_S:
6075 case LoongArch::XVFTINTH_L_S:
6076 case LoongArch::XVFTINTL_L_S:
6077 case LoongArch::XVFTINTRMH_L_S:
6078 case LoongArch::XVFTINTRML_L_S:
6079 case LoongArch::XVFTINTRM_L_D:
6080 case LoongArch::XVFTINTRM_W_S:
6081 case LoongArch::XVFTINTRNEH_L_S:
6082 case LoongArch::XVFTINTRNEL_L_S:
6083 case LoongArch::XVFTINTRNE_L_D:
6084 case LoongArch::XVFTINTRNE_W_S:
6085 case LoongArch::XVFTINTRPH_L_S:
6086 case LoongArch::XVFTINTRPL_L_S:
6087 case LoongArch::XVFTINTRP_L_D:
6088 case LoongArch::XVFTINTRP_W_S:
6089 case LoongArch::XVFTINTRZH_L_S:
6090 case LoongArch::XVFTINTRZL_L_S:
6091 case LoongArch::XVFTINTRZ_LU_D:
6092 case LoongArch::XVFTINTRZ_L_D:
6093 case LoongArch::XVFTINTRZ_WU_S:
6094 case LoongArch::XVFTINTRZ_W_S:
6095 case LoongArch::XVFTINT_LU_D:
6096 case LoongArch::XVFTINT_L_D:
6097 case LoongArch::XVFTINT_WU_S:
6098 case LoongArch::XVFTINT_W_S:
6099 case LoongArch::XVMSKGEZ_B:
6100 case LoongArch::XVMSKLTZ_B:
6101 case LoongArch::XVMSKLTZ_D:
6102 case LoongArch::XVMSKLTZ_H:
6103 case LoongArch::XVMSKLTZ_W:
6104 case LoongArch::XVMSKNZ_B:
6105 case LoongArch::XVNEG_B:
6106 case LoongArch::XVNEG_D:
6107 case LoongArch::XVNEG_H:
6108 case LoongArch::XVNEG_W:
6109 case LoongArch::XVPCNT_B:
6110 case LoongArch::XVPCNT_D:
6111 case LoongArch::XVPCNT_H:
6112 case LoongArch::XVPCNT_W:
6113 case LoongArch::XVREPLVE0_B:
6114 case LoongArch::XVREPLVE0_D:
6115 case LoongArch::XVREPLVE0_H:
6116 case LoongArch::XVREPLVE0_Q:
6117 case LoongArch::XVREPLVE0_W: {
6118 // op: xj
6119 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6120 op &= UINT64_C(31);
6121 op <<= 5;
6122 Value |= op;
6123 // op: xd
6124 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6125 op &= UINT64_C(31);
6126 Value |= op;
6127 break;
6128 }
6129 case LoongArch::XVABSD_B:
6130 case LoongArch::XVABSD_BU:
6131 case LoongArch::XVABSD_D:
6132 case LoongArch::XVABSD_DU:
6133 case LoongArch::XVABSD_H:
6134 case LoongArch::XVABSD_HU:
6135 case LoongArch::XVABSD_W:
6136 case LoongArch::XVABSD_WU:
6137 case LoongArch::XVADDA_B:
6138 case LoongArch::XVADDA_D:
6139 case LoongArch::XVADDA_H:
6140 case LoongArch::XVADDA_W:
6141 case LoongArch::XVADDWEV_D_W:
6142 case LoongArch::XVADDWEV_D_WU:
6143 case LoongArch::XVADDWEV_D_WU_W:
6144 case LoongArch::XVADDWEV_H_B:
6145 case LoongArch::XVADDWEV_H_BU:
6146 case LoongArch::XVADDWEV_H_BU_B:
6147 case LoongArch::XVADDWEV_Q_D:
6148 case LoongArch::XVADDWEV_Q_DU:
6149 case LoongArch::XVADDWEV_Q_DU_D:
6150 case LoongArch::XVADDWEV_W_H:
6151 case LoongArch::XVADDWEV_W_HU:
6152 case LoongArch::XVADDWEV_W_HU_H:
6153 case LoongArch::XVADDWOD_D_W:
6154 case LoongArch::XVADDWOD_D_WU:
6155 case LoongArch::XVADDWOD_D_WU_W:
6156 case LoongArch::XVADDWOD_H_B:
6157 case LoongArch::XVADDWOD_H_BU:
6158 case LoongArch::XVADDWOD_H_BU_B:
6159 case LoongArch::XVADDWOD_Q_D:
6160 case LoongArch::XVADDWOD_Q_DU:
6161 case LoongArch::XVADDWOD_Q_DU_D:
6162 case LoongArch::XVADDWOD_W_H:
6163 case LoongArch::XVADDWOD_W_HU:
6164 case LoongArch::XVADDWOD_W_HU_H:
6165 case LoongArch::XVADD_B:
6166 case LoongArch::XVADD_D:
6167 case LoongArch::XVADD_H:
6168 case LoongArch::XVADD_Q:
6169 case LoongArch::XVADD_W:
6170 case LoongArch::XVANDN_V:
6171 case LoongArch::XVAND_V:
6172 case LoongArch::XVAVGR_B:
6173 case LoongArch::XVAVGR_BU:
6174 case LoongArch::XVAVGR_D:
6175 case LoongArch::XVAVGR_DU:
6176 case LoongArch::XVAVGR_H:
6177 case LoongArch::XVAVGR_HU:
6178 case LoongArch::XVAVGR_W:
6179 case LoongArch::XVAVGR_WU:
6180 case LoongArch::XVAVG_B:
6181 case LoongArch::XVAVG_BU:
6182 case LoongArch::XVAVG_D:
6183 case LoongArch::XVAVG_DU:
6184 case LoongArch::XVAVG_H:
6185 case LoongArch::XVAVG_HU:
6186 case LoongArch::XVAVG_W:
6187 case LoongArch::XVAVG_WU:
6188 case LoongArch::XVBITCLR_B:
6189 case LoongArch::XVBITCLR_D:
6190 case LoongArch::XVBITCLR_H:
6191 case LoongArch::XVBITCLR_W:
6192 case LoongArch::XVBITREV_B:
6193 case LoongArch::XVBITREV_D:
6194 case LoongArch::XVBITREV_H:
6195 case LoongArch::XVBITREV_W:
6196 case LoongArch::XVBITSET_B:
6197 case LoongArch::XVBITSET_D:
6198 case LoongArch::XVBITSET_H:
6199 case LoongArch::XVBITSET_W:
6200 case LoongArch::XVDIV_B:
6201 case LoongArch::XVDIV_BU:
6202 case LoongArch::XVDIV_D:
6203 case LoongArch::XVDIV_DU:
6204 case LoongArch::XVDIV_H:
6205 case LoongArch::XVDIV_HU:
6206 case LoongArch::XVDIV_W:
6207 case LoongArch::XVDIV_WU:
6208 case LoongArch::XVFADD_D:
6209 case LoongArch::XVFADD_S:
6210 case LoongArch::XVFCMP_CAF_D:
6211 case LoongArch::XVFCMP_CAF_S:
6212 case LoongArch::XVFCMP_CEQ_D:
6213 case LoongArch::XVFCMP_CEQ_S:
6214 case LoongArch::XVFCMP_CLE_D:
6215 case LoongArch::XVFCMP_CLE_S:
6216 case LoongArch::XVFCMP_CLT_D:
6217 case LoongArch::XVFCMP_CLT_S:
6218 case LoongArch::XVFCMP_CNE_D:
6219 case LoongArch::XVFCMP_CNE_S:
6220 case LoongArch::XVFCMP_COR_D:
6221 case LoongArch::XVFCMP_COR_S:
6222 case LoongArch::XVFCMP_CUEQ_D:
6223 case LoongArch::XVFCMP_CUEQ_S:
6224 case LoongArch::XVFCMP_CULE_D:
6225 case LoongArch::XVFCMP_CULE_S:
6226 case LoongArch::XVFCMP_CULT_D:
6227 case LoongArch::XVFCMP_CULT_S:
6228 case LoongArch::XVFCMP_CUNE_D:
6229 case LoongArch::XVFCMP_CUNE_S:
6230 case LoongArch::XVFCMP_CUN_D:
6231 case LoongArch::XVFCMP_CUN_S:
6232 case LoongArch::XVFCMP_SAF_D:
6233 case LoongArch::XVFCMP_SAF_S:
6234 case LoongArch::XVFCMP_SEQ_D:
6235 case LoongArch::XVFCMP_SEQ_S:
6236 case LoongArch::XVFCMP_SLE_D:
6237 case LoongArch::XVFCMP_SLE_S:
6238 case LoongArch::XVFCMP_SLT_D:
6239 case LoongArch::XVFCMP_SLT_S:
6240 case LoongArch::XVFCMP_SNE_D:
6241 case LoongArch::XVFCMP_SNE_S:
6242 case LoongArch::XVFCMP_SOR_D:
6243 case LoongArch::XVFCMP_SOR_S:
6244 case LoongArch::XVFCMP_SUEQ_D:
6245 case LoongArch::XVFCMP_SUEQ_S:
6246 case LoongArch::XVFCMP_SULE_D:
6247 case LoongArch::XVFCMP_SULE_S:
6248 case LoongArch::XVFCMP_SULT_D:
6249 case LoongArch::XVFCMP_SULT_S:
6250 case LoongArch::XVFCMP_SUNE_D:
6251 case LoongArch::XVFCMP_SUNE_S:
6252 case LoongArch::XVFCMP_SUN_D:
6253 case LoongArch::XVFCMP_SUN_S:
6254 case LoongArch::XVFCVT_H_S:
6255 case LoongArch::XVFCVT_S_D:
6256 case LoongArch::XVFDIV_D:
6257 case LoongArch::XVFDIV_S:
6258 case LoongArch::XVFFINT_S_L:
6259 case LoongArch::XVFMAXA_D:
6260 case LoongArch::XVFMAXA_S:
6261 case LoongArch::XVFMAX_D:
6262 case LoongArch::XVFMAX_S:
6263 case LoongArch::XVFMINA_D:
6264 case LoongArch::XVFMINA_S:
6265 case LoongArch::XVFMIN_D:
6266 case LoongArch::XVFMIN_S:
6267 case LoongArch::XVFMUL_D:
6268 case LoongArch::XVFMUL_S:
6269 case LoongArch::XVFSUB_D:
6270 case LoongArch::XVFSUB_S:
6271 case LoongArch::XVFTINTRM_W_D:
6272 case LoongArch::XVFTINTRNE_W_D:
6273 case LoongArch::XVFTINTRP_W_D:
6274 case LoongArch::XVFTINTRZ_W_D:
6275 case LoongArch::XVFTINT_W_D:
6276 case LoongArch::XVHADDW_DU_WU:
6277 case LoongArch::XVHADDW_D_W:
6278 case LoongArch::XVHADDW_HU_BU:
6279 case LoongArch::XVHADDW_H_B:
6280 case LoongArch::XVHADDW_QU_DU:
6281 case LoongArch::XVHADDW_Q_D:
6282 case LoongArch::XVHADDW_WU_HU:
6283 case LoongArch::XVHADDW_W_H:
6284 case LoongArch::XVHSUBW_DU_WU:
6285 case LoongArch::XVHSUBW_D_W:
6286 case LoongArch::XVHSUBW_HU_BU:
6287 case LoongArch::XVHSUBW_H_B:
6288 case LoongArch::XVHSUBW_QU_DU:
6289 case LoongArch::XVHSUBW_Q_D:
6290 case LoongArch::XVHSUBW_WU_HU:
6291 case LoongArch::XVHSUBW_W_H:
6292 case LoongArch::XVILVH_B:
6293 case LoongArch::XVILVH_D:
6294 case LoongArch::XVILVH_H:
6295 case LoongArch::XVILVH_W:
6296 case LoongArch::XVILVL_B:
6297 case LoongArch::XVILVL_D:
6298 case LoongArch::XVILVL_H:
6299 case LoongArch::XVILVL_W:
6300 case LoongArch::XVMAX_B:
6301 case LoongArch::XVMAX_BU:
6302 case LoongArch::XVMAX_D:
6303 case LoongArch::XVMAX_DU:
6304 case LoongArch::XVMAX_H:
6305 case LoongArch::XVMAX_HU:
6306 case LoongArch::XVMAX_W:
6307 case LoongArch::XVMAX_WU:
6308 case LoongArch::XVMIN_B:
6309 case LoongArch::XVMIN_BU:
6310 case LoongArch::XVMIN_D:
6311 case LoongArch::XVMIN_DU:
6312 case LoongArch::XVMIN_H:
6313 case LoongArch::XVMIN_HU:
6314 case LoongArch::XVMIN_W:
6315 case LoongArch::XVMIN_WU:
6316 case LoongArch::XVMOD_B:
6317 case LoongArch::XVMOD_BU:
6318 case LoongArch::XVMOD_D:
6319 case LoongArch::XVMOD_DU:
6320 case LoongArch::XVMOD_H:
6321 case LoongArch::XVMOD_HU:
6322 case LoongArch::XVMOD_W:
6323 case LoongArch::XVMOD_WU:
6324 case LoongArch::XVMUH_B:
6325 case LoongArch::XVMUH_BU:
6326 case LoongArch::XVMUH_D:
6327 case LoongArch::XVMUH_DU:
6328 case LoongArch::XVMUH_H:
6329 case LoongArch::XVMUH_HU:
6330 case LoongArch::XVMUH_W:
6331 case LoongArch::XVMUH_WU:
6332 case LoongArch::XVMULWEV_D_W:
6333 case LoongArch::XVMULWEV_D_WU:
6334 case LoongArch::XVMULWEV_D_WU_W:
6335 case LoongArch::XVMULWEV_H_B:
6336 case LoongArch::XVMULWEV_H_BU:
6337 case LoongArch::XVMULWEV_H_BU_B:
6338 case LoongArch::XVMULWEV_Q_D:
6339 case LoongArch::XVMULWEV_Q_DU:
6340 case LoongArch::XVMULWEV_Q_DU_D:
6341 case LoongArch::XVMULWEV_W_H:
6342 case LoongArch::XVMULWEV_W_HU:
6343 case LoongArch::XVMULWEV_W_HU_H:
6344 case LoongArch::XVMULWOD_D_W:
6345 case LoongArch::XVMULWOD_D_WU:
6346 case LoongArch::XVMULWOD_D_WU_W:
6347 case LoongArch::XVMULWOD_H_B:
6348 case LoongArch::XVMULWOD_H_BU:
6349 case LoongArch::XVMULWOD_H_BU_B:
6350 case LoongArch::XVMULWOD_Q_D:
6351 case LoongArch::XVMULWOD_Q_DU:
6352 case LoongArch::XVMULWOD_Q_DU_D:
6353 case LoongArch::XVMULWOD_W_H:
6354 case LoongArch::XVMULWOD_W_HU:
6355 case LoongArch::XVMULWOD_W_HU_H:
6356 case LoongArch::XVMUL_B:
6357 case LoongArch::XVMUL_D:
6358 case LoongArch::XVMUL_H:
6359 case LoongArch::XVMUL_W:
6360 case LoongArch::XVNOR_V:
6361 case LoongArch::XVORN_V:
6362 case LoongArch::XVOR_V:
6363 case LoongArch::XVPACKEV_B:
6364 case LoongArch::XVPACKEV_D:
6365 case LoongArch::XVPACKEV_H:
6366 case LoongArch::XVPACKEV_W:
6367 case LoongArch::XVPACKOD_B:
6368 case LoongArch::XVPACKOD_D:
6369 case LoongArch::XVPACKOD_H:
6370 case LoongArch::XVPACKOD_W:
6371 case LoongArch::XVPERM_W:
6372 case LoongArch::XVPICKEV_B:
6373 case LoongArch::XVPICKEV_D:
6374 case LoongArch::XVPICKEV_H:
6375 case LoongArch::XVPICKEV_W:
6376 case LoongArch::XVPICKOD_B:
6377 case LoongArch::XVPICKOD_D:
6378 case LoongArch::XVPICKOD_H:
6379 case LoongArch::XVPICKOD_W:
6380 case LoongArch::XVROTR_B:
6381 case LoongArch::XVROTR_D:
6382 case LoongArch::XVROTR_H:
6383 case LoongArch::XVROTR_W:
6384 case LoongArch::XVSADD_B:
6385 case LoongArch::XVSADD_BU:
6386 case LoongArch::XVSADD_D:
6387 case LoongArch::XVSADD_DU:
6388 case LoongArch::XVSADD_H:
6389 case LoongArch::XVSADD_HU:
6390 case LoongArch::XVSADD_W:
6391 case LoongArch::XVSADD_WU:
6392 case LoongArch::XVSEQ_B:
6393 case LoongArch::XVSEQ_D:
6394 case LoongArch::XVSEQ_H:
6395 case LoongArch::XVSEQ_W:
6396 case LoongArch::XVSIGNCOV_B:
6397 case LoongArch::XVSIGNCOV_D:
6398 case LoongArch::XVSIGNCOV_H:
6399 case LoongArch::XVSIGNCOV_W:
6400 case LoongArch::XVSLE_B:
6401 case LoongArch::XVSLE_BU:
6402 case LoongArch::XVSLE_D:
6403 case LoongArch::XVSLE_DU:
6404 case LoongArch::XVSLE_H:
6405 case LoongArch::XVSLE_HU:
6406 case LoongArch::XVSLE_W:
6407 case LoongArch::XVSLE_WU:
6408 case LoongArch::XVSLL_B:
6409 case LoongArch::XVSLL_D:
6410 case LoongArch::XVSLL_H:
6411 case LoongArch::XVSLL_W:
6412 case LoongArch::XVSLT_B:
6413 case LoongArch::XVSLT_BU:
6414 case LoongArch::XVSLT_D:
6415 case LoongArch::XVSLT_DU:
6416 case LoongArch::XVSLT_H:
6417 case LoongArch::XVSLT_HU:
6418 case LoongArch::XVSLT_W:
6419 case LoongArch::XVSLT_WU:
6420 case LoongArch::XVSRAN_B_H:
6421 case LoongArch::XVSRAN_H_W:
6422 case LoongArch::XVSRAN_W_D:
6423 case LoongArch::XVSRARN_B_H:
6424 case LoongArch::XVSRARN_H_W:
6425 case LoongArch::XVSRARN_W_D:
6426 case LoongArch::XVSRAR_B:
6427 case LoongArch::XVSRAR_D:
6428 case LoongArch::XVSRAR_H:
6429 case LoongArch::XVSRAR_W:
6430 case LoongArch::XVSRA_B:
6431 case LoongArch::XVSRA_D:
6432 case LoongArch::XVSRA_H:
6433 case LoongArch::XVSRA_W:
6434 case LoongArch::XVSRLN_B_H:
6435 case LoongArch::XVSRLN_H_W:
6436 case LoongArch::XVSRLN_W_D:
6437 case LoongArch::XVSRLRN_B_H:
6438 case LoongArch::XVSRLRN_H_W:
6439 case LoongArch::XVSRLRN_W_D:
6440 case LoongArch::XVSRLR_B:
6441 case LoongArch::XVSRLR_D:
6442 case LoongArch::XVSRLR_H:
6443 case LoongArch::XVSRLR_W:
6444 case LoongArch::XVSRL_B:
6445 case LoongArch::XVSRL_D:
6446 case LoongArch::XVSRL_H:
6447 case LoongArch::XVSRL_W:
6448 case LoongArch::XVSSRAN_BU_H:
6449 case LoongArch::XVSSRAN_B_H:
6450 case LoongArch::XVSSRAN_HU_W:
6451 case LoongArch::XVSSRAN_H_W:
6452 case LoongArch::XVSSRAN_WU_D:
6453 case LoongArch::XVSSRAN_W_D:
6454 case LoongArch::XVSSRARN_BU_H:
6455 case LoongArch::XVSSRARN_B_H:
6456 case LoongArch::XVSSRARN_HU_W:
6457 case LoongArch::XVSSRARN_H_W:
6458 case LoongArch::XVSSRARN_WU_D:
6459 case LoongArch::XVSSRARN_W_D:
6460 case LoongArch::XVSSRLN_BU_H:
6461 case LoongArch::XVSSRLN_B_H:
6462 case LoongArch::XVSSRLN_HU_W:
6463 case LoongArch::XVSSRLN_H_W:
6464 case LoongArch::XVSSRLN_WU_D:
6465 case LoongArch::XVSSRLN_W_D:
6466 case LoongArch::XVSSRLRN_BU_H:
6467 case LoongArch::XVSSRLRN_B_H:
6468 case LoongArch::XVSSRLRN_HU_W:
6469 case LoongArch::XVSSRLRN_H_W:
6470 case LoongArch::XVSSRLRN_WU_D:
6471 case LoongArch::XVSSRLRN_W_D:
6472 case LoongArch::XVSSUB_B:
6473 case LoongArch::XVSSUB_BU:
6474 case LoongArch::XVSSUB_D:
6475 case LoongArch::XVSSUB_DU:
6476 case LoongArch::XVSSUB_H:
6477 case LoongArch::XVSSUB_HU:
6478 case LoongArch::XVSSUB_W:
6479 case LoongArch::XVSSUB_WU:
6480 case LoongArch::XVSUBWEV_D_W:
6481 case LoongArch::XVSUBWEV_D_WU:
6482 case LoongArch::XVSUBWEV_H_B:
6483 case LoongArch::XVSUBWEV_H_BU:
6484 case LoongArch::XVSUBWEV_Q_D:
6485 case LoongArch::XVSUBWEV_Q_DU:
6486 case LoongArch::XVSUBWEV_W_H:
6487 case LoongArch::XVSUBWEV_W_HU:
6488 case LoongArch::XVSUBWOD_D_W:
6489 case LoongArch::XVSUBWOD_D_WU:
6490 case LoongArch::XVSUBWOD_H_B:
6491 case LoongArch::XVSUBWOD_H_BU:
6492 case LoongArch::XVSUBWOD_Q_D:
6493 case LoongArch::XVSUBWOD_Q_DU:
6494 case LoongArch::XVSUBWOD_W_H:
6495 case LoongArch::XVSUBWOD_W_HU:
6496 case LoongArch::XVSUB_B:
6497 case LoongArch::XVSUB_D:
6498 case LoongArch::XVSUB_H:
6499 case LoongArch::XVSUB_Q:
6500 case LoongArch::XVSUB_W:
6501 case LoongArch::XVXOR_V: {
6502 // op: xk
6503 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6504 op &= UINT64_C(31);
6505 op <<= 10;
6506 Value |= op;
6507 // op: xj
6508 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6509 op &= UINT64_C(31);
6510 op <<= 5;
6511 Value |= op;
6512 // op: xd
6513 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6514 op &= UINT64_C(31);
6515 Value |= op;
6516 break;
6517 }
6518 case LoongArch::XVFRSTP_B:
6519 case LoongArch::XVFRSTP_H:
6520 case LoongArch::XVMADDWEV_D_W:
6521 case LoongArch::XVMADDWEV_D_WU:
6522 case LoongArch::XVMADDWEV_D_WU_W:
6523 case LoongArch::XVMADDWEV_H_B:
6524 case LoongArch::XVMADDWEV_H_BU:
6525 case LoongArch::XVMADDWEV_H_BU_B:
6526 case LoongArch::XVMADDWEV_Q_D:
6527 case LoongArch::XVMADDWEV_Q_DU:
6528 case LoongArch::XVMADDWEV_Q_DU_D:
6529 case LoongArch::XVMADDWEV_W_H:
6530 case LoongArch::XVMADDWEV_W_HU:
6531 case LoongArch::XVMADDWEV_W_HU_H:
6532 case LoongArch::XVMADDWOD_D_W:
6533 case LoongArch::XVMADDWOD_D_WU:
6534 case LoongArch::XVMADDWOD_D_WU_W:
6535 case LoongArch::XVMADDWOD_H_B:
6536 case LoongArch::XVMADDWOD_H_BU:
6537 case LoongArch::XVMADDWOD_H_BU_B:
6538 case LoongArch::XVMADDWOD_Q_D:
6539 case LoongArch::XVMADDWOD_Q_DU:
6540 case LoongArch::XVMADDWOD_Q_DU_D:
6541 case LoongArch::XVMADDWOD_W_H:
6542 case LoongArch::XVMADDWOD_W_HU:
6543 case LoongArch::XVMADDWOD_W_HU_H:
6544 case LoongArch::XVMADD_B:
6545 case LoongArch::XVMADD_D:
6546 case LoongArch::XVMADD_H:
6547 case LoongArch::XVMADD_W:
6548 case LoongArch::XVMSUB_B:
6549 case LoongArch::XVMSUB_D:
6550 case LoongArch::XVMSUB_H:
6551 case LoongArch::XVMSUB_W:
6552 case LoongArch::XVSHUF_D:
6553 case LoongArch::XVSHUF_H:
6554 case LoongArch::XVSHUF_W: {
6555 // op: xk
6556 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
6557 op &= UINT64_C(31);
6558 op <<= 10;
6559 Value |= op;
6560 // op: xj
6561 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6562 op &= UINT64_C(31);
6563 op <<= 5;
6564 Value |= op;
6565 // op: xd
6566 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6567 op &= UINT64_C(31);
6568 Value |= op;
6569 break;
6570 }
6571 default:
6572 std::string msg;
6573 raw_string_ostream Msg(msg);
6574 Msg << "Not supported instr: " << MI;
6575 report_fatal_error(reason: Msg.str().c_str());
6576 }
6577 return Value;
6578}
6579
6580#ifdef GET_OPERAND_BIT_OFFSET
6581#undef GET_OPERAND_BIT_OFFSET
6582
6583uint32_t LoongArchMCCodeEmitter::getOperandBitOffset(const MCInst &MI,
6584 unsigned OpNum,
6585 const MCSubtargetInfo &STI) const {
6586 switch (MI.getOpcode()) {
6587 case LoongArch::ERTN:
6588 case LoongArch::GTLBFLUSH:
6589 case LoongArch::TLBCLR:
6590 case LoongArch::TLBFILL:
6591 case LoongArch::TLBFLUSH:
6592 case LoongArch::TLBRD:
6593 case LoongArch::TLBSRCH:
6594 case LoongArch::TLBWR:
6595 case LoongArch::X86CLRTM:
6596 case LoongArch::X86DECTOP:
6597 case LoongArch::X86INCTOP:
6598 case LoongArch::X86SETTM: {
6599 break;
6600 }
6601 case LoongArch::SET_CFR_FALSE:
6602 case LoongArch::SET_CFR_TRUE: {
6603 switch (OpNum) {
6604 case 0:
6605 // op: cd
6606 return 0;
6607 }
6608 break;
6609 }
6610 case LoongArch::BREAK:
6611 case LoongArch::DBAR:
6612 case LoongArch::DBCL:
6613 case LoongArch::HVCL:
6614 case LoongArch::IBAR:
6615 case LoongArch::IDLE:
6616 case LoongArch::SYSCALL: {
6617 switch (OpNum) {
6618 case 0:
6619 // op: imm15
6620 return 0;
6621 }
6622 break;
6623 }
6624 case LoongArch::JISCR0:
6625 case LoongArch::JISCR1: {
6626 switch (OpNum) {
6627 case 0:
6628 // op: imm21
6629 return 0;
6630 }
6631 break;
6632 }
6633 case LoongArch::B:
6634 case LoongArch::BL: {
6635 switch (OpNum) {
6636 case 0:
6637 // op: imm26
6638 return 0;
6639 }
6640 break;
6641 }
6642 case LoongArch::X86MTTOP: {
6643 switch (OpNum) {
6644 case 0:
6645 // op: ptr
6646 return 5;
6647 }
6648 break;
6649 }
6650 case LoongArch::X86MFTOP: {
6651 switch (OpNum) {
6652 case 0:
6653 // op: rd
6654 return 0;
6655 }
6656 break;
6657 }
6658 case LoongArch::X86DEC_B:
6659 case LoongArch::X86DEC_D:
6660 case LoongArch::X86DEC_H:
6661 case LoongArch::X86DEC_W:
6662 case LoongArch::X86INC_B:
6663 case LoongArch::X86INC_D:
6664 case LoongArch::X86INC_H:
6665 case LoongArch::X86INC_W: {
6666 switch (OpNum) {
6667 case 0:
6668 // op: rj
6669 return 5;
6670 }
6671 break;
6672 }
6673 case LoongArch::INVTLB: {
6674 switch (OpNum) {
6675 case 0:
6676 // op: rk
6677 return 10;
6678 case 1:
6679 // op: rj
6680 return 5;
6681 case 2:
6682 // op: op
6683 return 0;
6684 }
6685 break;
6686 }
6687 case LoongArch::CSRRD:
6688 case LoongArch::GCSRRD: {
6689 switch (OpNum) {
6690 case 1:
6691 // op: csr_num
6692 return 10;
6693 case 0:
6694 // op: rd
6695 return 0;
6696 }
6697 break;
6698 }
6699 case LoongArch::FABS_D:
6700 case LoongArch::FABS_S:
6701 case LoongArch::FCLASS_D:
6702 case LoongArch::FCLASS_S:
6703 case LoongArch::FCVT_D_S:
6704 case LoongArch::FCVT_LD_D:
6705 case LoongArch::FCVT_S_D:
6706 case LoongArch::FCVT_UD_D:
6707 case LoongArch::FFINT_D_L:
6708 case LoongArch::FFINT_D_W:
6709 case LoongArch::FFINT_S_L:
6710 case LoongArch::FFINT_S_W:
6711 case LoongArch::FLOGB_D:
6712 case LoongArch::FLOGB_S:
6713 case LoongArch::FNEG_D:
6714 case LoongArch::FNEG_S:
6715 case LoongArch::FRECIPE_D:
6716 case LoongArch::FRECIPE_S:
6717 case LoongArch::FRECIP_D:
6718 case LoongArch::FRECIP_S:
6719 case LoongArch::FRINT_D:
6720 case LoongArch::FRINT_S:
6721 case LoongArch::FRSQRTE_D:
6722 case LoongArch::FRSQRTE_S:
6723 case LoongArch::FRSQRT_D:
6724 case LoongArch::FRSQRT_S:
6725 case LoongArch::FSQRT_D:
6726 case LoongArch::FSQRT_S:
6727 case LoongArch::FTINTRM_L_D:
6728 case LoongArch::FTINTRM_L_S:
6729 case LoongArch::FTINTRM_W_D:
6730 case LoongArch::FTINTRM_W_S:
6731 case LoongArch::FTINTRNE_L_D:
6732 case LoongArch::FTINTRNE_L_S:
6733 case LoongArch::FTINTRNE_W_D:
6734 case LoongArch::FTINTRNE_W_S:
6735 case LoongArch::FTINTRP_L_D:
6736 case LoongArch::FTINTRP_L_S:
6737 case LoongArch::FTINTRP_W_D:
6738 case LoongArch::FTINTRP_W_S:
6739 case LoongArch::FTINTRZ_L_D:
6740 case LoongArch::FTINTRZ_L_S:
6741 case LoongArch::FTINTRZ_W_D:
6742 case LoongArch::FTINTRZ_W_S:
6743 case LoongArch::FTINT_L_D:
6744 case LoongArch::FTINT_L_S:
6745 case LoongArch::FTINT_W_D:
6746 case LoongArch::FTINT_W_S: {
6747 switch (OpNum) {
6748 case 1:
6749 // op: fj
6750 return 5;
6751 case 0:
6752 // op: fd
6753 return 0;
6754 }
6755 break;
6756 }
6757 case LoongArch::VLDI: {
6758 switch (OpNum) {
6759 case 1:
6760 // op: imm13
6761 return 5;
6762 case 0:
6763 // op: vd
6764 return 0;
6765 }
6766 break;
6767 }
6768 case LoongArch::XVLDI: {
6769 switch (OpNum) {
6770 case 1:
6771 // op: imm13
6772 return 5;
6773 case 0:
6774 // op: xd
6775 return 0;
6776 }
6777 break;
6778 }
6779 case LoongArch::LU12I_W:
6780 case LoongArch::PCADDI:
6781 case LoongArch::PCADDU12I:
6782 case LoongArch::PCADDU18I:
6783 case LoongArch::PCALAU12I: {
6784 switch (OpNum) {
6785 case 1:
6786 // op: imm20
6787 return 5;
6788 case 0:
6789 // op: rd
6790 return 0;
6791 }
6792 break;
6793 }
6794 case LoongArch::BCEQZ:
6795 case LoongArch::BCNEZ: {
6796 switch (OpNum) {
6797 case 1:
6798 // op: imm21
6799 return 0;
6800 case 0:
6801 // op: cj
6802 return 5;
6803 }
6804 break;
6805 }
6806 case LoongArch::BEQZ:
6807 case LoongArch::BNEZ: {
6808 switch (OpNum) {
6809 case 1:
6810 // op: imm21
6811 return 0;
6812 case 0:
6813 // op: rj
6814 return 5;
6815 }
6816 break;
6817 }
6818 case LoongArch::X86RCLI_B:
6819 case LoongArch::X86RCRI_B:
6820 case LoongArch::X86ROTLI_B:
6821 case LoongArch::X86ROTRI_B:
6822 case LoongArch::X86SLLI_B:
6823 case LoongArch::X86SRAI_B:
6824 case LoongArch::X86SRLI_B: {
6825 switch (OpNum) {
6826 case 1:
6827 // op: imm3
6828 return 10;
6829 case 0:
6830 // op: rj
6831 return 5;
6832 }
6833 break;
6834 }
6835 case LoongArch::SETARMJ:
6836 case LoongArch::SETX86J: {
6837 switch (OpNum) {
6838 case 1:
6839 // op: imm4
6840 return 10;
6841 case 0:
6842 // op: rd
6843 return 0;
6844 }
6845 break;
6846 }
6847 case LoongArch::ARMMOV_D:
6848 case LoongArch::ARMMOV_W:
6849 case LoongArch::ARMNOT_W:
6850 case LoongArch::ARMRRX_W:
6851 case LoongArch::X86RCLI_H:
6852 case LoongArch::X86RCRI_H:
6853 case LoongArch::X86ROTLI_H:
6854 case LoongArch::X86ROTRI_H:
6855 case LoongArch::X86SLLI_H:
6856 case LoongArch::X86SRAI_H:
6857 case LoongArch::X86SRLI_H: {
6858 switch (OpNum) {
6859 case 1:
6860 // op: imm4
6861 return 10;
6862 case 0:
6863 // op: rj
6864 return 5;
6865 }
6866 break;
6867 }
6868 case LoongArch::ARMROTRI_W:
6869 case LoongArch::ARMSLLI_W:
6870 case LoongArch::ARMSRAI_W:
6871 case LoongArch::ARMSRLI_W: {
6872 switch (OpNum) {
6873 case 1:
6874 // op: imm5
6875 return 10;
6876 case 0:
6877 // op: rj
6878 return 5;
6879 case 2:
6880 // op: imm4
6881 return 0;
6882 }
6883 break;
6884 }
6885 case LoongArch::X86RCLI_W:
6886 case LoongArch::X86RCRI_W:
6887 case LoongArch::X86ROTLI_W:
6888 case LoongArch::X86ROTRI_W:
6889 case LoongArch::X86SLLI_W:
6890 case LoongArch::X86SRAI_W:
6891 case LoongArch::X86SRLI_W: {
6892 switch (OpNum) {
6893 case 1:
6894 // op: imm5
6895 return 10;
6896 case 0:
6897 // op: rj
6898 return 5;
6899 }
6900 break;
6901 }
6902 case LoongArch::X86RCLI_D:
6903 case LoongArch::X86RCRI_D:
6904 case LoongArch::X86ROTLI_D:
6905 case LoongArch::X86ROTRI_D:
6906 case LoongArch::X86SLLI_D:
6907 case LoongArch::X86SRAI_D:
6908 case LoongArch::X86SRLI_D: {
6909 switch (OpNum) {
6910 case 1:
6911 // op: imm6
6912 return 10;
6913 case 0:
6914 // op: rj
6915 return 5;
6916 }
6917 break;
6918 }
6919 case LoongArch::ARMMFFLAG:
6920 case LoongArch::ARMMTFLAG:
6921 case LoongArch::X86MFFLAG:
6922 case LoongArch::X86MTFLAG: {
6923 switch (OpNum) {
6924 case 1:
6925 // op: imm8
6926 return 10;
6927 case 0:
6928 // op: rd
6929 return 0;
6930 }
6931 break;
6932 }
6933 case LoongArch::BITREV_4B:
6934 case LoongArch::BITREV_8B:
6935 case LoongArch::BITREV_D:
6936 case LoongArch::BITREV_W:
6937 case LoongArch::CLO_D:
6938 case LoongArch::CLO_W:
6939 case LoongArch::CLZ_D:
6940 case LoongArch::CLZ_W:
6941 case LoongArch::CPUCFG:
6942 case LoongArch::CTO_D:
6943 case LoongArch::CTO_W:
6944 case LoongArch::CTZ_D:
6945 case LoongArch::CTZ_W:
6946 case LoongArch::EXT_W_B:
6947 case LoongArch::EXT_W_H:
6948 case LoongArch::IOCSRRD_B:
6949 case LoongArch::IOCSRRD_D:
6950 case LoongArch::IOCSRRD_H:
6951 case LoongArch::IOCSRRD_W:
6952 case LoongArch::IOCSRWR_B:
6953 case LoongArch::IOCSRWR_D:
6954 case LoongArch::IOCSRWR_H:
6955 case LoongArch::IOCSRWR_W:
6956 case LoongArch::LLACQ_D:
6957 case LoongArch::LLACQ_W:
6958 case LoongArch::RDTIMEH_W:
6959 case LoongArch::RDTIMEL_W:
6960 case LoongArch::RDTIME_D:
6961 case LoongArch::REVB_2H:
6962 case LoongArch::REVB_2W:
6963 case LoongArch::REVB_4H:
6964 case LoongArch::REVB_D:
6965 case LoongArch::REVH_2W:
6966 case LoongArch::REVH_D:
6967 case LoongArch::SETX86LOOPE:
6968 case LoongArch::SETX86LOOPNE: {
6969 switch (OpNum) {
6970 case 1:
6971 // op: rj
6972 return 5;
6973 case 0:
6974 // op: rd
6975 return 0;
6976 }
6977 break;
6978 }
6979 case LoongArch::MOVGR2SCR: {
6980 switch (OpNum) {
6981 case 1:
6982 // op: rj
6983 return 5;
6984 case 0:
6985 // op: sd
6986 return 0;
6987 }
6988 break;
6989 }
6990 case LoongArch::VREPLGR2VR_B:
6991 case LoongArch::VREPLGR2VR_D:
6992 case LoongArch::VREPLGR2VR_H:
6993 case LoongArch::VREPLGR2VR_W: {
6994 switch (OpNum) {
6995 case 1:
6996 // op: rj
6997 return 5;
6998 case 0:
6999 // op: vd
7000 return 0;
7001 }
7002 break;
7003 }
7004 case LoongArch::XVREPLGR2VR_B:
7005 case LoongArch::XVREPLGR2VR_D:
7006 case LoongArch::XVREPLGR2VR_H:
7007 case LoongArch::XVREPLGR2VR_W: {
7008 switch (OpNum) {
7009 case 1:
7010 // op: rj
7011 return 5;
7012 case 0:
7013 // op: xd
7014 return 0;
7015 }
7016 break;
7017 }
7018 case LoongArch::ASRTGT_D:
7019 case LoongArch::ASRTLE_D:
7020 case LoongArch::X86ADC_B:
7021 case LoongArch::X86ADC_D:
7022 case LoongArch::X86ADC_H:
7023 case LoongArch::X86ADC_W:
7024 case LoongArch::X86ADD_B:
7025 case LoongArch::X86ADD_D:
7026 case LoongArch::X86ADD_DU:
7027 case LoongArch::X86ADD_H:
7028 case LoongArch::X86ADD_W:
7029 case LoongArch::X86ADD_WU:
7030 case LoongArch::X86AND_B:
7031 case LoongArch::X86AND_D:
7032 case LoongArch::X86AND_H:
7033 case LoongArch::X86AND_W:
7034 case LoongArch::X86MUL_B:
7035 case LoongArch::X86MUL_BU:
7036 case LoongArch::X86MUL_D:
7037 case LoongArch::X86MUL_DU:
7038 case LoongArch::X86MUL_H:
7039 case LoongArch::X86MUL_HU:
7040 case LoongArch::X86MUL_W:
7041 case LoongArch::X86MUL_WU:
7042 case LoongArch::X86OR_B:
7043 case LoongArch::X86OR_D:
7044 case LoongArch::X86OR_H:
7045 case LoongArch::X86OR_W:
7046 case LoongArch::X86RCL_B:
7047 case LoongArch::X86RCL_D:
7048 case LoongArch::X86RCL_H:
7049 case LoongArch::X86RCL_W:
7050 case LoongArch::X86RCR_B:
7051 case LoongArch::X86RCR_D:
7052 case LoongArch::X86RCR_H:
7053 case LoongArch::X86RCR_W:
7054 case LoongArch::X86ROTL_B:
7055 case LoongArch::X86ROTL_D:
7056 case LoongArch::X86ROTL_H:
7057 case LoongArch::X86ROTL_W:
7058 case LoongArch::X86ROTR_B:
7059 case LoongArch::X86ROTR_D:
7060 case LoongArch::X86ROTR_H:
7061 case LoongArch::X86ROTR_W:
7062 case LoongArch::X86SBC_B:
7063 case LoongArch::X86SBC_D:
7064 case LoongArch::X86SBC_H:
7065 case LoongArch::X86SBC_W:
7066 case LoongArch::X86SLL_B:
7067 case LoongArch::X86SLL_D:
7068 case LoongArch::X86SLL_H:
7069 case LoongArch::X86SLL_W:
7070 case LoongArch::X86SRA_B:
7071 case LoongArch::X86SRA_D:
7072 case LoongArch::X86SRA_H:
7073 case LoongArch::X86SRA_W:
7074 case LoongArch::X86SRL_B:
7075 case LoongArch::X86SRL_D:
7076 case LoongArch::X86SRL_H:
7077 case LoongArch::X86SRL_W:
7078 case LoongArch::X86SUB_B:
7079 case LoongArch::X86SUB_D:
7080 case LoongArch::X86SUB_DU:
7081 case LoongArch::X86SUB_H:
7082 case LoongArch::X86SUB_W:
7083 case LoongArch::X86SUB_WU:
7084 case LoongArch::X86XOR_B:
7085 case LoongArch::X86XOR_D:
7086 case LoongArch::X86XOR_H:
7087 case LoongArch::X86XOR_W: {
7088 switch (OpNum) {
7089 case 1:
7090 // op: rk
7091 return 10;
7092 case 0:
7093 // op: rj
7094 return 5;
7095 }
7096 break;
7097 }
7098 case LoongArch::AMADD_B:
7099 case LoongArch::AMADD_D:
7100 case LoongArch::AMADD_H:
7101 case LoongArch::AMADD_W:
7102 case LoongArch::AMADD__DB_B:
7103 case LoongArch::AMADD__DB_D:
7104 case LoongArch::AMADD__DB_H:
7105 case LoongArch::AMADD__DB_W:
7106 case LoongArch::AMAND_D:
7107 case LoongArch::AMAND_W:
7108 case LoongArch::AMAND__DB_D:
7109 case LoongArch::AMAND__DB_W:
7110 case LoongArch::AMMAX_D:
7111 case LoongArch::AMMAX_DU:
7112 case LoongArch::AMMAX_W:
7113 case LoongArch::AMMAX_WU:
7114 case LoongArch::AMMAX__DB_D:
7115 case LoongArch::AMMAX__DB_DU:
7116 case LoongArch::AMMAX__DB_W:
7117 case LoongArch::AMMAX__DB_WU:
7118 case LoongArch::AMMIN_D:
7119 case LoongArch::AMMIN_DU:
7120 case LoongArch::AMMIN_W:
7121 case LoongArch::AMMIN_WU:
7122 case LoongArch::AMMIN__DB_D:
7123 case LoongArch::AMMIN__DB_DU:
7124 case LoongArch::AMMIN__DB_W:
7125 case LoongArch::AMMIN__DB_WU:
7126 case LoongArch::AMOR_D:
7127 case LoongArch::AMOR_W:
7128 case LoongArch::AMOR__DB_D:
7129 case LoongArch::AMOR__DB_W:
7130 case LoongArch::AMSWAP_B:
7131 case LoongArch::AMSWAP_D:
7132 case LoongArch::AMSWAP_H:
7133 case LoongArch::AMSWAP_W:
7134 case LoongArch::AMSWAP__DB_B:
7135 case LoongArch::AMSWAP__DB_D:
7136 case LoongArch::AMSWAP__DB_H:
7137 case LoongArch::AMSWAP__DB_W:
7138 case LoongArch::AMXOR_D:
7139 case LoongArch::AMXOR_W:
7140 case LoongArch::AMXOR__DB_D:
7141 case LoongArch::AMXOR__DB_W: {
7142 switch (OpNum) {
7143 case 1:
7144 // op: rk
7145 return 10;
7146 case 2:
7147 // op: rj
7148 return 5;
7149 case 0:
7150 // op: rd
7151 return 0;
7152 }
7153 break;
7154 }
7155 case LoongArch::LDPTE: {
7156 switch (OpNum) {
7157 case 1:
7158 // op: seq
7159 return 10;
7160 case 0:
7161 // op: rj
7162 return 5;
7163 }
7164 break;
7165 }
7166 case LoongArch::MOVSCR2GR: {
7167 switch (OpNum) {
7168 case 1:
7169 // op: sj
7170 return 5;
7171 case 0:
7172 // op: rd
7173 return 0;
7174 }
7175 break;
7176 }
7177 case LoongArch::FMOV_D:
7178 case LoongArch::FMOV_S:
7179 case LoongArch::MOVCF2FR_xS:
7180 case LoongArch::MOVCF2GR:
7181 case LoongArch::MOVFCSR2GR:
7182 case LoongArch::MOVFR2CF_xS:
7183 case LoongArch::MOVFR2GR_D:
7184 case LoongArch::MOVFR2GR_S:
7185 case LoongArch::MOVFR2GR_S_64:
7186 case LoongArch::MOVFRH2GR_S:
7187 case LoongArch::MOVGR2CF:
7188 case LoongArch::MOVGR2FCSR:
7189 case LoongArch::MOVGR2FR_D:
7190 case LoongArch::MOVGR2FR_W:
7191 case LoongArch::MOVGR2FR_W_64: {
7192 switch (OpNum) {
7193 case 1:
7194 // op: src
7195 return 5;
7196 case 0:
7197 // op: dst
7198 return 0;
7199 }
7200 break;
7201 }
7202 case LoongArch::VSETALLNEZ_B:
7203 case LoongArch::VSETALLNEZ_D:
7204 case LoongArch::VSETALLNEZ_H:
7205 case LoongArch::VSETALLNEZ_W:
7206 case LoongArch::VSETANYEQZ_B:
7207 case LoongArch::VSETANYEQZ_D:
7208 case LoongArch::VSETANYEQZ_H:
7209 case LoongArch::VSETANYEQZ_W:
7210 case LoongArch::VSETEQZ_V:
7211 case LoongArch::VSETNEZ_V: {
7212 switch (OpNum) {
7213 case 1:
7214 // op: vj
7215 return 5;
7216 case 0:
7217 // op: cd
7218 return 0;
7219 }
7220 break;
7221 }
7222 case LoongArch::VCLO_B:
7223 case LoongArch::VCLO_D:
7224 case LoongArch::VCLO_H:
7225 case LoongArch::VCLO_W:
7226 case LoongArch::VCLZ_B:
7227 case LoongArch::VCLZ_D:
7228 case LoongArch::VCLZ_H:
7229 case LoongArch::VCLZ_W:
7230 case LoongArch::VEXTH_DU_WU:
7231 case LoongArch::VEXTH_D_W:
7232 case LoongArch::VEXTH_HU_BU:
7233 case LoongArch::VEXTH_H_B:
7234 case LoongArch::VEXTH_QU_DU:
7235 case LoongArch::VEXTH_Q_D:
7236 case LoongArch::VEXTH_WU_HU:
7237 case LoongArch::VEXTH_W_H:
7238 case LoongArch::VEXTL_QU_DU:
7239 case LoongArch::VEXTL_Q_D:
7240 case LoongArch::VFCLASS_D:
7241 case LoongArch::VFCLASS_S:
7242 case LoongArch::VFCVTH_D_S:
7243 case LoongArch::VFCVTH_S_H:
7244 case LoongArch::VFCVTL_D_S:
7245 case LoongArch::VFCVTL_S_H:
7246 case LoongArch::VFFINTH_D_W:
7247 case LoongArch::VFFINTL_D_W:
7248 case LoongArch::VFFINT_D_L:
7249 case LoongArch::VFFINT_D_LU:
7250 case LoongArch::VFFINT_S_W:
7251 case LoongArch::VFFINT_S_WU:
7252 case LoongArch::VFLOGB_D:
7253 case LoongArch::VFLOGB_S:
7254 case LoongArch::VFRECIPE_D:
7255 case LoongArch::VFRECIPE_S:
7256 case LoongArch::VFRECIP_D:
7257 case LoongArch::VFRECIP_S:
7258 case LoongArch::VFRINTRM_D:
7259 case LoongArch::VFRINTRM_S:
7260 case LoongArch::VFRINTRNE_D:
7261 case LoongArch::VFRINTRNE_S:
7262 case LoongArch::VFRINTRP_D:
7263 case LoongArch::VFRINTRP_S:
7264 case LoongArch::VFRINTRZ_D:
7265 case LoongArch::VFRINTRZ_S:
7266 case LoongArch::VFRINT_D:
7267 case LoongArch::VFRINT_S:
7268 case LoongArch::VFRSQRTE_D:
7269 case LoongArch::VFRSQRTE_S:
7270 case LoongArch::VFRSQRT_D:
7271 case LoongArch::VFRSQRT_S:
7272 case LoongArch::VFSQRT_D:
7273 case LoongArch::VFSQRT_S:
7274 case LoongArch::VFTINTH_L_S:
7275 case LoongArch::VFTINTL_L_S:
7276 case LoongArch::VFTINTRMH_L_S:
7277 case LoongArch::VFTINTRML_L_S:
7278 case LoongArch::VFTINTRM_L_D:
7279 case LoongArch::VFTINTRM_W_S:
7280 case LoongArch::VFTINTRNEH_L_S:
7281 case LoongArch::VFTINTRNEL_L_S:
7282 case LoongArch::VFTINTRNE_L_D:
7283 case LoongArch::VFTINTRNE_W_S:
7284 case LoongArch::VFTINTRPH_L_S:
7285 case LoongArch::VFTINTRPL_L_S:
7286 case LoongArch::VFTINTRP_L_D:
7287 case LoongArch::VFTINTRP_W_S:
7288 case LoongArch::VFTINTRZH_L_S:
7289 case LoongArch::VFTINTRZL_L_S:
7290 case LoongArch::VFTINTRZ_LU_D:
7291 case LoongArch::VFTINTRZ_L_D:
7292 case LoongArch::VFTINTRZ_WU_S:
7293 case LoongArch::VFTINTRZ_W_S:
7294 case LoongArch::VFTINT_LU_D:
7295 case LoongArch::VFTINT_L_D:
7296 case LoongArch::VFTINT_WU_S:
7297 case LoongArch::VFTINT_W_S:
7298 case LoongArch::VMSKGEZ_B:
7299 case LoongArch::VMSKLTZ_B:
7300 case LoongArch::VMSKLTZ_D:
7301 case LoongArch::VMSKLTZ_H:
7302 case LoongArch::VMSKLTZ_W:
7303 case LoongArch::VMSKNZ_B:
7304 case LoongArch::VNEG_B:
7305 case LoongArch::VNEG_D:
7306 case LoongArch::VNEG_H:
7307 case LoongArch::VNEG_W:
7308 case LoongArch::VPCNT_B:
7309 case LoongArch::VPCNT_D:
7310 case LoongArch::VPCNT_H:
7311 case LoongArch::VPCNT_W: {
7312 switch (OpNum) {
7313 case 1:
7314 // op: vj
7315 return 5;
7316 case 0:
7317 // op: vd
7318 return 0;
7319 }
7320 break;
7321 }
7322 case LoongArch::XVSETALLNEZ_B:
7323 case LoongArch::XVSETALLNEZ_D:
7324 case LoongArch::XVSETALLNEZ_H:
7325 case LoongArch::XVSETALLNEZ_W:
7326 case LoongArch::XVSETANYEQZ_B:
7327 case LoongArch::XVSETANYEQZ_D:
7328 case LoongArch::XVSETANYEQZ_H:
7329 case LoongArch::XVSETANYEQZ_W:
7330 case LoongArch::XVSETEQZ_V:
7331 case LoongArch::XVSETNEZ_V: {
7332 switch (OpNum) {
7333 case 1:
7334 // op: xj
7335 return 5;
7336 case 0:
7337 // op: cd
7338 return 0;
7339 }
7340 break;
7341 }
7342 case LoongArch::VEXT2XV_DU_BU:
7343 case LoongArch::VEXT2XV_DU_HU:
7344 case LoongArch::VEXT2XV_DU_WU:
7345 case LoongArch::VEXT2XV_D_B:
7346 case LoongArch::VEXT2XV_D_H:
7347 case LoongArch::VEXT2XV_D_W:
7348 case LoongArch::VEXT2XV_HU_BU:
7349 case LoongArch::VEXT2XV_H_B:
7350 case LoongArch::VEXT2XV_WU_BU:
7351 case LoongArch::VEXT2XV_WU_HU:
7352 case LoongArch::VEXT2XV_W_B:
7353 case LoongArch::VEXT2XV_W_H:
7354 case LoongArch::XVCLO_B:
7355 case LoongArch::XVCLO_D:
7356 case LoongArch::XVCLO_H:
7357 case LoongArch::XVCLO_W:
7358 case LoongArch::XVCLZ_B:
7359 case LoongArch::XVCLZ_D:
7360 case LoongArch::XVCLZ_H:
7361 case LoongArch::XVCLZ_W:
7362 case LoongArch::XVEXTH_DU_WU:
7363 case LoongArch::XVEXTH_D_W:
7364 case LoongArch::XVEXTH_HU_BU:
7365 case LoongArch::XVEXTH_H_B:
7366 case LoongArch::XVEXTH_QU_DU:
7367 case LoongArch::XVEXTH_Q_D:
7368 case LoongArch::XVEXTH_WU_HU:
7369 case LoongArch::XVEXTH_W_H:
7370 case LoongArch::XVEXTL_QU_DU:
7371 case LoongArch::XVEXTL_Q_D:
7372 case LoongArch::XVFCLASS_D:
7373 case LoongArch::XVFCLASS_S:
7374 case LoongArch::XVFCVTH_D_S:
7375 case LoongArch::XVFCVTH_S_H:
7376 case LoongArch::XVFCVTL_D_S:
7377 case LoongArch::XVFCVTL_S_H:
7378 case LoongArch::XVFFINTH_D_W:
7379 case LoongArch::XVFFINTL_D_W:
7380 case LoongArch::XVFFINT_D_L:
7381 case LoongArch::XVFFINT_D_LU:
7382 case LoongArch::XVFFINT_S_W:
7383 case LoongArch::XVFFINT_S_WU:
7384 case LoongArch::XVFLOGB_D:
7385 case LoongArch::XVFLOGB_S:
7386 case LoongArch::XVFRECIPE_D:
7387 case LoongArch::XVFRECIPE_S:
7388 case LoongArch::XVFRECIP_D:
7389 case LoongArch::XVFRECIP_S:
7390 case LoongArch::XVFRINTRM_D:
7391 case LoongArch::XVFRINTRM_S:
7392 case LoongArch::XVFRINTRNE_D:
7393 case LoongArch::XVFRINTRNE_S:
7394 case LoongArch::XVFRINTRP_D:
7395 case LoongArch::XVFRINTRP_S:
7396 case LoongArch::XVFRINTRZ_D:
7397 case LoongArch::XVFRINTRZ_S:
7398 case LoongArch::XVFRINT_D:
7399 case LoongArch::XVFRINT_S:
7400 case LoongArch::XVFRSQRTE_D:
7401 case LoongArch::XVFRSQRTE_S:
7402 case LoongArch::XVFRSQRT_D:
7403 case LoongArch::XVFRSQRT_S:
7404 case LoongArch::XVFSQRT_D:
7405 case LoongArch::XVFSQRT_S:
7406 case LoongArch::XVFTINTH_L_S:
7407 case LoongArch::XVFTINTL_L_S:
7408 case LoongArch::XVFTINTRMH_L_S:
7409 case LoongArch::XVFTINTRML_L_S:
7410 case LoongArch::XVFTINTRM_L_D:
7411 case LoongArch::XVFTINTRM_W_S:
7412 case LoongArch::XVFTINTRNEH_L_S:
7413 case LoongArch::XVFTINTRNEL_L_S:
7414 case LoongArch::XVFTINTRNE_L_D:
7415 case LoongArch::XVFTINTRNE_W_S:
7416 case LoongArch::XVFTINTRPH_L_S:
7417 case LoongArch::XVFTINTRPL_L_S:
7418 case LoongArch::XVFTINTRP_L_D:
7419 case LoongArch::XVFTINTRP_W_S:
7420 case LoongArch::XVFTINTRZH_L_S:
7421 case LoongArch::XVFTINTRZL_L_S:
7422 case LoongArch::XVFTINTRZ_LU_D:
7423 case LoongArch::XVFTINTRZ_L_D:
7424 case LoongArch::XVFTINTRZ_WU_S:
7425 case LoongArch::XVFTINTRZ_W_S:
7426 case LoongArch::XVFTINT_LU_D:
7427 case LoongArch::XVFTINT_L_D:
7428 case LoongArch::XVFTINT_WU_S:
7429 case LoongArch::XVFTINT_W_S:
7430 case LoongArch::XVMSKGEZ_B:
7431 case LoongArch::XVMSKLTZ_B:
7432 case LoongArch::XVMSKLTZ_D:
7433 case LoongArch::XVMSKLTZ_H:
7434 case LoongArch::XVMSKLTZ_W:
7435 case LoongArch::XVMSKNZ_B:
7436 case LoongArch::XVNEG_B:
7437 case LoongArch::XVNEG_D:
7438 case LoongArch::XVNEG_H:
7439 case LoongArch::XVNEG_W:
7440 case LoongArch::XVPCNT_B:
7441 case LoongArch::XVPCNT_D:
7442 case LoongArch::XVPCNT_H:
7443 case LoongArch::XVPCNT_W:
7444 case LoongArch::XVREPLVE0_B:
7445 case LoongArch::XVREPLVE0_D:
7446 case LoongArch::XVREPLVE0_H:
7447 case LoongArch::XVREPLVE0_Q:
7448 case LoongArch::XVREPLVE0_W: {
7449 switch (OpNum) {
7450 case 1:
7451 // op: xj
7452 return 5;
7453 case 0:
7454 // op: xd
7455 return 0;
7456 }
7457 break;
7458 }
7459 case LoongArch::CSRWR:
7460 case LoongArch::GCSRWR: {
7461 switch (OpNum) {
7462 case 2:
7463 // op: csr_num
7464 return 10;
7465 case 1:
7466 // op: rd
7467 return 0;
7468 }
7469 break;
7470 }
7471 case LoongArch::FCMP_CAF_D:
7472 case LoongArch::FCMP_CAF_S:
7473 case LoongArch::FCMP_CEQ_D:
7474 case LoongArch::FCMP_CEQ_S:
7475 case LoongArch::FCMP_CLE_D:
7476 case LoongArch::FCMP_CLE_S:
7477 case LoongArch::FCMP_CLT_D:
7478 case LoongArch::FCMP_CLT_S:
7479 case LoongArch::FCMP_CNE_D:
7480 case LoongArch::FCMP_CNE_S:
7481 case LoongArch::FCMP_COR_D:
7482 case LoongArch::FCMP_COR_S:
7483 case LoongArch::FCMP_CUEQ_D:
7484 case LoongArch::FCMP_CUEQ_S:
7485 case LoongArch::FCMP_CULE_D:
7486 case LoongArch::FCMP_CULE_S:
7487 case LoongArch::FCMP_CULT_D:
7488 case LoongArch::FCMP_CULT_S:
7489 case LoongArch::FCMP_CUNE_D:
7490 case LoongArch::FCMP_CUNE_S:
7491 case LoongArch::FCMP_CUN_D:
7492 case LoongArch::FCMP_CUN_S:
7493 case LoongArch::FCMP_SAF_D:
7494 case LoongArch::FCMP_SAF_S:
7495 case LoongArch::FCMP_SEQ_D:
7496 case LoongArch::FCMP_SEQ_S:
7497 case LoongArch::FCMP_SLE_D:
7498 case LoongArch::FCMP_SLE_S:
7499 case LoongArch::FCMP_SLT_D:
7500 case LoongArch::FCMP_SLT_S:
7501 case LoongArch::FCMP_SNE_D:
7502 case LoongArch::FCMP_SNE_S:
7503 case LoongArch::FCMP_SOR_D:
7504 case LoongArch::FCMP_SOR_S:
7505 case LoongArch::FCMP_SUEQ_D:
7506 case LoongArch::FCMP_SUEQ_S:
7507 case LoongArch::FCMP_SULE_D:
7508 case LoongArch::FCMP_SULE_S:
7509 case LoongArch::FCMP_SULT_D:
7510 case LoongArch::FCMP_SULT_S:
7511 case LoongArch::FCMP_SUNE_D:
7512 case LoongArch::FCMP_SUNE_S:
7513 case LoongArch::FCMP_SUN_D:
7514 case LoongArch::FCMP_SUN_S: {
7515 switch (OpNum) {
7516 case 2:
7517 // op: fk
7518 return 10;
7519 case 1:
7520 // op: fj
7521 return 5;
7522 case 0:
7523 // op: cd
7524 return 0;
7525 }
7526 break;
7527 }
7528 case LoongArch::FADD_D:
7529 case LoongArch::FADD_S:
7530 case LoongArch::FCOPYSIGN_D:
7531 case LoongArch::FCOPYSIGN_S:
7532 case LoongArch::FCVT_D_LD:
7533 case LoongArch::FDIV_D:
7534 case LoongArch::FDIV_S:
7535 case LoongArch::FMAXA_D:
7536 case LoongArch::FMAXA_S:
7537 case LoongArch::FMAX_D:
7538 case LoongArch::FMAX_S:
7539 case LoongArch::FMINA_D:
7540 case LoongArch::FMINA_S:
7541 case LoongArch::FMIN_D:
7542 case LoongArch::FMIN_S:
7543 case LoongArch::FMUL_D:
7544 case LoongArch::FMUL_S:
7545 case LoongArch::FSCALEB_D:
7546 case LoongArch::FSCALEB_S:
7547 case LoongArch::FSUB_D:
7548 case LoongArch::FSUB_S: {
7549 switch (OpNum) {
7550 case 2:
7551 // op: fk
7552 return 10;
7553 case 1:
7554 // op: fj
7555 return 5;
7556 case 0:
7557 // op: fd
7558 return 0;
7559 }
7560 break;
7561 }
7562 case LoongArch::VPICKVE2GR_D:
7563 case LoongArch::VPICKVE2GR_DU: {
7564 switch (OpNum) {
7565 case 2:
7566 // op: imm1
7567 return 10;
7568 case 1:
7569 // op: vj
7570 return 5;
7571 case 0:
7572 // op: rd
7573 return 0;
7574 }
7575 break;
7576 }
7577 case LoongArch::VREPLVEI_D: {
7578 switch (OpNum) {
7579 case 2:
7580 // op: imm1
7581 return 10;
7582 case 1:
7583 // op: vj
7584 return 5;
7585 case 0:
7586 // op: vd
7587 return 0;
7588 }
7589 break;
7590 }
7591 case LoongArch::XVREPL128VEI_D: {
7592 switch (OpNum) {
7593 case 2:
7594 // op: imm1
7595 return 10;
7596 case 1:
7597 // op: xj
7598 return 5;
7599 case 0:
7600 // op: xd
7601 return 0;
7602 }
7603 break;
7604 }
7605 case LoongArch::VLDREPL_W: {
7606 switch (OpNum) {
7607 case 2:
7608 // op: imm10
7609 return 10;
7610 case 1:
7611 // op: rj
7612 return 5;
7613 case 0:
7614 // op: vd
7615 return 0;
7616 }
7617 break;
7618 }
7619 case LoongArch::XVLDREPL_W: {
7620 switch (OpNum) {
7621 case 2:
7622 // op: imm10
7623 return 10;
7624 case 1:
7625 // op: rj
7626 return 5;
7627 case 0:
7628 // op: xd
7629 return 0;
7630 }
7631 break;
7632 }
7633 case LoongArch::VLDREPL_H: {
7634 switch (OpNum) {
7635 case 2:
7636 // op: imm11
7637 return 10;
7638 case 1:
7639 // op: rj
7640 return 5;
7641 case 0:
7642 // op: vd
7643 return 0;
7644 }
7645 break;
7646 }
7647 case LoongArch::XVLDREPL_H: {
7648 switch (OpNum) {
7649 case 2:
7650 // op: imm11
7651 return 10;
7652 case 1:
7653 // op: rj
7654 return 5;
7655 case 0:
7656 // op: xd
7657 return 0;
7658 }
7659 break;
7660 }
7661 case LoongArch::FLD_D:
7662 case LoongArch::FLD_S:
7663 case LoongArch::FST_D:
7664 case LoongArch::FST_S: {
7665 switch (OpNum) {
7666 case 2:
7667 // op: imm12
7668 return 10;
7669 case 1:
7670 // op: rj
7671 return 5;
7672 case 0:
7673 // op: fd
7674 return 0;
7675 }
7676 break;
7677 }
7678 case LoongArch::PRELD: {
7679 switch (OpNum) {
7680 case 2:
7681 // op: imm12
7682 return 10;
7683 case 1:
7684 // op: rj
7685 return 5;
7686 case 0:
7687 // op: imm5
7688 return 0;
7689 }
7690 break;
7691 }
7692 case LoongArch::CACOP: {
7693 switch (OpNum) {
7694 case 2:
7695 // op: imm12
7696 return 10;
7697 case 1:
7698 // op: rj
7699 return 5;
7700 case 0:
7701 // op: op
7702 return 0;
7703 }
7704 break;
7705 }
7706 case LoongArch::ADDI_D:
7707 case LoongArch::ADDI_W:
7708 case LoongArch::ANDI:
7709 case LoongArch::LDL_D:
7710 case LoongArch::LDL_W:
7711 case LoongArch::LDR_D:
7712 case LoongArch::LDR_W:
7713 case LoongArch::LD_B:
7714 case LoongArch::LD_BU:
7715 case LoongArch::LD_D:
7716 case LoongArch::LD_H:
7717 case LoongArch::LD_HU:
7718 case LoongArch::LD_W:
7719 case LoongArch::LD_WU:
7720 case LoongArch::LU52I_D:
7721 case LoongArch::ORI:
7722 case LoongArch::SLTI:
7723 case LoongArch::SLTUI:
7724 case LoongArch::STL_D:
7725 case LoongArch::STL_W:
7726 case LoongArch::STR_D:
7727 case LoongArch::STR_W:
7728 case LoongArch::ST_B:
7729 case LoongArch::ST_D:
7730 case LoongArch::ST_H:
7731 case LoongArch::ST_W:
7732 case LoongArch::XORI: {
7733 switch (OpNum) {
7734 case 2:
7735 // op: imm12
7736 return 10;
7737 case 1:
7738 // op: rj
7739 return 5;
7740 case 0:
7741 // op: rd
7742 return 0;
7743 }
7744 break;
7745 }
7746 case LoongArch::VLD:
7747 case LoongArch::VLDREPL_B:
7748 case LoongArch::VST: {
7749 switch (OpNum) {
7750 case 2:
7751 // op: imm12
7752 return 10;
7753 case 1:
7754 // op: rj
7755 return 5;
7756 case 0:
7757 // op: vd
7758 return 0;
7759 }
7760 break;
7761 }
7762 case LoongArch::XVLD:
7763 case LoongArch::XVLDREPL_B:
7764 case LoongArch::XVST: {
7765 switch (OpNum) {
7766 case 2:
7767 // op: imm12
7768 return 10;
7769 case 1:
7770 // op: rj
7771 return 5;
7772 case 0:
7773 // op: xd
7774 return 0;
7775 }
7776 break;
7777 }
7778 case LoongArch::LDPTR_D:
7779 case LoongArch::LDPTR_W:
7780 case LoongArch::LL_D:
7781 case LoongArch::LL_W:
7782 case LoongArch::STPTR_D:
7783 case LoongArch::STPTR_W: {
7784 switch (OpNum) {
7785 case 2:
7786 // op: imm14
7787 return 10;
7788 case 1:
7789 // op: rj
7790 return 5;
7791 case 0:
7792 // op: rd
7793 return 0;
7794 }
7795 break;
7796 }
7797 case LoongArch::BEQ:
7798 case LoongArch::BGE:
7799 case LoongArch::BGEU:
7800 case LoongArch::BLT:
7801 case LoongArch::BLTU:
7802 case LoongArch::BNE: {
7803 switch (OpNum) {
7804 case 2:
7805 // op: imm16
7806 return 10;
7807 case 0:
7808 // op: rj
7809 return 5;
7810 case 1:
7811 // op: rd
7812 return 0;
7813 }
7814 break;
7815 }
7816 case LoongArch::ADDU16I_D:
7817 case LoongArch::JIRL: {
7818 switch (OpNum) {
7819 case 2:
7820 // op: imm16
7821 return 10;
7822 case 1:
7823 // op: rj
7824 return 5;
7825 case 0:
7826 // op: rd
7827 return 0;
7828 }
7829 break;
7830 }
7831 case LoongArch::VPICKVE2GR_W:
7832 case LoongArch::VPICKVE2GR_WU: {
7833 switch (OpNum) {
7834 case 2:
7835 // op: imm2
7836 return 10;
7837 case 1:
7838 // op: vj
7839 return 5;
7840 case 0:
7841 // op: rd
7842 return 0;
7843 }
7844 break;
7845 }
7846 case LoongArch::VREPLVEI_W: {
7847 switch (OpNum) {
7848 case 2:
7849 // op: imm2
7850 return 10;
7851 case 1:
7852 // op: vj
7853 return 5;
7854 case 0:
7855 // op: vd
7856 return 0;
7857 }
7858 break;
7859 }
7860 case LoongArch::XVPICKVE2GR_D:
7861 case LoongArch::XVPICKVE2GR_DU: {
7862 switch (OpNum) {
7863 case 2:
7864 // op: imm2
7865 return 10;
7866 case 1:
7867 // op: xj
7868 return 5;
7869 case 0:
7870 // op: rd
7871 return 0;
7872 }
7873 break;
7874 }
7875 case LoongArch::XVPICKVE_D:
7876 case LoongArch::XVREPL128VEI_W: {
7877 switch (OpNum) {
7878 case 2:
7879 // op: imm2
7880 return 10;
7881 case 1:
7882 // op: xj
7883 return 5;
7884 case 0:
7885 // op: xd
7886 return 0;
7887 }
7888 break;
7889 }
7890 case LoongArch::LU32I_D: {
7891 switch (OpNum) {
7892 case 2:
7893 // op: imm20
7894 return 5;
7895 case 1:
7896 // op: rd
7897 return 0;
7898 }
7899 break;
7900 }
7901 case LoongArch::RCRI_B:
7902 case LoongArch::ROTRI_B: {
7903 switch (OpNum) {
7904 case 2:
7905 // op: imm3
7906 return 10;
7907 case 1:
7908 // op: rj
7909 return 5;
7910 case 0:
7911 // op: rd
7912 return 0;
7913 }
7914 break;
7915 }
7916 case LoongArch::VPICKVE2GR_H:
7917 case LoongArch::VPICKVE2GR_HU: {
7918 switch (OpNum) {
7919 case 2:
7920 // op: imm3
7921 return 10;
7922 case 1:
7923 // op: vj
7924 return 5;
7925 case 0:
7926 // op: rd
7927 return 0;
7928 }
7929 break;
7930 }
7931 case LoongArch::VBITCLRI_B:
7932 case LoongArch::VBITREVI_B:
7933 case LoongArch::VBITSETI_B:
7934 case LoongArch::VREPLVEI_H:
7935 case LoongArch::VROTRI_B:
7936 case LoongArch::VSAT_B:
7937 case LoongArch::VSAT_BU:
7938 case LoongArch::VSLLI_B:
7939 case LoongArch::VSLLWIL_HU_BU:
7940 case LoongArch::VSLLWIL_H_B:
7941 case LoongArch::VSRAI_B:
7942 case LoongArch::VSRARI_B:
7943 case LoongArch::VSRLI_B:
7944 case LoongArch::VSRLRI_B: {
7945 switch (OpNum) {
7946 case 2:
7947 // op: imm3
7948 return 10;
7949 case 1:
7950 // op: vj
7951 return 5;
7952 case 0:
7953 // op: vd
7954 return 0;
7955 }
7956 break;
7957 }
7958 case LoongArch::XVPICKVE2GR_W:
7959 case LoongArch::XVPICKVE2GR_WU: {
7960 switch (OpNum) {
7961 case 2:
7962 // op: imm3
7963 return 10;
7964 case 1:
7965 // op: xj
7966 return 5;
7967 case 0:
7968 // op: rd
7969 return 0;
7970 }
7971 break;
7972 }
7973 case LoongArch::XVBITCLRI_B:
7974 case LoongArch::XVBITREVI_B:
7975 case LoongArch::XVBITSETI_B:
7976 case LoongArch::XVPICKVE_W:
7977 case LoongArch::XVREPL128VEI_H:
7978 case LoongArch::XVROTRI_B:
7979 case LoongArch::XVSAT_B:
7980 case LoongArch::XVSAT_BU:
7981 case LoongArch::XVSLLI_B:
7982 case LoongArch::XVSLLWIL_HU_BU:
7983 case LoongArch::XVSLLWIL_H_B:
7984 case LoongArch::XVSRAI_B:
7985 case LoongArch::XVSRARI_B:
7986 case LoongArch::XVSRLI_B:
7987 case LoongArch::XVSRLRI_B: {
7988 switch (OpNum) {
7989 case 2:
7990 // op: imm3
7991 return 10;
7992 case 1:
7993 // op: xj
7994 return 5;
7995 case 0:
7996 // op: xd
7997 return 0;
7998 }
7999 break;
8000 }
8001 case LoongArch::ARMADC_W:
8002 case LoongArch::ARMADD_W:
8003 case LoongArch::ARMAND_W:
8004 case LoongArch::ARMOR_W:
8005 case LoongArch::ARMROTR_W:
8006 case LoongArch::ARMSBC_W:
8007 case LoongArch::ARMSLL_W:
8008 case LoongArch::ARMSRA_W:
8009 case LoongArch::ARMSRL_W:
8010 case LoongArch::ARMSUB_W:
8011 case LoongArch::ARMXOR_W: {
8012 switch (OpNum) {
8013 case 2:
8014 // op: imm4
8015 return 0;
8016 case 1:
8017 // op: rk
8018 return 10;
8019 case 0:
8020 // op: rj
8021 return 5;
8022 }
8023 break;
8024 }
8025 case LoongArch::ARMMOVE:
8026 case LoongArch::RCRI_H:
8027 case LoongArch::ROTRI_H: {
8028 switch (OpNum) {
8029 case 2:
8030 // op: imm4
8031 return 10;
8032 case 1:
8033 // op: rj
8034 return 5;
8035 case 0:
8036 // op: rd
8037 return 0;
8038 }
8039 break;
8040 }
8041 case LoongArch::VPICKVE2GR_B:
8042 case LoongArch::VPICKVE2GR_BU: {
8043 switch (OpNum) {
8044 case 2:
8045 // op: imm4
8046 return 10;
8047 case 1:
8048 // op: vj
8049 return 5;
8050 case 0:
8051 // op: rd
8052 return 0;
8053 }
8054 break;
8055 }
8056 case LoongArch::VBITCLRI_H:
8057 case LoongArch::VBITREVI_H:
8058 case LoongArch::VBITSETI_H:
8059 case LoongArch::VREPLVEI_B:
8060 case LoongArch::VROTRI_H:
8061 case LoongArch::VSAT_H:
8062 case LoongArch::VSAT_HU:
8063 case LoongArch::VSLLI_H:
8064 case LoongArch::VSLLWIL_WU_HU:
8065 case LoongArch::VSLLWIL_W_H:
8066 case LoongArch::VSRAI_H:
8067 case LoongArch::VSRARI_H:
8068 case LoongArch::VSRLI_H:
8069 case LoongArch::VSRLRI_H: {
8070 switch (OpNum) {
8071 case 2:
8072 // op: imm4
8073 return 10;
8074 case 1:
8075 // op: vj
8076 return 5;
8077 case 0:
8078 // op: vd
8079 return 0;
8080 }
8081 break;
8082 }
8083 case LoongArch::XVBITCLRI_H:
8084 case LoongArch::XVBITREVI_H:
8085 case LoongArch::XVBITSETI_H:
8086 case LoongArch::XVREPL128VEI_B:
8087 case LoongArch::XVROTRI_H:
8088 case LoongArch::XVSAT_H:
8089 case LoongArch::XVSAT_HU:
8090 case LoongArch::XVSLLI_H:
8091 case LoongArch::XVSLLWIL_WU_HU:
8092 case LoongArch::XVSLLWIL_W_H:
8093 case LoongArch::XVSRAI_H:
8094 case LoongArch::XVSRARI_H:
8095 case LoongArch::XVSRLI_H:
8096 case LoongArch::XVSRLRI_H: {
8097 switch (OpNum) {
8098 case 2:
8099 // op: imm4
8100 return 10;
8101 case 1:
8102 // op: xj
8103 return 5;
8104 case 0:
8105 // op: xd
8106 return 0;
8107 }
8108 break;
8109 }
8110 case LoongArch::ADDU12I_D:
8111 case LoongArch::ADDU12I_W:
8112 case LoongArch::RCRI_W:
8113 case LoongArch::ROTRI_W:
8114 case LoongArch::SLLI_W:
8115 case LoongArch::SRAI_W:
8116 case LoongArch::SRLI_W: {
8117 switch (OpNum) {
8118 case 2:
8119 // op: imm5
8120 return 10;
8121 case 1:
8122 // op: rj
8123 return 5;
8124 case 0:
8125 // op: rd
8126 return 0;
8127 }
8128 break;
8129 }
8130 case LoongArch::VADDI_BU:
8131 case LoongArch::VADDI_DU:
8132 case LoongArch::VADDI_HU:
8133 case LoongArch::VADDI_WU:
8134 case LoongArch::VBITCLRI_W:
8135 case LoongArch::VBITREVI_W:
8136 case LoongArch::VBITSETI_W:
8137 case LoongArch::VBSLL_V:
8138 case LoongArch::VBSRL_V:
8139 case LoongArch::VMAXI_B:
8140 case LoongArch::VMAXI_BU:
8141 case LoongArch::VMAXI_D:
8142 case LoongArch::VMAXI_DU:
8143 case LoongArch::VMAXI_H:
8144 case LoongArch::VMAXI_HU:
8145 case LoongArch::VMAXI_W:
8146 case LoongArch::VMAXI_WU:
8147 case LoongArch::VMINI_B:
8148 case LoongArch::VMINI_BU:
8149 case LoongArch::VMINI_D:
8150 case LoongArch::VMINI_DU:
8151 case LoongArch::VMINI_H:
8152 case LoongArch::VMINI_HU:
8153 case LoongArch::VMINI_W:
8154 case LoongArch::VMINI_WU:
8155 case LoongArch::VROTRI_W:
8156 case LoongArch::VSAT_W:
8157 case LoongArch::VSAT_WU:
8158 case LoongArch::VSEQI_B:
8159 case LoongArch::VSEQI_D:
8160 case LoongArch::VSEQI_H:
8161 case LoongArch::VSEQI_W:
8162 case LoongArch::VSLEI_B:
8163 case LoongArch::VSLEI_BU:
8164 case LoongArch::VSLEI_D:
8165 case LoongArch::VSLEI_DU:
8166 case LoongArch::VSLEI_H:
8167 case LoongArch::VSLEI_HU:
8168 case LoongArch::VSLEI_W:
8169 case LoongArch::VSLEI_WU:
8170 case LoongArch::VSLLI_W:
8171 case LoongArch::VSLLWIL_DU_WU:
8172 case LoongArch::VSLLWIL_D_W:
8173 case LoongArch::VSLTI_B:
8174 case LoongArch::VSLTI_BU:
8175 case LoongArch::VSLTI_D:
8176 case LoongArch::VSLTI_DU:
8177 case LoongArch::VSLTI_H:
8178 case LoongArch::VSLTI_HU:
8179 case LoongArch::VSLTI_W:
8180 case LoongArch::VSLTI_WU:
8181 case LoongArch::VSRAI_W:
8182 case LoongArch::VSRARI_W:
8183 case LoongArch::VSRLI_W:
8184 case LoongArch::VSRLRI_W:
8185 case LoongArch::VSUBI_BU:
8186 case LoongArch::VSUBI_DU:
8187 case LoongArch::VSUBI_HU:
8188 case LoongArch::VSUBI_WU: {
8189 switch (OpNum) {
8190 case 2:
8191 // op: imm5
8192 return 10;
8193 case 1:
8194 // op: vj
8195 return 5;
8196 case 0:
8197 // op: vd
8198 return 0;
8199 }
8200 break;
8201 }
8202 case LoongArch::XVADDI_BU:
8203 case LoongArch::XVADDI_DU:
8204 case LoongArch::XVADDI_HU:
8205 case LoongArch::XVADDI_WU:
8206 case LoongArch::XVBITCLRI_W:
8207 case LoongArch::XVBITREVI_W:
8208 case LoongArch::XVBITSETI_W:
8209 case LoongArch::XVBSLL_V:
8210 case LoongArch::XVBSRL_V:
8211 case LoongArch::XVHSELI_D:
8212 case LoongArch::XVMAXI_B:
8213 case LoongArch::XVMAXI_BU:
8214 case LoongArch::XVMAXI_D:
8215 case LoongArch::XVMAXI_DU:
8216 case LoongArch::XVMAXI_H:
8217 case LoongArch::XVMAXI_HU:
8218 case LoongArch::XVMAXI_W:
8219 case LoongArch::XVMAXI_WU:
8220 case LoongArch::XVMINI_B:
8221 case LoongArch::XVMINI_BU:
8222 case LoongArch::XVMINI_D:
8223 case LoongArch::XVMINI_DU:
8224 case LoongArch::XVMINI_H:
8225 case LoongArch::XVMINI_HU:
8226 case LoongArch::XVMINI_W:
8227 case LoongArch::XVMINI_WU:
8228 case LoongArch::XVROTRI_W:
8229 case LoongArch::XVSAT_W:
8230 case LoongArch::XVSAT_WU:
8231 case LoongArch::XVSEQI_B:
8232 case LoongArch::XVSEQI_D:
8233 case LoongArch::XVSEQI_H:
8234 case LoongArch::XVSEQI_W:
8235 case LoongArch::XVSLEI_B:
8236 case LoongArch::XVSLEI_BU:
8237 case LoongArch::XVSLEI_D:
8238 case LoongArch::XVSLEI_DU:
8239 case LoongArch::XVSLEI_H:
8240 case LoongArch::XVSLEI_HU:
8241 case LoongArch::XVSLEI_W:
8242 case LoongArch::XVSLEI_WU:
8243 case LoongArch::XVSLLI_W:
8244 case LoongArch::XVSLLWIL_DU_WU:
8245 case LoongArch::XVSLLWIL_D_W:
8246 case LoongArch::XVSLTI_B:
8247 case LoongArch::XVSLTI_BU:
8248 case LoongArch::XVSLTI_D:
8249 case LoongArch::XVSLTI_DU:
8250 case LoongArch::XVSLTI_H:
8251 case LoongArch::XVSLTI_HU:
8252 case LoongArch::XVSLTI_W:
8253 case LoongArch::XVSLTI_WU:
8254 case LoongArch::XVSRAI_W:
8255 case LoongArch::XVSRARI_W:
8256 case LoongArch::XVSRLI_W:
8257 case LoongArch::XVSRLRI_W:
8258 case LoongArch::XVSUBI_BU:
8259 case LoongArch::XVSUBI_DU:
8260 case LoongArch::XVSUBI_HU:
8261 case LoongArch::XVSUBI_WU: {
8262 switch (OpNum) {
8263 case 2:
8264 // op: imm5
8265 return 10;
8266 case 1:
8267 // op: xj
8268 return 5;
8269 case 0:
8270 // op: xd
8271 return 0;
8272 }
8273 break;
8274 }
8275 case LoongArch::RCRI_D:
8276 case LoongArch::ROTRI_D:
8277 case LoongArch::SLLI_D:
8278 case LoongArch::SRAI_D:
8279 case LoongArch::SRLI_D: {
8280 switch (OpNum) {
8281 case 2:
8282 // op: imm6
8283 return 10;
8284 case 1:
8285 // op: rj
8286 return 5;
8287 case 0:
8288 // op: rd
8289 return 0;
8290 }
8291 break;
8292 }
8293 case LoongArch::VBITCLRI_D:
8294 case LoongArch::VBITREVI_D:
8295 case LoongArch::VBITSETI_D:
8296 case LoongArch::VROTRI_D:
8297 case LoongArch::VSAT_D:
8298 case LoongArch::VSAT_DU:
8299 case LoongArch::VSLLI_D:
8300 case LoongArch::VSRAI_D:
8301 case LoongArch::VSRARI_D:
8302 case LoongArch::VSRLI_D:
8303 case LoongArch::VSRLRI_D: {
8304 switch (OpNum) {
8305 case 2:
8306 // op: imm6
8307 return 10;
8308 case 1:
8309 // op: vj
8310 return 5;
8311 case 0:
8312 // op: vd
8313 return 0;
8314 }
8315 break;
8316 }
8317 case LoongArch::XVBITCLRI_D:
8318 case LoongArch::XVBITREVI_D:
8319 case LoongArch::XVBITSETI_D:
8320 case LoongArch::XVROTRI_D:
8321 case LoongArch::XVSAT_D:
8322 case LoongArch::XVSAT_DU:
8323 case LoongArch::XVSLLI_D:
8324 case LoongArch::XVSRAI_D:
8325 case LoongArch::XVSRARI_D:
8326 case LoongArch::XVSRLI_D:
8327 case LoongArch::XVSRLRI_D: {
8328 switch (OpNum) {
8329 case 2:
8330 // op: imm6
8331 return 10;
8332 case 1:
8333 // op: xj
8334 return 5;
8335 case 0:
8336 // op: xd
8337 return 0;
8338 }
8339 break;
8340 }
8341 case LoongArch::X86SETTAG: {
8342 switch (OpNum) {
8343 case 2:
8344 // op: imm8
8345 return 10;
8346 case 1:
8347 // op: imm5
8348 return 5;
8349 case 0:
8350 // op: rd
8351 return 0;
8352 }
8353 break;
8354 }
8355 case LoongArch::LDDIR: {
8356 switch (OpNum) {
8357 case 2:
8358 // op: imm8
8359 return 10;
8360 case 1:
8361 // op: rj
8362 return 5;
8363 case 0:
8364 // op: rd
8365 return 0;
8366 }
8367 break;
8368 }
8369 case LoongArch::VANDI_B:
8370 case LoongArch::VNORI_B:
8371 case LoongArch::VORI_B:
8372 case LoongArch::VSHUF4I_B:
8373 case LoongArch::VSHUF4I_H:
8374 case LoongArch::VSHUF4I_W:
8375 case LoongArch::VXORI_B: {
8376 switch (OpNum) {
8377 case 2:
8378 // op: imm8
8379 return 10;
8380 case 1:
8381 // op: vj
8382 return 5;
8383 case 0:
8384 // op: vd
8385 return 0;
8386 }
8387 break;
8388 }
8389 case LoongArch::XVANDI_B:
8390 case LoongArch::XVNORI_B:
8391 case LoongArch::XVORI_B:
8392 case LoongArch::XVPERMI_D:
8393 case LoongArch::XVSHUF4I_B:
8394 case LoongArch::XVSHUF4I_H:
8395 case LoongArch::XVSHUF4I_W:
8396 case LoongArch::XVXORI_B: {
8397 switch (OpNum) {
8398 case 2:
8399 // op: imm8
8400 return 10;
8401 case 1:
8402 // op: xj
8403 return 5;
8404 case 0:
8405 // op: xd
8406 return 0;
8407 }
8408 break;
8409 }
8410 case LoongArch::VLDREPL_D: {
8411 switch (OpNum) {
8412 case 2:
8413 // op: imm9
8414 return 10;
8415 case 1:
8416 // op: rj
8417 return 5;
8418 case 0:
8419 // op: vd
8420 return 0;
8421 }
8422 break;
8423 }
8424 case LoongArch::XVLDREPL_D: {
8425 switch (OpNum) {
8426 case 2:
8427 // op: imm9
8428 return 10;
8429 case 1:
8430 // op: rj
8431 return 5;
8432 case 0:
8433 // op: xd
8434 return 0;
8435 }
8436 break;
8437 }
8438 case LoongArch::BSTRPICK_D: {
8439 switch (OpNum) {
8440 case 2:
8441 // op: msbd
8442 return 16;
8443 case 3:
8444 // op: lsbd
8445 return 10;
8446 case 1:
8447 // op: rj
8448 return 5;
8449 case 0:
8450 // op: rd
8451 return 0;
8452 }
8453 break;
8454 }
8455 case LoongArch::BSTRPICK_W: {
8456 switch (OpNum) {
8457 case 2:
8458 // op: msbw
8459 return 16;
8460 case 3:
8461 // op: lsbw
8462 return 10;
8463 case 1:
8464 // op: rj
8465 return 5;
8466 case 0:
8467 // op: rd
8468 return 0;
8469 }
8470 break;
8471 }
8472 case LoongArch::SCREL_D:
8473 case LoongArch::SCREL_W: {
8474 switch (OpNum) {
8475 case 2:
8476 // op: rj
8477 return 5;
8478 case 1:
8479 // op: rd
8480 return 0;
8481 }
8482 break;
8483 }
8484 case LoongArch::FLDGT_D:
8485 case LoongArch::FLDGT_S:
8486 case LoongArch::FLDLE_D:
8487 case LoongArch::FLDLE_S:
8488 case LoongArch::FLDX_D:
8489 case LoongArch::FLDX_S:
8490 case LoongArch::FSTGT_D:
8491 case LoongArch::FSTGT_S:
8492 case LoongArch::FSTLE_D:
8493 case LoongArch::FSTLE_S:
8494 case LoongArch::FSTX_D:
8495 case LoongArch::FSTX_S: {
8496 switch (OpNum) {
8497 case 2:
8498 // op: rk
8499 return 10;
8500 case 1:
8501 // op: rj
8502 return 5;
8503 case 0:
8504 // op: fd
8505 return 0;
8506 }
8507 break;
8508 }
8509 case LoongArch::PRELDX: {
8510 switch (OpNum) {
8511 case 2:
8512 // op: rk
8513 return 10;
8514 case 1:
8515 // op: rj
8516 return 5;
8517 case 0:
8518 // op: imm5
8519 return 0;
8520 }
8521 break;
8522 }
8523 case LoongArch::ADC_B:
8524 case LoongArch::ADC_D:
8525 case LoongArch::ADC_H:
8526 case LoongArch::ADC_W:
8527 case LoongArch::ADD_D:
8528 case LoongArch::ADD_W:
8529 case LoongArch::AND:
8530 case LoongArch::ANDN:
8531 case LoongArch::CRCC_W_B_W:
8532 case LoongArch::CRCC_W_D_W:
8533 case LoongArch::CRCC_W_H_W:
8534 case LoongArch::CRCC_W_W_W:
8535 case LoongArch::CRC_W_B_W:
8536 case LoongArch::CRC_W_D_W:
8537 case LoongArch::CRC_W_H_W:
8538 case LoongArch::CRC_W_W_W:
8539 case LoongArch::DIV_D:
8540 case LoongArch::DIV_DU:
8541 case LoongArch::DIV_W:
8542 case LoongArch::DIV_WU:
8543 case LoongArch::LDGT_B:
8544 case LoongArch::LDGT_D:
8545 case LoongArch::LDGT_H:
8546 case LoongArch::LDGT_W:
8547 case LoongArch::LDLE_B:
8548 case LoongArch::LDLE_D:
8549 case LoongArch::LDLE_H:
8550 case LoongArch::LDLE_W:
8551 case LoongArch::LDX_B:
8552 case LoongArch::LDX_BU:
8553 case LoongArch::LDX_D:
8554 case LoongArch::LDX_H:
8555 case LoongArch::LDX_HU:
8556 case LoongArch::LDX_W:
8557 case LoongArch::LDX_WU:
8558 case LoongArch::MASKEQZ:
8559 case LoongArch::MASKNEZ:
8560 case LoongArch::MOD_D:
8561 case LoongArch::MOD_DU:
8562 case LoongArch::MOD_W:
8563 case LoongArch::MOD_WU:
8564 case LoongArch::MULH_D:
8565 case LoongArch::MULH_DU:
8566 case LoongArch::MULH_W:
8567 case LoongArch::MULH_WU:
8568 case LoongArch::MULW_D_W:
8569 case LoongArch::MULW_D_WU:
8570 case LoongArch::MUL_D:
8571 case LoongArch::MUL_W:
8572 case LoongArch::NOR:
8573 case LoongArch::OR:
8574 case LoongArch::ORN:
8575 case LoongArch::RCR_B:
8576 case LoongArch::RCR_D:
8577 case LoongArch::RCR_H:
8578 case LoongArch::RCR_W:
8579 case LoongArch::ROTR_B:
8580 case LoongArch::ROTR_D:
8581 case LoongArch::ROTR_H:
8582 case LoongArch::ROTR_W:
8583 case LoongArch::SBC_B:
8584 case LoongArch::SBC_D:
8585 case LoongArch::SBC_H:
8586 case LoongArch::SBC_W:
8587 case LoongArch::SLL_D:
8588 case LoongArch::SLL_W:
8589 case LoongArch::SLT:
8590 case LoongArch::SLTU:
8591 case LoongArch::SRA_D:
8592 case LoongArch::SRA_W:
8593 case LoongArch::SRL_D:
8594 case LoongArch::SRL_W:
8595 case LoongArch::STGT_B:
8596 case LoongArch::STGT_D:
8597 case LoongArch::STGT_H:
8598 case LoongArch::STGT_W:
8599 case LoongArch::STLE_B:
8600 case LoongArch::STLE_D:
8601 case LoongArch::STLE_H:
8602 case LoongArch::STLE_W:
8603 case LoongArch::STX_B:
8604 case LoongArch::STX_D:
8605 case LoongArch::STX_H:
8606 case LoongArch::STX_W:
8607 case LoongArch::SUB_D:
8608 case LoongArch::SUB_W:
8609 case LoongArch::XOR: {
8610 switch (OpNum) {
8611 case 2:
8612 // op: rk
8613 return 10;
8614 case 1:
8615 // op: rj
8616 return 5;
8617 case 0:
8618 // op: rd
8619 return 0;
8620 }
8621 break;
8622 }
8623 case LoongArch::VLDX:
8624 case LoongArch::VSTX: {
8625 switch (OpNum) {
8626 case 2:
8627 // op: rk
8628 return 10;
8629 case 1:
8630 // op: rj
8631 return 5;
8632 case 0:
8633 // op: vd
8634 return 0;
8635 }
8636 break;
8637 }
8638 case LoongArch::XVLDX:
8639 case LoongArch::XVSTX: {
8640 switch (OpNum) {
8641 case 2:
8642 // op: rk
8643 return 10;
8644 case 1:
8645 // op: rj
8646 return 5;
8647 case 0:
8648 // op: xd
8649 return 0;
8650 }
8651 break;
8652 }
8653 case LoongArch::VREPLVE_B:
8654 case LoongArch::VREPLVE_D:
8655 case LoongArch::VREPLVE_H:
8656 case LoongArch::VREPLVE_W: {
8657 switch (OpNum) {
8658 case 2:
8659 // op: rk
8660 return 10;
8661 case 1:
8662 // op: vj
8663 return 5;
8664 case 0:
8665 // op: vd
8666 return 0;
8667 }
8668 break;
8669 }
8670 case LoongArch::XVREPLVE_B:
8671 case LoongArch::XVREPLVE_D:
8672 case LoongArch::XVREPLVE_H:
8673 case LoongArch::XVREPLVE_W: {
8674 switch (OpNum) {
8675 case 2:
8676 // op: rk
8677 return 10;
8678 case 1:
8679 // op: xj
8680 return 5;
8681 case 0:
8682 // op: xd
8683 return 0;
8684 }
8685 break;
8686 }
8687 case LoongArch::AMCAS_B:
8688 case LoongArch::AMCAS_D:
8689 case LoongArch::AMCAS_H:
8690 case LoongArch::AMCAS_W:
8691 case LoongArch::AMCAS__DB_B:
8692 case LoongArch::AMCAS__DB_D:
8693 case LoongArch::AMCAS__DB_H:
8694 case LoongArch::AMCAS__DB_W:
8695 case LoongArch::SC_Q: {
8696 switch (OpNum) {
8697 case 2:
8698 // op: rk
8699 return 10;
8700 case 3:
8701 // op: rj
8702 return 5;
8703 case 1:
8704 // op: rd
8705 return 0;
8706 }
8707 break;
8708 }
8709 case LoongArch::MOVGR2FRH_W: {
8710 switch (OpNum) {
8711 case 2:
8712 // op: src
8713 return 5;
8714 case 1:
8715 // op: dst
8716 return 0;
8717 }
8718 break;
8719 }
8720 case LoongArch::VABSD_B:
8721 case LoongArch::VABSD_BU:
8722 case LoongArch::VABSD_D:
8723 case LoongArch::VABSD_DU:
8724 case LoongArch::VABSD_H:
8725 case LoongArch::VABSD_HU:
8726 case LoongArch::VABSD_W:
8727 case LoongArch::VABSD_WU:
8728 case LoongArch::VADDA_B:
8729 case LoongArch::VADDA_D:
8730 case LoongArch::VADDA_H:
8731 case LoongArch::VADDA_W:
8732 case LoongArch::VADDWEV_D_W:
8733 case LoongArch::VADDWEV_D_WU:
8734 case LoongArch::VADDWEV_D_WU_W:
8735 case LoongArch::VADDWEV_H_B:
8736 case LoongArch::VADDWEV_H_BU:
8737 case LoongArch::VADDWEV_H_BU_B:
8738 case LoongArch::VADDWEV_Q_D:
8739 case LoongArch::VADDWEV_Q_DU:
8740 case LoongArch::VADDWEV_Q_DU_D:
8741 case LoongArch::VADDWEV_W_H:
8742 case LoongArch::VADDWEV_W_HU:
8743 case LoongArch::VADDWEV_W_HU_H:
8744 case LoongArch::VADDWOD_D_W:
8745 case LoongArch::VADDWOD_D_WU:
8746 case LoongArch::VADDWOD_D_WU_W:
8747 case LoongArch::VADDWOD_H_B:
8748 case LoongArch::VADDWOD_H_BU:
8749 case LoongArch::VADDWOD_H_BU_B:
8750 case LoongArch::VADDWOD_Q_D:
8751 case LoongArch::VADDWOD_Q_DU:
8752 case LoongArch::VADDWOD_Q_DU_D:
8753 case LoongArch::VADDWOD_W_H:
8754 case LoongArch::VADDWOD_W_HU:
8755 case LoongArch::VADDWOD_W_HU_H:
8756 case LoongArch::VADD_B:
8757 case LoongArch::VADD_D:
8758 case LoongArch::VADD_H:
8759 case LoongArch::VADD_Q:
8760 case LoongArch::VADD_W:
8761 case LoongArch::VANDN_V:
8762 case LoongArch::VAND_V:
8763 case LoongArch::VAVGR_B:
8764 case LoongArch::VAVGR_BU:
8765 case LoongArch::VAVGR_D:
8766 case LoongArch::VAVGR_DU:
8767 case LoongArch::VAVGR_H:
8768 case LoongArch::VAVGR_HU:
8769 case LoongArch::VAVGR_W:
8770 case LoongArch::VAVGR_WU:
8771 case LoongArch::VAVG_B:
8772 case LoongArch::VAVG_BU:
8773 case LoongArch::VAVG_D:
8774 case LoongArch::VAVG_DU:
8775 case LoongArch::VAVG_H:
8776 case LoongArch::VAVG_HU:
8777 case LoongArch::VAVG_W:
8778 case LoongArch::VAVG_WU:
8779 case LoongArch::VBITCLR_B:
8780 case LoongArch::VBITCLR_D:
8781 case LoongArch::VBITCLR_H:
8782 case LoongArch::VBITCLR_W:
8783 case LoongArch::VBITREV_B:
8784 case LoongArch::VBITREV_D:
8785 case LoongArch::VBITREV_H:
8786 case LoongArch::VBITREV_W:
8787 case LoongArch::VBITSET_B:
8788 case LoongArch::VBITSET_D:
8789 case LoongArch::VBITSET_H:
8790 case LoongArch::VBITSET_W:
8791 case LoongArch::VDIV_B:
8792 case LoongArch::VDIV_BU:
8793 case LoongArch::VDIV_D:
8794 case LoongArch::VDIV_DU:
8795 case LoongArch::VDIV_H:
8796 case LoongArch::VDIV_HU:
8797 case LoongArch::VDIV_W:
8798 case LoongArch::VDIV_WU:
8799 case LoongArch::VFADD_D:
8800 case LoongArch::VFADD_S:
8801 case LoongArch::VFCMP_CAF_D:
8802 case LoongArch::VFCMP_CAF_S:
8803 case LoongArch::VFCMP_CEQ_D:
8804 case LoongArch::VFCMP_CEQ_S:
8805 case LoongArch::VFCMP_CLE_D:
8806 case LoongArch::VFCMP_CLE_S:
8807 case LoongArch::VFCMP_CLT_D:
8808 case LoongArch::VFCMP_CLT_S:
8809 case LoongArch::VFCMP_CNE_D:
8810 case LoongArch::VFCMP_CNE_S:
8811 case LoongArch::VFCMP_COR_D:
8812 case LoongArch::VFCMP_COR_S:
8813 case LoongArch::VFCMP_CUEQ_D:
8814 case LoongArch::VFCMP_CUEQ_S:
8815 case LoongArch::VFCMP_CULE_D:
8816 case LoongArch::VFCMP_CULE_S:
8817 case LoongArch::VFCMP_CULT_D:
8818 case LoongArch::VFCMP_CULT_S:
8819 case LoongArch::VFCMP_CUNE_D:
8820 case LoongArch::VFCMP_CUNE_S:
8821 case LoongArch::VFCMP_CUN_D:
8822 case LoongArch::VFCMP_CUN_S:
8823 case LoongArch::VFCMP_SAF_D:
8824 case LoongArch::VFCMP_SAF_S:
8825 case LoongArch::VFCMP_SEQ_D:
8826 case LoongArch::VFCMP_SEQ_S:
8827 case LoongArch::VFCMP_SLE_D:
8828 case LoongArch::VFCMP_SLE_S:
8829 case LoongArch::VFCMP_SLT_D:
8830 case LoongArch::VFCMP_SLT_S:
8831 case LoongArch::VFCMP_SNE_D:
8832 case LoongArch::VFCMP_SNE_S:
8833 case LoongArch::VFCMP_SOR_D:
8834 case LoongArch::VFCMP_SOR_S:
8835 case LoongArch::VFCMP_SUEQ_D:
8836 case LoongArch::VFCMP_SUEQ_S:
8837 case LoongArch::VFCMP_SULE_D:
8838 case LoongArch::VFCMP_SULE_S:
8839 case LoongArch::VFCMP_SULT_D:
8840 case LoongArch::VFCMP_SULT_S:
8841 case LoongArch::VFCMP_SUNE_D:
8842 case LoongArch::VFCMP_SUNE_S:
8843 case LoongArch::VFCMP_SUN_D:
8844 case LoongArch::VFCMP_SUN_S:
8845 case LoongArch::VFCVT_H_S:
8846 case LoongArch::VFCVT_S_D:
8847 case LoongArch::VFDIV_D:
8848 case LoongArch::VFDIV_S:
8849 case LoongArch::VFFINT_S_L:
8850 case LoongArch::VFMAXA_D:
8851 case LoongArch::VFMAXA_S:
8852 case LoongArch::VFMAX_D:
8853 case LoongArch::VFMAX_S:
8854 case LoongArch::VFMINA_D:
8855 case LoongArch::VFMINA_S:
8856 case LoongArch::VFMIN_D:
8857 case LoongArch::VFMIN_S:
8858 case LoongArch::VFMUL_D:
8859 case LoongArch::VFMUL_S:
8860 case LoongArch::VFSUB_D:
8861 case LoongArch::VFSUB_S:
8862 case LoongArch::VFTINTRM_W_D:
8863 case LoongArch::VFTINTRNE_W_D:
8864 case LoongArch::VFTINTRP_W_D:
8865 case LoongArch::VFTINTRZ_W_D:
8866 case LoongArch::VFTINT_W_D:
8867 case LoongArch::VHADDW_DU_WU:
8868 case LoongArch::VHADDW_D_W:
8869 case LoongArch::VHADDW_HU_BU:
8870 case LoongArch::VHADDW_H_B:
8871 case LoongArch::VHADDW_QU_DU:
8872 case LoongArch::VHADDW_Q_D:
8873 case LoongArch::VHADDW_WU_HU:
8874 case LoongArch::VHADDW_W_H:
8875 case LoongArch::VHSUBW_DU_WU:
8876 case LoongArch::VHSUBW_D_W:
8877 case LoongArch::VHSUBW_HU_BU:
8878 case LoongArch::VHSUBW_H_B:
8879 case LoongArch::VHSUBW_QU_DU:
8880 case LoongArch::VHSUBW_Q_D:
8881 case LoongArch::VHSUBW_WU_HU:
8882 case LoongArch::VHSUBW_W_H:
8883 case LoongArch::VILVH_B:
8884 case LoongArch::VILVH_D:
8885 case LoongArch::VILVH_H:
8886 case LoongArch::VILVH_W:
8887 case LoongArch::VILVL_B:
8888 case LoongArch::VILVL_D:
8889 case LoongArch::VILVL_H:
8890 case LoongArch::VILVL_W:
8891 case LoongArch::VMAX_B:
8892 case LoongArch::VMAX_BU:
8893 case LoongArch::VMAX_D:
8894 case LoongArch::VMAX_DU:
8895 case LoongArch::VMAX_H:
8896 case LoongArch::VMAX_HU:
8897 case LoongArch::VMAX_W:
8898 case LoongArch::VMAX_WU:
8899 case LoongArch::VMIN_B:
8900 case LoongArch::VMIN_BU:
8901 case LoongArch::VMIN_D:
8902 case LoongArch::VMIN_DU:
8903 case LoongArch::VMIN_H:
8904 case LoongArch::VMIN_HU:
8905 case LoongArch::VMIN_W:
8906 case LoongArch::VMIN_WU:
8907 case LoongArch::VMOD_B:
8908 case LoongArch::VMOD_BU:
8909 case LoongArch::VMOD_D:
8910 case LoongArch::VMOD_DU:
8911 case LoongArch::VMOD_H:
8912 case LoongArch::VMOD_HU:
8913 case LoongArch::VMOD_W:
8914 case LoongArch::VMOD_WU:
8915 case LoongArch::VMUH_B:
8916 case LoongArch::VMUH_BU:
8917 case LoongArch::VMUH_D:
8918 case LoongArch::VMUH_DU:
8919 case LoongArch::VMUH_H:
8920 case LoongArch::VMUH_HU:
8921 case LoongArch::VMUH_W:
8922 case LoongArch::VMUH_WU:
8923 case LoongArch::VMULWEV_D_W:
8924 case LoongArch::VMULWEV_D_WU:
8925 case LoongArch::VMULWEV_D_WU_W:
8926 case LoongArch::VMULWEV_H_B:
8927 case LoongArch::VMULWEV_H_BU:
8928 case LoongArch::VMULWEV_H_BU_B:
8929 case LoongArch::VMULWEV_Q_D:
8930 case LoongArch::VMULWEV_Q_DU:
8931 case LoongArch::VMULWEV_Q_DU_D:
8932 case LoongArch::VMULWEV_W_H:
8933 case LoongArch::VMULWEV_W_HU:
8934 case LoongArch::VMULWEV_W_HU_H:
8935 case LoongArch::VMULWOD_D_W:
8936 case LoongArch::VMULWOD_D_WU:
8937 case LoongArch::VMULWOD_D_WU_W:
8938 case LoongArch::VMULWOD_H_B:
8939 case LoongArch::VMULWOD_H_BU:
8940 case LoongArch::VMULWOD_H_BU_B:
8941 case LoongArch::VMULWOD_Q_D:
8942 case LoongArch::VMULWOD_Q_DU:
8943 case LoongArch::VMULWOD_Q_DU_D:
8944 case LoongArch::VMULWOD_W_H:
8945 case LoongArch::VMULWOD_W_HU:
8946 case LoongArch::VMULWOD_W_HU_H:
8947 case LoongArch::VMUL_B:
8948 case LoongArch::VMUL_D:
8949 case LoongArch::VMUL_H:
8950 case LoongArch::VMUL_W:
8951 case LoongArch::VNOR_V:
8952 case LoongArch::VORN_V:
8953 case LoongArch::VOR_V:
8954 case LoongArch::VPACKEV_B:
8955 case LoongArch::VPACKEV_D:
8956 case LoongArch::VPACKEV_H:
8957 case LoongArch::VPACKEV_W:
8958 case LoongArch::VPACKOD_B:
8959 case LoongArch::VPACKOD_D:
8960 case LoongArch::VPACKOD_H:
8961 case LoongArch::VPACKOD_W:
8962 case LoongArch::VPICKEV_B:
8963 case LoongArch::VPICKEV_D:
8964 case LoongArch::VPICKEV_H:
8965 case LoongArch::VPICKEV_W:
8966 case LoongArch::VPICKOD_B:
8967 case LoongArch::VPICKOD_D:
8968 case LoongArch::VPICKOD_H:
8969 case LoongArch::VPICKOD_W:
8970 case LoongArch::VROTR_B:
8971 case LoongArch::VROTR_D:
8972 case LoongArch::VROTR_H:
8973 case LoongArch::VROTR_W:
8974 case LoongArch::VSADD_B:
8975 case LoongArch::VSADD_BU:
8976 case LoongArch::VSADD_D:
8977 case LoongArch::VSADD_DU:
8978 case LoongArch::VSADD_H:
8979 case LoongArch::VSADD_HU:
8980 case LoongArch::VSADD_W:
8981 case LoongArch::VSADD_WU:
8982 case LoongArch::VSEQ_B:
8983 case LoongArch::VSEQ_D:
8984 case LoongArch::VSEQ_H:
8985 case LoongArch::VSEQ_W:
8986 case LoongArch::VSIGNCOV_B:
8987 case LoongArch::VSIGNCOV_D:
8988 case LoongArch::VSIGNCOV_H:
8989 case LoongArch::VSIGNCOV_W:
8990 case LoongArch::VSLE_B:
8991 case LoongArch::VSLE_BU:
8992 case LoongArch::VSLE_D:
8993 case LoongArch::VSLE_DU:
8994 case LoongArch::VSLE_H:
8995 case LoongArch::VSLE_HU:
8996 case LoongArch::VSLE_W:
8997 case LoongArch::VSLE_WU:
8998 case LoongArch::VSLL_B:
8999 case LoongArch::VSLL_D:
9000 case LoongArch::VSLL_H:
9001 case LoongArch::VSLL_W:
9002 case LoongArch::VSLT_B:
9003 case LoongArch::VSLT_BU:
9004 case LoongArch::VSLT_D:
9005 case LoongArch::VSLT_DU:
9006 case LoongArch::VSLT_H:
9007 case LoongArch::VSLT_HU:
9008 case LoongArch::VSLT_W:
9009 case LoongArch::VSLT_WU:
9010 case LoongArch::VSRAN_B_H:
9011 case LoongArch::VSRAN_H_W:
9012 case LoongArch::VSRAN_W_D:
9013 case LoongArch::VSRARN_B_H:
9014 case LoongArch::VSRARN_H_W:
9015 case LoongArch::VSRARN_W_D:
9016 case LoongArch::VSRAR_B:
9017 case LoongArch::VSRAR_D:
9018 case LoongArch::VSRAR_H:
9019 case LoongArch::VSRAR_W:
9020 case LoongArch::VSRA_B:
9021 case LoongArch::VSRA_D:
9022 case LoongArch::VSRA_H:
9023 case LoongArch::VSRA_W:
9024 case LoongArch::VSRLN_B_H:
9025 case LoongArch::VSRLN_H_W:
9026 case LoongArch::VSRLN_W_D:
9027 case LoongArch::VSRLRN_B_H:
9028 case LoongArch::VSRLRN_H_W:
9029 case LoongArch::VSRLRN_W_D:
9030 case LoongArch::VSRLR_B:
9031 case LoongArch::VSRLR_D:
9032 case LoongArch::VSRLR_H:
9033 case LoongArch::VSRLR_W:
9034 case LoongArch::VSRL_B:
9035 case LoongArch::VSRL_D:
9036 case LoongArch::VSRL_H:
9037 case LoongArch::VSRL_W:
9038 case LoongArch::VSSRAN_BU_H:
9039 case LoongArch::VSSRAN_B_H:
9040 case LoongArch::VSSRAN_HU_W:
9041 case LoongArch::VSSRAN_H_W:
9042 case LoongArch::VSSRAN_WU_D:
9043 case LoongArch::VSSRAN_W_D:
9044 case LoongArch::VSSRARN_BU_H:
9045 case LoongArch::VSSRARN_B_H:
9046 case LoongArch::VSSRARN_HU_W:
9047 case LoongArch::VSSRARN_H_W:
9048 case LoongArch::VSSRARN_WU_D:
9049 case LoongArch::VSSRARN_W_D:
9050 case LoongArch::VSSRLN_BU_H:
9051 case LoongArch::VSSRLN_B_H:
9052 case LoongArch::VSSRLN_HU_W:
9053 case LoongArch::VSSRLN_H_W:
9054 case LoongArch::VSSRLN_WU_D:
9055 case LoongArch::VSSRLN_W_D:
9056 case LoongArch::VSSRLRN_BU_H:
9057 case LoongArch::VSSRLRN_B_H:
9058 case LoongArch::VSSRLRN_HU_W:
9059 case LoongArch::VSSRLRN_H_W:
9060 case LoongArch::VSSRLRN_WU_D:
9061 case LoongArch::VSSRLRN_W_D:
9062 case LoongArch::VSSUB_B:
9063 case LoongArch::VSSUB_BU:
9064 case LoongArch::VSSUB_D:
9065 case LoongArch::VSSUB_DU:
9066 case LoongArch::VSSUB_H:
9067 case LoongArch::VSSUB_HU:
9068 case LoongArch::VSSUB_W:
9069 case LoongArch::VSSUB_WU:
9070 case LoongArch::VSUBWEV_D_W:
9071 case LoongArch::VSUBWEV_D_WU:
9072 case LoongArch::VSUBWEV_H_B:
9073 case LoongArch::VSUBWEV_H_BU:
9074 case LoongArch::VSUBWEV_Q_D:
9075 case LoongArch::VSUBWEV_Q_DU:
9076 case LoongArch::VSUBWEV_W_H:
9077 case LoongArch::VSUBWEV_W_HU:
9078 case LoongArch::VSUBWOD_D_W:
9079 case LoongArch::VSUBWOD_D_WU:
9080 case LoongArch::VSUBWOD_H_B:
9081 case LoongArch::VSUBWOD_H_BU:
9082 case LoongArch::VSUBWOD_Q_D:
9083 case LoongArch::VSUBWOD_Q_DU:
9084 case LoongArch::VSUBWOD_W_H:
9085 case LoongArch::VSUBWOD_W_HU:
9086 case LoongArch::VSUB_B:
9087 case LoongArch::VSUB_D:
9088 case LoongArch::VSUB_H:
9089 case LoongArch::VSUB_Q:
9090 case LoongArch::VSUB_W:
9091 case LoongArch::VXOR_V: {
9092 switch (OpNum) {
9093 case 2:
9094 // op: vk
9095 return 10;
9096 case 1:
9097 // op: vj
9098 return 5;
9099 case 0:
9100 // op: vd
9101 return 0;
9102 }
9103 break;
9104 }
9105 case LoongArch::XVABSD_B:
9106 case LoongArch::XVABSD_BU:
9107 case LoongArch::XVABSD_D:
9108 case LoongArch::XVABSD_DU:
9109 case LoongArch::XVABSD_H:
9110 case LoongArch::XVABSD_HU:
9111 case LoongArch::XVABSD_W:
9112 case LoongArch::XVABSD_WU:
9113 case LoongArch::XVADDA_B:
9114 case LoongArch::XVADDA_D:
9115 case LoongArch::XVADDA_H:
9116 case LoongArch::XVADDA_W:
9117 case LoongArch::XVADDWEV_D_W:
9118 case LoongArch::XVADDWEV_D_WU:
9119 case LoongArch::XVADDWEV_D_WU_W:
9120 case LoongArch::XVADDWEV_H_B:
9121 case LoongArch::XVADDWEV_H_BU:
9122 case LoongArch::XVADDWEV_H_BU_B:
9123 case LoongArch::XVADDWEV_Q_D:
9124 case LoongArch::XVADDWEV_Q_DU:
9125 case LoongArch::XVADDWEV_Q_DU_D:
9126 case LoongArch::XVADDWEV_W_H:
9127 case LoongArch::XVADDWEV_W_HU:
9128 case LoongArch::XVADDWEV_W_HU_H:
9129 case LoongArch::XVADDWOD_D_W:
9130 case LoongArch::XVADDWOD_D_WU:
9131 case LoongArch::XVADDWOD_D_WU_W:
9132 case LoongArch::XVADDWOD_H_B:
9133 case LoongArch::XVADDWOD_H_BU:
9134 case LoongArch::XVADDWOD_H_BU_B:
9135 case LoongArch::XVADDWOD_Q_D:
9136 case LoongArch::XVADDWOD_Q_DU:
9137 case LoongArch::XVADDWOD_Q_DU_D:
9138 case LoongArch::XVADDWOD_W_H:
9139 case LoongArch::XVADDWOD_W_HU:
9140 case LoongArch::XVADDWOD_W_HU_H:
9141 case LoongArch::XVADD_B:
9142 case LoongArch::XVADD_D:
9143 case LoongArch::XVADD_H:
9144 case LoongArch::XVADD_Q:
9145 case LoongArch::XVADD_W:
9146 case LoongArch::XVANDN_V:
9147 case LoongArch::XVAND_V:
9148 case LoongArch::XVAVGR_B:
9149 case LoongArch::XVAVGR_BU:
9150 case LoongArch::XVAVGR_D:
9151 case LoongArch::XVAVGR_DU:
9152 case LoongArch::XVAVGR_H:
9153 case LoongArch::XVAVGR_HU:
9154 case LoongArch::XVAVGR_W:
9155 case LoongArch::XVAVGR_WU:
9156 case LoongArch::XVAVG_B:
9157 case LoongArch::XVAVG_BU:
9158 case LoongArch::XVAVG_D:
9159 case LoongArch::XVAVG_DU:
9160 case LoongArch::XVAVG_H:
9161 case LoongArch::XVAVG_HU:
9162 case LoongArch::XVAVG_W:
9163 case LoongArch::XVAVG_WU:
9164 case LoongArch::XVBITCLR_B:
9165 case LoongArch::XVBITCLR_D:
9166 case LoongArch::XVBITCLR_H:
9167 case LoongArch::XVBITCLR_W:
9168 case LoongArch::XVBITREV_B:
9169 case LoongArch::XVBITREV_D:
9170 case LoongArch::XVBITREV_H:
9171 case LoongArch::XVBITREV_W:
9172 case LoongArch::XVBITSET_B:
9173 case LoongArch::XVBITSET_D:
9174 case LoongArch::XVBITSET_H:
9175 case LoongArch::XVBITSET_W:
9176 case LoongArch::XVDIV_B:
9177 case LoongArch::XVDIV_BU:
9178 case LoongArch::XVDIV_D:
9179 case LoongArch::XVDIV_DU:
9180 case LoongArch::XVDIV_H:
9181 case LoongArch::XVDIV_HU:
9182 case LoongArch::XVDIV_W:
9183 case LoongArch::XVDIV_WU:
9184 case LoongArch::XVFADD_D:
9185 case LoongArch::XVFADD_S:
9186 case LoongArch::XVFCMP_CAF_D:
9187 case LoongArch::XVFCMP_CAF_S:
9188 case LoongArch::XVFCMP_CEQ_D:
9189 case LoongArch::XVFCMP_CEQ_S:
9190 case LoongArch::XVFCMP_CLE_D:
9191 case LoongArch::XVFCMP_CLE_S:
9192 case LoongArch::XVFCMP_CLT_D:
9193 case LoongArch::XVFCMP_CLT_S:
9194 case LoongArch::XVFCMP_CNE_D:
9195 case LoongArch::XVFCMP_CNE_S:
9196 case LoongArch::XVFCMP_COR_D:
9197 case LoongArch::XVFCMP_COR_S:
9198 case LoongArch::XVFCMP_CUEQ_D:
9199 case LoongArch::XVFCMP_CUEQ_S:
9200 case LoongArch::XVFCMP_CULE_D:
9201 case LoongArch::XVFCMP_CULE_S:
9202 case LoongArch::XVFCMP_CULT_D:
9203 case LoongArch::XVFCMP_CULT_S:
9204 case LoongArch::XVFCMP_CUNE_D:
9205 case LoongArch::XVFCMP_CUNE_S:
9206 case LoongArch::XVFCMP_CUN_D:
9207 case LoongArch::XVFCMP_CUN_S:
9208 case LoongArch::XVFCMP_SAF_D:
9209 case LoongArch::XVFCMP_SAF_S:
9210 case LoongArch::XVFCMP_SEQ_D:
9211 case LoongArch::XVFCMP_SEQ_S:
9212 case LoongArch::XVFCMP_SLE_D:
9213 case LoongArch::XVFCMP_SLE_S:
9214 case LoongArch::XVFCMP_SLT_D:
9215 case LoongArch::XVFCMP_SLT_S:
9216 case LoongArch::XVFCMP_SNE_D:
9217 case LoongArch::XVFCMP_SNE_S:
9218 case LoongArch::XVFCMP_SOR_D:
9219 case LoongArch::XVFCMP_SOR_S:
9220 case LoongArch::XVFCMP_SUEQ_D:
9221 case LoongArch::XVFCMP_SUEQ_S:
9222 case LoongArch::XVFCMP_SULE_D:
9223 case LoongArch::XVFCMP_SULE_S:
9224 case LoongArch::XVFCMP_SULT_D:
9225 case LoongArch::XVFCMP_SULT_S:
9226 case LoongArch::XVFCMP_SUNE_D:
9227 case LoongArch::XVFCMP_SUNE_S:
9228 case LoongArch::XVFCMP_SUN_D:
9229 case LoongArch::XVFCMP_SUN_S:
9230 case LoongArch::XVFCVT_H_S:
9231 case LoongArch::XVFCVT_S_D:
9232 case LoongArch::XVFDIV_D:
9233 case LoongArch::XVFDIV_S:
9234 case LoongArch::XVFFINT_S_L:
9235 case LoongArch::XVFMAXA_D:
9236 case LoongArch::XVFMAXA_S:
9237 case LoongArch::XVFMAX_D:
9238 case LoongArch::XVFMAX_S:
9239 case LoongArch::XVFMINA_D:
9240 case LoongArch::XVFMINA_S:
9241 case LoongArch::XVFMIN_D:
9242 case LoongArch::XVFMIN_S:
9243 case LoongArch::XVFMUL_D:
9244 case LoongArch::XVFMUL_S:
9245 case LoongArch::XVFSUB_D:
9246 case LoongArch::XVFSUB_S:
9247 case LoongArch::XVFTINTRM_W_D:
9248 case LoongArch::XVFTINTRNE_W_D:
9249 case LoongArch::XVFTINTRP_W_D:
9250 case LoongArch::XVFTINTRZ_W_D:
9251 case LoongArch::XVFTINT_W_D:
9252 case LoongArch::XVHADDW_DU_WU:
9253 case LoongArch::XVHADDW_D_W:
9254 case LoongArch::XVHADDW_HU_BU:
9255 case LoongArch::XVHADDW_H_B:
9256 case LoongArch::XVHADDW_QU_DU:
9257 case LoongArch::XVHADDW_Q_D:
9258 case LoongArch::XVHADDW_WU_HU:
9259 case LoongArch::XVHADDW_W_H:
9260 case LoongArch::XVHSUBW_DU_WU:
9261 case LoongArch::XVHSUBW_D_W:
9262 case LoongArch::XVHSUBW_HU_BU:
9263 case LoongArch::XVHSUBW_H_B:
9264 case LoongArch::XVHSUBW_QU_DU:
9265 case LoongArch::XVHSUBW_Q_D:
9266 case LoongArch::XVHSUBW_WU_HU:
9267 case LoongArch::XVHSUBW_W_H:
9268 case LoongArch::XVILVH_B:
9269 case LoongArch::XVILVH_D:
9270 case LoongArch::XVILVH_H:
9271 case LoongArch::XVILVH_W:
9272 case LoongArch::XVILVL_B:
9273 case LoongArch::XVILVL_D:
9274 case LoongArch::XVILVL_H:
9275 case LoongArch::XVILVL_W:
9276 case LoongArch::XVMAX_B:
9277 case LoongArch::XVMAX_BU:
9278 case LoongArch::XVMAX_D:
9279 case LoongArch::XVMAX_DU:
9280 case LoongArch::XVMAX_H:
9281 case LoongArch::XVMAX_HU:
9282 case LoongArch::XVMAX_W:
9283 case LoongArch::XVMAX_WU:
9284 case LoongArch::XVMIN_B:
9285 case LoongArch::XVMIN_BU:
9286 case LoongArch::XVMIN_D:
9287 case LoongArch::XVMIN_DU:
9288 case LoongArch::XVMIN_H:
9289 case LoongArch::XVMIN_HU:
9290 case LoongArch::XVMIN_W:
9291 case LoongArch::XVMIN_WU:
9292 case LoongArch::XVMOD_B:
9293 case LoongArch::XVMOD_BU:
9294 case LoongArch::XVMOD_D:
9295 case LoongArch::XVMOD_DU:
9296 case LoongArch::XVMOD_H:
9297 case LoongArch::XVMOD_HU:
9298 case LoongArch::XVMOD_W:
9299 case LoongArch::XVMOD_WU:
9300 case LoongArch::XVMUH_B:
9301 case LoongArch::XVMUH_BU:
9302 case LoongArch::XVMUH_D:
9303 case LoongArch::XVMUH_DU:
9304 case LoongArch::XVMUH_H:
9305 case LoongArch::XVMUH_HU:
9306 case LoongArch::XVMUH_W:
9307 case LoongArch::XVMUH_WU:
9308 case LoongArch::XVMULWEV_D_W:
9309 case LoongArch::XVMULWEV_D_WU:
9310 case LoongArch::XVMULWEV_D_WU_W:
9311 case LoongArch::XVMULWEV_H_B:
9312 case LoongArch::XVMULWEV_H_BU:
9313 case LoongArch::XVMULWEV_H_BU_B:
9314 case LoongArch::XVMULWEV_Q_D:
9315 case LoongArch::XVMULWEV_Q_DU:
9316 case LoongArch::XVMULWEV_Q_DU_D:
9317 case LoongArch::XVMULWEV_W_H:
9318 case LoongArch::XVMULWEV_W_HU:
9319 case LoongArch::XVMULWEV_W_HU_H:
9320 case LoongArch::XVMULWOD_D_W:
9321 case LoongArch::XVMULWOD_D_WU:
9322 case LoongArch::XVMULWOD_D_WU_W:
9323 case LoongArch::XVMULWOD_H_B:
9324 case LoongArch::XVMULWOD_H_BU:
9325 case LoongArch::XVMULWOD_H_BU_B:
9326 case LoongArch::XVMULWOD_Q_D:
9327 case LoongArch::XVMULWOD_Q_DU:
9328 case LoongArch::XVMULWOD_Q_DU_D:
9329 case LoongArch::XVMULWOD_W_H:
9330 case LoongArch::XVMULWOD_W_HU:
9331 case LoongArch::XVMULWOD_W_HU_H:
9332 case LoongArch::XVMUL_B:
9333 case LoongArch::XVMUL_D:
9334 case LoongArch::XVMUL_H:
9335 case LoongArch::XVMUL_W:
9336 case LoongArch::XVNOR_V:
9337 case LoongArch::XVORN_V:
9338 case LoongArch::XVOR_V:
9339 case LoongArch::XVPACKEV_B:
9340 case LoongArch::XVPACKEV_D:
9341 case LoongArch::XVPACKEV_H:
9342 case LoongArch::XVPACKEV_W:
9343 case LoongArch::XVPACKOD_B:
9344 case LoongArch::XVPACKOD_D:
9345 case LoongArch::XVPACKOD_H:
9346 case LoongArch::XVPACKOD_W:
9347 case LoongArch::XVPERM_W:
9348 case LoongArch::XVPICKEV_B:
9349 case LoongArch::XVPICKEV_D:
9350 case LoongArch::XVPICKEV_H:
9351 case LoongArch::XVPICKEV_W:
9352 case LoongArch::XVPICKOD_B:
9353 case LoongArch::XVPICKOD_D:
9354 case LoongArch::XVPICKOD_H:
9355 case LoongArch::XVPICKOD_W:
9356 case LoongArch::XVROTR_B:
9357 case LoongArch::XVROTR_D:
9358 case LoongArch::XVROTR_H:
9359 case LoongArch::XVROTR_W:
9360 case LoongArch::XVSADD_B:
9361 case LoongArch::XVSADD_BU:
9362 case LoongArch::XVSADD_D:
9363 case LoongArch::XVSADD_DU:
9364 case LoongArch::XVSADD_H:
9365 case LoongArch::XVSADD_HU:
9366 case LoongArch::XVSADD_W:
9367 case LoongArch::XVSADD_WU:
9368 case LoongArch::XVSEQ_B:
9369 case LoongArch::XVSEQ_D:
9370 case LoongArch::XVSEQ_H:
9371 case LoongArch::XVSEQ_W:
9372 case LoongArch::XVSIGNCOV_B:
9373 case LoongArch::XVSIGNCOV_D:
9374 case LoongArch::XVSIGNCOV_H:
9375 case LoongArch::XVSIGNCOV_W:
9376 case LoongArch::XVSLE_B:
9377 case LoongArch::XVSLE_BU:
9378 case LoongArch::XVSLE_D:
9379 case LoongArch::XVSLE_DU:
9380 case LoongArch::XVSLE_H:
9381 case LoongArch::XVSLE_HU:
9382 case LoongArch::XVSLE_W:
9383 case LoongArch::XVSLE_WU:
9384 case LoongArch::XVSLL_B:
9385 case LoongArch::XVSLL_D:
9386 case LoongArch::XVSLL_H:
9387 case LoongArch::XVSLL_W:
9388 case LoongArch::XVSLT_B:
9389 case LoongArch::XVSLT_BU:
9390 case LoongArch::XVSLT_D:
9391 case LoongArch::XVSLT_DU:
9392 case LoongArch::XVSLT_H:
9393 case LoongArch::XVSLT_HU:
9394 case LoongArch::XVSLT_W:
9395 case LoongArch::XVSLT_WU:
9396 case LoongArch::XVSRAN_B_H:
9397 case LoongArch::XVSRAN_H_W:
9398 case LoongArch::XVSRAN_W_D:
9399 case LoongArch::XVSRARN_B_H:
9400 case LoongArch::XVSRARN_H_W:
9401 case LoongArch::XVSRARN_W_D:
9402 case LoongArch::XVSRAR_B:
9403 case LoongArch::XVSRAR_D:
9404 case LoongArch::XVSRAR_H:
9405 case LoongArch::XVSRAR_W:
9406 case LoongArch::XVSRA_B:
9407 case LoongArch::XVSRA_D:
9408 case LoongArch::XVSRA_H:
9409 case LoongArch::XVSRA_W:
9410 case LoongArch::XVSRLN_B_H:
9411 case LoongArch::XVSRLN_H_W:
9412 case LoongArch::XVSRLN_W_D:
9413 case LoongArch::XVSRLRN_B_H:
9414 case LoongArch::XVSRLRN_H_W:
9415 case LoongArch::XVSRLRN_W_D:
9416 case LoongArch::XVSRLR_B:
9417 case LoongArch::XVSRLR_D:
9418 case LoongArch::XVSRLR_H:
9419 case LoongArch::XVSRLR_W:
9420 case LoongArch::XVSRL_B:
9421 case LoongArch::XVSRL_D:
9422 case LoongArch::XVSRL_H:
9423 case LoongArch::XVSRL_W:
9424 case LoongArch::XVSSRAN_BU_H:
9425 case LoongArch::XVSSRAN_B_H:
9426 case LoongArch::XVSSRAN_HU_W:
9427 case LoongArch::XVSSRAN_H_W:
9428 case LoongArch::XVSSRAN_WU_D:
9429 case LoongArch::XVSSRAN_W_D:
9430 case LoongArch::XVSSRARN_BU_H:
9431 case LoongArch::XVSSRARN_B_H:
9432 case LoongArch::XVSSRARN_HU_W:
9433 case LoongArch::XVSSRARN_H_W:
9434 case LoongArch::XVSSRARN_WU_D:
9435 case LoongArch::XVSSRARN_W_D:
9436 case LoongArch::XVSSRLN_BU_H:
9437 case LoongArch::XVSSRLN_B_H:
9438 case LoongArch::XVSSRLN_HU_W:
9439 case LoongArch::XVSSRLN_H_W:
9440 case LoongArch::XVSSRLN_WU_D:
9441 case LoongArch::XVSSRLN_W_D:
9442 case LoongArch::XVSSRLRN_BU_H:
9443 case LoongArch::XVSSRLRN_B_H:
9444 case LoongArch::XVSSRLRN_HU_W:
9445 case LoongArch::XVSSRLRN_H_W:
9446 case LoongArch::XVSSRLRN_WU_D:
9447 case LoongArch::XVSSRLRN_W_D:
9448 case LoongArch::XVSSUB_B:
9449 case LoongArch::XVSSUB_BU:
9450 case LoongArch::XVSSUB_D:
9451 case LoongArch::XVSSUB_DU:
9452 case LoongArch::XVSSUB_H:
9453 case LoongArch::XVSSUB_HU:
9454 case LoongArch::XVSSUB_W:
9455 case LoongArch::XVSSUB_WU:
9456 case LoongArch::XVSUBWEV_D_W:
9457 case LoongArch::XVSUBWEV_D_WU:
9458 case LoongArch::XVSUBWEV_H_B:
9459 case LoongArch::XVSUBWEV_H_BU:
9460 case LoongArch::XVSUBWEV_Q_D:
9461 case LoongArch::XVSUBWEV_Q_DU:
9462 case LoongArch::XVSUBWEV_W_H:
9463 case LoongArch::XVSUBWEV_W_HU:
9464 case LoongArch::XVSUBWOD_D_W:
9465 case LoongArch::XVSUBWOD_D_WU:
9466 case LoongArch::XVSUBWOD_H_B:
9467 case LoongArch::XVSUBWOD_H_BU:
9468 case LoongArch::XVSUBWOD_Q_D:
9469 case LoongArch::XVSUBWOD_Q_DU:
9470 case LoongArch::XVSUBWOD_W_H:
9471 case LoongArch::XVSUBWOD_W_HU:
9472 case LoongArch::XVSUB_B:
9473 case LoongArch::XVSUB_D:
9474 case LoongArch::XVSUB_H:
9475 case LoongArch::XVSUB_Q:
9476 case LoongArch::XVSUB_W:
9477 case LoongArch::XVXOR_V: {
9478 switch (OpNum) {
9479 case 2:
9480 // op: xk
9481 return 10;
9482 case 1:
9483 // op: xj
9484 return 5;
9485 case 0:
9486 // op: xd
9487 return 0;
9488 }
9489 break;
9490 }
9491 case LoongArch::FSEL_xD:
9492 case LoongArch::FSEL_xS: {
9493 switch (OpNum) {
9494 case 3:
9495 // op: ca
9496 return 15;
9497 case 2:
9498 // op: fk
9499 return 10;
9500 case 1:
9501 // op: fj
9502 return 5;
9503 case 0:
9504 // op: fd
9505 return 0;
9506 }
9507 break;
9508 }
9509 case LoongArch::CSRXCHG:
9510 case LoongArch::GCSRXCHG: {
9511 switch (OpNum) {
9512 case 3:
9513 // op: csr_num
9514 return 10;
9515 case 2:
9516 // op: rj
9517 return 5;
9518 case 1:
9519 // op: rd
9520 return 0;
9521 }
9522 break;
9523 }
9524 case LoongArch::FMADD_D:
9525 case LoongArch::FMADD_S:
9526 case LoongArch::FMSUB_D:
9527 case LoongArch::FMSUB_S:
9528 case LoongArch::FNMADD_D:
9529 case LoongArch::FNMADD_S:
9530 case LoongArch::FNMSUB_D:
9531 case LoongArch::FNMSUB_S: {
9532 switch (OpNum) {
9533 case 3:
9534 // op: fa
9535 return 15;
9536 case 2:
9537 // op: fk
9538 return 10;
9539 case 1:
9540 // op: fj
9541 return 5;
9542 case 0:
9543 // op: fd
9544 return 0;
9545 }
9546 break;
9547 }
9548 case LoongArch::VINSGR2VR_D: {
9549 switch (OpNum) {
9550 case 3:
9551 // op: imm1
9552 return 10;
9553 case 2:
9554 // op: rj
9555 return 5;
9556 case 1:
9557 // op: vd
9558 return 0;
9559 }
9560 break;
9561 }
9562 case LoongArch::VSTELM_D: {
9563 switch (OpNum) {
9564 case 3:
9565 // op: imm1
9566 return 18;
9567 case 2:
9568 // op: imm8
9569 return 10;
9570 case 1:
9571 // op: rj
9572 return 5;
9573 case 0:
9574 // op: vd
9575 return 0;
9576 }
9577 break;
9578 }
9579 case LoongArch::SC_D:
9580 case LoongArch::SC_W: {
9581 switch (OpNum) {
9582 case 3:
9583 // op: imm14
9584 return 10;
9585 case 2:
9586 // op: rj
9587 return 5;
9588 case 1:
9589 // op: rd
9590 return 0;
9591 }
9592 break;
9593 }
9594 case LoongArch::VINSGR2VR_W: {
9595 switch (OpNum) {
9596 case 3:
9597 // op: imm2
9598 return 10;
9599 case 2:
9600 // op: rj
9601 return 5;
9602 case 1:
9603 // op: vd
9604 return 0;
9605 }
9606 break;
9607 }
9608 case LoongArch::XVINSGR2VR_D: {
9609 switch (OpNum) {
9610 case 3:
9611 // op: imm2
9612 return 10;
9613 case 2:
9614 // op: rj
9615 return 5;
9616 case 1:
9617 // op: xd
9618 return 0;
9619 }
9620 break;
9621 }
9622 case LoongArch::XVINSVE0_D: {
9623 switch (OpNum) {
9624 case 3:
9625 // op: imm2
9626 return 10;
9627 case 2:
9628 // op: xj
9629 return 5;
9630 case 1:
9631 // op: xd
9632 return 0;
9633 }
9634 break;
9635 }
9636 case LoongArch::ALSL_D:
9637 case LoongArch::ALSL_W:
9638 case LoongArch::ALSL_WU:
9639 case LoongArch::BYTEPICK_W: {
9640 switch (OpNum) {
9641 case 3:
9642 // op: imm2
9643 return 15;
9644 case 2:
9645 // op: rk
9646 return 10;
9647 case 1:
9648 // op: rj
9649 return 5;
9650 case 0:
9651 // op: rd
9652 return 0;
9653 }
9654 break;
9655 }
9656 case LoongArch::VSTELM_W: {
9657 switch (OpNum) {
9658 case 3:
9659 // op: imm2
9660 return 18;
9661 case 2:
9662 // op: imm8
9663 return 10;
9664 case 1:
9665 // op: rj
9666 return 5;
9667 case 0:
9668 // op: vd
9669 return 0;
9670 }
9671 break;
9672 }
9673 case LoongArch::XVSTELM_D: {
9674 switch (OpNum) {
9675 case 3:
9676 // op: imm2
9677 return 18;
9678 case 2:
9679 // op: imm8
9680 return 10;
9681 case 1:
9682 // op: rj
9683 return 5;
9684 case 0:
9685 // op: xd
9686 return 0;
9687 }
9688 break;
9689 }
9690 case LoongArch::VINSGR2VR_H: {
9691 switch (OpNum) {
9692 case 3:
9693 // op: imm3
9694 return 10;
9695 case 2:
9696 // op: rj
9697 return 5;
9698 case 1:
9699 // op: vd
9700 return 0;
9701 }
9702 break;
9703 }
9704 case LoongArch::XVINSGR2VR_W: {
9705 switch (OpNum) {
9706 case 3:
9707 // op: imm3
9708 return 10;
9709 case 2:
9710 // op: rj
9711 return 5;
9712 case 1:
9713 // op: xd
9714 return 0;
9715 }
9716 break;
9717 }
9718 case LoongArch::XVINSVE0_W: {
9719 switch (OpNum) {
9720 case 3:
9721 // op: imm3
9722 return 10;
9723 case 2:
9724 // op: xj
9725 return 5;
9726 case 1:
9727 // op: xd
9728 return 0;
9729 }
9730 break;
9731 }
9732 case LoongArch::BYTEPICK_D: {
9733 switch (OpNum) {
9734 case 3:
9735 // op: imm3
9736 return 15;
9737 case 2:
9738 // op: rk
9739 return 10;
9740 case 1:
9741 // op: rj
9742 return 5;
9743 case 0:
9744 // op: rd
9745 return 0;
9746 }
9747 break;
9748 }
9749 case LoongArch::VSTELM_H: {
9750 switch (OpNum) {
9751 case 3:
9752 // op: imm3
9753 return 18;
9754 case 2:
9755 // op: imm8
9756 return 10;
9757 case 1:
9758 // op: rj
9759 return 5;
9760 case 0:
9761 // op: vd
9762 return 0;
9763 }
9764 break;
9765 }
9766 case LoongArch::XVSTELM_W: {
9767 switch (OpNum) {
9768 case 3:
9769 // op: imm3
9770 return 18;
9771 case 2:
9772 // op: imm8
9773 return 10;
9774 case 1:
9775 // op: rj
9776 return 5;
9777 case 0:
9778 // op: xd
9779 return 0;
9780 }
9781 break;
9782 }
9783 case LoongArch::VINSGR2VR_B: {
9784 switch (OpNum) {
9785 case 3:
9786 // op: imm4
9787 return 10;
9788 case 2:
9789 // op: rj
9790 return 5;
9791 case 1:
9792 // op: vd
9793 return 0;
9794 }
9795 break;
9796 }
9797 case LoongArch::VSRANI_B_H:
9798 case LoongArch::VSRARNI_B_H:
9799 case LoongArch::VSRLNI_B_H:
9800 case LoongArch::VSRLRNI_B_H:
9801 case LoongArch::VSSRANI_BU_H:
9802 case LoongArch::VSSRANI_B_H:
9803 case LoongArch::VSSRARNI_BU_H:
9804 case LoongArch::VSSRARNI_B_H:
9805 case LoongArch::VSSRLNI_BU_H:
9806 case LoongArch::VSSRLNI_B_H:
9807 case LoongArch::VSSRLRNI_BU_H:
9808 case LoongArch::VSSRLRNI_B_H: {
9809 switch (OpNum) {
9810 case 3:
9811 // op: imm4
9812 return 10;
9813 case 2:
9814 // op: vj
9815 return 5;
9816 case 1:
9817 // op: vd
9818 return 0;
9819 }
9820 break;
9821 }
9822 case LoongArch::XVSRANI_B_H:
9823 case LoongArch::XVSRARNI_B_H:
9824 case LoongArch::XVSRLNI_B_H:
9825 case LoongArch::XVSRLRNI_B_H:
9826 case LoongArch::XVSSRANI_BU_H:
9827 case LoongArch::XVSSRANI_B_H:
9828 case LoongArch::XVSSRARNI_BU_H:
9829 case LoongArch::XVSSRARNI_B_H:
9830 case LoongArch::XVSSRLNI_BU_H:
9831 case LoongArch::XVSSRLNI_B_H:
9832 case LoongArch::XVSSRLRNI_BU_H:
9833 case LoongArch::XVSSRLRNI_B_H: {
9834 switch (OpNum) {
9835 case 3:
9836 // op: imm4
9837 return 10;
9838 case 2:
9839 // op: xj
9840 return 5;
9841 case 1:
9842 // op: xd
9843 return 0;
9844 }
9845 break;
9846 }
9847 case LoongArch::VSTELM_B: {
9848 switch (OpNum) {
9849 case 3:
9850 // op: imm4
9851 return 18;
9852 case 2:
9853 // op: imm8
9854 return 10;
9855 case 1:
9856 // op: rj
9857 return 5;
9858 case 0:
9859 // op: vd
9860 return 0;
9861 }
9862 break;
9863 }
9864 case LoongArch::XVSTELM_H: {
9865 switch (OpNum) {
9866 case 3:
9867 // op: imm4
9868 return 18;
9869 case 2:
9870 // op: imm8
9871 return 10;
9872 case 1:
9873 // op: rj
9874 return 5;
9875 case 0:
9876 // op: xd
9877 return 0;
9878 }
9879 break;
9880 }
9881 case LoongArch::VFRSTPI_B:
9882 case LoongArch::VFRSTPI_H:
9883 case LoongArch::VSRANI_H_W:
9884 case LoongArch::VSRARNI_H_W:
9885 case LoongArch::VSRLNI_H_W:
9886 case LoongArch::VSRLRNI_H_W:
9887 case LoongArch::VSSRANI_HU_W:
9888 case LoongArch::VSSRANI_H_W:
9889 case LoongArch::VSSRARNI_HU_W:
9890 case LoongArch::VSSRARNI_H_W:
9891 case LoongArch::VSSRLNI_HU_W:
9892 case LoongArch::VSSRLNI_H_W:
9893 case LoongArch::VSSRLRNI_HU_W:
9894 case LoongArch::VSSRLRNI_H_W: {
9895 switch (OpNum) {
9896 case 3:
9897 // op: imm5
9898 return 10;
9899 case 2:
9900 // op: vj
9901 return 5;
9902 case 1:
9903 // op: vd
9904 return 0;
9905 }
9906 break;
9907 }
9908 case LoongArch::XVFRSTPI_B:
9909 case LoongArch::XVFRSTPI_H:
9910 case LoongArch::XVSRANI_H_W:
9911 case LoongArch::XVSRARNI_H_W:
9912 case LoongArch::XVSRLNI_H_W:
9913 case LoongArch::XVSRLRNI_H_W:
9914 case LoongArch::XVSSRANI_HU_W:
9915 case LoongArch::XVSSRANI_H_W:
9916 case LoongArch::XVSSRARNI_HU_W:
9917 case LoongArch::XVSSRARNI_H_W:
9918 case LoongArch::XVSSRLNI_HU_W:
9919 case LoongArch::XVSSRLNI_H_W:
9920 case LoongArch::XVSSRLRNI_HU_W:
9921 case LoongArch::XVSSRLRNI_H_W: {
9922 switch (OpNum) {
9923 case 3:
9924 // op: imm5
9925 return 10;
9926 case 2:
9927 // op: xj
9928 return 5;
9929 case 1:
9930 // op: xd
9931 return 0;
9932 }
9933 break;
9934 }
9935 case LoongArch::XVSTELM_B: {
9936 switch (OpNum) {
9937 case 3:
9938 // op: imm5
9939 return 18;
9940 case 2:
9941 // op: imm8
9942 return 10;
9943 case 1:
9944 // op: rj
9945 return 5;
9946 case 0:
9947 // op: xd
9948 return 0;
9949 }
9950 break;
9951 }
9952 case LoongArch::VSRANI_W_D:
9953 case LoongArch::VSRARNI_W_D:
9954 case LoongArch::VSRLNI_W_D:
9955 case LoongArch::VSRLRNI_W_D:
9956 case LoongArch::VSSRANI_WU_D:
9957 case LoongArch::VSSRANI_W_D:
9958 case LoongArch::VSSRARNI_WU_D:
9959 case LoongArch::VSSRARNI_W_D:
9960 case LoongArch::VSSRLNI_WU_D:
9961 case LoongArch::VSSRLNI_W_D:
9962 case LoongArch::VSSRLRNI_WU_D:
9963 case LoongArch::VSSRLRNI_W_D: {
9964 switch (OpNum) {
9965 case 3:
9966 // op: imm6
9967 return 10;
9968 case 2:
9969 // op: vj
9970 return 5;
9971 case 1:
9972 // op: vd
9973 return 0;
9974 }
9975 break;
9976 }
9977 case LoongArch::XVSRANI_W_D:
9978 case LoongArch::XVSRARNI_W_D:
9979 case LoongArch::XVSRLNI_W_D:
9980 case LoongArch::XVSRLRNI_W_D:
9981 case LoongArch::XVSSRANI_WU_D:
9982 case LoongArch::XVSSRANI_W_D:
9983 case LoongArch::XVSSRARNI_WU_D:
9984 case LoongArch::XVSSRARNI_W_D:
9985 case LoongArch::XVSSRLNI_WU_D:
9986 case LoongArch::XVSSRLNI_W_D:
9987 case LoongArch::XVSSRLRNI_WU_D:
9988 case LoongArch::XVSSRLRNI_W_D: {
9989 switch (OpNum) {
9990 case 3:
9991 // op: imm6
9992 return 10;
9993 case 2:
9994 // op: xj
9995 return 5;
9996 case 1:
9997 // op: xd
9998 return 0;
9999 }
10000 break;
10001 }
10002 case LoongArch::VSRANI_D_Q:
10003 case LoongArch::VSRARNI_D_Q:
10004 case LoongArch::VSRLNI_D_Q:
10005 case LoongArch::VSRLRNI_D_Q:
10006 case LoongArch::VSSRANI_DU_Q:
10007 case LoongArch::VSSRANI_D_Q:
10008 case LoongArch::VSSRARNI_DU_Q:
10009 case LoongArch::VSSRARNI_D_Q:
10010 case LoongArch::VSSRLNI_DU_Q:
10011 case LoongArch::VSSRLNI_D_Q:
10012 case LoongArch::VSSRLRNI_DU_Q:
10013 case LoongArch::VSSRLRNI_D_Q: {
10014 switch (OpNum) {
10015 case 3:
10016 // op: imm7
10017 return 10;
10018 case 2:
10019 // op: vj
10020 return 5;
10021 case 1:
10022 // op: vd
10023 return 0;
10024 }
10025 break;
10026 }
10027 case LoongArch::XVSRANI_D_Q:
10028 case LoongArch::XVSRARNI_D_Q:
10029 case LoongArch::XVSRLNI_D_Q:
10030 case LoongArch::XVSRLRNI_D_Q:
10031 case LoongArch::XVSSRANI_DU_Q:
10032 case LoongArch::XVSSRANI_D_Q:
10033 case LoongArch::XVSSRARNI_DU_Q:
10034 case LoongArch::XVSSRARNI_D_Q:
10035 case LoongArch::XVSSRLNI_DU_Q:
10036 case LoongArch::XVSSRLNI_D_Q:
10037 case LoongArch::XVSSRLRNI_DU_Q:
10038 case LoongArch::XVSSRLRNI_D_Q: {
10039 switch (OpNum) {
10040 case 3:
10041 // op: imm7
10042 return 10;
10043 case 2:
10044 // op: xj
10045 return 5;
10046 case 1:
10047 // op: xd
10048 return 0;
10049 }
10050 break;
10051 }
10052 case LoongArch::VBITSELI_B:
10053 case LoongArch::VEXTRINS_B:
10054 case LoongArch::VEXTRINS_D:
10055 case LoongArch::VEXTRINS_H:
10056 case LoongArch::VEXTRINS_W:
10057 case LoongArch::VPERMI_W:
10058 case LoongArch::VSHUF4I_D: {
10059 switch (OpNum) {
10060 case 3:
10061 // op: imm8
10062 return 10;
10063 case 2:
10064 // op: vj
10065 return 5;
10066 case 1:
10067 // op: vd
10068 return 0;
10069 }
10070 break;
10071 }
10072 case LoongArch::XVBITSELI_B:
10073 case LoongArch::XVEXTRINS_B:
10074 case LoongArch::XVEXTRINS_D:
10075 case LoongArch::XVEXTRINS_H:
10076 case LoongArch::XVEXTRINS_W:
10077 case LoongArch::XVPERMI_Q:
10078 case LoongArch::XVPERMI_W:
10079 case LoongArch::XVSHUF4I_D: {
10080 switch (OpNum) {
10081 case 3:
10082 // op: imm8
10083 return 10;
10084 case 2:
10085 // op: xj
10086 return 5;
10087 case 1:
10088 // op: xd
10089 return 0;
10090 }
10091 break;
10092 }
10093 case LoongArch::BSTRINS_D: {
10094 switch (OpNum) {
10095 case 3:
10096 // op: msbd
10097 return 16;
10098 case 4:
10099 // op: lsbd
10100 return 10;
10101 case 2:
10102 // op: rj
10103 return 5;
10104 case 1:
10105 // op: rd
10106 return 0;
10107 }
10108 break;
10109 }
10110 case LoongArch::BSTRINS_W: {
10111 switch (OpNum) {
10112 case 3:
10113 // op: msbw
10114 return 16;
10115 case 4:
10116 // op: lsbw
10117 return 10;
10118 case 2:
10119 // op: rj
10120 return 5;
10121 case 1:
10122 // op: rd
10123 return 0;
10124 }
10125 break;
10126 }
10127 case LoongArch::VBITSEL_V:
10128 case LoongArch::VFMADD_D:
10129 case LoongArch::VFMADD_S:
10130 case LoongArch::VFMSUB_D:
10131 case LoongArch::VFMSUB_S:
10132 case LoongArch::VFNMADD_D:
10133 case LoongArch::VFNMADD_S:
10134 case LoongArch::VFNMSUB_D:
10135 case LoongArch::VFNMSUB_S:
10136 case LoongArch::VSHUF_B: {
10137 switch (OpNum) {
10138 case 3:
10139 // op: va
10140 return 15;
10141 case 2:
10142 // op: vk
10143 return 10;
10144 case 1:
10145 // op: vj
10146 return 5;
10147 case 0:
10148 // op: vd
10149 return 0;
10150 }
10151 break;
10152 }
10153 case LoongArch::VFRSTP_B:
10154 case LoongArch::VFRSTP_H:
10155 case LoongArch::VMADDWEV_D_W:
10156 case LoongArch::VMADDWEV_D_WU:
10157 case LoongArch::VMADDWEV_D_WU_W:
10158 case LoongArch::VMADDWEV_H_B:
10159 case LoongArch::VMADDWEV_H_BU:
10160 case LoongArch::VMADDWEV_H_BU_B:
10161 case LoongArch::VMADDWEV_Q_D:
10162 case LoongArch::VMADDWEV_Q_DU:
10163 case LoongArch::VMADDWEV_Q_DU_D:
10164 case LoongArch::VMADDWEV_W_H:
10165 case LoongArch::VMADDWEV_W_HU:
10166 case LoongArch::VMADDWEV_W_HU_H:
10167 case LoongArch::VMADDWOD_D_W:
10168 case LoongArch::VMADDWOD_D_WU:
10169 case LoongArch::VMADDWOD_D_WU_W:
10170 case LoongArch::VMADDWOD_H_B:
10171 case LoongArch::VMADDWOD_H_BU:
10172 case LoongArch::VMADDWOD_H_BU_B:
10173 case LoongArch::VMADDWOD_Q_D:
10174 case LoongArch::VMADDWOD_Q_DU:
10175 case LoongArch::VMADDWOD_Q_DU_D:
10176 case LoongArch::VMADDWOD_W_H:
10177 case LoongArch::VMADDWOD_W_HU:
10178 case LoongArch::VMADDWOD_W_HU_H:
10179 case LoongArch::VMADD_B:
10180 case LoongArch::VMADD_D:
10181 case LoongArch::VMADD_H:
10182 case LoongArch::VMADD_W:
10183 case LoongArch::VMSUB_B:
10184 case LoongArch::VMSUB_D:
10185 case LoongArch::VMSUB_H:
10186 case LoongArch::VMSUB_W:
10187 case LoongArch::VSHUF_D:
10188 case LoongArch::VSHUF_H:
10189 case LoongArch::VSHUF_W: {
10190 switch (OpNum) {
10191 case 3:
10192 // op: vk
10193 return 10;
10194 case 2:
10195 // op: vj
10196 return 5;
10197 case 1:
10198 // op: vd
10199 return 0;
10200 }
10201 break;
10202 }
10203 case LoongArch::XVBITSEL_V:
10204 case LoongArch::XVFMADD_D:
10205 case LoongArch::XVFMADD_S:
10206 case LoongArch::XVFMSUB_D:
10207 case LoongArch::XVFMSUB_S:
10208 case LoongArch::XVFNMADD_D:
10209 case LoongArch::XVFNMADD_S:
10210 case LoongArch::XVFNMSUB_D:
10211 case LoongArch::XVFNMSUB_S:
10212 case LoongArch::XVSHUF_B: {
10213 switch (OpNum) {
10214 case 3:
10215 // op: xa
10216 return 15;
10217 case 2:
10218 // op: xk
10219 return 10;
10220 case 1:
10221 // op: xj
10222 return 5;
10223 case 0:
10224 // op: xd
10225 return 0;
10226 }
10227 break;
10228 }
10229 case LoongArch::XVFRSTP_B:
10230 case LoongArch::XVFRSTP_H:
10231 case LoongArch::XVMADDWEV_D_W:
10232 case LoongArch::XVMADDWEV_D_WU:
10233 case LoongArch::XVMADDWEV_D_WU_W:
10234 case LoongArch::XVMADDWEV_H_B:
10235 case LoongArch::XVMADDWEV_H_BU:
10236 case LoongArch::XVMADDWEV_H_BU_B:
10237 case LoongArch::XVMADDWEV_Q_D:
10238 case LoongArch::XVMADDWEV_Q_DU:
10239 case LoongArch::XVMADDWEV_Q_DU_D:
10240 case LoongArch::XVMADDWEV_W_H:
10241 case LoongArch::XVMADDWEV_W_HU:
10242 case LoongArch::XVMADDWEV_W_HU_H:
10243 case LoongArch::XVMADDWOD_D_W:
10244 case LoongArch::XVMADDWOD_D_WU:
10245 case LoongArch::XVMADDWOD_D_WU_W:
10246 case LoongArch::XVMADDWOD_H_B:
10247 case LoongArch::XVMADDWOD_H_BU:
10248 case LoongArch::XVMADDWOD_H_BU_B:
10249 case LoongArch::XVMADDWOD_Q_D:
10250 case LoongArch::XVMADDWOD_Q_DU:
10251 case LoongArch::XVMADDWOD_Q_DU_D:
10252 case LoongArch::XVMADDWOD_W_H:
10253 case LoongArch::XVMADDWOD_W_HU:
10254 case LoongArch::XVMADDWOD_W_HU_H:
10255 case LoongArch::XVMADD_B:
10256 case LoongArch::XVMADD_D:
10257 case LoongArch::XVMADD_H:
10258 case LoongArch::XVMADD_W:
10259 case LoongArch::XVMSUB_B:
10260 case LoongArch::XVMSUB_D:
10261 case LoongArch::XVMSUB_H:
10262 case LoongArch::XVMSUB_W:
10263 case LoongArch::XVSHUF_D:
10264 case LoongArch::XVSHUF_H:
10265 case LoongArch::XVSHUF_W: {
10266 switch (OpNum) {
10267 case 3:
10268 // op: xk
10269 return 10;
10270 case 2:
10271 // op: xj
10272 return 5;
10273 case 1:
10274 // op: xd
10275 return 0;
10276 }
10277 break;
10278 }
10279 }
10280 std::string msg;
10281 raw_string_ostream Msg(msg);
10282 Msg << "Not supported instr[opcode]: " << MI << "[" << OpNum << "]";
10283 report_fatal_error(Msg.str().c_str());
10284}
10285
10286#endif // GET_OPERAND_BIT_OFFSET
10287
10288