1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11namespace llvm::Mips {
12 enum {
13 PHI = 0,
14 INLINEASM = 1,
15 INLINEASM_BR = 2,
16 CFI_INSTRUCTION = 3,
17 EH_LABEL = 4,
18 GC_LABEL = 5,
19 ANNOTATION_LABEL = 6,
20 KILL = 7,
21 EXTRACT_SUBREG = 8,
22 INSERT_SUBREG = 9,
23 IMPLICIT_DEF = 10,
24 INIT_UNDEF = 11,
25 SUBREG_TO_REG = 12,
26 COPY_TO_REGCLASS = 13,
27 DBG_VALUE = 14,
28 DBG_VALUE_LIST = 15,
29 DBG_INSTR_REF = 16,
30 DBG_PHI = 17,
31 DBG_LABEL = 18,
32 REG_SEQUENCE = 19,
33 COPY = 20,
34 BUNDLE = 21,
35 LIFETIME_START = 22,
36 LIFETIME_END = 23,
37 PSEUDO_PROBE = 24,
38 ARITH_FENCE = 25,
39 STACKMAP = 26,
40 FENTRY_CALL = 27,
41 PATCHPOINT = 28,
42 LOAD_STACK_GUARD = 29,
43 PREALLOCATED_SETUP = 30,
44 PREALLOCATED_ARG = 31,
45 STATEPOINT = 32,
46 LOCAL_ESCAPE = 33,
47 FAULTING_OP = 34,
48 PATCHABLE_OP = 35,
49 PATCHABLE_FUNCTION_ENTER = 36,
50 PATCHABLE_RET = 37,
51 PATCHABLE_FUNCTION_EXIT = 38,
52 PATCHABLE_TAIL_CALL = 39,
53 PATCHABLE_EVENT_CALL = 40,
54 PATCHABLE_TYPED_EVENT_CALL = 41,
55 ICALL_BRANCH_FUNNEL = 42,
56 FAKE_USE = 43,
57 MEMBARRIER = 44,
58 JUMP_TABLE_DEBUG_INFO = 45,
59 CONVERGENCECTRL_ENTRY = 46,
60 CONVERGENCECTRL_ANCHOR = 47,
61 CONVERGENCECTRL_LOOP = 48,
62 CONVERGENCECTRL_GLUE = 49,
63 G_ASSERT_SEXT = 50,
64 G_ASSERT_ZEXT = 51,
65 G_ASSERT_ALIGN = 52,
66 G_ADD = 53,
67 G_SUB = 54,
68 G_MUL = 55,
69 G_SDIV = 56,
70 G_UDIV = 57,
71 G_SREM = 58,
72 G_UREM = 59,
73 G_SDIVREM = 60,
74 G_UDIVREM = 61,
75 G_AND = 62,
76 G_OR = 63,
77 G_XOR = 64,
78 G_ABDS = 65,
79 G_ABDU = 66,
80 G_IMPLICIT_DEF = 67,
81 G_PHI = 68,
82 G_FRAME_INDEX = 69,
83 G_GLOBAL_VALUE = 70,
84 G_PTRAUTH_GLOBAL_VALUE = 71,
85 G_CONSTANT_POOL = 72,
86 G_EXTRACT = 73,
87 G_UNMERGE_VALUES = 74,
88 G_INSERT = 75,
89 G_MERGE_VALUES = 76,
90 G_BUILD_VECTOR = 77,
91 G_BUILD_VECTOR_TRUNC = 78,
92 G_CONCAT_VECTORS = 79,
93 G_PTRTOINT = 80,
94 G_INTTOPTR = 81,
95 G_BITCAST = 82,
96 G_FREEZE = 83,
97 G_CONSTANT_FOLD_BARRIER = 84,
98 G_INTRINSIC_FPTRUNC_ROUND = 85,
99 G_INTRINSIC_TRUNC = 86,
100 G_INTRINSIC_ROUND = 87,
101 G_INTRINSIC_LRINT = 88,
102 G_INTRINSIC_LLRINT = 89,
103 G_INTRINSIC_ROUNDEVEN = 90,
104 G_READCYCLECOUNTER = 91,
105 G_READSTEADYCOUNTER = 92,
106 G_LOAD = 93,
107 G_SEXTLOAD = 94,
108 G_ZEXTLOAD = 95,
109 G_INDEXED_LOAD = 96,
110 G_INDEXED_SEXTLOAD = 97,
111 G_INDEXED_ZEXTLOAD = 98,
112 G_STORE = 99,
113 G_INDEXED_STORE = 100,
114 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 101,
115 G_ATOMIC_CMPXCHG = 102,
116 G_ATOMICRMW_XCHG = 103,
117 G_ATOMICRMW_ADD = 104,
118 G_ATOMICRMW_SUB = 105,
119 G_ATOMICRMW_AND = 106,
120 G_ATOMICRMW_NAND = 107,
121 G_ATOMICRMW_OR = 108,
122 G_ATOMICRMW_XOR = 109,
123 G_ATOMICRMW_MAX = 110,
124 G_ATOMICRMW_MIN = 111,
125 G_ATOMICRMW_UMAX = 112,
126 G_ATOMICRMW_UMIN = 113,
127 G_ATOMICRMW_FADD = 114,
128 G_ATOMICRMW_FSUB = 115,
129 G_ATOMICRMW_FMAX = 116,
130 G_ATOMICRMW_FMIN = 117,
131 G_ATOMICRMW_FMAXIMUM = 118,
132 G_ATOMICRMW_FMINIMUM = 119,
133 G_ATOMICRMW_UINC_WRAP = 120,
134 G_ATOMICRMW_UDEC_WRAP = 121,
135 G_ATOMICRMW_USUB_COND = 122,
136 G_ATOMICRMW_USUB_SAT = 123,
137 G_FENCE = 124,
138 G_PREFETCH = 125,
139 G_BRCOND = 126,
140 G_BRINDIRECT = 127,
141 G_INVOKE_REGION_START = 128,
142 G_INTRINSIC = 129,
143 G_INTRINSIC_W_SIDE_EFFECTS = 130,
144 G_INTRINSIC_CONVERGENT = 131,
145 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 132,
146 G_ANYEXT = 133,
147 G_TRUNC = 134,
148 G_CONSTANT = 135,
149 G_FCONSTANT = 136,
150 G_VASTART = 137,
151 G_VAARG = 138,
152 G_SEXT = 139,
153 G_SEXT_INREG = 140,
154 G_ZEXT = 141,
155 G_SHL = 142,
156 G_LSHR = 143,
157 G_ASHR = 144,
158 G_FSHL = 145,
159 G_FSHR = 146,
160 G_ROTR = 147,
161 G_ROTL = 148,
162 G_ICMP = 149,
163 G_FCMP = 150,
164 G_SCMP = 151,
165 G_UCMP = 152,
166 G_SELECT = 153,
167 G_UADDO = 154,
168 G_UADDE = 155,
169 G_USUBO = 156,
170 G_USUBE = 157,
171 G_SADDO = 158,
172 G_SADDE = 159,
173 G_SSUBO = 160,
174 G_SSUBE = 161,
175 G_UMULO = 162,
176 G_SMULO = 163,
177 G_UMULH = 164,
178 G_SMULH = 165,
179 G_UADDSAT = 166,
180 G_SADDSAT = 167,
181 G_USUBSAT = 168,
182 G_SSUBSAT = 169,
183 G_USHLSAT = 170,
184 G_SSHLSAT = 171,
185 G_SMULFIX = 172,
186 G_UMULFIX = 173,
187 G_SMULFIXSAT = 174,
188 G_UMULFIXSAT = 175,
189 G_SDIVFIX = 176,
190 G_UDIVFIX = 177,
191 G_SDIVFIXSAT = 178,
192 G_UDIVFIXSAT = 179,
193 G_FADD = 180,
194 G_FSUB = 181,
195 G_FMUL = 182,
196 G_FMA = 183,
197 G_FMAD = 184,
198 G_FDIV = 185,
199 G_FREM = 186,
200 G_FPOW = 187,
201 G_FPOWI = 188,
202 G_FEXP = 189,
203 G_FEXP2 = 190,
204 G_FEXP10 = 191,
205 G_FLOG = 192,
206 G_FLOG2 = 193,
207 G_FLOG10 = 194,
208 G_FLDEXP = 195,
209 G_FFREXP = 196,
210 G_FNEG = 197,
211 G_FPEXT = 198,
212 G_FPTRUNC = 199,
213 G_FPTOSI = 200,
214 G_FPTOUI = 201,
215 G_SITOFP = 202,
216 G_UITOFP = 203,
217 G_FPTOSI_SAT = 204,
218 G_FPTOUI_SAT = 205,
219 G_FABS = 206,
220 G_FCOPYSIGN = 207,
221 G_IS_FPCLASS = 208,
222 G_FCANONICALIZE = 209,
223 G_FMINNUM = 210,
224 G_FMAXNUM = 211,
225 G_FMINNUM_IEEE = 212,
226 G_FMAXNUM_IEEE = 213,
227 G_FMINIMUM = 214,
228 G_FMAXIMUM = 215,
229 G_FMINIMUMNUM = 216,
230 G_FMAXIMUMNUM = 217,
231 G_GET_FPENV = 218,
232 G_SET_FPENV = 219,
233 G_RESET_FPENV = 220,
234 G_GET_FPMODE = 221,
235 G_SET_FPMODE = 222,
236 G_RESET_FPMODE = 223,
237 G_PTR_ADD = 224,
238 G_PTRMASK = 225,
239 G_SMIN = 226,
240 G_SMAX = 227,
241 G_UMIN = 228,
242 G_UMAX = 229,
243 G_ABS = 230,
244 G_LROUND = 231,
245 G_LLROUND = 232,
246 G_BR = 233,
247 G_BRJT = 234,
248 G_VSCALE = 235,
249 G_INSERT_SUBVECTOR = 236,
250 G_EXTRACT_SUBVECTOR = 237,
251 G_INSERT_VECTOR_ELT = 238,
252 G_EXTRACT_VECTOR_ELT = 239,
253 G_SHUFFLE_VECTOR = 240,
254 G_SPLAT_VECTOR = 241,
255 G_STEP_VECTOR = 242,
256 G_VECTOR_COMPRESS = 243,
257 G_CTTZ = 244,
258 G_CTTZ_ZERO_UNDEF = 245,
259 G_CTLZ = 246,
260 G_CTLZ_ZERO_UNDEF = 247,
261 G_CTPOP = 248,
262 G_BSWAP = 249,
263 G_BITREVERSE = 250,
264 G_FCEIL = 251,
265 G_FCOS = 252,
266 G_FSIN = 253,
267 G_FSINCOS = 254,
268 G_FTAN = 255,
269 G_FACOS = 256,
270 G_FASIN = 257,
271 G_FATAN = 258,
272 G_FATAN2 = 259,
273 G_FCOSH = 260,
274 G_FSINH = 261,
275 G_FTANH = 262,
276 G_FSQRT = 263,
277 G_FFLOOR = 264,
278 G_FRINT = 265,
279 G_FNEARBYINT = 266,
280 G_ADDRSPACE_CAST = 267,
281 G_BLOCK_ADDR = 268,
282 G_JUMP_TABLE = 269,
283 G_DYN_STACKALLOC = 270,
284 G_STACKSAVE = 271,
285 G_STACKRESTORE = 272,
286 G_STRICT_FADD = 273,
287 G_STRICT_FSUB = 274,
288 G_STRICT_FMUL = 275,
289 G_STRICT_FDIV = 276,
290 G_STRICT_FREM = 277,
291 G_STRICT_FMA = 278,
292 G_STRICT_FSQRT = 279,
293 G_STRICT_FLDEXP = 280,
294 G_READ_REGISTER = 281,
295 G_WRITE_REGISTER = 282,
296 G_MEMCPY = 283,
297 G_MEMCPY_INLINE = 284,
298 G_MEMMOVE = 285,
299 G_MEMSET = 286,
300 G_BZERO = 287,
301 G_TRAP = 288,
302 G_DEBUGTRAP = 289,
303 G_UBSANTRAP = 290,
304 G_VECREDUCE_SEQ_FADD = 291,
305 G_VECREDUCE_SEQ_FMUL = 292,
306 G_VECREDUCE_FADD = 293,
307 G_VECREDUCE_FMUL = 294,
308 G_VECREDUCE_FMAX = 295,
309 G_VECREDUCE_FMIN = 296,
310 G_VECREDUCE_FMAXIMUM = 297,
311 G_VECREDUCE_FMINIMUM = 298,
312 G_VECREDUCE_ADD = 299,
313 G_VECREDUCE_MUL = 300,
314 G_VECREDUCE_AND = 301,
315 G_VECREDUCE_OR = 302,
316 G_VECREDUCE_XOR = 303,
317 G_VECREDUCE_SMAX = 304,
318 G_VECREDUCE_SMIN = 305,
319 G_VECREDUCE_UMAX = 306,
320 G_VECREDUCE_UMIN = 307,
321 G_SBFX = 308,
322 G_UBFX = 309,
323 ABSMacro = 310,
324 ADJCALLSTACKDOWN = 311,
325 ADJCALLSTACKUP = 312,
326 AND_V_D_PSEUDO = 313,
327 AND_V_H_PSEUDO = 314,
328 AND_V_W_PSEUDO = 315,
329 ATOMIC_CMP_SWAP_I16 = 316,
330 ATOMIC_CMP_SWAP_I16_POSTRA = 317,
331 ATOMIC_CMP_SWAP_I32 = 318,
332 ATOMIC_CMP_SWAP_I32_POSTRA = 319,
333 ATOMIC_CMP_SWAP_I64 = 320,
334 ATOMIC_CMP_SWAP_I64_POSTRA = 321,
335 ATOMIC_CMP_SWAP_I8 = 322,
336 ATOMIC_CMP_SWAP_I8_POSTRA = 323,
337 ATOMIC_LOAD_ADD_I16 = 324,
338 ATOMIC_LOAD_ADD_I16_POSTRA = 325,
339 ATOMIC_LOAD_ADD_I32 = 326,
340 ATOMIC_LOAD_ADD_I32_POSTRA = 327,
341 ATOMIC_LOAD_ADD_I64 = 328,
342 ATOMIC_LOAD_ADD_I64_POSTRA = 329,
343 ATOMIC_LOAD_ADD_I8 = 330,
344 ATOMIC_LOAD_ADD_I8_POSTRA = 331,
345 ATOMIC_LOAD_AND_I16 = 332,
346 ATOMIC_LOAD_AND_I16_POSTRA = 333,
347 ATOMIC_LOAD_AND_I32 = 334,
348 ATOMIC_LOAD_AND_I32_POSTRA = 335,
349 ATOMIC_LOAD_AND_I64 = 336,
350 ATOMIC_LOAD_AND_I64_POSTRA = 337,
351 ATOMIC_LOAD_AND_I8 = 338,
352 ATOMIC_LOAD_AND_I8_POSTRA = 339,
353 ATOMIC_LOAD_MAX_I16 = 340,
354 ATOMIC_LOAD_MAX_I16_POSTRA = 341,
355 ATOMIC_LOAD_MAX_I32 = 342,
356 ATOMIC_LOAD_MAX_I32_POSTRA = 343,
357 ATOMIC_LOAD_MAX_I64 = 344,
358 ATOMIC_LOAD_MAX_I64_POSTRA = 345,
359 ATOMIC_LOAD_MAX_I8 = 346,
360 ATOMIC_LOAD_MAX_I8_POSTRA = 347,
361 ATOMIC_LOAD_MIN_I16 = 348,
362 ATOMIC_LOAD_MIN_I16_POSTRA = 349,
363 ATOMIC_LOAD_MIN_I32 = 350,
364 ATOMIC_LOAD_MIN_I32_POSTRA = 351,
365 ATOMIC_LOAD_MIN_I64 = 352,
366 ATOMIC_LOAD_MIN_I64_POSTRA = 353,
367 ATOMIC_LOAD_MIN_I8 = 354,
368 ATOMIC_LOAD_MIN_I8_POSTRA = 355,
369 ATOMIC_LOAD_NAND_I16 = 356,
370 ATOMIC_LOAD_NAND_I16_POSTRA = 357,
371 ATOMIC_LOAD_NAND_I32 = 358,
372 ATOMIC_LOAD_NAND_I32_POSTRA = 359,
373 ATOMIC_LOAD_NAND_I64 = 360,
374 ATOMIC_LOAD_NAND_I64_POSTRA = 361,
375 ATOMIC_LOAD_NAND_I8 = 362,
376 ATOMIC_LOAD_NAND_I8_POSTRA = 363,
377 ATOMIC_LOAD_OR_I16 = 364,
378 ATOMIC_LOAD_OR_I16_POSTRA = 365,
379 ATOMIC_LOAD_OR_I32 = 366,
380 ATOMIC_LOAD_OR_I32_POSTRA = 367,
381 ATOMIC_LOAD_OR_I64 = 368,
382 ATOMIC_LOAD_OR_I64_POSTRA = 369,
383 ATOMIC_LOAD_OR_I8 = 370,
384 ATOMIC_LOAD_OR_I8_POSTRA = 371,
385 ATOMIC_LOAD_SUB_I16 = 372,
386 ATOMIC_LOAD_SUB_I16_POSTRA = 373,
387 ATOMIC_LOAD_SUB_I32 = 374,
388 ATOMIC_LOAD_SUB_I32_POSTRA = 375,
389 ATOMIC_LOAD_SUB_I64 = 376,
390 ATOMIC_LOAD_SUB_I64_POSTRA = 377,
391 ATOMIC_LOAD_SUB_I8 = 378,
392 ATOMIC_LOAD_SUB_I8_POSTRA = 379,
393 ATOMIC_LOAD_UMAX_I16 = 380,
394 ATOMIC_LOAD_UMAX_I16_POSTRA = 381,
395 ATOMIC_LOAD_UMAX_I32 = 382,
396 ATOMIC_LOAD_UMAX_I32_POSTRA = 383,
397 ATOMIC_LOAD_UMAX_I64 = 384,
398 ATOMIC_LOAD_UMAX_I64_POSTRA = 385,
399 ATOMIC_LOAD_UMAX_I8 = 386,
400 ATOMIC_LOAD_UMAX_I8_POSTRA = 387,
401 ATOMIC_LOAD_UMIN_I16 = 388,
402 ATOMIC_LOAD_UMIN_I16_POSTRA = 389,
403 ATOMIC_LOAD_UMIN_I32 = 390,
404 ATOMIC_LOAD_UMIN_I32_POSTRA = 391,
405 ATOMIC_LOAD_UMIN_I64 = 392,
406 ATOMIC_LOAD_UMIN_I64_POSTRA = 393,
407 ATOMIC_LOAD_UMIN_I8 = 394,
408 ATOMIC_LOAD_UMIN_I8_POSTRA = 395,
409 ATOMIC_LOAD_XOR_I16 = 396,
410 ATOMIC_LOAD_XOR_I16_POSTRA = 397,
411 ATOMIC_LOAD_XOR_I32 = 398,
412 ATOMIC_LOAD_XOR_I32_POSTRA = 399,
413 ATOMIC_LOAD_XOR_I64 = 400,
414 ATOMIC_LOAD_XOR_I64_POSTRA = 401,
415 ATOMIC_LOAD_XOR_I8 = 402,
416 ATOMIC_LOAD_XOR_I8_POSTRA = 403,
417 ATOMIC_SWAP_I16 = 404,
418 ATOMIC_SWAP_I16_POSTRA = 405,
419 ATOMIC_SWAP_I32 = 406,
420 ATOMIC_SWAP_I32_POSTRA = 407,
421 ATOMIC_SWAP_I64 = 408,
422 ATOMIC_SWAP_I64_POSTRA = 409,
423 ATOMIC_SWAP_I8 = 410,
424 ATOMIC_SWAP_I8_POSTRA = 411,
425 B = 412,
426 BAL_BR = 413,
427 BAL_BR_MM = 414,
428 BEQLImmMacro = 415,
429 BGE = 416,
430 BGEImmMacro = 417,
431 BGEL = 418,
432 BGELImmMacro = 419,
433 BGEU = 420,
434 BGEUImmMacro = 421,
435 BGEUL = 422,
436 BGEULImmMacro = 423,
437 BGT = 424,
438 BGTImmMacro = 425,
439 BGTL = 426,
440 BGTLImmMacro = 427,
441 BGTU = 428,
442 BGTUImmMacro = 429,
443 BGTUL = 430,
444 BGTULImmMacro = 431,
445 BLE = 432,
446 BLEImmMacro = 433,
447 BLEL = 434,
448 BLELImmMacro = 435,
449 BLEU = 436,
450 BLEUImmMacro = 437,
451 BLEUL = 438,
452 BLEULImmMacro = 439,
453 BLT = 440,
454 BLTImmMacro = 441,
455 BLTL = 442,
456 BLTLImmMacro = 443,
457 BLTU = 444,
458 BLTUImmMacro = 445,
459 BLTUL = 446,
460 BLTULImmMacro = 447,
461 BNELImmMacro = 448,
462 BPOSGE32_PSEUDO = 449,
463 BSEL_D_PSEUDO = 450,
464 BSEL_FD_PSEUDO = 451,
465 BSEL_FW_PSEUDO = 452,
466 BSEL_H_PSEUDO = 453,
467 BSEL_W_PSEUDO = 454,
468 B_MM = 455,
469 B_MMR6_Pseudo = 456,
470 B_MM_Pseudo = 457,
471 BeqImm = 458,
472 BneImm = 459,
473 BteqzT8CmpX16 = 460,
474 BteqzT8CmpiX16 = 461,
475 BteqzT8SltX16 = 462,
476 BteqzT8SltiX16 = 463,
477 BteqzT8SltiuX16 = 464,
478 BteqzT8SltuX16 = 465,
479 BtnezT8CmpX16 = 466,
480 BtnezT8CmpiX16 = 467,
481 BtnezT8SltX16 = 468,
482 BtnezT8SltiX16 = 469,
483 BtnezT8SltiuX16 = 470,
484 BtnezT8SltuX16 = 471,
485 BuildPairF64 = 472,
486 BuildPairF64_64 = 473,
487 CFTC1 = 474,
488 CONSTPOOL_ENTRY = 475,
489 COPY_FD_PSEUDO = 476,
490 COPY_FW_PSEUDO = 477,
491 CTTC1 = 478,
492 Constant32 = 479,
493 DMULImmMacro = 480,
494 DMULMacro = 481,
495 DMULOMacro = 482,
496 DMULOUMacro = 483,
497 DROL = 484,
498 DROLImm = 485,
499 DROR = 486,
500 DRORImm = 487,
501 DSDivIMacro = 488,
502 DSDivMacro = 489,
503 DSRemIMacro = 490,
504 DSRemMacro = 491,
505 DUDivIMacro = 492,
506 DUDivMacro = 493,
507 DURemIMacro = 494,
508 DURemMacro = 495,
509 ERet = 496,
510 ExtractElementF64 = 497,
511 ExtractElementF64_64 = 498,
512 FABS_D = 499,
513 FABS_W = 500,
514 FEXP2_D_1_PSEUDO = 501,
515 FEXP2_W_1_PSEUDO = 502,
516 FILL_FD_PSEUDO = 503,
517 FILL_FW_PSEUDO = 504,
518 GotPrologue16 = 505,
519 INSERT_B_VIDX64_PSEUDO = 506,
520 INSERT_B_VIDX_PSEUDO = 507,
521 INSERT_D_VIDX64_PSEUDO = 508,
522 INSERT_D_VIDX_PSEUDO = 509,
523 INSERT_FD_PSEUDO = 510,
524 INSERT_FD_VIDX64_PSEUDO = 511,
525 INSERT_FD_VIDX_PSEUDO = 512,
526 INSERT_FW_PSEUDO = 513,
527 INSERT_FW_VIDX64_PSEUDO = 514,
528 INSERT_FW_VIDX_PSEUDO = 515,
529 INSERT_H_VIDX64_PSEUDO = 516,
530 INSERT_H_VIDX_PSEUDO = 517,
531 INSERT_W_VIDX64_PSEUDO = 518,
532 INSERT_W_VIDX_PSEUDO = 519,
533 JALR64Pseudo = 520,
534 JALRHB64Pseudo = 521,
535 JALRHBPseudo = 522,
536 JALRPseudo = 523,
537 JAL_MMR6 = 524,
538 JalOneReg = 525,
539 JalTwoReg = 526,
540 LDMacro = 527,
541 LDR_D = 528,
542 LDR_W = 529,
543 LD_F16 = 530,
544 LOAD_ACC128 = 531,
545 LOAD_ACC64 = 532,
546 LOAD_ACC64DSP = 533,
547 LOAD_CCOND_DSP = 534,
548 LONG_BRANCH_ADDiu = 535,
549 LONG_BRANCH_ADDiu2Op = 536,
550 LONG_BRANCH_DADDiu = 537,
551 LONG_BRANCH_DADDiu2Op = 538,
552 LONG_BRANCH_LUi = 539,
553 LONG_BRANCH_LUi2Op = 540,
554 LONG_BRANCH_LUi2Op_64 = 541,
555 LWM_MM = 542,
556 LoadAddrImm32 = 543,
557 LoadAddrImm64 = 544,
558 LoadAddrReg32 = 545,
559 LoadAddrReg64 = 546,
560 LoadImm32 = 547,
561 LoadImm64 = 548,
562 LoadImmDoubleFGR = 549,
563 LoadImmDoubleFGR_32 = 550,
564 LoadImmDoubleGPR = 551,
565 LoadImmSingleFGR = 552,
566 LoadImmSingleGPR = 553,
567 LwConstant32 = 554,
568 MFTACX = 555,
569 MFTC0 = 556,
570 MFTC1 = 557,
571 MFTDSP = 558,
572 MFTGPR = 559,
573 MFTHC1 = 560,
574 MFTHI = 561,
575 MFTLO = 562,
576 MIPSeh_return32 = 563,
577 MIPSeh_return64 = 564,
578 MSA_FP_EXTEND_D_PSEUDO = 565,
579 MSA_FP_EXTEND_W_PSEUDO = 566,
580 MSA_FP_ROUND_D_PSEUDO = 567,
581 MSA_FP_ROUND_W_PSEUDO = 568,
582 MTTACX = 569,
583 MTTC0 = 570,
584 MTTC1 = 571,
585 MTTDSP = 572,
586 MTTGPR = 573,
587 MTTHC1 = 574,
588 MTTHI = 575,
589 MTTLO = 576,
590 MULImmMacro = 577,
591 MULOMacro = 578,
592 MULOUMacro = 579,
593 MultRxRy16 = 580,
594 MultRxRyRz16 = 581,
595 MultuRxRy16 = 582,
596 MultuRxRyRz16 = 583,
597 NOP = 584,
598 NORImm = 585,
599 NORImm64 = 586,
600 NOR_V_D_PSEUDO = 587,
601 NOR_V_H_PSEUDO = 588,
602 NOR_V_W_PSEUDO = 589,
603 OR_V_D_PSEUDO = 590,
604 OR_V_H_PSEUDO = 591,
605 OR_V_W_PSEUDO = 592,
606 PseudoCMPU_EQ_QB = 593,
607 PseudoCMPU_LE_QB = 594,
608 PseudoCMPU_LT_QB = 595,
609 PseudoCMP_EQ_PH = 596,
610 PseudoCMP_LE_PH = 597,
611 PseudoCMP_LT_PH = 598,
612 PseudoCVT_D32_W = 599,
613 PseudoCVT_D64_L = 600,
614 PseudoCVT_D64_W = 601,
615 PseudoCVT_S_L = 602,
616 PseudoCVT_S_W = 603,
617 PseudoDMULT = 604,
618 PseudoDMULTu = 605,
619 PseudoDSDIV = 606,
620 PseudoDUDIV = 607,
621 PseudoD_SELECT_I = 608,
622 PseudoD_SELECT_I64 = 609,
623 PseudoIndirectBranch = 610,
624 PseudoIndirectBranch64 = 611,
625 PseudoIndirectBranch64R6 = 612,
626 PseudoIndirectBranchR6 = 613,
627 PseudoIndirectBranch_MM = 614,
628 PseudoIndirectBranch_MMR6 = 615,
629 PseudoIndirectHazardBranch = 616,
630 PseudoIndirectHazardBranch64 = 617,
631 PseudoIndrectHazardBranch64R6 = 618,
632 PseudoIndrectHazardBranchR6 = 619,
633 PseudoMADD = 620,
634 PseudoMADDU = 621,
635 PseudoMADDU_MM = 622,
636 PseudoMADD_MM = 623,
637 PseudoMFHI = 624,
638 PseudoMFHI64 = 625,
639 PseudoMFHI_MM = 626,
640 PseudoMFLO = 627,
641 PseudoMFLO64 = 628,
642 PseudoMFLO_MM = 629,
643 PseudoMSUB = 630,
644 PseudoMSUBU = 631,
645 PseudoMSUBU_MM = 632,
646 PseudoMSUB_MM = 633,
647 PseudoMTLOHI = 634,
648 PseudoMTLOHI64 = 635,
649 PseudoMTLOHI_DSP = 636,
650 PseudoMTLOHI_MM = 637,
651 PseudoMULT = 638,
652 PseudoMULT_MM = 639,
653 PseudoMULTu = 640,
654 PseudoMULTu_MM = 641,
655 PseudoPICK_PH = 642,
656 PseudoPICK_QB = 643,
657 PseudoReturn = 644,
658 PseudoReturn64 = 645,
659 PseudoSDIV = 646,
660 PseudoSELECTFP_F_D32 = 647,
661 PseudoSELECTFP_F_D64 = 648,
662 PseudoSELECTFP_F_I = 649,
663 PseudoSELECTFP_F_I64 = 650,
664 PseudoSELECTFP_F_S = 651,
665 PseudoSELECTFP_T_D32 = 652,
666 PseudoSELECTFP_T_D64 = 653,
667 PseudoSELECTFP_T_I = 654,
668 PseudoSELECTFP_T_I64 = 655,
669 PseudoSELECTFP_T_S = 656,
670 PseudoSELECT_D32 = 657,
671 PseudoSELECT_D64 = 658,
672 PseudoSELECT_I = 659,
673 PseudoSELECT_I64 = 660,
674 PseudoSELECT_S = 661,
675 PseudoTRUNC_W_D = 662,
676 PseudoTRUNC_W_D32 = 663,
677 PseudoTRUNC_W_S = 664,
678 PseudoUDIV = 665,
679 ROL = 666,
680 ROLImm = 667,
681 ROR = 668,
682 RORImm = 669,
683 RetRA = 670,
684 RetRA16 = 671,
685 SDC1_M1 = 672,
686 SDIV_MM_Pseudo = 673,
687 SDMacro = 674,
688 SDivIMacro = 675,
689 SDivMacro = 676,
690 SEQIMacro = 677,
691 SEQMacro = 678,
692 SGE = 679,
693 SGEImm = 680,
694 SGEImm64 = 681,
695 SGEU = 682,
696 SGEUImm = 683,
697 SGEUImm64 = 684,
698 SGTImm = 685,
699 SGTImm64 = 686,
700 SGTUImm = 687,
701 SGTUImm64 = 688,
702 SLE = 689,
703 SLEImm = 690,
704 SLEImm64 = 691,
705 SLEU = 692,
706 SLEUImm = 693,
707 SLEUImm64 = 694,
708 SLTImm64 = 695,
709 SLTUImm64 = 696,
710 SNEIMacro = 697,
711 SNEMacro = 698,
712 SNZ_B_PSEUDO = 699,
713 SNZ_D_PSEUDO = 700,
714 SNZ_H_PSEUDO = 701,
715 SNZ_V_PSEUDO = 702,
716 SNZ_W_PSEUDO = 703,
717 SRemIMacro = 704,
718 SRemMacro = 705,
719 STORE_ACC128 = 706,
720 STORE_ACC64 = 707,
721 STORE_ACC64DSP = 708,
722 STORE_CCOND_DSP = 709,
723 STR_D = 710,
724 STR_W = 711,
725 ST_F16 = 712,
726 SWM_MM = 713,
727 SZ_B_PSEUDO = 714,
728 SZ_D_PSEUDO = 715,
729 SZ_H_PSEUDO = 716,
730 SZ_V_PSEUDO = 717,
731 SZ_W_PSEUDO = 718,
732 SaaAddr = 719,
733 SaadAddr = 720,
734 SelBeqZ = 721,
735 SelBneZ = 722,
736 SelTBteqZCmp = 723,
737 SelTBteqZCmpi = 724,
738 SelTBteqZSlt = 725,
739 SelTBteqZSlti = 726,
740 SelTBteqZSltiu = 727,
741 SelTBteqZSltu = 728,
742 SelTBtneZCmp = 729,
743 SelTBtneZCmpi = 730,
744 SelTBtneZSlt = 731,
745 SelTBtneZSlti = 732,
746 SelTBtneZSltiu = 733,
747 SelTBtneZSltu = 734,
748 SltCCRxRy16 = 735,
749 SltiCCRxImmX16 = 736,
750 SltiuCCRxImmX16 = 737,
751 SltuCCRxRy16 = 738,
752 SltuRxRyRz16 = 739,
753 TAILCALL = 740,
754 TAILCALL64R6REG = 741,
755 TAILCALLHB64R6REG = 742,
756 TAILCALLHBR6REG = 743,
757 TAILCALLR6REG = 744,
758 TAILCALLREG = 745,
759 TAILCALLREG64 = 746,
760 TAILCALLREGHB = 747,
761 TAILCALLREGHB64 = 748,
762 TAILCALLREG_MM = 749,
763 TAILCALLREG_MMR6 = 750,
764 TAILCALL_MM = 751,
765 TAILCALL_MMR6 = 752,
766 TRAP = 753,
767 TRAP_MM = 754,
768 UDIV_MM_Pseudo = 755,
769 UDivIMacro = 756,
770 UDivMacro = 757,
771 URemIMacro = 758,
772 URemMacro = 759,
773 Ulh = 760,
774 Ulhu = 761,
775 Ulw = 762,
776 Ush = 763,
777 Usw = 764,
778 XOR_V_D_PSEUDO = 765,
779 XOR_V_H_PSEUDO = 766,
780 XOR_V_W_PSEUDO = 767,
781 ABSQ_S_PH = 768,
782 ABSQ_S_PH_MM = 769,
783 ABSQ_S_QB = 770,
784 ABSQ_S_QB_MMR2 = 771,
785 ABSQ_S_W = 772,
786 ABSQ_S_W_MM = 773,
787 ADD = 774,
788 ADDIUPC = 775,
789 ADDIUPC_MM = 776,
790 ADDIUPC_MMR6 = 777,
791 ADDIUR1SP_MM = 778,
792 ADDIUR2_MM = 779,
793 ADDIUS5_MM = 780,
794 ADDIUSP_MM = 781,
795 ADDIU_MMR6 = 782,
796 ADDQH_PH = 783,
797 ADDQH_PH_MMR2 = 784,
798 ADDQH_R_PH = 785,
799 ADDQH_R_PH_MMR2 = 786,
800 ADDQH_R_W = 787,
801 ADDQH_R_W_MMR2 = 788,
802 ADDQH_W = 789,
803 ADDQH_W_MMR2 = 790,
804 ADDQ_PH = 791,
805 ADDQ_PH_MM = 792,
806 ADDQ_S_PH = 793,
807 ADDQ_S_PH_MM = 794,
808 ADDQ_S_W = 795,
809 ADDQ_S_W_MM = 796,
810 ADDR_PS64 = 797,
811 ADDSC = 798,
812 ADDSC_MM = 799,
813 ADDS_A_B = 800,
814 ADDS_A_D = 801,
815 ADDS_A_H = 802,
816 ADDS_A_W = 803,
817 ADDS_S_B = 804,
818 ADDS_S_D = 805,
819 ADDS_S_H = 806,
820 ADDS_S_W = 807,
821 ADDS_U_B = 808,
822 ADDS_U_D = 809,
823 ADDS_U_H = 810,
824 ADDS_U_W = 811,
825 ADDU16_MM = 812,
826 ADDU16_MMR6 = 813,
827 ADDUH_QB = 814,
828 ADDUH_QB_MMR2 = 815,
829 ADDUH_R_QB = 816,
830 ADDUH_R_QB_MMR2 = 817,
831 ADDU_MMR6 = 818,
832 ADDU_PH = 819,
833 ADDU_PH_MMR2 = 820,
834 ADDU_QB = 821,
835 ADDU_QB_MM = 822,
836 ADDU_S_PH = 823,
837 ADDU_S_PH_MMR2 = 824,
838 ADDU_S_QB = 825,
839 ADDU_S_QB_MM = 826,
840 ADDVI_B = 827,
841 ADDVI_D = 828,
842 ADDVI_H = 829,
843 ADDVI_W = 830,
844 ADDV_B = 831,
845 ADDV_D = 832,
846 ADDV_H = 833,
847 ADDV_W = 834,
848 ADDWC = 835,
849 ADDWC_MM = 836,
850 ADD_A_B = 837,
851 ADD_A_D = 838,
852 ADD_A_H = 839,
853 ADD_A_W = 840,
854 ADD_MM = 841,
855 ADD_MMR6 = 842,
856 ADDi = 843,
857 ADDi_MM = 844,
858 ADDiu = 845,
859 ADDiu_MM = 846,
860 ADDu = 847,
861 ADDu_MM = 848,
862 ALIGN = 849,
863 ALIGN_MMR6 = 850,
864 ALUIPC = 851,
865 ALUIPC_MMR6 = 852,
866 AND = 853,
867 AND16_MM = 854,
868 AND16_MMR6 = 855,
869 AND64 = 856,
870 ANDI16_MM = 857,
871 ANDI16_MMR6 = 858,
872 ANDI_B = 859,
873 ANDI_MMR6 = 860,
874 AND_MM = 861,
875 AND_MMR6 = 862,
876 AND_V = 863,
877 ANDi = 864,
878 ANDi64 = 865,
879 ANDi_MM = 866,
880 APPEND = 867,
881 APPEND_MMR2 = 868,
882 ASUB_S_B = 869,
883 ASUB_S_D = 870,
884 ASUB_S_H = 871,
885 ASUB_S_W = 872,
886 ASUB_U_B = 873,
887 ASUB_U_D = 874,
888 ASUB_U_H = 875,
889 ASUB_U_W = 876,
890 AUI = 877,
891 AUIPC = 878,
892 AUIPC_MMR6 = 879,
893 AUI_MMR6 = 880,
894 AVER_S_B = 881,
895 AVER_S_D = 882,
896 AVER_S_H = 883,
897 AVER_S_W = 884,
898 AVER_U_B = 885,
899 AVER_U_D = 886,
900 AVER_U_H = 887,
901 AVER_U_W = 888,
902 AVE_S_B = 889,
903 AVE_S_D = 890,
904 AVE_S_H = 891,
905 AVE_S_W = 892,
906 AVE_U_B = 893,
907 AVE_U_D = 894,
908 AVE_U_H = 895,
909 AVE_U_W = 896,
910 AddiuRxImmX16 = 897,
911 AddiuRxPcImmX16 = 898,
912 AddiuRxRxImm16 = 899,
913 AddiuRxRxImmX16 = 900,
914 AddiuRxRyOffMemX16 = 901,
915 AddiuSpImm16 = 902,
916 AddiuSpImmX16 = 903,
917 AdduRxRyRz16 = 904,
918 AndRxRxRy16 = 905,
919 B16_MM = 906,
920 BADDu = 907,
921 BAL = 908,
922 BALC = 909,
923 BALC_MMR6 = 910,
924 BALIGN = 911,
925 BALIGN_MMR2 = 912,
926 BBIT0 = 913,
927 BBIT032 = 914,
928 BBIT1 = 915,
929 BBIT132 = 916,
930 BC = 917,
931 BC16_MMR6 = 918,
932 BC1EQZ = 919,
933 BC1EQZC_MMR6 = 920,
934 BC1F = 921,
935 BC1FL = 922,
936 BC1F_MM = 923,
937 BC1NEZ = 924,
938 BC1NEZC_MMR6 = 925,
939 BC1T = 926,
940 BC1TL = 927,
941 BC1T_MM = 928,
942 BC2EQZ = 929,
943 BC2EQZC_MMR6 = 930,
944 BC2NEZ = 931,
945 BC2NEZC_MMR6 = 932,
946 BCLRI_B = 933,
947 BCLRI_D = 934,
948 BCLRI_H = 935,
949 BCLRI_W = 936,
950 BCLR_B = 937,
951 BCLR_D = 938,
952 BCLR_H = 939,
953 BCLR_W = 940,
954 BC_MMR6 = 941,
955 BEQ = 942,
956 BEQ64 = 943,
957 BEQC = 944,
958 BEQC64 = 945,
959 BEQC_MMR6 = 946,
960 BEQL = 947,
961 BEQZ16_MM = 948,
962 BEQZALC = 949,
963 BEQZALC_MMR6 = 950,
964 BEQZC = 951,
965 BEQZC16_MMR6 = 952,
966 BEQZC64 = 953,
967 BEQZC_MM = 954,
968 BEQZC_MMR6 = 955,
969 BEQ_MM = 956,
970 BGEC = 957,
971 BGEC64 = 958,
972 BGEC_MMR6 = 959,
973 BGEUC = 960,
974 BGEUC64 = 961,
975 BGEUC_MMR6 = 962,
976 BGEZ = 963,
977 BGEZ64 = 964,
978 BGEZAL = 965,
979 BGEZALC = 966,
980 BGEZALC_MMR6 = 967,
981 BGEZALL = 968,
982 BGEZALS_MM = 969,
983 BGEZAL_MM = 970,
984 BGEZC = 971,
985 BGEZC64 = 972,
986 BGEZC_MMR6 = 973,
987 BGEZL = 974,
988 BGEZ_MM = 975,
989 BGTZ = 976,
990 BGTZ64 = 977,
991 BGTZALC = 978,
992 BGTZALC_MMR6 = 979,
993 BGTZC = 980,
994 BGTZC64 = 981,
995 BGTZC_MMR6 = 982,
996 BGTZL = 983,
997 BGTZ_MM = 984,
998 BINSLI_B = 985,
999 BINSLI_D = 986,
1000 BINSLI_H = 987,
1001 BINSLI_W = 988,
1002 BINSL_B = 989,
1003 BINSL_D = 990,
1004 BINSL_H = 991,
1005 BINSL_W = 992,
1006 BINSRI_B = 993,
1007 BINSRI_D = 994,
1008 BINSRI_H = 995,
1009 BINSRI_W = 996,
1010 BINSR_B = 997,
1011 BINSR_D = 998,
1012 BINSR_H = 999,
1013 BINSR_W = 1000,
1014 BITREV = 1001,
1015 BITREV_MM = 1002,
1016 BITSWAP = 1003,
1017 BITSWAP_MMR6 = 1004,
1018 BLEZ = 1005,
1019 BLEZ64 = 1006,
1020 BLEZALC = 1007,
1021 BLEZALC_MMR6 = 1008,
1022 BLEZC = 1009,
1023 BLEZC64 = 1010,
1024 BLEZC_MMR6 = 1011,
1025 BLEZL = 1012,
1026 BLEZ_MM = 1013,
1027 BLTC = 1014,
1028 BLTC64 = 1015,
1029 BLTC_MMR6 = 1016,
1030 BLTUC = 1017,
1031 BLTUC64 = 1018,
1032 BLTUC_MMR6 = 1019,
1033 BLTZ = 1020,
1034 BLTZ64 = 1021,
1035 BLTZAL = 1022,
1036 BLTZALC = 1023,
1037 BLTZALC_MMR6 = 1024,
1038 BLTZALL = 1025,
1039 BLTZALS_MM = 1026,
1040 BLTZAL_MM = 1027,
1041 BLTZC = 1028,
1042 BLTZC64 = 1029,
1043 BLTZC_MMR6 = 1030,
1044 BLTZL = 1031,
1045 BLTZ_MM = 1032,
1046 BMNZI_B = 1033,
1047 BMNZ_V = 1034,
1048 BMZI_B = 1035,
1049 BMZ_V = 1036,
1050 BNE = 1037,
1051 BNE64 = 1038,
1052 BNEC = 1039,
1053 BNEC64 = 1040,
1054 BNEC_MMR6 = 1041,
1055 BNEGI_B = 1042,
1056 BNEGI_D = 1043,
1057 BNEGI_H = 1044,
1058 BNEGI_W = 1045,
1059 BNEG_B = 1046,
1060 BNEG_D = 1047,
1061 BNEG_H = 1048,
1062 BNEG_W = 1049,
1063 BNEL = 1050,
1064 BNEZ16_MM = 1051,
1065 BNEZALC = 1052,
1066 BNEZALC_MMR6 = 1053,
1067 BNEZC = 1054,
1068 BNEZC16_MMR6 = 1055,
1069 BNEZC64 = 1056,
1070 BNEZC_MM = 1057,
1071 BNEZC_MMR6 = 1058,
1072 BNE_MM = 1059,
1073 BNVC = 1060,
1074 BNVC_MMR6 = 1061,
1075 BNZ_B = 1062,
1076 BNZ_D = 1063,
1077 BNZ_H = 1064,
1078 BNZ_V = 1065,
1079 BNZ_W = 1066,
1080 BOVC = 1067,
1081 BOVC_MMR6 = 1068,
1082 BPOSGE32 = 1069,
1083 BPOSGE32C_MMR3 = 1070,
1084 BPOSGE32_MM = 1071,
1085 BREAK = 1072,
1086 BREAK16_MM = 1073,
1087 BREAK16_MMR6 = 1074,
1088 BREAK_MM = 1075,
1089 BREAK_MMR6 = 1076,
1090 BSELI_B = 1077,
1091 BSEL_V = 1078,
1092 BSETI_B = 1079,
1093 BSETI_D = 1080,
1094 BSETI_H = 1081,
1095 BSETI_W = 1082,
1096 BSET_B = 1083,
1097 BSET_D = 1084,
1098 BSET_H = 1085,
1099 BSET_W = 1086,
1100 BZ_B = 1087,
1101 BZ_D = 1088,
1102 BZ_H = 1089,
1103 BZ_V = 1090,
1104 BZ_W = 1091,
1105 BeqzRxImm16 = 1092,
1106 BeqzRxImmX16 = 1093,
1107 Bimm16 = 1094,
1108 BimmX16 = 1095,
1109 BnezRxImm16 = 1096,
1110 BnezRxImmX16 = 1097,
1111 Break16 = 1098,
1112 Bteqz16 = 1099,
1113 BteqzX16 = 1100,
1114 Btnez16 = 1101,
1115 BtnezX16 = 1102,
1116 CACHE = 1103,
1117 CACHEE = 1104,
1118 CACHEE_MM = 1105,
1119 CACHE_MM = 1106,
1120 CACHE_MMR6 = 1107,
1121 CACHE_R6 = 1108,
1122 CEIL_L_D64 = 1109,
1123 CEIL_L_D_MMR6 = 1110,
1124 CEIL_L_S = 1111,
1125 CEIL_L_S_MMR6 = 1112,
1126 CEIL_W_D32 = 1113,
1127 CEIL_W_D64 = 1114,
1128 CEIL_W_D_MMR6 = 1115,
1129 CEIL_W_MM = 1116,
1130 CEIL_W_S = 1117,
1131 CEIL_W_S_MM = 1118,
1132 CEIL_W_S_MMR6 = 1119,
1133 CEQI_B = 1120,
1134 CEQI_D = 1121,
1135 CEQI_H = 1122,
1136 CEQI_W = 1123,
1137 CEQ_B = 1124,
1138 CEQ_D = 1125,
1139 CEQ_H = 1126,
1140 CEQ_W = 1127,
1141 CFC1 = 1128,
1142 CFC1_MM = 1129,
1143 CFC2_MM = 1130,
1144 CFCMSA = 1131,
1145 CINS = 1132,
1146 CINS32 = 1133,
1147 CINS64_32 = 1134,
1148 CINS_i32 = 1135,
1149 CLASS_D = 1136,
1150 CLASS_D_MMR6 = 1137,
1151 CLASS_S = 1138,
1152 CLASS_S_MMR6 = 1139,
1153 CLEI_S_B = 1140,
1154 CLEI_S_D = 1141,
1155 CLEI_S_H = 1142,
1156 CLEI_S_W = 1143,
1157 CLEI_U_B = 1144,
1158 CLEI_U_D = 1145,
1159 CLEI_U_H = 1146,
1160 CLEI_U_W = 1147,
1161 CLE_S_B = 1148,
1162 CLE_S_D = 1149,
1163 CLE_S_H = 1150,
1164 CLE_S_W = 1151,
1165 CLE_U_B = 1152,
1166 CLE_U_D = 1153,
1167 CLE_U_H = 1154,
1168 CLE_U_W = 1155,
1169 CLO = 1156,
1170 CLO_MM = 1157,
1171 CLO_MMR6 = 1158,
1172 CLO_R6 = 1159,
1173 CLTI_S_B = 1160,
1174 CLTI_S_D = 1161,
1175 CLTI_S_H = 1162,
1176 CLTI_S_W = 1163,
1177 CLTI_U_B = 1164,
1178 CLTI_U_D = 1165,
1179 CLTI_U_H = 1166,
1180 CLTI_U_W = 1167,
1181 CLT_S_B = 1168,
1182 CLT_S_D = 1169,
1183 CLT_S_H = 1170,
1184 CLT_S_W = 1171,
1185 CLT_U_B = 1172,
1186 CLT_U_D = 1173,
1187 CLT_U_H = 1174,
1188 CLT_U_W = 1175,
1189 CLZ = 1176,
1190 CLZ_MM = 1177,
1191 CLZ_MMR6 = 1178,
1192 CLZ_R6 = 1179,
1193 CMPGDU_EQ_QB = 1180,
1194 CMPGDU_EQ_QB_MMR2 = 1181,
1195 CMPGDU_LE_QB = 1182,
1196 CMPGDU_LE_QB_MMR2 = 1183,
1197 CMPGDU_LT_QB = 1184,
1198 CMPGDU_LT_QB_MMR2 = 1185,
1199 CMPGU_EQ_QB = 1186,
1200 CMPGU_EQ_QB_MM = 1187,
1201 CMPGU_LE_QB = 1188,
1202 CMPGU_LE_QB_MM = 1189,
1203 CMPGU_LT_QB = 1190,
1204 CMPGU_LT_QB_MM = 1191,
1205 CMPU_EQ_QB = 1192,
1206 CMPU_EQ_QB_MM = 1193,
1207 CMPU_LE_QB = 1194,
1208 CMPU_LE_QB_MM = 1195,
1209 CMPU_LT_QB = 1196,
1210 CMPU_LT_QB_MM = 1197,
1211 CMP_AF_D_MMR6 = 1198,
1212 CMP_AF_S_MMR6 = 1199,
1213 CMP_EQ_D = 1200,
1214 CMP_EQ_D_MMR6 = 1201,
1215 CMP_EQ_PH = 1202,
1216 CMP_EQ_PH_MM = 1203,
1217 CMP_EQ_S = 1204,
1218 CMP_EQ_S_MMR6 = 1205,
1219 CMP_F_D = 1206,
1220 CMP_F_S = 1207,
1221 CMP_LE_D = 1208,
1222 CMP_LE_D_MMR6 = 1209,
1223 CMP_LE_PH = 1210,
1224 CMP_LE_PH_MM = 1211,
1225 CMP_LE_S = 1212,
1226 CMP_LE_S_MMR6 = 1213,
1227 CMP_LT_D = 1214,
1228 CMP_LT_D_MMR6 = 1215,
1229 CMP_LT_PH = 1216,
1230 CMP_LT_PH_MM = 1217,
1231 CMP_LT_S = 1218,
1232 CMP_LT_S_MMR6 = 1219,
1233 CMP_SAF_D = 1220,
1234 CMP_SAF_D_MMR6 = 1221,
1235 CMP_SAF_S = 1222,
1236 CMP_SAF_S_MMR6 = 1223,
1237 CMP_SEQ_D = 1224,
1238 CMP_SEQ_D_MMR6 = 1225,
1239 CMP_SEQ_S = 1226,
1240 CMP_SEQ_S_MMR6 = 1227,
1241 CMP_SLE_D = 1228,
1242 CMP_SLE_D_MMR6 = 1229,
1243 CMP_SLE_S = 1230,
1244 CMP_SLE_S_MMR6 = 1231,
1245 CMP_SLT_D = 1232,
1246 CMP_SLT_D_MMR6 = 1233,
1247 CMP_SLT_S = 1234,
1248 CMP_SLT_S_MMR6 = 1235,
1249 CMP_SUEQ_D = 1236,
1250 CMP_SUEQ_D_MMR6 = 1237,
1251 CMP_SUEQ_S = 1238,
1252 CMP_SUEQ_S_MMR6 = 1239,
1253 CMP_SULE_D = 1240,
1254 CMP_SULE_D_MMR6 = 1241,
1255 CMP_SULE_S = 1242,
1256 CMP_SULE_S_MMR6 = 1243,
1257 CMP_SULT_D = 1244,
1258 CMP_SULT_D_MMR6 = 1245,
1259 CMP_SULT_S = 1246,
1260 CMP_SULT_S_MMR6 = 1247,
1261 CMP_SUN_D = 1248,
1262 CMP_SUN_D_MMR6 = 1249,
1263 CMP_SUN_S = 1250,
1264 CMP_SUN_S_MMR6 = 1251,
1265 CMP_UEQ_D = 1252,
1266 CMP_UEQ_D_MMR6 = 1253,
1267 CMP_UEQ_S = 1254,
1268 CMP_UEQ_S_MMR6 = 1255,
1269 CMP_ULE_D = 1256,
1270 CMP_ULE_D_MMR6 = 1257,
1271 CMP_ULE_S = 1258,
1272 CMP_ULE_S_MMR6 = 1259,
1273 CMP_ULT_D = 1260,
1274 CMP_ULT_D_MMR6 = 1261,
1275 CMP_ULT_S = 1262,
1276 CMP_ULT_S_MMR6 = 1263,
1277 CMP_UN_D = 1264,
1278 CMP_UN_D_MMR6 = 1265,
1279 CMP_UN_S = 1266,
1280 CMP_UN_S_MMR6 = 1267,
1281 COPY_S_B = 1268,
1282 COPY_S_D = 1269,
1283 COPY_S_H = 1270,
1284 COPY_S_W = 1271,
1285 COPY_U_B = 1272,
1286 COPY_U_H = 1273,
1287 COPY_U_W = 1274,
1288 CRC32B = 1275,
1289 CRC32CB = 1276,
1290 CRC32CD = 1277,
1291 CRC32CH = 1278,
1292 CRC32CW = 1279,
1293 CRC32D = 1280,
1294 CRC32H = 1281,
1295 CRC32W = 1282,
1296 CTC1 = 1283,
1297 CTC1_MM = 1284,
1298 CTC2_MM = 1285,
1299 CTCMSA = 1286,
1300 CVT_D32_S = 1287,
1301 CVT_D32_S_MM = 1288,
1302 CVT_D32_W = 1289,
1303 CVT_D32_W_MM = 1290,
1304 CVT_D64_L = 1291,
1305 CVT_D64_S = 1292,
1306 CVT_D64_S_MM = 1293,
1307 CVT_D64_W = 1294,
1308 CVT_D64_W_MM = 1295,
1309 CVT_D_L_MMR6 = 1296,
1310 CVT_L_D64 = 1297,
1311 CVT_L_D64_MM = 1298,
1312 CVT_L_D_MMR6 = 1299,
1313 CVT_L_S = 1300,
1314 CVT_L_S_MM = 1301,
1315 CVT_L_S_MMR6 = 1302,
1316 CVT_PS_PW64 = 1303,
1317 CVT_PS_S64 = 1304,
1318 CVT_PW_PS64 = 1305,
1319 CVT_S_D32 = 1306,
1320 CVT_S_D32_MM = 1307,
1321 CVT_S_D64 = 1308,
1322 CVT_S_D64_MM = 1309,
1323 CVT_S_L = 1310,
1324 CVT_S_L_MMR6 = 1311,
1325 CVT_S_PL64 = 1312,
1326 CVT_S_PU64 = 1313,
1327 CVT_S_W = 1314,
1328 CVT_S_W_MM = 1315,
1329 CVT_S_W_MMR6 = 1316,
1330 CVT_W_D32 = 1317,
1331 CVT_W_D32_MM = 1318,
1332 CVT_W_D64 = 1319,
1333 CVT_W_D64_MM = 1320,
1334 CVT_W_S = 1321,
1335 CVT_W_S_MM = 1322,
1336 CVT_W_S_MMR6 = 1323,
1337 C_EQ_D32 = 1324,
1338 C_EQ_D32_MM = 1325,
1339 C_EQ_D64 = 1326,
1340 C_EQ_D64_MM = 1327,
1341 C_EQ_S = 1328,
1342 C_EQ_S_MM = 1329,
1343 C_F_D32 = 1330,
1344 C_F_D32_MM = 1331,
1345 C_F_D64 = 1332,
1346 C_F_D64_MM = 1333,
1347 C_F_S = 1334,
1348 C_F_S_MM = 1335,
1349 C_LE_D32 = 1336,
1350 C_LE_D32_MM = 1337,
1351 C_LE_D64 = 1338,
1352 C_LE_D64_MM = 1339,
1353 C_LE_S = 1340,
1354 C_LE_S_MM = 1341,
1355 C_LT_D32 = 1342,
1356 C_LT_D32_MM = 1343,
1357 C_LT_D64 = 1344,
1358 C_LT_D64_MM = 1345,
1359 C_LT_S = 1346,
1360 C_LT_S_MM = 1347,
1361 C_NGE_D32 = 1348,
1362 C_NGE_D32_MM = 1349,
1363 C_NGE_D64 = 1350,
1364 C_NGE_D64_MM = 1351,
1365 C_NGE_S = 1352,
1366 C_NGE_S_MM = 1353,
1367 C_NGLE_D32 = 1354,
1368 C_NGLE_D32_MM = 1355,
1369 C_NGLE_D64 = 1356,
1370 C_NGLE_D64_MM = 1357,
1371 C_NGLE_S = 1358,
1372 C_NGLE_S_MM = 1359,
1373 C_NGL_D32 = 1360,
1374 C_NGL_D32_MM = 1361,
1375 C_NGL_D64 = 1362,
1376 C_NGL_D64_MM = 1363,
1377 C_NGL_S = 1364,
1378 C_NGL_S_MM = 1365,
1379 C_NGT_D32 = 1366,
1380 C_NGT_D32_MM = 1367,
1381 C_NGT_D64 = 1368,
1382 C_NGT_D64_MM = 1369,
1383 C_NGT_S = 1370,
1384 C_NGT_S_MM = 1371,
1385 C_OLE_D32 = 1372,
1386 C_OLE_D32_MM = 1373,
1387 C_OLE_D64 = 1374,
1388 C_OLE_D64_MM = 1375,
1389 C_OLE_S = 1376,
1390 C_OLE_S_MM = 1377,
1391 C_OLT_D32 = 1378,
1392 C_OLT_D32_MM = 1379,
1393 C_OLT_D64 = 1380,
1394 C_OLT_D64_MM = 1381,
1395 C_OLT_S = 1382,
1396 C_OLT_S_MM = 1383,
1397 C_SEQ_D32 = 1384,
1398 C_SEQ_D32_MM = 1385,
1399 C_SEQ_D64 = 1386,
1400 C_SEQ_D64_MM = 1387,
1401 C_SEQ_S = 1388,
1402 C_SEQ_S_MM = 1389,
1403 C_SF_D32 = 1390,
1404 C_SF_D32_MM = 1391,
1405 C_SF_D64 = 1392,
1406 C_SF_D64_MM = 1393,
1407 C_SF_S = 1394,
1408 C_SF_S_MM = 1395,
1409 C_UEQ_D32 = 1396,
1410 C_UEQ_D32_MM = 1397,
1411 C_UEQ_D64 = 1398,
1412 C_UEQ_D64_MM = 1399,
1413 C_UEQ_S = 1400,
1414 C_UEQ_S_MM = 1401,
1415 C_ULE_D32 = 1402,
1416 C_ULE_D32_MM = 1403,
1417 C_ULE_D64 = 1404,
1418 C_ULE_D64_MM = 1405,
1419 C_ULE_S = 1406,
1420 C_ULE_S_MM = 1407,
1421 C_ULT_D32 = 1408,
1422 C_ULT_D32_MM = 1409,
1423 C_ULT_D64 = 1410,
1424 C_ULT_D64_MM = 1411,
1425 C_ULT_S = 1412,
1426 C_ULT_S_MM = 1413,
1427 C_UN_D32 = 1414,
1428 C_UN_D32_MM = 1415,
1429 C_UN_D64 = 1416,
1430 C_UN_D64_MM = 1417,
1431 C_UN_S = 1418,
1432 C_UN_S_MM = 1419,
1433 CmpRxRy16 = 1420,
1434 CmpiRxImm16 = 1421,
1435 CmpiRxImmX16 = 1422,
1436 DADD = 1423,
1437 DADDi = 1424,
1438 DADDiu = 1425,
1439 DADDu = 1426,
1440 DAHI = 1427,
1441 DALIGN = 1428,
1442 DATI = 1429,
1443 DAUI = 1430,
1444 DBITSWAP = 1431,
1445 DCLO = 1432,
1446 DCLO_R6 = 1433,
1447 DCLZ = 1434,
1448 DCLZ_R6 = 1435,
1449 DDIV = 1436,
1450 DDIVU = 1437,
1451 DERET = 1438,
1452 DERET_MM = 1439,
1453 DERET_MMR6 = 1440,
1454 DEXT = 1441,
1455 DEXT64_32 = 1442,
1456 DEXTM = 1443,
1457 DEXTU = 1444,
1458 DI = 1445,
1459 DINS = 1446,
1460 DINSM = 1447,
1461 DINSU = 1448,
1462 DIV = 1449,
1463 DIVU = 1450,
1464 DIVU_MMR6 = 1451,
1465 DIV_MMR6 = 1452,
1466 DIV_S_B = 1453,
1467 DIV_S_D = 1454,
1468 DIV_S_H = 1455,
1469 DIV_S_W = 1456,
1470 DIV_U_B = 1457,
1471 DIV_U_D = 1458,
1472 DIV_U_H = 1459,
1473 DIV_U_W = 1460,
1474 DI_MM = 1461,
1475 DI_MMR6 = 1462,
1476 DLSA = 1463,
1477 DLSA_R6 = 1464,
1478 DMFC0 = 1465,
1479 DMFC1 = 1466,
1480 DMFC2 = 1467,
1481 DMFC2_OCTEON = 1468,
1482 DMFGC0 = 1469,
1483 DMOD = 1470,
1484 DMODU = 1471,
1485 DMT = 1472,
1486 DMTC0 = 1473,
1487 DMTC1 = 1474,
1488 DMTC2 = 1475,
1489 DMTC2_OCTEON = 1476,
1490 DMTGC0 = 1477,
1491 DMUH = 1478,
1492 DMUHU = 1479,
1493 DMUL = 1480,
1494 DMULT = 1481,
1495 DMULTu = 1482,
1496 DMULU = 1483,
1497 DMUL_R6 = 1484,
1498 DOTP_S_D = 1485,
1499 DOTP_S_H = 1486,
1500 DOTP_S_W = 1487,
1501 DOTP_U_D = 1488,
1502 DOTP_U_H = 1489,
1503 DOTP_U_W = 1490,
1504 DPADD_S_D = 1491,
1505 DPADD_S_H = 1492,
1506 DPADD_S_W = 1493,
1507 DPADD_U_D = 1494,
1508 DPADD_U_H = 1495,
1509 DPADD_U_W = 1496,
1510 DPAQX_SA_W_PH = 1497,
1511 DPAQX_SA_W_PH_MMR2 = 1498,
1512 DPAQX_S_W_PH = 1499,
1513 DPAQX_S_W_PH_MMR2 = 1500,
1514 DPAQ_SA_L_W = 1501,
1515 DPAQ_SA_L_W_MM = 1502,
1516 DPAQ_S_W_PH = 1503,
1517 DPAQ_S_W_PH_MM = 1504,
1518 DPAU_H_QBL = 1505,
1519 DPAU_H_QBL_MM = 1506,
1520 DPAU_H_QBR = 1507,
1521 DPAU_H_QBR_MM = 1508,
1522 DPAX_W_PH = 1509,
1523 DPAX_W_PH_MMR2 = 1510,
1524 DPA_W_PH = 1511,
1525 DPA_W_PH_MMR2 = 1512,
1526 DPOP = 1513,
1527 DPSQX_SA_W_PH = 1514,
1528 DPSQX_SA_W_PH_MMR2 = 1515,
1529 DPSQX_S_W_PH = 1516,
1530 DPSQX_S_W_PH_MMR2 = 1517,
1531 DPSQ_SA_L_W = 1518,
1532 DPSQ_SA_L_W_MM = 1519,
1533 DPSQ_S_W_PH = 1520,
1534 DPSQ_S_W_PH_MM = 1521,
1535 DPSUB_S_D = 1522,
1536 DPSUB_S_H = 1523,
1537 DPSUB_S_W = 1524,
1538 DPSUB_U_D = 1525,
1539 DPSUB_U_H = 1526,
1540 DPSUB_U_W = 1527,
1541 DPSU_H_QBL = 1528,
1542 DPSU_H_QBL_MM = 1529,
1543 DPSU_H_QBR = 1530,
1544 DPSU_H_QBR_MM = 1531,
1545 DPSX_W_PH = 1532,
1546 DPSX_W_PH_MMR2 = 1533,
1547 DPS_W_PH = 1534,
1548 DPS_W_PH_MMR2 = 1535,
1549 DROTR = 1536,
1550 DROTR32 = 1537,
1551 DROTRV = 1538,
1552 DSBH = 1539,
1553 DSDIV = 1540,
1554 DSHD = 1541,
1555 DSLL = 1542,
1556 DSLL32 = 1543,
1557 DSLL64_32 = 1544,
1558 DSLLV = 1545,
1559 DSRA = 1546,
1560 DSRA32 = 1547,
1561 DSRAV = 1548,
1562 DSRL = 1549,
1563 DSRL32 = 1550,
1564 DSRLV = 1551,
1565 DSUB = 1552,
1566 DSUBu = 1553,
1567 DUDIV = 1554,
1568 DVP = 1555,
1569 DVPE = 1556,
1570 DVP_MMR6 = 1557,
1571 DivRxRy16 = 1558,
1572 DivuRxRy16 = 1559,
1573 EHB = 1560,
1574 EHB_MM = 1561,
1575 EHB_MMR6 = 1562,
1576 EI = 1563,
1577 EI_MM = 1564,
1578 EI_MMR6 = 1565,
1579 EMT = 1566,
1580 ERET = 1567,
1581 ERETNC = 1568,
1582 ERETNC_MMR6 = 1569,
1583 ERET_MM = 1570,
1584 ERET_MMR6 = 1571,
1585 EVP = 1572,
1586 EVPE = 1573,
1587 EVP_MMR6 = 1574,
1588 EXT = 1575,
1589 EXTP = 1576,
1590 EXTPDP = 1577,
1591 EXTPDPV = 1578,
1592 EXTPDPV_MM = 1579,
1593 EXTPDP_MM = 1580,
1594 EXTPV = 1581,
1595 EXTPV_MM = 1582,
1596 EXTP_MM = 1583,
1597 EXTRV_RS_W = 1584,
1598 EXTRV_RS_W_MM = 1585,
1599 EXTRV_R_W = 1586,
1600 EXTRV_R_W_MM = 1587,
1601 EXTRV_S_H = 1588,
1602 EXTRV_S_H_MM = 1589,
1603 EXTRV_W = 1590,
1604 EXTRV_W_MM = 1591,
1605 EXTR_RS_W = 1592,
1606 EXTR_RS_W_MM = 1593,
1607 EXTR_R_W = 1594,
1608 EXTR_R_W_MM = 1595,
1609 EXTR_S_H = 1596,
1610 EXTR_S_H_MM = 1597,
1611 EXTR_W = 1598,
1612 EXTR_W_MM = 1599,
1613 EXTS = 1600,
1614 EXTS32 = 1601,
1615 EXT_MM = 1602,
1616 EXT_MMR6 = 1603,
1617 FABS_D32 = 1604,
1618 FABS_D32_MM = 1605,
1619 FABS_D64 = 1606,
1620 FABS_D64_MM = 1607,
1621 FABS_S = 1608,
1622 FABS_S_MM = 1609,
1623 FADD_D = 1610,
1624 FADD_D32 = 1611,
1625 FADD_D32_MM = 1612,
1626 FADD_D64 = 1613,
1627 FADD_D64_MM = 1614,
1628 FADD_PS64 = 1615,
1629 FADD_S = 1616,
1630 FADD_S_MM = 1617,
1631 FADD_S_MMR6 = 1618,
1632 FADD_W = 1619,
1633 FCAF_D = 1620,
1634 FCAF_W = 1621,
1635 FCEQ_D = 1622,
1636 FCEQ_W = 1623,
1637 FCLASS_D = 1624,
1638 FCLASS_W = 1625,
1639 FCLE_D = 1626,
1640 FCLE_W = 1627,
1641 FCLT_D = 1628,
1642 FCLT_W = 1629,
1643 FCMP_D32 = 1630,
1644 FCMP_D32_MM = 1631,
1645 FCMP_D64 = 1632,
1646 FCMP_S32 = 1633,
1647 FCMP_S32_MM = 1634,
1648 FCNE_D = 1635,
1649 FCNE_W = 1636,
1650 FCOR_D = 1637,
1651 FCOR_W = 1638,
1652 FCUEQ_D = 1639,
1653 FCUEQ_W = 1640,
1654 FCULE_D = 1641,
1655 FCULE_W = 1642,
1656 FCULT_D = 1643,
1657 FCULT_W = 1644,
1658 FCUNE_D = 1645,
1659 FCUNE_W = 1646,
1660 FCUN_D = 1647,
1661 FCUN_W = 1648,
1662 FDIV_D = 1649,
1663 FDIV_D32 = 1650,
1664 FDIV_D32_MM = 1651,
1665 FDIV_D64 = 1652,
1666 FDIV_D64_MM = 1653,
1667 FDIV_S = 1654,
1668 FDIV_S_MM = 1655,
1669 FDIV_S_MMR6 = 1656,
1670 FDIV_W = 1657,
1671 FEXDO_H = 1658,
1672 FEXDO_W = 1659,
1673 FEXP2_D = 1660,
1674 FEXP2_W = 1661,
1675 FEXUPL_D = 1662,
1676 FEXUPL_W = 1663,
1677 FEXUPR_D = 1664,
1678 FEXUPR_W = 1665,
1679 FFINT_S_D = 1666,
1680 FFINT_S_W = 1667,
1681 FFINT_U_D = 1668,
1682 FFINT_U_W = 1669,
1683 FFQL_D = 1670,
1684 FFQL_W = 1671,
1685 FFQR_D = 1672,
1686 FFQR_W = 1673,
1687 FILL_B = 1674,
1688 FILL_D = 1675,
1689 FILL_H = 1676,
1690 FILL_W = 1677,
1691 FLOG2_D = 1678,
1692 FLOG2_W = 1679,
1693 FLOOR_L_D64 = 1680,
1694 FLOOR_L_D_MMR6 = 1681,
1695 FLOOR_L_S = 1682,
1696 FLOOR_L_S_MMR6 = 1683,
1697 FLOOR_W_D32 = 1684,
1698 FLOOR_W_D64 = 1685,
1699 FLOOR_W_D_MMR6 = 1686,
1700 FLOOR_W_MM = 1687,
1701 FLOOR_W_S = 1688,
1702 FLOOR_W_S_MM = 1689,
1703 FLOOR_W_S_MMR6 = 1690,
1704 FMADD_D = 1691,
1705 FMADD_W = 1692,
1706 FMAX_A_D = 1693,
1707 FMAX_A_W = 1694,
1708 FMAX_D = 1695,
1709 FMAX_W = 1696,
1710 FMIN_A_D = 1697,
1711 FMIN_A_W = 1698,
1712 FMIN_D = 1699,
1713 FMIN_W = 1700,
1714 FMOV_D32 = 1701,
1715 FMOV_D32_MM = 1702,
1716 FMOV_D64 = 1703,
1717 FMOV_D64_MM = 1704,
1718 FMOV_D_MMR6 = 1705,
1719 FMOV_S = 1706,
1720 FMOV_S_MM = 1707,
1721 FMOV_S_MMR6 = 1708,
1722 FMSUB_D = 1709,
1723 FMSUB_W = 1710,
1724 FMUL_D = 1711,
1725 FMUL_D32 = 1712,
1726 FMUL_D32_MM = 1713,
1727 FMUL_D64 = 1714,
1728 FMUL_D64_MM = 1715,
1729 FMUL_PS64 = 1716,
1730 FMUL_S = 1717,
1731 FMUL_S_MM = 1718,
1732 FMUL_S_MMR6 = 1719,
1733 FMUL_W = 1720,
1734 FNEG_D32 = 1721,
1735 FNEG_D32_MM = 1722,
1736 FNEG_D64 = 1723,
1737 FNEG_D64_MM = 1724,
1738 FNEG_S = 1725,
1739 FNEG_S_MM = 1726,
1740 FNEG_S_MMR6 = 1727,
1741 FORK = 1728,
1742 FRCP_D = 1729,
1743 FRCP_W = 1730,
1744 FRINT_D = 1731,
1745 FRINT_W = 1732,
1746 FRSQRT_D = 1733,
1747 FRSQRT_W = 1734,
1748 FSAF_D = 1735,
1749 FSAF_W = 1736,
1750 FSEQ_D = 1737,
1751 FSEQ_W = 1738,
1752 FSLE_D = 1739,
1753 FSLE_W = 1740,
1754 FSLT_D = 1741,
1755 FSLT_W = 1742,
1756 FSNE_D = 1743,
1757 FSNE_W = 1744,
1758 FSOR_D = 1745,
1759 FSOR_W = 1746,
1760 FSQRT_D = 1747,
1761 FSQRT_D32 = 1748,
1762 FSQRT_D32_MM = 1749,
1763 FSQRT_D64 = 1750,
1764 FSQRT_D64_MM = 1751,
1765 FSQRT_S = 1752,
1766 FSQRT_S_MM = 1753,
1767 FSQRT_W = 1754,
1768 FSUB_D = 1755,
1769 FSUB_D32 = 1756,
1770 FSUB_D32_MM = 1757,
1771 FSUB_D64 = 1758,
1772 FSUB_D64_MM = 1759,
1773 FSUB_PS64 = 1760,
1774 FSUB_S = 1761,
1775 FSUB_S_MM = 1762,
1776 FSUB_S_MMR6 = 1763,
1777 FSUB_W = 1764,
1778 FSUEQ_D = 1765,
1779 FSUEQ_W = 1766,
1780 FSULE_D = 1767,
1781 FSULE_W = 1768,
1782 FSULT_D = 1769,
1783 FSULT_W = 1770,
1784 FSUNE_D = 1771,
1785 FSUNE_W = 1772,
1786 FSUN_D = 1773,
1787 FSUN_W = 1774,
1788 FTINT_S_D = 1775,
1789 FTINT_S_W = 1776,
1790 FTINT_U_D = 1777,
1791 FTINT_U_W = 1778,
1792 FTQ_H = 1779,
1793 FTQ_W = 1780,
1794 FTRUNC_S_D = 1781,
1795 FTRUNC_S_W = 1782,
1796 FTRUNC_U_D = 1783,
1797 FTRUNC_U_W = 1784,
1798 GINVI = 1785,
1799 GINVI_MMR6 = 1786,
1800 GINVT = 1787,
1801 GINVT_MMR6 = 1788,
1802 HADD_S_D = 1789,
1803 HADD_S_H = 1790,
1804 HADD_S_W = 1791,
1805 HADD_U_D = 1792,
1806 HADD_U_H = 1793,
1807 HADD_U_W = 1794,
1808 HSUB_S_D = 1795,
1809 HSUB_S_H = 1796,
1810 HSUB_S_W = 1797,
1811 HSUB_U_D = 1798,
1812 HSUB_U_H = 1799,
1813 HSUB_U_W = 1800,
1814 HYPCALL = 1801,
1815 HYPCALL_MM = 1802,
1816 ILVEV_B = 1803,
1817 ILVEV_D = 1804,
1818 ILVEV_H = 1805,
1819 ILVEV_W = 1806,
1820 ILVL_B = 1807,
1821 ILVL_D = 1808,
1822 ILVL_H = 1809,
1823 ILVL_W = 1810,
1824 ILVOD_B = 1811,
1825 ILVOD_D = 1812,
1826 ILVOD_H = 1813,
1827 ILVOD_W = 1814,
1828 ILVR_B = 1815,
1829 ILVR_D = 1816,
1830 ILVR_H = 1817,
1831 ILVR_W = 1818,
1832 INS = 1819,
1833 INSERT_B = 1820,
1834 INSERT_D = 1821,
1835 INSERT_H = 1822,
1836 INSERT_W = 1823,
1837 INSV = 1824,
1838 INSVE_B = 1825,
1839 INSVE_D = 1826,
1840 INSVE_H = 1827,
1841 INSVE_W = 1828,
1842 INSV_MM = 1829,
1843 INS_MM = 1830,
1844 INS_MMR6 = 1831,
1845 J = 1832,
1846 JAL = 1833,
1847 JALR = 1834,
1848 JALR16_MM = 1835,
1849 JALR64 = 1836,
1850 JALRC16_MMR6 = 1837,
1851 JALRC_HB_MMR6 = 1838,
1852 JALRC_MMR6 = 1839,
1853 JALRS16_MM = 1840,
1854 JALRS_MM = 1841,
1855 JALR_HB = 1842,
1856 JALR_HB64 = 1843,
1857 JALR_MM = 1844,
1858 JALS_MM = 1845,
1859 JALX = 1846,
1860 JALX_MM = 1847,
1861 JAL_MM = 1848,
1862 JIALC = 1849,
1863 JIALC64 = 1850,
1864 JIALC_MMR6 = 1851,
1865 JIC = 1852,
1866 JIC64 = 1853,
1867 JIC_MMR6 = 1854,
1868 JR = 1855,
1869 JR16_MM = 1856,
1870 JR64 = 1857,
1871 JRADDIUSP = 1858,
1872 JRC16_MM = 1859,
1873 JRC16_MMR6 = 1860,
1874 JRCADDIUSP_MMR6 = 1861,
1875 JR_HB = 1862,
1876 JR_HB64 = 1863,
1877 JR_HB64_R6 = 1864,
1878 JR_HB_R6 = 1865,
1879 JR_MM = 1866,
1880 J_MM = 1867,
1881 Jal16 = 1868,
1882 JalB16 = 1869,
1883 JrRa16 = 1870,
1884 JrcRa16 = 1871,
1885 JrcRx16 = 1872,
1886 JumpLinkReg16 = 1873,
1887 LB = 1874,
1888 LB64 = 1875,
1889 LBE = 1876,
1890 LBE_MM = 1877,
1891 LBU16_MM = 1878,
1892 LBUX = 1879,
1893 LBUX_MM = 1880,
1894 LBU_MMR6 = 1881,
1895 LB_MM = 1882,
1896 LB_MMR6 = 1883,
1897 LBu = 1884,
1898 LBu64 = 1885,
1899 LBuE = 1886,
1900 LBuE_MM = 1887,
1901 LBu_MM = 1888,
1902 LD = 1889,
1903 LDC1 = 1890,
1904 LDC164 = 1891,
1905 LDC1_D64_MMR6 = 1892,
1906 LDC1_MM_D32 = 1893,
1907 LDC1_MM_D64 = 1894,
1908 LDC2 = 1895,
1909 LDC2_MMR6 = 1896,
1910 LDC2_R6 = 1897,
1911 LDC3 = 1898,
1912 LDI_B = 1899,
1913 LDI_D = 1900,
1914 LDI_H = 1901,
1915 LDI_W = 1902,
1916 LDL = 1903,
1917 LDPC = 1904,
1918 LDR = 1905,
1919 LDXC1 = 1906,
1920 LDXC164 = 1907,
1921 LD_B = 1908,
1922 LD_D = 1909,
1923 LD_H = 1910,
1924 LD_W = 1911,
1925 LEA_ADDiu = 1912,
1926 LEA_ADDiu64 = 1913,
1927 LEA_ADDiu_MM = 1914,
1928 LH = 1915,
1929 LH64 = 1916,
1930 LHE = 1917,
1931 LHE_MM = 1918,
1932 LHU16_MM = 1919,
1933 LHX = 1920,
1934 LHX_MM = 1921,
1935 LH_MM = 1922,
1936 LHu = 1923,
1937 LHu64 = 1924,
1938 LHuE = 1925,
1939 LHuE_MM = 1926,
1940 LHu_MM = 1927,
1941 LI16_MM = 1928,
1942 LI16_MMR6 = 1929,
1943 LL = 1930,
1944 LL64 = 1931,
1945 LL64_R6 = 1932,
1946 LLD = 1933,
1947 LLD_R6 = 1934,
1948 LLE = 1935,
1949 LLE_MM = 1936,
1950 LL_MM = 1937,
1951 LL_MMR6 = 1938,
1952 LL_R6 = 1939,
1953 LSA = 1940,
1954 LSA_MMR6 = 1941,
1955 LSA_R6 = 1942,
1956 LUI_MMR6 = 1943,
1957 LUXC1 = 1944,
1958 LUXC164 = 1945,
1959 LUXC1_MM = 1946,
1960 LUi = 1947,
1961 LUi64 = 1948,
1962 LUi_MM = 1949,
1963 LW = 1950,
1964 LW16_MM = 1951,
1965 LW64 = 1952,
1966 LWC1 = 1953,
1967 LWC1_MM = 1954,
1968 LWC2 = 1955,
1969 LWC2_MMR6 = 1956,
1970 LWC2_R6 = 1957,
1971 LWC3 = 1958,
1972 LWDSP = 1959,
1973 LWDSP_MM = 1960,
1974 LWE = 1961,
1975 LWE_MM = 1962,
1976 LWGP_MM = 1963,
1977 LWL = 1964,
1978 LWL64 = 1965,
1979 LWLE = 1966,
1980 LWLE_MM = 1967,
1981 LWL_MM = 1968,
1982 LWM16_MM = 1969,
1983 LWM16_MMR6 = 1970,
1984 LWM32_MM = 1971,
1985 LWPC = 1972,
1986 LWPC_MMR6 = 1973,
1987 LWP_MM = 1974,
1988 LWR = 1975,
1989 LWR64 = 1976,
1990 LWRE = 1977,
1991 LWRE_MM = 1978,
1992 LWR_MM = 1979,
1993 LWSP_MM = 1980,
1994 LWUPC = 1981,
1995 LWU_MM = 1982,
1996 LWX = 1983,
1997 LWXC1 = 1984,
1998 LWXC1_MM = 1985,
1999 LWXS_MM = 1986,
2000 LWX_MM = 1987,
2001 LW_MM = 1988,
2002 LW_MMR6 = 1989,
2003 LWu = 1990,
2004 LbRxRyOffMemX16 = 1991,
2005 LbuRxRyOffMemX16 = 1992,
2006 LhRxRyOffMemX16 = 1993,
2007 LhuRxRyOffMemX16 = 1994,
2008 LiRxImm16 = 1995,
2009 LiRxImmAlignX16 = 1996,
2010 LiRxImmX16 = 1997,
2011 LwRxPcTcp16 = 1998,
2012 LwRxPcTcpX16 = 1999,
2013 LwRxRyOffMemX16 = 2000,
2014 LwRxSpImmX16 = 2001,
2015 MADD = 2002,
2016 MADDF_D = 2003,
2017 MADDF_D_MMR6 = 2004,
2018 MADDF_S = 2005,
2019 MADDF_S_MMR6 = 2006,
2020 MADDR_Q_H = 2007,
2021 MADDR_Q_W = 2008,
2022 MADDU = 2009,
2023 MADDU_DSP = 2010,
2024 MADDU_DSP_MM = 2011,
2025 MADDU_MM = 2012,
2026 MADDV_B = 2013,
2027 MADDV_D = 2014,
2028 MADDV_H = 2015,
2029 MADDV_W = 2016,
2030 MADD_D32 = 2017,
2031 MADD_D32_MM = 2018,
2032 MADD_D64 = 2019,
2033 MADD_DSP = 2020,
2034 MADD_DSP_MM = 2021,
2035 MADD_MM = 2022,
2036 MADD_Q_H = 2023,
2037 MADD_Q_W = 2024,
2038 MADD_S = 2025,
2039 MADD_S_MM = 2026,
2040 MAQ_SA_W_PHL = 2027,
2041 MAQ_SA_W_PHL_MM = 2028,
2042 MAQ_SA_W_PHR = 2029,
2043 MAQ_SA_W_PHR_MM = 2030,
2044 MAQ_S_W_PHL = 2031,
2045 MAQ_S_W_PHL_MM = 2032,
2046 MAQ_S_W_PHR = 2033,
2047 MAQ_S_W_PHR_MM = 2034,
2048 MAXA_D = 2035,
2049 MAXA_D_MMR6 = 2036,
2050 MAXA_S = 2037,
2051 MAXA_S_MMR6 = 2038,
2052 MAXI_S_B = 2039,
2053 MAXI_S_D = 2040,
2054 MAXI_S_H = 2041,
2055 MAXI_S_W = 2042,
2056 MAXI_U_B = 2043,
2057 MAXI_U_D = 2044,
2058 MAXI_U_H = 2045,
2059 MAXI_U_W = 2046,
2060 MAX_A_B = 2047,
2061 MAX_A_D = 2048,
2062 MAX_A_H = 2049,
2063 MAX_A_W = 2050,
2064 MAX_D = 2051,
2065 MAX_D_MMR6 = 2052,
2066 MAX_S = 2053,
2067 MAX_S_B = 2054,
2068 MAX_S_D = 2055,
2069 MAX_S_H = 2056,
2070 MAX_S_MMR6 = 2057,
2071 MAX_S_W = 2058,
2072 MAX_U_B = 2059,
2073 MAX_U_D = 2060,
2074 MAX_U_H = 2061,
2075 MAX_U_W = 2062,
2076 MFC0 = 2063,
2077 MFC0_MMR6 = 2064,
2078 MFC1 = 2065,
2079 MFC1_D64 = 2066,
2080 MFC1_MM = 2067,
2081 MFC1_MMR6 = 2068,
2082 MFC2 = 2069,
2083 MFC2_MMR6 = 2070,
2084 MFGC0 = 2071,
2085 MFGC0_MM = 2072,
2086 MFHC0_MMR6 = 2073,
2087 MFHC1_D32 = 2074,
2088 MFHC1_D32_MM = 2075,
2089 MFHC1_D64 = 2076,
2090 MFHC1_D64_MM = 2077,
2091 MFHC2_MMR6 = 2078,
2092 MFHGC0 = 2079,
2093 MFHGC0_MM = 2080,
2094 MFHI = 2081,
2095 MFHI16_MM = 2082,
2096 MFHI64 = 2083,
2097 MFHI_DSP = 2084,
2098 MFHI_DSP_MM = 2085,
2099 MFHI_MM = 2086,
2100 MFLO = 2087,
2101 MFLO16_MM = 2088,
2102 MFLO64 = 2089,
2103 MFLO_DSP = 2090,
2104 MFLO_DSP_MM = 2091,
2105 MFLO_MM = 2092,
2106 MFTR = 2093,
2107 MINA_D = 2094,
2108 MINA_D_MMR6 = 2095,
2109 MINA_S = 2096,
2110 MINA_S_MMR6 = 2097,
2111 MINI_S_B = 2098,
2112 MINI_S_D = 2099,
2113 MINI_S_H = 2100,
2114 MINI_S_W = 2101,
2115 MINI_U_B = 2102,
2116 MINI_U_D = 2103,
2117 MINI_U_H = 2104,
2118 MINI_U_W = 2105,
2119 MIN_A_B = 2106,
2120 MIN_A_D = 2107,
2121 MIN_A_H = 2108,
2122 MIN_A_W = 2109,
2123 MIN_D = 2110,
2124 MIN_D_MMR6 = 2111,
2125 MIN_S = 2112,
2126 MIN_S_B = 2113,
2127 MIN_S_D = 2114,
2128 MIN_S_H = 2115,
2129 MIN_S_MMR6 = 2116,
2130 MIN_S_W = 2117,
2131 MIN_U_B = 2118,
2132 MIN_U_D = 2119,
2133 MIN_U_H = 2120,
2134 MIN_U_W = 2121,
2135 MOD = 2122,
2136 MODSUB = 2123,
2137 MODSUB_MM = 2124,
2138 MODU = 2125,
2139 MODU_MMR6 = 2126,
2140 MOD_MMR6 = 2127,
2141 MOD_S_B = 2128,
2142 MOD_S_D = 2129,
2143 MOD_S_H = 2130,
2144 MOD_S_W = 2131,
2145 MOD_U_B = 2132,
2146 MOD_U_D = 2133,
2147 MOD_U_H = 2134,
2148 MOD_U_W = 2135,
2149 MOVE16_MM = 2136,
2150 MOVE16_MMR6 = 2137,
2151 MOVEP_MM = 2138,
2152 MOVEP_MMR6 = 2139,
2153 MOVE_V = 2140,
2154 MOVF_D32 = 2141,
2155 MOVF_D32_MM = 2142,
2156 MOVF_D64 = 2143,
2157 MOVF_I = 2144,
2158 MOVF_I64 = 2145,
2159 MOVF_I_MM = 2146,
2160 MOVF_S = 2147,
2161 MOVF_S_MM = 2148,
2162 MOVN_I64_D64 = 2149,
2163 MOVN_I64_I = 2150,
2164 MOVN_I64_I64 = 2151,
2165 MOVN_I64_S = 2152,
2166 MOVN_I_D32 = 2153,
2167 MOVN_I_D32_MM = 2154,
2168 MOVN_I_D64 = 2155,
2169 MOVN_I_I = 2156,
2170 MOVN_I_I64 = 2157,
2171 MOVN_I_MM = 2158,
2172 MOVN_I_S = 2159,
2173 MOVN_I_S_MM = 2160,
2174 MOVT_D32 = 2161,
2175 MOVT_D32_MM = 2162,
2176 MOVT_D64 = 2163,
2177 MOVT_I = 2164,
2178 MOVT_I64 = 2165,
2179 MOVT_I_MM = 2166,
2180 MOVT_S = 2167,
2181 MOVT_S_MM = 2168,
2182 MOVZ_I64_D64 = 2169,
2183 MOVZ_I64_I = 2170,
2184 MOVZ_I64_I64 = 2171,
2185 MOVZ_I64_S = 2172,
2186 MOVZ_I_D32 = 2173,
2187 MOVZ_I_D32_MM = 2174,
2188 MOVZ_I_D64 = 2175,
2189 MOVZ_I_I = 2176,
2190 MOVZ_I_I64 = 2177,
2191 MOVZ_I_MM = 2178,
2192 MOVZ_I_S = 2179,
2193 MOVZ_I_S_MM = 2180,
2194 MSUB = 2181,
2195 MSUBF_D = 2182,
2196 MSUBF_D_MMR6 = 2183,
2197 MSUBF_S = 2184,
2198 MSUBF_S_MMR6 = 2185,
2199 MSUBR_Q_H = 2186,
2200 MSUBR_Q_W = 2187,
2201 MSUBU = 2188,
2202 MSUBU_DSP = 2189,
2203 MSUBU_DSP_MM = 2190,
2204 MSUBU_MM = 2191,
2205 MSUBV_B = 2192,
2206 MSUBV_D = 2193,
2207 MSUBV_H = 2194,
2208 MSUBV_W = 2195,
2209 MSUB_D32 = 2196,
2210 MSUB_D32_MM = 2197,
2211 MSUB_D64 = 2198,
2212 MSUB_DSP = 2199,
2213 MSUB_DSP_MM = 2200,
2214 MSUB_MM = 2201,
2215 MSUB_Q_H = 2202,
2216 MSUB_Q_W = 2203,
2217 MSUB_S = 2204,
2218 MSUB_S_MM = 2205,
2219 MTC0 = 2206,
2220 MTC0_MMR6 = 2207,
2221 MTC1 = 2208,
2222 MTC1_D64 = 2209,
2223 MTC1_D64_MM = 2210,
2224 MTC1_MM = 2211,
2225 MTC1_MMR6 = 2212,
2226 MTC2 = 2213,
2227 MTC2_MMR6 = 2214,
2228 MTGC0 = 2215,
2229 MTGC0_MM = 2216,
2230 MTHC0_MMR6 = 2217,
2231 MTHC1_D32 = 2218,
2232 MTHC1_D32_MM = 2219,
2233 MTHC1_D64 = 2220,
2234 MTHC1_D64_MM = 2221,
2235 MTHC2_MMR6 = 2222,
2236 MTHGC0 = 2223,
2237 MTHGC0_MM = 2224,
2238 MTHI = 2225,
2239 MTHI64 = 2226,
2240 MTHI_DSP = 2227,
2241 MTHI_DSP_MM = 2228,
2242 MTHI_MM = 2229,
2243 MTHLIP = 2230,
2244 MTHLIP_MM = 2231,
2245 MTLO = 2232,
2246 MTLO64 = 2233,
2247 MTLO_DSP = 2234,
2248 MTLO_DSP_MM = 2235,
2249 MTLO_MM = 2236,
2250 MTM0 = 2237,
2251 MTM1 = 2238,
2252 MTM2 = 2239,
2253 MTP0 = 2240,
2254 MTP1 = 2241,
2255 MTP2 = 2242,
2256 MTTR = 2243,
2257 MUH = 2244,
2258 MUHU = 2245,
2259 MUHU_MMR6 = 2246,
2260 MUH_MMR6 = 2247,
2261 MUL = 2248,
2262 MULEQ_S_W_PHL = 2249,
2263 MULEQ_S_W_PHL_MM = 2250,
2264 MULEQ_S_W_PHR = 2251,
2265 MULEQ_S_W_PHR_MM = 2252,
2266 MULEU_S_PH_QBL = 2253,
2267 MULEU_S_PH_QBL_MM = 2254,
2268 MULEU_S_PH_QBR = 2255,
2269 MULEU_S_PH_QBR_MM = 2256,
2270 MULQ_RS_PH = 2257,
2271 MULQ_RS_PH_MM = 2258,
2272 MULQ_RS_W = 2259,
2273 MULQ_RS_W_MMR2 = 2260,
2274 MULQ_S_PH = 2261,
2275 MULQ_S_PH_MMR2 = 2262,
2276 MULQ_S_W = 2263,
2277 MULQ_S_W_MMR2 = 2264,
2278 MULR_PS64 = 2265,
2279 MULR_Q_H = 2266,
2280 MULR_Q_W = 2267,
2281 MULSAQ_S_W_PH = 2268,
2282 MULSAQ_S_W_PH_MM = 2269,
2283 MULSA_W_PH = 2270,
2284 MULSA_W_PH_MMR2 = 2271,
2285 MULT = 2272,
2286 MULTU_DSP = 2273,
2287 MULTU_DSP_MM = 2274,
2288 MULT_DSP = 2275,
2289 MULT_DSP_MM = 2276,
2290 MULT_MM = 2277,
2291 MULTu = 2278,
2292 MULTu_MM = 2279,
2293 MULU = 2280,
2294 MULU_MMR6 = 2281,
2295 MULV_B = 2282,
2296 MULV_D = 2283,
2297 MULV_H = 2284,
2298 MULV_W = 2285,
2299 MUL_MM = 2286,
2300 MUL_MMR6 = 2287,
2301 MUL_PH = 2288,
2302 MUL_PH_MMR2 = 2289,
2303 MUL_Q_H = 2290,
2304 MUL_Q_W = 2291,
2305 MUL_R6 = 2292,
2306 MUL_S_PH = 2293,
2307 MUL_S_PH_MMR2 = 2294,
2308 Mfhi16 = 2295,
2309 Mflo16 = 2296,
2310 Move32R16 = 2297,
2311 MoveR3216 = 2298,
2312 NAL = 2299,
2313 NLOC_B = 2300,
2314 NLOC_D = 2301,
2315 NLOC_H = 2302,
2316 NLOC_W = 2303,
2317 NLZC_B = 2304,
2318 NLZC_D = 2305,
2319 NLZC_H = 2306,
2320 NLZC_W = 2307,
2321 NMADD_D32 = 2308,
2322 NMADD_D32_MM = 2309,
2323 NMADD_D64 = 2310,
2324 NMADD_S = 2311,
2325 NMADD_S_MM = 2312,
2326 NMSUB_D32 = 2313,
2327 NMSUB_D32_MM = 2314,
2328 NMSUB_D64 = 2315,
2329 NMSUB_S = 2316,
2330 NMSUB_S_MM = 2317,
2331 NOR = 2318,
2332 NOR64 = 2319,
2333 NORI_B = 2320,
2334 NOR_MM = 2321,
2335 NOR_MMR6 = 2322,
2336 NOR_V = 2323,
2337 NOT16_MM = 2324,
2338 NOT16_MMR6 = 2325,
2339 NegRxRy16 = 2326,
2340 NotRxRy16 = 2327,
2341 OR = 2328,
2342 OR16_MM = 2329,
2343 OR16_MMR6 = 2330,
2344 OR64 = 2331,
2345 ORI_B = 2332,
2346 ORI_MMR6 = 2333,
2347 OR_MM = 2334,
2348 OR_MMR6 = 2335,
2349 OR_V = 2336,
2350 ORi = 2337,
2351 ORi64 = 2338,
2352 ORi_MM = 2339,
2353 OrRxRxRy16 = 2340,
2354 PACKRL_PH = 2341,
2355 PACKRL_PH_MM = 2342,
2356 PAUSE = 2343,
2357 PAUSE_MM = 2344,
2358 PAUSE_MMR6 = 2345,
2359 PCKEV_B = 2346,
2360 PCKEV_D = 2347,
2361 PCKEV_H = 2348,
2362 PCKEV_W = 2349,
2363 PCKOD_B = 2350,
2364 PCKOD_D = 2351,
2365 PCKOD_H = 2352,
2366 PCKOD_W = 2353,
2367 PCNT_B = 2354,
2368 PCNT_D = 2355,
2369 PCNT_H = 2356,
2370 PCNT_W = 2357,
2371 PICK_PH = 2358,
2372 PICK_PH_MM = 2359,
2373 PICK_QB = 2360,
2374 PICK_QB_MM = 2361,
2375 PLL_PS64 = 2362,
2376 PLU_PS64 = 2363,
2377 POP = 2364,
2378 PRECEQU_PH_QBL = 2365,
2379 PRECEQU_PH_QBLA = 2366,
2380 PRECEQU_PH_QBLA_MM = 2367,
2381 PRECEQU_PH_QBL_MM = 2368,
2382 PRECEQU_PH_QBR = 2369,
2383 PRECEQU_PH_QBRA = 2370,
2384 PRECEQU_PH_QBRA_MM = 2371,
2385 PRECEQU_PH_QBR_MM = 2372,
2386 PRECEQ_W_PHL = 2373,
2387 PRECEQ_W_PHL_MM = 2374,
2388 PRECEQ_W_PHR = 2375,
2389 PRECEQ_W_PHR_MM = 2376,
2390 PRECEU_PH_QBL = 2377,
2391 PRECEU_PH_QBLA = 2378,
2392 PRECEU_PH_QBLA_MM = 2379,
2393 PRECEU_PH_QBL_MM = 2380,
2394 PRECEU_PH_QBR = 2381,
2395 PRECEU_PH_QBRA = 2382,
2396 PRECEU_PH_QBRA_MM = 2383,
2397 PRECEU_PH_QBR_MM = 2384,
2398 PRECRQU_S_QB_PH = 2385,
2399 PRECRQU_S_QB_PH_MM = 2386,
2400 PRECRQ_PH_W = 2387,
2401 PRECRQ_PH_W_MM = 2388,
2402 PRECRQ_QB_PH = 2389,
2403 PRECRQ_QB_PH_MM = 2390,
2404 PRECRQ_RS_PH_W = 2391,
2405 PRECRQ_RS_PH_W_MM = 2392,
2406 PRECR_QB_PH = 2393,
2407 PRECR_QB_PH_MMR2 = 2394,
2408 PRECR_SRA_PH_W = 2395,
2409 PRECR_SRA_PH_W_MMR2 = 2396,
2410 PRECR_SRA_R_PH_W = 2397,
2411 PRECR_SRA_R_PH_W_MMR2 = 2398,
2412 PREF = 2399,
2413 PREFE = 2400,
2414 PREFE_MM = 2401,
2415 PREFX_MM = 2402,
2416 PREF_MM = 2403,
2417 PREF_MMR6 = 2404,
2418 PREF_R6 = 2405,
2419 PREPEND = 2406,
2420 PREPEND_MMR2 = 2407,
2421 PUL_PS64 = 2408,
2422 PUU_PS64 = 2409,
2423 RADDU_W_QB = 2410,
2424 RADDU_W_QB_MM = 2411,
2425 RDDSP = 2412,
2426 RDDSP_MM = 2413,
2427 RDHWR = 2414,
2428 RDHWR64 = 2415,
2429 RDHWR_MM = 2416,
2430 RDHWR_MMR6 = 2417,
2431 RDPGPR_MMR6 = 2418,
2432 RECIP_D32 = 2419,
2433 RECIP_D32_MM = 2420,
2434 RECIP_D64 = 2421,
2435 RECIP_D64_MM = 2422,
2436 RECIP_S = 2423,
2437 RECIP_S_MM = 2424,
2438 REPLV_PH = 2425,
2439 REPLV_PH_MM = 2426,
2440 REPLV_QB = 2427,
2441 REPLV_QB_MM = 2428,
2442 REPL_PH = 2429,
2443 REPL_PH_MM = 2430,
2444 REPL_QB = 2431,
2445 REPL_QB_MM = 2432,
2446 RINT_D = 2433,
2447 RINT_D_MMR6 = 2434,
2448 RINT_S = 2435,
2449 RINT_S_MMR6 = 2436,
2450 ROTR = 2437,
2451 ROTRV = 2438,
2452 ROTRV_MM = 2439,
2453 ROTR_MM = 2440,
2454 ROUND_L_D64 = 2441,
2455 ROUND_L_D_MMR6 = 2442,
2456 ROUND_L_S = 2443,
2457 ROUND_L_S_MMR6 = 2444,
2458 ROUND_W_D32 = 2445,
2459 ROUND_W_D64 = 2446,
2460 ROUND_W_D_MMR6 = 2447,
2461 ROUND_W_MM = 2448,
2462 ROUND_W_S = 2449,
2463 ROUND_W_S_MM = 2450,
2464 ROUND_W_S_MMR6 = 2451,
2465 RSQRT_D32 = 2452,
2466 RSQRT_D32_MM = 2453,
2467 RSQRT_D64 = 2454,
2468 RSQRT_D64_MM = 2455,
2469 RSQRT_S = 2456,
2470 RSQRT_S_MM = 2457,
2471 Restore16 = 2458,
2472 RestoreX16 = 2459,
2473 SAA = 2460,
2474 SAAD = 2461,
2475 SAT_S_B = 2462,
2476 SAT_S_D = 2463,
2477 SAT_S_H = 2464,
2478 SAT_S_W = 2465,
2479 SAT_U_B = 2466,
2480 SAT_U_D = 2467,
2481 SAT_U_H = 2468,
2482 SAT_U_W = 2469,
2483 SB = 2470,
2484 SB16_MM = 2471,
2485 SB16_MMR6 = 2472,
2486 SB64 = 2473,
2487 SBE = 2474,
2488 SBE_MM = 2475,
2489 SB_MM = 2476,
2490 SB_MMR6 = 2477,
2491 SC = 2478,
2492 SC64 = 2479,
2493 SC64_R6 = 2480,
2494 SCD = 2481,
2495 SCD_R6 = 2482,
2496 SCE = 2483,
2497 SCE_MM = 2484,
2498 SC_MM = 2485,
2499 SC_MMR6 = 2486,
2500 SC_R6 = 2487,
2501 SD = 2488,
2502 SDBBP = 2489,
2503 SDBBP16_MM = 2490,
2504 SDBBP16_MMR6 = 2491,
2505 SDBBP_MM = 2492,
2506 SDBBP_MMR6 = 2493,
2507 SDBBP_R6 = 2494,
2508 SDC1 = 2495,
2509 SDC164 = 2496,
2510 SDC1_D64_MMR6 = 2497,
2511 SDC1_MM_D32 = 2498,
2512 SDC1_MM_D64 = 2499,
2513 SDC2 = 2500,
2514 SDC2_MMR6 = 2501,
2515 SDC2_R6 = 2502,
2516 SDC3 = 2503,
2517 SDIV = 2504,
2518 SDIV_MM = 2505,
2519 SDL = 2506,
2520 SDR = 2507,
2521 SDXC1 = 2508,
2522 SDXC164 = 2509,
2523 SEB = 2510,
2524 SEB64 = 2511,
2525 SEB_MM = 2512,
2526 SEH = 2513,
2527 SEH64 = 2514,
2528 SEH_MM = 2515,
2529 SELEQZ = 2516,
2530 SELEQZ64 = 2517,
2531 SELEQZ_D = 2518,
2532 SELEQZ_D_MMR6 = 2519,
2533 SELEQZ_MMR6 = 2520,
2534 SELEQZ_S = 2521,
2535 SELEQZ_S_MMR6 = 2522,
2536 SELNEZ = 2523,
2537 SELNEZ64 = 2524,
2538 SELNEZ_D = 2525,
2539 SELNEZ_D_MMR6 = 2526,
2540 SELNEZ_MMR6 = 2527,
2541 SELNEZ_S = 2528,
2542 SELNEZ_S_MMR6 = 2529,
2543 SEL_D = 2530,
2544 SEL_D_MMR6 = 2531,
2545 SEL_S = 2532,
2546 SEL_S_MMR6 = 2533,
2547 SEQ = 2534,
2548 SEQi = 2535,
2549 SH = 2536,
2550 SH16_MM = 2537,
2551 SH16_MMR6 = 2538,
2552 SH64 = 2539,
2553 SHE = 2540,
2554 SHE_MM = 2541,
2555 SHF_B = 2542,
2556 SHF_H = 2543,
2557 SHF_W = 2544,
2558 SHILO = 2545,
2559 SHILOV = 2546,
2560 SHILOV_MM = 2547,
2561 SHILO_MM = 2548,
2562 SHLLV_PH = 2549,
2563 SHLLV_PH_MM = 2550,
2564 SHLLV_QB = 2551,
2565 SHLLV_QB_MM = 2552,
2566 SHLLV_S_PH = 2553,
2567 SHLLV_S_PH_MM = 2554,
2568 SHLLV_S_W = 2555,
2569 SHLLV_S_W_MM = 2556,
2570 SHLL_PH = 2557,
2571 SHLL_PH_MM = 2558,
2572 SHLL_QB = 2559,
2573 SHLL_QB_MM = 2560,
2574 SHLL_S_PH = 2561,
2575 SHLL_S_PH_MM = 2562,
2576 SHLL_S_W = 2563,
2577 SHLL_S_W_MM = 2564,
2578 SHRAV_PH = 2565,
2579 SHRAV_PH_MM = 2566,
2580 SHRAV_QB = 2567,
2581 SHRAV_QB_MMR2 = 2568,
2582 SHRAV_R_PH = 2569,
2583 SHRAV_R_PH_MM = 2570,
2584 SHRAV_R_QB = 2571,
2585 SHRAV_R_QB_MMR2 = 2572,
2586 SHRAV_R_W = 2573,
2587 SHRAV_R_W_MM = 2574,
2588 SHRA_PH = 2575,
2589 SHRA_PH_MM = 2576,
2590 SHRA_QB = 2577,
2591 SHRA_QB_MMR2 = 2578,
2592 SHRA_R_PH = 2579,
2593 SHRA_R_PH_MM = 2580,
2594 SHRA_R_QB = 2581,
2595 SHRA_R_QB_MMR2 = 2582,
2596 SHRA_R_W = 2583,
2597 SHRA_R_W_MM = 2584,
2598 SHRLV_PH = 2585,
2599 SHRLV_PH_MMR2 = 2586,
2600 SHRLV_QB = 2587,
2601 SHRLV_QB_MM = 2588,
2602 SHRL_PH = 2589,
2603 SHRL_PH_MMR2 = 2590,
2604 SHRL_QB = 2591,
2605 SHRL_QB_MM = 2592,
2606 SH_MM = 2593,
2607 SH_MMR6 = 2594,
2608 SIGRIE = 2595,
2609 SIGRIE_MMR6 = 2596,
2610 SLDI_B = 2597,
2611 SLDI_D = 2598,
2612 SLDI_H = 2599,
2613 SLDI_W = 2600,
2614 SLD_B = 2601,
2615 SLD_D = 2602,
2616 SLD_H = 2603,
2617 SLD_W = 2604,
2618 SLL = 2605,
2619 SLL16_MM = 2606,
2620 SLL16_MMR6 = 2607,
2621 SLL64_32 = 2608,
2622 SLL64_64 = 2609,
2623 SLLI_B = 2610,
2624 SLLI_D = 2611,
2625 SLLI_H = 2612,
2626 SLLI_W = 2613,
2627 SLLV = 2614,
2628 SLLV_MM = 2615,
2629 SLL_B = 2616,
2630 SLL_D = 2617,
2631 SLL_H = 2618,
2632 SLL_MM = 2619,
2633 SLL_MMR6 = 2620,
2634 SLL_W = 2621,
2635 SLT = 2622,
2636 SLT64 = 2623,
2637 SLT_MM = 2624,
2638 SLTi = 2625,
2639 SLTi64 = 2626,
2640 SLTi_MM = 2627,
2641 SLTiu = 2628,
2642 SLTiu64 = 2629,
2643 SLTiu_MM = 2630,
2644 SLTu = 2631,
2645 SLTu64 = 2632,
2646 SLTu_MM = 2633,
2647 SNE = 2634,
2648 SNEi = 2635,
2649 SPLATI_B = 2636,
2650 SPLATI_D = 2637,
2651 SPLATI_H = 2638,
2652 SPLATI_W = 2639,
2653 SPLAT_B = 2640,
2654 SPLAT_D = 2641,
2655 SPLAT_H = 2642,
2656 SPLAT_W = 2643,
2657 SRA = 2644,
2658 SRAI_B = 2645,
2659 SRAI_D = 2646,
2660 SRAI_H = 2647,
2661 SRAI_W = 2648,
2662 SRARI_B = 2649,
2663 SRARI_D = 2650,
2664 SRARI_H = 2651,
2665 SRARI_W = 2652,
2666 SRAR_B = 2653,
2667 SRAR_D = 2654,
2668 SRAR_H = 2655,
2669 SRAR_W = 2656,
2670 SRAV = 2657,
2671 SRAV_MM = 2658,
2672 SRA_B = 2659,
2673 SRA_D = 2660,
2674 SRA_H = 2661,
2675 SRA_MM = 2662,
2676 SRA_W = 2663,
2677 SRL = 2664,
2678 SRL16_MM = 2665,
2679 SRL16_MMR6 = 2666,
2680 SRLI_B = 2667,
2681 SRLI_D = 2668,
2682 SRLI_H = 2669,
2683 SRLI_W = 2670,
2684 SRLRI_B = 2671,
2685 SRLRI_D = 2672,
2686 SRLRI_H = 2673,
2687 SRLRI_W = 2674,
2688 SRLR_B = 2675,
2689 SRLR_D = 2676,
2690 SRLR_H = 2677,
2691 SRLR_W = 2678,
2692 SRLV = 2679,
2693 SRLV_MM = 2680,
2694 SRL_B = 2681,
2695 SRL_D = 2682,
2696 SRL_H = 2683,
2697 SRL_MM = 2684,
2698 SRL_W = 2685,
2699 SSNOP = 2686,
2700 SSNOP_MM = 2687,
2701 SSNOP_MMR6 = 2688,
2702 ST_B = 2689,
2703 ST_D = 2690,
2704 ST_H = 2691,
2705 ST_W = 2692,
2706 SUB = 2693,
2707 SUBQH_PH = 2694,
2708 SUBQH_PH_MMR2 = 2695,
2709 SUBQH_R_PH = 2696,
2710 SUBQH_R_PH_MMR2 = 2697,
2711 SUBQH_R_W = 2698,
2712 SUBQH_R_W_MMR2 = 2699,
2713 SUBQH_W = 2700,
2714 SUBQH_W_MMR2 = 2701,
2715 SUBQ_PH = 2702,
2716 SUBQ_PH_MM = 2703,
2717 SUBQ_S_PH = 2704,
2718 SUBQ_S_PH_MM = 2705,
2719 SUBQ_S_W = 2706,
2720 SUBQ_S_W_MM = 2707,
2721 SUBSUS_U_B = 2708,
2722 SUBSUS_U_D = 2709,
2723 SUBSUS_U_H = 2710,
2724 SUBSUS_U_W = 2711,
2725 SUBSUU_S_B = 2712,
2726 SUBSUU_S_D = 2713,
2727 SUBSUU_S_H = 2714,
2728 SUBSUU_S_W = 2715,
2729 SUBS_S_B = 2716,
2730 SUBS_S_D = 2717,
2731 SUBS_S_H = 2718,
2732 SUBS_S_W = 2719,
2733 SUBS_U_B = 2720,
2734 SUBS_U_D = 2721,
2735 SUBS_U_H = 2722,
2736 SUBS_U_W = 2723,
2737 SUBU16_MM = 2724,
2738 SUBU16_MMR6 = 2725,
2739 SUBUH_QB = 2726,
2740 SUBUH_QB_MMR2 = 2727,
2741 SUBUH_R_QB = 2728,
2742 SUBUH_R_QB_MMR2 = 2729,
2743 SUBU_MMR6 = 2730,
2744 SUBU_PH = 2731,
2745 SUBU_PH_MMR2 = 2732,
2746 SUBU_QB = 2733,
2747 SUBU_QB_MM = 2734,
2748 SUBU_S_PH = 2735,
2749 SUBU_S_PH_MMR2 = 2736,
2750 SUBU_S_QB = 2737,
2751 SUBU_S_QB_MM = 2738,
2752 SUBVI_B = 2739,
2753 SUBVI_D = 2740,
2754 SUBVI_H = 2741,
2755 SUBVI_W = 2742,
2756 SUBV_B = 2743,
2757 SUBV_D = 2744,
2758 SUBV_H = 2745,
2759 SUBV_W = 2746,
2760 SUB_MM = 2747,
2761 SUB_MMR6 = 2748,
2762 SUBu = 2749,
2763 SUBu_MM = 2750,
2764 SUXC1 = 2751,
2765 SUXC164 = 2752,
2766 SUXC1_MM = 2753,
2767 SW = 2754,
2768 SW16_MM = 2755,
2769 SW16_MMR6 = 2756,
2770 SW64 = 2757,
2771 SWC1 = 2758,
2772 SWC1_MM = 2759,
2773 SWC2 = 2760,
2774 SWC2_MMR6 = 2761,
2775 SWC2_R6 = 2762,
2776 SWC3 = 2763,
2777 SWDSP = 2764,
2778 SWDSP_MM = 2765,
2779 SWE = 2766,
2780 SWE_MM = 2767,
2781 SWL = 2768,
2782 SWL64 = 2769,
2783 SWLE = 2770,
2784 SWLE_MM = 2771,
2785 SWL_MM = 2772,
2786 SWM16_MM = 2773,
2787 SWM16_MMR6 = 2774,
2788 SWM32_MM = 2775,
2789 SWP_MM = 2776,
2790 SWR = 2777,
2791 SWR64 = 2778,
2792 SWRE = 2779,
2793 SWRE_MM = 2780,
2794 SWR_MM = 2781,
2795 SWSP_MM = 2782,
2796 SWSP_MMR6 = 2783,
2797 SWXC1 = 2784,
2798 SWXC1_MM = 2785,
2799 SW_MM = 2786,
2800 SW_MMR6 = 2787,
2801 SYNC = 2788,
2802 SYNCI = 2789,
2803 SYNCI_MM = 2790,
2804 SYNCI_MMR6 = 2791,
2805 SYNC_MM = 2792,
2806 SYNC_MMR6 = 2793,
2807 SYSCALL = 2794,
2808 SYSCALL_MM = 2795,
2809 Save16 = 2796,
2810 SaveX16 = 2797,
2811 SbRxRyOffMemX16 = 2798,
2812 SebRx16 = 2799,
2813 SehRx16 = 2800,
2814 ShRxRyOffMemX16 = 2801,
2815 SllX16 = 2802,
2816 SllvRxRy16 = 2803,
2817 SltRxRy16 = 2804,
2818 SltiRxImm16 = 2805,
2819 SltiRxImmX16 = 2806,
2820 SltiuRxImm16 = 2807,
2821 SltiuRxImmX16 = 2808,
2822 SltuRxRy16 = 2809,
2823 SraX16 = 2810,
2824 SravRxRy16 = 2811,
2825 SrlX16 = 2812,
2826 SrlvRxRy16 = 2813,
2827 SubuRxRyRz16 = 2814,
2828 SwRxRyOffMemX16 = 2815,
2829 SwRxSpImmX16 = 2816,
2830 TEQ = 2817,
2831 TEQI = 2818,
2832 TEQI_MM = 2819,
2833 TEQ_MM = 2820,
2834 TGE = 2821,
2835 TGEI = 2822,
2836 TGEIU = 2823,
2837 TGEIU_MM = 2824,
2838 TGEI_MM = 2825,
2839 TGEU = 2826,
2840 TGEU_MM = 2827,
2841 TGE_MM = 2828,
2842 TLBGINV = 2829,
2843 TLBGINVF = 2830,
2844 TLBGINVF_MM = 2831,
2845 TLBGINV_MM = 2832,
2846 TLBGP = 2833,
2847 TLBGP_MM = 2834,
2848 TLBGR = 2835,
2849 TLBGR_MM = 2836,
2850 TLBGWI = 2837,
2851 TLBGWI_MM = 2838,
2852 TLBGWR = 2839,
2853 TLBGWR_MM = 2840,
2854 TLBINV = 2841,
2855 TLBINVF = 2842,
2856 TLBINVF_MMR6 = 2843,
2857 TLBINV_MMR6 = 2844,
2858 TLBP = 2845,
2859 TLBP_MM = 2846,
2860 TLBR = 2847,
2861 TLBR_MM = 2848,
2862 TLBWI = 2849,
2863 TLBWI_MM = 2850,
2864 TLBWR = 2851,
2865 TLBWR_MM = 2852,
2866 TLT = 2853,
2867 TLTI = 2854,
2868 TLTIU_MM = 2855,
2869 TLTI_MM = 2856,
2870 TLTU = 2857,
2871 TLTU_MM = 2858,
2872 TLT_MM = 2859,
2873 TNE = 2860,
2874 TNEI = 2861,
2875 TNEI_MM = 2862,
2876 TNE_MM = 2863,
2877 TRUNC_L_D64 = 2864,
2878 TRUNC_L_D_MMR6 = 2865,
2879 TRUNC_L_S = 2866,
2880 TRUNC_L_S_MMR6 = 2867,
2881 TRUNC_W_D32 = 2868,
2882 TRUNC_W_D64 = 2869,
2883 TRUNC_W_D_MMR6 = 2870,
2884 TRUNC_W_MM = 2871,
2885 TRUNC_W_S = 2872,
2886 TRUNC_W_S_MM = 2873,
2887 TRUNC_W_S_MMR6 = 2874,
2888 TTLTIU = 2875,
2889 UDIV = 2876,
2890 UDIV_MM = 2877,
2891 V3MULU = 2878,
2892 VMM0 = 2879,
2893 VMULU = 2880,
2894 VSHF_B = 2881,
2895 VSHF_D = 2882,
2896 VSHF_H = 2883,
2897 VSHF_W = 2884,
2898 WAIT = 2885,
2899 WAIT_MM = 2886,
2900 WAIT_MMR6 = 2887,
2901 WRDSP = 2888,
2902 WRDSP_MM = 2889,
2903 WRPGPR_MMR6 = 2890,
2904 WSBH = 2891,
2905 WSBH_MM = 2892,
2906 WSBH_MMR6 = 2893,
2907 XOR = 2894,
2908 XOR16_MM = 2895,
2909 XOR16_MMR6 = 2896,
2910 XOR64 = 2897,
2911 XORI_B = 2898,
2912 XORI_MMR6 = 2899,
2913 XOR_MM = 2900,
2914 XOR_MMR6 = 2901,
2915 XOR_V = 2902,
2916 XORi = 2903,
2917 XORi64 = 2904,
2918 XORi_MM = 2905,
2919 XorRxRxRy16 = 2906,
2920 YIELD = 2907,
2921 INSTRUCTION_LIST_END = 2908
2922 };
2923
2924} // end namespace llvm::Mips
2925#endif // GET_INSTRINFO_ENUM
2926
2927#ifdef GET_INSTRINFO_SCHED_ENUM
2928#undef GET_INSTRINFO_SCHED_ENUM
2929namespace llvm::Mips::Sched {
2930
2931 enum {
2932 NoInstrModel = 0,
2933 IIPseudo = 1,
2934 II_B = 2,
2935 II_BCCZAL = 3,
2936 II_MTC1 = 4,
2937 II_MFC1 = 5,
2938 II_JALR = 6,
2939 II_JAL = 7,
2940 II_CVT = 8,
2941 II_DMULT = 9,
2942 II_DMULTU = 10,
2943 II_DDIV = 11,
2944 II_DDIVU = 12,
2945 II_IndirectBranchPseudo = 13,
2946 II_MADD = 14,
2947 II_MADDU = 15,
2948 II_MFHI_MFLO = 16,
2949 II_MSUB = 17,
2950 II_MSUBU = 18,
2951 II_MTHI_MTLO = 19,
2952 II_MULT = 20,
2953 II_MULTU = 21,
2954 II_ReturnPseudo = 22,
2955 II_DIV = 23,
2956 II_DIVU = 24,
2957 II_J = 25,
2958 II_JR = 26,
2959 II_TRAP = 27,
2960 II_ADD = 28,
2961 II_ADDIUPC = 29,
2962 II_ADDIU = 30,
2963 II_ADDR_PS = 31,
2964 II_ADDU = 32,
2965 II_ADDI = 33,
2966 II_ALIGN = 34,
2967 II_ALUIPC = 35,
2968 II_AND = 36,
2969 II_ANDI = 37,
2970 II_AUI = 38,
2971 II_AUIPC = 39,
2972 IIM16Alu = 40,
2973 II_BADDU = 41,
2974 II_BC = 42,
2975 II_BALC = 43,
2976 II_BBIT = 44,
2977 II_BC1CCZ = 45,
2978 II_BC1F = 46,
2979 II_BC1FL = 47,
2980 II_BC1T = 48,
2981 II_BC1TL = 49,
2982 II_BC2CCZ = 50,
2983 II_BCC = 51,
2984 II_BCCC = 52,
2985 II_BCCZ = 53,
2986 II_BCCZC = 54,
2987 II_BCCZALS = 55,
2988 II_BITSWAP = 56,
2989 II_BREAK = 57,
2990 II_CACHE = 58,
2991 II_CACHEE = 59,
2992 II_CEIL = 60,
2993 II_CFC1 = 61,
2994 II_CFC2 = 62,
2995 II_INS = 63,
2996 II_CLASS_D = 64,
2997 II_CLASS_S = 65,
2998 II_CLO = 66,
2999 II_CLZ = 67,
3000 II_CMP_CC_D = 68,
3001 II_CMP_CC_S = 69,
3002 II_CRC32B = 70,
3003 II_CRC32CB = 71,
3004 II_CRC32CD = 72,
3005 II_CRC32CH = 73,
3006 II_CRC32CW = 74,
3007 II_CRC32D = 75,
3008 II_CRC32H = 76,
3009 II_CRC32W = 77,
3010 II_CTC1 = 78,
3011 II_CTC2 = 79,
3012 II_C_CC_D = 80,
3013 II_C_CC_S = 81,
3014 II_DADD = 82,
3015 II_DADDI = 83,
3016 II_DADDIU = 84,
3017 II_DADDU = 85,
3018 II_DAHI = 86,
3019 II_DALIGN = 87,
3020 II_DATI = 88,
3021 II_DAUI = 89,
3022 II_DBITSWAP = 90,
3023 II_DCLO = 91,
3024 II_DCLZ = 92,
3025 II_DERET = 93,
3026 II_EXT = 94,
3027 II_DI = 95,
3028 II_DLSA = 96,
3029 II_DMFC0 = 97,
3030 II_DMFC1 = 98,
3031 II_DMFC2 = 99,
3032 II_DMFGC0 = 100,
3033 II_DMOD = 101,
3034 II_DMODU = 102,
3035 II_DMT = 103,
3036 II_DMTC0 = 104,
3037 II_DMTC1 = 105,
3038 II_DMTC2 = 106,
3039 II_DMTGC0 = 107,
3040 II_DMUH = 108,
3041 II_DMUHU = 109,
3042 II_DMUL = 110,
3043 II_POP = 111,
3044 II_DROTR = 112,
3045 II_DROTR32 = 113,
3046 II_DROTRV = 114,
3047 II_DSBH = 115,
3048 II_DSHD = 116,
3049 II_DSLL = 117,
3050 II_DSLL32 = 118,
3051 II_DSLLV = 119,
3052 II_DSRA = 120,
3053 II_DSRA32 = 121,
3054 II_DSRAV = 122,
3055 II_DSRL = 123,
3056 II_DSRL32 = 124,
3057 II_DSRLV = 125,
3058 II_DSUB = 126,
3059 II_DSUBU = 127,
3060 II_DVP = 128,
3061 II_DVPE = 129,
3062 II_EHB = 130,
3063 II_EI = 131,
3064 II_EMT = 132,
3065 II_ERET = 133,
3066 II_ERETNC = 134,
3067 II_EVP = 135,
3068 II_EVPE = 136,
3069 II_ABS = 137,
3070 II_SQRT_D = 138,
3071 II_ADD_D = 139,
3072 II_ADD_PS = 140,
3073 II_ADD_S = 141,
3074 II_DIV_D = 142,
3075 II_DIV_S = 143,
3076 II_FLOOR = 144,
3077 II_MOV_D = 145,
3078 II_MOV_S = 146,
3079 II_MUL_D = 147,
3080 II_MUL_PS = 148,
3081 II_MUL_S = 149,
3082 II_NEG = 150,
3083 II_FORK = 151,
3084 II_SQRT_S = 152,
3085 II_SUB_D = 153,
3086 II_SUB_PS = 154,
3087 II_SUB_S = 155,
3088 II_GINVI = 156,
3089 II_GINVT = 157,
3090 II_HYPCALL = 158,
3091 II_JALR_HB = 159,
3092 II_JALRC = 160,
3093 II_JALRS = 161,
3094 II_JALS = 162,
3095 II_JIALC = 163,
3096 II_JIC = 164,
3097 II_JRADDIUSP = 165,
3098 II_JRC = 166,
3099 II_JR_HB = 167,
3100 II_LB = 168,
3101 II_LBE = 169,
3102 II_LBU = 170,
3103 II_LBUE = 171,
3104 II_LD = 172,
3105 II_LDC1 = 173,
3106 II_LDC2 = 174,
3107 II_LDC3 = 175,
3108 II_LDL = 176,
3109 II_LDPC = 177,
3110 II_LDR = 178,
3111 II_LDXC1 = 179,
3112 II_LH = 180,
3113 II_LHE = 181,
3114 II_LHU = 182,
3115 II_LHUE = 183,
3116 II_LI = 184,
3117 II_LL = 185,
3118 II_LLD = 186,
3119 II_LLE = 187,
3120 II_LSA = 188,
3121 II_LUI = 189,
3122 II_LUXC1 = 190,
3123 II_LW = 191,
3124 II_LWC1 = 192,
3125 II_LWC2 = 193,
3126 II_LWC3 = 194,
3127 II_LWE = 195,
3128 II_LWL = 196,
3129 II_LWLE = 197,
3130 II_LWM = 198,
3131 II_LWPC = 199,
3132 II_LWP = 200,
3133 II_LWR = 201,
3134 II_LWRE = 202,
3135 II_LWUPC = 203,
3136 II_LWU = 204,
3137 II_LWXC1 = 205,
3138 II_LWXS = 206,
3139 II_MADDF_D = 207,
3140 II_MADDF_S = 208,
3141 II_MADD_D = 209,
3142 II_MADD_S = 210,
3143 II_MAX_D = 211,
3144 II_MAXA_D = 212,
3145 II_MAX_S = 213,
3146 II_MAXA_S = 214,
3147 II_MFC0 = 215,
3148 II_MFC2 = 216,
3149 II_MFGC0 = 217,
3150 II_MFHC0 = 218,
3151 II_MFHC1 = 219,
3152 II_MFHGC0 = 220,
3153 II_MFTR = 221,
3154 II_MIN_S = 222,
3155 II_MINA_D = 223,
3156 II_MIN_D = 224,
3157 II_MINA_S = 225,
3158 II_MOD = 226,
3159 II_MODU = 227,
3160 II_MOVE = 228,
3161 II_MOVF_D = 229,
3162 II_MOVF = 230,
3163 II_MOVF_S = 231,
3164 II_MOVN_D = 232,
3165 II_MOVN = 233,
3166 II_MOVN_S = 234,
3167 II_MOVT_D = 235,
3168 II_MOVT = 236,
3169 II_MOVT_S = 237,
3170 II_MOVZ_D = 238,
3171 II_MOVZ = 239,
3172 II_MOVZ_S = 240,
3173 II_MSUBF_D = 241,
3174 II_MSUBF_S = 242,
3175 II_MSUB_D = 243,
3176 II_MSUB_S = 244,
3177 II_MTC0 = 245,
3178 II_MTC2 = 246,
3179 II_MTGC0 = 247,
3180 II_MTHC0 = 248,
3181 II_MTHC1 = 249,
3182 II_MTHGC0 = 250,
3183 II_MTTR = 251,
3184 II_MUH = 252,
3185 II_MUHU = 253,
3186 II_MUL = 254,
3187 II_MULR_PS = 255,
3188 II_MULU = 256,
3189 II_NMADD_D = 257,
3190 II_NMADD_S = 258,
3191 II_NMSUB_D = 259,
3192 II_NMSUB_S = 260,
3193 II_NOR = 261,
3194 II_NOT = 262,
3195 II_OR = 263,
3196 II_ORI = 264,
3197 II_PAUSE = 265,
3198 II_PREF = 266,
3199 II_PREFE = 267,
3200 II_RDHWR = 268,
3201 II_RDPGPR = 269,
3202 II_RECIP_D = 270,
3203 II_RECIP_S = 271,
3204 II_RINT_D = 272,
3205 II_RINT_S = 273,
3206 II_ROTR = 274,
3207 II_ROTRV = 275,
3208 II_ROUND = 276,
3209 II_RSQRT_D = 277,
3210 II_RSQRT_S = 278,
3211 II_RESTORE = 279,
3212 II_SB = 280,
3213 II_SBE = 281,
3214 II_SC = 282,
3215 II_SCD = 283,
3216 II_SCE = 284,
3217 II_SD = 285,
3218 II_SDBBP = 286,
3219 II_SDC1 = 287,
3220 II_SDC2 = 288,
3221 II_SDC3 = 289,
3222 II_SDL = 290,
3223 II_SDR = 291,
3224 II_SDXC1 = 292,
3225 II_SEB = 293,
3226 II_SEH = 294,
3227 II_SELCCZ = 295,
3228 II_SELCCZ_D = 296,
3229 II_SELCCZ_S = 297,
3230 II_SEL_D = 298,
3231 II_SEL_S = 299,
3232 II_SEQ_SNE = 300,
3233 II_SEQI_SNEI = 301,
3234 II_SH = 302,
3235 II_SHE = 303,
3236 II_SIGRIE = 304,
3237 II_SLL = 305,
3238 II_SLLV = 306,
3239 II_SLT_SLTU = 307,
3240 II_SLTI_SLTIU = 308,
3241 II_SRA = 309,
3242 II_SRAV = 310,
3243 II_SRL = 311,
3244 II_SRLV = 312,
3245 II_SSNOP = 313,
3246 II_SUB = 314,
3247 II_SUBU = 315,
3248 II_SUXC1 = 316,
3249 II_SW = 317,
3250 II_SWC1 = 318,
3251 II_SWC2 = 319,
3252 II_SWC3 = 320,
3253 II_SWE = 321,
3254 II_SWL = 322,
3255 II_SWLE = 323,
3256 II_SWM = 324,
3257 II_SWP = 325,
3258 II_SWR = 326,
3259 II_SWRE = 327,
3260 II_SWXC1 = 328,
3261 II_SYNC = 329,
3262 II_SYNCI = 330,
3263 II_SYSCALL = 331,
3264 II_SAVE = 332,
3265 II_TEQ = 333,
3266 II_TEQI = 334,
3267 II_TGE = 335,
3268 II_TGEI = 336,
3269 II_TGEIU = 337,
3270 II_TGEU = 338,
3271 II_TLBGINV = 339,
3272 II_TLBGINVF = 340,
3273 II_TLBGP = 341,
3274 II_TLBGR = 342,
3275 II_TLBGWI = 343,
3276 II_TLBGWR = 344,
3277 II_TLBINV = 345,
3278 II_TLBINVF = 346,
3279 II_TLBP = 347,
3280 II_TLBR = 348,
3281 II_TLBWI = 349,
3282 II_TLBWR = 350,
3283 II_TLT = 351,
3284 II_TLTI = 352,
3285 II_TTLTIU = 353,
3286 II_TLTU = 354,
3287 II_TNE = 355,
3288 II_TNEI = 356,
3289 II_TRUNC = 357,
3290 II_WAIT = 358,
3291 II_WRPGPR = 359,
3292 II_WSBH = 360,
3293 II_XOR = 361,
3294 II_XORI = 362,
3295 II_YIELD = 363,
3296 SB = 364,
3297 SD = 365,
3298 SH = 366,
3299 SW = 367,
3300 SDC1_SDC164 = 368,
3301 SWC1 = 369,
3302 SWC2_R6 = 370,
3303 SDC2_R6 = 371,
3304 SDC3 = 372,
3305 SC_R6_SC64_R6 = 373,
3306 SCD_R6 = 374,
3307 SYNCI = 375,
3308 TLBP = 376,
3309 TLBR = 377,
3310 TLBWI = 378,
3311 TLBWR = 379,
3312 TLBINV = 380,
3313 TLBINVF = 381,
3314 CACHE_R6 = 382,
3315 LB_LB64 = 383,
3316 LBu_LBu64 = 384,
3317 LD = 385,
3318 LH_LH64 = 386,
3319 LHu_LHu64 = 387,
3320 LW_LW64 = 388,
3321 LWu = 389,
3322 LDC1_LDC164 = 390,
3323 LWC1 = 391,
3324 LD_F16_ST_F16 = 392,
3325 LDC2_R6 = 393,
3326 LDC3 = 394,
3327 LWC2_R6 = 395,
3328 LLD_R6 = 396,
3329 LL_R6_LL64_R6 = 397,
3330 LWPC = 398,
3331 LWUPC = 399,
3332 LDPC = 400,
3333 ST_B_ST_H_ST_W_ST_D = 401,
3334 LWL64 = 402,
3335 LWR64 = 403,
3336 SB64 = 404,
3337 SH64 = 405,
3338 SW64 = 406,
3339 SWL64 = 407,
3340 SWR64 = 408,
3341 PREF_PREF_R6 = 409,
3342 PAUSE = 410,
3343 SYNC = 411,
3344 J_TAILCALL = 412,
3345 JAL = 413,
3346 JALR_JALR64_JALR64Pseudo_JALRHBPseudo_JALRPseudo_JALRHB64Pseudo = 414,
3347 B = 415,
3348 BEQ_BNE_BEQ64_BNE64 = 416,
3349 BGEZ_BGTZ_BLEZ_BLTZ_BGEZ64_BGTZ64_BLEZ64_BLTZ64 = 417,
3350 JIALC_JIALC64_JIC = 418,
3351 JIC64 = 419,
3352 JR64_TAILCALL64R6REG_TAILCALLR6REG_TAILCALLHB64R6REG_TAILCALLHBR6REG = 420,
3353 JR_HB_R6_JR_HB64_R6 = 421,
3354 NAL = 422,
3355 SDBBP_R6 = 423,
3356 SYSCALL = 424,
3357 BEQC64_BGEC64_BGEUC64_BLTC64_BLTUC64_BNEC64_BEQC_BNEC_BGEC_BLTC_BGEUC_BLTUC_BOVC_BNVC = 425,
3358 BEQZC64_BGTZC64_BLEZC64_BNEZC64_BEQZC_BNEZC_BLEZC_BGEZC_BGTZC_BLTZC_BEQZALC_BNEZALC_BLEZALC_BGEZALC_BGTZALC_BLTZALC_BGEZC64_BLTZC64 = 426,
3359 PseudoIndirectBranchR6_PseudoIndirectBranch64R6_PseudoIndrectHazardBranch64R6_PseudoIndrectHazardBranchR6 = 427,
3360 BC_BAL = 428,
3361 BALC = 429,
3362 BC1EQZ_BC1NEZ = 430,
3363 BREAK = 431,
3364 ERET = 432,
3365 ERETNC = 433,
3366 BAL_BR = 434,
3367 DERET = 435,
3368 JALR_HB_JALR_HB64 = 436,
3369 PseudoReturn_PseudoReturn64 = 437,
3370 ERet_RetRA = 438,
3371 BC2EQZ_BC2NEZ = 439,
3372 TLT = 440,
3373 TLTU = 441,
3374 TNE = 442,
3375 WAIT = 443,
3376 DI = 444,
3377 TRAP = 445,
3378 EI = 446,
3379 ADD = 447,
3380 ADDiu = 448,
3381 ADDIUPC = 449,
3382 ADDu = 450,
3383 ALIGN = 451,
3384 ALUIPC = 452,
3385 AND_AND64_ANDi64 = 453,
3386 ANDi = 454,
3387 AUI = 455,
3388 AUIPC = 456,
3389 BITSWAP = 457,
3390 CFC1 = 458,
3391 CLO_R6 = 459,
3392 CLZ_R6 = 460,
3393 CTC1 = 461,
3394 DADD = 462,
3395 DADDiu = 463,
3396 DADDu = 464,
3397 DAHI = 465,
3398 DALIGN = 466,
3399 DATI = 467,
3400 DAUI = 468,
3401 DBITSWAP = 469,
3402 DCLO_R6 = 470,
3403 DCLZ_R6 = 471,
3404 DEXT_DEXT64_32_DEXTM_DEXTU_EXT = 472,
3405 DINS_DINSM_DINSU_INS = 473,
3406 DLSA_R6_DLSA = 474,
3407 DMFC1 = 475,
3408 DMTC1 = 476,
3409 DROTR = 477,
3410 DROTR32 = 478,
3411 DROTRV = 479,
3412 DSBH = 480,
3413 DSHD = 481,
3414 DSLL_DSLL64_32 = 482,
3415 DSLL32 = 483,
3416 DSLLV = 484,
3417 DSRA = 485,
3418 DSRA32 = 486,
3419 DSRAV = 487,
3420 DSRL = 488,
3421 DSRL32 = 489,
3422 DSRLV = 490,
3423 DSUB = 491,
3424 DSUBu = 492,
3425 LSA_LSA_R6 = 493,
3426 LUi_LUi64 = 494,
3427 MFC1_MFC1_D64_ExtractElementF64_ExtractElementF64_64 = 495,
3428 MFC0 = 496,
3429 MFC2 = 497,
3430 MTC0 = 498,
3431 MTC2 = 499,
3432 MFHC1_D32_MFHC1_D64 = 500,
3433 MTC1_MTC1_D64_BuildPairF64_BuildPairF64_64 = 501,
3434 MTHC1_D32_MTHC1_D64 = 502,
3435 NOP_LONG_BRANCH_LUi2Op_64_LONG_BRANCH_DADDiu2Op_LONG_BRANCH_DADDiu = 503,
3436 NOR_NOR64 = 504,
3437 OR_OR64_ORi64 = 505,
3438 ORi = 506,
3439 ROTR = 507,
3440 ROTRV = 508,
3441 SEB_SEB64 = 509,
3442 SEH_SEH64 = 510,
3443 SELEQZ_SELEQZ64_SELNEZ_SELNEZ64 = 511,
3444 SLL_SLL64_32_SLL64_64 = 512,
3445 SLLV = 513,
3446 SLT_SLTu_SLT64_SLTu64 = 514,
3447 SLTi_SLTiu_SLTi64_SLTiu64 = 515,
3448 SRA = 516,
3449 SRAV = 517,
3450 SRL = 518,
3451 SRLV = 519,
3452 SSNOP = 520,
3453 SUB = 521,
3454 SUBu = 522,
3455 WSBH = 523,
3456 XOR_XOR64_XORi64 = 524,
3457 XORi = 525,
3458 TEQ = 526,
3459 TGE = 527,
3460 TGEU = 528,
3461 COPY = 529,
3462 SELNEZ_D_SELEQZ_D = 530,
3463 SELNEZ_S_SELEQZ_S = 531,
3464 SEL_D = 532,
3465 SEL_S = 533,
3466 EHB = 534,
3467 RDHWR_RDHWR64 = 535,
3468 EVP = 536,
3469 DVP = 537,
3470 DMFC0 = 538,
3471 DMFC2 = 539,
3472 DMTC0 = 540,
3473 DMTC2 = 541,
3474 MUL_R6 = 542,
3475 MULU = 543,
3476 MUH = 544,
3477 MUHU = 545,
3478 DMUL_R6_DMULU = 546,
3479 DMUH = 547,
3480 DMUHU = 548,
3481 DIV = 549,
3482 DIVU = 550,
3483 MOD = 551,
3484 MODU = 552,
3485 DDIV = 553,
3486 DMOD = 554,
3487 DDIVU = 555,
3488 DMODU = 556,
3489 MOD_S_B_MOD_S_D_MOD_S_H_MOD_S_W_MOD_U_B_MOD_U_D_MOD_U_H_MOD_U_W = 557,
3490 FABS_S = 558,
3491 FNEG_S_FNEG_D32_FNEG_D64 = 559,
3492 FMOV_S = 560,
3493 FMOV_D32_FMOV_D64 = 561,
3494 CLASS_S = 562,
3495 CLASS_D = 563,
3496 FADD_S = 564,
3497 FSUB_S = 565,
3498 FSUB_D32_FSUB_D64 = 566,
3499 FMUL_S = 567,
3500 FMUL_D32_FMUL_D64 = 568,
3501 FDIV_S = 569,
3502 FSQRT_S = 570,
3503 FDIV_D32_FDIV_D64 = 571,
3504 FSQRT_D_FSQRT_W_FRSQRT_D_FRSQRT_W_FRCP_D_FRCP_W = 572,
3505 FSQRT_D32_FSQRT_D64 = 573,
3506 RECIP_S = 574,
3507 RECIP_D32_RECIP_D64 = 575,
3508 RSQRT_S = 576,
3509 RSQRT_D32_RSQRT_D64 = 577,
3510 DIV_S_B_DIV_S_D_DIV_S_H_DIV_S_W = 578,
3511 DIV_U_B_DIV_U_D_DIV_U_H_DIV_U_W = 579,
3512 ADDV_B_ADDV_H_ADDV_W_ADDV_D_ADDVI_B_ADDVI_H_ADDVI_W_ADDVI_D_SUBV_B_SUBV_H_SUBV_W_SUBV_D_SUBVI_B_SUBVI_H_SUBVI_W_SUBVI_D = 580,
3513 ASUB_S_B_ASUB_S_D_ASUB_S_H_ASUB_S_W = 581,
3514 ASUB_U_B_ASUB_U_D_ASUB_U_H_ASUB_U_W = 582,
3515 SUBSUS_U_B_SUBSUS_U_D_SUBSUS_U_H_SUBSUS_U_W = 583,
3516 MAX_D_MAXA_D = 584,
3517 MAX_S_MAXA_S = 585,
3518 MIN_D_MINA_S = 586,
3519 MIN_S_MINA_D = 587,
3520 ADD_A_B_ADD_A_H_ADD_A_W_ADD_A_D_ADDS_A_B_ADDS_A_H_ADDS_A_W_ADDS_A_D_ADDS_S_B_ADDS_S_H_ADDS_S_W_ADDS_S_D_ADDS_U_B_ADDS_U_H_ADDS_U_W_ADDS_U_D_HADD_S_H_HADD_S_W_HADD_S_D_HADD_U_H_HADD_U_W_HADD_U_D_SUBS_S_B_SUBS_S_H_SUBS_S_W_SUBS_S_D_SUBS_U_B_SUBS_U_H_SUBS_U_W_SUBS_U_D_SUBSUU_S_B_SUBSUU_S_H_SUBSUU_S_W_SUBSUU_S_D_HSUB_S_H_HSUB_S_W_HSUB_S_D_HSUB_U_H_HSUB_U_W_HSUB_U_D_AVE_S_B_AVE_S_H_AVE_S_W_AVE_S_D_AVE_U_B_AVE_U_H_AVE_U_W_AVE_U_D_AVER_S_B_AVER_S_H_AVER_S_W_AVER_S_D_AVER_U_B_AVER_U_H_AVER_U_W_AVER_U_D_MIN_A_B_MIN_A_H_MIN_A_W_MIN_A_D_MIN_S_B_MIN_S_H_MIN_S_W_MIN_S_D_MIN_U_B_MIN_U_H_MIN_U_W_MIN_U_D_MINI_S_B_MINI_S_H_MINI_S_W_MINI_S_D_MINI_U_B_MINI_U_H_MINI_U_W_MINI_U_D_MAX_A_B_MAX_A_H_MAX_A_W_MAX_A_D_MAX_S_B_MAX_S_H_MAX_S_W_MAX_S_D_MAX_U_B_MAX_U_H_MAX_U_W_MAX_U_D_MAXI_S_B_MAXI_S_H_MAXI_S_W_MAXI_S_D_MAXI_U_B_MAXI_U_H_MAXI_U_W_MAXI_U_D_CEQ_B_CEQ_H_CEQ_W_CEQ_D_CEQI_B_CEQI_H_CEQI_W_CEQI_D_CLE_S_B_CLE_S_H_CLE_S_W_CLE_S_D_CLE_U_B_CLE_U_H_CLE_U_W_CLE_U_D_CLEI_S_B_CLEI_S_H_CLEI_S_W_CLEI_S_D_CLEI_U_B_CLEI_U_H_CLEI_U_W_CLEI_U_D_CLT_S_B_CLT_S_H_CLT_S_W_CLT_S_D_CLT_U_B_CLT_U_H_CLT_U_W_CLT_U_D_CLTI_S_B_CLTI_S_H_CLTI_S_W_CLTI_S_D_CLTI_U_B_CLTI_U_H_CLTI_U_W_CLTI_U_D = 588,
3521 SAT_S_B_SAT_S_H_SAT_S_W_SAT_S_D_SAT_U_B_SAT_U_H_SAT_U_W_SAT_U_D_PCNT_B_PCNT_H_PCNT_W_PCNT_D = 589,
3522 SLL_B_SLL_H_SLL_W_SLL_D_SLLI_B_SLLI_H_SLLI_W_SLLI_D_SRA_B_SRA_H_SRA_W_SRA_D_SRAI_B_SRAI_H_SRAI_W_SRAI_D_SRAR_B_SRAR_H_SRAR_W_SRAR_D_SRARI_B_SRARI_H_SRARI_W_SRARI_D_SRL_B_SRL_H_SRL_W_SRL_D_SRLI_B_SRLI_H_SRLI_W_SRLI_D_SRLR_B_SRLR_H_SRLR_W_SRLR_D_SRLRI_B_SRLRI_H_SRLRI_W_SRLRI_D_NLOC_B_NLOC_H_NLOC_W_NLOC_D_NLZC_B_NLZC_H_NLZC_W_NLZC_D_BNEG_B_BNEG_H_BNEG_W_BNEG_D_BNEGI_B_BNEGI_H_BNEGI_W_BNEGI_D_BCLR_B_BCLR_H_BCLR_W_BCLR_D_BCLRI_B_BCLRI_H_BCLRI_W_BCLRI_D_SHF_B_SHF_H_SHF_W = 590,
3523 AND_V_ANDI_B_OR_V_ORI_B_XOR_V_XORI_B_NOR_V_NORI_B = 591,
3524 NOR_V_D_PSEUDO_NOR_V_H_PSEUDO_NOR_V_W_PSEUDO = 592,
3525 OR_V_D_PSEUDO_OR_V_H_PSEUDO_OR_V_W_PSEUDO = 593,
3526 XOR_V_D_PSEUDO_XOR_V_H_PSEUDO_XOR_V_W_PSEUDO = 594,
3527 AND_V_D_PSEUDO_AND_V_H_PSEUDO_AND_V_W_PSEUDO = 595,
3528 ILVEV_B_ILVEV_D_ILVEV_H_ILVEV_W = 596,
3529 ILVL_B_ILVL_D_ILVL_H_ILVL_W = 597,
3530 ILVOD_B_ILVOD_D_ILVOD_H_ILVOD_W = 598,
3531 ILVR_B_ILVR_D_ILVR_H_ILVR_W = 599,
3532 PCKEV_B_PCKEV_D_PCKEV_H_PCKEV_W = 600,
3533 PCKOD_B_PCKOD_D_PCKOD_H_PCKOD_W = 601,
3534 FILL_B_FILL_D_FILL_H_FILL_W = 602,
3535 FILL_FD_PSEUDO_FILL_FW_PSEUDO = 603,
3536 INSERT_FD_PSEUDO_INSERT_FW_PSEUDO = 604,
3537 SPLAT_B_SPLAT_D_SPLAT_H_SPLAT_W = 605,
3538 SPLATI_B_SPLATI_D_SPLATI_H_SPLATI_W = 606,
3539 CTCMSA_CFCMSA_COPY_S_B_COPY_S_H_COPY_S_W_COPY_S_D_COPY_U_B_COPY_U_H_COPY_U_W_BNZ_B_BNZ_H_BNZ_W_BNZ_D_BNZ_V_BZ_B_BZ_H_BZ_W_BZ_D_BZ_V = 607,
3540 LD_B_LD_H_LD_W_LD_D = 608,
3541 LDI_B_LDI_H_LDI_W_LDI_D_MOVE_V = 609,
3542 FCAF_W_FCAF_D_FCUN_W_FCUN_D_FCOR_W_FCOR_D_FCEQ_W_FCEQ_D_FCUNE_W_FCUNE_D_FCUEQ_W_FCUEQ_D_FCNE_W_FCNE_D_FCLT_W_FCLT_D_FCULT_W_FCULT_D_FCLE_W_FCLE_D_FCULE_W_FCULE_D_FSAF_W_FSAF_D_FSUN_W_FSUN_D_FSOR_W_FSOR_D_FSEQ_W_FSEQ_D_FSUNE_W_FSUNE_D_FSUEQ_W_FSUEQ_D_FSNE_W_FSNE_D_FSLT_W_FSLT_D_FSULT_W_FSULT_D_FSLE_W_FSLE_D_FSULE_W_FSULE_D = 610,
3543 FMAX_W_FMAX_D_FMAX_A_W_FMAX_A_D_FMIN_W_FMIN_D_FMIN_A_W_FMIN_A_D_FCLASS_W_FCLASS_D_FABS_D_FABS_W = 611,
3544 FABS_D32_FABS_D64 = 612,
3545 CMP_UN_D = 613,
3546 CMP_UN_S = 614,
3547 CMP_UEQ_D = 615,
3548 CMP_UEQ_S = 616,
3549 CMP_EQ_D = 617,
3550 CMP_EQ_S = 618,
3551 CMP_LT_D = 619,
3552 CMP_LT_S = 620,
3553 CMP_ULT_D = 621,
3554 CMP_ULT_S = 622,
3555 CMP_LE_D = 623,
3556 CMP_LE_S = 624,
3557 CMP_ULE_D = 625,
3558 CMP_ULE_S = 626,
3559 CMP_F_D = 627,
3560 CMP_F_S = 628,
3561 CMP_SAF_D = 629,
3562 CMP_SAF_S = 630,
3563 CMP_SEQ_D = 631,
3564 CMP_SEQ_S = 632,
3565 CMP_SLE_D = 633,
3566 CMP_SLE_S = 634,
3567 CMP_SLT_D = 635,
3568 CMP_SLT_S = 636,
3569 CMP_SUEQ_D = 637,
3570 CMP_SUEQ_S = 638,
3571 CMP_SULE_D = 639,
3572 CMP_SULE_S = 640,
3573 CMP_SULT_D = 641,
3574 CMP_SULT_S = 642,
3575 CMP_SUN_D = 643,
3576 CMP_SUN_S = 644,
3577 TRUNC_W_S_TRUNC_L_S_TRUNC_L_D64_TRUNC_W_D32_TRUNC_W_D64 = 645,
3578 PseudoTRUNC_W_D_PseudoTRUNC_W_D32_PseudoTRUNC_W_S = 646,
3579 ROUND_W_S_ROUND_L_S_ROUND_L_D64_ROUND_W_D32_ROUND_W_D64 = 647,
3580 FLOOR_W_S_FLOOR_L_S_FLOOR_L_D64_FLOOR_W_D32_FLOOR_W_D64 = 648,
3581 CVT_D32_S_CVT_D32_W_CVT_D64_W_CVT_D64_S_CVT_D64_L_CVT_L_S_CVT_L_D64_CVT_S_W_CVT_S_D32_CVT_S_PU64_CVT_S_PL64_CVT_S_L_CVT_S_D64_CVT_W_S_CVT_W_D64_CVT_W_D32 = 649,
3582 CEIL_W_S_CEIL_L_S_CEIL_L_D64_CEIL_W_D32_CEIL_W_D64 = 650,
3583 RINT_D = 651,
3584 RINT_S = 652,
3585 BMZ_V_BMZI_B_BMNZ_V_BMNZI_B_INSERT_B_INSERT_H_INSERT_W_INSERT_D_INSVE_B_INSVE_H_INSVE_W_INSVE_D = 653,
3586 BSELI_B_BSEL_V = 654,
3587 BSEL_D_PSEUDO_BSEL_FD_PSEUDO_BSEL_FW_PSEUDO_BSEL_H_PSEUDO_BSEL_W_PSEUDO = 655,
3588 BINSL_B_BINSL_H_BINSL_W_BINSL_D_BINSLI_B_BINSLI_H_BINSLI_W_BINSLI_D_BINSR_B_BINSR_H_BINSR_W_BINSR_D_BINSRI_B_BINSRI_H_BINSRI_W_BINSRI_D_VSHF_B_VSHF_H_VSHF_W_VSHF_D_SLD_B_SLD_H_SLD_W_SLD_D_SLDI_B_SLDI_H_SLDI_W_SLDI_D_BSET_B_BSET_H_BSET_W_BSET_D_BSETI_B_BSETI_H_BSETI_W_BSETI_D = 656,
3589 MADDV_B_MADDV_H_MADDV_W_MADDV_D_MSUBV_B_MSUBV_H_MSUBV_W_MSUBV_D_MULV_B_MULV_H_MULV_W_MULV_D_DOTP_S_H_DOTP_S_W_DOTP_S_D_DOTP_U_H_DOTP_U_W_DOTP_U_D_MUL_Q_H_MUL_Q_W_MULR_Q_H_MULR_Q_W_MSUB_Q_H_MSUB_Q_W_MSUBR_Q_H_MSUBR_Q_W_MADD_Q_H_MADD_Q_W_MADDR_Q_H_MADDR_Q_W = 657,
3590 FLOG2_W_FLOG2_D = 658,
3591 FADD_W_FADD_D_FSUB_W_FSUB_D_FEXDO_H_FEXDO_W_FEXUPL_W_FEXUPL_D_FEXUPR_W_FEXUPR_D_FFINT_S_W_FFINT_S_D_FFINT_U_W_FFINT_U_D_FFQL_W_FFQL_D_FFQR_W_FFQR_D_FTINT_S_W_FTINT_S_D_FTINT_U_W_FTINT_U_D_FTRUNC_S_W_FTRUNC_S_D_FTRUNC_U_W_FTRUNC_U_D_FTQ_H_FTQ_W_FRINT_W_FRINT_D = 659,
3592 FADD_D32_FADD_D64 = 660,
3593 PseudoCVT_D32_W_PseudoCVT_D64_L_PseudoCVT_D64_W_PseudoCVT_S_L_PseudoCVT_S_W = 661,
3594 FMUL_W_FMUL_D_FEXP2_W_FEXP2_D_DPADD_S_H_DPADD_S_W_DPADD_S_D_DPADD_U_H_DPADD_U_W_DPADD_U_D_DPSUB_S_H_DPSUB_S_W_DPSUB_S_D_DPSUB_U_H_DPSUB_U_W_DPSUB_U_D = 662,
3595 FMADD_W_FMADD_D_FMSUB_W_FMSUB_D = 663,
3596 MSUBF_D = 664,
3597 MSUBF_S = 665,
3598 MADDF_D = 666,
3599 MADDF_S = 667,
3600 FDIV_D = 668,
3601 FDIV_W = 669,
3602 ATOMIC_SWAP_I16_POSTRA_ATOMIC_SWAP_I32_POSTRA_ATOMIC_SWAP_I64_POSTRA_ATOMIC_SWAP_I8_POSTRA = 670,
3603 ATOMIC_CMP_SWAP_I16_POSTRA_ATOMIC_CMP_SWAP_I32_POSTRA_ATOMIC_CMP_SWAP_I64_POSTRA_ATOMIC_CMP_SWAP_I8_POSTRA = 671,
3604 ATOMIC_LOAD_ADD_I16_POSTRA_ATOMIC_LOAD_ADD_I32_POSTRA_ATOMIC_LOAD_ADD_I64_POSTRA_ATOMIC_LOAD_ADD_I8_POSTRA_ATOMIC_LOAD_AND_I16_POSTRA_ATOMIC_LOAD_AND_I32_POSTRA_ATOMIC_LOAD_AND_I64_POSTRA_ATOMIC_LOAD_AND_I8_POSTRA_ATOMIC_LOAD_MAX_I16_POSTRA_ATOMIC_LOAD_MAX_I32_POSTRA_ATOMIC_LOAD_MAX_I64_POSTRA_ATOMIC_LOAD_MAX_I8_POSTRA_ATOMIC_LOAD_MIN_I16_POSTRA_ATOMIC_LOAD_MIN_I32_POSTRA_ATOMIC_LOAD_MIN_I64_POSTRA_ATOMIC_LOAD_MIN_I8_POSTRA_ATOMIC_LOAD_NAND_I16_POSTRA_ATOMIC_LOAD_NAND_I32_POSTRA_ATOMIC_LOAD_NAND_I64_POSTRA_ATOMIC_LOAD_NAND_I8_POSTRA_ATOMIC_LOAD_OR_I16_POSTRA_ATOMIC_LOAD_OR_I32_POSTRA_ATOMIC_LOAD_OR_I64_POSTRA_ATOMIC_LOAD_OR_I8_POSTRA_ATOMIC_LOAD_SUB_I16_POSTRA_ATOMIC_LOAD_SUB_I32_POSTRA_ATOMIC_LOAD_SUB_I64_POSTRA_ATOMIC_LOAD_SUB_I8_POSTRA_ATOMIC_LOAD_UMAX_I16_POSTRA_ATOMIC_LOAD_UMAX_I32_POSTRA_ATOMIC_LOAD_UMAX_I64_POSTRA_ATOMIC_LOAD_UMAX_I8_POSTRA_ATOMIC_LOAD_UMIN_I16_POSTRA_ATOMIC_LOAD_UMIN_I32_POSTRA_ATOMIC_LOAD_UMIN_I64_POSTRA_ATOMIC_LOAD_UMIN_I8_POSTRA_ATOMIC_LOAD_XOR_I16_POSTRA_ATOMIC_LOAD_XOR_I32_POSTRA_ATOMIC_LOAD_XOR_I64_POSTRA_ATOMIC_LOAD_XOR_I8_POSTRA = 672,
3605 AND = 673,
3606 LUi = 674,
3607 NOR = 675,
3608 OR = 676,
3609 SLTi_SLTiu = 677,
3610 XOR = 678,
3611 NOP = 679,
3612 BAL = 680,
3613 BEQ_BNE = 681,
3614 BEQL_BNEL = 682,
3615 BGEZ_BGTZ_BLEZ_BLTZ = 683,
3616 BGEZAL_BGEZALL_BLTZAL_BLTZALL = 684,
3617 BGEZL_BGTZL_BLEZL_BLTZL = 685,
3618 JR_TAILCALLREG_TAILCALLREGHB = 686,
3619 JR_HB = 687,
3620 PseudoIndirectBranch_PseudoIndirectHazardBranch = 688,
3621 PseudoReturn = 689,
3622 SDBBP = 690,
3623 TEQI = 691,
3624 TGEI = 692,
3625 TGEIU = 693,
3626 TLTI = 694,
3627 TNEI = 695,
3628 TTLTIU = 696,
3629 JALR_JALRHBPseudo_JALRPseudo = 697,
3630 JALR_HB = 698,
3631 JALX = 699,
3632 HYPCALL = 700,
3633 MFGC0 = 701,
3634 MFHGC0 = 702,
3635 MTGC0 = 703,
3636 MTHGC0 = 704,
3637 TLBGINV = 705,
3638 TLBGINVF = 706,
3639 TLBGP = 707,
3640 TLBGR = 708,
3641 TLBGWI = 709,
3642 TLBGWR = 710,
3643 LB = 711,
3644 LBu = 712,
3645 LH = 713,
3646 LHu = 714,
3647 LW = 715,
3648 LL = 716,
3649 LWC2 = 717,
3650 LWC3 = 718,
3651 LDC2 = 719,
3652 LBE = 720,
3653 LBuE = 721,
3654 LHE = 722,
3655 LHuE = 723,
3656 LWE = 724,
3657 LLE = 725,
3658 LWL = 726,
3659 LWR = 727,
3660 LWLE = 728,
3661 LWRE = 729,
3662 SWC2 = 730,
3663 SWC3 = 731,
3664 SDC2 = 732,
3665 SC = 733,
3666 SBE = 734,
3667 SHE = 735,
3668 SWE = 736,
3669 SCE = 737,
3670 SWL = 738,
3671 SWR = 739,
3672 SWLE = 740,
3673 SWRE = 741,
3674 PREF = 742,
3675 PREFE = 743,
3676 CACHE = 744,
3677 CACHEE = 745,
3678 CLO = 746,
3679 CLZ = 747,
3680 MFHI_MFLO_PseudoMFHI_PseudoMFLO = 748,
3681 RDHWR = 749,
3682 MOVN_I_I = 750,
3683 MOVZ_I_I = 751,
3684 PseudoSDIV_SDIV = 752,
3685 PseudoUDIV_UDIV = 753,
3686 MUL = 754,
3687 MULT_PseudoMULT = 755,
3688 MULTu_PseudoMULTu = 756,
3689 MADD_PseudoMADD = 757,
3690 MADDU_PseudoMADDU = 758,
3691 MSUB_PseudoMSUB = 759,
3692 MSUBU_PseudoMSUBU = 760,
3693 MTHI_MTLO_PseudoMTLOHI = 761,
3694 EXT = 762,
3695 INS = 763,
3696 ADDi = 764,
3697 SEB = 765,
3698 SEH = 766,
3699 SLT_SLTu = 767,
3700 SLL = 768,
3701 LSA = 769,
3702 VSHF_B_VSHF_D_VSHF_H_VSHF_W = 770,
3703 BINSLI_B_BINSLI_D_BINSLI_H_BINSLI_W_BINSL_B_BINSL_D_BINSL_H_BINSL_W = 771,
3704 BINSRI_B_BINSRI_D_BINSRI_H_BINSRI_W_BINSR_B_BINSR_D_BINSR_H_BINSR_W = 772,
3705 INSERT_B_INSERT_D_INSERT_H_INSERT_W = 773,
3706 SLDI_B_SLDI_D_SLDI_H_SLDI_W_SLD_B_SLD_D_SLD_H_SLD_W = 774,
3707 BCLRI_B_BCLRI_D_BCLRI_H_BCLRI_W_BCLR_B_BCLR_D_BCLR_H_BCLR_W = 775,
3708 BNEGI_B_BNEGI_D_BNEGI_H_BNEGI_W_BNEG_B_BNEG_D_BNEG_H_BNEG_W = 776,
3709 BMNZI_B_BMNZ_V_BMZI_B_BMZ_V = 777,
3710 PCNT_B_PCNT_D_PCNT_H_PCNT_W = 778,
3711 BNZ_B_BNZ_D_BNZ_H_BNZ_V_BNZ_W_BZ_B_BZ_D_BZ_H_BZ_V_BZ_W = 779,
3712 CFCMSA_CTCMSA = 780,
3713 MOVF_D32_MOVF_D64 = 781,
3714 MOVF_S = 782,
3715 MOVT_D32_MOVT_D64 = 783,
3716 MOVT_S = 784,
3717 ADD_A_B_ADD_A_D_ADD_A_H_ADD_A_W = 785,
3718 ADDS_A_B_ADDS_A_D_ADDS_A_H_ADDS_A_W_ADDS_S_B_ADDS_S_D_ADDS_S_H_ADDS_S_W_ADDS_U_B_ADDS_U_D_ADDS_U_H_ADDS_U_W = 786,
3719 ADDVI_B_ADDVI_D_ADDVI_H_ADDVI_W_ADDV_B_ADDV_D_ADDV_H_ADDV_W = 787,
3720 AVER_S_B_AVER_S_D_AVER_S_H_AVER_S_W_AVER_U_B_AVER_U_D_AVER_U_H_AVER_U_W_AVE_S_B_AVE_S_D_AVE_S_H_AVE_S_W_AVE_U_B_AVE_U_D_AVE_U_H_AVE_U_W = 788,
3721 SHF_B_SHF_H_SHF_W = 789,
3722 MOVE_V = 790,
3723 AND_V_NOR_V_OR_V_XOR_V = 791,
3724 FEXP2_D_FEXP2_W = 792,
3725 CLTI_S_B_CLTI_S_D_CLTI_S_H_CLTI_S_W_CLTI_U_B_CLTI_U_D_CLTI_U_H_CLTI_U_W_CLT_S_B_CLT_S_D_CLT_S_H_CLT_S_W_CLT_U_B_CLT_U_D_CLT_U_H_CLT_U_W = 793,
3726 CLEI_S_B_CLEI_S_D_CLEI_S_H_CLEI_S_W_CLEI_U_B_CLEI_U_D_CLEI_U_H_CLEI_U_W_CLE_S_B_CLE_S_D_CLE_S_H_CLE_S_W_CLE_U_B_CLE_U_D_CLE_U_H_CLE_U_W = 794,
3727 CEQI_B_CEQI_D_CEQI_H_CEQI_W_CEQ_B_CEQ_D_CEQ_H_CEQ_W = 795,
3728 FSAF_D_FSAF_W_FSEQ_D_FSEQ_W_FSLE_D_FSLE_W_FSLT_D_FSLT_W_FSNE_D_FSNE_W_FSOR_D_FSOR_W = 796,
3729 FSUEQ_D_FSUEQ_W = 797,
3730 FSULE_D_FSULE_W = 798,
3731 FSULT_D_FSULT_W = 799,
3732 FSUNE_D_FSUNE_W = 800,
3733 FSUN_D_FSUN_W = 801,
3734 FCAF_D_FCAF_W = 802,
3735 FCEQ_D_FCEQ_W = 803,
3736 FCLE_D_FCLE_W = 804,
3737 FCLT_D_FCLT_W = 805,
3738 FCNE_D_FCNE_W = 806,
3739 FCOR_D_FCOR_W = 807,
3740 FCUEQ_D_FCUEQ_W = 808,
3741 FCULE_D_FCULE_W = 809,
3742 FCULT_D_FCULT_W = 810,
3743 FCUNE_D_FCUNE_W = 811,
3744 FABS_D_FABS_W = 812,
3745 FFINT_S_D_FFINT_S_W_FFINT_U_D_FFINT_U_W = 813,
3746 FFQL_D_FFQL_W = 814,
3747 FFQR_D_FFQR_W = 815,
3748 FTINT_S_D_FTINT_S_W_FTINT_U_D_FTINT_U_W = 816,
3749 FRINT_D_FRINT_W = 817,
3750 FTQ_H_FTQ_W = 818,
3751 FTRUNC_S_D_FTRUNC_S_W_FTRUNC_U_D_FTRUNC_U_W = 819,
3752 FEXDO_H_FEXDO_W = 820,
3753 FEXUPL_D_FEXUPL_W = 821,
3754 FEXUPR_D_FEXUPR_W = 822,
3755 FCLASS_D_FCLASS_W = 823,
3756 FMAX_A_D_FMAX_A_W = 824,
3757 FMAX_D_FMAX_W = 825,
3758 FMIN_A_D_FMIN_A_W = 826,
3759 SUBS_S_B_SUBS_S_D_SUBS_S_H_SUBS_S_W_SUBS_U_B_SUBS_U_D_SUBS_U_H_SUBS_U_W = 827,
3760 SUBSUU_S_B_SUBSUU_S_D_SUBSUU_S_H_SUBSUU_S_W = 828,
3761 SUBVI_B_SUBVI_D_SUBVI_H_SUBVI_W = 829,
3762 HADD_S_D_HADD_S_H_HADD_S_W_HADD_U_D_HADD_U_H_HADD_U_W = 830,
3763 HSUB_S_D_HSUB_S_H_HSUB_S_W_HSUB_U_D_HSUB_U_H_HSUB_U_W = 831,
3764 MAX_S_B_MAX_S_D_MAX_S_H_MAX_S_W_MIN_S_B_MIN_S_D_MIN_S_H_MIN_S_W = 832,
3765 MAX_U_B_MAX_U_D_MAX_U_H_MAX_U_W_MIN_U_B_MIN_U_D_MIN_U_H_MIN_U_W = 833,
3766 MAX_A_B_MAX_A_D_MAX_A_H_MAX_A_W_MIN_A_B_MIN_A_D_MIN_A_H_MIN_A_W = 834,
3767 SRAI_B_SRAI_D_SRAI_H_SRAI_W_SRA_B_SRA_D_SRA_H_SRA_W = 835,
3768 SRLI_B_SRLI_D_SRLI_H_SRLI_W_SRL_B_SRL_D_SRL_H_SRL_W = 836,
3769 SRARI_B_SRARI_D_SRARI_H_SRARI_W_SRAR_B_SRAR_D_SRAR_H_SRAR_W = 837,
3770 SRLRI_B_SRLRI_D_SRLRI_H_SRLRI_W_SRLR_B_SRLR_D_SRLR_H_SRLR_W = 838,
3771 SLLI_B_SLLI_D_SLLI_H_SLLI_W_SLL_B_SLL_D_SLL_H_SLL_W = 839,
3772 FADD_PS64 = 840,
3773 FMUL_PS64 = 841,
3774 FSUB_PS64 = 842,
3775 CVT_D32_S_CVT_D32_W_CVT_D64_L_CVT_D64_S_CVT_D64_W_CVT_L_D64_CVT_L_S_CVT_S_D32_CVT_S_D64_CVT_S_L_CVT_S_W_CVT_W_D32_CVT_W_D64_CVT_W_S = 843,
3776 CVT_PS_S64 = 844,
3777 C_EQ_D32_C_EQ_D64_C_F_D32_C_F_D64_C_LE_D32_C_LE_D64_C_LT_D32_C_LT_D64_C_NGE_D32_C_NGE_D64_C_NGLE_D32_C_NGLE_D64_C_NGL_D32_C_NGL_D64_C_NGT_D32_C_NGT_D64_C_OLE_D32_C_OLE_D64_C_OLT_D32_C_OLT_D64_C_SEQ_D32_C_SEQ_D64_C_SF_D32_C_SF_D64_C_UEQ_D32_C_UEQ_D64_C_ULE_D32_C_ULE_D64_C_ULT_D32_C_ULT_D64_C_UN_D32_C_UN_D64 = 845,
3778 C_EQ_S_C_F_S_C_LE_S_C_LT_S_C_NGE_S_C_NGLE_S_C_NGL_S_C_NGT_S_C_OLE_S_C_OLT_S_C_SEQ_S_C_SF_S_C_UEQ_S_C_ULE_S_C_ULT_S_C_UN_S = 846,
3779 FCMP_D32_FCMP_D64 = 847,
3780 FCMP_S32 = 848,
3781 PLL_PS64_PLU_PS64_PUL_PS64_PUU_PS64 = 849,
3782 FRCP_D_FRCP_W = 850,
3783 FRSQRT_D_FRSQRT_W = 851,
3784 FMADD_D_FMADD_W = 852,
3785 FSQRT_W = 853,
3786 FMUL_D_FMUL_W = 854,
3787 FADD_D_FADD_W = 855,
3788 DPADD_S_D_DPADD_S_H_DPADD_S_W_DPADD_U_D_DPADD_U_H_DPADD_U_W = 856,
3789 DOTP_S_D_DOTP_S_H_DOTP_S_W_DOTP_U_D_DOTP_U_H_DOTP_U_W = 857,
3790 MSUBV_B_MSUBV_D_MSUBV_H_MSUBV_W = 858,
3791 MADDV_B_MADDV_D_MADDV_H_MADDV_W = 859,
3792 MULV_B_MULV_D_MULV_H_MULV_W = 860,
3793 MADDR_Q_H_MADDR_Q_W = 861,
3794 MADD_Q_H_MADD_Q_W = 862,
3795 MSUBR_Q_H_MSUBR_Q_W = 863,
3796 MSUB_Q_H_MSUB_Q_W = 864,
3797 MULR_Q_H_MULR_Q_W = 865,
3798 MADD_D32_MADD_D64 = 866,
3799 MADD_S = 867,
3800 MSUB_D32_MSUB_D64 = 868,
3801 MSUB_S = 869,
3802 NMADD_D32_NMADD_D64 = 870,
3803 NMADD_S = 871,
3804 NMSUB_D32_NMSUB_D64 = 872,
3805 NMSUB_S = 873,
3806 COPY_U_B_COPY_U_H_COPY_U_W = 874,
3807 BC1F = 875,
3808 BC1FL = 876,
3809 BC1T = 877,
3810 BC1TL = 878,
3811 MOVF_I = 879,
3812 MOVT_I = 880,
3813 SDXC1_SDXC164 = 881,
3814 SWXC1 = 882,
3815 SUXC1_SUXC164 = 883,
3816 ST_F16 = 884,
3817 MOVN_I_D32_MOVN_I_D64 = 885,
3818 MOVN_I_S = 886,
3819 MOVZ_I_D32_MOVZ_I_D64 = 887,
3820 MOVZ_I_S = 888,
3821 LDXC1_LDXC164 = 889,
3822 LWXC1 = 890,
3823 LUXC1_LUXC164 = 891,
3824 LEA_ADDiu = 892,
3825 SELEQZ_SELNEZ = 893,
3826 AddiuRxImmX16_AddiuRxRxImm16_AddiuRxRxImmX16_AddiuRxRyOffMemX16_AddiuRxPcImmX16_AddiuSpImm16_AddiuSpImmX16_AdduRxRyRz16_AndRxRxRy16_CmpRxRy16_CmpiRxImm16_CmpiRxImmX16_LiRxImm16_LiRxImmX16_LiRxImmAlignX16_Move32R16_MoveR3216_Mfhi16_Mflo16_NegRxRy16_NotRxRy16_OrRxRxRy16_SebRx16_SehRx16_SllX16_SllvRxRy16_SltiRxImm16_SltiRxImmX16_SltiuRxImm16_SltiuRxImmX16_SltRxRy16_SltuRxRy16_SravRxRy16_SraX16_SrlvRxRy16_SrlX16_SubuRxRyRz16_XorRxRxRy16 = 894,
3827 SltiCCRxImmX16_SltiuCCRxImmX16_SltCCRxRy16_SltuRxRyRz16_SltuCCRxRy16 = 895,
3828 Constant32_LwConstant32_GotPrologue16_CONSTPOOL_ENTRY = 896,
3829 ADDIUPC_MM_ADDIUR1SP_MM_ADDIUR2_MM_ADDIUS5_MM_ADDIUSP_MM_ADDiu_MM_LEA_ADDiu_MM = 897,
3830 ADDU16_MM_ADDu_MM = 898,
3831 ADD_MM = 899,
3832 ADDi_MM = 900,
3833 AND16_MM_ANDI16_MM_AND_MM = 901,
3834 ANDi_MM = 902,
3835 CLO_MM = 903,
3836 CLZ_MM = 904,
3837 EXT_MM = 905,
3838 INS_MM = 906,
3839 LI16_MM = 907,
3840 LUi_MM = 908,
3841 MOVE16_MM = 909,
3842 MOVEP_MM = 910,
3843 NOR_MM = 911,
3844 NOT16_MM = 912,
3845 OR16_MM_OR_MM = 913,
3846 ORi_MM = 914,
3847 ROTRV_MM = 915,
3848 ROTR_MM = 916,
3849 SEB_MM = 917,
3850 SEH_MM = 918,
3851 SLL16_MM_SLL_MM = 919,
3852 SLLV_MM = 920,
3853 SLT_MM_SLTu_MM = 921,
3854 SLTi_MM_SLTiu_MM = 922,
3855 SRAV_MM = 923,
3856 SRA_MM = 924,
3857 SRL16_MM_SRL_MM = 925,
3858 SRLV_MM = 926,
3859 SSNOP_MM = 927,
3860 SUBU16_MM_SUBu_MM = 928,
3861 SUB_MM = 929,
3862 WSBH_MM = 930,
3863 XOR16_MM_XOR_MM = 931,
3864 XORi_MM = 932,
3865 ADDIUPC_MMR6 = 933,
3866 ADDIU_MMR6 = 934,
3867 ADDU16_MMR6_ADDU_MMR6 = 935,
3868 ADD_MMR6 = 936,
3869 ALIGN_MMR6 = 937,
3870 ALUIPC_MMR6 = 938,
3871 AND16_MMR6_ANDI16_MMR6_AND_MMR6 = 939,
3872 ANDI_MMR6 = 940,
3873 AUIPC_MMR6 = 941,
3874 AUI_MMR6 = 942,
3875 BITSWAP_MMR6 = 943,
3876 CLO_MMR6 = 944,
3877 CLZ_MMR6 = 945,
3878 EXT_MMR6 = 946,
3879 INS_MMR6 = 947,
3880 LI16_MMR6 = 948,
3881 LSA_MMR6 = 949,
3882 LUI_MMR6 = 950,
3883 MOVE16_MMR6 = 951,
3884 NOR_MMR6 = 952,
3885 NOT16_MMR6 = 953,
3886 OR16_MMR6_OR_MMR6 = 954,
3887 ORI_MMR6 = 955,
3888 SELEQZ_MMR6_SELNEZ_MMR6 = 956,
3889 SLL16_MMR6_SLL_MMR6 = 957,
3890 SRL16_MMR6 = 958,
3891 SSNOP_MMR6 = 959,
3892 SUBU16_MMR6_SUBU_MMR6 = 960,
3893 SUB_MMR6 = 961,
3894 WSBH_MMR6 = 962,
3895 XOR16_MMR6_XOR_MMR6 = 963,
3896 XORI_MMR6 = 964,
3897 DEXT64_32 = 965,
3898 DSLL64_32 = 966,
3899 ORi64 = 967,
3900 DADDi = 968,
3901 DCLO = 969,
3902 DCLZ = 970,
3903 LEA_ADDiu64 = 971,
3904 MADD = 972,
3905 MADDU = 973,
3906 MSUB = 974,
3907 MSUBU = 975,
3908 PseudoMADD_MM = 976,
3909 PseudoMADDU_MM = 977,
3910 PseudoMSUB_MM = 978,
3911 PseudoMSUBU_MM = 979,
3912 PseudoMULT_MM = 980,
3913 PseudoMULTu_MM = 981,
3914 PseudoMULT = 982,
3915 PseudoMULTu = 983,
3916 PseudoMFHI_MM_PseudoMFLO_MM = 984,
3917 PseudoMTLOHI_MM = 985,
3918 MultRxRy16_MultuRxRy16_MultRxRyRz16_MultuRxRyRz16 = 986,
3919 DivRxRy16 = 987,
3920 DivuRxRy16 = 988,
3921 MULT_MM = 989,
3922 MULTu_MM = 990,
3923 MADD_MM = 991,
3924 MADDU_MM = 992,
3925 MSUB_MM = 993,
3926 MSUBU_MM = 994,
3927 MUL_MM = 995,
3928 SDIV_MM_SDIV_MM_Pseudo = 996,
3929 UDIV_MM_UDIV_MM_Pseudo = 997,
3930 MFHI16_MM_MFLO16_MM_MFHI_MM_MFLO_MM = 998,
3931 MOVF_I_MM = 999,
3932 MOVT_I_MM = 1000,
3933 MTHI_MM_MTLO_MM = 1001,
3934 RDHWR_MM = 1002,
3935 MUHU_MMR6 = 1003,
3936 MUH_MMR6 = 1004,
3937 MULU_MMR6 = 1005,
3938 MUL_MMR6 = 1006,
3939 MODU_MMR6 = 1007,
3940 MOD_MMR6 = 1008,
3941 DIVU_MMR6 = 1009,
3942 DIV_MMR6 = 1010,
3943 RDHWR_MMR6 = 1011,
3944 DMULU = 1012,
3945 DMULT_PseudoDMULT = 1013,
3946 DMULTu_PseudoDMULTu = 1014,
3947 DSDIV_PseudoDSDIV = 1015,
3948 DUDIV_PseudoDUDIV = 1016,
3949 MFHI64_MFLO64_PseudoMFHI64_PseudoMFLO64 = 1017,
3950 PseudoMTLOHI64 = 1018,
3951 MTHI64_MTLO64 = 1019,
3952 MOVN_I_I64_MOVN_I64_I_MOVN_I64_I64 = 1020,
3953 MOVZ_I_I64_MOVZ_I64_I_MOVZ_I64_I64 = 1021,
3954 BLTZAL = 1022,
3955 J = 1023,
3956 JR = 1024,
3957 ERet = 1025,
3958 BGEZAL = 1026,
3959 BEQZALC_BGEZALC_BGTZALC_BLEZALC_BLTZALC_BNEZALC = 1027,
3960 JIALC = 1028,
3961 BEQC_BGEC_BGEUC_BLTC_BLTUC_BNEC_BNVC_BOVC = 1029,
3962 BEQZC_BGEZC_BGTZC_BLEZC_BLTZC_BNEZC = 1030,
3963 JIC = 1031,
3964 JR_HB_R6 = 1032,
3965 SIGRIE = 1033,
3966 PseudoIndirectBranchR6_PseudoIndrectHazardBranchR6 = 1034,
3967 TAILCALLR6REG_TAILCALLHBR6REG = 1035,
3968 Bimm16_BimmX16_BeqzRxImm16_BeqzRxImmX16_BnezRxImm16_BnezRxImmX16_Bteqz16_BteqzX16_Btnez16_BtnezX16_JrRa16_JrcRa16_JrcRx16 = 1036,
3969 BteqzT8CmpX16_BteqzT8CmpiX16_BteqzT8SltX16_BteqzT8SltuX16_BteqzT8SltiX16_BteqzT8SltiuX16_BtnezT8CmpX16_BtnezT8CmpiX16_BtnezT8SltX16_BtnezT8SltuX16_BtnezT8SltiX16_BtnezT8SltiuX16_RetRA16 = 1037,
3970 Jal16_JalB16 = 1038,
3971 JumpLinkReg16 = 1039,
3972 Break16 = 1040,
3973 SelBeqZ_SelTBteqZCmp_SelTBteqZCmpi_SelTBteqZSlt_SelTBteqZSlti_SelTBteqZSltu_SelTBteqZSltiu_SelBneZ_SelTBtneZCmp_SelTBtneZCmpi_SelTBtneZSlt_SelTBtneZSlti_SelTBtneZSltu_SelTBtneZSltiu = 1041,
3974 B16_MM_B_MM = 1042,
3975 BAL_BR_MM = 1043,
3976 BC1F_MM = 1044,
3977 BC1T_MM = 1045,
3978 BEQZ16_MM_BGEZ_MM_BGTZ_MM_BLEZ_MM_BLTZ_MM_BNEZ16_MM = 1046,
3979 BEQZC_MM_BNEZC_MM = 1047,
3980 BEQ_MM_BNE_MM = 1048,
3981 DERET_MM = 1049,
3982 ERET_MM = 1050,
3983 JR16_MM_JR_MM = 1051,
3984 J_MM = 1052,
3985 B_MM_Pseudo = 1053,
3986 BGEZALS_MM_BLTZALS_MM = 1054,
3987 BGEZAL_MM_BLTZAL_MM = 1055,
3988 JALR16_MM_JALR_MM = 1056,
3989 JALRS16_MM_JALRS_MM = 1057,
3990 JALS_MM = 1058,
3991 JALX_MM_JAL_MM = 1059,
3992 TAILCALLREG_MM = 1060,
3993 TAILCALL_MM = 1061,
3994 PseudoIndirectBranch_MM = 1062,
3995 BREAK16_MM_BREAK_MM = 1063,
3996 SDBBP16_MM_SDBBP_MM = 1064,
3997 SYSCALL_MM = 1065,
3998 TEQI_MM = 1066,
3999 TEQ_MM = 1067,
4000 TGEIU_MM = 1068,
4001 TGEI_MM = 1069,
4002 TGEU_MM = 1070,
4003 TGE_MM = 1071,
4004 TLTIU_MM = 1072,
4005 TLTI_MM = 1073,
4006 TLTU_MM = 1074,
4007 TLT_MM = 1075,
4008 TNEI_MM = 1076,
4009 TNE_MM = 1077,
4010 TRAP_MM = 1078,
4011 BC16_MMR6_BC_MMR6 = 1079,
4012 BC1EQZC_MMR6_BC1NEZC_MMR6 = 1080,
4013 BC2EQZC_MMR6_BC2NEZC_MMR6 = 1081,
4014 BEQC_MMR6_BGEC_MMR6_BGEUC_MMR6_BLTC_MMR6_BLTUC_MMR6_BNEC_MMR6_BNVC_MMR6_BOVC_MMR6 = 1082,
4015 BEQZC16_MMR6_BNEZC16_MMR6 = 1083,
4016 BEQZC_MMR6_BGEZC_MMR6_BGTZC_MMR6_BLEZC_MMR6_BLTZC_MMR6_BNEZC_MMR6 = 1084,
4017 DERET_MMR6 = 1085,
4018 ERETNC_MMR6 = 1086,
4019 JAL_MMR6 = 1087,
4020 ERET_MMR6 = 1088,
4021 JIC_MMR6 = 1089,
4022 JRADDIUSP_JRCADDIUSP_MMR6 = 1090,
4023 JRC16_MM = 1091,
4024 JRC16_MMR6 = 1092,
4025 SIGRIE_MMR6 = 1093,
4026 B_MMR6_Pseudo = 1094,
4027 PseudoIndirectBranch_MMR6 = 1095,
4028 BALC_MMR6 = 1096,
4029 BEQZALC_MMR6_BGEZALC_MMR6_BGTZALC_MMR6_BLEZALC_MMR6_BLTZALC_MMR6_BNEZALC_MMR6 = 1097,
4030 JALRC16_MMR6 = 1098,
4031 JALRC_HB_MMR6 = 1099,
4032 JALRC_MMR6 = 1100,
4033 JIALC_MMR6 = 1101,
4034 TAILCALLREG_MMR6 = 1102,
4035 TAILCALL_MMR6 = 1103,
4036 BREAK16_MMR6_BREAK_MMR6 = 1104,
4037 SDBBP_MMR6_SDBBP16_MMR6 = 1105,
4038 JR64 = 1106,
4039 JR_HB64 = 1107,
4040 TAILCALLREG64_TAILCALLREGHB64 = 1108,
4041 PseudoIndirectBranch64_PseudoIndirectHazardBranch64 = 1109,
4042 TLBP_MM = 1110,
4043 TLBR_MM = 1111,
4044 TLBWI_MM = 1112,
4045 TLBWR_MM = 1113,
4046 DI_MM = 1114,
4047 EI_MM = 1115,
4048 EHB_MM = 1116,
4049 PAUSE_MM = 1117,
4050 WAIT_MM = 1118,
4051 RDPGPR_MMR6 = 1119,
4052 WRPGPR_MMR6 = 1120,
4053 TLBINV_MMR6 = 1121,
4054 TLBINVF_MMR6 = 1122,
4055 MFHC0_MMR6 = 1123,
4056 MFC0_MMR6 = 1124,
4057 MFHC2_MMR6_MFC2_MMR6 = 1125,
4058 MTHC0_MMR6 = 1126,
4059 MTC0_MMR6 = 1127,
4060 MTHC2_MMR6_MTC2_MMR6 = 1128,
4061 EVP_MMR6 = 1129,
4062 DVP_MMR6 = 1130,
4063 DI_MMR6 = 1131,
4064 EI_MMR6 = 1132,
4065 EHB_MMR6 = 1133,
4066 PAUSE_MMR6 = 1134,
4067 WAIT_MMR6 = 1135,
4068 CFC2_MM = 1136,
4069 CTC2_MM = 1137,
4070 DMT = 1138,
4071 DVPE = 1139,
4072 EMT = 1140,
4073 EVPE = 1141,
4074 MFTR = 1142,
4075 MTTR = 1143,
4076 YIELD = 1144,
4077 FORK = 1145,
4078 DMFGC0 = 1146,
4079 DMTGC0 = 1147,
4080 HYPCALL_MM = 1148,
4081 TLBGINVF_MM = 1149,
4082 TLBGINV_MM = 1150,
4083 TLBGP_MM = 1151,
4084 TLBGR_MM = 1152,
4085 TLBGWI_MM = 1153,
4086 TLBGWR_MM = 1154,
4087 MFGC0_MM = 1155,
4088 MFHGC0_MM = 1156,
4089 MTGC0_MM = 1157,
4090 MTHGC0_MM = 1158,
4091 SC_MMR6 = 1159,
4092 LL_R6 = 1160,
4093 SC_R6 = 1161,
4094 GINVI = 1162,
4095 GINVT = 1163,
4096 LBE_MM = 1164,
4097 LBuE_MM = 1165,
4098 LHE_MM = 1166,
4099 LHuE_MM = 1167,
4100 LWE_MM = 1168,
4101 LWLE_MM = 1169,
4102 LWRE_MM = 1170,
4103 LLE_MM = 1171,
4104 SBE_MM = 1172,
4105 SB_MM = 1173,
4106 SHE_MM = 1174,
4107 SWE_MM = 1175,
4108 SWLE_MM = 1176,
4109 SWRE_MM = 1177,
4110 SCE_MM = 1178,
4111 PREFE_MM = 1179,
4112 CACHEE_MM = 1180,
4113 Restore16_RestoreX16 = 1181,
4114 LbRxRyOffMemX16 = 1182,
4115 LbuRxRyOffMemX16 = 1183,
4116 LhRxRyOffMemX16 = 1184,
4117 LhuRxRyOffMemX16 = 1185,
4118 LwRxRyOffMemX16_LwRxSpImmX16_LwRxPcTcp16_LwRxPcTcpX16 = 1186,
4119 Save16_SaveX16 = 1187,
4120 SbRxRyOffMemX16 = 1188,
4121 ShRxRyOffMemX16 = 1189,
4122 SwRxRyOffMemX16_SwRxSpImmX16 = 1190,
4123 LBU16_MM_LBu_MM = 1191,
4124 LB_MM = 1192,
4125 LHU16_MM_LHu_MM = 1193,
4126 LH_MM = 1194,
4127 LL_MM = 1195,
4128 LW16_MM_LWGP_MM_LWSP_MM_LW_MM = 1196,
4129 LWL_MM = 1197,
4130 LWM16_MM_LWM32_MM = 1198,
4131 LWP_MM = 1199,
4132 LWR_MM = 1200,
4133 LWU_MM = 1201,
4134 LWXS_MM = 1202,
4135 SB16_MM = 1203,
4136 SC_MM = 1204,
4137 SH16_MM_SH_MM = 1205,
4138 SW16_MM_SWSP_MM_SW_MM = 1206,
4139 SWL_MM = 1207,
4140 SWM16_MM_SWM32_MM = 1208,
4141 SWM_MM = 1209,
4142 SWP_MM = 1210,
4143 SWR_MM = 1211,
4144 PREF_MM_PREFX_MM = 1212,
4145 CACHE_MM = 1213,
4146 SYNC_MM = 1214,
4147 SYNCI_MM = 1215,
4148 GINVI_MMR6 = 1216,
4149 GINVT_MMR6 = 1217,
4150 LBU_MMR6 = 1218,
4151 LB_MMR6 = 1219,
4152 LDC2_MMR6 = 1220,
4153 LL_MMR6 = 1221,
4154 LWM16_MMR6 = 1222,
4155 LWC2_MMR6 = 1223,
4156 LWPC_MMR6 = 1224,
4157 LW_MMR6 = 1225,
4158 SB16_MMR6_SB_MMR6 = 1226,
4159 SDC2_MMR6 = 1227,
4160 SH16_MMR6_SH_MMR6 = 1228,
4161 SW16_MMR6_SWSP_MMR6_SW_MMR6 = 1229,
4162 SWC2_MMR6 = 1230,
4163 SWM16_MMR6 = 1231,
4164 SYNC_MMR6 = 1232,
4165 SYNCI_MMR6 = 1233,
4166 PREF_MMR6 = 1234,
4167 CACHE_MMR6 = 1235,
4168 LL64_LLD = 1236,
4169 LDL = 1237,
4170 LDR = 1238,
4171 SC64_SCD = 1239,
4172 SDL = 1240,
4173 SDR = 1241,
4174 CRC32B = 1242,
4175 CRC32H = 1243,
4176 CRC32W = 1244,
4177 CRC32CB = 1245,
4178 CRC32CH = 1246,
4179 CRC32CW = 1247,
4180 CRC32D = 1248,
4181 CRC32CD = 1249,
4182 BADDu = 1250,
4183 BBIT0_BBIT032_BBIT1_BBIT132 = 1251,
4184 CINS_CINS32_CINS64_32_CINS_i32 = 1252,
4185 DMFC2_OCTEON = 1253,
4186 DMTC2_OCTEON = 1254,
4187 DPOP_POP = 1255,
4188 EXTS_EXTS32 = 1256,
4189 MTM0_MTM1_MTM2_MTP0_MTP1_MTP2 = 1257,
4190 SEQ_SNE = 1258,
4191 SEQi_SNEi = 1259,
4192 V3MULU_VMM0_VMULU = 1260,
4193 DMUL = 1261,
4194 SAA_SAAD = 1262,
4195 ADDR_PS64 = 1263,
4196 CVT_PS_PW64_CVT_PW_PS64 = 1264,
4197 MULR_PS64 = 1265,
4198 MOVT_I64 = 1266,
4199 MOVF_I64 = 1267,
4200 MOVZ_I64_S = 1268,
4201 MOVN_I64_D64 = 1269,
4202 MOVN_I64_S = 1270,
4203 MOVZ_I64_D64 = 1271,
4204 MOVF_D32_MM = 1272,
4205 MOVF_S_MM = 1273,
4206 MOVN_I_D32_MM = 1274,
4207 MOVN_I_S_MM = 1275,
4208 MOVT_D32_MM = 1276,
4209 MOVT_S_MM = 1277,
4210 MOVZ_I_D32_MM = 1278,
4211 MOVZ_I_S_MM = 1279,
4212 CVT_D32_S_MM_CVT_D32_W_MM_CVT_D64_S_MM_CVT_D64_W_MM_CVT_L_D64_MM_CVT_L_S_MM_CVT_S_D32_MM_CVT_S_D64_MM_CVT_S_W_MM_CVT_W_D32_MM_CVT_W_D64_MM_CVT_W_S_MM = 1280,
4213 CEIL_W_MM_CEIL_W_S_MM = 1281,
4214 FLOOR_W_MM_FLOOR_W_S_MM = 1282,
4215 NMADD_S_MM = 1283,
4216 NMADD_D32_MM = 1284,
4217 NMSUB_S_MM = 1285,
4218 NMSUB_D32_MM = 1286,
4219 MADD_S_MM = 1287,
4220 MADD_D32_MM = 1288,
4221 ROUND_W_MM_ROUND_W_S_MM = 1289,
4222 TRUNC_W_MM_TRUNC_W_S_MM = 1290,
4223 C_F_D32_MM_C_F_D64_MM = 1291,
4224 C_F_S_MM = 1292,
4225 C_EQ_D32_MM_C_EQ_D64_MM_C_LE_D32_MM_C_LE_D64_MM_C_LT_D32_MM_C_LT_D64_MM_C_SF_D32_MM_C_SF_D64_MM_C_UN_D32_MM_C_UN_D64_MM = 1293,
4226 C_EQ_S_MM_C_LE_S_MM_C_LT_S_MM_C_SF_S_MM_C_UN_S_MM = 1294,
4227 C_NGE_D32_MM_C_NGE_D64_MM_C_NGL_D32_MM_C_NGL_D64_MM_C_NGT_D32_MM_C_NGT_D64_MM_C_OLE_D32_MM_C_OLE_D64_MM_C_OLT_D32_MM_C_OLT_D64_MM_C_SEQ_D32_MM_C_SEQ_D64_MM_C_UEQ_D32_MM_C_UEQ_D64_MM_C_ULE_D32_MM_C_ULE_D64_MM_C_ULT_D32_MM_C_ULT_D64_MM = 1295,
4228 C_NGE_S_MM_C_NGL_S_MM_C_NGT_S_MM_C_OLE_S_MM_C_OLT_S_MM_C_SEQ_S_MM_C_UEQ_S_MM_C_ULE_S_MM_C_ULT_S_MM = 1296,
4229 C_NGLE_D32_MM_C_NGLE_D64_MM = 1297,
4230 C_NGLE_S_MM = 1298,
4231 FCMP_S32_MM = 1299,
4232 FCMP_D32_MM = 1300,
4233 MFC1_MM = 1301,
4234 MFHC1_D32_MM_MFHC1_D64_MM = 1302,
4235 MTC1_MM_MTC1_D64_MM = 1303,
4236 MTHC1_D32_MM_MTHC1_D64_MM = 1304,
4237 FABS_D32_MM_FABS_D64_MM = 1305,
4238 FABS_S_MM = 1306,
4239 FNEG_D32_MM_FNEG_D64_MM_FNEG_S_MM = 1307,
4240 FADD_D32_MM_FADD_D64_MM = 1308,
4241 FADD_S_MM = 1309,
4242 FMOV_D32_MM_FMOV_D64_MM = 1310,
4243 FMOV_S_MM = 1311,
4244 FMUL_D32_MM_FMUL_D64_MM = 1312,
4245 FMUL_S_MM = 1313,
4246 FSUB_D32_MM_FSUB_D64_MM = 1314,
4247 FSUB_S_MM = 1315,
4248 MSUB_S_MM = 1316,
4249 MSUB_D32_MM = 1317,
4250 FDIV_S_MM = 1318,
4251 FDIV_D32_MM_FDIV_D64_MM = 1319,
4252 FSQRT_S_MM = 1320,
4253 FSQRT_D32_MM_FSQRT_D64_MM = 1321,
4254 RECIP_S_MM_RSQRT_S_MM = 1322,
4255 RECIP_D32_MM_RECIP_D64_MM_RSQRT_D32_MM_RSQRT_D64_MM = 1323,
4256 SDC1_MM_D32_SDC1_MM_D64 = 1324,
4257 SWC1_MM = 1325,
4258 SUXC1_MM = 1326,
4259 SWXC1_MM = 1327,
4260 CFC1_MM = 1328,
4261 CTC1_MM = 1329,
4262 LDC1_MM_D32_LDC1_MM_D64 = 1330,
4263 LUXC1_MM = 1331,
4264 LWC1_MM = 1332,
4265 LWXC1_MM = 1333,
4266 FNEG_S_MMR6 = 1334,
4267 CMP_AF_D_MMR6_CMP_EQ_D_MMR6_CMP_LE_D_MMR6_CMP_LT_D_MMR6_CMP_UN_D_MMR6 = 1335,
4268 CMP_AF_S_MMR6_CMP_EQ_S_MMR6_CMP_LE_S_MMR6_CMP_LT_S_MMR6_CMP_UN_S_MMR6 = 1336,
4269 CMP_SAF_D_MMR6_CMP_SEQ_D_MMR6_CMP_SLE_D_MMR6_CMP_SLT_D_MMR6_CMP_SUN_D_MMR6_CMP_UEQ_D_MMR6_CMP_ULE_D_MMR6_CMP_ULT_D_MMR6 = 1337,
4270 CMP_SAF_S_MMR6_CMP_SEQ_S_MMR6_CMP_SLE_S_MMR6_CMP_SLT_S_MMR6_CMP_SUN_S_MMR6_CMP_UEQ_S_MMR6_CMP_ULE_S_MMR6_CMP_ULT_S_MMR6 = 1338,
4271 CMP_SUEQ_D_MMR6_CMP_SULE_D_MMR6_CMP_SULT_D_MMR6 = 1339,
4272 CMP_SUEQ_S_MMR6_CMP_SULE_S_MMR6_CMP_SULT_S_MMR6 = 1340,
4273 CVT_D_L_MMR6_CVT_L_D_MMR6_CVT_L_S_MMR6_CVT_S_L_MMR6_CVT_S_W_MMR6_CVT_W_S_MMR6 = 1341,
4274 TRUNC_L_D_MMR6_TRUNC_L_S_MMR6_TRUNC_W_D_MMR6_TRUNC_W_S_MMR6 = 1342,
4275 ROUND_L_D_MMR6_ROUND_L_S_MMR6_ROUND_W_D_MMR6_ROUND_W_S_MMR6 = 1343,
4276 FLOOR_L_D_MMR6_FLOOR_L_S_MMR6_FLOOR_W_D_MMR6_FLOOR_W_S_MMR6 = 1344,
4277 CEIL_L_D_MMR6_CEIL_L_S_MMR6_CEIL_W_D_MMR6_CEIL_W_S_MMR6 = 1345,
4278 MFC1_MMR6 = 1346,
4279 MTC1_MMR6 = 1347,
4280 CLASS_S_MMR6_CLASS_D_MMR6 = 1348,
4281 FADD_S_MMR6 = 1349,
4282 MAX_D_MMR6 = 1350,
4283 MAX_S_MMR6 = 1351,
4284 MIN_D_MMR6 = 1352,
4285 MIN_S_MMR6 = 1353,
4286 MAXA_D_MMR6 = 1354,
4287 MAXA_S_MMR6 = 1355,
4288 MINA_D_MMR6 = 1356,
4289 MINA_S_MMR6 = 1357,
4290 SELEQZ_D_MMR6_SELNEZ_D_MMR6 = 1358,
4291 SELEQZ_S_MMR6_SELNEZ_S_MMR6 = 1359,
4292 SEL_D_MMR6 = 1360,
4293 SEL_S_MMR6 = 1361,
4294 RINT_S_MMR6_RINT_D_MMR6 = 1362,
4295 MADDF_D_MMR6 = 1363,
4296 MADDF_S_MMR6 = 1364,
4297 MSUBF_D_MMR6 = 1365,
4298 MSUBF_S_MMR6 = 1366,
4299 FMOV_S_MMR6 = 1367,
4300 FMUL_S_MMR6 = 1368,
4301 FSUB_S_MMR6 = 1369,
4302 FMOV_D_MMR6 = 1370,
4303 FDIV_S_MMR6 = 1371,
4304 SDC1_D64_MMR6 = 1372,
4305 LDC1_D64_MMR6 = 1373,
4306 SWDSP = 1374,
4307 LWDSP = 1375,
4308 PseudoMTLOHI_DSP = 1376,
4309 EXTRV_RS_W = 1377,
4310 EXTRV_R_W = 1378,
4311 EXTRV_S_H = 1379,
4312 EXTRV_W = 1380,
4313 EXTR_RS_W = 1381,
4314 EXTR_R_W = 1382,
4315 EXTR_S_H = 1383,
4316 EXTR_W = 1384,
4317 INSV = 1385,
4318 MTHLIP = 1386,
4319 MTHI_DSP = 1387,
4320 MTLO_DSP = 1388,
4321 ABSQ_S_PH = 1389,
4322 ABSQ_S_W = 1390,
4323 ADDQ_PH = 1391,
4324 ADDQ_S_PH = 1392,
4325 ADDQ_S_W = 1393,
4326 ADDSC = 1394,
4327 ADDU_QB = 1395,
4328 ADDU_S_QB = 1396,
4329 ADDWC = 1397,
4330 BITREV = 1398,
4331 BPOSGE32 = 1399,
4332 CMPGU_EQ_QB = 1400,
4333 CMPGU_LE_QB = 1401,
4334 CMPGU_LT_QB = 1402,
4335 CMPU_EQ_QB = 1403,
4336 CMPU_LE_QB = 1404,
4337 CMPU_LT_QB = 1405,
4338 CMP_EQ_PH = 1406,
4339 CMP_LE_PH = 1407,
4340 CMP_LT_PH = 1408,
4341 DPAQ_SA_L_W = 1409,
4342 DPAQ_S_W_PH = 1410,
4343 DPAU_H_QBL = 1411,
4344 DPAU_H_QBR = 1412,
4345 DPSQ_SA_L_W = 1413,
4346 DPSQ_S_W_PH = 1414,
4347 DPSU_H_QBL = 1415,
4348 DPSU_H_QBR = 1416,
4349 EXTPDPV = 1417,
4350 EXTPDP = 1418,
4351 EXTPV = 1419,
4352 EXTP = 1420,
4353 LBUX = 1421,
4354 LHX = 1422,
4355 LWX = 1423,
4356 MADDU_DSP = 1424,
4357 MADD_DSP = 1425,
4358 MAQ_SA_W_PHL = 1426,
4359 MAQ_SA_W_PHR = 1427,
4360 MAQ_S_W_PHL = 1428,
4361 MAQ_S_W_PHR = 1429,
4362 MFHI_DSP = 1430,
4363 MFLO_DSP = 1431,
4364 MODSUB = 1432,
4365 MSUBU_DSP = 1433,
4366 MSUB_DSP = 1434,
4367 MULEQ_S_W_PHL = 1435,
4368 MULEQ_S_W_PHR = 1436,
4369 MULEU_S_PH_QBL = 1437,
4370 MULEU_S_PH_QBR = 1438,
4371 MULQ_RS_PH = 1439,
4372 MULSAQ_S_W_PH = 1440,
4373 MULTU_DSP = 1441,
4374 MULT_DSP = 1442,
4375 PACKRL_PH = 1443,
4376 PICK_PH = 1444,
4377 PICK_QB = 1445,
4378 PRECEQU_PH_QBLA = 1446,
4379 PRECEQU_PH_QBL = 1447,
4380 PRECEQU_PH_QBRA = 1448,
4381 PRECEQU_PH_QBR = 1449,
4382 PRECEQ_W_PHL = 1450,
4383 PRECEQ_W_PHR = 1451,
4384 PRECEU_PH_QBLA = 1452,
4385 PRECEU_PH_QBL = 1453,
4386 PRECEU_PH_QBRA = 1454,
4387 PRECEU_PH_QBR = 1455,
4388 PRECRQU_S_QB_PH = 1456,
4389 PRECRQ_PH_W = 1457,
4390 PRECRQ_QB_PH = 1458,
4391 PRECRQ_RS_PH_W = 1459,
4392 RADDU_W_QB = 1460,
4393 RDDSP = 1461,
4394 REPLV_PH = 1462,
4395 REPLV_QB = 1463,
4396 REPL_PH = 1464,
4397 REPL_QB = 1465,
4398 SHILOV = 1466,
4399 SHILO = 1467,
4400 SHLLV_PH = 1468,
4401 SHLLV_QB = 1469,
4402 SHLLV_S_PH = 1470,
4403 SHLLV_S_W = 1471,
4404 SHLL_PH = 1472,
4405 SHLL_QB = 1473,
4406 SHLL_S_PH = 1474,
4407 SHLL_S_W = 1475,
4408 SHRAV_PH = 1476,
4409 SHRAV_R_PH = 1477,
4410 SHRAV_R_W = 1478,
4411 SHRA_PH = 1479,
4412 SHRA_R_PH = 1480,
4413 SHRA_R_W = 1481,
4414 SHRLV_QB = 1482,
4415 SHRL_QB = 1483,
4416 SUBQ_PH = 1484,
4417 SUBQ_S_PH = 1485,
4418 SUBQ_S_W = 1486,
4419 SUBU_QB = 1487,
4420 SUBU_S_QB = 1488,
4421 WRDSP = 1489,
4422 PseudoCMPU_EQ_QB_PseudoCMPU_LE_QB_PseudoCMPU_LT_QB_PseudoCMP_EQ_PH_PseudoCMP_LE_PH_PseudoCMP_LT_PH = 1490,
4423 PseudoPICK_PH_PseudoPICK_QB = 1491,
4424 ABSQ_S_QB = 1492,
4425 ADDQH_PH = 1493,
4426 ADDQH_R_PH = 1494,
4427 ADDQH_R_W = 1495,
4428 ADDQH_W = 1496,
4429 ADDUH_QB = 1497,
4430 ADDUH_R_QB = 1498,
4431 ADDU_PH = 1499,
4432 ADDU_S_PH = 1500,
4433 APPEND = 1501,
4434 BALIGN = 1502,
4435 CMPGDU_EQ_QB = 1503,
4436 CMPGDU_LE_QB = 1504,
4437 CMPGDU_LT_QB = 1505,
4438 DPA_W_PH = 1506,
4439 DPAQX_SA_W_PH = 1507,
4440 DPAQX_S_W_PH = 1508,
4441 DPAX_W_PH = 1509,
4442 DPS_W_PH = 1510,
4443 DPSQX_S_W_PH = 1511,
4444 DPSQX_SA_W_PH = 1512,
4445 DPSX_W_PH = 1513,
4446 MUL_PH = 1514,
4447 MUL_S_PH = 1515,
4448 MULQ_RS_W = 1516,
4449 MULQ_S_PH = 1517,
4450 MULQ_S_W = 1518,
4451 MULSA_W_PH = 1519,
4452 PRECR_QB_PH = 1520,
4453 PRECR_SRA_PH_W = 1521,
4454 PRECR_SRA_R_PH_W = 1522,
4455 PREPEND = 1523,
4456 SHRA_QB = 1524,
4457 SHRA_R_QB = 1525,
4458 SHRAV_QB = 1526,
4459 SHRAV_R_QB = 1527,
4460 SHRL_PH = 1528,
4461 SHRLV_PH = 1529,
4462 SUBQH_PH = 1530,
4463 SUBQH_R_PH = 1531,
4464 SUBQH_W = 1532,
4465 SUBQH_R_W = 1533,
4466 SUBU_PH = 1534,
4467 SUBU_S_PH = 1535,
4468 SUBUH_QB = 1536,
4469 SUBUH_R_QB = 1537,
4470 LWDSP_MM = 1538,
4471 SWDSP_MM = 1539,
4472 ABSQ_S_PH_MM = 1540,
4473 ABSQ_S_W_MM = 1541,
4474 ADDQ_PH_MM = 1542,
4475 ADDQ_S_PH_MM = 1543,
4476 ADDQ_S_W_MM = 1544,
4477 ADDSC_MM = 1545,
4478 ADDU_QB_MM = 1546,
4479 ADDU_S_QB_MM = 1547,
4480 ADDWC_MM = 1548,
4481 BITREV_MM = 1549,
4482 BPOSGE32_MM = 1550,
4483 CMPGU_EQ_QB_MM = 1551,
4484 CMPGU_LE_QB_MM = 1552,
4485 CMPGU_LT_QB_MM = 1553,
4486 CMPU_EQ_QB_MM = 1554,
4487 CMPU_LE_QB_MM = 1555,
4488 CMPU_LT_QB_MM = 1556,
4489 CMP_EQ_PH_MM = 1557,
4490 CMP_LE_PH_MM = 1558,
4491 CMP_LT_PH_MM = 1559,
4492 DPAQ_SA_L_W_MM = 1560,
4493 DPAQ_S_W_PH_MM = 1561,
4494 DPAU_H_QBL_MM = 1562,
4495 DPAU_H_QBR_MM = 1563,
4496 DPSQ_SA_L_W_MM = 1564,
4497 DPSQ_S_W_PH_MM = 1565,
4498 DPSU_H_QBL_MM = 1566,
4499 DPSU_H_QBR_MM = 1567,
4500 EXTPDPV_MM = 1568,
4501 EXTPDP_MM = 1569,
4502 EXTPV_MM = 1570,
4503 EXTP_MM = 1571,
4504 EXTRV_RS_W_MM = 1572,
4505 EXTRV_R_W_MM = 1573,
4506 EXTRV_S_H_MM = 1574,
4507 EXTRV_W_MM = 1575,
4508 EXTR_RS_W_MM = 1576,
4509 EXTR_R_W_MM = 1577,
4510 EXTR_S_H_MM = 1578,
4511 EXTR_W_MM = 1579,
4512 INSV_MM = 1580,
4513 LBUX_MM = 1581,
4514 LHX_MM = 1582,
4515 LWX_MM = 1583,
4516 MADDU_DSP_MM = 1584,
4517 MADD_DSP_MM = 1585,
4518 MAQ_SA_W_PHL_MM = 1586,
4519 MAQ_SA_W_PHR_MM = 1587,
4520 MAQ_S_W_PHL_MM = 1588,
4521 MAQ_S_W_PHR_MM = 1589,
4522 MFHI_DSP_MM = 1590,
4523 MFLO_DSP_MM = 1591,
4524 MODSUB_MM = 1592,
4525 MOVEP_MMR6 = 1593,
4526 MOVN_I_MM = 1594,
4527 MOVZ_I_MM = 1595,
4528 MSUBU_DSP_MM = 1596,
4529 MSUB_DSP_MM = 1597,
4530 MTHI_DSP_MM = 1598,
4531 MTHLIP_MM = 1599,
4532 MTLO_DSP_MM = 1600,
4533 MULEQ_S_W_PHL_MM = 1601,
4534 MULEQ_S_W_PHR_MM = 1602,
4535 MULEU_S_PH_QBL_MM = 1603,
4536 MULEU_S_PH_QBR_MM = 1604,
4537 MULQ_RS_PH_MM = 1605,
4538 MULSAQ_S_W_PH_MM = 1606,
4539 MULTU_DSP_MM = 1607,
4540 MULT_DSP_MM = 1608,
4541 PACKRL_PH_MM = 1609,
4542 PICK_PH_MM = 1610,
4543 PICK_QB_MM = 1611,
4544 PRECEQU_PH_QBLA_MM = 1612,
4545 PRECEQU_PH_QBL_MM = 1613,
4546 PRECEQU_PH_QBRA_MM = 1614,
4547 PRECEQU_PH_QBR_MM = 1615,
4548 PRECEQ_W_PHL_MM = 1616,
4549 PRECEQ_W_PHR_MM = 1617,
4550 PRECEU_PH_QBLA_MM = 1618,
4551 PRECEU_PH_QBL_MM = 1619,
4552 PRECEU_PH_QBRA_MM = 1620,
4553 PRECEU_PH_QBR_MM = 1621,
4554 PRECRQU_S_QB_PH_MM = 1622,
4555 PRECRQ_PH_W_MM = 1623,
4556 PRECRQ_QB_PH_MM = 1624,
4557 PRECRQ_RS_PH_W_MM = 1625,
4558 RADDU_W_QB_MM = 1626,
4559 RDDSP_MM = 1627,
4560 REPLV_PH_MM = 1628,
4561 REPLV_QB_MM = 1629,
4562 REPL_PH_MM = 1630,
4563 REPL_QB_MM = 1631,
4564 SHILOV_MM = 1632,
4565 SHILO_MM = 1633,
4566 SHLLV_PH_MM = 1634,
4567 SHLLV_QB_MM = 1635,
4568 SHLLV_S_PH_MM = 1636,
4569 SHLLV_S_W_MM = 1637,
4570 SHLL_PH_MM = 1638,
4571 SHLL_QB_MM = 1639,
4572 SHLL_S_PH_MM = 1640,
4573 SHLL_S_W_MM = 1641,
4574 SHRAV_PH_MM = 1642,
4575 SHRAV_R_PH_MM = 1643,
4576 SHRAV_R_W_MM = 1644,
4577 SHRA_PH_MM = 1645,
4578 SHRA_R_PH_MM = 1646,
4579 SHRA_R_W_MM = 1647,
4580 SHRLV_QB_MM = 1648,
4581 SHRL_QB_MM = 1649,
4582 SUBQ_PH_MM = 1650,
4583 SUBQ_S_PH_MM = 1651,
4584 SUBQ_S_W_MM = 1652,
4585 SUBU_QB_MM = 1653,
4586 SUBU_S_QB_MM = 1654,
4587 WRDSP_MM = 1655,
4588 ABSQ_S_QB_MMR2 = 1656,
4589 ADDQH_PH_MMR2 = 1657,
4590 ADDQH_R_PH_MMR2 = 1658,
4591 ADDQH_R_W_MMR2 = 1659,
4592 ADDQH_W_MMR2 = 1660,
4593 ADDUH_QB_MMR2 = 1661,
4594 ADDUH_R_QB_MMR2 = 1662,
4595 ADDU_PH_MMR2 = 1663,
4596 ADDU_S_PH_MMR2 = 1664,
4597 APPEND_MMR2 = 1665,
4598 BALIGN_MMR2 = 1666,
4599 CMPGDU_EQ_QB_MMR2 = 1667,
4600 CMPGDU_LE_QB_MMR2 = 1668,
4601 CMPGDU_LT_QB_MMR2 = 1669,
4602 DPA_W_PH_MMR2 = 1670,
4603 DPAQX_SA_W_PH_MMR2 = 1671,
4604 DPAQX_S_W_PH_MMR2 = 1672,
4605 DPAX_W_PH_MMR2 = 1673,
4606 DPS_W_PH_MMR2 = 1674,
4607 DPSQX_S_W_PH_MMR2 = 1675,
4608 DPSQX_SA_W_PH_MMR2 = 1676,
4609 DPSX_W_PH_MMR2 = 1677,
4610 MUL_PH_MMR2 = 1678,
4611 MUL_S_PH_MMR2 = 1679,
4612 MULQ_RS_W_MMR2 = 1680,
4613 MULQ_S_PH_MMR2 = 1681,
4614 MULQ_S_W_MMR2 = 1682,
4615 MULSA_W_PH_MMR2 = 1683,
4616 PRECR_QB_PH_MMR2 = 1684,
4617 PRECR_SRA_PH_W_MMR2 = 1685,
4618 PRECR_SRA_R_PH_W_MMR2 = 1686,
4619 PREPEND_MMR2 = 1687,
4620 SHRA_QB_MMR2 = 1688,
4621 SHRA_R_QB_MMR2 = 1689,
4622 SHRAV_QB_MMR2 = 1690,
4623 SHRAV_R_QB_MMR2 = 1691,
4624 SHRL_PH_MMR2 = 1692,
4625 SHRLV_PH_MMR2 = 1693,
4626 SUBQH_PH_MMR2 = 1694,
4627 SUBQH_R_PH_MMR2 = 1695,
4628 SUBQH_W_MMR2 = 1696,
4629 SUBQH_R_W_MMR2 = 1697,
4630 SUBU_PH_MMR2 = 1698,
4631 SUBU_S_PH_MMR2 = 1699,
4632 SUBUH_QB_MMR2 = 1700,
4633 SUBUH_R_QB_MMR2 = 1701,
4634 BPOSGE32C_MMR3 = 1702,
4635 SCHED_LIST_END = 1703
4636 };
4637} // end namespace llvm::Mips::Sched
4638#endif // GET_INSTRINFO_SCHED_ENUM
4639
4640#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
4641namespace llvm {
4642
4643struct MipsInstrTable {
4644 MCInstrDesc Insts[2908];
4645 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
4646 MCOperandInfo OperandInfo[1142];
4647 static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps");
4648 MCPhysReg ImplicitOps[67];
4649};
4650
4651} // end namespace llvm
4652#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
4653
4654#ifdef GET_INSTRINFO_MC_DESC
4655#undef GET_INSTRINFO_MC_DESC
4656namespace llvm {
4657
4658static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0);
4659static constexpr unsigned MipsImpOpBase = sizeof MipsInstrTable::OperandInfo / (sizeof(MCPhysReg));
4660
4661extern const MipsInstrTable MipsDescs = {
4662 {
4663 { 2907, 2, 1, 4, 1144, 0, 0, 152, MipsImpOpBase + 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2907 = YIELD
4664 { 2906, 3, 1, 2, 894, 0, 0, 588, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #2906 = XorRxRxRy16
4665 { 2905, 3, 1, 4, 932, 0, 0, 241, MipsImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // Inst #2905 = XORi_MM
4666 { 2904, 3, 1, 4, 524, 0, 0, 232, MipsImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // Inst #2904 = XORi64
4667 { 2903, 3, 1, 4, 525, 0, 0, 241, MipsImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // Inst #2903 = XORi
4668 { 2902, 3, 1, 4, 791, 0, 0, 551, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2902 = XOR_V
4669 { 2901, 3, 1, 4, 963, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2901 = XOR_MMR6
4670 { 2900, 3, 1, 4, 931, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2900 = XOR_MM
4671 { 2899, 3, 1, 4, 964, 0, 0, 241, MipsImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // Inst #2899 = XORI_MMR6
4672 { 2898, 3, 1, 4, 591, 0, 0, 557, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2898 = XORI_B
4673 { 2897, 3, 1, 4, 524, 0, 0, 235, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2897 = XOR64
4674 { 2896, 3, 1, 2, 963, 0, 0, 573, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2896 = XOR16_MMR6
4675 { 2895, 3, 1, 2, 931, 0, 0, 573, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2895 = XOR16_MM
4676 { 2894, 3, 1, 4, 678, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2894 = XOR
4677 { 2893, 2, 1, 4, 962, 0, 0, 152, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2893 = WSBH_MMR6
4678 { 2892, 2, 1, 4, 930, 0, 0, 152, MipsImpOpBase + 0, 0, 0x1ULL }, // Inst #2892 = WSBH_MM
4679 { 2891, 2, 1, 4, 523, 0, 0, 152, MipsImpOpBase + 0, 0, 0x1ULL }, // Inst #2891 = WSBH
4680 { 2890, 2, 1, 4, 1120, 0, 0, 152, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2890 = WRPGPR_MMR6
4681 { 2889, 2, 0, 4, 1655, 0, 0, 371, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2889 = WRDSP_MM
4682 { 2888, 2, 0, 4, 1489, 0, 0, 371, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2888 = WRDSP
4683 { 2887, 1, 0, 4, 1135, 0, 0, 0, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2887 = WAIT_MMR6
4684 { 2886, 1, 0, 4, 1118, 0, 0, 0, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2886 = WAIT_MM
4685 { 2885, 0, 0, 4, 443, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2885 = WAIT
4686 { 2884, 4, 1, 4, 770, 0, 0, 202, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2884 = VSHF_W
4687 { 2883, 4, 1, 4, 770, 0, 0, 206, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2883 = VSHF_H
4688 { 2882, 4, 1, 4, 770, 0, 0, 198, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2882 = VSHF_D
4689 { 2881, 4, 1, 4, 770, 0, 0, 618, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2881 = VSHF_B
4690 { 2880, 3, 1, 4, 1260, 0, 5, 235, MipsImpOpBase + 62, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2880 = VMULU
4691 { 2879, 3, 1, 4, 1260, 0, 4, 235, MipsImpOpBase + 42, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2879 = VMM0
4692 { 2878, 3, 1, 4, 1260, 0, 3, 235, MipsImpOpBase + 59, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2878 = V3MULU
4693 { 2877, 2, 0, 4, 997, 0, 2, 152, MipsImpOpBase + 7, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2877 = UDIV_MM
4694 { 2876, 2, 0, 4, 753, 0, 2, 152, MipsImpOpBase + 7, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2876 = UDIV
4695 { 2875, 2, 0, 4, 696, 0, 0, 371, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2875 = TTLTIU
4696 { 2874, 2, 1, 4, 1342, 0, 0, 643, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2874 = TRUNC_W_S_MMR6
4697 { 2873, 2, 1, 4, 1290, 0, 0, 643, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2873 = TRUNC_W_S_MM
4698 { 2872, 2, 1, 4, 645, 0, 0, 643, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2872 = TRUNC_W_S
4699 { 2871, 2, 1, 4, 1290, 0, 0, 639, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2871 = TRUNC_W_MM
4700 { 2870, 2, 1, 4, 1342, 0, 0, 641, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2870 = TRUNC_W_D_MMR6
4701 { 2869, 2, 1, 4, 645, 0, 0, 641, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2869 = TRUNC_W_D64
4702 { 2868, 2, 1, 4, 645, 0, 0, 639, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2868 = TRUNC_W_D32
4703 { 2867, 2, 1, 4, 1342, 0, 0, 637, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2867 = TRUNC_L_S_MMR6
4704 { 2866, 2, 1, 4, 645, 0, 0, 637, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2866 = TRUNC_L_S
4705 { 2865, 2, 1, 4, 1342, 0, 0, 635, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2865 = TRUNC_L_D_MMR6
4706 { 2864, 2, 1, 4, 645, 0, 0, 635, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2864 = TRUNC_L_D64
4707 { 2863, 3, 0, 4, 1077, 0, 0, 241, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2863 = TNE_MM
4708 { 2862, 2, 0, 4, 1076, 0, 0, 371, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2862 = TNEI_MM
4709 { 2861, 2, 0, 4, 695, 0, 0, 371, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2861 = TNEI
4710 { 2860, 3, 0, 4, 442, 0, 0, 241, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2860 = TNE
4711 { 2859, 3, 0, 4, 1075, 0, 0, 241, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2859 = TLT_MM
4712 { 2858, 3, 0, 4, 1074, 0, 0, 241, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2858 = TLTU_MM
4713 { 2857, 3, 0, 4, 441, 0, 0, 241, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2857 = TLTU
4714 { 2856, 2, 0, 4, 1073, 0, 0, 371, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2856 = TLTI_MM
4715 { 2855, 2, 0, 4, 1072, 0, 0, 371, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2855 = TLTIU_MM
4716 { 2854, 2, 0, 4, 694, 0, 0, 371, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2854 = TLTI
4717 { 2853, 3, 0, 4, 440, 0, 0, 241, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2853 = TLT
4718 { 2852, 0, 0, 4, 1113, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2852 = TLBWR_MM
4719 { 2851, 0, 0, 4, 379, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2851 = TLBWR
4720 { 2850, 0, 0, 4, 1112, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2850 = TLBWI_MM
4721 { 2849, 0, 0, 4, 378, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2849 = TLBWI
4722 { 2848, 0, 0, 4, 1111, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2848 = TLBR_MM
4723 { 2847, 0, 0, 4, 377, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2847 = TLBR
4724 { 2846, 0, 0, 4, 1110, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2846 = TLBP_MM
4725 { 2845, 0, 0, 4, 376, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2845 = TLBP
4726 { 2844, 0, 0, 4, 1121, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2844 = TLBINV_MMR6
4727 { 2843, 0, 0, 4, 1122, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2843 = TLBINVF_MMR6
4728 { 2842, 0, 0, 4, 381, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2842 = TLBINVF
4729 { 2841, 0, 0, 4, 380, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2841 = TLBINV
4730 { 2840, 0, 0, 4, 1154, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2840 = TLBGWR_MM
4731 { 2839, 0, 0, 4, 710, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2839 = TLBGWR
4732 { 2838, 0, 0, 4, 1153, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2838 = TLBGWI_MM
4733 { 2837, 0, 0, 4, 709, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2837 = TLBGWI
4734 { 2836, 0, 0, 4, 1152, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2836 = TLBGR_MM
4735 { 2835, 0, 0, 4, 708, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2835 = TLBGR
4736 { 2834, 0, 0, 4, 1151, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2834 = TLBGP_MM
4737 { 2833, 0, 0, 4, 707, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2833 = TLBGP
4738 { 2832, 0, 0, 4, 1150, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2832 = TLBGINV_MM
4739 { 2831, 0, 0, 4, 1149, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2831 = TLBGINVF_MM
4740 { 2830, 0, 0, 4, 706, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2830 = TLBGINVF
4741 { 2829, 0, 0, 4, 705, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2829 = TLBGINV
4742 { 2828, 3, 0, 4, 1071, 0, 0, 241, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2828 = TGE_MM
4743 { 2827, 3, 0, 4, 1070, 0, 0, 241, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2827 = TGEU_MM
4744 { 2826, 3, 0, 4, 528, 0, 0, 241, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2826 = TGEU
4745 { 2825, 2, 0, 4, 1069, 0, 0, 371, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2825 = TGEI_MM
4746 { 2824, 2, 0, 4, 1068, 0, 0, 371, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2824 = TGEIU_MM
4747 { 2823, 2, 0, 4, 693, 0, 0, 371, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2823 = TGEIU
4748 { 2822, 2, 0, 4, 692, 0, 0, 371, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2822 = TGEI
4749 { 2821, 3, 0, 4, 527, 0, 0, 241, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2821 = TGE
4750 { 2820, 3, 0, 4, 1067, 0, 0, 241, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2820 = TEQ_MM
4751 { 2819, 2, 0, 4, 1066, 0, 0, 371, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2819 = TEQI_MM
4752 { 2818, 2, 0, 4, 691, 0, 0, 371, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2818 = TEQI
4753 { 2817, 3, 0, 4, 526, 0, 0, 241, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2817 = TEQ
4754 { 2816, 3, 0, 4, 1190, 0, 0, 585, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2816 = SwRxSpImmX16
4755 { 2815, 3, 0, 4, 1190, 0, 0, 926, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2815 = SwRxRyOffMemX16
4756 { 2814, 3, 1, 2, 894, 0, 0, 408, MipsImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #2814 = SubuRxRyRz16
4757 { 2813, 3, 1, 2, 894, 0, 0, 588, MipsImpOpBase + 0, 0, 0x0ULL }, // Inst #2813 = SrlvRxRy16
4758 { 2812, 3, 1, 4, 894, 0, 0, 532, MipsImpOpBase + 0, 0, 0x0ULL }, // Inst #2812 = SrlX16
4759 { 2811, 3, 1, 2, 894, 0, 0, 588, MipsImpOpBase + 0, 0, 0x0ULL }, // Inst #2811 = SravRxRy16
4760 { 2810, 3, 1, 4, 894, 0, 0, 532, MipsImpOpBase + 0, 0, 0x0ULL }, // Inst #2810 = SraX16
4761 { 2809, 2, 0, 2, 894, 0, 1, 406, MipsImpOpBase + 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2809 = SltuRxRy16
4762 { 2808, 2, 0, 4, 894, 0, 1, 580, MipsImpOpBase + 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2808 = SltiuRxImmX16
4763 { 2807, 2, 0, 2, 894, 0, 1, 580, MipsImpOpBase + 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2807 = SltiuRxImm16
4764 { 2806, 2, 0, 4, 894, 0, 1, 580, MipsImpOpBase + 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2806 = SltiRxImmX16
4765 { 2805, 2, 0, 2, 894, 0, 1, 580, MipsImpOpBase + 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2805 = SltiRxImm16
4766 { 2804, 2, 0, 2, 894, 0, 1, 406, MipsImpOpBase + 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2804 = SltRxRy16
4767 { 2803, 3, 1, 2, 894, 0, 0, 588, MipsImpOpBase + 0, 0, 0x0ULL }, // Inst #2803 = SllvRxRy16
4768 { 2802, 3, 1, 4, 894, 0, 0, 532, MipsImpOpBase + 0, 0, 0x0ULL }, // Inst #2802 = SllX16
4769 { 2801, 3, 0, 4, 1189, 0, 0, 926, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2801 = ShRxRyOffMemX16
4770 { 2800, 2, 1, 2, 894, 0, 0, 1140, MipsImpOpBase + 0, 0, 0x0ULL }, // Inst #2800 = SehRx16
4771 { 2799, 2, 1, 2, 894, 0, 0, 1140, MipsImpOpBase + 0, 0, 0x0ULL }, // Inst #2799 = SebRx16
4772 { 2798, 3, 0, 4, 1188, 0, 0, 926, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2798 = SbRxRyOffMemX16
4773 { 2797, 0, 0, 2, 1187, 1, 1, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2797 = SaveX16
4774 { 2796, 0, 0, 2, 1187, 1, 1, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2796 = Save16
4775 { 2795, 1, 0, 4, 1065, 0, 0, 0, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2795 = SYSCALL_MM
4776 { 2794, 1, 0, 4, 424, 0, 0, 0, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2794 = SYSCALL
4777 { 2793, 1, 0, 4, 1232, 0, 0, 0, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2793 = SYNC_MMR6
4778 { 2792, 1, 0, 4, 1214, 0, 0, 0, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2792 = SYNC_MM
4779 { 2791, 2, 0, 4, 1233, 0, 0, 1138, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2791 = SYNCI_MMR6
4780 { 2790, 2, 0, 4, 1215, 0, 0, 1138, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2790 = SYNCI_MM
4781 { 2789, 2, 0, 4, 375, 0, 0, 1138, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2789 = SYNCI
4782 { 2788, 1, 0, 4, 411, 0, 0, 0, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2788 = SYNC
4783 { 2787, 3, 0, 4, 1229, 0, 0, 319, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #2787 = SW_MMR6
4784 { 2786, 3, 0, 4, 1206, 0, 0, 319, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2786 = SW_MM
4785 { 2785, 3, 0, 4, 1327, 0, 0, 923, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // Inst #2785 = SWXC1_MM
4786 { 2784, 3, 0, 4, 882, 0, 0, 923, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // Inst #2784 = SWXC1
4787 { 2783, 3, 0, 2, 1229, 0, 0, 920, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2783 = SWSP_MMR6
4788 { 2782, 3, 0, 2, 1206, 0, 0, 920, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2782 = SWSP_MM
4789 { 2781, 3, 0, 4, 1211, 0, 0, 319, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2781 = SWR_MM
4790 { 2780, 3, 0, 4, 1177, 0, 0, 319, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2780 = SWRE_MM
4791 { 2779, 3, 0, 4, 741, 0, 0, 319, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2779 = SWRE
4792 { 2778, 3, 0, 4, 408, 0, 0, 368, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2778 = SWR64
4793 { 2777, 3, 0, 4, 739, 0, 0, 319, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2777 = SWR
4794 { 2776, 4, 0, 4, 1210, 0, 0, 916, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #2776 = SWP_MM
4795 { 2775, 3, 0, 4, 1208, 0, 0, 361, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #2775 = SWM32_MM
4796 { 2774, 3, 0, 2, 1231, 0, 0, 913, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2774 = SWM16_MMR6
4797 { 2773, 3, 0, 2, 1208, 0, 0, 913, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2773 = SWM16_MM
4798 { 2772, 3, 0, 4, 1207, 0, 0, 319, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2772 = SWL_MM
4799 { 2771, 3, 0, 4, 1176, 0, 0, 319, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2771 = SWLE_MM
4800 { 2770, 3, 0, 4, 740, 0, 0, 319, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2770 = SWLE
4801 { 2769, 3, 0, 4, 407, 0, 0, 368, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2769 = SWL64
4802 { 2768, 3, 0, 4, 738, 0, 0, 319, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2768 = SWL
4803 { 2767, 3, 0, 4, 1175, 0, 0, 319, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #2767 = SWE_MM
4804 { 2766, 3, 0, 4, 736, 0, 0, 319, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2766 = SWE
4805 { 2765, 3, 0, 4, 1539, 0, 0, 903, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #2765 = SWDSP_MM
4806 { 2764, 3, 0, 4, 1374, 0, 0, 903, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #2764 = SWDSP
4807 { 2763, 3, 0, 4, 731, 0, 0, 861, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // Inst #2763 = SWC3
4808 { 2762, 3, 0, 4, 370, 0, 0, 855, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2762 = SWC2_R6
4809 { 2761, 3, 0, 4, 1230, 0, 0, 858, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x6ULL }, // Inst #2761 = SWC2_MMR6
4810 { 2760, 3, 0, 4, 730, 0, 0, 855, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // Inst #2760 = SWC2
4811 { 2759, 3, 0, 4, 1325, 0, 0, 900, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // Inst #2759 = SWC1_MM
4812 { 2758, 3, 0, 4, 369, 0, 0, 900, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // Inst #2758 = SWC1
4813 { 2757, 3, 0, 4, 406, 0, 0, 368, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2757 = SW64
4814 { 2756, 3, 0, 2, 1229, 0, 0, 1072, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2756 = SW16_MMR6
4815 { 2755, 3, 0, 2, 1206, 0, 0, 1072, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2755 = SW16_MM
4816 { 2754, 3, 0, 4, 367, 0, 0, 319, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2754 = SW
4817 { 2753, 3, 0, 4, 1326, 0, 0, 879, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL }, // Inst #2753 = SUXC1_MM
4818 { 2752, 3, 0, 4, 883, 0, 0, 879, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL }, // Inst #2752 = SUXC164
4819 { 2751, 3, 0, 4, 883, 0, 0, 876, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL }, // Inst #2751 = SUXC1
4820 { 2750, 3, 1, 4, 928, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2750 = SUBu_MM
4821 { 2749, 3, 1, 4, 522, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2749 = SUBu
4822 { 2748, 3, 1, 4, 961, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2748 = SUB_MMR6
4823 { 2747, 3, 1, 4, 929, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2747 = SUB_MM
4824 { 2746, 3, 1, 4, 580, 0, 0, 160, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2746 = SUBV_W
4825 { 2745, 3, 1, 4, 580, 0, 0, 157, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2745 = SUBV_H
4826 { 2744, 3, 1, 4, 580, 0, 0, 154, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2744 = SUBV_D
4827 { 2743, 3, 1, 4, 580, 0, 0, 551, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2743 = SUBV_B
4828 { 2742, 3, 1, 4, 829, 0, 0, 566, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2742 = SUBVI_W
4829 { 2741, 3, 1, 4, 829, 0, 0, 563, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2741 = SUBVI_H
4830 { 2740, 3, 1, 4, 829, 0, 0, 560, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2740 = SUBVI_D
4831 { 2739, 3, 1, 4, 829, 0, 0, 557, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2739 = SUBVI_B
4832 { 2738, 3, 1, 4, 1654, 0, 1, 545, MipsImpOpBase + 10, 0, 0x6ULL }, // Inst #2738 = SUBU_S_QB_MM
4833 { 2737, 3, 1, 4, 1488, 0, 1, 545, MipsImpOpBase + 10, 0, 0x6ULL }, // Inst #2737 = SUBU_S_QB
4834 { 2736, 3, 1, 4, 1699, 0, 1, 545, MipsImpOpBase + 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2736 = SUBU_S_PH_MMR2
4835 { 2735, 3, 1, 4, 1535, 0, 1, 545, MipsImpOpBase + 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2735 = SUBU_S_PH
4836 { 2734, 3, 1, 4, 1653, 0, 1, 545, MipsImpOpBase + 10, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2734 = SUBU_QB_MM
4837 { 2733, 3, 1, 4, 1487, 0, 1, 545, MipsImpOpBase + 10, 0, 0x6ULL }, // Inst #2733 = SUBU_QB
4838 { 2732, 3, 1, 4, 1698, 0, 1, 545, MipsImpOpBase + 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2732 = SUBU_PH_MMR2
4839 { 2731, 3, 1, 4, 1534, 0, 1, 545, MipsImpOpBase + 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2731 = SUBU_PH
4840 { 2730, 3, 1, 4, 960, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2730 = SUBU_MMR6
4841 { 2729, 3, 1, 4, 1701, 0, 0, 545, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2729 = SUBUH_R_QB_MMR2
4842 { 2728, 3, 1, 4, 1537, 0, 0, 545, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2728 = SUBUH_R_QB
4843 { 2727, 3, 1, 4, 1700, 0, 0, 545, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2727 = SUBUH_QB_MMR2
4844 { 2726, 3, 1, 4, 1536, 0, 0, 545, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2726 = SUBUH_QB
4845 { 2725, 3, 1, 2, 960, 0, 0, 554, MipsImpOpBase + 0, 0, 0x0ULL }, // Inst #2725 = SUBU16_MMR6
4846 { 2724, 3, 1, 2, 928, 0, 0, 554, MipsImpOpBase + 0, 0, 0x0ULL }, // Inst #2724 = SUBU16_MM
4847 { 2723, 3, 1, 4, 827, 0, 0, 160, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2723 = SUBS_U_W
4848 { 2722, 3, 1, 4, 827, 0, 0, 157, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2722 = SUBS_U_H
4849 { 2721, 3, 1, 4, 827, 0, 0, 154, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2721 = SUBS_U_D
4850 { 2720, 3, 1, 4, 827, 0, 0, 551, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2720 = SUBS_U_B
4851 { 2719, 3, 1, 4, 827, 0, 0, 160, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2719 = SUBS_S_W
4852 { 2718, 3, 1, 4, 827, 0, 0, 157, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2718 = SUBS_S_H
4853 { 2717, 3, 1, 4, 827, 0, 0, 154, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2717 = SUBS_S_D
4854 { 2716, 3, 1, 4, 827, 0, 0, 551, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2716 = SUBS_S_B
4855 { 2715, 3, 1, 4, 828, 0, 0, 160, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2715 = SUBSUU_S_W
4856 { 2714, 3, 1, 4, 828, 0, 0, 157, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2714 = SUBSUU_S_H
4857 { 2713, 3, 1, 4, 828, 0, 0, 154, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2713 = SUBSUU_S_D
4858 { 2712, 3, 1, 4, 828, 0, 0, 551, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2712 = SUBSUU_S_B
4859 { 2711, 3, 1, 4, 583, 0, 0, 160, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2711 = SUBSUS_U_W
4860 { 2710, 3, 1, 4, 583, 0, 0, 157, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2710 = SUBSUS_U_H
4861 { 2709, 3, 1, 4, 583, 0, 0, 154, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2709 = SUBSUS_U_D
4862 { 2708, 3, 1, 4, 583, 0, 0, 551, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2708 = SUBSUS_U_B
4863 { 2707, 3, 1, 4, 1652, 0, 1, 238, MipsImpOpBase + 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2707 = SUBQ_S_W_MM
4864 { 2706, 3, 1, 4, 1486, 0, 1, 238, MipsImpOpBase + 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2706 = SUBQ_S_W
4865 { 2705, 3, 1, 4, 1651, 0, 1, 545, MipsImpOpBase + 10, 0, 0x6ULL }, // Inst #2705 = SUBQ_S_PH_MM
4866 { 2704, 3, 1, 4, 1485, 0, 1, 545, MipsImpOpBase + 10, 0, 0x6ULL }, // Inst #2704 = SUBQ_S_PH
4867 { 2703, 3, 1, 4, 1650, 0, 1, 545, MipsImpOpBase + 10, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2703 = SUBQ_PH_MM
4868 { 2702, 3, 1, 4, 1484, 0, 1, 545, MipsImpOpBase + 10, 0, 0x6ULL }, // Inst #2702 = SUBQ_PH
4869 { 2701, 3, 1, 4, 1696, 0, 0, 238, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2701 = SUBQH_W_MMR2
4870 { 2700, 3, 1, 4, 1532, 0, 0, 238, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2700 = SUBQH_W
4871 { 2699, 3, 1, 4, 1697, 0, 0, 238, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2699 = SUBQH_R_W_MMR2
4872 { 2698, 3, 1, 4, 1533, 0, 0, 238, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2698 = SUBQH_R_W
4873 { 2697, 3, 1, 4, 1695, 0, 0, 545, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2697 = SUBQH_R_PH_MMR2
4874 { 2696, 3, 1, 4, 1531, 0, 0, 545, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2696 = SUBQH_R_PH
4875 { 2695, 3, 1, 4, 1694, 0, 0, 545, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2695 = SUBQH_PH_MMR2
4876 { 2694, 3, 1, 4, 1530, 0, 0, 545, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2694 = SUBQH_PH
4877 { 2693, 3, 1, 4, 521, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2693 = SUB
4878 { 2692, 3, 0, 4, 401, 0, 0, 891, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x6ULL }, // Inst #2692 = ST_W
4879 { 2691, 3, 0, 4, 401, 0, 0, 888, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x6ULL }, // Inst #2691 = ST_H
4880 { 2690, 3, 0, 4, 401, 0, 0, 885, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x6ULL }, // Inst #2690 = ST_D
4881 { 2689, 3, 0, 4, 401, 0, 0, 882, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x6ULL }, // Inst #2689 = ST_B
4882 { 2688, 0, 0, 4, 959, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2688 = SSNOP_MMR6
4883 { 2687, 0, 0, 4, 927, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2687 = SSNOP_MM
4884 { 2686, 0, 0, 4, 520, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2686 = SSNOP
4885 { 2685, 3, 1, 4, 836, 0, 0, 160, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2685 = SRL_W
4886 { 2684, 3, 1, 4, 925, 0, 0, 241, MipsImpOpBase + 0, 0, 0x1ULL }, // Inst #2684 = SRL_MM
4887 { 2683, 3, 1, 4, 836, 0, 0, 157, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2683 = SRL_H
4888 { 2682, 3, 1, 4, 836, 0, 0, 154, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2682 = SRL_D
4889 { 2681, 3, 1, 4, 836, 0, 0, 551, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2681 = SRL_B
4890 { 2680, 3, 1, 4, 926, 0, 0, 238, MipsImpOpBase + 0, 0, 0x1ULL }, // Inst #2680 = SRLV_MM
4891 { 2679, 3, 1, 4, 519, 0, 0, 238, MipsImpOpBase + 0, 0, 0x1ULL }, // Inst #2679 = SRLV
4892 { 2678, 3, 1, 4, 838, 0, 0, 160, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2678 = SRLR_W
4893 { 2677, 3, 1, 4, 838, 0, 0, 157, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2677 = SRLR_H
4894 { 2676, 3, 1, 4, 838, 0, 0, 154, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2676 = SRLR_D
4895 { 2675, 3, 1, 4, 838, 0, 0, 551, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2675 = SRLR_B
4896 { 2674, 3, 1, 4, 838, 0, 0, 566, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2674 = SRLRI_W
4897 { 2673, 3, 1, 4, 838, 0, 0, 563, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2673 = SRLRI_H
4898 { 2672, 3, 1, 4, 838, 0, 0, 560, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2672 = SRLRI_D
4899 { 2671, 3, 1, 4, 838, 0, 0, 557, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2671 = SRLRI_B
4900 { 2670, 3, 1, 4, 836, 0, 0, 566, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2670 = SRLI_W
4901 { 2669, 3, 1, 4, 836, 0, 0, 563, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2669 = SRLI_H
4902 { 2668, 3, 1, 4, 836, 0, 0, 560, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2668 = SRLI_D
4903 { 2667, 3, 1, 4, 836, 0, 0, 557, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2667 = SRLI_B
4904 { 2666, 3, 1, 2, 958, 0, 0, 539, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2666 = SRL16_MMR6
4905 { 2665, 3, 1, 2, 925, 0, 0, 539, MipsImpOpBase + 0, 0, 0x0ULL }, // Inst #2665 = SRL16_MM
4906 { 2664, 3, 1, 4, 518, 0, 0, 241, MipsImpOpBase + 0, 0, 0x1ULL }, // Inst #2664 = SRL
4907 { 2663, 3, 1, 4, 835, 0, 0, 160, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2663 = SRA_W
4908 { 2662, 3, 1, 4, 924, 0, 0, 241, MipsImpOpBase + 0, 0, 0x1ULL }, // Inst #2662 = SRA_MM
4909 { 2661, 3, 1, 4, 835, 0, 0, 157, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2661 = SRA_H
4910 { 2660, 3, 1, 4, 835, 0, 0, 154, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2660 = SRA_D
4911 { 2659, 3, 1, 4, 835, 0, 0, 551, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2659 = SRA_B
4912 { 2658, 3, 1, 4, 923, 0, 0, 238, MipsImpOpBase + 0, 0, 0x1ULL }, // Inst #2658 = SRAV_MM
4913 { 2657, 3, 1, 4, 517, 0, 0, 238, MipsImpOpBase + 0, 0, 0x1ULL }, // Inst #2657 = SRAV
4914 { 2656, 3, 1, 4, 837, 0, 0, 160, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2656 = SRAR_W
4915 { 2655, 3, 1, 4, 837, 0, 0, 157, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2655 = SRAR_H
4916 { 2654, 3, 1, 4, 837, 0, 0, 154, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2654 = SRAR_D
4917 { 2653, 3, 1, 4, 837, 0, 0, 551, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2653 = SRAR_B
4918 { 2652, 3, 1, 4, 837, 0, 0, 566, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2652 = SRARI_W
4919 { 2651, 3, 1, 4, 837, 0, 0, 563, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2651 = SRARI_H
4920 { 2650, 3, 1, 4, 837, 0, 0, 560, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2650 = SRARI_D
4921 { 2649, 3, 1, 4, 837, 0, 0, 557, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2649 = SRARI_B
4922 { 2648, 3, 1, 4, 835, 0, 0, 566, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2648 = SRAI_W
4923 { 2647, 3, 1, 4, 835, 0, 0, 563, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2647 = SRAI_H
4924 { 2646, 3, 1, 4, 835, 0, 0, 560, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2646 = SRAI_D
4925 { 2645, 3, 1, 4, 835, 0, 0, 557, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2645 = SRAI_B
4926 { 2644, 3, 1, 4, 516, 0, 0, 241, MipsImpOpBase + 0, 0, 0x1ULL }, // Inst #2644 = SRA
4927 { 2643, 3, 1, 4, 605, 0, 0, 1135, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2643 = SPLAT_W
4928 { 2642, 3, 1, 4, 605, 0, 0, 1132, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2642 = SPLAT_H
4929 { 2641, 3, 1, 4, 605, 0, 0, 1129, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2641 = SPLAT_D
4930 { 2640, 3, 1, 4, 605, 0, 0, 1126, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2640 = SPLAT_B
4931 { 2639, 3, 1, 4, 606, 0, 0, 566, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2639 = SPLATI_W
4932 { 2638, 3, 1, 4, 606, 0, 0, 563, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2638 = SPLATI_H
4933 { 2637, 3, 1, 4, 606, 0, 0, 560, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2637 = SPLATI_D
4934 { 2636, 3, 1, 4, 606, 0, 0, 557, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2636 = SPLATI_B
4935 { 2635, 3, 1, 4, 1259, 0, 0, 232, MipsImpOpBase + 0, 0, 0x2ULL }, // Inst #2635 = SNEi
4936 { 2634, 3, 1, 4, 1258, 0, 0, 235, MipsImpOpBase + 0, 0, 0x1ULL }, // Inst #2634 = SNE
4937 { 2633, 3, 1, 4, 921, 0, 0, 238, MipsImpOpBase + 0, 0, 0x1ULL }, // Inst #2633 = SLTu_MM
4938 { 2632, 3, 1, 4, 514, 0, 0, 1120, MipsImpOpBase + 0, 0, 0x1ULL }, // Inst #2632 = SLTu64
4939 { 2631, 3, 1, 4, 767, 0, 0, 238, MipsImpOpBase + 0, 0, 0x1ULL }, // Inst #2631 = SLTu
4940 { 2630, 3, 1, 4, 922, 0, 0, 241, MipsImpOpBase + 0, 0, 0x2ULL }, // Inst #2630 = SLTiu_MM
4941 { 2629, 3, 1, 4, 515, 0, 0, 1123, MipsImpOpBase + 0, 0, 0x2ULL }, // Inst #2629 = SLTiu64
4942 { 2628, 3, 1, 4, 677, 0, 0, 241, MipsImpOpBase + 0, 0, 0x2ULL }, // Inst #2628 = SLTiu
4943 { 2627, 3, 1, 4, 922, 0, 0, 241, MipsImpOpBase + 0, 0, 0x2ULL }, // Inst #2627 = SLTi_MM
4944 { 2626, 3, 1, 4, 515, 0, 0, 1123, MipsImpOpBase + 0, 0, 0x2ULL }, // Inst #2626 = SLTi64
4945 { 2625, 3, 1, 4, 677, 0, 0, 241, MipsImpOpBase + 0, 0, 0x2ULL }, // Inst #2625 = SLTi
4946 { 2624, 3, 1, 4, 921, 0, 0, 238, MipsImpOpBase + 0, 0, 0x1ULL }, // Inst #2624 = SLT_MM
4947 { 2623, 3, 1, 4, 514, 0, 0, 1120, MipsImpOpBase + 0, 0, 0x1ULL }, // Inst #2623 = SLT64
4948 { 2622, 3, 1, 4, 767, 0, 0, 238, MipsImpOpBase + 0, 0, 0x1ULL }, // Inst #2622 = SLT
4949 { 2621, 3, 1, 4, 839, 0, 0, 160, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2621 = SLL_W
4950 { 2620, 3, 1, 4, 957, 0, 0, 241, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2620 = SLL_MMR6
4951 { 2619, 3, 1, 4, 919, 0, 0, 241, MipsImpOpBase + 0, 0, 0x1ULL }, // Inst #2619 = SLL_MM
4952 { 2618, 3, 1, 4, 839, 0, 0, 157, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2618 = SLL_H
4953 { 2617, 3, 1, 4, 839, 0, 0, 154, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2617 = SLL_D
4954 { 2616, 3, 1, 4, 839, 0, 0, 551, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2616 = SLL_B
4955 { 2615, 3, 1, 4, 920, 0, 0, 238, MipsImpOpBase + 0, 0, 0x1ULL }, // Inst #2615 = SLLV_MM
4956 { 2614, 3, 1, 4, 513, 0, 0, 238, MipsImpOpBase + 0, 0, 0x1ULL }, // Inst #2614 = SLLV
4957 { 2613, 3, 1, 4, 839, 0, 0, 566, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2613 = SLLI_W
4958 { 2612, 3, 1, 4, 839, 0, 0, 563, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2612 = SLLI_H
4959 { 2611, 3, 1, 4, 839, 0, 0, 560, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2611 = SLLI_D
4960 { 2610, 3, 1, 4, 839, 0, 0, 557, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2610 = SLLI_B
4961 { 2609, 2, 1, 4, 512, 0, 0, 389, MipsImpOpBase + 0, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2609 = SLL64_64
4962 { 2608, 2, 1, 4, 512, 0, 0, 758, MipsImpOpBase + 0, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2608 = SLL64_32
4963 { 2607, 3, 1, 2, 957, 0, 0, 539, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2607 = SLL16_MMR6
4964 { 2606, 3, 1, 2, 919, 0, 0, 539, MipsImpOpBase + 0, 0, 0x0ULL }, // Inst #2606 = SLL16_MM
4965 { 2605, 3, 1, 4, 768, 0, 0, 241, MipsImpOpBase + 0, 0, 0x1ULL }, // Inst #2605 = SLL
4966 { 2604, 4, 1, 4, 774, 0, 0, 1116, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2604 = SLD_W
4967 { 2603, 4, 1, 4, 774, 0, 0, 1112, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2603 = SLD_H
4968 { 2602, 4, 1, 4, 774, 0, 0, 1108, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2602 = SLD_D
4969 { 2601, 4, 1, 4, 774, 0, 0, 1104, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2601 = SLD_B
4970 { 2600, 4, 1, 4, 774, 0, 0, 614, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2600 = SLDI_W
4971 { 2599, 4, 1, 4, 774, 0, 0, 610, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2599 = SLDI_H
4972 { 2598, 4, 1, 4, 774, 0, 0, 606, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2598 = SLDI_D
4973 { 2597, 4, 1, 4, 774, 0, 0, 602, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2597 = SLDI_B
4974 { 2596, 1, 0, 4, 1093, 0, 0, 0, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2596 = SIGRIE_MMR6
4975 { 2595, 1, 0, 4, 1033, 0, 0, 0, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2595 = SIGRIE
4976 { 2594, 3, 0, 4, 1228, 0, 0, 319, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #2594 = SH_MMR6
4977 { 2593, 3, 0, 4, 1205, 0, 0, 319, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2593 = SH_MM
4978 { 2592, 3, 1, 4, 1649, 0, 0, 1101, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2592 = SHRL_QB_MM
4979 { 2591, 3, 1, 4, 1483, 0, 0, 1101, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2591 = SHRL_QB
4980 { 2590, 3, 1, 4, 1692, 0, 0, 1101, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2590 = SHRL_PH_MMR2
4981 { 2589, 3, 1, 4, 1528, 0, 0, 1101, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2589 = SHRL_PH
4982 { 2588, 3, 1, 4, 1648, 0, 0, 1098, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2588 = SHRLV_QB_MM
4983 { 2587, 3, 1, 4, 1482, 0, 0, 1098, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2587 = SHRLV_QB
4984 { 2586, 3, 1, 4, 1693, 0, 0, 1098, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2586 = SHRLV_PH_MMR2
4985 { 2585, 3, 1, 4, 1529, 0, 0, 1098, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2585 = SHRLV_PH
4986 { 2584, 3, 1, 4, 1647, 0, 0, 241, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2584 = SHRA_R_W_MM
4987 { 2583, 3, 1, 4, 1481, 0, 0, 241, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2583 = SHRA_R_W
4988 { 2582, 3, 1, 4, 1689, 0, 0, 1101, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2582 = SHRA_R_QB_MMR2
4989 { 2581, 3, 1, 4, 1525, 0, 0, 1101, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2581 = SHRA_R_QB
4990 { 2580, 3, 1, 4, 1646, 0, 0, 1101, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2580 = SHRA_R_PH_MM
4991 { 2579, 3, 1, 4, 1480, 0, 0, 1101, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2579 = SHRA_R_PH
4992 { 2578, 3, 1, 4, 1688, 0, 0, 1101, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2578 = SHRA_QB_MMR2
4993 { 2577, 3, 1, 4, 1524, 0, 0, 1101, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2577 = SHRA_QB
4994 { 2576, 3, 1, 4, 1645, 0, 0, 1101, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2576 = SHRA_PH_MM
4995 { 2575, 3, 1, 4, 1479, 0, 0, 1101, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2575 = SHRA_PH
4996 { 2574, 3, 1, 4, 1644, 0, 0, 238, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2574 = SHRAV_R_W_MM
4997 { 2573, 3, 1, 4, 1478, 0, 0, 238, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2573 = SHRAV_R_W
4998 { 2572, 3, 1, 4, 1691, 0, 0, 1098, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2572 = SHRAV_R_QB_MMR2
4999 { 2571, 3, 1, 4, 1527, 0, 0, 1098, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2571 = SHRAV_R_QB
5000 { 2570, 3, 1, 4, 1643, 0, 0, 1098, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2570 = SHRAV_R_PH_MM
5001 { 2569, 3, 1, 4, 1477, 0, 0, 1098, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2569 = SHRAV_R_PH
5002 { 2568, 3, 1, 4, 1690, 0, 0, 1098, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2568 = SHRAV_QB_MMR2
5003 { 2567, 3, 1, 4, 1526, 0, 0, 1098, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2567 = SHRAV_QB
5004 { 2566, 3, 1, 4, 1642, 0, 0, 1098, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2566 = SHRAV_PH_MM
5005 { 2565, 3, 1, 4, 1476, 0, 0, 1098, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2565 = SHRAV_PH
5006 { 2564, 3, 1, 4, 1641, 0, 1, 241, MipsImpOpBase + 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2564 = SHLL_S_W_MM
5007 { 2563, 3, 1, 4, 1475, 0, 1, 241, MipsImpOpBase + 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2563 = SHLL_S_W
5008 { 2562, 3, 1, 4, 1640, 0, 1, 1101, MipsImpOpBase + 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2562 = SHLL_S_PH_MM
5009 { 2561, 3, 1, 4, 1474, 0, 1, 1101, MipsImpOpBase + 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2561 = SHLL_S_PH
5010 { 2560, 3, 1, 4, 1639, 0, 1, 1101, MipsImpOpBase + 58, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2560 = SHLL_QB_MM
5011 { 2559, 3, 1, 4, 1473, 0, 1, 1101, MipsImpOpBase + 58, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2559 = SHLL_QB
5012 { 2558, 3, 1, 4, 1638, 0, 1, 1101, MipsImpOpBase + 58, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2558 = SHLL_PH_MM
5013 { 2557, 3, 1, 4, 1472, 0, 1, 1101, MipsImpOpBase + 58, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2557 = SHLL_PH
5014 { 2556, 3, 1, 4, 1637, 0, 1, 238, MipsImpOpBase + 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2556 = SHLLV_S_W_MM
5015 { 2555, 3, 1, 4, 1471, 0, 1, 238, MipsImpOpBase + 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2555 = SHLLV_S_W
5016 { 2554, 3, 1, 4, 1636, 0, 1, 1098, MipsImpOpBase + 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2554 = SHLLV_S_PH_MM
5017 { 2553, 3, 1, 4, 1470, 0, 1, 1098, MipsImpOpBase + 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2553 = SHLLV_S_PH
5018 { 2552, 3, 1, 4, 1635, 0, 1, 1098, MipsImpOpBase + 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2552 = SHLLV_QB_MM
5019 { 2551, 3, 1, 4, 1469, 0, 1, 1098, MipsImpOpBase + 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2551 = SHLLV_QB
5020 { 2550, 3, 1, 4, 1634, 0, 1, 1098, MipsImpOpBase + 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2550 = SHLLV_PH_MM
5021 { 2549, 3, 1, 4, 1468, 0, 1, 1098, MipsImpOpBase + 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2549 = SHLLV_PH
5022 { 2548, 3, 1, 4, 1633, 0, 0, 1095, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2548 = SHILO_MM
5023 { 2547, 3, 1, 4, 1632, 0, 0, 1037, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2547 = SHILOV_MM
5024 { 2546, 3, 1, 4, 1466, 0, 0, 1037, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2546 = SHILOV
5025 { 2545, 3, 1, 4, 1467, 0, 0, 1095, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2545 = SHILO
5026 { 2544, 3, 1, 4, 789, 0, 0, 566, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2544 = SHF_W
5027 { 2543, 3, 1, 4, 789, 0, 0, 563, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2543 = SHF_H
5028 { 2542, 3, 1, 4, 789, 0, 0, 557, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2542 = SHF_B
5029 { 2541, 3, 0, 4, 1174, 0, 0, 319, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #2541 = SHE_MM
5030 { 2540, 3, 0, 4, 735, 0, 0, 319, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2540 = SHE
5031 { 2539, 3, 0, 4, 405, 0, 0, 368, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2539 = SH64
5032 { 2538, 3, 0, 2, 1228, 0, 0, 1072, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2538 = SH16_MMR6
5033 { 2537, 3, 0, 2, 1205, 0, 0, 1072, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2537 = SH16_MM
5034 { 2536, 3, 0, 4, 366, 0, 0, 319, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2536 = SH
5035 { 2535, 3, 1, 4, 1259, 0, 0, 232, MipsImpOpBase + 0, 0, 0x2ULL }, // Inst #2535 = SEQi
5036 { 2534, 3, 1, 4, 1258, 0, 0, 235, MipsImpOpBase + 0, 0, 0x1ULL }, // Inst #2534 = SEQ
5037 { 2533, 4, 1, 4, 1361, 0, 0, 1091, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2533 = SEL_S_MMR6
5038 { 2532, 4, 1, 4, 533, 0, 0, 1091, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2532 = SEL_S
5039 { 2531, 4, 1, 4, 1360, 0, 0, 932, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2531 = SEL_D_MMR6
5040 { 2530, 4, 1, 4, 532, 0, 0, 932, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2530 = SEL_D
5041 { 2529, 3, 1, 4, 1359, 0, 0, 771, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2529 = SELNEZ_S_MMR6
5042 { 2528, 3, 1, 4, 531, 0, 0, 771, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2528 = SELNEZ_S
5043 { 2527, 3, 1, 4, 956, 0, 0, 238, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2527 = SELNEZ_MMR6
5044 { 2526, 3, 1, 4, 1358, 0, 0, 548, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2526 = SELNEZ_D_MMR6
5045 { 2525, 3, 1, 4, 530, 0, 0, 548, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2525 = SELNEZ_D
5046 { 2524, 3, 1, 4, 511, 0, 0, 235, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2524 = SELNEZ64
5047 { 2523, 3, 1, 4, 893, 0, 0, 238, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2523 = SELNEZ
5048 { 2522, 3, 1, 4, 1359, 0, 0, 771, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2522 = SELEQZ_S_MMR6
5049 { 2521, 3, 1, 4, 531, 0, 0, 771, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2521 = SELEQZ_S
5050 { 2520, 3, 1, 4, 956, 0, 0, 238, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2520 = SELEQZ_MMR6
5051 { 2519, 3, 1, 4, 1358, 0, 0, 548, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2519 = SELEQZ_D_MMR6
5052 { 2518, 3, 1, 4, 530, 0, 0, 548, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2518 = SELEQZ_D
5053 { 2517, 3, 1, 4, 511, 0, 0, 235, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2517 = SELEQZ64
5054 { 2516, 3, 1, 4, 893, 0, 0, 238, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2516 = SELEQZ
5055 { 2515, 2, 1, 4, 918, 0, 0, 152, MipsImpOpBase + 0, 0, 0x1ULL }, // Inst #2515 = SEH_MM
5056 { 2514, 2, 1, 4, 510, 0, 0, 389, MipsImpOpBase + 0, 0, 0x1ULL }, // Inst #2514 = SEH64
5057 { 2513, 2, 1, 4, 766, 0, 0, 152, MipsImpOpBase + 0, 0, 0x1ULL }, // Inst #2513 = SEH
5058 { 2512, 2, 1, 4, 917, 0, 0, 152, MipsImpOpBase + 0, 0, 0x1ULL }, // Inst #2512 = SEB_MM
5059 { 2511, 2, 1, 4, 509, 0, 0, 389, MipsImpOpBase + 0, 0, 0x1ULL }, // Inst #2511 = SEB64
5060 { 2510, 2, 1, 4, 765, 0, 0, 152, MipsImpOpBase + 0, 0, 0x1ULL }, // Inst #2510 = SEB
5061 { 2509, 3, 0, 4, 881, 0, 0, 879, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // Inst #2509 = SDXC164
5062 { 2508, 3, 0, 4, 881, 0, 0, 876, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // Inst #2508 = SDXC1
5063 { 2507, 3, 0, 4, 1241, 0, 0, 368, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2507 = SDR
5064 { 2506, 3, 0, 4, 1240, 0, 0, 368, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2506 = SDL
5065 { 2505, 2, 0, 4, 996, 0, 2, 152, MipsImpOpBase + 7, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2505 = SDIV_MM
5066 { 2504, 2, 0, 4, 752, 0, 2, 152, MipsImpOpBase + 7, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2504 = SDIV
5067 { 2503, 3, 0, 4, 372, 0, 0, 861, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // Inst #2503 = SDC3
5068 { 2502, 3, 0, 4, 371, 0, 0, 855, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2502 = SDC2_R6
5069 { 2501, 3, 0, 4, 1227, 0, 0, 858, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x6ULL }, // Inst #2501 = SDC2_MMR6
5070 { 2500, 3, 0, 4, 732, 0, 0, 855, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // Inst #2500 = SDC2
5071 { 2499, 3, 0, 4, 1324, 0, 0, 852, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // Inst #2499 = SDC1_MM_D64
5072 { 2498, 3, 0, 4, 1324, 0, 0, 504, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // Inst #2498 = SDC1_MM_D32
5073 { 2497, 3, 0, 4, 1372, 0, 0, 852, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x6ULL }, // Inst #2497 = SDC1_D64_MMR6
5074 { 2496, 3, 0, 4, 368, 0, 0, 852, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // Inst #2496 = SDC164
5075 { 2495, 3, 0, 4, 368, 0, 0, 504, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // Inst #2495 = SDC1
5076 { 2494, 1, 0, 4, 423, 0, 0, 0, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2494 = SDBBP_R6
5077 { 2493, 1, 0, 4, 1105, 0, 0, 0, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2493 = SDBBP_MMR6
5078 { 2492, 1, 0, 4, 1064, 0, 0, 0, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2492 = SDBBP_MM
5079 { 2491, 1, 0, 2, 1105, 0, 0, 0, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2491 = SDBBP16_MMR6
5080 { 2490, 1, 0, 2, 1064, 0, 0, 0, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2490 = SDBBP16_MM
5081 { 2489, 1, 0, 4, 690, 0, 0, 0, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2489 = SDBBP
5082 { 2488, 3, 0, 4, 365, 0, 0, 368, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2488 = SD
5083 { 2487, 4, 1, 4, 1161, 0, 0, 1079, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2487 = SC_R6
5084 { 2486, 4, 1, 4, 1159, 0, 0, 1075, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2486 = SC_MMR6
5085 { 2485, 4, 1, 4, 1204, 0, 0, 1075, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #2485 = SC_MM
5086 { 2484, 4, 1, 4, 1178, 0, 0, 1075, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #2484 = SCE_MM
5087 { 2483, 4, 1, 4, 737, 0, 0, 1075, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2483 = SCE
5088 { 2482, 4, 1, 4, 374, 0, 0, 1087, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2482 = SCD_R6
5089 { 2481, 4, 1, 4, 1239, 0, 0, 1083, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #2481 = SCD
5090 { 2480, 4, 1, 4, 373, 0, 0, 1079, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2480 = SC64_R6
5091 { 2479, 4, 1, 4, 1239, 0, 0, 1075, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #2479 = SC64
5092 { 2478, 4, 1, 4, 733, 0, 0, 1075, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #2478 = SC
5093 { 2477, 3, 0, 4, 1226, 0, 0, 319, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #2477 = SB_MMR6
5094 { 2476, 3, 0, 4, 1173, 0, 0, 319, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2476 = SB_MM
5095 { 2475, 3, 0, 4, 1172, 0, 0, 319, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #2475 = SBE_MM
5096 { 2474, 3, 0, 4, 734, 0, 0, 319, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2474 = SBE
5097 { 2473, 3, 0, 4, 404, 0, 0, 368, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2473 = SB64
5098 { 2472, 3, 0, 2, 1226, 0, 0, 1072, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2472 = SB16_MMR6
5099 { 2471, 3, 0, 2, 1203, 0, 0, 1072, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2471 = SB16_MM
5100 { 2470, 3, 0, 4, 364, 0, 0, 319, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2470 = SB
5101 { 2469, 3, 1, 4, 589, 0, 0, 566, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2469 = SAT_U_W
5102 { 2468, 3, 1, 4, 589, 0, 0, 563, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2468 = SAT_U_H
5103 { 2467, 3, 1, 4, 589, 0, 0, 560, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2467 = SAT_U_D
5104 { 2466, 3, 1, 4, 589, 0, 0, 557, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2466 = SAT_U_B
5105 { 2465, 3, 1, 4, 589, 0, 0, 566, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2465 = SAT_S_W
5106 { 2464, 3, 1, 4, 589, 0, 0, 563, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2464 = SAT_S_H
5107 { 2463, 3, 1, 4, 589, 0, 0, 560, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2463 = SAT_S_D
5108 { 2462, 3, 1, 4, 589, 0, 0, 557, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2462 = SAT_S_B
5109 { 2461, 2, 0, 4, 1262, 0, 0, 389, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2461 = SAAD
5110 { 2460, 2, 0, 4, 1262, 0, 0, 389, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2460 = SAA
5111 { 2459, 0, 0, 2, 1181, 1, 1, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2459 = RestoreX16
5112 { 2458, 0, 0, 2, 1181, 1, 1, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2458 = Restore16
5113 { 2457, 2, 1, 4, 1322, 0, 0, 643, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2457 = RSQRT_S_MM
5114 { 2456, 2, 1, 4, 576, 0, 0, 643, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2456 = RSQRT_S
5115 { 2455, 2, 1, 4, 1323, 0, 0, 635, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2455 = RSQRT_D64_MM
5116 { 2454, 2, 1, 4, 577, 0, 0, 635, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2454 = RSQRT_D64
5117 { 2453, 2, 1, 4, 1323, 0, 0, 766, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2453 = RSQRT_D32_MM
5118 { 2452, 2, 1, 4, 577, 0, 0, 766, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2452 = RSQRT_D32
5119 { 2451, 2, 1, 4, 1343, 0, 0, 643, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2451 = ROUND_W_S_MMR6
5120 { 2450, 2, 1, 4, 1289, 0, 0, 643, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2450 = ROUND_W_S_MM
5121 { 2449, 2, 1, 4, 647, 0, 0, 643, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2449 = ROUND_W_S
5122 { 2448, 2, 1, 4, 1289, 0, 0, 639, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2448 = ROUND_W_MM
5123 { 2447, 2, 1, 4, 1343, 0, 0, 635, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2447 = ROUND_W_D_MMR6
5124 { 2446, 2, 1, 4, 647, 0, 0, 641, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2446 = ROUND_W_D64
5125 { 2445, 2, 1, 4, 647, 0, 0, 639, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2445 = ROUND_W_D32
5126 { 2444, 2, 1, 4, 1343, 0, 0, 637, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2444 = ROUND_L_S_MMR6
5127 { 2443, 2, 1, 4, 647, 0, 0, 637, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2443 = ROUND_L_S
5128 { 2442, 2, 1, 4, 1343, 0, 0, 635, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2442 = ROUND_L_D_MMR6
5129 { 2441, 2, 1, 4, 647, 0, 0, 635, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2441 = ROUND_L_D64
5130 { 2440, 3, 1, 4, 916, 0, 0, 241, MipsImpOpBase + 0, 0, 0x1ULL }, // Inst #2440 = ROTR_MM
5131 { 2439, 3, 1, 4, 915, 0, 0, 238, MipsImpOpBase + 0, 0, 0x1ULL }, // Inst #2439 = ROTRV_MM
5132 { 2438, 3, 1, 4, 508, 0, 0, 238, MipsImpOpBase + 0, 0, 0x1ULL }, // Inst #2438 = ROTRV
5133 { 2437, 3, 1, 4, 507, 0, 0, 241, MipsImpOpBase + 0, 0, 0x1ULL }, // Inst #2437 = ROTR
5134 { 2436, 2, 1, 4, 1362, 0, 0, 643, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2436 = RINT_S_MMR6
5135 { 2435, 2, 1, 4, 652, 0, 0, 643, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2435 = RINT_S
5136 { 2434, 2, 1, 4, 1362, 0, 0, 635, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2434 = RINT_D_MMR6
5137 { 2433, 2, 1, 4, 651, 0, 0, 635, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2433 = RINT_D
5138 { 2432, 2, 1, 4, 1631, 0, 0, 1070, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2432 = REPL_QB_MM
5139 { 2431, 2, 1, 4, 1465, 0, 0, 1070, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2431 = REPL_QB
5140 { 2430, 2, 1, 4, 1630, 0, 0, 1070, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2430 = REPL_PH_MM
5141 { 2429, 2, 1, 4, 1464, 0, 0, 1070, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2429 = REPL_PH
5142 { 2428, 2, 1, 4, 1629, 0, 0, 1068, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2428 = REPLV_QB_MM
5143 { 2427, 2, 1, 4, 1463, 0, 0, 1068, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2427 = REPLV_QB
5144 { 2426, 2, 1, 4, 1628, 0, 0, 1068, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2426 = REPLV_PH_MM
5145 { 2425, 2, 1, 4, 1462, 0, 0, 1068, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2425 = REPLV_PH
5146 { 2424, 2, 1, 4, 1322, 0, 0, 643, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2424 = RECIP_S_MM
5147 { 2423, 2, 1, 4, 574, 0, 0, 643, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2423 = RECIP_S
5148 { 2422, 2, 1, 4, 1323, 0, 0, 635, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2422 = RECIP_D64_MM
5149 { 2421, 2, 1, 4, 575, 0, 0, 635, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2421 = RECIP_D64
5150 { 2420, 2, 1, 4, 1323, 0, 0, 766, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2420 = RECIP_D32_MM
5151 { 2419, 2, 1, 4, 575, 0, 0, 766, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2419 = RECIP_D32
5152 { 2418, 2, 1, 4, 1119, 0, 0, 152, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2418 = RDPGPR_MMR6
5153 { 2417, 3, 1, 4, 1011, 0, 0, 1062, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2417 = RDHWR_MMR6
5154 { 2416, 3, 1, 4, 1002, 0, 0, 1062, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2416 = RDHWR_MM
5155 { 2415, 3, 1, 4, 535, 0, 0, 1065, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2415 = RDHWR64
5156 { 2414, 3, 1, 4, 749, 0, 0, 1062, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2414 = RDHWR
5157 { 2413, 2, 1, 4, 1627, 0, 0, 371, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #2413 = RDDSP_MM
5158 { 2412, 2, 1, 4, 1461, 0, 0, 371, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #2412 = RDDSP
5159 { 2411, 2, 1, 4, 1626, 0, 0, 1050, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2411 = RADDU_W_QB_MM
5160 { 2410, 2, 1, 4, 1460, 0, 0, 1050, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2410 = RADDU_W_QB
5161 { 2409, 3, 1, 4, 849, 0, 0, 548, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2409 = PUU_PS64
5162 { 2408, 3, 1, 4, 849, 0, 0, 548, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2408 = PUL_PS64
5163 { 2407, 4, 1, 4, 1687, 0, 0, 576, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2407 = PREPEND_MMR2
5164 { 2406, 4, 1, 4, 1523, 0, 0, 576, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2406 = PREPEND
5165 { 2405, 3, 0, 4, 409, 0, 0, 632, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2405 = PREF_R6
5166 { 2404, 3, 0, 4, 1234, 0, 0, 632, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2404 = PREF_MMR6
5167 { 2403, 3, 0, 4, 1212, 0, 0, 632, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2403 = PREF_MM
5168 { 2402, 3, 0, 4, 1212, 0, 0, 1059, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2402 = PREFX_MM
5169 { 2401, 3, 0, 4, 1179, 0, 0, 632, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2401 = PREFE_MM
5170 { 2400, 3, 0, 4, 743, 0, 0, 632, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2400 = PREFE
5171 { 2399, 3, 0, 4, 742, 0, 0, 632, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2399 = PREF
5172 { 2398, 4, 1, 4, 1686, 0, 0, 1055, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2398 = PRECR_SRA_R_PH_W_MMR2
5173 { 2397, 4, 1, 4, 1522, 0, 0, 1055, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2397 = PRECR_SRA_R_PH_W
5174 { 2396, 4, 1, 4, 1685, 0, 0, 1055, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2396 = PRECR_SRA_PH_W_MMR2
5175 { 2395, 4, 1, 4, 1521, 0, 0, 1055, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2395 = PRECR_SRA_PH_W
5176 { 2394, 3, 1, 4, 1684, 0, 0, 545, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2394 = PRECR_QB_PH_MMR2
5177 { 2393, 3, 1, 4, 1520, 0, 0, 545, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2393 = PRECR_QB_PH
5178 { 2392, 3, 1, 4, 1625, 0, 1, 1052, MipsImpOpBase + 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2392 = PRECRQ_RS_PH_W_MM
5179 { 2391, 3, 1, 4, 1459, 0, 1, 1052, MipsImpOpBase + 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2391 = PRECRQ_RS_PH_W
5180 { 2390, 3, 1, 4, 1624, 0, 0, 545, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2390 = PRECRQ_QB_PH_MM
5181 { 2389, 3, 1, 4, 1458, 0, 0, 545, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2389 = PRECRQ_QB_PH
5182 { 2388, 3, 1, 4, 1623, 0, 0, 1052, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2388 = PRECRQ_PH_W_MM
5183 { 2387, 3, 1, 4, 1457, 0, 0, 1052, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2387 = PRECRQ_PH_W
5184 { 2386, 3, 1, 4, 1622, 0, 1, 545, MipsImpOpBase + 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2386 = PRECRQU_S_QB_PH_MM
5185 { 2385, 3, 1, 4, 1456, 0, 1, 545, MipsImpOpBase + 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2385 = PRECRQU_S_QB_PH
5186 { 2384, 2, 1, 4, 1621, 0, 0, 535, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2384 = PRECEU_PH_QBR_MM
5187 { 2383, 2, 1, 4, 1620, 0, 0, 535, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2383 = PRECEU_PH_QBRA_MM
5188 { 2382, 2, 1, 4, 1454, 0, 0, 535, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2382 = PRECEU_PH_QBRA
5189 { 2381, 2, 1, 4, 1455, 0, 0, 535, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2381 = PRECEU_PH_QBR
5190 { 2380, 2, 1, 4, 1619, 0, 0, 535, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2380 = PRECEU_PH_QBL_MM
5191 { 2379, 2, 1, 4, 1618, 0, 0, 535, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2379 = PRECEU_PH_QBLA_MM
5192 { 2378, 2, 1, 4, 1452, 0, 0, 535, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2378 = PRECEU_PH_QBLA
5193 { 2377, 2, 1, 4, 1453, 0, 0, 535, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2377 = PRECEU_PH_QBL
5194 { 2376, 2, 1, 4, 1617, 0, 0, 1050, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2376 = PRECEQ_W_PHR_MM
5195 { 2375, 2, 1, 4, 1451, 0, 0, 1050, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2375 = PRECEQ_W_PHR
5196 { 2374, 2, 1, 4, 1616, 0, 0, 1050, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2374 = PRECEQ_W_PHL_MM
5197 { 2373, 2, 1, 4, 1450, 0, 0, 1050, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2373 = PRECEQ_W_PHL
5198 { 2372, 2, 1, 4, 1615, 0, 0, 535, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2372 = PRECEQU_PH_QBR_MM
5199 { 2371, 2, 1, 4, 1614, 0, 0, 535, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2371 = PRECEQU_PH_QBRA_MM
5200 { 2370, 2, 1, 4, 1448, 0, 0, 535, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2370 = PRECEQU_PH_QBRA
5201 { 2369, 2, 1, 4, 1449, 0, 0, 535, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2369 = PRECEQU_PH_QBR
5202 { 2368, 2, 1, 4, 1613, 0, 0, 535, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2368 = PRECEQU_PH_QBL_MM
5203 { 2367, 2, 1, 4, 1612, 0, 0, 535, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2367 = PRECEQU_PH_QBLA_MM
5204 { 2366, 2, 1, 4, 1446, 0, 0, 535, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2366 = PRECEQU_PH_QBLA
5205 { 2365, 2, 1, 4, 1447, 0, 0, 535, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2365 = PRECEQU_PH_QBL
5206 { 2364, 2, 1, 4, 1255, 0, 0, 152, MipsImpOpBase + 0, 0, 0x1ULL }, // Inst #2364 = POP
5207 { 2363, 3, 1, 4, 849, 0, 0, 548, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2363 = PLU_PS64
5208 { 2362, 3, 1, 4, 849, 0, 0, 548, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2362 = PLL_PS64
5209 { 2361, 3, 1, 4, 1611, 1, 0, 545, MipsImpOpBase + 14, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #2361 = PICK_QB_MM
5210 { 2360, 3, 1, 4, 1445, 1, 0, 545, MipsImpOpBase + 14, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #2360 = PICK_QB
5211 { 2359, 3, 1, 4, 1610, 1, 0, 545, MipsImpOpBase + 14, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #2359 = PICK_PH_MM
5212 { 2358, 3, 1, 4, 1444, 1, 0, 545, MipsImpOpBase + 14, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #2358 = PICK_PH
5213 { 2357, 2, 1, 4, 778, 0, 0, 252, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2357 = PCNT_W
5214 { 2356, 2, 1, 4, 778, 0, 0, 1046, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2356 = PCNT_H
5215 { 2355, 2, 1, 4, 778, 0, 0, 250, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2355 = PCNT_D
5216 { 2354, 2, 1, 4, 778, 0, 0, 968, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2354 = PCNT_B
5217 { 2353, 3, 1, 4, 601, 0, 0, 160, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2353 = PCKOD_W
5218 { 2352, 3, 1, 4, 601, 0, 0, 157, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2352 = PCKOD_H
5219 { 2351, 3, 1, 4, 601, 0, 0, 154, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2351 = PCKOD_D
5220 { 2350, 3, 1, 4, 601, 0, 0, 551, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2350 = PCKOD_B
5221 { 2349, 3, 1, 4, 600, 0, 0, 160, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2349 = PCKEV_W
5222 { 2348, 3, 1, 4, 600, 0, 0, 157, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2348 = PCKEV_H
5223 { 2347, 3, 1, 4, 600, 0, 0, 154, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2347 = PCKEV_D
5224 { 2346, 3, 1, 4, 600, 0, 0, 551, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2346 = PCKEV_B
5225 { 2345, 0, 0, 4, 1134, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2345 = PAUSE_MMR6
5226 { 2344, 0, 0, 4, 1117, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2344 = PAUSE_MM
5227 { 2343, 0, 0, 4, 410, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2343 = PAUSE
5228 { 2342, 3, 1, 4, 1609, 0, 0, 545, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2342 = PACKRL_PH_MM
5229 { 2341, 3, 1, 4, 1443, 0, 0, 545, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2341 = PACKRL_PH
5230 { 2340, 3, 1, 2, 894, 0, 0, 588, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #2340 = OrRxRxRy16
5231 { 2339, 3, 1, 4, 914, 0, 0, 241, MipsImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // Inst #2339 = ORi_MM
5232 { 2338, 3, 1, 4, 967, 0, 0, 232, MipsImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // Inst #2338 = ORi64
5233 { 2337, 3, 1, 4, 506, 0, 0, 241, MipsImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // Inst #2337 = ORi
5234 { 2336, 3, 1, 4, 791, 0, 0, 551, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2336 = OR_V
5235 { 2335, 3, 1, 4, 954, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2335 = OR_MMR6
5236 { 2334, 3, 1, 4, 913, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2334 = OR_MM
5237 { 2333, 3, 1, 4, 955, 0, 0, 241, MipsImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // Inst #2333 = ORI_MMR6
5238 { 2332, 3, 1, 4, 591, 0, 0, 557, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2332 = ORI_B
5239 { 2331, 3, 1, 4, 505, 0, 0, 235, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2331 = OR64
5240 { 2330, 3, 1, 2, 954, 0, 0, 573, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2330 = OR16_MMR6
5241 { 2329, 3, 1, 2, 913, 0, 0, 573, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2329 = OR16_MM
5242 { 2328, 3, 1, 4, 676, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2328 = OR
5243 { 2327, 2, 1, 2, 894, 0, 0, 406, MipsImpOpBase + 0, 0, 0x0ULL }, // Inst #2327 = NotRxRy16
5244 { 2326, 2, 1, 2, 894, 0, 0, 406, MipsImpOpBase + 0, 0, 0x0ULL }, // Inst #2326 = NegRxRy16
5245 { 2325, 2, 1, 2, 953, 0, 0, 1048, MipsImpOpBase + 0, 0, 0x0ULL }, // Inst #2325 = NOT16_MMR6
5246 { 2324, 2, 1, 2, 912, 0, 0, 1048, MipsImpOpBase + 0, 0, 0x0ULL }, // Inst #2324 = NOT16_MM
5247 { 2323, 3, 1, 4, 791, 0, 0, 551, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2323 = NOR_V
5248 { 2322, 3, 1, 4, 952, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x1ULL }, // Inst #2322 = NOR_MMR6
5249 { 2321, 3, 1, 4, 911, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x1ULL }, // Inst #2321 = NOR_MM
5250 { 2320, 3, 1, 4, 591, 0, 0, 557, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2320 = NORI_B
5251 { 2319, 3, 1, 4, 504, 0, 0, 235, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x1ULL }, // Inst #2319 = NOR64
5252 { 2318, 3, 1, 4, 675, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x1ULL }, // Inst #2318 = NOR
5253 { 2317, 4, 1, 4, 1285, 0, 0, 948, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2317 = NMSUB_S_MM
5254 { 2316, 4, 1, 4, 873, 0, 0, 948, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2316 = NMSUB_S
5255 { 2315, 4, 1, 4, 872, 0, 0, 944, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2315 = NMSUB_D64
5256 { 2314, 4, 1, 4, 1286, 0, 0, 940, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2314 = NMSUB_D32_MM
5257 { 2313, 4, 1, 4, 872, 0, 0, 940, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2313 = NMSUB_D32
5258 { 2312, 4, 1, 4, 1283, 0, 0, 948, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2312 = NMADD_S_MM
5259 { 2311, 4, 1, 4, 871, 0, 0, 948, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2311 = NMADD_S
5260 { 2310, 4, 1, 4, 870, 0, 0, 944, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2310 = NMADD_D64
5261 { 2309, 4, 1, 4, 1284, 0, 0, 940, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2309 = NMADD_D32_MM
5262 { 2308, 4, 1, 4, 870, 0, 0, 940, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2308 = NMADD_D32
5263 { 2307, 2, 1, 4, 590, 0, 0, 252, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2307 = NLZC_W
5264 { 2306, 2, 1, 4, 590, 0, 0, 1046, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2306 = NLZC_H
5265 { 2305, 2, 1, 4, 590, 0, 0, 250, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2305 = NLZC_D
5266 { 2304, 2, 1, 4, 590, 0, 0, 968, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2304 = NLZC_B
5267 { 2303, 2, 1, 4, 590, 0, 0, 252, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2303 = NLOC_W
5268 { 2302, 2, 1, 4, 590, 0, 0, 1046, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2302 = NLOC_H
5269 { 2301, 2, 1, 4, 590, 0, 0, 250, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2301 = NLOC_D
5270 { 2300, 2, 1, 4, 590, 0, 0, 968, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2300 = NLOC_B
5271 { 2299, 0, 0, 4, 422, 0, 1, 1, MipsImpOpBase + 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2299 = NAL
5272 { 2298, 2, 1, 2, 894, 0, 0, 1044, MipsImpOpBase + 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2298 = MoveR3216
5273 { 2297, 2, 1, 2, 894, 0, 0, 1042, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2297 = Move32R16
5274 { 2296, 1, 1, 2, 894, 1, 0, 845, MipsImpOpBase + 40, 0, 0x0ULL }, // Inst #2296 = Mflo16
5275 { 2295, 1, 1, 2, 894, 1, 0, 845, MipsImpOpBase + 38, 0|(1ULL<<MCID::MoveReg), 0x0ULL }, // Inst #2295 = Mfhi16
5276 { 2294, 3, 1, 4, 1679, 0, 1, 545, MipsImpOpBase + 57, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2294 = MUL_S_PH_MMR2
5277 { 2293, 3, 1, 4, 1515, 0, 1, 545, MipsImpOpBase + 57, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2293 = MUL_S_PH
5278 { 2292, 3, 1, 4, 542, 0, 0, 238, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2292 = MUL_R6
5279 { 2291, 3, 1, 4, 657, 0, 0, 160, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2291 = MUL_Q_W
5280 { 2290, 3, 1, 4, 657, 0, 0, 157, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2290 = MUL_Q_H
5281 { 2289, 3, 1, 4, 1678, 0, 1, 545, MipsImpOpBase + 57, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2289 = MUL_PH_MMR2
5282 { 2288, 3, 1, 4, 1514, 0, 1, 545, MipsImpOpBase + 57, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2288 = MUL_PH
5283 { 2287, 3, 1, 4, 1006, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2287 = MUL_MMR6
5284 { 2286, 3, 1, 4, 995, 0, 2, 238, MipsImpOpBase + 7, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2286 = MUL_MM
5285 { 2285, 3, 1, 4, 860, 0, 0, 160, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2285 = MULV_W
5286 { 2284, 3, 1, 4, 860, 0, 0, 157, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2284 = MULV_H
5287 { 2283, 3, 1, 4, 860, 0, 0, 154, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2283 = MULV_D
5288 { 2282, 3, 1, 4, 860, 0, 0, 551, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2282 = MULV_B
5289 { 2281, 3, 1, 4, 1005, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2281 = MULU_MMR6
5290 { 2280, 3, 1, 4, 543, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2280 = MULU
5291 { 2279, 2, 0, 4, 990, 0, 2, 152, MipsImpOpBase + 7, 0|(1ULL<<MCID::Commutable), 0x1ULL }, // Inst #2279 = MULTu_MM
5292 { 2278, 2, 0, 4, 756, 0, 2, 152, MipsImpOpBase + 7, 0|(1ULL<<MCID::Commutable), 0x1ULL }, // Inst #2278 = MULTu
5293 { 2277, 2, 0, 4, 989, 0, 2, 152, MipsImpOpBase + 7, 0|(1ULL<<MCID::Commutable), 0x1ULL }, // Inst #2277 = MULT_MM
5294 { 2276, 3, 1, 4, 1608, 0, 0, 448, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #2276 = MULT_DSP_MM
5295 { 2275, 3, 1, 4, 1442, 0, 0, 448, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #2275 = MULT_DSP
5296 { 2274, 3, 1, 4, 1607, 0, 0, 448, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #2274 = MULTU_DSP_MM
5297 { 2273, 3, 1, 4, 1441, 0, 0, 448, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #2273 = MULTU_DSP
5298 { 2272, 2, 0, 4, 755, 0, 2, 152, MipsImpOpBase + 7, 0|(1ULL<<MCID::Commutable), 0x1ULL }, // Inst #2272 = MULT
5299 { 2271, 4, 1, 4, 1683, 0, 0, 751, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2271 = MULSA_W_PH_MMR2
5300 { 2270, 4, 1, 4, 1519, 0, 0, 751, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2270 = MULSA_W_PH
5301 { 2269, 4, 1, 4, 1606, 0, 1, 751, MipsImpOpBase + 22, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2269 = MULSAQ_S_W_PH_MM
5302 { 2268, 4, 1, 4, 1440, 0, 1, 751, MipsImpOpBase + 22, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2268 = MULSAQ_S_W_PH
5303 { 2267, 3, 1, 4, 865, 0, 0, 160, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2267 = MULR_Q_W
5304 { 2266, 3, 1, 4, 865, 0, 0, 157, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2266 = MULR_Q_H
5305 { 2265, 3, 1, 4, 1265, 0, 0, 548, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2265 = MULR_PS64
5306 { 2264, 3, 1, 4, 1682, 0, 1, 238, MipsImpOpBase + 57, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2264 = MULQ_S_W_MMR2
5307 { 2263, 3, 1, 4, 1518, 0, 1, 238, MipsImpOpBase + 57, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2263 = MULQ_S_W
5308 { 2262, 3, 1, 4, 1681, 0, 1, 545, MipsImpOpBase + 57, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2262 = MULQ_S_PH_MMR2
5309 { 2261, 3, 1, 4, 1517, 0, 1, 545, MipsImpOpBase + 57, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2261 = MULQ_S_PH
5310 { 2260, 3, 1, 4, 1680, 0, 1, 238, MipsImpOpBase + 57, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2260 = MULQ_RS_W_MMR2
5311 { 2259, 3, 1, 4, 1516, 0, 1, 238, MipsImpOpBase + 57, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2259 = MULQ_RS_W
5312 { 2258, 3, 1, 4, 1605, 0, 1, 545, MipsImpOpBase + 57, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2258 = MULQ_RS_PH_MM
5313 { 2257, 3, 1, 4, 1439, 0, 1, 545, MipsImpOpBase + 57, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2257 = MULQ_RS_PH
5314 { 2256, 3, 1, 4, 1604, 0, 1, 545, MipsImpOpBase + 57, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2256 = MULEU_S_PH_QBR_MM
5315 { 2255, 3, 1, 4, 1438, 0, 1, 545, MipsImpOpBase + 57, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2255 = MULEU_S_PH_QBR
5316 { 2254, 3, 1, 4, 1603, 0, 1, 545, MipsImpOpBase + 57, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2254 = MULEU_S_PH_QBL_MM
5317 { 2253, 3, 1, 4, 1437, 0, 1, 545, MipsImpOpBase + 57, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2253 = MULEU_S_PH_QBL
5318 { 2252, 3, 1, 4, 1602, 0, 1, 663, MipsImpOpBase + 57, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2252 = MULEQ_S_W_PHR_MM
5319 { 2251, 3, 1, 4, 1436, 0, 1, 663, MipsImpOpBase + 57, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2251 = MULEQ_S_W_PHR
5320 { 2250, 3, 1, 4, 1601, 0, 1, 663, MipsImpOpBase + 57, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2250 = MULEQ_S_W_PHL_MM
5321 { 2249, 3, 1, 4, 1435, 0, 1, 663, MipsImpOpBase + 57, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2249 = MULEQ_S_W_PHL
5322 { 2248, 3, 1, 4, 754, 0, 2, 238, MipsImpOpBase + 7, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2248 = MUL
5323 { 2247, 3, 1, 4, 1004, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2247 = MUH_MMR6
5324 { 2246, 3, 1, 4, 1003, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2246 = MUHU_MMR6
5325 { 2245, 3, 1, 4, 545, 0, 0, 238, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2245 = MUHU
5326 { 2244, 3, 1, 4, 544, 0, 0, 238, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2244 = MUH
5327 { 2243, 5, 1, 4, 1143, 0, 0, 959, MipsImpOpBase + 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2243 = MTTR
5328 { 2242, 1, 0, 4, 1257, 0, 1, 318, MipsImpOpBase + 56, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2242 = MTP2
5329 { 2241, 1, 0, 4, 1257, 0, 1, 318, MipsImpOpBase + 55, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2241 = MTP1
5330 { 2240, 1, 0, 4, 1257, 0, 1, 318, MipsImpOpBase + 54, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2240 = MTP0
5331 { 2239, 1, 0, 4, 1257, 0, 4, 318, MipsImpOpBase + 50, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2239 = MTM2
5332 { 2238, 1, 0, 4, 1257, 0, 4, 318, MipsImpOpBase + 46, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2238 = MTM1
5333 { 2237, 1, 0, 4, 1257, 0, 4, 318, MipsImpOpBase + 42, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2237 = MTM0
5334 { 2236, 1, 0, 4, 1001, 0, 1, 197, MipsImpOpBase + 40, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2236 = MTLO_MM
5335 { 2235, 2, 1, 4, 1600, 0, 0, 1040, MipsImpOpBase + 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2235 = MTLO_DSP_MM
5336 { 2234, 2, 1, 4, 1388, 0, 0, 1040, MipsImpOpBase + 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2234 = MTLO_DSP
5337 { 2233, 1, 0, 4, 1019, 0, 1, 318, MipsImpOpBase + 41, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2233 = MTLO64
5338 { 2232, 1, 0, 4, 761, 0, 1, 197, MipsImpOpBase + 40, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2232 = MTLO
5339 { 2231, 3, 1, 4, 1599, 0, 1, 1037, MipsImpOpBase + 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2231 = MTHLIP_MM
5340 { 2230, 3, 1, 4, 1386, 0, 1, 1037, MipsImpOpBase + 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2230 = MTHLIP
5341 { 2229, 1, 0, 4, 1001, 0, 1, 197, MipsImpOpBase + 38, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2229 = MTHI_MM
5342 { 2228, 2, 1, 4, 1598, 0, 0, 1035, MipsImpOpBase + 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2228 = MTHI_DSP_MM
5343 { 2227, 2, 1, 4, 1387, 0, 0, 1035, MipsImpOpBase + 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2227 = MTHI_DSP
5344 { 2226, 1, 0, 4, 1019, 0, 1, 318, MipsImpOpBase + 39, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2226 = MTHI64
5345 { 2225, 1, 0, 4, 761, 0, 1, 197, MipsImpOpBase + 38, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2225 = MTHI
5346 { 2224, 3, 1, 4, 1158, 0, 0, 401, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2224 = MTHGC0_MM
5347 { 2223, 3, 1, 4, 704, 0, 0, 401, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2223 = MTHGC0
5348 { 2222, 2, 1, 4, 1128, 0, 0, 686, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2222 = MTHC2_MMR6
5349 { 2221, 3, 1, 4, 1304, 0, 0, 1032, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2221 = MTHC1_D64_MM
5350 { 2220, 3, 1, 4, 502, 0, 0, 1032, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2220 = MTHC1_D64
5351 { 2219, 3, 1, 4, 1304, 0, 0, 1029, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2219 = MTHC1_D32_MM
5352 { 2218, 3, 1, 4, 502, 0, 0, 1029, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2218 = MTHC1_D32
5353 { 2217, 3, 1, 4, 1126, 0, 0, 401, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2217 = MTHC0_MMR6
5354 { 2216, 3, 1, 4, 1157, 0, 0, 401, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2216 = MTGC0_MM
5355 { 2215, 3, 1, 4, 703, 0, 0, 401, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2215 = MTGC0
5356 { 2214, 2, 1, 4, 1128, 0, 0, 686, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2214 = MTC2_MMR6
5357 { 2213, 3, 1, 4, 499, 0, 0, 1026, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2213 = MTC2
5358 { 2212, 2, 1, 4, 1347, 0, 0, 404, MipsImpOpBase + 0, 0|(1ULL<<MCID::Bitcast), 0x6ULL }, // Inst #2212 = MTC1_MMR6
5359 { 2211, 2, 1, 4, 1303, 0, 0, 404, MipsImpOpBase + 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL }, // Inst #2211 = MTC1_MM
5360 { 2210, 2, 1, 4, 1303, 0, 0, 418, MipsImpOpBase + 0, 0|(1ULL<<MCID::MoveReg), 0x4ULL }, // Inst #2210 = MTC1_D64_MM
5361 { 2209, 2, 1, 4, 501, 0, 0, 418, MipsImpOpBase + 0, 0|(1ULL<<MCID::MoveReg), 0x4ULL }, // Inst #2209 = MTC1_D64
5362 { 2208, 2, 1, 4, 501, 0, 0, 404, MipsImpOpBase + 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL }, // Inst #2208 = MTC1
5363 { 2207, 3, 1, 4, 1127, 0, 0, 401, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2207 = MTC0_MMR6
5364 { 2206, 3, 1, 4, 498, 0, 0, 401, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2206 = MTC0
5365 { 2205, 4, 1, 4, 1316, 0, 0, 948, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2205 = MSUB_S_MM
5366 { 2204, 4, 1, 4, 869, 0, 0, 948, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2204 = MSUB_S
5367 { 2203, 4, 1, 4, 864, 0, 0, 202, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2203 = MSUB_Q_W
5368 { 2202, 4, 1, 4, 864, 0, 0, 206, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2202 = MSUB_Q_H
5369 { 2201, 2, 0, 4, 993, 2, 2, 152, MipsImpOpBase + 32, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2201 = MSUB_MM
5370 { 2200, 4, 1, 4, 1597, 0, 0, 751, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2200 = MSUB_DSP_MM
5371 { 2199, 4, 1, 4, 1434, 0, 0, 751, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2199 = MSUB_DSP
5372 { 2198, 4, 1, 4, 868, 0, 0, 944, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2198 = MSUB_D64
5373 { 2197, 4, 1, 4, 1317, 0, 0, 940, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2197 = MSUB_D32_MM
5374 { 2196, 4, 1, 4, 868, 0, 0, 940, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2196 = MSUB_D32
5375 { 2195, 4, 1, 4, 858, 0, 0, 202, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2195 = MSUBV_W
5376 { 2194, 4, 1, 4, 858, 0, 0, 206, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2194 = MSUBV_H
5377 { 2193, 4, 1, 4, 858, 0, 0, 198, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2193 = MSUBV_D
5378 { 2192, 4, 1, 4, 858, 0, 0, 618, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2192 = MSUBV_B
5379 { 2191, 2, 0, 4, 994, 2, 2, 152, MipsImpOpBase + 32, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2191 = MSUBU_MM
5380 { 2190, 4, 1, 4, 1596, 0, 0, 751, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2190 = MSUBU_DSP_MM
5381 { 2189, 4, 1, 4, 1433, 0, 0, 751, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2189 = MSUBU_DSP
5382 { 2188, 2, 0, 4, 975, 2, 2, 152, MipsImpOpBase + 32, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2188 = MSUBU
5383 { 2187, 4, 1, 4, 863, 0, 0, 202, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2187 = MSUBR_Q_W
5384 { 2186, 4, 1, 4, 863, 0, 0, 206, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2186 = MSUBR_Q_H
5385 { 2185, 4, 1, 4, 1366, 0, 0, 936, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2185 = MSUBF_S_MMR6
5386 { 2184, 4, 1, 4, 665, 0, 0, 936, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2184 = MSUBF_S
5387 { 2183, 4, 1, 4, 1365, 0, 0, 932, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2183 = MSUBF_D_MMR6
5388 { 2182, 4, 1, 4, 664, 0, 0, 932, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2182 = MSUBF_D
5389 { 2181, 2, 0, 4, 974, 2, 2, 152, MipsImpOpBase + 32, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2181 = MSUB
5390 { 2180, 4, 1, 4, 1279, 0, 0, 1022, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2180 = MOVZ_I_S_MM
5391 { 2179, 4, 1, 4, 888, 0, 0, 1022, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2179 = MOVZ_I_S
5392 { 2178, 4, 1, 4, 1595, 0, 0, 1014, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2178 = MOVZ_I_MM
5393 { 2177, 4, 1, 4, 1021, 0, 0, 1018, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2177 = MOVZ_I_I64
5394 { 2176, 4, 1, 4, 751, 0, 0, 1014, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2176 = MOVZ_I_I
5395 { 2175, 4, 1, 4, 887, 0, 0, 1010, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2175 = MOVZ_I_D64
5396 { 2174, 4, 1, 4, 1278, 0, 0, 1006, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2174 = MOVZ_I_D32_MM
5397 { 2173, 4, 1, 4, 887, 0, 0, 1006, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2173 = MOVZ_I_D32
5398 { 2172, 4, 1, 4, 1268, 0, 0, 1002, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2172 = MOVZ_I64_S
5399 { 2171, 4, 1, 4, 1021, 0, 0, 998, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2171 = MOVZ_I64_I64
5400 { 2170, 4, 1, 4, 1021, 0, 0, 994, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2170 = MOVZ_I64_I
5401 { 2169, 4, 1, 4, 1271, 0, 0, 990, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2169 = MOVZ_I64_D64
5402 { 2168, 4, 1, 4, 1277, 0, 0, 986, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2168 = MOVT_S_MM
5403 { 2167, 4, 1, 4, 784, 0, 0, 986, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2167 = MOVT_S
5404 { 2166, 4, 1, 4, 1000, 0, 0, 978, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2166 = MOVT_I_MM
5405 { 2165, 4, 1, 4, 1266, 0, 0, 982, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2165 = MOVT_I64
5406 { 2164, 4, 1, 4, 880, 0, 0, 978, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2164 = MOVT_I
5407 { 2163, 4, 1, 4, 783, 0, 0, 974, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2163 = MOVT_D64
5408 { 2162, 4, 1, 4, 1276, 0, 0, 970, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2162 = MOVT_D32_MM
5409 { 2161, 4, 1, 4, 783, 0, 0, 970, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2161 = MOVT_D32
5410 { 2160, 4, 1, 4, 1275, 0, 0, 1022, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2160 = MOVN_I_S_MM
5411 { 2159, 4, 1, 4, 886, 0, 0, 1022, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2159 = MOVN_I_S
5412 { 2158, 4, 1, 4, 1594, 0, 0, 1014, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2158 = MOVN_I_MM
5413 { 2157, 4, 1, 4, 1020, 0, 0, 1018, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2157 = MOVN_I_I64
5414 { 2156, 4, 1, 4, 750, 0, 0, 1014, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2156 = MOVN_I_I
5415 { 2155, 4, 1, 4, 885, 0, 0, 1010, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2155 = MOVN_I_D64
5416 { 2154, 4, 1, 4, 1274, 0, 0, 1006, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2154 = MOVN_I_D32_MM
5417 { 2153, 4, 1, 4, 885, 0, 0, 1006, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2153 = MOVN_I_D32
5418 { 2152, 4, 1, 4, 1270, 0, 0, 1002, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2152 = MOVN_I64_S
5419 { 2151, 4, 1, 4, 1020, 0, 0, 998, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2151 = MOVN_I64_I64
5420 { 2150, 4, 1, 4, 1020, 0, 0, 994, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2150 = MOVN_I64_I
5421 { 2149, 4, 1, 4, 1269, 0, 0, 990, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2149 = MOVN_I64_D64
5422 { 2148, 4, 1, 4, 1273, 0, 0, 986, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2148 = MOVF_S_MM
5423 { 2147, 4, 1, 4, 782, 0, 0, 986, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2147 = MOVF_S
5424 { 2146, 4, 1, 4, 999, 0, 0, 978, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2146 = MOVF_I_MM
5425 { 2145, 4, 1, 4, 1267, 0, 0, 982, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2145 = MOVF_I64
5426 { 2144, 4, 1, 4, 879, 0, 0, 978, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2144 = MOVF_I
5427 { 2143, 4, 1, 4, 781, 0, 0, 974, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2143 = MOVF_D64
5428 { 2142, 4, 1, 4, 1272, 0, 0, 970, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2142 = MOVF_D32_MM
5429 { 2141, 4, 1, 4, 781, 0, 0, 970, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2141 = MOVF_D32
5430 { 2140, 2, 1, 4, 790, 0, 0, 968, MipsImpOpBase + 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2140 = MOVE_V
5431 { 2139, 4, 2, 2, 1593, 0, 0, 964, MipsImpOpBase + 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2139 = MOVEP_MMR6
5432 { 2138, 4, 2, 2, 910, 0, 0, 964, MipsImpOpBase + 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2138 = MOVEP_MM
5433 { 2137, 2, 1, 2, 951, 0, 0, 152, MipsImpOpBase + 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2137 = MOVE16_MMR6
5434 { 2136, 2, 1, 2, 909, 0, 0, 152, MipsImpOpBase + 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2136 = MOVE16_MM
5435 { 2135, 3, 1, 4, 557, 0, 0, 160, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2135 = MOD_U_W
5436 { 2134, 3, 1, 4, 557, 0, 0, 157, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2134 = MOD_U_H
5437 { 2133, 3, 1, 4, 557, 0, 0, 154, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2133 = MOD_U_D
5438 { 2132, 3, 1, 4, 557, 0, 0, 551, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2132 = MOD_U_B
5439 { 2131, 3, 1, 4, 557, 0, 0, 160, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2131 = MOD_S_W
5440 { 2130, 3, 1, 4, 557, 0, 0, 157, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2130 = MOD_S_H
5441 { 2129, 3, 1, 4, 557, 0, 0, 154, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2129 = MOD_S_D
5442 { 2128, 3, 1, 4, 557, 0, 0, 551, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2128 = MOD_S_B
5443 { 2127, 3, 1, 4, 1008, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // Inst #2127 = MOD_MMR6
5444 { 2126, 3, 1, 4, 1007, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // Inst #2126 = MODU_MMR6
5445 { 2125, 3, 1, 4, 552, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // Inst #2125 = MODU
5446 { 2124, 3, 1, 4, 1592, 0, 0, 238, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2124 = MODSUB_MM
5447 { 2123, 3, 1, 4, 1432, 0, 0, 238, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2123 = MODSUB
5448 { 2122, 3, 1, 4, 551, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // Inst #2122 = MOD
5449 { 2121, 3, 1, 4, 833, 0, 0, 160, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2121 = MIN_U_W
5450 { 2120, 3, 1, 4, 833, 0, 0, 157, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2120 = MIN_U_H
5451 { 2119, 3, 1, 4, 833, 0, 0, 154, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2119 = MIN_U_D
5452 { 2118, 3, 1, 4, 833, 0, 0, 551, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2118 = MIN_U_B
5453 { 2117, 3, 1, 4, 832, 0, 0, 160, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2117 = MIN_S_W
5454 { 2116, 3, 1, 4, 1353, 0, 0, 771, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2116 = MIN_S_MMR6
5455 { 2115, 3, 1, 4, 832, 0, 0, 157, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2115 = MIN_S_H
5456 { 2114, 3, 1, 4, 832, 0, 0, 154, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2114 = MIN_S_D
5457 { 2113, 3, 1, 4, 832, 0, 0, 551, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2113 = MIN_S_B
5458 { 2112, 3, 1, 4, 587, 0, 0, 771, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2112 = MIN_S
5459 { 2111, 3, 1, 4, 1352, 0, 0, 548, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2111 = MIN_D_MMR6
5460 { 2110, 3, 1, 4, 586, 0, 0, 548, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2110 = MIN_D
5461 { 2109, 3, 1, 4, 834, 0, 0, 160, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2109 = MIN_A_W
5462 { 2108, 3, 1, 4, 834, 0, 0, 157, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2108 = MIN_A_H
5463 { 2107, 3, 1, 4, 834, 0, 0, 154, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2107 = MIN_A_D
5464 { 2106, 3, 1, 4, 834, 0, 0, 551, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2106 = MIN_A_B
5465 { 2105, 3, 1, 4, 588, 0, 0, 566, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2105 = MINI_U_W
5466 { 2104, 3, 1, 4, 588, 0, 0, 563, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2104 = MINI_U_H
5467 { 2103, 3, 1, 4, 588, 0, 0, 560, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2103 = MINI_U_D
5468 { 2102, 3, 1, 4, 588, 0, 0, 557, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2102 = MINI_U_B
5469 { 2101, 3, 1, 4, 588, 0, 0, 566, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2101 = MINI_S_W
5470 { 2100, 3, 1, 4, 588, 0, 0, 563, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2100 = MINI_S_H
5471 { 2099, 3, 1, 4, 588, 0, 0, 560, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2099 = MINI_S_D
5472 { 2098, 3, 1, 4, 588, 0, 0, 557, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2098 = MINI_S_B
5473 { 2097, 3, 1, 4, 1357, 0, 0, 771, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2097 = MINA_S_MMR6
5474 { 2096, 3, 1, 4, 586, 0, 0, 771, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2096 = MINA_S
5475 { 2095, 3, 1, 4, 1356, 0, 0, 548, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2095 = MINA_D_MMR6
5476 { 2094, 3, 1, 4, 587, 0, 0, 548, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2094 = MINA_D
5477 { 2093, 5, 1, 4, 1142, 0, 0, 959, MipsImpOpBase + 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2093 = MFTR
5478 { 2092, 1, 1, 4, 998, 1, 0, 197, MipsImpOpBase + 36, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2092 = MFLO_MM
5479 { 2091, 2, 1, 4, 1591, 0, 0, 382, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2091 = MFLO_DSP_MM
5480 { 2090, 2, 1, 4, 1431, 0, 0, 382, MipsImpOpBase + 0, 0|(1ULL<<MCID::MoveReg), 0x6ULL }, // Inst #2090 = MFLO_DSP
5481 { 2089, 1, 1, 4, 1017, 1, 0, 318, MipsImpOpBase + 37, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2089 = MFLO64
5482 { 2088, 1, 1, 2, 998, 1, 0, 197, MipsImpOpBase + 36, 0|(1ULL<<MCID::MoveReg), 0x0ULL }, // Inst #2088 = MFLO16_MM
5483 { 2087, 1, 1, 4, 748, 1, 0, 197, MipsImpOpBase + 36, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2087 = MFLO
5484 { 2086, 1, 1, 4, 998, 1, 0, 197, MipsImpOpBase + 36, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2086 = MFHI_MM
5485 { 2085, 2, 1, 4, 1590, 0, 0, 382, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2085 = MFHI_DSP_MM
5486 { 2084, 2, 1, 4, 1430, 0, 0, 382, MipsImpOpBase + 0, 0|(1ULL<<MCID::MoveReg), 0x6ULL }, // Inst #2084 = MFHI_DSP
5487 { 2083, 1, 1, 4, 1017, 1, 0, 318, MipsImpOpBase + 37, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2083 = MFHI64
5488 { 2082, 1, 1, 2, 998, 1, 0, 197, MipsImpOpBase + 36, 0|(1ULL<<MCID::MoveReg), 0x0ULL }, // Inst #2082 = MFHI16_MM
5489 { 2081, 1, 1, 4, 748, 1, 0, 197, MipsImpOpBase + 36, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2081 = MFHI
5490 { 2080, 3, 1, 4, 1156, 0, 0, 384, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2080 = MFHGC0_MM
5491 { 2079, 3, 1, 4, 702, 0, 0, 384, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2079 = MFHGC0
5492 { 2078, 2, 1, 4, 1125, 0, 0, 647, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2078 = MFHC2_MMR6
5493 { 2077, 2, 1, 4, 1302, 0, 0, 952, MipsImpOpBase + 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2077 = MFHC1_D64_MM
5494 { 2076, 2, 1, 4, 500, 0, 0, 952, MipsImpOpBase + 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2076 = MFHC1_D64
5495 { 2075, 2, 1, 4, 1302, 0, 0, 957, MipsImpOpBase + 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2075 = MFHC1_D32_MM
5496 { 2074, 2, 1, 4, 500, 0, 0, 957, MipsImpOpBase + 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2074 = MFHC1_D32
5497 { 2073, 3, 1, 4, 1123, 0, 0, 384, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2073 = MFHC0_MMR6
5498 { 2072, 3, 1, 4, 1155, 0, 0, 384, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2072 = MFGC0_MM
5499 { 2071, 3, 1, 4, 701, 0, 0, 384, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2071 = MFGC0
5500 { 2070, 2, 1, 4, 1125, 0, 0, 647, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2070 = MFC2_MMR6
5501 { 2069, 3, 1, 4, 497, 0, 0, 954, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2069 = MFC2
5502 { 2068, 2, 1, 4, 1346, 0, 0, 387, MipsImpOpBase + 0, 0|(1ULL<<MCID::Bitcast), 0x6ULL }, // Inst #2068 = MFC1_MMR6
5503 { 2067, 2, 1, 4, 1301, 0, 0, 387, MipsImpOpBase + 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL }, // Inst #2067 = MFC1_MM
5504 { 2066, 2, 1, 4, 495, 0, 0, 952, MipsImpOpBase + 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2066 = MFC1_D64
5505 { 2065, 2, 1, 4, 495, 0, 0, 387, MipsImpOpBase + 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL }, // Inst #2065 = MFC1
5506 { 2064, 3, 1, 4, 1124, 0, 0, 384, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2064 = MFC0_MMR6
5507 { 2063, 3, 1, 4, 496, 0, 0, 384, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2063 = MFC0
5508 { 2062, 3, 1, 4, 833, 0, 0, 160, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2062 = MAX_U_W
5509 { 2061, 3, 1, 4, 833, 0, 0, 157, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2061 = MAX_U_H
5510 { 2060, 3, 1, 4, 833, 0, 0, 154, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2060 = MAX_U_D
5511 { 2059, 3, 1, 4, 833, 0, 0, 551, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2059 = MAX_U_B
5512 { 2058, 3, 1, 4, 832, 0, 0, 160, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2058 = MAX_S_W
5513 { 2057, 3, 1, 4, 1351, 0, 0, 771, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2057 = MAX_S_MMR6
5514 { 2056, 3, 1, 4, 832, 0, 0, 157, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2056 = MAX_S_H
5515 { 2055, 3, 1, 4, 832, 0, 0, 154, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2055 = MAX_S_D
5516 { 2054, 3, 1, 4, 832, 0, 0, 551, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2054 = MAX_S_B
5517 { 2053, 3, 1, 4, 585, 0, 0, 771, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2053 = MAX_S
5518 { 2052, 3, 1, 4, 1350, 0, 0, 548, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2052 = MAX_D_MMR6
5519 { 2051, 3, 1, 4, 584, 0, 0, 548, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2051 = MAX_D
5520 { 2050, 3, 1, 4, 834, 0, 0, 160, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2050 = MAX_A_W
5521 { 2049, 3, 1, 4, 834, 0, 0, 157, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2049 = MAX_A_H
5522 { 2048, 3, 1, 4, 834, 0, 0, 154, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2048 = MAX_A_D
5523 { 2047, 3, 1, 4, 834, 0, 0, 551, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2047 = MAX_A_B
5524 { 2046, 3, 1, 4, 588, 0, 0, 566, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2046 = MAXI_U_W
5525 { 2045, 3, 1, 4, 588, 0, 0, 563, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2045 = MAXI_U_H
5526 { 2044, 3, 1, 4, 588, 0, 0, 560, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2044 = MAXI_U_D
5527 { 2043, 3, 1, 4, 588, 0, 0, 557, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2043 = MAXI_U_B
5528 { 2042, 3, 1, 4, 588, 0, 0, 566, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2042 = MAXI_S_W
5529 { 2041, 3, 1, 4, 588, 0, 0, 563, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2041 = MAXI_S_H
5530 { 2040, 3, 1, 4, 588, 0, 0, 560, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2040 = MAXI_S_D
5531 { 2039, 3, 1, 4, 588, 0, 0, 557, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2039 = MAXI_S_B
5532 { 2038, 3, 1, 4, 1355, 0, 0, 771, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2038 = MAXA_S_MMR6
5533 { 2037, 3, 1, 4, 585, 0, 0, 771, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2037 = MAXA_S
5534 { 2036, 3, 1, 4, 1354, 0, 0, 548, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2036 = MAXA_D_MMR6
5535 { 2035, 3, 1, 4, 584, 0, 0, 548, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2035 = MAXA_D
5536 { 2034, 4, 1, 4, 1589, 0, 1, 751, MipsImpOpBase + 22, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2034 = MAQ_S_W_PHR_MM
5537 { 2033, 4, 1, 4, 1429, 0, 1, 751, MipsImpOpBase + 22, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2033 = MAQ_S_W_PHR
5538 { 2032, 4, 1, 4, 1588, 0, 1, 751, MipsImpOpBase + 22, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2032 = MAQ_S_W_PHL_MM
5539 { 2031, 4, 1, 4, 1428, 0, 1, 751, MipsImpOpBase + 22, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2031 = MAQ_S_W_PHL
5540 { 2030, 4, 1, 4, 1587, 0, 1, 751, MipsImpOpBase + 22, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2030 = MAQ_SA_W_PHR_MM
5541 { 2029, 4, 1, 4, 1427, 0, 1, 751, MipsImpOpBase + 22, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2029 = MAQ_SA_W_PHR
5542 { 2028, 4, 1, 4, 1586, 0, 1, 751, MipsImpOpBase + 22, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2028 = MAQ_SA_W_PHL_MM
5543 { 2027, 4, 1, 4, 1426, 0, 1, 751, MipsImpOpBase + 22, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2027 = MAQ_SA_W_PHL
5544 { 2026, 4, 1, 4, 1287, 0, 0, 948, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2026 = MADD_S_MM
5545 { 2025, 4, 1, 4, 867, 0, 0, 948, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2025 = MADD_S
5546 { 2024, 4, 1, 4, 862, 0, 0, 202, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2024 = MADD_Q_W
5547 { 2023, 4, 1, 4, 862, 0, 0, 206, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2023 = MADD_Q_H
5548 { 2022, 2, 0, 4, 991, 2, 2, 152, MipsImpOpBase + 32, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2022 = MADD_MM
5549 { 2021, 4, 1, 4, 1585, 0, 0, 751, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2021 = MADD_DSP_MM
5550 { 2020, 4, 1, 4, 1425, 0, 0, 751, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2020 = MADD_DSP
5551 { 2019, 4, 1, 4, 866, 0, 0, 944, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2019 = MADD_D64
5552 { 2018, 4, 1, 4, 1288, 0, 0, 940, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2018 = MADD_D32_MM
5553 { 2017, 4, 1, 4, 866, 0, 0, 940, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #2017 = MADD_D32
5554 { 2016, 4, 1, 4, 859, 0, 0, 202, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2016 = MADDV_W
5555 { 2015, 4, 1, 4, 859, 0, 0, 206, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2015 = MADDV_H
5556 { 2014, 4, 1, 4, 859, 0, 0, 198, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2014 = MADDV_D
5557 { 2013, 4, 1, 4, 859, 0, 0, 618, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2013 = MADDV_B
5558 { 2012, 2, 0, 4, 992, 2, 2, 152, MipsImpOpBase + 32, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2012 = MADDU_MM
5559 { 2011, 4, 1, 4, 1584, 0, 0, 751, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2011 = MADDU_DSP_MM
5560 { 2010, 4, 1, 4, 1424, 0, 0, 751, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2010 = MADDU_DSP
5561 { 2009, 2, 0, 4, 973, 2, 2, 152, MipsImpOpBase + 32, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2009 = MADDU
5562 { 2008, 4, 1, 4, 861, 0, 0, 202, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2008 = MADDR_Q_W
5563 { 2007, 4, 1, 4, 861, 0, 0, 206, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #2007 = MADDR_Q_H
5564 { 2006, 4, 1, 4, 1364, 0, 0, 936, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2006 = MADDF_S_MMR6
5565 { 2005, 4, 1, 4, 667, 0, 0, 936, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2005 = MADDF_S
5566 { 2004, 4, 1, 4, 1363, 0, 0, 932, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2004 = MADDF_D_MMR6
5567 { 2003, 4, 1, 4, 666, 0, 0, 932, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2003 = MADDF_D
5568 { 2002, 2, 0, 4, 972, 2, 2, 152, MipsImpOpBase + 32, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2002 = MADD
5569 { 2001, 3, 1, 4, 1186, 0, 0, 585, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #2001 = LwRxSpImmX16
5570 { 2000, 3, 1, 4, 1186, 0, 0, 926, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2000 = LwRxRyOffMemX16
5571 { 1999, 3, 1, 4, 1186, 0, 0, 929, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1999 = LwRxPcTcpX16
5572 { 1998, 3, 1, 2, 1186, 0, 0, 929, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1998 = LwRxPcTcp16
5573 { 1997, 2, 1, 4, 894, 0, 0, 580, MipsImpOpBase + 0, 0, 0x0ULL }, // Inst #1997 = LiRxImmX16
5574 { 1996, 2, 1, 4, 894, 0, 0, 580, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1996 = LiRxImmAlignX16
5575 { 1995, 2, 1, 2, 894, 0, 0, 580, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1995 = LiRxImm16
5576 { 1994, 3, 1, 4, 1185, 0, 0, 926, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1994 = LhuRxRyOffMemX16
5577 { 1993, 3, 1, 4, 1184, 0, 0, 926, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1993 = LhRxRyOffMemX16
5578 { 1992, 3, 1, 4, 1183, 0, 0, 926, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1992 = LbuRxRyOffMemX16
5579 { 1991, 3, 1, 4, 1182, 0, 0, 926, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1991 = LbRxRyOffMemX16
5580 { 1990, 3, 1, 4, 389, 0, 0, 368, MipsImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1990 = LWu
5581 { 1989, 3, 1, 4, 1225, 0, 0, 319, MipsImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1989 = LW_MMR6
5582 { 1988, 3, 1, 4, 1196, 0, 0, 319, MipsImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1988 = LW_MM
5583 { 1987, 3, 1, 4, 1583, 0, 0, 849, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1987 = LWX_MM
5584 { 1986, 3, 1, 4, 1202, 0, 0, 849, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL }, // Inst #1986 = LWXS_MM
5585 { 1985, 3, 1, 4, 1333, 0, 0, 923, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // Inst #1985 = LWXC1_MM
5586 { 1984, 3, 1, 4, 890, 0, 0, 923, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // Inst #1984 = LWXC1
5587 { 1983, 3, 1, 4, 1423, 0, 0, 849, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1983 = LWX
5588 { 1982, 3, 1, 4, 1201, 0, 0, 319, MipsImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1982 = LWU_MM
5589 { 1981, 2, 1, 4, 399, 0, 0, 371, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1981 = LWUPC
5590 { 1980, 3, 1, 2, 1196, 0, 0, 920, MipsImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1980 = LWSP_MM
5591 { 1979, 4, 1, 4, 1200, 0, 0, 909, MipsImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1979 = LWR_MM
5592 { 1978, 4, 1, 4, 1170, 0, 0, 909, MipsImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1978 = LWRE_MM
5593 { 1977, 4, 1, 4, 729, 0, 0, 909, MipsImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1977 = LWRE
5594 { 1976, 4, 1, 4, 403, 0, 0, 872, MipsImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1976 = LWR64
5595 { 1975, 4, 1, 4, 727, 0, 0, 909, MipsImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1975 = LWR
5596 { 1974, 4, 2, 4, 1199, 0, 0, 916, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1974 = LWP_MM
5597 { 1973, 2, 1, 4, 1224, 0, 0, 371, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1973 = LWPC_MMR6
5598 { 1972, 2, 1, 4, 398, 0, 0, 371, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1972 = LWPC
5599 { 1971, 3, 1, 4, 1198, 0, 0, 361, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1971 = LWM32_MM
5600 { 1970, 3, 1, 2, 1222, 0, 0, 913, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1970 = LWM16_MMR6
5601 { 1969, 3, 1, 2, 1198, 0, 0, 913, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1969 = LWM16_MM
5602 { 1968, 4, 1, 4, 1197, 0, 0, 909, MipsImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1968 = LWL_MM
5603 { 1967, 4, 1, 4, 1169, 0, 0, 909, MipsImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1967 = LWLE_MM
5604 { 1966, 4, 1, 4, 728, 0, 0, 909, MipsImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1966 = LWLE
5605 { 1965, 4, 1, 4, 402, 0, 0, 872, MipsImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1965 = LWL64
5606 { 1964, 4, 1, 4, 726, 0, 0, 909, MipsImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1964 = LWL
5607 { 1963, 3, 1, 2, 1196, 0, 0, 906, MipsImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1963 = LWGP_MM
5608 { 1962, 3, 1, 4, 1168, 0, 0, 319, MipsImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1962 = LWE_MM
5609 { 1961, 3, 1, 4, 724, 0, 0, 319, MipsImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1961 = LWE
5610 { 1960, 3, 1, 4, 1538, 0, 0, 903, MipsImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1960 = LWDSP_MM
5611 { 1959, 3, 1, 4, 1375, 0, 0, 903, MipsImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1959 = LWDSP
5612 { 1958, 3, 1, 4, 718, 0, 0, 861, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // Inst #1958 = LWC3
5613 { 1957, 3, 1, 4, 395, 0, 0, 855, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1957 = LWC2_R6
5614 { 1956, 3, 1, 4, 1223, 0, 0, 858, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1956 = LWC2_MMR6
5615 { 1955, 3, 1, 4, 717, 0, 0, 855, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // Inst #1955 = LWC2
5616 { 1954, 3, 1, 4, 1332, 0, 0, 900, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // Inst #1954 = LWC1_MM
5617 { 1953, 3, 1, 4, 391, 0, 0, 900, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // Inst #1953 = LWC1
5618 { 1952, 3, 1, 4, 388, 0, 0, 368, MipsImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1952 = LW64
5619 { 1951, 3, 1, 2, 1196, 0, 0, 846, MipsImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1951 = LW16_MM
5620 { 1950, 3, 1, 4, 715, 0, 0, 319, MipsImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1950 = LW
5621 { 1949, 2, 1, 4, 908, 0, 0, 371, MipsImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL }, // Inst #1949 = LUi_MM
5622 { 1948, 2, 1, 4, 494, 0, 0, 366, MipsImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL }, // Inst #1948 = LUi64
5623 { 1947, 2, 1, 4, 674, 0, 0, 371, MipsImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL }, // Inst #1947 = LUi
5624 { 1946, 3, 1, 4, 1331, 0, 0, 879, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL }, // Inst #1946 = LUXC1_MM
5625 { 1945, 3, 1, 4, 891, 0, 0, 879, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL }, // Inst #1945 = LUXC164
5626 { 1944, 3, 1, 4, 891, 0, 0, 876, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL }, // Inst #1944 = LUXC1
5627 { 1943, 2, 1, 4, 950, 0, 0, 371, MipsImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // Inst #1943 = LUI_MMR6
5628 { 1942, 4, 1, 4, 493, 0, 0, 569, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1942 = LSA_R6
5629 { 1941, 4, 1, 4, 949, 0, 0, 569, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1941 = LSA_MMR6
5630 { 1940, 4, 1, 4, 769, 0, 0, 569, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1940 = LSA
5631 { 1939, 3, 1, 4, 1160, 0, 0, 894, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1939 = LL_R6
5632 { 1938, 3, 1, 4, 1221, 0, 0, 319, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1938 = LL_MMR6
5633 { 1937, 3, 1, 4, 1195, 0, 0, 319, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1937 = LL_MM
5634 { 1936, 3, 1, 4, 1171, 0, 0, 319, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1936 = LLE_MM
5635 { 1935, 3, 1, 4, 725, 0, 0, 319, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1935 = LLE
5636 { 1934, 3, 1, 4, 396, 0, 0, 897, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1934 = LLD_R6
5637 { 1933, 3, 1, 4, 1236, 0, 0, 368, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1933 = LLD
5638 { 1932, 3, 1, 4, 397, 0, 0, 894, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1932 = LL64_R6
5639 { 1931, 3, 1, 4, 1236, 0, 0, 319, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1931 = LL64
5640 { 1930, 3, 1, 4, 716, 0, 0, 319, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1930 = LL
5641 { 1929, 2, 1, 2, 948, 0, 0, 537, MipsImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #1929 = LI16_MMR6
5642 { 1928, 2, 1, 2, 907, 0, 0, 537, MipsImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #1928 = LI16_MM
5643 { 1927, 3, 1, 4, 1193, 0, 0, 319, MipsImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1927 = LHu_MM
5644 { 1926, 3, 1, 4, 1167, 0, 0, 319, MipsImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1926 = LHuE_MM
5645 { 1925, 3, 1, 4, 723, 0, 0, 319, MipsImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1925 = LHuE
5646 { 1924, 3, 1, 4, 387, 0, 0, 368, MipsImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1924 = LHu64
5647 { 1923, 3, 1, 4, 714, 0, 0, 319, MipsImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1923 = LHu
5648 { 1922, 3, 1, 4, 1194, 0, 0, 319, MipsImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1922 = LH_MM
5649 { 1921, 3, 1, 4, 1582, 0, 0, 849, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1921 = LHX_MM
5650 { 1920, 3, 1, 4, 1422, 0, 0, 849, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1920 = LHX
5651 { 1919, 3, 1, 2, 1193, 0, 0, 846, MipsImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1919 = LHU16_MM
5652 { 1918, 3, 1, 4, 1166, 0, 0, 319, MipsImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1918 = LHE_MM
5653 { 1917, 3, 1, 4, 722, 0, 0, 319, MipsImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1917 = LHE
5654 { 1916, 3, 1, 4, 386, 0, 0, 368, MipsImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1916 = LH64
5655 { 1915, 3, 1, 4, 713, 0, 0, 319, MipsImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1915 = LH
5656 { 1914, 3, 1, 4, 897, 0, 0, 319, MipsImpOpBase + 0, 0, 0x2ULL }, // Inst #1914 = LEA_ADDiu_MM
5657 { 1913, 3, 1, 4, 971, 0, 0, 368, MipsImpOpBase + 0, 0, 0x2ULL }, // Inst #1913 = LEA_ADDiu64
5658 { 1912, 3, 1, 4, 892, 0, 0, 319, MipsImpOpBase + 0, 0, 0x2ULL }, // Inst #1912 = LEA_ADDiu
5659 { 1911, 3, 1, 4, 608, 0, 0, 891, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1911 = LD_W
5660 { 1910, 3, 1, 4, 608, 0, 0, 888, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1910 = LD_H
5661 { 1909, 3, 1, 4, 608, 0, 0, 885, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1909 = LD_D
5662 { 1908, 3, 1, 4, 608, 0, 0, 882, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1908 = LD_B
5663 { 1907, 3, 1, 4, 889, 0, 0, 879, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // Inst #1907 = LDXC164
5664 { 1906, 3, 1, 4, 889, 0, 0, 876, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // Inst #1906 = LDXC1
5665 { 1905, 4, 1, 4, 1238, 0, 0, 872, MipsImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1905 = LDR
5666 { 1904, 2, 1, 4, 400, 0, 0, 366, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1904 = LDPC
5667 { 1903, 4, 1, 4, 1237, 0, 0, 872, MipsImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1903 = LDL
5668 { 1902, 2, 1, 4, 609, 0, 0, 870, MipsImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable), 0x6ULL }, // Inst #1902 = LDI_W
5669 { 1901, 2, 1, 4, 609, 0, 0, 868, MipsImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable), 0x6ULL }, // Inst #1901 = LDI_H
5670 { 1900, 2, 1, 4, 609, 0, 0, 866, MipsImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable), 0x6ULL }, // Inst #1900 = LDI_D
5671 { 1899, 2, 1, 4, 609, 0, 0, 864, MipsImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable), 0x6ULL }, // Inst #1899 = LDI_B
5672 { 1898, 3, 1, 4, 394, 0, 0, 861, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // Inst #1898 = LDC3
5673 { 1897, 3, 1, 4, 393, 0, 0, 855, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1897 = LDC2_R6
5674 { 1896, 3, 1, 4, 1220, 0, 0, 858, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1896 = LDC2_MMR6
5675 { 1895, 3, 1, 4, 719, 0, 0, 855, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // Inst #1895 = LDC2
5676 { 1894, 3, 1, 4, 1330, 0, 0, 852, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // Inst #1894 = LDC1_MM_D64
5677 { 1893, 3, 1, 4, 1330, 0, 0, 504, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // Inst #1893 = LDC1_MM_D32
5678 { 1892, 3, 1, 4, 1373, 0, 0, 852, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1892 = LDC1_D64_MMR6
5679 { 1891, 3, 1, 4, 390, 0, 0, 852, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // Inst #1891 = LDC164
5680 { 1890, 3, 1, 4, 390, 0, 0, 504, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // Inst #1890 = LDC1
5681 { 1889, 3, 1, 4, 385, 0, 0, 368, MipsImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1889 = LD
5682 { 1888, 3, 1, 4, 1191, 0, 0, 319, MipsImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1888 = LBu_MM
5683 { 1887, 3, 1, 4, 1165, 0, 0, 319, MipsImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1887 = LBuE_MM
5684 { 1886, 3, 1, 4, 721, 0, 0, 319, MipsImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1886 = LBuE
5685 { 1885, 3, 1, 4, 384, 0, 0, 368, MipsImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1885 = LBu64
5686 { 1884, 3, 1, 4, 712, 0, 0, 319, MipsImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1884 = LBu
5687 { 1883, 3, 1, 4, 1219, 0, 0, 319, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1883 = LB_MMR6
5688 { 1882, 3, 1, 4, 1192, 0, 0, 319, MipsImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1882 = LB_MM
5689 { 1881, 3, 1, 4, 1218, 0, 0, 319, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1881 = LBU_MMR6
5690 { 1880, 3, 1, 4, 1581, 0, 0, 849, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1880 = LBUX_MM
5691 { 1879, 3, 1, 4, 1421, 0, 0, 849, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1879 = LBUX
5692 { 1878, 3, 1, 2, 1191, 0, 0, 846, MipsImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1878 = LBU16_MM
5693 { 1877, 3, 1, 4, 1164, 0, 0, 319, MipsImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1877 = LBE_MM
5694 { 1876, 3, 1, 4, 720, 0, 0, 319, MipsImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1876 = LBE
5695 { 1875, 3, 1, 4, 383, 0, 0, 368, MipsImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1875 = LB64
5696 { 1874, 3, 1, 4, 711, 0, 0, 319, MipsImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1874 = LB
5697 { 1873, 1, 0, 2, 1039, 0, 1, 845, MipsImpOpBase + 3, 0|(1ULL<<MCID::Call), 0x0ULL }, // Inst #1873 = JumpLinkReg16
5698 { 1872, 1, 0, 2, 1036, 0, 0, 845, MipsImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1872 = JrcRx16
5699 { 1871, 0, 0, 2, 1036, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1871 = JrcRa16
5700 { 1870, 0, 0, 2, 1036, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1870 = JrRa16
5701 { 1869, 1, 0, 6, 1038, 0, 1, 0, MipsImpOpBase + 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1869 = JalB16
5702 { 1868, 1, 0, 6, 1038, 0, 1, 0, MipsImpOpBase + 3, 0|(1ULL<<MCID::Call), 0x0ULL }, // Inst #1868 = Jal16
5703 { 1867, 1, 0, 4, 1052, 0, 1, 0, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x13ULL }, // Inst #1867 = J_MM
5704 { 1866, 1, 0, 4, 1051, 0, 0, 197, MipsImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL }, // Inst #1866 = JR_MM
5705 { 1865, 1, 0, 4, 1032, 0, 0, 197, MipsImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1865 = JR_HB_R6
5706 { 1864, 1, 0, 4, 421, 0, 0, 318, MipsImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1864 = JR_HB64_R6
5707 { 1863, 1, 0, 4, 1107, 0, 0, 318, MipsImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL }, // Inst #1863 = JR_HB64
5708 { 1862, 1, 0, 4, 687, 0, 0, 197, MipsImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL }, // Inst #1862 = JR_HB
5709 { 1861, 1, 0, 2, 1090, 0, 0, 0, MipsImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1861 = JRCADDIUSP_MMR6
5710 { 1860, 1, 0, 2, 1092, 0, 0, 197, MipsImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1860 = JRC16_MMR6
5711 { 1859, 1, 0, 2, 1091, 0, 0, 197, MipsImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1859 = JRC16_MM
5712 { 1858, 1, 0, 2, 1090, 0, 0, 0, MipsImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1858 = JRADDIUSP
5713 { 1857, 1, 0, 4, 1106, 0, 0, 318, MipsImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL }, // Inst #1857 = JR64
5714 { 1856, 1, 0, 2, 1051, 0, 0, 197, MipsImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1856 = JR16_MM
5715 { 1855, 1, 0, 4, 1024, 0, 0, 197, MipsImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL }, // Inst #1855 = JR
5716 { 1854, 2, 0, 4, 1089, 0, 1, 371, MipsImpOpBase + 2, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1854 = JIC_MMR6
5717 { 1853, 2, 0, 4, 419, 0, 1, 366, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1853 = JIC64
5718 { 1852, 2, 0, 4, 1031, 0, 1, 371, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1852 = JIC
5719 { 1851, 2, 0, 4, 1101, 0, 1, 371, MipsImpOpBase + 3, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1851 = JIALC_MMR6
5720 { 1850, 2, 0, 4, 418, 0, 1, 366, MipsImpOpBase + 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1850 = JIALC64
5721 { 1849, 2, 0, 4, 1028, 0, 1, 371, MipsImpOpBase + 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1849 = JIALC
5722 { 1848, 1, 0, 4, 1059, 0, 1, 0, MipsImpOpBase + 3, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x13ULL }, // Inst #1848 = JAL_MM
5723 { 1847, 1, 0, 4, 1059, 0, 1, 0, MipsImpOpBase + 3, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x13ULL }, // Inst #1847 = JALX_MM
5724 { 1846, 1, 0, 4, 699, 0, 1, 0, MipsImpOpBase + 3, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x13ULL }, // Inst #1846 = JALX
5725 { 1845, 1, 0, 4, 1058, 0, 1, 0, MipsImpOpBase + 3, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x3ULL }, // Inst #1845 = JALS_MM
5726 { 1844, 2, 1, 4, 1056, 0, 1, 152, MipsImpOpBase + 3, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL }, // Inst #1844 = JALR_MM
5727 { 1843, 2, 1, 4, 436, 0, 0, 389, MipsImpOpBase + 0, 0|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL }, // Inst #1843 = JALR_HB64
5728 { 1842, 2, 1, 4, 698, 0, 0, 152, MipsImpOpBase + 0, 0|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL }, // Inst #1842 = JALR_HB
5729 { 1841, 2, 1, 4, 1057, 0, 1, 152, MipsImpOpBase + 3, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1841 = JALRS_MM
5730 { 1840, 1, 0, 2, 1057, 0, 1, 197, MipsImpOpBase + 3, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1840 = JALRS16_MM
5731 { 1839, 2, 1, 4, 1100, 0, 1, 152, MipsImpOpBase + 3, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1839 = JALRC_MMR6
5732 { 1838, 2, 1, 4, 1099, 0, 0, 152, MipsImpOpBase + 0, 0|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::UnmodeledSideEffects), 0x3ULL }, // Inst #1838 = JALRC_HB_MMR6
5733 { 1837, 1, 0, 2, 1098, 0, 1, 197, MipsImpOpBase + 3, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #1837 = JALRC16_MMR6
5734 { 1836, 2, 1, 4, 414, 0, 1, 389, MipsImpOpBase + 3, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL }, // Inst #1836 = JALR64
5735 { 1835, 1, 0, 2, 1056, 0, 1, 197, MipsImpOpBase + 3, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #1835 = JALR16_MM
5736 { 1834, 2, 1, 4, 697, 0, 1, 152, MipsImpOpBase + 3, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL }, // Inst #1834 = JALR
5737 { 1833, 1, 0, 4, 413, 0, 1, 0, MipsImpOpBase + 3, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x13ULL }, // Inst #1833 = JAL
5738 { 1832, 1, 0, 4, 1023, 0, 1, 0, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x13ULL }, // Inst #1832 = J
5739 { 1831, 5, 1, 4, 947, 0, 0, 801, MipsImpOpBase + 0, 0, 0x1ULL }, // Inst #1831 = INS_MMR6
5740 { 1830, 5, 1, 4, 906, 0, 0, 801, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1830 = INS_MM
5741 { 1829, 3, 1, 4, 1580, 2, 0, 822, MipsImpOpBase + 30, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1829 = INSV_MM
5742 { 1828, 5, 1, 4, 653, 0, 0, 840, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1828 = INSVE_W
5743 { 1827, 5, 1, 4, 653, 0, 0, 835, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1827 = INSVE_H
5744 { 1826, 5, 1, 4, 653, 0, 0, 830, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1826 = INSVE_D
5745 { 1825, 5, 1, 4, 653, 0, 0, 825, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1825 = INSVE_B
5746 { 1824, 3, 1, 4, 1385, 2, 0, 822, MipsImpOpBase + 30, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1824 = INSV
5747 { 1823, 4, 1, 4, 773, 0, 0, 818, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1823 = INSERT_W
5748 { 1822, 4, 1, 4, 773, 0, 0, 814, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1822 = INSERT_H
5749 { 1821, 4, 1, 4, 773, 0, 0, 810, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1821 = INSERT_D
5750 { 1820, 4, 1, 4, 773, 0, 0, 806, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1820 = INSERT_B
5751 { 1819, 5, 1, 4, 763, 0, 0, 801, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1819 = INS
5752 { 1818, 3, 1, 4, 599, 0, 0, 160, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1818 = ILVR_W
5753 { 1817, 3, 1, 4, 599, 0, 0, 157, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1817 = ILVR_H
5754 { 1816, 3, 1, 4, 599, 0, 0, 154, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1816 = ILVR_D
5755 { 1815, 3, 1, 4, 599, 0, 0, 551, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1815 = ILVR_B
5756 { 1814, 3, 1, 4, 598, 0, 0, 160, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1814 = ILVOD_W
5757 { 1813, 3, 1, 4, 598, 0, 0, 157, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1813 = ILVOD_H
5758 { 1812, 3, 1, 4, 598, 0, 0, 154, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1812 = ILVOD_D
5759 { 1811, 3, 1, 4, 598, 0, 0, 551, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1811 = ILVOD_B
5760 { 1810, 3, 1, 4, 597, 0, 0, 160, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1810 = ILVL_W
5761 { 1809, 3, 1, 4, 597, 0, 0, 157, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1809 = ILVL_H
5762 { 1808, 3, 1, 4, 597, 0, 0, 154, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1808 = ILVL_D
5763 { 1807, 3, 1, 4, 597, 0, 0, 551, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1807 = ILVL_B
5764 { 1806, 3, 1, 4, 596, 0, 0, 160, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1806 = ILVEV_W
5765 { 1805, 3, 1, 4, 596, 0, 0, 157, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1805 = ILVEV_H
5766 { 1804, 3, 1, 4, 596, 0, 0, 154, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1804 = ILVEV_D
5767 { 1803, 3, 1, 4, 596, 0, 0, 551, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1803 = ILVEV_B
5768 { 1802, 1, 0, 4, 1148, 0, 0, 0, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1802 = HYPCALL_MM
5769 { 1801, 1, 0, 4, 700, 0, 0, 0, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1801 = HYPCALL
5770 { 1800, 3, 1, 4, 831, 0, 0, 736, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1800 = HSUB_U_W
5771 { 1799, 3, 1, 4, 831, 0, 0, 733, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1799 = HSUB_U_H
5772 { 1798, 3, 1, 4, 831, 0, 0, 730, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1798 = HSUB_U_D
5773 { 1797, 3, 1, 4, 831, 0, 0, 736, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1797 = HSUB_S_W
5774 { 1796, 3, 1, 4, 831, 0, 0, 733, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1796 = HSUB_S_H
5775 { 1795, 3, 1, 4, 831, 0, 0, 730, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1795 = HSUB_S_D
5776 { 1794, 3, 1, 4, 830, 0, 0, 736, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1794 = HADD_U_W
5777 { 1793, 3, 1, 4, 830, 0, 0, 733, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1793 = HADD_U_H
5778 { 1792, 3, 1, 4, 830, 0, 0, 730, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1792 = HADD_U_D
5779 { 1791, 3, 1, 4, 830, 0, 0, 736, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1791 = HADD_S_W
5780 { 1790, 3, 1, 4, 830, 0, 0, 733, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1790 = HADD_S_H
5781 { 1789, 3, 1, 4, 830, 0, 0, 730, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1789 = HADD_S_D
5782 { 1788, 2, 0, 4, 1217, 0, 0, 371, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1788 = GINVT_MMR6
5783 { 1787, 2, 0, 4, 1163, 0, 0, 371, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1787 = GINVT
5784 { 1786, 1, 0, 4, 1216, 0, 0, 197, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1786 = GINVI_MMR6
5785 { 1785, 1, 0, 4, 1162, 0, 0, 197, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1785 = GINVI
5786 { 1784, 2, 1, 4, 819, 0, 0, 252, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1784 = FTRUNC_U_W
5787 { 1783, 2, 1, 4, 819, 0, 0, 250, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1783 = FTRUNC_U_D
5788 { 1782, 2, 1, 4, 819, 0, 0, 252, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1782 = FTRUNC_S_W
5789 { 1781, 2, 1, 4, 819, 0, 0, 250, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1781 = FTRUNC_S_D
5790 { 1780, 3, 1, 4, 818, 0, 0, 786, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1780 = FTQ_W
5791 { 1779, 3, 1, 4, 818, 0, 0, 783, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1779 = FTQ_H
5792 { 1778, 2, 1, 4, 816, 0, 0, 252, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1778 = FTINT_U_W
5793 { 1777, 2, 1, 4, 816, 0, 0, 250, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1777 = FTINT_U_D
5794 { 1776, 2, 1, 4, 816, 0, 0, 252, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1776 = FTINT_S_W
5795 { 1775, 2, 1, 4, 816, 0, 0, 250, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1775 = FTINT_S_D
5796 { 1774, 3, 1, 4, 801, 0, 0, 160, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1774 = FSUN_W
5797 { 1773, 3, 1, 4, 801, 0, 0, 154, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1773 = FSUN_D
5798 { 1772, 3, 1, 4, 800, 0, 0, 160, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1772 = FSUNE_W
5799 { 1771, 3, 1, 4, 800, 0, 0, 154, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1771 = FSUNE_D
5800 { 1770, 3, 1, 4, 799, 0, 0, 160, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1770 = FSULT_W
5801 { 1769, 3, 1, 4, 799, 0, 0, 154, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1769 = FSULT_D
5802 { 1768, 3, 1, 4, 798, 0, 0, 160, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1768 = FSULE_W
5803 { 1767, 3, 1, 4, 798, 0, 0, 154, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1767 = FSULE_D
5804 { 1766, 3, 1, 4, 797, 0, 0, 160, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1766 = FSUEQ_W
5805 { 1765, 3, 1, 4, 797, 0, 0, 154, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1765 = FSUEQ_D
5806 { 1764, 3, 1, 4, 659, 0, 0, 160, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1764 = FSUB_W
5807 { 1763, 3, 1, 4, 1369, 0, 0, 771, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1763 = FSUB_S_MMR6
5808 { 1762, 3, 1, 4, 1315, 0, 0, 771, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1762 = FSUB_S_MM
5809 { 1761, 3, 1, 4, 565, 0, 0, 771, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1761 = FSUB_S
5810 { 1760, 3, 1, 4, 842, 0, 0, 548, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1760 = FSUB_PS64
5811 { 1759, 3, 1, 4, 1314, 0, 0, 548, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1759 = FSUB_D64_MM
5812 { 1758, 3, 1, 4, 566, 0, 0, 548, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1758 = FSUB_D64
5813 { 1757, 3, 1, 4, 1314, 0, 0, 768, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1757 = FSUB_D32_MM
5814 { 1756, 3, 1, 4, 566, 0, 0, 768, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1756 = FSUB_D32
5815 { 1755, 3, 1, 4, 659, 0, 0, 154, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1755 = FSUB_D
5816 { 1754, 2, 1, 4, 853, 0, 0, 252, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1754 = FSQRT_W
5817 { 1753, 2, 1, 4, 1320, 0, 0, 643, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1753 = FSQRT_S_MM
5818 { 1752, 2, 1, 4, 570, 0, 0, 643, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1752 = FSQRT_S
5819 { 1751, 2, 1, 4, 1321, 0, 0, 635, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1751 = FSQRT_D64_MM
5820 { 1750, 2, 1, 4, 573, 0, 0, 635, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1750 = FSQRT_D64
5821 { 1749, 2, 1, 4, 1321, 0, 0, 766, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1749 = FSQRT_D32_MM
5822 { 1748, 2, 1, 4, 573, 0, 0, 766, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1748 = FSQRT_D32
5823 { 1747, 2, 1, 4, 572, 0, 0, 250, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1747 = FSQRT_D
5824 { 1746, 3, 1, 4, 796, 0, 0, 160, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1746 = FSOR_W
5825 { 1745, 3, 1, 4, 796, 0, 0, 154, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1745 = FSOR_D
5826 { 1744, 3, 1, 4, 796, 0, 0, 160, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1744 = FSNE_W
5827 { 1743, 3, 1, 4, 796, 0, 0, 154, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1743 = FSNE_D
5828 { 1742, 3, 1, 4, 796, 0, 0, 160, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1742 = FSLT_W
5829 { 1741, 3, 1, 4, 796, 0, 0, 154, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1741 = FSLT_D
5830 { 1740, 3, 1, 4, 796, 0, 0, 160, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1740 = FSLE_W
5831 { 1739, 3, 1, 4, 796, 0, 0, 154, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1739 = FSLE_D
5832 { 1738, 3, 1, 4, 796, 0, 0, 160, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1738 = FSEQ_W
5833 { 1737, 3, 1, 4, 796, 0, 0, 154, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1737 = FSEQ_D
5834 { 1736, 3, 1, 4, 796, 0, 0, 160, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1736 = FSAF_W
5835 { 1735, 3, 1, 4, 796, 0, 0, 154, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1735 = FSAF_D
5836 { 1734, 2, 1, 4, 851, 0, 0, 252, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1734 = FRSQRT_W
5837 { 1733, 2, 1, 4, 851, 0, 0, 250, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1733 = FRSQRT_D
5838 { 1732, 2, 1, 4, 817, 0, 0, 252, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1732 = FRINT_W
5839 { 1731, 2, 1, 4, 817, 0, 0, 250, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1731 = FRINT_D
5840 { 1730, 2, 1, 4, 850, 0, 0, 252, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1730 = FRCP_W
5841 { 1729, 2, 1, 4, 850, 0, 0, 250, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1729 = FRCP_D
5842 { 1728, 3, 2, 4, 1145, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1728 = FORK
5843 { 1727, 2, 1, 4, 1334, 0, 0, 643, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1727 = FNEG_S_MMR6
5844 { 1726, 2, 1, 4, 1307, 0, 0, 643, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1726 = FNEG_S_MM
5845 { 1725, 2, 1, 4, 559, 0, 0, 643, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1725 = FNEG_S
5846 { 1724, 2, 1, 4, 1307, 0, 0, 635, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1724 = FNEG_D64_MM
5847 { 1723, 2, 1, 4, 559, 0, 0, 635, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1723 = FNEG_D64
5848 { 1722, 2, 1, 4, 1307, 0, 0, 766, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1722 = FNEG_D32_MM
5849 { 1721, 2, 1, 4, 559, 0, 0, 766, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1721 = FNEG_D32
5850 { 1720, 3, 1, 4, 854, 0, 0, 160, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1720 = FMUL_W
5851 { 1719, 3, 1, 4, 1368, 0, 0, 771, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1719 = FMUL_S_MMR6
5852 { 1718, 3, 1, 4, 1313, 0, 0, 771, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x4ULL }, // Inst #1718 = FMUL_S_MM
5853 { 1717, 3, 1, 4, 567, 0, 0, 771, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x4ULL }, // Inst #1717 = FMUL_S
5854 { 1716, 3, 1, 4, 841, 0, 0, 548, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1716 = FMUL_PS64
5855 { 1715, 3, 1, 4, 1312, 0, 0, 548, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x4ULL }, // Inst #1715 = FMUL_D64_MM
5856 { 1714, 3, 1, 4, 568, 0, 0, 548, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x4ULL }, // Inst #1714 = FMUL_D64
5857 { 1713, 3, 1, 4, 1312, 0, 0, 768, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x4ULL }, // Inst #1713 = FMUL_D32_MM
5858 { 1712, 3, 1, 4, 568, 0, 0, 768, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x4ULL }, // Inst #1712 = FMUL_D32
5859 { 1711, 3, 1, 4, 854, 0, 0, 154, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1711 = FMUL_D
5860 { 1710, 4, 1, 4, 663, 0, 0, 202, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1710 = FMSUB_W
5861 { 1709, 4, 1, 4, 663, 0, 0, 198, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1709 = FMSUB_D
5862 { 1708, 2, 1, 4, 1367, 0, 0, 643, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1708 = FMOV_S_MMR6
5863 { 1707, 2, 1, 4, 1311, 0, 0, 643, MipsImpOpBase + 0, 0|(1ULL<<MCID::MoveReg), 0x4ULL }, // Inst #1707 = FMOV_S_MM
5864 { 1706, 2, 1, 4, 560, 0, 0, 643, MipsImpOpBase + 0, 0|(1ULL<<MCID::MoveReg), 0x4ULL }, // Inst #1706 = FMOV_S
5865 { 1705, 2, 1, 4, 1370, 0, 0, 635, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1705 = FMOV_D_MMR6
5866 { 1704, 2, 1, 4, 1310, 0, 0, 635, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1704 = FMOV_D64_MM
5867 { 1703, 2, 1, 4, 561, 0, 0, 635, MipsImpOpBase + 0, 0|(1ULL<<MCID::MoveReg), 0x4ULL }, // Inst #1703 = FMOV_D64
5868 { 1702, 2, 1, 4, 1310, 0, 0, 766, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1702 = FMOV_D32_MM
5869 { 1701, 2, 1, 4, 561, 0, 0, 766, MipsImpOpBase + 0, 0|(1ULL<<MCID::MoveReg), 0x4ULL }, // Inst #1701 = FMOV_D32
5870 { 1700, 3, 1, 4, 611, 0, 0, 160, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1700 = FMIN_W
5871 { 1699, 3, 1, 4, 611, 0, 0, 154, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1699 = FMIN_D
5872 { 1698, 3, 1, 4, 826, 0, 0, 160, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1698 = FMIN_A_W
5873 { 1697, 3, 1, 4, 826, 0, 0, 154, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1697 = FMIN_A_D
5874 { 1696, 3, 1, 4, 825, 0, 0, 160, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1696 = FMAX_W
5875 { 1695, 3, 1, 4, 825, 0, 0, 154, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1695 = FMAX_D
5876 { 1694, 3, 1, 4, 824, 0, 0, 160, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1694 = FMAX_A_W
5877 { 1693, 3, 1, 4, 824, 0, 0, 154, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1693 = FMAX_A_D
5878 { 1692, 4, 1, 4, 852, 0, 0, 202, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1692 = FMADD_W
5879 { 1691, 4, 1, 4, 852, 0, 0, 198, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1691 = FMADD_D
5880 { 1690, 2, 1, 4, 1344, 0, 0, 643, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1690 = FLOOR_W_S_MMR6
5881 { 1689, 2, 1, 4, 1282, 0, 0, 643, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1689 = FLOOR_W_S_MM
5882 { 1688, 2, 1, 4, 648, 0, 0, 643, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1688 = FLOOR_W_S
5883 { 1687, 2, 1, 4, 1282, 0, 0, 639, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1687 = FLOOR_W_MM
5884 { 1686, 2, 1, 4, 1344, 0, 0, 639, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1686 = FLOOR_W_D_MMR6
5885 { 1685, 2, 1, 4, 648, 0, 0, 641, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1685 = FLOOR_W_D64
5886 { 1684, 2, 1, 4, 648, 0, 0, 639, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1684 = FLOOR_W_D32
5887 { 1683, 2, 1, 4, 1344, 0, 0, 637, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1683 = FLOOR_L_S_MMR6
5888 { 1682, 2, 1, 4, 648, 0, 0, 637, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1682 = FLOOR_L_S
5889 { 1681, 2, 1, 4, 1344, 0, 0, 635, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1681 = FLOOR_L_D_MMR6
5890 { 1680, 2, 1, 4, 648, 0, 0, 635, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1680 = FLOOR_L_D64
5891 { 1679, 2, 1, 4, 658, 0, 0, 252, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1679 = FLOG2_W
5892 { 1678, 2, 1, 4, 658, 0, 0, 250, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1678 = FLOG2_D
5893 { 1677, 2, 1, 4, 602, 0, 0, 799, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1677 = FILL_W
5894 { 1676, 2, 1, 4, 602, 0, 0, 797, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1676 = FILL_H
5895 { 1675, 2, 1, 4, 602, 0, 0, 795, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1675 = FILL_D
5896 { 1674, 2, 1, 4, 602, 0, 0, 793, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1674 = FILL_B
5897 { 1673, 2, 1, 4, 815, 0, 0, 791, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1673 = FFQR_W
5898 { 1672, 2, 1, 4, 815, 0, 0, 789, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1672 = FFQR_D
5899 { 1671, 2, 1, 4, 814, 0, 0, 791, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1671 = FFQL_W
5900 { 1670, 2, 1, 4, 814, 0, 0, 789, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1670 = FFQL_D
5901 { 1669, 2, 1, 4, 813, 0, 0, 252, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1669 = FFINT_U_W
5902 { 1668, 2, 1, 4, 813, 0, 0, 250, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1668 = FFINT_U_D
5903 { 1667, 2, 1, 4, 813, 0, 0, 252, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1667 = FFINT_S_W
5904 { 1666, 2, 1, 4, 813, 0, 0, 250, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1666 = FFINT_S_D
5905 { 1665, 2, 1, 4, 822, 0, 0, 791, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1665 = FEXUPR_W
5906 { 1664, 2, 1, 4, 822, 0, 0, 789, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1664 = FEXUPR_D
5907 { 1663, 2, 1, 4, 821, 0, 0, 791, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1663 = FEXUPL_W
5908 { 1662, 2, 1, 4, 821, 0, 0, 789, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1662 = FEXUPL_D
5909 { 1661, 3, 1, 4, 792, 0, 0, 160, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1661 = FEXP2_W
5910 { 1660, 3, 1, 4, 792, 0, 0, 154, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1660 = FEXP2_D
5911 { 1659, 3, 1, 4, 820, 0, 0, 786, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1659 = FEXDO_W
5912 { 1658, 3, 1, 4, 820, 0, 0, 783, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1658 = FEXDO_H
5913 { 1657, 3, 1, 4, 669, 0, 0, 160, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1657 = FDIV_W
5914 { 1656, 3, 1, 4, 1371, 0, 0, 771, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1656 = FDIV_S_MMR6
5915 { 1655, 3, 1, 4, 1318, 0, 0, 771, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1655 = FDIV_S_MM
5916 { 1654, 3, 1, 4, 569, 0, 0, 771, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1654 = FDIV_S
5917 { 1653, 3, 1, 4, 1319, 0, 0, 548, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1653 = FDIV_D64_MM
5918 { 1652, 3, 1, 4, 571, 0, 0, 548, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1652 = FDIV_D64
5919 { 1651, 3, 1, 4, 1319, 0, 0, 768, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1651 = FDIV_D32_MM
5920 { 1650, 3, 1, 4, 571, 0, 0, 768, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1650 = FDIV_D32
5921 { 1649, 3, 1, 4, 668, 0, 0, 154, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1649 = FDIV_D
5922 { 1648, 3, 1, 4, 610, 0, 0, 160, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1648 = FCUN_W
5923 { 1647, 3, 1, 4, 610, 0, 0, 154, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1647 = FCUN_D
5924 { 1646, 3, 1, 4, 811, 0, 0, 160, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1646 = FCUNE_W
5925 { 1645, 3, 1, 4, 811, 0, 0, 154, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1645 = FCUNE_D
5926 { 1644, 3, 1, 4, 810, 0, 0, 160, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1644 = FCULT_W
5927 { 1643, 3, 1, 4, 810, 0, 0, 154, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1643 = FCULT_D
5928 { 1642, 3, 1, 4, 809, 0, 0, 160, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1642 = FCULE_W
5929 { 1641, 3, 1, 4, 809, 0, 0, 154, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1641 = FCULE_D
5930 { 1640, 3, 1, 4, 808, 0, 0, 160, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1640 = FCUEQ_W
5931 { 1639, 3, 1, 4, 808, 0, 0, 154, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1639 = FCUEQ_D
5932 { 1638, 3, 1, 4, 807, 0, 0, 160, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1638 = FCOR_W
5933 { 1637, 3, 1, 4, 807, 0, 0, 154, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1637 = FCOR_D
5934 { 1636, 3, 1, 4, 806, 0, 0, 160, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1636 = FCNE_W
5935 { 1635, 3, 1, 4, 806, 0, 0, 154, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1635 = FCNE_D
5936 { 1634, 3, 0, 4, 1299, 0, 1, 780, MipsImpOpBase + 29, 0, 0x44ULL }, // Inst #1634 = FCMP_S32_MM
5937 { 1633, 3, 0, 4, 848, 0, 1, 780, MipsImpOpBase + 29, 0, 0x44ULL }, // Inst #1633 = FCMP_S32
5938 { 1632, 3, 0, 4, 847, 0, 1, 777, MipsImpOpBase + 29, 0, 0x44ULL }, // Inst #1632 = FCMP_D64
5939 { 1631, 3, 0, 4, 1300, 0, 1, 774, MipsImpOpBase + 29, 0, 0x44ULL }, // Inst #1631 = FCMP_D32_MM
5940 { 1630, 3, 0, 4, 847, 0, 1, 774, MipsImpOpBase + 29, 0, 0x44ULL }, // Inst #1630 = FCMP_D32
5941 { 1629, 3, 1, 4, 805, 0, 0, 160, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1629 = FCLT_W
5942 { 1628, 3, 1, 4, 805, 0, 0, 154, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1628 = FCLT_D
5943 { 1627, 3, 1, 4, 804, 0, 0, 160, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1627 = FCLE_W
5944 { 1626, 3, 1, 4, 804, 0, 0, 154, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1626 = FCLE_D
5945 { 1625, 2, 1, 4, 823, 0, 0, 252, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1625 = FCLASS_W
5946 { 1624, 2, 1, 4, 823, 0, 0, 250, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1624 = FCLASS_D
5947 { 1623, 3, 1, 4, 803, 0, 0, 160, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1623 = FCEQ_W
5948 { 1622, 3, 1, 4, 803, 0, 0, 154, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1622 = FCEQ_D
5949 { 1621, 3, 1, 4, 802, 0, 0, 160, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1621 = FCAF_W
5950 { 1620, 3, 1, 4, 802, 0, 0, 154, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1620 = FCAF_D
5951 { 1619, 3, 1, 4, 855, 0, 0, 160, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1619 = FADD_W
5952 { 1618, 3, 1, 4, 1349, 0, 0, 771, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1618 = FADD_S_MMR6
5953 { 1617, 3, 1, 4, 1309, 0, 0, 771, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x4ULL }, // Inst #1617 = FADD_S_MM
5954 { 1616, 3, 1, 4, 564, 0, 0, 771, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x4ULL }, // Inst #1616 = FADD_S
5955 { 1615, 3, 1, 4, 840, 0, 0, 548, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1615 = FADD_PS64
5956 { 1614, 3, 1, 4, 1308, 0, 0, 548, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x4ULL }, // Inst #1614 = FADD_D64_MM
5957 { 1613, 3, 1, 4, 660, 0, 0, 548, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x4ULL }, // Inst #1613 = FADD_D64
5958 { 1612, 3, 1, 4, 1308, 0, 0, 768, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x4ULL }, // Inst #1612 = FADD_D32_MM
5959 { 1611, 3, 1, 4, 660, 0, 0, 768, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x4ULL }, // Inst #1611 = FADD_D32
5960 { 1610, 3, 1, 4, 855, 0, 0, 154, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1610 = FADD_D
5961 { 1609, 2, 1, 4, 1306, 0, 0, 643, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1609 = FABS_S_MM
5962 { 1608, 2, 1, 4, 558, 0, 0, 643, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1608 = FABS_S
5963 { 1607, 2, 1, 4, 1305, 0, 0, 635, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1607 = FABS_D64_MM
5964 { 1606, 2, 1, 4, 612, 0, 0, 635, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1606 = FABS_D64
5965 { 1605, 2, 1, 4, 1305, 0, 0, 766, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1605 = FABS_D32_MM
5966 { 1604, 2, 1, 4, 612, 0, 0, 766, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1604 = FABS_D32
5967 { 1603, 4, 1, 4, 946, 0, 0, 659, MipsImpOpBase + 0, 0, 0x1ULL }, // Inst #1603 = EXT_MMR6
5968 { 1602, 4, 1, 4, 905, 0, 0, 659, MipsImpOpBase + 0, 0, 0x1ULL }, // Inst #1602 = EXT_MM
5969 { 1601, 4, 1, 4, 1256, 0, 0, 651, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1601 = EXTS32
5970 { 1600, 4, 1, 4, 1256, 0, 0, 651, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1600 = EXTS
5971 { 1599, 3, 1, 4, 1579, 0, 1, 760, MipsImpOpBase + 28, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1599 = EXTR_W_MM
5972 { 1598, 3, 1, 4, 1384, 0, 1, 760, MipsImpOpBase + 28, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1598 = EXTR_W
5973 { 1597, 3, 1, 4, 1578, 0, 1, 760, MipsImpOpBase + 28, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1597 = EXTR_S_H_MM
5974 { 1596, 3, 1, 4, 1383, 0, 1, 760, MipsImpOpBase + 28, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1596 = EXTR_S_H
5975 { 1595, 3, 1, 4, 1577, 0, 1, 760, MipsImpOpBase + 28, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1595 = EXTR_R_W_MM
5976 { 1594, 3, 1, 4, 1382, 0, 1, 760, MipsImpOpBase + 28, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1594 = EXTR_R_W
5977 { 1593, 3, 1, 4, 1576, 0, 1, 760, MipsImpOpBase + 28, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1593 = EXTR_RS_W_MM
5978 { 1592, 3, 1, 4, 1381, 0, 1, 760, MipsImpOpBase + 28, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1592 = EXTR_RS_W
5979 { 1591, 3, 1, 4, 1575, 0, 1, 763, MipsImpOpBase + 28, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1591 = EXTRV_W_MM
5980 { 1590, 3, 1, 4, 1380, 0, 1, 763, MipsImpOpBase + 28, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1590 = EXTRV_W
5981 { 1589, 3, 1, 4, 1574, 0, 1, 763, MipsImpOpBase + 28, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1589 = EXTRV_S_H_MM
5982 { 1588, 3, 1, 4, 1379, 0, 1, 763, MipsImpOpBase + 28, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1588 = EXTRV_S_H
5983 { 1587, 3, 1, 4, 1573, 0, 1, 763, MipsImpOpBase + 28, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1587 = EXTRV_R_W_MM
5984 { 1586, 3, 1, 4, 1378, 0, 1, 763, MipsImpOpBase + 28, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1586 = EXTRV_R_W
5985 { 1585, 3, 1, 4, 1572, 0, 1, 763, MipsImpOpBase + 28, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1585 = EXTRV_RS_W_MM
5986 { 1584, 3, 1, 4, 1377, 0, 1, 763, MipsImpOpBase + 28, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1584 = EXTRV_RS_W
5987 { 1583, 3, 1, 4, 1571, 1, 1, 760, MipsImpOpBase + 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1583 = EXTP_MM
5988 { 1582, 3, 1, 4, 1570, 1, 1, 763, MipsImpOpBase + 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1582 = EXTPV_MM
5989 { 1581, 3, 1, 4, 1419, 1, 1, 763, MipsImpOpBase + 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1581 = EXTPV
5990 { 1580, 3, 1, 4, 1569, 1, 2, 760, MipsImpOpBase + 25, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1580 = EXTPDP_MM
5991 { 1579, 3, 1, 4, 1568, 1, 2, 763, MipsImpOpBase + 25, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1579 = EXTPDPV_MM
5992 { 1578, 3, 1, 4, 1417, 1, 2, 763, MipsImpOpBase + 25, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1578 = EXTPDPV
5993 { 1577, 3, 1, 4, 1418, 1, 2, 760, MipsImpOpBase + 25, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1577 = EXTPDP
5994 { 1576, 3, 1, 4, 1420, 1, 1, 760, MipsImpOpBase + 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1576 = EXTP
5995 { 1575, 4, 1, 4, 762, 0, 0, 659, MipsImpOpBase + 0, 0, 0x1ULL }, // Inst #1575 = EXT
5996 { 1574, 1, 1, 4, 1129, 0, 0, 197, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1574 = EVP_MMR6
5997 { 1573, 1, 1, 4, 1141, 0, 0, 197, MipsImpOpBase + 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1573 = EVPE
5998 { 1572, 1, 1, 4, 536, 0, 0, 197, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1572 = EVP
5999 { 1571, 0, 0, 4, 1088, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1571 = ERET_MMR6
6000 { 1570, 0, 0, 4, 1050, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1570 = ERET_MM
6001 { 1569, 0, 0, 4, 1086, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1569 = ERETNC_MMR6
6002 { 1568, 0, 0, 4, 433, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1568 = ERETNC
6003 { 1567, 0, 0, 4, 432, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1567 = ERET
6004 { 1566, 1, 1, 4, 1140, 0, 0, 197, MipsImpOpBase + 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1566 = EMT
6005 { 1565, 1, 1, 4, 1132, 0, 0, 197, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1565 = EI_MMR6
6006 { 1564, 1, 1, 4, 1115, 0, 0, 197, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1564 = EI_MM
6007 { 1563, 1, 1, 4, 446, 0, 0, 197, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1563 = EI
6008 { 1562, 0, 0, 4, 1133, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1562 = EHB_MMR6
6009 { 1561, 0, 0, 4, 1116, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1561 = EHB_MM
6010 { 1560, 0, 0, 4, 534, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1560 = EHB
6011 { 1559, 2, 0, 2, 988, 0, 2, 406, MipsImpOpBase + 7, 0, 0x0ULL }, // Inst #1559 = DivuRxRy16
6012 { 1558, 2, 0, 2, 987, 0, 2, 406, MipsImpOpBase + 7, 0, 0x0ULL }, // Inst #1558 = DivRxRy16
6013 { 1557, 1, 1, 4, 1130, 0, 0, 197, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1557 = DVP_MMR6
6014 { 1556, 1, 1, 4, 1139, 0, 0, 197, MipsImpOpBase + 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1556 = DVPE
6015 { 1555, 1, 1, 4, 537, 0, 0, 197, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1555 = DVP
6016 { 1554, 2, 0, 4, 1016, 0, 2, 389, MipsImpOpBase + 20, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1554 = DUDIV
6017 { 1553, 3, 1, 4, 492, 0, 0, 235, MipsImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #1553 = DSUBu
6018 { 1552, 3, 1, 4, 491, 0, 0, 235, MipsImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1552 = DSUB
6019 { 1551, 3, 1, 4, 490, 0, 0, 755, MipsImpOpBase + 0, 0, 0x1ULL }, // Inst #1551 = DSRLV
6020 { 1550, 3, 1, 4, 489, 0, 0, 232, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1550 = DSRL32
6021 { 1549, 3, 1, 4, 488, 0, 0, 232, MipsImpOpBase + 0, 0, 0x1ULL }, // Inst #1549 = DSRL
6022 { 1548, 3, 1, 4, 487, 0, 0, 755, MipsImpOpBase + 0, 0, 0x1ULL }, // Inst #1548 = DSRAV
6023 { 1547, 3, 1, 4, 486, 0, 0, 232, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1547 = DSRA32
6024 { 1546, 3, 1, 4, 485, 0, 0, 232, MipsImpOpBase + 0, 0, 0x1ULL }, // Inst #1546 = DSRA
6025 { 1545, 3, 1, 4, 484, 0, 0, 755, MipsImpOpBase + 0, 0, 0x1ULL }, // Inst #1545 = DSLLV
6026 { 1544, 2, 1, 4, 966, 0, 0, 758, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1544 = DSLL64_32
6027 { 1543, 3, 1, 4, 483, 0, 0, 232, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1543 = DSLL32
6028 { 1542, 3, 1, 4, 482, 0, 0, 232, MipsImpOpBase + 0, 0, 0x1ULL }, // Inst #1542 = DSLL
6029 { 1541, 2, 1, 4, 481, 0, 0, 389, MipsImpOpBase + 0, 0, 0x1ULL }, // Inst #1541 = DSHD
6030 { 1540, 2, 0, 4, 1015, 0, 2, 389, MipsImpOpBase + 20, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1540 = DSDIV
6031 { 1539, 2, 1, 4, 480, 0, 0, 389, MipsImpOpBase + 0, 0, 0x1ULL }, // Inst #1539 = DSBH
6032 { 1538, 3, 1, 4, 479, 0, 0, 755, MipsImpOpBase + 0, 0, 0x1ULL }, // Inst #1538 = DROTRV
6033 { 1537, 3, 1, 4, 478, 0, 0, 232, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1537 = DROTR32
6034 { 1536, 3, 1, 4, 477, 0, 0, 232, MipsImpOpBase + 0, 0, 0x1ULL }, // Inst #1536 = DROTR
6035 { 1535, 4, 1, 4, 1674, 0, 0, 751, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1535 = DPS_W_PH_MMR2
6036 { 1534, 4, 1, 4, 1510, 0, 0, 751, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1534 = DPS_W_PH
6037 { 1533, 4, 1, 4, 1677, 0, 0, 751, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1533 = DPSX_W_PH_MMR2
6038 { 1532, 4, 1, 4, 1513, 0, 0, 751, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1532 = DPSX_W_PH
6039 { 1531, 4, 1, 4, 1567, 0, 0, 751, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1531 = DPSU_H_QBR_MM
6040 { 1530, 4, 1, 4, 1416, 0, 0, 751, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1530 = DPSU_H_QBR
6041 { 1529, 4, 1, 4, 1566, 0, 0, 751, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1529 = DPSU_H_QBL_MM
6042 { 1528, 4, 1, 4, 1415, 0, 0, 751, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1528 = DPSU_H_QBL
6043 { 1527, 4, 1, 4, 662, 0, 0, 747, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1527 = DPSUB_U_W
6044 { 1526, 4, 1, 4, 662, 0, 0, 743, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1526 = DPSUB_U_H
6045 { 1525, 4, 1, 4, 662, 0, 0, 739, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1525 = DPSUB_U_D
6046 { 1524, 4, 1, 4, 662, 0, 0, 747, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1524 = DPSUB_S_W
6047 { 1523, 4, 1, 4, 662, 0, 0, 743, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1523 = DPSUB_S_H
6048 { 1522, 4, 1, 4, 662, 0, 0, 739, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1522 = DPSUB_S_D
6049 { 1521, 4, 1, 4, 1565, 0, 1, 751, MipsImpOpBase + 22, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1521 = DPSQ_S_W_PH_MM
6050 { 1520, 4, 1, 4, 1414, 0, 1, 751, MipsImpOpBase + 22, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1520 = DPSQ_S_W_PH
6051 { 1519, 4, 1, 4, 1564, 0, 1, 751, MipsImpOpBase + 22, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1519 = DPSQ_SA_L_W_MM
6052 { 1518, 4, 1, 4, 1413, 0, 1, 751, MipsImpOpBase + 22, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1518 = DPSQ_SA_L_W
6053 { 1517, 4, 1, 4, 1675, 0, 1, 751, MipsImpOpBase + 22, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1517 = DPSQX_S_W_PH_MMR2
6054 { 1516, 4, 1, 4, 1511, 0, 1, 751, MipsImpOpBase + 22, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1516 = DPSQX_S_W_PH
6055 { 1515, 4, 1, 4, 1676, 0, 1, 751, MipsImpOpBase + 22, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1515 = DPSQX_SA_W_PH_MMR2
6056 { 1514, 4, 1, 4, 1512, 0, 1, 751, MipsImpOpBase + 22, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1514 = DPSQX_SA_W_PH
6057 { 1513, 2, 1, 4, 1255, 0, 0, 389, MipsImpOpBase + 0, 0, 0x1ULL }, // Inst #1513 = DPOP
6058 { 1512, 4, 1, 4, 1670, 0, 0, 751, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1512 = DPA_W_PH_MMR2
6059 { 1511, 4, 1, 4, 1506, 0, 0, 751, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1511 = DPA_W_PH
6060 { 1510, 4, 1, 4, 1673, 0, 0, 751, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1510 = DPAX_W_PH_MMR2
6061 { 1509, 4, 1, 4, 1509, 0, 0, 751, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1509 = DPAX_W_PH
6062 { 1508, 4, 1, 4, 1563, 0, 0, 751, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1508 = DPAU_H_QBR_MM
6063 { 1507, 4, 1, 4, 1412, 0, 0, 751, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1507 = DPAU_H_QBR
6064 { 1506, 4, 1, 4, 1562, 0, 0, 751, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1506 = DPAU_H_QBL_MM
6065 { 1505, 4, 1, 4, 1411, 0, 0, 751, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1505 = DPAU_H_QBL
6066 { 1504, 4, 1, 4, 1561, 0, 1, 751, MipsImpOpBase + 22, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1504 = DPAQ_S_W_PH_MM
6067 { 1503, 4, 1, 4, 1410, 0, 1, 751, MipsImpOpBase + 22, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1503 = DPAQ_S_W_PH
6068 { 1502, 4, 1, 4, 1560, 0, 1, 751, MipsImpOpBase + 22, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1502 = DPAQ_SA_L_W_MM
6069 { 1501, 4, 1, 4, 1409, 0, 1, 751, MipsImpOpBase + 22, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1501 = DPAQ_SA_L_W
6070 { 1500, 4, 1, 4, 1672, 0, 1, 751, MipsImpOpBase + 22, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1500 = DPAQX_S_W_PH_MMR2
6071 { 1499, 4, 1, 4, 1508, 0, 1, 751, MipsImpOpBase + 22, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1499 = DPAQX_S_W_PH
6072 { 1498, 4, 1, 4, 1671, 0, 1, 751, MipsImpOpBase + 22, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1498 = DPAQX_SA_W_PH_MMR2
6073 { 1497, 4, 1, 4, 1507, 0, 1, 751, MipsImpOpBase + 22, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1497 = DPAQX_SA_W_PH
6074 { 1496, 4, 1, 4, 856, 0, 0, 747, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1496 = DPADD_U_W
6075 { 1495, 4, 1, 4, 856, 0, 0, 743, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1495 = DPADD_U_H
6076 { 1494, 4, 1, 4, 856, 0, 0, 739, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1494 = DPADD_U_D
6077 { 1493, 4, 1, 4, 856, 0, 0, 747, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1493 = DPADD_S_W
6078 { 1492, 4, 1, 4, 856, 0, 0, 743, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1492 = DPADD_S_H
6079 { 1491, 4, 1, 4, 856, 0, 0, 739, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1491 = DPADD_S_D
6080 { 1490, 3, 1, 4, 857, 0, 0, 736, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1490 = DOTP_U_W
6081 { 1489, 3, 1, 4, 857, 0, 0, 733, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1489 = DOTP_U_H
6082 { 1488, 3, 1, 4, 857, 0, 0, 730, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1488 = DOTP_U_D
6083 { 1487, 3, 1, 4, 857, 0, 0, 736, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1487 = DOTP_S_W
6084 { 1486, 3, 1, 4, 857, 0, 0, 733, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1486 = DOTP_S_H
6085 { 1485, 3, 1, 4, 857, 0, 0, 730, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1485 = DOTP_S_D
6086 { 1484, 3, 1, 4, 546, 0, 0, 235, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1484 = DMUL_R6
6087 { 1483, 3, 1, 4, 1012, 0, 0, 235, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1483 = DMULU
6088 { 1482, 2, 0, 4, 1014, 0, 2, 389, MipsImpOpBase + 20, 0|(1ULL<<MCID::Commutable), 0x1ULL }, // Inst #1482 = DMULTu
6089 { 1481, 2, 0, 4, 1013, 0, 2, 389, MipsImpOpBase + 20, 0|(1ULL<<MCID::Commutable), 0x1ULL }, // Inst #1481 = DMULT
6090 { 1480, 3, 1, 4, 1261, 0, 5, 235, MipsImpOpBase + 15, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #1480 = DMUL
6091 { 1479, 3, 1, 4, 548, 0, 0, 235, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1479 = DMUHU
6092 { 1478, 3, 1, 4, 547, 0, 0, 235, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1478 = DMUH
6093 { 1477, 3, 1, 4, 1147, 0, 0, 724, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1477 = DMTGC0
6094 { 1476, 2, 2, 4, 1254, 0, 0, 366, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1476 = DMTC2_OCTEON
6095 { 1475, 3, 1, 4, 541, 0, 0, 727, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1475 = DMTC2
6096 { 1474, 2, 1, 4, 476, 0, 0, 416, MipsImpOpBase + 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL }, // Inst #1474 = DMTC1
6097 { 1473, 3, 1, 4, 540, 0, 0, 724, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1473 = DMTC0
6098 { 1472, 1, 1, 4, 1138, 0, 0, 197, MipsImpOpBase + 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1472 = DMT
6099 { 1471, 3, 1, 4, 556, 0, 0, 235, MipsImpOpBase + 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // Inst #1471 = DMODU
6100 { 1470, 3, 1, 4, 554, 0, 0, 235, MipsImpOpBase + 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // Inst #1470 = DMOD
6101 { 1469, 3, 1, 4, 1146, 0, 0, 716, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1469 = DMFGC0
6102 { 1468, 2, 2, 4, 1253, 0, 0, 366, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1468 = DMFC2_OCTEON
6103 { 1467, 3, 1, 4, 539, 0, 0, 721, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1467 = DMFC2
6104 { 1466, 2, 1, 4, 475, 0, 0, 719, MipsImpOpBase + 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL }, // Inst #1466 = DMFC1
6105 { 1465, 3, 1, 4, 538, 0, 0, 716, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1465 = DMFC0
6106 { 1464, 4, 1, 4, 474, 0, 0, 707, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1464 = DLSA_R6
6107 { 1463, 4, 1, 4, 474, 0, 0, 707, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1463 = DLSA
6108 { 1462, 1, 1, 4, 1131, 0, 0, 197, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1462 = DI_MMR6
6109 { 1461, 1, 1, 4, 1114, 0, 0, 197, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1461 = DI_MM
6110 { 1460, 3, 1, 4, 579, 0, 0, 160, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1460 = DIV_U_W
6111 { 1459, 3, 1, 4, 579, 0, 0, 157, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1459 = DIV_U_H
6112 { 1458, 3, 1, 4, 579, 0, 0, 154, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1458 = DIV_U_D
6113 { 1457, 3, 1, 4, 579, 0, 0, 551, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1457 = DIV_U_B
6114 { 1456, 3, 1, 4, 578, 0, 0, 160, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1456 = DIV_S_W
6115 { 1455, 3, 1, 4, 578, 0, 0, 157, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1455 = DIV_S_H
6116 { 1454, 3, 1, 4, 578, 0, 0, 154, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1454 = DIV_S_D
6117 { 1453, 3, 1, 4, 578, 0, 0, 551, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1453 = DIV_S_B
6118 { 1452, 3, 1, 4, 1010, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // Inst #1452 = DIV_MMR6
6119 { 1451, 3, 1, 4, 1009, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // Inst #1451 = DIVU_MMR6
6120 { 1450, 3, 1, 4, 550, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // Inst #1450 = DIVU
6121 { 1449, 3, 1, 4, 549, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // Inst #1449 = DIV
6122 { 1448, 5, 1, 4, 473, 0, 0, 711, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1448 = DINSU
6123 { 1447, 5, 1, 4, 473, 0, 0, 711, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1447 = DINSM
6124 { 1446, 5, 1, 4, 473, 0, 0, 711, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1446 = DINS
6125 { 1445, 1, 1, 4, 444, 0, 0, 197, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1445 = DI
6126 { 1444, 4, 1, 4, 472, 0, 0, 651, MipsImpOpBase + 0, 0, 0x1ULL }, // Inst #1444 = DEXTU
6127 { 1443, 4, 1, 4, 472, 0, 0, 651, MipsImpOpBase + 0, 0, 0x1ULL }, // Inst #1443 = DEXTM
6128 { 1442, 4, 1, 4, 965, 0, 0, 655, MipsImpOpBase + 0, 0, 0x1ULL }, // Inst #1442 = DEXT64_32
6129 { 1441, 4, 1, 4, 472, 0, 0, 651, MipsImpOpBase + 0, 0, 0x1ULL }, // Inst #1441 = DEXT
6130 { 1440, 0, 0, 4, 1085, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1440 = DERET_MMR6
6131 { 1439, 0, 0, 4, 1049, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1439 = DERET_MM
6132 { 1438, 0, 0, 4, 435, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1438 = DERET
6133 { 1437, 3, 1, 4, 555, 0, 0, 235, MipsImpOpBase + 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // Inst #1437 = DDIVU
6134 { 1436, 3, 1, 4, 553, 0, 0, 235, MipsImpOpBase + 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // Inst #1436 = DDIV
6135 { 1435, 2, 1, 4, 471, 0, 0, 389, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1435 = DCLZ_R6
6136 { 1434, 2, 1, 4, 970, 0, 0, 389, MipsImpOpBase + 0, 0, 0x1ULL }, // Inst #1434 = DCLZ
6137 { 1433, 2, 1, 4, 470, 0, 0, 389, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1433 = DCLO_R6
6138 { 1432, 2, 1, 4, 969, 0, 0, 389, MipsImpOpBase + 0, 0, 0x1ULL }, // Inst #1432 = DCLO
6139 { 1431, 2, 1, 4, 469, 0, 0, 389, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1431 = DBITSWAP
6140 { 1430, 3, 1, 4, 468, 0, 0, 232, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1430 = DAUI
6141 { 1429, 3, 1, 4, 467, 0, 0, 704, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1429 = DATI
6142 { 1428, 4, 1, 4, 466, 0, 0, 707, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1428 = DALIGN
6143 { 1427, 3, 1, 4, 465, 0, 0, 704, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1427 = DAHI
6144 { 1426, 3, 1, 4, 464, 0, 0, 235, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #1426 = DADDu
6145 { 1425, 3, 1, 4, 463, 0, 0, 232, MipsImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL }, // Inst #1425 = DADDiu
6146 { 1424, 3, 1, 4, 968, 0, 0, 232, MipsImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1424 = DADDi
6147 { 1423, 3, 1, 4, 462, 0, 0, 235, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1423 = DADD
6148 { 1422, 2, 0, 4, 894, 0, 1, 580, MipsImpOpBase + 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1422 = CmpiRxImmX16
6149 { 1421, 2, 0, 2, 894, 0, 1, 580, MipsImpOpBase + 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1421 = CmpiRxImm16
6150 { 1420, 2, 0, 2, 894, 0, 1, 406, MipsImpOpBase + 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1420 = CmpRxRy16
6151 { 1419, 3, 1, 4, 1294, 0, 0, 701, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1419 = C_UN_S_MM
6152 { 1418, 3, 1, 4, 846, 0, 0, 701, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1418 = C_UN_S
6153 { 1417, 3, 1, 4, 1293, 0, 0, 698, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1417 = C_UN_D64_MM
6154 { 1416, 3, 1, 4, 845, 0, 0, 698, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1416 = C_UN_D64
6155 { 1415, 3, 1, 4, 1293, 0, 0, 695, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1415 = C_UN_D32_MM
6156 { 1414, 3, 1, 4, 845, 0, 0, 695, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1414 = C_UN_D32
6157 { 1413, 3, 1, 4, 1296, 0, 0, 701, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1413 = C_ULT_S_MM
6158 { 1412, 3, 1, 4, 846, 0, 0, 701, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1412 = C_ULT_S
6159 { 1411, 3, 1, 4, 1295, 0, 0, 698, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1411 = C_ULT_D64_MM
6160 { 1410, 3, 1, 4, 845, 0, 0, 698, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1410 = C_ULT_D64
6161 { 1409, 3, 1, 4, 1295, 0, 0, 695, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1409 = C_ULT_D32_MM
6162 { 1408, 3, 1, 4, 845, 0, 0, 695, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1408 = C_ULT_D32
6163 { 1407, 3, 1, 4, 1296, 0, 0, 701, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1407 = C_ULE_S_MM
6164 { 1406, 3, 1, 4, 846, 0, 0, 701, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1406 = C_ULE_S
6165 { 1405, 3, 1, 4, 1295, 0, 0, 698, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1405 = C_ULE_D64_MM
6166 { 1404, 3, 1, 4, 845, 0, 0, 698, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1404 = C_ULE_D64
6167 { 1403, 3, 1, 4, 1295, 0, 0, 695, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1403 = C_ULE_D32_MM
6168 { 1402, 3, 1, 4, 845, 0, 0, 695, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1402 = C_ULE_D32
6169 { 1401, 3, 1, 4, 1296, 0, 0, 701, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1401 = C_UEQ_S_MM
6170 { 1400, 3, 1, 4, 846, 0, 0, 701, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1400 = C_UEQ_S
6171 { 1399, 3, 1, 4, 1295, 0, 0, 698, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1399 = C_UEQ_D64_MM
6172 { 1398, 3, 1, 4, 845, 0, 0, 698, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1398 = C_UEQ_D64
6173 { 1397, 3, 1, 4, 1295, 0, 0, 695, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1397 = C_UEQ_D32_MM
6174 { 1396, 3, 1, 4, 845, 0, 0, 695, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1396 = C_UEQ_D32
6175 { 1395, 3, 1, 4, 1294, 0, 0, 701, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1395 = C_SF_S_MM
6176 { 1394, 3, 1, 4, 846, 0, 0, 701, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1394 = C_SF_S
6177 { 1393, 3, 1, 4, 1293, 0, 0, 698, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1393 = C_SF_D64_MM
6178 { 1392, 3, 1, 4, 845, 0, 0, 698, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1392 = C_SF_D64
6179 { 1391, 3, 1, 4, 1293, 0, 0, 695, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1391 = C_SF_D32_MM
6180 { 1390, 3, 1, 4, 845, 0, 0, 695, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1390 = C_SF_D32
6181 { 1389, 3, 1, 4, 1296, 0, 0, 701, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1389 = C_SEQ_S_MM
6182 { 1388, 3, 1, 4, 846, 0, 0, 701, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1388 = C_SEQ_S
6183 { 1387, 3, 1, 4, 1295, 0, 0, 698, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1387 = C_SEQ_D64_MM
6184 { 1386, 3, 1, 4, 845, 0, 0, 698, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1386 = C_SEQ_D64
6185 { 1385, 3, 1, 4, 1295, 0, 0, 695, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1385 = C_SEQ_D32_MM
6186 { 1384, 3, 1, 4, 845, 0, 0, 695, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1384 = C_SEQ_D32
6187 { 1383, 3, 1, 4, 1296, 0, 0, 701, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1383 = C_OLT_S_MM
6188 { 1382, 3, 1, 4, 846, 0, 0, 701, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1382 = C_OLT_S
6189 { 1381, 3, 1, 4, 1295, 0, 0, 698, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1381 = C_OLT_D64_MM
6190 { 1380, 3, 1, 4, 845, 0, 0, 698, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1380 = C_OLT_D64
6191 { 1379, 3, 1, 4, 1295, 0, 0, 695, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1379 = C_OLT_D32_MM
6192 { 1378, 3, 1, 4, 845, 0, 0, 695, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1378 = C_OLT_D32
6193 { 1377, 3, 1, 4, 1296, 0, 0, 701, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1377 = C_OLE_S_MM
6194 { 1376, 3, 1, 4, 846, 0, 0, 701, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1376 = C_OLE_S
6195 { 1375, 3, 1, 4, 1295, 0, 0, 698, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1375 = C_OLE_D64_MM
6196 { 1374, 3, 1, 4, 845, 0, 0, 698, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1374 = C_OLE_D64
6197 { 1373, 3, 1, 4, 1295, 0, 0, 695, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1373 = C_OLE_D32_MM
6198 { 1372, 3, 1, 4, 845, 0, 0, 695, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1372 = C_OLE_D32
6199 { 1371, 3, 1, 4, 1296, 0, 0, 701, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1371 = C_NGT_S_MM
6200 { 1370, 3, 1, 4, 846, 0, 0, 701, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1370 = C_NGT_S
6201 { 1369, 3, 1, 4, 1295, 0, 0, 698, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1369 = C_NGT_D64_MM
6202 { 1368, 3, 1, 4, 845, 0, 0, 698, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1368 = C_NGT_D64
6203 { 1367, 3, 1, 4, 1295, 0, 0, 695, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1367 = C_NGT_D32_MM
6204 { 1366, 3, 1, 4, 845, 0, 0, 695, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1366 = C_NGT_D32
6205 { 1365, 3, 1, 4, 1296, 0, 0, 701, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1365 = C_NGL_S_MM
6206 { 1364, 3, 1, 4, 846, 0, 0, 701, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1364 = C_NGL_S
6207 { 1363, 3, 1, 4, 1295, 0, 0, 698, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1363 = C_NGL_D64_MM
6208 { 1362, 3, 1, 4, 845, 0, 0, 698, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1362 = C_NGL_D64
6209 { 1361, 3, 1, 4, 1295, 0, 0, 695, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1361 = C_NGL_D32_MM
6210 { 1360, 3, 1, 4, 845, 0, 0, 695, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1360 = C_NGL_D32
6211 { 1359, 3, 1, 4, 1298, 0, 0, 701, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1359 = C_NGLE_S_MM
6212 { 1358, 3, 1, 4, 846, 0, 0, 701, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1358 = C_NGLE_S
6213 { 1357, 3, 1, 4, 1297, 0, 0, 698, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1357 = C_NGLE_D64_MM
6214 { 1356, 3, 1, 4, 845, 0, 0, 698, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1356 = C_NGLE_D64
6215 { 1355, 3, 1, 4, 1297, 0, 0, 695, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1355 = C_NGLE_D32_MM
6216 { 1354, 3, 1, 4, 845, 0, 0, 695, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1354 = C_NGLE_D32
6217 { 1353, 3, 1, 4, 1296, 0, 0, 701, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1353 = C_NGE_S_MM
6218 { 1352, 3, 1, 4, 846, 0, 0, 701, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1352 = C_NGE_S
6219 { 1351, 3, 1, 4, 1295, 0, 0, 698, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1351 = C_NGE_D64_MM
6220 { 1350, 3, 1, 4, 845, 0, 0, 698, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1350 = C_NGE_D64
6221 { 1349, 3, 1, 4, 1295, 0, 0, 695, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1349 = C_NGE_D32_MM
6222 { 1348, 3, 1, 4, 845, 0, 0, 695, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1348 = C_NGE_D32
6223 { 1347, 3, 1, 4, 1294, 0, 0, 701, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1347 = C_LT_S_MM
6224 { 1346, 3, 1, 4, 846, 0, 0, 701, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1346 = C_LT_S
6225 { 1345, 3, 1, 4, 1293, 0, 0, 698, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1345 = C_LT_D64_MM
6226 { 1344, 3, 1, 4, 845, 0, 0, 698, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1344 = C_LT_D64
6227 { 1343, 3, 1, 4, 1293, 0, 0, 695, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1343 = C_LT_D32_MM
6228 { 1342, 3, 1, 4, 845, 0, 0, 695, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1342 = C_LT_D32
6229 { 1341, 3, 1, 4, 1294, 0, 0, 701, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1341 = C_LE_S_MM
6230 { 1340, 3, 1, 4, 846, 0, 0, 701, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1340 = C_LE_S
6231 { 1339, 3, 1, 4, 1293, 0, 0, 698, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1339 = C_LE_D64_MM
6232 { 1338, 3, 1, 4, 845, 0, 0, 698, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1338 = C_LE_D64
6233 { 1337, 3, 1, 4, 1293, 0, 0, 695, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1337 = C_LE_D32_MM
6234 { 1336, 3, 1, 4, 845, 0, 0, 695, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1336 = C_LE_D32
6235 { 1335, 3, 1, 4, 1292, 0, 0, 701, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1335 = C_F_S_MM
6236 { 1334, 3, 1, 4, 846, 0, 0, 701, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1334 = C_F_S
6237 { 1333, 3, 1, 4, 1291, 0, 0, 698, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1333 = C_F_D64_MM
6238 { 1332, 3, 1, 4, 845, 0, 0, 698, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1332 = C_F_D64
6239 { 1331, 3, 1, 4, 1291, 0, 0, 695, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1331 = C_F_D32_MM
6240 { 1330, 3, 1, 4, 845, 0, 0, 695, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1330 = C_F_D32
6241 { 1329, 3, 1, 4, 1294, 0, 0, 701, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1329 = C_EQ_S_MM
6242 { 1328, 3, 1, 4, 846, 0, 0, 701, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1328 = C_EQ_S
6243 { 1327, 3, 1, 4, 1293, 0, 0, 698, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1327 = C_EQ_D64_MM
6244 { 1326, 3, 1, 4, 845, 0, 0, 698, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1326 = C_EQ_D64
6245 { 1325, 3, 1, 4, 1293, 0, 0, 695, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1325 = C_EQ_D32_MM
6246 { 1324, 3, 1, 4, 845, 0, 0, 695, MipsImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1324 = C_EQ_D32
6247 { 1323, 2, 1, 4, 1341, 0, 0, 643, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1323 = CVT_W_S_MMR6
6248 { 1322, 2, 1, 4, 1280, 0, 0, 643, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1322 = CVT_W_S_MM
6249 { 1321, 2, 1, 4, 843, 0, 0, 643, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1321 = CVT_W_S
6250 { 1320, 2, 1, 4, 1280, 0, 0, 641, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1320 = CVT_W_D64_MM
6251 { 1319, 2, 1, 4, 843, 0, 0, 641, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1319 = CVT_W_D64
6252 { 1318, 2, 1, 4, 1280, 0, 0, 639, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1318 = CVT_W_D32_MM
6253 { 1317, 2, 1, 4, 843, 0, 0, 639, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1317 = CVT_W_D32
6254 { 1316, 2, 1, 4, 1341, 0, 0, 643, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1316 = CVT_S_W_MMR6
6255 { 1315, 2, 1, 4, 1280, 0, 0, 643, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1315 = CVT_S_W_MM
6256 { 1314, 2, 1, 4, 843, 0, 0, 643, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1314 = CVT_S_W
6257 { 1313, 2, 1, 4, 649, 0, 0, 641, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1313 = CVT_S_PU64
6258 { 1312, 2, 1, 4, 649, 0, 0, 641, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1312 = CVT_S_PL64
6259 { 1311, 2, 1, 4, 1341, 0, 0, 637, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1311 = CVT_S_L_MMR6
6260 { 1310, 2, 1, 4, 843, 0, 0, 641, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1310 = CVT_S_L
6261 { 1309, 2, 1, 4, 1280, 0, 0, 641, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1309 = CVT_S_D64_MM
6262 { 1308, 2, 1, 4, 843, 0, 0, 641, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1308 = CVT_S_D64
6263 { 1307, 2, 1, 4, 1280, 0, 0, 639, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1307 = CVT_S_D32_MM
6264 { 1306, 2, 1, 4, 843, 0, 0, 639, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1306 = CVT_S_D32
6265 { 1305, 2, 1, 4, 1264, 0, 0, 635, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1305 = CVT_PW_PS64
6266 { 1304, 3, 1, 4, 844, 0, 0, 692, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1304 = CVT_PS_S64
6267 { 1303, 2, 1, 4, 1264, 0, 0, 635, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1303 = CVT_PS_PW64
6268 { 1302, 2, 1, 4, 1341, 0, 0, 637, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1302 = CVT_L_S_MMR6
6269 { 1301, 2, 1, 4, 1280, 0, 0, 637, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1301 = CVT_L_S_MM
6270 { 1300, 2, 1, 4, 843, 0, 0, 637, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1300 = CVT_L_S
6271 { 1299, 2, 1, 4, 1341, 0, 0, 635, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1299 = CVT_L_D_MMR6
6272 { 1298, 2, 1, 4, 1280, 0, 0, 635, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1298 = CVT_L_D64_MM
6273 { 1297, 2, 1, 4, 843, 0, 0, 635, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1297 = CVT_L_D64
6274 { 1296, 2, 1, 4, 1341, 0, 0, 635, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1296 = CVT_D_L_MMR6
6275 { 1295, 2, 1, 4, 1280, 0, 0, 637, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1295 = CVT_D64_W_MM
6276 { 1294, 2, 1, 4, 843, 0, 0, 637, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1294 = CVT_D64_W
6277 { 1293, 2, 1, 4, 1280, 0, 0, 637, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1293 = CVT_D64_S_MM
6278 { 1292, 2, 1, 4, 843, 0, 0, 637, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1292 = CVT_D64_S
6279 { 1291, 2, 1, 4, 843, 0, 0, 635, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1291 = CVT_D64_L
6280 { 1290, 2, 1, 4, 1280, 0, 0, 690, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1290 = CVT_D32_W_MM
6281 { 1289, 2, 1, 4, 843, 0, 0, 690, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1289 = CVT_D32_W
6282 { 1288, 2, 1, 4, 1280, 0, 0, 690, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1288 = CVT_D32_S_MM
6283 { 1287, 2, 1, 4, 843, 0, 0, 690, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1287 = CVT_D32_S
6284 { 1286, 2, 0, 4, 780, 0, 0, 688, MipsImpOpBase + 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1286 = CTCMSA
6285 { 1285, 2, 1, 4, 1137, 0, 0, 686, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1285 = CTC2_MM
6286 { 1284, 2, 1, 4, 1329, 0, 0, 684, MipsImpOpBase + 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1284 = CTC1_MM
6287 { 1283, 2, 1, 4, 461, 0, 0, 684, MipsImpOpBase + 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1283 = CTC1
6288 { 1282, 3, 1, 4, 1244, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1282 = CRC32W
6289 { 1281, 3, 1, 4, 1243, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1281 = CRC32H
6290 { 1280, 3, 1, 4, 1248, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1280 = CRC32D
6291 { 1279, 3, 1, 4, 1247, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1279 = CRC32CW
6292 { 1278, 3, 1, 4, 1246, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1278 = CRC32CH
6293 { 1277, 3, 1, 4, 1249, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1277 = CRC32CD
6294 { 1276, 3, 1, 4, 1245, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1276 = CRC32CB
6295 { 1275, 3, 1, 4, 1242, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1275 = CRC32B
6296 { 1274, 3, 1, 4, 874, 0, 0, 681, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1274 = COPY_U_W
6297 { 1273, 3, 1, 4, 874, 0, 0, 678, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1273 = COPY_U_H
6298 { 1272, 3, 1, 4, 874, 0, 0, 672, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1272 = COPY_U_B
6299 { 1271, 3, 1, 4, 607, 0, 0, 681, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1271 = COPY_S_W
6300 { 1270, 3, 1, 4, 607, 0, 0, 678, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1270 = COPY_S_H
6301 { 1269, 3, 1, 4, 607, 0, 0, 675, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1269 = COPY_S_D
6302 { 1268, 3, 1, 4, 607, 0, 0, 672, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1268 = COPY_S_B
6303 { 1267, 3, 1, 4, 1336, 0, 0, 669, MipsImpOpBase + 0, 0, 0x16ULL }, // Inst #1267 = CMP_UN_S_MMR6
6304 { 1266, 3, 1, 4, 614, 0, 0, 669, MipsImpOpBase + 0, 0, 0x16ULL }, // Inst #1266 = CMP_UN_S
6305 { 1265, 3, 1, 4, 1335, 0, 0, 666, MipsImpOpBase + 0, 0, 0x16ULL }, // Inst #1265 = CMP_UN_D_MMR6
6306 { 1264, 3, 1, 4, 613, 0, 0, 666, MipsImpOpBase + 0, 0, 0x16ULL }, // Inst #1264 = CMP_UN_D
6307 { 1263, 3, 1, 4, 1338, 0, 0, 669, MipsImpOpBase + 0, 0, 0x16ULL }, // Inst #1263 = CMP_ULT_S_MMR6
6308 { 1262, 3, 1, 4, 622, 0, 0, 669, MipsImpOpBase + 0, 0, 0x16ULL }, // Inst #1262 = CMP_ULT_S
6309 { 1261, 3, 1, 4, 1337, 0, 0, 666, MipsImpOpBase + 0, 0, 0x16ULL }, // Inst #1261 = CMP_ULT_D_MMR6
6310 { 1260, 3, 1, 4, 621, 0, 0, 666, MipsImpOpBase + 0, 0, 0x16ULL }, // Inst #1260 = CMP_ULT_D
6311 { 1259, 3, 1, 4, 1338, 0, 0, 669, MipsImpOpBase + 0, 0, 0x16ULL }, // Inst #1259 = CMP_ULE_S_MMR6
6312 { 1258, 3, 1, 4, 626, 0, 0, 669, MipsImpOpBase + 0, 0, 0x16ULL }, // Inst #1258 = CMP_ULE_S
6313 { 1257, 3, 1, 4, 1337, 0, 0, 666, MipsImpOpBase + 0, 0, 0x16ULL }, // Inst #1257 = CMP_ULE_D_MMR6
6314 { 1256, 3, 1, 4, 625, 0, 0, 666, MipsImpOpBase + 0, 0, 0x16ULL }, // Inst #1256 = CMP_ULE_D
6315 { 1255, 3, 1, 4, 1338, 0, 0, 669, MipsImpOpBase + 0, 0, 0x16ULL }, // Inst #1255 = CMP_UEQ_S_MMR6
6316 { 1254, 3, 1, 4, 616, 0, 0, 669, MipsImpOpBase + 0, 0, 0x16ULL }, // Inst #1254 = CMP_UEQ_S
6317 { 1253, 3, 1, 4, 1337, 0, 0, 666, MipsImpOpBase + 0, 0, 0x16ULL }, // Inst #1253 = CMP_UEQ_D_MMR6
6318 { 1252, 3, 1, 4, 615, 0, 0, 666, MipsImpOpBase + 0, 0, 0x16ULL }, // Inst #1252 = CMP_UEQ_D
6319 { 1251, 3, 1, 4, 1338, 0, 0, 669, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1251 = CMP_SUN_S_MMR6
6320 { 1250, 3, 1, 4, 644, 0, 0, 669, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1250 = CMP_SUN_S
6321 { 1249, 3, 1, 4, 1337, 0, 0, 666, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1249 = CMP_SUN_D_MMR6
6322 { 1248, 3, 1, 4, 643, 0, 0, 666, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1248 = CMP_SUN_D
6323 { 1247, 3, 1, 4, 1340, 0, 0, 669, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1247 = CMP_SULT_S_MMR6
6324 { 1246, 3, 1, 4, 642, 0, 0, 669, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1246 = CMP_SULT_S
6325 { 1245, 3, 1, 4, 1339, 0, 0, 666, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1245 = CMP_SULT_D_MMR6
6326 { 1244, 3, 1, 4, 641, 0, 0, 666, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1244 = CMP_SULT_D
6327 { 1243, 3, 1, 4, 1340, 0, 0, 669, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1243 = CMP_SULE_S_MMR6
6328 { 1242, 3, 1, 4, 640, 0, 0, 669, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1242 = CMP_SULE_S
6329 { 1241, 3, 1, 4, 1339, 0, 0, 666, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1241 = CMP_SULE_D_MMR6
6330 { 1240, 3, 1, 4, 639, 0, 0, 666, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1240 = CMP_SULE_D
6331 { 1239, 3, 1, 4, 1340, 0, 0, 669, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1239 = CMP_SUEQ_S_MMR6
6332 { 1238, 3, 1, 4, 638, 0, 0, 669, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1238 = CMP_SUEQ_S
6333 { 1237, 3, 1, 4, 1339, 0, 0, 666, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1237 = CMP_SUEQ_D_MMR6
6334 { 1236, 3, 1, 4, 637, 0, 0, 666, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1236 = CMP_SUEQ_D
6335 { 1235, 3, 1, 4, 1338, 0, 0, 669, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1235 = CMP_SLT_S_MMR6
6336 { 1234, 3, 1, 4, 636, 0, 0, 669, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1234 = CMP_SLT_S
6337 { 1233, 3, 1, 4, 1337, 0, 0, 666, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1233 = CMP_SLT_D_MMR6
6338 { 1232, 3, 1, 4, 635, 0, 0, 666, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1232 = CMP_SLT_D
6339 { 1231, 3, 1, 4, 1338, 0, 0, 669, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1231 = CMP_SLE_S_MMR6
6340 { 1230, 3, 1, 4, 634, 0, 0, 669, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1230 = CMP_SLE_S
6341 { 1229, 3, 1, 4, 1337, 0, 0, 666, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1229 = CMP_SLE_D_MMR6
6342 { 1228, 3, 1, 4, 633, 0, 0, 666, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1228 = CMP_SLE_D
6343 { 1227, 3, 1, 4, 1338, 0, 0, 669, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1227 = CMP_SEQ_S_MMR6
6344 { 1226, 3, 1, 4, 632, 0, 0, 669, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1226 = CMP_SEQ_S
6345 { 1225, 3, 1, 4, 1337, 0, 0, 666, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1225 = CMP_SEQ_D_MMR6
6346 { 1224, 3, 1, 4, 631, 0, 0, 666, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1224 = CMP_SEQ_D
6347 { 1223, 3, 1, 4, 1338, 0, 0, 669, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1223 = CMP_SAF_S_MMR6
6348 { 1222, 3, 1, 4, 630, 0, 0, 669, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1222 = CMP_SAF_S
6349 { 1221, 3, 1, 4, 1337, 0, 0, 666, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1221 = CMP_SAF_D_MMR6
6350 { 1220, 3, 1, 4, 629, 0, 0, 666, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1220 = CMP_SAF_D
6351 { 1219, 3, 1, 4, 1336, 0, 0, 669, MipsImpOpBase + 0, 0, 0x16ULL }, // Inst #1219 = CMP_LT_S_MMR6
6352 { 1218, 3, 1, 4, 620, 0, 0, 669, MipsImpOpBase + 0, 0, 0x16ULL }, // Inst #1218 = CMP_LT_S
6353 { 1217, 2, 0, 4, 1559, 0, 1, 535, MipsImpOpBase + 14, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1217 = CMP_LT_PH_MM
6354 { 1216, 2, 0, 4, 1408, 0, 1, 535, MipsImpOpBase + 14, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1216 = CMP_LT_PH
6355 { 1215, 3, 1, 4, 1335, 0, 0, 666, MipsImpOpBase + 0, 0, 0x16ULL }, // Inst #1215 = CMP_LT_D_MMR6
6356 { 1214, 3, 1, 4, 619, 0, 0, 666, MipsImpOpBase + 0, 0, 0x16ULL }, // Inst #1214 = CMP_LT_D
6357 { 1213, 3, 1, 4, 1336, 0, 0, 669, MipsImpOpBase + 0, 0, 0x16ULL }, // Inst #1213 = CMP_LE_S_MMR6
6358 { 1212, 3, 1, 4, 624, 0, 0, 669, MipsImpOpBase + 0, 0, 0x16ULL }, // Inst #1212 = CMP_LE_S
6359 { 1211, 2, 0, 4, 1558, 0, 1, 535, MipsImpOpBase + 14, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1211 = CMP_LE_PH_MM
6360 { 1210, 2, 0, 4, 1407, 0, 1, 535, MipsImpOpBase + 14, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1210 = CMP_LE_PH
6361 { 1209, 3, 1, 4, 1335, 0, 0, 666, MipsImpOpBase + 0, 0, 0x16ULL }, // Inst #1209 = CMP_LE_D_MMR6
6362 { 1208, 3, 1, 4, 623, 0, 0, 666, MipsImpOpBase + 0, 0, 0x16ULL }, // Inst #1208 = CMP_LE_D
6363 { 1207, 3, 1, 4, 628, 0, 0, 669, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1207 = CMP_F_S
6364 { 1206, 3, 1, 4, 627, 0, 0, 666, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1206 = CMP_F_D
6365 { 1205, 3, 1, 4, 1336, 0, 0, 669, MipsImpOpBase + 0, 0, 0x16ULL }, // Inst #1205 = CMP_EQ_S_MMR6
6366 { 1204, 3, 1, 4, 618, 0, 0, 669, MipsImpOpBase + 0, 0, 0x16ULL }, // Inst #1204 = CMP_EQ_S
6367 { 1203, 2, 0, 4, 1557, 0, 1, 535, MipsImpOpBase + 14, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1203 = CMP_EQ_PH_MM
6368 { 1202, 2, 0, 4, 1406, 0, 1, 535, MipsImpOpBase + 14, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1202 = CMP_EQ_PH
6369 { 1201, 3, 1, 4, 1335, 0, 0, 666, MipsImpOpBase + 0, 0, 0x16ULL }, // Inst #1201 = CMP_EQ_D_MMR6
6370 { 1200, 3, 1, 4, 617, 0, 0, 666, MipsImpOpBase + 0, 0, 0x16ULL }, // Inst #1200 = CMP_EQ_D
6371 { 1199, 3, 1, 4, 1336, 0, 0, 669, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1199 = CMP_AF_S_MMR6
6372 { 1198, 3, 1, 4, 1335, 0, 0, 666, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1198 = CMP_AF_D_MMR6
6373 { 1197, 2, 0, 4, 1556, 0, 1, 535, MipsImpOpBase + 14, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1197 = CMPU_LT_QB_MM
6374 { 1196, 2, 0, 4, 1405, 0, 1, 535, MipsImpOpBase + 14, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1196 = CMPU_LT_QB
6375 { 1195, 2, 0, 4, 1555, 0, 1, 535, MipsImpOpBase + 14, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1195 = CMPU_LE_QB_MM
6376 { 1194, 2, 0, 4, 1404, 0, 1, 535, MipsImpOpBase + 14, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1194 = CMPU_LE_QB
6377 { 1193, 2, 0, 4, 1554, 0, 1, 535, MipsImpOpBase + 14, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1193 = CMPU_EQ_QB_MM
6378 { 1192, 2, 0, 4, 1403, 0, 1, 535, MipsImpOpBase + 14, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1192 = CMPU_EQ_QB
6379 { 1191, 3, 1, 4, 1553, 0, 0, 663, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1191 = CMPGU_LT_QB_MM
6380 { 1190, 3, 1, 4, 1402, 0, 0, 663, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1190 = CMPGU_LT_QB
6381 { 1189, 3, 1, 4, 1552, 0, 0, 663, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1189 = CMPGU_LE_QB_MM
6382 { 1188, 3, 1, 4, 1401, 0, 0, 663, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1188 = CMPGU_LE_QB
6383 { 1187, 3, 1, 4, 1551, 0, 0, 663, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1187 = CMPGU_EQ_QB_MM
6384 { 1186, 3, 1, 4, 1400, 0, 0, 663, MipsImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1186 = CMPGU_EQ_QB
6385 { 1185, 3, 1, 4, 1669, 0, 1, 663, MipsImpOpBase + 14, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1185 = CMPGDU_LT_QB_MMR2
6386 { 1184, 3, 1, 4, 1505, 0, 1, 663, MipsImpOpBase + 14, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1184 = CMPGDU_LT_QB
6387 { 1183, 3, 1, 4, 1668, 0, 1, 663, MipsImpOpBase + 14, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1183 = CMPGDU_LE_QB_MMR2
6388 { 1182, 3, 1, 4, 1504, 0, 1, 663, MipsImpOpBase + 14, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1182 = CMPGDU_LE_QB
6389 { 1181, 3, 1, 4, 1667, 0, 1, 663, MipsImpOpBase + 14, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1181 = CMPGDU_EQ_QB_MMR2
6390 { 1180, 3, 1, 4, 1503, 0, 1, 663, MipsImpOpBase + 14, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1180 = CMPGDU_EQ_QB
6391 { 1179, 2, 1, 4, 460, 0, 0, 152, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1179 = CLZ_R6
6392 { 1178, 2, 1, 4, 945, 0, 0, 152, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1178 = CLZ_MMR6
6393 { 1177, 2, 1, 4, 904, 0, 0, 152, MipsImpOpBase + 0, 0, 0x1ULL }, // Inst #1177 = CLZ_MM
6394 { 1176, 2, 1, 4, 747, 0, 0, 152, MipsImpOpBase + 0, 0, 0x1ULL }, // Inst #1176 = CLZ
6395 { 1175, 3, 1, 4, 793, 0, 0, 160, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1175 = CLT_U_W
6396 { 1174, 3, 1, 4, 793, 0, 0, 157, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1174 = CLT_U_H
6397 { 1173, 3, 1, 4, 793, 0, 0, 154, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1173 = CLT_U_D
6398 { 1172, 3, 1, 4, 793, 0, 0, 551, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1172 = CLT_U_B
6399 { 1171, 3, 1, 4, 793, 0, 0, 160, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1171 = CLT_S_W
6400 { 1170, 3, 1, 4, 793, 0, 0, 157, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1170 = CLT_S_H
6401 { 1169, 3, 1, 4, 793, 0, 0, 154, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1169 = CLT_S_D
6402 { 1168, 3, 1, 4, 793, 0, 0, 551, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1168 = CLT_S_B
6403 { 1167, 3, 1, 4, 793, 0, 0, 566, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1167 = CLTI_U_W
6404 { 1166, 3, 1, 4, 793, 0, 0, 563, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1166 = CLTI_U_H
6405 { 1165, 3, 1, 4, 793, 0, 0, 560, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1165 = CLTI_U_D
6406 { 1164, 3, 1, 4, 793, 0, 0, 557, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1164 = CLTI_U_B
6407 { 1163, 3, 1, 4, 793, 0, 0, 566, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1163 = CLTI_S_W
6408 { 1162, 3, 1, 4, 793, 0, 0, 563, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1162 = CLTI_S_H
6409 { 1161, 3, 1, 4, 793, 0, 0, 560, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1161 = CLTI_S_D
6410 { 1160, 3, 1, 4, 793, 0, 0, 557, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1160 = CLTI_S_B
6411 { 1159, 2, 1, 4, 459, 0, 0, 152, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1159 = CLO_R6
6412 { 1158, 2, 1, 4, 944, 0, 0, 152, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1158 = CLO_MMR6
6413 { 1157, 2, 1, 4, 903, 0, 0, 152, MipsImpOpBase + 0, 0, 0x1ULL }, // Inst #1157 = CLO_MM
6414 { 1156, 2, 1, 4, 746, 0, 0, 152, MipsImpOpBase + 0, 0, 0x1ULL }, // Inst #1156 = CLO
6415 { 1155, 3, 1, 4, 794, 0, 0, 160, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1155 = CLE_U_W
6416 { 1154, 3, 1, 4, 794, 0, 0, 157, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1154 = CLE_U_H
6417 { 1153, 3, 1, 4, 794, 0, 0, 154, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1153 = CLE_U_D
6418 { 1152, 3, 1, 4, 794, 0, 0, 551, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1152 = CLE_U_B
6419 { 1151, 3, 1, 4, 794, 0, 0, 160, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1151 = CLE_S_W
6420 { 1150, 3, 1, 4, 794, 0, 0, 157, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1150 = CLE_S_H
6421 { 1149, 3, 1, 4, 794, 0, 0, 154, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1149 = CLE_S_D
6422 { 1148, 3, 1, 4, 794, 0, 0, 551, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1148 = CLE_S_B
6423 { 1147, 3, 1, 4, 794, 0, 0, 566, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1147 = CLEI_U_W
6424 { 1146, 3, 1, 4, 794, 0, 0, 563, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1146 = CLEI_U_H
6425 { 1145, 3, 1, 4, 794, 0, 0, 560, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1145 = CLEI_U_D
6426 { 1144, 3, 1, 4, 794, 0, 0, 557, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1144 = CLEI_U_B
6427 { 1143, 3, 1, 4, 794, 0, 0, 566, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1143 = CLEI_S_W
6428 { 1142, 3, 1, 4, 794, 0, 0, 563, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1142 = CLEI_S_H
6429 { 1141, 3, 1, 4, 794, 0, 0, 560, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1141 = CLEI_S_D
6430 { 1140, 3, 1, 4, 794, 0, 0, 557, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1140 = CLEI_S_B
6431 { 1139, 2, 1, 4, 1348, 0, 0, 643, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1139 = CLASS_S_MMR6
6432 { 1138, 2, 1, 4, 562, 0, 0, 643, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1138 = CLASS_S
6433 { 1137, 2, 1, 4, 1348, 0, 0, 635, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1137 = CLASS_D_MMR6
6434 { 1136, 2, 1, 4, 563, 0, 0, 635, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1136 = CLASS_D
6435 { 1135, 4, 1, 4, 1252, 0, 0, 659, MipsImpOpBase + 0, 0, 0x1ULL }, // Inst #1135 = CINS_i32
6436 { 1134, 4, 1, 4, 1252, 0, 0, 655, MipsImpOpBase + 0, 0, 0x1ULL }, // Inst #1134 = CINS64_32
6437 { 1133, 4, 1, 4, 1252, 0, 0, 651, MipsImpOpBase + 0, 0, 0x1ULL }, // Inst #1133 = CINS32
6438 { 1132, 4, 1, 4, 1252, 0, 0, 651, MipsImpOpBase + 0, 0, 0x1ULL }, // Inst #1132 = CINS
6439 { 1131, 2, 1, 4, 780, 0, 0, 649, MipsImpOpBase + 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1131 = CFCMSA
6440 { 1130, 2, 1, 4, 1136, 0, 0, 647, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1130 = CFC2_MM
6441 { 1129, 2, 1, 4, 1328, 0, 0, 645, MipsImpOpBase + 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1129 = CFC1_MM
6442 { 1128, 2, 1, 4, 458, 0, 0, 645, MipsImpOpBase + 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1128 = CFC1
6443 { 1127, 3, 1, 4, 795, 0, 0, 160, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1127 = CEQ_W
6444 { 1126, 3, 1, 4, 795, 0, 0, 157, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1126 = CEQ_H
6445 { 1125, 3, 1, 4, 795, 0, 0, 154, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1125 = CEQ_D
6446 { 1124, 3, 1, 4, 795, 0, 0, 551, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1124 = CEQ_B
6447 { 1123, 3, 1, 4, 795, 0, 0, 566, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1123 = CEQI_W
6448 { 1122, 3, 1, 4, 795, 0, 0, 563, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1122 = CEQI_H
6449 { 1121, 3, 1, 4, 795, 0, 0, 560, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1121 = CEQI_D
6450 { 1120, 3, 1, 4, 795, 0, 0, 557, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1120 = CEQI_B
6451 { 1119, 2, 1, 4, 1345, 0, 0, 643, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1119 = CEIL_W_S_MMR6
6452 { 1118, 2, 1, 4, 1281, 0, 0, 643, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1118 = CEIL_W_S_MM
6453 { 1117, 2, 1, 4, 650, 0, 0, 643, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1117 = CEIL_W_S
6454 { 1116, 2, 1, 4, 1281, 0, 0, 639, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1116 = CEIL_W_MM
6455 { 1115, 2, 1, 4, 1345, 0, 0, 639, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1115 = CEIL_W_D_MMR6
6456 { 1114, 2, 1, 4, 650, 0, 0, 641, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1114 = CEIL_W_D64
6457 { 1113, 2, 1, 4, 650, 0, 0, 639, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1113 = CEIL_W_D32
6458 { 1112, 2, 1, 4, 1345, 0, 0, 637, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1112 = CEIL_L_S_MMR6
6459 { 1111, 2, 1, 4, 650, 0, 0, 637, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1111 = CEIL_L_S
6460 { 1110, 2, 1, 4, 1345, 0, 0, 635, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1110 = CEIL_L_D_MMR6
6461 { 1109, 2, 1, 4, 650, 0, 0, 635, MipsImpOpBase + 0, 0, 0x4ULL }, // Inst #1109 = CEIL_L_D64
6462 { 1108, 3, 0, 4, 382, 0, 0, 632, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1108 = CACHE_R6
6463 { 1107, 3, 0, 4, 1235, 0, 0, 632, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1107 = CACHE_MMR6
6464 { 1106, 3, 0, 4, 1213, 0, 0, 632, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1106 = CACHE_MM
6465 { 1105, 3, 0, 4, 1180, 0, 0, 632, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1105 = CACHEE_MM
6466 { 1104, 3, 0, 4, 745, 0, 0, 632, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1104 = CACHEE
6467 { 1103, 3, 0, 4, 744, 0, 0, 632, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1103 = CACHE
6468 { 1102, 1, 0, 4, 1036, 1, 0, 0, MipsImpOpBase + 9, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1102 = BtnezX16
6469 { 1101, 1, 0, 2, 1036, 1, 0, 0, MipsImpOpBase + 9, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1101 = Btnez16
6470 { 1100, 1, 0, 4, 1036, 1, 0, 0, MipsImpOpBase + 9, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1100 = BteqzX16
6471 { 1099, 1, 0, 2, 1036, 1, 0, 0, MipsImpOpBase + 9, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1099 = Bteqz16
6472 { 1098, 0, 0, 2, 1040, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1098 = Break16
6473 { 1097, 2, 0, 4, 1036, 0, 0, 630, MipsImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1097 = BnezRxImmX16
6474 { 1096, 2, 0, 2, 1036, 0, 0, 630, MipsImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1096 = BnezRxImm16
6475 { 1095, 1, 0, 4, 1036, 0, 0, 190, MipsImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1095 = BimmX16
6476 { 1094, 1, 0, 2, 1036, 0, 0, 190, MipsImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1094 = Bimm16
6477 { 1093, 2, 0, 4, 1036, 0, 0, 630, MipsImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1093 = BeqzRxImmX16
6478 { 1092, 2, 0, 2, 1036, 0, 0, 630, MipsImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1092 = BeqzRxImm16
6479 { 1091, 2, 0, 4, 779, 0, 1, 628, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1091 = BZ_W
6480 { 1090, 2, 0, 4, 779, 0, 1, 622, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1090 = BZ_V
6481 { 1089, 2, 0, 4, 779, 0, 1, 626, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1089 = BZ_H
6482 { 1088, 2, 0, 4, 779, 0, 1, 624, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1088 = BZ_D
6483 { 1087, 2, 0, 4, 779, 0, 1, 622, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1087 = BZ_B
6484 { 1086, 3, 1, 4, 656, 0, 0, 160, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1086 = BSET_W
6485 { 1085, 3, 1, 4, 656, 0, 0, 157, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1085 = BSET_H
6486 { 1084, 3, 1, 4, 656, 0, 0, 154, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1084 = BSET_D
6487 { 1083, 3, 1, 4, 656, 0, 0, 551, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1083 = BSET_B
6488 { 1082, 3, 1, 4, 656, 0, 0, 566, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1082 = BSETI_W
6489 { 1081, 3, 1, 4, 656, 0, 0, 563, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1081 = BSETI_H
6490 { 1080, 3, 1, 4, 656, 0, 0, 560, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1080 = BSETI_D
6491 { 1079, 3, 1, 4, 656, 0, 0, 557, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1079 = BSETI_B
6492 { 1078, 4, 1, 4, 654, 0, 0, 618, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1078 = BSEL_V
6493 { 1077, 4, 1, 4, 654, 0, 0, 602, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1077 = BSELI_B
6494 { 1076, 2, 0, 4, 1104, 0, 0, 13, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1076 = BREAK_MMR6
6495 { 1075, 2, 0, 4, 1063, 0, 0, 13, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1075 = BREAK_MM
6496 { 1074, 1, 0, 2, 1104, 0, 0, 0, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1074 = BREAK16_MMR6
6497 { 1073, 1, 0, 2, 1063, 0, 0, 0, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1073 = BREAK16_MM
6498 { 1072, 2, 0, 4, 431, 0, 0, 13, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1072 = BREAK
6499 { 1071, 1, 0, 4, 1550, 0, 0, 190, MipsImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1071 = BPOSGE32_MM
6500 { 1070, 1, 0, 4, 1702, 0, 0, 190, MipsImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1070 = BPOSGE32C_MMR3
6501 { 1069, 1, 0, 4, 1399, 0, 0, 190, MipsImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1069 = BPOSGE32
6502 { 1068, 3, 0, 4, 1082, 0, 1, 194, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1068 = BOVC_MMR6
6503 { 1067, 3, 0, 4, 1029, 0, 1, 194, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #1067 = BOVC
6504 { 1066, 2, 0, 4, 779, 0, 1, 628, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1066 = BNZ_W
6505 { 1065, 2, 0, 4, 779, 0, 1, 622, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1065 = BNZ_V
6506 { 1064, 2, 0, 4, 779, 0, 1, 626, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1064 = BNZ_H
6507 { 1063, 2, 0, 4, 779, 0, 1, 624, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1063 = BNZ_D
6508 { 1062, 2, 0, 4, 779, 0, 1, 622, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1062 = BNZ_B
6509 { 1061, 3, 0, 4, 1082, 0, 1, 194, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1061 = BNVC_MMR6
6510 { 1060, 3, 0, 4, 1029, 0, 1, 194, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #1060 = BNVC
6511 { 1059, 3, 0, 4, 1048, 0, 1, 194, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #1059 = BNE_MM
6512 { 1058, 2, 0, 4, 1084, 0, 1, 357, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL }, // Inst #1058 = BNEZC_MMR6
6513 { 1057, 2, 0, 4, 1047, 0, 1, 357, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1057 = BNEZC_MM
6514 { 1056, 2, 0, 4, 426, 0, 1, 359, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #1056 = BNEZC64
6515 { 1055, 2, 0, 2, 1083, 0, 1, 600, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1055 = BNEZC16_MMR6
6516 { 1054, 2, 0, 4, 1030, 0, 1, 357, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #1054 = BNEZC
6517 { 1053, 2, 0, 4, 1097, 0, 1, 357, MipsImpOpBase + 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1053 = BNEZALC_MMR6
6518 { 1052, 2, 0, 4, 1027, 0, 1, 357, MipsImpOpBase + 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #1052 = BNEZALC
6519 { 1051, 2, 0, 2, 1046, 0, 1, 600, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1051 = BNEZ16_MM
6520 { 1050, 3, 0, 4, 682, 0, 1, 194, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #1050 = BNEL
6521 { 1049, 3, 1, 4, 776, 0, 0, 160, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1049 = BNEG_W
6522 { 1048, 3, 1, 4, 776, 0, 0, 157, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1048 = BNEG_H
6523 { 1047, 3, 1, 4, 776, 0, 0, 154, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1047 = BNEG_D
6524 { 1046, 3, 1, 4, 776, 0, 0, 551, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1046 = BNEG_B
6525 { 1045, 3, 1, 4, 776, 0, 0, 566, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1045 = BNEGI_W
6526 { 1044, 3, 1, 4, 776, 0, 0, 563, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1044 = BNEGI_H
6527 { 1043, 3, 1, 4, 776, 0, 0, 560, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1043 = BNEGI_D
6528 { 1042, 3, 1, 4, 776, 0, 0, 557, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1042 = BNEGI_B
6529 { 1041, 3, 0, 4, 1082, 0, 1, 194, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1041 = BNEC_MMR6
6530 { 1040, 3, 0, 4, 425, 0, 1, 351, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #1040 = BNEC64
6531 { 1039, 3, 0, 4, 1029, 0, 1, 194, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #1039 = BNEC
6532 { 1038, 3, 0, 4, 416, 0, 1, 351, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #1038 = BNE64
6533 { 1037, 3, 0, 4, 681, 0, 1, 194, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #1037 = BNE
6534 { 1036, 4, 1, 4, 777, 0, 0, 618, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1036 = BMZ_V
6535 { 1035, 4, 1, 4, 777, 0, 0, 602, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1035 = BMZI_B
6536 { 1034, 4, 1, 4, 777, 0, 0, 618, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1034 = BMNZ_V
6537 { 1033, 4, 1, 4, 777, 0, 0, 602, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1033 = BMNZI_B
6538 { 1032, 2, 0, 4, 1046, 0, 1, 357, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #1032 = BLTZ_MM
6539 { 1031, 2, 0, 4, 685, 0, 1, 357, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #1031 = BLTZL
6540 { 1030, 2, 0, 4, 1084, 0, 1, 357, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1030 = BLTZC_MMR6
6541 { 1029, 2, 0, 4, 426, 0, 1, 359, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #1029 = BLTZC64
6542 { 1028, 2, 0, 4, 1030, 0, 1, 357, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #1028 = BLTZC
6543 { 1027, 2, 0, 4, 1055, 0, 1, 357, MipsImpOpBase + 3, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #1027 = BLTZAL_MM
6544 { 1026, 2, 0, 4, 1054, 0, 1, 357, MipsImpOpBase + 3, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1026 = BLTZALS_MM
6545 { 1025, 2, 0, 4, 684, 0, 1, 357, MipsImpOpBase + 3, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #1025 = BLTZALL
6546 { 1024, 2, 0, 4, 1097, 0, 1, 357, MipsImpOpBase + 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1024 = BLTZALC_MMR6
6547 { 1023, 2, 0, 4, 1027, 0, 1, 357, MipsImpOpBase + 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #1023 = BLTZALC
6548 { 1022, 2, 0, 4, 1022, 0, 1, 357, MipsImpOpBase + 3, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #1022 = BLTZAL
6549 { 1021, 2, 0, 4, 417, 0, 1, 359, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #1021 = BLTZ64
6550 { 1020, 2, 0, 4, 683, 0, 1, 357, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #1020 = BLTZ
6551 { 1019, 3, 0, 4, 1082, 0, 1, 194, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1019 = BLTUC_MMR6
6552 { 1018, 3, 0, 4, 425, 0, 1, 351, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #1018 = BLTUC64
6553 { 1017, 3, 0, 4, 1029, 0, 1, 194, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #1017 = BLTUC
6554 { 1016, 3, 0, 4, 1082, 0, 1, 194, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1016 = BLTC_MMR6
6555 { 1015, 3, 0, 4, 425, 0, 1, 351, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #1015 = BLTC64
6556 { 1014, 3, 0, 4, 1029, 0, 1, 194, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #1014 = BLTC
6557 { 1013, 2, 0, 4, 1046, 0, 1, 357, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #1013 = BLEZ_MM
6558 { 1012, 2, 0, 4, 685, 0, 1, 357, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #1012 = BLEZL
6559 { 1011, 2, 0, 4, 1084, 0, 1, 357, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1011 = BLEZC_MMR6
6560 { 1010, 2, 0, 4, 426, 0, 1, 359, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #1010 = BLEZC64
6561 { 1009, 2, 0, 4, 1030, 0, 1, 357, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #1009 = BLEZC
6562 { 1008, 2, 0, 4, 1097, 0, 1, 357, MipsImpOpBase + 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1008 = BLEZALC_MMR6
6563 { 1007, 2, 0, 4, 1027, 0, 1, 357, MipsImpOpBase + 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #1007 = BLEZALC
6564 { 1006, 2, 0, 4, 417, 0, 1, 359, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #1006 = BLEZ64
6565 { 1005, 2, 0, 4, 683, 0, 1, 357, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #1005 = BLEZ
6566 { 1004, 2, 1, 4, 943, 0, 0, 152, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1004 = BITSWAP_MMR6
6567 { 1003, 2, 1, 4, 457, 0, 0, 152, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1003 = BITSWAP
6568 { 1002, 2, 1, 4, 1549, 0, 0, 152, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1002 = BITREV_MM
6569 { 1001, 2, 1, 4, 1398, 0, 0, 152, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1001 = BITREV
6570 { 1000, 4, 1, 4, 772, 0, 0, 202, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #1000 = BINSR_W
6571 { 999, 4, 1, 4, 772, 0, 0, 206, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #999 = BINSR_H
6572 { 998, 4, 1, 4, 772, 0, 0, 198, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #998 = BINSR_D
6573 { 997, 4, 1, 4, 772, 0, 0, 618, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #997 = BINSR_B
6574 { 996, 4, 1, 4, 772, 0, 0, 614, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #996 = BINSRI_W
6575 { 995, 4, 1, 4, 772, 0, 0, 610, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #995 = BINSRI_H
6576 { 994, 4, 1, 4, 772, 0, 0, 606, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #994 = BINSRI_D
6577 { 993, 4, 1, 4, 772, 0, 0, 602, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #993 = BINSRI_B
6578 { 992, 4, 1, 4, 771, 0, 0, 202, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #992 = BINSL_W
6579 { 991, 4, 1, 4, 771, 0, 0, 206, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #991 = BINSL_H
6580 { 990, 4, 1, 4, 771, 0, 0, 198, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #990 = BINSL_D
6581 { 989, 4, 1, 4, 771, 0, 0, 618, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #989 = BINSL_B
6582 { 988, 4, 1, 4, 771, 0, 0, 614, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #988 = BINSLI_W
6583 { 987, 4, 1, 4, 771, 0, 0, 610, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #987 = BINSLI_H
6584 { 986, 4, 1, 4, 771, 0, 0, 606, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #986 = BINSLI_D
6585 { 985, 4, 1, 4, 771, 0, 0, 602, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #985 = BINSLI_B
6586 { 984, 2, 0, 4, 1046, 0, 1, 357, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #984 = BGTZ_MM
6587 { 983, 2, 0, 4, 685, 0, 1, 357, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #983 = BGTZL
6588 { 982, 2, 0, 4, 1084, 0, 1, 357, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #982 = BGTZC_MMR6
6589 { 981, 2, 0, 4, 426, 0, 1, 359, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #981 = BGTZC64
6590 { 980, 2, 0, 4, 1030, 0, 1, 357, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #980 = BGTZC
6591 { 979, 2, 0, 4, 1097, 0, 1, 357, MipsImpOpBase + 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #979 = BGTZALC_MMR6
6592 { 978, 2, 0, 4, 1027, 0, 1, 357, MipsImpOpBase + 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #978 = BGTZALC
6593 { 977, 2, 0, 4, 417, 0, 1, 359, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #977 = BGTZ64
6594 { 976, 2, 0, 4, 683, 0, 1, 357, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #976 = BGTZ
6595 { 975, 2, 0, 4, 1046, 0, 1, 357, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #975 = BGEZ_MM
6596 { 974, 2, 0, 4, 685, 0, 1, 357, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #974 = BGEZL
6597 { 973, 2, 0, 4, 1084, 0, 1, 357, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #973 = BGEZC_MMR6
6598 { 972, 2, 0, 4, 426, 0, 1, 359, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #972 = BGEZC64
6599 { 971, 2, 0, 4, 1030, 0, 1, 357, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #971 = BGEZC
6600 { 970, 2, 0, 4, 1055, 0, 1, 357, MipsImpOpBase + 3, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #970 = BGEZAL_MM
6601 { 969, 2, 0, 4, 1054, 0, 1, 357, MipsImpOpBase + 3, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #969 = BGEZALS_MM
6602 { 968, 2, 0, 4, 684, 0, 1, 357, MipsImpOpBase + 3, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #968 = BGEZALL
6603 { 967, 2, 0, 4, 1097, 0, 1, 357, MipsImpOpBase + 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #967 = BGEZALC_MMR6
6604 { 966, 2, 0, 4, 1027, 0, 1, 357, MipsImpOpBase + 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #966 = BGEZALC
6605 { 965, 2, 0, 4, 1026, 0, 1, 357, MipsImpOpBase + 3, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #965 = BGEZAL
6606 { 964, 2, 0, 4, 417, 0, 1, 359, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #964 = BGEZ64
6607 { 963, 2, 0, 4, 683, 0, 1, 357, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #963 = BGEZ
6608 { 962, 3, 0, 4, 1082, 0, 1, 194, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #962 = BGEUC_MMR6
6609 { 961, 3, 0, 4, 425, 0, 1, 351, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #961 = BGEUC64
6610 { 960, 3, 0, 4, 1029, 0, 1, 194, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #960 = BGEUC
6611 { 959, 3, 0, 4, 1082, 0, 1, 194, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #959 = BGEC_MMR6
6612 { 958, 3, 0, 4, 425, 0, 1, 351, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #958 = BGEC64
6613 { 957, 3, 0, 4, 1029, 0, 1, 194, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #957 = BGEC
6614 { 956, 3, 0, 4, 1048, 0, 1, 194, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #956 = BEQ_MM
6615 { 955, 2, 0, 4, 1084, 0, 1, 357, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL }, // Inst #955 = BEQZC_MMR6
6616 { 954, 2, 0, 4, 1047, 0, 1, 357, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #954 = BEQZC_MM
6617 { 953, 2, 0, 4, 426, 0, 1, 359, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #953 = BEQZC64
6618 { 952, 2, 0, 2, 1083, 0, 1, 600, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #952 = BEQZC16_MMR6
6619 { 951, 2, 0, 4, 1030, 0, 1, 357, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #951 = BEQZC
6620 { 950, 2, 0, 4, 1097, 0, 1, 357, MipsImpOpBase + 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #950 = BEQZALC_MMR6
6621 { 949, 2, 0, 4, 1027, 0, 1, 357, MipsImpOpBase + 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #949 = BEQZALC
6622 { 948, 2, 0, 2, 1046, 0, 1, 600, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #948 = BEQZ16_MM
6623 { 947, 3, 0, 4, 682, 0, 1, 194, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #947 = BEQL
6624 { 946, 3, 0, 4, 1082, 0, 1, 194, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #946 = BEQC_MMR6
6625 { 945, 3, 0, 4, 425, 0, 1, 351, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #945 = BEQC64
6626 { 944, 3, 0, 4, 1029, 0, 1, 194, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #944 = BEQC
6627 { 943, 3, 0, 4, 416, 0, 1, 351, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #943 = BEQ64
6628 { 942, 3, 0, 4, 681, 0, 1, 194, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #942 = BEQ
6629 { 941, 1, 0, 4, 1079, 0, 0, 190, MipsImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x16ULL }, // Inst #941 = BC_MMR6
6630 { 940, 3, 1, 4, 775, 0, 0, 160, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #940 = BCLR_W
6631 { 939, 3, 1, 4, 775, 0, 0, 157, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #939 = BCLR_H
6632 { 938, 3, 1, 4, 775, 0, 0, 154, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #938 = BCLR_D
6633 { 937, 3, 1, 4, 775, 0, 0, 551, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #937 = BCLR_B
6634 { 936, 3, 1, 4, 775, 0, 0, 566, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #936 = BCLRI_W
6635 { 935, 3, 1, 4, 775, 0, 0, 563, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #935 = BCLRI_H
6636 { 934, 3, 1, 4, 775, 0, 0, 560, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #934 = BCLRI_D
6637 { 933, 3, 1, 4, 775, 0, 0, 557, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #933 = BCLRI_B
6638 { 932, 2, 0, 4, 1081, 0, 1, 598, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #932 = BC2NEZC_MMR6
6639 { 931, 2, 0, 4, 439, 0, 0, 598, MipsImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #931 = BC2NEZ
6640 { 930, 2, 0, 4, 1081, 0, 1, 598, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #930 = BC2EQZC_MMR6
6641 { 929, 2, 0, 4, 439, 0, 0, 598, MipsImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #929 = BC2EQZ
6642 { 928, 2, 0, 4, 1045, 0, 1, 596, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x45ULL }, // Inst #928 = BC1T_MM
6643 { 927, 2, 0, 4, 878, 0, 1, 596, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x45ULL }, // Inst #927 = BC1TL
6644 { 926, 2, 0, 4, 877, 0, 1, 596, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x45ULL }, // Inst #926 = BC1T
6645 { 925, 2, 0, 4, 1080, 0, 1, 594, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #925 = BC1NEZC_MMR6
6646 { 924, 2, 0, 4, 430, 0, 0, 594, MipsImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #924 = BC1NEZ
6647 { 923, 2, 0, 4, 1044, 0, 1, 596, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x45ULL }, // Inst #923 = BC1F_MM
6648 { 922, 2, 0, 4, 876, 0, 1, 596, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x45ULL }, // Inst #922 = BC1FL
6649 { 921, 2, 0, 4, 875, 0, 1, 596, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x45ULL }, // Inst #921 = BC1F
6650 { 920, 2, 0, 4, 1080, 0, 1, 594, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #920 = BC1EQZC_MMR6
6651 { 919, 2, 0, 4, 430, 0, 0, 594, MipsImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #919 = BC1EQZ
6652 { 918, 1, 0, 2, 1079, 0, 1, 190, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #918 = BC16_MMR6
6653 { 917, 1, 0, 4, 428, 0, 0, 190, MipsImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #917 = BC
6654 { 916, 3, 0, 4, 1251, 0, 1, 591, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL }, // Inst #916 = BBIT132
6655 { 915, 3, 0, 4, 1251, 0, 1, 591, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL }, // Inst #915 = BBIT1
6656 { 914, 3, 0, 4, 1251, 0, 1, 591, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL }, // Inst #914 = BBIT032
6657 { 913, 3, 0, 4, 1251, 0, 1, 591, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL }, // Inst #913 = BBIT0
6658 { 912, 4, 1, 4, 1666, 0, 0, 576, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #912 = BALIGN_MMR2
6659 { 911, 4, 1, 4, 1502, 0, 0, 576, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #911 = BALIGN
6660 { 910, 1, 0, 4, 1096, 0, 1, 190, MipsImpOpBase + 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #910 = BALC_MMR6
6661 { 909, 1, 0, 4, 429, 0, 1, 190, MipsImpOpBase + 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #909 = BALC
6662 { 908, 1, 0, 4, 680, 0, 1, 190, MipsImpOpBase + 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #908 = BAL
6663 { 907, 3, 1, 4, 1250, 0, 0, 235, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #907 = BADDu
6664 { 906, 1, 0, 2, 1042, 0, 1, 190, MipsImpOpBase + 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #906 = B16_MM
6665 { 905, 3, 1, 2, 894, 0, 0, 588, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #905 = AndRxRxRy16
6666 { 904, 3, 1, 2, 894, 0, 0, 408, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #904 = AdduRxRyRz16
6667 { 903, 1, 0, 4, 894, 1, 1, 0, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #903 = AddiuSpImmX16
6668 { 902, 1, 0, 2, 894, 1, 1, 0, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #902 = AddiuSpImm16
6669 { 901, 3, 1, 4, 894, 0, 0, 585, MipsImpOpBase + 0, 0, 0x0ULL }, // Inst #901 = AddiuRxRyOffMemX16
6670 { 900, 3, 1, 4, 894, 0, 0, 582, MipsImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #900 = AddiuRxRxImmX16
6671 { 899, 3, 1, 2, 894, 0, 0, 582, MipsImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #899 = AddiuRxRxImm16
6672 { 898, 2, 1, 4, 894, 0, 0, 580, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #898 = AddiuRxPcImmX16
6673 { 897, 2, 1, 4, 894, 0, 0, 580, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #897 = AddiuRxImmX16
6674 { 896, 3, 1, 4, 788, 0, 0, 160, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #896 = AVE_U_W
6675 { 895, 3, 1, 4, 788, 0, 0, 157, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #895 = AVE_U_H
6676 { 894, 3, 1, 4, 788, 0, 0, 154, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #894 = AVE_U_D
6677 { 893, 3, 1, 4, 788, 0, 0, 551, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #893 = AVE_U_B
6678 { 892, 3, 1, 4, 788, 0, 0, 160, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #892 = AVE_S_W
6679 { 891, 3, 1, 4, 788, 0, 0, 157, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #891 = AVE_S_H
6680 { 890, 3, 1, 4, 788, 0, 0, 154, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #890 = AVE_S_D
6681 { 889, 3, 1, 4, 788, 0, 0, 551, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #889 = AVE_S_B
6682 { 888, 3, 1, 4, 788, 0, 0, 160, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #888 = AVER_U_W
6683 { 887, 3, 1, 4, 788, 0, 0, 157, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #887 = AVER_U_H
6684 { 886, 3, 1, 4, 788, 0, 0, 154, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #886 = AVER_U_D
6685 { 885, 3, 1, 4, 788, 0, 0, 551, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #885 = AVER_U_B
6686 { 884, 3, 1, 4, 788, 0, 0, 160, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #884 = AVER_S_W
6687 { 883, 3, 1, 4, 788, 0, 0, 157, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #883 = AVER_S_H
6688 { 882, 3, 1, 4, 788, 0, 0, 154, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #882 = AVER_S_D
6689 { 881, 3, 1, 4, 788, 0, 0, 551, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #881 = AVER_S_B
6690 { 880, 3, 1, 4, 942, 0, 0, 241, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #880 = AUI_MMR6
6691 { 879, 2, 1, 4, 941, 0, 0, 371, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #879 = AUIPC_MMR6
6692 { 878, 2, 1, 4, 456, 0, 0, 371, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #878 = AUIPC
6693 { 877, 3, 1, 4, 455, 0, 0, 241, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #877 = AUI
6694 { 876, 3, 1, 4, 582, 0, 0, 160, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #876 = ASUB_U_W
6695 { 875, 3, 1, 4, 582, 0, 0, 157, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #875 = ASUB_U_H
6696 { 874, 3, 1, 4, 582, 0, 0, 154, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #874 = ASUB_U_D
6697 { 873, 3, 1, 4, 582, 0, 0, 551, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #873 = ASUB_U_B
6698 { 872, 3, 1, 4, 581, 0, 0, 160, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #872 = ASUB_S_W
6699 { 871, 3, 1, 4, 581, 0, 0, 157, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #871 = ASUB_S_H
6700 { 870, 3, 1, 4, 581, 0, 0, 154, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #870 = ASUB_S_D
6701 { 869, 3, 1, 4, 581, 0, 0, 551, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #869 = ASUB_S_B
6702 { 868, 4, 1, 4, 1665, 0, 0, 576, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #868 = APPEND_MMR2
6703 { 867, 4, 1, 4, 1501, 0, 0, 576, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #867 = APPEND
6704 { 866, 3, 1, 4, 902, 0, 0, 241, MipsImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // Inst #866 = ANDi_MM
6705 { 865, 3, 1, 4, 453, 0, 0, 232, MipsImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // Inst #865 = ANDi64
6706 { 864, 3, 1, 4, 454, 0, 0, 241, MipsImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // Inst #864 = ANDi
6707 { 863, 3, 1, 4, 791, 0, 0, 551, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #863 = AND_V
6708 { 862, 3, 1, 4, 939, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #862 = AND_MMR6
6709 { 861, 3, 1, 4, 901, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #861 = AND_MM
6710 { 860, 3, 1, 4, 940, 0, 0, 241, MipsImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // Inst #860 = ANDI_MMR6
6711 { 859, 3, 1, 4, 591, 0, 0, 557, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #859 = ANDI_B
6712 { 858, 3, 1, 2, 939, 0, 0, 539, MipsImpOpBase + 0, 0, 0x0ULL }, // Inst #858 = ANDI16_MMR6
6713 { 857, 3, 1, 2, 901, 0, 0, 539, MipsImpOpBase + 0, 0, 0x0ULL }, // Inst #857 = ANDI16_MM
6714 { 856, 3, 1, 4, 453, 0, 0, 235, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #856 = AND64
6715 { 855, 3, 1, 2, 939, 0, 0, 573, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #855 = AND16_MMR6
6716 { 854, 3, 1, 2, 901, 0, 0, 573, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #854 = AND16_MM
6717 { 853, 3, 1, 4, 673, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #853 = AND
6718 { 852, 2, 1, 4, 938, 0, 0, 371, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #852 = ALUIPC_MMR6
6719 { 851, 2, 1, 4, 452, 0, 0, 371, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #851 = ALUIPC
6720 { 850, 4, 1, 4, 937, 0, 0, 569, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #850 = ALIGN_MMR6
6721 { 849, 4, 1, 4, 451, 0, 0, 569, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #849 = ALIGN
6722 { 848, 3, 1, 4, 898, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #848 = ADDu_MM
6723 { 847, 3, 1, 4, 450, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #847 = ADDu
6724 { 846, 3, 1, 4, 897, 0, 0, 241, MipsImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // Inst #846 = ADDiu_MM
6725 { 845, 3, 1, 4, 448, 0, 0, 241, MipsImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL }, // Inst #845 = ADDiu
6726 { 844, 3, 1, 4, 900, 0, 0, 241, MipsImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #844 = ADDi_MM
6727 { 843, 3, 1, 4, 764, 0, 0, 241, MipsImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #843 = ADDi
6728 { 842, 3, 1, 4, 936, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #842 = ADD_MMR6
6729 { 841, 3, 1, 4, 899, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #841 = ADD_MM
6730 { 840, 3, 1, 4, 785, 0, 0, 160, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #840 = ADD_A_W
6731 { 839, 3, 1, 4, 785, 0, 0, 157, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #839 = ADD_A_H
6732 { 838, 3, 1, 4, 785, 0, 0, 154, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #838 = ADD_A_D
6733 { 837, 3, 1, 4, 785, 0, 0, 551, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #837 = ADD_A_B
6734 { 836, 3, 1, 4, 1548, 1, 1, 238, MipsImpOpBase + 12, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #836 = ADDWC_MM
6735 { 835, 3, 1, 4, 1397, 1, 1, 238, MipsImpOpBase + 12, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #835 = ADDWC
6736 { 834, 3, 1, 4, 787, 0, 0, 160, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #834 = ADDV_W
6737 { 833, 3, 1, 4, 787, 0, 0, 157, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #833 = ADDV_H
6738 { 832, 3, 1, 4, 787, 0, 0, 154, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #832 = ADDV_D
6739 { 831, 3, 1, 4, 787, 0, 0, 551, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #831 = ADDV_B
6740 { 830, 3, 1, 4, 787, 0, 0, 566, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #830 = ADDVI_W
6741 { 829, 3, 1, 4, 787, 0, 0, 563, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #829 = ADDVI_H
6742 { 828, 3, 1, 4, 787, 0, 0, 560, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #828 = ADDVI_D
6743 { 827, 3, 1, 4, 787, 0, 0, 557, MipsImpOpBase + 0, 0, 0x6ULL }, // Inst #827 = ADDVI_B
6744 { 826, 3, 1, 4, 1547, 0, 1, 545, MipsImpOpBase + 10, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #826 = ADDU_S_QB_MM
6745 { 825, 3, 1, 4, 1396, 0, 1, 545, MipsImpOpBase + 10, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #825 = ADDU_S_QB
6746 { 824, 3, 1, 4, 1664, 0, 1, 545, MipsImpOpBase + 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #824 = ADDU_S_PH_MMR2
6747 { 823, 3, 1, 4, 1500, 0, 1, 545, MipsImpOpBase + 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #823 = ADDU_S_PH
6748 { 822, 3, 1, 4, 1546, 0, 1, 545, MipsImpOpBase + 10, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #822 = ADDU_QB_MM
6749 { 821, 3, 1, 4, 1395, 0, 1, 545, MipsImpOpBase + 10, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #821 = ADDU_QB
6750 { 820, 3, 1, 4, 1663, 0, 1, 545, MipsImpOpBase + 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #820 = ADDU_PH_MMR2
6751 { 819, 3, 1, 4, 1499, 0, 1, 545, MipsImpOpBase + 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #819 = ADDU_PH
6752 { 818, 3, 1, 4, 935, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #818 = ADDU_MMR6
6753 { 817, 3, 1, 4, 1662, 0, 0, 545, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #817 = ADDUH_R_QB_MMR2
6754 { 816, 3, 1, 4, 1498, 0, 0, 545, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #816 = ADDUH_R_QB
6755 { 815, 3, 1, 4, 1661, 0, 0, 545, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #815 = ADDUH_QB_MMR2
6756 { 814, 3, 1, 4, 1497, 0, 0, 545, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #814 = ADDUH_QB
6757 { 813, 3, 1, 2, 935, 0, 0, 554, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #813 = ADDU16_MMR6
6758 { 812, 3, 1, 2, 898, 0, 0, 554, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #812 = ADDU16_MM
6759 { 811, 3, 1, 4, 786, 0, 0, 160, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #811 = ADDS_U_W
6760 { 810, 3, 1, 4, 786, 0, 0, 157, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #810 = ADDS_U_H
6761 { 809, 3, 1, 4, 786, 0, 0, 154, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #809 = ADDS_U_D
6762 { 808, 3, 1, 4, 786, 0, 0, 551, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #808 = ADDS_U_B
6763 { 807, 3, 1, 4, 786, 0, 0, 160, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #807 = ADDS_S_W
6764 { 806, 3, 1, 4, 786, 0, 0, 157, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #806 = ADDS_S_H
6765 { 805, 3, 1, 4, 786, 0, 0, 154, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #805 = ADDS_S_D
6766 { 804, 3, 1, 4, 786, 0, 0, 551, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #804 = ADDS_S_B
6767 { 803, 3, 1, 4, 786, 0, 0, 160, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #803 = ADDS_A_W
6768 { 802, 3, 1, 4, 786, 0, 0, 157, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #802 = ADDS_A_H
6769 { 801, 3, 1, 4, 786, 0, 0, 154, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #801 = ADDS_A_D
6770 { 800, 3, 1, 4, 786, 0, 0, 551, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #800 = ADDS_A_B
6771 { 799, 3, 1, 4, 1545, 0, 1, 238, MipsImpOpBase + 11, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #799 = ADDSC_MM
6772 { 798, 3, 1, 4, 1394, 0, 1, 238, MipsImpOpBase + 11, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #798 = ADDSC
6773 { 797, 3, 1, 4, 1263, 0, 0, 548, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #797 = ADDR_PS64
6774 { 796, 3, 1, 4, 1544, 0, 1, 238, MipsImpOpBase + 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #796 = ADDQ_S_W_MM
6775 { 795, 3, 1, 4, 1393, 0, 1, 238, MipsImpOpBase + 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #795 = ADDQ_S_W
6776 { 794, 3, 1, 4, 1543, 0, 1, 545, MipsImpOpBase + 10, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #794 = ADDQ_S_PH_MM
6777 { 793, 3, 1, 4, 1392, 0, 1, 545, MipsImpOpBase + 10, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #793 = ADDQ_S_PH
6778 { 792, 3, 1, 4, 1542, 0, 1, 545, MipsImpOpBase + 10, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #792 = ADDQ_PH_MM
6779 { 791, 3, 1, 4, 1391, 0, 1, 545, MipsImpOpBase + 10, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #791 = ADDQ_PH
6780 { 790, 3, 1, 4, 1660, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #790 = ADDQH_W_MMR2
6781 { 789, 3, 1, 4, 1496, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #789 = ADDQH_W
6782 { 788, 3, 1, 4, 1659, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #788 = ADDQH_R_W_MMR2
6783 { 787, 3, 1, 4, 1495, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #787 = ADDQH_R_W
6784 { 786, 3, 1, 4, 1658, 0, 0, 545, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #786 = ADDQH_R_PH_MMR2
6785 { 785, 3, 1, 4, 1494, 0, 0, 545, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #785 = ADDQH_R_PH
6786 { 784, 3, 1, 4, 1657, 0, 0, 545, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #784 = ADDQH_PH_MMR2
6787 { 783, 3, 1, 4, 1493, 0, 0, 545, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #783 = ADDQH_PH
6788 { 782, 3, 1, 4, 934, 0, 0, 241, MipsImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // Inst #782 = ADDIU_MMR6
6789 { 781, 1, 0, 2, 897, 0, 0, 0, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #781 = ADDIUSP_MM
6790 { 780, 3, 1, 2, 897, 0, 0, 542, MipsImpOpBase + 0, 0, 0x0ULL }, // Inst #780 = ADDIUS5_MM
6791 { 779, 3, 1, 2, 897, 0, 0, 539, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #779 = ADDIUR2_MM
6792 { 778, 2, 1, 2, 897, 0, 0, 537, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #778 = ADDIUR1SP_MM
6793 { 777, 2, 1, 4, 933, 0, 0, 371, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #777 = ADDIUPC_MMR6
6794 { 776, 2, 1, 4, 897, 0, 0, 537, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #776 = ADDIUPC_MM
6795 { 775, 2, 1, 4, 449, 0, 0, 371, MipsImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #775 = ADDIUPC
6796 { 774, 3, 1, 4, 447, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #774 = ADD
6797 { 773, 2, 1, 4, 1541, 0, 1, 152, MipsImpOpBase + 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #773 = ABSQ_S_W_MM
6798 { 772, 2, 1, 4, 1390, 0, 1, 152, MipsImpOpBase + 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #772 = ABSQ_S_W
6799 { 771, 2, 1, 4, 1656, 0, 1, 535, MipsImpOpBase + 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #771 = ABSQ_S_QB_MMR2
6800 { 770, 2, 1, 4, 1492, 0, 1, 535, MipsImpOpBase + 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #770 = ABSQ_S_QB
6801 { 769, 2, 1, 4, 1540, 0, 1, 535, MipsImpOpBase + 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #769 = ABSQ_S_PH_MM
6802 { 768, 2, 1, 4, 1389, 0, 1, 535, MipsImpOpBase + 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #768 = ABSQ_S_PH
6803 { 767, 3, 1, 4, 594, 0, 0, 160, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #767 = XOR_V_W_PSEUDO
6804 { 766, 3, 1, 4, 594, 0, 0, 157, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #766 = XOR_V_H_PSEUDO
6805 { 765, 3, 1, 4, 594, 0, 0, 154, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #765 = XOR_V_D_PSEUDO
6806 { 764, 3, 1, 4, 1, 0, 0, 319, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #764 = Usw
6807 { 763, 3, 1, 4, 1, 0, 0, 319, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #763 = Ush
6808 { 762, 3, 1, 4, 1, 0, 0, 319, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #762 = Ulw
6809 { 761, 3, 1, 4, 1, 0, 0, 319, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #761 = Ulhu
6810 { 760, 3, 1, 4, 1, 0, 0, 319, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #760 = Ulh
6811 { 759, 3, 1, 4, 1, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #759 = URemMacro
6812 { 758, 3, 1, 4, 1, 0, 0, 241, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #758 = URemIMacro
6813 { 757, 3, 1, 4, 1, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #757 = UDivMacro
6814 { 756, 3, 1, 4, 1, 0, 0, 241, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #756 = UDivIMacro
6815 { 755, 3, 1, 4, 997, 0, 0, 445, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #755 = UDIV_MM_Pseudo
6816 { 754, 0, 0, 4, 1078, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Trap)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #754 = TRAP_MM
6817 { 753, 0, 0, 4, 445, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Trap)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #753 = TRAP
6818 { 752, 1, 0, 4, 1103, 0, 1, 0, MipsImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // Inst #752 = TAILCALL_MMR6
6819 { 751, 1, 0, 4, 1061, 0, 1, 0, MipsImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // Inst #751 = TAILCALL_MM
6820 { 750, 1, 0, 4, 1102, 0, 1, 197, MipsImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // Inst #750 = TAILCALLREG_MMR6
6821 { 749, 1, 0, 4, 1060, 0, 1, 197, MipsImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // Inst #749 = TAILCALLREG_MM
6822 { 748, 1, 0, 4, 1108, 0, 1, 318, MipsImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // Inst #748 = TAILCALLREGHB64
6823 { 747, 1, 0, 4, 686, 0, 1, 197, MipsImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // Inst #747 = TAILCALLREGHB
6824 { 746, 1, 0, 4, 1108, 0, 1, 318, MipsImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // Inst #746 = TAILCALLREG64
6825 { 745, 1, 0, 4, 686, 0, 1, 197, MipsImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // Inst #745 = TAILCALLREG
6826 { 744, 1, 0, 4, 1035, 0, 1, 197, MipsImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // Inst #744 = TAILCALLR6REG
6827 { 743, 1, 0, 4, 1035, 0, 1, 197, MipsImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // Inst #743 = TAILCALLHBR6REG
6828 { 742, 1, 0, 4, 420, 0, 1, 318, MipsImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // Inst #742 = TAILCALLHB64R6REG
6829 { 741, 1, 0, 4, 420, 0, 1, 318, MipsImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // Inst #741 = TAILCALL64R6REG
6830 { 740, 1, 0, 4, 412, 0, 1, 0, MipsImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // Inst #740 = TAILCALL
6831 { 739, 3, 1, 2, 895, 0, 1, 408, MipsImpOpBase + 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #739 = SltuRxRyRz16
6832 { 738, 3, 1, 2, 895, 0, 0, 408, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #738 = SltuCCRxRy16
6833 { 737, 3, 1, 2, 895, 0, 0, 532, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #737 = SltiuCCRxImmX16
6834 { 736, 3, 1, 2, 895, 0, 0, 532, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #736 = SltiCCRxImmX16
6835 { 735, 3, 1, 2, 895, 0, 0, 408, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #735 = SltCCRxRy16
6836 { 734, 5, 1, 2, 1041, 0, 0, 522, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #734 = SelTBtneZSltu
6837 { 733, 5, 1, 2, 1041, 0, 0, 527, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #733 = SelTBtneZSltiu
6838 { 732, 5, 1, 2, 1041, 0, 0, 527, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #732 = SelTBtneZSlti
6839 { 731, 5, 1, 2, 1041, 0, 0, 522, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #731 = SelTBtneZSlt
6840 { 730, 5, 1, 2, 1041, 0, 0, 527, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #730 = SelTBtneZCmpi
6841 { 729, 5, 1, 2, 1041, 0, 0, 522, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #729 = SelTBtneZCmp
6842 { 728, 5, 1, 2, 1041, 0, 0, 522, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #728 = SelTBteqZSltu
6843 { 727, 5, 1, 2, 1041, 0, 0, 527, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #727 = SelTBteqZSltiu
6844 { 726, 5, 1, 2, 1041, 0, 0, 527, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #726 = SelTBteqZSlti
6845 { 725, 5, 1, 2, 1041, 0, 0, 522, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #725 = SelTBteqZSlt
6846 { 724, 5, 1, 2, 1041, 0, 0, 527, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #724 = SelTBteqZCmpi
6847 { 723, 5, 1, 2, 1041, 0, 0, 522, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #723 = SelTBteqZCmp
6848 { 722, 4, 1, 2, 1041, 0, 0, 518, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #722 = SelBneZ
6849 { 721, 4, 1, 2, 1041, 0, 0, 518, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #721 = SelBeqZ
6850 { 720, 3, 0, 4, 1, 0, 0, 368, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #720 = SaadAddr
6851 { 719, 3, 0, 4, 1, 0, 0, 368, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #719 = SaaAddr
6852 { 718, 2, 1, 4, 1, 0, 0, 516, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #718 = SZ_W_PSEUDO
6853 { 717, 2, 1, 4, 1, 0, 0, 510, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #717 = SZ_V_PSEUDO
6854 { 716, 2, 1, 4, 1, 0, 0, 514, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #716 = SZ_H_PSEUDO
6855 { 715, 2, 1, 4, 1, 0, 0, 512, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #715 = SZ_D_PSEUDO
6856 { 714, 2, 1, 4, 1, 0, 0, 510, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #714 = SZ_B_PSEUDO
6857 { 713, 3, 0, 4, 1209, 0, 0, 361, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #713 = SWM_MM
6858 { 712, 3, 0, 4, 884, 0, 0, 328, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #712 = ST_F16
6859 { 711, 3, 0, 4, 1, 0, 0, 325, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #711 = STR_W
6860 { 710, 3, 0, 4, 1, 0, 0, 322, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #710 = STR_D
6861 { 709, 3, 0, 4, 0, 0, 0, 340, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #709 = STORE_CCOND_DSP
6862 { 708, 3, 0, 4, 0, 0, 0, 337, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #708 = STORE_ACC64DSP
6863 { 707, 3, 0, 4, 0, 0, 0, 334, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #707 = STORE_ACC64
6864 { 706, 3, 0, 4, 0, 0, 0, 331, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #706 = STORE_ACC128
6865 { 705, 3, 1, 4, 1, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #705 = SRemMacro
6866 { 704, 3, 1, 4, 1, 0, 0, 241, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #704 = SRemIMacro
6867 { 703, 2, 1, 4, 1, 0, 0, 516, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #703 = SNZ_W_PSEUDO
6868 { 702, 2, 1, 4, 1, 0, 0, 510, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #702 = SNZ_V_PSEUDO
6869 { 701, 2, 1, 4, 1, 0, 0, 514, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #701 = SNZ_H_PSEUDO
6870 { 700, 2, 1, 4, 1, 0, 0, 512, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #700 = SNZ_D_PSEUDO
6871 { 699, 2, 1, 4, 1, 0, 0, 510, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #699 = SNZ_B_PSEUDO
6872 { 698, 3, 1, 4, 1, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #698 = SNEMacro
6873 { 697, 3, 1, 4, 1, 0, 0, 241, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #697 = SNEIMacro
6874 { 696, 3, 1, 4, 1, 0, 0, 232, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #696 = SLTUImm64
6875 { 695, 3, 1, 4, 1, 0, 0, 232, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #695 = SLTImm64
6876 { 694, 3, 1, 4, 1, 0, 0, 232, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #694 = SLEUImm64
6877 { 693, 3, 1, 4, 1, 0, 0, 241, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #693 = SLEUImm
6878 { 692, 3, 1, 4, 1, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #692 = SLEU
6879 { 691, 3, 1, 4, 1, 0, 0, 232, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #691 = SLEImm64
6880 { 690, 3, 1, 4, 1, 0, 0, 241, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #690 = SLEImm
6881 { 689, 3, 1, 4, 1, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #689 = SLE
6882 { 688, 3, 1, 4, 1, 0, 0, 232, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #688 = SGTUImm64
6883 { 687, 3, 1, 4, 1, 0, 0, 241, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #687 = SGTUImm
6884 { 686, 3, 1, 4, 1, 0, 0, 232, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #686 = SGTImm64
6885 { 685, 3, 1, 4, 1, 0, 0, 241, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #685 = SGTImm
6886 { 684, 3, 1, 4, 1, 0, 0, 232, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #684 = SGEUImm64
6887 { 683, 3, 1, 4, 1, 0, 0, 241, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #683 = SGEUImm
6888 { 682, 3, 1, 4, 1, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #682 = SGEU
6889 { 681, 3, 1, 4, 1, 0, 0, 232, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #681 = SGEImm64
6890 { 680, 3, 1, 4, 1, 0, 0, 241, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #680 = SGEImm
6891 { 679, 3, 1, 4, 1, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #679 = SGE
6892 { 678, 3, 1, 4, 1, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #678 = SEQMacro
6893 { 677, 3, 1, 4, 1, 0, 0, 241, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #677 = SEQIMacro
6894 { 676, 3, 1, 4, 1, 0, 0, 507, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #676 = SDivMacro
6895 { 675, 3, 1, 4, 1, 0, 0, 241, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #675 = SDivIMacro
6896 { 674, 3, 1, 4, 1, 0, 0, 319, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #674 = SDMacro
6897 { 673, 3, 1, 4, 996, 0, 0, 445, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #673 = SDIV_MM_Pseudo
6898 { 672, 3, 1, 4, 1, 0, 0, 504, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #672 = SDC1_M1
6899 { 671, 0, 0, 2, 1037, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x0ULL }, // Inst #671 = RetRA16
6900 { 670, 0, 0, 4, 438, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // Inst #670 = RetRA
6901 { 669, 3, 0, 4, 1, 0, 0, 241, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #669 = RORImm
6902 { 668, 3, 0, 4, 1, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #668 = ROR
6903 { 667, 3, 0, 4, 1, 0, 0, 241, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #667 = ROLImm
6904 { 666, 3, 0, 4, 1, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #666 = ROL
6905 { 665, 3, 1, 4, 753, 0, 0, 445, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #665 = PseudoUDIV
6906 { 664, 3, 1, 4, 646, 0, 0, 501, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #664 = PseudoTRUNC_W_S
6907 { 663, 3, 1, 4, 646, 0, 0, 498, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #663 = PseudoTRUNC_W_D32
6908 { 662, 3, 1, 4, 646, 0, 0, 495, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #662 = PseudoTRUNC_W_D
6909 { 661, 4, 1, 4, 1, 0, 0, 491, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #661 = PseudoSELECT_S
6910 { 660, 4, 1, 4, 1, 0, 0, 487, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #660 = PseudoSELECT_I64
6911 { 659, 4, 1, 4, 1, 0, 0, 483, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #659 = PseudoSELECT_I
6912 { 658, 4, 1, 4, 1, 0, 0, 479, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #658 = PseudoSELECT_D64
6913 { 657, 4, 1, 4, 1, 0, 0, 475, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #657 = PseudoSELECT_D32
6914 { 656, 4, 1, 4, 1, 0, 0, 471, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #656 = PseudoSELECTFP_T_S
6915 { 655, 4, 1, 4, 1, 0, 0, 467, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #655 = PseudoSELECTFP_T_I64
6916 { 654, 4, 1, 4, 1, 0, 0, 463, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #654 = PseudoSELECTFP_T_I
6917 { 653, 4, 1, 4, 1, 0, 0, 459, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #653 = PseudoSELECTFP_T_D64
6918 { 652, 4, 1, 4, 1, 0, 0, 455, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #652 = PseudoSELECTFP_T_D32
6919 { 651, 4, 1, 4, 1, 0, 0, 471, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #651 = PseudoSELECTFP_F_S
6920 { 650, 4, 1, 4, 1, 0, 0, 467, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #650 = PseudoSELECTFP_F_I64
6921 { 649, 4, 1, 4, 1, 0, 0, 463, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #649 = PseudoSELECTFP_F_I
6922 { 648, 4, 1, 4, 1, 0, 0, 459, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #648 = PseudoSELECTFP_F_D64
6923 { 647, 4, 1, 4, 1, 0, 0, 455, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #647 = PseudoSELECTFP_F_D32
6924 { 646, 3, 1, 4, 752, 0, 0, 445, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #646 = PseudoSDIV
6925 { 645, 1, 0, 4, 437, 0, 0, 318, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // Inst #645 = PseudoReturn64
6926 { 644, 1, 0, 4, 689, 0, 0, 197, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // Inst #644 = PseudoReturn
6927 { 643, 4, 1, 4, 1491, 0, 0, 451, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #643 = PseudoPICK_QB
6928 { 642, 4, 1, 4, 1491, 0, 0, 451, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #642 = PseudoPICK_PH
6929 { 641, 3, 1, 4, 981, 0, 0, 445, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #641 = PseudoMULTu_MM
6930 { 640, 3, 1, 4, 983, 0, 0, 445, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #640 = PseudoMULTu
6931 { 639, 3, 1, 4, 980, 0, 0, 445, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #639 = PseudoMULT_MM
6932 { 638, 3, 1, 4, 982, 0, 0, 445, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #638 = PseudoMULT
6933 { 637, 3, 1, 4, 985, 0, 0, 445, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #637 = PseudoMTLOHI_MM
6934 { 636, 3, 1, 4, 1376, 0, 0, 448, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #636 = PseudoMTLOHI_DSP
6935 { 635, 3, 1, 4, 1018, 0, 0, 420, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #635 = PseudoMTLOHI64
6936 { 634, 3, 1, 4, 761, 0, 0, 445, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #634 = PseudoMTLOHI
6937 { 633, 4, 1, 4, 978, 0, 0, 437, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #633 = PseudoMSUB_MM
6938 { 632, 4, 1, 4, 979, 0, 0, 437, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #632 = PseudoMSUBU_MM
6939 { 631, 4, 1, 4, 760, 0, 0, 437, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #631 = PseudoMSUBU
6940 { 630, 4, 1, 4, 759, 0, 0, 437, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #630 = PseudoMSUB
6941 { 629, 2, 1, 4, 984, 0, 0, 441, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #629 = PseudoMFLO_MM
6942 { 628, 2, 1, 4, 1017, 0, 0, 443, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #628 = PseudoMFLO64
6943 { 627, 2, 1, 4, 748, 0, 0, 441, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #627 = PseudoMFLO
6944 { 626, 2, 1, 4, 984, 0, 0, 441, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #626 = PseudoMFHI_MM
6945 { 625, 2, 1, 4, 1017, 0, 0, 443, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #625 = PseudoMFHI64
6946 { 624, 2, 1, 4, 748, 0, 0, 441, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #624 = PseudoMFHI
6947 { 623, 4, 1, 4, 976, 0, 0, 437, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #623 = PseudoMADD_MM
6948 { 622, 4, 1, 4, 977, 0, 0, 437, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #622 = PseudoMADDU_MM
6949 { 621, 4, 1, 4, 758, 0, 0, 437, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #621 = PseudoMADDU
6950 { 620, 4, 1, 4, 757, 0, 0, 437, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #620 = PseudoMADD
6951 { 619, 1, 0, 4, 1034, 0, 0, 197, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // Inst #619 = PseudoIndrectHazardBranchR6
6952 { 618, 1, 0, 4, 427, 0, 0, 318, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // Inst #618 = PseudoIndrectHazardBranch64R6
6953 { 617, 1, 0, 4, 1109, 0, 0, 318, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // Inst #617 = PseudoIndirectHazardBranch64
6954 { 616, 1, 0, 4, 688, 0, 0, 197, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // Inst #616 = PseudoIndirectHazardBranch
6955 { 615, 1, 0, 4, 1095, 0, 0, 197, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // Inst #615 = PseudoIndirectBranch_MMR6
6956 { 614, 1, 0, 4, 1062, 0, 0, 197, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // Inst #614 = PseudoIndirectBranch_MM
6957 { 613, 1, 0, 4, 1034, 0, 0, 197, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // Inst #613 = PseudoIndirectBranchR6
6958 { 612, 1, 0, 4, 427, 0, 0, 318, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // Inst #612 = PseudoIndirectBranch64R6
6959 { 611, 1, 0, 4, 1109, 0, 0, 318, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // Inst #611 = PseudoIndirectBranch64
6960 { 610, 1, 0, 4, 688, 0, 0, 197, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // Inst #610 = PseudoIndirectBranch
6961 { 609, 7, 2, 4, 1, 0, 0, 430, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #609 = PseudoD_SELECT_I64
6962 { 608, 7, 2, 4, 1, 0, 0, 423, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #608 = PseudoD_SELECT_I
6963 { 607, 3, 1, 4, 1016, 0, 0, 420, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #607 = PseudoDUDIV
6964 { 606, 3, 1, 4, 1015, 0, 0, 420, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #606 = PseudoDSDIV
6965 { 605, 3, 1, 4, 1014, 0, 0, 420, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #605 = PseudoDMULTu
6966 { 604, 3, 1, 4, 1013, 0, 0, 420, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #604 = PseudoDMULT
6967 { 603, 2, 1, 4, 661, 0, 0, 404, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x4ULL }, // Inst #603 = PseudoCVT_S_W
6968 { 602, 2, 1, 4, 661, 0, 0, 416, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x4ULL }, // Inst #602 = PseudoCVT_S_L
6969 { 601, 2, 1, 4, 661, 0, 0, 418, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x4ULL }, // Inst #601 = PseudoCVT_D64_W
6970 { 600, 2, 1, 4, 661, 0, 0, 416, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x4ULL }, // Inst #600 = PseudoCVT_D64_L
6971 { 599, 2, 1, 4, 661, 0, 0, 414, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x4ULL }, // Inst #599 = PseudoCVT_D32_W
6972 { 598, 3, 1, 4, 1490, 0, 0, 411, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #598 = PseudoCMP_LT_PH
6973 { 597, 3, 1, 4, 1490, 0, 0, 411, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #597 = PseudoCMP_LE_PH
6974 { 596, 3, 1, 4, 1490, 0, 0, 411, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #596 = PseudoCMP_EQ_PH
6975 { 595, 3, 1, 4, 1490, 0, 0, 411, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #595 = PseudoCMPU_LT_QB
6976 { 594, 3, 1, 4, 1490, 0, 0, 411, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #594 = PseudoCMPU_LE_QB
6977 { 593, 3, 1, 4, 1490, 0, 0, 411, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #593 = PseudoCMPU_EQ_QB
6978 { 592, 3, 1, 4, 593, 0, 0, 160, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #592 = OR_V_W_PSEUDO
6979 { 591, 3, 1, 4, 593, 0, 0, 157, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #591 = OR_V_H_PSEUDO
6980 { 590, 3, 1, 4, 593, 0, 0, 154, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #590 = OR_V_D_PSEUDO
6981 { 589, 3, 1, 4, 592, 0, 0, 160, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #589 = NOR_V_W_PSEUDO
6982 { 588, 3, 1, 4, 592, 0, 0, 157, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #588 = NOR_V_H_PSEUDO
6983 { 587, 3, 1, 4, 592, 0, 0, 154, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #587 = NOR_V_D_PSEUDO
6984 { 586, 3, 1, 4, 1, 0, 0, 232, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #586 = NORImm64
6985 { 585, 3, 1, 4, 1, 0, 0, 241, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #585 = NORImm
6986 { 584, 0, 0, 4, 679, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #584 = NOP
6987 { 583, 3, 1, 2, 986, 0, 2, 408, MipsImpOpBase + 7, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #583 = MultuRxRyRz16
6988 { 582, 2, 0, 2, 986, 0, 2, 406, MipsImpOpBase + 7, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #582 = MultuRxRy16
6989 { 581, 3, 1, 2, 986, 0, 2, 408, MipsImpOpBase + 7, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #581 = MultRxRyRz16
6990 { 580, 2, 0, 2, 986, 0, 2, 406, MipsImpOpBase + 7, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #580 = MultRxRy16
6991 { 579, 3, 0, 4, 1, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #579 = MULOUMacro
6992 { 578, 3, 0, 4, 1, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #578 = MULOMacro
6993 { 577, 3, 0, 4, 1, 0, 0, 241, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #577 = MULImmMacro
6994 { 576, 2, 1, 4, 1, 0, 0, 399, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #576 = MTTLO
6995 { 575, 2, 1, 4, 1, 0, 0, 399, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #575 = MTTHI
6996 { 574, 2, 1, 4, 1, 0, 0, 404, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #574 = MTTHC1
6997 { 573, 2, 1, 4, 1, 0, 0, 152, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #573 = MTTGPR
6998 { 572, 1, 0, 4, 1, 0, 0, 197, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #572 = MTTDSP
6999 { 571, 2, 1, 4, 1, 0, 0, 404, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #571 = MTTC1
7000 { 570, 3, 1, 4, 1, 0, 0, 401, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #570 = MTTC0
7001 { 569, 2, 1, 4, 1, 0, 0, 399, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #569 = MTTACX
7002 { 568, 2, 1, 4, 1, 0, 0, 397, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #568 = MSA_FP_ROUND_W_PSEUDO
7003 { 567, 2, 1, 4, 1, 0, 0, 395, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #567 = MSA_FP_ROUND_D_PSEUDO
7004 { 566, 2, 1, 4, 1, 0, 0, 393, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #566 = MSA_FP_EXTEND_W_PSEUDO
7005 { 565, 2, 1, 4, 1, 0, 0, 391, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #565 = MSA_FP_EXTEND_D_PSEUDO
7006 { 564, 2, 0, 4, 1, 2, 0, 389, MipsImpOpBase + 5, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x10ULL }, // Inst #564 = MIPSeh_return64
7007 { 563, 2, 0, 4, 1, 2, 0, 152, MipsImpOpBase + 5, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x10ULL }, // Inst #563 = MIPSeh_return32
7008 { 562, 2, 1, 4, 1, 0, 0, 382, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #562 = MFTLO
7009 { 561, 2, 1, 4, 1, 0, 0, 382, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #561 = MFTHI
7010 { 560, 2, 1, 4, 1, 0, 0, 387, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #560 = MFTHC1
7011 { 559, 3, 1, 4, 1, 0, 0, 241, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #559 = MFTGPR
7012 { 558, 1, 1, 4, 1, 0, 0, 197, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #558 = MFTDSP
7013 { 557, 2, 1, 4, 1, 0, 0, 387, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #557 = MFTC1
7014 { 556, 3, 1, 4, 1, 0, 0, 384, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #556 = MFTC0
7015 { 555, 2, 1, 4, 1, 0, 0, 382, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #555 = MFTACX
7016 { 554, 3, 1, 2, 896, 0, 0, 379, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #554 = LwConstant32
7017 { 553, 2, 1, 4, 1, 0, 0, 371, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #553 = LoadImmSingleGPR
7018 { 552, 2, 1, 4, 1, 0, 0, 377, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #552 = LoadImmSingleFGR
7019 { 551, 2, 1, 4, 1, 0, 0, 371, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #551 = LoadImmDoubleGPR
7020 { 550, 2, 1, 4, 1, 0, 0, 375, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #550 = LoadImmDoubleFGR_32
7021 { 549, 2, 1, 4, 1, 0, 0, 373, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #549 = LoadImmDoubleFGR
7022 { 548, 2, 1, 4, 1, 0, 0, 366, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #548 = LoadImm64
7023 { 547, 2, 1, 4, 1, 0, 0, 371, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #547 = LoadImm32
7024 { 546, 3, 1, 4, 1, 0, 0, 368, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #546 = LoadAddrReg64
7025 { 545, 3, 1, 4, 1, 0, 0, 319, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #545 = LoadAddrReg32
7026 { 544, 2, 1, 4, 1, 0, 0, 366, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #544 = LoadAddrImm64
7027 { 543, 2, 1, 4, 1, 0, 0, 364, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #543 = LoadAddrImm32
7028 { 542, 3, 1, 4, 1, 0, 0, 361, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #542 = LWM_MM
7029 { 541, 2, 1, 4, 503, 0, 0, 359, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #541 = LONG_BRANCH_LUi2Op_64
7030 { 540, 2, 1, 4, 1, 0, 0, 357, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #540 = LONG_BRANCH_LUi2Op
7031 { 539, 3, 1, 4, 1, 0, 0, 354, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #539 = LONG_BRANCH_LUi
7032 { 538, 3, 1, 4, 503, 0, 0, 351, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #538 = LONG_BRANCH_DADDiu2Op
7033 { 537, 4, 1, 4, 503, 0, 0, 347, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #537 = LONG_BRANCH_DADDiu
7034 { 536, 3, 1, 4, 1, 0, 0, 194, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #536 = LONG_BRANCH_ADDiu2Op
7035 { 535, 4, 1, 4, 1, 0, 0, 343, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #535 = LONG_BRANCH_ADDiu
7036 { 534, 3, 1, 4, 0, 0, 0, 340, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #534 = LOAD_CCOND_DSP
7037 { 533, 3, 1, 4, 0, 0, 0, 337, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #533 = LOAD_ACC64DSP
7038 { 532, 3, 1, 4, 0, 0, 0, 334, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #532 = LOAD_ACC64
7039 { 531, 3, 1, 4, 0, 0, 0, 331, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #531 = LOAD_ACC128
7040 { 530, 3, 1, 4, 392, 0, 0, 328, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #530 = LD_F16
7041 { 529, 3, 1, 4, 1, 0, 0, 325, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #529 = LDR_W
7042 { 528, 3, 1, 4, 1, 0, 0, 322, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #528 = LDR_D
7043 { 527, 3, 1, 4, 1, 0, 0, 319, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #527 = LDMacro
7044 { 526, 2, 1, 4, 1, 0, 0, 152, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #526 = JalTwoReg
7045 { 525, 1, 0, 4, 1, 0, 0, 197, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #525 = JalOneReg
7046 { 524, 1, 0, 4, 1087, 0, 1, 0, MipsImpOpBase + 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x10ULL }, // Inst #524 = JAL_MMR6
7047 { 523, 1, 0, 4, 697, 0, 1, 197, MipsImpOpBase + 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x10ULL }, // Inst #523 = JALRPseudo
7048 { 522, 1, 0, 4, 697, 0, 1, 197, MipsImpOpBase + 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x10ULL }, // Inst #522 = JALRHBPseudo
7049 { 521, 1, 0, 4, 414, 0, 1, 318, MipsImpOpBase + 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x10ULL }, // Inst #521 = JALRHB64Pseudo
7050 { 520, 1, 0, 4, 414, 0, 1, 318, MipsImpOpBase + 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x10ULL }, // Inst #520 = JALR64Pseudo
7051 { 519, 4, 1, 4, 1, 0, 0, 314, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #519 = INSERT_W_VIDX_PSEUDO
7052 { 518, 4, 1, 4, 1, 0, 0, 310, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #518 = INSERT_W_VIDX64_PSEUDO
7053 { 517, 4, 1, 4, 1, 0, 0, 306, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #517 = INSERT_H_VIDX_PSEUDO
7054 { 516, 4, 1, 4, 1, 0, 0, 302, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #516 = INSERT_H_VIDX64_PSEUDO
7055 { 515, 4, 1, 4, 1, 0, 0, 298, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #515 = INSERT_FW_VIDX_PSEUDO
7056 { 514, 4, 1, 4, 1, 0, 0, 294, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #514 = INSERT_FW_VIDX64_PSEUDO
7057 { 513, 4, 1, 4, 604, 0, 0, 290, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #513 = INSERT_FW_PSEUDO
7058 { 512, 4, 1, 4, 1, 0, 0, 286, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #512 = INSERT_FD_VIDX_PSEUDO
7059 { 511, 4, 1, 4, 1, 0, 0, 282, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #511 = INSERT_FD_VIDX64_PSEUDO
7060 { 510, 4, 1, 4, 604, 0, 0, 278, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #510 = INSERT_FD_PSEUDO
7061 { 509, 4, 1, 4, 1, 0, 0, 274, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #509 = INSERT_D_VIDX_PSEUDO
7062 { 508, 4, 1, 4, 1, 0, 0, 270, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #508 = INSERT_D_VIDX64_PSEUDO
7063 { 507, 4, 1, 4, 1, 0, 0, 266, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #507 = INSERT_B_VIDX_PSEUDO
7064 { 506, 4, 1, 4, 1, 0, 0, 262, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #506 = INSERT_B_VIDX64_PSEUDO
7065 { 505, 4, 2, 2, 896, 0, 0, 258, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #505 = GotPrologue16
7066 { 504, 2, 1, 4, 603, 0, 0, 256, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #504 = FILL_FW_PSEUDO
7067 { 503, 2, 1, 4, 603, 0, 0, 254, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #503 = FILL_FD_PSEUDO
7068 { 502, 2, 1, 4, 1, 0, 0, 252, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #502 = FEXP2_W_1_PSEUDO
7069 { 501, 2, 1, 4, 1, 0, 0, 250, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #501 = FEXP2_D_1_PSEUDO
7070 { 500, 2, 1, 4, 812, 0, 0, 252, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #500 = FABS_W
7071 { 499, 2, 1, 4, 812, 0, 0, 250, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #499 = FABS_D
7072 { 498, 3, 1, 4, 495, 0, 0, 247, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #498 = ExtractElementF64_64
7073 { 497, 3, 1, 4, 495, 0, 0, 244, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #497 = ExtractElementF64
7074 { 496, 0, 0, 4, 1025, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #496 = ERet
7075 { 495, 3, 1, 4, 1, 0, 0, 235, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #495 = DURemMacro
7076 { 494, 3, 1, 4, 1, 0, 0, 232, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #494 = DURemIMacro
7077 { 493, 3, 1, 4, 1, 0, 0, 235, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #493 = DUDivMacro
7078 { 492, 3, 1, 4, 1, 0, 0, 232, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #492 = DUDivIMacro
7079 { 491, 3, 1, 4, 1, 0, 0, 235, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #491 = DSRemMacro
7080 { 490, 3, 1, 4, 1, 0, 0, 232, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #490 = DSRemIMacro
7081 { 489, 3, 1, 4, 1, 0, 0, 235, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #489 = DSDivMacro
7082 { 488, 3, 1, 4, 1, 0, 0, 232, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #488 = DSDivIMacro
7083 { 487, 3, 0, 4, 1, 0, 0, 241, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #487 = DRORImm
7084 { 486, 3, 0, 4, 1, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #486 = DROR
7085 { 485, 3, 0, 4, 1, 0, 0, 241, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #485 = DROLImm
7086 { 484, 3, 0, 4, 1, 0, 0, 238, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #484 = DROL
7087 { 483, 3, 0, 4, 1, 0, 0, 235, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #483 = DMULOUMacro
7088 { 482, 3, 0, 4, 1, 0, 0, 235, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #482 = DMULOMacro
7089 { 481, 3, 0, 4, 1, 0, 0, 235, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #481 = DMULMacro
7090 { 480, 3, 0, 4, 1, 0, 0, 232, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #480 = DMULImmMacro
7091 { 479, 1, 0, 2, 896, 0, 0, 0, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #479 = Constant32
7092 { 478, 2, 1, 4, 1, 0, 0, 230, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #478 = CTTC1
7093 { 477, 3, 1, 4, 1, 0, 0, 227, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #477 = COPY_FW_PSEUDO
7094 { 476, 3, 1, 4, 1, 0, 0, 224, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #476 = COPY_FD_PSEUDO
7095 { 475, 3, 0, 2, 896, 0, 0, 2, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #475 = CONSTPOOL_ENTRY
7096 { 474, 2, 1, 4, 1, 0, 0, 222, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #474 = CFTC1
7097 { 473, 3, 1, 4, 501, 0, 0, 219, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #473 = BuildPairF64_64
7098 { 472, 3, 1, 4, 501, 0, 0, 216, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #472 = BuildPairF64
7099 { 471, 3, 0, 2, 1037, 0, 0, 210, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #471 = BtnezT8SltuX16
7100 { 470, 3, 0, 2, 1037, 0, 0, 213, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #470 = BtnezT8SltiuX16
7101 { 469, 3, 0, 2, 1037, 0, 0, 213, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #469 = BtnezT8SltiX16
7102 { 468, 3, 0, 2, 1037, 0, 0, 210, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #468 = BtnezT8SltX16
7103 { 467, 3, 0, 2, 1037, 0, 0, 213, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #467 = BtnezT8CmpiX16
7104 { 466, 3, 0, 2, 1037, 0, 0, 210, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #466 = BtnezT8CmpX16
7105 { 465, 3, 0, 2, 1037, 0, 0, 210, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #465 = BteqzT8SltuX16
7106 { 464, 3, 0, 2, 1037, 0, 0, 213, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #464 = BteqzT8SltiuX16
7107 { 463, 3, 0, 2, 1037, 0, 0, 213, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #463 = BteqzT8SltiX16
7108 { 462, 3, 0, 2, 1037, 0, 0, 210, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #462 = BteqzT8SltX16
7109 { 461, 3, 0, 2, 1037, 0, 0, 213, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #461 = BteqzT8CmpiX16
7110 { 460, 3, 0, 2, 1037, 0, 0, 210, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #460 = BteqzT8CmpX16
7111 { 459, 3, 1, 4, 1, 0, 0, 191, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #459 = BneImm
7112 { 458, 3, 1, 4, 1, 0, 0, 191, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #458 = BeqImm
7113 { 457, 1, 0, 4, 1053, 0, 0, 190, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #457 = B_MM_Pseudo
7114 { 456, 1, 0, 4, 1094, 0, 0, 190, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #456 = B_MMR6_Pseudo
7115 { 455, 1, 0, 4, 1042, 0, 1, 190, MipsImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // Inst #455 = B_MM
7116 { 454, 4, 1, 4, 655, 0, 0, 202, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #454 = BSEL_W_PSEUDO
7117 { 453, 4, 1, 4, 655, 0, 0, 206, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #453 = BSEL_H_PSEUDO
7118 { 452, 4, 1, 4, 655, 0, 0, 202, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #452 = BSEL_FW_PSEUDO
7119 { 451, 4, 1, 4, 655, 0, 0, 198, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #451 = BSEL_FD_PSEUDO
7120 { 450, 4, 1, 4, 655, 0, 0, 198, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #450 = BSEL_D_PSEUDO
7121 { 449, 1, 1, 4, 1, 1, 0, 197, MipsImpOpBase + 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #449 = BPOSGE32_PSEUDO
7122 { 448, 3, 0, 4, 1, 0, 0, 191, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #448 = BNELImmMacro
7123 { 447, 3, 0, 4, 1, 0, 0, 191, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #447 = BLTULImmMacro
7124 { 446, 3, 0, 4, 1, 0, 0, 194, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #446 = BLTUL
7125 { 445, 3, 0, 4, 1, 0, 0, 191, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #445 = BLTUImmMacro
7126 { 444, 3, 0, 4, 1, 0, 0, 194, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #444 = BLTU
7127 { 443, 3, 0, 4, 1, 0, 0, 191, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #443 = BLTLImmMacro
7128 { 442, 3, 0, 4, 1, 0, 0, 194, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #442 = BLTL
7129 { 441, 3, 0, 4, 1, 0, 0, 191, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #441 = BLTImmMacro
7130 { 440, 3, 0, 4, 1, 0, 0, 194, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #440 = BLT
7131 { 439, 3, 0, 4, 1, 0, 0, 191, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #439 = BLEULImmMacro
7132 { 438, 3, 0, 4, 1, 0, 0, 194, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #438 = BLEUL
7133 { 437, 3, 0, 4, 1, 0, 0, 191, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #437 = BLEUImmMacro
7134 { 436, 3, 0, 4, 1, 0, 0, 194, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #436 = BLEU
7135 { 435, 3, 0, 4, 1, 0, 0, 191, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #435 = BLELImmMacro
7136 { 434, 3, 0, 4, 1, 0, 0, 194, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #434 = BLEL
7137 { 433, 3, 0, 4, 1, 0, 0, 191, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #433 = BLEImmMacro
7138 { 432, 3, 0, 4, 1, 0, 0, 194, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #432 = BLE
7139 { 431, 3, 0, 4, 1, 0, 0, 191, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #431 = BGTULImmMacro
7140 { 430, 3, 0, 4, 1, 0, 0, 194, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #430 = BGTUL
7141 { 429, 3, 0, 4, 1, 0, 0, 191, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #429 = BGTUImmMacro
7142 { 428, 3, 0, 4, 1, 0, 0, 194, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #428 = BGTU
7143 { 427, 3, 0, 4, 1, 0, 0, 191, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #427 = BGTLImmMacro
7144 { 426, 3, 0, 4, 1, 0, 0, 194, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #426 = BGTL
7145 { 425, 3, 0, 4, 1, 0, 0, 191, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #425 = BGTImmMacro
7146 { 424, 3, 0, 4, 1, 0, 0, 194, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #424 = BGT
7147 { 423, 3, 0, 4, 1, 0, 0, 191, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #423 = BGEULImmMacro
7148 { 422, 3, 0, 4, 1, 0, 0, 194, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #422 = BGEUL
7149 { 421, 3, 0, 4, 1, 0, 0, 191, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #421 = BGEUImmMacro
7150 { 420, 3, 0, 4, 1, 0, 0, 194, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #420 = BGEU
7151 { 419, 3, 0, 4, 1, 0, 0, 191, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #419 = BGELImmMacro
7152 { 418, 3, 0, 4, 1, 0, 0, 194, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #418 = BGEL
7153 { 417, 3, 0, 4, 1, 0, 0, 191, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #417 = BGEImmMacro
7154 { 416, 3, 0, 4, 1, 0, 0, 194, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #416 = BGE
7155 { 415, 3, 0, 4, 1, 0, 0, 191, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #415 = BEQLImmMacro
7156 { 414, 1, 0, 4, 1043, 0, 1, 190, MipsImpOpBase + 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #414 = BAL_BR_MM
7157 { 413, 1, 0, 4, 434, 0, 1, 190, MipsImpOpBase + 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #413 = BAL_BR
7158 { 412, 1, 0, 4, 415, 0, 1, 190, MipsImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // Inst #412 = B
7159 { 411, 6, 1, 4, 670, 0, 0, 181, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #411 = ATOMIC_SWAP_I8_POSTRA
7160 { 410, 3, 1, 4, 1, 0, 0, 178, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #410 = ATOMIC_SWAP_I8
7161 { 409, 3, 1, 4, 670, 0, 0, 187, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #409 = ATOMIC_SWAP_I64_POSTRA
7162 { 408, 3, 1, 4, 1, 0, 0, 187, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #408 = ATOMIC_SWAP_I64
7163 { 407, 3, 1, 4, 670, 0, 0, 178, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #407 = ATOMIC_SWAP_I32_POSTRA
7164 { 406, 3, 1, 4, 1, 0, 0, 178, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #406 = ATOMIC_SWAP_I32
7165 { 405, 6, 1, 4, 670, 0, 0, 181, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #405 = ATOMIC_SWAP_I16_POSTRA
7166 { 404, 3, 1, 4, 1, 0, 0, 178, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #404 = ATOMIC_SWAP_I16
7167 { 403, 6, 1, 4, 672, 0, 0, 181, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #403 = ATOMIC_LOAD_XOR_I8_POSTRA
7168 { 402, 3, 1, 4, 1, 0, 0, 178, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #402 = ATOMIC_LOAD_XOR_I8
7169 { 401, 3, 1, 4, 672, 0, 0, 187, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #401 = ATOMIC_LOAD_XOR_I64_POSTRA
7170 { 400, 3, 1, 4, 1, 0, 0, 187, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #400 = ATOMIC_LOAD_XOR_I64
7171 { 399, 3, 1, 4, 672, 0, 0, 178, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #399 = ATOMIC_LOAD_XOR_I32_POSTRA
7172 { 398, 3, 1, 4, 1, 0, 0, 178, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #398 = ATOMIC_LOAD_XOR_I32
7173 { 397, 6, 1, 4, 672, 0, 0, 181, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #397 = ATOMIC_LOAD_XOR_I16_POSTRA
7174 { 396, 3, 1, 4, 1, 0, 0, 178, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #396 = ATOMIC_LOAD_XOR_I16
7175 { 395, 6, 1, 4, 672, 0, 0, 181, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #395 = ATOMIC_LOAD_UMIN_I8_POSTRA
7176 { 394, 3, 1, 4, 1, 0, 0, 178, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #394 = ATOMIC_LOAD_UMIN_I8
7177 { 393, 3, 1, 4, 672, 0, 0, 187, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #393 = ATOMIC_LOAD_UMIN_I64_POSTRA
7178 { 392, 3, 1, 4, 1, 0, 0, 187, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #392 = ATOMIC_LOAD_UMIN_I64
7179 { 391, 3, 1, 4, 672, 0, 0, 178, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #391 = ATOMIC_LOAD_UMIN_I32_POSTRA
7180 { 390, 3, 1, 4, 1, 0, 0, 178, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #390 = ATOMIC_LOAD_UMIN_I32
7181 { 389, 6, 1, 4, 672, 0, 0, 181, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #389 = ATOMIC_LOAD_UMIN_I16_POSTRA
7182 { 388, 3, 1, 4, 1, 0, 0, 178, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #388 = ATOMIC_LOAD_UMIN_I16
7183 { 387, 6, 1, 4, 672, 0, 0, 181, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #387 = ATOMIC_LOAD_UMAX_I8_POSTRA
7184 { 386, 3, 1, 4, 1, 0, 0, 178, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #386 = ATOMIC_LOAD_UMAX_I8
7185 { 385, 3, 1, 4, 672, 0, 0, 187, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #385 = ATOMIC_LOAD_UMAX_I64_POSTRA
7186 { 384, 3, 1, 4, 1, 0, 0, 187, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #384 = ATOMIC_LOAD_UMAX_I64
7187 { 383, 3, 1, 4, 672, 0, 0, 178, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #383 = ATOMIC_LOAD_UMAX_I32_POSTRA
7188 { 382, 3, 1, 4, 1, 0, 0, 178, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #382 = ATOMIC_LOAD_UMAX_I32
7189 { 381, 6, 1, 4, 672, 0, 0, 181, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #381 = ATOMIC_LOAD_UMAX_I16_POSTRA
7190 { 380, 3, 1, 4, 1, 0, 0, 178, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #380 = ATOMIC_LOAD_UMAX_I16
7191 { 379, 6, 1, 4, 672, 0, 0, 181, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #379 = ATOMIC_LOAD_SUB_I8_POSTRA
7192 { 378, 3, 1, 4, 1, 0, 0, 178, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #378 = ATOMIC_LOAD_SUB_I8
7193 { 377, 3, 1, 4, 672, 0, 0, 187, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #377 = ATOMIC_LOAD_SUB_I64_POSTRA
7194 { 376, 3, 1, 4, 1, 0, 0, 187, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #376 = ATOMIC_LOAD_SUB_I64
7195 { 375, 3, 1, 4, 672, 0, 0, 178, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #375 = ATOMIC_LOAD_SUB_I32_POSTRA
7196 { 374, 3, 1, 4, 1, 0, 0, 178, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #374 = ATOMIC_LOAD_SUB_I32
7197 { 373, 6, 1, 4, 672, 0, 0, 181, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #373 = ATOMIC_LOAD_SUB_I16_POSTRA
7198 { 372, 3, 1, 4, 1, 0, 0, 178, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #372 = ATOMIC_LOAD_SUB_I16
7199 { 371, 6, 1, 4, 672, 0, 0, 181, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #371 = ATOMIC_LOAD_OR_I8_POSTRA
7200 { 370, 3, 1, 4, 1, 0, 0, 178, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #370 = ATOMIC_LOAD_OR_I8
7201 { 369, 3, 1, 4, 672, 0, 0, 187, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #369 = ATOMIC_LOAD_OR_I64_POSTRA
7202 { 368, 3, 1, 4, 1, 0, 0, 187, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #368 = ATOMIC_LOAD_OR_I64
7203 { 367, 3, 1, 4, 672, 0, 0, 178, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #367 = ATOMIC_LOAD_OR_I32_POSTRA
7204 { 366, 3, 1, 4, 1, 0, 0, 178, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #366 = ATOMIC_LOAD_OR_I32
7205 { 365, 6, 1, 4, 672, 0, 0, 181, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #365 = ATOMIC_LOAD_OR_I16_POSTRA
7206 { 364, 3, 1, 4, 1, 0, 0, 178, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #364 = ATOMIC_LOAD_OR_I16
7207 { 363, 6, 1, 4, 672, 0, 0, 181, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #363 = ATOMIC_LOAD_NAND_I8_POSTRA
7208 { 362, 3, 1, 4, 1, 0, 0, 178, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #362 = ATOMIC_LOAD_NAND_I8
7209 { 361, 3, 1, 4, 672, 0, 0, 187, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #361 = ATOMIC_LOAD_NAND_I64_POSTRA
7210 { 360, 3, 1, 4, 1, 0, 0, 187, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #360 = ATOMIC_LOAD_NAND_I64
7211 { 359, 3, 1, 4, 672, 0, 0, 178, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #359 = ATOMIC_LOAD_NAND_I32_POSTRA
7212 { 358, 3, 1, 4, 1, 0, 0, 178, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #358 = ATOMIC_LOAD_NAND_I32
7213 { 357, 6, 1, 4, 672, 0, 0, 181, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #357 = ATOMIC_LOAD_NAND_I16_POSTRA
7214 { 356, 3, 1, 4, 1, 0, 0, 178, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #356 = ATOMIC_LOAD_NAND_I16
7215 { 355, 6, 1, 4, 672, 0, 0, 181, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #355 = ATOMIC_LOAD_MIN_I8_POSTRA
7216 { 354, 3, 1, 4, 1, 0, 0, 178, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #354 = ATOMIC_LOAD_MIN_I8
7217 { 353, 3, 1, 4, 672, 0, 0, 187, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #353 = ATOMIC_LOAD_MIN_I64_POSTRA
7218 { 352, 3, 1, 4, 1, 0, 0, 187, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #352 = ATOMIC_LOAD_MIN_I64
7219 { 351, 3, 1, 4, 672, 0, 0, 178, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #351 = ATOMIC_LOAD_MIN_I32_POSTRA
7220 { 350, 3, 1, 4, 1, 0, 0, 178, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #350 = ATOMIC_LOAD_MIN_I32
7221 { 349, 6, 1, 4, 672, 0, 0, 181, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #349 = ATOMIC_LOAD_MIN_I16_POSTRA
7222 { 348, 3, 1, 4, 1, 0, 0, 178, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #348 = ATOMIC_LOAD_MIN_I16
7223 { 347, 6, 1, 4, 672, 0, 0, 181, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #347 = ATOMIC_LOAD_MAX_I8_POSTRA
7224 { 346, 3, 1, 4, 1, 0, 0, 178, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #346 = ATOMIC_LOAD_MAX_I8
7225 { 345, 3, 1, 4, 672, 0, 0, 187, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #345 = ATOMIC_LOAD_MAX_I64_POSTRA
7226 { 344, 3, 1, 4, 1, 0, 0, 187, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #344 = ATOMIC_LOAD_MAX_I64
7227 { 343, 3, 1, 4, 672, 0, 0, 178, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #343 = ATOMIC_LOAD_MAX_I32_POSTRA
7228 { 342, 3, 1, 4, 1, 0, 0, 178, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #342 = ATOMIC_LOAD_MAX_I32
7229 { 341, 6, 1, 4, 672, 0, 0, 181, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #341 = ATOMIC_LOAD_MAX_I16_POSTRA
7230 { 340, 3, 1, 4, 1, 0, 0, 178, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #340 = ATOMIC_LOAD_MAX_I16
7231 { 339, 6, 1, 4, 672, 0, 0, 181, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #339 = ATOMIC_LOAD_AND_I8_POSTRA
7232 { 338, 3, 1, 4, 1, 0, 0, 178, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #338 = ATOMIC_LOAD_AND_I8
7233 { 337, 3, 1, 4, 672, 0, 0, 187, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #337 = ATOMIC_LOAD_AND_I64_POSTRA
7234 { 336, 3, 1, 4, 1, 0, 0, 187, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #336 = ATOMIC_LOAD_AND_I64
7235 { 335, 3, 1, 4, 672, 0, 0, 178, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #335 = ATOMIC_LOAD_AND_I32_POSTRA
7236 { 334, 3, 1, 4, 1, 0, 0, 178, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #334 = ATOMIC_LOAD_AND_I32
7237 { 333, 6, 1, 4, 672, 0, 0, 181, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #333 = ATOMIC_LOAD_AND_I16_POSTRA
7238 { 332, 3, 1, 4, 1, 0, 0, 178, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #332 = ATOMIC_LOAD_AND_I16
7239 { 331, 6, 1, 4, 672, 0, 0, 181, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #331 = ATOMIC_LOAD_ADD_I8_POSTRA
7240 { 330, 3, 1, 4, 1, 0, 0, 178, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #330 = ATOMIC_LOAD_ADD_I8
7241 { 329, 3, 1, 4, 672, 0, 0, 187, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #329 = ATOMIC_LOAD_ADD_I64_POSTRA
7242 { 328, 3, 1, 4, 1, 0, 0, 187, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #328 = ATOMIC_LOAD_ADD_I64
7243 { 327, 3, 1, 4, 672, 0, 0, 178, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #327 = ATOMIC_LOAD_ADD_I32_POSTRA
7244 { 326, 3, 1, 4, 1, 0, 0, 178, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #326 = ATOMIC_LOAD_ADD_I32
7245 { 325, 6, 1, 4, 672, 0, 0, 181, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #325 = ATOMIC_LOAD_ADD_I16_POSTRA
7246 { 324, 3, 1, 4, 1, 0, 0, 178, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #324 = ATOMIC_LOAD_ADD_I16
7247 { 323, 7, 1, 4, 671, 0, 0, 167, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #323 = ATOMIC_CMP_SWAP_I8_POSTRA
7248 { 322, 4, 1, 4, 1, 0, 0, 163, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #322 = ATOMIC_CMP_SWAP_I8
7249 { 321, 4, 1, 4, 671, 0, 0, 174, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #321 = ATOMIC_CMP_SWAP_I64_POSTRA
7250 { 320, 4, 1, 4, 1, 0, 0, 174, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #320 = ATOMIC_CMP_SWAP_I64
7251 { 319, 4, 1, 4, 671, 0, 0, 163, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #319 = ATOMIC_CMP_SWAP_I32_POSTRA
7252 { 318, 4, 1, 4, 1, 0, 0, 163, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #318 = ATOMIC_CMP_SWAP_I32
7253 { 317, 7, 1, 4, 671, 0, 0, 167, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #317 = ATOMIC_CMP_SWAP_I16_POSTRA
7254 { 316, 4, 1, 4, 1, 0, 0, 163, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #316 = ATOMIC_CMP_SWAP_I16
7255 { 315, 3, 1, 4, 595, 0, 0, 160, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #315 = AND_V_W_PSEUDO
7256 { 314, 3, 1, 4, 595, 0, 0, 157, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #314 = AND_V_H_PSEUDO
7257 { 313, 3, 1, 4, 595, 0, 0, 154, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #313 = AND_V_D_PSEUDO
7258 { 312, 2, 0, 4, 1, 1, 1, 21, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #312 = ADJCALLSTACKUP
7259 { 311, 2, 0, 4, 1, 1, 1, 21, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #311 = ADJCALLSTACKDOWN
7260 { 310, 2, 1, 4, 1, 0, 0, 152, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #310 = ABSMacro
7261 { 309, 4, 1, 0, 0, 0, 0, 148, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #309 = G_UBFX
7262 { 308, 4, 1, 0, 0, 0, 0, 148, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #308 = G_SBFX
7263 { 307, 2, 1, 0, 0, 0, 0, 61, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #307 = G_VECREDUCE_UMIN
7264 { 306, 2, 1, 0, 0, 0, 0, 61, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #306 = G_VECREDUCE_UMAX
7265 { 305, 2, 1, 0, 0, 0, 0, 61, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #305 = G_VECREDUCE_SMIN
7266 { 304, 2, 1, 0, 0, 0, 0, 61, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #304 = G_VECREDUCE_SMAX
7267 { 303, 2, 1, 0, 0, 0, 0, 61, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #303 = G_VECREDUCE_XOR
7268 { 302, 2, 1, 0, 0, 0, 0, 61, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #302 = G_VECREDUCE_OR
7269 { 301, 2, 1, 0, 0, 0, 0, 61, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #301 = G_VECREDUCE_AND
7270 { 300, 2, 1, 0, 0, 0, 0, 61, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #300 = G_VECREDUCE_MUL
7271 { 299, 2, 1, 0, 0, 0, 0, 61, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #299 = G_VECREDUCE_ADD
7272 { 298, 2, 1, 0, 0, 0, 0, 61, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #298 = G_VECREDUCE_FMINIMUM
7273 { 297, 2, 1, 0, 0, 0, 0, 61, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #297 = G_VECREDUCE_FMAXIMUM
7274 { 296, 2, 1, 0, 0, 0, 0, 61, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #296 = G_VECREDUCE_FMIN
7275 { 295, 2, 1, 0, 0, 0, 0, 61, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #295 = G_VECREDUCE_FMAX
7276 { 294, 2, 1, 0, 0, 0, 0, 61, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #294 = G_VECREDUCE_FMUL
7277 { 293, 2, 1, 0, 0, 0, 0, 61, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #293 = G_VECREDUCE_FADD
7278 { 292, 3, 1, 0, 0, 0, 0, 131, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #292 = G_VECREDUCE_SEQ_FMUL
7279 { 291, 3, 1, 0, 0, 0, 0, 131, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #291 = G_VECREDUCE_SEQ_FADD
7280 { 290, 1, 0, 0, 0, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #290 = G_UBSANTRAP
7281 { 289, 0, 0, 0, 0, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #289 = G_DEBUGTRAP
7282 { 288, 0, 0, 0, 0, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #288 = G_TRAP
7283 { 287, 3, 0, 0, 0, 0, 0, 58, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #287 = G_BZERO
7284 { 286, 4, 0, 0, 0, 0, 0, 144, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #286 = G_MEMSET
7285 { 285, 4, 0, 0, 0, 0, 0, 144, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #285 = G_MEMMOVE
7286 { 284, 3, 0, 0, 0, 0, 0, 131, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #284 = G_MEMCPY_INLINE
7287 { 283, 4, 0, 0, 0, 0, 0, 144, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #283 = G_MEMCPY
7288 { 282, 2, 0, 0, 0, 0, 0, 142, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #282 = G_WRITE_REGISTER
7289 { 281, 2, 1, 0, 0, 0, 0, 51, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #281 = G_READ_REGISTER
7290 { 280, 3, 1, 0, 0, 0, 0, 101, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #280 = G_STRICT_FLDEXP
7291 { 279, 2, 1, 0, 0, 0, 0, 67, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #279 = G_STRICT_FSQRT
7292 { 278, 4, 1, 0, 0, 0, 0, 46, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #278 = G_STRICT_FMA
7293 { 277, 3, 1, 0, 0, 0, 0, 43, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #277 = G_STRICT_FREM
7294 { 276, 3, 1, 0, 0, 0, 0, 43, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #276 = G_STRICT_FDIV
7295 { 275, 3, 1, 0, 0, 0, 0, 43, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #275 = G_STRICT_FMUL
7296 { 274, 3, 1, 0, 0, 0, 0, 43, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #274 = G_STRICT_FSUB
7297 { 273, 3, 1, 0, 0, 0, 0, 43, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #273 = G_STRICT_FADD
7298 { 272, 1, 0, 0, 0, 0, 0, 50, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #272 = G_STACKRESTORE
7299 { 271, 1, 1, 0, 0, 0, 0, 50, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #271 = G_STACKSAVE
7300 { 270, 3, 1, 0, 0, 0, 0, 69, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #270 = G_DYN_STACKALLOC
7301 { 269, 2, 1, 0, 0, 0, 0, 51, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #269 = G_JUMP_TABLE
7302 { 268, 2, 1, 0, 0, 0, 0, 51, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #268 = G_BLOCK_ADDR
7303 { 267, 2, 1, 0, 0, 0, 0, 61, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #267 = G_ADDRSPACE_CAST
7304 { 266, 2, 1, 0, 0, 0, 0, 67, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #266 = G_FNEARBYINT
7305 { 265, 2, 1, 0, 0, 0, 0, 67, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #265 = G_FRINT
7306 { 264, 2, 1, 0, 0, 0, 0, 67, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #264 = G_FFLOOR
7307 { 263, 2, 1, 0, 0, 0, 0, 67, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #263 = G_FSQRT
7308 { 262, 2, 1, 0, 0, 0, 0, 67, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #262 = G_FTANH
7309 { 261, 2, 1, 0, 0, 0, 0, 67, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #261 = G_FSINH
7310 { 260, 2, 1, 0, 0, 0, 0, 67, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #260 = G_FCOSH
7311 { 259, 3, 1, 0, 0, 0, 0, 43, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #259 = G_FATAN2
7312 { 258, 2, 1, 0, 0, 0, 0, 67, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #258 = G_FATAN
7313 { 257, 2, 1, 0, 0, 0, 0, 67, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #257 = G_FASIN
7314 { 256, 2, 1, 0, 0, 0, 0, 67, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #256 = G_FACOS
7315 { 255, 2, 1, 0, 0, 0, 0, 67, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #255 = G_FTAN
7316 { 254, 3, 2, 0, 0, 0, 0, 43, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #254 = G_FSINCOS
7317 { 253, 2, 1, 0, 0, 0, 0, 67, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #253 = G_FSIN
7318 { 252, 2, 1, 0, 0, 0, 0, 67, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #252 = G_FCOS
7319 { 251, 2, 1, 0, 0, 0, 0, 67, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #251 = G_FCEIL
7320 { 250, 2, 1, 0, 0, 0, 0, 67, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #250 = G_BITREVERSE
7321 { 249, 2, 1, 0, 0, 0, 0, 67, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #249 = G_BSWAP
7322 { 248, 2, 1, 0, 0, 0, 0, 61, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #248 = G_CTPOP
7323 { 247, 2, 1, 0, 0, 0, 0, 61, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #247 = G_CTLZ_ZERO_UNDEF
7324 { 246, 2, 1, 0, 0, 0, 0, 61, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #246 = G_CTLZ
7325 { 245, 2, 1, 0, 0, 0, 0, 61, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #245 = G_CTTZ_ZERO_UNDEF
7326 { 244, 2, 1, 0, 0, 0, 0, 61, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #244 = G_CTTZ
7327 { 243, 4, 1, 0, 0, 0, 0, 138, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #243 = G_VECTOR_COMPRESS
7328 { 242, 2, 1, 0, 0, 0, 0, 51, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #242 = G_STEP_VECTOR
7329 { 241, 2, 1, 0, 0, 0, 0, 61, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #241 = G_SPLAT_VECTOR
7330 { 240, 4, 1, 0, 0, 0, 0, 134, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #240 = G_SHUFFLE_VECTOR
7331 { 239, 3, 1, 0, 0, 0, 0, 131, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #239 = G_EXTRACT_VECTOR_ELT
7332 { 238, 4, 1, 0, 0, 0, 0, 127, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #238 = G_INSERT_VECTOR_ELT
7333 { 237, 3, 1, 0, 0, 0, 0, 58, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #237 = G_EXTRACT_SUBVECTOR
7334 { 236, 4, 1, 0, 0, 0, 0, 63, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #236 = G_INSERT_SUBVECTOR
7335 { 235, 2, 1, 0, 0, 0, 0, 51, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #235 = G_VSCALE
7336 { 234, 3, 0, 0, 0, 0, 0, 124, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #234 = G_BRJT
7337 { 233, 1, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #233 = G_BR
7338 { 232, 2, 1, 0, 0, 0, 0, 61, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #232 = G_LLROUND
7339 { 231, 2, 1, 0, 0, 0, 0, 61, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #231 = G_LROUND
7340 { 230, 2, 1, 0, 0, 0, 0, 67, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #230 = G_ABS
7341 { 229, 3, 1, 0, 0, 0, 0, 43, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #229 = G_UMAX
7342 { 228, 3, 1, 0, 0, 0, 0, 43, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #228 = G_UMIN
7343 { 227, 3, 1, 0, 0, 0, 0, 43, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #227 = G_SMAX
7344 { 226, 3, 1, 0, 0, 0, 0, 43, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #226 = G_SMIN
7345 { 225, 3, 1, 0, 0, 0, 0, 101, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #225 = G_PTRMASK
7346 { 224, 3, 1, 0, 0, 0, 0, 101, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #224 = G_PTR_ADD
7347 { 223, 0, 0, 0, 0, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #223 = G_RESET_FPMODE
7348 { 222, 1, 0, 0, 0, 0, 0, 50, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #222 = G_SET_FPMODE
7349 { 221, 1, 1, 0, 0, 0, 0, 50, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #221 = G_GET_FPMODE
7350 { 220, 0, 0, 0, 0, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #220 = G_RESET_FPENV
7351 { 219, 1, 0, 0, 0, 0, 0, 50, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #219 = G_SET_FPENV
7352 { 218, 1, 1, 0, 0, 0, 0, 50, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #218 = G_GET_FPENV
7353 { 217, 3, 1, 0, 0, 0, 0, 43, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #217 = G_FMAXIMUMNUM
7354 { 216, 3, 1, 0, 0, 0, 0, 43, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #216 = G_FMINIMUMNUM
7355 { 215, 3, 1, 0, 0, 0, 0, 43, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #215 = G_FMAXIMUM
7356 { 214, 3, 1, 0, 0, 0, 0, 43, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #214 = G_FMINIMUM
7357 { 213, 3, 1, 0, 0, 0, 0, 43, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #213 = G_FMAXNUM_IEEE
7358 { 212, 3, 1, 0, 0, 0, 0, 43, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #212 = G_FMINNUM_IEEE
7359 { 211, 3, 1, 0, 0, 0, 0, 43, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #211 = G_FMAXNUM
7360 { 210, 3, 1, 0, 0, 0, 0, 43, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #210 = G_FMINNUM
7361 { 209, 2, 1, 0, 0, 0, 0, 67, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #209 = G_FCANONICALIZE
7362 { 208, 3, 1, 0, 0, 0, 0, 98, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #208 = G_IS_FPCLASS
7363 { 207, 3, 1, 0, 0, 0, 0, 101, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #207 = G_FCOPYSIGN
7364 { 206, 2, 1, 0, 0, 0, 0, 67, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #206 = G_FABS
7365 { 205, 2, 1, 0, 0, 0, 0, 61, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #205 = G_FPTOUI_SAT
7366 { 204, 2, 1, 0, 0, 0, 0, 61, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #204 = G_FPTOSI_SAT
7367 { 203, 2, 1, 0, 0, 0, 0, 61, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #203 = G_UITOFP
7368 { 202, 2, 1, 0, 0, 0, 0, 61, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #202 = G_SITOFP
7369 { 201, 2, 1, 0, 0, 0, 0, 61, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #201 = G_FPTOUI
7370 { 200, 2, 1, 0, 0, 0, 0, 61, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #200 = G_FPTOSI
7371 { 199, 2, 1, 0, 0, 0, 0, 61, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #199 = G_FPTRUNC
7372 { 198, 2, 1, 0, 0, 0, 0, 61, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #198 = G_FPEXT
7373 { 197, 2, 1, 0, 0, 0, 0, 67, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #197 = G_FNEG
7374 { 196, 3, 2, 0, 0, 0, 0, 91, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #196 = G_FFREXP
7375 { 195, 3, 1, 0, 0, 0, 0, 101, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #195 = G_FLDEXP
7376 { 194, 2, 1, 0, 0, 0, 0, 67, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #194 = G_FLOG10
7377 { 193, 2, 1, 0, 0, 0, 0, 67, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #193 = G_FLOG2
7378 { 192, 2, 1, 0, 0, 0, 0, 67, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #192 = G_FLOG
7379 { 191, 2, 1, 0, 0, 0, 0, 67, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #191 = G_FEXP10
7380 { 190, 2, 1, 0, 0, 0, 0, 67, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #190 = G_FEXP2
7381 { 189, 2, 1, 0, 0, 0, 0, 67, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #189 = G_FEXP
7382 { 188, 3, 1, 0, 0, 0, 0, 101, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #188 = G_FPOWI
7383 { 187, 3, 1, 0, 0, 0, 0, 43, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #187 = G_FPOW
7384 { 186, 3, 1, 0, 0, 0, 0, 43, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #186 = G_FREM
7385 { 185, 3, 1, 0, 0, 0, 0, 43, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #185 = G_FDIV
7386 { 184, 4, 1, 0, 0, 0, 0, 46, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #184 = G_FMAD
7387 { 183, 4, 1, 0, 0, 0, 0, 46, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #183 = G_FMA
7388 { 182, 3, 1, 0, 0, 0, 0, 43, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #182 = G_FMUL
7389 { 181, 3, 1, 0, 0, 0, 0, 43, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #181 = G_FSUB
7390 { 180, 3, 1, 0, 0, 0, 0, 43, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #180 = G_FADD
7391 { 179, 4, 1, 0, 0, 0, 0, 120, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #179 = G_UDIVFIXSAT
7392 { 178, 4, 1, 0, 0, 0, 0, 120, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #178 = G_SDIVFIXSAT
7393 { 177, 4, 1, 0, 0, 0, 0, 120, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #177 = G_UDIVFIX
7394 { 176, 4, 1, 0, 0, 0, 0, 120, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #176 = G_SDIVFIX
7395 { 175, 4, 1, 0, 0, 0, 0, 120, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #175 = G_UMULFIXSAT
7396 { 174, 4, 1, 0, 0, 0, 0, 120, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #174 = G_SMULFIXSAT
7397 { 173, 4, 1, 0, 0, 0, 0, 120, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #173 = G_UMULFIX
7398 { 172, 4, 1, 0, 0, 0, 0, 120, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #172 = G_SMULFIX
7399 { 171, 3, 1, 0, 0, 0, 0, 101, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #171 = G_SSHLSAT
7400 { 170, 3, 1, 0, 0, 0, 0, 101, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #170 = G_USHLSAT
7401 { 169, 3, 1, 0, 0, 0, 0, 43, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #169 = G_SSUBSAT
7402 { 168, 3, 1, 0, 0, 0, 0, 43, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #168 = G_USUBSAT
7403 { 167, 3, 1, 0, 0, 0, 0, 43, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #167 = G_SADDSAT
7404 { 166, 3, 1, 0, 0, 0, 0, 43, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #166 = G_UADDSAT
7405 { 165, 3, 1, 0, 0, 0, 0, 43, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #165 = G_SMULH
7406 { 164, 3, 1, 0, 0, 0, 0, 43, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #164 = G_UMULH
7407 { 163, 4, 2, 0, 0, 0, 0, 87, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #163 = G_SMULO
7408 { 162, 4, 2, 0, 0, 0, 0, 87, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #162 = G_UMULO
7409 { 161, 5, 2, 0, 0, 0, 0, 115, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #161 = G_SSUBE
7410 { 160, 4, 2, 0, 0, 0, 0, 87, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #160 = G_SSUBO
7411 { 159, 5, 2, 0, 0, 0, 0, 115, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #159 = G_SADDE
7412 { 158, 4, 2, 0, 0, 0, 0, 87, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #158 = G_SADDO
7413 { 157, 5, 2, 0, 0, 0, 0, 115, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #157 = G_USUBE
7414 { 156, 4, 2, 0, 0, 0, 0, 87, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #156 = G_USUBO
7415 { 155, 5, 2, 0, 0, 0, 0, 115, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #155 = G_UADDE
7416 { 154, 4, 2, 0, 0, 0, 0, 87, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #154 = G_UADDO
7417 { 153, 4, 1, 0, 0, 0, 0, 87, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #153 = G_SELECT
7418 { 152, 3, 1, 0, 0, 0, 0, 112, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #152 = G_UCMP
7419 { 151, 3, 1, 0, 0, 0, 0, 112, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #151 = G_SCMP
7420 { 150, 4, 1, 0, 0, 0, 0, 108, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #150 = G_FCMP
7421 { 149, 4, 1, 0, 0, 0, 0, 108, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #149 = G_ICMP
7422 { 148, 3, 1, 0, 0, 0, 0, 101, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #148 = G_ROTL
7423 { 147, 3, 1, 0, 0, 0, 0, 101, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #147 = G_ROTR
7424 { 146, 4, 1, 0, 0, 0, 0, 104, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #146 = G_FSHR
7425 { 145, 4, 1, 0, 0, 0, 0, 104, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #145 = G_FSHL
7426 { 144, 3, 1, 0, 0, 0, 0, 101, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #144 = G_ASHR
7427 { 143, 3, 1, 0, 0, 0, 0, 101, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #143 = G_LSHR
7428 { 142, 3, 1, 0, 0, 0, 0, 101, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #142 = G_SHL
7429 { 141, 2, 1, 0, 0, 0, 0, 61, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #141 = G_ZEXT
7430 { 140, 3, 1, 0, 0, 0, 0, 40, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #140 = G_SEXT_INREG
7431 { 139, 2, 1, 0, 0, 0, 0, 61, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #139 = G_SEXT
7432 { 138, 3, 1, 0, 0, 0, 0, 98, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #138 = G_VAARG
7433 { 137, 1, 0, 0, 0, 0, 0, 50, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #137 = G_VASTART
7434 { 136, 2, 1, 0, 0, 0, 0, 51, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #136 = G_FCONSTANT
7435 { 135, 2, 1, 0, 0, 0, 0, 51, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #135 = G_CONSTANT
7436 { 134, 2, 1, 0, 0, 0, 0, 61, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #134 = G_TRUNC
7437 { 133, 2, 1, 0, 0, 0, 0, 61, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #133 = G_ANYEXT
7438 { 132, 1, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #132 = G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
7439 { 131, 1, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #131 = G_INTRINSIC_CONVERGENT
7440 { 130, 1, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #130 = G_INTRINSIC_W_SIDE_EFFECTS
7441 { 129, 1, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #129 = G_INTRINSIC
7442 { 128, 0, 0, 0, 0, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #128 = G_INVOKE_REGION_START
7443 { 127, 1, 0, 0, 0, 0, 0, 50, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #127 = G_BRINDIRECT
7444 { 126, 2, 0, 0, 0, 0, 0, 51, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #126 = G_BRCOND
7445 { 125, 4, 0, 0, 0, 0, 0, 94, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #125 = G_PREFETCH
7446 { 124, 2, 0, 0, 0, 0, 0, 21, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #124 = G_FENCE
7447 { 123, 3, 1, 0, 0, 0, 0, 91, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #123 = G_ATOMICRMW_USUB_SAT
7448 { 122, 3, 1, 0, 0, 0, 0, 91, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #122 = G_ATOMICRMW_USUB_COND
7449 { 121, 3, 1, 0, 0, 0, 0, 91, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #121 = G_ATOMICRMW_UDEC_WRAP
7450 { 120, 3, 1, 0, 0, 0, 0, 91, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #120 = G_ATOMICRMW_UINC_WRAP
7451 { 119, 3, 1, 0, 0, 0, 0, 91, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #119 = G_ATOMICRMW_FMINIMUM
7452 { 118, 3, 1, 0, 0, 0, 0, 91, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #118 = G_ATOMICRMW_FMAXIMUM
7453 { 117, 3, 1, 0, 0, 0, 0, 91, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #117 = G_ATOMICRMW_FMIN
7454 { 116, 3, 1, 0, 0, 0, 0, 91, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #116 = G_ATOMICRMW_FMAX
7455 { 115, 3, 1, 0, 0, 0, 0, 91, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #115 = G_ATOMICRMW_FSUB
7456 { 114, 3, 1, 0, 0, 0, 0, 91, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #114 = G_ATOMICRMW_FADD
7457 { 113, 3, 1, 0, 0, 0, 0, 91, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #113 = G_ATOMICRMW_UMIN
7458 { 112, 3, 1, 0, 0, 0, 0, 91, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #112 = G_ATOMICRMW_UMAX
7459 { 111, 3, 1, 0, 0, 0, 0, 91, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #111 = G_ATOMICRMW_MIN
7460 { 110, 3, 1, 0, 0, 0, 0, 91, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #110 = G_ATOMICRMW_MAX
7461 { 109, 3, 1, 0, 0, 0, 0, 91, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #109 = G_ATOMICRMW_XOR
7462 { 108, 3, 1, 0, 0, 0, 0, 91, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #108 = G_ATOMICRMW_OR
7463 { 107, 3, 1, 0, 0, 0, 0, 91, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #107 = G_ATOMICRMW_NAND
7464 { 106, 3, 1, 0, 0, 0, 0, 91, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #106 = G_ATOMICRMW_AND
7465 { 105, 3, 1, 0, 0, 0, 0, 91, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #105 = G_ATOMICRMW_SUB
7466 { 104, 3, 1, 0, 0, 0, 0, 91, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #104 = G_ATOMICRMW_ADD
7467 { 103, 3, 1, 0, 0, 0, 0, 91, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #103 = G_ATOMICRMW_XCHG
7468 { 102, 4, 1, 0, 0, 0, 0, 87, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #102 = G_ATOMIC_CMPXCHG
7469 { 101, 5, 2, 0, 0, 0, 0, 82, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #101 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
7470 { 100, 5, 1, 0, 0, 0, 0, 77, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #100 = G_INDEXED_STORE
7471 { 99, 2, 0, 0, 0, 0, 0, 61, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #99 = G_STORE
7472 { 98, 5, 2, 0, 0, 0, 0, 72, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #98 = G_INDEXED_ZEXTLOAD
7473 { 97, 5, 2, 0, 0, 0, 0, 72, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #97 = G_INDEXED_SEXTLOAD
7474 { 96, 5, 2, 0, 0, 0, 0, 72, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #96 = G_INDEXED_LOAD
7475 { 95, 2, 1, 0, 0, 0, 0, 61, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #95 = G_ZEXTLOAD
7476 { 94, 2, 1, 0, 0, 0, 0, 61, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #94 = G_SEXTLOAD
7477 { 93, 2, 1, 0, 0, 0, 0, 61, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #93 = G_LOAD
7478 { 92, 1, 1, 0, 0, 0, 0, 50, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #92 = G_READSTEADYCOUNTER
7479 { 91, 1, 1, 0, 0, 0, 0, 50, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #91 = G_READCYCLECOUNTER
7480 { 90, 2, 1, 0, 0, 0, 0, 67, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #90 = G_INTRINSIC_ROUNDEVEN
7481 { 89, 2, 1, 0, 0, 0, 0, 61, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #89 = G_INTRINSIC_LLRINT
7482 { 88, 2, 1, 0, 0, 0, 0, 61, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #88 = G_INTRINSIC_LRINT
7483 { 87, 2, 1, 0, 0, 0, 0, 67, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #87 = G_INTRINSIC_ROUND
7484 { 86, 2, 1, 0, 0, 0, 0, 67, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #86 = G_INTRINSIC_TRUNC
7485 { 85, 3, 1, 0, 0, 0, 0, 69, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #85 = G_INTRINSIC_FPTRUNC_ROUND
7486 { 84, 2, 1, 0, 0, 0, 0, 67, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #84 = G_CONSTANT_FOLD_BARRIER
7487 { 83, 2, 1, 0, 0, 0, 0, 67, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #83 = G_FREEZE
7488 { 82, 2, 1, 0, 0, 0, 0, 61, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #82 = G_BITCAST
7489 { 81, 2, 1, 0, 0, 0, 0, 61, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #81 = G_INTTOPTR
7490 { 80, 2, 1, 0, 0, 0, 0, 61, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #80 = G_PTRTOINT
7491 { 79, 2, 1, 0, 0, 0, 0, 61, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #79 = G_CONCAT_VECTORS
7492 { 78, 2, 1, 0, 0, 0, 0, 61, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #78 = G_BUILD_VECTOR_TRUNC
7493 { 77, 2, 1, 0, 0, 0, 0, 61, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #77 = G_BUILD_VECTOR
7494 { 76, 2, 1, 0, 0, 0, 0, 61, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #76 = G_MERGE_VALUES
7495 { 75, 4, 1, 0, 0, 0, 0, 63, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #75 = G_INSERT
7496 { 74, 2, 1, 0, 0, 0, 0, 61, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #74 = G_UNMERGE_VALUES
7497 { 73, 3, 1, 0, 0, 0, 0, 58, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #73 = G_EXTRACT
7498 { 72, 2, 1, 0, 0, 0, 0, 51, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #72 = G_CONSTANT_POOL
7499 { 71, 5, 1, 0, 0, 0, 0, 53, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #71 = G_PTRAUTH_GLOBAL_VALUE
7500 { 70, 2, 1, 0, 0, 0, 0, 51, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #70 = G_GLOBAL_VALUE
7501 { 69, 2, 1, 0, 0, 0, 0, 51, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #69 = G_FRAME_INDEX
7502 { 68, 1, 1, 0, 0, 0, 0, 50, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #68 = G_PHI
7503 { 67, 1, 1, 0, 0, 0, 0, 50, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #67 = G_IMPLICIT_DEF
7504 { 66, 3, 1, 0, 0, 0, 0, 43, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #66 = G_ABDU
7505 { 65, 3, 1, 0, 0, 0, 0, 43, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #65 = G_ABDS
7506 { 64, 3, 1, 0, 0, 0, 0, 43, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #64 = G_XOR
7507 { 63, 3, 1, 0, 0, 0, 0, 43, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #63 = G_OR
7508 { 62, 3, 1, 0, 0, 0, 0, 43, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #62 = G_AND
7509 { 61, 4, 2, 0, 0, 0, 0, 46, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #61 = G_UDIVREM
7510 { 60, 4, 2, 0, 0, 0, 0, 46, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #60 = G_SDIVREM
7511 { 59, 3, 1, 0, 0, 0, 0, 43, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #59 = G_UREM
7512 { 58, 3, 1, 0, 0, 0, 0, 43, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #58 = G_SREM
7513 { 57, 3, 1, 0, 0, 0, 0, 43, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #57 = G_UDIV
7514 { 56, 3, 1, 0, 0, 0, 0, 43, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #56 = G_SDIV
7515 { 55, 3, 1, 0, 0, 0, 0, 43, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #55 = G_MUL
7516 { 54, 3, 1, 0, 0, 0, 0, 43, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #54 = G_SUB
7517 { 53, 3, 1, 0, 0, 0, 0, 43, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #53 = G_ADD
7518 { 52, 3, 1, 0, 0, 0, 0, 40, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #52 = G_ASSERT_ALIGN
7519 { 51, 3, 1, 0, 0, 0, 0, 40, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #51 = G_ASSERT_ZEXT
7520 { 50, 3, 1, 0, 0, 0, 0, 40, MipsImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #50 = G_ASSERT_SEXT
7521 { 49, 1, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #49 = CONVERGENCECTRL_GLUE
7522 { 48, 2, 1, 0, 0, 0, 0, 13, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #48 = CONVERGENCECTRL_LOOP
7523 { 47, 1, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #47 = CONVERGENCECTRL_ANCHOR
7524 { 46, 1, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #46 = CONVERGENCECTRL_ENTRY
7525 { 45, 1, 0, 0, 0, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #45 = JUMP_TABLE_DEBUG_INFO
7526 { 44, 0, 0, 0, 0, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #44 = MEMBARRIER
7527 { 43, 0, 0, 0, 0, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #43 = FAKE_USE
7528 { 42, 0, 0, 0, 0, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #42 = ICALL_BRANCH_FUNNEL
7529 { 41, 3, 0, 0, 0, 0, 0, 37, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #41 = PATCHABLE_TYPED_EVENT_CALL
7530 { 40, 2, 0, 0, 0, 0, 0, 35, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #40 = PATCHABLE_EVENT_CALL
7531 { 39, 0, 0, 0, 0, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #39 = PATCHABLE_TAIL_CALL
7532 { 38, 0, 0, 0, 0, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #38 = PATCHABLE_FUNCTION_EXIT
7533 { 37, 0, 0, 0, 0, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #37 = PATCHABLE_RET
7534 { 36, 0, 0, 0, 0, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #36 = PATCHABLE_FUNCTION_ENTER
7535 { 35, 0, 0, 0, 0, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #35 = PATCHABLE_OP
7536 { 34, 1, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #34 = FAULTING_OP
7537 { 33, 2, 0, 0, 0, 0, 0, 33, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #33 = LOCAL_ESCAPE
7538 { 32, 0, 0, 0, 0, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #32 = STATEPOINT
7539 { 31, 3, 1, 0, 0, 0, 0, 30, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #31 = PREALLOCATED_ARG
7540 { 30, 1, 0, 0, 0, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #30 = PREALLOCATED_SETUP
7541 { 29, 1, 1, 0, 0, 0, 0, 29, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #29 = LOAD_STACK_GUARD
7542 { 28, 6, 1, 0, 0, 0, 0, 23, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #28 = PATCHPOINT
7543 { 27, 0, 0, 0, 0, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #27 = FENTRY_CALL
7544 { 26, 2, 0, 0, 0, 0, 0, 21, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #26 = STACKMAP
7545 { 25, 2, 1, 0, 0, 0, 0, 19, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #25 = ARITH_FENCE
7546 { 24, 4, 0, 0, 0, 0, 0, 15, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #24 = PSEUDO_PROBE
7547 { 23, 1, 0, 0, 0, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #23 = LIFETIME_END
7548 { 22, 1, 0, 0, 0, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #22 = LIFETIME_START
7549 { 21, 0, 0, 0, 0, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #21 = BUNDLE
7550 { 20, 2, 1, 0, 529, 0, 0, 13, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #20 = COPY
7551 { 19, 2, 1, 0, 0, 0, 0, 13, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #19 = REG_SEQUENCE
7552 { 18, 1, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #18 = DBG_LABEL
7553 { 17, 0, 0, 0, 0, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #17 = DBG_PHI
7554 { 16, 0, 0, 0, 0, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #16 = DBG_INSTR_REF
7555 { 15, 0, 0, 0, 0, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #15 = DBG_VALUE_LIST
7556 { 14, 0, 0, 0, 0, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #14 = DBG_VALUE
7557 { 13, 3, 1, 0, 0, 0, 0, 2, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #13 = COPY_TO_REGCLASS
7558 { 12, 4, 1, 0, 0, 0, 0, 9, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #12 = SUBREG_TO_REG
7559 { 11, 1, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #11 = INIT_UNDEF
7560 { 10, 1, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #10 = IMPLICIT_DEF
7561 { 9, 4, 1, 0, 0, 0, 0, 5, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #9 = INSERT_SUBREG
7562 { 8, 3, 1, 0, 0, 0, 0, 2, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #8 = EXTRACT_SUBREG
7563 { 7, 0, 0, 0, 0, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #7 = KILL
7564 { 6, 1, 0, 0, 0, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #6 = ANNOTATION_LABEL
7565 { 5, 1, 0, 0, 0, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #5 = GC_LABEL
7566 { 4, 1, 0, 0, 0, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #4 = EH_LABEL
7567 { 3, 1, 0, 0, 0, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #3 = CFI_INSTRUCTION
7568 { 2, 0, 0, 0, 0, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2 = INLINEASM_BR
7569 { 1, 0, 0, 0, 0, 0, 0, 1, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #1 = INLINEASM
7570 { 0, 1, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #0 = PHI
7571 }, {
7572 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7573 /* 1 */
7574 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7575 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7576 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7577 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7578 /* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7579 /* 15 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7580 /* 19 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
7581 /* 21 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7582 /* 23 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7583 /* 29 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
7584 /* 30 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7585 /* 33 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7586 /* 35 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7587 /* 37 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7588 /* 40 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
7589 /* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
7590 /* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
7591 /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
7592 /* 51 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7593 /* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7594 /* 58 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
7595 /* 61 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
7596 /* 63 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
7597 /* 67 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
7598 /* 69 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7599 /* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7600 /* 77 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7601 /* 82 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
7602 /* 87 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
7603 /* 91 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
7604 /* 94 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7605 /* 98 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7606 /* 101 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
7607 /* 104 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
7608 /* 108 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
7609 /* 112 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
7610 /* 115 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
7611 /* 120 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
7612 /* 124 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
7613 /* 127 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
7614 /* 131 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
7615 /* 134 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7616 /* 138 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
7617 /* 142 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
7618 /* 144 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
7619 /* 148 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
7620 /* 152 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7621 /* 154 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7622 /* 157 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7623 /* 160 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7624 /* 163 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7625 /* 167 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7626 /* 174 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7627 /* 178 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7628 /* 181 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7629 /* 187 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7630 /* 190 */ { -1, 0, MCOI::OPERAND_PCREL, 0 },
7631 /* 191 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
7632 /* 194 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
7633 /* 197 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7634 /* 198 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7635 /* 202 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7636 /* 206 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7637 /* 210 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
7638 /* 213 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
7639 /* 216 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7640 /* 219 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7641 /* 222 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7642 /* 224 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7643 /* 227 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7644 /* 230 */ { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7645 /* 232 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7646 /* 235 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7647 /* 238 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7648 /* 241 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7649 /* 244 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7650 /* 247 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7651 /* 250 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7652 /* 252 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7653 /* 254 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7654 /* 256 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7655 /* 258 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7656 /* 262 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7657 /* 266 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7658 /* 270 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7659 /* 274 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7660 /* 278 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7661 /* 282 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7662 /* 286 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7663 /* 290 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7664 /* 294 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7665 /* 298 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7666 /* 302 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7667 /* 306 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7668 /* 310 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7669 /* 314 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7670 /* 318 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7671 /* 319 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 },
7672 /* 322 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7673 /* 325 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7674 /* 328 */ { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 },
7675 /* 331 */ { Mips::ACC128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 },
7676 /* 334 */ { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 },
7677 /* 337 */ { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 },
7678 /* 340 */ { Mips::DSPCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 },
7679 /* 343 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
7680 /* 347 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
7681 /* 351 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
7682 /* 354 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
7683 /* 357 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
7684 /* 359 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
7685 /* 361 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 },
7686 /* 364 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7687 /* 366 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7688 /* 368 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 },
7689 /* 371 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7690 /* 373 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7691 /* 375 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7692 /* 377 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7693 /* 379 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7694 /* 382 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7695 /* 384 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7696 /* 387 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7697 /* 389 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7698 /* 391 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7699 /* 393 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7700 /* 395 */ { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7701 /* 397 */ { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7702 /* 399 */ { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7703 /* 401 */ { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7704 /* 404 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7705 /* 406 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7706 /* 408 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7707 /* 411 */ { Mips::DSPCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7708 /* 414 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7709 /* 416 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7710 /* 418 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7711 /* 420 */ { Mips::ACC128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7712 /* 423 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7713 /* 430 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7714 /* 437 */ { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7715 /* 441 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7716 /* 443 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7717 /* 445 */ { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7718 /* 448 */ { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7719 /* 451 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7720 /* 455 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7721 /* 459 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7722 /* 463 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7723 /* 467 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7724 /* 471 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7725 /* 475 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7726 /* 479 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7727 /* 483 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7728 /* 487 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7729 /* 491 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7730 /* 495 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7731 /* 498 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7732 /* 501 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7733 /* 504 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 },
7734 /* 507 */ { Mips::GPR32NONZERORegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7735 /* 510 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7736 /* 512 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7737 /* 514 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7738 /* 516 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7739 /* 518 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7740 /* 522 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7741 /* 527 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7742 /* 532 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7743 /* 535 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7744 /* 537 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7745 /* 539 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7746 /* 542 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7747 /* 545 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7748 /* 548 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7749 /* 551 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7750 /* 554 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7751 /* 557 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7752 /* 560 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7753 /* 563 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7754 /* 566 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7755 /* 569 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7756 /* 573 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7757 /* 576 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7758 /* 580 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7759 /* 582 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7760 /* 585 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsPlusSPRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7761 /* 588 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7762 /* 591 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
7763 /* 594 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
7764 /* 596 */ { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
7765 /* 598 */ { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
7766 /* 600 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
7767 /* 602 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7768 /* 606 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7769 /* 610 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7770 /* 614 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7771 /* 618 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7772 /* 622 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
7773 /* 624 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
7774 /* 626 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
7775 /* 628 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
7776 /* 630 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
7777 /* 632 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7778 /* 635 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7779 /* 637 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7780 /* 639 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7781 /* 641 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7782 /* 643 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7783 /* 645 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7784 /* 647 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7785 /* 649 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSACtrlRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7786 /* 651 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7787 /* 655 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7788 /* 659 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7789 /* 663 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7790 /* 666 */ { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7791 /* 669 */ { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7792 /* 672 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7793 /* 675 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7794 /* 678 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7795 /* 681 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7796 /* 684 */ { Mips::CCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7797 /* 686 */ { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7798 /* 688 */ { Mips::MSACtrlRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7799 /* 690 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7800 /* 692 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7801 /* 695 */ { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7802 /* 698 */ { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7803 /* 701 */ { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7804 /* 704 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7805 /* 707 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7806 /* 711 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7807 /* 716 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7808 /* 719 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7809 /* 721 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7810 /* 724 */ { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7811 /* 727 */ { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7812 /* 730 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7813 /* 733 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7814 /* 736 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7815 /* 739 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7816 /* 743 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7817 /* 747 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7818 /* 751 */ { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7819 /* 755 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7820 /* 758 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7821 /* 760 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7822 /* 763 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7823 /* 766 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7824 /* 768 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7825 /* 771 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7826 /* 774 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7827 /* 777 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7828 /* 780 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7829 /* 783 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7830 /* 786 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7831 /* 789 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7832 /* 791 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7833 /* 793 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7834 /* 795 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7835 /* 797 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7836 /* 799 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7837 /* 801 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7838 /* 806 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7839 /* 810 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7840 /* 814 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7841 /* 818 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7842 /* 822 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7843 /* 825 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7844 /* 830 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7845 /* 835 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7846 /* 840 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7847 /* 845 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7848 /* 846 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 },
7849 /* 849 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
7850 /* 852 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 },
7851 /* 855 */ { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 },
7852 /* 858 */ { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 },
7853 /* 861 */ { Mips::COP3RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 },
7854 /* 864 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7855 /* 866 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7856 /* 868 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7857 /* 870 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7858 /* 872 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7859 /* 876 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
7860 /* 879 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
7861 /* 882 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 },
7862 /* 885 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 },
7863 /* 888 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 },
7864 /* 891 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 },
7865 /* 894 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MipsII::OPERAND_MEM_SIMM9, 0 }, { -1, 0, MipsII::OPERAND_MEM_SIMM9, 0 },
7866 /* 897 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MipsII::OPERAND_MEM_SIMM9, 0 }, { -1, 0, MipsII::OPERAND_MEM_SIMM9, 0 },
7867 /* 900 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 },
7868 /* 903 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 },
7869 /* 906 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 3, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 },
7870 /* 909 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7871 /* 913 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 2, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 },
7872 /* 916 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 },
7873 /* 920 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 2, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 },
7874 /* 923 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
7875 /* 926 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7876 /* 929 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7877 /* 932 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7878 /* 936 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7879 /* 940 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7880 /* 944 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7881 /* 948 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7882 /* 952 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7883 /* 954 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7884 /* 957 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7885 /* 959 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7886 /* 964 */ { Mips::GPRMM16MovePPairFirstRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16MovePPairSecondRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16MovePRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16MovePRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7887 /* 968 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7888 /* 970 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7889 /* 974 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7890 /* 978 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7891 /* 982 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7892 /* 986 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7893 /* 990 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7894 /* 994 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7895 /* 998 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7896 /* 1002 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7897 /* 1006 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7898 /* 1010 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7899 /* 1014 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7900 /* 1018 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7901 /* 1022 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7902 /* 1026 */ { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7903 /* 1029 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7904 /* 1032 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7905 /* 1035 */ { Mips::HI32DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7906 /* 1037 */ { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7907 /* 1040 */ { Mips::LO32DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7908 /* 1042 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7909 /* 1044 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7910 /* 1046 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7911 /* 1048 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7912 /* 1050 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7913 /* 1052 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7914 /* 1055 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7915 /* 1059 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7916 /* 1062 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::HWRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7917 /* 1065 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::HWRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7918 /* 1068 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7919 /* 1070 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7920 /* 1072 */ { Mips::GPRMM16ZeroRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 },
7921 /* 1075 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 },
7922 /* 1079 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MipsII::OPERAND_MEM_SIMM9, 0 }, { -1, 0, MipsII::OPERAND_MEM_SIMM9, 0 },
7923 /* 1083 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 },
7924 /* 1087 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MipsII::OPERAND_MEM_SIMM9, 0 }, { -1, 0, MipsII::OPERAND_MEM_SIMM9, 0 },
7925 /* 1091 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7926 /* 1095 */ { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7927 /* 1098 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7928 /* 1101 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7929 /* 1104 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7930 /* 1108 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7931 /* 1112 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7932 /* 1116 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7933 /* 1120 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7934 /* 1123 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7935 /* 1126 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7936 /* 1129 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7937 /* 1132 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7938 /* 1135 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7939 /* 1138 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 },
7940 /* 1140 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7941 }, {
7942 /* 0 */
7943 /* 0 */ Mips::SP, Mips::SP,
7944 /* 2 */ Mips::AT,
7945 /* 3 */ Mips::RA,
7946 /* 4 */ Mips::DSPPos,
7947 /* 5 */ Mips::V0, Mips::V1,
7948 /* 7 */ Mips::HI0, Mips::LO0,
7949 /* 9 */ Mips::T8,
7950 /* 10 */ Mips::DSPOutFlag20,
7951 /* 11 */ Mips::DSPCarry,
7952 /* 12 */ Mips::DSPCarry, Mips::DSPOutFlag20,
7953 /* 14 */ Mips::DSPCCond,
7954 /* 15 */ Mips::HI0, Mips::LO0, Mips::P0, Mips::P1, Mips::P2,
7955 /* 20 */ Mips::HI0_64, Mips::LO0_64,
7956 /* 22 */ Mips::DSPOutFlag16_19,
7957 /* 23 */ Mips::DSPPos, Mips::DSPEFI,
7958 /* 25 */ Mips::DSPPos, Mips::DSPPos, Mips::DSPEFI,
7959 /* 28 */ Mips::DSPOutFlag23,
7960 /* 29 */ Mips::FCC0,
7961 /* 30 */ Mips::DSPPos, Mips::DSPSCount,
7962 /* 32 */ Mips::HI0, Mips::LO0, Mips::HI0, Mips::LO0,
7963 /* 36 */ Mips::AC0,
7964 /* 37 */ Mips::AC0_64,
7965 /* 38 */ Mips::HI0,
7966 /* 39 */ Mips::HI0_64,
7967 /* 40 */ Mips::LO0,
7968 /* 41 */ Mips::LO0_64,
7969 /* 42 */ Mips::MPL0, Mips::P0, Mips::P1, Mips::P2,
7970 /* 46 */ Mips::MPL1, Mips::P0, Mips::P1, Mips::P2,
7971 /* 50 */ Mips::MPL2, Mips::P0, Mips::P1, Mips::P2,
7972 /* 54 */ Mips::P0,
7973 /* 55 */ Mips::P1,
7974 /* 56 */ Mips::P2,
7975 /* 57 */ Mips::DSPOutFlag21,
7976 /* 58 */ Mips::DSPOutFlag22,
7977 /* 59 */ Mips::P0, Mips::P1, Mips::P2,
7978 /* 62 */ Mips::MPL1, Mips::MPL2, Mips::P0, Mips::P1, Mips::P2,
7979 }
7980};
7981
7982
7983#ifdef __GNUC__
7984#pragma GCC diagnostic push
7985#pragma GCC diagnostic ignored "-Woverlength-strings"
7986#endif
7987extern const char MipsInstrNameData[] = {
7988 /* 0 */ "G_FLOG10\000"
7989 /* 9 */ "G_FEXP10\000"
7990 /* 18 */ "DMFC0\000"
7991 /* 24 */ "DMFGC0\000"
7992 /* 31 */ "MFHGC0\000"
7993 /* 38 */ "MTHGC0\000"
7994 /* 45 */ "DMTGC0\000"
7995 /* 52 */ "MFTC0\000"
7996 /* 58 */ "DMTC0\000"
7997 /* 64 */ "MTTC0\000"
7998 /* 70 */ "VMM0\000"
7999 /* 75 */ "MTM0\000"
8000 /* 80 */ "MTP0\000"
8001 /* 85 */ "BBIT0\000"
8002 /* 91 */ "LDC1\000"
8003 /* 96 */ "SDC1\000"
8004 /* 101 */ "CFC1\000"
8005 /* 106 */ "DMFC1\000"
8006 /* 112 */ "MFTHC1\000"
8007 /* 119 */ "MTTHC1\000"
8008 /* 126 */ "CTC1\000"
8009 /* 131 */ "CFTC1\000"
8010 /* 137 */ "MFTC1\000"
8011 /* 143 */ "DMTC1\000"
8012 /* 149 */ "CTTC1\000"
8013 /* 155 */ "MTTC1\000"
8014 /* 161 */ "LWC1\000"
8015 /* 166 */ "SWC1\000"
8016 /* 171 */ "LDXC1\000"
8017 /* 177 */ "SDXC1\000"
8018 /* 183 */ "LUXC1\000"
8019 /* 189 */ "SUXC1\000"
8020 /* 195 */ "LWXC1\000"
8021 /* 201 */ "SWXC1\000"
8022 /* 207 */ "MTM1\000"
8023 /* 212 */ "SDC1_M1\000"
8024 /* 220 */ "MTP1\000"
8025 /* 225 */ "BBIT1\000"
8026 /* 231 */ "BBIT032\000"
8027 /* 239 */ "BBIT132\000"
8028 /* 247 */ "DSRA32\000"
8029 /* 254 */ "MFHC1_D32\000"
8030 /* 264 */ "MTHC1_D32\000"
8031 /* 274 */ "FSUB_D32\000"
8032 /* 283 */ "NMSUB_D32\000"
8033 /* 293 */ "FADD_D32\000"
8034 /* 302 */ "NMADD_D32\000"
8035 /* 312 */ "C_NGE_D32\000"
8036 /* 322 */ "C_NGLE_D32\000"
8037 /* 333 */ "C_OLE_D32\000"
8038 /* 343 */ "C_ULE_D32\000"
8039 /* 353 */ "C_LE_D32\000"
8040 /* 362 */ "C_SF_D32\000"
8041 /* 371 */ "MOVF_D32\000"
8042 /* 380 */ "C_F_D32\000"
8043 /* 388 */ "PseudoSELECTFP_F_D32\000"
8044 /* 409 */ "FNEG_D32\000"
8045 /* 418 */ "MOVN_I_D32\000"
8046 /* 429 */ "MOVZ_I_D32\000"
8047 /* 440 */ "C_NGL_D32\000"
8048 /* 450 */ "FMUL_D32\000"
8049 /* 459 */ "LDC1_MM_D32\000"
8050 /* 471 */ "SDC1_MM_D32\000"
8051 /* 483 */ "C_UN_D32\000"
8052 /* 492 */ "RECIP_D32\000"
8053 /* 502 */ "FCMP_D32\000"
8054 /* 511 */ "C_SEQ_D32\000"
8055 /* 521 */ "C_UEQ_D32\000"
8056 /* 531 */ "C_EQ_D32\000"
8057 /* 540 */ "FABS_D32\000"
8058 /* 549 */ "CVT_S_D32\000"
8059 /* 559 */ "PseudoSELECT_D32\000"
8060 /* 576 */ "C_NGT_D32\000"
8061 /* 586 */ "C_OLT_D32\000"
8062 /* 596 */ "C_ULT_D32\000"
8063 /* 606 */ "C_LT_D32\000"
8064 /* 615 */ "FSQRT_D32\000"
8065 /* 625 */ "RSQRT_D32\000"
8066 /* 635 */ "MOVT_D32\000"
8067 /* 644 */ "PseudoSELECTFP_T_D32\000"
8068 /* 665 */ "FDIV_D32\000"
8069 /* 674 */ "FMOV_D32\000"
8070 /* 683 */ "PseudoTRUNC_W_D32\000"
8071 /* 701 */ "ROUND_W_D32\000"
8072 /* 713 */ "CEIL_W_D32\000"
8073 /* 724 */ "FLOOR_W_D32\000"
8074 /* 736 */ "CVT_W_D32\000"
8075 /* 746 */ "BPOSGE32\000"
8076 /* 755 */ "ATOMIC_LOAD_SUB_I32\000"
8077 /* 775 */ "ATOMIC_LOAD_ADD_I32\000"
8078 /* 795 */ "ATOMIC_LOAD_NAND_I32\000"
8079 /* 816 */ "ATOMIC_LOAD_AND_I32\000"
8080 /* 836 */ "ATOMIC_LOAD_UMIN_I32\000"
8081 /* 857 */ "ATOMIC_LOAD_MIN_I32\000"
8082 /* 877 */ "ATOMIC_SWAP_I32\000"
8083 /* 893 */ "ATOMIC_CMP_SWAP_I32\000"
8084 /* 913 */ "ATOMIC_LOAD_XOR_I32\000"
8085 /* 933 */ "ATOMIC_LOAD_OR_I32\000"
8086 /* 952 */ "ATOMIC_LOAD_UMAX_I32\000"
8087 /* 973 */ "ATOMIC_LOAD_MAX_I32\000"
8088 /* 993 */ "DSLL32\000"
8089 /* 1000 */ "DSRL32\000"
8090 /* 1007 */ "DROTR32\000"
8091 /* 1015 */ "CINS32\000"
8092 /* 1022 */ "EXTS32\000"
8093 /* 1029 */ "FCMP_S32\000"
8094 /* 1038 */ "DSLL64_32\000"
8095 /* 1048 */ "CINS64_32\000"
8096 /* 1058 */ "DEXT64_32\000"
8097 /* 1068 */ "LoadImmDoubleFGR_32\000"
8098 /* 1088 */ "LoadAddrReg32\000"
8099 /* 1102 */ "CINS_i32\000"
8100 /* 1111 */ "LoadImm32\000"
8101 /* 1121 */ "LoadAddrImm32\000"
8102 /* 1135 */ "MIPSeh_return32\000"
8103 /* 1151 */ "LwConstant32\000"
8104 /* 1164 */ "LDC2\000"
8105 /* 1169 */ "SDC2\000"
8106 /* 1174 */ "DMFC2\000"
8107 /* 1180 */ "DMTC2\000"
8108 /* 1186 */ "LWC2\000"
8109 /* 1191 */ "SWC2\000"
8110 /* 1196 */ "G_FLOG2\000"
8111 /* 1204 */ "MTM2\000"
8112 /* 1209 */ "G_FATAN2\000"
8113 /* 1218 */ "MTP2\000"
8114 /* 1223 */ "G_FEXP2\000"
8115 /* 1231 */ "SHRA_QB_MMR2\000"
8116 /* 1244 */ "CMPGDU_LE_QB_MMR2\000"
8117 /* 1262 */ "SUBUH_QB_MMR2\000"
8118 /* 1276 */ "ADDUH_QB_MMR2\000"
8119 /* 1290 */ "CMPGDU_EQ_QB_MMR2\000"
8120 /* 1308 */ "SHRA_R_QB_MMR2\000"
8121 /* 1323 */ "SUBUH_R_QB_MMR2\000"
8122 /* 1339 */ "ADDUH_R_QB_MMR2\000"
8123 /* 1355 */ "SHRAV_R_QB_MMR2\000"
8124 /* 1371 */ "ABSQ_S_QB_MMR2\000"
8125 /* 1386 */ "CMPGDU_LT_QB_MMR2\000"
8126 /* 1404 */ "SHRAV_QB_MMR2\000"
8127 /* 1418 */ "PREPEND_MMR2\000"
8128 /* 1431 */ "APPEND_MMR2\000"
8129 /* 1443 */ "PRECR_QB_PH_MMR2\000"
8130 /* 1460 */ "SUBQH_PH_MMR2\000"
8131 /* 1474 */ "ADDQH_PH_MMR2\000"
8132 /* 1488 */ "SHRL_PH_MMR2\000"
8133 /* 1501 */ "MUL_PH_MMR2\000"
8134 /* 1513 */ "SUBQH_R_PH_MMR2\000"
8135 /* 1529 */ "ADDQH_R_PH_MMR2\000"
8136 /* 1545 */ "MUL_S_PH_MMR2\000"
8137 /* 1559 */ "MULQ_S_PH_MMR2\000"
8138 /* 1574 */ "SUBU_S_PH_MMR2\000"
8139 /* 1589 */ "ADDU_S_PH_MMR2\000"
8140 /* 1604 */ "SUBU_PH_MMR2\000"
8141 /* 1617 */ "ADDU_PH_MMR2\000"
8142 /* 1630 */ "SHRLV_PH_MMR2\000"
8143 /* 1644 */ "DPA_W_PH_MMR2\000"
8144 /* 1658 */ "MULSA_W_PH_MMR2\000"
8145 /* 1674 */ "DPAQX_SA_W_PH_MMR2\000"
8146 /* 1693 */ "DPSQX_SA_W_PH_MMR2\000"
8147 /* 1712 */ "DPS_W_PH_MMR2\000"
8148 /* 1726 */ "DPAQX_S_W_PH_MMR2\000"
8149 /* 1744 */ "DPSQX_S_W_PH_MMR2\000"
8150 /* 1762 */ "DPAX_W_PH_MMR2\000"
8151 /* 1777 */ "DPSX_W_PH_MMR2\000"
8152 /* 1792 */ "BALIGN_MMR2\000"
8153 /* 1804 */ "PRECR_SRA_PH_W_MMR2\000"
8154 /* 1824 */ "PRECR_SRA_R_PH_W_MMR2\000"
8155 /* 1846 */ "SUBQH_W_MMR2\000"
8156 /* 1859 */ "ADDQH_W_MMR2\000"
8157 /* 1872 */ "SUBQH_R_W_MMR2\000"
8158 /* 1887 */ "ADDQH_R_W_MMR2\000"
8159 /* 1902 */ "MULQ_RS_W_MMR2\000"
8160 /* 1917 */ "MULQ_S_W_MMR2\000"
8161 /* 1931 */ "LDC3\000"
8162 /* 1936 */ "SDC3\000"
8163 /* 1941 */ "LWC3\000"
8164 /* 1946 */ "SWC3\000"
8165 /* 1951 */ "BPOSGE32C_MMR3\000"
8166 /* 1966 */ "LDC164\000"
8167 /* 1973 */ "SDC164\000"
8168 /* 1980 */ "LDXC164\000"
8169 /* 1988 */ "SDXC164\000"
8170 /* 1996 */ "LUXC164\000"
8171 /* 2004 */ "SUXC164\000"
8172 /* 2012 */ "SEB64\000"
8173 /* 2018 */ "TAILCALLREGHB64\000"
8174 /* 2034 */ "JR_HB64\000"
8175 /* 2042 */ "JALR_HB64\000"
8176 /* 2052 */ "LB64\000"
8177 /* 2057 */ "SB64\000"
8178 /* 2062 */ "LOAD_ACC64\000"
8179 /* 2073 */ "STORE_ACC64\000"
8180 /* 2085 */ "BGEC64\000"
8181 /* 2092 */ "BNEC64\000"
8182 /* 2099 */ "JIC64\000"
8183 /* 2105 */ "JIALC64\000"
8184 /* 2113 */ "BEQC64\000"
8185 /* 2120 */ "SC64\000"
8186 /* 2125 */ "BLTC64\000"
8187 /* 2132 */ "BGEUC64\000"
8188 /* 2140 */ "BLTUC64\000"
8189 /* 2148 */ "BGEZC64\000"
8190 /* 2156 */ "BLEZC64\000"
8191 /* 2164 */ "BNEZC64\000"
8192 /* 2172 */ "BEQZC64\000"
8193 /* 2180 */ "BGTZC64\000"
8194 /* 2188 */ "BLTZC64\000"
8195 /* 2196 */ "AND64\000"
8196 /* 2202 */ "MFC1_D64\000"
8197 /* 2211 */ "MFHC1_D64\000"
8198 /* 2221 */ "MTHC1_D64\000"
8199 /* 2231 */ "MTC1_D64\000"
8200 /* 2240 */ "MOVN_I64_D64\000"
8201 /* 2253 */ "MOVZ_I64_D64\000"
8202 /* 2266 */ "FSUB_D64\000"
8203 /* 2275 */ "NMSUB_D64\000"
8204 /* 2285 */ "FADD_D64\000"
8205 /* 2294 */ "NMADD_D64\000"
8206 /* 2304 */ "C_NGE_D64\000"
8207 /* 2314 */ "C_NGLE_D64\000"
8208 /* 2325 */ "C_OLE_D64\000"
8209 /* 2335 */ "C_ULE_D64\000"
8210 /* 2345 */ "C_LE_D64\000"
8211 /* 2354 */ "C_SF_D64\000"
8212 /* 2363 */ "MOVF_D64\000"
8213 /* 2372 */ "C_F_D64\000"
8214 /* 2380 */ "PseudoSELECTFP_F_D64\000"
8215 /* 2401 */ "FNEG_D64\000"
8216 /* 2410 */ "MOVN_I_D64\000"
8217 /* 2421 */ "MOVZ_I_D64\000"
8218 /* 2432 */ "C_NGL_D64\000"
8219 /* 2442 */ "FMUL_D64\000"
8220 /* 2451 */ "TRUNC_L_D64\000"
8221 /* 2463 */ "ROUND_L_D64\000"
8222 /* 2475 */ "CEIL_L_D64\000"
8223 /* 2486 */ "FLOOR_L_D64\000"
8224 /* 2498 */ "CVT_L_D64\000"
8225 /* 2508 */ "LDC1_MM_D64\000"
8226 /* 2520 */ "SDC1_MM_D64\000"
8227 /* 2532 */ "C_UN_D64\000"
8228 /* 2541 */ "RECIP_D64\000"
8229 /* 2551 */ "FCMP_D64\000"
8230 /* 2560 */ "C_SEQ_D64\000"
8231 /* 2570 */ "C_UEQ_D64\000"
8232 /* 2580 */ "C_EQ_D64\000"
8233 /* 2589 */ "FABS_D64\000"
8234 /* 2598 */ "CVT_S_D64\000"
8235 /* 2608 */ "PseudoSELECT_D64\000"
8236 /* 2625 */ "C_NGT_D64\000"
8237 /* 2635 */ "C_OLT_D64\000"
8238 /* 2645 */ "C_ULT_D64\000"
8239 /* 2655 */ "C_LT_D64\000"
8240 /* 2664 */ "FSQRT_D64\000"
8241 /* 2674 */ "RSQRT_D64\000"
8242 /* 2684 */ "MOVT_D64\000"
8243 /* 2693 */ "PseudoSELECTFP_T_D64\000"
8244 /* 2714 */ "FDIV_D64\000"
8245 /* 2723 */ "FMOV_D64\000"
8246 /* 2732 */ "TRUNC_W_D64\000"
8247 /* 2744 */ "ROUND_W_D64\000"
8248 /* 2756 */ "CEIL_W_D64\000"
8249 /* 2767 */ "FLOOR_W_D64\000"
8250 /* 2779 */ "CVT_W_D64\000"
8251 /* 2789 */ "BNE64\000"
8252 /* 2795 */ "BuildPairF64\000"
8253 /* 2808 */ "ExtractElementF64\000"
8254 /* 2826 */ "TAILCALLREG64\000"
8255 /* 2840 */ "SEH64\000"
8256 /* 2846 */ "LH64\000"
8257 /* 2851 */ "SH64\000"
8258 /* 2856 */ "PseudoMFHI64\000"
8259 /* 2869 */ "PseudoMTLOHI64\000"
8260 /* 2884 */ "MTHI64\000"
8261 /* 2891 */ "MOVN_I64_I64\000"
8262 /* 2904 */ "MOVZ_I64_I64\000"
8263 /* 2917 */ "ATOMIC_LOAD_SUB_I64\000"
8264 /* 2937 */ "ATOMIC_LOAD_ADD_I64\000"
8265 /* 2957 */ "ATOMIC_LOAD_NAND_I64\000"
8266 /* 2978 */ "ATOMIC_LOAD_AND_I64\000"
8267 /* 2998 */ "MOVF_I64\000"
8268 /* 3007 */ "PseudoSELECTFP_F_I64\000"
8269 /* 3028 */ "MOVN_I_I64\000"
8270 /* 3039 */ "MOVZ_I_I64\000"
8271 /* 3050 */ "ATOMIC_LOAD_UMIN_I64\000"
8272 /* 3071 */ "ATOMIC_LOAD_MIN_I64\000"
8273 /* 3091 */ "ATOMIC_SWAP_I64\000"
8274 /* 3107 */ "ATOMIC_CMP_SWAP_I64\000"
8275 /* 3127 */ "ATOMIC_LOAD_XOR_I64\000"
8276 /* 3147 */ "ATOMIC_LOAD_OR_I64\000"
8277 /* 3166 */ "PseudoD_SELECT_I64\000"
8278 /* 3185 */ "PseudoSELECT_I64\000"
8279 /* 3202 */ "MOVT_I64\000"
8280 /* 3211 */ "PseudoSELECTFP_T_I64\000"
8281 /* 3232 */ "ATOMIC_LOAD_UMAX_I64\000"
8282 /* 3253 */ "ATOMIC_LOAD_MAX_I64\000"
8283 /* 3273 */ "LL64\000"
8284 /* 3278 */ "CVT_S_PL64\000"
8285 /* 3289 */ "LWL64\000"
8286 /* 3295 */ "SWL64\000"
8287 /* 3301 */ "PseudoMFLO64\000"
8288 /* 3314 */ "MTLO64\000"
8289 /* 3321 */ "BEQ64\000"
8290 /* 3327 */ "JR64\000"
8291 /* 3332 */ "JALR64\000"
8292 /* 3339 */ "NOR64\000"
8293 /* 3345 */ "XOR64\000"
8294 /* 3351 */ "RDHWR64\000"
8295 /* 3359 */ "LWR64\000"
8296 /* 3365 */ "SWR64\000"
8297 /* 3371 */ "FSUB_PS64\000"
8298 /* 3381 */ "FADD_PS64\000"
8299 /* 3391 */ "PLL_PS64\000"
8300 /* 3400 */ "FMUL_PS64\000"
8301 /* 3410 */ "PUL_PS64\000"
8302 /* 3419 */ "ADDR_PS64\000"
8303 /* 3429 */ "MULR_PS64\000"
8304 /* 3439 */ "PLU_PS64\000"
8305 /* 3448 */ "PUU_PS64\000"
8306 /* 3457 */ "CVT_PW_PS64\000"
8307 /* 3469 */ "CVT_PS_S64\000"
8308 /* 3480 */ "SLT64\000"
8309 /* 3486 */ "CVT_S_PU64\000"
8310 /* 3497 */ "LW64\000"
8311 /* 3502 */ "CVT_PS_PW64\000"
8312 /* 3514 */ "SW64\000"
8313 /* 3519 */ "BGEZ64\000"
8314 /* 3526 */ "BLEZ64\000"
8315 /* 3533 */ "SELNEZ64\000"
8316 /* 3542 */ "SELEQZ64\000"
8317 /* 3551 */ "BGTZ64\000"
8318 /* 3558 */ "BLTZ64\000"
8319 /* 3565 */ "BuildPairF64_64\000"
8320 /* 3581 */ "ExtractElementF64_64\000"
8321 /* 3602 */ "SLL64_64\000"
8322 /* 3611 */ "LONG_BRANCH_LUi2Op_64\000"
8323 /* 3633 */ "LoadAddrReg64\000"
8324 /* 3647 */ "PseudoIndirectHazardBranch64\000"
8325 /* 3676 */ "PseudoIndirectBranch64\000"
8326 /* 3699 */ "ANDi64\000"
8327 /* 3706 */ "XORi64\000"
8328 /* 3713 */ "SLTi64\000"
8329 /* 3720 */ "LUi64\000"
8330 /* 3726 */ "SGEImm64\000"
8331 /* 3735 */ "SLEImm64\000"
8332 /* 3744 */ "NORImm64\000"
8333 /* 3753 */ "SGTImm64\000"
8334 /* 3762 */ "SLTImm64\000"
8335 /* 3771 */ "SGEUImm64\000"
8336 /* 3781 */ "SLEUImm64\000"
8337 /* 3791 */ "SGTUImm64\000"
8338 /* 3801 */ "SLTUImm64\000"
8339 /* 3811 */ "LoadImm64\000"
8340 /* 3821 */ "LoadAddrImm64\000"
8341 /* 3835 */ "PseudoReturn64\000"
8342 /* 3850 */ "MIPSeh_return64\000"
8343 /* 3866 */ "LBu64\000"
8344 /* 3872 */ "LHu64\000"
8345 /* 3878 */ "SLTu64\000"
8346 /* 3885 */ "LEA_ADDiu64\000"
8347 /* 3897 */ "SLTiu64\000"
8348 /* 3905 */ "MoveR3216\000"
8349 /* 3915 */ "RetRA16\000"
8350 /* 3923 */ "JalB16\000"
8351 /* 3930 */ "LD_F16\000"
8352 /* 3937 */ "ST_F16\000"
8353 /* 3944 */ "ATOMIC_LOAD_SUB_I16\000"
8354 /* 3964 */ "ATOMIC_LOAD_ADD_I16\000"
8355 /* 3984 */ "ATOMIC_LOAD_NAND_I16\000"
8356 /* 4005 */ "ATOMIC_LOAD_AND_I16\000"
8357 /* 4025 */ "ATOMIC_LOAD_UMIN_I16\000"
8358 /* 4046 */ "ATOMIC_LOAD_MIN_I16\000"
8359 /* 4066 */ "ATOMIC_SWAP_I16\000"
8360 /* 4082 */ "ATOMIC_CMP_SWAP_I16\000"
8361 /* 4102 */ "ATOMIC_LOAD_XOR_I16\000"
8362 /* 4122 */ "ATOMIC_LOAD_OR_I16\000"
8363 /* 4141 */ "ATOMIC_LOAD_UMAX_I16\000"
8364 /* 4162 */ "ATOMIC_LOAD_MAX_I16\000"
8365 /* 4182 */ "Move32R16\000"
8366 /* 4192 */ "SraX16\000"
8367 /* 4199 */ "RestoreX16\000"
8368 /* 4210 */ "SaveX16\000"
8369 /* 4218 */ "BtnezT8CmpiX16\000"
8370 /* 4233 */ "BteqzT8CmpiX16\000"
8371 /* 4248 */ "BtnezT8SltiX16\000"
8372 /* 4263 */ "BteqzT8SltiX16\000"
8373 /* 4278 */ "SllX16\000"
8374 /* 4285 */ "SrlX16\000"
8375 /* 4292 */ "LbRxRyOffMemX16\000"
8376 /* 4308 */ "SbRxRyOffMemX16\000"
8377 /* 4324 */ "LhRxRyOffMemX16\000"
8378 /* 4340 */ "ShRxRyOffMemX16\000"
8379 /* 4356 */ "LbuRxRyOffMemX16\000"
8380 /* 4373 */ "LhuRxRyOffMemX16\000"
8381 /* 4390 */ "AddiuRxRyOffMemX16\000"
8382 /* 4409 */ "LwRxRyOffMemX16\000"
8383 /* 4425 */ "SwRxRyOffMemX16\000"
8384 /* 4441 */ "AddiuRxPcImmX16\000"
8385 /* 4457 */ "AddiuSpImmX16\000"
8386 /* 4471 */ "LwRxSpImmX16\000"
8387 /* 4484 */ "SwRxSpImmX16\000"
8388 /* 4497 */ "SltiCCRxImmX16\000"
8389 /* 4512 */ "SltiuCCRxImmX16\000"
8390 /* 4528 */ "LiRxImmX16\000"
8391 /* 4539 */ "CmpiRxImmX16\000"
8392 /* 4552 */ "SltiRxImmX16\000"
8393 /* 4565 */ "AddiuRxImmX16\000"
8394 /* 4579 */ "SltiuRxImmX16\000"
8395 /* 4593 */ "AddiuRxRxImmX16\000"
8396 /* 4609 */ "BnezRxImmX16\000"
8397 /* 4622 */ "BeqzRxImmX16\000"
8398 /* 4635 */ "BimmX16\000"
8399 /* 4643 */ "LiRxImmAlignX16\000"
8400 /* 4659 */ "LwRxPcTcpX16\000"
8401 /* 4672 */ "BtnezT8CmpX16\000"
8402 /* 4686 */ "BteqzT8CmpX16\000"
8403 /* 4700 */ "BtnezT8SltX16\000"
8404 /* 4714 */ "BteqzT8SltX16\000"
8405 /* 4728 */ "BtnezT8SltiuX16\000"
8406 /* 4744 */ "BteqzT8SltiuX16\000"
8407 /* 4760 */ "BtnezT8SltuX16\000"
8408 /* 4775 */ "BteqzT8SltuX16\000"
8409 /* 4790 */ "BtnezX16\000"
8410 /* 4799 */ "BteqzX16\000"
8411 /* 4808 */ "JrcRa16\000"
8412 /* 4816 */ "JrRa16\000"
8413 /* 4823 */ "Restore16\000"
8414 /* 4833 */ "GotPrologue16\000"
8415 /* 4847 */ "Save16\000"
8416 /* 4854 */ "JumpLinkReg16\000"
8417 /* 4868 */ "Mfhi16\000"
8418 /* 4875 */ "Break16\000"
8419 /* 4883 */ "Jal16\000"
8420 /* 4889 */ "AddiuSpImm16\000"
8421 /* 4902 */ "LiRxImm16\000"
8422 /* 4912 */ "CmpiRxImm16\000"
8423 /* 4924 */ "SltiRxImm16\000"
8424 /* 4936 */ "SltiuRxImm16\000"
8425 /* 4949 */ "AddiuRxRxImm16\000"
8426 /* 4964 */ "BnezRxImm16\000"
8427 /* 4976 */ "BeqzRxImm16\000"
8428 /* 4988 */ "Bimm16\000"
8429 /* 4995 */ "Mflo16\000"
8430 /* 5002 */ "LwRxPcTcp16\000"
8431 /* 5014 */ "SebRx16\000"
8432 /* 5022 */ "JrcRx16\000"
8433 /* 5030 */ "SehRx16\000"
8434 /* 5038 */ "SltCCRxRy16\000"
8435 /* 5050 */ "SltuCCRxRy16\000"
8436 /* 5063 */ "NegRxRy16\000"
8437 /* 5073 */ "CmpRxRy16\000"
8438 /* 5083 */ "SltRxRy16\000"
8439 /* 5093 */ "MultRxRy16\000"
8440 /* 5104 */ "NotRxRy16\000"
8441 /* 5114 */ "SltuRxRy16\000"
8442 /* 5125 */ "MultuRxRy16\000"
8443 /* 5137 */ "DivuRxRy16\000"
8444 /* 5148 */ "SravRxRy16\000"
8445 /* 5159 */ "DivRxRy16\000"
8446 /* 5169 */ "SllvRxRy16\000"
8447 /* 5180 */ "SrlvRxRy16\000"
8448 /* 5191 */ "AndRxRxRy16\000"
8449 /* 5203 */ "OrRxRxRy16\000"
8450 /* 5214 */ "XorRxRxRy16\000"
8451 /* 5226 */ "MultRxRyRz16\000"
8452 /* 5239 */ "SubuRxRyRz16\000"
8453 /* 5252 */ "AdduRxRyRz16\000"
8454 /* 5265 */ "SltuRxRyRz16\000"
8455 /* 5278 */ "MultuRxRyRz16\000"
8456 /* 5292 */ "Btnez16\000"
8457 /* 5300 */ "Bteqz16\000"
8458 /* 5308 */ "PseudoIndrectHazardBranch64R6\000"
8459 /* 5338 */ "PseudoIndirectBranch64R6\000"
8460 /* 5363 */ "MFC0_MMR6\000"
8461 /* 5373 */ "MFHC0_MMR6\000"
8462 /* 5384 */ "MTHC0_MMR6\000"
8463 /* 5395 */ "MTC0_MMR6\000"
8464 /* 5405 */ "MFC1_MMR6\000"
8465 /* 5415 */ "MTC1_MMR6\000"
8466 /* 5425 */ "LDC2_MMR6\000"
8467 /* 5435 */ "SDC2_MMR6\000"
8468 /* 5445 */ "MFC2_MMR6\000"
8469 /* 5455 */ "MFHC2_MMR6\000"
8470 /* 5466 */ "MTHC2_MMR6\000"
8471 /* 5477 */ "MTC2_MMR6\000"
8472 /* 5487 */ "LWC2_MMR6\000"
8473 /* 5497 */ "SWC2_MMR6\000"
8474 /* 5507 */ "LDC1_D64_MMR6\000"
8475 /* 5521 */ "SDC1_D64_MMR6\000"
8476 /* 5535 */ "SB16_MMR6\000"
8477 /* 5545 */ "BC16_MMR6\000"
8478 /* 5555 */ "JRC16_MMR6\000"
8479 /* 5566 */ "JALRC16_MMR6\000"
8480 /* 5579 */ "BNEZC16_MMR6\000"
8481 /* 5592 */ "BEQZC16_MMR6\000"
8482 /* 5605 */ "AND16_MMR6\000"
8483 /* 5616 */ "MOVE16_MMR6\000"
8484 /* 5628 */ "SH16_MMR6\000"
8485 /* 5638 */ "ANDI16_MMR6\000"
8486 /* 5650 */ "LI16_MMR6\000"
8487 /* 5660 */ "BREAK16_MMR6\000"
8488 /* 5673 */ "SLL16_MMR6\000"
8489 /* 5684 */ "SRL16_MMR6\000"
8490 /* 5695 */ "LWM16_MMR6\000"
8491 /* 5706 */ "SWM16_MMR6\000"
8492 /* 5717 */ "SDBBP16_MMR6\000"
8493 /* 5730 */ "XOR16_MMR6\000"
8494 /* 5741 */ "NOT16_MMR6\000"
8495 /* 5752 */ "SUBU16_MMR6\000"
8496 /* 5764 */ "ADDU16_MMR6\000"
8497 /* 5776 */ "SW16_MMR6\000"
8498 /* 5786 */ "LSA_MMR6\000"
8499 /* 5795 */ "EHB_MMR6\000"
8500 /* 5804 */ "JALRC_HB_MMR6\000"
8501 /* 5818 */ "LB_MMR6\000"
8502 /* 5826 */ "SB_MMR6\000"
8503 /* 5834 */ "SUB_MMR6\000"
8504 /* 5843 */ "BC_MMR6\000"
8505 /* 5851 */ "BGEC_MMR6\000"
8506 /* 5861 */ "BNEC_MMR6\000"
8507 /* 5871 */ "JIC_MMR6\000"
8508 /* 5880 */ "BALC_MMR6\000"
8509 /* 5890 */ "JIALC_MMR6\000"
8510 /* 5901 */ "BGEZALC_MMR6\000"
8511 /* 5914 */ "BLEZALC_MMR6\000"
8512 /* 5927 */ "BNEZALC_MMR6\000"
8513 /* 5940 */ "BEQZALC_MMR6\000"
8514 /* 5953 */ "BGTZALC_MMR6\000"
8515 /* 5966 */ "BLTZALC_MMR6\000"
8516 /* 5979 */ "ERETNC_MMR6\000"
8517 /* 5991 */ "SYNC_MMR6\000"
8518 /* 6001 */ "AUIPC_MMR6\000"
8519 /* 6012 */ "ALUIPC_MMR6\000"
8520 /* 6024 */ "ADDIUPC_MMR6\000"
8521 /* 6037 */ "LWPC_MMR6\000"
8522 /* 6047 */ "BEQC_MMR6\000"
8523 /* 6057 */ "JALRC_MMR6\000"
8524 /* 6068 */ "SC_MMR6\000"
8525 /* 6076 */ "BLTC_MMR6\000"
8526 /* 6086 */ "BGEUC_MMR6\000"
8527 /* 6097 */ "BLTUC_MMR6\000"
8528 /* 6108 */ "BNVC_MMR6\000"
8529 /* 6118 */ "BOVC_MMR6\000"
8530 /* 6128 */ "BGEZC_MMR6\000"
8531 /* 6139 */ "BLEZC_MMR6\000"
8532 /* 6150 */ "BC1NEZC_MMR6\000"
8533 /* 6163 */ "BC2NEZC_MMR6\000"
8534 /* 6176 */ "BNEZC_MMR6\000"
8535 /* 6187 */ "BC1EQZC_MMR6\000"
8536 /* 6200 */ "BC2EQZC_MMR6\000"
8537 /* 6213 */ "BEQZC_MMR6\000"
8538 /* 6224 */ "BGTZC_MMR6\000"
8539 /* 6235 */ "BLTZC_MMR6\000"
8540 /* 6246 */ "ADD_MMR6\000"
8541 /* 6255 */ "AND_MMR6\000"
8542 /* 6264 */ "MOD_MMR6\000"
8543 /* 6273 */ "MINA_D_MMR6\000"
8544 /* 6285 */ "MAXA_D_MMR6\000"
8545 /* 6297 */ "CMP_SLE_D_MMR6\000"
8546 /* 6312 */ "CMP_SULE_D_MMR6\000"
8547 /* 6328 */ "CMP_ULE_D_MMR6\000"
8548 /* 6343 */ "CMP_LE_D_MMR6\000"
8549 /* 6357 */ "CMP_SAF_D_MMR6\000"
8550 /* 6372 */ "CMP_AF_D_MMR6\000"
8551 /* 6386 */ "MSUBF_D_MMR6\000"
8552 /* 6399 */ "MADDF_D_MMR6\000"
8553 /* 6412 */ "SEL_D_MMR6\000"
8554 /* 6423 */ "TRUNC_L_D_MMR6\000"
8555 /* 6438 */ "ROUND_L_D_MMR6\000"
8556 /* 6453 */ "CEIL_L_D_MMR6\000"
8557 /* 6467 */ "FLOOR_L_D_MMR6\000"
8558 /* 6482 */ "CVT_L_D_MMR6\000"
8559 /* 6495 */ "MIN_D_MMR6\000"
8560 /* 6506 */ "CMP_SUN_D_MMR6\000"
8561 /* 6521 */ "CMP_UN_D_MMR6\000"
8562 /* 6535 */ "CMP_SEQ_D_MMR6\000"
8563 /* 6550 */ "CMP_SUEQ_D_MMR6\000"
8564 /* 6566 */ "CMP_UEQ_D_MMR6\000"
8565 /* 6581 */ "CMP_EQ_D_MMR6\000"
8566 /* 6595 */ "CLASS_D_MMR6\000"
8567 /* 6608 */ "CMP_SLT_D_MMR6\000"
8568 /* 6623 */ "CMP_SULT_D_MMR6\000"
8569 /* 6639 */ "CMP_ULT_D_MMR6\000"
8570 /* 6654 */ "CMP_LT_D_MMR6\000"
8571 /* 6668 */ "RINT_D_MMR6\000"
8572 /* 6680 */ "FMOV_D_MMR6\000"
8573 /* 6692 */ "TRUNC_W_D_MMR6\000"
8574 /* 6707 */ "ROUND_W_D_MMR6\000"
8575 /* 6722 */ "CEIL_W_D_MMR6\000"
8576 /* 6736 */ "FLOOR_W_D_MMR6\000"
8577 /* 6751 */ "MAX_D_MMR6\000"
8578 /* 6762 */ "SELNEZ_D_MMR6\000"
8579 /* 6776 */ "SELEQZ_D_MMR6\000"
8580 /* 6790 */ "CACHE_MMR6\000"
8581 /* 6801 */ "SIGRIE_MMR6\000"
8582 /* 6813 */ "PAUSE_MMR6\000"
8583 /* 6824 */ "PREF_MMR6\000"
8584 /* 6834 */ "TLBINVF_MMR6\000"
8585 /* 6847 */ "TAILCALLREG_MMR6\000"
8586 /* 6864 */ "WSBH_MMR6\000"
8587 /* 6874 */ "SH_MMR6\000"
8588 /* 6882 */ "MUH_MMR6\000"
8589 /* 6891 */ "SYNCI_MMR6\000"
8590 /* 6902 */ "ANDI_MMR6\000"
8591 /* 6912 */ "EI_MMR6\000"
8592 /* 6920 */ "XORI_MMR6\000"
8593 /* 6930 */ "AUI_MMR6\000"
8594 /* 6939 */ "LUI_MMR6\000"
8595 /* 6948 */ "GINVI_MMR6\000"
8596 /* 6959 */ "BREAK_MMR6\000"
8597 /* 6970 */ "JAL_MMR6\000"
8598 /* 6979 */ "TAILCALL_MMR6\000"
8599 /* 6993 */ "SLL_MMR6\000"
8600 /* 7002 */ "MUL_MMR6\000"
8601 /* 7011 */ "CVT_D_L_MMR6\000"
8602 /* 7024 */ "CVT_S_L_MMR6\000"
8603 /* 7037 */ "ALIGN_MMR6\000"
8604 /* 7048 */ "CLO_MMR6\000"
8605 /* 7057 */ "BITSWAP_MMR6\000"
8606 /* 7070 */ "SDBBP_MMR6\000"
8607 /* 7081 */ "MOVEP_MMR6\000"
8608 /* 7092 */ "SSNOP_MMR6\000"
8609 /* 7103 */ "JRCADDIUSP_MMR6\000"
8610 /* 7119 */ "SWSP_MMR6\000"
8611 /* 7129 */ "DVP_MMR6\000"
8612 /* 7138 */ "EVP_MMR6\000"
8613 /* 7147 */ "NOR_MMR6\000"
8614 /* 7156 */ "XOR_MMR6\000"
8615 /* 7165 */ "RDPGPR_MMR6\000"
8616 /* 7177 */ "WRPGPR_MMR6\000"
8617 /* 7189 */ "RDHWR_MMR6\000"
8618 /* 7200 */ "INS_MMR6\000"
8619 /* 7209 */ "MINA_S_MMR6\000"
8620 /* 7221 */ "MAXA_S_MMR6\000"
8621 /* 7233 */ "FSUB_S_MMR6\000"
8622 /* 7245 */ "FADD_S_MMR6\000"
8623 /* 7257 */ "CMP_SLE_S_MMR6\000"
8624 /* 7272 */ "CMP_SULE_S_MMR6\000"
8625 /* 7288 */ "CMP_ULE_S_MMR6\000"
8626 /* 7303 */ "CMP_LE_S_MMR6\000"
8627 /* 7317 */ "CMP_SAF_S_MMR6\000"
8628 /* 7332 */ "CMP_AF_S_MMR6\000"
8629 /* 7346 */ "MSUBF_S_MMR6\000"
8630 /* 7359 */ "MADDF_S_MMR6\000"
8631 /* 7372 */ "FNEG_S_MMR6\000"
8632 /* 7384 */ "SEL_S_MMR6\000"
8633 /* 7395 */ "FMUL_S_MMR6\000"
8634 /* 7407 */ "TRUNC_L_S_MMR6\000"
8635 /* 7422 */ "ROUND_L_S_MMR6\000"
8636 /* 7437 */ "CEIL_L_S_MMR6\000"
8637 /* 7451 */ "FLOOR_L_S_MMR6\000"
8638 /* 7466 */ "CVT_L_S_MMR6\000"
8639 /* 7479 */ "MIN_S_MMR6\000"
8640 /* 7490 */ "CMP_SUN_S_MMR6\000"
8641 /* 7505 */ "CMP_UN_S_MMR6\000"
8642 /* 7519 */ "CMP_SEQ_S_MMR6\000"
8643 /* 7534 */ "CMP_SUEQ_S_MMR6\000"
8644 /* 7550 */ "CMP_UEQ_S_MMR6\000"
8645 /* 7565 */ "CMP_EQ_S_MMR6\000"
8646 /* 7579 */ "CLASS_S_MMR6\000"
8647 /* 7592 */ "CMP_SLT_S_MMR6\000"
8648 /* 7607 */ "CMP_SULT_S_MMR6\000"
8649 /* 7623 */ "CMP_ULT_S_MMR6\000"
8650 /* 7638 */ "CMP_LT_S_MMR6\000"
8651 /* 7652 */ "RINT_S_MMR6\000"
8652 /* 7664 */ "FDIV_S_MMR6\000"
8653 /* 7676 */ "FMOV_S_MMR6\000"
8654 /* 7688 */ "TRUNC_W_S_MMR6\000"
8655 /* 7703 */ "ROUND_W_S_MMR6\000"
8656 /* 7718 */ "CEIL_W_S_MMR6\000"
8657 /* 7732 */ "FLOOR_W_S_MMR6\000"
8658 /* 7747 */ "CVT_W_S_MMR6\000"
8659 /* 7760 */ "MAX_S_MMR6\000"
8660 /* 7771 */ "SELNEZ_S_MMR6\000"
8661 /* 7785 */ "SELEQZ_S_MMR6\000"
8662 /* 7799 */ "DERET_MMR6\000"
8663 /* 7810 */ "WAIT_MMR6\000"
8664 /* 7820 */ "GINVT_MMR6\000"
8665 /* 7831 */ "EXT_MMR6\000"
8666 /* 7840 */ "LBU_MMR6\000"
8667 /* 7849 */ "SUBU_MMR6\000"
8668 /* 7859 */ "ADDU_MMR6\000"
8669 /* 7869 */ "MODU_MMR6\000"
8670 /* 7879 */ "MUHU_MMR6\000"
8671 /* 7889 */ "ADDIU_MMR6\000"
8672 /* 7900 */ "MULU_MMR6\000"
8673 /* 7910 */ "DIVU_MMR6\000"
8674 /* 7920 */ "DIV_MMR6\000"
8675 /* 7929 */ "TLBINV_MMR6\000"
8676 /* 7941 */ "LW_MMR6\000"
8677 /* 7949 */ "SW_MMR6\000"
8678 /* 7957 */ "CVT_S_W_MMR6\000"
8679 /* 7970 */ "SELNEZ_MMR6\000"
8680 /* 7982 */ "CLZ_MMR6\000"
8681 /* 7991 */ "SELEQZ_MMR6\000"
8682 /* 8003 */ "PseudoIndirectBranch_MMR6\000"
8683 /* 8029 */ "LDC2_R6\000"
8684 /* 8037 */ "SDC2_R6\000"
8685 /* 8045 */ "LWC2_R6\000"
8686 /* 8053 */ "SWC2_R6\000"
8687 /* 8061 */ "JR_HB64_R6\000"
8688 /* 8072 */ "SC64_R6\000"
8689 /* 8080 */ "LL64_R6\000"
8690 /* 8088 */ "DLSA_R6\000"
8691 /* 8096 */ "JR_HB_R6\000"
8692 /* 8105 */ "SC_R6\000"
8693 /* 8111 */ "SCD_R6\000"
8694 /* 8118 */ "LLD_R6\000"
8695 /* 8125 */ "CACHE_R6\000"
8696 /* 8134 */ "PREF_R6\000"
8697 /* 8142 */ "LL_R6\000"
8698 /* 8148 */ "DMUL_R6\000"
8699 /* 8156 */ "DCLO_R6\000"
8700 /* 8164 */ "SDBBP_R6\000"
8701 /* 8173 */ "DCLZ_R6\000"
8702 /* 8181 */ "PseudoIndrectHazardBranchR6\000"
8703 /* 8209 */ "PseudoIndirectBranchR6\000"
8704 /* 8232 */ "LOAD_ACC128\000"
8705 /* 8244 */ "STORE_ACC128\000"
8706 /* 8257 */ "ATOMIC_LOAD_SUB_I8\000"
8707 /* 8276 */ "ATOMIC_LOAD_ADD_I8\000"
8708 /* 8295 */ "ATOMIC_LOAD_NAND_I8\000"
8709 /* 8315 */ "ATOMIC_LOAD_AND_I8\000"
8710 /* 8334 */ "ATOMIC_LOAD_UMIN_I8\000"
8711 /* 8354 */ "ATOMIC_LOAD_MIN_I8\000"
8712 /* 8373 */ "ATOMIC_SWAP_I8\000"
8713 /* 8388 */ "ATOMIC_CMP_SWAP_I8\000"
8714 /* 8407 */ "ATOMIC_LOAD_XOR_I8\000"
8715 /* 8426 */ "ATOMIC_LOAD_OR_I8\000"
8716 /* 8444 */ "ATOMIC_LOAD_UMAX_I8\000"
8717 /* 8464 */ "ATOMIC_LOAD_MAX_I8\000"
8718 /* 8483 */ "SAA\000"
8719 /* 8487 */ "PRECEU_PH_QBLA\000"
8720 /* 8502 */ "PRECEQU_PH_QBLA\000"
8721 /* 8518 */ "G_FMA\000"
8722 /* 8524 */ "G_STRICT_FMA\000"
8723 /* 8537 */ "PRECEU_PH_QBRA\000"
8724 /* 8552 */ "PRECEQU_PH_QBRA\000"
8725 /* 8568 */ "DSRA\000"
8726 /* 8573 */ "ATOMIC_LOAD_SUB_I32_POSTRA\000"
8727 /* 8600 */ "ATOMIC_LOAD_ADD_I32_POSTRA\000"
8728 /* 8627 */ "ATOMIC_LOAD_NAND_I32_POSTRA\000"
8729 /* 8655 */ "ATOMIC_LOAD_AND_I32_POSTRA\000"
8730 /* 8682 */ "ATOMIC_LOAD_UMIN_I32_POSTRA\000"
8731 /* 8710 */ "ATOMIC_LOAD_MIN_I32_POSTRA\000"
8732 /* 8737 */ "ATOMIC_SWAP_I32_POSTRA\000"
8733 /* 8760 */ "ATOMIC_CMP_SWAP_I32_POSTRA\000"
8734 /* 8787 */ "ATOMIC_LOAD_XOR_I32_POSTRA\000"
8735 /* 8814 */ "ATOMIC_LOAD_OR_I32_POSTRA\000"
8736 /* 8840 */ "ATOMIC_LOAD_UMAX_I32_POSTRA\000"
8737 /* 8868 */ "ATOMIC_LOAD_MAX_I32_POSTRA\000"
8738 /* 8895 */ "ATOMIC_LOAD_SUB_I64_POSTRA\000"
8739 /* 8922 */ "ATOMIC_LOAD_ADD_I64_POSTRA\000"
8740 /* 8949 */ "ATOMIC_LOAD_NAND_I64_POSTRA\000"
8741 /* 8977 */ "ATOMIC_LOAD_AND_I64_POSTRA\000"
8742 /* 9004 */ "ATOMIC_LOAD_UMIN_I64_POSTRA\000"
8743 /* 9032 */ "ATOMIC_LOAD_MIN_I64_POSTRA\000"
8744 /* 9059 */ "ATOMIC_SWAP_I64_POSTRA\000"
8745 /* 9082 */ "ATOMIC_CMP_SWAP_I64_POSTRA\000"
8746 /* 9109 */ "ATOMIC_LOAD_XOR_I64_POSTRA\000"
8747 /* 9136 */ "ATOMIC_LOAD_OR_I64_POSTRA\000"
8748 /* 9162 */ "ATOMIC_LOAD_UMAX_I64_POSTRA\000"
8749 /* 9190 */ "ATOMIC_LOAD_MAX_I64_POSTRA\000"
8750 /* 9217 */ "ATOMIC_LOAD_SUB_I16_POSTRA\000"
8751 /* 9244 */ "ATOMIC_LOAD_ADD_I16_POSTRA\000"
8752 /* 9271 */ "ATOMIC_LOAD_NAND_I16_POSTRA\000"
8753 /* 9299 */ "ATOMIC_LOAD_AND_I16_POSTRA\000"
8754 /* 9326 */ "ATOMIC_LOAD_UMIN_I16_POSTRA\000"
8755 /* 9354 */ "ATOMIC_LOAD_MIN_I16_POSTRA\000"
8756 /* 9381 */ "ATOMIC_SWAP_I16_POSTRA\000"
8757 /* 9404 */ "ATOMIC_CMP_SWAP_I16_POSTRA\000"
8758 /* 9431 */ "ATOMIC_LOAD_XOR_I16_POSTRA\000"
8759 /* 9458 */ "ATOMIC_LOAD_OR_I16_POSTRA\000"
8760 /* 9484 */ "ATOMIC_LOAD_UMAX_I16_POSTRA\000"
8761 /* 9512 */ "ATOMIC_LOAD_MAX_I16_POSTRA\000"
8762 /* 9539 */ "ATOMIC_LOAD_SUB_I8_POSTRA\000"
8763 /* 9565 */ "ATOMIC_LOAD_ADD_I8_POSTRA\000"
8764 /* 9591 */ "ATOMIC_LOAD_NAND_I8_POSTRA\000"
8765 /* 9618 */ "ATOMIC_LOAD_AND_I8_POSTRA\000"
8766 /* 9644 */ "ATOMIC_LOAD_UMIN_I8_POSTRA\000"
8767 /* 9671 */ "ATOMIC_LOAD_MIN_I8_POSTRA\000"
8768 /* 9697 */ "ATOMIC_SWAP_I8_POSTRA\000"
8769 /* 9719 */ "ATOMIC_CMP_SWAP_I8_POSTRA\000"
8770 /* 9745 */ "ATOMIC_LOAD_XOR_I8_POSTRA\000"
8771 /* 9771 */ "ATOMIC_LOAD_OR_I8_POSTRA\000"
8772 /* 9796 */ "ATOMIC_LOAD_UMAX_I8_POSTRA\000"
8773 /* 9823 */ "ATOMIC_LOAD_MAX_I8_POSTRA\000"
8774 /* 9849 */ "RetRA\000"
8775 /* 9855 */ "DLSA\000"
8776 /* 9860 */ "CFCMSA\000"
8777 /* 9867 */ "CTCMSA\000"
8778 /* 9874 */ "CRC32B\000"
8779 /* 9881 */ "CRC32CB\000"
8780 /* 9889 */ "SEB\000"
8781 /* 9893 */ "EHB\000"
8782 /* 9897 */ "TAILCALLREGHB\000"
8783 /* 9911 */ "JR_HB\000"
8784 /* 9917 */ "JALR_HB\000"
8785 /* 9925 */ "LB\000"
8786 /* 9928 */ "SHRA_QB\000"
8787 /* 9936 */ "CMPGDU_LE_QB\000"
8788 /* 9949 */ "CMPGU_LE_QB\000"
8789 /* 9961 */ "PseudoCMPU_LE_QB\000"
8790 /* 9978 */ "SUBUH_QB\000"
8791 /* 9987 */ "ADDUH_QB\000"
8792 /* 9996 */ "PseudoPICK_QB\000"
8793 /* 10010 */ "SHLL_QB\000"
8794 /* 10018 */ "REPL_QB\000"
8795 /* 10026 */ "SHRL_QB\000"
8796 /* 10034 */ "CMPGDU_EQ_QB\000"
8797 /* 10047 */ "CMPGU_EQ_QB\000"
8798 /* 10059 */ "PseudoCMPU_EQ_QB\000"
8799 /* 10076 */ "SHRA_R_QB\000"
8800 /* 10086 */ "SUBUH_R_QB\000"
8801 /* 10097 */ "ADDUH_R_QB\000"
8802 /* 10108 */ "SHRAV_R_QB\000"
8803 /* 10119 */ "ABSQ_S_QB\000"
8804 /* 10129 */ "SUBU_S_QB\000"
8805 /* 10139 */ "ADDU_S_QB\000"
8806 /* 10149 */ "CMPGDU_LT_QB\000"
8807 /* 10162 */ "CMPGU_LT_QB\000"
8808 /* 10174 */ "PseudoCMPU_LT_QB\000"
8809 /* 10191 */ "SUBU_QB\000"
8810 /* 10199 */ "ADDU_QB\000"
8811 /* 10207 */ "SHRAV_QB\000"
8812 /* 10216 */ "SHLLV_QB\000"
8813 /* 10225 */ "REPLV_QB\000"
8814 /* 10234 */ "SHRLV_QB\000"
8815 /* 10243 */ "RADDU_W_QB\000"
8816 /* 10254 */ "SB\000"
8817 /* 10257 */ "MODSUB\000"
8818 /* 10264 */ "G_FSUB\000"
8819 /* 10271 */ "G_STRICT_FSUB\000"
8820 /* 10285 */ "G_ATOMICRMW_FSUB\000"
8821 /* 10302 */ "PseudoMSUB\000"
8822 /* 10313 */ "G_SUB\000"
8823 /* 10319 */ "G_ATOMICRMW_SUB\000"
8824 /* 10335 */ "SRA_B\000"
8825 /* 10341 */ "ADD_A_B\000"
8826 /* 10349 */ "MIN_A_B\000"
8827 /* 10357 */ "ADDS_A_B\000"
8828 /* 10366 */ "MAX_A_B\000"
8829 /* 10374 */ "NLOC_B\000"
8830 /* 10381 */ "NLZC_B\000"
8831 /* 10388 */ "SLD_B\000"
8832 /* 10394 */ "PCKOD_B\000"
8833 /* 10402 */ "ILVOD_B\000"
8834 /* 10410 */ "INSVE_B\000"
8835 /* 10418 */ "VSHF_B\000"
8836 /* 10425 */ "BNEG_B\000"
8837 /* 10432 */ "SRAI_B\000"
8838 /* 10439 */ "SLDI_B\000"
8839 /* 10446 */ "ANDI_B\000"
8840 /* 10453 */ "BNEGI_B\000"
8841 /* 10461 */ "BSELI_B\000"
8842 /* 10469 */ "SLLI_B\000"
8843 /* 10476 */ "SRLI_B\000"
8844 /* 10483 */ "BINSLI_B\000"
8845 /* 10492 */ "CEQI_B\000"
8846 /* 10499 */ "SRARI_B\000"
8847 /* 10507 */ "BCLRI_B\000"
8848 /* 10515 */ "SRLRI_B\000"
8849 /* 10523 */ "NORI_B\000"
8850 /* 10530 */ "XORI_B\000"
8851 /* 10537 */ "BINSRI_B\000"
8852 /* 10546 */ "SPLATI_B\000"
8853 /* 10555 */ "BSETI_B\000"
8854 /* 10563 */ "SUBVI_B\000"
8855 /* 10571 */ "ADDVI_B\000"
8856 /* 10579 */ "BMZI_B\000"
8857 /* 10586 */ "BMNZI_B\000"
8858 /* 10594 */ "FILL_B\000"
8859 /* 10601 */ "SLL_B\000"
8860 /* 10607 */ "SRL_B\000"
8861 /* 10613 */ "BINSL_B\000"
8862 /* 10621 */ "ILVL_B\000"
8863 /* 10628 */ "CEQ_B\000"
8864 /* 10634 */ "SRAR_B\000"
8865 /* 10641 */ "BCLR_B\000"
8866 /* 10648 */ "SRLR_B\000"
8867 /* 10655 */ "BINSR_B\000"
8868 /* 10663 */ "ILVR_B\000"
8869 /* 10670 */ "ASUB_S_B\000"
8870 /* 10679 */ "MOD_S_B\000"
8871 /* 10687 */ "CLE_S_B\000"
8872 /* 10695 */ "AVE_S_B\000"
8873 /* 10703 */ "CLEI_S_B\000"
8874 /* 10712 */ "MINI_S_B\000"
8875 /* 10721 */ "CLTI_S_B\000"
8876 /* 10730 */ "MAXI_S_B\000"
8877 /* 10739 */ "MIN_S_B\000"
8878 /* 10747 */ "AVER_S_B\000"
8879 /* 10756 */ "SUBS_S_B\000"
8880 /* 10765 */ "ADDS_S_B\000"
8881 /* 10774 */ "SAT_S_B\000"
8882 /* 10782 */ "CLT_S_B\000"
8883 /* 10790 */ "SUBSUU_S_B\000"
8884 /* 10801 */ "DIV_S_B\000"
8885 /* 10809 */ "MAX_S_B\000"
8886 /* 10817 */ "COPY_S_B\000"
8887 /* 10826 */ "SPLAT_B\000"
8888 /* 10834 */ "BSET_B\000"
8889 /* 10841 */ "PCNT_B\000"
8890 /* 10848 */ "INSERT_B\000"
8891 /* 10857 */ "ST_B\000"
8892 /* 10862 */ "ASUB_U_B\000"
8893 /* 10871 */ "MOD_U_B\000"
8894 /* 10879 */ "CLE_U_B\000"
8895 /* 10887 */ "AVE_U_B\000"
8896 /* 10895 */ "CLEI_U_B\000"
8897 /* 10904 */ "MINI_U_B\000"
8898 /* 10913 */ "CLTI_U_B\000"
8899 /* 10922 */ "MAXI_U_B\000"
8900 /* 10931 */ "MIN_U_B\000"
8901 /* 10939 */ "AVER_U_B\000"
8902 /* 10948 */ "SUBS_U_B\000"
8903 /* 10957 */ "ADDS_U_B\000"
8904 /* 10966 */ "SUBSUS_U_B\000"
8905 /* 10977 */ "SAT_U_B\000"
8906 /* 10985 */ "CLT_U_B\000"
8907 /* 10993 */ "DIV_U_B\000"
8908 /* 11001 */ "MAX_U_B\000"
8909 /* 11009 */ "COPY_U_B\000"
8910 /* 11018 */ "MSUBV_B\000"
8911 /* 11026 */ "MADDV_B\000"
8912 /* 11034 */ "PCKEV_B\000"
8913 /* 11042 */ "ILVEV_B\000"
8914 /* 11050 */ "MULV_B\000"
8915 /* 11057 */ "BZ_B\000"
8916 /* 11062 */ "BNZ_B\000"
8917 /* 11068 */ "BC\000"
8918 /* 11071 */ "BGEC\000"
8919 /* 11076 */ "BNEC\000"
8920 /* 11081 */ "JIC\000"
8921 /* 11085 */ "G_INTRINSIC\000"
8922 /* 11097 */ "BALC\000"
8923 /* 11102 */ "JIALC\000"
8924 /* 11108 */ "BGEZALC\000"
8925 /* 11116 */ "BLEZALC\000"
8926 /* 11124 */ "BNEZALC\000"
8927 /* 11132 */ "BEQZALC\000"
8928 /* 11140 */ "BGTZALC\000"
8929 /* 11148 */ "BLTZALC\000"
8930 /* 11156 */ "ERETNC\000"
8931 /* 11163 */ "G_FPTRUNC\000"
8932 /* 11173 */ "G_INTRINSIC_TRUNC\000"
8933 /* 11191 */ "G_TRUNC\000"
8934 /* 11199 */ "G_BUILD_VECTOR_TRUNC\000"
8935 /* 11220 */ "SYNC\000"
8936 /* 11225 */ "G_DYN_STACKALLOC\000"
8937 /* 11242 */ "LDPC\000"
8938 /* 11247 */ "AUIPC\000"
8939 /* 11253 */ "ALUIPC\000"
8940 /* 11260 */ "ADDIUPC\000"
8941 /* 11268 */ "LWUPC\000"
8942 /* 11274 */ "LWPC\000"
8943 /* 11279 */ "BEQC\000"
8944 /* 11284 */ "ADDSC\000"
8945 /* 11290 */ "BLTC\000"
8946 /* 11295 */ "BGEUC\000"
8947 /* 11301 */ "BLTUC\000"
8948 /* 11307 */ "BNVC\000"
8949 /* 11312 */ "BOVC\000"
8950 /* 11317 */ "ADDWC\000"
8951 /* 11323 */ "BGEZC\000"
8952 /* 11329 */ "BLEZC\000"
8953 /* 11335 */ "BNEZC\000"
8954 /* 11341 */ "BEQZC\000"
8955 /* 11347 */ "BGTZC\000"
8956 /* 11353 */ "BLTZC\000"
8957 /* 11359 */ "CRC32D\000"
8958 /* 11366 */ "SAAD\000"
8959 /* 11371 */ "G_FMAD\000"
8960 /* 11378 */ "G_INDEXED_SEXTLOAD\000"
8961 /* 11397 */ "G_SEXTLOAD\000"
8962 /* 11408 */ "G_INDEXED_ZEXTLOAD\000"
8963 /* 11427 */ "G_ZEXTLOAD\000"
8964 /* 11438 */ "G_INDEXED_LOAD\000"
8965 /* 11453 */ "G_LOAD\000"
8966 /* 11460 */ "CRC32CD\000"
8967 /* 11468 */ "SCD\000"
8968 /* 11472 */ "DADD\000"
8969 /* 11477 */ "G_VECREDUCE_FADD\000"
8970 /* 11494 */ "G_FADD\000"
8971 /* 11501 */ "G_VECREDUCE_SEQ_FADD\000"
8972 /* 11522 */ "G_STRICT_FADD\000"
8973 /* 11536 */ "G_ATOMICRMW_FADD\000"
8974 /* 11553 */ "PseudoMADD\000"
8975 /* 11564 */ "G_VECREDUCE_ADD\000"
8976 /* 11580 */ "G_ADD\000"
8977 /* 11586 */ "G_PTR_ADD\000"
8978 /* 11596 */ "G_ATOMICRMW_ADD\000"
8979 /* 11612 */ "DSHD\000"
8980 /* 11617 */ "YIELD\000"
8981 /* 11623 */ "LLD\000"
8982 /* 11627 */ "G_ATOMICRMW_NAND\000"
8983 /* 11644 */ "G_VECREDUCE_AND\000"
8984 /* 11660 */ "G_AND\000"
8985 /* 11666 */ "G_ATOMICRMW_AND\000"
8986 /* 11682 */ "PREPEND\000"
8987 /* 11690 */ "APPEND\000"
8988 /* 11697 */ "LIFETIME_END\000"
8989 /* 11710 */ "G_BRCOND\000"
8990 /* 11719 */ "G_ATOMICRMW_USUB_COND\000"
8991 /* 11741 */ "G_LLROUND\000"
8992 /* 11751 */ "G_LROUND\000"
8993 /* 11760 */ "G_INTRINSIC_ROUND\000"
8994 /* 11778 */ "G_INTRINSIC_FPTRUNC_ROUND\000"
8995 /* 11804 */ "DMOD\000"
8996 /* 11809 */ "LOAD_STACK_GUARD\000"
8997 /* 11826 */ "SD\000"
8998 /* 11829 */ "FLOG2_D\000"
8999 /* 11837 */ "FEXP2_D\000"
9000 /* 11845 */ "MINA_D\000"
9001 /* 11852 */ "SRA_D\000"
9002 /* 11858 */ "MAXA_D\000"
9003 /* 11865 */ "ADD_A_D\000"
9004 /* 11873 */ "FMIN_A_D\000"
9005 /* 11882 */ "ADDS_A_D\000"
9006 /* 11891 */ "FMAX_A_D\000"
9007 /* 11900 */ "FSUB_D\000"
9008 /* 11907 */ "FMSUB_D\000"
9009 /* 11915 */ "NLOC_D\000"
9010 /* 11922 */ "NLZC_D\000"
9011 /* 11929 */ "FADD_D\000"
9012 /* 11936 */ "FMADD_D\000"
9013 /* 11944 */ "SLD_D\000"
9014 /* 11950 */ "PCKOD_D\000"
9015 /* 11958 */ "ILVOD_D\000"
9016 /* 11966 */ "FCLE_D\000"
9017 /* 11973 */ "FSLE_D\000"
9018 /* 11980 */ "CMP_SLE_D\000"
9019 /* 11990 */ "FCULE_D\000"
9020 /* 11998 */ "FSULE_D\000"
9021 /* 12006 */ "CMP_SULE_D\000"
9022 /* 12017 */ "CMP_ULE_D\000"
9023 /* 12027 */ "CMP_LE_D\000"
9024 /* 12036 */ "FCNE_D\000"
9025 /* 12043 */ "FSNE_D\000"
9026 /* 12050 */ "FCUNE_D\000"
9027 /* 12058 */ "FSUNE_D\000"
9028 /* 12066 */ "INSVE_D\000"
9029 /* 12074 */ "FCAF_D\000"
9030 /* 12081 */ "FSAF_D\000"
9031 /* 12088 */ "CMP_SAF_D\000"
9032 /* 12098 */ "MSUBF_D\000"
9033 /* 12106 */ "MADDF_D\000"
9034 /* 12114 */ "VSHF_D\000"
9035 /* 12121 */ "CMP_F_D\000"
9036 /* 12129 */ "BNEG_D\000"
9037 /* 12136 */ "SRAI_D\000"
9038 /* 12143 */ "SLDI_D\000"
9039 /* 12150 */ "BNEGI_D\000"
9040 /* 12158 */ "SLLI_D\000"
9041 /* 12165 */ "SRLI_D\000"
9042 /* 12172 */ "BINSLI_D\000"
9043 /* 12181 */ "CEQI_D\000"
9044 /* 12188 */ "SRARI_D\000"
9045 /* 12196 */ "BCLRI_D\000"
9046 /* 12204 */ "SRLRI_D\000"
9047 /* 12212 */ "BINSRI_D\000"
9048 /* 12221 */ "SPLATI_D\000"
9049 /* 12230 */ "BSETI_D\000"
9050 /* 12238 */ "SUBVI_D\000"
9051 /* 12246 */ "ADDVI_D\000"
9052 /* 12254 */ "SEL_D\000"
9053 /* 12260 */ "FILL_D\000"
9054 /* 12267 */ "SLL_D\000"
9055 /* 12273 */ "FEXUPL_D\000"
9056 /* 12282 */ "FFQL_D\000"
9057 /* 12289 */ "SRL_D\000"
9058 /* 12295 */ "BINSL_D\000"
9059 /* 12303 */ "FMUL_D\000"
9060 /* 12310 */ "ILVL_D\000"
9061 /* 12317 */ "FMIN_D\000"
9062 /* 12324 */ "FCUN_D\000"
9063 /* 12331 */ "FSUN_D\000"
9064 /* 12338 */ "CMP_SUN_D\000"
9065 /* 12348 */ "CMP_UN_D\000"
9066 /* 12357 */ "FRCP_D\000"
9067 /* 12364 */ "FCEQ_D\000"
9068 /* 12371 */ "FSEQ_D\000"
9069 /* 12378 */ "CMP_SEQ_D\000"
9070 /* 12388 */ "FCUEQ_D\000"
9071 /* 12396 */ "FSUEQ_D\000"
9072 /* 12404 */ "CMP_SUEQ_D\000"
9073 /* 12415 */ "CMP_UEQ_D\000"
9074 /* 12425 */ "CMP_EQ_D\000"
9075 /* 12434 */ "SRAR_D\000"
9076 /* 12441 */ "LDR_D\000"
9077 /* 12447 */ "BCLR_D\000"
9078 /* 12454 */ "SRLR_D\000"
9079 /* 12461 */ "FCOR_D\000"
9080 /* 12468 */ "FSOR_D\000"
9081 /* 12475 */ "FEXUPR_D\000"
9082 /* 12484 */ "FFQR_D\000"
9083 /* 12491 */ "BINSR_D\000"
9084 /* 12499 */ "STR_D\000"
9085 /* 12505 */ "ILVR_D\000"
9086 /* 12512 */ "FABS_D\000"
9087 /* 12519 */ "FCLASS_D\000"
9088 /* 12528 */ "ASUB_S_D\000"
9089 /* 12537 */ "HSUB_S_D\000"
9090 /* 12546 */ "DPSUB_S_D\000"
9091 /* 12556 */ "FTRUNC_S_D\000"
9092 /* 12567 */ "HADD_S_D\000"
9093 /* 12576 */ "DPADD_S_D\000"
9094 /* 12586 */ "MOD_S_D\000"
9095 /* 12594 */ "CLE_S_D\000"
9096 /* 12602 */ "AVE_S_D\000"
9097 /* 12610 */ "CLEI_S_D\000"
9098 /* 12619 */ "MINI_S_D\000"
9099 /* 12628 */ "CLTI_S_D\000"
9100 /* 12637 */ "MAXI_S_D\000"
9101 /* 12646 */ "MIN_S_D\000"
9102 /* 12654 */ "DOTP_S_D\000"
9103 /* 12663 */ "AVER_S_D\000"
9104 /* 12672 */ "SUBS_S_D\000"
9105 /* 12681 */ "ADDS_S_D\000"
9106 /* 12690 */ "SAT_S_D\000"
9107 /* 12698 */ "CLT_S_D\000"
9108 /* 12706 */ "FFINT_S_D\000"
9109 /* 12716 */ "FTINT_S_D\000"
9110 /* 12726 */ "SUBSUU_S_D\000"
9111 /* 12737 */ "DIV_S_D\000"
9112 /* 12745 */ "MAX_S_D\000"
9113 /* 12753 */ "COPY_S_D\000"
9114 /* 12762 */ "SPLAT_D\000"
9115 /* 12770 */ "BSET_D\000"
9116 /* 12777 */ "FCLT_D\000"
9117 /* 12784 */ "FSLT_D\000"
9118 /* 12791 */ "CMP_SLT_D\000"
9119 /* 12801 */ "FCULT_D\000"
9120 /* 12809 */ "FSULT_D\000"
9121 /* 12817 */ "CMP_SULT_D\000"
9122 /* 12828 */ "CMP_ULT_D\000"
9123 /* 12838 */ "CMP_LT_D\000"
9124 /* 12847 */ "PCNT_D\000"
9125 /* 12854 */ "FRINT_D\000"
9126 /* 12862 */ "INSERT_D\000"
9127 /* 12871 */ "FSQRT_D\000"
9128 /* 12879 */ "FRSQRT_D\000"
9129 /* 12888 */ "ST_D\000"
9130 /* 12893 */ "ASUB_U_D\000"
9131 /* 12902 */ "HSUB_U_D\000"
9132 /* 12911 */ "DPSUB_U_D\000"
9133 /* 12921 */ "FTRUNC_U_D\000"
9134 /* 12932 */ "HADD_U_D\000"
9135 /* 12941 */ "DPADD_U_D\000"
9136 /* 12951 */ "MOD_U_D\000"
9137 /* 12959 */ "CLE_U_D\000"
9138 /* 12967 */ "AVE_U_D\000"
9139 /* 12975 */ "CLEI_U_D\000"
9140 /* 12984 */ "MINI_U_D\000"
9141 /* 12993 */ "CLTI_U_D\000"
9142 /* 13002 */ "MAXI_U_D\000"
9143 /* 13011 */ "MIN_U_D\000"
9144 /* 13019 */ "DOTP_U_D\000"
9145 /* 13028 */ "AVER_U_D\000"
9146 /* 13037 */ "SUBS_U_D\000"
9147 /* 13046 */ "ADDS_U_D\000"
9148 /* 13055 */ "SUBSUS_U_D\000"
9149 /* 13066 */ "SAT_U_D\000"
9150 /* 13074 */ "CLT_U_D\000"
9151 /* 13082 */ "FFINT_U_D\000"
9152 /* 13092 */ "FTINT_U_D\000"
9153 /* 13102 */ "DIV_U_D\000"
9154 /* 13110 */ "MAX_U_D\000"
9155 /* 13118 */ "MSUBV_D\000"
9156 /* 13126 */ "MADDV_D\000"
9157 /* 13134 */ "PCKEV_D\000"
9158 /* 13142 */ "ILVEV_D\000"
9159 /* 13150 */ "FDIV_D\000"
9160 /* 13157 */ "MULV_D\000"
9161 /* 13164 */ "PseudoTRUNC_W_D\000"
9162 /* 13180 */ "FMAX_D\000"
9163 /* 13187 */ "BZ_D\000"
9164 /* 13192 */ "SELNEZ_D\000"
9165 /* 13201 */ "BNZ_D\000"
9166 /* 13207 */ "SELEQZ_D\000"
9167 /* 13216 */ "LBE\000"
9168 /* 13220 */ "PSEUDO_PROBE\000"
9169 /* 13233 */ "SBE\000"
9170 /* 13237 */ "G_SSUBE\000"
9171 /* 13245 */ "G_USUBE\000"
9172 /* 13253 */ "G_FENCE\000"
9173 /* 13261 */ "ARITH_FENCE\000"
9174 /* 13273 */ "REG_SEQUENCE\000"
9175 /* 13286 */ "SCE\000"
9176 /* 13290 */ "G_SADDE\000"
9177 /* 13298 */ "G_UADDE\000"
9178 /* 13306 */ "G_GET_FPMODE\000"
9179 /* 13319 */ "G_RESET_FPMODE\000"
9180 /* 13334 */ "G_SET_FPMODE\000"
9181 /* 13347 */ "G_FMINNUM_IEEE\000"
9182 /* 13362 */ "G_FMAXNUM_IEEE\000"
9183 /* 13377 */ "CACHEE\000"
9184 /* 13384 */ "PREFE\000"
9185 /* 13390 */ "BGE\000"
9186 /* 13394 */ "SGE\000"
9187 /* 13398 */ "TGE\000"
9188 /* 13402 */ "CACHE\000"
9189 /* 13408 */ "LHE\000"
9190 /* 13412 */ "SHE\000"
9191 /* 13416 */ "SIGRIE\000"
9192 /* 13423 */ "G_VSCALE\000"
9193 /* 13432 */ "G_JUMP_TABLE\000"
9194 /* 13445 */ "BUNDLE\000"
9195 /* 13452 */ "LLE\000"
9196 /* 13456 */ "SLE\000"
9197 /* 13460 */ "LWLE\000"
9198 /* 13465 */ "SWLE\000"
9199 /* 13470 */ "BNE\000"
9200 /* 13474 */ "G_MEMCPY_INLINE\000"
9201 /* 13490 */ "SNE\000"
9202 /* 13494 */ "TNE\000"
9203 /* 13498 */ "LOCAL_ESCAPE\000"
9204 /* 13511 */ "DVPE\000"
9205 /* 13516 */ "EVPE\000"
9206 /* 13521 */ "G_STACKRESTORE\000"
9207 /* 13536 */ "G_INDEXED_STORE\000"
9208 /* 13552 */ "G_STORE\000"
9209 /* 13560 */ "LWRE\000"
9210 /* 13565 */ "SWRE\000"
9211 /* 13570 */ "G_BITREVERSE\000"
9212 /* 13583 */ "PAUSE\000"
9213 /* 13589 */ "FAKE_USE\000"
9214 /* 13598 */ "DBG_VALUE\000"
9215 /* 13608 */ "G_GLOBAL_VALUE\000"
9216 /* 13623 */ "G_PTRAUTH_GLOBAL_VALUE\000"
9217 /* 13646 */ "CONVERGENCECTRL_GLUE\000"
9218 /* 13667 */ "G_STACKSAVE\000"
9219 /* 13679 */ "G_MEMMOVE\000"
9220 /* 13689 */ "LWE\000"
9221 /* 13693 */ "SWE\000"
9222 /* 13697 */ "G_FREEZE\000"
9223 /* 13706 */ "G_FCANONICALIZE\000"
9224 /* 13722 */ "LBuE\000"
9225 /* 13727 */ "LHuE\000"
9226 /* 13732 */ "BC1F\000"
9227 /* 13737 */ "G_CTLZ_ZERO_UNDEF\000"
9228 /* 13755 */ "G_CTTZ_ZERO_UNDEF\000"
9229 /* 13773 */ "INIT_UNDEF\000"
9230 /* 13784 */ "G_IMPLICIT_DEF\000"
9231 /* 13799 */ "PREF\000"
9232 /* 13804 */ "DBG_INSTR_REF\000"
9233 /* 13818 */ "TLBINVF\000"
9234 /* 13826 */ "TLBGINVF\000"
9235 /* 13835 */ "G_FNEG\000"
9236 /* 13842 */ "TAILCALLHB64R6REG\000"
9237 /* 13860 */ "TAILCALL64R6REG\000"
9238 /* 13876 */ "TAILCALLHBR6REG\000"
9239 /* 13892 */ "TAILCALLR6REG\000"
9240 /* 13906 */ "EXTRACT_SUBREG\000"
9241 /* 13921 */ "INSERT_SUBREG\000"
9242 /* 13935 */ "TAILCALLREG\000"
9243 /* 13947 */ "G_SEXT_INREG\000"
9244 /* 13960 */ "SUBREG_TO_REG\000"
9245 /* 13974 */ "G_ATOMIC_CMPXCHG\000"
9246 /* 13991 */ "G_ATOMICRMW_XCHG\000"
9247 /* 14008 */ "G_FLOG\000"
9248 /* 14015 */ "G_VAARG\000"
9249 /* 14023 */ "PREALLOCATED_ARG\000"
9250 /* 14040 */ "CRC32H\000"
9251 /* 14047 */ "DSBH\000"
9252 /* 14052 */ "WSBH\000"
9253 /* 14057 */ "CRC32CH\000"
9254 /* 14065 */ "G_PREFETCH\000"
9255 /* 14076 */ "SEH\000"
9256 /* 14080 */ "G_SMULH\000"
9257 /* 14088 */ "G_UMULH\000"
9258 /* 14096 */ "G_FTANH\000"
9259 /* 14104 */ "G_FSINH\000"
9260 /* 14112 */ "SHRA_PH\000"
9261 /* 14120 */ "PRECRQ_QB_PH\000"
9262 /* 14133 */ "PRECR_QB_PH\000"
9263 /* 14145 */ "PRECRQU_S_QB_PH\000"
9264 /* 14161 */ "PseudoCMP_LE_PH\000"
9265 /* 14177 */ "SUBQH_PH\000"
9266 /* 14186 */ "ADDQH_PH\000"
9267 /* 14195 */ "PseudoPICK_PH\000"
9268 /* 14209 */ "SHLL_PH\000"
9269 /* 14217 */ "REPL_PH\000"
9270 /* 14225 */ "SHRL_PH\000"
9271 /* 14233 */ "PACKRL_PH\000"
9272 /* 14243 */ "MUL_PH\000"
9273 /* 14250 */ "SUBQ_PH\000"
9274 /* 14258 */ "ADDQ_PH\000"
9275 /* 14266 */ "PseudoCMP_EQ_PH\000"
9276 /* 14282 */ "SHRA_R_PH\000"
9277 /* 14292 */ "SUBQH_R_PH\000"
9278 /* 14303 */ "ADDQH_R_PH\000"
9279 /* 14314 */ "SHRAV_R_PH\000"
9280 /* 14325 */ "MULQ_RS_PH\000"
9281 /* 14336 */ "SHLL_S_PH\000"
9282 /* 14346 */ "MUL_S_PH\000"
9283 /* 14355 */ "SUBQ_S_PH\000"
9284 /* 14365 */ "ADDQ_S_PH\000"
9285 /* 14375 */ "MULQ_S_PH\000"
9286 /* 14385 */ "ABSQ_S_PH\000"
9287 /* 14395 */ "SUBU_S_PH\000"
9288 /* 14405 */ "ADDU_S_PH\000"
9289 /* 14415 */ "SHLLV_S_PH\000"
9290 /* 14426 */ "PseudoCMP_LT_PH\000"
9291 /* 14442 */ "SUBU_PH\000"
9292 /* 14450 */ "ADDU_PH\000"
9293 /* 14458 */ "SHRAV_PH\000"
9294 /* 14467 */ "SHLLV_PH\000"
9295 /* 14476 */ "REPLV_PH\000"
9296 /* 14485 */ "SHRLV_PH\000"
9297 /* 14494 */ "DPA_W_PH\000"
9298 /* 14503 */ "MULSA_W_PH\000"
9299 /* 14514 */ "DPAQX_SA_W_PH\000"
9300 /* 14528 */ "DPSQX_SA_W_PH\000"
9301 /* 14542 */ "DPS_W_PH\000"
9302 /* 14551 */ "DPAQ_S_W_PH\000"
9303 /* 14563 */ "MULSAQ_S_W_PH\000"
9304 /* 14577 */ "DPSQ_S_W_PH\000"
9305 /* 14589 */ "DPAQX_S_W_PH\000"
9306 /* 14602 */ "DPSQX_S_W_PH\000"
9307 /* 14615 */ "DPAX_W_PH\000"
9308 /* 14625 */ "DPSX_W_PH\000"
9309 /* 14635 */ "G_FCOSH\000"
9310 /* 14643 */ "DMUH\000"
9311 /* 14648 */ "SRA_H\000"
9312 /* 14654 */ "ADD_A_H\000"
9313 /* 14662 */ "MIN_A_H\000"
9314 /* 14670 */ "ADDS_A_H\000"
9315 /* 14679 */ "MAX_A_H\000"
9316 /* 14687 */ "NLOC_H\000"
9317 /* 14694 */ "NLZC_H\000"
9318 /* 14701 */ "SLD_H\000"
9319 /* 14707 */ "PCKOD_H\000"
9320 /* 14715 */ "ILVOD_H\000"
9321 /* 14723 */ "INSVE_H\000"
9322 /* 14731 */ "VSHF_H\000"
9323 /* 14738 */ "BNEG_H\000"
9324 /* 14745 */ "SRAI_H\000"
9325 /* 14752 */ "SLDI_H\000"
9326 /* 14759 */ "BNEGI_H\000"
9327 /* 14767 */ "SLLI_H\000"
9328 /* 14774 */ "SRLI_H\000"
9329 /* 14781 */ "BINSLI_H\000"
9330 /* 14790 */ "CEQI_H\000"
9331 /* 14797 */ "SRARI_H\000"
9332 /* 14805 */ "BCLRI_H\000"
9333 /* 14813 */ "SRLRI_H\000"
9334 /* 14821 */ "BINSRI_H\000"
9335 /* 14830 */ "SPLATI_H\000"
9336 /* 14839 */ "BSETI_H\000"
9337 /* 14847 */ "SUBVI_H\000"
9338 /* 14855 */ "ADDVI_H\000"
9339 /* 14863 */ "FILL_H\000"
9340 /* 14870 */ "SLL_H\000"
9341 /* 14876 */ "SRL_H\000"
9342 /* 14882 */ "BINSL_H\000"
9343 /* 14890 */ "ILVL_H\000"
9344 /* 14897 */ "FEXDO_H\000"
9345 /* 14905 */ "CEQ_H\000"
9346 /* 14911 */ "FTQ_H\000"
9347 /* 14917 */ "MSUB_Q_H\000"
9348 /* 14926 */ "MADD_Q_H\000"
9349 /* 14935 */ "MUL_Q_H\000"
9350 /* 14943 */ "MSUBR_Q_H\000"
9351 /* 14953 */ "MADDR_Q_H\000"
9352 /* 14963 */ "MULR_Q_H\000"
9353 /* 14972 */ "SRAR_H\000"
9354 /* 14979 */ "BCLR_H\000"
9355 /* 14986 */ "SRLR_H\000"
9356 /* 14993 */ "BINSR_H\000"
9357 /* 15001 */ "ILVR_H\000"
9358 /* 15008 */ "ASUB_S_H\000"
9359 /* 15017 */ "HSUB_S_H\000"
9360 /* 15026 */ "DPSUB_S_H\000"
9361 /* 15036 */ "HADD_S_H\000"
9362 /* 15045 */ "DPADD_S_H\000"
9363 /* 15055 */ "MOD_S_H\000"
9364 /* 15063 */ "CLE_S_H\000"
9365 /* 15071 */ "AVE_S_H\000"
9366 /* 15079 */ "CLEI_S_H\000"
9367 /* 15088 */ "MINI_S_H\000"
9368 /* 15097 */ "CLTI_S_H\000"
9369 /* 15106 */ "MAXI_S_H\000"
9370 /* 15115 */ "MIN_S_H\000"
9371 /* 15123 */ "DOTP_S_H\000"
9372 /* 15132 */ "AVER_S_H\000"
9373 /* 15141 */ "EXTR_S_H\000"
9374 /* 15150 */ "SUBS_S_H\000"
9375 /* 15159 */ "ADDS_S_H\000"
9376 /* 15168 */ "SAT_S_H\000"
9377 /* 15176 */ "CLT_S_H\000"
9378 /* 15184 */ "SUBSUU_S_H\000"
9379 /* 15195 */ "DIV_S_H\000"
9380 /* 15203 */ "EXTRV_S_H\000"
9381 /* 15213 */ "MAX_S_H\000"
9382 /* 15221 */ "COPY_S_H\000"
9383 /* 15230 */ "SPLAT_H\000"
9384 /* 15238 */ "BSET_H\000"
9385 /* 15245 */ "PCNT_H\000"
9386 /* 15252 */ "INSERT_H\000"
9387 /* 15261 */ "ST_H\000"
9388 /* 15266 */ "ASUB_U_H\000"
9389 /* 15275 */ "HSUB_U_H\000"
9390 /* 15284 */ "DPSUB_U_H\000"
9391 /* 15294 */ "HADD_U_H\000"
9392 /* 15303 */ "DPADD_U_H\000"
9393 /* 15313 */ "MOD_U_H\000"
9394 /* 15321 */ "CLE_U_H\000"
9395 /* 15329 */ "AVE_U_H\000"
9396 /* 15337 */ "CLEI_U_H\000"
9397 /* 15346 */ "MINI_U_H\000"
9398 /* 15355 */ "CLTI_U_H\000"
9399 /* 15364 */ "MAXI_U_H\000"
9400 /* 15373 */ "MIN_U_H\000"
9401 /* 15381 */ "DOTP_U_H\000"
9402 /* 15390 */ "AVER_U_H\000"
9403 /* 15399 */ "SUBS_U_H\000"
9404 /* 15408 */ "ADDS_U_H\000"
9405 /* 15417 */ "SUBSUS_U_H\000"
9406 /* 15428 */ "SAT_U_H\000"
9407 /* 15436 */ "CLT_U_H\000"
9408 /* 15444 */ "DIV_U_H\000"
9409 /* 15452 */ "MAX_U_H\000"
9410 /* 15460 */ "COPY_U_H\000"
9411 /* 15469 */ "MSUBV_H\000"
9412 /* 15477 */ "MADDV_H\000"
9413 /* 15485 */ "PCKEV_H\000"
9414 /* 15493 */ "ILVEV_H\000"
9415 /* 15501 */ "MULV_H\000"
9416 /* 15508 */ "BZ_H\000"
9417 /* 15513 */ "BNZ_H\000"
9418 /* 15519 */ "SYNCI\000"
9419 /* 15525 */ "DI\000"
9420 /* 15528 */ "TGEI\000"
9421 /* 15533 */ "TNEI\000"
9422 /* 15538 */ "DAHI\000"
9423 /* 15543 */ "PseudoMFHI\000"
9424 /* 15554 */ "PseudoMTLOHI\000"
9425 /* 15567 */ "DBG_PHI\000"
9426 /* 15575 */ "MFTHI\000"
9427 /* 15581 */ "MTHI\000"
9428 /* 15586 */ "MTTHI\000"
9429 /* 15592 */ "TEQI\000"
9430 /* 15597 */ "G_FPTOSI\000"
9431 /* 15606 */ "DATI\000"
9432 /* 15611 */ "TLTI\000"
9433 /* 15616 */ "DAUI\000"
9434 /* 15621 */ "G_FPTOUI\000"
9435 /* 15630 */ "GINVI\000"
9436 /* 15636 */ "TLBWI\000"
9437 /* 15642 */ "TLBGWI\000"
9438 /* 15649 */ "G_FPOWI\000"
9439 /* 15657 */ "MOVN_I64_I\000"
9440 /* 15668 */ "MOVZ_I64_I\000"
9441 /* 15679 */ "MOVF_I\000"
9442 /* 15686 */ "PseudoSELECTFP_F_I\000"
9443 /* 15705 */ "MOVN_I_I\000"
9444 /* 15714 */ "MOVZ_I_I\000"
9445 /* 15723 */ "PseudoD_SELECT_I\000"
9446 /* 15740 */ "PseudoSELECT_I\000"
9447 /* 15755 */ "MOVT_I\000"
9448 /* 15762 */ "PseudoSELECTFP_T_I\000"
9449 /* 15781 */ "J\000"
9450 /* 15783 */ "BREAK\000"
9451 /* 15789 */ "FORK\000"
9452 /* 15794 */ "G_PTRMASK\000"
9453 /* 15804 */ "BAL\000"
9454 /* 15808 */ "JAL\000"
9455 /* 15812 */ "NAL\000"
9456 /* 15816 */ "BGEZAL\000"
9457 /* 15823 */ "BLTZAL\000"
9458 /* 15830 */ "MULEU_S_PH_QBL\000"
9459 /* 15845 */ "PRECEU_PH_QBL\000"
9460 /* 15859 */ "PRECEQU_PH_QBL\000"
9461 /* 15874 */ "DPAU_H_QBL\000"
9462 /* 15885 */ "DPSU_H_QBL\000"
9463 /* 15896 */ "LDL\000"
9464 /* 15900 */ "SDL\000"
9465 /* 15904 */ "GC_LABEL\000"
9466 /* 15913 */ "DBG_LABEL\000"
9467 /* 15923 */ "EH_LABEL\000"
9468 /* 15932 */ "ANNOTATION_LABEL\000"
9469 /* 15949 */ "BGEL\000"
9470 /* 15954 */ "BLEL\000"
9471 /* 15959 */ "BNEL\000"
9472 /* 15964 */ "ICALL_BRANCH_FUNNEL\000"
9473 /* 15984 */ "BC1FL\000"
9474 /* 15990 */ "MAQ_SA_W_PHL\000"
9475 /* 16003 */ "PRECEQ_W_PHL\000"
9476 /* 16016 */ "MAQ_S_W_PHL\000"
9477 /* 16028 */ "MULEQ_S_W_PHL\000"
9478 /* 16042 */ "G_FSHL\000"
9479 /* 16049 */ "G_SHL\000"
9480 /* 16055 */ "G_FCEIL\000"
9481 /* 16063 */ "TAILCALL\000"
9482 /* 16072 */ "HYPCALL\000"
9483 /* 16080 */ "SYSCALL\000"
9484 /* 16088 */ "PATCHABLE_TAIL_CALL\000"
9485 /* 16108 */ "PATCHABLE_TYPED_EVENT_CALL\000"
9486 /* 16135 */ "PATCHABLE_EVENT_CALL\000"
9487 /* 16156 */ "FENTRY_CALL\000"
9488 /* 16168 */ "BGEZALL\000"
9489 /* 16176 */ "BLTZALL\000"
9490 /* 16184 */ "KILL\000"
9491 /* 16189 */ "DSLL\000"
9492 /* 16194 */ "G_CONSTANT_POOL\000"
9493 /* 16210 */ "DROL\000"
9494 /* 16215 */ "BEQL\000"
9495 /* 16220 */ "DSRL\000"
9496 /* 16225 */ "BC1TL\000"
9497 /* 16231 */ "BGTL\000"
9498 /* 16236 */ "BLTL\000"
9499 /* 16241 */ "G_ROTL\000"
9500 /* 16248 */ "BGEUL\000"
9501 /* 16254 */ "BLEUL\000"
9502 /* 16260 */ "DMUL\000"
9503 /* 16265 */ "G_VECREDUCE_FMUL\000"
9504 /* 16282 */ "G_FMUL\000"
9505 /* 16289 */ "G_VECREDUCE_SEQ_FMUL\000"
9506 /* 16310 */ "G_STRICT_FMUL\000"
9507 /* 16324 */ "G_VECREDUCE_MUL\000"
9508 /* 16340 */ "G_MUL\000"
9509 /* 16346 */ "BGTUL\000"
9510 /* 16352 */ "BLTUL\000"
9511 /* 16358 */ "LWL\000"
9512 /* 16362 */ "SWL\000"
9513 /* 16366 */ "BGEZL\000"
9514 /* 16372 */ "BLEZL\000"
9515 /* 16378 */ "BGTZL\000"
9516 /* 16384 */ "BLTZL\000"
9517 /* 16390 */ "PseudoCVT_D64_L\000"
9518 /* 16406 */ "PseudoCVT_S_L\000"
9519 /* 16420 */ "G_FREM\000"
9520 /* 16427 */ "G_STRICT_FREM\000"
9521 /* 16441 */ "G_SREM\000"
9522 /* 16448 */ "G_UREM\000"
9523 /* 16455 */ "G_SDIVREM\000"
9524 /* 16465 */ "G_UDIVREM\000"
9525 /* 16475 */ "MFGC0_MM\000"
9526 /* 16484 */ "MFHGC0_MM\000"
9527 /* 16494 */ "MTHGC0_MM\000"
9528 /* 16504 */ "MTGC0_MM\000"
9529 /* 16513 */ "CFC1_MM\000"
9530 /* 16521 */ "MFC1_MM\000"
9531 /* 16529 */ "CTC1_MM\000"
9532 /* 16537 */ "MTC1_MM\000"
9533 /* 16545 */ "LWC1_MM\000"
9534 /* 16553 */ "SWC1_MM\000"
9535 /* 16561 */ "LUXC1_MM\000"
9536 /* 16570 */ "SUXC1_MM\000"
9537 /* 16579 */ "LWXC1_MM\000"
9538 /* 16588 */ "SWXC1_MM\000"
9539 /* 16597 */ "MFHC1_D32_MM\000"
9540 /* 16610 */ "MTHC1_D32_MM\000"
9541 /* 16623 */ "FSUB_D32_MM\000"
9542 /* 16635 */ "NMSUB_D32_MM\000"
9543 /* 16648 */ "FADD_D32_MM\000"
9544 /* 16660 */ "NMADD_D32_MM\000"
9545 /* 16673 */ "C_NGE_D32_MM\000"
9546 /* 16686 */ "C_NGLE_D32_MM\000"
9547 /* 16700 */ "C_OLE_D32_MM\000"
9548 /* 16713 */ "C_ULE_D32_MM\000"
9549 /* 16726 */ "C_LE_D32_MM\000"
9550 /* 16738 */ "C_SF_D32_MM\000"
9551 /* 16750 */ "MOVF_D32_MM\000"
9552 /* 16762 */ "C_F_D32_MM\000"
9553 /* 16773 */ "FNEG_D32_MM\000"
9554 /* 16785 */ "MOVN_I_D32_MM\000"
9555 /* 16799 */ "MOVZ_I_D32_MM\000"
9556 /* 16813 */ "C_NGL_D32_MM\000"
9557 /* 16826 */ "FMUL_D32_MM\000"
9558 /* 16838 */ "C_UN_D32_MM\000"
9559 /* 16850 */ "RECIP_D32_MM\000"
9560 /* 16863 */ "FCMP_D32_MM\000"
9561 /* 16875 */ "C_SEQ_D32_MM\000"
9562 /* 16888 */ "C_UEQ_D32_MM\000"
9563 /* 16901 */ "C_EQ_D32_MM\000"
9564 /* 16913 */ "FABS_D32_MM\000"
9565 /* 16925 */ "CVT_S_D32_MM\000"
9566 /* 16938 */ "C_NGT_D32_MM\000"
9567 /* 16951 */ "C_OLT_D32_MM\000"
9568 /* 16964 */ "C_ULT_D32_MM\000"
9569 /* 16977 */ "C_LT_D32_MM\000"
9570 /* 16989 */ "FSQRT_D32_MM\000"
9571 /* 17002 */ "RSQRT_D32_MM\000"
9572 /* 17015 */ "MOVT_D32_MM\000"
9573 /* 17027 */ "FDIV_D32_MM\000"
9574 /* 17039 */ "FMOV_D32_MM\000"
9575 /* 17051 */ "CVT_W_D32_MM\000"
9576 /* 17064 */ "BPOSGE32_MM\000"
9577 /* 17076 */ "LWM32_MM\000"
9578 /* 17085 */ "SWM32_MM\000"
9579 /* 17094 */ "FCMP_S32_MM\000"
9580 /* 17106 */ "CFC2_MM\000"
9581 /* 17114 */ "CTC2_MM\000"
9582 /* 17122 */ "ADDIUR2_MM\000"
9583 /* 17133 */ "MFHC1_D64_MM\000"
9584 /* 17146 */ "MTHC1_D64_MM\000"
9585 /* 17159 */ "MTC1_D64_MM\000"
9586 /* 17171 */ "FSUB_D64_MM\000"
9587 /* 17183 */ "FADD_D64_MM\000"
9588 /* 17195 */ "C_NGE_D64_MM\000"
9589 /* 17208 */ "C_NGLE_D64_MM\000"
9590 /* 17222 */ "C_OLE_D64_MM\000"
9591 /* 17235 */ "C_ULE_D64_MM\000"
9592 /* 17248 */ "C_LE_D64_MM\000"
9593 /* 17260 */ "C_SF_D64_MM\000"
9594 /* 17272 */ "C_F_D64_MM\000"
9595 /* 17283 */ "FNEG_D64_MM\000"
9596 /* 17295 */ "C_NGL_D64_MM\000"
9597 /* 17308 */ "FMUL_D64_MM\000"
9598 /* 17320 */ "CVT_L_D64_MM\000"
9599 /* 17333 */ "C_UN_D64_MM\000"
9600 /* 17345 */ "RECIP_D64_MM\000"
9601 /* 17358 */ "C_SEQ_D64_MM\000"
9602 /* 17371 */ "C_UEQ_D64_MM\000"
9603 /* 17384 */ "C_EQ_D64_MM\000"
9604 /* 17396 */ "FABS_D64_MM\000"
9605 /* 17408 */ "CVT_S_D64_MM\000"
9606 /* 17421 */ "C_NGT_D64_MM\000"
9607 /* 17434 */ "C_OLT_D64_MM\000"
9608 /* 17447 */ "C_ULT_D64_MM\000"
9609 /* 17460 */ "C_LT_D64_MM\000"
9610 /* 17472 */ "FSQRT_D64_MM\000"
9611 /* 17485 */ "RSQRT_D64_MM\000"
9612 /* 17498 */ "FDIV_D64_MM\000"
9613 /* 17510 */ "FMOV_D64_MM\000"
9614 /* 17522 */ "CVT_W_D64_MM\000"
9615 /* 17535 */ "ADDIUS5_MM\000"
9616 /* 17546 */ "SB16_MM\000"
9617 /* 17554 */ "JRC16_MM\000"
9618 /* 17563 */ "AND16_MM\000"
9619 /* 17572 */ "MOVE16_MM\000"
9620 /* 17582 */ "SH16_MM\000"
9621 /* 17590 */ "ANDI16_MM\000"
9622 /* 17600 */ "MFHI16_MM\000"
9623 /* 17610 */ "LI16_MM\000"
9624 /* 17618 */ "BREAK16_MM\000"
9625 /* 17629 */ "SLL16_MM\000"
9626 /* 17638 */ "SRL16_MM\000"
9627 /* 17647 */ "LWM16_MM\000"
9628 /* 17656 */ "SWM16_MM\000"
9629 /* 17665 */ "MFLO16_MM\000"
9630 /* 17675 */ "SDBBP16_MM\000"
9631 /* 17686 */ "JR16_MM\000"
9632 /* 17694 */ "JALR16_MM\000"
9633 /* 17704 */ "XOR16_MM\000"
9634 /* 17713 */ "JALRS16_MM\000"
9635 /* 17724 */ "NOT16_MM\000"
9636 /* 17733 */ "LBU16_MM\000"
9637 /* 17742 */ "SUBU16_MM\000"
9638 /* 17752 */ "ADDU16_MM\000"
9639 /* 17762 */ "LHU16_MM\000"
9640 /* 17771 */ "LW16_MM\000"
9641 /* 17779 */ "SW16_MM\000"
9642 /* 17787 */ "BNEZ16_MM\000"
9643 /* 17797 */ "BEQZ16_MM\000"
9644 /* 17807 */ "PRECEU_PH_QBLA_MM\000"
9645 /* 17825 */ "PRECEQU_PH_QBLA_MM\000"
9646 /* 17844 */ "PRECEU_PH_QBRA_MM\000"
9647 /* 17862 */ "PRECEQU_PH_QBRA_MM\000"
9648 /* 17881 */ "SRA_MM\000"
9649 /* 17888 */ "SEB_MM\000"
9650 /* 17895 */ "EHB_MM\000"
9651 /* 17902 */ "LB_MM\000"
9652 /* 17908 */ "CMPGU_LE_QB_MM\000"
9653 /* 17923 */ "CMPU_LE_QB_MM\000"
9654 /* 17937 */ "PICK_QB_MM\000"
9655 /* 17948 */ "SHLL_QB_MM\000"
9656 /* 17959 */ "REPL_QB_MM\000"
9657 /* 17970 */ "SHRL_QB_MM\000"
9658 /* 17981 */ "CMPGU_EQ_QB_MM\000"
9659 /* 17996 */ "CMPU_EQ_QB_MM\000"
9660 /* 18010 */ "SUBU_S_QB_MM\000"
9661 /* 18023 */ "ADDU_S_QB_MM\000"
9662 /* 18036 */ "CMPGU_LT_QB_MM\000"
9663 /* 18051 */ "CMPU_LT_QB_MM\000"
9664 /* 18065 */ "SUBU_QB_MM\000"
9665 /* 18076 */ "ADDU_QB_MM\000"
9666 /* 18087 */ "SHLLV_QB_MM\000"
9667 /* 18099 */ "REPLV_QB_MM\000"
9668 /* 18111 */ "SHRLV_QB_MM\000"
9669 /* 18123 */ "RADDU_W_QB_MM\000"
9670 /* 18137 */ "SB_MM\000"
9671 /* 18143 */ "MODSUB_MM\000"
9672 /* 18153 */ "PseudoMSUB_MM\000"
9673 /* 18167 */ "SYNC_MM\000"
9674 /* 18175 */ "ADDIUPC_MM\000"
9675 /* 18186 */ "ADDSC_MM\000"
9676 /* 18195 */ "ADDWC_MM\000"
9677 /* 18204 */ "BNEZC_MM\000"
9678 /* 18213 */ "BEQZC_MM\000"
9679 /* 18222 */ "PseudoMADD_MM\000"
9680 /* 18236 */ "AND_MM\000"
9681 /* 18243 */ "LBE_MM\000"
9682 /* 18250 */ "SBE_MM\000"
9683 /* 18257 */ "SCE_MM\000"
9684 /* 18264 */ "CACHEE_MM\000"
9685 /* 18274 */ "PREFE_MM\000"
9686 /* 18283 */ "TGE_MM\000"
9687 /* 18290 */ "CACHE_MM\000"
9688 /* 18299 */ "LHE_MM\000"
9689 /* 18306 */ "SHE_MM\000"
9690 /* 18313 */ "LLE_MM\000"
9691 /* 18320 */ "LWLE_MM\000"
9692 /* 18328 */ "SWLE_MM\000"
9693 /* 18336 */ "BNE_MM\000"
9694 /* 18343 */ "TNE_MM\000"
9695 /* 18350 */ "LWRE_MM\000"
9696 /* 18358 */ "SWRE_MM\000"
9697 /* 18366 */ "PAUSE_MM\000"
9698 /* 18375 */ "LWE_MM\000"
9699 /* 18382 */ "SWE_MM\000"
9700 /* 18389 */ "LBuE_MM\000"
9701 /* 18397 */ "LHuE_MM\000"
9702 /* 18405 */ "BC1F_MM\000"
9703 /* 18413 */ "PREF_MM\000"
9704 /* 18421 */ "TLBGINVF_MM\000"
9705 /* 18433 */ "TAILCALLREG_MM\000"
9706 /* 18448 */ "WSBH_MM\000"
9707 /* 18456 */ "SEH_MM\000"
9708 /* 18463 */ "LH_MM\000"
9709 /* 18469 */ "SHRA_PH_MM\000"
9710 /* 18480 */ "PRECRQ_QB_PH_MM\000"
9711 /* 18496 */ "PRECRQU_S_QB_PH_MM\000"
9712 /* 18515 */ "CMP_LE_PH_MM\000"
9713 /* 18528 */ "PICK_PH_MM\000"
9714 /* 18539 */ "SHLL_PH_MM\000"
9715 /* 18550 */ "REPL_PH_MM\000"
9716 /* 18561 */ "PACKRL_PH_MM\000"
9717 /* 18574 */ "SUBQ_PH_MM\000"
9718 /* 18585 */ "ADDQ_PH_MM\000"
9719 /* 18596 */ "CMP_EQ_PH_MM\000"
9720 /* 18609 */ "SHRA_R_PH_MM\000"
9721 /* 18622 */ "SHRAV_R_PH_MM\000"
9722 /* 18636 */ "MULQ_RS_PH_MM\000"
9723 /* 18650 */ "SHLL_S_PH_MM\000"
9724 /* 18663 */ "SUBQ_S_PH_MM\000"
9725 /* 18676 */ "ADDQ_S_PH_MM\000"
9726 /* 18689 */ "ABSQ_S_PH_MM\000"
9727 /* 18702 */ "SHLLV_S_PH_MM\000"
9728 /* 18716 */ "CMP_LT_PH_MM\000"
9729 /* 18729 */ "SHRAV_PH_MM\000"
9730 /* 18741 */ "SHLLV_PH_MM\000"
9731 /* 18753 */ "REPLV_PH_MM\000"
9732 /* 18765 */ "DPAQ_S_W_PH_MM\000"
9733 /* 18780 */ "MULSAQ_S_W_PH_MM\000"
9734 /* 18797 */ "DPSQ_S_W_PH_MM\000"
9735 /* 18812 */ "SH_MM\000"
9736 /* 18818 */ "EXTR_S_H_MM\000"
9737 /* 18830 */ "EXTRV_S_H_MM\000"
9738 /* 18843 */ "SYNCI_MM\000"
9739 /* 18852 */ "DI_MM\000"
9740 /* 18858 */ "TGEI_MM\000"
9741 /* 18866 */ "TNEI_MM\000"
9742 /* 18874 */ "PseudoMFHI_MM\000"
9743 /* 18888 */ "PseudoMTLOHI_MM\000"
9744 /* 18904 */ "MTHI_MM\000"
9745 /* 18912 */ "TEQI_MM\000"
9746 /* 18920 */ "TLTI_MM\000"
9747 /* 18928 */ "TLBWI_MM\000"
9748 /* 18937 */ "TLBGWI_MM\000"
9749 /* 18947 */ "MOVF_I_MM\000"
9750 /* 18957 */ "MOVN_I_MM\000"
9751 /* 18967 */ "MOVT_I_MM\000"
9752 /* 18977 */ "MOVZ_I_MM\000"
9753 /* 18987 */ "J_MM\000"
9754 /* 18992 */ "BREAK_MM\000"
9755 /* 19001 */ "JAL_MM\000"
9756 /* 19008 */ "BGEZAL_MM\000"
9757 /* 19018 */ "BLTZAL_MM\000"
9758 /* 19028 */ "MULEU_S_PH_QBL_MM\000"
9759 /* 19046 */ "PRECEU_PH_QBL_MM\000"
9760 /* 19063 */ "PRECEQU_PH_QBL_MM\000"
9761 /* 19081 */ "DPAU_H_QBL_MM\000"
9762 /* 19095 */ "DPSU_H_QBL_MM\000"
9763 /* 19109 */ "MAQ_SA_W_PHL_MM\000"
9764 /* 19125 */ "PRECEQ_W_PHL_MM\000"
9765 /* 19141 */ "MAQ_S_W_PHL_MM\000"
9766 /* 19156 */ "MULEQ_S_W_PHL_MM\000"
9767 /* 19173 */ "TAILCALL_MM\000"
9768 /* 19185 */ "HYPCALL_MM\000"
9769 /* 19196 */ "SYSCALL_MM\000"
9770 /* 19207 */ "SLL_MM\000"
9771 /* 19214 */ "SRL_MM\000"
9772 /* 19221 */ "MUL_MM\000"
9773 /* 19228 */ "LWL_MM\000"
9774 /* 19235 */ "SWL_MM\000"
9775 /* 19242 */ "LWM_MM\000"
9776 /* 19249 */ "SWM_MM\000"
9777 /* 19256 */ "CLO_MM\000"
9778 /* 19263 */ "PseudoMFLO_MM\000"
9779 /* 19277 */ "SHILO_MM\000"
9780 /* 19286 */ "MTLO_MM\000"
9781 /* 19294 */ "TRAP_MM\000"
9782 /* 19302 */ "SDBBP_MM\000"
9783 /* 19311 */ "TLBP_MM\000"
9784 /* 19319 */ "EXTPDP_MM\000"
9785 /* 19329 */ "MOVEP_MM\000"
9786 /* 19338 */ "TLBGP_MM\000"
9787 /* 19347 */ "LWGP_MM\000"
9788 /* 19355 */ "MTHLIP_MM\000"
9789 /* 19365 */ "SSNOP_MM\000"
9790 /* 19374 */ "ADDIUR1SP_MM\000"
9791 /* 19387 */ "RDDSP_MM\000"
9792 /* 19396 */ "WRDSP_MM\000"
9793 /* 19405 */ "LWDSP_MM\000"
9794 /* 19414 */ "SWDSP_MM\000"
9795 /* 19423 */ "MSUB_DSP_MM\000"
9796 /* 19435 */ "MADD_DSP_MM\000"
9797 /* 19447 */ "MFHI_DSP_MM\000"
9798 /* 19459 */ "MTHI_DSP_MM\000"
9799 /* 19471 */ "MFLO_DSP_MM\000"
9800 /* 19483 */ "MTLO_DSP_MM\000"
9801 /* 19495 */ "MULT_DSP_MM\000"
9802 /* 19507 */ "MSUBU_DSP_MM\000"
9803 /* 19520 */ "MADDU_DSP_MM\000"
9804 /* 19533 */ "MULTU_DSP_MM\000"
9805 /* 19546 */ "ADDIUSP_MM\000"
9806 /* 19557 */ "LWSP_MM\000"
9807 /* 19565 */ "SWSP_MM\000"
9808 /* 19573 */ "EXTP_MM\000"
9809 /* 19581 */ "LWP_MM\000"
9810 /* 19588 */ "SWP_MM\000"
9811 /* 19595 */ "BEQ_MM\000"
9812 /* 19602 */ "TEQ_MM\000"
9813 /* 19609 */ "TLBR_MM\000"
9814 /* 19617 */ "MULEU_S_PH_QBR_MM\000"
9815 /* 19635 */ "PRECEU_PH_QBR_MM\000"
9816 /* 19652 */ "PRECEQU_PH_QBR_MM\000"
9817 /* 19670 */ "DPAU_H_QBR_MM\000"
9818 /* 19684 */ "DPSU_H_QBR_MM\000"
9819 /* 19698 */ "BAL_BR_MM\000"
9820 /* 19708 */ "TLBGR_MM\000"
9821 /* 19717 */ "MAQ_SA_W_PHR_MM\000"
9822 /* 19733 */ "PRECEQ_W_PHR_MM\000"
9823 /* 19749 */ "MAQ_S_W_PHR_MM\000"
9824 /* 19764 */ "MULEQ_S_W_PHR_MM\000"
9825 /* 19781 */ "JR_MM\000"
9826 /* 19787 */ "JALR_MM\000"
9827 /* 19795 */ "NOR_MM\000"
9828 /* 19802 */ "XOR_MM\000"
9829 /* 19809 */ "ROTR_MM\000"
9830 /* 19817 */ "TLBWR_MM\000"
9831 /* 19826 */ "TLBGWR_MM\000"
9832 /* 19836 */ "RDHWR_MM\000"
9833 /* 19845 */ "LWR_MM\000"
9834 /* 19852 */ "SWR_MM\000"
9835 /* 19859 */ "JALS_MM\000"
9836 /* 19867 */ "BGEZALS_MM\000"
9837 /* 19878 */ "BLTZALS_MM\000"
9838 /* 19889 */ "INS_MM\000"
9839 /* 19896 */ "JALRS_MM\000"
9840 /* 19905 */ "LWXS_MM\000"
9841 /* 19913 */ "CVT_D32_S_MM\000"
9842 /* 19926 */ "CVT_D64_S_MM\000"
9843 /* 19939 */ "FSUB_S_MM\000"
9844 /* 19949 */ "NMSUB_S_MM\000"
9845 /* 19960 */ "FADD_S_MM\000"
9846 /* 19970 */ "NMADD_S_MM\000"
9847 /* 19981 */ "C_NGE_S_MM\000"
9848 /* 19992 */ "C_NGLE_S_MM\000"
9849 /* 20004 */ "C_OLE_S_MM\000"
9850 /* 20015 */ "C_ULE_S_MM\000"
9851 /* 20026 */ "C_LE_S_MM\000"
9852 /* 20036 */ "C_SF_S_MM\000"
9853 /* 20046 */ "MOVF_S_MM\000"
9854 /* 20056 */ "C_F_S_MM\000"
9855 /* 20065 */ "FNEG_S_MM\000"
9856 /* 20075 */ "MOVN_I_S_MM\000"
9857 /* 20087 */ "MOVZ_I_S_MM\000"
9858 /* 20099 */ "C_NGL_S_MM\000"
9859 /* 20110 */ "FMUL_S_MM\000"
9860 /* 20120 */ "CVT_L_S_MM\000"
9861 /* 20131 */ "C_UN_S_MM\000"
9862 /* 20141 */ "RECIP_S_MM\000"
9863 /* 20152 */ "C_SEQ_S_MM\000"
9864 /* 20163 */ "C_UEQ_S_MM\000"
9865 /* 20174 */ "C_EQ_S_MM\000"
9866 /* 20184 */ "FABS_S_MM\000"
9867 /* 20194 */ "C_NGT_S_MM\000"
9868 /* 20205 */ "C_OLT_S_MM\000"
9869 /* 20216 */ "C_ULT_S_MM\000"
9870 /* 20227 */ "C_LT_S_MM\000"
9871 /* 20237 */ "FSQRT_S_MM\000"
9872 /* 20248 */ "RSQRT_S_MM\000"
9873 /* 20259 */ "MOVT_S_MM\000"
9874 /* 20269 */ "FDIV_S_MM\000"
9875 /* 20279 */ "FMOV_S_MM\000"
9876 /* 20289 */ "TRUNC_W_S_MM\000"
9877 /* 20302 */ "ROUND_W_S_MM\000"
9878 /* 20315 */ "CEIL_W_S_MM\000"
9879 /* 20327 */ "FLOOR_W_S_MM\000"
9880 /* 20340 */ "CVT_W_S_MM\000"
9881 /* 20351 */ "BC1T_MM\000"
9882 /* 20359 */ "DERET_MM\000"
9883 /* 20368 */ "WAIT_MM\000"
9884 /* 20376 */ "SLT_MM\000"
9885 /* 20383 */ "TLT_MM\000"
9886 /* 20390 */ "PseudoMULT_MM\000"
9887 /* 20404 */ "EXT_MM\000"
9888 /* 20411 */ "PseudoMSUBU_MM\000"
9889 /* 20426 */ "PseudoMADDU_MM\000"
9890 /* 20441 */ "TGEU_MM\000"
9891 /* 20449 */ "TGEIU_MM\000"
9892 /* 20458 */ "TLTIU_MM\000"
9893 /* 20467 */ "TLTU_MM\000"
9894 /* 20475 */ "LWU_MM\000"
9895 /* 20482 */ "SRAV_MM\000"
9896 /* 20490 */ "BITREV_MM\000"
9897 /* 20500 */ "SDIV_MM\000"
9898 /* 20508 */ "UDIV_MM\000"
9899 /* 20516 */ "SLLV_MM\000"
9900 /* 20524 */ "SRLV_MM\000"
9901 /* 20532 */ "TLBGINV_MM\000"
9902 /* 20543 */ "SHILOV_MM\000"
9903 /* 20553 */ "EXTPDPV_MM\000"
9904 /* 20564 */ "EXTPV_MM\000"
9905 /* 20573 */ "ROTRV_MM\000"
9906 /* 20582 */ "INSV_MM\000"
9907 /* 20590 */ "LW_MM\000"
9908 /* 20596 */ "SW_MM\000"
9909 /* 20602 */ "CVT_D32_W_MM\000"
9910 /* 20615 */ "CVT_D64_W_MM\000"
9911 /* 20628 */ "TRUNC_W_MM\000"
9912 /* 20639 */ "ROUND_W_MM\000"
9913 /* 20650 */ "PRECRQ_PH_W_MM\000"
9914 /* 20665 */ "PRECRQ_RS_PH_W_MM\000"
9915 /* 20683 */ "CEIL_W_MM\000"
9916 /* 20693 */ "DPAQ_SA_L_W_MM\000"
9917 /* 20708 */ "DPSQ_SA_L_W_MM\000"
9918 /* 20723 */ "FLOOR_W_MM\000"
9919 /* 20734 */ "EXTR_W_MM\000"
9920 /* 20744 */ "SHRA_R_W_MM\000"
9921 /* 20756 */ "EXTR_R_W_MM\000"
9922 /* 20768 */ "SHRAV_R_W_MM\000"
9923 /* 20781 */ "EXTRV_R_W_MM\000"
9924 /* 20794 */ "EXTR_RS_W_MM\000"
9925 /* 20807 */ "EXTRV_RS_W_MM\000"
9926 /* 20821 */ "SHLL_S_W_MM\000"
9927 /* 20833 */ "SUBQ_S_W_MM\000"
9928 /* 20845 */ "ADDQ_S_W_MM\000"
9929 /* 20857 */ "ABSQ_S_W_MM\000"
9930 /* 20869 */ "CVT_S_W_MM\000"
9931 /* 20880 */ "SHLLV_S_W_MM\000"
9932 /* 20893 */ "EXTRV_W_MM\000"
9933 /* 20904 */ "PREFX_MM\000"
9934 /* 20913 */ "LHX_MM\000"
9935 /* 20920 */ "JALX_MM\000"
9936 /* 20928 */ "LBUX_MM\000"
9937 /* 20936 */ "LWX_MM\000"
9938 /* 20943 */ "BGEZ_MM\000"
9939 /* 20951 */ "BLEZ_MM\000"
9940 /* 20959 */ "CLZ_MM\000"
9941 /* 20966 */ "BGTZ_MM\000"
9942 /* 20974 */ "BLTZ_MM\000"
9943 /* 20982 */ "PseudoIndirectBranch_MM\000"
9944 /* 21006 */ "ADDi_MM\000"
9945 /* 21014 */ "ANDi_MM\000"
9946 /* 21022 */ "XORi_MM\000"
9947 /* 21030 */ "SLTi_MM\000"
9948 /* 21038 */ "LUi_MM\000"
9949 /* 21045 */ "LBu_MM\000"
9950 /* 21052 */ "SUBu_MM\000"
9951 /* 21060 */ "ADDu_MM\000"
9952 /* 21068 */ "LHu_MM\000"
9953 /* 21075 */ "SLTu_MM\000"
9954 /* 21083 */ "PseudoMULTu_MM\000"
9955 /* 21098 */ "LEA_ADDiu_MM\000"
9956 /* 21111 */ "SLTiu_MM\000"
9957 /* 21120 */ "INLINEASM\000"
9958 /* 21130 */ "DINSM\000"
9959 /* 21136 */ "DEXTM\000"
9960 /* 21142 */ "G_VECREDUCE_FMINIMUM\000"
9961 /* 21163 */ "G_FMINIMUM\000"
9962 /* 21174 */ "G_ATOMICRMW_FMINIMUM\000"
9963 /* 21195 */ "G_VECREDUCE_FMAXIMUM\000"
9964 /* 21216 */ "G_FMAXIMUM\000"
9965 /* 21227 */ "G_ATOMICRMW_FMAXIMUM\000"
9966 /* 21248 */ "G_FMINIMUMNUM\000"
9967 /* 21262 */ "G_FMAXIMUMNUM\000"
9968 /* 21276 */ "G_FMINNUM\000"
9969 /* 21286 */ "G_FMAXNUM\000"
9970 /* 21296 */ "G_FATAN\000"
9971 /* 21304 */ "G_FTAN\000"
9972 /* 21311 */ "G_INTRINSIC_ROUNDEVEN\000"
9973 /* 21333 */ "BALIGN\000"
9974 /* 21340 */ "DALIGN\000"
9975 /* 21347 */ "G_ASSERT_ALIGN\000"
9976 /* 21362 */ "G_FCOPYSIGN\000"
9977 /* 21374 */ "G_VECREDUCE_FMIN\000"
9978 /* 21391 */ "G_ATOMICRMW_FMIN\000"
9979 /* 21408 */ "G_VECREDUCE_SMIN\000"
9980 /* 21425 */ "G_SMIN\000"
9981 /* 21432 */ "G_VECREDUCE_UMIN\000"
9982 /* 21449 */ "G_UMIN\000"
9983 /* 21456 */ "G_ATOMICRMW_UMIN\000"
9984 /* 21473 */ "G_ATOMICRMW_MIN\000"
9985 /* 21489 */ "G_FASIN\000"
9986 /* 21497 */ "G_FSIN\000"
9987 /* 21504 */ "DMFC2_OCTEON\000"
9988 /* 21517 */ "DMTC2_OCTEON\000"
9989 /* 21530 */ "CFI_INSTRUCTION\000"
9990 /* 21546 */ "ADJCALLSTACKDOWN\000"
9991 /* 21563 */ "G_SSUBO\000"
9992 /* 21571 */ "G_USUBO\000"
9993 /* 21579 */ "G_SADDO\000"
9994 /* 21587 */ "G_UADDO\000"
9995 /* 21595 */ "FEXP2_D_1_PSEUDO\000"
9996 /* 21612 */ "FEXP2_W_1_PSEUDO\000"
9997 /* 21629 */ "BPOSGE32_PSEUDO\000"
9998 /* 21645 */ "INSERT_B_VIDX64_PSEUDO\000"
9999 /* 21668 */ "INSERT_FD_VIDX64_PSEUDO\000"
10000 /* 21692 */ "INSERT_D_VIDX64_PSEUDO\000"
10001 /* 21715 */ "INSERT_H_VIDX64_PSEUDO\000"
10002 /* 21738 */ "INSERT_FW_VIDX64_PSEUDO\000"
10003 /* 21762 */ "INSERT_W_VIDX64_PSEUDO\000"
10004 /* 21785 */ "SNZ_B_PSEUDO\000"
10005 /* 21798 */ "SZ_B_PSEUDO\000"
10006 /* 21810 */ "BSEL_FD_PSEUDO\000"
10007 /* 21825 */ "FILL_FD_PSEUDO\000"
10008 /* 21840 */ "INSERT_FD_PSEUDO\000"
10009 /* 21857 */ "COPY_FD_PSEUDO\000"
10010 /* 21872 */ "MSA_FP_EXTEND_D_PSEUDO\000"
10011 /* 21895 */ "MSA_FP_ROUND_D_PSEUDO\000"
10012 /* 21917 */ "BSEL_D_PSEUDO\000"
10013 /* 21931 */ "AND_V_D_PSEUDO\000"
10014 /* 21946 */ "NOR_V_D_PSEUDO\000"
10015 /* 21961 */ "XOR_V_D_PSEUDO\000"
10016 /* 21976 */ "SNZ_D_PSEUDO\000"
10017 /* 21989 */ "SZ_D_PSEUDO\000"
10018 /* 22001 */ "BSEL_H_PSEUDO\000"
10019 /* 22015 */ "AND_V_H_PSEUDO\000"
10020 /* 22030 */ "NOR_V_H_PSEUDO\000"
10021 /* 22045 */ "XOR_V_H_PSEUDO\000"
10022 /* 22060 */ "SNZ_H_PSEUDO\000"
10023 /* 22073 */ "SZ_H_PSEUDO\000"
10024 /* 22085 */ "SNZ_V_PSEUDO\000"
10025 /* 22098 */ "SZ_V_PSEUDO\000"
10026 /* 22110 */ "BSEL_FW_PSEUDO\000"
10027 /* 22125 */ "FILL_FW_PSEUDO\000"
10028 /* 22140 */ "INSERT_FW_PSEUDO\000"
10029 /* 22157 */ "COPY_FW_PSEUDO\000"
10030 /* 22172 */ "MSA_FP_EXTEND_W_PSEUDO\000"
10031 /* 22195 */ "MSA_FP_ROUND_W_PSEUDO\000"
10032 /* 22217 */ "BSEL_W_PSEUDO\000"
10033 /* 22231 */ "AND_V_W_PSEUDO\000"
10034 /* 22246 */ "NOR_V_W_PSEUDO\000"
10035 /* 22261 */ "XOR_V_W_PSEUDO\000"
10036 /* 22276 */ "SNZ_W_PSEUDO\000"
10037 /* 22289 */ "SZ_W_PSEUDO\000"
10038 /* 22301 */ "INSERT_B_VIDX_PSEUDO\000"
10039 /* 22322 */ "INSERT_FD_VIDX_PSEUDO\000"
10040 /* 22344 */ "INSERT_D_VIDX_PSEUDO\000"
10041 /* 22365 */ "INSERT_H_VIDX_PSEUDO\000"
10042 /* 22386 */ "INSERT_FW_VIDX_PSEUDO\000"
10043 /* 22408 */ "INSERT_W_VIDX_PSEUDO\000"
10044 /* 22429 */ "JUMP_TABLE_DEBUG_INFO\000"
10045 /* 22451 */ "DCLO\000"
10046 /* 22456 */ "PseudoMFLO\000"
10047 /* 22467 */ "SHILO\000"
10048 /* 22473 */ "MFTLO\000"
10049 /* 22479 */ "MTLO\000"
10050 /* 22484 */ "MTTLO\000"
10051 /* 22490 */ "G_SMULO\000"
10052 /* 22498 */ "G_UMULO\000"
10053 /* 22506 */ "G_BZERO\000"
10054 /* 22514 */ "STACKMAP\000"
10055 /* 22523 */ "G_DEBUGTRAP\000"
10056 /* 22535 */ "G_UBSANTRAP\000"
10057 /* 22547 */ "G_TRAP\000"
10058 /* 22554 */ "G_ATOMICRMW_UDEC_WRAP\000"
10059 /* 22576 */ "G_ATOMICRMW_UINC_WRAP\000"
10060 /* 22598 */ "G_BSWAP\000"
10061 /* 22606 */ "DBITSWAP\000"
10062 /* 22615 */ "SDBBP\000"
10063 /* 22621 */ "TLBP\000"
10064 /* 22626 */ "EXTPDP\000"
10065 /* 22633 */ "G_SITOFP\000"
10066 /* 22642 */ "G_UITOFP\000"
10067 /* 22651 */ "TLBGP\000"
10068 /* 22657 */ "MTHLIP\000"
10069 /* 22664 */ "G_FCMP\000"
10070 /* 22671 */ "G_ICMP\000"
10071 /* 22678 */ "G_SCMP\000"
10072 /* 22685 */ "G_UCMP\000"
10073 /* 22692 */ "SSNOP\000"
10074 /* 22698 */ "CONVERGENCECTRL_LOOP\000"
10075 /* 22719 */ "DPOP\000"
10076 /* 22724 */ "G_CTPOP\000"
10077 /* 22732 */ "PATCHABLE_OP\000"
10078 /* 22745 */ "FAULTING_OP\000"
10079 /* 22757 */ "LOAD_ACC64DSP\000"
10080 /* 22771 */ "STORE_ACC64DSP\000"
10081 /* 22786 */ "RDDSP\000"
10082 /* 22792 */ "WRDSP\000"
10083 /* 22798 */ "MFTDSP\000"
10084 /* 22805 */ "MTTDSP\000"
10085 /* 22812 */ "LWDSP\000"
10086 /* 22818 */ "SWDSP\000"
10087 /* 22824 */ "MSUB_DSP\000"
10088 /* 22833 */ "MADD_DSP\000"
10089 /* 22842 */ "LOAD_CCOND_DSP\000"
10090 /* 22857 */ "STORE_CCOND_DSP\000"
10091 /* 22873 */ "MFHI_DSP\000"
10092 /* 22882 */ "PseudoMTLOHI_DSP\000"
10093 /* 22899 */ "MTHI_DSP\000"
10094 /* 22908 */ "MFLO_DSP\000"
10095 /* 22917 */ "MTLO_DSP\000"
10096 /* 22926 */ "MULT_DSP\000"
10097 /* 22935 */ "MSUBU_DSP\000"
10098 /* 22945 */ "MADDU_DSP\000"
10099 /* 22955 */ "MULTU_DSP\000"
10100 /* 22965 */ "JRADDIUSP\000"
10101 /* 22975 */ "EXTP\000"
10102 /* 22980 */ "ADJCALLSTACKUP\000"
10103 /* 22995 */ "PREALLOCATED_SETUP\000"
10104 /* 23014 */ "DVP\000"
10105 /* 23018 */ "EVP\000"
10106 /* 23022 */ "G_FLDEXP\000"
10107 /* 23031 */ "G_STRICT_FLDEXP\000"
10108 /* 23047 */ "G_FEXP\000"
10109 /* 23054 */ "G_FFREXP\000"
10110 /* 23063 */ "BEQ\000"
10111 /* 23067 */ "SEQ\000"
10112 /* 23071 */ "TEQ\000"
10113 /* 23075 */ "TLBR\000"
10114 /* 23080 */ "MULEU_S_PH_QBR\000"
10115 /* 23095 */ "PRECEU_PH_QBR\000"
10116 /* 23109 */ "PRECEQU_PH_QBR\000"
10117 /* 23124 */ "DPAU_H_QBR\000"
10118 /* 23135 */ "DPSU_H_QBR\000"
10119 /* 23146 */ "G_BR\000"
10120 /* 23151 */ "BAL_BR\000"
10121 /* 23158 */ "INLINEASM_BR\000"
10122 /* 23171 */ "G_BLOCK_ADDR\000"
10123 /* 23184 */ "LDR\000"
10124 /* 23188 */ "SDR\000"
10125 /* 23192 */ "MEMBARRIER\000"
10126 /* 23203 */ "G_CONSTANT_FOLD_BARRIER\000"
10127 /* 23227 */ "PATCHABLE_FUNCTION_ENTER\000"
10128 /* 23252 */ "G_READCYCLECOUNTER\000"
10129 /* 23271 */ "G_READSTEADYCOUNTER\000"
10130 /* 23291 */ "G_READ_REGISTER\000"
10131 /* 23307 */ "G_WRITE_REGISTER\000"
10132 /* 23324 */ "TLBGR\000"
10133 /* 23330 */ "LoadImmDoubleFGR\000"
10134 /* 23347 */ "LoadImmSingleFGR\000"
10135 /* 23364 */ "MAQ_SA_W_PHR\000"
10136 /* 23377 */ "PRECEQ_W_PHR\000"
10137 /* 23390 */ "MAQ_S_W_PHR\000"
10138 /* 23402 */ "MULEQ_S_W_PHR\000"
10139 /* 23416 */ "G_ASHR\000"
10140 /* 23423 */ "G_FSHR\000"
10141 /* 23430 */ "G_LSHR\000"
10142 /* 23437 */ "JR\000"
10143 /* 23440 */ "JALR\000"
10144 /* 23445 */ "CONVERGENCECTRL_ANCHOR\000"
10145 /* 23468 */ "NOR\000"
10146 /* 23472 */ "G_FFLOOR\000"
10147 /* 23481 */ "DROR\000"
10148 /* 23486 */ "G_EXTRACT_SUBVECTOR\000"
10149 /* 23506 */ "G_INSERT_SUBVECTOR\000"
10150 /* 23525 */ "G_BUILD_VECTOR\000"
10151 /* 23540 */ "G_SHUFFLE_VECTOR\000"
10152 /* 23557 */ "G_STEP_VECTOR\000"
10153 /* 23571 */ "G_SPLAT_VECTOR\000"
10154 /* 23586 */ "G_VECREDUCE_XOR\000"
10155 /* 23602 */ "G_XOR\000"
10156 /* 23608 */ "G_ATOMICRMW_XOR\000"
10157 /* 23624 */ "G_VECREDUCE_OR\000"
10158 /* 23639 */ "G_OR\000"
10159 /* 23644 */ "G_ATOMICRMW_OR\000"
10160 /* 23659 */ "MFTGPR\000"
10161 /* 23666 */ "MTTGPR\000"
10162 /* 23673 */ "LoadImmDoubleGPR\000"
10163 /* 23690 */ "LoadImmSingleGPR\000"
10164 /* 23707 */ "MFTR\000"
10165 /* 23712 */ "DROTR\000"
10166 /* 23718 */ "G_ROTR\000"
10167 /* 23725 */ "G_INTTOPTR\000"
10168 /* 23736 */ "MTTR\000"
10169 /* 23741 */ "TLBWR\000"
10170 /* 23747 */ "TLBGWR\000"
10171 /* 23754 */ "RDHWR\000"
10172 /* 23760 */ "LWR\000"
10173 /* 23764 */ "SWR\000"
10174 /* 23768 */ "G_FABS\000"
10175 /* 23775 */ "G_ABS\000"
10176 /* 23781 */ "G_ABDS\000"
10177 /* 23788 */ "G_UNMERGE_VALUES\000"
10178 /* 23805 */ "G_MERGE_VALUES\000"
10179 /* 23820 */ "CINS\000"
10180 /* 23825 */ "DINS\000"
10181 /* 23830 */ "G_FACOS\000"
10182 /* 23838 */ "G_FCOS\000"
10183 /* 23845 */ "G_FSINCOS\000"
10184 /* 23855 */ "G_CONCAT_VECTORS\000"
10185 /* 23872 */ "COPY_TO_REGCLASS\000"
10186 /* 23889 */ "G_IS_FPCLASS\000"
10187 /* 23902 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000"
10188 /* 23932 */ "G_VECTOR_COMPRESS\000"
10189 /* 23950 */ "G_INTRINSIC_W_SIDE_EFFECTS\000"
10190 /* 23977 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000"
10191 /* 24015 */ "EXTS\000"
10192 /* 24020 */ "CVT_D32_S\000"
10193 /* 24030 */ "CVT_D64_S\000"
10194 /* 24040 */ "MOVN_I64_S\000"
10195 /* 24051 */ "MOVZ_I64_S\000"
10196 /* 24062 */ "MINA_S\000"
10197 /* 24069 */ "MAXA_S\000"
10198 /* 24076 */ "FSUB_S\000"
10199 /* 24083 */ "NMSUB_S\000"
10200 /* 24091 */ "FADD_S\000"
10201 /* 24098 */ "NMADD_S\000"
10202 /* 24106 */ "C_NGE_S\000"
10203 /* 24114 */ "C_NGLE_S\000"
10204 /* 24123 */ "C_OLE_S\000"
10205 /* 24131 */ "CMP_SLE_S\000"
10206 /* 24141 */ "CMP_SULE_S\000"
10207 /* 24152 */ "C_ULE_S\000"
10208 /* 24160 */ "CMP_ULE_S\000"
10209 /* 24170 */ "C_LE_S\000"
10210 /* 24177 */ "CMP_LE_S\000"
10211 /* 24186 */ "CMP_SAF_S\000"
10212 /* 24196 */ "MSUBF_S\000"
10213 /* 24204 */ "MADDF_S\000"
10214 /* 24212 */ "C_SF_S\000"
10215 /* 24219 */ "MOVF_S\000"
10216 /* 24226 */ "C_F_S\000"
10217 /* 24232 */ "PseudoSELECTFP_F_S\000"
10218 /* 24251 */ "CMP_F_S\000"
10219 /* 24259 */ "FNEG_S\000"
10220 /* 24266 */ "MOVN_I_S\000"
10221 /* 24275 */ "MOVZ_I_S\000"
10222 /* 24284 */ "SEL_S\000"
10223 /* 24290 */ "C_NGL_S\000"
10224 /* 24298 */ "FMUL_S\000"
10225 /* 24305 */ "TRUNC_L_S\000"
10226 /* 24315 */ "ROUND_L_S\000"
10227 /* 24325 */ "CEIL_L_S\000"
10228 /* 24334 */ "FLOOR_L_S\000"
10229 /* 24344 */ "CVT_L_S\000"
10230 /* 24352 */ "MIN_S\000"
10231 /* 24358 */ "CMP_SUN_S\000"
10232 /* 24368 */ "C_UN_S\000"
10233 /* 24375 */ "CMP_UN_S\000"
10234 /* 24384 */ "RECIP_S\000"
10235 /* 24392 */ "C_SEQ_S\000"
10236 /* 24400 */ "CMP_SEQ_S\000"
10237 /* 24410 */ "CMP_SUEQ_S\000"
10238 /* 24421 */ "C_UEQ_S\000"
10239 /* 24429 */ "CMP_UEQ_S\000"
10240 /* 24439 */ "C_EQ_S\000"
10241 /* 24446 */ "CMP_EQ_S\000"
10242 /* 24455 */ "FABS_S\000"
10243 /* 24462 */ "CLASS_S\000"
10244 /* 24470 */ "PseudoSELECT_S\000"
10245 /* 24485 */ "C_NGT_S\000"
10246 /* 24493 */ "C_OLT_S\000"
10247 /* 24501 */ "CMP_SLT_S\000"
10248 /* 24511 */ "CMP_SULT_S\000"
10249 /* 24522 */ "C_ULT_S\000"
10250 /* 24530 */ "CMP_ULT_S\000"
10251 /* 24540 */ "C_LT_S\000"
10252 /* 24547 */ "CMP_LT_S\000"
10253 /* 24556 */ "RINT_S\000"
10254 /* 24563 */ "FSQRT_S\000"
10255 /* 24571 */ "RSQRT_S\000"
10256 /* 24579 */ "MOVT_S\000"
10257 /* 24586 */ "PseudoSELECTFP_T_S\000"
10258 /* 24605 */ "FDIV_S\000"
10259 /* 24612 */ "FMOV_S\000"
10260 /* 24619 */ "PseudoTRUNC_W_S\000"
10261 /* 24635 */ "ROUND_W_S\000"
10262 /* 24645 */ "CEIL_W_S\000"
10263 /* 24654 */ "FLOOR_W_S\000"
10264 /* 24664 */ "CVT_W_S\000"
10265 /* 24672 */ "MAX_S\000"
10266 /* 24678 */ "SELNEZ_S\000"
10267 /* 24687 */ "SELEQZ_S\000"
10268 /* 24696 */ "BC1T\000"
10269 /* 24701 */ "G_SSUBSAT\000"
10270 /* 24711 */ "G_USUBSAT\000"
10271 /* 24721 */ "G_SADDSAT\000"
10272 /* 24731 */ "G_UADDSAT\000"
10273 /* 24741 */ "G_SSHLSAT\000"
10274 /* 24751 */ "G_USHLSAT\000"
10275 /* 24761 */ "G_SMULFIXSAT\000"
10276 /* 24774 */ "G_UMULFIXSAT\000"
10277 /* 24787 */ "G_SDIVFIXSAT\000"
10278 /* 24800 */ "G_UDIVFIXSAT\000"
10279 /* 24813 */ "G_ATOMICRMW_USUB_SAT\000"
10280 /* 24834 */ "G_FPTOSI_SAT\000"
10281 /* 24847 */ "G_FPTOUI_SAT\000"
10282 /* 24860 */ "G_EXTRACT\000"
10283 /* 24870 */ "G_SELECT\000"
10284 /* 24879 */ "G_BRINDIRECT\000"
10285 /* 24892 */ "DERET\000"
10286 /* 24898 */ "PATCHABLE_RET\000"
10287 /* 24912 */ "G_MEMSET\000"
10288 /* 24921 */ "BGT\000"
10289 /* 24925 */ "WAIT\000"
10290 /* 24930 */ "PATCHABLE_FUNCTION_EXIT\000"
10291 /* 24954 */ "G_BRJT\000"
10292 /* 24961 */ "BLT\000"
10293 /* 24965 */ "G_EXTRACT_VECTOR_ELT\000"
10294 /* 24986 */ "G_INSERT_VECTOR_ELT\000"
10295 /* 25006 */ "SLT\000"
10296 /* 25010 */ "TLT\000"
10297 /* 25014 */ "PseudoDMULT\000"
10298 /* 25026 */ "PseudoMULT\000"
10299 /* 25037 */ "DMT\000"
10300 /* 25041 */ "EMT\000"
10301 /* 25045 */ "G_FCONSTANT\000"
10302 /* 25057 */ "G_CONSTANT\000"
10303 /* 25068 */ "G_INTRINSIC_CONVERGENT\000"
10304 /* 25091 */ "STATEPOINT\000"
10305 /* 25102 */ "PATCHPOINT\000"
10306 /* 25113 */ "G_PTRTOINT\000"
10307 /* 25124 */ "G_FRINT\000"
10308 /* 25132 */ "G_INTRINSIC_LLRINT\000"
10309 /* 25151 */ "G_INTRINSIC_LRINT\000"
10310 /* 25169 */ "G_FNEARBYINT\000"
10311 /* 25182 */ "G_VASTART\000"
10312 /* 25192 */ "LIFETIME_START\000"
10313 /* 25207 */ "G_INVOKE_REGION_START\000"
10314 /* 25229 */ "G_INSERT\000"
10315 /* 25238 */ "G_FSQRT\000"
10316 /* 25246 */ "G_STRICT_FSQRT\000"
10317 /* 25261 */ "G_BITCAST\000"
10318 /* 25271 */ "G_ADDRSPACE_CAST\000"
10319 /* 25288 */ "DBG_VALUE_LIST\000"
10320 /* 25303 */ "GINVT\000"
10321 /* 25309 */ "DEXT\000"
10322 /* 25314 */ "G_FPEXT\000"
10323 /* 25322 */ "G_SEXT\000"
10324 /* 25329 */ "G_ASSERT_SEXT\000"
10325 /* 25343 */ "G_ANYEXT\000"
10326 /* 25352 */ "G_ZEXT\000"
10327 /* 25359 */ "G_ASSERT_ZEXT\000"
10328 /* 25373 */ "PseudoMSUBU\000"
10329 /* 25385 */ "G_ABDU\000"
10330 /* 25392 */ "PseudoMADDU\000"
10331 /* 25404 */ "DMODU\000"
10332 /* 25410 */ "BGEU\000"
10333 /* 25415 */ "SGEU\000"
10334 /* 25420 */ "TGEU\000"
10335 /* 25425 */ "BLEU\000"
10336 /* 25430 */ "SLEU\000"
10337 /* 25435 */ "DMUHU\000"
10338 /* 25441 */ "TGEIU\000"
10339 /* 25447 */ "TTLTIU\000"
10340 /* 25454 */ "V3MULU\000"
10341 /* 25461 */ "DMULU\000"
10342 /* 25467 */ "VMULU\000"
10343 /* 25473 */ "DINSU\000"
10344 /* 25479 */ "BGTU\000"
10345 /* 25484 */ "BLTU\000"
10346 /* 25489 */ "TLTU\000"
10347 /* 25494 */ "DEXTU\000"
10348 /* 25500 */ "DDIVU\000"
10349 /* 25506 */ "DSRAV\000"
10350 /* 25512 */ "BITREV\000"
10351 /* 25519 */ "DDIV\000"
10352 /* 25524 */ "G_FDIV\000"
10353 /* 25531 */ "G_STRICT_FDIV\000"
10354 /* 25545 */ "PseudoDSDIV\000"
10355 /* 25557 */ "G_SDIV\000"
10356 /* 25564 */ "PseudoSDIV\000"
10357 /* 25575 */ "PseudoDUDIV\000"
10358 /* 25587 */ "G_UDIV\000"
10359 /* 25594 */ "PseudoUDIV\000"
10360 /* 25605 */ "DSLLV\000"
10361 /* 25611 */ "DSRLV\000"
10362 /* 25617 */ "G_GET_FPENV\000"
10363 /* 25629 */ "G_RESET_FPENV\000"
10364 /* 25643 */ "G_SET_FPENV\000"
10365 /* 25655 */ "TLBINV\000"
10366 /* 25662 */ "TLBGINV\000"
10367 /* 25670 */ "SHILOV\000"
10368 /* 25677 */ "EXTPDPV\000"
10369 /* 25685 */ "EXTPV\000"
10370 /* 25691 */ "DROTRV\000"
10371 /* 25698 */ "INSV\000"
10372 /* 25703 */ "AND_V\000"
10373 /* 25709 */ "MOVE_V\000"
10374 /* 25716 */ "BSEL_V\000"
10375 /* 25723 */ "NOR_V\000"
10376 /* 25729 */ "XOR_V\000"
10377 /* 25735 */ "BZ_V\000"
10378 /* 25740 */ "BMZ_V\000"
10379 /* 25746 */ "BNZ_V\000"
10380 /* 25752 */ "BMNZ_V\000"
10381 /* 25759 */ "CRC32W\000"
10382 /* 25766 */ "CRC32CW\000"
10383 /* 25774 */ "LW\000"
10384 /* 25777 */ "G_FPOW\000"
10385 /* 25784 */ "SW\000"
10386 /* 25787 */ "PseudoCVT_D32_W\000"
10387 /* 25803 */ "FLOG2_W\000"
10388 /* 25811 */ "FEXP2_W\000"
10389 /* 25819 */ "PseudoCVT_D64_W\000"
10390 /* 25835 */ "SRA_W\000"
10391 /* 25841 */ "ADD_A_W\000"
10392 /* 25849 */ "FMIN_A_W\000"
10393 /* 25858 */ "ADDS_A_W\000"
10394 /* 25867 */ "FMAX_A_W\000"
10395 /* 25876 */ "FSUB_W\000"
10396 /* 25883 */ "FMSUB_W\000"
10397 /* 25891 */ "NLOC_W\000"
10398 /* 25898 */ "NLZC_W\000"
10399 /* 25905 */ "FADD_W\000"
10400 /* 25912 */ "FMADD_W\000"
10401 /* 25920 */ "SLD_W\000"
10402 /* 25926 */ "PCKOD_W\000"
10403 /* 25934 */ "ILVOD_W\000"
10404 /* 25942 */ "FCLE_W\000"
10405 /* 25949 */ "FSLE_W\000"
10406 /* 25956 */ "FCULE_W\000"
10407 /* 25964 */ "FSULE_W\000"
10408 /* 25972 */ "FCNE_W\000"
10409 /* 25979 */ "FSNE_W\000"
10410 /* 25986 */ "FCUNE_W\000"
10411 /* 25994 */ "FSUNE_W\000"
10412 /* 26002 */ "INSVE_W\000"
10413 /* 26010 */ "FCAF_W\000"
10414 /* 26017 */ "FSAF_W\000"
10415 /* 26024 */ "VSHF_W\000"
10416 /* 26031 */ "BNEG_W\000"
10417 /* 26038 */ "PRECR_SRA_PH_W\000"
10418 /* 26053 */ "PRECRQ_PH_W\000"
10419 /* 26065 */ "PRECR_SRA_R_PH_W\000"
10420 /* 26082 */ "PRECRQ_RS_PH_W\000"
10421 /* 26097 */ "SUBQH_W\000"
10422 /* 26105 */ "ADDQH_W\000"
10423 /* 26113 */ "SRAI_W\000"
10424 /* 26120 */ "SLDI_W\000"
10425 /* 26127 */ "BNEGI_W\000"
10426 /* 26135 */ "SLLI_W\000"
10427 /* 26142 */ "SRLI_W\000"
10428 /* 26149 */ "BINSLI_W\000"
10429 /* 26158 */ "CEQI_W\000"
10430 /* 26165 */ "SRARI_W\000"
10431 /* 26173 */ "BCLRI_W\000"
10432 /* 26181 */ "SRLRI_W\000"
10433 /* 26189 */ "BINSRI_W\000"
10434 /* 26198 */ "SPLATI_W\000"
10435 /* 26207 */ "BSETI_W\000"
10436 /* 26215 */ "SUBVI_W\000"
10437 /* 26223 */ "ADDVI_W\000"
10438 /* 26231 */ "FILL_W\000"
10439 /* 26238 */ "SLL_W\000"
10440 /* 26244 */ "FEXUPL_W\000"
10441 /* 26253 */ "FFQL_W\000"
10442 /* 26260 */ "SRL_W\000"
10443 /* 26266 */ "BINSL_W\000"
10444 /* 26274 */ "FMUL_W\000"
10445 /* 26281 */ "ILVL_W\000"
10446 /* 26288 */ "DPAQ_SA_L_W\000"
10447 /* 26300 */ "DPSQ_SA_L_W\000"
10448 /* 26312 */ "FMIN_W\000"
10449 /* 26319 */ "FCUN_W\000"
10450 /* 26326 */ "FSUN_W\000"
10451 /* 26333 */ "FEXDO_W\000"
10452 /* 26341 */ "FRCP_W\000"
10453 /* 26348 */ "FCEQ_W\000"
10454 /* 26355 */ "FSEQ_W\000"
10455 /* 26362 */ "FCUEQ_W\000"
10456 /* 26370 */ "FSUEQ_W\000"
10457 /* 26378 */ "FTQ_W\000"
10458 /* 26384 */ "MSUB_Q_W\000"
10459 /* 26393 */ "MADD_Q_W\000"
10460 /* 26402 */ "MUL_Q_W\000"
10461 /* 26410 */ "MSUBR_Q_W\000"
10462 /* 26420 */ "MADDR_Q_W\000"
10463 /* 26430 */ "MULR_Q_W\000"
10464 /* 26439 */ "SRAR_W\000"
10465 /* 26446 */ "LDR_W\000"
10466 /* 26452 */ "BCLR_W\000"
10467 /* 26459 */ "SRLR_W\000"
10468 /* 26466 */ "FCOR_W\000"
10469 /* 26473 */ "FSOR_W\000"
10470 /* 26480 */ "FEXUPR_W\000"
10471 /* 26489 */ "FFQR_W\000"
10472 /* 26496 */ "BINSR_W\000"
10473 /* 26504 */ "STR_W\000"
10474 /* 26510 */ "EXTR_W\000"
10475 /* 26517 */ "ILVR_W\000"
10476 /* 26524 */ "SHRA_R_W\000"
10477 /* 26533 */ "SUBQH_R_W\000"
10478 /* 26543 */ "ADDQH_R_W\000"
10479 /* 26553 */ "EXTR_R_W\000"
10480 /* 26562 */ "SHRAV_R_W\000"
10481 /* 26572 */ "EXTRV_R_W\000"
10482 /* 26582 */ "FABS_W\000"
10483 /* 26589 */ "MULQ_RS_W\000"
10484 /* 26599 */ "EXTR_RS_W\000"
10485 /* 26609 */ "EXTRV_RS_W\000"
10486 /* 26620 */ "FCLASS_W\000"
10487 /* 26629 */ "ASUB_S_W\000"
10488 /* 26638 */ "HSUB_S_W\000"
10489 /* 26647 */ "DPSUB_S_W\000"
10490 /* 26657 */ "FTRUNC_S_W\000"
10491 /* 26668 */ "HADD_S_W\000"
10492 /* 26677 */ "DPADD_S_W\000"
10493 /* 26687 */ "MOD_S_W\000"
10494 /* 26695 */ "CLE_S_W\000"
10495 /* 26703 */ "AVE_S_W\000"
10496 /* 26711 */ "CLEI_S_W\000"
10497 /* 26720 */ "MINI_S_W\000"
10498 /* 26729 */ "CLTI_S_W\000"
10499 /* 26738 */ "MAXI_S_W\000"
10500 /* 26747 */ "SHLL_S_W\000"
10501 /* 26756 */ "MIN_S_W\000"
10502 /* 26764 */ "DOTP_S_W\000"
10503 /* 26773 */ "SUBQ_S_W\000"
10504 /* 26782 */ "ADDQ_S_W\000"
10505 /* 26791 */ "MULQ_S_W\000"
10506 /* 26800 */ "ABSQ_S_W\000"
10507 /* 26809 */ "AVER_S_W\000"
10508 /* 26818 */ "SUBS_S_W\000"
10509 /* 26827 */ "ADDS_S_W\000"
10510 /* 26836 */ "SAT_S_W\000"
10511 /* 26844 */ "CLT_S_W\000"
10512 /* 26852 */ "FFINT_S_W\000"
10513 /* 26862 */ "FTINT_S_W\000"
10514 /* 26872 */ "PseudoCVT_S_W\000"
10515 /* 26886 */ "SUBSUU_S_W\000"
10516 /* 26897 */ "DIV_S_W\000"
10517 /* 26905 */ "SHLLV_S_W\000"
10518 /* 26915 */ "MAX_S_W\000"
10519 /* 26923 */ "COPY_S_W\000"
10520 /* 26932 */ "SPLAT_W\000"
10521 /* 26940 */ "BSET_W\000"
10522 /* 26947 */ "FCLT_W\000"
10523 /* 26954 */ "FSLT_W\000"
10524 /* 26961 */ "FCULT_W\000"
10525 /* 26969 */ "FSULT_W\000"
10526 /* 26977 */ "PCNT_W\000"
10527 /* 26984 */ "FRINT_W\000"
10528 /* 26992 */ "INSERT_W\000"
10529 /* 27001 */ "FSQRT_W\000"
10530 /* 27009 */ "FRSQRT_W\000"
10531 /* 27018 */ "ST_W\000"
10532 /* 27023 */ "ASUB_U_W\000"
10533 /* 27032 */ "HSUB_U_W\000"
10534 /* 27041 */ "DPSUB_U_W\000"
10535 /* 27051 */ "FTRUNC_U_W\000"
10536 /* 27062 */ "HADD_U_W\000"
10537 /* 27071 */ "DPADD_U_W\000"
10538 /* 27081 */ "MOD_U_W\000"
10539 /* 27089 */ "CLE_U_W\000"
10540 /* 27097 */ "AVE_U_W\000"
10541 /* 27105 */ "CLEI_U_W\000"
10542 /* 27114 */ "MINI_U_W\000"
10543 /* 27123 */ "CLTI_U_W\000"
10544 /* 27132 */ "MAXI_U_W\000"
10545 /* 27141 */ "MIN_U_W\000"
10546 /* 27149 */ "DOTP_U_W\000"
10547 /* 27158 */ "AVER_U_W\000"
10548 /* 27167 */ "SUBS_U_W\000"
10549 /* 27176 */ "ADDS_U_W\000"
10550 /* 27185 */ "SUBSUS_U_W\000"
10551 /* 27196 */ "SAT_U_W\000"
10552 /* 27204 */ "CLT_U_W\000"
10553 /* 27212 */ "FFINT_U_W\000"
10554 /* 27222 */ "FTINT_U_W\000"
10555 /* 27232 */ "DIV_U_W\000"
10556 /* 27240 */ "MAX_U_W\000"
10557 /* 27248 */ "COPY_U_W\000"
10558 /* 27257 */ "MSUBV_W\000"
10559 /* 27265 */ "MADDV_W\000"
10560 /* 27273 */ "PCKEV_W\000"
10561 /* 27281 */ "ILVEV_W\000"
10562 /* 27289 */ "FDIV_W\000"
10563 /* 27296 */ "MULV_W\000"
10564 /* 27303 */ "EXTRV_W\000"
10565 /* 27311 */ "FMAX_W\000"
10566 /* 27318 */ "BZ_W\000"
10567 /* 27323 */ "BNZ_W\000"
10568 /* 27329 */ "G_VECREDUCE_FMAX\000"
10569 /* 27346 */ "G_ATOMICRMW_FMAX\000"
10570 /* 27363 */ "G_VECREDUCE_SMAX\000"
10571 /* 27380 */ "G_SMAX\000"
10572 /* 27387 */ "G_VECREDUCE_UMAX\000"
10573 /* 27404 */ "G_UMAX\000"
10574 /* 27411 */ "G_ATOMICRMW_UMAX\000"
10575 /* 27428 */ "G_ATOMICRMW_MAX\000"
10576 /* 27444 */ "MFTACX\000"
10577 /* 27451 */ "MTTACX\000"
10578 /* 27458 */ "G_FRAME_INDEX\000"
10579 /* 27472 */ "G_SBFX\000"
10580 /* 27479 */ "G_UBFX\000"
10581 /* 27486 */ "LHX\000"
10582 /* 27490 */ "G_SMULFIX\000"
10583 /* 27500 */ "G_UMULFIX\000"
10584 /* 27510 */ "G_SDIVFIX\000"
10585 /* 27520 */ "G_UDIVFIX\000"
10586 /* 27530 */ "JALX\000"
10587 /* 27535 */ "LBUX\000"
10588 /* 27540 */ "LWX\000"
10589 /* 27544 */ "G_MEMCPY\000"
10590 /* 27553 */ "COPY\000"
10591 /* 27558 */ "CONSTPOOL_ENTRY\000"
10592 /* 27574 */ "CONVERGENCECTRL_ENTRY\000"
10593 /* 27596 */ "BGEZ\000"
10594 /* 27601 */ "BLEZ\000"
10595 /* 27606 */ "BC1NEZ\000"
10596 /* 27613 */ "BC2NEZ\000"
10597 /* 27620 */ "SELNEZ\000"
10598 /* 27627 */ "DCLZ\000"
10599 /* 27632 */ "G_CTLZ\000"
10600 /* 27639 */ "BC1EQZ\000"
10601 /* 27646 */ "BC2EQZ\000"
10602 /* 27653 */ "SELEQZ\000"
10603 /* 27660 */ "BGTZ\000"
10604 /* 27665 */ "BLTZ\000"
10605 /* 27670 */ "G_CTTZ\000"
10606 /* 27677 */ "SelBneZ\000"
10607 /* 27685 */ "SelBeqZ\000"
10608 /* 27693 */ "JalOneReg\000"
10609 /* 27703 */ "JalTwoReg\000"
10610 /* 27713 */ "PseudoIndirectHazardBranch\000"
10611 /* 27740 */ "PseudoIndirectBranch\000"
10612 /* 27761 */ "Ulh\000"
10613 /* 27765 */ "Ush\000"
10614 /* 27769 */ "DADDi\000"
10615 /* 27775 */ "ANDi\000"
10616 /* 27780 */ "SNEi\000"
10617 /* 27785 */ "SEQi\000"
10618 /* 27790 */ "XORi\000"
10619 /* 27795 */ "SLTi\000"
10620 /* 27800 */ "LONG_BRANCH_LUi\000"
10621 /* 27816 */ "SelTBtneZCmpi\000"
10622 /* 27830 */ "SelTBteqZCmpi\000"
10623 /* 27844 */ "SelTBtneZSlti\000"
10624 /* 27858 */ "SelTBteqZSlti\000"
10625 /* 27872 */ "SGEImm\000"
10626 /* 27879 */ "SLEImm\000"
10627 /* 27886 */ "DROLImm\000"
10628 /* 27894 */ "NORImm\000"
10629 /* 27901 */ "DRORImm\000"
10630 /* 27909 */ "SGTImm\000"
10631 /* 27916 */ "SGEUImm\000"
10632 /* 27924 */ "SLEUImm\000"
10633 /* 27932 */ "SGTUImm\000"
10634 /* 27940 */ "BneImm\000"
10635 /* 27947 */ "BeqImm\000"
10636 /* 27954 */ "PseudoReturn\000"
10637 /* 27967 */ "JALRHB64Pseudo\000"
10638 /* 27982 */ "JALR64Pseudo\000"
10639 /* 27995 */ "JALRHBPseudo\000"
10640 /* 28008 */ "JALRPseudo\000"
10641 /* 28019 */ "B_MMR6_Pseudo\000"
10642 /* 28033 */ "B_MM_Pseudo\000"
10643 /* 28045 */ "SDIV_MM_Pseudo\000"
10644 /* 28060 */ "UDIV_MM_Pseudo\000"
10645 /* 28075 */ "LDMacro\000"
10646 /* 28083 */ "SDMacro\000"
10647 /* 28091 */ "SNEMacro\000"
10648 /* 28100 */ "SNEIMacro\000"
10649 /* 28110 */ "SEQIMacro\000"
10650 /* 28120 */ "DSRemIMacro\000"
10651 /* 28132 */ "DURemIMacro\000"
10652 /* 28144 */ "DSDivIMacro\000"
10653 /* 28156 */ "DUDivIMacro\000"
10654 /* 28168 */ "DMULMacro\000"
10655 /* 28178 */ "DMULOMacro\000"
10656 /* 28189 */ "SEQMacro\000"
10657 /* 28198 */ "ABSMacro\000"
10658 /* 28207 */ "DMULOUMacro\000"
10659 /* 28219 */ "DSRemMacro\000"
10660 /* 28230 */ "DURemMacro\000"
10661 /* 28241 */ "BGEImmMacro\000"
10662 /* 28253 */ "BLEImmMacro\000"
10663 /* 28265 */ "BGELImmMacro\000"
10664 /* 28278 */ "BLELImmMacro\000"
10665 /* 28291 */ "BNELImmMacro\000"
10666 /* 28304 */ "BEQLImmMacro\000"
10667 /* 28317 */ "BGTLImmMacro\000"
10668 /* 28330 */ "BLTLImmMacro\000"
10669 /* 28343 */ "BGEULImmMacro\000"
10670 /* 28357 */ "BLEULImmMacro\000"
10671 /* 28371 */ "DMULImmMacro\000"
10672 /* 28384 */ "BGTULImmMacro\000"
10673 /* 28398 */ "BLTULImmMacro\000"
10674 /* 28412 */ "BGTImmMacro\000"
10675 /* 28424 */ "BLTImmMacro\000"
10676 /* 28436 */ "BGEUImmMacro\000"
10677 /* 28449 */ "BLEUImmMacro\000"
10678 /* 28462 */ "BGTUImmMacro\000"
10679 /* 28475 */ "BLTUImmMacro\000"
10680 /* 28488 */ "DSDivMacro\000"
10681 /* 28499 */ "DUDivMacro\000"
10682 /* 28510 */ "LONG_BRANCH_LUi2Op\000"
10683 /* 28529 */ "LONG_BRANCH_DADDiu2Op\000"
10684 /* 28551 */ "LONG_BRANCH_ADDiu2Op\000"
10685 /* 28572 */ "SelTBtneZCmp\000"
10686 /* 28585 */ "SelTBteqZCmp\000"
10687 /* 28598 */ "SaaAddr\000"
10688 /* 28606 */ "SaadAddr\000"
10689 /* 28615 */ "ERet\000"
10690 /* 28620 */ "SelTBtneZSlt\000"
10691 /* 28633 */ "SelTBteqZSlt\000"
10692 /* 28646 */ "LBu\000"
10693 /* 28650 */ "DSUBu\000"
10694 /* 28656 */ "BADDu\000"
10695 /* 28662 */ "DADDu\000"
10696 /* 28668 */ "LHu\000"
10697 /* 28672 */ "SLTu\000"
10698 /* 28677 */ "PseudoDMULTu\000"
10699 /* 28690 */ "PseudoMULTu\000"
10700 /* 28702 */ "LWu\000"
10701 /* 28706 */ "Ulhu\000"
10702 /* 28711 */ "LONG_BRANCH_DADDiu\000"
10703 /* 28730 */ "LEA_ADDiu\000"
10704 /* 28740 */ "LONG_BRANCH_ADDiu\000"
10705 /* 28758 */ "SLTiu\000"
10706 /* 28764 */ "SelTBtneZSltiu\000"
10707 /* 28779 */ "SelTBteqZSltiu\000"
10708 /* 28794 */ "SelTBtneZSltu\000"
10709 /* 28808 */ "SelTBteqZSltu\000"
10710 /* 28822 */ "Ulw\000"
10711 /* 28826 */ "Usw\000"
10712};
10713#ifdef __GNUC__
10714#pragma GCC diagnostic pop
10715#endif
10716
10717extern const unsigned MipsInstrNameIndices[] = {
10718 15571U, 21120U, 23158U, 21530U, 15923U, 15904U, 15932U, 16184U,
10719 13906U, 13921U, 13786U, 13773U, 13960U, 23872U, 13598U, 25288U,
10720 13804U, 15567U, 15913U, 13273U, 27553U, 13445U, 25192U, 11697U,
10721 13220U, 13261U, 22514U, 16156U, 25102U, 11809U, 22995U, 14023U,
10722 25091U, 13498U, 22745U, 22732U, 23227U, 24898U, 24930U, 16088U,
10723 16135U, 16108U, 15964U, 13589U, 23192U, 22429U, 27574U, 23445U,
10724 22698U, 13646U, 25329U, 25359U, 21347U, 11580U, 10313U, 16340U,
10725 25557U, 25587U, 16441U, 16448U, 16455U, 16465U, 11660U, 23639U,
10726 23602U, 23781U, 25385U, 13784U, 15569U, 27458U, 13608U, 13623U,
10727 16194U, 24860U, 23788U, 25229U, 23805U, 23525U, 11199U, 23855U,
10728 25113U, 23725U, 25261U, 13697U, 23203U, 11778U, 11173U, 11760U,
10729 25151U, 25132U, 21311U, 23252U, 23271U, 11453U, 11397U, 11427U,
10730 11438U, 11378U, 11408U, 13552U, 13536U, 23902U, 13974U, 13991U,
10731 11596U, 10319U, 11666U, 11627U, 23644U, 23608U, 27428U, 21473U,
10732 27411U, 21456U, 11536U, 10285U, 27346U, 21391U, 21227U, 21174U,
10733 22576U, 22554U, 11719U, 24813U, 13253U, 14065U, 11710U, 24879U,
10734 25207U, 11085U, 23950U, 25068U, 23977U, 25343U, 11191U, 25057U,
10735 25045U, 25182U, 14015U, 25322U, 13947U, 25352U, 16049U, 23430U,
10736 23416U, 16042U, 23423U, 23718U, 16241U, 22671U, 22664U, 22678U,
10737 22685U, 24870U, 21587U, 13298U, 21571U, 13245U, 21579U, 13290U,
10738 21563U, 13237U, 22498U, 22490U, 14088U, 14080U, 24731U, 24721U,
10739 24711U, 24701U, 24751U, 24741U, 27490U, 27500U, 24761U, 24774U,
10740 27510U, 27520U, 24787U, 24800U, 11494U, 10264U, 16282U, 8518U,
10741 11371U, 25524U, 16420U, 25777U, 15649U, 23047U, 1223U, 9U,
10742 14008U, 1196U, 0U, 23022U, 23054U, 13835U, 25314U, 11163U,
10743 15597U, 15621U, 22633U, 22642U, 24834U, 24847U, 23768U, 21362U,
10744 23889U, 13706U, 21276U, 21286U, 13347U, 13362U, 21163U, 21216U,
10745 21248U, 21262U, 25617U, 25643U, 25629U, 13306U, 13334U, 13319U,
10746 11586U, 15794U, 21425U, 27380U, 21449U, 27404U, 23775U, 11751U,
10747 11741U, 23146U, 24954U, 13423U, 23506U, 23486U, 24986U, 24965U,
10748 23540U, 23571U, 23557U, 23932U, 27670U, 13755U, 27632U, 13737U,
10749 22724U, 22598U, 13570U, 16055U, 23838U, 21497U, 23845U, 21304U,
10750 23830U, 21489U, 21296U, 1209U, 14635U, 14104U, 14096U, 25238U,
10751 23472U, 25124U, 25169U, 25271U, 23171U, 13432U, 11225U, 13667U,
10752 13521U, 11522U, 10271U, 16310U, 25531U, 16427U, 8524U, 25246U,
10753 23031U, 23291U, 23307U, 27544U, 13474U, 13679U, 24912U, 22506U,
10754 22547U, 22523U, 22535U, 11501U, 16289U, 11477U, 16265U, 27329U,
10755 21374U, 21195U, 21142U, 11564U, 16324U, 11644U, 23624U, 23586U,
10756 27363U, 21408U, 27387U, 21432U, 27472U, 27479U, 28198U, 21546U,
10757 22980U, 21931U, 22015U, 22231U, 4082U, 9404U, 893U, 8760U,
10758 3107U, 9082U, 8388U, 9719U, 3964U, 9244U, 775U, 8600U,
10759 2937U, 8922U, 8276U, 9565U, 4005U, 9299U, 816U, 8655U,
10760 2978U, 8977U, 8315U, 9618U, 4162U, 9512U, 973U, 8868U,
10761 3253U, 9190U, 8464U, 9823U, 4046U, 9354U, 857U, 8710U,
10762 3071U, 9032U, 8354U, 9671U, 3984U, 9271U, 795U, 8627U,
10763 2957U, 8949U, 8295U, 9591U, 4122U, 9458U, 933U, 8814U,
10764 3147U, 9136U, 8426U, 9771U, 3944U, 9217U, 755U, 8573U,
10765 2917U, 8895U, 8257U, 9539U, 4141U, 9484U, 952U, 8840U,
10766 3232U, 9162U, 8444U, 9796U, 4025U, 9326U, 836U, 8682U,
10767 3050U, 9004U, 8334U, 9644U, 4102U, 9431U, 913U, 8787U,
10768 3127U, 9109U, 8407U, 9745U, 4066U, 9381U, 877U, 8737U,
10769 3091U, 9059U, 8373U, 9697U, 9879U, 23151U, 19698U, 28304U,
10770 13390U, 28241U, 15949U, 28265U, 25410U, 28436U, 16248U, 28343U,
10771 24921U, 28412U, 16231U, 28317U, 25479U, 28462U, 16346U, 28384U,
10772 13441U, 28253U, 15954U, 28278U, 25425U, 28449U, 16254U, 28357U,
10773 24961U, 28424U, 16236U, 28330U, 25484U, 28475U, 16352U, 28398U,
10774 28291U, 21629U, 21917U, 21810U, 22110U, 22001U, 22217U, 17890U,
10775 28019U, 28033U, 27947U, 27940U, 4686U, 4233U, 4714U, 4263U,
10776 4744U, 4775U, 4672U, 4218U, 4700U, 4248U, 4728U, 4760U,
10777 2795U, 3565U, 131U, 27558U, 21857U, 22157U, 149U, 1153U,
10778 28371U, 28168U, 28178U, 28207U, 16210U, 27886U, 23481U, 27901U,
10779 28144U, 28488U, 28120U, 28219U, 28156U, 28499U, 28132U, 28230U,
10780 28615U, 2808U, 3581U, 12512U, 26582U, 21595U, 21612U, 21825U,
10781 22125U, 4833U, 21645U, 22301U, 21692U, 22344U, 21840U, 21668U,
10782 22322U, 22140U, 21738U, 22386U, 21715U, 22365U, 21762U, 22408U,
10783 27982U, 27967U, 27995U, 28008U, 6970U, 27693U, 27703U, 28075U,
10784 12441U, 26446U, 3930U, 8232U, 2062U, 22757U, 22842U, 28740U,
10785 28551U, 28711U, 28529U, 27800U, 28510U, 3611U, 19242U, 1121U,
10786 3821U, 1088U, 3633U, 1111U, 3811U, 23330U, 1068U, 23673U,
10787 23347U, 23690U, 1151U, 27444U, 52U, 137U, 22798U, 23659U,
10788 112U, 15575U, 22473U, 1135U, 3850U, 21872U, 22172U, 21895U,
10789 22195U, 27451U, 64U, 155U, 22805U, 23666U, 119U, 15586U,
10790 22484U, 28372U, 28179U, 28208U, 5093U, 5226U, 5125U, 5278U,
10791 22694U, 27894U, 3744U, 21946U, 22030U, 22246U, 21947U, 22031U,
10792 22247U, 10059U, 9961U, 10174U, 14266U, 14161U, 14426U, 25787U,
10793 16390U, 25819U, 16406U, 26872U, 25014U, 28677U, 25545U, 25575U,
10794 15723U, 3166U, 27740U, 3676U, 5338U, 8209U, 20982U, 8003U,
10795 27713U, 3647U, 5308U, 8181U, 11553U, 25392U, 20426U, 18222U,
10796 15543U, 2856U, 18874U, 22456U, 3301U, 19263U, 10302U, 25373U,
10797 20411U, 18153U, 15554U, 2869U, 22882U, 18888U, 25026U, 20390U,
10798 28690U, 21083U, 14195U, 9996U, 27954U, 3835U, 25564U, 388U,
10799 2380U, 15686U, 3007U, 24232U, 644U, 2693U, 15762U, 3211U,
10800 24586U, 559U, 2608U, 15740U, 3185U, 24470U, 13164U, 683U,
10801 24619U, 25594U, 16211U, 27887U, 23482U, 27902U, 9849U, 3915U,
10802 212U, 28045U, 28083U, 28145U, 28489U, 28110U, 28189U, 13394U,
10803 27872U, 3726U, 25415U, 27916U, 3771U, 27909U, 3753U, 27932U,
10804 3791U, 13456U, 27879U, 3735U, 25430U, 27924U, 3781U, 3762U,
10805 3801U, 28100U, 28091U, 21785U, 21976U, 22060U, 22085U, 22276U,
10806 28121U, 28220U, 8244U, 2073U, 22771U, 22857U, 12499U, 26504U,
10807 3937U, 19249U, 21798U, 21989U, 22073U, 22098U, 22289U, 28598U,
10808 28606U, 27685U, 27677U, 28585U, 27830U, 28633U, 27858U, 28779U,
10809 28808U, 28572U, 27816U, 28620U, 27844U, 28764U, 28794U, 5038U,
10810 4497U, 4512U, 5050U, 5265U, 16063U, 13860U, 13842U, 13876U,
10811 13892U, 13935U, 2826U, 9897U, 2018U, 18433U, 6847U, 19173U,
10812 6979U, 22530U, 19294U, 28060U, 28157U, 28500U, 28133U, 28231U,
10813 27761U, 28706U, 28822U, 27765U, 28826U, 21961U, 22045U, 22261U,
10814 14385U, 18689U, 10119U, 1371U, 26800U, 20857U, 11473U, 11260U,
10815 18175U, 6024U, 19374U, 17122U, 17535U, 19546U, 7889U, 14186U,
10816 1474U, 14303U, 1529U, 26543U, 1887U, 26105U, 1859U, 14258U,
10817 18585U, 14365U, 18676U, 26782U, 20845U, 3419U, 11284U, 18186U,
10818 10357U, 11882U, 14670U, 25858U, 10765U, 12681U, 15159U, 26827U,
10819 10957U, 13046U, 15408U, 27176U, 17752U, 5764U, 9987U, 1276U,
10820 10097U, 1339U, 7859U, 14450U, 1617U, 10199U, 18076U, 14405U,
10821 1589U, 10139U, 18023U, 10571U, 12246U, 14855U, 26223U, 11027U,
10822 13127U, 15478U, 27266U, 11317U, 18195U, 10341U, 11865U, 14654U,
10823 25841U, 18229U, 6246U, 27770U, 21006U, 28724U, 21102U, 28657U,
10824 21060U, 21334U, 7037U, 11253U, 6012U, 11640U, 17563U, 5605U,
10825 2196U, 17590U, 5638U, 10446U, 6902U, 18236U, 6255U, 25703U,
10826 27775U, 3699U, 21014U, 11690U, 1431U, 10670U, 12528U, 15008U,
10827 26629U, 10862U, 12893U, 15266U, 27023U, 15617U, 11247U, 6001U,
10828 6930U, 10747U, 12663U, 15132U, 26809U, 10939U, 13028U, 15390U,
10829 27158U, 10695U, 12602U, 15071U, 26703U, 10887U, 12967U, 15329U,
10830 27097U, 4565U, 4441U, 4949U, 4593U, 4390U, 4889U, 4457U,
10831 5252U, 5191U, 17547U, 28656U, 15804U, 11097U, 5880U, 21333U,
10832 1792U, 85U, 231U, 225U, 239U, 11068U, 5545U, 27639U,
10833 6187U, 13732U, 15984U, 18405U, 27606U, 6150U, 24696U, 16225U,
10834 20351U, 27646U, 6200U, 27613U, 6163U, 10507U, 12196U, 14805U,
10835 26173U, 10641U, 12447U, 14979U, 26452U, 5843U, 23063U, 3321U,
10836 11279U, 2113U, 6047U, 16215U, 17797U, 11132U, 5940U, 11341U,
10837 5592U, 2172U, 18213U, 6213U, 19595U, 11071U, 2085U, 5851U,
10838 11295U, 2132U, 6086U, 27596U, 3519U, 15816U, 11108U, 5901U,
10839 16168U, 19867U, 19008U, 11323U, 2148U, 6128U, 16366U, 20943U,
10840 27660U, 3551U, 11140U, 5953U, 11347U, 2180U, 6224U, 16378U,
10841 20966U, 10483U, 12172U, 14781U, 26149U, 10613U, 12295U, 14882U,
10842 26266U, 10537U, 12212U, 14821U, 26189U, 10655U, 12491U, 14993U,
10843 26496U, 25512U, 20490U, 22607U, 7057U, 27601U, 3526U, 11116U,
10844 5914U, 11329U, 2156U, 6139U, 16372U, 20951U, 11290U, 2125U,
10845 6076U, 11301U, 2140U, 6097U, 27665U, 3558U, 15823U, 11148U,
10846 5966U, 16176U, 19878U, 19018U, 11353U, 2188U, 6235U, 16384U,
10847 20974U, 10586U, 25752U, 10579U, 25740U, 13470U, 2789U, 11076U,
10848 2092U, 5861U, 10453U, 12150U, 14759U, 26127U, 10425U, 12129U,
10849 14738U, 26031U, 15959U, 17787U, 11124U, 5927U, 11335U, 5579U,
10850 2164U, 18204U, 6176U, 18336U, 11307U, 6108U, 11062U, 13201U,
10851 15513U, 25746U, 27323U, 11312U, 6118U, 746U, 1951U, 17064U,
10852 15783U, 17618U, 5660U, 18992U, 6959U, 10461U, 25716U, 10555U,
10853 12230U, 14839U, 26207U, 10834U, 12770U, 15238U, 26940U, 11057U,
10854 13187U, 15508U, 25735U, 27318U, 4976U, 4622U, 4988U, 4635U,
10855 4964U, 4609U, 4875U, 5300U, 4799U, 5292U, 4790U, 13402U,
10856 13377U, 18264U, 18290U, 6790U, 8125U, 2475U, 6453U, 24325U,
10857 7437U, 713U, 2756U, 6722U, 20683U, 24645U, 20315U, 7718U,
10858 10492U, 12181U, 14790U, 26158U, 10628U, 12365U, 14905U, 26349U,
10859 101U, 16513U, 17106U, 9860U, 23820U, 1015U, 1048U, 1102U,
10860 12520U, 6595U, 24462U, 7579U, 10703U, 12610U, 15079U, 26711U,
10861 10895U, 12975U, 15337U, 27105U, 10687U, 12594U, 15063U, 26695U,
10862 10879U, 12959U, 15321U, 27089U, 22452U, 19256U, 7048U, 8157U,
10863 10721U, 12628U, 15097U, 26729U, 10913U, 12993U, 15355U, 27123U,
10864 10782U, 12698U, 15176U, 26844U, 10985U, 13074U, 15436U, 27204U,
10865 27628U, 20959U, 7982U, 8174U, 10034U, 1290U, 9936U, 1244U,
10866 10149U, 1386U, 10047U, 17981U, 9949U, 17908U, 10162U, 18036U,
10867 10065U, 17996U, 9967U, 17923U, 10180U, 18051U, 6372U, 7332U,
10868 12425U, 6581U, 14272U, 18596U, 24446U, 7565U, 12121U, 24251U,
10869 12027U, 6343U, 14167U, 18515U, 24177U, 7303U, 12838U, 6654U,
10870 14432U, 18716U, 24547U, 7638U, 12088U, 6357U, 24186U, 7317U,
10871 12378U, 6535U, 24400U, 7519U, 11980U, 6297U, 24131U, 7257U,
10872 12791U, 6608U, 24501U, 7592U, 12404U, 6550U, 24410U, 7534U,
10873 12006U, 6312U, 24141U, 7272U, 12817U, 6623U, 24511U, 7607U,
10874 12338U, 6506U, 24358U, 7490U, 12415U, 6566U, 24429U, 7550U,
10875 12017U, 6328U, 24160U, 7288U, 12828U, 6639U, 24530U, 7623U,
10876 12348U, 6521U, 24375U, 7505U, 10817U, 12753U, 15221U, 26923U,
10877 11009U, 15460U, 27248U, 9874U, 9881U, 11460U, 14057U, 25766U,
10878 11359U, 14040U, 25759U, 126U, 16529U, 17114U, 9867U, 24020U,
10879 19913U, 25793U, 20602U, 16396U, 24030U, 19926U, 25825U, 20615U,
10880 7011U, 2498U, 17320U, 6482U, 24344U, 20120U, 7466U, 3502U,
10881 3469U, 3457U, 549U, 16925U, 2598U, 17408U, 16412U, 7024U,
10882 3278U, 3486U, 26878U, 20869U, 7957U, 736U, 17051U, 2779U,
10883 17522U, 24664U, 20340U, 7747U, 531U, 16901U, 2580U, 17384U,
10884 24439U, 20174U, 380U, 16762U, 2372U, 17272U, 24226U, 20056U,
10885 353U, 16726U, 2345U, 17248U, 24170U, 20026U, 606U, 16977U,
10886 2655U, 17460U, 24540U, 20227U, 312U, 16673U, 2304U, 17195U,
10887 24106U, 19981U, 322U, 16686U, 2314U, 17208U, 24114U, 19992U,
10888 440U, 16813U, 2432U, 17295U, 24290U, 20099U, 576U, 16938U,
10889 2625U, 17421U, 24485U, 20194U, 333U, 16700U, 2325U, 17222U,
10890 24123U, 20004U, 586U, 16951U, 2635U, 17434U, 24493U, 20205U,
10891 511U, 16875U, 2560U, 17358U, 24392U, 20152U, 362U, 16738U,
10892 2354U, 17260U, 24212U, 20036U, 521U, 16888U, 2570U, 17371U,
10893 24421U, 20163U, 343U, 16713U, 2335U, 17235U, 24152U, 20015U,
10894 596U, 16964U, 2645U, 17447U, 24522U, 20216U, 483U, 16838U,
10895 2532U, 17333U, 24368U, 20131U, 5073U, 4912U, 4539U, 11472U,
10896 27769U, 28723U, 28662U, 15538U, 21340U, 15606U, 15616U, 22606U,
10897 22451U, 8156U, 27627U, 8173U, 25519U, 25500U, 24892U, 20359U,
10898 7799U, 25309U, 1058U, 21136U, 25494U, 15525U, 23825U, 21130U,
10899 25473U, 25520U, 25501U, 7910U, 7920U, 10801U, 12737U, 15195U,
10900 26897U, 10993U, 13102U, 15444U, 27232U, 18852U, 6904U, 9855U,
10901 8088U, 18U, 106U, 1174U, 21504U, 24U, 11804U, 25404U,
10902 25037U, 58U, 143U, 1180U, 21517U, 45U, 14643U, 25435U,
10903 16260U, 25020U, 28683U, 25461U, 8148U, 12654U, 15123U, 26764U,
10904 13019U, 15381U, 27149U, 12576U, 15045U, 26677U, 12941U, 15303U,
10905 27071U, 14514U, 1674U, 14589U, 1726U, 26288U, 20693U, 14551U,
10906 18765U, 15874U, 19081U, 23124U, 19670U, 14615U, 1762U, 14494U,
10907 1644U, 22719U, 14528U, 1693U, 14602U, 1744U, 26300U, 20708U,
10908 14577U, 18797U, 12546U, 15026U, 26647U, 12911U, 15284U, 27041U,
10909 15885U, 19095U, 23135U, 19684U, 14625U, 1777U, 14542U, 1712U,
10910 23712U, 1007U, 25691U, 14047U, 25551U, 11612U, 16189U, 993U,
10911 1038U, 25605U, 8568U, 247U, 25506U, 16220U, 1000U, 25611U,
10912 10259U, 28650U, 25581U, 23014U, 13511U, 7129U, 5159U, 5137U,
10913 9893U, 17895U, 5795U, 15530U, 18860U, 6912U, 25041U, 24893U,
10914 11156U, 5979U, 20360U, 7800U, 23018U, 13516U, 7138U, 25310U,
10915 22975U, 22626U, 25677U, 20553U, 19319U, 25685U, 20564U, 19573U,
10916 26609U, 20807U, 26572U, 20781U, 15203U, 18830U, 27303U, 20893U,
10917 26599U, 20794U, 26553U, 20756U, 15141U, 18818U, 26510U, 20734U,
10918 24015U, 1022U, 20404U, 7831U, 540U, 16913U, 2589U, 17396U,
10919 24455U, 20184U, 11929U, 293U, 16648U, 2285U, 17183U, 3381U,
10920 24091U, 19960U, 7245U, 25905U, 12074U, 26010U, 12364U, 26348U,
10921 12519U, 26620U, 11966U, 25942U, 12777U, 26947U, 502U, 16863U,
10922 2551U, 1029U, 17094U, 12036U, 25972U, 12461U, 26466U, 12388U,
10923 26362U, 11990U, 25956U, 12801U, 26961U, 12050U, 25986U, 12324U,
10924 26319U, 13150U, 665U, 17027U, 2714U, 17498U, 24605U, 20269U,
10925 7664U, 27289U, 14897U, 26333U, 11837U, 25811U, 12273U, 26244U,
10926 12475U, 26480U, 12706U, 26852U, 13082U, 27212U, 12282U, 26253U,
10927 12484U, 26489U, 10594U, 12260U, 14863U, 26231U, 11829U, 25803U,
10928 2486U, 6467U, 24334U, 7451U, 724U, 2767U, 6736U, 20723U,
10929 24654U, 20327U, 7732U, 11936U, 25912U, 11891U, 25867U, 13180U,
10930 27311U, 11873U, 25849U, 12317U, 26312U, 674U, 17039U, 2723U,
10931 17510U, 6680U, 24612U, 20279U, 7676U, 11907U, 25883U, 12303U,
10932 450U, 16826U, 2442U, 17308U, 3400U, 24298U, 20110U, 7395U,
10933 26274U, 409U, 16773U, 2401U, 17283U, 24259U, 20065U, 7372U,
10934 15789U, 12357U, 26341U, 12854U, 26984U, 12879U, 27009U, 12081U,
10935 26017U, 12371U, 26355U, 11973U, 25949U, 12784U, 26954U, 12043U,
10936 25979U, 12468U, 26473U, 12871U, 615U, 16989U, 2664U, 17472U,
10937 24563U, 20237U, 27001U, 11900U, 274U, 16623U, 2266U, 17171U,
10938 3371U, 24076U, 19939U, 7233U, 25876U, 12396U, 26370U, 11998U,
10939 25964U, 12809U, 26969U, 12058U, 25994U, 12331U, 26326U, 12716U,
10940 26862U, 13092U, 27222U, 14911U, 26378U, 12556U, 26657U, 12921U,
10941 27051U, 15630U, 6948U, 25303U, 7820U, 12567U, 15036U, 26668U,
10942 12932U, 15294U, 27062U, 12537U, 15017U, 26638U, 12902U, 15275U,
10943 27032U, 16072U, 19185U, 11042U, 13142U, 15493U, 27281U, 10621U,
10944 12310U, 14890U, 26281U, 10402U, 11958U, 14715U, 25934U, 10663U,
10945 12505U, 15001U, 26517U, 23821U, 10848U, 12862U, 15252U, 26992U,
10946 25698U, 10410U, 12066U, 14723U, 26002U, 20582U, 19889U, 7200U,
10947 15781U, 15808U, 23440U, 17694U, 3332U, 5566U, 5804U, 6057U,
10948 17713U, 19896U, 9917U, 2042U, 19787U, 19859U, 27530U, 20920U,
10949 19001U, 11102U, 2105U, 5890U, 11081U, 2099U, 5871U, 23437U,
10950 17686U, 3327U, 22965U, 17554U, 5555U, 7103U, 9911U, 2034U,
10951 8061U, 8096U, 19781U, 18987U, 4883U, 3923U, 4816U, 4808U,
10952 5022U, 4854U, 9925U, 2052U, 13216U, 18243U, 17733U, 27535U,
10953 20928U, 7840U, 17902U, 5818U, 28646U, 3866U, 13722U, 18389U,
10954 21045U, 11620U, 91U, 1966U, 5507U, 459U, 2508U, 1164U,
10955 5425U, 8029U, 1931U, 10440U, 12144U, 14753U, 26121U, 15896U,
10956 11242U, 23184U, 171U, 1980U, 10389U, 11945U, 14702U, 25921U,
10957 28730U, 3885U, 21098U, 14085U, 2846U, 13408U, 18299U, 17762U,
10958 27486U, 20913U, 18463U, 28668U, 3872U, 13727U, 18397U, 21068U,
10959 17610U, 5650U, 16069U, 3273U, 8080U, 11623U, 8118U, 13452U,
10960 18313U, 19179U, 6985U, 8142U, 9856U, 5786U, 8089U, 6939U,
10961 183U, 1996U, 16561U, 27812U, 3720U, 21038U, 25774U, 17771U,
10962 3497U, 161U, 16545U, 1186U, 5487U, 8045U, 1941U, 22812U,
10963 19405U, 13689U, 18375U, 19347U, 16358U, 3289U, 13460U, 18320U,
10964 19228U, 17647U, 5695U, 17076U, 11274U, 6037U, 19581U, 23760U,
10965 3359U, 13560U, 18350U, 19845U, 19557U, 11268U, 20475U, 27540U,
10966 195U, 16579U, 19905U, 20936U, 20590U, 7941U, 28702U, 4292U,
10967 4356U, 4324U, 4373U, 4902U, 4643U, 4528U, 5002U, 4659U,
10968 4409U, 4471U, 11559U, 12106U, 6399U, 24204U, 7359U, 14953U,
10969 26420U, 25398U, 22945U, 19520U, 20432U, 11026U, 13126U, 15477U,
10970 27265U, 303U, 16661U, 2295U, 22833U, 19435U, 18228U, 14926U,
10971 26393U, 24099U, 19971U, 15990U, 19109U, 23364U, 19717U, 16016U,
10972 19141U, 23390U, 19749U, 11858U, 6285U, 24069U, 7221U, 10730U,
10973 12637U, 15106U, 26738U, 10922U, 13002U, 15364U, 27132U, 10366U,
10974 11892U, 14679U, 25868U, 13181U, 6751U, 24672U, 10809U, 12745U,
10975 15213U, 7760U, 26915U, 11001U, 13110U, 15452U, 27240U, 19U,
10976 5363U, 107U, 2202U, 16521U, 5405U, 1175U, 5445U, 25U,
10977 16475U, 5373U, 254U, 16597U, 2211U, 17133U, 5455U, 31U,
10978 16484U, 15549U, 17600U, 2862U, 22873U, 19447U, 18880U, 22462U,
10979 17665U, 3307U, 22908U, 19471U, 19269U, 23707U, 11845U, 6273U,
10980 24062U, 7209U, 10712U, 12619U, 15088U, 26720U, 10904U, 12984U,
10981 15346U, 27114U, 10349U, 11874U, 14662U, 25850U, 12318U, 6495U,
10982 24352U, 10739U, 12646U, 15115U, 7479U, 26756U, 10931U, 13011U,
10983 15373U, 27141U, 11805U, 10257U, 18143U, 25405U, 7869U, 6264U,
10984 10679U, 12586U, 15055U, 26687U, 10871U, 12951U, 15313U, 27081U,
10985 17572U, 5616U, 19329U, 7081U, 25709U, 371U, 16750U, 2363U,
10986 15679U, 2998U, 18947U, 24219U, 20046U, 2240U, 15657U, 2891U,
10987 24040U, 418U, 16785U, 2410U, 15705U, 3028U, 18957U, 24266U,
10988 20075U, 635U, 17015U, 2684U, 15755U, 3202U, 18967U, 24579U,
10989 20259U, 2253U, 15668U, 2904U, 24051U, 429U, 16799U, 2421U,
10990 15714U, 3039U, 18977U, 24275U, 20087U, 10308U, 12098U, 6386U,
10991 24196U, 7346U, 14943U, 26410U, 25379U, 22935U, 19507U, 20417U,
10992 11018U, 13118U, 15469U, 27257U, 284U, 16636U, 2276U, 22824U,
10993 19423U, 18159U, 14917U, 26384U, 24084U, 19950U, 59U, 5395U,
10994 144U, 2231U, 17159U, 16537U, 5415U, 1181U, 5477U, 46U,
10995 16504U, 5384U, 264U, 16610U, 2221U, 17146U, 5466U, 38U,
10996 16494U, 15581U, 2884U, 22899U, 19459U, 18904U, 22657U, 19355U,
10997 22479U, 3314U, 22917U, 19483U, 19286U, 75U, 207U, 1204U,
10998 80U, 220U, 1218U, 23736U, 14644U, 25436U, 7879U, 6882U,
10999 16261U, 16028U, 19156U, 23402U, 19764U, 15830U, 19028U, 23080U,
11000 19617U, 14325U, 18636U, 26589U, 1902U, 14375U, 1559U, 26791U,
11001 1917U, 3429U, 14963U, 26430U, 14563U, 18780U, 14503U, 1658U,
11002 25021U, 22955U, 19533U, 22926U, 19495U, 20396U, 28684U, 21089U,
11003 25456U, 7900U, 11050U, 13157U, 15501U, 27296U, 19221U, 7002U,
11004 14243U, 1501U, 14935U, 26402U, 8149U, 14346U, 1545U, 4868U,
11005 4995U, 4182U, 3905U, 15812U, 10374U, 11915U, 14687U, 25891U,
11006 10381U, 11922U, 14694U, 25898U, 302U, 16660U, 2294U, 24098U,
11007 19970U, 283U, 16635U, 2275U, 24083U, 19949U, 23468U, 3339U,
11008 10523U, 19795U, 7147U, 25723U, 17724U, 5741U, 5063U, 5104U,
11009 23465U, 17705U, 5731U, 3340U, 10524U, 6921U, 19796U, 7148U,
11010 25724U, 27791U, 3707U, 21023U, 5203U, 14233U, 18561U, 13583U,
11011 18366U, 6813U, 11034U, 13134U, 15485U, 27273U, 10394U, 11950U,
11012 14707U, 25926U, 10841U, 12847U, 15245U, 26977U, 14201U, 18528U,
11013 10002U, 17937U, 3391U, 3439U, 22720U, 15859U, 8502U, 17825U,
11014 19063U, 23109U, 8552U, 17862U, 19652U, 16003U, 19125U, 23377U,
11015 19733U, 15845U, 8487U, 17807U, 19046U, 23095U, 8537U, 17844U,
11016 19635U, 14145U, 18496U, 26053U, 20650U, 14120U, 18480U, 26082U,
11017 20665U, 14133U, 1443U, 26038U, 1804U, 26065U, 1824U, 13799U,
11018 13384U, 18274U, 20904U, 18413U, 6824U, 8134U, 11682U, 1418U,
11019 3410U, 3448U, 10243U, 18123U, 22786U, 19387U, 23754U, 3351U,
11020 19836U, 7189U, 7165U, 492U, 16850U, 2541U, 17345U, 24384U,
11021 20141U, 14476U, 18753U, 10225U, 18099U, 14217U, 18550U, 10018U,
11022 17959U, 12855U, 6668U, 24556U, 7652U, 23713U, 25692U, 20573U,
11023 19809U, 2463U, 6438U, 24315U, 7422U, 701U, 2744U, 6707U,
11024 20639U, 24635U, 20302U, 7703U, 625U, 17002U, 2674U, 17485U,
11025 24571U, 20248U, 4823U, 4199U, 8483U, 11366U, 10774U, 12690U,
11026 15168U, 26836U, 10977U, 13066U, 15428U, 27196U, 10254U, 17546U,
11027 5535U, 2057U, 13233U, 18250U, 18137U, 5826U, 11287U, 2120U,
11028 8072U, 11468U, 8111U, 13286U, 18257U, 18189U, 6068U, 8105U,
11029 11826U, 22615U, 17675U, 5717U, 19302U, 7070U, 8164U, 96U,
11030 1973U, 5521U, 471U, 2520U, 1169U, 5435U, 8037U, 1936U,
11031 25552U, 20500U, 15900U, 23188U, 177U, 1988U, 9889U, 2012U,
11032 17888U, 14076U, 2840U, 18456U, 27653U, 3542U, 13207U, 6776U,
11033 7991U, 24687U, 7785U, 27620U, 3533U, 13192U, 6762U, 7970U,
11034 24678U, 7771U, 12254U, 6412U, 24284U, 7384U, 23067U, 27785U,
11035 14640U, 17582U, 5628U, 2851U, 13412U, 18306U, 10419U, 14732U,
11036 26025U, 22467U, 25670U, 20543U, 19277U, 14467U, 18741U, 10216U,
11037 18087U, 14415U, 18702U, 26905U, 20880U, 14209U, 18539U, 10010U,
11038 17948U, 14336U, 18650U, 26747U, 20821U, 14458U, 18729U, 10207U,
11039 1404U, 14314U, 18622U, 10108U, 1355U, 26562U, 20768U, 14112U,
11040 18469U, 9928U, 1231U, 14282U, 18609U, 10076U, 1308U, 26524U,
11041 20744U, 14485U, 1630U, 10234U, 18111U, 14225U, 1488U, 10026U,
11042 17970U, 18812U, 6874U, 13416U, 6801U, 10439U, 12143U, 14752U,
11043 26120U, 10388U, 11944U, 14701U, 25920U, 16190U, 17629U, 5673U,
11044 1039U, 3602U, 10469U, 12158U, 14767U, 26135U, 25606U, 20516U,
11045 10601U, 12267U, 14870U, 19207U, 6993U, 26238U, 25006U, 3480U,
11046 20376U, 27795U, 3713U, 21030U, 28758U, 3897U, 21111U, 28672U,
11047 3878U, 21075U, 13490U, 27780U, 10546U, 12221U, 14830U, 26198U,
11048 10826U, 12762U, 15230U, 26932U, 8569U, 10432U, 12136U, 14745U,
11049 26113U, 10499U, 12188U, 14797U, 26165U, 10634U, 12434U, 14972U,
11050 26439U, 25507U, 20482U, 10335U, 11852U, 14648U, 17881U, 25835U,
11051 16221U, 17638U, 5684U, 10476U, 12165U, 14774U, 26142U, 10515U,
11052 12204U, 14813U, 26181U, 10648U, 12454U, 14986U, 26459U, 25612U,
11053 20524U, 10607U, 12289U, 14876U, 19214U, 26260U, 22692U, 19365U,
11054 7092U, 10857U, 12888U, 15261U, 27018U, 10260U, 14177U, 1460U,
11055 14292U, 1513U, 26533U, 1872U, 26097U, 1846U, 14250U, 18574U,
11056 14355U, 18663U, 26773U, 20833U, 10966U, 13055U, 15417U, 27185U,
11057 10790U, 12726U, 15184U, 26886U, 10756U, 12672U, 15150U, 26818U,
11058 10948U, 13037U, 15399U, 27167U, 17742U, 5752U, 9978U, 1262U,
11059 10086U, 1323U, 7849U, 14442U, 1604U, 10191U, 18065U, 14395U,
11060 1574U, 10129U, 18010U, 10563U, 12238U, 14847U, 26215U, 11019U,
11061 13119U, 15470U, 27258U, 18146U, 5834U, 28651U, 21052U, 189U,
11062 2004U, 16570U, 25784U, 17779U, 5776U, 3514U, 166U, 16553U,
11063 1191U, 5497U, 8053U, 1946U, 22818U, 19414U, 13693U, 18382U,
11064 16362U, 3295U, 13465U, 18328U, 19235U, 17656U, 5706U, 17085U,
11065 19588U, 23764U, 3365U, 13565U, 18358U, 19852U, 19565U, 7119U,
11066 201U, 16588U, 20596U, 7949U, 11220U, 15519U, 18843U, 6891U,
11067 18167U, 5991U, 16080U, 19196U, 4847U, 4210U, 4308U, 5014U,
11068 5030U, 4340U, 4278U, 5169U, 5083U, 4924U, 4552U, 4936U,
11069 4579U, 5114U, 4192U, 5148U, 4285U, 5180U, 5239U, 4425U,
11070 4484U, 23071U, 15592U, 18912U, 19602U, 13398U, 15528U, 25441U,
11071 20449U, 18858U, 25420U, 20441U, 18283U, 25662U, 13826U, 18421U,
11072 20532U, 22651U, 19338U, 23324U, 19708U, 15642U, 18937U, 23747U,
11073 19826U, 25655U, 13818U, 6834U, 7929U, 22621U, 19311U, 23075U,
11074 19609U, 15636U, 18928U, 23741U, 19817U, 25010U, 15611U, 20458U,
11075 18920U, 25489U, 20467U, 20383U, 13494U, 15533U, 18866U, 18343U,
11076 2451U, 6423U, 24305U, 7407U, 689U, 2732U, 6692U, 20628U,
11077 24625U, 20289U, 7688U, 25447U, 25582U, 20508U, 25454U, 70U,
11078 25467U, 10418U, 12114U, 14731U, 26024U, 24925U, 20368U, 7810U,
11079 22792U, 19396U, 7177U, 14052U, 18448U, 6864U, 23598U, 17704U,
11080 5730U, 3345U, 10530U, 6920U, 19802U, 7156U, 25729U, 27790U,
11081 3706U, 21022U, 5214U, 11617U,
11082};
11083
11084static inline void InitMipsMCInstrInfo(MCInstrInfo *II) {
11085 II->InitMCInstrInfo(MipsDescs.Insts, MipsInstrNameIndices, MipsInstrNameData, nullptr, nullptr, 2908);
11086}
11087
11088} // end namespace llvm
11089#endif // GET_INSTRINFO_MC_DESC
11090
11091#ifdef GET_INSTRINFO_HEADER
11092#undef GET_INSTRINFO_HEADER
11093namespace llvm {
11094struct MipsGenInstrInfo : public TargetInstrInfo {
11095 explicit MipsGenInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
11096 ~MipsGenInstrInfo() override = default;
11097
11098};
11099} // end namespace llvm
11100#endif // GET_INSTRINFO_HEADER
11101
11102#ifdef GET_INSTRINFO_HELPER_DECLS
11103#undef GET_INSTRINFO_HELPER_DECLS
11104
11105
11106#endif // GET_INSTRINFO_HELPER_DECLS
11107
11108#ifdef GET_INSTRINFO_HELPERS
11109#undef GET_INSTRINFO_HELPERS
11110
11111#endif // GET_INSTRINFO_HELPERS
11112
11113#ifdef GET_INSTRINFO_CTOR_DTOR
11114#undef GET_INSTRINFO_CTOR_DTOR
11115namespace llvm {
11116extern const MipsInstrTable MipsDescs;
11117extern const unsigned MipsInstrNameIndices[];
11118extern const char MipsInstrNameData[];
11119MipsGenInstrInfo::MipsGenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
11120 : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
11121 InitMCInstrInfo(MipsDescs.Insts, MipsInstrNameIndices, MipsInstrNameData, nullptr, nullptr, 2908);
11122}
11123} // end namespace llvm
11124#endif // GET_INSTRINFO_CTOR_DTOR
11125
11126#ifdef GET_INSTRINFO_MC_HELPER_DECLS
11127#undef GET_INSTRINFO_MC_HELPER_DECLS
11128
11129namespace llvm {
11130class MCInst;
11131class FeatureBitset;
11132
11133namespace Mips_MC {
11134
11135void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
11136
11137} // end namespace Mips_MC
11138} // end namespace llvm
11139
11140#endif // GET_INSTRINFO_MC_HELPER_DECLS
11141
11142#ifdef GET_INSTRINFO_MC_HELPERS
11143#undef GET_INSTRINFO_MC_HELPERS
11144
11145namespace llvm::Mips_MC {
11146} // end namespace llvm::Mips_MC
11147#endif // GET_GENISTRINFO_MC_HELPERS
11148
11149#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
11150 defined(GET_AVAILABLE_OPCODE_CHECKER)
11151#define GET_COMPUTE_FEATURES
11152#endif
11153#ifdef GET_COMPUTE_FEATURES
11154#undef GET_COMPUTE_FEATURES
11155namespace llvm::Mips_MC {
11156// Bits for subtarget features that participate in instruction matching.
11157enum SubtargetFeatureBits : uint8_t {
11158 Feature_HasMips2Bit = 11,
11159 Feature_HasMips3_32Bit = 14,
11160 Feature_HasMips3_32r2Bit = 15,
11161 Feature_HasMips3Bit = 12,
11162 Feature_NotMips3Bit = 47,
11163 Feature_HasMips4_32Bit = 16,
11164 Feature_NotMips4_32Bit = 48,
11165 Feature_HasMips4_32r2Bit = 17,
11166 Feature_HasMips5_32r2Bit = 18,
11167 Feature_HasMips32Bit = 19,
11168 Feature_HasMips32r2Bit = 20,
11169 Feature_HasMips32r5Bit = 21,
11170 Feature_HasMips32r6Bit = 22,
11171 Feature_NotMips32r6Bit = 49,
11172 Feature_IsGP64bitBit = 33,
11173 Feature_IsGP32bitBit = 32,
11174 Feature_IsPTR64bitBit = 37,
11175 Feature_IsPTR32bitBit = 36,
11176 Feature_HasMips64Bit = 23,
11177 Feature_NotMips64Bit = 50,
11178 Feature_HasMips64r2Bit = 24,
11179 Feature_HasMips64r5Bit = 25,
11180 Feature_HasMips64r6Bit = 26,
11181 Feature_NotMips64r6Bit = 51,
11182 Feature_InMips16ModeBit = 30,
11183 Feature_NotInMips16ModeBit = 46,
11184 Feature_HasCnMipsBit = 1,
11185 Feature_NotCnMipsBit = 42,
11186 Feature_HasCnMipsPBit = 2,
11187 Feature_NotCnMipsPBit = 43,
11188 Feature_IsSym32Bit = 39,
11189 Feature_IsSym64Bit = 40,
11190 Feature_HasStdEncBit = 27,
11191 Feature_InMicroMipsBit = 29,
11192 Feature_NotInMicroMipsBit = 45,
11193 Feature_HasEVABit = 6,
11194 Feature_HasMSABit = 8,
11195 Feature_HasMadd4Bit = 10,
11196 Feature_HasMTBit = 9,
11197 Feature_UseIndirectJumpsHazardBit = 52,
11198 Feature_NoIndirectJumpGuardsBit = 41,
11199 Feature_HasCRCBit = 0,
11200 Feature_HasVirtBit = 28,
11201 Feature_HasGINVBit = 7,
11202 Feature_IsFP64bitBit = 31,
11203 Feature_NotFP64bitBit = 44,
11204 Feature_IsSingleFloatBit = 38,
11205 Feature_IsNotSingleFloatBit = 34,
11206 Feature_IsNotSoftFloatBit = 35,
11207 Feature_HasMips3DBit = 13,
11208 Feature_HasDSPBit = 3,
11209 Feature_HasDSPR2Bit = 4,
11210 Feature_HasDSPR3Bit = 5,
11211};
11212
11213inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
11214 FeatureBitset Features;
11215 if (FB[Mips::FeatureMips2])
11216 Features.set(Feature_HasMips2Bit);
11217 if (FB[Mips::FeatureMips3_32])
11218 Features.set(Feature_HasMips3_32Bit);
11219 if (FB[Mips::FeatureMips3_32r2])
11220 Features.set(Feature_HasMips3_32r2Bit);
11221 if (FB[Mips::FeatureMips3])
11222 Features.set(Feature_HasMips3Bit);
11223 if (!FB[Mips::FeatureMips3])
11224 Features.set(Feature_NotMips3Bit);
11225 if (FB[Mips::FeatureMips4_32])
11226 Features.set(Feature_HasMips4_32Bit);
11227 if (!FB[Mips::FeatureMips4_32])
11228 Features.set(Feature_NotMips4_32Bit);
11229 if (FB[Mips::FeatureMips4_32r2])
11230 Features.set(Feature_HasMips4_32r2Bit);
11231 if (FB[Mips::FeatureMips5_32r2])
11232 Features.set(Feature_HasMips5_32r2Bit);
11233 if (FB[Mips::FeatureMips32])
11234 Features.set(Feature_HasMips32Bit);
11235 if (FB[Mips::FeatureMips32r2])
11236 Features.set(Feature_HasMips32r2Bit);
11237 if (FB[Mips::FeatureMips32r5])
11238 Features.set(Feature_HasMips32r5Bit);
11239 if (FB[Mips::FeatureMips32r6])
11240 Features.set(Feature_HasMips32r6Bit);
11241 if (!FB[Mips::FeatureMips32r6])
11242 Features.set(Feature_NotMips32r6Bit);
11243 if (FB[Mips::FeatureGP64Bit])
11244 Features.set(Feature_IsGP64bitBit);
11245 if (!FB[Mips::FeatureGP64Bit])
11246 Features.set(Feature_IsGP32bitBit);
11247 if (FB[Mips::FeaturePTR64Bit])
11248 Features.set(Feature_IsPTR64bitBit);
11249 if (!FB[Mips::FeaturePTR64Bit])
11250 Features.set(Feature_IsPTR32bitBit);
11251 if (FB[Mips::FeatureMips64])
11252 Features.set(Feature_HasMips64Bit);
11253 if (!FB[Mips::FeatureMips64])
11254 Features.set(Feature_NotMips64Bit);
11255 if (FB[Mips::FeatureMips64r2])
11256 Features.set(Feature_HasMips64r2Bit);
11257 if (FB[Mips::FeatureMips64r5])
11258 Features.set(Feature_HasMips64r5Bit);
11259 if (FB[Mips::FeatureMips64r6])
11260 Features.set(Feature_HasMips64r6Bit);
11261 if (!FB[Mips::FeatureMips64r6])
11262 Features.set(Feature_NotMips64r6Bit);
11263 if (FB[Mips::FeatureMips16])
11264 Features.set(Feature_InMips16ModeBit);
11265 if (!FB[Mips::FeatureMips16])
11266 Features.set(Feature_NotInMips16ModeBit);
11267 if (FB[Mips::FeatureCnMips])
11268 Features.set(Feature_HasCnMipsBit);
11269 if (!FB[Mips::FeatureCnMips])
11270 Features.set(Feature_NotCnMipsBit);
11271 if (FB[Mips::FeatureCnMipsP])
11272 Features.set(Feature_HasCnMipsPBit);
11273 if (!FB[Mips::FeatureCnMipsP])
11274 Features.set(Feature_NotCnMipsPBit);
11275 if (FB[Mips::FeatureSym32])
11276 Features.set(Feature_IsSym32Bit);
11277 if (!FB[Mips::FeatureSym32])
11278 Features.set(Feature_IsSym64Bit);
11279 if (!FB[Mips::FeatureMips16])
11280 Features.set(Feature_HasStdEncBit);
11281 if (FB[Mips::FeatureMicroMips])
11282 Features.set(Feature_InMicroMipsBit);
11283 if (!FB[Mips::FeatureMicroMips])
11284 Features.set(Feature_NotInMicroMipsBit);
11285 if (FB[Mips::FeatureEVA])
11286 Features.set(Feature_HasEVABit);
11287 if (FB[Mips::FeatureMSA])
11288 Features.set(Feature_HasMSABit);
11289 if (!FB[Mips::FeatureNoMadd4])
11290 Features.set(Feature_HasMadd4Bit);
11291 if (FB[Mips::FeatureMT])
11292 Features.set(Feature_HasMTBit);
11293 if (FB[Mips::FeatureUseIndirectJumpsHazard])
11294 Features.set(Feature_UseIndirectJumpsHazardBit);
11295 if (!FB[Mips::FeatureUseIndirectJumpsHazard])
11296 Features.set(Feature_NoIndirectJumpGuardsBit);
11297 if (FB[Mips::FeatureCRC])
11298 Features.set(Feature_HasCRCBit);
11299 if (FB[Mips::FeatureVirt])
11300 Features.set(Feature_HasVirtBit);
11301 if (FB[Mips::FeatureGINV])
11302 Features.set(Feature_HasGINVBit);
11303 if (FB[Mips::FeatureFP64Bit])
11304 Features.set(Feature_IsFP64bitBit);
11305 if (!FB[Mips::FeatureFP64Bit])
11306 Features.set(Feature_NotFP64bitBit);
11307 if (FB[Mips::FeatureSingleFloat])
11308 Features.set(Feature_IsSingleFloatBit);
11309 if (!FB[Mips::FeatureSingleFloat])
11310 Features.set(Feature_IsNotSingleFloatBit);
11311 if (!FB[Mips::FeatureSoftFloat])
11312 Features.set(Feature_IsNotSoftFloatBit);
11313 if (FB[Mips::FeatureMips3D])
11314 Features.set(Feature_HasMips3DBit);
11315 if (FB[Mips::FeatureDSP])
11316 Features.set(Feature_HasDSPBit);
11317 if (FB[Mips::FeatureDSPR2])
11318 Features.set(Feature_HasDSPR2Bit);
11319 if (FB[Mips::FeatureDSPR3])
11320 Features.set(Feature_HasDSPR3Bit);
11321 return Features;
11322}
11323
11324inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
11325 enum : uint8_t {
11326 CEFBS_None,
11327 CEFBS_HasCnMips,
11328 CEFBS_HasCnMipsP,
11329 CEFBS_HasDSP,
11330 CEFBS_HasDSPR2,
11331 CEFBS_HasMSA,
11332 CEFBS_HasMT,
11333 CEFBS_InMicroMips,
11334 CEFBS_InMips16Mode,
11335 CEFBS_IsGP32bit,
11336 CEFBS_IsGP64bit,
11337 CEFBS_IsNotSoftFloat,
11338 CEFBS_NotCnMips,
11339 CEFBS_NotInMips16Mode,
11340 CEFBS_HasDSP_NotInMicroMips,
11341 CEFBS_HasStdEnc_HasMSA,
11342 CEFBS_HasStdEnc_HasMips32,
11343 CEFBS_HasStdEnc_HasMips32r6,
11344 CEFBS_HasStdEnc_HasMips64,
11345 CEFBS_HasStdEnc_HasMips64r6,
11346 CEFBS_HasStdEnc_IsNotSoftFloat,
11347 CEFBS_HasStdEnc_NotInMicroMips,
11348 CEFBS_HasStdEnc_NotMips3,
11349 CEFBS_HasStdEnc_NotMips4_32,
11350 CEFBS_InMicroMips_HasDSP,
11351 CEFBS_InMicroMips_HasDSPR2,
11352 CEFBS_InMicroMips_HasDSPR3,
11353 CEFBS_InMicroMips_HasEVA,
11354 CEFBS_InMicroMips_HasMips32r6,
11355 CEFBS_InMicroMips_IsNotSoftFloat,
11356 CEFBS_InMicroMips_NotMips32r6,
11357 CEFBS_IsFP64bit_IsNotSoftFloat,
11358 CEFBS_IsGP32bit_NotInMicroMips,
11359 CEFBS_NotFP64bit_IsNotSoftFloat,
11360 CEFBS_NotInMips16Mode_HasDSP,
11361 CEFBS_NotInMips16Mode_IsGP64bit,
11362 CEFBS_NotInMips16Mode_IsNotSoftFloat,
11363 CEFBS_NotInMips16Mode_IsPTR64bit,
11364 CEFBS_HasMips3_NotMips64r6_NotCnMips,
11365 CEFBS_HasMips64_HasCnMips_NotInMicroMips,
11366 CEFBS_HasStdEnc_HasMSA_HasMips64,
11367 CEFBS_HasStdEnc_HasMT_NotInMicroMips,
11368 CEFBS_HasStdEnc_HasMips2_NotInMicroMips,
11369 CEFBS_HasStdEnc_HasMips3_NotInMicroMips,
11370 CEFBS_HasStdEnc_HasMips32_NotInMicroMips,
11371 CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips,
11372 CEFBS_HasStdEnc_HasMips32r5_NotInMicroMips,
11373 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips,
11374 CEFBS_HasStdEnc_HasMips3_32_NotInMicroMips,
11375 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips,
11376 CEFBS_HasStdEnc_HasMips64r5_HasVirt,
11377 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips,
11378 CEFBS_HasStdEnc_IsFP64bit_NotMips4_32,
11379 CEFBS_HasStdEnc_IsGP64bit_HasMips3,
11380 CEFBS_HasStdEnc_IsGP64bit_HasMips32r2,
11381 CEFBS_HasStdEnc_IsGP64bit_HasMips32r6,
11382 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6,
11383 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
11384 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat,
11385 CEFBS_HasStdEnc_NotFP64bit_NotMips4_32,
11386 CEFBS_HasStdEnc_NotInMicroMips_NoIndirectJumpGuards,
11387 CEFBS_HasStdEnc_NotInMips16Mode_NotInMicroMips,
11388 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6,
11389 CEFBS_InMicroMips_HasMips32r5_HasVirt,
11390 CEFBS_InMicroMips_HasMips32r6_HasGINV,
11391 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat,
11392 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat,
11393 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat,
11394 CEFBS_InMicroMips_NotMips32r6_HasDSP,
11395 CEFBS_InMicroMips_NotMips32r6_HasEVA,
11396 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat,
11397 CEFBS_InMicroMips_NotMips32r6_NotMips64r6,
11398 CEFBS_NotInMips16Mode_IsFP64bit_IsNotSoftFloat,
11399 CEFBS_NotInMips16Mode_IsGP64bit_NotInMicroMips,
11400 CEFBS_NotInMips16Mode_IsPTR64bit_NoIndirectJumpGuards,
11401 CEFBS_NotInMips16Mode_IsPTR64bit_NotInMicroMips,
11402 CEFBS_NotInMips16Mode_IsPTR64bit_UseIndirectJumpsHazard,
11403 CEFBS_NotInMips16Mode_NotFP64bit_IsNotSoftFloat,
11404 CEFBS_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard,
11405 CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips,
11406 CEFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips,
11407 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6,
11408 CEFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips,
11409 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6,
11410 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6,
11411 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips,
11412 CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6,
11413 CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips,
11414 CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips,
11415 CEFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips,
11416 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips,
11417 CEFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips,
11418 CEFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips,
11419 CEFBS_HasStdEnc_HasMips64_NotMips64r6_NotInMicroMips,
11420 CEFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips,
11421 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips,
11422 CEFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips,
11423 CEFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips,
11424 CEFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips,
11425 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips,
11426 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips,
11427 CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat,
11428 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat,
11429 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat,
11430 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4,
11431 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips,
11432 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips,
11433 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips,
11434 CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards,
11435 CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard,
11436 CEFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips,
11437 CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips,
11438 CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat,
11439 CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards,
11440 CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard,
11441 CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips,
11442 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips,
11443 CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips,
11444 CEFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips,
11445 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips,
11446 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat,
11447 CEFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips,
11448 CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips,
11449 CEFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips,
11450 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips,
11451 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
11452 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips,
11453 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4,
11454 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
11455 CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips,
11456 CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
11457 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat,
11458 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
11459 CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips,
11460 CEFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips,
11461 CEFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips,
11462 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
11463 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards,
11464 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards,
11465 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard,
11466 CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard,
11467 CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips,
11468 CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4,
11469 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D,
11470 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
11471 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
11472 CEFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
11473 CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
11474 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
11475 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
11476 CEFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
11477 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips,
11478 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4,
11479 CEFBS_HasStdEnc_IsGP64bit_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
11480 CEFBS_HasStdEnc_IsPTR64bit_HasMips3_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards,
11481 CEFBS_HasStdEnc_IsPTR64bit_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard,
11482 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips,
11483 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4,
11484 };
11485
11486 static constexpr FeatureBitset FeatureBitsets[] = {
11487 {}, // CEFBS_None
11488 {Feature_HasCnMipsBit, },
11489 {Feature_HasCnMipsPBit, },
11490 {Feature_HasDSPBit, },
11491 {Feature_HasDSPR2Bit, },
11492 {Feature_HasMSABit, },
11493 {Feature_HasMTBit, },
11494 {Feature_InMicroMipsBit, },
11495 {Feature_InMips16ModeBit, },
11496 {Feature_IsGP32bitBit, },
11497 {Feature_IsGP64bitBit, },
11498 {Feature_IsNotSoftFloatBit, },
11499 {Feature_NotCnMipsBit, },
11500 {Feature_NotInMips16ModeBit, },
11501 {Feature_HasDSPBit, Feature_NotInMicroMipsBit, },
11502 {Feature_HasStdEncBit, Feature_HasMSABit, },
11503 {Feature_HasStdEncBit, Feature_HasMips32Bit, },
11504 {Feature_HasStdEncBit, Feature_HasMips32r6Bit, },
11505 {Feature_HasStdEncBit, Feature_HasMips64Bit, },
11506 {Feature_HasStdEncBit, Feature_HasMips64r6Bit, },
11507 {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, },
11508 {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
11509 {Feature_HasStdEncBit, Feature_NotMips3Bit, },
11510 {Feature_HasStdEncBit, Feature_NotMips4_32Bit, },
11511 {Feature_InMicroMipsBit, Feature_HasDSPBit, },
11512 {Feature_InMicroMipsBit, Feature_HasDSPR2Bit, },
11513 {Feature_InMicroMipsBit, Feature_HasDSPR3Bit, },
11514 {Feature_InMicroMipsBit, Feature_HasEVABit, },
11515 {Feature_InMicroMipsBit, Feature_HasMips32r6Bit, },
11516 {Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, },
11517 {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, },
11518 {Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, },
11519 {Feature_IsGP32bitBit, Feature_NotInMicroMipsBit, },
11520 {Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, },
11521 {Feature_NotInMips16ModeBit, Feature_HasDSPBit, },
11522 {Feature_NotInMips16ModeBit, Feature_IsGP64bitBit, },
11523 {Feature_NotInMips16ModeBit, Feature_IsNotSoftFloatBit, },
11524 {Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, },
11525 {Feature_HasMips3Bit, Feature_NotMips64r6Bit, Feature_NotCnMipsBit, },
11526 {Feature_HasMips64Bit, Feature_HasCnMipsBit, Feature_NotInMicroMipsBit, },
11527 {Feature_HasStdEncBit, Feature_HasMSABit, Feature_HasMips64Bit, },
11528 {Feature_HasStdEncBit, Feature_HasMTBit, Feature_NotInMicroMipsBit, },
11529 {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotInMicroMipsBit, },
11530 {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotInMicroMipsBit, },
11531 {Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotInMicroMipsBit, },
11532 {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotInMicroMipsBit, },
11533 {Feature_HasStdEncBit, Feature_HasMips32r5Bit, Feature_NotInMicroMipsBit, },
11534 {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_NotInMicroMipsBit, },
11535 {Feature_HasStdEncBit, Feature_HasMips3_32Bit, Feature_NotInMicroMipsBit, },
11536 {Feature_HasStdEncBit, Feature_HasMips64r2Bit, Feature_NotInMicroMipsBit, },
11537 {Feature_HasStdEncBit, Feature_HasMips64r5Bit, Feature_HasVirtBit, },
11538 {Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_NotInMicroMipsBit, },
11539 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotMips4_32Bit, },
11540 {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips3Bit, },
11541 {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips32r2Bit, },
11542 {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips32r6Bit, },
11543 {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips64r6Bit, },
11544 {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
11545 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, },
11546 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotMips4_32Bit, },
11547 {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, },
11548 {Feature_HasStdEncBit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, },
11549 {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
11550 {Feature_InMicroMipsBit, Feature_HasMips32r5Bit, Feature_HasVirtBit, },
11551 {Feature_InMicroMipsBit, Feature_HasMips32r6Bit, Feature_HasGINVBit, },
11552 {Feature_InMicroMipsBit, Feature_HasMips32r6Bit, Feature_IsNotSoftFloatBit, },
11553 {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, },
11554 {Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, },
11555 {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_HasDSPBit, },
11556 {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_HasEVABit, },
11557 {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, },
11558 {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
11559 {Feature_NotInMips16ModeBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, },
11560 {Feature_NotInMips16ModeBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, },
11561 {Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, Feature_NoIndirectJumpGuardsBit, },
11562 {Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, Feature_NotInMicroMipsBit, },
11563 {Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, Feature_UseIndirectJumpsHazardBit, },
11564 {Feature_NotInMips16ModeBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, },
11565 {Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, },
11566 {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
11567 {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotCnMipsBit, Feature_NotInMicroMipsBit, },
11568 {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
11569 {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
11570 {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
11571 {Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
11572 {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_HasEVABit, Feature_NotInMicroMipsBit, },
11573 {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
11574 {Feature_HasStdEncBit, Feature_HasMips32r5Bit, Feature_HasVirtBit, Feature_NotInMicroMipsBit, },
11575 {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_HasCRCBit, Feature_NotInMicroMipsBit, },
11576 {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_HasGINVBit, Feature_NotInMicroMipsBit, },
11577 {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
11578 {Feature_HasStdEncBit, Feature_HasMips3_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
11579 {Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
11580 {Feature_HasStdEncBit, Feature_HasMips64Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },
11581 {Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_HasCRCBit, Feature_NotInMicroMipsBit, },
11582 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
11583 {Feature_HasStdEncBit, Feature_IsGP32bitBit, Feature_HasMips32r6Bit, Feature_NotInMicroMipsBit, },
11584 {Feature_HasStdEncBit, Feature_IsPTR32bitBit, Feature_HasMips32r6Bit, Feature_NotInMicroMipsBit, },
11585 {Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips64r6Bit, Feature_NotInMicroMipsBit, },
11586 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
11587 {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },
11588 {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_HasMips32r6Bit, Feature_IsNotSoftFloatBit, },
11589 {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, },
11590 {Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, },
11591 {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, },
11592 {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },
11593 {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },
11594 {Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },
11595 {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, },
11596 {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, },
11597 {Feature_HasStdEncBit, Feature_HasMips3_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },
11598 {Feature_HasStdEncBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },
11599 {Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, },
11600 {Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, },
11601 {Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, },
11602 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
11603 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
11604 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips3_32Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
11605 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips3_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
11606 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
11607 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, },
11608 {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips64Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },
11609 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
11610 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
11611 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
11612 {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
11613 {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotCnMipsBit, Feature_NotInMicroMipsBit, },
11614 {Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, },
11615 {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
11616 {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_HasEVABit, Feature_NotInMicroMipsBit, },
11617 {Feature_HasStdEncBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
11618 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, },
11619 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
11620 {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },
11621 {Feature_HasStdEncBit, Feature_IsPTR32bitBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },
11622 {Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },
11623 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
11624 {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, },
11625 {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, },
11626 {Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, },
11627 {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, },
11628 {Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, Feature_NotInMicroMipsBit, },
11629 {Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_HasMadd4Bit, },
11630 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMips3DBit, },
11631 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
11632 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
11633 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips5_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
11634 {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
11635 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
11636 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
11637 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips5_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
11638 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, Feature_NotInMicroMipsBit, },
11639 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_HasMadd4Bit, },
11640 {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_IsFP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
11641 {Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, },
11642 {Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, },
11643 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, Feature_NotInMicroMipsBit, },
11644 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_HasMadd4Bit, },
11645 };
11646 static constexpr uint8_t RequiredFeaturesRefs[] = {
11647 CEFBS_None, // PHI = 0
11648 CEFBS_None, // INLINEASM = 1
11649 CEFBS_None, // INLINEASM_BR = 2
11650 CEFBS_None, // CFI_INSTRUCTION = 3
11651 CEFBS_None, // EH_LABEL = 4
11652 CEFBS_None, // GC_LABEL = 5
11653 CEFBS_None, // ANNOTATION_LABEL = 6
11654 CEFBS_None, // KILL = 7
11655 CEFBS_None, // EXTRACT_SUBREG = 8
11656 CEFBS_None, // INSERT_SUBREG = 9
11657 CEFBS_None, // IMPLICIT_DEF = 10
11658 CEFBS_None, // INIT_UNDEF = 11
11659 CEFBS_None, // SUBREG_TO_REG = 12
11660 CEFBS_None, // COPY_TO_REGCLASS = 13
11661 CEFBS_None, // DBG_VALUE = 14
11662 CEFBS_None, // DBG_VALUE_LIST = 15
11663 CEFBS_None, // DBG_INSTR_REF = 16
11664 CEFBS_None, // DBG_PHI = 17
11665 CEFBS_None, // DBG_LABEL = 18
11666 CEFBS_None, // REG_SEQUENCE = 19
11667 CEFBS_None, // COPY = 20
11668 CEFBS_None, // BUNDLE = 21
11669 CEFBS_None, // LIFETIME_START = 22
11670 CEFBS_None, // LIFETIME_END = 23
11671 CEFBS_None, // PSEUDO_PROBE = 24
11672 CEFBS_None, // ARITH_FENCE = 25
11673 CEFBS_None, // STACKMAP = 26
11674 CEFBS_None, // FENTRY_CALL = 27
11675 CEFBS_None, // PATCHPOINT = 28
11676 CEFBS_None, // LOAD_STACK_GUARD = 29
11677 CEFBS_None, // PREALLOCATED_SETUP = 30
11678 CEFBS_None, // PREALLOCATED_ARG = 31
11679 CEFBS_None, // STATEPOINT = 32
11680 CEFBS_None, // LOCAL_ESCAPE = 33
11681 CEFBS_None, // FAULTING_OP = 34
11682 CEFBS_None, // PATCHABLE_OP = 35
11683 CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 36
11684 CEFBS_None, // PATCHABLE_RET = 37
11685 CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 38
11686 CEFBS_None, // PATCHABLE_TAIL_CALL = 39
11687 CEFBS_None, // PATCHABLE_EVENT_CALL = 40
11688 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 41
11689 CEFBS_None, // ICALL_BRANCH_FUNNEL = 42
11690 CEFBS_None, // FAKE_USE = 43
11691 CEFBS_None, // MEMBARRIER = 44
11692 CEFBS_None, // JUMP_TABLE_DEBUG_INFO = 45
11693 CEFBS_None, // CONVERGENCECTRL_ENTRY = 46
11694 CEFBS_None, // CONVERGENCECTRL_ANCHOR = 47
11695 CEFBS_None, // CONVERGENCECTRL_LOOP = 48
11696 CEFBS_None, // CONVERGENCECTRL_GLUE = 49
11697 CEFBS_None, // G_ASSERT_SEXT = 50
11698 CEFBS_None, // G_ASSERT_ZEXT = 51
11699 CEFBS_None, // G_ASSERT_ALIGN = 52
11700 CEFBS_None, // G_ADD = 53
11701 CEFBS_None, // G_SUB = 54
11702 CEFBS_None, // G_MUL = 55
11703 CEFBS_None, // G_SDIV = 56
11704 CEFBS_None, // G_UDIV = 57
11705 CEFBS_None, // G_SREM = 58
11706 CEFBS_None, // G_UREM = 59
11707 CEFBS_None, // G_SDIVREM = 60
11708 CEFBS_None, // G_UDIVREM = 61
11709 CEFBS_None, // G_AND = 62
11710 CEFBS_None, // G_OR = 63
11711 CEFBS_None, // G_XOR = 64
11712 CEFBS_None, // G_ABDS = 65
11713 CEFBS_None, // G_ABDU = 66
11714 CEFBS_None, // G_IMPLICIT_DEF = 67
11715 CEFBS_None, // G_PHI = 68
11716 CEFBS_None, // G_FRAME_INDEX = 69
11717 CEFBS_None, // G_GLOBAL_VALUE = 70
11718 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE = 71
11719 CEFBS_None, // G_CONSTANT_POOL = 72
11720 CEFBS_None, // G_EXTRACT = 73
11721 CEFBS_None, // G_UNMERGE_VALUES = 74
11722 CEFBS_None, // G_INSERT = 75
11723 CEFBS_None, // G_MERGE_VALUES = 76
11724 CEFBS_None, // G_BUILD_VECTOR = 77
11725 CEFBS_None, // G_BUILD_VECTOR_TRUNC = 78
11726 CEFBS_None, // G_CONCAT_VECTORS = 79
11727 CEFBS_None, // G_PTRTOINT = 80
11728 CEFBS_None, // G_INTTOPTR = 81
11729 CEFBS_None, // G_BITCAST = 82
11730 CEFBS_None, // G_FREEZE = 83
11731 CEFBS_None, // G_CONSTANT_FOLD_BARRIER = 84
11732 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND = 85
11733 CEFBS_None, // G_INTRINSIC_TRUNC = 86
11734 CEFBS_None, // G_INTRINSIC_ROUND = 87
11735 CEFBS_None, // G_INTRINSIC_LRINT = 88
11736 CEFBS_None, // G_INTRINSIC_LLRINT = 89
11737 CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 90
11738 CEFBS_None, // G_READCYCLECOUNTER = 91
11739 CEFBS_None, // G_READSTEADYCOUNTER = 92
11740 CEFBS_None, // G_LOAD = 93
11741 CEFBS_None, // G_SEXTLOAD = 94
11742 CEFBS_None, // G_ZEXTLOAD = 95
11743 CEFBS_None, // G_INDEXED_LOAD = 96
11744 CEFBS_None, // G_INDEXED_SEXTLOAD = 97
11745 CEFBS_None, // G_INDEXED_ZEXTLOAD = 98
11746 CEFBS_None, // G_STORE = 99
11747 CEFBS_None, // G_INDEXED_STORE = 100
11748 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 101
11749 CEFBS_None, // G_ATOMIC_CMPXCHG = 102
11750 CEFBS_None, // G_ATOMICRMW_XCHG = 103
11751 CEFBS_None, // G_ATOMICRMW_ADD = 104
11752 CEFBS_None, // G_ATOMICRMW_SUB = 105
11753 CEFBS_None, // G_ATOMICRMW_AND = 106
11754 CEFBS_None, // G_ATOMICRMW_NAND = 107
11755 CEFBS_None, // G_ATOMICRMW_OR = 108
11756 CEFBS_None, // G_ATOMICRMW_XOR = 109
11757 CEFBS_None, // G_ATOMICRMW_MAX = 110
11758 CEFBS_None, // G_ATOMICRMW_MIN = 111
11759 CEFBS_None, // G_ATOMICRMW_UMAX = 112
11760 CEFBS_None, // G_ATOMICRMW_UMIN = 113
11761 CEFBS_None, // G_ATOMICRMW_FADD = 114
11762 CEFBS_None, // G_ATOMICRMW_FSUB = 115
11763 CEFBS_None, // G_ATOMICRMW_FMAX = 116
11764 CEFBS_None, // G_ATOMICRMW_FMIN = 117
11765 CEFBS_None, // G_ATOMICRMW_FMAXIMUM = 118
11766 CEFBS_None, // G_ATOMICRMW_FMINIMUM = 119
11767 CEFBS_None, // G_ATOMICRMW_UINC_WRAP = 120
11768 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP = 121
11769 CEFBS_None, // G_ATOMICRMW_USUB_COND = 122
11770 CEFBS_None, // G_ATOMICRMW_USUB_SAT = 123
11771 CEFBS_None, // G_FENCE = 124
11772 CEFBS_None, // G_PREFETCH = 125
11773 CEFBS_None, // G_BRCOND = 126
11774 CEFBS_None, // G_BRINDIRECT = 127
11775 CEFBS_None, // G_INVOKE_REGION_START = 128
11776 CEFBS_None, // G_INTRINSIC = 129
11777 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 130
11778 CEFBS_None, // G_INTRINSIC_CONVERGENT = 131
11779 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 132
11780 CEFBS_None, // G_ANYEXT = 133
11781 CEFBS_None, // G_TRUNC = 134
11782 CEFBS_None, // G_CONSTANT = 135
11783 CEFBS_None, // G_FCONSTANT = 136
11784 CEFBS_None, // G_VASTART = 137
11785 CEFBS_None, // G_VAARG = 138
11786 CEFBS_None, // G_SEXT = 139
11787 CEFBS_None, // G_SEXT_INREG = 140
11788 CEFBS_None, // G_ZEXT = 141
11789 CEFBS_None, // G_SHL = 142
11790 CEFBS_None, // G_LSHR = 143
11791 CEFBS_None, // G_ASHR = 144
11792 CEFBS_None, // G_FSHL = 145
11793 CEFBS_None, // G_FSHR = 146
11794 CEFBS_None, // G_ROTR = 147
11795 CEFBS_None, // G_ROTL = 148
11796 CEFBS_None, // G_ICMP = 149
11797 CEFBS_None, // G_FCMP = 150
11798 CEFBS_None, // G_SCMP = 151
11799 CEFBS_None, // G_UCMP = 152
11800 CEFBS_None, // G_SELECT = 153
11801 CEFBS_None, // G_UADDO = 154
11802 CEFBS_None, // G_UADDE = 155
11803 CEFBS_None, // G_USUBO = 156
11804 CEFBS_None, // G_USUBE = 157
11805 CEFBS_None, // G_SADDO = 158
11806 CEFBS_None, // G_SADDE = 159
11807 CEFBS_None, // G_SSUBO = 160
11808 CEFBS_None, // G_SSUBE = 161
11809 CEFBS_None, // G_UMULO = 162
11810 CEFBS_None, // G_SMULO = 163
11811 CEFBS_None, // G_UMULH = 164
11812 CEFBS_None, // G_SMULH = 165
11813 CEFBS_None, // G_UADDSAT = 166
11814 CEFBS_None, // G_SADDSAT = 167
11815 CEFBS_None, // G_USUBSAT = 168
11816 CEFBS_None, // G_SSUBSAT = 169
11817 CEFBS_None, // G_USHLSAT = 170
11818 CEFBS_None, // G_SSHLSAT = 171
11819 CEFBS_None, // G_SMULFIX = 172
11820 CEFBS_None, // G_UMULFIX = 173
11821 CEFBS_None, // G_SMULFIXSAT = 174
11822 CEFBS_None, // G_UMULFIXSAT = 175
11823 CEFBS_None, // G_SDIVFIX = 176
11824 CEFBS_None, // G_UDIVFIX = 177
11825 CEFBS_None, // G_SDIVFIXSAT = 178
11826 CEFBS_None, // G_UDIVFIXSAT = 179
11827 CEFBS_None, // G_FADD = 180
11828 CEFBS_None, // G_FSUB = 181
11829 CEFBS_None, // G_FMUL = 182
11830 CEFBS_None, // G_FMA = 183
11831 CEFBS_None, // G_FMAD = 184
11832 CEFBS_None, // G_FDIV = 185
11833 CEFBS_None, // G_FREM = 186
11834 CEFBS_None, // G_FPOW = 187
11835 CEFBS_None, // G_FPOWI = 188
11836 CEFBS_None, // G_FEXP = 189
11837 CEFBS_None, // G_FEXP2 = 190
11838 CEFBS_None, // G_FEXP10 = 191
11839 CEFBS_None, // G_FLOG = 192
11840 CEFBS_None, // G_FLOG2 = 193
11841 CEFBS_None, // G_FLOG10 = 194
11842 CEFBS_None, // G_FLDEXP = 195
11843 CEFBS_None, // G_FFREXP = 196
11844 CEFBS_None, // G_FNEG = 197
11845 CEFBS_None, // G_FPEXT = 198
11846 CEFBS_None, // G_FPTRUNC = 199
11847 CEFBS_None, // G_FPTOSI = 200
11848 CEFBS_None, // G_FPTOUI = 201
11849 CEFBS_None, // G_SITOFP = 202
11850 CEFBS_None, // G_UITOFP = 203
11851 CEFBS_None, // G_FPTOSI_SAT = 204
11852 CEFBS_None, // G_FPTOUI_SAT = 205
11853 CEFBS_None, // G_FABS = 206
11854 CEFBS_None, // G_FCOPYSIGN = 207
11855 CEFBS_None, // G_IS_FPCLASS = 208
11856 CEFBS_None, // G_FCANONICALIZE = 209
11857 CEFBS_None, // G_FMINNUM = 210
11858 CEFBS_None, // G_FMAXNUM = 211
11859 CEFBS_None, // G_FMINNUM_IEEE = 212
11860 CEFBS_None, // G_FMAXNUM_IEEE = 213
11861 CEFBS_None, // G_FMINIMUM = 214
11862 CEFBS_None, // G_FMAXIMUM = 215
11863 CEFBS_None, // G_FMINIMUMNUM = 216
11864 CEFBS_None, // G_FMAXIMUMNUM = 217
11865 CEFBS_None, // G_GET_FPENV = 218
11866 CEFBS_None, // G_SET_FPENV = 219
11867 CEFBS_None, // G_RESET_FPENV = 220
11868 CEFBS_None, // G_GET_FPMODE = 221
11869 CEFBS_None, // G_SET_FPMODE = 222
11870 CEFBS_None, // G_RESET_FPMODE = 223
11871 CEFBS_None, // G_PTR_ADD = 224
11872 CEFBS_None, // G_PTRMASK = 225
11873 CEFBS_None, // G_SMIN = 226
11874 CEFBS_None, // G_SMAX = 227
11875 CEFBS_None, // G_UMIN = 228
11876 CEFBS_None, // G_UMAX = 229
11877 CEFBS_None, // G_ABS = 230
11878 CEFBS_None, // G_LROUND = 231
11879 CEFBS_None, // G_LLROUND = 232
11880 CEFBS_None, // G_BR = 233
11881 CEFBS_None, // G_BRJT = 234
11882 CEFBS_None, // G_VSCALE = 235
11883 CEFBS_None, // G_INSERT_SUBVECTOR = 236
11884 CEFBS_None, // G_EXTRACT_SUBVECTOR = 237
11885 CEFBS_None, // G_INSERT_VECTOR_ELT = 238
11886 CEFBS_None, // G_EXTRACT_VECTOR_ELT = 239
11887 CEFBS_None, // G_SHUFFLE_VECTOR = 240
11888 CEFBS_None, // G_SPLAT_VECTOR = 241
11889 CEFBS_None, // G_STEP_VECTOR = 242
11890 CEFBS_None, // G_VECTOR_COMPRESS = 243
11891 CEFBS_None, // G_CTTZ = 244
11892 CEFBS_None, // G_CTTZ_ZERO_UNDEF = 245
11893 CEFBS_None, // G_CTLZ = 246
11894 CEFBS_None, // G_CTLZ_ZERO_UNDEF = 247
11895 CEFBS_None, // G_CTPOP = 248
11896 CEFBS_None, // G_BSWAP = 249
11897 CEFBS_None, // G_BITREVERSE = 250
11898 CEFBS_None, // G_FCEIL = 251
11899 CEFBS_None, // G_FCOS = 252
11900 CEFBS_None, // G_FSIN = 253
11901 CEFBS_None, // G_FSINCOS = 254
11902 CEFBS_None, // G_FTAN = 255
11903 CEFBS_None, // G_FACOS = 256
11904 CEFBS_None, // G_FASIN = 257
11905 CEFBS_None, // G_FATAN = 258
11906 CEFBS_None, // G_FATAN2 = 259
11907 CEFBS_None, // G_FCOSH = 260
11908 CEFBS_None, // G_FSINH = 261
11909 CEFBS_None, // G_FTANH = 262
11910 CEFBS_None, // G_FSQRT = 263
11911 CEFBS_None, // G_FFLOOR = 264
11912 CEFBS_None, // G_FRINT = 265
11913 CEFBS_None, // G_FNEARBYINT = 266
11914 CEFBS_None, // G_ADDRSPACE_CAST = 267
11915 CEFBS_None, // G_BLOCK_ADDR = 268
11916 CEFBS_None, // G_JUMP_TABLE = 269
11917 CEFBS_None, // G_DYN_STACKALLOC = 270
11918 CEFBS_None, // G_STACKSAVE = 271
11919 CEFBS_None, // G_STACKRESTORE = 272
11920 CEFBS_None, // G_STRICT_FADD = 273
11921 CEFBS_None, // G_STRICT_FSUB = 274
11922 CEFBS_None, // G_STRICT_FMUL = 275
11923 CEFBS_None, // G_STRICT_FDIV = 276
11924 CEFBS_None, // G_STRICT_FREM = 277
11925 CEFBS_None, // G_STRICT_FMA = 278
11926 CEFBS_None, // G_STRICT_FSQRT = 279
11927 CEFBS_None, // G_STRICT_FLDEXP = 280
11928 CEFBS_None, // G_READ_REGISTER = 281
11929 CEFBS_None, // G_WRITE_REGISTER = 282
11930 CEFBS_None, // G_MEMCPY = 283
11931 CEFBS_None, // G_MEMCPY_INLINE = 284
11932 CEFBS_None, // G_MEMMOVE = 285
11933 CEFBS_None, // G_MEMSET = 286
11934 CEFBS_None, // G_BZERO = 287
11935 CEFBS_None, // G_TRAP = 288
11936 CEFBS_None, // G_DEBUGTRAP = 289
11937 CEFBS_None, // G_UBSANTRAP = 290
11938 CEFBS_None, // G_VECREDUCE_SEQ_FADD = 291
11939 CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 292
11940 CEFBS_None, // G_VECREDUCE_FADD = 293
11941 CEFBS_None, // G_VECREDUCE_FMUL = 294
11942 CEFBS_None, // G_VECREDUCE_FMAX = 295
11943 CEFBS_None, // G_VECREDUCE_FMIN = 296
11944 CEFBS_None, // G_VECREDUCE_FMAXIMUM = 297
11945 CEFBS_None, // G_VECREDUCE_FMINIMUM = 298
11946 CEFBS_None, // G_VECREDUCE_ADD = 299
11947 CEFBS_None, // G_VECREDUCE_MUL = 300
11948 CEFBS_None, // G_VECREDUCE_AND = 301
11949 CEFBS_None, // G_VECREDUCE_OR = 302
11950 CEFBS_None, // G_VECREDUCE_XOR = 303
11951 CEFBS_None, // G_VECREDUCE_SMAX = 304
11952 CEFBS_None, // G_VECREDUCE_SMIN = 305
11953 CEFBS_None, // G_VECREDUCE_UMAX = 306
11954 CEFBS_None, // G_VECREDUCE_UMIN = 307
11955 CEFBS_None, // G_SBFX = 308
11956 CEFBS_None, // G_UBFX = 309
11957 CEFBS_None, // ABSMacro = 310
11958 CEFBS_None, // ADJCALLSTACKDOWN = 311
11959 CEFBS_None, // ADJCALLSTACKUP = 312
11960 CEFBS_HasStdEnc_HasMSA, // AND_V_D_PSEUDO = 313
11961 CEFBS_HasStdEnc_HasMSA, // AND_V_H_PSEUDO = 314
11962 CEFBS_HasStdEnc_HasMSA, // AND_V_W_PSEUDO = 315
11963 CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I16 = 316
11964 CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I16_POSTRA = 317
11965 CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I32 = 318
11966 CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I32_POSTRA = 319
11967 CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I64 = 320
11968 CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I64_POSTRA = 321
11969 CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I8 = 322
11970 CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I8_POSTRA = 323
11971 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I16 = 324
11972 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I16_POSTRA = 325
11973 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I32 = 326
11974 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I32_POSTRA = 327
11975 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I64 = 328
11976 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I64_POSTRA = 329
11977 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I8 = 330
11978 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I8_POSTRA = 331
11979 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I16 = 332
11980 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I16_POSTRA = 333
11981 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I32 = 334
11982 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I32_POSTRA = 335
11983 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I64 = 336
11984 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I64_POSTRA = 337
11985 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I8 = 338
11986 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I8_POSTRA = 339
11987 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I16 = 340
11988 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I16_POSTRA = 341
11989 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I32 = 342
11990 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I32_POSTRA = 343
11991 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I64 = 344
11992 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I64_POSTRA = 345
11993 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I8 = 346
11994 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I8_POSTRA = 347
11995 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I16 = 348
11996 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I16_POSTRA = 349
11997 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I32 = 350
11998 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I32_POSTRA = 351
11999 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I64 = 352
12000 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I64_POSTRA = 353
12001 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I8 = 354
12002 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I8_POSTRA = 355
12003 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I16 = 356
12004 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I16_POSTRA = 357
12005 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I32 = 358
12006 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I32_POSTRA = 359
12007 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I64 = 360
12008 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I64_POSTRA = 361
12009 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I8 = 362
12010 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I8_POSTRA = 363
12011 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I16 = 364
12012 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I16_POSTRA = 365
12013 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I32 = 366
12014 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I32_POSTRA = 367
12015 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I64 = 368
12016 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I64_POSTRA = 369
12017 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I8 = 370
12018 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I8_POSTRA = 371
12019 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I16 = 372
12020 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I16_POSTRA = 373
12021 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I32 = 374
12022 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I32_POSTRA = 375
12023 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I64 = 376
12024 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I64_POSTRA = 377
12025 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I8 = 378
12026 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I8_POSTRA = 379
12027 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I16 = 380
12028 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I16_POSTRA = 381
12029 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I32 = 382
12030 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I32_POSTRA = 383
12031 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I64 = 384
12032 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I64_POSTRA = 385
12033 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I8 = 386
12034 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I8_POSTRA = 387
12035 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I16 = 388
12036 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I16_POSTRA = 389
12037 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I32 = 390
12038 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I32_POSTRA = 391
12039 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I64 = 392
12040 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I64_POSTRA = 393
12041 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I8 = 394
12042 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I8_POSTRA = 395
12043 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I16 = 396
12044 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I16_POSTRA = 397
12045 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I32 = 398
12046 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I32_POSTRA = 399
12047 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I64 = 400
12048 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I64_POSTRA = 401
12049 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I8 = 402
12050 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I8_POSTRA = 403
12051 CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I16 = 404
12052 CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I16_POSTRA = 405
12053 CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I32 = 406
12054 CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I32_POSTRA = 407
12055 CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I64 = 408
12056 CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I64_POSTRA = 409
12057 CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I8 = 410
12058 CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I8_POSTRA = 411
12059 CEFBS_HasStdEnc_NotInMicroMips, // B = 412
12060 CEFBS_HasStdEnc_NotInMicroMips, // BAL_BR = 413
12061 CEFBS_InMicroMips_NotMips32r6, // BAL_BR_MM = 414
12062 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BEQLImmMacro = 415
12063 CEFBS_None, // BGE = 416
12064 CEFBS_None, // BGEImmMacro = 417
12065 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGEL = 418
12066 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGELImmMacro = 419
12067 CEFBS_None, // BGEU = 420
12068 CEFBS_None, // BGEUImmMacro = 421
12069 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGEUL = 422
12070 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGEULImmMacro = 423
12071 CEFBS_None, // BGT = 424
12072 CEFBS_None, // BGTImmMacro = 425
12073 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGTL = 426
12074 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGTLImmMacro = 427
12075 CEFBS_None, // BGTU = 428
12076 CEFBS_None, // BGTUImmMacro = 429
12077 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGTUL = 430
12078 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGTULImmMacro = 431
12079 CEFBS_None, // BLE = 432
12080 CEFBS_None, // BLEImmMacro = 433
12081 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLEL = 434
12082 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLELImmMacro = 435
12083 CEFBS_None, // BLEU = 436
12084 CEFBS_None, // BLEUImmMacro = 437
12085 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLEUL = 438
12086 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLEULImmMacro = 439
12087 CEFBS_None, // BLT = 440
12088 CEFBS_None, // BLTImmMacro = 441
12089 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLTL = 442
12090 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLTLImmMacro = 443
12091 CEFBS_None, // BLTU = 444
12092 CEFBS_None, // BLTUImmMacro = 445
12093 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLTUL = 446
12094 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLTULImmMacro = 447
12095 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BNELImmMacro = 448
12096 CEFBS_None, // BPOSGE32_PSEUDO = 449
12097 CEFBS_HasStdEnc_HasMSA, // BSEL_D_PSEUDO = 450
12098 CEFBS_HasStdEnc_HasMSA, // BSEL_FD_PSEUDO = 451
12099 CEFBS_HasStdEnc_HasMSA, // BSEL_FW_PSEUDO = 452
12100 CEFBS_HasStdEnc_HasMSA, // BSEL_H_PSEUDO = 453
12101 CEFBS_HasStdEnc_HasMSA, // BSEL_W_PSEUDO = 454
12102 CEFBS_InMicroMips_NotMips32r6, // B_MM = 455
12103 CEFBS_None, // B_MMR6_Pseudo = 456
12104 CEFBS_InMicroMips, // B_MM_Pseudo = 457
12105 CEFBS_None, // BeqImm = 458
12106 CEFBS_None, // BneImm = 459
12107 CEFBS_InMips16Mode, // BteqzT8CmpX16 = 460
12108 CEFBS_InMips16Mode, // BteqzT8CmpiX16 = 461
12109 CEFBS_InMips16Mode, // BteqzT8SltX16 = 462
12110 CEFBS_InMips16Mode, // BteqzT8SltiX16 = 463
12111 CEFBS_InMips16Mode, // BteqzT8SltiuX16 = 464
12112 CEFBS_InMips16Mode, // BteqzT8SltuX16 = 465
12113 CEFBS_InMips16Mode, // BtnezT8CmpX16 = 466
12114 CEFBS_InMips16Mode, // BtnezT8CmpiX16 = 467
12115 CEFBS_InMips16Mode, // BtnezT8SltX16 = 468
12116 CEFBS_InMips16Mode, // BtnezT8SltiX16 = 469
12117 CEFBS_InMips16Mode, // BtnezT8SltiuX16 = 470
12118 CEFBS_InMips16Mode, // BtnezT8SltuX16 = 471
12119 CEFBS_NotInMips16Mode_NotFP64bit_IsNotSoftFloat, // BuildPairF64 = 472
12120 CEFBS_NotInMips16Mode_IsFP64bit_IsNotSoftFloat, // BuildPairF64_64 = 473
12121 CEFBS_HasMT, // CFTC1 = 474
12122 CEFBS_InMips16Mode, // CONSTPOOL_ENTRY = 475
12123 CEFBS_HasStdEnc_HasMSA, // COPY_FD_PSEUDO = 476
12124 CEFBS_HasStdEnc_HasMSA, // COPY_FW_PSEUDO = 477
12125 CEFBS_HasMT, // CTTC1 = 478
12126 CEFBS_InMips16Mode, // Constant32 = 479
12127 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // DMULImmMacro = 480
12128 CEFBS_HasMips3_NotMips64r6_NotCnMips, // DMULMacro = 481
12129 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // DMULOMacro = 482
12130 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // DMULOUMacro = 483
12131 CEFBS_HasStdEnc_HasMips64, // DROL = 484
12132 CEFBS_HasStdEnc_HasMips64, // DROLImm = 485
12133 CEFBS_HasStdEnc_HasMips64, // DROR = 486
12134 CEFBS_HasStdEnc_HasMips64, // DRORImm = 487
12135 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DSDivIMacro = 488
12136 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DSDivMacro = 489
12137 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DSRemIMacro = 490
12138 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DSRemMacro = 491
12139 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DUDivIMacro = 492
12140 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DUDivMacro = 493
12141 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DURemIMacro = 494
12142 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DURemMacro = 495
12143 CEFBS_NotInMips16Mode, // ERet = 496
12144 CEFBS_NotInMips16Mode_NotFP64bit_IsNotSoftFloat, // ExtractElementF64 = 497
12145 CEFBS_NotInMips16Mode_IsFP64bit_IsNotSoftFloat, // ExtractElementF64_64 = 498
12146 CEFBS_HasStdEnc_HasMSA, // FABS_D = 499
12147 CEFBS_HasStdEnc_HasMSA, // FABS_W = 500
12148 CEFBS_HasStdEnc_HasMSA, // FEXP2_D_1_PSEUDO = 501
12149 CEFBS_HasStdEnc_HasMSA, // FEXP2_W_1_PSEUDO = 502
12150 CEFBS_HasStdEnc_HasMSA, // FILL_FD_PSEUDO = 503
12151 CEFBS_HasStdEnc_HasMSA, // FILL_FW_PSEUDO = 504
12152 CEFBS_InMips16Mode, // GotPrologue16 = 505
12153 CEFBS_HasStdEnc_HasMSA, // INSERT_B_VIDX64_PSEUDO = 506
12154 CEFBS_HasStdEnc_HasMSA, // INSERT_B_VIDX_PSEUDO = 507
12155 CEFBS_HasStdEnc_HasMSA, // INSERT_D_VIDX64_PSEUDO = 508
12156 CEFBS_HasStdEnc_HasMSA, // INSERT_D_VIDX_PSEUDO = 509
12157 CEFBS_HasStdEnc_HasMSA, // INSERT_FD_PSEUDO = 510
12158 CEFBS_HasStdEnc_HasMSA, // INSERT_FD_VIDX64_PSEUDO = 511
12159 CEFBS_HasStdEnc_HasMSA, // INSERT_FD_VIDX_PSEUDO = 512
12160 CEFBS_HasStdEnc_HasMSA, // INSERT_FW_PSEUDO = 513
12161 CEFBS_HasStdEnc_HasMSA, // INSERT_FW_VIDX64_PSEUDO = 514
12162 CEFBS_HasStdEnc_HasMSA, // INSERT_FW_VIDX_PSEUDO = 515
12163 CEFBS_HasStdEnc_HasMSA, // INSERT_H_VIDX64_PSEUDO = 516
12164 CEFBS_HasStdEnc_HasMSA, // INSERT_H_VIDX_PSEUDO = 517
12165 CEFBS_HasStdEnc_HasMSA, // INSERT_W_VIDX64_PSEUDO = 518
12166 CEFBS_HasStdEnc_HasMSA, // INSERT_W_VIDX_PSEUDO = 519
12167 CEFBS_NotInMips16Mode_IsPTR64bit_NoIndirectJumpGuards, // JALR64Pseudo = 520
12168 CEFBS_NotInMips16Mode_IsPTR64bit_UseIndirectJumpsHazard, // JALRHB64Pseudo = 521
12169 CEFBS_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // JALRHBPseudo = 522
12170 CEFBS_HasStdEnc_NotInMicroMips_NoIndirectJumpGuards, // JALRPseudo = 523
12171 CEFBS_InMicroMips_HasMips32r6, // JAL_MMR6 = 524
12172 CEFBS_None, // JalOneReg = 525
12173 CEFBS_None, // JalTwoReg = 526
12174 CEFBS_HasStdEnc_NotMips3, // LDMacro = 527
12175 CEFBS_NotInMips16Mode, // LDR_D = 528
12176 CEFBS_NotInMips16Mode, // LDR_W = 529
12177 CEFBS_HasMSA, // LD_F16 = 530
12178 CEFBS_NotInMips16Mode, // LOAD_ACC128 = 531
12179 CEFBS_NotInMips16Mode, // LOAD_ACC64 = 532
12180 CEFBS_NotInMips16Mode, // LOAD_ACC64DSP = 533
12181 CEFBS_NotInMips16Mode, // LOAD_CCOND_DSP = 534
12182 CEFBS_NotInMips16Mode, // LONG_BRANCH_ADDiu = 535
12183 CEFBS_NotInMips16Mode, // LONG_BRANCH_ADDiu2Op = 536
12184 CEFBS_NotInMips16Mode_IsGP64bit, // LONG_BRANCH_DADDiu = 537
12185 CEFBS_NotInMips16Mode_IsGP64bit, // LONG_BRANCH_DADDiu2Op = 538
12186 CEFBS_NotInMips16Mode, // LONG_BRANCH_LUi = 539
12187 CEFBS_NotInMips16Mode, // LONG_BRANCH_LUi2Op = 540
12188 CEFBS_NotInMips16Mode_IsGP64bit, // LONG_BRANCH_LUi2Op_64 = 541
12189 CEFBS_InMicroMips, // LWM_MM = 542
12190 CEFBS_None, // LoadAddrImm32 = 543
12191 CEFBS_None, // LoadAddrImm64 = 544
12192 CEFBS_None, // LoadAddrReg32 = 545
12193 CEFBS_None, // LoadAddrReg64 = 546
12194 CEFBS_None, // LoadImm32 = 547
12195 CEFBS_None, // LoadImm64 = 548
12196 CEFBS_IsFP64bit_IsNotSoftFloat, // LoadImmDoubleFGR = 549
12197 CEFBS_NotFP64bit_IsNotSoftFloat, // LoadImmDoubleFGR_32 = 550
12198 CEFBS_None, // LoadImmDoubleGPR = 551
12199 CEFBS_IsNotSoftFloat, // LoadImmSingleFGR = 552
12200 CEFBS_None, // LoadImmSingleGPR = 553
12201 CEFBS_InMips16Mode, // LwConstant32 = 554
12202 CEFBS_HasMT, // MFTACX = 555
12203 CEFBS_HasMT, // MFTC0 = 556
12204 CEFBS_HasMT, // MFTC1 = 557
12205 CEFBS_HasMT, // MFTDSP = 558
12206 CEFBS_HasMT, // MFTGPR = 559
12207 CEFBS_HasMT, // MFTHC1 = 560
12208 CEFBS_HasMT, // MFTHI = 561
12209 CEFBS_HasMT, // MFTLO = 562
12210 CEFBS_None, // MIPSeh_return32 = 563
12211 CEFBS_None, // MIPSeh_return64 = 564
12212 CEFBS_HasMSA, // MSA_FP_EXTEND_D_PSEUDO = 565
12213 CEFBS_HasMSA, // MSA_FP_EXTEND_W_PSEUDO = 566
12214 CEFBS_HasMSA, // MSA_FP_ROUND_D_PSEUDO = 567
12215 CEFBS_HasMSA, // MSA_FP_ROUND_W_PSEUDO = 568
12216 CEFBS_HasMT, // MTTACX = 569
12217 CEFBS_HasMT, // MTTC0 = 570
12218 CEFBS_HasMT, // MTTC1 = 571
12219 CEFBS_HasMT, // MTTDSP = 572
12220 CEFBS_HasMT, // MTTGPR = 573
12221 CEFBS_HasMT, // MTTHC1 = 574
12222 CEFBS_HasMT, // MTTHI = 575
12223 CEFBS_HasMT, // MTTLO = 576
12224 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // MULImmMacro = 577
12225 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // MULOMacro = 578
12226 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // MULOUMacro = 579
12227 CEFBS_InMips16Mode, // MultRxRy16 = 580
12228 CEFBS_InMips16Mode, // MultRxRyRz16 = 581
12229 CEFBS_InMips16Mode, // MultuRxRy16 = 582
12230 CEFBS_InMips16Mode, // MultuRxRyRz16 = 583
12231 CEFBS_HasStdEnc_NotInMicroMips, // NOP = 584
12232 CEFBS_IsGP32bit, // NORImm = 585
12233 CEFBS_IsGP64bit, // NORImm64 = 586
12234 CEFBS_HasStdEnc_HasMSA, // NOR_V_D_PSEUDO = 587
12235 CEFBS_HasStdEnc_HasMSA, // NOR_V_H_PSEUDO = 588
12236 CEFBS_HasStdEnc_HasMSA, // NOR_V_W_PSEUDO = 589
12237 CEFBS_HasStdEnc_HasMSA, // OR_V_D_PSEUDO = 590
12238 CEFBS_HasStdEnc_HasMSA, // OR_V_H_PSEUDO = 591
12239 CEFBS_HasStdEnc_HasMSA, // OR_V_W_PSEUDO = 592
12240 CEFBS_HasDSP, // PseudoCMPU_EQ_QB = 593
12241 CEFBS_HasDSP, // PseudoCMPU_LE_QB = 594
12242 CEFBS_HasDSP, // PseudoCMPU_LT_QB = 595
12243 CEFBS_HasDSP, // PseudoCMP_EQ_PH = 596
12244 CEFBS_HasDSP, // PseudoCMP_LE_PH = 597
12245 CEFBS_HasDSP, // PseudoCMP_LT_PH = 598
12246 CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_D32_W = 599
12247 CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_D64_L = 600
12248 CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_D64_W = 601
12249 CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_S_L = 602
12250 CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_S_W = 603
12251 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoDMULT = 604
12252 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoDMULTu = 605
12253 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoDSDIV = 606
12254 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoDUDIV = 607
12255 CEFBS_HasStdEnc_NotMips4_32, // PseudoD_SELECT_I = 608
12256 CEFBS_HasStdEnc_NotMips4_32, // PseudoD_SELECT_I64 = 609
12257 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // PseudoIndirectBranch = 610
12258 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // PseudoIndirectBranch64 = 611
12259 CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // PseudoIndirectBranch64R6 = 612
12260 CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // PseudoIndirectBranchR6 = 613
12261 CEFBS_InMicroMips_NotMips32r6, // PseudoIndirectBranch_MM = 614
12262 CEFBS_InMicroMips_HasMips32r6, // PseudoIndirectBranch_MMR6 = 615
12263 CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // PseudoIndirectHazardBranch = 616
12264 CEFBS_HasStdEnc_IsPTR64bit_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // PseudoIndirectHazardBranch64 = 617
12265 CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // PseudoIndrectHazardBranch64R6 = 618
12266 CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // PseudoIndrectHazardBranchR6 = 619
12267 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, // PseudoMADD = 620
12268 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, // PseudoMADDU = 621
12269 CEFBS_InMicroMips_NotMips32r6, // PseudoMADDU_MM = 622
12270 CEFBS_InMicroMips_NotMips32r6, // PseudoMADD_MM = 623
12271 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMFHI = 624
12272 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoMFHI64 = 625
12273 CEFBS_InMicroMips_NotMips32r6, // PseudoMFHI_MM = 626
12274 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMFLO = 627
12275 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoMFLO64 = 628
12276 CEFBS_InMicroMips_NotMips32r6, // PseudoMFLO_MM = 629
12277 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, // PseudoMSUB = 630
12278 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, // PseudoMSUBU = 631
12279 CEFBS_InMicroMips_NotMips32r6, // PseudoMSUBU_MM = 632
12280 CEFBS_InMicroMips_NotMips32r6, // PseudoMSUB_MM = 633
12281 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMTLOHI = 634
12282 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoMTLOHI64 = 635
12283 CEFBS_NotInMips16Mode_HasDSP, // PseudoMTLOHI_DSP = 636
12284 CEFBS_InMicroMips_NotMips32r6, // PseudoMTLOHI_MM = 637
12285 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMULT = 638
12286 CEFBS_InMicroMips_NotMips32r6, // PseudoMULT_MM = 639
12287 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMULTu = 640
12288 CEFBS_InMicroMips_NotMips32r6, // PseudoMULTu_MM = 641
12289 CEFBS_HasDSP, // PseudoPICK_PH = 642
12290 CEFBS_HasDSP, // PseudoPICK_QB = 643
12291 CEFBS_None, // PseudoReturn = 644
12292 CEFBS_IsGP64bit, // PseudoReturn64 = 645
12293 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // PseudoSDIV = 646
12294 CEFBS_HasStdEnc_NotFP64bit_NotMips4_32, // PseudoSELECTFP_F_D32 = 647
12295 CEFBS_HasStdEnc_IsFP64bit_NotMips4_32, // PseudoSELECTFP_F_D64 = 648
12296 CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_F_I = 649
12297 CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_F_I64 = 650
12298 CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_F_S = 651
12299 CEFBS_HasStdEnc_NotFP64bit_NotMips4_32, // PseudoSELECTFP_T_D32 = 652
12300 CEFBS_HasStdEnc_IsFP64bit_NotMips4_32, // PseudoSELECTFP_T_D64 = 653
12301 CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_T_I = 654
12302 CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_T_I64 = 655
12303 CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_T_S = 656
12304 CEFBS_HasStdEnc_NotFP64bit_NotMips4_32, // PseudoSELECT_D32 = 657
12305 CEFBS_HasStdEnc_IsFP64bit_NotMips4_32, // PseudoSELECT_D64 = 658
12306 CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECT_I = 659
12307 CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECT_I64 = 660
12308 CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECT_S = 661
12309 CEFBS_IsFP64bit_IsNotSoftFloat, // PseudoTRUNC_W_D = 662
12310 CEFBS_NotFP64bit_IsNotSoftFloat, // PseudoTRUNC_W_D32 = 663
12311 CEFBS_None, // PseudoTRUNC_W_S = 664
12312 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // PseudoUDIV = 665
12313 CEFBS_None, // ROL = 666
12314 CEFBS_None, // ROLImm = 667
12315 CEFBS_None, // ROR = 668
12316 CEFBS_None, // RORImm = 669
12317 CEFBS_NotInMips16Mode, // RetRA = 670
12318 CEFBS_InMips16Mode, // RetRA16 = 671
12319 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat, // SDC1_M1 = 672
12320 CEFBS_InMicroMips_NotMips32r6_NotMips64r6, // SDIV_MM_Pseudo = 673
12321 CEFBS_HasStdEnc_NotMips3, // SDMacro = 674
12322 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // SDivIMacro = 675
12323 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // SDivMacro = 676
12324 CEFBS_NotCnMips, // SEQIMacro = 677
12325 CEFBS_NotCnMips, // SEQMacro = 678
12326 CEFBS_HasStdEnc_NotInMicroMips, // SGE = 679
12327 CEFBS_IsGP32bit_NotInMicroMips, // SGEImm = 680
12328 CEFBS_IsGP64bit, // SGEImm64 = 681
12329 CEFBS_HasStdEnc_NotInMicroMips, // SGEU = 682
12330 CEFBS_IsGP32bit_NotInMicroMips, // SGEUImm = 683
12331 CEFBS_IsGP64bit, // SGEUImm64 = 684
12332 CEFBS_IsGP32bit_NotInMicroMips, // SGTImm = 685
12333 CEFBS_IsGP64bit, // SGTImm64 = 686
12334 CEFBS_IsGP32bit_NotInMicroMips, // SGTUImm = 687
12335 CEFBS_IsGP64bit, // SGTUImm64 = 688
12336 CEFBS_HasStdEnc_NotInMicroMips, // SLE = 689
12337 CEFBS_IsGP32bit_NotInMicroMips, // SLEImm = 690
12338 CEFBS_IsGP64bit, // SLEImm64 = 691
12339 CEFBS_HasStdEnc_NotInMicroMips, // SLEU = 692
12340 CEFBS_IsGP32bit_NotInMicroMips, // SLEUImm = 693
12341 CEFBS_IsGP64bit, // SLEUImm64 = 694
12342 CEFBS_IsGP64bit, // SLTImm64 = 695
12343 CEFBS_IsGP64bit, // SLTUImm64 = 696
12344 CEFBS_NotCnMips, // SNEIMacro = 697
12345 CEFBS_NotCnMips, // SNEMacro = 698
12346 CEFBS_None, // SNZ_B_PSEUDO = 699
12347 CEFBS_None, // SNZ_D_PSEUDO = 700
12348 CEFBS_None, // SNZ_H_PSEUDO = 701
12349 CEFBS_None, // SNZ_V_PSEUDO = 702
12350 CEFBS_None, // SNZ_W_PSEUDO = 703
12351 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // SRemIMacro = 704
12352 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // SRemMacro = 705
12353 CEFBS_NotInMips16Mode, // STORE_ACC128 = 706
12354 CEFBS_NotInMips16Mode, // STORE_ACC64 = 707
12355 CEFBS_NotInMips16Mode, // STORE_ACC64DSP = 708
12356 CEFBS_NotInMips16Mode, // STORE_CCOND_DSP = 709
12357 CEFBS_NotInMips16Mode, // STR_D = 710
12358 CEFBS_NotInMips16Mode, // STR_W = 711
12359 CEFBS_HasMSA, // ST_F16 = 712
12360 CEFBS_InMicroMips, // SWM_MM = 713
12361 CEFBS_None, // SZ_B_PSEUDO = 714
12362 CEFBS_None, // SZ_D_PSEUDO = 715
12363 CEFBS_None, // SZ_H_PSEUDO = 716
12364 CEFBS_None, // SZ_V_PSEUDO = 717
12365 CEFBS_None, // SZ_W_PSEUDO = 718
12366 CEFBS_HasCnMipsP, // SaaAddr = 719
12367 CEFBS_HasCnMipsP, // SaadAddr = 720
12368 CEFBS_InMips16Mode, // SelBeqZ = 721
12369 CEFBS_InMips16Mode, // SelBneZ = 722
12370 CEFBS_InMips16Mode, // SelTBteqZCmp = 723
12371 CEFBS_InMips16Mode, // SelTBteqZCmpi = 724
12372 CEFBS_InMips16Mode, // SelTBteqZSlt = 725
12373 CEFBS_InMips16Mode, // SelTBteqZSlti = 726
12374 CEFBS_InMips16Mode, // SelTBteqZSltiu = 727
12375 CEFBS_InMips16Mode, // SelTBteqZSltu = 728
12376 CEFBS_InMips16Mode, // SelTBtneZCmp = 729
12377 CEFBS_InMips16Mode, // SelTBtneZCmpi = 730
12378 CEFBS_InMips16Mode, // SelTBtneZSlt = 731
12379 CEFBS_InMips16Mode, // SelTBtneZSlti = 732
12380 CEFBS_InMips16Mode, // SelTBtneZSltiu = 733
12381 CEFBS_InMips16Mode, // SelTBtneZSltu = 734
12382 CEFBS_InMips16Mode, // SltCCRxRy16 = 735
12383 CEFBS_InMips16Mode, // SltiCCRxImmX16 = 736
12384 CEFBS_InMips16Mode, // SltiuCCRxImmX16 = 737
12385 CEFBS_InMips16Mode, // SltuCCRxRy16 = 738
12386 CEFBS_InMips16Mode, // SltuRxRyRz16 = 739
12387 CEFBS_HasStdEnc_NotInMips16Mode_NotInMicroMips, // TAILCALL = 740
12388 CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // TAILCALL64R6REG = 741
12389 CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // TAILCALLHB64R6REG = 742
12390 CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // TAILCALLHBR6REG = 743
12391 CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // TAILCALLR6REG = 744
12392 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // TAILCALLREG = 745
12393 CEFBS_HasStdEnc_IsPTR64bit_HasMips3_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // TAILCALLREG64 = 746
12394 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // TAILCALLREGHB = 747
12395 CEFBS_HasStdEnc_IsPTR64bit_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // TAILCALLREGHB64 = 748
12396 CEFBS_InMicroMips_NotMips32r6, // TAILCALLREG_MM = 749
12397 CEFBS_InMicroMips_HasMips32r6, // TAILCALLREG_MMR6 = 750
12398 CEFBS_InMicroMips_NotMips32r6, // TAILCALL_MM = 751
12399 CEFBS_InMicroMips_HasMips32r6, // TAILCALL_MMR6 = 752
12400 CEFBS_HasStdEnc_NotInMicroMips, // TRAP = 753
12401 CEFBS_InMicroMips, // TRAP_MM = 754
12402 CEFBS_InMicroMips_NotMips32r6_NotMips64r6, // UDIV_MM_Pseudo = 755
12403 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // UDivIMacro = 756
12404 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // UDivMacro = 757
12405 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // URemIMacro = 758
12406 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // URemMacro = 759
12407 CEFBS_None, // Ulh = 760
12408 CEFBS_None, // Ulhu = 761
12409 CEFBS_None, // Ulw = 762
12410 CEFBS_None, // Ush = 763
12411 CEFBS_None, // Usw = 764
12412 CEFBS_HasStdEnc_HasMSA, // XOR_V_D_PSEUDO = 765
12413 CEFBS_HasStdEnc_HasMSA, // XOR_V_H_PSEUDO = 766
12414 CEFBS_HasStdEnc_HasMSA, // XOR_V_W_PSEUDO = 767
12415 CEFBS_HasDSP, // ABSQ_S_PH = 768
12416 CEFBS_InMicroMips_HasDSP, // ABSQ_S_PH_MM = 769
12417 CEFBS_HasDSPR2, // ABSQ_S_QB = 770
12418 CEFBS_InMicroMips_HasDSPR2, // ABSQ_S_QB_MMR2 = 771
12419 CEFBS_HasDSP, // ABSQ_S_W = 772
12420 CEFBS_InMicroMips_HasDSP, // ABSQ_S_W_MM = 773
12421 CEFBS_HasStdEnc_NotInMicroMips, // ADD = 774
12422 CEFBS_HasStdEnc_HasMips32r6, // ADDIUPC = 775
12423 CEFBS_InMicroMips_NotMips32r6, // ADDIUPC_MM = 776
12424 CEFBS_InMicroMips_HasMips32r6, // ADDIUPC_MMR6 = 777
12425 CEFBS_InMicroMips, // ADDIUR1SP_MM = 778
12426 CEFBS_InMicroMips, // ADDIUR2_MM = 779
12427 CEFBS_InMicroMips, // ADDIUS5_MM = 780
12428 CEFBS_InMicroMips, // ADDIUSP_MM = 781
12429 CEFBS_InMicroMips_HasMips32r6, // ADDIU_MMR6 = 782
12430 CEFBS_HasDSPR2, // ADDQH_PH = 783
12431 CEFBS_InMicroMips_HasDSPR2, // ADDQH_PH_MMR2 = 784
12432 CEFBS_HasDSPR2, // ADDQH_R_PH = 785
12433 CEFBS_InMicroMips_HasDSPR2, // ADDQH_R_PH_MMR2 = 786
12434 CEFBS_HasDSPR2, // ADDQH_R_W = 787
12435 CEFBS_InMicroMips_HasDSPR2, // ADDQH_R_W_MMR2 = 788
12436 CEFBS_HasDSPR2, // ADDQH_W = 789
12437 CEFBS_InMicroMips_HasDSPR2, // ADDQH_W_MMR2 = 790
12438 CEFBS_HasDSP, // ADDQ_PH = 791
12439 CEFBS_InMicroMips_HasDSP, // ADDQ_PH_MM = 792
12440 CEFBS_HasDSP, // ADDQ_S_PH = 793
12441 CEFBS_InMicroMips_HasDSP, // ADDQ_S_PH_MM = 794
12442 CEFBS_HasDSP, // ADDQ_S_W = 795
12443 CEFBS_InMicroMips_HasDSP, // ADDQ_S_W_MM = 796
12444 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, // ADDR_PS64 = 797
12445 CEFBS_HasDSP, // ADDSC = 798
12446 CEFBS_InMicroMips_HasDSP, // ADDSC_MM = 799
12447 CEFBS_HasStdEnc_HasMSA, // ADDS_A_B = 800
12448 CEFBS_HasStdEnc_HasMSA, // ADDS_A_D = 801
12449 CEFBS_HasStdEnc_HasMSA, // ADDS_A_H = 802
12450 CEFBS_HasStdEnc_HasMSA, // ADDS_A_W = 803
12451 CEFBS_HasStdEnc_HasMSA, // ADDS_S_B = 804
12452 CEFBS_HasStdEnc_HasMSA, // ADDS_S_D = 805
12453 CEFBS_HasStdEnc_HasMSA, // ADDS_S_H = 806
12454 CEFBS_HasStdEnc_HasMSA, // ADDS_S_W = 807
12455 CEFBS_HasStdEnc_HasMSA, // ADDS_U_B = 808
12456 CEFBS_HasStdEnc_HasMSA, // ADDS_U_D = 809
12457 CEFBS_HasStdEnc_HasMSA, // ADDS_U_H = 810
12458 CEFBS_HasStdEnc_HasMSA, // ADDS_U_W = 811
12459 CEFBS_InMicroMips_NotMips32r6, // ADDU16_MM = 812
12460 CEFBS_InMicroMips_HasMips32r6, // ADDU16_MMR6 = 813
12461 CEFBS_HasDSPR2, // ADDUH_QB = 814
12462 CEFBS_InMicroMips_HasDSPR2, // ADDUH_QB_MMR2 = 815
12463 CEFBS_HasDSPR2, // ADDUH_R_QB = 816
12464 CEFBS_InMicroMips_HasDSPR2, // ADDUH_R_QB_MMR2 = 817
12465 CEFBS_InMicroMips_HasMips32r6, // ADDU_MMR6 = 818
12466 CEFBS_HasDSPR2, // ADDU_PH = 819
12467 CEFBS_InMicroMips_HasDSPR2, // ADDU_PH_MMR2 = 820
12468 CEFBS_HasDSP, // ADDU_QB = 821
12469 CEFBS_InMicroMips_HasDSP, // ADDU_QB_MM = 822
12470 CEFBS_HasDSPR2, // ADDU_S_PH = 823
12471 CEFBS_InMicroMips_HasDSPR2, // ADDU_S_PH_MMR2 = 824
12472 CEFBS_HasDSP, // ADDU_S_QB = 825
12473 CEFBS_InMicroMips_HasDSP, // ADDU_S_QB_MM = 826
12474 CEFBS_HasStdEnc_HasMSA, // ADDVI_B = 827
12475 CEFBS_HasStdEnc_HasMSA, // ADDVI_D = 828
12476 CEFBS_HasStdEnc_HasMSA, // ADDVI_H = 829
12477 CEFBS_HasStdEnc_HasMSA, // ADDVI_W = 830
12478 CEFBS_HasStdEnc_HasMSA, // ADDV_B = 831
12479 CEFBS_HasStdEnc_HasMSA, // ADDV_D = 832
12480 CEFBS_HasStdEnc_HasMSA, // ADDV_H = 833
12481 CEFBS_HasStdEnc_HasMSA, // ADDV_W = 834
12482 CEFBS_HasDSP, // ADDWC = 835
12483 CEFBS_InMicroMips_HasDSP, // ADDWC_MM = 836
12484 CEFBS_HasStdEnc_HasMSA, // ADD_A_B = 837
12485 CEFBS_HasStdEnc_HasMSA, // ADD_A_D = 838
12486 CEFBS_HasStdEnc_HasMSA, // ADD_A_H = 839
12487 CEFBS_HasStdEnc_HasMSA, // ADD_A_W = 840
12488 CEFBS_InMicroMips_NotMips32r6, // ADD_MM = 841
12489 CEFBS_InMicroMips_HasMips32r6, // ADD_MMR6 = 842
12490 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // ADDi = 843
12491 CEFBS_InMicroMips_NotMips32r6, // ADDi_MM = 844
12492 CEFBS_HasStdEnc_NotInMicroMips, // ADDiu = 845
12493 CEFBS_InMicroMips_NotMips32r6, // ADDiu_MM = 846
12494 CEFBS_HasStdEnc_NotInMicroMips, // ADDu = 847
12495 CEFBS_InMicroMips_NotMips32r6, // ADDu_MM = 848
12496 CEFBS_HasStdEnc_HasMips32r6, // ALIGN = 849
12497 CEFBS_InMicroMips_HasMips32r6, // ALIGN_MMR6 = 850
12498 CEFBS_HasStdEnc_HasMips32r6, // ALUIPC = 851
12499 CEFBS_InMicroMips_HasMips32r6, // ALUIPC_MMR6 = 852
12500 CEFBS_HasStdEnc_NotInMicroMips, // AND = 853
12501 CEFBS_InMicroMips_NotMips32r6, // AND16_MM = 854
12502 CEFBS_InMicroMips_HasMips32r6, // AND16_MMR6 = 855
12503 CEFBS_NotInMips16Mode_IsGP64bit, // AND64 = 856
12504 CEFBS_InMicroMips_NotMips32r6, // ANDI16_MM = 857
12505 CEFBS_InMicroMips_HasMips32r6, // ANDI16_MMR6 = 858
12506 CEFBS_HasStdEnc_HasMSA, // ANDI_B = 859
12507 CEFBS_InMicroMips_HasMips32r6, // ANDI_MMR6 = 860
12508 CEFBS_InMicroMips_NotMips32r6, // AND_MM = 861
12509 CEFBS_InMicroMips_HasMips32r6, // AND_MMR6 = 862
12510 CEFBS_HasStdEnc_HasMSA, // AND_V = 863
12511 CEFBS_HasStdEnc_NotInMicroMips, // ANDi = 864
12512 CEFBS_NotInMips16Mode_IsGP64bit, // ANDi64 = 865
12513 CEFBS_InMicroMips_NotMips32r6, // ANDi_MM = 866
12514 CEFBS_HasDSPR2, // APPEND = 867
12515 CEFBS_InMicroMips_HasDSPR2, // APPEND_MMR2 = 868
12516 CEFBS_HasStdEnc_HasMSA, // ASUB_S_B = 869
12517 CEFBS_HasStdEnc_HasMSA, // ASUB_S_D = 870
12518 CEFBS_HasStdEnc_HasMSA, // ASUB_S_H = 871
12519 CEFBS_HasStdEnc_HasMSA, // ASUB_S_W = 872
12520 CEFBS_HasStdEnc_HasMSA, // ASUB_U_B = 873
12521 CEFBS_HasStdEnc_HasMSA, // ASUB_U_D = 874
12522 CEFBS_HasStdEnc_HasMSA, // ASUB_U_H = 875
12523 CEFBS_HasStdEnc_HasMSA, // ASUB_U_W = 876
12524 CEFBS_HasStdEnc_HasMips32r6, // AUI = 877
12525 CEFBS_HasStdEnc_HasMips32r6, // AUIPC = 878
12526 CEFBS_InMicroMips_HasMips32r6, // AUIPC_MMR6 = 879
12527 CEFBS_InMicroMips_HasMips32r6, // AUI_MMR6 = 880
12528 CEFBS_HasStdEnc_HasMSA, // AVER_S_B = 881
12529 CEFBS_HasStdEnc_HasMSA, // AVER_S_D = 882
12530 CEFBS_HasStdEnc_HasMSA, // AVER_S_H = 883
12531 CEFBS_HasStdEnc_HasMSA, // AVER_S_W = 884
12532 CEFBS_HasStdEnc_HasMSA, // AVER_U_B = 885
12533 CEFBS_HasStdEnc_HasMSA, // AVER_U_D = 886
12534 CEFBS_HasStdEnc_HasMSA, // AVER_U_H = 887
12535 CEFBS_HasStdEnc_HasMSA, // AVER_U_W = 888
12536 CEFBS_HasStdEnc_HasMSA, // AVE_S_B = 889
12537 CEFBS_HasStdEnc_HasMSA, // AVE_S_D = 890
12538 CEFBS_HasStdEnc_HasMSA, // AVE_S_H = 891
12539 CEFBS_HasStdEnc_HasMSA, // AVE_S_W = 892
12540 CEFBS_HasStdEnc_HasMSA, // AVE_U_B = 893
12541 CEFBS_HasStdEnc_HasMSA, // AVE_U_D = 894
12542 CEFBS_HasStdEnc_HasMSA, // AVE_U_H = 895
12543 CEFBS_HasStdEnc_HasMSA, // AVE_U_W = 896
12544 CEFBS_InMips16Mode, // AddiuRxImmX16 = 897
12545 CEFBS_InMips16Mode, // AddiuRxPcImmX16 = 898
12546 CEFBS_InMips16Mode, // AddiuRxRxImm16 = 899
12547 CEFBS_InMips16Mode, // AddiuRxRxImmX16 = 900
12548 CEFBS_InMips16Mode, // AddiuRxRyOffMemX16 = 901
12549 CEFBS_InMips16Mode, // AddiuSpImm16 = 902
12550 CEFBS_InMips16Mode, // AddiuSpImmX16 = 903
12551 CEFBS_InMips16Mode, // AdduRxRyRz16 = 904
12552 CEFBS_InMips16Mode, // AndRxRxRy16 = 905
12553 CEFBS_InMicroMips, // B16_MM = 906
12554 CEFBS_HasCnMips, // BADDu = 907
12555 CEFBS_HasStdEnc_HasMips32r6, // BAL = 908
12556 CEFBS_HasStdEnc_HasMips32r6, // BALC = 909
12557 CEFBS_InMicroMips_HasMips32r6, // BALC_MMR6 = 910
12558 CEFBS_HasDSPR2, // BALIGN = 911
12559 CEFBS_InMicroMips_HasDSPR2, // BALIGN_MMR2 = 912
12560 CEFBS_HasCnMips, // BBIT0 = 913
12561 CEFBS_HasCnMips, // BBIT032 = 914
12562 CEFBS_HasCnMips, // BBIT1 = 915
12563 CEFBS_HasCnMips, // BBIT132 = 916
12564 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BC = 917
12565 CEFBS_InMicroMips_HasMips32r6, // BC16_MMR6 = 918
12566 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // BC1EQZ = 919
12567 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // BC1EQZC_MMR6 = 920
12568 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // BC1F = 921
12569 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // BC1FL = 922
12570 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // BC1F_MM = 923
12571 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // BC1NEZ = 924
12572 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // BC1NEZC_MMR6 = 925
12573 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // BC1T = 926
12574 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // BC1TL = 927
12575 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // BC1T_MM = 928
12576 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BC2EQZ = 929
12577 CEFBS_InMicroMips_HasMips32r6, // BC2EQZC_MMR6 = 930
12578 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BC2NEZ = 931
12579 CEFBS_InMicroMips_HasMips32r6, // BC2NEZC_MMR6 = 932
12580 CEFBS_HasStdEnc_HasMSA, // BCLRI_B = 933
12581 CEFBS_HasStdEnc_HasMSA, // BCLRI_D = 934
12582 CEFBS_HasStdEnc_HasMSA, // BCLRI_H = 935
12583 CEFBS_HasStdEnc_HasMSA, // BCLRI_W = 936
12584 CEFBS_HasStdEnc_HasMSA, // BCLR_B = 937
12585 CEFBS_HasStdEnc_HasMSA, // BCLR_D = 938
12586 CEFBS_HasStdEnc_HasMSA, // BCLR_H = 939
12587 CEFBS_HasStdEnc_HasMSA, // BCLR_W = 940
12588 CEFBS_InMicroMips_HasMips32r6, // BC_MMR6 = 941
12589 CEFBS_HasStdEnc_NotInMicroMips, // BEQ = 942
12590 CEFBS_NotInMips16Mode_IsGP64bit, // BEQ64 = 943
12591 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BEQC = 944
12592 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BEQC64 = 945
12593 CEFBS_InMicroMips_HasMips32r6, // BEQC_MMR6 = 946
12594 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BEQL = 947
12595 CEFBS_InMicroMips_NotMips32r6, // BEQZ16_MM = 948
12596 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BEQZALC = 949
12597 CEFBS_InMicroMips_HasMips32r6, // BEQZALC_MMR6 = 950
12598 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BEQZC = 951
12599 CEFBS_InMicroMips_HasMips32r6, // BEQZC16_MMR6 = 952
12600 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BEQZC64 = 953
12601 CEFBS_InMicroMips_NotMips32r6, // BEQZC_MM = 954
12602 CEFBS_InMicroMips_HasMips32r6, // BEQZC_MMR6 = 955
12603 CEFBS_InMicroMips_NotMips32r6, // BEQ_MM = 956
12604 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGEC = 957
12605 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BGEC64 = 958
12606 CEFBS_InMicroMips_HasMips32r6, // BGEC_MMR6 = 959
12607 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGEUC = 960
12608 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BGEUC64 = 961
12609 CEFBS_InMicroMips_HasMips32r6, // BGEUC_MMR6 = 962
12610 CEFBS_HasStdEnc_NotInMicroMips, // BGEZ = 963
12611 CEFBS_NotInMips16Mode_IsGP64bit, // BGEZ64 = 964
12612 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // BGEZAL = 965
12613 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGEZALC = 966
12614 CEFBS_InMicroMips_HasMips32r6, // BGEZALC_MMR6 = 967
12615 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BGEZALL = 968
12616 CEFBS_InMicroMips_NotMips32r6, // BGEZALS_MM = 969
12617 CEFBS_InMicroMips_NotMips32r6, // BGEZAL_MM = 970
12618 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGEZC = 971
12619 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BGEZC64 = 972
12620 CEFBS_InMicroMips_HasMips32r6, // BGEZC_MMR6 = 973
12621 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BGEZL = 974
12622 CEFBS_InMicroMips_NotMips32r6, // BGEZ_MM = 975
12623 CEFBS_HasStdEnc_NotInMicroMips, // BGTZ = 976
12624 CEFBS_NotInMips16Mode_IsGP64bit, // BGTZ64 = 977
12625 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGTZALC = 978
12626 CEFBS_InMicroMips_HasMips32r6, // BGTZALC_MMR6 = 979
12627 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGTZC = 980
12628 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BGTZC64 = 981
12629 CEFBS_InMicroMips_HasMips32r6, // BGTZC_MMR6 = 982
12630 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BGTZL = 983
12631 CEFBS_InMicroMips_NotMips32r6, // BGTZ_MM = 984
12632 CEFBS_HasStdEnc_HasMSA, // BINSLI_B = 985
12633 CEFBS_HasStdEnc_HasMSA, // BINSLI_D = 986
12634 CEFBS_HasStdEnc_HasMSA, // BINSLI_H = 987
12635 CEFBS_HasStdEnc_HasMSA, // BINSLI_W = 988
12636 CEFBS_HasStdEnc_HasMSA, // BINSL_B = 989
12637 CEFBS_HasStdEnc_HasMSA, // BINSL_D = 990
12638 CEFBS_HasStdEnc_HasMSA, // BINSL_H = 991
12639 CEFBS_HasStdEnc_HasMSA, // BINSL_W = 992
12640 CEFBS_HasStdEnc_HasMSA, // BINSRI_B = 993
12641 CEFBS_HasStdEnc_HasMSA, // BINSRI_D = 994
12642 CEFBS_HasStdEnc_HasMSA, // BINSRI_H = 995
12643 CEFBS_HasStdEnc_HasMSA, // BINSRI_W = 996
12644 CEFBS_HasStdEnc_HasMSA, // BINSR_B = 997
12645 CEFBS_HasStdEnc_HasMSA, // BINSR_D = 998
12646 CEFBS_HasStdEnc_HasMSA, // BINSR_H = 999
12647 CEFBS_HasStdEnc_HasMSA, // BINSR_W = 1000
12648 CEFBS_HasDSP, // BITREV = 1001
12649 CEFBS_InMicroMips_HasDSP, // BITREV_MM = 1002
12650 CEFBS_HasStdEnc_HasMips32r6, // BITSWAP = 1003
12651 CEFBS_InMicroMips_HasMips32r6, // BITSWAP_MMR6 = 1004
12652 CEFBS_HasStdEnc_NotInMicroMips, // BLEZ = 1005
12653 CEFBS_NotInMips16Mode_IsGP64bit, // BLEZ64 = 1006
12654 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLEZALC = 1007
12655 CEFBS_InMicroMips_HasMips32r6, // BLEZALC_MMR6 = 1008
12656 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLEZC = 1009
12657 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BLEZC64 = 1010
12658 CEFBS_InMicroMips_HasMips32r6, // BLEZC_MMR6 = 1011
12659 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BLEZL = 1012
12660 CEFBS_InMicroMips_NotMips32r6, // BLEZ_MM = 1013
12661 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLTC = 1014
12662 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BLTC64 = 1015
12663 CEFBS_InMicroMips_HasMips32r6, // BLTC_MMR6 = 1016
12664 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLTUC = 1017
12665 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BLTUC64 = 1018
12666 CEFBS_InMicroMips_HasMips32r6, // BLTUC_MMR6 = 1019
12667 CEFBS_HasStdEnc_NotInMicroMips, // BLTZ = 1020
12668 CEFBS_NotInMips16Mode_IsGP64bit, // BLTZ64 = 1021
12669 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // BLTZAL = 1022
12670 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLTZALC = 1023
12671 CEFBS_InMicroMips_HasMips32r6, // BLTZALC_MMR6 = 1024
12672 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BLTZALL = 1025
12673 CEFBS_InMicroMips_NotMips32r6, // BLTZALS_MM = 1026
12674 CEFBS_InMicroMips_NotMips32r6, // BLTZAL_MM = 1027
12675 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLTZC = 1028
12676 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BLTZC64 = 1029
12677 CEFBS_InMicroMips_HasMips32r6, // BLTZC_MMR6 = 1030
12678 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BLTZL = 1031
12679 CEFBS_InMicroMips_NotMips32r6, // BLTZ_MM = 1032
12680 CEFBS_HasStdEnc_HasMSA, // BMNZI_B = 1033
12681 CEFBS_HasStdEnc_HasMSA, // BMNZ_V = 1034
12682 CEFBS_HasStdEnc_HasMSA, // BMZI_B = 1035
12683 CEFBS_HasStdEnc_HasMSA, // BMZ_V = 1036
12684 CEFBS_HasStdEnc_NotInMicroMips, // BNE = 1037
12685 CEFBS_NotInMips16Mode_IsGP64bit, // BNE64 = 1038
12686 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BNEC = 1039
12687 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BNEC64 = 1040
12688 CEFBS_InMicroMips_HasMips32r6, // BNEC_MMR6 = 1041
12689 CEFBS_HasStdEnc_HasMSA, // BNEGI_B = 1042
12690 CEFBS_HasStdEnc_HasMSA, // BNEGI_D = 1043
12691 CEFBS_HasStdEnc_HasMSA, // BNEGI_H = 1044
12692 CEFBS_HasStdEnc_HasMSA, // BNEGI_W = 1045
12693 CEFBS_HasStdEnc_HasMSA, // BNEG_B = 1046
12694 CEFBS_HasStdEnc_HasMSA, // BNEG_D = 1047
12695 CEFBS_HasStdEnc_HasMSA, // BNEG_H = 1048
12696 CEFBS_HasStdEnc_HasMSA, // BNEG_W = 1049
12697 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BNEL = 1050
12698 CEFBS_InMicroMips_NotMips32r6, // BNEZ16_MM = 1051
12699 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BNEZALC = 1052
12700 CEFBS_InMicroMips_HasMips32r6, // BNEZALC_MMR6 = 1053
12701 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BNEZC = 1054
12702 CEFBS_InMicroMips_HasMips32r6, // BNEZC16_MMR6 = 1055
12703 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BNEZC64 = 1056
12704 CEFBS_InMicroMips_NotMips32r6, // BNEZC_MM = 1057
12705 CEFBS_InMicroMips_HasMips32r6, // BNEZC_MMR6 = 1058
12706 CEFBS_InMicroMips_NotMips32r6, // BNE_MM = 1059
12707 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BNVC = 1060
12708 CEFBS_InMicroMips_HasMips32r6, // BNVC_MMR6 = 1061
12709 CEFBS_HasStdEnc_HasMSA, // BNZ_B = 1062
12710 CEFBS_HasStdEnc_HasMSA, // BNZ_D = 1063
12711 CEFBS_HasStdEnc_HasMSA, // BNZ_H = 1064
12712 CEFBS_HasStdEnc_HasMSA, // BNZ_V = 1065
12713 CEFBS_HasStdEnc_HasMSA, // BNZ_W = 1066
12714 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BOVC = 1067
12715 CEFBS_InMicroMips_HasMips32r6, // BOVC_MMR6 = 1068
12716 CEFBS_HasDSP_NotInMicroMips, // BPOSGE32 = 1069
12717 CEFBS_InMicroMips_HasDSPR3, // BPOSGE32C_MMR3 = 1070
12718 CEFBS_InMicroMips_NotMips32r6_HasDSP, // BPOSGE32_MM = 1071
12719 CEFBS_HasStdEnc_NotInMicroMips, // BREAK = 1072
12720 CEFBS_InMicroMips_NotMips32r6, // BREAK16_MM = 1073
12721 CEFBS_InMicroMips_HasMips32r6, // BREAK16_MMR6 = 1074
12722 CEFBS_InMicroMips, // BREAK_MM = 1075
12723 CEFBS_InMicroMips_HasMips32r6, // BREAK_MMR6 = 1076
12724 CEFBS_HasStdEnc_HasMSA, // BSELI_B = 1077
12725 CEFBS_HasStdEnc_HasMSA, // BSEL_V = 1078
12726 CEFBS_HasStdEnc_HasMSA, // BSETI_B = 1079
12727 CEFBS_HasStdEnc_HasMSA, // BSETI_D = 1080
12728 CEFBS_HasStdEnc_HasMSA, // BSETI_H = 1081
12729 CEFBS_HasStdEnc_HasMSA, // BSETI_W = 1082
12730 CEFBS_HasStdEnc_HasMSA, // BSET_B = 1083
12731 CEFBS_HasStdEnc_HasMSA, // BSET_D = 1084
12732 CEFBS_HasStdEnc_HasMSA, // BSET_H = 1085
12733 CEFBS_HasStdEnc_HasMSA, // BSET_W = 1086
12734 CEFBS_HasStdEnc_HasMSA, // BZ_B = 1087
12735 CEFBS_HasStdEnc_HasMSA, // BZ_D = 1088
12736 CEFBS_HasStdEnc_HasMSA, // BZ_H = 1089
12737 CEFBS_HasStdEnc_HasMSA, // BZ_V = 1090
12738 CEFBS_HasStdEnc_HasMSA, // BZ_W = 1091
12739 CEFBS_InMips16Mode, // BeqzRxImm16 = 1092
12740 CEFBS_InMips16Mode, // BeqzRxImmX16 = 1093
12741 CEFBS_InMips16Mode, // Bimm16 = 1094
12742 CEFBS_InMips16Mode, // BimmX16 = 1095
12743 CEFBS_InMips16Mode, // BnezRxImm16 = 1096
12744 CEFBS_InMips16Mode, // BnezRxImmX16 = 1097
12745 CEFBS_InMips16Mode, // Break16 = 1098
12746 CEFBS_InMips16Mode, // Bteqz16 = 1099
12747 CEFBS_InMips16Mode, // BteqzX16 = 1100
12748 CEFBS_InMips16Mode, // Btnez16 = 1101
12749 CEFBS_InMips16Mode, // BtnezX16 = 1102
12750 CEFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips, // CACHE = 1103
12751 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // CACHEE = 1104
12752 CEFBS_InMicroMips_HasEVA, // CACHEE_MM = 1105
12753 CEFBS_InMicroMips_NotMips32r6, // CACHE_MM = 1106
12754 CEFBS_InMicroMips_HasMips32r6, // CACHE_MMR6 = 1107
12755 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // CACHE_R6 = 1108
12756 CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, // CEIL_L_D64 = 1109
12757 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CEIL_L_D_MMR6 = 1110
12758 CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // CEIL_L_S = 1111
12759 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CEIL_L_S_MMR6 = 1112
12760 CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // CEIL_W_D32 = 1113
12761 CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // CEIL_W_D64 = 1114
12762 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CEIL_W_D_MMR6 = 1115
12763 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CEIL_W_MM = 1116
12764 CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // CEIL_W_S = 1117
12765 CEFBS_InMicroMips_IsNotSoftFloat, // CEIL_W_S_MM = 1118
12766 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CEIL_W_S_MMR6 = 1119
12767 CEFBS_HasStdEnc_HasMSA, // CEQI_B = 1120
12768 CEFBS_HasStdEnc_HasMSA, // CEQI_D = 1121
12769 CEFBS_HasStdEnc_HasMSA, // CEQI_H = 1122
12770 CEFBS_HasStdEnc_HasMSA, // CEQI_W = 1123
12771 CEFBS_HasStdEnc_HasMSA, // CEQ_B = 1124
12772 CEFBS_HasStdEnc_HasMSA, // CEQ_D = 1125
12773 CEFBS_HasStdEnc_HasMSA, // CEQ_H = 1126
12774 CEFBS_HasStdEnc_HasMSA, // CEQ_W = 1127
12775 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // CFC1 = 1128
12776 CEFBS_InMicroMips_IsNotSoftFloat, // CFC1_MM = 1129
12777 CEFBS_InMicroMips, // CFC2_MM = 1130
12778 CEFBS_HasStdEnc_HasMSA, // CFCMSA = 1131
12779 CEFBS_HasMips64_HasCnMips_NotInMicroMips, // CINS = 1132
12780 CEFBS_HasMips64_HasCnMips_NotInMicroMips, // CINS32 = 1133
12781 CEFBS_HasMips64_HasCnMips_NotInMicroMips, // CINS64_32 = 1134
12782 CEFBS_HasMips64_HasCnMips_NotInMicroMips, // CINS_i32 = 1135
12783 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CLASS_D = 1136
12784 CEFBS_InMicroMips_HasMips32r6, // CLASS_D_MMR6 = 1137
12785 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CLASS_S = 1138
12786 CEFBS_InMicroMips_HasMips32r6, // CLASS_S_MMR6 = 1139
12787 CEFBS_HasStdEnc_HasMSA, // CLEI_S_B = 1140
12788 CEFBS_HasStdEnc_HasMSA, // CLEI_S_D = 1141
12789 CEFBS_HasStdEnc_HasMSA, // CLEI_S_H = 1142
12790 CEFBS_HasStdEnc_HasMSA, // CLEI_S_W = 1143
12791 CEFBS_HasStdEnc_HasMSA, // CLEI_U_B = 1144
12792 CEFBS_HasStdEnc_HasMSA, // CLEI_U_D = 1145
12793 CEFBS_HasStdEnc_HasMSA, // CLEI_U_H = 1146
12794 CEFBS_HasStdEnc_HasMSA, // CLEI_U_W = 1147
12795 CEFBS_HasStdEnc_HasMSA, // CLE_S_B = 1148
12796 CEFBS_HasStdEnc_HasMSA, // CLE_S_D = 1149
12797 CEFBS_HasStdEnc_HasMSA, // CLE_S_H = 1150
12798 CEFBS_HasStdEnc_HasMSA, // CLE_S_W = 1151
12799 CEFBS_HasStdEnc_HasMSA, // CLE_U_B = 1152
12800 CEFBS_HasStdEnc_HasMSA, // CLE_U_D = 1153
12801 CEFBS_HasStdEnc_HasMSA, // CLE_U_H = 1154
12802 CEFBS_HasStdEnc_HasMSA, // CLE_U_W = 1155
12803 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // CLO = 1156
12804 CEFBS_InMicroMips, // CLO_MM = 1157
12805 CEFBS_InMicroMips_HasMips32r6, // CLO_MMR6 = 1158
12806 CEFBS_HasStdEnc_HasMips32r6, // CLO_R6 = 1159
12807 CEFBS_HasStdEnc_HasMSA, // CLTI_S_B = 1160
12808 CEFBS_HasStdEnc_HasMSA, // CLTI_S_D = 1161
12809 CEFBS_HasStdEnc_HasMSA, // CLTI_S_H = 1162
12810 CEFBS_HasStdEnc_HasMSA, // CLTI_S_W = 1163
12811 CEFBS_HasStdEnc_HasMSA, // CLTI_U_B = 1164
12812 CEFBS_HasStdEnc_HasMSA, // CLTI_U_D = 1165
12813 CEFBS_HasStdEnc_HasMSA, // CLTI_U_H = 1166
12814 CEFBS_HasStdEnc_HasMSA, // CLTI_U_W = 1167
12815 CEFBS_HasStdEnc_HasMSA, // CLT_S_B = 1168
12816 CEFBS_HasStdEnc_HasMSA, // CLT_S_D = 1169
12817 CEFBS_HasStdEnc_HasMSA, // CLT_S_H = 1170
12818 CEFBS_HasStdEnc_HasMSA, // CLT_S_W = 1171
12819 CEFBS_HasStdEnc_HasMSA, // CLT_U_B = 1172
12820 CEFBS_HasStdEnc_HasMSA, // CLT_U_D = 1173
12821 CEFBS_HasStdEnc_HasMSA, // CLT_U_H = 1174
12822 CEFBS_HasStdEnc_HasMSA, // CLT_U_W = 1175
12823 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // CLZ = 1176
12824 CEFBS_InMicroMips, // CLZ_MM = 1177
12825 CEFBS_InMicroMips_HasMips32r6, // CLZ_MMR6 = 1178
12826 CEFBS_HasStdEnc_HasMips32r6, // CLZ_R6 = 1179
12827 CEFBS_HasDSPR2, // CMPGDU_EQ_QB = 1180
12828 CEFBS_InMicroMips_HasDSPR2, // CMPGDU_EQ_QB_MMR2 = 1181
12829 CEFBS_HasDSPR2, // CMPGDU_LE_QB = 1182
12830 CEFBS_InMicroMips_HasDSPR2, // CMPGDU_LE_QB_MMR2 = 1183
12831 CEFBS_HasDSPR2, // CMPGDU_LT_QB = 1184
12832 CEFBS_InMicroMips_HasDSPR2, // CMPGDU_LT_QB_MMR2 = 1185
12833 CEFBS_HasDSP, // CMPGU_EQ_QB = 1186
12834 CEFBS_InMicroMips_HasDSP, // CMPGU_EQ_QB_MM = 1187
12835 CEFBS_HasDSP, // CMPGU_LE_QB = 1188
12836 CEFBS_InMicroMips_HasDSP, // CMPGU_LE_QB_MM = 1189
12837 CEFBS_HasDSP, // CMPGU_LT_QB = 1190
12838 CEFBS_InMicroMips_HasDSP, // CMPGU_LT_QB_MM = 1191
12839 CEFBS_HasDSP, // CMPU_EQ_QB = 1192
12840 CEFBS_InMicroMips_HasDSP, // CMPU_EQ_QB_MM = 1193
12841 CEFBS_HasDSP, // CMPU_LE_QB = 1194
12842 CEFBS_InMicroMips_HasDSP, // CMPU_LE_QB_MM = 1195
12843 CEFBS_HasDSP, // CMPU_LT_QB = 1196
12844 CEFBS_InMicroMips_HasDSP, // CMPU_LT_QB_MM = 1197
12845 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_AF_D_MMR6 = 1198
12846 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_AF_S_MMR6 = 1199
12847 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_EQ_D = 1200
12848 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_EQ_D_MMR6 = 1201
12849 CEFBS_HasDSP, // CMP_EQ_PH = 1202
12850 CEFBS_InMicroMips_HasDSP, // CMP_EQ_PH_MM = 1203
12851 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_EQ_S = 1204
12852 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_EQ_S_MMR6 = 1205
12853 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_F_D = 1206
12854 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_F_S = 1207
12855 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_LE_D = 1208
12856 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_LE_D_MMR6 = 1209
12857 CEFBS_HasDSP, // CMP_LE_PH = 1210
12858 CEFBS_InMicroMips_HasDSP, // CMP_LE_PH_MM = 1211
12859 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_LE_S = 1212
12860 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_LE_S_MMR6 = 1213
12861 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_LT_D = 1214
12862 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_LT_D_MMR6 = 1215
12863 CEFBS_HasDSP, // CMP_LT_PH = 1216
12864 CEFBS_InMicroMips_HasDSP, // CMP_LT_PH_MM = 1217
12865 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_LT_S = 1218
12866 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_LT_S_MMR6 = 1219
12867 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SAF_D = 1220
12868 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SAF_D_MMR6 = 1221
12869 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SAF_S = 1222
12870 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SAF_S_MMR6 = 1223
12871 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SEQ_D = 1224
12872 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SEQ_D_MMR6 = 1225
12873 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SEQ_S = 1226
12874 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SEQ_S_MMR6 = 1227
12875 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SLE_D = 1228
12876 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SLE_D_MMR6 = 1229
12877 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SLE_S = 1230
12878 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SLE_S_MMR6 = 1231
12879 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SLT_D = 1232
12880 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SLT_D_MMR6 = 1233
12881 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SLT_S = 1234
12882 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SLT_S_MMR6 = 1235
12883 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SUEQ_D = 1236
12884 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SUEQ_D_MMR6 = 1237
12885 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SUEQ_S = 1238
12886 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SUEQ_S_MMR6 = 1239
12887 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SULE_D = 1240
12888 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SULE_D_MMR6 = 1241
12889 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SULE_S = 1242
12890 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SULE_S_MMR6 = 1243
12891 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SULT_D = 1244
12892 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SULT_D_MMR6 = 1245
12893 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SULT_S = 1246
12894 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SULT_S_MMR6 = 1247
12895 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SUN_D = 1248
12896 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SUN_D_MMR6 = 1249
12897 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SUN_S = 1250
12898 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SUN_S_MMR6 = 1251
12899 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_UEQ_D = 1252
12900 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_UEQ_D_MMR6 = 1253
12901 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_UEQ_S = 1254
12902 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_UEQ_S_MMR6 = 1255
12903 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_ULE_D = 1256
12904 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_ULE_D_MMR6 = 1257
12905 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_ULE_S = 1258
12906 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_ULE_S_MMR6 = 1259
12907 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_ULT_D = 1260
12908 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_ULT_D_MMR6 = 1261
12909 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_ULT_S = 1262
12910 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_ULT_S_MMR6 = 1263
12911 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_UN_D = 1264
12912 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_UN_D_MMR6 = 1265
12913 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_UN_S = 1266
12914 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_UN_S_MMR6 = 1267
12915 CEFBS_HasStdEnc_HasMSA, // COPY_S_B = 1268
12916 CEFBS_HasStdEnc_HasMSA_HasMips64, // COPY_S_D = 1269
12917 CEFBS_HasStdEnc_HasMSA, // COPY_S_H = 1270
12918 CEFBS_HasStdEnc_HasMSA, // COPY_S_W = 1271
12919 CEFBS_HasStdEnc_HasMSA, // COPY_U_B = 1272
12920 CEFBS_HasStdEnc_HasMSA, // COPY_U_H = 1273
12921 CEFBS_HasStdEnc_HasMSA_HasMips64, // COPY_U_W = 1274
12922 CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32B = 1275
12923 CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32CB = 1276
12924 CEFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips, // CRC32CD = 1277
12925 CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32CH = 1278
12926 CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32CW = 1279
12927 CEFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips, // CRC32D = 1280
12928 CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32H = 1281
12929 CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32W = 1282
12930 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // CTC1 = 1283
12931 CEFBS_InMicroMips_IsNotSoftFloat, // CTC1_MM = 1284
12932 CEFBS_InMicroMips, // CTC2_MM = 1285
12933 CEFBS_HasStdEnc_HasMSA, // CTCMSA = 1286
12934 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_D32_S = 1287
12935 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CVT_D32_S_MM = 1288
12936 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_D32_W = 1289
12937 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CVT_D32_W_MM = 1290
12938 CEFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, // CVT_D64_L = 1291
12939 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_D64_S = 1292
12940 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_D64_S_MM = 1293
12941 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_D64_W = 1294
12942 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_D64_W_MM = 1295
12943 CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, // CVT_D_L_MMR6 = 1296
12944 CEFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, // CVT_L_D64 = 1297
12945 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_L_D64_MM = 1298
12946 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CVT_L_D_MMR6 = 1299
12947 CEFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, // CVT_L_S = 1300
12948 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_L_S_MM = 1301
12949 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CVT_L_S_MMR6 = 1302
12950 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, // CVT_PS_PW64 = 1303
12951 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // CVT_PS_S64 = 1304
12952 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, // CVT_PW_PS64 = 1305
12953 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_S_D32 = 1306
12954 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CVT_S_D32_MM = 1307
12955 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_S_D64 = 1308
12956 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_S_D64_MM = 1309
12957 CEFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, // CVT_S_L = 1310
12958 CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, // CVT_S_L_MMR6 = 1311
12959 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // CVT_S_PL64 = 1312
12960 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // CVT_S_PU64 = 1313
12961 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // CVT_S_W = 1314
12962 CEFBS_InMicroMips_IsNotSoftFloat, // CVT_S_W_MM = 1315
12963 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CVT_S_W_MMR6 = 1316
12964 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_W_D32 = 1317
12965 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CVT_W_D32_MM = 1318
12966 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_W_D64 = 1319
12967 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_W_D64_MM = 1320
12968 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // CVT_W_S = 1321
12969 CEFBS_InMicroMips_IsNotSoftFloat, // CVT_W_S_MM = 1322
12970 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CVT_W_S_MMR6 = 1323
12971 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_EQ_D32 = 1324
12972 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_EQ_D32_MM = 1325
12973 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_EQ_D64 = 1326
12974 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_EQ_D64_MM = 1327
12975 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_EQ_S = 1328
12976 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_EQ_S_MM = 1329
12977 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_F_D32 = 1330
12978 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_F_D32_MM = 1331
12979 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_F_D64 = 1332
12980 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_F_D64_MM = 1333
12981 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_F_S = 1334
12982 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_F_S_MM = 1335
12983 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LE_D32 = 1336
12984 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_LE_D32_MM = 1337
12985 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LE_D64 = 1338
12986 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_LE_D64_MM = 1339
12987 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LE_S = 1340
12988 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_LE_S_MM = 1341
12989 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LT_D32 = 1342
12990 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_LT_D32_MM = 1343
12991 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LT_D64 = 1344
12992 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_LT_D64_MM = 1345
12993 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LT_S = 1346
12994 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_LT_S_MM = 1347
12995 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGE_D32 = 1348
12996 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGE_D32_MM = 1349
12997 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGE_D64 = 1350
12998 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGE_D64_MM = 1351
12999 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGE_S = 1352
13000 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_NGE_S_MM = 1353
13001 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGLE_D32 = 1354
13002 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGLE_D32_MM = 1355
13003 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGLE_D64 = 1356
13004 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGLE_D64_MM = 1357
13005 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGLE_S = 1358
13006 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_NGLE_S_MM = 1359
13007 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGL_D32 = 1360
13008 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGL_D32_MM = 1361
13009 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGL_D64 = 1362
13010 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGL_D64_MM = 1363
13011 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGL_S = 1364
13012 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_NGL_S_MM = 1365
13013 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGT_D32 = 1366
13014 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGT_D32_MM = 1367
13015 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGT_D64 = 1368
13016 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGT_D64_MM = 1369
13017 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGT_S = 1370
13018 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_NGT_S_MM = 1371
13019 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLE_D32 = 1372
13020 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_OLE_D32_MM = 1373
13021 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLE_D64 = 1374
13022 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_OLE_D64_MM = 1375
13023 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLE_S = 1376
13024 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_OLE_S_MM = 1377
13025 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLT_D32 = 1378
13026 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_OLT_D32_MM = 1379
13027 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLT_D64 = 1380
13028 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_OLT_D64_MM = 1381
13029 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLT_S = 1382
13030 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_OLT_S_MM = 1383
13031 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SEQ_D32 = 1384
13032 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_SEQ_D32_MM = 1385
13033 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SEQ_D64 = 1386
13034 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_SEQ_D64_MM = 1387
13035 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SEQ_S = 1388
13036 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_SEQ_S_MM = 1389
13037 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SF_D32 = 1390
13038 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_SF_D32_MM = 1391
13039 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SF_D64 = 1392
13040 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_SF_D64_MM = 1393
13041 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SF_S = 1394
13042 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_SF_S_MM = 1395
13043 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UEQ_D32 = 1396
13044 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_UEQ_D32_MM = 1397
13045 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UEQ_D64 = 1398
13046 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_UEQ_D64_MM = 1399
13047 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UEQ_S = 1400
13048 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_UEQ_S_MM = 1401
13049 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULE_D32 = 1402
13050 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_ULE_D32_MM = 1403
13051 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULE_D64 = 1404
13052 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_ULE_D64_MM = 1405
13053 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULE_S = 1406
13054 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_ULE_S_MM = 1407
13055 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULT_D32 = 1408
13056 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_ULT_D32_MM = 1409
13057 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULT_D64 = 1410
13058 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_ULT_D64_MM = 1411
13059 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULT_S = 1412
13060 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_ULT_S_MM = 1413
13061 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UN_D32 = 1414
13062 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_UN_D32_MM = 1415
13063 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UN_D64 = 1416
13064 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_UN_D64_MM = 1417
13065 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UN_S = 1418
13066 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_UN_S_MM = 1419
13067 CEFBS_InMips16Mode, // CmpRxRy16 = 1420
13068 CEFBS_InMips16Mode, // CmpiRxImm16 = 1421
13069 CEFBS_InMips16Mode, // CmpiRxImmX16 = 1422
13070 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DADD = 1423
13071 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // DADDi = 1424
13072 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DADDiu = 1425
13073 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DADDu = 1426
13074 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DAHI = 1427
13075 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DALIGN = 1428
13076 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DATI = 1429
13077 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DAUI = 1430
13078 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DBITSWAP = 1431
13079 CEFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips, // DCLO = 1432
13080 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DCLO_R6 = 1433
13081 CEFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips, // DCLZ = 1434
13082 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DCLZ_R6 = 1435
13083 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DDIV = 1436
13084 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DDIVU = 1437
13085 CEFBS_HasStdEnc_HasMips32_NotInMicroMips, // DERET = 1438
13086 CEFBS_InMicroMips, // DERET_MM = 1439
13087 CEFBS_InMicroMips_HasMips32r6, // DERET_MMR6 = 1440
13088 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DEXT = 1441
13089 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DEXT64_32 = 1442
13090 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DEXTM = 1443
13091 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DEXTU = 1444
13092 CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // DI = 1445
13093 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DINS = 1446
13094 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DINSM = 1447
13095 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DINSU = 1448
13096 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // DIV = 1449
13097 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // DIVU = 1450
13098 CEFBS_InMicroMips_HasMips32r6, // DIVU_MMR6 = 1451
13099 CEFBS_InMicroMips_HasMips32r6, // DIV_MMR6 = 1452
13100 CEFBS_HasStdEnc_HasMSA, // DIV_S_B = 1453
13101 CEFBS_HasStdEnc_HasMSA, // DIV_S_D = 1454
13102 CEFBS_HasStdEnc_HasMSA, // DIV_S_H = 1455
13103 CEFBS_HasStdEnc_HasMSA, // DIV_S_W = 1456
13104 CEFBS_HasStdEnc_HasMSA, // DIV_U_B = 1457
13105 CEFBS_HasStdEnc_HasMSA, // DIV_U_D = 1458
13106 CEFBS_HasStdEnc_HasMSA, // DIV_U_H = 1459
13107 CEFBS_HasStdEnc_HasMSA, // DIV_U_W = 1460
13108 CEFBS_InMicroMips, // DI_MM = 1461
13109 CEFBS_InMicroMips_HasMips32r6, // DI_MMR6 = 1462
13110 CEFBS_HasStdEnc_HasMSA_HasMips64, // DLSA = 1463
13111 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DLSA_R6 = 1464
13112 CEFBS_HasStdEnc_IsGP64bit_HasMips3, // DMFC0 = 1465
13113 CEFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips, // DMFC1 = 1466
13114 CEFBS_HasStdEnc_IsGP64bit_HasMips3, // DMFC2 = 1467
13115 CEFBS_HasCnMips, // DMFC2_OCTEON = 1468
13116 CEFBS_HasStdEnc_HasMips64r5_HasVirt, // DMFGC0 = 1469
13117 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMOD = 1470
13118 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMODU = 1471
13119 CEFBS_HasStdEnc_HasMT_NotInMicroMips, // DMT = 1472
13120 CEFBS_HasStdEnc_IsGP64bit_HasMips3, // DMTC0 = 1473
13121 CEFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips, // DMTC1 = 1474
13122 CEFBS_HasStdEnc_IsGP64bit_HasMips3, // DMTC2 = 1475
13123 CEFBS_HasCnMips, // DMTC2_OCTEON = 1476
13124 CEFBS_HasStdEnc_HasMips64r5_HasVirt, // DMTGC0 = 1477
13125 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMUH = 1478
13126 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMUHU = 1479
13127 CEFBS_HasCnMips, // DMUL = 1480
13128 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DMULT = 1481
13129 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DMULTu = 1482
13130 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMULU = 1483
13131 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMUL_R6 = 1484
13132 CEFBS_HasStdEnc_HasMSA, // DOTP_S_D = 1485
13133 CEFBS_HasStdEnc_HasMSA, // DOTP_S_H = 1486
13134 CEFBS_HasStdEnc_HasMSA, // DOTP_S_W = 1487
13135 CEFBS_HasStdEnc_HasMSA, // DOTP_U_D = 1488
13136 CEFBS_HasStdEnc_HasMSA, // DOTP_U_H = 1489
13137 CEFBS_HasStdEnc_HasMSA, // DOTP_U_W = 1490
13138 CEFBS_HasStdEnc_HasMSA, // DPADD_S_D = 1491
13139 CEFBS_HasStdEnc_HasMSA, // DPADD_S_H = 1492
13140 CEFBS_HasStdEnc_HasMSA, // DPADD_S_W = 1493
13141 CEFBS_HasStdEnc_HasMSA, // DPADD_U_D = 1494
13142 CEFBS_HasStdEnc_HasMSA, // DPADD_U_H = 1495
13143 CEFBS_HasStdEnc_HasMSA, // DPADD_U_W = 1496
13144 CEFBS_HasDSPR2, // DPAQX_SA_W_PH = 1497
13145 CEFBS_InMicroMips_HasDSPR2, // DPAQX_SA_W_PH_MMR2 = 1498
13146 CEFBS_HasDSPR2, // DPAQX_S_W_PH = 1499
13147 CEFBS_InMicroMips_HasDSPR2, // DPAQX_S_W_PH_MMR2 = 1500
13148 CEFBS_HasDSP, // DPAQ_SA_L_W = 1501
13149 CEFBS_InMicroMips_HasDSP, // DPAQ_SA_L_W_MM = 1502
13150 CEFBS_HasDSP, // DPAQ_S_W_PH = 1503
13151 CEFBS_InMicroMips_HasDSP, // DPAQ_S_W_PH_MM = 1504
13152 CEFBS_HasDSP, // DPAU_H_QBL = 1505
13153 CEFBS_InMicroMips_HasDSP, // DPAU_H_QBL_MM = 1506
13154 CEFBS_HasDSP, // DPAU_H_QBR = 1507
13155 CEFBS_InMicroMips_HasDSP, // DPAU_H_QBR_MM = 1508
13156 CEFBS_HasDSPR2, // DPAX_W_PH = 1509
13157 CEFBS_InMicroMips_HasDSPR2, // DPAX_W_PH_MMR2 = 1510
13158 CEFBS_HasDSPR2, // DPA_W_PH = 1511
13159 CEFBS_InMicroMips_HasDSPR2, // DPA_W_PH_MMR2 = 1512
13160 CEFBS_HasCnMips, // DPOP = 1513
13161 CEFBS_HasDSPR2, // DPSQX_SA_W_PH = 1514
13162 CEFBS_InMicroMips_HasDSPR2, // DPSQX_SA_W_PH_MMR2 = 1515
13163 CEFBS_HasDSPR2, // DPSQX_S_W_PH = 1516
13164 CEFBS_InMicroMips_HasDSPR2, // DPSQX_S_W_PH_MMR2 = 1517
13165 CEFBS_HasDSP, // DPSQ_SA_L_W = 1518
13166 CEFBS_InMicroMips_HasDSP, // DPSQ_SA_L_W_MM = 1519
13167 CEFBS_HasDSP, // DPSQ_S_W_PH = 1520
13168 CEFBS_InMicroMips_HasDSP, // DPSQ_S_W_PH_MM = 1521
13169 CEFBS_HasStdEnc_HasMSA, // DPSUB_S_D = 1522
13170 CEFBS_HasStdEnc_HasMSA, // DPSUB_S_H = 1523
13171 CEFBS_HasStdEnc_HasMSA, // DPSUB_S_W = 1524
13172 CEFBS_HasStdEnc_HasMSA, // DPSUB_U_D = 1525
13173 CEFBS_HasStdEnc_HasMSA, // DPSUB_U_H = 1526
13174 CEFBS_HasStdEnc_HasMSA, // DPSUB_U_W = 1527
13175 CEFBS_HasDSP, // DPSU_H_QBL = 1528
13176 CEFBS_InMicroMips_HasDSP, // DPSU_H_QBL_MM = 1529
13177 CEFBS_HasDSP, // DPSU_H_QBR = 1530
13178 CEFBS_InMicroMips_HasDSP, // DPSU_H_QBR_MM = 1531
13179 CEFBS_HasDSPR2, // DPSX_W_PH = 1532
13180 CEFBS_InMicroMips_HasDSPR2, // DPSX_W_PH_MMR2 = 1533
13181 CEFBS_HasDSPR2, // DPS_W_PH = 1534
13182 CEFBS_InMicroMips_HasDSPR2, // DPS_W_PH_MMR2 = 1535
13183 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DROTR = 1536
13184 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DROTR32 = 1537
13185 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DROTRV = 1538
13186 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DSBH = 1539
13187 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DSDIV = 1540
13188 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DSHD = 1541
13189 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSLL = 1542
13190 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSLL32 = 1543
13191 CEFBS_NotInMips16Mode_IsGP64bit, // DSLL64_32 = 1544
13192 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSLLV = 1545
13193 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRA = 1546
13194 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRA32 = 1547
13195 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRAV = 1548
13196 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRL = 1549
13197 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRL32 = 1550
13198 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRLV = 1551
13199 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSUB = 1552
13200 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSUBu = 1553
13201 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DUDIV = 1554
13202 CEFBS_HasStdEnc_HasMips32r6, // DVP = 1555
13203 CEFBS_HasStdEnc_HasMT_NotInMicroMips, // DVPE = 1556
13204 CEFBS_InMicroMips_HasMips32r6, // DVP_MMR6 = 1557
13205 CEFBS_InMips16Mode, // DivRxRy16 = 1558
13206 CEFBS_InMips16Mode, // DivuRxRy16 = 1559
13207 CEFBS_HasStdEnc_NotInMicroMips, // EHB = 1560
13208 CEFBS_InMicroMips, // EHB_MM = 1561
13209 CEFBS_InMicroMips_HasMips32r6, // EHB_MMR6 = 1562
13210 CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // EI = 1563
13211 CEFBS_InMicroMips, // EI_MM = 1564
13212 CEFBS_InMicroMips_HasMips32r6, // EI_MMR6 = 1565
13213 CEFBS_HasStdEnc_HasMT_NotInMicroMips, // EMT = 1566
13214 CEFBS_HasStdEnc_HasMips3_32_NotInMicroMips, // ERET = 1567
13215 CEFBS_HasStdEnc_HasMips32r5_NotInMicroMips, // ERETNC = 1568
13216 CEFBS_InMicroMips_HasMips32r6, // ERETNC_MMR6 = 1569
13217 CEFBS_InMicroMips, // ERET_MM = 1570
13218 CEFBS_InMicroMips_HasMips32r6, // ERET_MMR6 = 1571
13219 CEFBS_HasStdEnc_HasMips32r6, // EVP = 1572
13220 CEFBS_HasStdEnc_HasMT_NotInMicroMips, // EVPE = 1573
13221 CEFBS_InMicroMips_HasMips32r6, // EVP_MMR6 = 1574
13222 CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // EXT = 1575
13223 CEFBS_HasDSP, // EXTP = 1576
13224 CEFBS_HasDSP, // EXTPDP = 1577
13225 CEFBS_HasDSP, // EXTPDPV = 1578
13226 CEFBS_InMicroMips_HasDSP, // EXTPDPV_MM = 1579
13227 CEFBS_InMicroMips_HasDSP, // EXTPDP_MM = 1580
13228 CEFBS_HasDSP, // EXTPV = 1581
13229 CEFBS_InMicroMips_HasDSP, // EXTPV_MM = 1582
13230 CEFBS_InMicroMips_HasDSP, // EXTP_MM = 1583
13231 CEFBS_HasDSP, // EXTRV_RS_W = 1584
13232 CEFBS_InMicroMips_HasDSP, // EXTRV_RS_W_MM = 1585
13233 CEFBS_HasDSP, // EXTRV_R_W = 1586
13234 CEFBS_InMicroMips_HasDSP, // EXTRV_R_W_MM = 1587
13235 CEFBS_HasDSP, // EXTRV_S_H = 1588
13236 CEFBS_InMicroMips_HasDSP, // EXTRV_S_H_MM = 1589
13237 CEFBS_HasDSP, // EXTRV_W = 1590
13238 CEFBS_InMicroMips_HasDSP, // EXTRV_W_MM = 1591
13239 CEFBS_HasDSP, // EXTR_RS_W = 1592
13240 CEFBS_InMicroMips_HasDSP, // EXTR_RS_W_MM = 1593
13241 CEFBS_HasDSP, // EXTR_R_W = 1594
13242 CEFBS_InMicroMips_HasDSP, // EXTR_R_W_MM = 1595
13243 CEFBS_HasDSP, // EXTR_S_H = 1596
13244 CEFBS_InMicroMips_HasDSP, // EXTR_S_H_MM = 1597
13245 CEFBS_HasDSP, // EXTR_W = 1598
13246 CEFBS_InMicroMips_HasDSP, // EXTR_W_MM = 1599
13247 CEFBS_HasMips64_HasCnMips_NotInMicroMips, // EXTS = 1600
13248 CEFBS_HasMips64_HasCnMips_NotInMicroMips, // EXTS32 = 1601
13249 CEFBS_InMicroMips_NotMips32r6, // EXT_MM = 1602
13250 CEFBS_InMicroMips_HasMips32r6, // EXT_MMR6 = 1603
13251 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FABS_D32 = 1604
13252 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FABS_D32_MM = 1605
13253 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FABS_D64 = 1606
13254 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FABS_D64_MM = 1607
13255 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FABS_S = 1608
13256 CEFBS_InMicroMips_IsNotSoftFloat, // FABS_S_MM = 1609
13257 CEFBS_HasStdEnc_HasMSA, // FADD_D = 1610
13258 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FADD_D32 = 1611
13259 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FADD_D32_MM = 1612
13260 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FADD_D64 = 1613
13261 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FADD_D64_MM = 1614
13262 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FADD_PS64 = 1615
13263 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FADD_S = 1616
13264 CEFBS_InMicroMips_IsNotSoftFloat, // FADD_S_MM = 1617
13265 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FADD_S_MMR6 = 1618
13266 CEFBS_HasStdEnc_HasMSA, // FADD_W = 1619
13267 CEFBS_HasStdEnc_HasMSA, // FCAF_D = 1620
13268 CEFBS_HasStdEnc_HasMSA, // FCAF_W = 1621
13269 CEFBS_HasStdEnc_HasMSA, // FCEQ_D = 1622
13270 CEFBS_HasStdEnc_HasMSA, // FCEQ_W = 1623
13271 CEFBS_HasStdEnc_HasMSA, // FCLASS_D = 1624
13272 CEFBS_HasStdEnc_HasMSA, // FCLASS_W = 1625
13273 CEFBS_HasStdEnc_HasMSA, // FCLE_D = 1626
13274 CEFBS_HasStdEnc_HasMSA, // FCLE_W = 1627
13275 CEFBS_HasStdEnc_HasMSA, // FCLT_D = 1628
13276 CEFBS_HasStdEnc_HasMSA, // FCLT_W = 1629
13277 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FCMP_D32 = 1630
13278 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // FCMP_D32_MM = 1631
13279 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat, // FCMP_D64 = 1632
13280 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FCMP_S32 = 1633
13281 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // FCMP_S32_MM = 1634
13282 CEFBS_HasStdEnc_HasMSA, // FCNE_D = 1635
13283 CEFBS_HasStdEnc_HasMSA, // FCNE_W = 1636
13284 CEFBS_HasStdEnc_HasMSA, // FCOR_D = 1637
13285 CEFBS_HasStdEnc_HasMSA, // FCOR_W = 1638
13286 CEFBS_HasStdEnc_HasMSA, // FCUEQ_D = 1639
13287 CEFBS_HasStdEnc_HasMSA, // FCUEQ_W = 1640
13288 CEFBS_HasStdEnc_HasMSA, // FCULE_D = 1641
13289 CEFBS_HasStdEnc_HasMSA, // FCULE_W = 1642
13290 CEFBS_HasStdEnc_HasMSA, // FCULT_D = 1643
13291 CEFBS_HasStdEnc_HasMSA, // FCULT_W = 1644
13292 CEFBS_HasStdEnc_HasMSA, // FCUNE_D = 1645
13293 CEFBS_HasStdEnc_HasMSA, // FCUNE_W = 1646
13294 CEFBS_HasStdEnc_HasMSA, // FCUN_D = 1647
13295 CEFBS_HasStdEnc_HasMSA, // FCUN_W = 1648
13296 CEFBS_HasStdEnc_HasMSA, // FDIV_D = 1649
13297 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FDIV_D32 = 1650
13298 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FDIV_D32_MM = 1651
13299 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FDIV_D64 = 1652
13300 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FDIV_D64_MM = 1653
13301 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FDIV_S = 1654
13302 CEFBS_InMicroMips_IsNotSoftFloat, // FDIV_S_MM = 1655
13303 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FDIV_S_MMR6 = 1656
13304 CEFBS_HasStdEnc_HasMSA, // FDIV_W = 1657
13305 CEFBS_HasStdEnc_HasMSA, // FEXDO_H = 1658
13306 CEFBS_HasStdEnc_HasMSA, // FEXDO_W = 1659
13307 CEFBS_HasStdEnc_HasMSA, // FEXP2_D = 1660
13308 CEFBS_HasStdEnc_HasMSA, // FEXP2_W = 1661
13309 CEFBS_HasStdEnc_HasMSA, // FEXUPL_D = 1662
13310 CEFBS_HasStdEnc_HasMSA, // FEXUPL_W = 1663
13311 CEFBS_HasStdEnc_HasMSA, // FEXUPR_D = 1664
13312 CEFBS_HasStdEnc_HasMSA, // FEXUPR_W = 1665
13313 CEFBS_HasStdEnc_HasMSA, // FFINT_S_D = 1666
13314 CEFBS_HasStdEnc_HasMSA, // FFINT_S_W = 1667
13315 CEFBS_HasStdEnc_HasMSA, // FFINT_U_D = 1668
13316 CEFBS_HasStdEnc_HasMSA, // FFINT_U_W = 1669
13317 CEFBS_HasStdEnc_HasMSA, // FFQL_D = 1670
13318 CEFBS_HasStdEnc_HasMSA, // FFQL_W = 1671
13319 CEFBS_HasStdEnc_HasMSA, // FFQR_D = 1672
13320 CEFBS_HasStdEnc_HasMSA, // FFQR_W = 1673
13321 CEFBS_HasStdEnc_HasMSA, // FILL_B = 1674
13322 CEFBS_HasStdEnc_HasMSA_HasMips64, // FILL_D = 1675
13323 CEFBS_HasStdEnc_HasMSA, // FILL_H = 1676
13324 CEFBS_HasStdEnc_HasMSA, // FILL_W = 1677
13325 CEFBS_HasStdEnc_HasMSA, // FLOG2_D = 1678
13326 CEFBS_HasStdEnc_HasMSA, // FLOG2_W = 1679
13327 CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, // FLOOR_L_D64 = 1680
13328 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FLOOR_L_D_MMR6 = 1681
13329 CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FLOOR_L_S = 1682
13330 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FLOOR_L_S_MMR6 = 1683
13331 CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FLOOR_W_D32 = 1684
13332 CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FLOOR_W_D64 = 1685
13333 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FLOOR_W_D_MMR6 = 1686
13334 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FLOOR_W_MM = 1687
13335 CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // FLOOR_W_S = 1688
13336 CEFBS_InMicroMips_IsNotSoftFloat, // FLOOR_W_S_MM = 1689
13337 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FLOOR_W_S_MMR6 = 1690
13338 CEFBS_HasStdEnc_HasMSA, // FMADD_D = 1691
13339 CEFBS_HasStdEnc_HasMSA, // FMADD_W = 1692
13340 CEFBS_HasStdEnc_HasMSA, // FMAX_A_D = 1693
13341 CEFBS_HasStdEnc_HasMSA, // FMAX_A_W = 1694
13342 CEFBS_HasStdEnc_HasMSA, // FMAX_D = 1695
13343 CEFBS_HasStdEnc_HasMSA, // FMAX_W = 1696
13344 CEFBS_HasStdEnc_HasMSA, // FMIN_A_D = 1697
13345 CEFBS_HasStdEnc_HasMSA, // FMIN_A_W = 1698
13346 CEFBS_HasStdEnc_HasMSA, // FMIN_D = 1699
13347 CEFBS_HasStdEnc_HasMSA, // FMIN_W = 1700
13348 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FMOV_D32 = 1701
13349 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FMOV_D32_MM = 1702
13350 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FMOV_D64 = 1703
13351 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FMOV_D64_MM = 1704
13352 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FMOV_D_MMR6 = 1705
13353 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FMOV_S = 1706
13354 CEFBS_InMicroMips_IsNotSoftFloat, // FMOV_S_MM = 1707
13355 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FMOV_S_MMR6 = 1708
13356 CEFBS_HasStdEnc_HasMSA, // FMSUB_D = 1709
13357 CEFBS_HasStdEnc_HasMSA, // FMSUB_W = 1710
13358 CEFBS_HasStdEnc_HasMSA, // FMUL_D = 1711
13359 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FMUL_D32 = 1712
13360 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FMUL_D32_MM = 1713
13361 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FMUL_D64 = 1714
13362 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FMUL_D64_MM = 1715
13363 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FMUL_PS64 = 1716
13364 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FMUL_S = 1717
13365 CEFBS_InMicroMips_IsNotSoftFloat, // FMUL_S_MM = 1718
13366 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FMUL_S_MMR6 = 1719
13367 CEFBS_HasStdEnc_HasMSA, // FMUL_W = 1720
13368 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FNEG_D32 = 1721
13369 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FNEG_D32_MM = 1722
13370 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FNEG_D64 = 1723
13371 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FNEG_D64_MM = 1724
13372 CEFBS_HasStdEnc_IsNotSoftFloat, // FNEG_S = 1725
13373 CEFBS_InMicroMips_IsNotSoftFloat, // FNEG_S_MM = 1726
13374 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FNEG_S_MMR6 = 1727
13375 CEFBS_HasStdEnc_HasMT_NotInMicroMips, // FORK = 1728
13376 CEFBS_HasStdEnc_HasMSA, // FRCP_D = 1729
13377 CEFBS_HasStdEnc_HasMSA, // FRCP_W = 1730
13378 CEFBS_HasStdEnc_HasMSA, // FRINT_D = 1731
13379 CEFBS_HasStdEnc_HasMSA, // FRINT_W = 1732
13380 CEFBS_HasStdEnc_HasMSA, // FRSQRT_D = 1733
13381 CEFBS_HasStdEnc_HasMSA, // FRSQRT_W = 1734
13382 CEFBS_HasStdEnc_HasMSA, // FSAF_D = 1735
13383 CEFBS_HasStdEnc_HasMSA, // FSAF_W = 1736
13384 CEFBS_HasStdEnc_HasMSA, // FSEQ_D = 1737
13385 CEFBS_HasStdEnc_HasMSA, // FSEQ_W = 1738
13386 CEFBS_HasStdEnc_HasMSA, // FSLE_D = 1739
13387 CEFBS_HasStdEnc_HasMSA, // FSLE_W = 1740
13388 CEFBS_HasStdEnc_HasMSA, // FSLT_D = 1741
13389 CEFBS_HasStdEnc_HasMSA, // FSLT_W = 1742
13390 CEFBS_HasStdEnc_HasMSA, // FSNE_D = 1743
13391 CEFBS_HasStdEnc_HasMSA, // FSNE_W = 1744
13392 CEFBS_HasStdEnc_HasMSA, // FSOR_D = 1745
13393 CEFBS_HasStdEnc_HasMSA, // FSOR_W = 1746
13394 CEFBS_HasStdEnc_HasMSA, // FSQRT_D = 1747
13395 CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FSQRT_D32 = 1748
13396 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FSQRT_D32_MM = 1749
13397 CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FSQRT_D64 = 1750
13398 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FSQRT_D64_MM = 1751
13399 CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // FSQRT_S = 1752
13400 CEFBS_InMicroMips_IsNotSoftFloat, // FSQRT_S_MM = 1753
13401 CEFBS_HasStdEnc_HasMSA, // FSQRT_W = 1754
13402 CEFBS_HasStdEnc_HasMSA, // FSUB_D = 1755
13403 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FSUB_D32 = 1756
13404 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FSUB_D32_MM = 1757
13405 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FSUB_D64 = 1758
13406 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FSUB_D64_MM = 1759
13407 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FSUB_PS64 = 1760
13408 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FSUB_S = 1761
13409 CEFBS_InMicroMips_IsNotSoftFloat, // FSUB_S_MM = 1762
13410 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FSUB_S_MMR6 = 1763
13411 CEFBS_HasStdEnc_HasMSA, // FSUB_W = 1764
13412 CEFBS_HasStdEnc_HasMSA, // FSUEQ_D = 1765
13413 CEFBS_HasStdEnc_HasMSA, // FSUEQ_W = 1766
13414 CEFBS_HasStdEnc_HasMSA, // FSULE_D = 1767
13415 CEFBS_HasStdEnc_HasMSA, // FSULE_W = 1768
13416 CEFBS_HasStdEnc_HasMSA, // FSULT_D = 1769
13417 CEFBS_HasStdEnc_HasMSA, // FSULT_W = 1770
13418 CEFBS_HasStdEnc_HasMSA, // FSUNE_D = 1771
13419 CEFBS_HasStdEnc_HasMSA, // FSUNE_W = 1772
13420 CEFBS_HasStdEnc_HasMSA, // FSUN_D = 1773
13421 CEFBS_HasStdEnc_HasMSA, // FSUN_W = 1774
13422 CEFBS_HasStdEnc_HasMSA, // FTINT_S_D = 1775
13423 CEFBS_HasStdEnc_HasMSA, // FTINT_S_W = 1776
13424 CEFBS_HasStdEnc_HasMSA, // FTINT_U_D = 1777
13425 CEFBS_HasStdEnc_HasMSA, // FTINT_U_W = 1778
13426 CEFBS_HasStdEnc_HasMSA, // FTQ_H = 1779
13427 CEFBS_HasStdEnc_HasMSA, // FTQ_W = 1780
13428 CEFBS_HasStdEnc_HasMSA, // FTRUNC_S_D = 1781
13429 CEFBS_HasStdEnc_HasMSA, // FTRUNC_S_W = 1782
13430 CEFBS_HasStdEnc_HasMSA, // FTRUNC_U_D = 1783
13431 CEFBS_HasStdEnc_HasMSA, // FTRUNC_U_W = 1784
13432 CEFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips, // GINVI = 1785
13433 CEFBS_InMicroMips_HasMips32r6_HasGINV, // GINVI_MMR6 = 1786
13434 CEFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips, // GINVT = 1787
13435 CEFBS_InMicroMips_HasMips32r6_HasGINV, // GINVT_MMR6 = 1788
13436 CEFBS_HasStdEnc_HasMSA, // HADD_S_D = 1789
13437 CEFBS_HasStdEnc_HasMSA, // HADD_S_H = 1790
13438 CEFBS_HasStdEnc_HasMSA, // HADD_S_W = 1791
13439 CEFBS_HasStdEnc_HasMSA, // HADD_U_D = 1792
13440 CEFBS_HasStdEnc_HasMSA, // HADD_U_H = 1793
13441 CEFBS_HasStdEnc_HasMSA, // HADD_U_W = 1794
13442 CEFBS_HasStdEnc_HasMSA, // HSUB_S_D = 1795
13443 CEFBS_HasStdEnc_HasMSA, // HSUB_S_H = 1796
13444 CEFBS_HasStdEnc_HasMSA, // HSUB_S_W = 1797
13445 CEFBS_HasStdEnc_HasMSA, // HSUB_U_D = 1798
13446 CEFBS_HasStdEnc_HasMSA, // HSUB_U_H = 1799
13447 CEFBS_HasStdEnc_HasMSA, // HSUB_U_W = 1800
13448 CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // HYPCALL = 1801
13449 CEFBS_InMicroMips_HasMips32r5_HasVirt, // HYPCALL_MM = 1802
13450 CEFBS_HasStdEnc_HasMSA, // ILVEV_B = 1803
13451 CEFBS_HasStdEnc_HasMSA, // ILVEV_D = 1804
13452 CEFBS_HasStdEnc_HasMSA, // ILVEV_H = 1805
13453 CEFBS_HasStdEnc_HasMSA, // ILVEV_W = 1806
13454 CEFBS_HasStdEnc_HasMSA, // ILVL_B = 1807
13455 CEFBS_HasStdEnc_HasMSA, // ILVL_D = 1808
13456 CEFBS_HasStdEnc_HasMSA, // ILVL_H = 1809
13457 CEFBS_HasStdEnc_HasMSA, // ILVL_W = 1810
13458 CEFBS_HasStdEnc_HasMSA, // ILVOD_B = 1811
13459 CEFBS_HasStdEnc_HasMSA, // ILVOD_D = 1812
13460 CEFBS_HasStdEnc_HasMSA, // ILVOD_H = 1813
13461 CEFBS_HasStdEnc_HasMSA, // ILVOD_W = 1814
13462 CEFBS_HasStdEnc_HasMSA, // ILVR_B = 1815
13463 CEFBS_HasStdEnc_HasMSA, // ILVR_D = 1816
13464 CEFBS_HasStdEnc_HasMSA, // ILVR_H = 1817
13465 CEFBS_HasStdEnc_HasMSA, // ILVR_W = 1818
13466 CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // INS = 1819
13467 CEFBS_HasStdEnc_HasMSA, // INSERT_B = 1820
13468 CEFBS_HasStdEnc_HasMSA_HasMips64, // INSERT_D = 1821
13469 CEFBS_HasStdEnc_HasMSA, // INSERT_H = 1822
13470 CEFBS_HasStdEnc_HasMSA, // INSERT_W = 1823
13471 CEFBS_HasDSP, // INSV = 1824
13472 CEFBS_HasStdEnc_HasMSA, // INSVE_B = 1825
13473 CEFBS_HasStdEnc_HasMSA, // INSVE_D = 1826
13474 CEFBS_HasStdEnc_HasMSA, // INSVE_H = 1827
13475 CEFBS_HasStdEnc_HasMSA, // INSVE_W = 1828
13476 CEFBS_InMicroMips_HasDSP, // INSV_MM = 1829
13477 CEFBS_InMicroMips_NotMips32r6, // INS_MM = 1830
13478 CEFBS_InMicroMips_HasMips32r6, // INS_MMR6 = 1831
13479 CEFBS_HasStdEnc_NotInMicroMips, // J = 1832
13480 CEFBS_HasStdEnc_NotInMicroMips, // JAL = 1833
13481 CEFBS_HasStdEnc_NotInMicroMips_NoIndirectJumpGuards, // JALR = 1834
13482 CEFBS_InMicroMips_NotMips32r6, // JALR16_MM = 1835
13483 CEFBS_NotInMips16Mode_IsPTR64bit, // JALR64 = 1836
13484 CEFBS_InMicroMips_HasMips32r6, // JALRC16_MMR6 = 1837
13485 CEFBS_InMicroMips_HasMips32r6, // JALRC_HB_MMR6 = 1838
13486 CEFBS_InMicroMips_HasMips32r6, // JALRC_MMR6 = 1839
13487 CEFBS_InMicroMips_NotMips32r6, // JALRS16_MM = 1840
13488 CEFBS_InMicroMips_NotMips32r6, // JALRS_MM = 1841
13489 CEFBS_HasStdEnc_HasMips32, // JALR_HB = 1842
13490 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // JALR_HB64 = 1843
13491 CEFBS_InMicroMips_NotMips32r6, // JALR_MM = 1844
13492 CEFBS_InMicroMips_NotMips32r6, // JALS_MM = 1845
13493 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // JALX = 1846
13494 CEFBS_InMicroMips_NotMips32r6, // JALX_MM = 1847
13495 CEFBS_InMicroMips_NotMips32r6, // JAL_MM = 1848
13496 CEFBS_HasStdEnc_HasMips32r6, // JIALC = 1849
13497 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // JIALC64 = 1850
13498 CEFBS_InMicroMips_HasMips32r6, // JIALC_MMR6 = 1851
13499 CEFBS_HasStdEnc_HasMips32r6, // JIC = 1852
13500 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // JIC64 = 1853
13501 CEFBS_InMicroMips_HasMips32r6, // JIC_MMR6 = 1854
13502 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // JR = 1855
13503 CEFBS_InMicroMips_NotMips32r6, // JR16_MM = 1856
13504 CEFBS_NotInMips16Mode_IsPTR64bit_NotInMicroMips, // JR64 = 1857
13505 CEFBS_InMicroMips_NotMips32r6, // JRADDIUSP = 1858
13506 CEFBS_InMicroMips_NotMips32r6, // JRC16_MM = 1859
13507 CEFBS_InMicroMips_HasMips32r6, // JRC16_MMR6 = 1860
13508 CEFBS_InMicroMips_HasMips32r6, // JRCADDIUSP_MMR6 = 1861
13509 CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6, // JR_HB = 1862
13510 CEFBS_HasStdEnc_HasMips64_NotMips64r6_NotInMicroMips, // JR_HB64 = 1863
13511 CEFBS_HasStdEnc_HasMips32r6, // JR_HB64_R6 = 1864
13512 CEFBS_HasStdEnc_HasMips32r6, // JR_HB_R6 = 1865
13513 CEFBS_InMicroMips_NotMips32r6, // JR_MM = 1866
13514 CEFBS_InMicroMips_NotMips32r6, // J_MM = 1867
13515 CEFBS_InMips16Mode, // Jal16 = 1868
13516 CEFBS_InMips16Mode, // JalB16 = 1869
13517 CEFBS_InMips16Mode, // JrRa16 = 1870
13518 CEFBS_InMips16Mode, // JrcRa16 = 1871
13519 CEFBS_InMips16Mode, // JrcRx16 = 1872
13520 CEFBS_InMips16Mode, // JumpLinkReg16 = 1873
13521 CEFBS_HasStdEnc_NotInMicroMips, // LB = 1874
13522 CEFBS_NotInMips16Mode_IsGP64bit, // LB64 = 1875
13523 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LBE = 1876
13524 CEFBS_InMicroMips_HasEVA, // LBE_MM = 1877
13525 CEFBS_InMicroMips, // LBU16_MM = 1878
13526 CEFBS_HasDSP, // LBUX = 1879
13527 CEFBS_InMicroMips_HasDSP, // LBUX_MM = 1880
13528 CEFBS_InMicroMips_HasMips32r6, // LBU_MMR6 = 1881
13529 CEFBS_InMicroMips, // LB_MM = 1882
13530 CEFBS_InMicroMips_HasMips32r6, // LB_MMR6 = 1883
13531 CEFBS_HasStdEnc_NotInMicroMips, // LBu = 1884
13532 CEFBS_NotInMips16Mode_IsGP64bit, // LBu64 = 1885
13533 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LBuE = 1886
13534 CEFBS_InMicroMips_HasEVA, // LBuE_MM = 1887
13535 CEFBS_InMicroMips, // LBu_MM = 1888
13536 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // LD = 1889
13537 CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // LDC1 = 1890
13538 CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // LDC164 = 1891
13539 CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, // LDC1_D64_MMR6 = 1892
13540 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // LDC1_MM_D32 = 1893
13541 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // LDC1_MM_D64 = 1894
13542 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // LDC2 = 1895
13543 CEFBS_InMicroMips_HasMips32r6, // LDC2_MMR6 = 1896
13544 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // LDC2_R6 = 1897
13545 CEFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips, // LDC3 = 1898
13546 CEFBS_HasStdEnc_HasMSA, // LDI_B = 1899
13547 CEFBS_HasStdEnc_HasMSA, // LDI_D = 1900
13548 CEFBS_HasStdEnc_HasMSA, // LDI_H = 1901
13549 CEFBS_HasStdEnc_HasMSA, // LDI_W = 1902
13550 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // LDL = 1903
13551 CEFBS_HasStdEnc_HasMips64r6, // LDPC = 1904
13552 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // LDR = 1905
13553 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // LDXC1 = 1906
13554 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, // LDXC164 = 1907
13555 CEFBS_HasStdEnc_HasMSA, // LD_B = 1908
13556 CEFBS_HasStdEnc_HasMSA, // LD_D = 1909
13557 CEFBS_HasStdEnc_HasMSA, // LD_H = 1910
13558 CEFBS_HasStdEnc_HasMSA, // LD_W = 1911
13559 CEFBS_HasStdEnc_NotInMicroMips, // LEA_ADDiu = 1912
13560 CEFBS_NotInMips16Mode_IsGP64bit_NotInMicroMips, // LEA_ADDiu64 = 1913
13561 CEFBS_InMicroMips, // LEA_ADDiu_MM = 1914
13562 CEFBS_HasStdEnc_NotInMicroMips, // LH = 1915
13563 CEFBS_NotInMips16Mode_IsGP64bit, // LH64 = 1916
13564 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LHE = 1917
13565 CEFBS_InMicroMips_HasEVA, // LHE_MM = 1918
13566 CEFBS_InMicroMips, // LHU16_MM = 1919
13567 CEFBS_HasDSP, // LHX = 1920
13568 CEFBS_InMicroMips_HasDSP, // LHX_MM = 1921
13569 CEFBS_InMicroMips, // LH_MM = 1922
13570 CEFBS_HasStdEnc_NotInMicroMips, // LHu = 1923
13571 CEFBS_NotInMips16Mode_IsGP64bit, // LHu64 = 1924
13572 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LHuE = 1925
13573 CEFBS_InMicroMips_HasEVA, // LHuE_MM = 1926
13574 CEFBS_InMicroMips, // LHu_MM = 1927
13575 CEFBS_InMicroMips_NotMips32r6, // LI16_MM = 1928
13576 CEFBS_InMicroMips_HasMips32r6, // LI16_MMR6 = 1929
13577 CEFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // LL = 1930
13578 CEFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // LL64 = 1931
13579 CEFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips, // LL64_R6 = 1932
13580 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // LLD = 1933
13581 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // LLD_R6 = 1934
13582 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LLE = 1935
13583 CEFBS_InMicroMips_HasEVA, // LLE_MM = 1936
13584 CEFBS_InMicroMips_NotMips32r6, // LL_MM = 1937
13585 CEFBS_InMicroMips_HasMips32r6, // LL_MMR6 = 1938
13586 CEFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips, // LL_R6 = 1939
13587 CEFBS_HasStdEnc_HasMSA, // LSA = 1940
13588 CEFBS_InMicroMips_HasMips32r6, // LSA_MMR6 = 1941
13589 CEFBS_HasStdEnc_HasMips32r6, // LSA_R6 = 1942
13590 CEFBS_InMicroMips_HasMips32r6, // LUI_MMR6 = 1943
13591 CEFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // LUXC1 = 1944
13592 CEFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // LUXC164 = 1945
13593 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // LUXC1_MM = 1946
13594 CEFBS_HasStdEnc_NotInMicroMips, // LUi = 1947
13595 CEFBS_NotInMips16Mode_IsGP64bit, // LUi64 = 1948
13596 CEFBS_InMicroMips_NotMips32r6, // LUi_MM = 1949
13597 CEFBS_HasStdEnc_NotInMicroMips, // LW = 1950
13598 CEFBS_InMicroMips, // LW16_MM = 1951
13599 CEFBS_NotInMips16Mode_IsGP64bit, // LW64 = 1952
13600 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // LWC1 = 1953
13601 CEFBS_InMicroMips_IsNotSoftFloat, // LWC1_MM = 1954
13602 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // LWC2 = 1955
13603 CEFBS_InMicroMips_HasMips32r6, // LWC2_MMR6 = 1956
13604 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // LWC2_R6 = 1957
13605 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips, // LWC3 = 1958
13606 CEFBS_NotInMips16Mode_HasDSP, // LWDSP = 1959
13607 CEFBS_InMicroMips_HasDSP, // LWDSP_MM = 1960
13608 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LWE = 1961
13609 CEFBS_InMicroMips_HasEVA, // LWE_MM = 1962
13610 CEFBS_InMicroMips, // LWGP_MM = 1963
13611 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // LWL = 1964
13612 CEFBS_NotInMips16Mode_IsGP64bit, // LWL64 = 1965
13613 CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, // LWLE = 1966
13614 CEFBS_InMicroMips_NotMips32r6_HasEVA, // LWLE_MM = 1967
13615 CEFBS_InMicroMips_NotMips32r6, // LWL_MM = 1968
13616 CEFBS_InMicroMips_NotMips32r6, // LWM16_MM = 1969
13617 CEFBS_InMicroMips_HasMips32r6, // LWM16_MMR6 = 1970
13618 CEFBS_InMicroMips, // LWM32_MM = 1971
13619 CEFBS_HasStdEnc_HasMips32r6, // LWPC = 1972
13620 CEFBS_InMicroMips_HasMips32r6, // LWPC_MMR6 = 1973
13621 CEFBS_InMicroMips, // LWP_MM = 1974
13622 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // LWR = 1975
13623 CEFBS_NotInMips16Mode_IsGP64bit, // LWR64 = 1976
13624 CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, // LWRE = 1977
13625 CEFBS_InMicroMips_NotMips32r6_HasEVA, // LWRE_MM = 1978
13626 CEFBS_InMicroMips_NotMips32r6, // LWR_MM = 1979
13627 CEFBS_InMicroMips, // LWSP_MM = 1980
13628 CEFBS_HasStdEnc_HasMips64r6, // LWUPC = 1981
13629 CEFBS_InMicroMips_NotMips32r6, // LWU_MM = 1982
13630 CEFBS_HasDSP, // LWX = 1983
13631 CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, // LWXC1 = 1984
13632 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // LWXC1_MM = 1985
13633 CEFBS_InMicroMips, // LWXS_MM = 1986
13634 CEFBS_InMicroMips_HasDSP, // LWX_MM = 1987
13635 CEFBS_InMicroMips, // LW_MM = 1988
13636 CEFBS_InMicroMips_HasMips32r6, // LW_MMR6 = 1989
13637 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // LWu = 1990
13638 CEFBS_InMips16Mode, // LbRxRyOffMemX16 = 1991
13639 CEFBS_InMips16Mode, // LbuRxRyOffMemX16 = 1992
13640 CEFBS_InMips16Mode, // LhRxRyOffMemX16 = 1993
13641 CEFBS_InMips16Mode, // LhuRxRyOffMemX16 = 1994
13642 CEFBS_InMips16Mode, // LiRxImm16 = 1995
13643 CEFBS_InMips16Mode, // LiRxImmAlignX16 = 1996
13644 CEFBS_InMips16Mode, // LiRxImmX16 = 1997
13645 CEFBS_InMips16Mode, // LwRxPcTcp16 = 1998
13646 CEFBS_InMips16Mode, // LwRxPcTcpX16 = 1999
13647 CEFBS_InMips16Mode, // LwRxRyOffMemX16 = 2000
13648 CEFBS_InMips16Mode, // LwRxSpImmX16 = 2001
13649 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MADD = 2002
13650 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MADDF_D = 2003
13651 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MADDF_D_MMR6 = 2004
13652 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MADDF_S = 2005
13653 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MADDF_S_MMR6 = 2006
13654 CEFBS_HasStdEnc_HasMSA, // MADDR_Q_H = 2007
13655 CEFBS_HasStdEnc_HasMSA, // MADDR_Q_W = 2008
13656 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MADDU = 2009
13657 CEFBS_HasDSP, // MADDU_DSP = 2010
13658 CEFBS_InMicroMips_HasDSP, // MADDU_DSP_MM = 2011
13659 CEFBS_InMicroMips_NotMips32r6, // MADDU_MM = 2012
13660 CEFBS_HasStdEnc_HasMSA, // MADDV_B = 2013
13661 CEFBS_HasStdEnc_HasMSA, // MADDV_D = 2014
13662 CEFBS_HasStdEnc_HasMSA, // MADDV_H = 2015
13663 CEFBS_HasStdEnc_HasMSA, // MADDV_W = 2016
13664 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MADD_D32 = 2017
13665 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, // MADD_D32_MM = 2018
13666 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MADD_D64 = 2019
13667 CEFBS_HasDSP, // MADD_DSP = 2020
13668 CEFBS_InMicroMips_HasDSP, // MADD_DSP_MM = 2021
13669 CEFBS_InMicroMips_NotMips32r6, // MADD_MM = 2022
13670 CEFBS_HasStdEnc_HasMSA, // MADD_Q_H = 2023
13671 CEFBS_HasStdEnc_HasMSA, // MADD_Q_W = 2024
13672 CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MADD_S = 2025
13673 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, // MADD_S_MM = 2026
13674 CEFBS_HasDSP, // MAQ_SA_W_PHL = 2027
13675 CEFBS_InMicroMips_HasDSP, // MAQ_SA_W_PHL_MM = 2028
13676 CEFBS_HasDSP, // MAQ_SA_W_PHR = 2029
13677 CEFBS_InMicroMips_HasDSP, // MAQ_SA_W_PHR_MM = 2030
13678 CEFBS_HasDSP, // MAQ_S_W_PHL = 2031
13679 CEFBS_InMicroMips_HasDSP, // MAQ_S_W_PHL_MM = 2032
13680 CEFBS_HasDSP, // MAQ_S_W_PHR = 2033
13681 CEFBS_InMicroMips_HasDSP, // MAQ_S_W_PHR_MM = 2034
13682 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MAXA_D = 2035
13683 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MAXA_D_MMR6 = 2036
13684 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MAXA_S = 2037
13685 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MAXA_S_MMR6 = 2038
13686 CEFBS_HasStdEnc_HasMSA, // MAXI_S_B = 2039
13687 CEFBS_HasStdEnc_HasMSA, // MAXI_S_D = 2040
13688 CEFBS_HasStdEnc_HasMSA, // MAXI_S_H = 2041
13689 CEFBS_HasStdEnc_HasMSA, // MAXI_S_W = 2042
13690 CEFBS_HasStdEnc_HasMSA, // MAXI_U_B = 2043
13691 CEFBS_HasStdEnc_HasMSA, // MAXI_U_D = 2044
13692 CEFBS_HasStdEnc_HasMSA, // MAXI_U_H = 2045
13693 CEFBS_HasStdEnc_HasMSA, // MAXI_U_W = 2046
13694 CEFBS_HasStdEnc_HasMSA, // MAX_A_B = 2047
13695 CEFBS_HasStdEnc_HasMSA, // MAX_A_D = 2048
13696 CEFBS_HasStdEnc_HasMSA, // MAX_A_H = 2049
13697 CEFBS_HasStdEnc_HasMSA, // MAX_A_W = 2050
13698 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MAX_D = 2051
13699 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MAX_D_MMR6 = 2052
13700 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MAX_S = 2053
13701 CEFBS_HasStdEnc_HasMSA, // MAX_S_B = 2054
13702 CEFBS_HasStdEnc_HasMSA, // MAX_S_D = 2055
13703 CEFBS_HasStdEnc_HasMSA, // MAX_S_H = 2056
13704 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MAX_S_MMR6 = 2057
13705 CEFBS_HasStdEnc_HasMSA, // MAX_S_W = 2058
13706 CEFBS_HasStdEnc_HasMSA, // MAX_U_B = 2059
13707 CEFBS_HasStdEnc_HasMSA, // MAX_U_D = 2060
13708 CEFBS_HasStdEnc_HasMSA, // MAX_U_H = 2061
13709 CEFBS_HasStdEnc_HasMSA, // MAX_U_W = 2062
13710 CEFBS_HasStdEnc_NotInMicroMips, // MFC0 = 2063
13711 CEFBS_InMicroMips_HasMips32r6, // MFC0_MMR6 = 2064
13712 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // MFC1 = 2065
13713 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // MFC1_D64 = 2066
13714 CEFBS_InMicroMips_IsNotSoftFloat, // MFC1_MM = 2067
13715 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MFC1_MMR6 = 2068
13716 CEFBS_HasStdEnc_NotInMicroMips, // MFC2 = 2069
13717 CEFBS_InMicroMips_HasMips32r6, // MFC2_MMR6 = 2070
13718 CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // MFGC0 = 2071
13719 CEFBS_InMicroMips_HasMips32r5_HasVirt, // MFGC0_MM = 2072
13720 CEFBS_InMicroMips_HasMips32r6, // MFHC0_MMR6 = 2073
13721 CEFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, // MFHC1_D32 = 2074
13722 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // MFHC1_D32_MM = 2075
13723 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, // MFHC1_D64 = 2076
13724 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // MFHC1_D64_MM = 2077
13725 CEFBS_InMicroMips_HasMips32r6, // MFHC2_MMR6 = 2078
13726 CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // MFHGC0 = 2079
13727 CEFBS_InMicroMips_HasMips32r5_HasVirt, // MFHGC0_MM = 2080
13728 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MFHI = 2081
13729 CEFBS_InMicroMips_NotMips32r6, // MFHI16_MM = 2082
13730 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // MFHI64 = 2083
13731 CEFBS_HasDSP, // MFHI_DSP = 2084
13732 CEFBS_InMicroMips_HasDSP, // MFHI_DSP_MM = 2085
13733 CEFBS_InMicroMips_NotMips32r6, // MFHI_MM = 2086
13734 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MFLO = 2087
13735 CEFBS_InMicroMips_NotMips32r6, // MFLO16_MM = 2088
13736 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // MFLO64 = 2089
13737 CEFBS_HasDSP, // MFLO_DSP = 2090
13738 CEFBS_InMicroMips_HasDSP, // MFLO_DSP_MM = 2091
13739 CEFBS_InMicroMips_NotMips32r6, // MFLO_MM = 2092
13740 CEFBS_HasStdEnc_HasMT_NotInMicroMips, // MFTR = 2093
13741 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MINA_D = 2094
13742 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MINA_D_MMR6 = 2095
13743 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MINA_S = 2096
13744 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MINA_S_MMR6 = 2097
13745 CEFBS_HasStdEnc_HasMSA, // MINI_S_B = 2098
13746 CEFBS_HasStdEnc_HasMSA, // MINI_S_D = 2099
13747 CEFBS_HasStdEnc_HasMSA, // MINI_S_H = 2100
13748 CEFBS_HasStdEnc_HasMSA, // MINI_S_W = 2101
13749 CEFBS_HasStdEnc_HasMSA, // MINI_U_B = 2102
13750 CEFBS_HasStdEnc_HasMSA, // MINI_U_D = 2103
13751 CEFBS_HasStdEnc_HasMSA, // MINI_U_H = 2104
13752 CEFBS_HasStdEnc_HasMSA, // MINI_U_W = 2105
13753 CEFBS_HasStdEnc_HasMSA, // MIN_A_B = 2106
13754 CEFBS_HasStdEnc_HasMSA, // MIN_A_D = 2107
13755 CEFBS_HasStdEnc_HasMSA, // MIN_A_H = 2108
13756 CEFBS_HasStdEnc_HasMSA, // MIN_A_W = 2109
13757 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MIN_D = 2110
13758 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MIN_D_MMR6 = 2111
13759 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MIN_S = 2112
13760 CEFBS_HasStdEnc_HasMSA, // MIN_S_B = 2113
13761 CEFBS_HasStdEnc_HasMSA, // MIN_S_D = 2114
13762 CEFBS_HasStdEnc_HasMSA, // MIN_S_H = 2115
13763 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MIN_S_MMR6 = 2116
13764 CEFBS_HasStdEnc_HasMSA, // MIN_S_W = 2117
13765 CEFBS_HasStdEnc_HasMSA, // MIN_U_B = 2118
13766 CEFBS_HasStdEnc_HasMSA, // MIN_U_D = 2119
13767 CEFBS_HasStdEnc_HasMSA, // MIN_U_H = 2120
13768 CEFBS_HasStdEnc_HasMSA, // MIN_U_W = 2121
13769 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MOD = 2122
13770 CEFBS_HasDSP, // MODSUB = 2123
13771 CEFBS_InMicroMips_HasDSP, // MODSUB_MM = 2124
13772 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MODU = 2125
13773 CEFBS_InMicroMips_HasMips32r6, // MODU_MMR6 = 2126
13774 CEFBS_InMicroMips_HasMips32r6, // MOD_MMR6 = 2127
13775 CEFBS_HasStdEnc_HasMSA, // MOD_S_B = 2128
13776 CEFBS_HasStdEnc_HasMSA, // MOD_S_D = 2129
13777 CEFBS_HasStdEnc_HasMSA, // MOD_S_H = 2130
13778 CEFBS_HasStdEnc_HasMSA, // MOD_S_W = 2131
13779 CEFBS_HasStdEnc_HasMSA, // MOD_U_B = 2132
13780 CEFBS_HasStdEnc_HasMSA, // MOD_U_D = 2133
13781 CEFBS_HasStdEnc_HasMSA, // MOD_U_H = 2134
13782 CEFBS_HasStdEnc_HasMSA, // MOD_U_W = 2135
13783 CEFBS_InMicroMips_NotMips32r6, // MOVE16_MM = 2136
13784 CEFBS_InMicroMips_HasMips32r6, // MOVE16_MMR6 = 2137
13785 CEFBS_InMicroMips_NotMips32r6, // MOVEP_MM = 2138
13786 CEFBS_InMicroMips_HasMips32r6, // MOVEP_MMR6 = 2139
13787 CEFBS_HasStdEnc_HasMSA, // MOVE_V = 2140
13788 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_D32 = 2141
13789 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // MOVF_D32_MM = 2142
13790 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_D64 = 2143
13791 CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_I = 2144
13792 CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_I64 = 2145
13793 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVF_I_MM = 2146
13794 CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_S = 2147
13795 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVF_S_MM = 2148
13796 CEFBS_HasStdEnc_IsGP64bit_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I64_D64 = 2149
13797 CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVN_I64_I = 2150
13798 CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVN_I64_I64 = 2151
13799 CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I64_S = 2152
13800 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I_D32 = 2153
13801 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // MOVN_I_D32_MM = 2154
13802 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I_D64 = 2155
13803 CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVN_I_I = 2156
13804 CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVN_I_I64 = 2157
13805 CEFBS_InMicroMips_NotMips32r6, // MOVN_I_MM = 2158
13806 CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I_S = 2159
13807 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVN_I_S_MM = 2160
13808 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_D32 = 2161
13809 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // MOVT_D32_MM = 2162
13810 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_D64 = 2163
13811 CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_I = 2164
13812 CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_I64 = 2165
13813 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVT_I_MM = 2166
13814 CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_S = 2167
13815 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVT_S_MM = 2168
13816 CEFBS_HasStdEnc_IsGP64bit_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I64_D64 = 2169
13817 CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVZ_I64_I = 2170
13818 CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVZ_I64_I64 = 2171
13819 CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I64_S = 2172
13820 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I_D32 = 2173
13821 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // MOVZ_I_D32_MM = 2174
13822 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I_D64 = 2175
13823 CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVZ_I_I = 2176
13824 CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVZ_I_I64 = 2177
13825 CEFBS_InMicroMips_NotMips32r6, // MOVZ_I_MM = 2178
13826 CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I_S = 2179
13827 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVZ_I_S_MM = 2180
13828 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MSUB = 2181
13829 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MSUBF_D = 2182
13830 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MSUBF_D_MMR6 = 2183
13831 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MSUBF_S = 2184
13832 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MSUBF_S_MMR6 = 2185
13833 CEFBS_HasStdEnc_HasMSA, // MSUBR_Q_H = 2186
13834 CEFBS_HasStdEnc_HasMSA, // MSUBR_Q_W = 2187
13835 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MSUBU = 2188
13836 CEFBS_HasDSP, // MSUBU_DSP = 2189
13837 CEFBS_InMicroMips_HasDSP, // MSUBU_DSP_MM = 2190
13838 CEFBS_InMicroMips_NotMips32r6, // MSUBU_MM = 2191
13839 CEFBS_HasStdEnc_HasMSA, // MSUBV_B = 2192
13840 CEFBS_HasStdEnc_HasMSA, // MSUBV_D = 2193
13841 CEFBS_HasStdEnc_HasMSA, // MSUBV_H = 2194
13842 CEFBS_HasStdEnc_HasMSA, // MSUBV_W = 2195
13843 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MSUB_D32 = 2196
13844 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, // MSUB_D32_MM = 2197
13845 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MSUB_D64 = 2198
13846 CEFBS_HasDSP, // MSUB_DSP = 2199
13847 CEFBS_InMicroMips_HasDSP, // MSUB_DSP_MM = 2200
13848 CEFBS_InMicroMips_NotMips32r6, // MSUB_MM = 2201
13849 CEFBS_HasStdEnc_HasMSA, // MSUB_Q_H = 2202
13850 CEFBS_HasStdEnc_HasMSA, // MSUB_Q_W = 2203
13851 CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MSUB_S = 2204
13852 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, // MSUB_S_MM = 2205
13853 CEFBS_HasStdEnc_NotInMicroMips, // MTC0 = 2206
13854 CEFBS_InMicroMips_HasMips32r6, // MTC0_MMR6 = 2207
13855 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // MTC1 = 2208
13856 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // MTC1_D64 = 2209
13857 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // MTC1_D64_MM = 2210
13858 CEFBS_InMicroMips_IsNotSoftFloat, // MTC1_MM = 2211
13859 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MTC1_MMR6 = 2212
13860 CEFBS_HasStdEnc_NotInMicroMips, // MTC2 = 2213
13861 CEFBS_InMicroMips_HasMips32r6, // MTC2_MMR6 = 2214
13862 CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // MTGC0 = 2215
13863 CEFBS_InMicroMips_HasMips32r5_HasVirt, // MTGC0_MM = 2216
13864 CEFBS_InMicroMips_HasMips32r6, // MTHC0_MMR6 = 2217
13865 CEFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, // MTHC1_D32 = 2218
13866 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // MTHC1_D32_MM = 2219
13867 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, // MTHC1_D64 = 2220
13868 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // MTHC1_D64_MM = 2221
13869 CEFBS_InMicroMips_HasMips32r6, // MTHC2_MMR6 = 2222
13870 CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // MTHGC0 = 2223
13871 CEFBS_InMicroMips_HasMips32r5_HasVirt, // MTHGC0_MM = 2224
13872 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MTHI = 2225
13873 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // MTHI64 = 2226
13874 CEFBS_HasDSP, // MTHI_DSP = 2227
13875 CEFBS_InMicroMips_HasDSP, // MTHI_DSP_MM = 2228
13876 CEFBS_InMicroMips_NotMips32r6, // MTHI_MM = 2229
13877 CEFBS_HasDSP, // MTHLIP = 2230
13878 CEFBS_InMicroMips_HasDSP, // MTHLIP_MM = 2231
13879 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MTLO = 2232
13880 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // MTLO64 = 2233
13881 CEFBS_HasDSP, // MTLO_DSP = 2234
13882 CEFBS_InMicroMips_HasDSP, // MTLO_DSP_MM = 2235
13883 CEFBS_InMicroMips_NotMips32r6, // MTLO_MM = 2236
13884 CEFBS_HasCnMips, // MTM0 = 2237
13885 CEFBS_HasCnMips, // MTM1 = 2238
13886 CEFBS_HasCnMips, // MTM2 = 2239
13887 CEFBS_HasCnMips, // MTP0 = 2240
13888 CEFBS_HasCnMips, // MTP1 = 2241
13889 CEFBS_HasCnMips, // MTP2 = 2242
13890 CEFBS_HasStdEnc_HasMT_NotInMicroMips, // MTTR = 2243
13891 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MUH = 2244
13892 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MUHU = 2245
13893 CEFBS_InMicroMips_HasMips32r6, // MUHU_MMR6 = 2246
13894 CEFBS_InMicroMips_HasMips32r6, // MUH_MMR6 = 2247
13895 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MUL = 2248
13896 CEFBS_HasDSP, // MULEQ_S_W_PHL = 2249
13897 CEFBS_InMicroMips_HasDSP, // MULEQ_S_W_PHL_MM = 2250
13898 CEFBS_HasDSP, // MULEQ_S_W_PHR = 2251
13899 CEFBS_InMicroMips_HasDSP, // MULEQ_S_W_PHR_MM = 2252
13900 CEFBS_HasDSP, // MULEU_S_PH_QBL = 2253
13901 CEFBS_InMicroMips_HasDSP, // MULEU_S_PH_QBL_MM = 2254
13902 CEFBS_HasDSP, // MULEU_S_PH_QBR = 2255
13903 CEFBS_InMicroMips_HasDSP, // MULEU_S_PH_QBR_MM = 2256
13904 CEFBS_HasDSP, // MULQ_RS_PH = 2257
13905 CEFBS_InMicroMips_HasDSP, // MULQ_RS_PH_MM = 2258
13906 CEFBS_HasDSPR2, // MULQ_RS_W = 2259
13907 CEFBS_InMicroMips_HasDSPR2, // MULQ_RS_W_MMR2 = 2260
13908 CEFBS_HasDSPR2, // MULQ_S_PH = 2261
13909 CEFBS_InMicroMips_HasDSPR2, // MULQ_S_PH_MMR2 = 2262
13910 CEFBS_HasDSPR2, // MULQ_S_W = 2263
13911 CEFBS_InMicroMips_HasDSPR2, // MULQ_S_W_MMR2 = 2264
13912 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, // MULR_PS64 = 2265
13913 CEFBS_HasStdEnc_HasMSA, // MULR_Q_H = 2266
13914 CEFBS_HasStdEnc_HasMSA, // MULR_Q_W = 2267
13915 CEFBS_HasDSP, // MULSAQ_S_W_PH = 2268
13916 CEFBS_InMicroMips_HasDSP, // MULSAQ_S_W_PH_MM = 2269
13917 CEFBS_HasDSPR2, // MULSA_W_PH = 2270
13918 CEFBS_InMicroMips_HasDSPR2, // MULSA_W_PH_MMR2 = 2271
13919 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MULT = 2272
13920 CEFBS_HasDSP, // MULTU_DSP = 2273
13921 CEFBS_InMicroMips_HasDSP, // MULTU_DSP_MM = 2274
13922 CEFBS_HasDSP, // MULT_DSP = 2275
13923 CEFBS_InMicroMips_HasDSP, // MULT_DSP_MM = 2276
13924 CEFBS_InMicroMips_NotMips32r6, // MULT_MM = 2277
13925 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MULTu = 2278
13926 CEFBS_InMicroMips_NotMips32r6, // MULTu_MM = 2279
13927 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MULU = 2280
13928 CEFBS_InMicroMips_HasMips32r6, // MULU_MMR6 = 2281
13929 CEFBS_HasStdEnc_HasMSA, // MULV_B = 2282
13930 CEFBS_HasStdEnc_HasMSA, // MULV_D = 2283
13931 CEFBS_HasStdEnc_HasMSA, // MULV_H = 2284
13932 CEFBS_HasStdEnc_HasMSA, // MULV_W = 2285
13933 CEFBS_InMicroMips_NotMips32r6, // MUL_MM = 2286
13934 CEFBS_InMicroMips_HasMips32r6, // MUL_MMR6 = 2287
13935 CEFBS_HasDSPR2, // MUL_PH = 2288
13936 CEFBS_InMicroMips_HasDSPR2, // MUL_PH_MMR2 = 2289
13937 CEFBS_HasStdEnc_HasMSA, // MUL_Q_H = 2290
13938 CEFBS_HasStdEnc_HasMSA, // MUL_Q_W = 2291
13939 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MUL_R6 = 2292
13940 CEFBS_HasDSPR2, // MUL_S_PH = 2293
13941 CEFBS_InMicroMips_HasDSPR2, // MUL_S_PH_MMR2 = 2294
13942 CEFBS_InMips16Mode, // Mfhi16 = 2295
13943 CEFBS_InMips16Mode, // Mflo16 = 2296
13944 CEFBS_InMips16Mode, // Move32R16 = 2297
13945 CEFBS_InMips16Mode, // MoveR3216 = 2298
13946 CEFBS_HasStdEnc_HasMips32r6, // NAL = 2299
13947 CEFBS_HasStdEnc_HasMSA, // NLOC_B = 2300
13948 CEFBS_HasStdEnc_HasMSA, // NLOC_D = 2301
13949 CEFBS_HasStdEnc_HasMSA, // NLOC_H = 2302
13950 CEFBS_HasStdEnc_HasMSA, // NLOC_W = 2303
13951 CEFBS_HasStdEnc_HasMSA, // NLZC_B = 2304
13952 CEFBS_HasStdEnc_HasMSA, // NLZC_D = 2305
13953 CEFBS_HasStdEnc_HasMSA, // NLZC_H = 2306
13954 CEFBS_HasStdEnc_HasMSA, // NLZC_W = 2307
13955 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMADD_D32 = 2308
13956 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, // NMADD_D32_MM = 2309
13957 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMADD_D64 = 2310
13958 CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMADD_S = 2311
13959 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, // NMADD_S_MM = 2312
13960 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMSUB_D32 = 2313
13961 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, // NMSUB_D32_MM = 2314
13962 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMSUB_D64 = 2315
13963 CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMSUB_S = 2316
13964 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, // NMSUB_S_MM = 2317
13965 CEFBS_HasStdEnc_NotInMicroMips, // NOR = 2318
13966 CEFBS_NotInMips16Mode_IsGP64bit, // NOR64 = 2319
13967 CEFBS_HasStdEnc_HasMSA, // NORI_B = 2320
13968 CEFBS_InMicroMips_NotMips32r6, // NOR_MM = 2321
13969 CEFBS_InMicroMips_HasMips32r6, // NOR_MMR6 = 2322
13970 CEFBS_HasStdEnc_HasMSA, // NOR_V = 2323
13971 CEFBS_InMicroMips_NotMips32r6, // NOT16_MM = 2324
13972 CEFBS_InMicroMips_HasMips32r6, // NOT16_MMR6 = 2325
13973 CEFBS_InMips16Mode, // NegRxRy16 = 2326
13974 CEFBS_InMips16Mode, // NotRxRy16 = 2327
13975 CEFBS_HasStdEnc_NotInMicroMips, // OR = 2328
13976 CEFBS_InMicroMips_NotMips32r6, // OR16_MM = 2329
13977 CEFBS_InMicroMips_HasMips32r6, // OR16_MMR6 = 2330
13978 CEFBS_NotInMips16Mode_IsGP64bit, // OR64 = 2331
13979 CEFBS_HasStdEnc_HasMSA, // ORI_B = 2332
13980 CEFBS_InMicroMips_HasMips32r6, // ORI_MMR6 = 2333
13981 CEFBS_InMicroMips_NotMips32r6, // OR_MM = 2334
13982 CEFBS_InMicroMips_HasMips32r6, // OR_MMR6 = 2335
13983 CEFBS_HasStdEnc_HasMSA, // OR_V = 2336
13984 CEFBS_HasStdEnc_NotInMicroMips, // ORi = 2337
13985 CEFBS_NotInMips16Mode_IsGP64bit, // ORi64 = 2338
13986 CEFBS_InMicroMips_NotMips32r6, // ORi_MM = 2339
13987 CEFBS_InMips16Mode, // OrRxRxRy16 = 2340
13988 CEFBS_HasDSP, // PACKRL_PH = 2341
13989 CEFBS_InMicroMips_HasDSP, // PACKRL_PH_MM = 2342
13990 CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // PAUSE = 2343
13991 CEFBS_InMicroMips, // PAUSE_MM = 2344
13992 CEFBS_InMicroMips_HasMips32r6, // PAUSE_MMR6 = 2345
13993 CEFBS_HasStdEnc_HasMSA, // PCKEV_B = 2346
13994 CEFBS_HasStdEnc_HasMSA, // PCKEV_D = 2347
13995 CEFBS_HasStdEnc_HasMSA, // PCKEV_H = 2348
13996 CEFBS_HasStdEnc_HasMSA, // PCKEV_W = 2349
13997 CEFBS_HasStdEnc_HasMSA, // PCKOD_B = 2350
13998 CEFBS_HasStdEnc_HasMSA, // PCKOD_D = 2351
13999 CEFBS_HasStdEnc_HasMSA, // PCKOD_H = 2352
14000 CEFBS_HasStdEnc_HasMSA, // PCKOD_W = 2353
14001 CEFBS_HasStdEnc_HasMSA, // PCNT_B = 2354
14002 CEFBS_HasStdEnc_HasMSA, // PCNT_D = 2355
14003 CEFBS_HasStdEnc_HasMSA, // PCNT_H = 2356
14004 CEFBS_HasStdEnc_HasMSA, // PCNT_W = 2357
14005 CEFBS_HasDSP, // PICK_PH = 2358
14006 CEFBS_InMicroMips_HasDSP, // PICK_PH_MM = 2359
14007 CEFBS_HasDSP, // PICK_QB = 2360
14008 CEFBS_InMicroMips_HasDSP, // PICK_QB_MM = 2361
14009 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // PLL_PS64 = 2362
14010 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // PLU_PS64 = 2363
14011 CEFBS_HasCnMips, // POP = 2364
14012 CEFBS_HasDSP, // PRECEQU_PH_QBL = 2365
14013 CEFBS_HasDSP, // PRECEQU_PH_QBLA = 2366
14014 CEFBS_InMicroMips_HasDSP, // PRECEQU_PH_QBLA_MM = 2367
14015 CEFBS_InMicroMips_HasDSP, // PRECEQU_PH_QBL_MM = 2368
14016 CEFBS_HasDSP, // PRECEQU_PH_QBR = 2369
14017 CEFBS_HasDSP, // PRECEQU_PH_QBRA = 2370
14018 CEFBS_InMicroMips_HasDSP, // PRECEQU_PH_QBRA_MM = 2371
14019 CEFBS_InMicroMips_HasDSP, // PRECEQU_PH_QBR_MM = 2372
14020 CEFBS_HasDSP, // PRECEQ_W_PHL = 2373
14021 CEFBS_InMicroMips_HasDSP, // PRECEQ_W_PHL_MM = 2374
14022 CEFBS_HasDSP, // PRECEQ_W_PHR = 2375
14023 CEFBS_InMicroMips_HasDSP, // PRECEQ_W_PHR_MM = 2376
14024 CEFBS_HasDSP, // PRECEU_PH_QBL = 2377
14025 CEFBS_HasDSP, // PRECEU_PH_QBLA = 2378
14026 CEFBS_InMicroMips_HasDSP, // PRECEU_PH_QBLA_MM = 2379
14027 CEFBS_InMicroMips_HasDSP, // PRECEU_PH_QBL_MM = 2380
14028 CEFBS_HasDSP, // PRECEU_PH_QBR = 2381
14029 CEFBS_HasDSP, // PRECEU_PH_QBRA = 2382
14030 CEFBS_InMicroMips_HasDSP, // PRECEU_PH_QBRA_MM = 2383
14031 CEFBS_InMicroMips_HasDSP, // PRECEU_PH_QBR_MM = 2384
14032 CEFBS_HasDSP, // PRECRQU_S_QB_PH = 2385
14033 CEFBS_InMicroMips_HasDSP, // PRECRQU_S_QB_PH_MM = 2386
14034 CEFBS_HasDSP, // PRECRQ_PH_W = 2387
14035 CEFBS_InMicroMips_HasDSP, // PRECRQ_PH_W_MM = 2388
14036 CEFBS_HasDSP, // PRECRQ_QB_PH = 2389
14037 CEFBS_InMicroMips_HasDSP, // PRECRQ_QB_PH_MM = 2390
14038 CEFBS_HasDSP, // PRECRQ_RS_PH_W = 2391
14039 CEFBS_InMicroMips_HasDSP, // PRECRQ_RS_PH_W_MM = 2392
14040 CEFBS_HasDSPR2, // PRECR_QB_PH = 2393
14041 CEFBS_InMicroMips_HasDSPR2, // PRECR_QB_PH_MMR2 = 2394
14042 CEFBS_HasDSPR2, // PRECR_SRA_PH_W = 2395
14043 CEFBS_InMicroMips_HasDSPR2, // PRECR_SRA_PH_W_MMR2 = 2396
14044 CEFBS_HasDSPR2, // PRECR_SRA_R_PH_W = 2397
14045 CEFBS_InMicroMips_HasDSPR2, // PRECR_SRA_R_PH_W_MMR2 = 2398
14046 CEFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips, // PREF = 2399
14047 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // PREFE = 2400
14048 CEFBS_InMicroMips_HasEVA, // PREFE_MM = 2401
14049 CEFBS_InMicroMips_NotMips32r6, // PREFX_MM = 2402
14050 CEFBS_InMicroMips_NotMips32r6, // PREF_MM = 2403
14051 CEFBS_InMicroMips_HasMips32r6, // PREF_MMR6 = 2404
14052 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // PREF_R6 = 2405
14053 CEFBS_HasDSPR2, // PREPEND = 2406
14054 CEFBS_InMicroMips_HasDSPR2, // PREPEND_MMR2 = 2407
14055 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // PUL_PS64 = 2408
14056 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // PUU_PS64 = 2409
14057 CEFBS_HasDSP, // RADDU_W_QB = 2410
14058 CEFBS_InMicroMips_HasDSP, // RADDU_W_QB_MM = 2411
14059 CEFBS_HasDSP, // RDDSP = 2412
14060 CEFBS_InMicroMips_HasDSP, // RDDSP_MM = 2413
14061 CEFBS_HasStdEnc_NotInMicroMips, // RDHWR = 2414
14062 CEFBS_NotInMips16Mode_IsGP64bit, // RDHWR64 = 2415
14063 CEFBS_InMicroMips_NotMips32r6, // RDHWR_MM = 2416
14064 CEFBS_InMicroMips_HasMips32r6, // RDHWR_MMR6 = 2417
14065 CEFBS_InMicroMips_HasMips32r6, // RDPGPR_MMR6 = 2418
14066 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RECIP_D32 = 2419
14067 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // RECIP_D32_MM = 2420
14068 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RECIP_D64 = 2421
14069 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // RECIP_D64_MM = 2422
14070 CEFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RECIP_S = 2423
14071 CEFBS_InMicroMips_IsNotSoftFloat, // RECIP_S_MM = 2424
14072 CEFBS_HasDSP, // REPLV_PH = 2425
14073 CEFBS_InMicroMips_HasDSP, // REPLV_PH_MM = 2426
14074 CEFBS_HasDSP, // REPLV_QB = 2427
14075 CEFBS_InMicroMips_HasDSP, // REPLV_QB_MM = 2428
14076 CEFBS_HasDSP, // REPL_PH = 2429
14077 CEFBS_InMicroMips_HasDSP, // REPL_PH_MM = 2430
14078 CEFBS_HasDSP, // REPL_QB = 2431
14079 CEFBS_InMicroMips_HasDSP, // REPL_QB_MM = 2432
14080 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // RINT_D = 2433
14081 CEFBS_InMicroMips_HasMips32r6, // RINT_D_MMR6 = 2434
14082 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // RINT_S = 2435
14083 CEFBS_InMicroMips_HasMips32r6, // RINT_S_MMR6 = 2436
14084 CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // ROTR = 2437
14085 CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // ROTRV = 2438
14086 CEFBS_InMicroMips, // ROTRV_MM = 2439
14087 CEFBS_InMicroMips, // ROTR_MM = 2440
14088 CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, // ROUND_L_D64 = 2441
14089 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // ROUND_L_D_MMR6 = 2442
14090 CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // ROUND_L_S = 2443
14091 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // ROUND_L_S_MMR6 = 2444
14092 CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // ROUND_W_D32 = 2445
14093 CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // ROUND_W_D64 = 2446
14094 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // ROUND_W_D_MMR6 = 2447
14095 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // ROUND_W_MM = 2448
14096 CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // ROUND_W_S = 2449
14097 CEFBS_InMicroMips_IsNotSoftFloat, // ROUND_W_S_MM = 2450
14098 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // ROUND_W_S_MMR6 = 2451
14099 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RSQRT_D32 = 2452
14100 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // RSQRT_D32_MM = 2453
14101 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RSQRT_D64 = 2454
14102 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // RSQRT_D64_MM = 2455
14103 CEFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RSQRT_S = 2456
14104 CEFBS_InMicroMips_IsNotSoftFloat, // RSQRT_S_MM = 2457
14105 CEFBS_InMips16Mode, // Restore16 = 2458
14106 CEFBS_InMips16Mode, // RestoreX16 = 2459
14107 CEFBS_HasCnMipsP, // SAA = 2460
14108 CEFBS_HasCnMipsP, // SAAD = 2461
14109 CEFBS_HasStdEnc_HasMSA, // SAT_S_B = 2462
14110 CEFBS_HasStdEnc_HasMSA, // SAT_S_D = 2463
14111 CEFBS_HasStdEnc_HasMSA, // SAT_S_H = 2464
14112 CEFBS_HasStdEnc_HasMSA, // SAT_S_W = 2465
14113 CEFBS_HasStdEnc_HasMSA, // SAT_U_B = 2466
14114 CEFBS_HasStdEnc_HasMSA, // SAT_U_D = 2467
14115 CEFBS_HasStdEnc_HasMSA, // SAT_U_H = 2468
14116 CEFBS_HasStdEnc_HasMSA, // SAT_U_W = 2469
14117 CEFBS_HasStdEnc_NotInMicroMips, // SB = 2470
14118 CEFBS_InMicroMips_NotMips32r6, // SB16_MM = 2471
14119 CEFBS_InMicroMips_HasMips32r6, // SB16_MMR6 = 2472
14120 CEFBS_NotInMips16Mode_IsGP64bit, // SB64 = 2473
14121 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // SBE = 2474
14122 CEFBS_InMicroMips_HasEVA, // SBE_MM = 2475
14123 CEFBS_InMicroMips, // SB_MM = 2476
14124 CEFBS_InMicroMips_HasMips32r6, // SB_MMR6 = 2477
14125 CEFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // SC = 2478
14126 CEFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // SC64 = 2479
14127 CEFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips, // SC64_R6 = 2480
14128 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // SCD = 2481
14129 CEFBS_HasStdEnc_HasMips32r6, // SCD_R6 = 2482
14130 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // SCE = 2483
14131 CEFBS_InMicroMips_HasEVA, // SCE_MM = 2484
14132 CEFBS_InMicroMips_NotMips32r6, // SC_MM = 2485
14133 CEFBS_InMicroMips_HasMips32r6, // SC_MMR6 = 2486
14134 CEFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips, // SC_R6 = 2487
14135 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // SD = 2488
14136 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // SDBBP = 2489
14137 CEFBS_InMicroMips_NotMips32r6, // SDBBP16_MM = 2490
14138 CEFBS_InMicroMips_HasMips32r6, // SDBBP16_MMR6 = 2491
14139 CEFBS_InMicroMips, // SDBBP_MM = 2492
14140 CEFBS_InMicroMips_HasMips32r6, // SDBBP_MMR6 = 2493
14141 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // SDBBP_R6 = 2494
14142 CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // SDC1 = 2495
14143 CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // SDC164 = 2496
14144 CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, // SDC1_D64_MMR6 = 2497
14145 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // SDC1_MM_D32 = 2498
14146 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // SDC1_MM_D64 = 2499
14147 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // SDC2 = 2500
14148 CEFBS_InMicroMips_HasMips32r6, // SDC2_MMR6 = 2501
14149 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // SDC2_R6 = 2502
14150 CEFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips, // SDC3 = 2503
14151 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // SDIV = 2504
14152 CEFBS_InMicroMips_NotMips32r6, // SDIV_MM = 2505
14153 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // SDL = 2506
14154 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // SDR = 2507
14155 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // SDXC1 = 2508
14156 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, // SDXC164 = 2509
14157 CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // SEB = 2510
14158 CEFBS_HasStdEnc_IsGP64bit_HasMips32r2, // SEB64 = 2511
14159 CEFBS_InMicroMips, // SEB_MM = 2512
14160 CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // SEH = 2513
14161 CEFBS_HasStdEnc_IsGP64bit_HasMips32r2, // SEH64 = 2514
14162 CEFBS_InMicroMips, // SEH_MM = 2515
14163 CEFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips, // SELEQZ = 2516
14164 CEFBS_HasStdEnc_IsGP64bit_HasMips32r6, // SELEQZ64 = 2517
14165 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SELEQZ_D = 2518
14166 CEFBS_InMicroMips_HasMips32r6, // SELEQZ_D_MMR6 = 2519
14167 CEFBS_InMicroMips_HasMips32r6, // SELEQZ_MMR6 = 2520
14168 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SELEQZ_S = 2521
14169 CEFBS_InMicroMips_HasMips32r6, // SELEQZ_S_MMR6 = 2522
14170 CEFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips, // SELNEZ = 2523
14171 CEFBS_HasStdEnc_IsGP64bit_HasMips32r6, // SELNEZ64 = 2524
14172 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SELNEZ_D = 2525
14173 CEFBS_InMicroMips_HasMips32r6, // SELNEZ_D_MMR6 = 2526
14174 CEFBS_InMicroMips_HasMips32r6, // SELNEZ_MMR6 = 2527
14175 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SELNEZ_S = 2528
14176 CEFBS_InMicroMips_HasMips32r6, // SELNEZ_S_MMR6 = 2529
14177 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SEL_D = 2530
14178 CEFBS_InMicroMips_HasMips32r6, // SEL_D_MMR6 = 2531
14179 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SEL_S = 2532
14180 CEFBS_InMicroMips_HasMips32r6, // SEL_S_MMR6 = 2533
14181 CEFBS_HasCnMips, // SEQ = 2534
14182 CEFBS_HasCnMips, // SEQi = 2535
14183 CEFBS_HasStdEnc_NotInMicroMips, // SH = 2536
14184 CEFBS_InMicroMips_NotMips32r6, // SH16_MM = 2537
14185 CEFBS_InMicroMips_HasMips32r6, // SH16_MMR6 = 2538
14186 CEFBS_NotInMips16Mode_IsGP64bit, // SH64 = 2539
14187 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // SHE = 2540
14188 CEFBS_InMicroMips_HasEVA, // SHE_MM = 2541
14189 CEFBS_HasStdEnc_HasMSA, // SHF_B = 2542
14190 CEFBS_HasStdEnc_HasMSA, // SHF_H = 2543
14191 CEFBS_HasStdEnc_HasMSA, // SHF_W = 2544
14192 CEFBS_HasDSP, // SHILO = 2545
14193 CEFBS_HasDSP, // SHILOV = 2546
14194 CEFBS_InMicroMips_HasDSP, // SHILOV_MM = 2547
14195 CEFBS_InMicroMips_HasDSP, // SHILO_MM = 2548
14196 CEFBS_HasDSP, // SHLLV_PH = 2549
14197 CEFBS_InMicroMips_HasDSP, // SHLLV_PH_MM = 2550
14198 CEFBS_HasDSP, // SHLLV_QB = 2551
14199 CEFBS_InMicroMips_HasDSP, // SHLLV_QB_MM = 2552
14200 CEFBS_HasDSP, // SHLLV_S_PH = 2553
14201 CEFBS_InMicroMips_HasDSP, // SHLLV_S_PH_MM = 2554
14202 CEFBS_HasDSP, // SHLLV_S_W = 2555
14203 CEFBS_InMicroMips_HasDSP, // SHLLV_S_W_MM = 2556
14204 CEFBS_HasDSP, // SHLL_PH = 2557
14205 CEFBS_InMicroMips_HasDSP, // SHLL_PH_MM = 2558
14206 CEFBS_HasDSP, // SHLL_QB = 2559
14207 CEFBS_InMicroMips_HasDSP, // SHLL_QB_MM = 2560
14208 CEFBS_HasDSP, // SHLL_S_PH = 2561
14209 CEFBS_InMicroMips_HasDSP, // SHLL_S_PH_MM = 2562
14210 CEFBS_HasDSP, // SHLL_S_W = 2563
14211 CEFBS_InMicroMips_HasDSP, // SHLL_S_W_MM = 2564
14212 CEFBS_HasDSP, // SHRAV_PH = 2565
14213 CEFBS_InMicroMips_HasDSP, // SHRAV_PH_MM = 2566
14214 CEFBS_HasDSPR2, // SHRAV_QB = 2567
14215 CEFBS_InMicroMips_HasDSPR2, // SHRAV_QB_MMR2 = 2568
14216 CEFBS_HasDSP, // SHRAV_R_PH = 2569
14217 CEFBS_InMicroMips_HasDSP, // SHRAV_R_PH_MM = 2570
14218 CEFBS_HasDSPR2, // SHRAV_R_QB = 2571
14219 CEFBS_InMicroMips_HasDSPR2, // SHRAV_R_QB_MMR2 = 2572
14220 CEFBS_HasDSP, // SHRAV_R_W = 2573
14221 CEFBS_InMicroMips_HasDSP, // SHRAV_R_W_MM = 2574
14222 CEFBS_HasDSP, // SHRA_PH = 2575
14223 CEFBS_InMicroMips_HasDSP, // SHRA_PH_MM = 2576
14224 CEFBS_HasDSPR2, // SHRA_QB = 2577
14225 CEFBS_InMicroMips_HasDSPR2, // SHRA_QB_MMR2 = 2578
14226 CEFBS_HasDSP, // SHRA_R_PH = 2579
14227 CEFBS_InMicroMips_HasDSP, // SHRA_R_PH_MM = 2580
14228 CEFBS_HasDSPR2, // SHRA_R_QB = 2581
14229 CEFBS_InMicroMips_HasDSPR2, // SHRA_R_QB_MMR2 = 2582
14230 CEFBS_HasDSP, // SHRA_R_W = 2583
14231 CEFBS_InMicroMips_HasDSP, // SHRA_R_W_MM = 2584
14232 CEFBS_HasDSPR2, // SHRLV_PH = 2585
14233 CEFBS_InMicroMips_HasDSPR2, // SHRLV_PH_MMR2 = 2586
14234 CEFBS_HasDSP, // SHRLV_QB = 2587
14235 CEFBS_InMicroMips_HasDSP, // SHRLV_QB_MM = 2588
14236 CEFBS_HasDSPR2, // SHRL_PH = 2589
14237 CEFBS_InMicroMips_HasDSPR2, // SHRL_PH_MMR2 = 2590
14238 CEFBS_HasDSP, // SHRL_QB = 2591
14239 CEFBS_InMicroMips_HasDSP, // SHRL_QB_MM = 2592
14240 CEFBS_InMicroMips, // SH_MM = 2593
14241 CEFBS_InMicroMips_HasMips32r6, // SH_MMR6 = 2594
14242 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // SIGRIE = 2595
14243 CEFBS_InMicroMips_HasMips32r6, // SIGRIE_MMR6 = 2596
14244 CEFBS_HasStdEnc_HasMSA, // SLDI_B = 2597
14245 CEFBS_HasStdEnc_HasMSA, // SLDI_D = 2598
14246 CEFBS_HasStdEnc_HasMSA, // SLDI_H = 2599
14247 CEFBS_HasStdEnc_HasMSA, // SLDI_W = 2600
14248 CEFBS_HasStdEnc_HasMSA, // SLD_B = 2601
14249 CEFBS_HasStdEnc_HasMSA, // SLD_D = 2602
14250 CEFBS_HasStdEnc_HasMSA, // SLD_H = 2603
14251 CEFBS_HasStdEnc_HasMSA, // SLD_W = 2604
14252 CEFBS_HasStdEnc_NotInMicroMips, // SLL = 2605
14253 CEFBS_InMicroMips_NotMips32r6, // SLL16_MM = 2606
14254 CEFBS_InMicroMips_HasMips32r6, // SLL16_MMR6 = 2607
14255 CEFBS_NotInMips16Mode_IsGP64bit, // SLL64_32 = 2608
14256 CEFBS_NotInMips16Mode_IsGP64bit, // SLL64_64 = 2609
14257 CEFBS_HasStdEnc_HasMSA, // SLLI_B = 2610
14258 CEFBS_HasStdEnc_HasMSA, // SLLI_D = 2611
14259 CEFBS_HasStdEnc_HasMSA, // SLLI_H = 2612
14260 CEFBS_HasStdEnc_HasMSA, // SLLI_W = 2613
14261 CEFBS_HasStdEnc_NotInMicroMips, // SLLV = 2614
14262 CEFBS_InMicroMips, // SLLV_MM = 2615
14263 CEFBS_HasStdEnc_HasMSA, // SLL_B = 2616
14264 CEFBS_HasStdEnc_HasMSA, // SLL_D = 2617
14265 CEFBS_HasStdEnc_HasMSA, // SLL_H = 2618
14266 CEFBS_InMicroMips, // SLL_MM = 2619
14267 CEFBS_InMicroMips_HasMips32r6, // SLL_MMR6 = 2620
14268 CEFBS_HasStdEnc_HasMSA, // SLL_W = 2621
14269 CEFBS_HasStdEnc_NotInMicroMips, // SLT = 2622
14270 CEFBS_NotInMips16Mode_IsGP64bit, // SLT64 = 2623
14271 CEFBS_InMicroMips, // SLT_MM = 2624
14272 CEFBS_HasStdEnc_NotInMicroMips, // SLTi = 2625
14273 CEFBS_NotInMips16Mode_IsGP64bit, // SLTi64 = 2626
14274 CEFBS_InMicroMips, // SLTi_MM = 2627
14275 CEFBS_HasStdEnc_NotInMicroMips, // SLTiu = 2628
14276 CEFBS_NotInMips16Mode_IsGP64bit, // SLTiu64 = 2629
14277 CEFBS_InMicroMips, // SLTiu_MM = 2630
14278 CEFBS_HasStdEnc_NotInMicroMips, // SLTu = 2631
14279 CEFBS_NotInMips16Mode_IsGP64bit, // SLTu64 = 2632
14280 CEFBS_InMicroMips, // SLTu_MM = 2633
14281 CEFBS_HasCnMips, // SNE = 2634
14282 CEFBS_HasCnMips, // SNEi = 2635
14283 CEFBS_HasStdEnc_HasMSA, // SPLATI_B = 2636
14284 CEFBS_HasStdEnc_HasMSA, // SPLATI_D = 2637
14285 CEFBS_HasStdEnc_HasMSA, // SPLATI_H = 2638
14286 CEFBS_HasStdEnc_HasMSA, // SPLATI_W = 2639
14287 CEFBS_HasStdEnc_HasMSA, // SPLAT_B = 2640
14288 CEFBS_HasStdEnc_HasMSA, // SPLAT_D = 2641
14289 CEFBS_HasStdEnc_HasMSA, // SPLAT_H = 2642
14290 CEFBS_HasStdEnc_HasMSA, // SPLAT_W = 2643
14291 CEFBS_HasStdEnc_NotInMicroMips, // SRA = 2644
14292 CEFBS_HasStdEnc_HasMSA, // SRAI_B = 2645
14293 CEFBS_HasStdEnc_HasMSA, // SRAI_D = 2646
14294 CEFBS_HasStdEnc_HasMSA, // SRAI_H = 2647
14295 CEFBS_HasStdEnc_HasMSA, // SRAI_W = 2648
14296 CEFBS_HasStdEnc_HasMSA, // SRARI_B = 2649
14297 CEFBS_HasStdEnc_HasMSA, // SRARI_D = 2650
14298 CEFBS_HasStdEnc_HasMSA, // SRARI_H = 2651
14299 CEFBS_HasStdEnc_HasMSA, // SRARI_W = 2652
14300 CEFBS_HasStdEnc_HasMSA, // SRAR_B = 2653
14301 CEFBS_HasStdEnc_HasMSA, // SRAR_D = 2654
14302 CEFBS_HasStdEnc_HasMSA, // SRAR_H = 2655
14303 CEFBS_HasStdEnc_HasMSA, // SRAR_W = 2656
14304 CEFBS_HasStdEnc_NotInMicroMips, // SRAV = 2657
14305 CEFBS_InMicroMips, // SRAV_MM = 2658
14306 CEFBS_HasStdEnc_HasMSA, // SRA_B = 2659
14307 CEFBS_HasStdEnc_HasMSA, // SRA_D = 2660
14308 CEFBS_HasStdEnc_HasMSA, // SRA_H = 2661
14309 CEFBS_InMicroMips, // SRA_MM = 2662
14310 CEFBS_HasStdEnc_HasMSA, // SRA_W = 2663
14311 CEFBS_HasStdEnc_NotInMicroMips, // SRL = 2664
14312 CEFBS_InMicroMips_NotMips32r6, // SRL16_MM = 2665
14313 CEFBS_InMicroMips_HasMips32r6, // SRL16_MMR6 = 2666
14314 CEFBS_HasStdEnc_HasMSA, // SRLI_B = 2667
14315 CEFBS_HasStdEnc_HasMSA, // SRLI_D = 2668
14316 CEFBS_HasStdEnc_HasMSA, // SRLI_H = 2669
14317 CEFBS_HasStdEnc_HasMSA, // SRLI_W = 2670
14318 CEFBS_HasStdEnc_HasMSA, // SRLRI_B = 2671
14319 CEFBS_HasStdEnc_HasMSA, // SRLRI_D = 2672
14320 CEFBS_HasStdEnc_HasMSA, // SRLRI_H = 2673
14321 CEFBS_HasStdEnc_HasMSA, // SRLRI_W = 2674
14322 CEFBS_HasStdEnc_HasMSA, // SRLR_B = 2675
14323 CEFBS_HasStdEnc_HasMSA, // SRLR_D = 2676
14324 CEFBS_HasStdEnc_HasMSA, // SRLR_H = 2677
14325 CEFBS_HasStdEnc_HasMSA, // SRLR_W = 2678
14326 CEFBS_HasStdEnc_NotInMicroMips, // SRLV = 2679
14327 CEFBS_InMicroMips, // SRLV_MM = 2680
14328 CEFBS_HasStdEnc_HasMSA, // SRL_B = 2681
14329 CEFBS_HasStdEnc_HasMSA, // SRL_D = 2682
14330 CEFBS_HasStdEnc_HasMSA, // SRL_H = 2683
14331 CEFBS_InMicroMips, // SRL_MM = 2684
14332 CEFBS_HasStdEnc_HasMSA, // SRL_W = 2685
14333 CEFBS_HasStdEnc_NotInMicroMips, // SSNOP = 2686
14334 CEFBS_InMicroMips, // SSNOP_MM = 2687
14335 CEFBS_InMicroMips_HasMips32r6, // SSNOP_MMR6 = 2688
14336 CEFBS_HasStdEnc_HasMSA, // ST_B = 2689
14337 CEFBS_HasStdEnc_HasMSA, // ST_D = 2690
14338 CEFBS_HasStdEnc_HasMSA, // ST_H = 2691
14339 CEFBS_HasStdEnc_HasMSA, // ST_W = 2692
14340 CEFBS_HasStdEnc_NotInMicroMips, // SUB = 2693
14341 CEFBS_HasDSPR2, // SUBQH_PH = 2694
14342 CEFBS_InMicroMips_HasDSPR2, // SUBQH_PH_MMR2 = 2695
14343 CEFBS_HasDSPR2, // SUBQH_R_PH = 2696
14344 CEFBS_InMicroMips_HasDSPR2, // SUBQH_R_PH_MMR2 = 2697
14345 CEFBS_HasDSPR2, // SUBQH_R_W = 2698
14346 CEFBS_InMicroMips_HasDSPR2, // SUBQH_R_W_MMR2 = 2699
14347 CEFBS_HasDSPR2, // SUBQH_W = 2700
14348 CEFBS_InMicroMips_HasDSPR2, // SUBQH_W_MMR2 = 2701
14349 CEFBS_HasDSP, // SUBQ_PH = 2702
14350 CEFBS_InMicroMips_HasDSP, // SUBQ_PH_MM = 2703
14351 CEFBS_HasDSP, // SUBQ_S_PH = 2704
14352 CEFBS_InMicroMips_HasDSP, // SUBQ_S_PH_MM = 2705
14353 CEFBS_HasDSP, // SUBQ_S_W = 2706
14354 CEFBS_InMicroMips_HasDSP, // SUBQ_S_W_MM = 2707
14355 CEFBS_HasStdEnc_HasMSA, // SUBSUS_U_B = 2708
14356 CEFBS_HasStdEnc_HasMSA, // SUBSUS_U_D = 2709
14357 CEFBS_HasStdEnc_HasMSA, // SUBSUS_U_H = 2710
14358 CEFBS_HasStdEnc_HasMSA, // SUBSUS_U_W = 2711
14359 CEFBS_HasStdEnc_HasMSA, // SUBSUU_S_B = 2712
14360 CEFBS_HasStdEnc_HasMSA, // SUBSUU_S_D = 2713
14361 CEFBS_HasStdEnc_HasMSA, // SUBSUU_S_H = 2714
14362 CEFBS_HasStdEnc_HasMSA, // SUBSUU_S_W = 2715
14363 CEFBS_HasStdEnc_HasMSA, // SUBS_S_B = 2716
14364 CEFBS_HasStdEnc_HasMSA, // SUBS_S_D = 2717
14365 CEFBS_HasStdEnc_HasMSA, // SUBS_S_H = 2718
14366 CEFBS_HasStdEnc_HasMSA, // SUBS_S_W = 2719
14367 CEFBS_HasStdEnc_HasMSA, // SUBS_U_B = 2720
14368 CEFBS_HasStdEnc_HasMSA, // SUBS_U_D = 2721
14369 CEFBS_HasStdEnc_HasMSA, // SUBS_U_H = 2722
14370 CEFBS_HasStdEnc_HasMSA, // SUBS_U_W = 2723
14371 CEFBS_InMicroMips_NotMips32r6, // SUBU16_MM = 2724
14372 CEFBS_InMicroMips_HasMips32r6, // SUBU16_MMR6 = 2725
14373 CEFBS_HasDSPR2, // SUBUH_QB = 2726
14374 CEFBS_InMicroMips_HasDSPR2, // SUBUH_QB_MMR2 = 2727
14375 CEFBS_HasDSPR2, // SUBUH_R_QB = 2728
14376 CEFBS_InMicroMips_HasDSPR2, // SUBUH_R_QB_MMR2 = 2729
14377 CEFBS_InMicroMips_HasMips32r6, // SUBU_MMR6 = 2730
14378 CEFBS_HasDSPR2, // SUBU_PH = 2731
14379 CEFBS_InMicroMips_HasDSPR2, // SUBU_PH_MMR2 = 2732
14380 CEFBS_HasDSP, // SUBU_QB = 2733
14381 CEFBS_InMicroMips_HasDSP, // SUBU_QB_MM = 2734
14382 CEFBS_HasDSPR2, // SUBU_S_PH = 2735
14383 CEFBS_InMicroMips_HasDSPR2, // SUBU_S_PH_MMR2 = 2736
14384 CEFBS_HasDSP, // SUBU_S_QB = 2737
14385 CEFBS_InMicroMips_HasDSP, // SUBU_S_QB_MM = 2738
14386 CEFBS_HasStdEnc_HasMSA, // SUBVI_B = 2739
14387 CEFBS_HasStdEnc_HasMSA, // SUBVI_D = 2740
14388 CEFBS_HasStdEnc_HasMSA, // SUBVI_H = 2741
14389 CEFBS_HasStdEnc_HasMSA, // SUBVI_W = 2742
14390 CEFBS_HasStdEnc_HasMSA, // SUBV_B = 2743
14391 CEFBS_HasStdEnc_HasMSA, // SUBV_D = 2744
14392 CEFBS_HasStdEnc_HasMSA, // SUBV_H = 2745
14393 CEFBS_HasStdEnc_HasMSA, // SUBV_W = 2746
14394 CEFBS_InMicroMips_NotMips32r6, // SUB_MM = 2747
14395 CEFBS_InMicroMips_HasMips32r6, // SUB_MMR6 = 2748
14396 CEFBS_HasStdEnc_NotInMicroMips, // SUBu = 2749
14397 CEFBS_InMicroMips_NotMips32r6, // SUBu_MM = 2750
14398 CEFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // SUXC1 = 2751
14399 CEFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // SUXC164 = 2752
14400 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // SUXC1_MM = 2753
14401 CEFBS_HasStdEnc_NotInMicroMips, // SW = 2754
14402 CEFBS_InMicroMips_NotMips32r6, // SW16_MM = 2755
14403 CEFBS_InMicroMips_HasMips32r6, // SW16_MMR6 = 2756
14404 CEFBS_NotInMips16Mode_IsGP64bit, // SW64 = 2757
14405 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // SWC1 = 2758
14406 CEFBS_InMicroMips_IsNotSoftFloat, // SWC1_MM = 2759
14407 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // SWC2 = 2760
14408 CEFBS_InMicroMips_HasMips32r6, // SWC2_MMR6 = 2761
14409 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // SWC2_R6 = 2762
14410 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips, // SWC3 = 2763
14411 CEFBS_NotInMips16Mode_HasDSP, // SWDSP = 2764
14412 CEFBS_InMicroMips_HasDSP, // SWDSP_MM = 2765
14413 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // SWE = 2766
14414 CEFBS_InMicroMips_HasEVA, // SWE_MM = 2767
14415 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // SWL = 2768
14416 CEFBS_NotInMips16Mode_IsGP64bit, // SWL64 = 2769
14417 CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, // SWLE = 2770
14418 CEFBS_InMicroMips_NotMips32r6_HasEVA, // SWLE_MM = 2771
14419 CEFBS_InMicroMips_NotMips32r6, // SWL_MM = 2772
14420 CEFBS_InMicroMips_NotMips32r6, // SWM16_MM = 2773
14421 CEFBS_InMicroMips_HasMips32r6, // SWM16_MMR6 = 2774
14422 CEFBS_InMicroMips, // SWM32_MM = 2775
14423 CEFBS_InMicroMips, // SWP_MM = 2776
14424 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // SWR = 2777
14425 CEFBS_NotInMips16Mode_IsGP64bit, // SWR64 = 2778
14426 CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, // SWRE = 2779
14427 CEFBS_InMicroMips_NotMips32r6_HasEVA, // SWRE_MM = 2780
14428 CEFBS_InMicroMips_NotMips32r6, // SWR_MM = 2781
14429 CEFBS_InMicroMips_NotMips32r6, // SWSP_MM = 2782
14430 CEFBS_InMicroMips_HasMips32r6, // SWSP_MMR6 = 2783
14431 CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, // SWXC1 = 2784
14432 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // SWXC1_MM = 2785
14433 CEFBS_InMicroMips, // SW_MM = 2786
14434 CEFBS_InMicroMips_HasMips32r6, // SW_MMR6 = 2787
14435 CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // SYNC = 2788
14436 CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // SYNCI = 2789
14437 CEFBS_InMicroMips_NotMips32r6, // SYNCI_MM = 2790
14438 CEFBS_InMicroMips_HasMips32r6, // SYNCI_MMR6 = 2791
14439 CEFBS_InMicroMips, // SYNC_MM = 2792
14440 CEFBS_InMicroMips_HasMips32r6, // SYNC_MMR6 = 2793
14441 CEFBS_HasStdEnc_NotInMicroMips, // SYSCALL = 2794
14442 CEFBS_InMicroMips, // SYSCALL_MM = 2795
14443 CEFBS_InMips16Mode, // Save16 = 2796
14444 CEFBS_InMips16Mode, // SaveX16 = 2797
14445 CEFBS_InMips16Mode, // SbRxRyOffMemX16 = 2798
14446 CEFBS_InMips16Mode, // SebRx16 = 2799
14447 CEFBS_InMips16Mode, // SehRx16 = 2800
14448 CEFBS_InMips16Mode, // ShRxRyOffMemX16 = 2801
14449 CEFBS_InMips16Mode, // SllX16 = 2802
14450 CEFBS_InMips16Mode, // SllvRxRy16 = 2803
14451 CEFBS_InMips16Mode, // SltRxRy16 = 2804
14452 CEFBS_InMips16Mode, // SltiRxImm16 = 2805
14453 CEFBS_InMips16Mode, // SltiRxImmX16 = 2806
14454 CEFBS_InMips16Mode, // SltiuRxImm16 = 2807
14455 CEFBS_InMips16Mode, // SltiuRxImmX16 = 2808
14456 CEFBS_InMips16Mode, // SltuRxRy16 = 2809
14457 CEFBS_InMips16Mode, // SraX16 = 2810
14458 CEFBS_InMips16Mode, // SravRxRy16 = 2811
14459 CEFBS_InMips16Mode, // SrlX16 = 2812
14460 CEFBS_InMips16Mode, // SrlvRxRy16 = 2813
14461 CEFBS_InMips16Mode, // SubuRxRyRz16 = 2814
14462 CEFBS_InMips16Mode, // SwRxRyOffMemX16 = 2815
14463 CEFBS_InMips16Mode, // SwRxSpImmX16 = 2816
14464 CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TEQ = 2817
14465 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TEQI = 2818
14466 CEFBS_InMicroMips_NotMips32r6, // TEQI_MM = 2819
14467 CEFBS_InMicroMips, // TEQ_MM = 2820
14468 CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TGE = 2821
14469 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TGEI = 2822
14470 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TGEIU = 2823
14471 CEFBS_InMicroMips_NotMips32r6, // TGEIU_MM = 2824
14472 CEFBS_InMicroMips_NotMips32r6, // TGEI_MM = 2825
14473 CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TGEU = 2826
14474 CEFBS_InMicroMips, // TGEU_MM = 2827
14475 CEFBS_InMicroMips, // TGE_MM = 2828
14476 CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGINV = 2829
14477 CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGINVF = 2830
14478 CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGINVF_MM = 2831
14479 CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGINV_MM = 2832
14480 CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGP = 2833
14481 CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGP_MM = 2834
14482 CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGR = 2835
14483 CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGR_MM = 2836
14484 CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGWI = 2837
14485 CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGWI_MM = 2838
14486 CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGWR = 2839
14487 CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGWR_MM = 2840
14488 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // TLBINV = 2841
14489 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // TLBINVF = 2842
14490 CEFBS_InMicroMips_HasMips32r6, // TLBINVF_MMR6 = 2843
14491 CEFBS_InMicroMips_HasMips32r6, // TLBINV_MMR6 = 2844
14492 CEFBS_HasStdEnc_NotInMicroMips, // TLBP = 2845
14493 CEFBS_InMicroMips, // TLBP_MM = 2846
14494 CEFBS_HasStdEnc_NotInMicroMips, // TLBR = 2847
14495 CEFBS_InMicroMips, // TLBR_MM = 2848
14496 CEFBS_HasStdEnc_NotInMicroMips, // TLBWI = 2849
14497 CEFBS_InMicroMips, // TLBWI_MM = 2850
14498 CEFBS_HasStdEnc_NotInMicroMips, // TLBWR = 2851
14499 CEFBS_InMicroMips, // TLBWR_MM = 2852
14500 CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TLT = 2853
14501 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TLTI = 2854
14502 CEFBS_InMicroMips_NotMips32r6, // TLTIU_MM = 2855
14503 CEFBS_InMicroMips_NotMips32r6, // TLTI_MM = 2856
14504 CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TLTU = 2857
14505 CEFBS_InMicroMips, // TLTU_MM = 2858
14506 CEFBS_InMicroMips, // TLT_MM = 2859
14507 CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TNE = 2860
14508 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TNEI = 2861
14509 CEFBS_InMicroMips_NotMips32r6, // TNEI_MM = 2862
14510 CEFBS_InMicroMips, // TNE_MM = 2863
14511 CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, // TRUNC_L_D64 = 2864
14512 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // TRUNC_L_D_MMR6 = 2865
14513 CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // TRUNC_L_S = 2866
14514 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // TRUNC_L_S_MMR6 = 2867
14515 CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // TRUNC_W_D32 = 2868
14516 CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // TRUNC_W_D64 = 2869
14517 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // TRUNC_W_D_MMR6 = 2870
14518 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // TRUNC_W_MM = 2871
14519 CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // TRUNC_W_S = 2872
14520 CEFBS_InMicroMips_IsNotSoftFloat, // TRUNC_W_S_MM = 2873
14521 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // TRUNC_W_S_MMR6 = 2874
14522 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TTLTIU = 2875
14523 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // UDIV = 2876
14524 CEFBS_InMicroMips_NotMips32r6, // UDIV_MM = 2877
14525 CEFBS_HasCnMips, // V3MULU = 2878
14526 CEFBS_HasCnMips, // VMM0 = 2879
14527 CEFBS_HasCnMips, // VMULU = 2880
14528 CEFBS_HasStdEnc_HasMSA, // VSHF_B = 2881
14529 CEFBS_HasStdEnc_HasMSA, // VSHF_D = 2882
14530 CEFBS_HasStdEnc_HasMSA, // VSHF_H = 2883
14531 CEFBS_HasStdEnc_HasMSA, // VSHF_W = 2884
14532 CEFBS_HasStdEnc_HasMips3_32_NotInMicroMips, // WAIT = 2885
14533 CEFBS_InMicroMips, // WAIT_MM = 2886
14534 CEFBS_InMicroMips_HasMips32r6, // WAIT_MMR6 = 2887
14535 CEFBS_HasDSP_NotInMicroMips, // WRDSP = 2888
14536 CEFBS_InMicroMips_HasDSP, // WRDSP_MM = 2889
14537 CEFBS_InMicroMips_HasMips32r6, // WRPGPR_MMR6 = 2890
14538 CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // WSBH = 2891
14539 CEFBS_InMicroMips, // WSBH_MM = 2892
14540 CEFBS_InMicroMips_HasMips32r6, // WSBH_MMR6 = 2893
14541 CEFBS_HasStdEnc_NotInMicroMips, // XOR = 2894
14542 CEFBS_InMicroMips_NotMips32r6, // XOR16_MM = 2895
14543 CEFBS_InMicroMips_HasMips32r6, // XOR16_MMR6 = 2896
14544 CEFBS_NotInMips16Mode_IsGP64bit, // XOR64 = 2897
14545 CEFBS_HasStdEnc_HasMSA, // XORI_B = 2898
14546 CEFBS_InMicroMips_HasMips32r6, // XORI_MMR6 = 2899
14547 CEFBS_InMicroMips_NotMips32r6, // XOR_MM = 2900
14548 CEFBS_InMicroMips_HasMips32r6, // XOR_MMR6 = 2901
14549 CEFBS_HasStdEnc_HasMSA, // XOR_V = 2902
14550 CEFBS_HasStdEnc_NotInMicroMips, // XORi = 2903
14551 CEFBS_NotInMips16Mode_IsGP64bit, // XORi64 = 2904
14552 CEFBS_InMicroMips_NotMips32r6, // XORi_MM = 2905
14553 CEFBS_InMips16Mode, // XorRxRxRy16 = 2906
14554 CEFBS_HasStdEnc_HasMT_NotInMicroMips, // YIELD = 2907
14555 };
14556
14557 assert(Opcode < 2908);
14558 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
14559}
14560
14561} // end namespace llvm::Mips_MC
14562#endif // GET_COMPUTE_FEATURES
14563
14564#ifdef GET_AVAILABLE_OPCODE_CHECKER
14565#undef GET_AVAILABLE_OPCODE_CHECKER
14566namespace llvm::Mips_MC {
14567bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
14568 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
14569 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
14570 FeatureBitset MissingFeatures =
14571 (AvailableFeatures & RequiredFeatures) ^
14572 RequiredFeatures;
14573 return !MissingFeatures.any();
14574}
14575} // end namespace llvm::Mips_MC
14576#endif // GET_AVAILABLE_OPCODE_CHECKER
14577
14578#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
14579#undef ENABLE_INSTR_PREDICATE_VERIFIER
14580#include <sstream>
14581
14582namespace llvm::Mips_MC {
14583#ifndef NDEBUG
14584static const char *SubtargetFeatureNames[] = {
14585 "Feature_HasCRC",
14586 "Feature_HasCnMips",
14587 "Feature_HasCnMipsP",
14588 "Feature_HasDSP",
14589 "Feature_HasDSPR2",
14590 "Feature_HasDSPR3",
14591 "Feature_HasEVA",
14592 "Feature_HasGINV",
14593 "Feature_HasMSA",
14594 "Feature_HasMT",
14595 "Feature_HasMadd4",
14596 "Feature_HasMips2",
14597 "Feature_HasMips3",
14598 "Feature_HasMips3D",
14599 "Feature_HasMips3_32",
14600 "Feature_HasMips3_32r2",
14601 "Feature_HasMips4_32",
14602 "Feature_HasMips4_32r2",
14603 "Feature_HasMips5_32r2",
14604 "Feature_HasMips32",
14605 "Feature_HasMips32r2",
14606 "Feature_HasMips32r5",
14607 "Feature_HasMips32r6",
14608 "Feature_HasMips64",
14609 "Feature_HasMips64r2",
14610 "Feature_HasMips64r5",
14611 "Feature_HasMips64r6",
14612 "Feature_HasStdEnc",
14613 "Feature_HasVirt",
14614 "Feature_InMicroMips",
14615 "Feature_InMips16Mode",
14616 "Feature_IsFP64bit",
14617 "Feature_IsGP32bit",
14618 "Feature_IsGP64bit",
14619 "Feature_IsNotSingleFloat",
14620 "Feature_IsNotSoftFloat",
14621 "Feature_IsPTR32bit",
14622 "Feature_IsPTR64bit",
14623 "Feature_IsSingleFloat",
14624 "Feature_IsSym32",
14625 "Feature_IsSym64",
14626 "Feature_NoIndirectJumpGuards",
14627 "Feature_NotCnMips",
14628 "Feature_NotCnMipsP",
14629 "Feature_NotFP64bit",
14630 "Feature_NotInMicroMips",
14631 "Feature_NotInMips16Mode",
14632 "Feature_NotMips3",
14633 "Feature_NotMips4_32",
14634 "Feature_NotMips32r6",
14635 "Feature_NotMips64",
14636 "Feature_NotMips64r6",
14637 "Feature_UseIndirectJumpsHazard",
14638 nullptr
14639};
14640
14641#endif // NDEBUG
14642
14643void verifyInstructionPredicates(
14644 unsigned Opcode, const FeatureBitset &Features) {
14645#ifndef NDEBUG
14646 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
14647 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
14648 FeatureBitset MissingFeatures =
14649 (AvailableFeatures & RequiredFeatures) ^
14650 RequiredFeatures;
14651 if (MissingFeatures.any()) {
14652 std::ostringstream Msg;
14653 Msg << "Attempting to emit " << &MipsInstrNameData[MipsInstrNameIndices[Opcode]]
14654 << " instruction but the ";
14655 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
14656 if (MissingFeatures.test(i))
14657 Msg << SubtargetFeatureNames[i] << " ";
14658 Msg << "predicate(s) are not met";
14659 report_fatal_error(Msg.str().c_str());
14660 }
14661#endif // NDEBUG
14662}
14663} // end namespace llvm::Mips_MC
14664#endif // ENABLE_INSTR_PREDICATE_VERIFIER
14665
14666#ifdef GET_INSTRMAP_INFO
14667#undef GET_INSTRMAP_INFO
14668namespace llvm::Mips {
14669
14670enum Arch {
14671 Arch_dsp,
14672 Arch_mmdsp,
14673 Arch_mipsr6,
14674 Arch_micromipsr6,
14675 Arch_se,
14676 Arch_micromips
14677};
14678
14679// Dsp2MicroMips
14680LLVM_READONLY
14681int Dsp2MicroMips(uint16_t Opcode, enum Arch inArch) {
14682 using namespace Mips;
14683 static constexpr uint16_t Table[][3] = {
14684 { ABSQ_S_PH, ABSQ_S_PH, ABSQ_S_PH_MM },
14685 { ABSQ_S_QB, ABSQ_S_QB, ABSQ_S_QB_MMR2 },
14686 { ABSQ_S_W, ABSQ_S_W, ABSQ_S_W_MM },
14687 { ADDQH_PH, ADDQH_PH, ADDQH_PH_MMR2 },
14688 { ADDQH_R_PH, ADDQH_R_PH, ADDQH_R_PH_MMR2 },
14689 { ADDQH_R_W, ADDQH_R_W, ADDQH_R_W_MMR2 },
14690 { ADDQH_W, ADDQH_W, ADDQH_W_MMR2 },
14691 { ADDQ_PH, ADDQ_PH, ADDQ_PH_MM },
14692 { ADDQ_S_PH, ADDQ_S_PH, ADDQ_S_PH_MM },
14693 { ADDQ_S_W, ADDQ_S_W, ADDQ_S_W_MM },
14694 { ADDSC, ADDSC, ADDSC_MM },
14695 { ADDUH_QB, ADDUH_QB, ADDUH_QB_MMR2 },
14696 { ADDUH_R_QB, ADDUH_R_QB, ADDUH_R_QB_MMR2 },
14697 { ADDU_PH, ADDU_PH, ADDU_PH_MMR2 },
14698 { ADDU_QB, ADDU_QB, ADDU_QB_MM },
14699 { ADDU_S_PH, ADDU_S_PH, ADDU_S_PH_MMR2 },
14700 { ADDU_S_QB, ADDU_S_QB, ADDU_S_QB_MM },
14701 { ADDWC, ADDWC, ADDWC_MM },
14702 { APPEND, APPEND, APPEND_MMR2 },
14703 { BALIGN, BALIGN, BALIGN_MMR2 },
14704 { BITREV, BITREV, BITREV_MM },
14705 { BPOSGE32, BPOSGE32, BPOSGE32_MM },
14706 { CMPGDU_EQ_QB, CMPGDU_EQ_QB, CMPGDU_EQ_QB_MMR2 },
14707 { CMPGDU_LE_QB, CMPGDU_LE_QB, CMPGDU_LE_QB_MMR2 },
14708 { CMPGDU_LT_QB, CMPGDU_LT_QB, CMPGDU_LT_QB_MMR2 },
14709 { CMPGU_EQ_QB, CMPGU_EQ_QB, CMPGU_EQ_QB_MM },
14710 { CMPGU_LE_QB, CMPGU_LE_QB, CMPGU_LE_QB_MM },
14711 { CMPGU_LT_QB, CMPGU_LT_QB, CMPGU_LT_QB_MM },
14712 { CMPU_EQ_QB, CMPU_EQ_QB, CMPU_EQ_QB_MM },
14713 { CMPU_LE_QB, CMPU_LE_QB, CMPU_LE_QB_MM },
14714 { CMPU_LT_QB, CMPU_LT_QB, CMPU_LT_QB_MM },
14715 { CMP_EQ_PH, CMP_EQ_PH, CMP_EQ_PH_MM },
14716 { CMP_LE_PH, CMP_LE_PH, CMP_LE_PH_MM },
14717 { CMP_LT_PH, CMP_LT_PH, CMP_LT_PH_MM },
14718 { DPAQX_SA_W_PH, DPAQX_SA_W_PH, DPAQX_SA_W_PH_MMR2 },
14719 { DPAQX_S_W_PH, DPAQX_S_W_PH, DPAQX_S_W_PH_MMR2 },
14720 { DPAQ_SA_L_W, DPAQ_SA_L_W, DPAQ_SA_L_W_MM },
14721 { DPAQ_S_W_PH, DPAQ_S_W_PH, DPAQ_S_W_PH_MM },
14722 { DPAU_H_QBL, DPAU_H_QBL, DPAU_H_QBL_MM },
14723 { DPAU_H_QBR, DPAU_H_QBR, DPAU_H_QBR_MM },
14724 { DPAX_W_PH, DPAX_W_PH, DPAX_W_PH_MMR2 },
14725 { DPA_W_PH, DPA_W_PH, DPA_W_PH_MMR2 },
14726 { DPSQX_SA_W_PH, DPSQX_SA_W_PH, DPSQX_SA_W_PH_MMR2 },
14727 { DPSQX_S_W_PH, DPSQX_S_W_PH, DPSQX_S_W_PH_MMR2 },
14728 { DPSQ_SA_L_W, DPSQ_SA_L_W, DPSQ_SA_L_W_MM },
14729 { DPSQ_S_W_PH, DPSQ_S_W_PH, DPSQ_S_W_PH_MM },
14730 { DPSU_H_QBL, DPSU_H_QBL, DPSU_H_QBL_MM },
14731 { DPSU_H_QBR, DPSU_H_QBR, DPSU_H_QBR_MM },
14732 { DPSX_W_PH, DPSX_W_PH, DPSX_W_PH_MMR2 },
14733 { DPS_W_PH, DPS_W_PH, DPS_W_PH_MMR2 },
14734 { EXTP, EXTP, EXTP_MM },
14735 { EXTPDP, EXTPDP, EXTPDP_MM },
14736 { EXTPDPV, EXTPDPV, EXTPDPV_MM },
14737 { EXTPV, EXTPV, EXTPV_MM },
14738 { EXTRV_RS_W, EXTRV_RS_W, EXTRV_RS_W_MM },
14739 { EXTRV_R_W, EXTRV_R_W, EXTRV_R_W_MM },
14740 { EXTRV_S_H, EXTRV_S_H, EXTRV_S_H_MM },
14741 { EXTRV_W, EXTRV_W, EXTRV_W_MM },
14742 { EXTR_RS_W, EXTR_RS_W, EXTR_RS_W_MM },
14743 { EXTR_R_W, EXTR_R_W, EXTR_R_W_MM },
14744 { EXTR_S_H, EXTR_S_H, EXTR_S_H_MM },
14745 { EXTR_W, EXTR_W, EXTR_W_MM },
14746 { INSV, INSV, INSV_MM },
14747 { LBUX, LBUX, LBUX_MM },
14748 { LHX, LHX, LHX_MM },
14749 { LWDSP, LWDSP, LWDSP_MM },
14750 { LWX, LWX, LWX_MM },
14751 { MADDU_DSP, MADDU_DSP, MADDU_DSP_MM },
14752 { MADD_DSP, MADD_DSP, MADD_DSP_MM },
14753 { MAQ_SA_W_PHL, MAQ_SA_W_PHL, MAQ_SA_W_PHL_MM },
14754 { MAQ_SA_W_PHR, MAQ_SA_W_PHR, MAQ_SA_W_PHR_MM },
14755 { MAQ_S_W_PHL, MAQ_S_W_PHL, MAQ_S_W_PHL_MM },
14756 { MAQ_S_W_PHR, MAQ_S_W_PHR, MAQ_S_W_PHR_MM },
14757 { MFHI_DSP, MFHI_DSP, MFHI_DSP_MM },
14758 { MFLO_DSP, MFLO_DSP, MFLO_DSP_MM },
14759 { MODSUB, MODSUB, MODSUB_MM },
14760 { MSUBU_DSP, MSUBU_DSP, MSUBU_DSP_MM },
14761 { MSUB_DSP, MSUB_DSP, MSUB_DSP_MM },
14762 { MTHI_DSP, MTHI_DSP, MTHI_DSP_MM },
14763 { MTHLIP, MTHLIP, MTHLIP_MM },
14764 { MTLO_DSP, MTLO_DSP, MTLO_DSP_MM },
14765 { MULEQ_S_W_PHL, MULEQ_S_W_PHL, MULEQ_S_W_PHL_MM },
14766 { MULEQ_S_W_PHR, MULEQ_S_W_PHR, MULEQ_S_W_PHR_MM },
14767 { MULEU_S_PH_QBL, MULEU_S_PH_QBL, MULEU_S_PH_QBL_MM },
14768 { MULEU_S_PH_QBR, MULEU_S_PH_QBR, MULEU_S_PH_QBR_MM },
14769 { MULQ_RS_PH, MULQ_RS_PH, MULQ_RS_PH_MM },
14770 { MULQ_RS_W, MULQ_RS_W, MULQ_RS_W_MMR2 },
14771 { MULQ_S_PH, MULQ_S_PH, MULQ_S_PH_MMR2 },
14772 { MULQ_S_W, MULQ_S_W, MULQ_S_W_MMR2 },
14773 { MULSAQ_S_W_PH, MULSAQ_S_W_PH, MULSAQ_S_W_PH_MM },
14774 { MULSA_W_PH, MULSA_W_PH, MULSA_W_PH_MMR2 },
14775 { MULTU_DSP, MULTU_DSP, MULTU_DSP_MM },
14776 { MULT_DSP, MULT_DSP, MULT_DSP_MM },
14777 { MUL_PH, MUL_PH, MUL_PH_MMR2 },
14778 { MUL_S_PH, MUL_S_PH, MUL_S_PH_MMR2 },
14779 { PACKRL_PH, PACKRL_PH, PACKRL_PH_MM },
14780 { PICK_PH, PICK_PH, PICK_PH_MM },
14781 { PICK_QB, PICK_QB, PICK_QB_MM },
14782 { PRECEQU_PH_QBL, PRECEQU_PH_QBL, PRECEQU_PH_QBL_MM },
14783 { PRECEQU_PH_QBLA, PRECEQU_PH_QBLA, PRECEQU_PH_QBLA_MM },
14784 { PRECEQU_PH_QBR, PRECEQU_PH_QBR, PRECEQU_PH_QBR_MM },
14785 { PRECEQU_PH_QBRA, PRECEQU_PH_QBRA, PRECEQU_PH_QBRA_MM },
14786 { PRECEQ_W_PHL, PRECEQ_W_PHL, PRECEQ_W_PHL_MM },
14787 { PRECEQ_W_PHR, PRECEQ_W_PHR, PRECEQ_W_PHR_MM },
14788 { PRECEU_PH_QBL, PRECEU_PH_QBL, PRECEU_PH_QBL_MM },
14789 { PRECEU_PH_QBLA, PRECEU_PH_QBLA, PRECEU_PH_QBLA_MM },
14790 { PRECEU_PH_QBR, PRECEU_PH_QBR, PRECEU_PH_QBR_MM },
14791 { PRECEU_PH_QBRA, PRECEU_PH_QBRA, PRECEU_PH_QBRA_MM },
14792 { PRECRQU_S_QB_PH, PRECRQU_S_QB_PH, PRECRQU_S_QB_PH_MM },
14793 { PRECRQ_PH_W, PRECRQ_PH_W, PRECRQ_PH_W_MM },
14794 { PRECRQ_QB_PH, PRECRQ_QB_PH, PRECRQ_QB_PH_MM },
14795 { PRECRQ_RS_PH_W, PRECRQ_RS_PH_W, PRECRQ_RS_PH_W_MM },
14796 { PRECR_QB_PH, PRECR_QB_PH, PRECR_QB_PH_MMR2 },
14797 { PRECR_SRA_PH_W, PRECR_SRA_PH_W, PRECR_SRA_PH_W_MMR2 },
14798 { PRECR_SRA_R_PH_W, PRECR_SRA_R_PH_W, PRECR_SRA_R_PH_W_MMR2 },
14799 { PREPEND, PREPEND, PREPEND_MMR2 },
14800 { RADDU_W_QB, RADDU_W_QB, RADDU_W_QB_MM },
14801 { RDDSP, RDDSP, RDDSP_MM },
14802 { REPLV_PH, REPLV_PH, REPLV_PH_MM },
14803 { REPLV_QB, REPLV_QB, REPLV_QB_MM },
14804 { REPL_PH, REPL_PH, REPL_PH_MM },
14805 { REPL_QB, REPL_QB, REPL_QB_MM },
14806 { SHILO, SHILO, SHILO_MM },
14807 { SHILOV, SHILOV, SHILOV_MM },
14808 { SHLLV_PH, SHLLV_PH, SHLLV_PH_MM },
14809 { SHLLV_QB, SHLLV_QB, SHLLV_QB_MM },
14810 { SHLLV_S_PH, SHLLV_S_PH, SHLLV_S_PH_MM },
14811 { SHLLV_S_W, SHLLV_S_W, SHLLV_S_W_MM },
14812 { SHLL_PH, SHLL_PH, SHLL_PH_MM },
14813 { SHLL_QB, SHLL_QB, SHLL_QB_MM },
14814 { SHLL_S_PH, SHLL_S_PH, SHLL_S_PH_MM },
14815 { SHLL_S_W, SHLL_S_W, SHLL_S_W_MM },
14816 { SHRAV_PH, SHRAV_PH, SHRAV_PH_MM },
14817 { SHRAV_QB, SHRAV_QB, SHRAV_QB_MMR2 },
14818 { SHRAV_R_PH, SHRAV_R_PH, SHRAV_R_PH_MM },
14819 { SHRAV_R_QB, SHRAV_R_QB, SHRAV_R_QB_MMR2 },
14820 { SHRAV_R_W, SHRAV_R_W, SHRAV_R_W_MM },
14821 { SHRA_PH, SHRA_PH, SHRA_PH_MM },
14822 { SHRA_QB, SHRA_QB, SHRA_QB_MMR2 },
14823 { SHRA_R_PH, SHRA_R_PH, SHRA_R_PH_MM },
14824 { SHRA_R_QB, SHRA_R_QB, SHRA_R_QB_MMR2 },
14825 { SHRA_R_W, SHRA_R_W, SHRA_R_W_MM },
14826 { SHRLV_PH, SHRLV_PH, SHRLV_PH_MMR2 },
14827 { SHRLV_QB, SHRLV_QB, SHRLV_QB_MM },
14828 { SHRL_PH, SHRL_PH, SHRL_PH_MMR2 },
14829 { SHRL_QB, SHRL_QB, SHRL_QB_MM },
14830 { SUBQH_PH, SUBQH_PH, SUBQH_PH_MMR2 },
14831 { SUBQH_R_PH, SUBQH_R_PH, SUBQH_R_PH_MMR2 },
14832 { SUBQH_R_W, SUBQH_R_W, SUBQH_R_W_MMR2 },
14833 { SUBQH_W, SUBQH_W, SUBQH_W_MMR2 },
14834 { SUBQ_PH, SUBQ_PH, SUBQ_PH_MM },
14835 { SUBQ_S_PH, SUBQ_S_PH, SUBQ_S_PH_MM },
14836 { SUBQ_S_W, SUBQ_S_W, SUBQ_S_W_MM },
14837 { SUBUH_QB, SUBUH_QB, SUBUH_QB_MMR2 },
14838 { SUBUH_R_QB, SUBUH_R_QB, SUBUH_R_QB_MMR2 },
14839 { SUBU_PH, SUBU_PH, SUBU_PH_MMR2 },
14840 { SUBU_QB, SUBU_QB, SUBU_QB_MM },
14841 { SUBU_S_PH, SUBU_S_PH, SUBU_S_PH_MMR2 },
14842 { SUBU_S_QB, SUBU_S_QB, SUBU_S_QB_MM },
14843 { SWDSP, SWDSP, SWDSP_MM },
14844 }; // End of Table
14845
14846 unsigned mid;
14847 unsigned start = 0;
14848 unsigned end = 160;
14849 while (start < end) {
14850 mid = start + (end - start) / 2;
14851 if (Opcode == Table[mid][0])
14852 break;
14853 if (Opcode < Table[mid][0])
14854 end = mid;
14855 else
14856 start = mid + 1;
14857 }
14858 if (start == end)
14859 return -1; // Instruction doesn't exist in this table.
14860
14861 if (inArch == Arch_dsp)
14862 return Table[mid][1];
14863 if (inArch == Arch_mmdsp)
14864 return Table[mid][2];
14865 return -1;}
14866
14867// MipsR62MicroMipsR6
14868LLVM_READONLY
14869int MipsR62MicroMipsR6(uint16_t Opcode, enum Arch inArch) {
14870 using namespace Mips;
14871 static constexpr uint16_t Table[][3] = {
14872 { ADDIUPC, ADDIUPC, ADDIUPC_MMR6 },
14873 { ALIGN, ALIGN, ALIGN_MMR6 },
14874 { ALUIPC, ALUIPC, ALUIPC_MMR6 },
14875 { AUI, AUI, AUI_MMR6 },
14876 { AUIPC, AUIPC, AUIPC_MMR6 },
14877 { BALC, BALC, BALC_MMR6 },
14878 { BC, BC, BC_MMR6 },
14879 { BEQC, BEQC, BEQC_MMR6 },
14880 { BEQZALC, BEQZALC, BEQZALC_MMR6 },
14881 { BEQZC, BEQZC, BEQZC_MMR6 },
14882 { BGEC, BGEC, BGEC_MMR6 },
14883 { BGEUC, BGEUC, BGEUC_MMR6 },
14884 { BGEZALC, BGEZALC, BGEZALC_MMR6 },
14885 { BGEZC, BGEZC, BGEZC_MMR6 },
14886 { BGTZALC, BGTZALC, BGTZALC_MMR6 },
14887 { BGTZC, BGTZC, BGTZC_MMR6 },
14888 { BITSWAP, BITSWAP, BITSWAP_MMR6 },
14889 { BLEZALC, BLEZALC, BLEZALC_MMR6 },
14890 { BLEZC, BLEZC, BLEZC_MMR6 },
14891 { BLTC, BLTC, BLTC_MMR6 },
14892 { BLTUC, BLTUC, BLTUC_MMR6 },
14893 { BLTZALC, BLTZALC, BLTZALC_MMR6 },
14894 { BLTZC, BLTZC, BLTZC_MMR6 },
14895 { BNEC, BNEC, BNEC_MMR6 },
14896 { BNEZALC, BNEZALC, BNEZALC_MMR6 },
14897 { BNEZC, BNEZC, BNEZC_MMR6 },
14898 { BNVC, BNVC, BNVC_MMR6 },
14899 { BOVC, BOVC, BOVC_MMR6 },
14900 { CACHE_R6, CACHE_R6, CACHE_MMR6 },
14901 { CLO_R6, CLO_R6, CLO_MMR6 },
14902 { CLZ_R6, CLZ_R6, CLZ_MMR6 },
14903 { CMP_EQ_D, CMP_EQ_D, CMP_EQ_D_MMR6 },
14904 { CMP_EQ_S, CMP_EQ_S, CMP_EQ_S_MMR6 },
14905 { CMP_F_D, CMP_F_D, CMP_AF_D_MMR6 },
14906 { CMP_F_S, CMP_F_S, CMP_AF_S_MMR6 },
14907 { CMP_LE_D, CMP_LE_D, CMP_LE_D_MMR6 },
14908 { CMP_LE_S, CMP_LE_S, CMP_LE_S_MMR6 },
14909 { CMP_LT_D, CMP_LT_D, CMP_LT_D_MMR6 },
14910 { CMP_LT_S, CMP_LT_S, CMP_LT_S_MMR6 },
14911 { CMP_SAF_D, CMP_SAF_D, CMP_SAF_D_MMR6 },
14912 { CMP_SAF_S, CMP_SAF_S, CMP_SAF_S_MMR6 },
14913 { CMP_SEQ_D, CMP_SEQ_D, CMP_SEQ_D_MMR6 },
14914 { CMP_SEQ_S, CMP_SEQ_S, CMP_SEQ_S_MMR6 },
14915 { CMP_SLE_D, CMP_SLE_D, CMP_SLE_D_MMR6 },
14916 { CMP_SLE_S, CMP_SLE_S, CMP_SLE_S_MMR6 },
14917 { CMP_SLT_D, CMP_SLT_D, CMP_SLT_D_MMR6 },
14918 { CMP_SLT_S, CMP_SLT_S, CMP_SLT_S_MMR6 },
14919 { CMP_SUEQ_D, CMP_SUEQ_D, CMP_SUEQ_D_MMR6 },
14920 { CMP_SUEQ_S, CMP_SUEQ_S, CMP_SUEQ_S_MMR6 },
14921 { CMP_SULE_D, CMP_SULE_D, CMP_SULE_D_MMR6 },
14922 { CMP_SULE_S, CMP_SULE_S, CMP_SULE_S_MMR6 },
14923 { CMP_SULT_D, CMP_SULT_D, CMP_SULT_D_MMR6 },
14924 { CMP_SULT_S, CMP_SULT_S, CMP_SULT_S_MMR6 },
14925 { CMP_SUN_D, CMP_SUN_D, CMP_SUN_D_MMR6 },
14926 { CMP_SUN_S, CMP_SUN_S, CMP_SUN_S_MMR6 },
14927 { CMP_UEQ_D, CMP_UEQ_D, CMP_UEQ_D_MMR6 },
14928 { CMP_UEQ_S, CMP_UEQ_S, CMP_UEQ_S_MMR6 },
14929 { CMP_ULE_D, CMP_ULE_D, CMP_ULE_D_MMR6 },
14930 { CMP_ULE_S, CMP_ULE_S, CMP_ULE_S_MMR6 },
14931 { CMP_ULT_D, CMP_ULT_D, CMP_ULT_D_MMR6 },
14932 { CMP_ULT_S, CMP_ULT_S, CMP_ULT_S_MMR6 },
14933 { CMP_UN_D, CMP_UN_D, CMP_UN_D_MMR6 },
14934 { CMP_UN_S, CMP_UN_S, CMP_UN_S_MMR6 },
14935 { CRC32B, CRC32B, (uint16_t)-1U },
14936 { CRC32CB, CRC32CB, (uint16_t)-1U },
14937 { CRC32CD, CRC32CD, (uint16_t)-1U },
14938 { CRC32CH, CRC32CH, (uint16_t)-1U },
14939 { CRC32CW, CRC32CW, (uint16_t)-1U },
14940 { CRC32D, CRC32D, (uint16_t)-1U },
14941 { CRC32H, CRC32H, (uint16_t)-1U },
14942 { CRC32W, CRC32W, (uint16_t)-1U },
14943 { DIV, DIV, DIV_MMR6 },
14944 { DIVU, DIVU, DIVU_MMR6 },
14945 { DVP, DVP, DVP_MMR6 },
14946 { EVP, EVP, EVP_MMR6 },
14947 { GINVI, GINVI, GINVI_MMR6 },
14948 { GINVT, GINVT, GINVT_MMR6 },
14949 { JIALC, JIALC, JIALC_MMR6 },
14950 { JIC, JIC, JIC_MMR6 },
14951 { LSA_R6, LSA_R6, LSA_MMR6 },
14952 { LWPC, LWPC, LWPC_MMR6 },
14953 { MOD, MOD, MOD_MMR6 },
14954 { MODU, MODU, MODU_MMR6 },
14955 { MUH, MUH, MUH_MMR6 },
14956 { MUHU, MUHU, MUHU_MMR6 },
14957 { MULU, MULU, MULU_MMR6 },
14958 { MUL_R6, MUL_R6, MUL_MMR6 },
14959 { PREF_R6, PREF_R6, PREF_MMR6 },
14960 { SELEQZ, SELEQZ, SELEQZ_MMR6 },
14961 { SELEQZ_D, SELEQZ_D, SELEQZ_D_MMR6 },
14962 { SELEQZ_S, SELEQZ_S, SELEQZ_S_MMR6 },
14963 { SELNEZ, SELNEZ, SELNEZ_MMR6 },
14964 { SELNEZ_D, SELNEZ_D, SELNEZ_D_MMR6 },
14965 { SELNEZ_S, SELNEZ_S, SELNEZ_S_MMR6 },
14966 { SEL_D, SEL_D, SEL_D_MMR6 },
14967 { SEL_S, SEL_S, SEL_S_MMR6 },
14968 }; // End of Table
14969
14970 unsigned mid;
14971 unsigned start = 0;
14972 unsigned end = 96;
14973 while (start < end) {
14974 mid = start + (end - start) / 2;
14975 if (Opcode == Table[mid][0])
14976 break;
14977 if (Opcode < Table[mid][0])
14978 end = mid;
14979 else
14980 start = mid + 1;
14981 }
14982 if (start == end)
14983 return -1; // Instruction doesn't exist in this table.
14984
14985 if (inArch == Arch_mipsr6)
14986 return Table[mid][1];
14987 if (inArch == Arch_micromipsr6)
14988 return Table[mid][2];
14989 return -1;}
14990
14991// Std2MicroMips
14992LLVM_READONLY
14993int Std2MicroMips(uint16_t Opcode, enum Arch inArch) {
14994 using namespace Mips;
14995 static constexpr uint16_t Table[][3] = {
14996 { ADD, ADD, ADD_MM },
14997 { ADDi, ADDi, ADDi_MM },
14998 { ADDiu, ADDiu, ADDiu_MM },
14999 { ADDu, ADDu, ADDu_MM },
15000 { AND, AND, AND_MM },
15001 { ANDi, ANDi, ANDi_MM },
15002 { BC1F, BC1F, BC1F_MM },
15003 { BC1FL, BC1FL, (uint16_t)-1U },
15004 { BC1T, BC1T, BC1T_MM },
15005 { BC1TL, BC1TL, (uint16_t)-1U },
15006 { BEQ, BEQ, BEQ_MM },
15007 { BEQL, BEQL, (uint16_t)-1U },
15008 { BGEZ, BGEZ, BGEZ_MM },
15009 { BGEZAL, BGEZAL, BGEZAL_MM },
15010 { BGEZALL, BGEZALL, (uint16_t)-1U },
15011 { BGEZL, BGEZL, (uint16_t)-1U },
15012 { BGTZ, BGTZ, BGTZ_MM },
15013 { BGTZL, BGTZL, (uint16_t)-1U },
15014 { BLEZ, BLEZ, BLEZ_MM },
15015 { BLEZL, BLEZL, (uint16_t)-1U },
15016 { BLTZ, BLTZ, BLTZ_MM },
15017 { BLTZAL, BLTZAL, BLTZAL_MM },
15018 { BLTZALL, BLTZALL, (uint16_t)-1U },
15019 { BLTZL, BLTZL, (uint16_t)-1U },
15020 { BNE, BNE, BNE_MM },
15021 { BNEL, BNEL, (uint16_t)-1U },
15022 { BREAK, BREAK, BREAK_MM },
15023 { CACHE, CACHE, CACHE_MM },
15024 { CACHEE, CACHEE, CACHEE_MM },
15025 { CEIL_W_D32, CEIL_W_D32, CEIL_W_MM },
15026 { CEIL_W_S, CEIL_W_S, CEIL_W_S_MM },
15027 { CFC1, CFC1, CFC1_MM },
15028 { CLO, CLO, CLO_MM },
15029 { CLZ, CLZ, CLZ_MM },
15030 { CTC1, CTC1, CTC1_MM },
15031 { CVT_D32_S, CVT_D32_S, CVT_D32_S_MM },
15032 { CVT_D32_W, CVT_D32_W, CVT_D32_W_MM },
15033 { CVT_L_D64, CVT_L_D64, CVT_L_D64_MM },
15034 { CVT_L_S, CVT_L_S, CVT_L_S_MM },
15035 { CVT_S_D32, CVT_S_D32, CVT_S_D32_MM },
15036 { CVT_S_W, CVT_S_W, CVT_S_W_MM },
15037 { CVT_W_D32, CVT_W_D32, CVT_W_D32_MM },
15038 { CVT_W_S, CVT_W_S, CVT_W_S_MM },
15039 { C_EQ_D32, C_EQ_D32, C_EQ_D32_MM },
15040 { C_EQ_D64, C_EQ_D64, C_EQ_D64_MM },
15041 { C_EQ_S, C_EQ_S, C_EQ_S_MM },
15042 { C_F_D32, C_F_D32, C_F_D32_MM },
15043 { C_F_D64, C_F_D64, C_F_D64_MM },
15044 { C_F_S, C_F_S, C_F_S_MM },
15045 { C_LE_D32, C_LE_D32, C_LE_D32_MM },
15046 { C_LE_D64, C_LE_D64, C_LE_D64_MM },
15047 { C_LE_S, C_LE_S, C_LE_S_MM },
15048 { C_LT_D32, C_LT_D32, C_LT_D32_MM },
15049 { C_LT_D64, C_LT_D64, C_LT_D64_MM },
15050 { C_LT_S, C_LT_S, C_LT_S_MM },
15051 { C_NGE_D32, C_NGE_D32, C_NGE_D32_MM },
15052 { C_NGE_D64, C_NGE_D64, C_NGE_D64_MM },
15053 { C_NGE_S, C_NGE_S, C_NGE_S_MM },
15054 { C_NGLE_D32, C_NGLE_D32, C_NGLE_D32_MM },
15055 { C_NGLE_D64, C_NGLE_D64, C_NGLE_D64_MM },
15056 { C_NGLE_S, C_NGLE_S, C_NGLE_S_MM },
15057 { C_NGL_D32, C_NGL_D32, C_NGL_D32_MM },
15058 { C_NGL_D64, C_NGL_D64, C_NGL_D64_MM },
15059 { C_NGL_S, C_NGL_S, C_NGL_S_MM },
15060 { C_NGT_D32, C_NGT_D32, C_NGT_D32_MM },
15061 { C_NGT_D64, C_NGT_D64, C_NGT_D64_MM },
15062 { C_NGT_S, C_NGT_S, C_NGT_S_MM },
15063 { C_OLE_D32, C_OLE_D32, C_OLE_D32_MM },
15064 { C_OLE_D64, C_OLE_D64, C_OLE_D64_MM },
15065 { C_OLE_S, C_OLE_S, C_OLE_S_MM },
15066 { C_OLT_D32, C_OLT_D32, C_OLT_D32_MM },
15067 { C_OLT_D64, C_OLT_D64, C_OLT_D64_MM },
15068 { C_OLT_S, C_OLT_S, C_OLT_S_MM },
15069 { C_SEQ_D32, C_SEQ_D32, C_SEQ_D32_MM },
15070 { C_SEQ_D64, C_SEQ_D64, C_SEQ_D64_MM },
15071 { C_SEQ_S, C_SEQ_S, C_SEQ_S_MM },
15072 { C_SF_D32, C_SF_D32, C_SF_D32_MM },
15073 { C_SF_D64, C_SF_D64, C_SF_D64_MM },
15074 { C_SF_S, C_SF_S, C_SF_S_MM },
15075 { C_UEQ_D32, C_UEQ_D32, C_UEQ_D32_MM },
15076 { C_UEQ_D64, C_UEQ_D64, C_UEQ_D64_MM },
15077 { C_UEQ_S, C_UEQ_S, C_UEQ_S_MM },
15078 { C_ULE_D32, C_ULE_D32, C_ULE_D32_MM },
15079 { C_ULE_D64, C_ULE_D64, C_ULE_D64_MM },
15080 { C_ULE_S, C_ULE_S, C_ULE_S_MM },
15081 { C_ULT_D32, C_ULT_D32, C_ULT_D32_MM },
15082 { C_ULT_D64, C_ULT_D64, C_ULT_D64_MM },
15083 { C_ULT_S, C_ULT_S, C_ULT_S_MM },
15084 { C_UN_D32, C_UN_D32, C_UN_D32_MM },
15085 { C_UN_D64, C_UN_D64, C_UN_D64_MM },
15086 { C_UN_S, C_UN_S, C_UN_S_MM },
15087 { DERET, DERET, DERET_MM },
15088 { DI, DI, DI_MM },
15089 { EHB, EHB, EHB_MM },
15090 { EI, EI, EI_MM },
15091 { ERET, ERET, ERET_MM },
15092 { ERETNC, ERETNC, (uint16_t)-1U },
15093 { EXT, EXT, EXT_MM },
15094 { FABS_D32, FABS_D32, FABS_D32_MM },
15095 { FABS_S, FABS_S, FABS_S_MM },
15096 { FADD_D32, FADD_D32, FADD_D32_MM },
15097 { FADD_S, FADD_S, FADD_S_MM },
15098 { FCMP_D32, FCMP_D32, FCMP_D32_MM },
15099 { FCMP_S32, FCMP_S32, FCMP_S32_MM },
15100 { FDIV_D32, FDIV_D32, FDIV_D32_MM },
15101 { FDIV_S, FDIV_S, FDIV_S_MM },
15102 { FLOOR_W_D32, FLOOR_W_D32, FLOOR_W_MM },
15103 { FLOOR_W_S, FLOOR_W_S, FLOOR_W_S_MM },
15104 { FMOV_D32, FMOV_D32, FMOV_D32_MM },
15105 { FMOV_S, FMOV_S, FMOV_S_MM },
15106 { FMUL_D32, FMUL_D32, FMUL_D32_MM },
15107 { FMUL_S, FMUL_S, FMUL_S_MM },
15108 { FNEG_D32, FNEG_D32, FNEG_D32_MM },
15109 { FNEG_S, FNEG_S, FNEG_S_MM },
15110 { FSQRT_D32, FSQRT_D32, FSQRT_D32_MM },
15111 { FSQRT_S, FSQRT_S, FSQRT_S_MM },
15112 { FSUB_D32, FSUB_D32, FSUB_D32_MM },
15113 { FSUB_S, FSUB_S, FSUB_S_MM },
15114 { HYPCALL, HYPCALL, HYPCALL_MM },
15115 { INS, INS, INS_MM },
15116 { J, J, J_MM },
15117 { JAL, JAL, JAL_MM },
15118 { JALX, JALX, JALX_MM },
15119 { JR, JR, JR_MM },
15120 { LB, LB, LB_MM },
15121 { LBE, LBE, LBE_MM },
15122 { LBu, LBu, LBu_MM },
15123 { LBuE, LBuE, LBuE_MM },
15124 { LDC1, LDC1, LDC1_MM_D32 },
15125 { LEA_ADDiu, LEA_ADDiu, LEA_ADDiu_MM },
15126 { LH, LH, LH_MM },
15127 { LHE, LHE, LHE_MM },
15128 { LHu, LHu, LHu_MM },
15129 { LHuE, LHuE, LHuE_MM },
15130 { LLE, LLE, LLE_MM },
15131 { LUXC1, LUXC1, LUXC1_MM },
15132 { LUi, LUi, LUi_MM },
15133 { LW, LW, LW_MM },
15134 { LWC1, LWC1, LWC1_MM },
15135 { LWE, LWE, LWE_MM },
15136 { LWL, LWL, LWL_MM },
15137 { LWLE, LWLE, LWLE_MM },
15138 { LWR, LWR, LWR_MM },
15139 { LWRE, LWRE, LWRE_MM },
15140 { LWXC1, LWXC1, LWXC1_MM },
15141 { LWu, LWu, LWU_MM },
15142 { MADD, MADD, MADD_MM },
15143 { MADDU, MADDU, MADDU_MM },
15144 { MADD_D32, MADD_D32, MADD_D32_MM },
15145 { MADD_S, MADD_S, MADD_S_MM },
15146 { MFC1, MFC1, MFC1_MM },
15147 { MFGC0, MFGC0, MFGC0_MM },
15148 { MFHC1_D32, MFHC1_D32, MFHC1_D32_MM },
15149 { MFHGC0, MFHGC0, MFHGC0_MM },
15150 { MFHI, MFHI, MFHI_MM },
15151 { MFLO, MFLO, MFLO_MM },
15152 { MOVF_D32, MOVF_D32, MOVF_D32_MM },
15153 { MOVF_I, MOVF_I, MOVF_I_MM },
15154 { MOVF_S, MOVF_S, MOVF_S_MM },
15155 { MOVN_I_D32, MOVN_I_D32, MOVN_I_D32_MM },
15156 { MOVN_I_I, MOVN_I_I, MOVN_I_MM },
15157 { MOVN_I_S, MOVN_I_S, MOVN_I_S_MM },
15158 { MOVT_D32, MOVT_D32, MOVT_D32_MM },
15159 { MOVT_I, MOVT_I, MOVT_I_MM },
15160 { MOVT_S, MOVT_S, MOVT_S_MM },
15161 { MOVZ_I_D32, MOVZ_I_D32, MOVZ_I_D32_MM },
15162 { MOVZ_I_I, MOVZ_I_I, MOVZ_I_MM },
15163 { MOVZ_I_S, MOVZ_I_S, MOVZ_I_S_MM },
15164 { MSUB, MSUB, MSUB_MM },
15165 { MSUBU, MSUBU, MSUBU_MM },
15166 { MSUB_D32, MSUB_D32, MSUB_D32_MM },
15167 { MSUB_S, MSUB_S, MSUB_S_MM },
15168 { MTC1, MTC1, MTC1_MM },
15169 { MTGC0, MTGC0, MTGC0_MM },
15170 { MTHC1_D32, MTHC1_D32, MTHC1_D32_MM },
15171 { MTHGC0, MTHGC0, MTHGC0_MM },
15172 { MTHI, MTHI, MTHI_MM },
15173 { MTLO, MTLO, MTLO_MM },
15174 { MUL, MUL, MUL_MM },
15175 { MULT, MULT, MULT_MM },
15176 { MULTu, MULTu, MULTu_MM },
15177 { NMADD_D32, NMADD_D32, NMADD_D32_MM },
15178 { NMADD_S, NMADD_S, NMADD_S_MM },
15179 { NMSUB_D32, NMSUB_D32, NMSUB_D32_MM },
15180 { NMSUB_S, NMSUB_S, NMSUB_S_MM },
15181 { NOR, NOR, NOR_MM },
15182 { OR, OR, OR_MM },
15183 { ORi, ORi, ORi_MM },
15184 { PAUSE, PAUSE, PAUSE_MM },
15185 { PREF, PREF, PREF_MM },
15186 { PREFE, PREFE, PREFE_MM },
15187 { RDHWR, RDHWR, RDHWR_MM },
15188 { RECIP_D32, RECIP_D32, RECIP_D32_MM },
15189 { RECIP_D64, RECIP_D64, RECIP_D64_MM },
15190 { RECIP_S, RECIP_S, RECIP_S_MM },
15191 { ROTR, ROTR, ROTR_MM },
15192 { ROTRV, ROTRV, ROTRV_MM },
15193 { ROUND_W_D32, ROUND_W_D32, ROUND_W_MM },
15194 { ROUND_W_S, ROUND_W_S, ROUND_W_S_MM },
15195 { RSQRT_D32, RSQRT_D32, RSQRT_D32_MM },
15196 { RSQRT_D64, RSQRT_D64, RSQRT_D64_MM },
15197 { RSQRT_S, RSQRT_S, RSQRT_S_MM },
15198 { SB, SB, SB_MM },
15199 { SBE, SBE, SBE_MM },
15200 { SCE, SCE, SCE_MM },
15201 { SDBBP, SDBBP, SDBBP_MM },
15202 { SDC1, SDC1, (uint16_t)-1U },
15203 { SDIV, SDIV, SDIV_MM },
15204 { SEB, SEB, SEB_MM },
15205 { SEH, SEH, SEH_MM },
15206 { SH, SH, SH_MM },
15207 { SHE, SHE, SHE_MM },
15208 { SLL, SLL, SLL_MM },
15209 { SLLV, SLLV, SLLV_MM },
15210 { SLT, SLT, SLT_MM },
15211 { SLTi, SLTi, SLTi_MM },
15212 { SLTiu, SLTiu, SLTiu_MM },
15213 { SLTu, SLTu, SLTu_MM },
15214 { SRA, SRA, SRA_MM },
15215 { SRAV, SRAV, SRAV_MM },
15216 { SRL, SRL, SRL_MM },
15217 { SRLV, SRLV, SRLV_MM },
15218 { SSNOP, SSNOP, SSNOP_MM },
15219 { SUB, SUB, SUB_MM },
15220 { SUBu, SUBu, SUBu_MM },
15221 { SUXC1, SUXC1, SUXC1_MM },
15222 { SW, SW, SW_MM },
15223 { SWC1, SWC1, SWC1_MM },
15224 { SWE, SWE, SWE_MM },
15225 { SWL, SWL, SWL_MM },
15226 { SWLE, SWLE, SWLE_MM },
15227 { SWR, SWR, SWR_MM },
15228 { SWRE, SWRE, SWRE_MM },
15229 { SWXC1, SWXC1, SWXC1_MM },
15230 { SYNC, SYNC, SYNC_MM },
15231 { SYNCI, SYNCI, SYNCI_MM },
15232 { SYSCALL, SYSCALL, SYSCALL_MM },
15233 { TEQ, TEQ, TEQ_MM },
15234 { TEQI, TEQI, TEQI_MM },
15235 { TGE, TGE, TGE_MM },
15236 { TGEI, TGEI, TGEI_MM },
15237 { TGEIU, TGEIU, TGEIU_MM },
15238 { TGEU, TGEU, TGEU_MM },
15239 { TLBGINV, TLBGINV, TLBGINV_MM },
15240 { TLBGINVF, TLBGINVF, TLBGINVF_MM },
15241 { TLBGP, TLBGP, TLBGP_MM },
15242 { TLBGR, TLBGR, TLBGR_MM },
15243 { TLBGWI, TLBGWI, TLBGWI_MM },
15244 { TLBGWR, TLBGWR, TLBGWR_MM },
15245 { TLBP, TLBP, TLBP_MM },
15246 { TLBR, TLBR, TLBR_MM },
15247 { TLBWI, TLBWI, TLBWI_MM },
15248 { TLBWR, TLBWR, TLBWR_MM },
15249 { TLT, TLT, TLT_MM },
15250 { TLTI, TLTI, TLTI_MM },
15251 { TLTU, TLTU, TLTU_MM },
15252 { TNE, TNE, TNE_MM },
15253 { TNEI, TNEI, TNEI_MM },
15254 { TRUNC_W_D32, TRUNC_W_D32, TRUNC_W_MM },
15255 { TRUNC_W_S, TRUNC_W_S, TRUNC_W_S_MM },
15256 { TTLTIU, TTLTIU, TLTIU_MM },
15257 { UDIV, UDIV, UDIV_MM },
15258 { WAIT, WAIT, WAIT_MM },
15259 { WSBH, WSBH, WSBH_MM },
15260 { XOR, XOR, XOR_MM },
15261 { XORi, XORi, XORi_MM },
15262 }; // End of Table
15263
15264 unsigned mid;
15265 unsigned start = 0;
15266 unsigned end = 266;
15267 while (start < end) {
15268 mid = start + (end - start) / 2;
15269 if (Opcode == Table[mid][0])
15270 break;
15271 if (Opcode < Table[mid][0])
15272 end = mid;
15273 else
15274 start = mid + 1;
15275 }
15276 if (start == end)
15277 return -1; // Instruction doesn't exist in this table.
15278
15279 if (inArch == Arch_se)
15280 return Table[mid][1];
15281 if (inArch == Arch_micromips)
15282 return Table[mid][2];
15283 return -1;}
15284
15285// Std2MicroMipsR6
15286LLVM_READONLY
15287int Std2MicroMipsR6(uint16_t Opcode, enum Arch inArch) {
15288 using namespace Mips;
15289 static constexpr uint16_t Table[][3] = {
15290 { ADD, ADD, ADD_MMR6 },
15291 { ADDiu, ADDiu, ADDIU_MMR6 },
15292 { ADDu, ADDu, ADDU_MMR6 },
15293 { AND, AND, AND_MMR6 },
15294 { ANDi, ANDi, ANDI_MMR6 },
15295 { BREAK, BREAK, BREAK_MMR6 },
15296 { CEIL_W_D64, CEIL_W_D64, CEIL_W_D_MMR6 },
15297 { CEIL_W_S, CEIL_W_S, CEIL_W_S_MMR6 },
15298 { CVT_W_D64, CVT_W_D64, (uint16_t)-1U },
15299 { DI, DI, DI_MMR6 },
15300 { EI, EI, EI_MMR6 },
15301 { EXT, EXT, EXT_MMR6 },
15302 { FABS_D64, FABS_D64, (uint16_t)-1U },
15303 { FLOOR_W_D64, FLOOR_W_D64, FLOOR_W_D_MMR6 },
15304 { FLOOR_W_S, FLOOR_W_S, FLOOR_W_S_MMR6 },
15305 { FMOV_D64, FMOV_D64, FMOV_D_MMR6 },
15306 { FNEG_D64, FNEG_D64, (uint16_t)-1U },
15307 { FSQRT_D64, FSQRT_D64, (uint16_t)-1U },
15308 { FSQRT_S, FSQRT_S, (uint16_t)-1U },
15309 { INS, INS, INS_MMR6 },
15310 { LDC1, LDC1, (uint16_t)-1U },
15311 { LDC164, LDC164, LDC1_D64_MMR6 },
15312 { LDC2, LDC2, LDC2_MMR6 },
15313 { LW, LW, LW_MMR6 },
15314 { LWC2, LWC2, LWC2_MMR6 },
15315 { MFC1, MFC1, MFC1_MMR6 },
15316 { MTC1, MTC1, MTC1_MMR6 },
15317 { MTHC1_D32, MTHC1_D32, (uint16_t)-1U },
15318 { NOR, NOR, NOR_MMR6 },
15319 { OR, OR, OR_MMR6 },
15320 { ORi, ORi, ORI_MMR6 },
15321 { PAUSE, PAUSE, PAUSE_MMR6 },
15322 { ROUND_W_D64, ROUND_W_D64, ROUND_W_D_MMR6 },
15323 { ROUND_W_S, ROUND_W_S, ROUND_W_S_MMR6 },
15324 { SB, SB, SB_MMR6 },
15325 { SDC164, SDC164, SDC1_D64_MMR6 },
15326 { SDC2, SDC2, SDC2_MMR6 },
15327 { SEB, SEB, (uint16_t)-1U },
15328 { SEH, SEH, (uint16_t)-1U },
15329 { SSNOP, SSNOP, SSNOP_MMR6 },
15330 { SUB, SUB, SUB_MMR6 },
15331 { SUBu, SUBu, SUBU_MMR6 },
15332 { SW, SW, SW_MMR6 },
15333 { SWC2, SWC2, SWC2_MMR6 },
15334 { SYNC, SYNC, SYNC_MMR6 },
15335 { SYNCI, SYNCI, SYNCI_MMR6 },
15336 { TRUNC_W_D64, TRUNC_W_D64, TRUNC_W_D_MMR6 },
15337 { TRUNC_W_S, TRUNC_W_S, TRUNC_W_S_MMR6 },
15338 { WAIT, WAIT, WAIT_MMR6 },
15339 { XOR, XOR, XOR_MMR6 },
15340 { XORi, XORi, XORI_MMR6 },
15341 }; // End of Table
15342
15343 unsigned mid;
15344 unsigned start = 0;
15345 unsigned end = 51;
15346 while (start < end) {
15347 mid = start + (end - start) / 2;
15348 if (Opcode == Table[mid][0])
15349 break;
15350 if (Opcode < Table[mid][0])
15351 end = mid;
15352 else
15353 start = mid + 1;
15354 }
15355 if (start == end)
15356 return -1; // Instruction doesn't exist in this table.
15357
15358 if (inArch == Arch_se)
15359 return Table[mid][1];
15360 if (inArch == Arch_micromipsr6)
15361 return Table[mid][2];
15362 return -1;}
15363
15364} // end namespace llvm::Mips
15365#endif // GET_INSTRMAP_INFO
15366
15367