1//===-- MipsMCTargetDesc.h - Mips Target Descriptions -----------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file provides Mips specific target descriptions.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCTARGETDESC_H
14#define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCTARGETDESC_H
15
16#include "llvm/Support/DataTypes.h"
17
18#include <memory>
19
20namespace llvm {
21class MCAsmBackend;
22class MCCodeEmitter;
23class MCContext;
24class MCInstrInfo;
25class MCObjectTargetWriter;
26class MCObjectWriter;
27class MCRegisterInfo;
28class MCStreamer;
29class MCSubtargetInfo;
30class MCTargetOptions;
31class StringRef;
32class Target;
33class Triple;
34
35MCCodeEmitter *createMipsMCCodeEmitterEB(const MCInstrInfo &MCII,
36 MCContext &Ctx);
37MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
38 MCContext &Ctx);
39
40MCAsmBackend *createMipsAsmBackend(const Target &T, const MCSubtargetInfo &STI,
41 const MCRegisterInfo &MRI,
42 const MCTargetOptions &Options);
43
44/// Construct an MIPS Windows COFF machine code streamer which will generate
45/// PE/COFF format object files.
46///
47/// Takes ownership of \p AB and \p CE.
48MCStreamer *createMipsWinCOFFStreamer(MCContext &C,
49 std::unique_ptr<MCAsmBackend> &&AB,
50 std::unique_ptr<MCObjectWriter> &&OW,
51 std::unique_ptr<MCCodeEmitter> &&CE);
52
53/// Construct a Mips ELF object writer.
54std::unique_ptr<MCObjectTargetWriter>
55createMipsELFObjectWriter(const Triple &TT, bool IsN32);
56/// Construct a Mips Win COFF object writer.
57std::unique_ptr<MCObjectTargetWriter> createMipsWinCOFFObjectWriter();
58
59namespace MIPS_MC {
60void initLLVMToCVRegMapping(MCRegisterInfo *MRI);
61
62StringRef selectMipsCPU(const Triple &TT, StringRef CPU);
63}
64
65} // End llvm namespace
66
67// Defines symbolic names for Mips registers. This defines a mapping from
68// register name to register number.
69#define GET_REGINFO_ENUM
70#include "MipsGenRegisterInfo.inc"
71
72// Defines symbolic names for the Mips instructions.
73#define GET_INSTRINFO_ENUM
74#define GET_INSTRINFO_MC_HELPER_DECLS
75#include "MipsGenInstrInfo.inc"
76
77#define GET_SUBTARGETINFO_ENUM
78#include "MipsGenSubtargetInfo.inc"
79
80#endif
81