1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register Enum Values *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_REGINFO_ENUM
11#undef GET_REGINFO_ENUM
12
13namespace llvm {
14
15class MCRegisterClass;
16extern const MCRegisterClass MipsMCRegisterClasses[];
17
18namespace Mips {
19enum : unsigned {
20 NoRegister,
21 AT = 1,
22 DSPCCond = 2,
23 DSPCarry = 3,
24 DSPEFI = 4,
25 DSPOutFlag = 5,
26 DSPPos = 6,
27 DSPSCount = 7,
28 FP = 8,
29 GP = 9,
30 MSAAccess = 10,
31 MSACSR = 11,
32 MSAIR = 12,
33 MSAMap = 13,
34 MSAModify = 14,
35 MSARequest = 15,
36 MSASave = 16,
37 MSAUnmap = 17,
38 PC = 18,
39 RA = 19,
40 SP = 20,
41 ZERO = 21,
42 A0 = 22,
43 A1 = 23,
44 A2 = 24,
45 A3 = 25,
46 AC0 = 26,
47 AC1 = 27,
48 AC2 = 28,
49 AC3 = 29,
50 AT_64 = 30,
51 COP00 = 31,
52 COP01 = 32,
53 COP02 = 33,
54 COP03 = 34,
55 COP04 = 35,
56 COP05 = 36,
57 COP06 = 37,
58 COP07 = 38,
59 COP08 = 39,
60 COP09 = 40,
61 COP20 = 41,
62 COP21 = 42,
63 COP22 = 43,
64 COP23 = 44,
65 COP24 = 45,
66 COP25 = 46,
67 COP26 = 47,
68 COP27 = 48,
69 COP28 = 49,
70 COP29 = 50,
71 COP30 = 51,
72 COP31 = 52,
73 COP32 = 53,
74 COP33 = 54,
75 COP34 = 55,
76 COP35 = 56,
77 COP36 = 57,
78 COP37 = 58,
79 COP38 = 59,
80 COP39 = 60,
81 COP010 = 61,
82 COP011 = 62,
83 COP012 = 63,
84 COP013 = 64,
85 COP014 = 65,
86 COP015 = 66,
87 COP016 = 67,
88 COP017 = 68,
89 COP018 = 69,
90 COP019 = 70,
91 COP020 = 71,
92 COP021 = 72,
93 COP022 = 73,
94 COP023 = 74,
95 COP024 = 75,
96 COP025 = 76,
97 COP026 = 77,
98 COP027 = 78,
99 COP028 = 79,
100 COP029 = 80,
101 COP030 = 81,
102 COP031 = 82,
103 COP210 = 83,
104 COP211 = 84,
105 COP212 = 85,
106 COP213 = 86,
107 COP214 = 87,
108 COP215 = 88,
109 COP216 = 89,
110 COP217 = 90,
111 COP218 = 91,
112 COP219 = 92,
113 COP220 = 93,
114 COP221 = 94,
115 COP222 = 95,
116 COP223 = 96,
117 COP224 = 97,
118 COP225 = 98,
119 COP226 = 99,
120 COP227 = 100,
121 COP228 = 101,
122 COP229 = 102,
123 COP230 = 103,
124 COP231 = 104,
125 COP310 = 105,
126 COP311 = 106,
127 COP312 = 107,
128 COP313 = 108,
129 COP314 = 109,
130 COP315 = 110,
131 COP316 = 111,
132 COP317 = 112,
133 COP318 = 113,
134 COP319 = 114,
135 COP320 = 115,
136 COP321 = 116,
137 COP322 = 117,
138 COP323 = 118,
139 COP324 = 119,
140 COP325 = 120,
141 COP326 = 121,
142 COP327 = 122,
143 COP328 = 123,
144 COP329 = 124,
145 COP330 = 125,
146 COP331 = 126,
147 D0 = 127,
148 D1 = 128,
149 D2 = 129,
150 D3 = 130,
151 D4 = 131,
152 D5 = 132,
153 D6 = 133,
154 D7 = 134,
155 D8 = 135,
156 D9 = 136,
157 D10 = 137,
158 D11 = 138,
159 D12 = 139,
160 D13 = 140,
161 D14 = 141,
162 D15 = 142,
163 DSPOutFlag20 = 143,
164 DSPOutFlag21 = 144,
165 DSPOutFlag22 = 145,
166 DSPOutFlag23 = 146,
167 F0 = 147,
168 F1 = 148,
169 F2 = 149,
170 F3 = 150,
171 F4 = 151,
172 F5 = 152,
173 F6 = 153,
174 F7 = 154,
175 F8 = 155,
176 F9 = 156,
177 F10 = 157,
178 F11 = 158,
179 F12 = 159,
180 F13 = 160,
181 F14 = 161,
182 F15 = 162,
183 F16 = 163,
184 F17 = 164,
185 F18 = 165,
186 F19 = 166,
187 F20 = 167,
188 F21 = 168,
189 F22 = 169,
190 F23 = 170,
191 F24 = 171,
192 F25 = 172,
193 F26 = 173,
194 F27 = 174,
195 F28 = 175,
196 F29 = 176,
197 F30 = 177,
198 F31 = 178,
199 FCC0 = 179,
200 FCC1 = 180,
201 FCC2 = 181,
202 FCC3 = 182,
203 FCC4 = 183,
204 FCC5 = 184,
205 FCC6 = 185,
206 FCC7 = 186,
207 FCR0 = 187,
208 FCR1 = 188,
209 FCR2 = 189,
210 FCR3 = 190,
211 FCR4 = 191,
212 FCR5 = 192,
213 FCR6 = 193,
214 FCR7 = 194,
215 FCR8 = 195,
216 FCR9 = 196,
217 FCR10 = 197,
218 FCR11 = 198,
219 FCR12 = 199,
220 FCR13 = 200,
221 FCR14 = 201,
222 FCR15 = 202,
223 FCR16 = 203,
224 FCR17 = 204,
225 FCR18 = 205,
226 FCR19 = 206,
227 FCR20 = 207,
228 FCR21 = 208,
229 FCR22 = 209,
230 FCR23 = 210,
231 FCR24 = 211,
232 FCR25 = 212,
233 FCR26 = 213,
234 FCR27 = 214,
235 FCR28 = 215,
236 FCR29 = 216,
237 FCR30 = 217,
238 FCR31 = 218,
239 FP_64 = 219,
240 F_HI0 = 220,
241 F_HI1 = 221,
242 F_HI2 = 222,
243 F_HI3 = 223,
244 F_HI4 = 224,
245 F_HI5 = 225,
246 F_HI6 = 226,
247 F_HI7 = 227,
248 F_HI8 = 228,
249 F_HI9 = 229,
250 F_HI10 = 230,
251 F_HI11 = 231,
252 F_HI12 = 232,
253 F_HI13 = 233,
254 F_HI14 = 234,
255 F_HI15 = 235,
256 F_HI16 = 236,
257 F_HI17 = 237,
258 F_HI18 = 238,
259 F_HI19 = 239,
260 F_HI20 = 240,
261 F_HI21 = 241,
262 F_HI22 = 242,
263 F_HI23 = 243,
264 F_HI24 = 244,
265 F_HI25 = 245,
266 F_HI26 = 246,
267 F_HI27 = 247,
268 F_HI28 = 248,
269 F_HI29 = 249,
270 F_HI30 = 250,
271 F_HI31 = 251,
272 GP_64 = 252,
273 HI0 = 253,
274 HI1 = 254,
275 HI2 = 255,
276 HI3 = 256,
277 HWR0 = 257,
278 HWR1 = 258,
279 HWR2 = 259,
280 HWR3 = 260,
281 HWR4 = 261,
282 HWR5 = 262,
283 HWR6 = 263,
284 HWR7 = 264,
285 HWR8 = 265,
286 HWR9 = 266,
287 HWR10 = 267,
288 HWR11 = 268,
289 HWR12 = 269,
290 HWR13 = 270,
291 HWR14 = 271,
292 HWR15 = 272,
293 HWR16 = 273,
294 HWR17 = 274,
295 HWR18 = 275,
296 HWR19 = 276,
297 HWR20 = 277,
298 HWR21 = 278,
299 HWR22 = 279,
300 HWR23 = 280,
301 HWR24 = 281,
302 HWR25 = 282,
303 HWR26 = 283,
304 HWR27 = 284,
305 HWR28 = 285,
306 HWR29 = 286,
307 HWR30 = 287,
308 HWR31 = 288,
309 K0 = 289,
310 K1 = 290,
311 LO0 = 291,
312 LO1 = 292,
313 LO2 = 293,
314 LO3 = 294,
315 MPL0 = 295,
316 MPL1 = 296,
317 MPL2 = 297,
318 MSA8 = 298,
319 MSA9 = 299,
320 MSA10 = 300,
321 MSA11 = 301,
322 MSA12 = 302,
323 MSA13 = 303,
324 MSA14 = 304,
325 MSA15 = 305,
326 MSA16 = 306,
327 MSA17 = 307,
328 MSA18 = 308,
329 MSA19 = 309,
330 MSA20 = 310,
331 MSA21 = 311,
332 MSA22 = 312,
333 MSA23 = 313,
334 MSA24 = 314,
335 MSA25 = 315,
336 MSA26 = 316,
337 MSA27 = 317,
338 MSA28 = 318,
339 MSA29 = 319,
340 MSA30 = 320,
341 MSA31 = 321,
342 P0 = 322,
343 P1 = 323,
344 P2 = 324,
345 RA_64 = 325,
346 S0 = 326,
347 S1 = 327,
348 S2 = 328,
349 S3 = 329,
350 S4 = 330,
351 S5 = 331,
352 S6 = 332,
353 S7 = 333,
354 SP_64 = 334,
355 T0 = 335,
356 T1 = 336,
357 T2 = 337,
358 T3 = 338,
359 T4 = 339,
360 T5 = 340,
361 T6 = 341,
362 T7 = 342,
363 T8 = 343,
364 T9 = 344,
365 V0 = 345,
366 V1 = 346,
367 W0 = 347,
368 W1 = 348,
369 W2 = 349,
370 W3 = 350,
371 W4 = 351,
372 W5 = 352,
373 W6 = 353,
374 W7 = 354,
375 W8 = 355,
376 W9 = 356,
377 W10 = 357,
378 W11 = 358,
379 W12 = 359,
380 W13 = 360,
381 W14 = 361,
382 W15 = 362,
383 W16 = 363,
384 W17 = 364,
385 W18 = 365,
386 W19 = 366,
387 W20 = 367,
388 W21 = 368,
389 W22 = 369,
390 W23 = 370,
391 W24 = 371,
392 W25 = 372,
393 W26 = 373,
394 W27 = 374,
395 W28 = 375,
396 W29 = 376,
397 W30 = 377,
398 W31 = 378,
399 ZERO_64 = 379,
400 A0_64 = 380,
401 A1_64 = 381,
402 A2_64 = 382,
403 A3_64 = 383,
404 AC0_64 = 384,
405 D0_64 = 385,
406 D1_64 = 386,
407 D2_64 = 387,
408 D3_64 = 388,
409 D4_64 = 389,
410 D5_64 = 390,
411 D6_64 = 391,
412 D7_64 = 392,
413 D8_64 = 393,
414 D9_64 = 394,
415 D10_64 = 395,
416 D11_64 = 396,
417 D12_64 = 397,
418 D13_64 = 398,
419 D14_64 = 399,
420 D15_64 = 400,
421 D16_64 = 401,
422 D17_64 = 402,
423 D18_64 = 403,
424 D19_64 = 404,
425 D20_64 = 405,
426 D21_64 = 406,
427 D22_64 = 407,
428 D23_64 = 408,
429 D24_64 = 409,
430 D25_64 = 410,
431 D26_64 = 411,
432 D27_64 = 412,
433 D28_64 = 413,
434 D29_64 = 414,
435 D30_64 = 415,
436 D31_64 = 416,
437 DSPOutFlag16_19 = 417,
438 HI0_64 = 418,
439 K0_64 = 419,
440 K1_64 = 420,
441 LO0_64 = 421,
442 S0_64 = 422,
443 S1_64 = 423,
444 S2_64 = 424,
445 S3_64 = 425,
446 S4_64 = 426,
447 S5_64 = 427,
448 S6_64 = 428,
449 S7_64 = 429,
450 T0_64 = 430,
451 T1_64 = 431,
452 T2_64 = 432,
453 T3_64 = 433,
454 T4_64 = 434,
455 T5_64 = 435,
456 T6_64 = 436,
457 T7_64 = 437,
458 T8_64 = 438,
459 T9_64 = 439,
460 V0_64 = 440,
461 V1_64 = 441,
462 NUM_TARGET_REGS // 442
463};
464} // end namespace Mips
465
466// Register classes
467
468namespace Mips {
469enum {
470 MSA128F16RegClassID = 0,
471 CCRRegClassID = 1,
472 COP0RegClassID = 2,
473 COP2RegClassID = 3,
474 COP3RegClassID = 4,
475 DSPRRegClassID = 5,
476 FGR32RegClassID = 6,
477 FGRCCRegClassID = 7,
478 GPR32RegClassID = 8,
479 HWRegsRegClassID = 9,
480 MSACtrlRegClassID = 10,
481 GPR32NONZERORegClassID = 11,
482 CPU16RegsPlusSPRegClassID = 12,
483 CPU16RegsRegClassID = 13,
484 FCCRegClassID = 14,
485 GPRMM16RegClassID = 15,
486 GPRMM16MovePRegClassID = 16,
487 GPRMM16ZeroRegClassID = 17,
488 CPU16Regs_and_GPRMM16ZeroRegClassID = 18,
489 GPR32NONZERO_and_GPRMM16MovePRegClassID = 19,
490 GPRMM16MovePPairSecondRegClassID = 20,
491 CPU16Regs_and_GPRMM16MovePRegClassID = 21,
492 GPRMM16MoveP_and_GPRMM16ZeroRegClassID = 22,
493 HI32DSPRegClassID = 23,
494 LO32DSPRegClassID = 24,
495 CPU16Regs_and_GPRMM16MovePPairSecondRegClassID = 25,
496 GPRMM16MovePPairFirstRegClassID = 26,
497 GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID = 27,
498 GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID = 28,
499 CPURARegRegClassID = 29,
500 CPUSPRegRegClassID = 30,
501 DSPCCRegClassID = 31,
502 GP32RegClassID = 32,
503 GPR32ZERORegClassID = 33,
504 HI32RegClassID = 34,
505 LO32RegClassID = 35,
506 SP32RegClassID = 36,
507 FGR64RegClassID = 37,
508 GPR64RegClassID = 38,
509 GPR64_with_sub_32_in_GPR32NONZERORegClassID = 39,
510 AFGR64RegClassID = 40,
511 GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID = 41,
512 GPR64_with_sub_32_in_CPU16RegsRegClassID = 42,
513 GPR64_with_sub_32_in_GPRMM16MovePRegClassID = 43,
514 GPR64_with_sub_32_in_GPRMM16ZeroRegClassID = 44,
515 GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID = 45,
516 GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID = 46,
517 GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClassID = 47,
518 ACC64DSPRegClassID = 48,
519 GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID = 49,
520 GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID = 50,
521 GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClassID = 51,
522 GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClassID = 52,
523 GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID = 53,
524 OCTEON_MPLRegClassID = 54,
525 OCTEON_PRegClassID = 55,
526 GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID = 56,
527 ACC64RegClassID = 57,
528 GP64RegClassID = 58,
529 GPR64_with_sub_32_in_CPURARegRegClassID = 59,
530 GPR64_with_sub_32_in_GPR32ZERORegClassID = 60,
531 HI64RegClassID = 61,
532 LO64RegClassID = 62,
533 SP64RegClassID = 63,
534 MSA128BRegClassID = 64,
535 MSA128DRegClassID = 65,
536 MSA128HRegClassID = 66,
537 MSA128WRegClassID = 67,
538 MSA128WEvensRegClassID = 68,
539 ACC128RegClassID = 69,
540
541};
542} // end namespace Mips
543
544
545// Subregister indices
546
547namespace Mips {
548enum : uint16_t {
549 NoSubRegister,
550 sub_32, // 1
551 sub_64, // 2
552 sub_dsp16_19, // 3
553 sub_dsp20, // 4
554 sub_dsp21, // 5
555 sub_dsp22, // 6
556 sub_dsp23, // 7
557 sub_hi, // 8
558 sub_lo, // 9
559 sub_hi_then_sub_32, // 10
560 sub_32_sub_hi_then_sub_32, // 11
561 NUM_TARGET_SUBREGS
562};
563} // end namespace Mips
564
565// Register pressure sets enum.
566namespace Mips {
567enum RegisterPressureSets {
568 DSPCC = 0,
569 GPR32ZERO = 1,
570 GPR64_with_sub_32_in_CPURAReg = 2,
571 HI32 = 3,
572 GPRMM16MovePPairFirst = 4,
573 CPU16Regs_and_GPRMM16MoveP = 5,
574 HI32DSP = 6,
575 LO32DSP = 7,
576 GPRMM16MovePPairSecond = 8,
577 GPRMM16MoveP = 9,
578 ACC64DSP = 10,
579 CPU16Regs = 11,
580 GPRMM16Zero_with_GPRMM16MovePPairSecond = 12,
581 CPU16Regs_with_GPRMM16MovePPairSecond = 13,
582 CPU16Regs_with_GPRMM16MoveP = 14,
583 DSPR = 15,
584 FGR32 = 16,
585 MSA128WEvens = 17,
586 FGR32_with_MSA128WEvens = 18,
587 MSA128F16 = 19,
588};
589} // end namespace Mips
590
591} // end namespace llvm
592
593#endif // GET_REGINFO_ENUM
594
595/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
596|* *|
597|* MC Register Information *|
598|* *|
599|* Automatically generated file, do not edit! *|
600|* *|
601\*===----------------------------------------------------------------------===*/
602
603
604#ifdef GET_REGINFO_MC_DESC
605#undef GET_REGINFO_MC_DESC
606
607namespace llvm {
608
609extern const int16_t MipsRegDiffLists[] = {
610 /* 0 */ -412, 0,
611 /* 2 */ -358, 0,
612 /* 4 */ -314, 0,
613 /* 6 */ -306, 0,
614 /* 8 */ -265, 0,
615 /* 10 */ -243, 0,
616 /* 12 */ 37, -130, 127, -165, -227, 0,
617 /* 18 */ -211, 0,
618 /* 20 */ -165, 0,
619 /* 22 */ -141, 0,
620 /* 24 */ -140, 0,
621 /* 26 */ -139, 0,
622 /* 28 */ -138, 0,
623 /* 30 */ -130, 0,
624 /* 32 */ -96, 0,
625 /* 34 */ -95, 0,
626 /* 36 */ 165, -38, 0,
627 /* 39 */ -20, 258, -38, 0,
628 /* 43 */ -21, 259, -38, 0,
629 /* 47 */ -22, 260, -38, 0,
630 /* 51 */ -23, 261, -38, 0,
631 /* 55 */ -24, 262, -38, 0,
632 /* 59 */ -25, 263, -38, 0,
633 /* 63 */ -26, 264, -38, 0,
634 /* 67 */ -27, 265, -38, 0,
635 /* 71 */ -28, 266, -38, 0,
636 /* 75 */ -29, 267, -38, 0,
637 /* 79 */ -30, 268, -38, 0,
638 /* 83 */ -31, 269, -38, 0,
639 /* 87 */ -32, 270, -38, 0,
640 /* 91 */ -33, 271, -38, 0,
641 /* 95 */ -34, 272, -38, 0,
642 /* 99 */ -35, 273, -38, 0,
643 /* 103 */ -36, 274, -38, 0,
644 /* 107 */ -265, 395, -37, 0,
645 /* 111 */ -227, 392, -34, 0,
646 /* 115 */ -29, 0,
647 /* 117 */ 412, -274, 1, 1, 1, 0,
648 /* 123 */ 1, 1, 1, 1, 0,
649 /* 128 */ 20, 1, 0,
650 /* 131 */ 21, 1, 0,
651 /* 134 */ 22, 1, 0,
652 /* 137 */ 23, 1, 0,
653 /* 140 */ 24, 1, 0,
654 /* 143 */ 25, 1, 0,
655 /* 146 */ 26, 1, 0,
656 /* 149 */ 27, 1, 0,
657 /* 152 */ 28, 1, 0,
658 /* 155 */ 29, 1, 0,
659 /* 158 */ 30, 1, 0,
660 /* 161 */ 31, 1, 0,
661 /* 164 */ 32, 1, 0,
662 /* 167 */ 33, 1, 0,
663 /* 170 */ 34, 1, 0,
664 /* 173 */ 35, 1, 0,
665 /* 176 */ 29, 0,
666 /* 178 */ 72, 0,
667 /* 180 */ 38, -238, 73, 0,
668 /* 184 */ 95, 0,
669 /* 186 */ 96, 0,
670 /* 188 */ 130, 0,
671 /* 190 */ 211, 0,
672 /* 192 */ 243, 0,
673 /* 194 */ 306, 0,
674 /* 196 */ 314, 0,
675 /* 198 */ 358, 0,
676};
677
678extern const LaneBitmask MipsLaneMaskLists[] = {
679 /* 0 */ LaneBitmask(0x0000000000000001),
680 /* 1 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020),
681 /* 6 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000040),
682 /* 8 */ LaneBitmask(0xFFFFFFFFFFFFFFFF),
683};
684
685extern const uint16_t MipsSubRegIdxLists[] = {
686 /* 0 */ 1,
687 /* 1 */ 3, 4, 5, 6, 7,
688 /* 6 */ 2, 9, 8,
689 /* 9 */ 9, 1, 8, 10, 11,
690};
691
692
693#ifdef __GNUC__
694#pragma GCC diagnostic push
695#pragma GCC diagnostic ignored "-Woverlength-strings"
696#endif
697extern const char MipsRegStrings[] = {
698 /* 0 */ "COP00\000"
699 /* 6 */ "COP010\000"
700 /* 13 */ "COP210\000"
701 /* 20 */ "COP310\000"
702 /* 27 */ "MSA10\000"
703 /* 33 */ "D10\000"
704 /* 37 */ "F10\000"
705 /* 41 */ "F_HI10\000"
706 /* 48 */ "FCR10\000"
707 /* 54 */ "HWR10\000"
708 /* 60 */ "W10\000"
709 /* 64 */ "COP020\000"
710 /* 71 */ "COP220\000"
711 /* 78 */ "COP320\000"
712 /* 85 */ "MSA20\000"
713 /* 91 */ "F20\000"
714 /* 95 */ "F_HI20\000"
715 /* 102 */ "COP20\000"
716 /* 108 */ "FCR20\000"
717 /* 114 */ "HWR20\000"
718 /* 120 */ "W20\000"
719 /* 124 */ "DSPOutFlag20\000"
720 /* 137 */ "COP030\000"
721 /* 144 */ "COP230\000"
722 /* 151 */ "COP330\000"
723 /* 158 */ "MSA30\000"
724 /* 164 */ "F30\000"
725 /* 168 */ "F_HI30\000"
726 /* 175 */ "COP30\000"
727 /* 181 */ "FCR30\000"
728 /* 187 */ "HWR30\000"
729 /* 193 */ "W30\000"
730 /* 197 */ "A0\000"
731 /* 200 */ "AC0\000"
732 /* 204 */ "FCC0\000"
733 /* 209 */ "D0\000"
734 /* 212 */ "F0\000"
735 /* 215 */ "F_HI0\000"
736 /* 221 */ "K0\000"
737 /* 224 */ "MPL0\000"
738 /* 229 */ "LO0\000"
739 /* 233 */ "P0\000"
740 /* 236 */ "FCR0\000"
741 /* 241 */ "HWR0\000"
742 /* 246 */ "S0\000"
743 /* 249 */ "T0\000"
744 /* 252 */ "V0\000"
745 /* 255 */ "W0\000"
746 /* 258 */ "COP01\000"
747 /* 264 */ "COP011\000"
748 /* 271 */ "COP211\000"
749 /* 278 */ "COP311\000"
750 /* 285 */ "MSA11\000"
751 /* 291 */ "D11\000"
752 /* 295 */ "F11\000"
753 /* 299 */ "F_HI11\000"
754 /* 306 */ "FCR11\000"
755 /* 312 */ "HWR11\000"
756 /* 318 */ "W11\000"
757 /* 322 */ "COP021\000"
758 /* 329 */ "COP221\000"
759 /* 336 */ "COP321\000"
760 /* 343 */ "MSA21\000"
761 /* 349 */ "F21\000"
762 /* 353 */ "F_HI21\000"
763 /* 360 */ "COP21\000"
764 /* 366 */ "FCR21\000"
765 /* 372 */ "HWR21\000"
766 /* 378 */ "W21\000"
767 /* 382 */ "DSPOutFlag21\000"
768 /* 395 */ "COP031\000"
769 /* 402 */ "COP231\000"
770 /* 409 */ "COP331\000"
771 /* 416 */ "MSA31\000"
772 /* 422 */ "F31\000"
773 /* 426 */ "F_HI31\000"
774 /* 433 */ "COP31\000"
775 /* 439 */ "FCR31\000"
776 /* 445 */ "HWR31\000"
777 /* 451 */ "W31\000"
778 /* 455 */ "A1\000"
779 /* 458 */ "AC1\000"
780 /* 462 */ "FCC1\000"
781 /* 467 */ "D1\000"
782 /* 470 */ "F1\000"
783 /* 473 */ "F_HI1\000"
784 /* 479 */ "K1\000"
785 /* 482 */ "MPL1\000"
786 /* 487 */ "LO1\000"
787 /* 491 */ "P1\000"
788 /* 494 */ "FCR1\000"
789 /* 499 */ "HWR1\000"
790 /* 504 */ "S1\000"
791 /* 507 */ "T1\000"
792 /* 510 */ "V1\000"
793 /* 513 */ "W1\000"
794 /* 516 */ "COP02\000"
795 /* 522 */ "COP012\000"
796 /* 529 */ "COP212\000"
797 /* 536 */ "COP312\000"
798 /* 543 */ "MSA12\000"
799 /* 549 */ "D12\000"
800 /* 553 */ "F12\000"
801 /* 557 */ "F_HI12\000"
802 /* 564 */ "FCR12\000"
803 /* 570 */ "HWR12\000"
804 /* 576 */ "W12\000"
805 /* 580 */ "COP022\000"
806 /* 587 */ "COP222\000"
807 /* 594 */ "COP322\000"
808 /* 601 */ "MSA22\000"
809 /* 607 */ "F22\000"
810 /* 611 */ "F_HI22\000"
811 /* 618 */ "COP22\000"
812 /* 624 */ "FCR22\000"
813 /* 630 */ "HWR22\000"
814 /* 636 */ "W22\000"
815 /* 640 */ "DSPOutFlag22\000"
816 /* 653 */ "COP32\000"
817 /* 659 */ "A2\000"
818 /* 662 */ "AC2\000"
819 /* 666 */ "FCC2\000"
820 /* 671 */ "D2\000"
821 /* 674 */ "F2\000"
822 /* 677 */ "F_HI2\000"
823 /* 683 */ "MPL2\000"
824 /* 688 */ "LO2\000"
825 /* 692 */ "P2\000"
826 /* 695 */ "FCR2\000"
827 /* 700 */ "HWR2\000"
828 /* 705 */ "S2\000"
829 /* 708 */ "T2\000"
830 /* 711 */ "W2\000"
831 /* 714 */ "COP03\000"
832 /* 720 */ "COP013\000"
833 /* 727 */ "COP213\000"
834 /* 734 */ "COP313\000"
835 /* 741 */ "MSA13\000"
836 /* 747 */ "D13\000"
837 /* 751 */ "F13\000"
838 /* 755 */ "F_HI13\000"
839 /* 762 */ "FCR13\000"
840 /* 768 */ "HWR13\000"
841 /* 774 */ "W13\000"
842 /* 778 */ "COP023\000"
843 /* 785 */ "COP223\000"
844 /* 792 */ "COP323\000"
845 /* 799 */ "MSA23\000"
846 /* 805 */ "F23\000"
847 /* 809 */ "F_HI23\000"
848 /* 816 */ "COP23\000"
849 /* 822 */ "FCR23\000"
850 /* 828 */ "HWR23\000"
851 /* 834 */ "W23\000"
852 /* 838 */ "DSPOutFlag23\000"
853 /* 851 */ "COP33\000"
854 /* 857 */ "A3\000"
855 /* 860 */ "AC3\000"
856 /* 864 */ "FCC3\000"
857 /* 869 */ "D3\000"
858 /* 872 */ "F3\000"
859 /* 875 */ "F_HI3\000"
860 /* 881 */ "LO3\000"
861 /* 885 */ "FCR3\000"
862 /* 890 */ "HWR3\000"
863 /* 895 */ "S3\000"
864 /* 898 */ "T3\000"
865 /* 901 */ "W3\000"
866 /* 904 */ "COP04\000"
867 /* 910 */ "COP014\000"
868 /* 917 */ "COP214\000"
869 /* 924 */ "COP314\000"
870 /* 931 */ "MSA14\000"
871 /* 937 */ "D14\000"
872 /* 941 */ "F14\000"
873 /* 945 */ "F_HI14\000"
874 /* 952 */ "FCR14\000"
875 /* 958 */ "HWR14\000"
876 /* 964 */ "W14\000"
877 /* 968 */ "COP024\000"
878 /* 975 */ "COP224\000"
879 /* 982 */ "COP324\000"
880 /* 989 */ "MSA24\000"
881 /* 995 */ "F24\000"
882 /* 999 */ "F_HI24\000"
883 /* 1006 */ "COP24\000"
884 /* 1012 */ "FCR24\000"
885 /* 1018 */ "HWR24\000"
886 /* 1024 */ "W24\000"
887 /* 1028 */ "COP34\000"
888 /* 1034 */ "D10_64\000"
889 /* 1041 */ "D20_64\000"
890 /* 1048 */ "D30_64\000"
891 /* 1055 */ "A0_64\000"
892 /* 1061 */ "AC0_64\000"
893 /* 1068 */ "D0_64\000"
894 /* 1074 */ "HI0_64\000"
895 /* 1081 */ "K0_64\000"
896 /* 1087 */ "LO0_64\000"
897 /* 1094 */ "S0_64\000"
898 /* 1100 */ "T0_64\000"
899 /* 1106 */ "V0_64\000"
900 /* 1112 */ "D11_64\000"
901 /* 1119 */ "D21_64\000"
902 /* 1126 */ "D31_64\000"
903 /* 1133 */ "A1_64\000"
904 /* 1139 */ "D1_64\000"
905 /* 1145 */ "K1_64\000"
906 /* 1151 */ "S1_64\000"
907 /* 1157 */ "T1_64\000"
908 /* 1163 */ "V1_64\000"
909 /* 1169 */ "D12_64\000"
910 /* 1176 */ "D22_64\000"
911 /* 1183 */ "A2_64\000"
912 /* 1189 */ "D2_64\000"
913 /* 1195 */ "S2_64\000"
914 /* 1201 */ "T2_64\000"
915 /* 1207 */ "D13_64\000"
916 /* 1214 */ "D23_64\000"
917 /* 1221 */ "A3_64\000"
918 /* 1227 */ "D3_64\000"
919 /* 1233 */ "S3_64\000"
920 /* 1239 */ "T3_64\000"
921 /* 1245 */ "D14_64\000"
922 /* 1252 */ "D24_64\000"
923 /* 1259 */ "D4_64\000"
924 /* 1265 */ "S4_64\000"
925 /* 1271 */ "T4_64\000"
926 /* 1277 */ "D15_64\000"
927 /* 1284 */ "D25_64\000"
928 /* 1291 */ "D5_64\000"
929 /* 1297 */ "S5_64\000"
930 /* 1303 */ "T5_64\000"
931 /* 1309 */ "D16_64\000"
932 /* 1316 */ "D26_64\000"
933 /* 1323 */ "D6_64\000"
934 /* 1329 */ "S6_64\000"
935 /* 1335 */ "T6_64\000"
936 /* 1341 */ "D17_64\000"
937 /* 1348 */ "D27_64\000"
938 /* 1355 */ "D7_64\000"
939 /* 1361 */ "S7_64\000"
940 /* 1367 */ "T7_64\000"
941 /* 1373 */ "D18_64\000"
942 /* 1380 */ "D28_64\000"
943 /* 1387 */ "D8_64\000"
944 /* 1393 */ "T8_64\000"
945 /* 1399 */ "D19_64\000"
946 /* 1406 */ "D29_64\000"
947 /* 1413 */ "D9_64\000"
948 /* 1419 */ "T9_64\000"
949 /* 1425 */ "RA_64\000"
950 /* 1431 */ "ZERO_64\000"
951 /* 1439 */ "FP_64\000"
952 /* 1445 */ "GP_64\000"
953 /* 1451 */ "SP_64\000"
954 /* 1457 */ "AT_64\000"
955 /* 1463 */ "FCC4\000"
956 /* 1468 */ "D4\000"
957 /* 1471 */ "F4\000"
958 /* 1474 */ "F_HI4\000"
959 /* 1480 */ "FCR4\000"
960 /* 1485 */ "HWR4\000"
961 /* 1490 */ "S4\000"
962 /* 1493 */ "T4\000"
963 /* 1496 */ "W4\000"
964 /* 1499 */ "COP05\000"
965 /* 1505 */ "COP015\000"
966 /* 1512 */ "COP215\000"
967 /* 1519 */ "COP315\000"
968 /* 1526 */ "MSA15\000"
969 /* 1532 */ "D15\000"
970 /* 1536 */ "F15\000"
971 /* 1540 */ "F_HI15\000"
972 /* 1547 */ "FCR15\000"
973 /* 1553 */ "HWR15\000"
974 /* 1559 */ "W15\000"
975 /* 1563 */ "COP025\000"
976 /* 1570 */ "COP225\000"
977 /* 1577 */ "COP325\000"
978 /* 1584 */ "MSA25\000"
979 /* 1590 */ "F25\000"
980 /* 1594 */ "F_HI25\000"
981 /* 1601 */ "COP25\000"
982 /* 1607 */ "FCR25\000"
983 /* 1613 */ "HWR25\000"
984 /* 1619 */ "W25\000"
985 /* 1623 */ "COP35\000"
986 /* 1629 */ "FCC5\000"
987 /* 1634 */ "D5\000"
988 /* 1637 */ "F5\000"
989 /* 1640 */ "F_HI5\000"
990 /* 1646 */ "FCR5\000"
991 /* 1651 */ "HWR5\000"
992 /* 1656 */ "S5\000"
993 /* 1659 */ "T5\000"
994 /* 1662 */ "W5\000"
995 /* 1665 */ "COP06\000"
996 /* 1671 */ "COP016\000"
997 /* 1678 */ "COP216\000"
998 /* 1685 */ "COP316\000"
999 /* 1692 */ "MSA16\000"
1000 /* 1698 */ "F16\000"
1001 /* 1702 */ "F_HI16\000"
1002 /* 1709 */ "FCR16\000"
1003 /* 1715 */ "HWR16\000"
1004 /* 1721 */ "W16\000"
1005 /* 1725 */ "COP026\000"
1006 /* 1732 */ "COP226\000"
1007 /* 1739 */ "COP326\000"
1008 /* 1746 */ "MSA26\000"
1009 /* 1752 */ "F26\000"
1010 /* 1756 */ "F_HI26\000"
1011 /* 1763 */ "COP26\000"
1012 /* 1769 */ "FCR26\000"
1013 /* 1775 */ "HWR26\000"
1014 /* 1781 */ "W26\000"
1015 /* 1785 */ "COP36\000"
1016 /* 1791 */ "FCC6\000"
1017 /* 1796 */ "D6\000"
1018 /* 1799 */ "F6\000"
1019 /* 1802 */ "F_HI6\000"
1020 /* 1808 */ "FCR6\000"
1021 /* 1813 */ "HWR6\000"
1022 /* 1818 */ "S6\000"
1023 /* 1821 */ "T6\000"
1024 /* 1824 */ "W6\000"
1025 /* 1827 */ "COP07\000"
1026 /* 1833 */ "COP017\000"
1027 /* 1840 */ "COP217\000"
1028 /* 1847 */ "COP317\000"
1029 /* 1854 */ "MSA17\000"
1030 /* 1860 */ "F17\000"
1031 /* 1864 */ "F_HI17\000"
1032 /* 1871 */ "FCR17\000"
1033 /* 1877 */ "HWR17\000"
1034 /* 1883 */ "W17\000"
1035 /* 1887 */ "COP027\000"
1036 /* 1894 */ "COP227\000"
1037 /* 1901 */ "COP327\000"
1038 /* 1908 */ "MSA27\000"
1039 /* 1914 */ "F27\000"
1040 /* 1918 */ "F_HI27\000"
1041 /* 1925 */ "COP27\000"
1042 /* 1931 */ "FCR27\000"
1043 /* 1937 */ "HWR27\000"
1044 /* 1943 */ "W27\000"
1045 /* 1947 */ "COP37\000"
1046 /* 1953 */ "FCC7\000"
1047 /* 1958 */ "D7\000"
1048 /* 1961 */ "F7\000"
1049 /* 1964 */ "F_HI7\000"
1050 /* 1970 */ "FCR7\000"
1051 /* 1975 */ "HWR7\000"
1052 /* 1980 */ "S7\000"
1053 /* 1983 */ "T7\000"
1054 /* 1986 */ "W7\000"
1055 /* 1989 */ "COP08\000"
1056 /* 1995 */ "COP018\000"
1057 /* 2002 */ "COP218\000"
1058 /* 2009 */ "COP318\000"
1059 /* 2016 */ "MSA18\000"
1060 /* 2022 */ "F18\000"
1061 /* 2026 */ "F_HI18\000"
1062 /* 2033 */ "FCR18\000"
1063 /* 2039 */ "HWR18\000"
1064 /* 2045 */ "W18\000"
1065 /* 2049 */ "COP028\000"
1066 /* 2056 */ "COP228\000"
1067 /* 2063 */ "COP328\000"
1068 /* 2070 */ "MSA28\000"
1069 /* 2076 */ "F28\000"
1070 /* 2080 */ "F_HI28\000"
1071 /* 2087 */ "COP28\000"
1072 /* 2093 */ "FCR28\000"
1073 /* 2099 */ "HWR28\000"
1074 /* 2105 */ "W28\000"
1075 /* 2109 */ "COP38\000"
1076 /* 2115 */ "MSA8\000"
1077 /* 2120 */ "D8\000"
1078 /* 2123 */ "F8\000"
1079 /* 2126 */ "F_HI8\000"
1080 /* 2132 */ "FCR8\000"
1081 /* 2137 */ "HWR8\000"
1082 /* 2142 */ "T8\000"
1083 /* 2145 */ "W8\000"
1084 /* 2148 */ "COP09\000"
1085 /* 2154 */ "COP019\000"
1086 /* 2161 */ "COP219\000"
1087 /* 2168 */ "COP319\000"
1088 /* 2175 */ "MSA19\000"
1089 /* 2181 */ "F19\000"
1090 /* 2185 */ "F_HI19\000"
1091 /* 2192 */ "FCR19\000"
1092 /* 2198 */ "HWR19\000"
1093 /* 2204 */ "W19\000"
1094 /* 2208 */ "DSPOutFlag16_19\000"
1095 /* 2224 */ "COP029\000"
1096 /* 2231 */ "COP229\000"
1097 /* 2238 */ "COP329\000"
1098 /* 2245 */ "MSA29\000"
1099 /* 2251 */ "F29\000"
1100 /* 2255 */ "F_HI29\000"
1101 /* 2262 */ "COP29\000"
1102 /* 2268 */ "FCR29\000"
1103 /* 2274 */ "HWR29\000"
1104 /* 2280 */ "W29\000"
1105 /* 2284 */ "COP39\000"
1106 /* 2290 */ "MSA9\000"
1107 /* 2295 */ "D9\000"
1108 /* 2298 */ "F9\000"
1109 /* 2301 */ "F_HI9\000"
1110 /* 2307 */ "FCR9\000"
1111 /* 2312 */ "HWR9\000"
1112 /* 2317 */ "T9\000"
1113 /* 2320 */ "W9\000"
1114 /* 2323 */ "RA\000"
1115 /* 2326 */ "PC\000"
1116 /* 2329 */ "DSPEFI\000"
1117 /* 2336 */ "ZERO\000"
1118 /* 2341 */ "FP\000"
1119 /* 2344 */ "GP\000"
1120 /* 2347 */ "SP\000"
1121 /* 2350 */ "MSAIR\000"
1122 /* 2356 */ "MSACSR\000"
1123 /* 2363 */ "AT\000"
1124 /* 2366 */ "DSPCCond\000"
1125 /* 2375 */ "MSASave\000"
1126 /* 2383 */ "DSPOutFlag\000"
1127 /* 2394 */ "MSAMap\000"
1128 /* 2401 */ "MSAUnmap\000"
1129 /* 2410 */ "DSPPos\000"
1130 /* 2417 */ "MSAAccess\000"
1131 /* 2427 */ "DSPSCount\000"
1132 /* 2437 */ "MSARequest\000"
1133 /* 2448 */ "MSAModify\000"
1134 /* 2458 */ "DSPCarry\000"
1135};
1136#ifdef __GNUC__
1137#pragma GCC diagnostic pop
1138#endif
1139
1140extern const MCRegisterDesc MipsRegDesc[] = { // Descriptors
1141 { 5, 0, 0, 0, 0, 0, 0, 0 },
1142 { 2363, 1, 176, 1, 4096, 8, 0, 0 },
1143 { 2366, 1, 1, 1, 4097, 8, 0, 0 },
1144 { 2458, 1, 1, 1, 4098, 8, 0, 0 },
1145 { 2329, 1, 1, 1, 4099, 8, 0, 0 },
1146 { 2383, 117, 1, 1, 503812, 1, 0, 0 },
1147 { 2410, 1, 1, 1, 4105, 8, 0, 0 },
1148 { 2427, 1, 1, 1, 4106, 8, 0, 0 },
1149 { 2341, 1, 190, 1, 4107, 8, 0, 0 },
1150 { 2344, 1, 192, 1, 4108, 8, 0, 0 },
1151 { 2417, 1, 1, 1, 4109, 8, 0, 0 },
1152 { 2356, 1, 1, 1, 4110, 8, 0, 0 },
1153 { 2350, 1, 1, 1, 4111, 8, 0, 0 },
1154 { 2394, 1, 1, 1, 4112, 8, 0, 0 },
1155 { 2448, 1, 1, 1, 4113, 8, 0, 0 },
1156 { 2437, 1, 1, 1, 4114, 8, 0, 0 },
1157 { 2375, 1, 1, 1, 4115, 8, 0, 0 },
1158 { 2401, 1, 1, 1, 4116, 8, 0, 0 },
1159 { 2326, 1, 1, 1, 4117, 8, 0, 0 },
1160 { 2323, 1, 194, 1, 4118, 8, 0, 0 },
1161 { 2347, 1, 196, 1, 4119, 8, 0, 0 },
1162 { 2336, 1, 198, 1, 4120, 8, 1, 0 },
1163 { 197, 1, 198, 1, 4121, 8, 0, 0 },
1164 { 455, 1, 198, 1, 4122, 8, 0, 0 },
1165 { 659, 1, 198, 1, 4123, 8, 0, 0 },
1166 { 857, 1, 198, 1, 4124, 8, 0, 0 },
1167 { 200, 68, 198, 7, 495645, 6, 0, 0 },
1168 { 458, 68, 1, 7, 495647, 6, 0, 0 },
1169 { 662, 68, 1, 7, 495649, 6, 0, 0 },
1170 { 860, 68, 1, 7, 495651, 6, 0, 0 },
1171 { 1457, 115, 1, 0, 4096, 0, 0, 0 },
1172 { 0, 1, 1, 1, 4133, 8, 0, 0 },
1173 { 258, 1, 1, 1, 4134, 8, 0, 0 },
1174 { 516, 1, 1, 1, 4135, 8, 0, 0 },
1175 { 714, 1, 1, 1, 4136, 8, 0, 0 },
1176 { 904, 1, 1, 1, 4137, 8, 0, 0 },
1177 { 1499, 1, 1, 1, 4138, 8, 0, 0 },
1178 { 1665, 1, 1, 1, 4139, 8, 0, 0 },
1179 { 1827, 1, 1, 1, 4140, 8, 0, 0 },
1180 { 1989, 1, 1, 1, 4141, 8, 0, 0 },
1181 { 2148, 1, 1, 1, 4142, 8, 0, 0 },
1182 { 102, 1, 1, 1, 4143, 8, 0, 0 },
1183 { 360, 1, 1, 1, 4144, 8, 0, 0 },
1184 { 618, 1, 1, 1, 4145, 8, 0, 0 },
1185 { 816, 1, 1, 1, 4146, 8, 0, 0 },
1186 { 1006, 1, 1, 1, 4147, 8, 0, 0 },
1187 { 1601, 1, 1, 1, 4148, 8, 0, 0 },
1188 { 1763, 1, 1, 1, 4149, 8, 0, 0 },
1189 { 1925, 1, 1, 1, 4150, 8, 0, 0 },
1190 { 2087, 1, 1, 1, 4151, 8, 0, 0 },
1191 { 2262, 1, 1, 1, 4152, 8, 0, 0 },
1192 { 175, 1, 1, 1, 4153, 8, 0, 0 },
1193 { 433, 1, 1, 1, 4154, 8, 0, 0 },
1194 { 653, 1, 1, 1, 4155, 8, 0, 0 },
1195 { 851, 1, 1, 1, 4156, 8, 0, 0 },
1196 { 1028, 1, 1, 1, 4157, 8, 0, 0 },
1197 { 1623, 1, 1, 1, 4158, 8, 0, 0 },
1198 { 1785, 1, 1, 1, 4159, 8, 0, 0 },
1199 { 1947, 1, 1, 1, 4160, 8, 0, 0 },
1200 { 2109, 1, 1, 1, 4161, 8, 0, 0 },
1201 { 2284, 1, 1, 1, 4162, 8, 0, 0 },
1202 { 6, 1, 1, 1, 4163, 8, 0, 0 },
1203 { 264, 1, 1, 1, 4164, 8, 0, 0 },
1204 { 522, 1, 1, 1, 4165, 8, 0, 0 },
1205 { 720, 1, 1, 1, 4166, 8, 0, 0 },
1206 { 910, 1, 1, 1, 4167, 8, 0, 0 },
1207 { 1505, 1, 1, 1, 4168, 8, 0, 0 },
1208 { 1671, 1, 1, 1, 4169, 8, 0, 0 },
1209 { 1833, 1, 1, 1, 4170, 8, 0, 0 },
1210 { 1995, 1, 1, 1, 4171, 8, 0, 0 },
1211 { 2154, 1, 1, 1, 4172, 8, 0, 0 },
1212 { 64, 1, 1, 1, 4173, 8, 0, 0 },
1213 { 322, 1, 1, 1, 4174, 8, 0, 0 },
1214 { 580, 1, 1, 1, 4175, 8, 0, 0 },
1215 { 778, 1, 1, 1, 4176, 8, 0, 0 },
1216 { 968, 1, 1, 1, 4177, 8, 0, 0 },
1217 { 1563, 1, 1, 1, 4178, 8, 0, 0 },
1218 { 1725, 1, 1, 1, 4179, 8, 0, 0 },
1219 { 1887, 1, 1, 1, 4180, 8, 0, 0 },
1220 { 2049, 1, 1, 1, 4181, 8, 0, 0 },
1221 { 2224, 1, 1, 1, 4182, 8, 0, 0 },
1222 { 137, 1, 1, 1, 4183, 8, 0, 0 },
1223 { 395, 1, 1, 1, 4184, 8, 0, 0 },
1224 { 13, 1, 1, 1, 4185, 8, 0, 0 },
1225 { 271, 1, 1, 1, 4186, 8, 0, 0 },
1226 { 529, 1, 1, 1, 4187, 8, 0, 0 },
1227 { 727, 1, 1, 1, 4188, 8, 0, 0 },
1228 { 917, 1, 1, 1, 4189, 8, 0, 0 },
1229 { 1512, 1, 1, 1, 4190, 8, 0, 0 },
1230 { 1678, 1, 1, 1, 4191, 8, 0, 0 },
1231 { 1840, 1, 1, 1, 4192, 8, 0, 0 },
1232 { 2002, 1, 1, 1, 4193, 8, 0, 0 },
1233 { 2161, 1, 1, 1, 4194, 8, 0, 0 },
1234 { 71, 1, 1, 1, 4195, 8, 0, 0 },
1235 { 329, 1, 1, 1, 4196, 8, 0, 0 },
1236 { 587, 1, 1, 1, 4197, 8, 0, 0 },
1237 { 785, 1, 1, 1, 4198, 8, 0, 0 },
1238 { 975, 1, 1, 1, 4199, 8, 0, 0 },
1239 { 1570, 1, 1, 1, 4200, 8, 0, 0 },
1240 { 1732, 1, 1, 1, 4201, 8, 0, 0 },
1241 { 1894, 1, 1, 1, 4202, 8, 0, 0 },
1242 { 2056, 1, 1, 1, 4203, 8, 0, 0 },
1243 { 2231, 1, 1, 1, 4204, 8, 0, 0 },
1244 { 144, 1, 1, 1, 4205, 8, 0, 0 },
1245 { 402, 1, 1, 1, 4206, 8, 0, 0 },
1246 { 20, 1, 1, 1, 4207, 8, 0, 0 },
1247 { 278, 1, 1, 1, 4208, 8, 0, 0 },
1248 { 536, 1, 1, 1, 4209, 8, 0, 0 },
1249 { 734, 1, 1, 1, 4210, 8, 0, 0 },
1250 { 924, 1, 1, 1, 4211, 8, 0, 0 },
1251 { 1519, 1, 1, 1, 4212, 8, 0, 0 },
1252 { 1685, 1, 1, 1, 4213, 8, 0, 0 },
1253 { 1847, 1, 1, 1, 4214, 8, 0, 0 },
1254 { 2009, 1, 1, 1, 4215, 8, 0, 0 },
1255 { 2168, 1, 1, 1, 4216, 8, 0, 0 },
1256 { 78, 1, 1, 1, 4217, 8, 0, 0 },
1257 { 336, 1, 1, 1, 4218, 8, 0, 0 },
1258 { 594, 1, 1, 1, 4219, 8, 0, 0 },
1259 { 792, 1, 1, 1, 4220, 8, 0, 0 },
1260 { 982, 1, 1, 1, 4221, 8, 0, 0 },
1261 { 1577, 1, 1, 1, 4222, 8, 0, 0 },
1262 { 1739, 1, 1, 1, 4223, 8, 0, 0 },
1263 { 1901, 1, 1, 1, 4224, 8, 0, 0 },
1264 { 2063, 1, 1, 1, 4225, 8, 0, 0 },
1265 { 2238, 1, 1, 1, 4226, 8, 0, 0 },
1266 { 151, 1, 1, 1, 4227, 8, 0, 0 },
1267 { 409, 1, 1, 1, 4228, 8, 0, 0 },
1268 { 209, 128, 1, 7, 495749, 6, 0, 0 },
1269 { 467, 131, 1, 7, 495751, 6, 0, 0 },
1270 { 671, 134, 1, 7, 495753, 6, 0, 0 },
1271 { 869, 137, 1, 7, 495755, 6, 0, 0 },
1272 { 1468, 140, 1, 7, 495757, 6, 0, 0 },
1273 { 1634, 143, 1, 7, 495759, 6, 0, 0 },
1274 { 1796, 146, 1, 7, 495761, 6, 0, 0 },
1275 { 1958, 149, 1, 7, 495763, 6, 0, 0 },
1276 { 2120, 152, 1, 7, 495765, 6, 0, 0 },
1277 { 2295, 155, 1, 7, 495767, 6, 0, 0 },
1278 { 33, 158, 1, 7, 495769, 6, 0, 0 },
1279 { 291, 161, 1, 7, 495771, 6, 0, 0 },
1280 { 549, 164, 1, 7, 495773, 6, 0, 0 },
1281 { 747, 167, 1, 7, 495775, 6, 0, 0 },
1282 { 937, 170, 1, 7, 495777, 6, 0, 0 },
1283 { 1532, 173, 1, 7, 495779, 6, 0, 0 },
1284 { 124, 1, 28, 1, 4101, 8, 0, 0 },
1285 { 382, 1, 26, 1, 4102, 8, 0, 0 },
1286 { 640, 1, 24, 1, 4103, 8, 0, 0 },
1287 { 838, 1, 22, 1, 4104, 8, 0, 0 },
1288 { 212, 1, 39, 1, 4229, 8, 0, 0 },
1289 { 470, 1, 43, 1, 4230, 8, 0, 0 },
1290 { 674, 1, 43, 1, 4231, 8, 0, 0 },
1291 { 872, 1, 47, 1, 4232, 8, 0, 0 },
1292 { 1471, 1, 47, 1, 4233, 8, 0, 0 },
1293 { 1637, 1, 51, 1, 4234, 8, 0, 0 },
1294 { 1799, 1, 51, 1, 4235, 8, 0, 0 },
1295 { 1961, 1, 55, 1, 4236, 8, 0, 0 },
1296 { 2123, 1, 55, 1, 4237, 8, 0, 0 },
1297 { 2298, 1, 59, 1, 4238, 8, 0, 0 },
1298 { 37, 1, 59, 1, 4239, 8, 0, 0 },
1299 { 295, 1, 63, 1, 4240, 8, 0, 0 },
1300 { 553, 1, 63, 1, 4241, 8, 0, 0 },
1301 { 751, 1, 67, 1, 4242, 8, 0, 0 },
1302 { 941, 1, 67, 1, 4243, 8, 0, 0 },
1303 { 1536, 1, 71, 1, 4244, 8, 0, 0 },
1304 { 1698, 1, 71, 1, 4245, 8, 0, 0 },
1305 { 1860, 1, 75, 1, 4246, 8, 0, 0 },
1306 { 2022, 1, 75, 1, 4247, 8, 0, 0 },
1307 { 2181, 1, 79, 1, 4248, 8, 0, 0 },
1308 { 91, 1, 79, 1, 4249, 8, 0, 0 },
1309 { 349, 1, 83, 1, 4250, 8, 0, 0 },
1310 { 607, 1, 83, 1, 4251, 8, 0, 0 },
1311 { 805, 1, 87, 1, 4252, 8, 0, 0 },
1312 { 995, 1, 87, 1, 4253, 8, 0, 0 },
1313 { 1590, 1, 91, 1, 4254, 8, 0, 0 },
1314 { 1752, 1, 91, 1, 4255, 8, 0, 0 },
1315 { 1914, 1, 95, 1, 4256, 8, 0, 0 },
1316 { 2076, 1, 95, 1, 4257, 8, 0, 0 },
1317 { 2251, 1, 99, 1, 4258, 8, 0, 0 },
1318 { 164, 1, 99, 1, 4259, 8, 0, 0 },
1319 { 422, 1, 103, 1, 4260, 8, 0, 0 },
1320 { 204, 1, 1, 1, 4261, 8, 0, 0 },
1321 { 462, 1, 1, 1, 4262, 8, 0, 0 },
1322 { 666, 1, 1, 1, 4263, 8, 0, 0 },
1323 { 864, 1, 1, 1, 4264, 8, 0, 0 },
1324 { 1463, 1, 1, 1, 4265, 8, 0, 0 },
1325 { 1629, 1, 1, 1, 4266, 8, 0, 0 },
1326 { 1791, 1, 1, 1, 4267, 8, 0, 0 },
1327 { 1953, 1, 1, 1, 4268, 8, 0, 0 },
1328 { 236, 1, 1, 1, 4269, 8, 0, 0 },
1329 { 494, 1, 1, 1, 4270, 8, 0, 0 },
1330 { 695, 1, 1, 1, 4271, 8, 0, 0 },
1331 { 885, 1, 1, 1, 4272, 8, 0, 0 },
1332 { 1480, 1, 1, 1, 4273, 8, 0, 0 },
1333 { 1646, 1, 1, 1, 4274, 8, 0, 0 },
1334 { 1808, 1, 1, 1, 4275, 8, 0, 0 },
1335 { 1970, 1, 1, 1, 4276, 8, 0, 0 },
1336 { 2132, 1, 1, 1, 4277, 8, 0, 0 },
1337 { 2307, 1, 1, 1, 4278, 8, 0, 0 },
1338 { 48, 1, 1, 1, 4279, 8, 0, 0 },
1339 { 306, 1, 1, 1, 4280, 8, 0, 0 },
1340 { 564, 1, 1, 1, 4281, 8, 0, 0 },
1341 { 762, 1, 1, 1, 4282, 8, 0, 0 },
1342 { 952, 1, 1, 1, 4283, 8, 0, 0 },
1343 { 1547, 1, 1, 1, 4284, 8, 0, 0 },
1344 { 1709, 1, 1, 1, 4285, 8, 0, 0 },
1345 { 1871, 1, 1, 1, 4286, 8, 0, 0 },
1346 { 2033, 1, 1, 1, 4287, 8, 0, 0 },
1347 { 2192, 1, 1, 1, 4288, 8, 0, 0 },
1348 { 108, 1, 1, 1, 4289, 8, 0, 0 },
1349 { 366, 1, 1, 1, 4290, 8, 0, 0 },
1350 { 624, 1, 1, 1, 4291, 8, 0, 0 },
1351 { 822, 1, 1, 1, 4292, 8, 0, 0 },
1352 { 1012, 1, 1, 1, 4293, 8, 0, 0 },
1353 { 1607, 1, 1, 1, 4294, 8, 0, 0 },
1354 { 1769, 1, 1, 1, 4295, 8, 0, 0 },
1355 { 1931, 1, 1, 1, 4296, 8, 0, 0 },
1356 { 2093, 1, 1, 1, 4297, 8, 0, 0 },
1357 { 2268, 1, 1, 1, 4298, 8, 0, 0 },
1358 { 181, 1, 1, 1, 4299, 8, 0, 0 },
1359 { 439, 1, 1, 1, 4300, 8, 0, 0 },
1360 { 1439, 18, 1, 0, 4107, 0, 0, 0 },
1361 { 215, 1, 36, 1, 4301, 8, 0, 0 },
1362 { 473, 1, 36, 1, 4302, 8, 0, 0 },
1363 { 677, 1, 36, 1, 4303, 8, 0, 0 },
1364 { 875, 1, 36, 1, 4304, 8, 0, 0 },
1365 { 1474, 1, 36, 1, 4305, 8, 0, 0 },
1366 { 1640, 1, 36, 1, 4306, 8, 0, 0 },
1367 { 1802, 1, 36, 1, 4307, 8, 0, 0 },
1368 { 1964, 1, 36, 1, 4308, 8, 0, 0 },
1369 { 2126, 1, 36, 1, 4309, 8, 0, 0 },
1370 { 2301, 1, 36, 1, 4310, 8, 0, 0 },
1371 { 41, 1, 36, 1, 4311, 8, 0, 0 },
1372 { 299, 1, 36, 1, 4312, 8, 0, 0 },
1373 { 557, 1, 36, 1, 4313, 8, 0, 0 },
1374 { 755, 1, 36, 1, 4314, 8, 0, 0 },
1375 { 945, 1, 36, 1, 4315, 8, 0, 0 },
1376 { 1540, 1, 36, 1, 4316, 8, 0, 0 },
1377 { 1702, 1, 36, 1, 4317, 8, 0, 0 },
1378 { 1864, 1, 36, 1, 4318, 8, 0, 0 },
1379 { 2026, 1, 36, 1, 4319, 8, 0, 0 },
1380 { 2185, 1, 36, 1, 4320, 8, 0, 0 },
1381 { 95, 1, 36, 1, 4321, 8, 0, 0 },
1382 { 353, 1, 36, 1, 4322, 8, 0, 0 },
1383 { 611, 1, 36, 1, 4323, 8, 0, 0 },
1384 { 809, 1, 36, 1, 4324, 8, 0, 0 },
1385 { 999, 1, 36, 1, 4325, 8, 0, 0 },
1386 { 1594, 1, 36, 1, 4326, 8, 0, 0 },
1387 { 1756, 1, 36, 1, 4327, 8, 0, 0 },
1388 { 1918, 1, 36, 1, 4328, 8, 0, 0 },
1389 { 2080, 1, 36, 1, 4329, 8, 0, 0 },
1390 { 2255, 1, 36, 1, 4330, 8, 0, 0 },
1391 { 168, 1, 36, 1, 4331, 8, 0, 0 },
1392 { 426, 1, 36, 1, 4332, 8, 0, 0 },
1393 { 1445, 10, 1, 0, 4108, 0, 0, 0 },
1394 { 217, 1, 111, 1, 4126, 8, 0, 0 },
1395 { 475, 1, 16, 1, 4128, 8, 0, 0 },
1396 { 679, 1, 16, 1, 4130, 8, 0, 0 },
1397 { 877, 1, 16, 1, 4132, 8, 0, 0 },
1398 { 241, 1, 1, 1, 4333, 8, 0, 0 },
1399 { 499, 1, 1, 1, 4334, 8, 0, 0 },
1400 { 700, 1, 1, 1, 4335, 8, 0, 0 },
1401 { 890, 1, 1, 1, 4336, 8, 0, 0 },
1402 { 1485, 1, 1, 1, 4337, 8, 0, 0 },
1403 { 1651, 1, 1, 1, 4338, 8, 0, 0 },
1404 { 1813, 1, 1, 1, 4339, 8, 0, 0 },
1405 { 1975, 1, 1, 1, 4340, 8, 0, 0 },
1406 { 2137, 1, 1, 1, 4341, 8, 0, 0 },
1407 { 2312, 1, 1, 1, 4342, 8, 0, 0 },
1408 { 54, 1, 1, 1, 4343, 8, 0, 0 },
1409 { 312, 1, 1, 1, 4344, 8, 0, 0 },
1410 { 570, 1, 1, 1, 4345, 8, 0, 0 },
1411 { 768, 1, 1, 1, 4346, 8, 0, 0 },
1412 { 958, 1, 1, 1, 4347, 8, 0, 0 },
1413 { 1553, 1, 1, 1, 4348, 8, 0, 0 },
1414 { 1715, 1, 1, 1, 4349, 8, 0, 0 },
1415 { 1877, 1, 1, 1, 4350, 8, 0, 0 },
1416 { 2039, 1, 1, 1, 4351, 8, 0, 0 },
1417 { 2198, 1, 1, 1, 4352, 8, 0, 0 },
1418 { 114, 1, 1, 1, 4353, 8, 0, 0 },
1419 { 372, 1, 1, 1, 4354, 8, 0, 0 },
1420 { 630, 1, 1, 1, 4355, 8, 0, 0 },
1421 { 828, 1, 1, 1, 4356, 8, 0, 0 },
1422 { 1018, 1, 1, 1, 4357, 8, 0, 0 },
1423 { 1613, 1, 1, 1, 4358, 8, 0, 0 },
1424 { 1775, 1, 1, 1, 4359, 8, 0, 0 },
1425 { 1937, 1, 1, 1, 4360, 8, 0, 0 },
1426 { 2099, 1, 1, 1, 4361, 8, 0, 0 },
1427 { 2274, 1, 1, 1, 4362, 8, 0, 0 },
1428 { 187, 1, 1, 1, 4363, 8, 0, 0 },
1429 { 445, 1, 1, 1, 4364, 8, 0, 0 },
1430 { 221, 1, 188, 1, 4365, 8, 0, 0 },
1431 { 479, 1, 188, 1, 4366, 8, 0, 0 },
1432 { 229, 1, 107, 1, 4125, 8, 0, 0 },
1433 { 487, 1, 8, 1, 4127, 8, 0, 0 },
1434 { 688, 1, 8, 1, 4129, 8, 0, 0 },
1435 { 881, 1, 8, 1, 4131, 8, 0, 0 },
1436 { 224, 1, 1, 1, 4367, 8, 0, 0 },
1437 { 482, 1, 1, 1, 4368, 8, 0, 0 },
1438 { 683, 1, 1, 1, 4369, 8, 0, 0 },
1439 { 2115, 1, 1, 1, 4370, 8, 0, 0 },
1440 { 2290, 1, 1, 1, 4371, 8, 0, 0 },
1441 { 27, 1, 1, 1, 4372, 8, 0, 0 },
1442 { 285, 1, 1, 1, 4373, 8, 0, 0 },
1443 { 543, 1, 1, 1, 4374, 8, 0, 0 },
1444 { 741, 1, 1, 1, 4375, 8, 0, 0 },
1445 { 931, 1, 1, 1, 4376, 8, 0, 0 },
1446 { 1526, 1, 1, 1, 4377, 8, 0, 0 },
1447 { 1692, 1, 1, 1, 4378, 8, 0, 0 },
1448 { 1854, 1, 1, 1, 4379, 8, 0, 0 },
1449 { 2016, 1, 1, 1, 4380, 8, 0, 0 },
1450 { 2175, 1, 1, 1, 4381, 8, 0, 0 },
1451 { 85, 1, 1, 1, 4382, 8, 0, 0 },
1452 { 343, 1, 1, 1, 4383, 8, 0, 0 },
1453 { 601, 1, 1, 1, 4384, 8, 0, 0 },
1454 { 799, 1, 1, 1, 4385, 8, 0, 0 },
1455 { 989, 1, 1, 1, 4386, 8, 0, 0 },
1456 { 1584, 1, 1, 1, 4387, 8, 0, 0 },
1457 { 1746, 1, 1, 1, 4388, 8, 0, 0 },
1458 { 1908, 1, 1, 1, 4389, 8, 0, 0 },
1459 { 2070, 1, 1, 1, 4390, 8, 0, 0 },
1460 { 2245, 1, 1, 1, 4391, 8, 0, 0 },
1461 { 158, 1, 1, 1, 4392, 8, 0, 0 },
1462 { 416, 1, 1, 1, 4393, 8, 0, 0 },
1463 { 233, 1, 1, 1, 4394, 8, 0, 0 },
1464 { 491, 1, 1, 1, 4395, 8, 0, 0 },
1465 { 692, 1, 1, 1, 4396, 8, 0, 0 },
1466 { 1425, 6, 1, 0, 4118, 0, 0, 0 },
1467 { 246, 1, 186, 1, 4397, 8, 0, 0 },
1468 { 504, 1, 186, 1, 4398, 8, 0, 0 },
1469 { 705, 1, 186, 1, 4399, 8, 0, 0 },
1470 { 895, 1, 186, 1, 4400, 8, 0, 0 },
1471 { 1490, 1, 186, 1, 4401, 8, 0, 0 },
1472 { 1656, 1, 186, 1, 4402, 8, 0, 0 },
1473 { 1818, 1, 186, 1, 4403, 8, 0, 0 },
1474 { 1980, 1, 186, 1, 4404, 8, 0, 0 },
1475 { 1451, 4, 1, 0, 4119, 0, 0, 0 },
1476 { 249, 1, 184, 1, 4405, 8, 0, 0 },
1477 { 507, 1, 184, 1, 4406, 8, 0, 0 },
1478 { 708, 1, 184, 1, 4407, 8, 0, 0 },
1479 { 898, 1, 184, 1, 4408, 8, 0, 0 },
1480 { 1493, 1, 184, 1, 4409, 8, 0, 0 },
1481 { 1659, 1, 184, 1, 4410, 8, 0, 0 },
1482 { 1821, 1, 184, 1, 4411, 8, 0, 0 },
1483 { 1983, 1, 184, 1, 4412, 8, 0, 0 },
1484 { 2142, 1, 184, 1, 4413, 8, 0, 0 },
1485 { 2317, 1, 184, 1, 4414, 8, 0, 0 },
1486 { 252, 1, 184, 1, 4415, 8, 0, 0 },
1487 { 510, 1, 184, 1, 4416, 8, 0, 0 },
1488 { 255, 180, 1, 6, 729221, 6, 0, 0 },
1489 { 513, 180, 1, 6, 729222, 6, 0, 0 },
1490 { 711, 180, 1, 6, 729223, 6, 0, 0 },
1491 { 901, 180, 1, 6, 729224, 6, 0, 0 },
1492 { 1496, 180, 1, 6, 729225, 6, 0, 0 },
1493 { 1662, 180, 1, 6, 729226, 6, 0, 0 },
1494 { 1824, 180, 1, 6, 729227, 6, 0, 0 },
1495 { 1986, 180, 1, 6, 729228, 6, 0, 0 },
1496 { 2145, 180, 1, 6, 729229, 6, 0, 0 },
1497 { 2320, 180, 1, 6, 729230, 6, 0, 0 },
1498 { 60, 180, 1, 6, 729231, 6, 0, 0 },
1499 { 318, 180, 1, 6, 729232, 6, 0, 0 },
1500 { 576, 180, 1, 6, 729233, 6, 0, 0 },
1501 { 774, 180, 1, 6, 729234, 6, 0, 0 },
1502 { 964, 180, 1, 6, 729235, 6, 0, 0 },
1503 { 1559, 180, 1, 6, 729236, 6, 0, 0 },
1504 { 1721, 180, 1, 6, 729237, 6, 0, 0 },
1505 { 1883, 180, 1, 6, 729238, 6, 0, 0 },
1506 { 2045, 180, 1, 6, 729239, 6, 0, 0 },
1507 { 2204, 180, 1, 6, 729240, 6, 0, 0 },
1508 { 120, 180, 1, 6, 729241, 6, 0, 0 },
1509 { 378, 180, 1, 6, 729242, 6, 0, 0 },
1510 { 636, 180, 1, 6, 729243, 6, 0, 0 },
1511 { 834, 180, 1, 6, 729244, 6, 0, 0 },
1512 { 1024, 180, 1, 6, 729245, 6, 0, 0 },
1513 { 1619, 180, 1, 6, 729246, 6, 0, 0 },
1514 { 1781, 180, 1, 6, 729247, 6, 0, 0 },
1515 { 1943, 180, 1, 6, 729248, 6, 0, 0 },
1516 { 2105, 180, 1, 6, 729249, 6, 0, 0 },
1517 { 2280, 180, 1, 6, 729250, 6, 0, 0 },
1518 { 193, 180, 1, 6, 729251, 6, 0, 0 },
1519 { 451, 180, 1, 6, 729252, 6, 0, 0 },
1520 { 1431, 2, 1, 0, 4120, 0, 1, 0 },
1521 { 1055, 2, 1, 0, 4121, 0, 0, 0 },
1522 { 1133, 2, 1, 0, 4122, 0, 0, 0 },
1523 { 1183, 2, 1, 0, 4123, 0, 0, 0 },
1524 { 1221, 2, 1, 0, 4124, 0, 0, 0 },
1525 { 1061, 12, 1, 9, 495645, 6, 0, 0 },
1526 { 1068, 181, 37, 7, 729221, 6, 0, 0 },
1527 { 1139, 181, 37, 7, 729222, 6, 0, 0 },
1528 { 1189, 181, 37, 7, 729223, 6, 0, 0 },
1529 { 1227, 181, 37, 7, 729224, 6, 0, 0 },
1530 { 1259, 181, 37, 7, 729225, 6, 0, 0 },
1531 { 1291, 181, 37, 7, 729226, 6, 0, 0 },
1532 { 1323, 181, 37, 7, 729227, 6, 0, 0 },
1533 { 1355, 181, 37, 7, 729228, 6, 0, 0 },
1534 { 1387, 181, 37, 7, 729229, 6, 0, 0 },
1535 { 1413, 181, 37, 7, 729230, 6, 0, 0 },
1536 { 1034, 181, 37, 7, 729231, 6, 0, 0 },
1537 { 1112, 181, 37, 7, 729232, 6, 0, 0 },
1538 { 1169, 181, 37, 7, 729233, 6, 0, 0 },
1539 { 1207, 181, 37, 7, 729234, 6, 0, 0 },
1540 { 1245, 181, 37, 7, 729235, 6, 0, 0 },
1541 { 1277, 181, 37, 7, 729236, 6, 0, 0 },
1542 { 1309, 181, 37, 7, 729237, 6, 0, 0 },
1543 { 1341, 181, 37, 7, 729238, 6, 0, 0 },
1544 { 1373, 181, 37, 7, 729239, 6, 0, 0 },
1545 { 1399, 181, 37, 7, 729240, 6, 0, 0 },
1546 { 1041, 181, 37, 7, 729241, 6, 0, 0 },
1547 { 1119, 181, 37, 7, 729242, 6, 0, 0 },
1548 { 1176, 181, 37, 7, 729243, 6, 0, 0 },
1549 { 1214, 181, 37, 7, 729244, 6, 0, 0 },
1550 { 1252, 181, 37, 7, 729245, 6, 0, 0 },
1551 { 1284, 181, 37, 7, 729246, 6, 0, 0 },
1552 { 1316, 181, 37, 7, 729247, 6, 0, 0 },
1553 { 1348, 181, 37, 7, 729248, 6, 0, 0 },
1554 { 1380, 181, 37, 7, 729249, 6, 0, 0 },
1555 { 1406, 181, 37, 7, 729250, 6, 0, 0 },
1556 { 1048, 181, 37, 7, 729251, 6, 0, 0 },
1557 { 1126, 181, 37, 7, 729252, 6, 0, 0 },
1558 { 2208, 1, 0, 1, 4100, 8, 0, 0 },
1559 { 1074, 20, 113, 0, 4126, 0, 0, 0 },
1560 { 1081, 30, 1, 0, 4365, 0, 0, 0 },
1561 { 1145, 30, 1, 0, 4366, 0, 0, 0 },
1562 { 1087, 30, 109, 0, 4125, 0, 0, 0 },
1563 { 1094, 32, 1, 0, 4397, 0, 0, 0 },
1564 { 1151, 32, 1, 0, 4398, 0, 0, 0 },
1565 { 1195, 32, 1, 0, 4399, 0, 0, 0 },
1566 { 1233, 32, 1, 0, 4400, 0, 0, 0 },
1567 { 1265, 32, 1, 0, 4401, 0, 0, 0 },
1568 { 1297, 32, 1, 0, 4402, 0, 0, 0 },
1569 { 1329, 32, 1, 0, 4403, 0, 0, 0 },
1570 { 1361, 32, 1, 0, 4404, 0, 0, 0 },
1571 { 1100, 34, 1, 0, 4405, 0, 0, 0 },
1572 { 1157, 34, 1, 0, 4406, 0, 0, 0 },
1573 { 1201, 34, 1, 0, 4407, 0, 0, 0 },
1574 { 1239, 34, 1, 0, 4408, 0, 0, 0 },
1575 { 1271, 34, 1, 0, 4409, 0, 0, 0 },
1576 { 1303, 34, 1, 0, 4410, 0, 0, 0 },
1577 { 1335, 34, 1, 0, 4411, 0, 0, 0 },
1578 { 1367, 34, 1, 0, 4412, 0, 0, 0 },
1579 { 1393, 34, 1, 0, 4413, 0, 0, 0 },
1580 { 1419, 34, 1, 0, 4414, 0, 0, 0 },
1581 { 1106, 34, 1, 0, 4415, 0, 0, 0 },
1582 { 1163, 34, 1, 0, 4416, 0, 0, 0 },
1583};
1584
1585extern const MCPhysReg MipsRegUnitRoots[][2] = {
1586 { Mips::AT },
1587 { Mips::DSPCCond },
1588 { Mips::DSPCarry },
1589 { Mips::DSPEFI },
1590 { Mips::DSPOutFlag16_19 },
1591 { Mips::DSPOutFlag20 },
1592 { Mips::DSPOutFlag21 },
1593 { Mips::DSPOutFlag22 },
1594 { Mips::DSPOutFlag23 },
1595 { Mips::DSPPos },
1596 { Mips::DSPSCount },
1597 { Mips::FP },
1598 { Mips::GP },
1599 { Mips::MSAAccess },
1600 { Mips::MSACSR },
1601 { Mips::MSAIR },
1602 { Mips::MSAMap },
1603 { Mips::MSAModify },
1604 { Mips::MSARequest },
1605 { Mips::MSASave },
1606 { Mips::MSAUnmap },
1607 { Mips::PC },
1608 { Mips::RA },
1609 { Mips::SP },
1610 { Mips::ZERO },
1611 { Mips::A0 },
1612 { Mips::A1 },
1613 { Mips::A2 },
1614 { Mips::A3 },
1615 { Mips::LO0 },
1616 { Mips::HI0 },
1617 { Mips::LO1 },
1618 { Mips::HI1 },
1619 { Mips::LO2 },
1620 { Mips::HI2 },
1621 { Mips::LO3 },
1622 { Mips::HI3 },
1623 { Mips::COP00 },
1624 { Mips::COP01 },
1625 { Mips::COP02 },
1626 { Mips::COP03 },
1627 { Mips::COP04 },
1628 { Mips::COP05 },
1629 { Mips::COP06 },
1630 { Mips::COP07 },
1631 { Mips::COP08 },
1632 { Mips::COP09 },
1633 { Mips::COP20 },
1634 { Mips::COP21 },
1635 { Mips::COP22 },
1636 { Mips::COP23 },
1637 { Mips::COP24 },
1638 { Mips::COP25 },
1639 { Mips::COP26 },
1640 { Mips::COP27 },
1641 { Mips::COP28 },
1642 { Mips::COP29 },
1643 { Mips::COP30 },
1644 { Mips::COP31 },
1645 { Mips::COP32 },
1646 { Mips::COP33 },
1647 { Mips::COP34 },
1648 { Mips::COP35 },
1649 { Mips::COP36 },
1650 { Mips::COP37 },
1651 { Mips::COP38 },
1652 { Mips::COP39 },
1653 { Mips::COP010 },
1654 { Mips::COP011 },
1655 { Mips::COP012 },
1656 { Mips::COP013 },
1657 { Mips::COP014 },
1658 { Mips::COP015 },
1659 { Mips::COP016 },
1660 { Mips::COP017 },
1661 { Mips::COP018 },
1662 { Mips::COP019 },
1663 { Mips::COP020 },
1664 { Mips::COP021 },
1665 { Mips::COP022 },
1666 { Mips::COP023 },
1667 { Mips::COP024 },
1668 { Mips::COP025 },
1669 { Mips::COP026 },
1670 { Mips::COP027 },
1671 { Mips::COP028 },
1672 { Mips::COP029 },
1673 { Mips::COP030 },
1674 { Mips::COP031 },
1675 { Mips::COP210 },
1676 { Mips::COP211 },
1677 { Mips::COP212 },
1678 { Mips::COP213 },
1679 { Mips::COP214 },
1680 { Mips::COP215 },
1681 { Mips::COP216 },
1682 { Mips::COP217 },
1683 { Mips::COP218 },
1684 { Mips::COP219 },
1685 { Mips::COP220 },
1686 { Mips::COP221 },
1687 { Mips::COP222 },
1688 { Mips::COP223 },
1689 { Mips::COP224 },
1690 { Mips::COP225 },
1691 { Mips::COP226 },
1692 { Mips::COP227 },
1693 { Mips::COP228 },
1694 { Mips::COP229 },
1695 { Mips::COP230 },
1696 { Mips::COP231 },
1697 { Mips::COP310 },
1698 { Mips::COP311 },
1699 { Mips::COP312 },
1700 { Mips::COP313 },
1701 { Mips::COP314 },
1702 { Mips::COP315 },
1703 { Mips::COP316 },
1704 { Mips::COP317 },
1705 { Mips::COP318 },
1706 { Mips::COP319 },
1707 { Mips::COP320 },
1708 { Mips::COP321 },
1709 { Mips::COP322 },
1710 { Mips::COP323 },
1711 { Mips::COP324 },
1712 { Mips::COP325 },
1713 { Mips::COP326 },
1714 { Mips::COP327 },
1715 { Mips::COP328 },
1716 { Mips::COP329 },
1717 { Mips::COP330 },
1718 { Mips::COP331 },
1719 { Mips::F0 },
1720 { Mips::F1 },
1721 { Mips::F2 },
1722 { Mips::F3 },
1723 { Mips::F4 },
1724 { Mips::F5 },
1725 { Mips::F6 },
1726 { Mips::F7 },
1727 { Mips::F8 },
1728 { Mips::F9 },
1729 { Mips::F10 },
1730 { Mips::F11 },
1731 { Mips::F12 },
1732 { Mips::F13 },
1733 { Mips::F14 },
1734 { Mips::F15 },
1735 { Mips::F16 },
1736 { Mips::F17 },
1737 { Mips::F18 },
1738 { Mips::F19 },
1739 { Mips::F20 },
1740 { Mips::F21 },
1741 { Mips::F22 },
1742 { Mips::F23 },
1743 { Mips::F24 },
1744 { Mips::F25 },
1745 { Mips::F26 },
1746 { Mips::F27 },
1747 { Mips::F28 },
1748 { Mips::F29 },
1749 { Mips::F30 },
1750 { Mips::F31 },
1751 { Mips::FCC0 },
1752 { Mips::FCC1 },
1753 { Mips::FCC2 },
1754 { Mips::FCC3 },
1755 { Mips::FCC4 },
1756 { Mips::FCC5 },
1757 { Mips::FCC6 },
1758 { Mips::FCC7 },
1759 { Mips::FCR0 },
1760 { Mips::FCR1 },
1761 { Mips::FCR2 },
1762 { Mips::FCR3 },
1763 { Mips::FCR4 },
1764 { Mips::FCR5 },
1765 { Mips::FCR6 },
1766 { Mips::FCR7 },
1767 { Mips::FCR8 },
1768 { Mips::FCR9 },
1769 { Mips::FCR10 },
1770 { Mips::FCR11 },
1771 { Mips::FCR12 },
1772 { Mips::FCR13 },
1773 { Mips::FCR14 },
1774 { Mips::FCR15 },
1775 { Mips::FCR16 },
1776 { Mips::FCR17 },
1777 { Mips::FCR18 },
1778 { Mips::FCR19 },
1779 { Mips::FCR20 },
1780 { Mips::FCR21 },
1781 { Mips::FCR22 },
1782 { Mips::FCR23 },
1783 { Mips::FCR24 },
1784 { Mips::FCR25 },
1785 { Mips::FCR26 },
1786 { Mips::FCR27 },
1787 { Mips::FCR28 },
1788 { Mips::FCR29 },
1789 { Mips::FCR30 },
1790 { Mips::FCR31 },
1791 { Mips::F_HI0 },
1792 { Mips::F_HI1 },
1793 { Mips::F_HI2 },
1794 { Mips::F_HI3 },
1795 { Mips::F_HI4 },
1796 { Mips::F_HI5 },
1797 { Mips::F_HI6 },
1798 { Mips::F_HI7 },
1799 { Mips::F_HI8 },
1800 { Mips::F_HI9 },
1801 { Mips::F_HI10 },
1802 { Mips::F_HI11 },
1803 { Mips::F_HI12 },
1804 { Mips::F_HI13 },
1805 { Mips::F_HI14 },
1806 { Mips::F_HI15 },
1807 { Mips::F_HI16 },
1808 { Mips::F_HI17 },
1809 { Mips::F_HI18 },
1810 { Mips::F_HI19 },
1811 { Mips::F_HI20 },
1812 { Mips::F_HI21 },
1813 { Mips::F_HI22 },
1814 { Mips::F_HI23 },
1815 { Mips::F_HI24 },
1816 { Mips::F_HI25 },
1817 { Mips::F_HI26 },
1818 { Mips::F_HI27 },
1819 { Mips::F_HI28 },
1820 { Mips::F_HI29 },
1821 { Mips::F_HI30 },
1822 { Mips::F_HI31 },
1823 { Mips::HWR0 },
1824 { Mips::HWR1 },
1825 { Mips::HWR2 },
1826 { Mips::HWR3 },
1827 { Mips::HWR4 },
1828 { Mips::HWR5 },
1829 { Mips::HWR6 },
1830 { Mips::HWR7 },
1831 { Mips::HWR8 },
1832 { Mips::HWR9 },
1833 { Mips::HWR10 },
1834 { Mips::HWR11 },
1835 { Mips::HWR12 },
1836 { Mips::HWR13 },
1837 { Mips::HWR14 },
1838 { Mips::HWR15 },
1839 { Mips::HWR16 },
1840 { Mips::HWR17 },
1841 { Mips::HWR18 },
1842 { Mips::HWR19 },
1843 { Mips::HWR20 },
1844 { Mips::HWR21 },
1845 { Mips::HWR22 },
1846 { Mips::HWR23 },
1847 { Mips::HWR24 },
1848 { Mips::HWR25 },
1849 { Mips::HWR26 },
1850 { Mips::HWR27 },
1851 { Mips::HWR28 },
1852 { Mips::HWR29 },
1853 { Mips::HWR30 },
1854 { Mips::HWR31 },
1855 { Mips::K0 },
1856 { Mips::K1 },
1857 { Mips::MPL0 },
1858 { Mips::MPL1 },
1859 { Mips::MPL2 },
1860 { Mips::MSA8 },
1861 { Mips::MSA9 },
1862 { Mips::MSA10 },
1863 { Mips::MSA11 },
1864 { Mips::MSA12 },
1865 { Mips::MSA13 },
1866 { Mips::MSA14 },
1867 { Mips::MSA15 },
1868 { Mips::MSA16 },
1869 { Mips::MSA17 },
1870 { Mips::MSA18 },
1871 { Mips::MSA19 },
1872 { Mips::MSA20 },
1873 { Mips::MSA21 },
1874 { Mips::MSA22 },
1875 { Mips::MSA23 },
1876 { Mips::MSA24 },
1877 { Mips::MSA25 },
1878 { Mips::MSA26 },
1879 { Mips::MSA27 },
1880 { Mips::MSA28 },
1881 { Mips::MSA29 },
1882 { Mips::MSA30 },
1883 { Mips::MSA31 },
1884 { Mips::P0 },
1885 { Mips::P1 },
1886 { Mips::P2 },
1887 { Mips::S0 },
1888 { Mips::S1 },
1889 { Mips::S2 },
1890 { Mips::S3 },
1891 { Mips::S4 },
1892 { Mips::S5 },
1893 { Mips::S6 },
1894 { Mips::S7 },
1895 { Mips::T0 },
1896 { Mips::T1 },
1897 { Mips::T2 },
1898 { Mips::T3 },
1899 { Mips::T4 },
1900 { Mips::T5 },
1901 { Mips::T6 },
1902 { Mips::T7 },
1903 { Mips::T8 },
1904 { Mips::T9 },
1905 { Mips::V0 },
1906 { Mips::V1 },
1907};
1908
1909namespace { // Register classes...
1910 // MSA128F16 Register Class...
1911 const MCPhysReg MSA128F16[] = {
1912 Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31,
1913 };
1914
1915 // MSA128F16 Bit set.
1916 const uint8_t MSA128F16Bits[] = {
1917 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
1918 };
1919
1920 // CCR Register Class...
1921 const MCPhysReg CCR[] = {
1922 Mips::FCR0, Mips::FCR1, Mips::FCR2, Mips::FCR3, Mips::FCR4, Mips::FCR5, Mips::FCR6, Mips::FCR7, Mips::FCR8, Mips::FCR9, Mips::FCR10, Mips::FCR11, Mips::FCR12, Mips::FCR13, Mips::FCR14, Mips::FCR15, Mips::FCR16, Mips::FCR17, Mips::FCR18, Mips::FCR19, Mips::FCR20, Mips::FCR21, Mips::FCR22, Mips::FCR23, Mips::FCR24, Mips::FCR25, Mips::FCR26, Mips::FCR27, Mips::FCR28, Mips::FCR29, Mips::FCR30, Mips::FCR31,
1923 };
1924
1925 // CCR Bit set.
1926 const uint8_t CCRBits[] = {
1927 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
1928 };
1929
1930 // COP0 Register Class...
1931 const MCPhysReg COP0[] = {
1932 Mips::COP00, Mips::COP01, Mips::COP02, Mips::COP03, Mips::COP04, Mips::COP05, Mips::COP06, Mips::COP07, Mips::COP08, Mips::COP09, Mips::COP010, Mips::COP011, Mips::COP012, Mips::COP013, Mips::COP014, Mips::COP015, Mips::COP016, Mips::COP017, Mips::COP018, Mips::COP019, Mips::COP020, Mips::COP021, Mips::COP022, Mips::COP023, Mips::COP024, Mips::COP025, Mips::COP026, Mips::COP027, Mips::COP028, Mips::COP029, Mips::COP030, Mips::COP031,
1933 };
1934
1935 // COP0 Bit set.
1936 const uint8_t COP0Bits[] = {
1937 0x00, 0x00, 0x00, 0x80, 0xff, 0x01, 0x00, 0xe0, 0xff, 0xff, 0x07,
1938 };
1939
1940 // COP2 Register Class...
1941 const MCPhysReg COP2[] = {
1942 Mips::COP20, Mips::COP21, Mips::COP22, Mips::COP23, Mips::COP24, Mips::COP25, Mips::COP26, Mips::COP27, Mips::COP28, Mips::COP29, Mips::COP210, Mips::COP211, Mips::COP212, Mips::COP213, Mips::COP214, Mips::COP215, Mips::COP216, Mips::COP217, Mips::COP218, Mips::COP219, Mips::COP220, Mips::COP221, Mips::COP222, Mips::COP223, Mips::COP224, Mips::COP225, Mips::COP226, Mips::COP227, Mips::COP228, Mips::COP229, Mips::COP230, Mips::COP231,
1943 };
1944
1945 // COP2 Bit set.
1946 const uint8_t COP2Bits[] = {
1947 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x07, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0x01,
1948 };
1949
1950 // COP3 Register Class...
1951 const MCPhysReg COP3[] = {
1952 Mips::COP30, Mips::COP31, Mips::COP32, Mips::COP33, Mips::COP34, Mips::COP35, Mips::COP36, Mips::COP37, Mips::COP38, Mips::COP39, Mips::COP310, Mips::COP311, Mips::COP312, Mips::COP313, Mips::COP314, Mips::COP315, Mips::COP316, Mips::COP317, Mips::COP318, Mips::COP319, Mips::COP320, Mips::COP321, Mips::COP322, Mips::COP323, Mips::COP324, Mips::COP325, Mips::COP326, Mips::COP327, Mips::COP328, Mips::COP329, Mips::COP330, Mips::COP331,
1953 };
1954
1955 // COP3 Bit set.
1956 const uint8_t COP3Bits[] = {
1957 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x7f,
1958 };
1959
1960 // DSPR Register Class...
1961 const MCPhysReg DSPR[] = {
1962 Mips::ZERO, Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP, Mips::SP, Mips::FP, Mips::RA,
1963 };
1964
1965 // DSPR Bit set.
1966 const uint8_t DSPRBits[] = {
1967 0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0xc0, 0xbf, 0xff, 0x07,
1968 };
1969
1970 // FGR32 Register Class...
1971 const MCPhysReg FGR32[] = {
1972 Mips::F0, Mips::F1, Mips::F2, Mips::F3, Mips::F4, Mips::F5, Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11, Mips::F12, Mips::F13, Mips::F14, Mips::F15, Mips::F16, Mips::F17, Mips::F18, Mips::F19, Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24, Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29, Mips::F30, Mips::F31,
1973 };
1974
1975 // FGR32 Bit set.
1976 const uint8_t FGR32Bits[] = {
1977 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
1978 };
1979
1980 // FGRCC Register Class...
1981 const MCPhysReg FGRCC[] = {
1982 Mips::F0, Mips::F1, Mips::F2, Mips::F3, Mips::F4, Mips::F5, Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11, Mips::F12, Mips::F13, Mips::F14, Mips::F15, Mips::F16, Mips::F17, Mips::F18, Mips::F19, Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24, Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29, Mips::F30, Mips::F31,
1983 };
1984
1985 // FGRCC Bit set.
1986 const uint8_t FGRCCBits[] = {
1987 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
1988 };
1989
1990 // GPR32 Register Class...
1991 const MCPhysReg GPR32[] = {
1992 Mips::ZERO, Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP, Mips::SP, Mips::FP, Mips::RA,
1993 };
1994
1995 // GPR32 Bit set.
1996 const uint8_t GPR32Bits[] = {
1997 0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0xc0, 0xbf, 0xff, 0x07,
1998 };
1999
2000 // HWRegs Register Class...
2001 const MCPhysReg HWRegs[] = {
2002 Mips::HWR0, Mips::HWR1, Mips::HWR2, Mips::HWR3, Mips::HWR4, Mips::HWR5, Mips::HWR6, Mips::HWR7, Mips::HWR8, Mips::HWR9, Mips::HWR10, Mips::HWR11, Mips::HWR12, Mips::HWR13, Mips::HWR14, Mips::HWR15, Mips::HWR16, Mips::HWR17, Mips::HWR18, Mips::HWR19, Mips::HWR20, Mips::HWR21, Mips::HWR22, Mips::HWR23, Mips::HWR24, Mips::HWR25, Mips::HWR26, Mips::HWR27, Mips::HWR28, Mips::HWR29, Mips::HWR30, Mips::HWR31,
2003 };
2004
2005 // HWRegs Bit set.
2006 const uint8_t HWRegsBits[] = {
2007 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
2008 };
2009
2010 // MSACtrl Register Class...
2011 const MCPhysReg MSACtrl[] = {
2012 Mips::MSAIR, Mips::MSACSR, Mips::MSAAccess, Mips::MSASave, Mips::MSAModify, Mips::MSARequest, Mips::MSAMap, Mips::MSAUnmap, Mips::MSA8, Mips::MSA9, Mips::MSA10, Mips::MSA11, Mips::MSA12, Mips::MSA13, Mips::MSA14, Mips::MSA15, Mips::MSA16, Mips::MSA17, Mips::MSA18, Mips::MSA19, Mips::MSA20, Mips::MSA21, Mips::MSA22, Mips::MSA23, Mips::MSA24, Mips::MSA25, Mips::MSA26, Mips::MSA27, Mips::MSA28, Mips::MSA29, Mips::MSA30, Mips::MSA31,
2013 };
2014
2015 // MSACtrl Bit set.
2016 const uint8_t MSACtrlBits[] = {
2017 0x00, 0xfc, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0x03,
2018 };
2019
2020 // GPR32NONZERO Register Class...
2021 const MCPhysReg GPR32NONZERO[] = {
2022 Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP, Mips::SP, Mips::FP, Mips::RA,
2023 };
2024
2025 // GPR32NONZERO Bit set.
2026 const uint8_t GPR32NONZEROBits[] = {
2027 0x02, 0x03, 0xd8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0xc0, 0xbf, 0xff, 0x07,
2028 };
2029
2030 // CPU16RegsPlusSP Register Class...
2031 const MCPhysReg CPU16RegsPlusSP[] = {
2032 Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::S0, Mips::S1, Mips::SP,
2033 };
2034
2035 // CPU16RegsPlusSP Bit set.
2036 const uint8_t CPU16RegsPlusSPBits[] = {
2037 0x00, 0x00, 0xd0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,
2038 };
2039
2040 // CPU16Regs Register Class...
2041 const MCPhysReg CPU16Regs[] = {
2042 Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::S0, Mips::S1,
2043 };
2044
2045 // CPU16Regs Bit set.
2046 const uint8_t CPU16RegsBits[] = {
2047 0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,
2048 };
2049
2050 // FCC Register Class...
2051 const MCPhysReg FCC[] = {
2052 Mips::FCC0, Mips::FCC1, Mips::FCC2, Mips::FCC3, Mips::FCC4, Mips::FCC5, Mips::FCC6, Mips::FCC7,
2053 };
2054
2055 // FCC Bit set.
2056 const uint8_t FCCBits[] = {
2057 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
2058 };
2059
2060 // GPRMM16 Register Class...
2061 const MCPhysReg GPRMM16[] = {
2062 Mips::S0, Mips::S1, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3,
2063 };
2064
2065 // GPRMM16 Bit set.
2066 const uint8_t GPRMM16Bits[] = {
2067 0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,
2068 };
2069
2070 // GPRMM16MoveP Register Class...
2071 const MCPhysReg GPRMM16MoveP[] = {
2072 Mips::ZERO, Mips::S1, Mips::V0, Mips::V1, Mips::S0, Mips::S2, Mips::S3, Mips::S4,
2073 };
2074
2075 // GPRMM16MoveP Bit set.
2076 const uint8_t GPRMM16MovePBits[] = {
2077 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x06,
2078 };
2079
2080 // GPRMM16Zero Register Class...
2081 const MCPhysReg GPRMM16Zero[] = {
2082 Mips::ZERO, Mips::S1, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3,
2083 };
2084
2085 // GPRMM16Zero Bit set.
2086 const uint8_t GPRMM16ZeroBits[] = {
2087 0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,
2088 };
2089
2090 // CPU16Regs_and_GPRMM16Zero Register Class...
2091 const MCPhysReg CPU16Regs_and_GPRMM16Zero[] = {
2092 Mips::S1, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3,
2093 };
2094
2095 // CPU16Regs_and_GPRMM16Zero Bit set.
2096 const uint8_t CPU16Regs_and_GPRMM16ZeroBits[] = {
2097 0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,
2098 };
2099
2100 // GPR32NONZERO_and_GPRMM16MoveP Register Class...
2101 const MCPhysReg GPR32NONZERO_and_GPRMM16MoveP[] = {
2102 Mips::S1, Mips::V0, Mips::V1, Mips::S0, Mips::S2, Mips::S3, Mips::S4,
2103 };
2104
2105 // GPR32NONZERO_and_GPRMM16MoveP Bit set.
2106 const uint8_t GPR32NONZERO_and_GPRMM16MovePBits[] = {
2107 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x06,
2108 };
2109
2110 // GPRMM16MovePPairSecond Register Class...
2111 const MCPhysReg GPRMM16MovePPairSecond[] = {
2112 Mips::A1, Mips::A2, Mips::A3, Mips::S5, Mips::S6,
2113 };
2114
2115 // GPRMM16MovePPairSecond Bit set.
2116 const uint8_t GPRMM16MovePPairSecondBits[] = {
2117 0x00, 0x00, 0x80, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18,
2118 };
2119
2120 // CPU16Regs_and_GPRMM16MoveP Register Class...
2121 const MCPhysReg CPU16Regs_and_GPRMM16MoveP[] = {
2122 Mips::S1, Mips::V0, Mips::V1, Mips::S0,
2123 };
2124
2125 // CPU16Regs_and_GPRMM16MoveP Bit set.
2126 const uint8_t CPU16Regs_and_GPRMM16MovePBits[] = {
2127 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,
2128 };
2129
2130 // GPRMM16MoveP_and_GPRMM16Zero Register Class...
2131 const MCPhysReg GPRMM16MoveP_and_GPRMM16Zero[] = {
2132 Mips::ZERO, Mips::S1, Mips::V0, Mips::V1,
2133 };
2134
2135 // GPRMM16MoveP_and_GPRMM16Zero Bit set.
2136 const uint8_t GPRMM16MoveP_and_GPRMM16ZeroBits[] = {
2137 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,
2138 };
2139
2140 // HI32DSP Register Class...
2141 const MCPhysReg HI32DSP[] = {
2142 Mips::HI0, Mips::HI1, Mips::HI2, Mips::HI3,
2143 };
2144
2145 // HI32DSP Bit set.
2146 const uint8_t HI32DSPBits[] = {
2147 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01,
2148 };
2149
2150 // LO32DSP Register Class...
2151 const MCPhysReg LO32DSP[] = {
2152 Mips::LO0, Mips::LO1, Mips::LO2, Mips::LO3,
2153 };
2154
2155 // LO32DSP Bit set.
2156 const uint8_t LO32DSPBits[] = {
2157 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78,
2158 };
2159
2160 // CPU16Regs_and_GPRMM16MovePPairSecond Register Class...
2161 const MCPhysReg CPU16Regs_and_GPRMM16MovePPairSecond[] = {
2162 Mips::A1, Mips::A2, Mips::A3,
2163 };
2164
2165 // CPU16Regs_and_GPRMM16MovePPairSecond Bit set.
2166 const uint8_t CPU16Regs_and_GPRMM16MovePPairSecondBits[] = {
2167 0x00, 0x00, 0x80, 0x03,
2168 };
2169
2170 // GPRMM16MovePPairFirst Register Class...
2171 const MCPhysReg GPRMM16MovePPairFirst[] = {
2172 Mips::A0, Mips::A1, Mips::A2,
2173 };
2174
2175 // GPRMM16MovePPairFirst Bit set.
2176 const uint8_t GPRMM16MovePPairFirstBits[] = {
2177 0x00, 0x00, 0xc0, 0x01,
2178 };
2179
2180 // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Register Class...
2181 const MCPhysReg GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = {
2182 Mips::S1, Mips::V0, Mips::V1,
2183 };
2184
2185 // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Bit set.
2186 const uint8_t GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = {
2187 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,
2188 };
2189
2190 // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond Register Class...
2191 const MCPhysReg GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond[] = {
2192 Mips::A1, Mips::A2,
2193 };
2194
2195 // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond Bit set.
2196 const uint8_t GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits[] = {
2197 0x00, 0x00, 0x80, 0x01,
2198 };
2199
2200 // CPURAReg Register Class...
2201 const MCPhysReg CPURAReg[] = {
2202 Mips::RA,
2203 };
2204
2205 // CPURAReg Bit set.
2206 const uint8_t CPURARegBits[] = {
2207 0x00, 0x00, 0x08,
2208 };
2209
2210 // CPUSPReg Register Class...
2211 const MCPhysReg CPUSPReg[] = {
2212 Mips::SP,
2213 };
2214
2215 // CPUSPReg Bit set.
2216 const uint8_t CPUSPRegBits[] = {
2217 0x00, 0x00, 0x10,
2218 };
2219
2220 // DSPCC Register Class...
2221 const MCPhysReg DSPCC[] = {
2222 Mips::DSPCCond,
2223 };
2224
2225 // DSPCC Bit set.
2226 const uint8_t DSPCCBits[] = {
2227 0x04,
2228 };
2229
2230 // GP32 Register Class...
2231 const MCPhysReg GP32[] = {
2232 Mips::GP,
2233 };
2234
2235 // GP32 Bit set.
2236 const uint8_t GP32Bits[] = {
2237 0x00, 0x02,
2238 };
2239
2240 // GPR32ZERO Register Class...
2241 const MCPhysReg GPR32ZERO[] = {
2242 Mips::ZERO,
2243 };
2244
2245 // GPR32ZERO Bit set.
2246 const uint8_t GPR32ZEROBits[] = {
2247 0x00, 0x00, 0x20,
2248 };
2249
2250 // HI32 Register Class...
2251 const MCPhysReg HI32[] = {
2252 Mips::HI0,
2253 };
2254
2255 // HI32 Bit set.
2256 const uint8_t HI32Bits[] = {
2257 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
2258 };
2259
2260 // LO32 Register Class...
2261 const MCPhysReg LO32[] = {
2262 Mips::LO0,
2263 };
2264
2265 // LO32 Bit set.
2266 const uint8_t LO32Bits[] = {
2267 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
2268 };
2269
2270 // SP32 Register Class...
2271 const MCPhysReg SP32[] = {
2272 Mips::SP,
2273 };
2274
2275 // SP32 Bit set.
2276 const uint8_t SP32Bits[] = {
2277 0x00, 0x00, 0x10,
2278 };
2279
2280 // FGR64 Register Class...
2281 const MCPhysReg FGR64[] = {
2282 Mips::D0_64, Mips::D1_64, Mips::D2_64, Mips::D3_64, Mips::D4_64, Mips::D5_64, Mips::D6_64, Mips::D7_64, Mips::D8_64, Mips::D9_64, Mips::D10_64, Mips::D11_64, Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64, Mips::D20_64, Mips::D21_64, Mips::D22_64, Mips::D23_64, Mips::D24_64, Mips::D25_64, Mips::D26_64, Mips::D27_64, Mips::D28_64, Mips::D29_64, Mips::D30_64, Mips::D31_64,
2283 };
2284
2285 // FGR64 Bit set.
2286 const uint8_t FGR64Bits[] = {
2287 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
2288 };
2289
2290 // GPR64 Register Class...
2291 const MCPhysReg GPR64[] = {
2292 Mips::ZERO_64, Mips::AT_64, Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64, Mips::T4_64, Mips::T5_64, Mips::T6_64, Mips::T7_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64, Mips::S5_64, Mips::S6_64, Mips::S7_64, Mips::T8_64, Mips::T9_64, Mips::K0_64, Mips::K1_64, Mips::GP_64, Mips::SP_64, Mips::FP_64, Mips::RA_64,
2293 };
2294
2295 // GPR64 Bit set.
2296 const uint8_t GPR64Bits[] = {
2297 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0xd8, 0xff, 0xff, 0x03,
2298 };
2299
2300 // GPR64_with_sub_32_in_GPR32NONZERO Register Class...
2301 const MCPhysReg GPR64_with_sub_32_in_GPR32NONZERO[] = {
2302 Mips::AT_64, Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64, Mips::T4_64, Mips::T5_64, Mips::T6_64, Mips::T7_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64, Mips::S5_64, Mips::S6_64, Mips::S7_64, Mips::T8_64, Mips::T9_64, Mips::K0_64, Mips::K1_64, Mips::GP_64, Mips::SP_64, Mips::FP_64, Mips::RA_64,
2303 };
2304
2305 // GPR64_with_sub_32_in_GPR32NONZERO Bit set.
2306 const uint8_t GPR64_with_sub_32_in_GPR32NONZEROBits[] = {
2307 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xd8, 0xff, 0xff, 0x03,
2308 };
2309
2310 // AFGR64 Register Class...
2311 const MCPhysReg AFGR64[] = {
2312 Mips::D0, Mips::D1, Mips::D2, Mips::D3, Mips::D4, Mips::D5, Mips::D6, Mips::D7, Mips::D8, Mips::D9, Mips::D10, Mips::D11, Mips::D12, Mips::D13, Mips::D14, Mips::D15,
2313 };
2314
2315 // AFGR64 Bit set.
2316 const uint8_t AFGR64Bits[] = {
2317 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
2318 };
2319
2320 // GPR64_with_sub_32_in_CPU16RegsPlusSP Register Class...
2321 const MCPhysReg GPR64_with_sub_32_in_CPU16RegsPlusSP[] = {
2322 Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S0_64, Mips::S1_64, Mips::SP_64,
2323 };
2324
2325 // GPR64_with_sub_32_in_CPU16RegsPlusSP Bit set.
2326 const uint8_t GPR64_with_sub_32_in_CPU16RegsPlusSPBits[] = {
2327 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03,
2328 };
2329
2330 // GPR64_with_sub_32_in_CPU16Regs Register Class...
2331 const MCPhysReg GPR64_with_sub_32_in_CPU16Regs[] = {
2332 Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S0_64, Mips::S1_64,
2333 };
2334
2335 // GPR64_with_sub_32_in_CPU16Regs Bit set.
2336 const uint8_t GPR64_with_sub_32_in_CPU16RegsBits[] = {
2337 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03,
2338 };
2339
2340 // GPR64_with_sub_32_in_GPRMM16MoveP Register Class...
2341 const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP[] = {
2342 Mips::ZERO_64, Mips::V0_64, Mips::V1_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64,
2343 };
2344
2345 // GPR64_with_sub_32_in_GPRMM16MoveP Bit set.
2346 const uint8_t GPR64_with_sub_32_in_GPRMM16MovePBits[] = {
2347 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x03,
2348 };
2349
2350 // GPR64_with_sub_32_in_GPRMM16Zero Register Class...
2351 const MCPhysReg GPR64_with_sub_32_in_GPRMM16Zero[] = {
2352 Mips::ZERO_64, Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S1_64,
2353 };
2354
2355 // GPR64_with_sub_32_in_GPRMM16Zero Bit set.
2356 const uint8_t GPR64_with_sub_32_in_GPRMM16ZeroBits[] = {
2357 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,
2358 };
2359
2360 // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero Register Class...
2361 const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero[] = {
2362 Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S1_64,
2363 };
2364
2365 // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero Bit set.
2366 const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits[] = {
2367 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,
2368 };
2369
2370 // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP Register Class...
2371 const MCPhysReg GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP[] = {
2372 Mips::V0_64, Mips::V1_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64,
2373 };
2374
2375 // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP Bit set.
2376 const uint8_t GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePBits[] = {
2377 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x03,
2378 };
2379
2380 // GPR64_with_sub_32_in_GPRMM16MovePPairSecond Register Class...
2381 const MCPhysReg GPR64_with_sub_32_in_GPRMM16MovePPairSecond[] = {
2382 Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S5_64, Mips::S6_64,
2383 };
2384
2385 // GPR64_with_sub_32_in_GPRMM16MovePPairSecond Bit set.
2386 const uint8_t GPR64_with_sub_32_in_GPRMM16MovePPairSecondBits[] = {
2387 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18,
2388 };
2389
2390 // ACC64DSP Register Class...
2391 const MCPhysReg ACC64DSP[] = {
2392 Mips::AC0, Mips::AC1, Mips::AC2, Mips::AC3,
2393 };
2394
2395 // ACC64DSP Bit set.
2396 const uint8_t ACC64DSPBits[] = {
2397 0x00, 0x00, 0x00, 0x3c,
2398 };
2399
2400 // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP Register Class...
2401 const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP[] = {
2402 Mips::V0_64, Mips::V1_64, Mips::S0_64, Mips::S1_64,
2403 };
2404
2405 // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP Bit set.
2406 const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits[] = {
2407 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03,
2408 };
2409
2410 // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero Register Class...
2411 const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero[] = {
2412 Mips::ZERO_64, Mips::V0_64, Mips::V1_64, Mips::S1_64,
2413 };
2414
2415 // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero Bit set.
2416 const uint8_t GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits[] = {
2417 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,
2418 };
2419
2420 // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond Register Class...
2421 const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond[] = {
2422 Mips::A1_64, Mips::A2_64, Mips::A3_64,
2423 };
2424
2425 // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond Bit set.
2426 const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondBits[] = {
2427 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0,
2428 };
2429
2430 // GPR64_with_sub_32_in_GPRMM16MovePPairFirst Register Class...
2431 const MCPhysReg GPR64_with_sub_32_in_GPRMM16MovePPairFirst[] = {
2432 Mips::A0_64, Mips::A1_64, Mips::A2_64,
2433 };
2434
2435 // GPR64_with_sub_32_in_GPRMM16MovePPairFirst Bit set.
2436 const uint8_t GPR64_with_sub_32_in_GPRMM16MovePPairFirstBits[] = {
2437 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70,
2438 };
2439
2440 // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Register Class...
2441 const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = {
2442 Mips::V0_64, Mips::V1_64, Mips::S1_64,
2443 };
2444
2445 // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Bit set.
2446 const uint8_t GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = {
2447 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,
2448 };
2449
2450 // OCTEON_MPL Register Class...
2451 const MCPhysReg OCTEON_MPL[] = {
2452 Mips::MPL0, Mips::MPL1, Mips::MPL2,
2453 };
2454
2455 // OCTEON_MPL Bit set.
2456 const uint8_t OCTEON_MPLBits[] = {
2457 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x03,
2458 };
2459
2460 // OCTEON_P Register Class...
2461 const MCPhysReg OCTEON_P[] = {
2462 Mips::P0, Mips::P1, Mips::P2,
2463 };
2464
2465 // OCTEON_P Bit set.
2466 const uint8_t OCTEON_PBits[] = {
2467 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c,
2468 };
2469
2470 // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond Register Class...
2471 const MCPhysReg GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond[] = {
2472 Mips::A1_64, Mips::A2_64,
2473 };
2474
2475 // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond Bit set.
2476 const uint8_t GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits[] = {
2477 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60,
2478 };
2479
2480 // ACC64 Register Class...
2481 const MCPhysReg ACC64[] = {
2482 Mips::AC0,
2483 };
2484
2485 // ACC64 Bit set.
2486 const uint8_t ACC64Bits[] = {
2487 0x00, 0x00, 0x00, 0x04,
2488 };
2489
2490 // GP64 Register Class...
2491 const MCPhysReg GP64[] = {
2492 Mips::GP_64,
2493 };
2494
2495 // GP64 Bit set.
2496 const uint8_t GP64Bits[] = {
2497 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
2498 };
2499
2500 // GPR64_with_sub_32_in_CPURAReg Register Class...
2501 const MCPhysReg GPR64_with_sub_32_in_CPURAReg[] = {
2502 Mips::RA_64,
2503 };
2504
2505 // GPR64_with_sub_32_in_CPURAReg Bit set.
2506 const uint8_t GPR64_with_sub_32_in_CPURARegBits[] = {
2507 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
2508 };
2509
2510 // GPR64_with_sub_32_in_GPR32ZERO Register Class...
2511 const MCPhysReg GPR64_with_sub_32_in_GPR32ZERO[] = {
2512 Mips::ZERO_64,
2513 };
2514
2515 // GPR64_with_sub_32_in_GPR32ZERO Bit set.
2516 const uint8_t GPR64_with_sub_32_in_GPR32ZEROBits[] = {
2517 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
2518 };
2519
2520 // HI64 Register Class...
2521 const MCPhysReg HI64[] = {
2522 Mips::HI0_64,
2523 };
2524
2525 // HI64 Bit set.
2526 const uint8_t HI64Bits[] = {
2527 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
2528 };
2529
2530 // LO64 Register Class...
2531 const MCPhysReg LO64[] = {
2532 Mips::LO0_64,
2533 };
2534
2535 // LO64 Bit set.
2536 const uint8_t LO64Bits[] = {
2537 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
2538 };
2539
2540 // SP64 Register Class...
2541 const MCPhysReg SP64[] = {
2542 Mips::SP_64,
2543 };
2544
2545 // SP64 Bit set.
2546 const uint8_t SP64Bits[] = {
2547 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
2548 };
2549
2550 // MSA128B Register Class...
2551 const MCPhysReg MSA128B[] = {
2552 Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31,
2553 };
2554
2555 // MSA128B Bit set.
2556 const uint8_t MSA128BBits[] = {
2557 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
2558 };
2559
2560 // MSA128D Register Class...
2561 const MCPhysReg MSA128D[] = {
2562 Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31,
2563 };
2564
2565 // MSA128D Bit set.
2566 const uint8_t MSA128DBits[] = {
2567 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
2568 };
2569
2570 // MSA128H Register Class...
2571 const MCPhysReg MSA128H[] = {
2572 Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31,
2573 };
2574
2575 // MSA128H Bit set.
2576 const uint8_t MSA128HBits[] = {
2577 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
2578 };
2579
2580 // MSA128W Register Class...
2581 const MCPhysReg MSA128W[] = {
2582 Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31,
2583 };
2584
2585 // MSA128W Bit set.
2586 const uint8_t MSA128WBits[] = {
2587 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
2588 };
2589
2590 // MSA128WEvens Register Class...
2591 const MCPhysReg MSA128WEvens[] = {
2592 Mips::W0, Mips::W2, Mips::W4, Mips::W6, Mips::W8, Mips::W10, Mips::W12, Mips::W14, Mips::W16, Mips::W18, Mips::W20, Mips::W22, Mips::W24, Mips::W26, Mips::W28, Mips::W30,
2593 };
2594
2595 // MSA128WEvens Bit set.
2596 const uint8_t MSA128WEvensBits[] = {
2597 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa8, 0xaa, 0xaa, 0xaa, 0x02,
2598 };
2599
2600 // ACC128 Register Class...
2601 const MCPhysReg ACC128[] = {
2602 Mips::AC0_64,
2603 };
2604
2605 // ACC128 Bit set.
2606 const uint8_t ACC128Bits[] = {
2607 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
2608 };
2609
2610} // end anonymous namespace
2611
2612
2613#ifdef __GNUC__
2614#pragma GCC diagnostic push
2615#pragma GCC diagnostic ignored "-Woverlength-strings"
2616#endif
2617extern const char MipsRegClassStrings[] = {
2618 /* 0 */ "COP0\000"
2619 /* 5 */ "HI32\000"
2620 /* 10 */ "LO32\000"
2621 /* 15 */ "GP32\000"
2622 /* 20 */ "SP32\000"
2623 /* 25 */ "FGR32\000"
2624 /* 31 */ "GPR32\000"
2625 /* 37 */ "COP2\000"
2626 /* 42 */ "COP3\000"
2627 /* 47 */ "ACC64\000"
2628 /* 53 */ "HI64\000"
2629 /* 58 */ "LO64\000"
2630 /* 63 */ "GP64\000"
2631 /* 68 */ "SP64\000"
2632 /* 73 */ "AFGR64\000"
2633 /* 80 */ "GPR64\000"
2634 /* 86 */ "MSA128F16\000"
2635 /* 96 */ "GPRMM16\000"
2636 /* 104 */ "ACC128\000"
2637 /* 111 */ "MSA128B\000"
2638 /* 119 */ "FCC\000"
2639 /* 123 */ "DSPCC\000"
2640 /* 129 */ "FGRCC\000"
2641 /* 135 */ "MSA128D\000"
2642 /* 143 */ "MSA128H\000"
2643 /* 151 */ "OCTEON_MPL\000"
2644 /* 162 */ "GPR64_with_sub_32_in_GPR32ZERO\000"
2645 /* 193 */ "GPR64_with_sub_32_in_GPR32NONZERO\000"
2646 /* 227 */ "HI32DSP\000"
2647 /* 235 */ "LO32DSP\000"
2648 /* 243 */ "ACC64DSP\000"
2649 /* 252 */ "GPR64_with_sub_32_in_CPU16RegsPlusSP\000"
2650 /* 289 */ "OCTEON_P\000"
2651 /* 298 */ "GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP\000"
2652 /* 349 */ "GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP\000"
2653 /* 397 */ "GPR64_with_sub_32_in_GPRMM16MoveP\000"
2654 /* 431 */ "CCR\000"
2655 /* 435 */ "DSPR\000"
2656 /* 440 */ "MSA128W\000"
2657 /* 448 */ "GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond\000"
2658 /* 506 */ "GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond\000"
2659 /* 576 */ "GPR64_with_sub_32_in_GPRMM16MovePPairSecond\000"
2660 /* 620 */ "GPR64_with_sub_32_in_CPURAReg\000"
2661 /* 650 */ "CPUSPReg\000"
2662 /* 659 */ "MSACtrl\000"
2663 /* 667 */ "GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero\000"
2664 /* 717 */ "GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero\000"
2665 /* 781 */ "GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero\000"
2666 /* 828 */ "GPR64_with_sub_32_in_GPRMM16Zero\000"
2667 /* 861 */ "GPR64_with_sub_32_in_CPU16Regs\000"
2668 /* 892 */ "HWRegs\000"
2669 /* 899 */ "MSA128WEvens\000"
2670 /* 912 */ "GPR64_with_sub_32_in_GPRMM16MovePPairFirst\000"
2671};
2672#ifdef __GNUC__
2673#pragma GCC diagnostic pop
2674#endif
2675
2676extern const MCRegisterClass MipsMCRegisterClasses[] = {
2677 { MSA128F16, MSA128F16Bits, 86, 32, sizeof(MSA128F16Bits), Mips::MSA128F16RegClassID, 16, 1, true, false },
2678 { CCR, CCRBits, 431, 32, sizeof(CCRBits), Mips::CCRRegClassID, 32, 1, false, false },
2679 { COP0, COP0Bits, 0, 32, sizeof(COP0Bits), Mips::COP0RegClassID, 32, 1, false, false },
2680 { COP2, COP2Bits, 37, 32, sizeof(COP2Bits), Mips::COP2RegClassID, 32, 1, false, false },
2681 { COP3, COP3Bits, 42, 32, sizeof(COP3Bits), Mips::COP3RegClassID, 32, 1, false, false },
2682 { DSPR, DSPRBits, 435, 32, sizeof(DSPRBits), Mips::DSPRRegClassID, 32, 1, true, false },
2683 { FGR32, FGR32Bits, 25, 32, sizeof(FGR32Bits), Mips::FGR32RegClassID, 32, 1, true, false },
2684 { FGRCC, FGRCCBits, 129, 32, sizeof(FGRCCBits), Mips::FGRCCRegClassID, 32, 1, true, false },
2685 { GPR32, GPR32Bits, 31, 32, sizeof(GPR32Bits), Mips::GPR32RegClassID, 32, 1, true, false },
2686 { HWRegs, HWRegsBits, 892, 32, sizeof(HWRegsBits), Mips::HWRegsRegClassID, 32, 1, false, false },
2687 { MSACtrl, MSACtrlBits, 659, 32, sizeof(MSACtrlBits), Mips::MSACtrlRegClassID, 32, 1, false, false },
2688 { GPR32NONZERO, GPR32NONZEROBits, 214, 31, sizeof(GPR32NONZEROBits), Mips::GPR32NONZERORegClassID, 32, 1, true, false },
2689 { CPU16RegsPlusSP, CPU16RegsPlusSPBits, 273, 9, sizeof(CPU16RegsPlusSPBits), Mips::CPU16RegsPlusSPRegClassID, 32, 1, true, false },
2690 { CPU16Regs, CPU16RegsBits, 882, 8, sizeof(CPU16RegsBits), Mips::CPU16RegsRegClassID, 32, 1, true, false },
2691 { FCC, FCCBits, 119, 8, sizeof(FCCBits), Mips::FCCRegClassID, 32, 1, false, false },
2692 { GPRMM16, GPRMM16Bits, 96, 8, sizeof(GPRMM16Bits), Mips::GPRMM16RegClassID, 32, 1, true, false },
2693 { GPRMM16MoveP, GPRMM16MovePBits, 336, 8, sizeof(GPRMM16MovePBits), Mips::GPRMM16MovePRegClassID, 32, 1, true, false },
2694 { GPRMM16Zero, GPRMM16ZeroBits, 705, 8, sizeof(GPRMM16ZeroBits), Mips::GPRMM16ZeroRegClassID, 32, 1, true, false },
2695 { CPU16Regs_and_GPRMM16Zero, CPU16Regs_and_GPRMM16ZeroBits, 755, 7, sizeof(CPU16Regs_and_GPRMM16ZeroBits), Mips::CPU16Regs_and_GPRMM16ZeroRegClassID, 32, 1, true, false },
2696 { GPR32NONZERO_and_GPRMM16MoveP, GPR32NONZERO_and_GPRMM16MovePBits, 319, 7, sizeof(GPR32NONZERO_and_GPRMM16MovePBits), Mips::GPR32NONZERO_and_GPRMM16MovePRegClassID, 32, 1, true, false },
2697 { GPRMM16MovePPairSecond, GPRMM16MovePPairSecondBits, 483, 5, sizeof(GPRMM16MovePPairSecondBits), Mips::GPRMM16MovePPairSecondRegClassID, 32, 1, true, false },
2698 { CPU16Regs_and_GPRMM16MoveP, CPU16Regs_and_GPRMM16MovePBits, 370, 4, sizeof(CPU16Regs_and_GPRMM16MovePBits), Mips::CPU16Regs_and_GPRMM16MovePRegClassID, 32, 1, true, false },
2699 { GPRMM16MoveP_and_GPRMM16Zero, GPRMM16MoveP_and_GPRMM16ZeroBits, 688, 4, sizeof(GPRMM16MoveP_and_GPRMM16ZeroBits), Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClassID, 32, 1, true, false },
2700 { HI32DSP, HI32DSPBits, 227, 4, sizeof(HI32DSPBits), Mips::HI32DSPRegClassID, 32, 1, true, false },
2701 { LO32DSP, LO32DSPBits, 235, 4, sizeof(LO32DSPBits), Mips::LO32DSPRegClassID, 32, 1, true, false },
2702 { CPU16Regs_and_GPRMM16MovePPairSecond, CPU16Regs_and_GPRMM16MovePPairSecondBits, 469, 3, sizeof(CPU16Regs_and_GPRMM16MovePPairSecondBits), Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClassID, 32, 1, true, false },
2703 { GPRMM16MovePPairFirst, GPRMM16MovePPairFirstBits, 933, 3, sizeof(GPRMM16MovePPairFirstBits), Mips::GPRMM16MovePPairFirstRegClassID, 32, 1, true, false },
2704 { GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero, GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits, 738, 3, sizeof(GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits), Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID, 32, 1, true, false },
2705 { GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond, GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits, 527, 2, sizeof(GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits), Mips::GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID, 32, 1, true, false },
2706 { CPURAReg, CPURARegBits, 641, 1, sizeof(CPURARegBits), Mips::CPURARegRegClassID, 32, 1, false, false },
2707 { CPUSPReg, CPUSPRegBits, 650, 1, sizeof(CPUSPRegBits), Mips::CPUSPRegRegClassID, 32, 1, false, false },
2708 { DSPCC, DSPCCBits, 123, 1, sizeof(DSPCCBits), Mips::DSPCCRegClassID, 32, 1, true, false },
2709 { GP32, GP32Bits, 15, 1, sizeof(GP32Bits), Mips::GP32RegClassID, 32, 1, false, false },
2710 { GPR32ZERO, GPR32ZEROBits, 183, 1, sizeof(GPR32ZEROBits), Mips::GPR32ZERORegClassID, 32, 1, true, false },
2711 { HI32, HI32Bits, 5, 1, sizeof(HI32Bits), Mips::HI32RegClassID, 32, 1, true, false },
2712 { LO32, LO32Bits, 10, 1, sizeof(LO32Bits), Mips::LO32RegClassID, 32, 1, true, false },
2713 { SP32, SP32Bits, 20, 1, sizeof(SP32Bits), Mips::SP32RegClassID, 32, 1, false, false },
2714 { FGR64, FGR64Bits, 74, 32, sizeof(FGR64Bits), Mips::FGR64RegClassID, 64, 1, true, false },
2715 { GPR64, GPR64Bits, 80, 32, sizeof(GPR64Bits), Mips::GPR64RegClassID, 64, 1, true, false },
2716 { GPR64_with_sub_32_in_GPR32NONZERO, GPR64_with_sub_32_in_GPR32NONZEROBits, 193, 31, sizeof(GPR64_with_sub_32_in_GPR32NONZEROBits), Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID, 64, 1, true, false },
2717 { AFGR64, AFGR64Bits, 73, 16, sizeof(AFGR64Bits), Mips::AFGR64RegClassID, 64, 1, true, false },
2718 { GPR64_with_sub_32_in_CPU16RegsPlusSP, GPR64_with_sub_32_in_CPU16RegsPlusSPBits, 252, 9, sizeof(GPR64_with_sub_32_in_CPU16RegsPlusSPBits), Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID, 64, 1, true, false },
2719 { GPR64_with_sub_32_in_CPU16Regs, GPR64_with_sub_32_in_CPU16RegsBits, 861, 8, sizeof(GPR64_with_sub_32_in_CPU16RegsBits), Mips::GPR64_with_sub_32_in_CPU16RegsRegClassID, 64, 1, true, false },
2720 { GPR64_with_sub_32_in_GPRMM16MoveP, GPR64_with_sub_32_in_GPRMM16MovePBits, 397, 8, sizeof(GPR64_with_sub_32_in_GPRMM16MovePBits), Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClassID, 64, 1, true, false },
2721 { GPR64_with_sub_32_in_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16ZeroBits, 828, 8, sizeof(GPR64_with_sub_32_in_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClassID, 64, 1, true, false },
2722 { GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits, 781, 7, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID, 64, 1, true, false },
2723 { GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP, GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePBits, 298, 7, sizeof(GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePBits), Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID, 64, 1, true, false },
2724 { GPR64_with_sub_32_in_GPRMM16MovePPairSecond, GPR64_with_sub_32_in_GPRMM16MovePPairSecondBits, 576, 5, sizeof(GPR64_with_sub_32_in_GPRMM16MovePPairSecondBits), Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClassID, 64, 1, true, false },
2725 { ACC64DSP, ACC64DSPBits, 243, 4, sizeof(ACC64DSPBits), Mips::ACC64DSPRegClassID, 64, 1, true, false },
2726 { GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits, 349, 4, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits), Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID, 64, 1, true, false },
2727 { GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits, 667, 4, sizeof(GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID, 64, 1, true, false },
2728 { GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondBits, 448, 3, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondBits), Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClassID, 64, 1, true, false },
2729 { GPR64_with_sub_32_in_GPRMM16MovePPairFirst, GPR64_with_sub_32_in_GPRMM16MovePPairFirstBits, 912, 3, sizeof(GPR64_with_sub_32_in_GPRMM16MovePPairFirstBits), Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClassID, 64, 1, true, false },
2730 { GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits, 717, 3, sizeof(GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID, 64, 1, true, false },
2731 { OCTEON_MPL, OCTEON_MPLBits, 151, 3, sizeof(OCTEON_MPLBits), Mips::OCTEON_MPLRegClassID, 64, 1, false, false },
2732 { OCTEON_P, OCTEON_PBits, 289, 3, sizeof(OCTEON_PBits), Mips::OCTEON_PRegClassID, 64, 1, false, false },
2733 { GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond, GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits, 506, 2, sizeof(GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits), Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID, 64, 1, true, false },
2734 { ACC64, ACC64Bits, 47, 1, sizeof(ACC64Bits), Mips::ACC64RegClassID, 64, 1, true, false },
2735 { GP64, GP64Bits, 63, 1, sizeof(GP64Bits), Mips::GP64RegClassID, 64, 1, false, false },
2736 { GPR64_with_sub_32_in_CPURAReg, GPR64_with_sub_32_in_CPURARegBits, 620, 1, sizeof(GPR64_with_sub_32_in_CPURARegBits), Mips::GPR64_with_sub_32_in_CPURARegRegClassID, 64, 1, true, false },
2737 { GPR64_with_sub_32_in_GPR32ZERO, GPR64_with_sub_32_in_GPR32ZEROBits, 162, 1, sizeof(GPR64_with_sub_32_in_GPR32ZEROBits), Mips::GPR64_with_sub_32_in_GPR32ZERORegClassID, 64, 1, true, false },
2738 { HI64, HI64Bits, 53, 1, sizeof(HI64Bits), Mips::HI64RegClassID, 64, 1, true, false },
2739 { LO64, LO64Bits, 58, 1, sizeof(LO64Bits), Mips::LO64RegClassID, 64, 1, true, false },
2740 { SP64, SP64Bits, 68, 1, sizeof(SP64Bits), Mips::SP64RegClassID, 64, 1, false, false },
2741 { MSA128B, MSA128BBits, 111, 32, sizeof(MSA128BBits), Mips::MSA128BRegClassID, 128, 1, true, false },
2742 { MSA128D, MSA128DBits, 135, 32, sizeof(MSA128DBits), Mips::MSA128DRegClassID, 128, 1, true, false },
2743 { MSA128H, MSA128HBits, 143, 32, sizeof(MSA128HBits), Mips::MSA128HRegClassID, 128, 1, true, false },
2744 { MSA128W, MSA128WBits, 440, 32, sizeof(MSA128WBits), Mips::MSA128WRegClassID, 128, 1, true, false },
2745 { MSA128WEvens, MSA128WEvensBits, 899, 16, sizeof(MSA128WEvensBits), Mips::MSA128WEvensRegClassID, 128, 1, true, false },
2746 { ACC128, ACC128Bits, 104, 1, sizeof(ACC128Bits), Mips::ACC128RegClassID, 128, 1, true, false },
2747};
2748
2749// Mips Dwarf<->LLVM register mappings.
2750extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0Dwarf2L[] = {
2751 { 0U, Mips::ZERO_64 },
2752 { 1U, Mips::AT_64 },
2753 { 2U, Mips::V0_64 },
2754 { 3U, Mips::V1_64 },
2755 { 4U, Mips::A0_64 },
2756 { 5U, Mips::A1_64 },
2757 { 6U, Mips::A2_64 },
2758 { 7U, Mips::A3_64 },
2759 { 8U, Mips::T0_64 },
2760 { 9U, Mips::T1_64 },
2761 { 10U, Mips::T2_64 },
2762 { 11U, Mips::T3_64 },
2763 { 12U, Mips::T4_64 },
2764 { 13U, Mips::T5_64 },
2765 { 14U, Mips::T6_64 },
2766 { 15U, Mips::T7_64 },
2767 { 16U, Mips::S0_64 },
2768 { 17U, Mips::S1_64 },
2769 { 18U, Mips::S2_64 },
2770 { 19U, Mips::S3_64 },
2771 { 20U, Mips::S4_64 },
2772 { 21U, Mips::S5_64 },
2773 { 22U, Mips::S6_64 },
2774 { 23U, Mips::S7_64 },
2775 { 24U, Mips::T8_64 },
2776 { 25U, Mips::T9_64 },
2777 { 26U, Mips::K0_64 },
2778 { 27U, Mips::K1_64 },
2779 { 28U, Mips::GP_64 },
2780 { 29U, Mips::SP_64 },
2781 { 30U, Mips::FP_64 },
2782 { 31U, Mips::RA_64 },
2783 { 32U, Mips::D0_64 },
2784 { 33U, Mips::D1_64 },
2785 { 34U, Mips::D2_64 },
2786 { 35U, Mips::D3_64 },
2787 { 36U, Mips::D4_64 },
2788 { 37U, Mips::D5_64 },
2789 { 38U, Mips::D6_64 },
2790 { 39U, Mips::D7_64 },
2791 { 40U, Mips::D8_64 },
2792 { 41U, Mips::D9_64 },
2793 { 42U, Mips::D10_64 },
2794 { 43U, Mips::D11_64 },
2795 { 44U, Mips::D12_64 },
2796 { 45U, Mips::D13_64 },
2797 { 46U, Mips::D14_64 },
2798 { 47U, Mips::D15_64 },
2799 { 48U, Mips::D16_64 },
2800 { 49U, Mips::D17_64 },
2801 { 50U, Mips::D18_64 },
2802 { 51U, Mips::D19_64 },
2803 { 52U, Mips::D20_64 },
2804 { 53U, Mips::D21_64 },
2805 { 54U, Mips::D22_64 },
2806 { 55U, Mips::D23_64 },
2807 { 56U, Mips::D24_64 },
2808 { 57U, Mips::D25_64 },
2809 { 58U, Mips::D26_64 },
2810 { 59U, Mips::D27_64 },
2811 { 60U, Mips::D28_64 },
2812 { 61U, Mips::D29_64 },
2813 { 62U, Mips::D30_64 },
2814 { 63U, Mips::D31_64 },
2815 { 64U, Mips::HI0 },
2816 { 65U, Mips::LO0 },
2817 { 176U, Mips::HI1 },
2818 { 177U, Mips::LO1 },
2819 { 178U, Mips::HI2 },
2820 { 179U, Mips::LO2 },
2821 { 180U, Mips::HI3 },
2822 { 181U, Mips::LO3 },
2823};
2824extern const unsigned MipsDwarfFlavour0Dwarf2LSize = std::size(MipsDwarfFlavour0Dwarf2L);
2825
2826extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0Dwarf2L[] = {
2827 { 0U, Mips::ZERO_64 },
2828 { 1U, Mips::AT_64 },
2829 { 2U, Mips::V0_64 },
2830 { 3U, Mips::V1_64 },
2831 { 4U, Mips::A0_64 },
2832 { 5U, Mips::A1_64 },
2833 { 6U, Mips::A2_64 },
2834 { 7U, Mips::A3_64 },
2835 { 8U, Mips::T0_64 },
2836 { 9U, Mips::T1_64 },
2837 { 10U, Mips::T2_64 },
2838 { 11U, Mips::T3_64 },
2839 { 12U, Mips::T4_64 },
2840 { 13U, Mips::T5_64 },
2841 { 14U, Mips::T6_64 },
2842 { 15U, Mips::T7_64 },
2843 { 16U, Mips::S0_64 },
2844 { 17U, Mips::S1_64 },
2845 { 18U, Mips::S2_64 },
2846 { 19U, Mips::S3_64 },
2847 { 20U, Mips::S4_64 },
2848 { 21U, Mips::S5_64 },
2849 { 22U, Mips::S6_64 },
2850 { 23U, Mips::S7_64 },
2851 { 24U, Mips::T8_64 },
2852 { 25U, Mips::T9_64 },
2853 { 26U, Mips::K0_64 },
2854 { 27U, Mips::K1_64 },
2855 { 28U, Mips::GP_64 },
2856 { 29U, Mips::SP_64 },
2857 { 30U, Mips::FP_64 },
2858 { 31U, Mips::RA_64 },
2859 { 32U, Mips::D0_64 },
2860 { 33U, Mips::D1_64 },
2861 { 34U, Mips::D2_64 },
2862 { 35U, Mips::D3_64 },
2863 { 36U, Mips::D4_64 },
2864 { 37U, Mips::D5_64 },
2865 { 38U, Mips::D6_64 },
2866 { 39U, Mips::D7_64 },
2867 { 40U, Mips::D8_64 },
2868 { 41U, Mips::D9_64 },
2869 { 42U, Mips::D10_64 },
2870 { 43U, Mips::D11_64 },
2871 { 44U, Mips::D12_64 },
2872 { 45U, Mips::D13_64 },
2873 { 46U, Mips::D14_64 },
2874 { 47U, Mips::D15_64 },
2875 { 48U, Mips::D16_64 },
2876 { 49U, Mips::D17_64 },
2877 { 50U, Mips::D18_64 },
2878 { 51U, Mips::D19_64 },
2879 { 52U, Mips::D20_64 },
2880 { 53U, Mips::D21_64 },
2881 { 54U, Mips::D22_64 },
2882 { 55U, Mips::D23_64 },
2883 { 56U, Mips::D24_64 },
2884 { 57U, Mips::D25_64 },
2885 { 58U, Mips::D26_64 },
2886 { 59U, Mips::D27_64 },
2887 { 60U, Mips::D28_64 },
2888 { 61U, Mips::D29_64 },
2889 { 62U, Mips::D30_64 },
2890 { 63U, Mips::D31_64 },
2891 { 64U, Mips::HI0 },
2892 { 65U, Mips::LO0 },
2893 { 176U, Mips::HI1 },
2894 { 177U, Mips::LO1 },
2895 { 178U, Mips::HI2 },
2896 { 179U, Mips::LO2 },
2897 { 180U, Mips::HI3 },
2898 { 181U, Mips::LO3 },
2899};
2900extern const unsigned MipsEHFlavour0Dwarf2LSize = std::size(MipsEHFlavour0Dwarf2L);
2901
2902extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0L2Dwarf[] = {
2903 { Mips::AT, 1U },
2904 { Mips::FP, 30U },
2905 { Mips::GP, 28U },
2906 { Mips::RA, 31U },
2907 { Mips::SP, 29U },
2908 { Mips::ZERO, 0U },
2909 { Mips::A0, 4U },
2910 { Mips::A1, 5U },
2911 { Mips::A2, 6U },
2912 { Mips::A3, 7U },
2913 { Mips::AT_64, 1U },
2914 { Mips::F0, 32U },
2915 { Mips::F1, 33U },
2916 { Mips::F2, 34U },
2917 { Mips::F3, 35U },
2918 { Mips::F4, 36U },
2919 { Mips::F5, 37U },
2920 { Mips::F6, 38U },
2921 { Mips::F7, 39U },
2922 { Mips::F8, 40U },
2923 { Mips::F9, 41U },
2924 { Mips::F10, 42U },
2925 { Mips::F11, 43U },
2926 { Mips::F12, 44U },
2927 { Mips::F13, 45U },
2928 { Mips::F14, 46U },
2929 { Mips::F15, 47U },
2930 { Mips::F16, 48U },
2931 { Mips::F17, 49U },
2932 { Mips::F18, 50U },
2933 { Mips::F19, 51U },
2934 { Mips::F20, 52U },
2935 { Mips::F21, 53U },
2936 { Mips::F22, 54U },
2937 { Mips::F23, 55U },
2938 { Mips::F24, 56U },
2939 { Mips::F25, 57U },
2940 { Mips::F26, 58U },
2941 { Mips::F27, 59U },
2942 { Mips::F28, 60U },
2943 { Mips::F29, 61U },
2944 { Mips::F30, 62U },
2945 { Mips::F31, 63U },
2946 { Mips::FP_64, 30U },
2947 { Mips::F_HI0, 32U },
2948 { Mips::F_HI1, 33U },
2949 { Mips::F_HI2, 34U },
2950 { Mips::F_HI3, 35U },
2951 { Mips::F_HI4, 36U },
2952 { Mips::F_HI5, 37U },
2953 { Mips::F_HI6, 38U },
2954 { Mips::F_HI7, 39U },
2955 { Mips::F_HI8, 40U },
2956 { Mips::F_HI9, 41U },
2957 { Mips::F_HI10, 42U },
2958 { Mips::F_HI11, 43U },
2959 { Mips::F_HI12, 44U },
2960 { Mips::F_HI13, 45U },
2961 { Mips::F_HI14, 46U },
2962 { Mips::F_HI15, 47U },
2963 { Mips::F_HI16, 48U },
2964 { Mips::F_HI17, 49U },
2965 { Mips::F_HI18, 50U },
2966 { Mips::F_HI19, 51U },
2967 { Mips::F_HI20, 52U },
2968 { Mips::F_HI21, 53U },
2969 { Mips::F_HI22, 54U },
2970 { Mips::F_HI23, 55U },
2971 { Mips::F_HI24, 56U },
2972 { Mips::F_HI25, 57U },
2973 { Mips::F_HI26, 58U },
2974 { Mips::F_HI27, 59U },
2975 { Mips::F_HI28, 60U },
2976 { Mips::F_HI29, 61U },
2977 { Mips::F_HI30, 62U },
2978 { Mips::F_HI31, 63U },
2979 { Mips::GP_64, 28U },
2980 { Mips::HI0, 64U },
2981 { Mips::HI1, 176U },
2982 { Mips::HI2, 178U },
2983 { Mips::HI3, 180U },
2984 { Mips::K0, 26U },
2985 { Mips::K1, 27U },
2986 { Mips::LO0, 65U },
2987 { Mips::LO1, 177U },
2988 { Mips::LO2, 179U },
2989 { Mips::LO3, 181U },
2990 { Mips::RA_64, 31U },
2991 { Mips::S0, 16U },
2992 { Mips::S1, 17U },
2993 { Mips::S2, 18U },
2994 { Mips::S3, 19U },
2995 { Mips::S4, 20U },
2996 { Mips::S5, 21U },
2997 { Mips::S6, 22U },
2998 { Mips::S7, 23U },
2999 { Mips::SP_64, 29U },
3000 { Mips::T0, 8U },
3001 { Mips::T1, 9U },
3002 { Mips::T2, 10U },
3003 { Mips::T3, 11U },
3004 { Mips::T4, 12U },
3005 { Mips::T5, 13U },
3006 { Mips::T6, 14U },
3007 { Mips::T7, 15U },
3008 { Mips::T8, 24U },
3009 { Mips::T9, 25U },
3010 { Mips::V0, 2U },
3011 { Mips::V1, 3U },
3012 { Mips::W0, 32U },
3013 { Mips::W1, 33U },
3014 { Mips::W2, 34U },
3015 { Mips::W3, 35U },
3016 { Mips::W4, 36U },
3017 { Mips::W5, 37U },
3018 { Mips::W6, 38U },
3019 { Mips::W7, 39U },
3020 { Mips::W8, 40U },
3021 { Mips::W9, 41U },
3022 { Mips::W10, 42U },
3023 { Mips::W11, 43U },
3024 { Mips::W12, 44U },
3025 { Mips::W13, 45U },
3026 { Mips::W14, 46U },
3027 { Mips::W15, 47U },
3028 { Mips::W16, 48U },
3029 { Mips::W17, 49U },
3030 { Mips::W18, 50U },
3031 { Mips::W19, 51U },
3032 { Mips::W20, 52U },
3033 { Mips::W21, 53U },
3034 { Mips::W22, 54U },
3035 { Mips::W23, 55U },
3036 { Mips::W24, 56U },
3037 { Mips::W25, 57U },
3038 { Mips::W26, 58U },
3039 { Mips::W27, 59U },
3040 { Mips::W28, 60U },
3041 { Mips::W29, 61U },
3042 { Mips::W30, 62U },
3043 { Mips::W31, 63U },
3044 { Mips::ZERO_64, 0U },
3045 { Mips::A0_64, 4U },
3046 { Mips::A1_64, 5U },
3047 { Mips::A2_64, 6U },
3048 { Mips::A3_64, 7U },
3049 { Mips::D0_64, 32U },
3050 { Mips::D1_64, 33U },
3051 { Mips::D2_64, 34U },
3052 { Mips::D3_64, 35U },
3053 { Mips::D4_64, 36U },
3054 { Mips::D5_64, 37U },
3055 { Mips::D6_64, 38U },
3056 { Mips::D7_64, 39U },
3057 { Mips::D8_64, 40U },
3058 { Mips::D9_64, 41U },
3059 { Mips::D10_64, 42U },
3060 { Mips::D11_64, 43U },
3061 { Mips::D12_64, 44U },
3062 { Mips::D13_64, 45U },
3063 { Mips::D14_64, 46U },
3064 { Mips::D15_64, 47U },
3065 { Mips::D16_64, 48U },
3066 { Mips::D17_64, 49U },
3067 { Mips::D18_64, 50U },
3068 { Mips::D19_64, 51U },
3069 { Mips::D20_64, 52U },
3070 { Mips::D21_64, 53U },
3071 { Mips::D22_64, 54U },
3072 { Mips::D23_64, 55U },
3073 { Mips::D24_64, 56U },
3074 { Mips::D25_64, 57U },
3075 { Mips::D26_64, 58U },
3076 { Mips::D27_64, 59U },
3077 { Mips::D28_64, 60U },
3078 { Mips::D29_64, 61U },
3079 { Mips::D30_64, 62U },
3080 { Mips::D31_64, 63U },
3081 { Mips::K0_64, 26U },
3082 { Mips::K1_64, 27U },
3083 { Mips::S0_64, 16U },
3084 { Mips::S1_64, 17U },
3085 { Mips::S2_64, 18U },
3086 { Mips::S3_64, 19U },
3087 { Mips::S4_64, 20U },
3088 { Mips::S5_64, 21U },
3089 { Mips::S6_64, 22U },
3090 { Mips::S7_64, 23U },
3091 { Mips::T0_64, 8U },
3092 { Mips::T1_64, 9U },
3093 { Mips::T2_64, 10U },
3094 { Mips::T3_64, 11U },
3095 { Mips::T4_64, 12U },
3096 { Mips::T5_64, 13U },
3097 { Mips::T6_64, 14U },
3098 { Mips::T7_64, 15U },
3099 { Mips::T8_64, 24U },
3100 { Mips::T9_64, 25U },
3101 { Mips::V0_64, 2U },
3102 { Mips::V1_64, 3U },
3103};
3104extern const unsigned MipsDwarfFlavour0L2DwarfSize = std::size(MipsDwarfFlavour0L2Dwarf);
3105
3106extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0L2Dwarf[] = {
3107 { Mips::AT, 1U },
3108 { Mips::FP, 30U },
3109 { Mips::GP, 28U },
3110 { Mips::RA, 31U },
3111 { Mips::SP, 29U },
3112 { Mips::ZERO, 0U },
3113 { Mips::A0, 4U },
3114 { Mips::A1, 5U },
3115 { Mips::A2, 6U },
3116 { Mips::A3, 7U },
3117 { Mips::AT_64, 1U },
3118 { Mips::F0, 32U },
3119 { Mips::F1, 33U },
3120 { Mips::F2, 34U },
3121 { Mips::F3, 35U },
3122 { Mips::F4, 36U },
3123 { Mips::F5, 37U },
3124 { Mips::F6, 38U },
3125 { Mips::F7, 39U },
3126 { Mips::F8, 40U },
3127 { Mips::F9, 41U },
3128 { Mips::F10, 42U },
3129 { Mips::F11, 43U },
3130 { Mips::F12, 44U },
3131 { Mips::F13, 45U },
3132 { Mips::F14, 46U },
3133 { Mips::F15, 47U },
3134 { Mips::F16, 48U },
3135 { Mips::F17, 49U },
3136 { Mips::F18, 50U },
3137 { Mips::F19, 51U },
3138 { Mips::F20, 52U },
3139 { Mips::F21, 53U },
3140 { Mips::F22, 54U },
3141 { Mips::F23, 55U },
3142 { Mips::F24, 56U },
3143 { Mips::F25, 57U },
3144 { Mips::F26, 58U },
3145 { Mips::F27, 59U },
3146 { Mips::F28, 60U },
3147 { Mips::F29, 61U },
3148 { Mips::F30, 62U },
3149 { Mips::F31, 63U },
3150 { Mips::FP_64, 30U },
3151 { Mips::F_HI0, 32U },
3152 { Mips::F_HI1, 33U },
3153 { Mips::F_HI2, 34U },
3154 { Mips::F_HI3, 35U },
3155 { Mips::F_HI4, 36U },
3156 { Mips::F_HI5, 37U },
3157 { Mips::F_HI6, 38U },
3158 { Mips::F_HI7, 39U },
3159 { Mips::F_HI8, 40U },
3160 { Mips::F_HI9, 41U },
3161 { Mips::F_HI10, 42U },
3162 { Mips::F_HI11, 43U },
3163 { Mips::F_HI12, 44U },
3164 { Mips::F_HI13, 45U },
3165 { Mips::F_HI14, 46U },
3166 { Mips::F_HI15, 47U },
3167 { Mips::F_HI16, 48U },
3168 { Mips::F_HI17, 49U },
3169 { Mips::F_HI18, 50U },
3170 { Mips::F_HI19, 51U },
3171 { Mips::F_HI20, 52U },
3172 { Mips::F_HI21, 53U },
3173 { Mips::F_HI22, 54U },
3174 { Mips::F_HI23, 55U },
3175 { Mips::F_HI24, 56U },
3176 { Mips::F_HI25, 57U },
3177 { Mips::F_HI26, 58U },
3178 { Mips::F_HI27, 59U },
3179 { Mips::F_HI28, 60U },
3180 { Mips::F_HI29, 61U },
3181 { Mips::F_HI30, 62U },
3182 { Mips::F_HI31, 63U },
3183 { Mips::GP_64, 28U },
3184 { Mips::HI0, 64U },
3185 { Mips::HI1, 176U },
3186 { Mips::HI2, 178U },
3187 { Mips::HI3, 180U },
3188 { Mips::K0, 26U },
3189 { Mips::K1, 27U },
3190 { Mips::LO0, 65U },
3191 { Mips::LO1, 177U },
3192 { Mips::LO2, 179U },
3193 { Mips::LO3, 181U },
3194 { Mips::RA_64, 31U },
3195 { Mips::S0, 16U },
3196 { Mips::S1, 17U },
3197 { Mips::S2, 18U },
3198 { Mips::S3, 19U },
3199 { Mips::S4, 20U },
3200 { Mips::S5, 21U },
3201 { Mips::S6, 22U },
3202 { Mips::S7, 23U },
3203 { Mips::SP_64, 29U },
3204 { Mips::T0, 8U },
3205 { Mips::T1, 9U },
3206 { Mips::T2, 10U },
3207 { Mips::T3, 11U },
3208 { Mips::T4, 12U },
3209 { Mips::T5, 13U },
3210 { Mips::T6, 14U },
3211 { Mips::T7, 15U },
3212 { Mips::T8, 24U },
3213 { Mips::T9, 25U },
3214 { Mips::V0, 2U },
3215 { Mips::V1, 3U },
3216 { Mips::W0, 32U },
3217 { Mips::W1, 33U },
3218 { Mips::W2, 34U },
3219 { Mips::W3, 35U },
3220 { Mips::W4, 36U },
3221 { Mips::W5, 37U },
3222 { Mips::W6, 38U },
3223 { Mips::W7, 39U },
3224 { Mips::W8, 40U },
3225 { Mips::W9, 41U },
3226 { Mips::W10, 42U },
3227 { Mips::W11, 43U },
3228 { Mips::W12, 44U },
3229 { Mips::W13, 45U },
3230 { Mips::W14, 46U },
3231 { Mips::W15, 47U },
3232 { Mips::W16, 48U },
3233 { Mips::W17, 49U },
3234 { Mips::W18, 50U },
3235 { Mips::W19, 51U },
3236 { Mips::W20, 52U },
3237 { Mips::W21, 53U },
3238 { Mips::W22, 54U },
3239 { Mips::W23, 55U },
3240 { Mips::W24, 56U },
3241 { Mips::W25, 57U },
3242 { Mips::W26, 58U },
3243 { Mips::W27, 59U },
3244 { Mips::W28, 60U },
3245 { Mips::W29, 61U },
3246 { Mips::W30, 62U },
3247 { Mips::W31, 63U },
3248 { Mips::ZERO_64, 0U },
3249 { Mips::A0_64, 4U },
3250 { Mips::A1_64, 5U },
3251 { Mips::A2_64, 6U },
3252 { Mips::A3_64, 7U },
3253 { Mips::D0_64, 32U },
3254 { Mips::D1_64, 33U },
3255 { Mips::D2_64, 34U },
3256 { Mips::D3_64, 35U },
3257 { Mips::D4_64, 36U },
3258 { Mips::D5_64, 37U },
3259 { Mips::D6_64, 38U },
3260 { Mips::D7_64, 39U },
3261 { Mips::D8_64, 40U },
3262 { Mips::D9_64, 41U },
3263 { Mips::D10_64, 42U },
3264 { Mips::D11_64, 43U },
3265 { Mips::D12_64, 44U },
3266 { Mips::D13_64, 45U },
3267 { Mips::D14_64, 46U },
3268 { Mips::D15_64, 47U },
3269 { Mips::D16_64, 48U },
3270 { Mips::D17_64, 49U },
3271 { Mips::D18_64, 50U },
3272 { Mips::D19_64, 51U },
3273 { Mips::D20_64, 52U },
3274 { Mips::D21_64, 53U },
3275 { Mips::D22_64, 54U },
3276 { Mips::D23_64, 55U },
3277 { Mips::D24_64, 56U },
3278 { Mips::D25_64, 57U },
3279 { Mips::D26_64, 58U },
3280 { Mips::D27_64, 59U },
3281 { Mips::D28_64, 60U },
3282 { Mips::D29_64, 61U },
3283 { Mips::D30_64, 62U },
3284 { Mips::D31_64, 63U },
3285 { Mips::K0_64, 26U },
3286 { Mips::K1_64, 27U },
3287 { Mips::S0_64, 16U },
3288 { Mips::S1_64, 17U },
3289 { Mips::S2_64, 18U },
3290 { Mips::S3_64, 19U },
3291 { Mips::S4_64, 20U },
3292 { Mips::S5_64, 21U },
3293 { Mips::S6_64, 22U },
3294 { Mips::S7_64, 23U },
3295 { Mips::T0_64, 8U },
3296 { Mips::T1_64, 9U },
3297 { Mips::T2_64, 10U },
3298 { Mips::T3_64, 11U },
3299 { Mips::T4_64, 12U },
3300 { Mips::T5_64, 13U },
3301 { Mips::T6_64, 14U },
3302 { Mips::T7_64, 15U },
3303 { Mips::T8_64, 24U },
3304 { Mips::T9_64, 25U },
3305 { Mips::V0_64, 2U },
3306 { Mips::V1_64, 3U },
3307};
3308extern const unsigned MipsEHFlavour0L2DwarfSize = std::size(MipsEHFlavour0L2Dwarf);
3309
3310extern const uint16_t MipsRegEncodingTable[] = {
3311 0,
3312 1,
3313 0,
3314 0,
3315 0,
3316 0,
3317 0,
3318 0,
3319 30,
3320 28,
3321 2,
3322 1,
3323 0,
3324 6,
3325 4,
3326 5,
3327 3,
3328 7,
3329 0,
3330 31,
3331 29,
3332 0,
3333 4,
3334 5,
3335 6,
3336 7,
3337 0,
3338 1,
3339 2,
3340 3,
3341 1,
3342 0,
3343 1,
3344 2,
3345 3,
3346 4,
3347 5,
3348 6,
3349 7,
3350 8,
3351 9,
3352 0,
3353 1,
3354 2,
3355 3,
3356 4,
3357 5,
3358 6,
3359 7,
3360 8,
3361 9,
3362 0,
3363 1,
3364 2,
3365 3,
3366 4,
3367 5,
3368 6,
3369 7,
3370 8,
3371 9,
3372 10,
3373 11,
3374 12,
3375 13,
3376 14,
3377 15,
3378 16,
3379 17,
3380 18,
3381 19,
3382 20,
3383 21,
3384 22,
3385 23,
3386 24,
3387 25,
3388 26,
3389 27,
3390 28,
3391 29,
3392 30,
3393 31,
3394 10,
3395 11,
3396 12,
3397 13,
3398 14,
3399 15,
3400 16,
3401 17,
3402 18,
3403 19,
3404 20,
3405 21,
3406 22,
3407 23,
3408 24,
3409 25,
3410 26,
3411 27,
3412 28,
3413 29,
3414 30,
3415 31,
3416 10,
3417 11,
3418 12,
3419 13,
3420 14,
3421 15,
3422 16,
3423 17,
3424 18,
3425 19,
3426 20,
3427 21,
3428 22,
3429 23,
3430 24,
3431 25,
3432 26,
3433 27,
3434 28,
3435 29,
3436 30,
3437 31,
3438 0,
3439 2,
3440 4,
3441 6,
3442 8,
3443 10,
3444 12,
3445 14,
3446 16,
3447 18,
3448 20,
3449 22,
3450 24,
3451 26,
3452 28,
3453 30,
3454 0,
3455 0,
3456 0,
3457 0,
3458 0,
3459 1,
3460 2,
3461 3,
3462 4,
3463 5,
3464 6,
3465 7,
3466 8,
3467 9,
3468 10,
3469 11,
3470 12,
3471 13,
3472 14,
3473 15,
3474 16,
3475 17,
3476 18,
3477 19,
3478 20,
3479 21,
3480 22,
3481 23,
3482 24,
3483 25,
3484 26,
3485 27,
3486 28,
3487 29,
3488 30,
3489 31,
3490 0,
3491 1,
3492 2,
3493 3,
3494 4,
3495 5,
3496 6,
3497 7,
3498 0,
3499 1,
3500 2,
3501 3,
3502 4,
3503 5,
3504 6,
3505 7,
3506 8,
3507 9,
3508 10,
3509 11,
3510 12,
3511 13,
3512 14,
3513 15,
3514 16,
3515 17,
3516 18,
3517 19,
3518 20,
3519 21,
3520 22,
3521 23,
3522 24,
3523 25,
3524 26,
3525 27,
3526 28,
3527 29,
3528 30,
3529 31,
3530 30,
3531 0,
3532 1,
3533 2,
3534 3,
3535 4,
3536 5,
3537 6,
3538 7,
3539 8,
3540 9,
3541 10,
3542 11,
3543 12,
3544 13,
3545 14,
3546 15,
3547 16,
3548 17,
3549 18,
3550 19,
3551 20,
3552 21,
3553 22,
3554 23,
3555 24,
3556 25,
3557 26,
3558 27,
3559 28,
3560 29,
3561 30,
3562 31,
3563 28,
3564 0,
3565 1,
3566 2,
3567 3,
3568 0,
3569 1,
3570 2,
3571 3,
3572 4,
3573 5,
3574 6,
3575 7,
3576 8,
3577 9,
3578 10,
3579 11,
3580 12,
3581 13,
3582 14,
3583 15,
3584 16,
3585 17,
3586 18,
3587 19,
3588 20,
3589 21,
3590 22,
3591 23,
3592 24,
3593 25,
3594 26,
3595 27,
3596 28,
3597 29,
3598 30,
3599 31,
3600 26,
3601 27,
3602 0,
3603 1,
3604 2,
3605 3,
3606 0,
3607 1,
3608 2,
3609 8,
3610 9,
3611 10,
3612 11,
3613 12,
3614 13,
3615 14,
3616 15,
3617 16,
3618 17,
3619 18,
3620 19,
3621 20,
3622 21,
3623 22,
3624 23,
3625 24,
3626 25,
3627 26,
3628 27,
3629 28,
3630 29,
3631 30,
3632 31,
3633 0,
3634 1,
3635 2,
3636 31,
3637 16,
3638 17,
3639 18,
3640 19,
3641 20,
3642 21,
3643 22,
3644 23,
3645 29,
3646 8,
3647 9,
3648 10,
3649 11,
3650 12,
3651 13,
3652 14,
3653 15,
3654 24,
3655 25,
3656 2,
3657 3,
3658 0,
3659 1,
3660 2,
3661 3,
3662 4,
3663 5,
3664 6,
3665 7,
3666 8,
3667 9,
3668 10,
3669 11,
3670 12,
3671 13,
3672 14,
3673 15,
3674 16,
3675 17,
3676 18,
3677 19,
3678 20,
3679 21,
3680 22,
3681 23,
3682 24,
3683 25,
3684 26,
3685 27,
3686 28,
3687 29,
3688 30,
3689 31,
3690 0,
3691 4,
3692 5,
3693 6,
3694 7,
3695 0,
3696 0,
3697 1,
3698 2,
3699 3,
3700 4,
3701 5,
3702 6,
3703 7,
3704 8,
3705 9,
3706 10,
3707 11,
3708 12,
3709 13,
3710 14,
3711 15,
3712 16,
3713 17,
3714 18,
3715 19,
3716 20,
3717 21,
3718 22,
3719 23,
3720 24,
3721 25,
3722 26,
3723 27,
3724 28,
3725 29,
3726 30,
3727 31,
3728 0,
3729 0,
3730 26,
3731 27,
3732 0,
3733 16,
3734 17,
3735 18,
3736 19,
3737 20,
3738 21,
3739 22,
3740 23,
3741 8,
3742 9,
3743 10,
3744 11,
3745 12,
3746 13,
3747 14,
3748 15,
3749 24,
3750 25,
3751 2,
3752 3,
3753};
3754static inline void InitMipsMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
3755 RI->InitMCRegisterInfo(MipsRegDesc, 442, RA, PC, MipsMCRegisterClasses, 70, MipsRegUnitRoots, 321, MipsRegDiffLists, MipsLaneMaskLists, MipsRegStrings, MipsRegClassStrings, MipsSubRegIdxLists, 12,
3756MipsRegEncodingTable);
3757
3758 switch (DwarfFlavour) {
3759 default:
3760 llvm_unreachable("Unknown DWARF flavour");
3761 case 0:
3762 RI->mapDwarfRegsToLLVMRegs(MipsDwarfFlavour0Dwarf2L, MipsDwarfFlavour0Dwarf2LSize, false);
3763 break;
3764 }
3765 switch (EHFlavour) {
3766 default:
3767 llvm_unreachable("Unknown DWARF flavour");
3768 case 0:
3769 RI->mapDwarfRegsToLLVMRegs(MipsEHFlavour0Dwarf2L, MipsEHFlavour0Dwarf2LSize, true);
3770 break;
3771 }
3772 switch (DwarfFlavour) {
3773 default:
3774 llvm_unreachable("Unknown DWARF flavour");
3775 case 0:
3776 RI->mapLLVMRegsToDwarfRegs(MipsDwarfFlavour0L2Dwarf, MipsDwarfFlavour0L2DwarfSize, false);
3777 break;
3778 }
3779 switch (EHFlavour) {
3780 default:
3781 llvm_unreachable("Unknown DWARF flavour");
3782 case 0:
3783 RI->mapLLVMRegsToDwarfRegs(MipsEHFlavour0L2Dwarf, MipsEHFlavour0L2DwarfSize, true);
3784 break;
3785 }
3786}
3787
3788} // end namespace llvm
3789
3790#endif // GET_REGINFO_MC_DESC
3791
3792/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
3793|* *|
3794|* Register Information Header Fragment *|
3795|* *|
3796|* Automatically generated file, do not edit! *|
3797|* *|
3798\*===----------------------------------------------------------------------===*/
3799
3800
3801#ifdef GET_REGINFO_HEADER
3802#undef GET_REGINFO_HEADER
3803
3804#include "llvm/CodeGen/TargetRegisterInfo.h"
3805
3806namespace llvm {
3807
3808class MipsFrameLowering;
3809
3810struct MipsGenRegisterInfo : public TargetRegisterInfo {
3811 explicit MipsGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
3812 unsigned PC = 0, unsigned HwMode = 0);
3813 unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
3814 unsigned reverseComposeSubRegIndicesImpl(unsigned, unsigned) const override;
3815 LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
3816 LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
3817 const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass *, unsigned) const override;
3818 const TargetRegisterClass *getSubRegisterClass(const TargetRegisterClass *, unsigned) const override;
3819 const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
3820 unsigned getRegUnitWeight(unsigned RegUnit) const override;
3821 unsigned getNumRegPressureSets() const override;
3822 const char *getRegPressureSetName(unsigned Idx) const override;
3823 unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
3824 const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
3825 const int *getRegUnitPressureSets(unsigned RegUnit) const override;
3826 ArrayRef<const char *> getRegMaskNames() const override;
3827 ArrayRef<const uint32_t *> getRegMasks() const override;
3828 bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override;
3829 bool isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const override;
3830 bool isFixedRegister(const MachineFunction &, MCRegister) const override;
3831 bool isArgumentRegister(const MachineFunction &, MCRegister) const override;
3832 bool isConstantPhysReg(MCRegister PhysReg) const override final;
3833 /// Devirtualized TargetFrameLowering.
3834 static const MipsFrameLowering *getFrameLowering(
3835 const MachineFunction &MF);
3836};
3837
3838namespace Mips { // Register classes
3839 extern const TargetRegisterClass MSA128F16RegClass;
3840 extern const TargetRegisterClass CCRRegClass;
3841 extern const TargetRegisterClass COP0RegClass;
3842 extern const TargetRegisterClass COP2RegClass;
3843 extern const TargetRegisterClass COP3RegClass;
3844 extern const TargetRegisterClass DSPRRegClass;
3845 extern const TargetRegisterClass FGR32RegClass;
3846 extern const TargetRegisterClass FGRCCRegClass;
3847 extern const TargetRegisterClass GPR32RegClass;
3848 extern const TargetRegisterClass HWRegsRegClass;
3849 extern const TargetRegisterClass MSACtrlRegClass;
3850 extern const TargetRegisterClass GPR32NONZERORegClass;
3851 extern const TargetRegisterClass CPU16RegsPlusSPRegClass;
3852 extern const TargetRegisterClass CPU16RegsRegClass;
3853 extern const TargetRegisterClass FCCRegClass;
3854 extern const TargetRegisterClass GPRMM16RegClass;
3855 extern const TargetRegisterClass GPRMM16MovePRegClass;
3856 extern const TargetRegisterClass GPRMM16ZeroRegClass;
3857 extern const TargetRegisterClass CPU16Regs_and_GPRMM16ZeroRegClass;
3858 extern const TargetRegisterClass GPR32NONZERO_and_GPRMM16MovePRegClass;
3859 extern const TargetRegisterClass GPRMM16MovePPairSecondRegClass;
3860 extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePRegClass;
3861 extern const TargetRegisterClass GPRMM16MoveP_and_GPRMM16ZeroRegClass;
3862 extern const TargetRegisterClass HI32DSPRegClass;
3863 extern const TargetRegisterClass LO32DSPRegClass;
3864 extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePPairSecondRegClass;
3865 extern const TargetRegisterClass GPRMM16MovePPairFirstRegClass;
3866 extern const TargetRegisterClass GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass;
3867 extern const TargetRegisterClass GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass;
3868 extern const TargetRegisterClass CPURARegRegClass;
3869 extern const TargetRegisterClass CPUSPRegRegClass;
3870 extern const TargetRegisterClass DSPCCRegClass;
3871 extern const TargetRegisterClass GP32RegClass;
3872 extern const TargetRegisterClass GPR32ZERORegClass;
3873 extern const TargetRegisterClass HI32RegClass;
3874 extern const TargetRegisterClass LO32RegClass;
3875 extern const TargetRegisterClass SP32RegClass;
3876 extern const TargetRegisterClass FGR64RegClass;
3877 extern const TargetRegisterClass GPR64RegClass;
3878 extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERORegClass;
3879 extern const TargetRegisterClass AFGR64RegClass;
3880 extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass;
3881 extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsRegClass;
3882 extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePRegClass;
3883 extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16ZeroRegClass;
3884 extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass;
3885 extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass;
3886 extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass;
3887 extern const TargetRegisterClass ACC64DSPRegClass;
3888 extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass;
3889 extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass;
3890 extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClass;
3891 extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClass;
3892 extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass;
3893 extern const TargetRegisterClass OCTEON_MPLRegClass;
3894 extern const TargetRegisterClass OCTEON_PRegClass;
3895 extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass;
3896 extern const TargetRegisterClass ACC64RegClass;
3897 extern const TargetRegisterClass GP64RegClass;
3898 extern const TargetRegisterClass GPR64_with_sub_32_in_CPURARegRegClass;
3899 extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32ZERORegClass;
3900 extern const TargetRegisterClass HI64RegClass;
3901 extern const TargetRegisterClass LO64RegClass;
3902 extern const TargetRegisterClass SP64RegClass;
3903 extern const TargetRegisterClass MSA128BRegClass;
3904 extern const TargetRegisterClass MSA128DRegClass;
3905 extern const TargetRegisterClass MSA128HRegClass;
3906 extern const TargetRegisterClass MSA128WRegClass;
3907 extern const TargetRegisterClass MSA128WEvensRegClass;
3908 extern const TargetRegisterClass ACC128RegClass;
3909} // end namespace Mips
3910
3911} // end namespace llvm
3912
3913#endif // GET_REGINFO_HEADER
3914
3915/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
3916|* *|
3917|* Target Register and Register Classes Information *|
3918|* *|
3919|* Automatically generated file, do not edit! *|
3920|* *|
3921\*===----------------------------------------------------------------------===*/
3922
3923
3924#ifdef GET_REGINFO_TARGET_DESC
3925#undef GET_REGINFO_TARGET_DESC
3926
3927namespace llvm {
3928
3929extern const MCRegisterClass MipsMCRegisterClasses[];
3930
3931static const MVT::SimpleValueType VTLists[] = {
3932 /* 0 */ MVT::i32, MVT::Other,
3933 /* 2 */ MVT::i64, MVT::Other,
3934 /* 4 */ MVT::f16, MVT::Other,
3935 /* 6 */ MVT::f32, MVT::Other,
3936 /* 8 */ MVT::f64, MVT::Other,
3937 /* 10 */ MVT::v16i8, MVT::Other,
3938 /* 12 */ MVT::v4i8, MVT::v2i16, MVT::Other,
3939 /* 15 */ MVT::v8i16, MVT::v8f16, MVT::Other,
3940 /* 18 */ MVT::v4i32, MVT::v4f32, MVT::Other,
3941 /* 21 */ MVT::v2i64, MVT::v2f64, MVT::Other,
3942 /* 24 */ MVT::Untyped, MVT::Other,
3943};
3944
3945static const char *SubRegIndexNameTable[] = { "sub_32", "sub_64", "sub_dsp16_19", "sub_dsp20", "sub_dsp21", "sub_dsp22", "sub_dsp23", "sub_hi", "sub_lo", "sub_hi_then_sub_32", "sub_32_sub_hi_then_sub_32", "" };
3946
3947static const TargetRegisterInfo::SubRegCoveredBits SubRegIdxRangeTable[] = {
3948 { 65535, 65535 },
3949 { 0, 32 }, // sub_32
3950 { 0, 64 }, // sub_64
3951 { 16, 4 }, // sub_dsp16_19
3952 { 20, 1 }, // sub_dsp20
3953 { 21, 1 }, // sub_dsp21
3954 { 22, 1 }, // sub_dsp22
3955 { 23, 1 }, // sub_dsp23
3956 { 32, 32 }, // sub_hi
3957 { 0, 32 }, // sub_lo
3958 { 32, 32 }, // sub_hi_then_sub_32
3959 { 0, 64 }, // sub_32_sub_hi_then_sub_32
3960};
3961
3962
3963static const LaneBitmask SubRegIndexLaneMaskTable[] = {
3964 LaneBitmask::getAll(),
3965 LaneBitmask(0x0000000000000001), // sub_32
3966 LaneBitmask(0x0000000000000041), // sub_64
3967 LaneBitmask(0x0000000000000002), // sub_dsp16_19
3968 LaneBitmask(0x0000000000000004), // sub_dsp20
3969 LaneBitmask(0x0000000000000008), // sub_dsp21
3970 LaneBitmask(0x0000000000000010), // sub_dsp22
3971 LaneBitmask(0x0000000000000020), // sub_dsp23
3972 LaneBitmask(0x0000000000000040), // sub_hi
3973 LaneBitmask(0x0000000000000001), // sub_lo
3974 LaneBitmask(0x0000000000000040), // sub_hi_then_sub_32
3975 LaneBitmask(0x0000000000000041), // sub_32_sub_hi_then_sub_32
3976 };
3977
3978
3979
3980static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
3981 // Mode = 0 (Default)
3982 { 16, 16, 128, /*VTLists+*/4 }, // MSA128F16
3983 { 32, 32, 32, /*VTLists+*/0 }, // CCR
3984 { 32, 32, 32, /*VTLists+*/0 }, // COP0
3985 { 32, 32, 32, /*VTLists+*/0 }, // COP2
3986 { 32, 32, 32, /*VTLists+*/0 }, // COP3
3987 { 32, 32, 32, /*VTLists+*/12 }, // DSPR
3988 { 32, 32, 32, /*VTLists+*/6 }, // FGR32
3989 { 32, 32, 32, /*VTLists+*/0 }, // FGRCC
3990 { 32, 32, 32, /*VTLists+*/0 }, // GPR32
3991 { 32, 32, 32, /*VTLists+*/0 }, // HWRegs
3992 { 32, 32, 32, /*VTLists+*/0 }, // MSACtrl
3993 { 32, 32, 32, /*VTLists+*/0 }, // GPR32NONZERO
3994 { 32, 32, 32, /*VTLists+*/0 }, // CPU16RegsPlusSP
3995 { 32, 32, 32, /*VTLists+*/0 }, // CPU16Regs
3996 { 32, 32, 32, /*VTLists+*/0 }, // FCC
3997 { 32, 32, 32, /*VTLists+*/0 }, // GPRMM16
3998 { 32, 32, 32, /*VTLists+*/0 }, // GPRMM16MoveP
3999 { 32, 32, 32, /*VTLists+*/0 }, // GPRMM16Zero
4000 { 32, 32, 32, /*VTLists+*/0 }, // CPU16Regs_and_GPRMM16Zero
4001 { 32, 32, 32, /*VTLists+*/0 }, // GPR32NONZERO_and_GPRMM16MoveP
4002 { 32, 32, 32, /*VTLists+*/0 }, // GPRMM16MovePPairSecond
4003 { 32, 32, 32, /*VTLists+*/0 }, // CPU16Regs_and_GPRMM16MoveP
4004 { 32, 32, 32, /*VTLists+*/0 }, // GPRMM16MoveP_and_GPRMM16Zero
4005 { 32, 32, 32, /*VTLists+*/0 }, // HI32DSP
4006 { 32, 32, 32, /*VTLists+*/0 }, // LO32DSP
4007 { 32, 32, 32, /*VTLists+*/0 }, // CPU16Regs_and_GPRMM16MovePPairSecond
4008 { 32, 32, 32, /*VTLists+*/0 }, // GPRMM16MovePPairFirst
4009 { 32, 32, 32, /*VTLists+*/0 }, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
4010 { 32, 32, 32, /*VTLists+*/0 }, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
4011 { 32, 32, 32, /*VTLists+*/0 }, // CPURAReg
4012 { 32, 32, 32, /*VTLists+*/0 }, // CPUSPReg
4013 { 32, 32, 32, /*VTLists+*/12 }, // DSPCC
4014 { 32, 32, 32, /*VTLists+*/0 }, // GP32
4015 { 32, 32, 32, /*VTLists+*/0 }, // GPR32ZERO
4016 { 32, 32, 32, /*VTLists+*/0 }, // HI32
4017 { 32, 32, 32, /*VTLists+*/0 }, // LO32
4018 { 32, 32, 32, /*VTLists+*/0 }, // SP32
4019 { 64, 64, 64, /*VTLists+*/8 }, // FGR64
4020 { 64, 64, 64, /*VTLists+*/2 }, // GPR64
4021 { 64, 64, 64, /*VTLists+*/2 }, // GPR64_with_sub_32_in_GPR32NONZERO
4022 { 64, 64, 64, /*VTLists+*/8 }, // AFGR64
4023 { 64, 64, 64, /*VTLists+*/2 }, // GPR64_with_sub_32_in_CPU16RegsPlusSP
4024 { 64, 64, 64, /*VTLists+*/2 }, // GPR64_with_sub_32_in_CPU16Regs
4025 { 64, 64, 64, /*VTLists+*/2 }, // GPR64_with_sub_32_in_GPRMM16MoveP
4026 { 64, 64, 64, /*VTLists+*/2 }, // GPR64_with_sub_32_in_GPRMM16Zero
4027 { 64, 64, 64, /*VTLists+*/2 }, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
4028 { 64, 64, 64, /*VTLists+*/2 }, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
4029 { 64, 64, 64, /*VTLists+*/2 }, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond
4030 { 64, 64, 64, /*VTLists+*/24 }, // ACC64DSP
4031 { 64, 64, 64, /*VTLists+*/2 }, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
4032 { 64, 64, 64, /*VTLists+*/2 }, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
4033 { 64, 64, 64, /*VTLists+*/2 }, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond
4034 { 64, 64, 64, /*VTLists+*/2 }, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst
4035 { 64, 64, 64, /*VTLists+*/2 }, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
4036 { 64, 64, 64, /*VTLists+*/2 }, // OCTEON_MPL
4037 { 64, 64, 64, /*VTLists+*/2 }, // OCTEON_P
4038 { 64, 64, 64, /*VTLists+*/2 }, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
4039 { 64, 64, 64, /*VTLists+*/24 }, // ACC64
4040 { 64, 64, 64, /*VTLists+*/2 }, // GP64
4041 { 64, 64, 64, /*VTLists+*/2 }, // GPR64_with_sub_32_in_CPURAReg
4042 { 64, 64, 64, /*VTLists+*/2 }, // GPR64_with_sub_32_in_GPR32ZERO
4043 { 64, 64, 64, /*VTLists+*/2 }, // HI64
4044 { 64, 64, 64, /*VTLists+*/2 }, // LO64
4045 { 64, 64, 64, /*VTLists+*/2 }, // SP64
4046 { 128, 128, 128, /*VTLists+*/10 }, // MSA128B
4047 { 128, 128, 128, /*VTLists+*/21 }, // MSA128D
4048 { 128, 128, 128, /*VTLists+*/15 }, // MSA128H
4049 { 128, 128, 128, /*VTLists+*/18 }, // MSA128W
4050 { 128, 128, 128, /*VTLists+*/18 }, // MSA128WEvens
4051 { 128, 128, 128, /*VTLists+*/24 }, // ACC128
4052};
4053static const uint32_t MSA128F16SubClassMask[] = {
4054 0x00000001, 0x00000000, 0x0000001f,
4055};
4056
4057static const uint32_t CCRSubClassMask[] = {
4058 0x00000002, 0x00000000, 0x00000000,
4059};
4060
4061static const uint32_t COP0SubClassMask[] = {
4062 0x00000004, 0x00000000, 0x00000000,
4063};
4064
4065static const uint32_t COP2SubClassMask[] = {
4066 0x00000008, 0x00000000, 0x00000000,
4067};
4068
4069static const uint32_t COP3SubClassMask[] = {
4070 0x00000010, 0x00000000, 0x00000000,
4071};
4072
4073static const uint32_t DSPRSubClassMask[] = {
4074 0x7e7fb920, 0x00000013, 0x00000000,
4075 0x00000000, 0x9d3efec0, 0x00000000, // sub_32
4076};
4077
4078static const uint32_t FGR32SubClassMask[] = {
4079 0x000000c0, 0x00000000, 0x00000000,
4080 0x00000000, 0x00000100, 0x00000000, // sub_hi
4081 0x00000001, 0x00000120, 0x0000001f, // sub_lo
4082};
4083
4084static const uint32_t FGRCCSubClassMask[] = {
4085 0x000000c0, 0x00000000, 0x00000000,
4086 0x00000000, 0x00000100, 0x00000000, // sub_hi
4087 0x00000001, 0x00000120, 0x0000001f, // sub_lo
4088};
4089
4090static const uint32_t GPR32SubClassMask[] = {
4091 0x7e7fb900, 0x00000013, 0x00000000,
4092 0x00000000, 0x9d3efec0, 0x00000000, // sub_32
4093};
4094
4095static const uint32_t HWRegsSubClassMask[] = {
4096 0x00000200, 0x00000000, 0x00000000,
4097};
4098
4099static const uint32_t MSACtrlSubClassMask[] = {
4100 0x00000400, 0x00000000, 0x00000000,
4101};
4102
4103static const uint32_t GPR32NONZEROSubClassMask[] = {
4104 0x7e3cb800, 0x00000011, 0x00000000,
4105 0x00000000, 0x8d3ae680, 0x00000000, // sub_32
4106};
4107
4108static const uint32_t CPU16RegsPlusSPSubClassMask[] = {
4109 0x5e24b000, 0x00000010, 0x00000000,
4110 0x00000000, 0x813a2600, 0x00000000, // sub_32
4111};
4112
4113static const uint32_t CPU16RegsSubClassMask[] = {
4114 0x1e24a000, 0x00000000, 0x00000000,
4115 0x00000000, 0x013a2400, 0x00000000, // sub_32
4116};
4117
4118static const uint32_t FCCSubClassMask[] = {
4119 0x00004000, 0x00000000, 0x00000000,
4120};
4121
4122static const uint32_t GPRMM16SubClassMask[] = {
4123 0x1e248000, 0x00000000, 0x00000000,
4124 0x00000000, 0x013a2400, 0x00000000, // sub_32
4125};
4126
4127static const uint32_t GPRMM16MovePSubClassMask[] = {
4128 0x08690000, 0x00000002, 0x00000000,
4129 0x00000000, 0x10264800, 0x00000000, // sub_32
4130};
4131
4132static const uint32_t GPRMM16ZeroSubClassMask[] = {
4133 0x1e460000, 0x00000002, 0x00000000,
4134 0x00000000, 0x113c3000, 0x00000000, // sub_32
4135};
4136
4137static const uint32_t CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {
4138 0x1e040000, 0x00000000, 0x00000000,
4139 0x00000000, 0x01382000, 0x00000000, // sub_32
4140};
4141
4142static const uint32_t GPR32NONZERO_and_GPRMM16MovePSubClassMask[] = {
4143 0x08280000, 0x00000000, 0x00000000,
4144 0x00000000, 0x00224000, 0x00000000, // sub_32
4145};
4146
4147static const uint32_t GPRMM16MovePPairSecondSubClassMask[] = {
4148 0x12100000, 0x00000000, 0x00000000,
4149 0x00000000, 0x01088000, 0x00000000, // sub_32
4150};
4151
4152static const uint32_t CPU16Regs_and_GPRMM16MovePSubClassMask[] = {
4153 0x08200000, 0x00000000, 0x00000000,
4154 0x00000000, 0x00220000, 0x00000000, // sub_32
4155};
4156
4157static const uint32_t GPRMM16MoveP_and_GPRMM16ZeroSubClassMask[] = {
4158 0x08400000, 0x00000002, 0x00000000,
4159 0x00000000, 0x10240000, 0x00000000, // sub_32
4160};
4161
4162static const uint32_t HI32DSPSubClassMask[] = {
4163 0x00800000, 0x00000004, 0x00000000,
4164 0x00000000, 0x20000000, 0x00000000, // sub_32
4165 0x00000000, 0x02010000, 0x00000000, // sub_hi
4166 0x00000000, 0x00000000, 0x00000020, // sub_hi_then_sub_32
4167};
4168
4169static const uint32_t LO32DSPSubClassMask[] = {
4170 0x01000000, 0x00000008, 0x00000000,
4171 0x00000000, 0x40000000, 0x00000020, // sub_32
4172 0x00000000, 0x02010000, 0x00000000, // sub_lo
4173};
4174
4175static const uint32_t CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask[] = {
4176 0x12000000, 0x00000000, 0x00000000,
4177 0x00000000, 0x01080000, 0x00000000, // sub_32
4178};
4179
4180static const uint32_t GPRMM16MovePPairFirstSubClassMask[] = {
4181 0x14000000, 0x00000000, 0x00000000,
4182 0x00000000, 0x01100000, 0x00000000, // sub_32
4183};
4184
4185static const uint32_t GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {
4186 0x08000000, 0x00000000, 0x00000000,
4187 0x00000000, 0x00200000, 0x00000000, // sub_32
4188};
4189
4190static const uint32_t GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask[] = {
4191 0x10000000, 0x00000000, 0x00000000,
4192 0x00000000, 0x01000000, 0x00000000, // sub_32
4193};
4194
4195static const uint32_t CPURARegSubClassMask[] = {
4196 0x20000000, 0x00000000, 0x00000000,
4197 0x00000000, 0x08000000, 0x00000000, // sub_32
4198};
4199
4200static const uint32_t CPUSPRegSubClassMask[] = {
4201 0x40000000, 0x00000010, 0x00000000,
4202 0x00000000, 0x80000000, 0x00000000, // sub_32
4203};
4204
4205static const uint32_t DSPCCSubClassMask[] = {
4206 0x80000000, 0x00000000, 0x00000000,
4207};
4208
4209static const uint32_t GP32SubClassMask[] = {
4210 0x00000000, 0x00000001, 0x00000000,
4211 0x00000000, 0x04000000, 0x00000000, // sub_32
4212};
4213
4214static const uint32_t GPR32ZEROSubClassMask[] = {
4215 0x00000000, 0x00000002, 0x00000000,
4216 0x00000000, 0x10000000, 0x00000000, // sub_32
4217};
4218
4219static const uint32_t HI32SubClassMask[] = {
4220 0x00000000, 0x00000004, 0x00000000,
4221 0x00000000, 0x20000000, 0x00000000, // sub_32
4222 0x00000000, 0x02000000, 0x00000000, // sub_hi
4223 0x00000000, 0x00000000, 0x00000020, // sub_hi_then_sub_32
4224};
4225
4226static const uint32_t LO32SubClassMask[] = {
4227 0x00000000, 0x00000008, 0x00000000,
4228 0x00000000, 0x40000000, 0x00000020, // sub_32
4229 0x00000000, 0x02000000, 0x00000000, // sub_lo
4230};
4231
4232static const uint32_t SP32SubClassMask[] = {
4233 0x00000000, 0x00000010, 0x00000000,
4234 0x00000000, 0x80000000, 0x00000000, // sub_32
4235};
4236
4237static const uint32_t FGR64SubClassMask[] = {
4238 0x00000000, 0x00000020, 0x00000000,
4239 0x00000001, 0x00000000, 0x0000001f, // sub_64
4240};
4241
4242static const uint32_t GPR64SubClassMask[] = {
4243 0x00000000, 0x9d3efec0, 0x00000000,
4244};
4245
4246static const uint32_t GPR64_with_sub_32_in_GPR32NONZEROSubClassMask[] = {
4247 0x00000000, 0x8d3ae680, 0x00000000,
4248};
4249
4250static const uint32_t AFGR64SubClassMask[] = {
4251 0x00000000, 0x00000100, 0x00000000,
4252};
4253
4254static const uint32_t GPR64_with_sub_32_in_CPU16RegsPlusSPSubClassMask[] = {
4255 0x00000000, 0x813a2600, 0x00000000,
4256};
4257
4258static const uint32_t GPR64_with_sub_32_in_CPU16RegsSubClassMask[] = {
4259 0x00000000, 0x013a2400, 0x00000000,
4260};
4261
4262static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePSubClassMask[] = {
4263 0x00000000, 0x10264800, 0x00000000,
4264};
4265
4266static const uint32_t GPR64_with_sub_32_in_GPRMM16ZeroSubClassMask[] = {
4267 0x00000000, 0x113c3000, 0x00000000,
4268};
4269
4270static const uint32_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {
4271 0x00000000, 0x01382000, 0x00000000,
4272};
4273
4274static const uint32_t GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSubClassMask[] = {
4275 0x00000000, 0x00224000, 0x00000000,
4276};
4277
4278static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePPairSecondSubClassMask[] = {
4279 0x00000000, 0x01088000, 0x00000000,
4280};
4281
4282static const uint32_t ACC64DSPSubClassMask[] = {
4283 0x00000000, 0x02010000, 0x00000000,
4284 0x00000000, 0x00000000, 0x00000020, // sub_32_sub_hi_then_sub_32
4285};
4286
4287static const uint32_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSubClassMask[] = {
4288 0x00000000, 0x00220000, 0x00000000,
4289};
4290
4291static const uint32_t GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSubClassMask[] = {
4292 0x00000000, 0x10240000, 0x00000000,
4293};
4294
4295static const uint32_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask[] = {
4296 0x00000000, 0x01080000, 0x00000000,
4297};
4298
4299static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePPairFirstSubClassMask[] = {
4300 0x00000000, 0x01100000, 0x00000000,
4301};
4302
4303static const uint32_t GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {
4304 0x00000000, 0x00200000, 0x00000000,
4305};
4306
4307static const uint32_t OCTEON_MPLSubClassMask[] = {
4308 0x00000000, 0x00400000, 0x00000000,
4309};
4310
4311static const uint32_t OCTEON_PSubClassMask[] = {
4312 0x00000000, 0x00800000, 0x00000000,
4313};
4314
4315static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask[] = {
4316 0x00000000, 0x01000000, 0x00000000,
4317};
4318
4319static const uint32_t ACC64SubClassMask[] = {
4320 0x00000000, 0x02000000, 0x00000000,
4321 0x00000000, 0x00000000, 0x00000020, // sub_32_sub_hi_then_sub_32
4322};
4323
4324static const uint32_t GP64SubClassMask[] = {
4325 0x00000000, 0x04000000, 0x00000000,
4326};
4327
4328static const uint32_t GPR64_with_sub_32_in_CPURARegSubClassMask[] = {
4329 0x00000000, 0x08000000, 0x00000000,
4330};
4331
4332static const uint32_t GPR64_with_sub_32_in_GPR32ZEROSubClassMask[] = {
4333 0x00000000, 0x10000000, 0x00000000,
4334};
4335
4336static const uint32_t HI64SubClassMask[] = {
4337 0x00000000, 0x20000000, 0x00000000,
4338 0x00000000, 0x00000000, 0x00000020, // sub_hi
4339};
4340
4341static const uint32_t LO64SubClassMask[] = {
4342 0x00000000, 0x40000000, 0x00000000,
4343 0x00000000, 0x00000000, 0x00000020, // sub_lo
4344};
4345
4346static const uint32_t SP64SubClassMask[] = {
4347 0x00000000, 0x80000000, 0x00000000,
4348};
4349
4350static const uint32_t MSA128BSubClassMask[] = {
4351 0x00000000, 0x00000000, 0x0000001f,
4352};
4353
4354static const uint32_t MSA128DSubClassMask[] = {
4355 0x00000000, 0x00000000, 0x0000001f,
4356};
4357
4358static const uint32_t MSA128HSubClassMask[] = {
4359 0x00000000, 0x00000000, 0x0000001f,
4360};
4361
4362static const uint32_t MSA128WSubClassMask[] = {
4363 0x00000000, 0x00000000, 0x0000001f,
4364};
4365
4366static const uint32_t MSA128WEvensSubClassMask[] = {
4367 0x00000000, 0x00000000, 0x00000010,
4368};
4369
4370static const uint32_t ACC128SubClassMask[] = {
4371 0x00000000, 0x00000000, 0x00000020,
4372};
4373
4374static const uint16_t SuperRegIdxSeqs[] = {
4375 /* 0 */ 1, 0,
4376 /* 2 */ 2, 0,
4377 /* 4 */ 8, 0,
4378 /* 6 */ 1, 9, 0,
4379 /* 9 */ 8, 9, 0,
4380 /* 12 */ 1, 8, 10, 0,
4381 /* 16 */ 11, 0,
4382};
4383
4384static unsigned const FGR32Superclasses[] = {
4385 Mips::FGRCCRegClassID,
4386};
4387
4388static unsigned const FGRCCSuperclasses[] = {
4389 Mips::FGR32RegClassID,
4390};
4391
4392static unsigned const GPR32Superclasses[] = {
4393 Mips::DSPRRegClassID,
4394};
4395
4396static unsigned const GPR32NONZEROSuperclasses[] = {
4397 Mips::DSPRRegClassID,
4398 Mips::GPR32RegClassID,
4399};
4400
4401static unsigned const CPU16RegsPlusSPSuperclasses[] = {
4402 Mips::DSPRRegClassID,
4403 Mips::GPR32RegClassID,
4404 Mips::GPR32NONZERORegClassID,
4405};
4406
4407static unsigned const CPU16RegsSuperclasses[] = {
4408 Mips::DSPRRegClassID,
4409 Mips::GPR32RegClassID,
4410 Mips::GPR32NONZERORegClassID,
4411 Mips::CPU16RegsPlusSPRegClassID,
4412};
4413
4414static unsigned const GPRMM16Superclasses[] = {
4415 Mips::DSPRRegClassID,
4416 Mips::GPR32RegClassID,
4417 Mips::GPR32NONZERORegClassID,
4418 Mips::CPU16RegsPlusSPRegClassID,
4419 Mips::CPU16RegsRegClassID,
4420};
4421
4422static unsigned const GPRMM16MovePSuperclasses[] = {
4423 Mips::DSPRRegClassID,
4424 Mips::GPR32RegClassID,
4425};
4426
4427static unsigned const GPRMM16ZeroSuperclasses[] = {
4428 Mips::DSPRRegClassID,
4429 Mips::GPR32RegClassID,
4430};
4431
4432static unsigned const CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {
4433 Mips::DSPRRegClassID,
4434 Mips::GPR32RegClassID,
4435 Mips::GPR32NONZERORegClassID,
4436 Mips::CPU16RegsPlusSPRegClassID,
4437 Mips::CPU16RegsRegClassID,
4438 Mips::GPRMM16RegClassID,
4439 Mips::GPRMM16ZeroRegClassID,
4440};
4441
4442static unsigned const GPR32NONZERO_and_GPRMM16MovePSuperclasses[] = {
4443 Mips::DSPRRegClassID,
4444 Mips::GPR32RegClassID,
4445 Mips::GPR32NONZERORegClassID,
4446 Mips::GPRMM16MovePRegClassID,
4447};
4448
4449static unsigned const GPRMM16MovePPairSecondSuperclasses[] = {
4450 Mips::DSPRRegClassID,
4451 Mips::GPR32RegClassID,
4452 Mips::GPR32NONZERORegClassID,
4453};
4454
4455static unsigned const CPU16Regs_and_GPRMM16MovePSuperclasses[] = {
4456 Mips::DSPRRegClassID,
4457 Mips::GPR32RegClassID,
4458 Mips::GPR32NONZERORegClassID,
4459 Mips::CPU16RegsPlusSPRegClassID,
4460 Mips::CPU16RegsRegClassID,
4461 Mips::GPRMM16RegClassID,
4462 Mips::GPRMM16MovePRegClassID,
4463 Mips::GPR32NONZERO_and_GPRMM16MovePRegClassID,
4464};
4465
4466static unsigned const GPRMM16MoveP_and_GPRMM16ZeroSuperclasses[] = {
4467 Mips::DSPRRegClassID,
4468 Mips::GPR32RegClassID,
4469 Mips::GPRMM16MovePRegClassID,
4470 Mips::GPRMM16ZeroRegClassID,
4471};
4472
4473static unsigned const CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses[] = {
4474 Mips::DSPRRegClassID,
4475 Mips::GPR32RegClassID,
4476 Mips::GPR32NONZERORegClassID,
4477 Mips::CPU16RegsPlusSPRegClassID,
4478 Mips::CPU16RegsRegClassID,
4479 Mips::GPRMM16RegClassID,
4480 Mips::GPRMM16ZeroRegClassID,
4481 Mips::CPU16Regs_and_GPRMM16ZeroRegClassID,
4482 Mips::GPRMM16MovePPairSecondRegClassID,
4483};
4484
4485static unsigned const GPRMM16MovePPairFirstSuperclasses[] = {
4486 Mips::DSPRRegClassID,
4487 Mips::GPR32RegClassID,
4488 Mips::GPR32NONZERORegClassID,
4489 Mips::CPU16RegsPlusSPRegClassID,
4490 Mips::CPU16RegsRegClassID,
4491 Mips::GPRMM16RegClassID,
4492 Mips::GPRMM16ZeroRegClassID,
4493 Mips::CPU16Regs_and_GPRMM16ZeroRegClassID,
4494};
4495
4496static unsigned const GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {
4497 Mips::DSPRRegClassID,
4498 Mips::GPR32RegClassID,
4499 Mips::GPR32NONZERORegClassID,
4500 Mips::CPU16RegsPlusSPRegClassID,
4501 Mips::CPU16RegsRegClassID,
4502 Mips::GPRMM16RegClassID,
4503 Mips::GPRMM16MovePRegClassID,
4504 Mips::GPRMM16ZeroRegClassID,
4505 Mips::CPU16Regs_and_GPRMM16ZeroRegClassID,
4506 Mips::GPR32NONZERO_and_GPRMM16MovePRegClassID,
4507 Mips::CPU16Regs_and_GPRMM16MovePRegClassID,
4508 Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClassID,
4509};
4510
4511static unsigned const GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses[] = {
4512 Mips::DSPRRegClassID,
4513 Mips::GPR32RegClassID,
4514 Mips::GPR32NONZERORegClassID,
4515 Mips::CPU16RegsPlusSPRegClassID,
4516 Mips::CPU16RegsRegClassID,
4517 Mips::GPRMM16RegClassID,
4518 Mips::GPRMM16ZeroRegClassID,
4519 Mips::CPU16Regs_and_GPRMM16ZeroRegClassID,
4520 Mips::GPRMM16MovePPairSecondRegClassID,
4521 Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClassID,
4522 Mips::GPRMM16MovePPairFirstRegClassID,
4523};
4524
4525static unsigned const CPURARegSuperclasses[] = {
4526 Mips::DSPRRegClassID,
4527 Mips::GPR32RegClassID,
4528 Mips::GPR32NONZERORegClassID,
4529};
4530
4531static unsigned const CPUSPRegSuperclasses[] = {
4532 Mips::DSPRRegClassID,
4533 Mips::GPR32RegClassID,
4534 Mips::GPR32NONZERORegClassID,
4535 Mips::CPU16RegsPlusSPRegClassID,
4536};
4537
4538static unsigned const GP32Superclasses[] = {
4539 Mips::DSPRRegClassID,
4540 Mips::GPR32RegClassID,
4541 Mips::GPR32NONZERORegClassID,
4542};
4543
4544static unsigned const GPR32ZEROSuperclasses[] = {
4545 Mips::DSPRRegClassID,
4546 Mips::GPR32RegClassID,
4547 Mips::GPRMM16MovePRegClassID,
4548 Mips::GPRMM16ZeroRegClassID,
4549 Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClassID,
4550};
4551
4552static unsigned const HI32Superclasses[] = {
4553 Mips::HI32DSPRegClassID,
4554};
4555
4556static unsigned const LO32Superclasses[] = {
4557 Mips::LO32DSPRegClassID,
4558};
4559
4560static unsigned const SP32Superclasses[] = {
4561 Mips::DSPRRegClassID,
4562 Mips::GPR32RegClassID,
4563 Mips::GPR32NONZERORegClassID,
4564 Mips::CPU16RegsPlusSPRegClassID,
4565 Mips::CPUSPRegRegClassID,
4566};
4567
4568static unsigned const GPR64_with_sub_32_in_GPR32NONZEROSuperclasses[] = {
4569 Mips::GPR64RegClassID,
4570};
4571
4572static unsigned const GPR64_with_sub_32_in_CPU16RegsPlusSPSuperclasses[] = {
4573 Mips::GPR64RegClassID,
4574 Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
4575};
4576
4577static unsigned const GPR64_with_sub_32_in_CPU16RegsSuperclasses[] = {
4578 Mips::GPR64RegClassID,
4579 Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
4580 Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID,
4581};
4582
4583static unsigned const GPR64_with_sub_32_in_GPRMM16MovePSuperclasses[] = {
4584 Mips::GPR64RegClassID,
4585};
4586
4587static unsigned const GPR64_with_sub_32_in_GPRMM16ZeroSuperclasses[] = {
4588 Mips::GPR64RegClassID,
4589};
4590
4591static unsigned const GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {
4592 Mips::GPR64RegClassID,
4593 Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
4594 Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID,
4595 Mips::GPR64_with_sub_32_in_CPU16RegsRegClassID,
4596 Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClassID,
4597};
4598
4599static unsigned const GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSuperclasses[] = {
4600 Mips::GPR64RegClassID,
4601 Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
4602 Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClassID,
4603};
4604
4605static unsigned const GPR64_with_sub_32_in_GPRMM16MovePPairSecondSuperclasses[] = {
4606 Mips::GPR64RegClassID,
4607 Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
4608};
4609
4610static unsigned const GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSuperclasses[] = {
4611 Mips::GPR64RegClassID,
4612 Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
4613 Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID,
4614 Mips::GPR64_with_sub_32_in_CPU16RegsRegClassID,
4615 Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClassID,
4616 Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID,
4617};
4618
4619static unsigned const GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSuperclasses[] = {
4620 Mips::GPR64RegClassID,
4621 Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClassID,
4622 Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClassID,
4623};
4624
4625static unsigned const GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses[] = {
4626 Mips::GPR64RegClassID,
4627 Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
4628 Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID,
4629 Mips::GPR64_with_sub_32_in_CPU16RegsRegClassID,
4630 Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClassID,
4631 Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID,
4632 Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClassID,
4633};
4634
4635static unsigned const GPR64_with_sub_32_in_GPRMM16MovePPairFirstSuperclasses[] = {
4636 Mips::GPR64RegClassID,
4637 Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
4638 Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID,
4639 Mips::GPR64_with_sub_32_in_CPU16RegsRegClassID,
4640 Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClassID,
4641 Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID,
4642};
4643
4644static unsigned const GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {
4645 Mips::GPR64RegClassID,
4646 Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
4647 Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID,
4648 Mips::GPR64_with_sub_32_in_CPU16RegsRegClassID,
4649 Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClassID,
4650 Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClassID,
4651 Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID,
4652 Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID,
4653 Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID,
4654 Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID,
4655};
4656
4657static unsigned const GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses[] = {
4658 Mips::GPR64RegClassID,
4659 Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
4660 Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID,
4661 Mips::GPR64_with_sub_32_in_CPU16RegsRegClassID,
4662 Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClassID,
4663 Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID,
4664 Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClassID,
4665 Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClassID,
4666 Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClassID,
4667};
4668
4669static unsigned const ACC64Superclasses[] = {
4670 Mips::ACC64DSPRegClassID,
4671};
4672
4673static unsigned const GP64Superclasses[] = {
4674 Mips::GPR64RegClassID,
4675 Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
4676};
4677
4678static unsigned const GPR64_with_sub_32_in_CPURARegSuperclasses[] = {
4679 Mips::GPR64RegClassID,
4680 Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
4681};
4682
4683static unsigned const GPR64_with_sub_32_in_GPR32ZEROSuperclasses[] = {
4684 Mips::GPR64RegClassID,
4685 Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClassID,
4686 Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClassID,
4687 Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID,
4688};
4689
4690static unsigned const SP64Superclasses[] = {
4691 Mips::GPR64RegClassID,
4692 Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
4693 Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID,
4694};
4695
4696static unsigned const MSA128BSuperclasses[] = {
4697 Mips::MSA128F16RegClassID,
4698 Mips::MSA128DRegClassID,
4699 Mips::MSA128HRegClassID,
4700 Mips::MSA128WRegClassID,
4701};
4702
4703static unsigned const MSA128DSuperclasses[] = {
4704 Mips::MSA128F16RegClassID,
4705 Mips::MSA128BRegClassID,
4706 Mips::MSA128HRegClassID,
4707 Mips::MSA128WRegClassID,
4708};
4709
4710static unsigned const MSA128HSuperclasses[] = {
4711 Mips::MSA128F16RegClassID,
4712 Mips::MSA128BRegClassID,
4713 Mips::MSA128DRegClassID,
4714 Mips::MSA128WRegClassID,
4715};
4716
4717static unsigned const MSA128WSuperclasses[] = {
4718 Mips::MSA128F16RegClassID,
4719 Mips::MSA128BRegClassID,
4720 Mips::MSA128DRegClassID,
4721 Mips::MSA128HRegClassID,
4722};
4723
4724static unsigned const MSA128WEvensSuperclasses[] = {
4725 Mips::MSA128F16RegClassID,
4726 Mips::MSA128BRegClassID,
4727 Mips::MSA128DRegClassID,
4728 Mips::MSA128HRegClassID,
4729 Mips::MSA128WRegClassID,
4730};
4731
4732
4733static inline unsigned FGR32AltOrderSelect(const MachineFunction &MF, bool Rev) {
4734 const auto & S = MF.getSubtarget<MipsSubtarget>();
4735 return S.isABI_O32() && !S.useOddSPReg();
4736 }
4737
4738static ArrayRef<MCPhysReg> FGR32GetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
4739 static const MCPhysReg AltOrder1[] = { Mips::F0, Mips::F2, Mips::F4, Mips::F6, Mips::F8, Mips::F10, Mips::F12, Mips::F14, Mips::F16, Mips::F18, Mips::F20, Mips::F22, Mips::F24, Mips::F26, Mips::F28, Mips::F30 };
4740 const MCRegisterClass &MCR = MipsMCRegisterClasses[Mips::FGR32RegClassID];
4741 const ArrayRef<MCPhysReg> Order[] = {
4742 ArrayRef(MCR.begin(), MCR.getNumRegs()),
4743 ArrayRef(AltOrder1)
4744 };
4745 const unsigned Select = FGR32AltOrderSelect(MF, Rev);
4746 assert(Select < 2);
4747 return Order[Select];
4748}
4749
4750static inline unsigned FGR64AltOrderSelect(const MachineFunction &MF, bool Rev) {
4751 const auto & S = MF.getSubtarget<MipsSubtarget>();
4752 return S.isABI_O32() && !S.useOddSPReg();
4753 }
4754
4755static ArrayRef<MCPhysReg> FGR64GetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
4756 static const MCPhysReg AltOrder1[] = { Mips::D0_64, Mips::D2_64, Mips::D4_64, Mips::D6_64, Mips::D8_64, Mips::D10_64, Mips::D12_64, Mips::D14_64, Mips::D16_64, Mips::D18_64, Mips::D20_64, Mips::D22_64, Mips::D24_64, Mips::D26_64, Mips::D28_64, Mips::D30_64 };
4757 const MCRegisterClass &MCR = MipsMCRegisterClasses[Mips::FGR64RegClassID];
4758 const ArrayRef<MCPhysReg> Order[] = {
4759 ArrayRef(MCR.begin(), MCR.getNumRegs()),
4760 ArrayRef(AltOrder1)
4761 };
4762 const unsigned Select = FGR64AltOrderSelect(MF, Rev);
4763 assert(Select < 2);
4764 return Order[Select];
4765}
4766
4767namespace Mips { // Register class instances
4768 extern const TargetRegisterClass MSA128F16RegClass = {
4769 &MipsMCRegisterClasses[MSA128F16RegClassID],
4770 MSA128F16SubClassMask,
4771 SuperRegIdxSeqs + 1,
4772 LaneBitmask(0x0000000000000041),
4773 0,
4774 false,
4775 0x00, /* TSFlags */
4776 true, /* HasDisjunctSubRegs */
4777 false, /* CoveredBySubRegs */
4778 nullptr, 0,
4779 nullptr
4780 };
4781
4782 extern const TargetRegisterClass CCRRegClass = {
4783 &MipsMCRegisterClasses[CCRRegClassID],
4784 CCRSubClassMask,
4785 SuperRegIdxSeqs + 1,
4786 LaneBitmask(0x0000000000000001),
4787 0,
4788 false,
4789 0x00, /* TSFlags */
4790 false, /* HasDisjunctSubRegs */
4791 false, /* CoveredBySubRegs */
4792 nullptr, 0,
4793 nullptr
4794 };
4795
4796 extern const TargetRegisterClass COP0RegClass = {
4797 &MipsMCRegisterClasses[COP0RegClassID],
4798 COP0SubClassMask,
4799 SuperRegIdxSeqs + 1,
4800 LaneBitmask(0x0000000000000001),
4801 0,
4802 false,
4803 0x00, /* TSFlags */
4804 false, /* HasDisjunctSubRegs */
4805 false, /* CoveredBySubRegs */
4806 nullptr, 0,
4807 nullptr
4808 };
4809
4810 extern const TargetRegisterClass COP2RegClass = {
4811 &MipsMCRegisterClasses[COP2RegClassID],
4812 COP2SubClassMask,
4813 SuperRegIdxSeqs + 1,
4814 LaneBitmask(0x0000000000000001),
4815 0,
4816 false,
4817 0x00, /* TSFlags */
4818 false, /* HasDisjunctSubRegs */
4819 false, /* CoveredBySubRegs */
4820 nullptr, 0,
4821 nullptr
4822 };
4823
4824 extern const TargetRegisterClass COP3RegClass = {
4825 &MipsMCRegisterClasses[COP3RegClassID],
4826 COP3SubClassMask,
4827 SuperRegIdxSeqs + 1,
4828 LaneBitmask(0x0000000000000001),
4829 0,
4830 false,
4831 0x00, /* TSFlags */
4832 false, /* HasDisjunctSubRegs */
4833 false, /* CoveredBySubRegs */
4834 nullptr, 0,
4835 nullptr
4836 };
4837
4838 extern const TargetRegisterClass DSPRRegClass = {
4839 &MipsMCRegisterClasses[DSPRRegClassID],
4840 DSPRSubClassMask,
4841 SuperRegIdxSeqs + 0,
4842 LaneBitmask(0x0000000000000001),
4843 0,
4844 false,
4845 0x00, /* TSFlags */
4846 false, /* HasDisjunctSubRegs */
4847 false, /* CoveredBySubRegs */
4848 nullptr, 0,
4849 nullptr
4850 };
4851
4852 extern const TargetRegisterClass FGR32RegClass = {
4853 &MipsMCRegisterClasses[FGR32RegClassID],
4854 FGR32SubClassMask,
4855 SuperRegIdxSeqs + 9,
4856 LaneBitmask(0x0000000000000001),
4857 0,
4858 false,
4859 0x00, /* TSFlags */
4860 false, /* HasDisjunctSubRegs */
4861 false, /* CoveredBySubRegs */
4862 FGR32Superclasses, 1,
4863 FGR32GetRawAllocationOrder
4864 };
4865
4866 extern const TargetRegisterClass FGRCCRegClass = {
4867 &MipsMCRegisterClasses[FGRCCRegClassID],
4868 FGRCCSubClassMask,
4869 SuperRegIdxSeqs + 9,
4870 LaneBitmask(0x0000000000000001),
4871 0,
4872 false,
4873 0x00, /* TSFlags */
4874 false, /* HasDisjunctSubRegs */
4875 false, /* CoveredBySubRegs */
4876 FGRCCSuperclasses, 1,
4877 nullptr
4878 };
4879
4880 extern const TargetRegisterClass GPR32RegClass = {
4881 &MipsMCRegisterClasses[GPR32RegClassID],
4882 GPR32SubClassMask,
4883 SuperRegIdxSeqs + 0,
4884 LaneBitmask(0x0000000000000001),
4885 0,
4886 false,
4887 0x00, /* TSFlags */
4888 false, /* HasDisjunctSubRegs */
4889 false, /* CoveredBySubRegs */
4890 GPR32Superclasses, 1,
4891 nullptr
4892 };
4893
4894 extern const TargetRegisterClass HWRegsRegClass = {
4895 &MipsMCRegisterClasses[HWRegsRegClassID],
4896 HWRegsSubClassMask,
4897 SuperRegIdxSeqs + 1,
4898 LaneBitmask(0x0000000000000001),
4899 0,
4900 false,
4901 0x00, /* TSFlags */
4902 false, /* HasDisjunctSubRegs */
4903 false, /* CoveredBySubRegs */
4904 nullptr, 0,
4905 nullptr
4906 };
4907
4908 extern const TargetRegisterClass MSACtrlRegClass = {
4909 &MipsMCRegisterClasses[MSACtrlRegClassID],
4910 MSACtrlSubClassMask,
4911 SuperRegIdxSeqs + 1,
4912 LaneBitmask(0x0000000000000001),
4913 0,
4914 false,
4915 0x00, /* TSFlags */
4916 false, /* HasDisjunctSubRegs */
4917 false, /* CoveredBySubRegs */
4918 nullptr, 0,
4919 nullptr
4920 };
4921
4922 extern const TargetRegisterClass GPR32NONZERORegClass = {
4923 &MipsMCRegisterClasses[GPR32NONZERORegClassID],
4924 GPR32NONZEROSubClassMask,
4925 SuperRegIdxSeqs + 0,
4926 LaneBitmask(0x0000000000000001),
4927 0,
4928 false,
4929 0x00, /* TSFlags */
4930 false, /* HasDisjunctSubRegs */
4931 false, /* CoveredBySubRegs */
4932 GPR32NONZEROSuperclasses, 2,
4933 nullptr
4934 };
4935
4936 extern const TargetRegisterClass CPU16RegsPlusSPRegClass = {
4937 &MipsMCRegisterClasses[CPU16RegsPlusSPRegClassID],
4938 CPU16RegsPlusSPSubClassMask,
4939 SuperRegIdxSeqs + 0,
4940 LaneBitmask(0x0000000000000001),
4941 0,
4942 false,
4943 0x00, /* TSFlags */
4944 false, /* HasDisjunctSubRegs */
4945 false, /* CoveredBySubRegs */
4946 CPU16RegsPlusSPSuperclasses, 3,
4947 nullptr
4948 };
4949
4950 extern const TargetRegisterClass CPU16RegsRegClass = {
4951 &MipsMCRegisterClasses[CPU16RegsRegClassID],
4952 CPU16RegsSubClassMask,
4953 SuperRegIdxSeqs + 0,
4954 LaneBitmask(0x0000000000000001),
4955 0,
4956 false,
4957 0x00, /* TSFlags */
4958 false, /* HasDisjunctSubRegs */
4959 false, /* CoveredBySubRegs */
4960 CPU16RegsSuperclasses, 4,
4961 nullptr
4962 };
4963
4964 extern const TargetRegisterClass FCCRegClass = {
4965 &MipsMCRegisterClasses[FCCRegClassID],
4966 FCCSubClassMask,
4967 SuperRegIdxSeqs + 1,
4968 LaneBitmask(0x0000000000000001),
4969 0,
4970 false,
4971 0x00, /* TSFlags */
4972 false, /* HasDisjunctSubRegs */
4973 false, /* CoveredBySubRegs */
4974 nullptr, 0,
4975 nullptr
4976 };
4977
4978 extern const TargetRegisterClass GPRMM16RegClass = {
4979 &MipsMCRegisterClasses[GPRMM16RegClassID],
4980 GPRMM16SubClassMask,
4981 SuperRegIdxSeqs + 0,
4982 LaneBitmask(0x0000000000000001),
4983 0,
4984 false,
4985 0x00, /* TSFlags */
4986 false, /* HasDisjunctSubRegs */
4987 false, /* CoveredBySubRegs */
4988 GPRMM16Superclasses, 5,
4989 nullptr
4990 };
4991
4992 extern const TargetRegisterClass GPRMM16MovePRegClass = {
4993 &MipsMCRegisterClasses[GPRMM16MovePRegClassID],
4994 GPRMM16MovePSubClassMask,
4995 SuperRegIdxSeqs + 0,
4996 LaneBitmask(0x0000000000000001),
4997 0,
4998 false,
4999 0x00, /* TSFlags */
5000 false, /* HasDisjunctSubRegs */
5001 false, /* CoveredBySubRegs */
5002 GPRMM16MovePSuperclasses, 2,
5003 nullptr
5004 };
5005
5006 extern const TargetRegisterClass GPRMM16ZeroRegClass = {
5007 &MipsMCRegisterClasses[GPRMM16ZeroRegClassID],
5008 GPRMM16ZeroSubClassMask,
5009 SuperRegIdxSeqs + 0,
5010 LaneBitmask(0x0000000000000001),
5011 0,
5012 false,
5013 0x00, /* TSFlags */
5014 false, /* HasDisjunctSubRegs */
5015 false, /* CoveredBySubRegs */
5016 GPRMM16ZeroSuperclasses, 2,
5017 nullptr
5018 };
5019
5020 extern const TargetRegisterClass CPU16Regs_and_GPRMM16ZeroRegClass = {
5021 &MipsMCRegisterClasses[CPU16Regs_and_GPRMM16ZeroRegClassID],
5022 CPU16Regs_and_GPRMM16ZeroSubClassMask,
5023 SuperRegIdxSeqs + 0,
5024 LaneBitmask(0x0000000000000001),
5025 0,
5026 false,
5027 0x00, /* TSFlags */
5028 false, /* HasDisjunctSubRegs */
5029 false, /* CoveredBySubRegs */
5030 CPU16Regs_and_GPRMM16ZeroSuperclasses, 7,
5031 nullptr
5032 };
5033
5034 extern const TargetRegisterClass GPR32NONZERO_and_GPRMM16MovePRegClass = {
5035 &MipsMCRegisterClasses[GPR32NONZERO_and_GPRMM16MovePRegClassID],
5036 GPR32NONZERO_and_GPRMM16MovePSubClassMask,
5037 SuperRegIdxSeqs + 0,
5038 LaneBitmask(0x0000000000000001),
5039 0,
5040 false,
5041 0x00, /* TSFlags */
5042 false, /* HasDisjunctSubRegs */
5043 false, /* CoveredBySubRegs */
5044 GPR32NONZERO_and_GPRMM16MovePSuperclasses, 4,
5045 nullptr
5046 };
5047
5048 extern const TargetRegisterClass GPRMM16MovePPairSecondRegClass = {
5049 &MipsMCRegisterClasses[GPRMM16MovePPairSecondRegClassID],
5050 GPRMM16MovePPairSecondSubClassMask,
5051 SuperRegIdxSeqs + 0,
5052 LaneBitmask(0x0000000000000001),
5053 0,
5054 false,
5055 0x00, /* TSFlags */
5056 false, /* HasDisjunctSubRegs */
5057 false, /* CoveredBySubRegs */
5058 GPRMM16MovePPairSecondSuperclasses, 3,
5059 nullptr
5060 };
5061
5062 extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePRegClass = {
5063 &MipsMCRegisterClasses[CPU16Regs_and_GPRMM16MovePRegClassID],
5064 CPU16Regs_and_GPRMM16MovePSubClassMask,
5065 SuperRegIdxSeqs + 0,
5066 LaneBitmask(0x0000000000000001),
5067 0,
5068 false,
5069 0x00, /* TSFlags */
5070 false, /* HasDisjunctSubRegs */
5071 false, /* CoveredBySubRegs */
5072 CPU16Regs_and_GPRMM16MovePSuperclasses, 8,
5073 nullptr
5074 };
5075
5076 extern const TargetRegisterClass GPRMM16MoveP_and_GPRMM16ZeroRegClass = {
5077 &MipsMCRegisterClasses[GPRMM16MoveP_and_GPRMM16ZeroRegClassID],
5078 GPRMM16MoveP_and_GPRMM16ZeroSubClassMask,
5079 SuperRegIdxSeqs + 0,
5080 LaneBitmask(0x0000000000000001),
5081 0,
5082 false,
5083 0x00, /* TSFlags */
5084 false, /* HasDisjunctSubRegs */
5085 false, /* CoveredBySubRegs */
5086 GPRMM16MoveP_and_GPRMM16ZeroSuperclasses, 4,
5087 nullptr
5088 };
5089
5090 extern const TargetRegisterClass HI32DSPRegClass = {
5091 &MipsMCRegisterClasses[HI32DSPRegClassID],
5092 HI32DSPSubClassMask,
5093 SuperRegIdxSeqs + 12,
5094 LaneBitmask(0x0000000000000001),
5095 0,
5096 false,
5097 0x00, /* TSFlags */
5098 false, /* HasDisjunctSubRegs */
5099 false, /* CoveredBySubRegs */
5100 nullptr, 0,
5101 nullptr
5102 };
5103
5104 extern const TargetRegisterClass LO32DSPRegClass = {
5105 &MipsMCRegisterClasses[LO32DSPRegClassID],
5106 LO32DSPSubClassMask,
5107 SuperRegIdxSeqs + 6,
5108 LaneBitmask(0x0000000000000001),
5109 0,
5110 false,
5111 0x00, /* TSFlags */
5112 false, /* HasDisjunctSubRegs */
5113 false, /* CoveredBySubRegs */
5114 nullptr, 0,
5115 nullptr
5116 };
5117
5118 extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePPairSecondRegClass = {
5119 &MipsMCRegisterClasses[CPU16Regs_and_GPRMM16MovePPairSecondRegClassID],
5120 CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask,
5121 SuperRegIdxSeqs + 0,
5122 LaneBitmask(0x0000000000000001),
5123 0,
5124 false,
5125 0x00, /* TSFlags */
5126 false, /* HasDisjunctSubRegs */
5127 false, /* CoveredBySubRegs */
5128 CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses, 9,
5129 nullptr
5130 };
5131
5132 extern const TargetRegisterClass GPRMM16MovePPairFirstRegClass = {
5133 &MipsMCRegisterClasses[GPRMM16MovePPairFirstRegClassID],
5134 GPRMM16MovePPairFirstSubClassMask,
5135 SuperRegIdxSeqs + 0,
5136 LaneBitmask(0x0000000000000001),
5137 0,
5138 false,
5139 0x00, /* TSFlags */
5140 false, /* HasDisjunctSubRegs */
5141 false, /* CoveredBySubRegs */
5142 GPRMM16MovePPairFirstSuperclasses, 8,
5143 nullptr
5144 };
5145
5146 extern const TargetRegisterClass GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass = {
5147 &MipsMCRegisterClasses[GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID],
5148 GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask,
5149 SuperRegIdxSeqs + 0,
5150 LaneBitmask(0x0000000000000001),
5151 0,
5152 false,
5153 0x00, /* TSFlags */
5154 false, /* HasDisjunctSubRegs */
5155 false, /* CoveredBySubRegs */
5156 GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses, 12,
5157 nullptr
5158 };
5159
5160 extern const TargetRegisterClass GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass = {
5161 &MipsMCRegisterClasses[GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID],
5162 GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask,
5163 SuperRegIdxSeqs + 0,
5164 LaneBitmask(0x0000000000000001),
5165 0,
5166 false,
5167 0x00, /* TSFlags */
5168 false, /* HasDisjunctSubRegs */
5169 false, /* CoveredBySubRegs */
5170 GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses, 11,
5171 nullptr
5172 };
5173
5174 extern const TargetRegisterClass CPURARegRegClass = {
5175 &MipsMCRegisterClasses[CPURARegRegClassID],
5176 CPURARegSubClassMask,
5177 SuperRegIdxSeqs + 0,
5178 LaneBitmask(0x0000000000000001),
5179 0,
5180 false,
5181 0x00, /* TSFlags */
5182 false, /* HasDisjunctSubRegs */
5183 false, /* CoveredBySubRegs */
5184 CPURARegSuperclasses, 3,
5185 nullptr
5186 };
5187
5188 extern const TargetRegisterClass CPUSPRegRegClass = {
5189 &MipsMCRegisterClasses[CPUSPRegRegClassID],
5190 CPUSPRegSubClassMask,
5191 SuperRegIdxSeqs + 0,
5192 LaneBitmask(0x0000000000000001),
5193 0,
5194 false,
5195 0x00, /* TSFlags */
5196 false, /* HasDisjunctSubRegs */
5197 false, /* CoveredBySubRegs */
5198 CPUSPRegSuperclasses, 4,
5199 nullptr
5200 };
5201
5202 extern const TargetRegisterClass DSPCCRegClass = {
5203 &MipsMCRegisterClasses[DSPCCRegClassID],
5204 DSPCCSubClassMask,
5205 SuperRegIdxSeqs + 1,
5206 LaneBitmask(0x0000000000000001),
5207 0,
5208 false,
5209 0x00, /* TSFlags */
5210 false, /* HasDisjunctSubRegs */
5211 false, /* CoveredBySubRegs */
5212 nullptr, 0,
5213 nullptr
5214 };
5215
5216 extern const TargetRegisterClass GP32RegClass = {
5217 &MipsMCRegisterClasses[GP32RegClassID],
5218 GP32SubClassMask,
5219 SuperRegIdxSeqs + 0,
5220 LaneBitmask(0x0000000000000001),
5221 0,
5222 false,
5223 0x00, /* TSFlags */
5224 false, /* HasDisjunctSubRegs */
5225 false, /* CoveredBySubRegs */
5226 GP32Superclasses, 3,
5227 nullptr
5228 };
5229
5230 extern const TargetRegisterClass GPR32ZERORegClass = {
5231 &MipsMCRegisterClasses[GPR32ZERORegClassID],
5232 GPR32ZEROSubClassMask,
5233 SuperRegIdxSeqs + 0,
5234 LaneBitmask(0x0000000000000001),
5235 0,
5236 false,
5237 0x00, /* TSFlags */
5238 false, /* HasDisjunctSubRegs */
5239 false, /* CoveredBySubRegs */
5240 GPR32ZEROSuperclasses, 5,
5241 nullptr
5242 };
5243
5244 extern const TargetRegisterClass HI32RegClass = {
5245 &MipsMCRegisterClasses[HI32RegClassID],
5246 HI32SubClassMask,
5247 SuperRegIdxSeqs + 12,
5248 LaneBitmask(0x0000000000000001),
5249 0,
5250 false,
5251 0x00, /* TSFlags */
5252 false, /* HasDisjunctSubRegs */
5253 false, /* CoveredBySubRegs */
5254 HI32Superclasses, 1,
5255 nullptr
5256 };
5257
5258 extern const TargetRegisterClass LO32RegClass = {
5259 &MipsMCRegisterClasses[LO32RegClassID],
5260 LO32SubClassMask,
5261 SuperRegIdxSeqs + 6,
5262 LaneBitmask(0x0000000000000001),
5263 0,
5264 false,
5265 0x00, /* TSFlags */
5266 false, /* HasDisjunctSubRegs */
5267 false, /* CoveredBySubRegs */
5268 LO32Superclasses, 1,
5269 nullptr
5270 };
5271
5272 extern const TargetRegisterClass SP32RegClass = {
5273 &MipsMCRegisterClasses[SP32RegClassID],
5274 SP32SubClassMask,
5275 SuperRegIdxSeqs + 0,
5276 LaneBitmask(0x0000000000000001),
5277 0,
5278 false,
5279 0x00, /* TSFlags */
5280 false, /* HasDisjunctSubRegs */
5281 false, /* CoveredBySubRegs */
5282 SP32Superclasses, 5,
5283 nullptr
5284 };
5285
5286 extern const TargetRegisterClass FGR64RegClass = {
5287 &MipsMCRegisterClasses[FGR64RegClassID],
5288 FGR64SubClassMask,
5289 SuperRegIdxSeqs + 2,
5290 LaneBitmask(0x0000000000000041),
5291 0,
5292 false,
5293 0x00, /* TSFlags */
5294 true, /* HasDisjunctSubRegs */
5295 true, /* CoveredBySubRegs */
5296 nullptr, 0,
5297 FGR64GetRawAllocationOrder
5298 };
5299
5300 extern const TargetRegisterClass GPR64RegClass = {
5301 &MipsMCRegisterClasses[GPR64RegClassID],
5302 GPR64SubClassMask,
5303 SuperRegIdxSeqs + 1,
5304 LaneBitmask(0x0000000000000001),
5305 0,
5306 false,
5307 0x00, /* TSFlags */
5308 false, /* HasDisjunctSubRegs */
5309 false, /* CoveredBySubRegs */
5310 nullptr, 0,
5311 nullptr
5312 };
5313
5314 extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERORegClass = {
5315 &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPR32NONZERORegClassID],
5316 GPR64_with_sub_32_in_GPR32NONZEROSubClassMask,
5317 SuperRegIdxSeqs + 1,
5318 LaneBitmask(0x0000000000000001),
5319 0,
5320 false,
5321 0x00, /* TSFlags */
5322 false, /* HasDisjunctSubRegs */
5323 false, /* CoveredBySubRegs */
5324 GPR64_with_sub_32_in_GPR32NONZEROSuperclasses, 1,
5325 nullptr
5326 };
5327
5328 extern const TargetRegisterClass AFGR64RegClass = {
5329 &MipsMCRegisterClasses[AFGR64RegClassID],
5330 AFGR64SubClassMask,
5331 SuperRegIdxSeqs + 1,
5332 LaneBitmask(0x0000000000000041),
5333 0,
5334 false,
5335 0x00, /* TSFlags */
5336 true, /* HasDisjunctSubRegs */
5337 true, /* CoveredBySubRegs */
5338 nullptr, 0,
5339 nullptr
5340 };
5341
5342 extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass = {
5343 &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID],
5344 GPR64_with_sub_32_in_CPU16RegsPlusSPSubClassMask,
5345 SuperRegIdxSeqs + 1,
5346 LaneBitmask(0x0000000000000001),
5347 0,
5348 false,
5349 0x00, /* TSFlags */
5350 false, /* HasDisjunctSubRegs */
5351 false, /* CoveredBySubRegs */
5352 GPR64_with_sub_32_in_CPU16RegsPlusSPSuperclasses, 2,
5353 nullptr
5354 };
5355
5356 extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsRegClass = {
5357 &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16RegsRegClassID],
5358 GPR64_with_sub_32_in_CPU16RegsSubClassMask,
5359 SuperRegIdxSeqs + 1,
5360 LaneBitmask(0x0000000000000001),
5361 0,
5362 false,
5363 0x00, /* TSFlags */
5364 false, /* HasDisjunctSubRegs */
5365 false, /* CoveredBySubRegs */
5366 GPR64_with_sub_32_in_CPU16RegsSuperclasses, 3,
5367 nullptr
5368 };
5369
5370 extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePRegClass = {
5371 &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePRegClassID],
5372 GPR64_with_sub_32_in_GPRMM16MovePSubClassMask,
5373 SuperRegIdxSeqs + 1,
5374 LaneBitmask(0x0000000000000001),
5375 0,
5376 false,
5377 0x00, /* TSFlags */
5378 false, /* HasDisjunctSubRegs */
5379 false, /* CoveredBySubRegs */
5380 GPR64_with_sub_32_in_GPRMM16MovePSuperclasses, 1,
5381 nullptr
5382 };
5383
5384 extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16ZeroRegClass = {
5385 &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16ZeroRegClassID],
5386 GPR64_with_sub_32_in_GPRMM16ZeroSubClassMask,
5387 SuperRegIdxSeqs + 1,
5388 LaneBitmask(0x0000000000000001),
5389 0,
5390 false,
5391 0x00, /* TSFlags */
5392 false, /* HasDisjunctSubRegs */
5393 false, /* CoveredBySubRegs */
5394 GPR64_with_sub_32_in_GPRMM16ZeroSuperclasses, 1,
5395 nullptr
5396 };
5397
5398 extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass = {
5399 &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID],
5400 GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSubClassMask,
5401 SuperRegIdxSeqs + 1,
5402 LaneBitmask(0x0000000000000001),
5403 0,
5404 false,
5405 0x00, /* TSFlags */
5406 false, /* HasDisjunctSubRegs */
5407 false, /* CoveredBySubRegs */
5408 GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSuperclasses, 5,
5409 nullptr
5410 };
5411
5412 extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass = {
5413 &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID],
5414 GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSubClassMask,
5415 SuperRegIdxSeqs + 1,
5416 LaneBitmask(0x0000000000000001),
5417 0,
5418 false,
5419 0x00, /* TSFlags */
5420 false, /* HasDisjunctSubRegs */
5421 false, /* CoveredBySubRegs */
5422 GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSuperclasses, 3,
5423 nullptr
5424 };
5425
5426 extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass = {
5427 &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClassID],
5428 GPR64_with_sub_32_in_GPRMM16MovePPairSecondSubClassMask,
5429 SuperRegIdxSeqs + 1,
5430 LaneBitmask(0x0000000000000001),
5431 0,
5432 false,
5433 0x00, /* TSFlags */
5434 false, /* HasDisjunctSubRegs */
5435 false, /* CoveredBySubRegs */
5436 GPR64_with_sub_32_in_GPRMM16MovePPairSecondSuperclasses, 2,
5437 nullptr
5438 };
5439
5440 extern const TargetRegisterClass ACC64DSPRegClass = {
5441 &MipsMCRegisterClasses[ACC64DSPRegClassID],
5442 ACC64DSPSubClassMask,
5443 SuperRegIdxSeqs + 16,
5444 LaneBitmask(0x0000000000000041),
5445 0,
5446 false,
5447 0x00, /* TSFlags */
5448 true, /* HasDisjunctSubRegs */
5449 true, /* CoveredBySubRegs */
5450 nullptr, 0,
5451 nullptr
5452 };
5453
5454 extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass = {
5455 &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID],
5456 GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSubClassMask,
5457 SuperRegIdxSeqs + 1,
5458 LaneBitmask(0x0000000000000001),
5459 0,
5460 false,
5461 0x00, /* TSFlags */
5462 false, /* HasDisjunctSubRegs */
5463 false, /* CoveredBySubRegs */
5464 GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSuperclasses, 6,
5465 nullptr
5466 };
5467
5468 extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass = {
5469 &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID],
5470 GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSubClassMask,
5471 SuperRegIdxSeqs + 1,
5472 LaneBitmask(0x0000000000000001),
5473 0,
5474 false,
5475 0x00, /* TSFlags */
5476 false, /* HasDisjunctSubRegs */
5477 false, /* CoveredBySubRegs */
5478 GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSuperclasses, 3,
5479 nullptr
5480 };
5481
5482 extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClass = {
5483 &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClassID],
5484 GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask,
5485 SuperRegIdxSeqs + 1,
5486 LaneBitmask(0x0000000000000001),
5487 0,
5488 false,
5489 0x00, /* TSFlags */
5490 false, /* HasDisjunctSubRegs */
5491 false, /* CoveredBySubRegs */
5492 GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses, 7,
5493 nullptr
5494 };
5495
5496 extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClass = {
5497 &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClassID],
5498 GPR64_with_sub_32_in_GPRMM16MovePPairFirstSubClassMask,
5499 SuperRegIdxSeqs + 1,
5500 LaneBitmask(0x0000000000000001),
5501 0,
5502 false,
5503 0x00, /* TSFlags */
5504 false, /* HasDisjunctSubRegs */
5505 false, /* CoveredBySubRegs */
5506 GPR64_with_sub_32_in_GPRMM16MovePPairFirstSuperclasses, 6,
5507 nullptr
5508 };
5509
5510 extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass = {
5511 &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID],
5512 GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask,
5513 SuperRegIdxSeqs + 1,
5514 LaneBitmask(0x0000000000000001),
5515 0,
5516 false,
5517 0x00, /* TSFlags */
5518 false, /* HasDisjunctSubRegs */
5519 false, /* CoveredBySubRegs */
5520 GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses, 10,
5521 nullptr
5522 };
5523
5524 extern const TargetRegisterClass OCTEON_MPLRegClass = {
5525 &MipsMCRegisterClasses[OCTEON_MPLRegClassID],
5526 OCTEON_MPLSubClassMask,
5527 SuperRegIdxSeqs + 1,
5528 LaneBitmask(0x0000000000000001),
5529 0,
5530 false,
5531 0x00, /* TSFlags */
5532 false, /* HasDisjunctSubRegs */
5533 false, /* CoveredBySubRegs */
5534 nullptr, 0,
5535 nullptr
5536 };
5537
5538 extern const TargetRegisterClass OCTEON_PRegClass = {
5539 &MipsMCRegisterClasses[OCTEON_PRegClassID],
5540 OCTEON_PSubClassMask,
5541 SuperRegIdxSeqs + 1,
5542 LaneBitmask(0x0000000000000001),
5543 0,
5544 false,
5545 0x00, /* TSFlags */
5546 false, /* HasDisjunctSubRegs */
5547 false, /* CoveredBySubRegs */
5548 nullptr, 0,
5549 nullptr
5550 };
5551
5552 extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass = {
5553 &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID],
5554 GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask,
5555 SuperRegIdxSeqs + 1,
5556 LaneBitmask(0x0000000000000001),
5557 0,
5558 false,
5559 0x00, /* TSFlags */
5560 false, /* HasDisjunctSubRegs */
5561 false, /* CoveredBySubRegs */
5562 GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses, 9,
5563 nullptr
5564 };
5565
5566 extern const TargetRegisterClass ACC64RegClass = {
5567 &MipsMCRegisterClasses[ACC64RegClassID],
5568 ACC64SubClassMask,
5569 SuperRegIdxSeqs + 16,
5570 LaneBitmask(0x0000000000000041),
5571 0,
5572 false,
5573 0x00, /* TSFlags */
5574 true, /* HasDisjunctSubRegs */
5575 true, /* CoveredBySubRegs */
5576 ACC64Superclasses, 1,
5577 nullptr
5578 };
5579
5580 extern const TargetRegisterClass GP64RegClass = {
5581 &MipsMCRegisterClasses[GP64RegClassID],
5582 GP64SubClassMask,
5583 SuperRegIdxSeqs + 1,
5584 LaneBitmask(0x0000000000000001),
5585 0,
5586 false,
5587 0x00, /* TSFlags */
5588 false, /* HasDisjunctSubRegs */
5589 false, /* CoveredBySubRegs */
5590 GP64Superclasses, 2,
5591 nullptr
5592 };
5593
5594 extern const TargetRegisterClass GPR64_with_sub_32_in_CPURARegRegClass = {
5595 &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPURARegRegClassID],
5596 GPR64_with_sub_32_in_CPURARegSubClassMask,
5597 SuperRegIdxSeqs + 1,
5598 LaneBitmask(0x0000000000000001),
5599 0,
5600 false,
5601 0x00, /* TSFlags */
5602 false, /* HasDisjunctSubRegs */
5603 false, /* CoveredBySubRegs */
5604 GPR64_with_sub_32_in_CPURARegSuperclasses, 2,
5605 nullptr
5606 };
5607
5608 extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32ZERORegClass = {
5609 &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPR32ZERORegClassID],
5610 GPR64_with_sub_32_in_GPR32ZEROSubClassMask,
5611 SuperRegIdxSeqs + 1,
5612 LaneBitmask(0x0000000000000001),
5613 0,
5614 false,
5615 0x00, /* TSFlags */
5616 false, /* HasDisjunctSubRegs */
5617 false, /* CoveredBySubRegs */
5618 GPR64_with_sub_32_in_GPR32ZEROSuperclasses, 4,
5619 nullptr
5620 };
5621
5622 extern const TargetRegisterClass HI64RegClass = {
5623 &MipsMCRegisterClasses[HI64RegClassID],
5624 HI64SubClassMask,
5625 SuperRegIdxSeqs + 4,
5626 LaneBitmask(0x0000000000000001),
5627 0,
5628 false,
5629 0x00, /* TSFlags */
5630 false, /* HasDisjunctSubRegs */
5631 false, /* CoveredBySubRegs */
5632 nullptr, 0,
5633 nullptr
5634 };
5635
5636 extern const TargetRegisterClass LO64RegClass = {
5637 &MipsMCRegisterClasses[LO64RegClassID],
5638 LO64SubClassMask,
5639 SuperRegIdxSeqs + 7,
5640 LaneBitmask(0x0000000000000001),
5641 0,
5642 false,
5643 0x00, /* TSFlags */
5644 false, /* HasDisjunctSubRegs */
5645 false, /* CoveredBySubRegs */
5646 nullptr, 0,
5647 nullptr
5648 };
5649
5650 extern const TargetRegisterClass SP64RegClass = {
5651 &MipsMCRegisterClasses[SP64RegClassID],
5652 SP64SubClassMask,
5653 SuperRegIdxSeqs + 1,
5654 LaneBitmask(0x0000000000000001),
5655 0,
5656 false,
5657 0x00, /* TSFlags */
5658 false, /* HasDisjunctSubRegs */
5659 false, /* CoveredBySubRegs */
5660 SP64Superclasses, 3,
5661 nullptr
5662 };
5663
5664 extern const TargetRegisterClass MSA128BRegClass = {
5665 &MipsMCRegisterClasses[MSA128BRegClassID],
5666 MSA128BSubClassMask,
5667 SuperRegIdxSeqs + 1,
5668 LaneBitmask(0x0000000000000041),
5669 0,
5670 false,
5671 0x00, /* TSFlags */
5672 true, /* HasDisjunctSubRegs */
5673 false, /* CoveredBySubRegs */
5674 MSA128BSuperclasses, 4,
5675 nullptr
5676 };
5677
5678 extern const TargetRegisterClass MSA128DRegClass = {
5679 &MipsMCRegisterClasses[MSA128DRegClassID],
5680 MSA128DSubClassMask,
5681 SuperRegIdxSeqs + 1,
5682 LaneBitmask(0x0000000000000041),
5683 0,
5684 false,
5685 0x00, /* TSFlags */
5686 true, /* HasDisjunctSubRegs */
5687 false, /* CoveredBySubRegs */
5688 MSA128DSuperclasses, 4,
5689 nullptr
5690 };
5691
5692 extern const TargetRegisterClass MSA128HRegClass = {
5693 &MipsMCRegisterClasses[MSA128HRegClassID],
5694 MSA128HSubClassMask,
5695 SuperRegIdxSeqs + 1,
5696 LaneBitmask(0x0000000000000041),
5697 0,
5698 false,
5699 0x00, /* TSFlags */
5700 true, /* HasDisjunctSubRegs */
5701 false, /* CoveredBySubRegs */
5702 MSA128HSuperclasses, 4,
5703 nullptr
5704 };
5705
5706 extern const TargetRegisterClass MSA128WRegClass = {
5707 &MipsMCRegisterClasses[MSA128WRegClassID],
5708 MSA128WSubClassMask,
5709 SuperRegIdxSeqs + 1,
5710 LaneBitmask(0x0000000000000041),
5711 0,
5712 false,
5713 0x00, /* TSFlags */
5714 true, /* HasDisjunctSubRegs */
5715 false, /* CoveredBySubRegs */
5716 MSA128WSuperclasses, 4,
5717 nullptr
5718 };
5719
5720 extern const TargetRegisterClass MSA128WEvensRegClass = {
5721 &MipsMCRegisterClasses[MSA128WEvensRegClassID],
5722 MSA128WEvensSubClassMask,
5723 SuperRegIdxSeqs + 1,
5724 LaneBitmask(0x0000000000000041),
5725 0,
5726 false,
5727 0x00, /* TSFlags */
5728 true, /* HasDisjunctSubRegs */
5729 false, /* CoveredBySubRegs */
5730 MSA128WEvensSuperclasses, 5,
5731 nullptr
5732 };
5733
5734 extern const TargetRegisterClass ACC128RegClass = {
5735 &MipsMCRegisterClasses[ACC128RegClassID],
5736 ACC128SubClassMask,
5737 SuperRegIdxSeqs + 1,
5738 LaneBitmask(0x0000000000000041),
5739 0,
5740 false,
5741 0x00, /* TSFlags */
5742 true, /* HasDisjunctSubRegs */
5743 true, /* CoveredBySubRegs */
5744 nullptr, 0,
5745 nullptr
5746 };
5747
5748} // end namespace Mips
5749
5750namespace {
5751 const TargetRegisterClass *const RegisterClasses[] = {
5752 &Mips::MSA128F16RegClass,
5753 &Mips::CCRRegClass,
5754 &Mips::COP0RegClass,
5755 &Mips::COP2RegClass,
5756 &Mips::COP3RegClass,
5757 &Mips::DSPRRegClass,
5758 &Mips::FGR32RegClass,
5759 &Mips::FGRCCRegClass,
5760 &Mips::GPR32RegClass,
5761 &Mips::HWRegsRegClass,
5762 &Mips::MSACtrlRegClass,
5763 &Mips::GPR32NONZERORegClass,
5764 &Mips::CPU16RegsPlusSPRegClass,
5765 &Mips::CPU16RegsRegClass,
5766 &Mips::FCCRegClass,
5767 &Mips::GPRMM16RegClass,
5768 &Mips::GPRMM16MovePRegClass,
5769 &Mips::GPRMM16ZeroRegClass,
5770 &Mips::CPU16Regs_and_GPRMM16ZeroRegClass,
5771 &Mips::GPR32NONZERO_and_GPRMM16MovePRegClass,
5772 &Mips::GPRMM16MovePPairSecondRegClass,
5773 &Mips::CPU16Regs_and_GPRMM16MovePRegClass,
5774 &Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClass,
5775 &Mips::HI32DSPRegClass,
5776 &Mips::LO32DSPRegClass,
5777 &Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClass,
5778 &Mips::GPRMM16MovePPairFirstRegClass,
5779 &Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass,
5780 &Mips::GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass,
5781 &Mips::CPURARegRegClass,
5782 &Mips::CPUSPRegRegClass,
5783 &Mips::DSPCCRegClass,
5784 &Mips::GP32RegClass,
5785 &Mips::GPR32ZERORegClass,
5786 &Mips::HI32RegClass,
5787 &Mips::LO32RegClass,
5788 &Mips::SP32RegClass,
5789 &Mips::FGR64RegClass,
5790 &Mips::GPR64RegClass,
5791 &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
5792 &Mips::AFGR64RegClass,
5793 &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
5794 &Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,
5795 &Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,
5796 &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,
5797 &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass,
5798 &Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass,
5799 &Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass,
5800 &Mips::ACC64DSPRegClass,
5801 &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass,
5802 &Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass,
5803 &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClass,
5804 &Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClass,
5805 &Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass,
5806 &Mips::OCTEON_MPLRegClass,
5807 &Mips::OCTEON_PRegClass,
5808 &Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass,
5809 &Mips::ACC64RegClass,
5810 &Mips::GP64RegClass,
5811 &Mips::GPR64_with_sub_32_in_CPURARegRegClass,
5812 &Mips::GPR64_with_sub_32_in_GPR32ZERORegClass,
5813 &Mips::HI64RegClass,
5814 &Mips::LO64RegClass,
5815 &Mips::SP64RegClass,
5816 &Mips::MSA128BRegClass,
5817 &Mips::MSA128DRegClass,
5818 &Mips::MSA128HRegClass,
5819 &Mips::MSA128WRegClass,
5820 &Mips::MSA128WEvensRegClass,
5821 &Mips::ACC128RegClass,
5822 };
5823} // end anonymous namespace
5824
5825static const uint8_t CostPerUseTable[] = {
58260, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
5827
5828
5829static const bool InAllocatableClassTable[] = {
5830false, true, true, false, false, false, false, false, true, true, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
5831
5832
5833static const TargetRegisterInfoDesc MipsRegInfoDesc = { // Extra Descriptors
5834CostPerUseTable, 1, InAllocatableClassTable};
5835
5836unsigned MipsGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
5837 static const uint8_t RowMap[11] = {
5838 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1,
5839 };
5840 static const uint8_t Rows[2][11] = {
5841 { Mips::sub_hi_then_sub_32, 0, 0, 0, 0, 0, 0, Mips::sub_hi, Mips::sub_lo, 0, 0, },
5842 { Mips::sub_32, 0, 0, 0, 0, 0, 0, Mips::sub_hi_then_sub_32, Mips::sub_32, 0, 0, },
5843 };
5844
5845 --IdxA; assert(IdxA < 11); (void) IdxA;
5846 --IdxB; assert(IdxB < 11);
5847 return Rows[RowMap[IdxA]][IdxB];
5848}
5849
5850unsigned MipsGenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
5851 static const uint8_t Table[11][11] = {
5852 { 0, 0, 0, 0, 0, 0, 0, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, 0, },
5853 { 0, 0, 0, 0, 0, 0, 0, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, 0, },
5854 { 0, 0, 0, 0, 0, 0, 0, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, 0, },
5855 { 0, 0, 0, 0, 0, 0, 0, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, 0, },
5856 { 0, 0, 0, 0, 0, 0, 0, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, 0, },
5857 { 0, 0, 0, 0, 0, 0, 0, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, 0, },
5858 { 0, 0, 0, 0, 0, 0, 0, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, 0, },
5859 { 0, 0, 0, 0, 0, 0, 0, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, 0, },
5860 { Mips::sub_32, 0, 0, 0, 0, 0, 0, 0, 0, Mips::sub_hi, 0, },
5861 { 0, 0, 0, 0, 0, 0, 0, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, 0, },
5862 { Mips::sub_32, 0, 0, 0, 0, 0, 0, 0, 0, Mips::sub_hi, 0, },
5863 };
5864
5865 --IdxA; assert(IdxA < 11);
5866 --IdxB; assert(IdxB < 11);
5867 return Table[IdxA][IdxB];
5868 }
5869
5870 struct MaskRolOp {
5871 LaneBitmask Mask;
5872 uint8_t RotateLeft;
5873 };
5874 static const MaskRolOp LaneMaskComposeSequences[] = {
5875 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 0 }, { LaneBitmask::getNone(), 0 }, // Sequence 0
5876 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 1 }, { LaneBitmask::getNone(), 0 }, // Sequence 2
5877 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 2 }, { LaneBitmask::getNone(), 0 }, // Sequence 4
5878 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 3 }, { LaneBitmask::getNone(), 0 }, // Sequence 6
5879 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 4 }, { LaneBitmask::getNone(), 0 }, // Sequence 8
5880 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 5 }, { LaneBitmask::getNone(), 0 }, // Sequence 10
5881 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 6 }, { LaneBitmask::getNone(), 0 } // Sequence 12
5882 };
5883 static const uint8_t CompositeSequences[] = {
5884 0, // to sub_32
5885 0, // to sub_64
5886 2, // to sub_dsp16_19
5887 4, // to sub_dsp20
5888 6, // to sub_dsp21
5889 8, // to sub_dsp22
5890 10, // to sub_dsp23
5891 12, // to sub_hi
5892 0, // to sub_lo
5893 12, // to sub_hi_then_sub_32
5894 0 // to sub_32_sub_hi_then_sub_32
5895 };
5896
5897LaneBitmask MipsGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
5898 --IdxA; assert(IdxA < 11 && "Subregister index out of bounds");
5899 LaneBitmask Result;
5900 for (const MaskRolOp *Ops =
5901 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
5902 Ops->Mask.any(); ++Ops) {
5903 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
5904 if (unsigned S = Ops->RotateLeft)
5905 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
5906 else
5907 Result |= LaneBitmask(M);
5908 }
5909 return Result;
5910}
5911
5912LaneBitmask MipsGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
5913 LaneMask &= getSubRegIndexLaneMask(IdxA);
5914 --IdxA; assert(IdxA < 11 && "Subregister index out of bounds");
5915 LaneBitmask Result;
5916 for (const MaskRolOp *Ops =
5917 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
5918 Ops->Mask.any(); ++Ops) {
5919 LaneBitmask::Type M = LaneMask.getAsInteger();
5920 if (unsigned S = Ops->RotateLeft)
5921 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
5922 else
5923 Result |= LaneBitmask(M);
5924 }
5925 return Result;
5926}
5927
5928const TargetRegisterClass *MipsGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
5929 static const uint8_t Table[70][11] = {
5930 { // MSA128F16
5931 0, // sub_32
5932 1, // sub_64 -> MSA128F16
5933 0, // sub_dsp16_19
5934 0, // sub_dsp20
5935 0, // sub_dsp21
5936 0, // sub_dsp22
5937 0, // sub_dsp23
5938 1, // sub_hi -> MSA128F16
5939 1, // sub_lo -> MSA128F16
5940 0, // sub_hi_then_sub_32
5941 0, // sub_32_sub_hi_then_sub_32
5942 },
5943 { // CCR
5944 0, // sub_32
5945 0, // sub_64
5946 0, // sub_dsp16_19
5947 0, // sub_dsp20
5948 0, // sub_dsp21
5949 0, // sub_dsp22
5950 0, // sub_dsp23
5951 0, // sub_hi
5952 0, // sub_lo
5953 0, // sub_hi_then_sub_32
5954 0, // sub_32_sub_hi_then_sub_32
5955 },
5956 { // COP0
5957 0, // sub_32
5958 0, // sub_64
5959 0, // sub_dsp16_19
5960 0, // sub_dsp20
5961 0, // sub_dsp21
5962 0, // sub_dsp22
5963 0, // sub_dsp23
5964 0, // sub_hi
5965 0, // sub_lo
5966 0, // sub_hi_then_sub_32
5967 0, // sub_32_sub_hi_then_sub_32
5968 },
5969 { // COP2
5970 0, // sub_32
5971 0, // sub_64
5972 0, // sub_dsp16_19
5973 0, // sub_dsp20
5974 0, // sub_dsp21
5975 0, // sub_dsp22
5976 0, // sub_dsp23
5977 0, // sub_hi
5978 0, // sub_lo
5979 0, // sub_hi_then_sub_32
5980 0, // sub_32_sub_hi_then_sub_32
5981 },
5982 { // COP3
5983 0, // sub_32
5984 0, // sub_64
5985 0, // sub_dsp16_19
5986 0, // sub_dsp20
5987 0, // sub_dsp21
5988 0, // sub_dsp22
5989 0, // sub_dsp23
5990 0, // sub_hi
5991 0, // sub_lo
5992 0, // sub_hi_then_sub_32
5993 0, // sub_32_sub_hi_then_sub_32
5994 },
5995 { // DSPR
5996 0, // sub_32
5997 0, // sub_64
5998 0, // sub_dsp16_19
5999 0, // sub_dsp20
6000 0, // sub_dsp21
6001 0, // sub_dsp22
6002 0, // sub_dsp23
6003 0, // sub_hi
6004 0, // sub_lo
6005 0, // sub_hi_then_sub_32
6006 0, // sub_32_sub_hi_then_sub_32
6007 },
6008 { // FGR32
6009 0, // sub_32
6010 0, // sub_64
6011 0, // sub_dsp16_19
6012 0, // sub_dsp20
6013 0, // sub_dsp21
6014 0, // sub_dsp22
6015 0, // sub_dsp23
6016 0, // sub_hi
6017 0, // sub_lo
6018 0, // sub_hi_then_sub_32
6019 0, // sub_32_sub_hi_then_sub_32
6020 },
6021 { // FGRCC
6022 0, // sub_32
6023 0, // sub_64
6024 0, // sub_dsp16_19
6025 0, // sub_dsp20
6026 0, // sub_dsp21
6027 0, // sub_dsp22
6028 0, // sub_dsp23
6029 0, // sub_hi
6030 0, // sub_lo
6031 0, // sub_hi_then_sub_32
6032 0, // sub_32_sub_hi_then_sub_32
6033 },
6034 { // GPR32
6035 0, // sub_32
6036 0, // sub_64
6037 0, // sub_dsp16_19
6038 0, // sub_dsp20
6039 0, // sub_dsp21
6040 0, // sub_dsp22
6041 0, // sub_dsp23
6042 0, // sub_hi
6043 0, // sub_lo
6044 0, // sub_hi_then_sub_32
6045 0, // sub_32_sub_hi_then_sub_32
6046 },
6047 { // HWRegs
6048 0, // sub_32
6049 0, // sub_64
6050 0, // sub_dsp16_19
6051 0, // sub_dsp20
6052 0, // sub_dsp21
6053 0, // sub_dsp22
6054 0, // sub_dsp23
6055 0, // sub_hi
6056 0, // sub_lo
6057 0, // sub_hi_then_sub_32
6058 0, // sub_32_sub_hi_then_sub_32
6059 },
6060 { // MSACtrl
6061 0, // sub_32
6062 0, // sub_64
6063 0, // sub_dsp16_19
6064 0, // sub_dsp20
6065 0, // sub_dsp21
6066 0, // sub_dsp22
6067 0, // sub_dsp23
6068 0, // sub_hi
6069 0, // sub_lo
6070 0, // sub_hi_then_sub_32
6071 0, // sub_32_sub_hi_then_sub_32
6072 },
6073 { // GPR32NONZERO
6074 0, // sub_32
6075 0, // sub_64
6076 0, // sub_dsp16_19
6077 0, // sub_dsp20
6078 0, // sub_dsp21
6079 0, // sub_dsp22
6080 0, // sub_dsp23
6081 0, // sub_hi
6082 0, // sub_lo
6083 0, // sub_hi_then_sub_32
6084 0, // sub_32_sub_hi_then_sub_32
6085 },
6086 { // CPU16RegsPlusSP
6087 0, // sub_32
6088 0, // sub_64
6089 0, // sub_dsp16_19
6090 0, // sub_dsp20
6091 0, // sub_dsp21
6092 0, // sub_dsp22
6093 0, // sub_dsp23
6094 0, // sub_hi
6095 0, // sub_lo
6096 0, // sub_hi_then_sub_32
6097 0, // sub_32_sub_hi_then_sub_32
6098 },
6099 { // CPU16Regs
6100 0, // sub_32
6101 0, // sub_64
6102 0, // sub_dsp16_19
6103 0, // sub_dsp20
6104 0, // sub_dsp21
6105 0, // sub_dsp22
6106 0, // sub_dsp23
6107 0, // sub_hi
6108 0, // sub_lo
6109 0, // sub_hi_then_sub_32
6110 0, // sub_32_sub_hi_then_sub_32
6111 },
6112 { // FCC
6113 0, // sub_32
6114 0, // sub_64
6115 0, // sub_dsp16_19
6116 0, // sub_dsp20
6117 0, // sub_dsp21
6118 0, // sub_dsp22
6119 0, // sub_dsp23
6120 0, // sub_hi
6121 0, // sub_lo
6122 0, // sub_hi_then_sub_32
6123 0, // sub_32_sub_hi_then_sub_32
6124 },
6125 { // GPRMM16
6126 0, // sub_32
6127 0, // sub_64
6128 0, // sub_dsp16_19
6129 0, // sub_dsp20
6130 0, // sub_dsp21
6131 0, // sub_dsp22
6132 0, // sub_dsp23
6133 0, // sub_hi
6134 0, // sub_lo
6135 0, // sub_hi_then_sub_32
6136 0, // sub_32_sub_hi_then_sub_32
6137 },
6138 { // GPRMM16MoveP
6139 0, // sub_32
6140 0, // sub_64
6141 0, // sub_dsp16_19
6142 0, // sub_dsp20
6143 0, // sub_dsp21
6144 0, // sub_dsp22
6145 0, // sub_dsp23
6146 0, // sub_hi
6147 0, // sub_lo
6148 0, // sub_hi_then_sub_32
6149 0, // sub_32_sub_hi_then_sub_32
6150 },
6151 { // GPRMM16Zero
6152 0, // sub_32
6153 0, // sub_64
6154 0, // sub_dsp16_19
6155 0, // sub_dsp20
6156 0, // sub_dsp21
6157 0, // sub_dsp22
6158 0, // sub_dsp23
6159 0, // sub_hi
6160 0, // sub_lo
6161 0, // sub_hi_then_sub_32
6162 0, // sub_32_sub_hi_then_sub_32
6163 },
6164 { // CPU16Regs_and_GPRMM16Zero
6165 0, // sub_32
6166 0, // sub_64
6167 0, // sub_dsp16_19
6168 0, // sub_dsp20
6169 0, // sub_dsp21
6170 0, // sub_dsp22
6171 0, // sub_dsp23
6172 0, // sub_hi
6173 0, // sub_lo
6174 0, // sub_hi_then_sub_32
6175 0, // sub_32_sub_hi_then_sub_32
6176 },
6177 { // GPR32NONZERO_and_GPRMM16MoveP
6178 0, // sub_32
6179 0, // sub_64
6180 0, // sub_dsp16_19
6181 0, // sub_dsp20
6182 0, // sub_dsp21
6183 0, // sub_dsp22
6184 0, // sub_dsp23
6185 0, // sub_hi
6186 0, // sub_lo
6187 0, // sub_hi_then_sub_32
6188 0, // sub_32_sub_hi_then_sub_32
6189 },
6190 { // GPRMM16MovePPairSecond
6191 0, // sub_32
6192 0, // sub_64
6193 0, // sub_dsp16_19
6194 0, // sub_dsp20
6195 0, // sub_dsp21
6196 0, // sub_dsp22
6197 0, // sub_dsp23
6198 0, // sub_hi
6199 0, // sub_lo
6200 0, // sub_hi_then_sub_32
6201 0, // sub_32_sub_hi_then_sub_32
6202 },
6203 { // CPU16Regs_and_GPRMM16MoveP
6204 0, // sub_32
6205 0, // sub_64
6206 0, // sub_dsp16_19
6207 0, // sub_dsp20
6208 0, // sub_dsp21
6209 0, // sub_dsp22
6210 0, // sub_dsp23
6211 0, // sub_hi
6212 0, // sub_lo
6213 0, // sub_hi_then_sub_32
6214 0, // sub_32_sub_hi_then_sub_32
6215 },
6216 { // GPRMM16MoveP_and_GPRMM16Zero
6217 0, // sub_32
6218 0, // sub_64
6219 0, // sub_dsp16_19
6220 0, // sub_dsp20
6221 0, // sub_dsp21
6222 0, // sub_dsp22
6223 0, // sub_dsp23
6224 0, // sub_hi
6225 0, // sub_lo
6226 0, // sub_hi_then_sub_32
6227 0, // sub_32_sub_hi_then_sub_32
6228 },
6229 { // HI32DSP
6230 0, // sub_32
6231 0, // sub_64
6232 0, // sub_dsp16_19
6233 0, // sub_dsp20
6234 0, // sub_dsp21
6235 0, // sub_dsp22
6236 0, // sub_dsp23
6237 0, // sub_hi
6238 0, // sub_lo
6239 0, // sub_hi_then_sub_32
6240 0, // sub_32_sub_hi_then_sub_32
6241 },
6242 { // LO32DSP
6243 0, // sub_32
6244 0, // sub_64
6245 0, // sub_dsp16_19
6246 0, // sub_dsp20
6247 0, // sub_dsp21
6248 0, // sub_dsp22
6249 0, // sub_dsp23
6250 0, // sub_hi
6251 0, // sub_lo
6252 0, // sub_hi_then_sub_32
6253 0, // sub_32_sub_hi_then_sub_32
6254 },
6255 { // CPU16Regs_and_GPRMM16MovePPairSecond
6256 0, // sub_32
6257 0, // sub_64
6258 0, // sub_dsp16_19
6259 0, // sub_dsp20
6260 0, // sub_dsp21
6261 0, // sub_dsp22
6262 0, // sub_dsp23
6263 0, // sub_hi
6264 0, // sub_lo
6265 0, // sub_hi_then_sub_32
6266 0, // sub_32_sub_hi_then_sub_32
6267 },
6268 { // GPRMM16MovePPairFirst
6269 0, // sub_32
6270 0, // sub_64
6271 0, // sub_dsp16_19
6272 0, // sub_dsp20
6273 0, // sub_dsp21
6274 0, // sub_dsp22
6275 0, // sub_dsp23
6276 0, // sub_hi
6277 0, // sub_lo
6278 0, // sub_hi_then_sub_32
6279 0, // sub_32_sub_hi_then_sub_32
6280 },
6281 { // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
6282 0, // sub_32
6283 0, // sub_64
6284 0, // sub_dsp16_19
6285 0, // sub_dsp20
6286 0, // sub_dsp21
6287 0, // sub_dsp22
6288 0, // sub_dsp23
6289 0, // sub_hi
6290 0, // sub_lo
6291 0, // sub_hi_then_sub_32
6292 0, // sub_32_sub_hi_then_sub_32
6293 },
6294 { // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
6295 0, // sub_32
6296 0, // sub_64
6297 0, // sub_dsp16_19
6298 0, // sub_dsp20
6299 0, // sub_dsp21
6300 0, // sub_dsp22
6301 0, // sub_dsp23
6302 0, // sub_hi
6303 0, // sub_lo
6304 0, // sub_hi_then_sub_32
6305 0, // sub_32_sub_hi_then_sub_32
6306 },
6307 { // CPURAReg
6308 0, // sub_32
6309 0, // sub_64
6310 0, // sub_dsp16_19
6311 0, // sub_dsp20
6312 0, // sub_dsp21
6313 0, // sub_dsp22
6314 0, // sub_dsp23
6315 0, // sub_hi
6316 0, // sub_lo
6317 0, // sub_hi_then_sub_32
6318 0, // sub_32_sub_hi_then_sub_32
6319 },
6320 { // CPUSPReg
6321 0, // sub_32
6322 0, // sub_64
6323 0, // sub_dsp16_19
6324 0, // sub_dsp20
6325 0, // sub_dsp21
6326 0, // sub_dsp22
6327 0, // sub_dsp23
6328 0, // sub_hi
6329 0, // sub_lo
6330 0, // sub_hi_then_sub_32
6331 0, // sub_32_sub_hi_then_sub_32
6332 },
6333 { // DSPCC
6334 0, // sub_32
6335 0, // sub_64
6336 0, // sub_dsp16_19
6337 0, // sub_dsp20
6338 0, // sub_dsp21
6339 0, // sub_dsp22
6340 0, // sub_dsp23
6341 0, // sub_hi
6342 0, // sub_lo
6343 0, // sub_hi_then_sub_32
6344 0, // sub_32_sub_hi_then_sub_32
6345 },
6346 { // GP32
6347 0, // sub_32
6348 0, // sub_64
6349 0, // sub_dsp16_19
6350 0, // sub_dsp20
6351 0, // sub_dsp21
6352 0, // sub_dsp22
6353 0, // sub_dsp23
6354 0, // sub_hi
6355 0, // sub_lo
6356 0, // sub_hi_then_sub_32
6357 0, // sub_32_sub_hi_then_sub_32
6358 },
6359 { // GPR32ZERO
6360 0, // sub_32
6361 0, // sub_64
6362 0, // sub_dsp16_19
6363 0, // sub_dsp20
6364 0, // sub_dsp21
6365 0, // sub_dsp22
6366 0, // sub_dsp23
6367 0, // sub_hi
6368 0, // sub_lo
6369 0, // sub_hi_then_sub_32
6370 0, // sub_32_sub_hi_then_sub_32
6371 },
6372 { // HI32
6373 0, // sub_32
6374 0, // sub_64
6375 0, // sub_dsp16_19
6376 0, // sub_dsp20
6377 0, // sub_dsp21
6378 0, // sub_dsp22
6379 0, // sub_dsp23
6380 0, // sub_hi
6381 0, // sub_lo
6382 0, // sub_hi_then_sub_32
6383 0, // sub_32_sub_hi_then_sub_32
6384 },
6385 { // LO32
6386 0, // sub_32
6387 0, // sub_64
6388 0, // sub_dsp16_19
6389 0, // sub_dsp20
6390 0, // sub_dsp21
6391 0, // sub_dsp22
6392 0, // sub_dsp23
6393 0, // sub_hi
6394 0, // sub_lo
6395 0, // sub_hi_then_sub_32
6396 0, // sub_32_sub_hi_then_sub_32
6397 },
6398 { // SP32
6399 0, // sub_32
6400 0, // sub_64
6401 0, // sub_dsp16_19
6402 0, // sub_dsp20
6403 0, // sub_dsp21
6404 0, // sub_dsp22
6405 0, // sub_dsp23
6406 0, // sub_hi
6407 0, // sub_lo
6408 0, // sub_hi_then_sub_32
6409 0, // sub_32_sub_hi_then_sub_32
6410 },
6411 { // FGR64
6412 0, // sub_32
6413 0, // sub_64
6414 0, // sub_dsp16_19
6415 0, // sub_dsp20
6416 0, // sub_dsp21
6417 0, // sub_dsp22
6418 0, // sub_dsp23
6419 38, // sub_hi -> FGR64
6420 38, // sub_lo -> FGR64
6421 0, // sub_hi_then_sub_32
6422 0, // sub_32_sub_hi_then_sub_32
6423 },
6424 { // GPR64
6425 39, // sub_32 -> GPR64
6426 0, // sub_64
6427 0, // sub_dsp16_19
6428 0, // sub_dsp20
6429 0, // sub_dsp21
6430 0, // sub_dsp22
6431 0, // sub_dsp23
6432 0, // sub_hi
6433 0, // sub_lo
6434 0, // sub_hi_then_sub_32
6435 0, // sub_32_sub_hi_then_sub_32
6436 },
6437 { // GPR64_with_sub_32_in_GPR32NONZERO
6438 40, // sub_32 -> GPR64_with_sub_32_in_GPR32NONZERO
6439 0, // sub_64
6440 0, // sub_dsp16_19
6441 0, // sub_dsp20
6442 0, // sub_dsp21
6443 0, // sub_dsp22
6444 0, // sub_dsp23
6445 0, // sub_hi
6446 0, // sub_lo
6447 0, // sub_hi_then_sub_32
6448 0, // sub_32_sub_hi_then_sub_32
6449 },
6450 { // AFGR64
6451 0, // sub_32
6452 0, // sub_64
6453 0, // sub_dsp16_19
6454 0, // sub_dsp20
6455 0, // sub_dsp21
6456 0, // sub_dsp22
6457 0, // sub_dsp23
6458 41, // sub_hi -> AFGR64
6459 41, // sub_lo -> AFGR64
6460 0, // sub_hi_then_sub_32
6461 0, // sub_32_sub_hi_then_sub_32
6462 },
6463 { // GPR64_with_sub_32_in_CPU16RegsPlusSP
6464 42, // sub_32 -> GPR64_with_sub_32_in_CPU16RegsPlusSP
6465 0, // sub_64
6466 0, // sub_dsp16_19
6467 0, // sub_dsp20
6468 0, // sub_dsp21
6469 0, // sub_dsp22
6470 0, // sub_dsp23
6471 0, // sub_hi
6472 0, // sub_lo
6473 0, // sub_hi_then_sub_32
6474 0, // sub_32_sub_hi_then_sub_32
6475 },
6476 { // GPR64_with_sub_32_in_CPU16Regs
6477 43, // sub_32 -> GPR64_with_sub_32_in_CPU16Regs
6478 0, // sub_64
6479 0, // sub_dsp16_19
6480 0, // sub_dsp20
6481 0, // sub_dsp21
6482 0, // sub_dsp22
6483 0, // sub_dsp23
6484 0, // sub_hi
6485 0, // sub_lo
6486 0, // sub_hi_then_sub_32
6487 0, // sub_32_sub_hi_then_sub_32
6488 },
6489 { // GPR64_with_sub_32_in_GPRMM16MoveP
6490 44, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MoveP
6491 0, // sub_64
6492 0, // sub_dsp16_19
6493 0, // sub_dsp20
6494 0, // sub_dsp21
6495 0, // sub_dsp22
6496 0, // sub_dsp23
6497 0, // sub_hi
6498 0, // sub_lo
6499 0, // sub_hi_then_sub_32
6500 0, // sub_32_sub_hi_then_sub_32
6501 },
6502 { // GPR64_with_sub_32_in_GPRMM16Zero
6503 45, // sub_32 -> GPR64_with_sub_32_in_GPRMM16Zero
6504 0, // sub_64
6505 0, // sub_dsp16_19
6506 0, // sub_dsp20
6507 0, // sub_dsp21
6508 0, // sub_dsp22
6509 0, // sub_dsp23
6510 0, // sub_hi
6511 0, // sub_lo
6512 0, // sub_hi_then_sub_32
6513 0, // sub_32_sub_hi_then_sub_32
6514 },
6515 { // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
6516 46, // sub_32 -> GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
6517 0, // sub_64
6518 0, // sub_dsp16_19
6519 0, // sub_dsp20
6520 0, // sub_dsp21
6521 0, // sub_dsp22
6522 0, // sub_dsp23
6523 0, // sub_hi
6524 0, // sub_lo
6525 0, // sub_hi_then_sub_32
6526 0, // sub_32_sub_hi_then_sub_32
6527 },
6528 { // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
6529 47, // sub_32 -> GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
6530 0, // sub_64
6531 0, // sub_dsp16_19
6532 0, // sub_dsp20
6533 0, // sub_dsp21
6534 0, // sub_dsp22
6535 0, // sub_dsp23
6536 0, // sub_hi
6537 0, // sub_lo
6538 0, // sub_hi_then_sub_32
6539 0, // sub_32_sub_hi_then_sub_32
6540 },
6541 { // GPR64_with_sub_32_in_GPRMM16MovePPairSecond
6542 48, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MovePPairSecond
6543 0, // sub_64
6544 0, // sub_dsp16_19
6545 0, // sub_dsp20
6546 0, // sub_dsp21
6547 0, // sub_dsp22
6548 0, // sub_dsp23
6549 0, // sub_hi
6550 0, // sub_lo
6551 0, // sub_hi_then_sub_32
6552 0, // sub_32_sub_hi_then_sub_32
6553 },
6554 { // ACC64DSP
6555 0, // sub_32
6556 0, // sub_64
6557 0, // sub_dsp16_19
6558 0, // sub_dsp20
6559 0, // sub_dsp21
6560 0, // sub_dsp22
6561 0, // sub_dsp23
6562 49, // sub_hi -> ACC64DSP
6563 49, // sub_lo -> ACC64DSP
6564 0, // sub_hi_then_sub_32
6565 0, // sub_32_sub_hi_then_sub_32
6566 },
6567 { // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
6568 50, // sub_32 -> GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
6569 0, // sub_64
6570 0, // sub_dsp16_19
6571 0, // sub_dsp20
6572 0, // sub_dsp21
6573 0, // sub_dsp22
6574 0, // sub_dsp23
6575 0, // sub_hi
6576 0, // sub_lo
6577 0, // sub_hi_then_sub_32
6578 0, // sub_32_sub_hi_then_sub_32
6579 },
6580 { // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
6581 51, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
6582 0, // sub_64
6583 0, // sub_dsp16_19
6584 0, // sub_dsp20
6585 0, // sub_dsp21
6586 0, // sub_dsp22
6587 0, // sub_dsp23
6588 0, // sub_hi
6589 0, // sub_lo
6590 0, // sub_hi_then_sub_32
6591 0, // sub_32_sub_hi_then_sub_32
6592 },
6593 { // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond
6594 52, // sub_32 -> GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond
6595 0, // sub_64
6596 0, // sub_dsp16_19
6597 0, // sub_dsp20
6598 0, // sub_dsp21
6599 0, // sub_dsp22
6600 0, // sub_dsp23
6601 0, // sub_hi
6602 0, // sub_lo
6603 0, // sub_hi_then_sub_32
6604 0, // sub_32_sub_hi_then_sub_32
6605 },
6606 { // GPR64_with_sub_32_in_GPRMM16MovePPairFirst
6607 53, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MovePPairFirst
6608 0, // sub_64
6609 0, // sub_dsp16_19
6610 0, // sub_dsp20
6611 0, // sub_dsp21
6612 0, // sub_dsp22
6613 0, // sub_dsp23
6614 0, // sub_hi
6615 0, // sub_lo
6616 0, // sub_hi_then_sub_32
6617 0, // sub_32_sub_hi_then_sub_32
6618 },
6619 { // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
6620 54, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
6621 0, // sub_64
6622 0, // sub_dsp16_19
6623 0, // sub_dsp20
6624 0, // sub_dsp21
6625 0, // sub_dsp22
6626 0, // sub_dsp23
6627 0, // sub_hi
6628 0, // sub_lo
6629 0, // sub_hi_then_sub_32
6630 0, // sub_32_sub_hi_then_sub_32
6631 },
6632 { // OCTEON_MPL
6633 0, // sub_32
6634 0, // sub_64
6635 0, // sub_dsp16_19
6636 0, // sub_dsp20
6637 0, // sub_dsp21
6638 0, // sub_dsp22
6639 0, // sub_dsp23
6640 0, // sub_hi
6641 0, // sub_lo
6642 0, // sub_hi_then_sub_32
6643 0, // sub_32_sub_hi_then_sub_32
6644 },
6645 { // OCTEON_P
6646 0, // sub_32
6647 0, // sub_64
6648 0, // sub_dsp16_19
6649 0, // sub_dsp20
6650 0, // sub_dsp21
6651 0, // sub_dsp22
6652 0, // sub_dsp23
6653 0, // sub_hi
6654 0, // sub_lo
6655 0, // sub_hi_then_sub_32
6656 0, // sub_32_sub_hi_then_sub_32
6657 },
6658 { // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
6659 57, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
6660 0, // sub_64
6661 0, // sub_dsp16_19
6662 0, // sub_dsp20
6663 0, // sub_dsp21
6664 0, // sub_dsp22
6665 0, // sub_dsp23
6666 0, // sub_hi
6667 0, // sub_lo
6668 0, // sub_hi_then_sub_32
6669 0, // sub_32_sub_hi_then_sub_32
6670 },
6671 { // ACC64
6672 0, // sub_32
6673 0, // sub_64
6674 0, // sub_dsp16_19
6675 0, // sub_dsp20
6676 0, // sub_dsp21
6677 0, // sub_dsp22
6678 0, // sub_dsp23
6679 58, // sub_hi -> ACC64
6680 58, // sub_lo -> ACC64
6681 0, // sub_hi_then_sub_32
6682 0, // sub_32_sub_hi_then_sub_32
6683 },
6684 { // GP64
6685 59, // sub_32 -> GP64
6686 0, // sub_64
6687 0, // sub_dsp16_19
6688 0, // sub_dsp20
6689 0, // sub_dsp21
6690 0, // sub_dsp22
6691 0, // sub_dsp23
6692 0, // sub_hi
6693 0, // sub_lo
6694 0, // sub_hi_then_sub_32
6695 0, // sub_32_sub_hi_then_sub_32
6696 },
6697 { // GPR64_with_sub_32_in_CPURAReg
6698 60, // sub_32 -> GPR64_with_sub_32_in_CPURAReg
6699 0, // sub_64
6700 0, // sub_dsp16_19
6701 0, // sub_dsp20
6702 0, // sub_dsp21
6703 0, // sub_dsp22
6704 0, // sub_dsp23
6705 0, // sub_hi
6706 0, // sub_lo
6707 0, // sub_hi_then_sub_32
6708 0, // sub_32_sub_hi_then_sub_32
6709 },
6710 { // GPR64_with_sub_32_in_GPR32ZERO
6711 61, // sub_32 -> GPR64_with_sub_32_in_GPR32ZERO
6712 0, // sub_64
6713 0, // sub_dsp16_19
6714 0, // sub_dsp20
6715 0, // sub_dsp21
6716 0, // sub_dsp22
6717 0, // sub_dsp23
6718 0, // sub_hi
6719 0, // sub_lo
6720 0, // sub_hi_then_sub_32
6721 0, // sub_32_sub_hi_then_sub_32
6722 },
6723 { // HI64
6724 62, // sub_32 -> HI64
6725 0, // sub_64
6726 0, // sub_dsp16_19
6727 0, // sub_dsp20
6728 0, // sub_dsp21
6729 0, // sub_dsp22
6730 0, // sub_dsp23
6731 0, // sub_hi
6732 0, // sub_lo
6733 0, // sub_hi_then_sub_32
6734 0, // sub_32_sub_hi_then_sub_32
6735 },
6736 { // LO64
6737 63, // sub_32 -> LO64
6738 0, // sub_64
6739 0, // sub_dsp16_19
6740 0, // sub_dsp20
6741 0, // sub_dsp21
6742 0, // sub_dsp22
6743 0, // sub_dsp23
6744 0, // sub_hi
6745 0, // sub_lo
6746 0, // sub_hi_then_sub_32
6747 0, // sub_32_sub_hi_then_sub_32
6748 },
6749 { // SP64
6750 64, // sub_32 -> SP64
6751 0, // sub_64
6752 0, // sub_dsp16_19
6753 0, // sub_dsp20
6754 0, // sub_dsp21
6755 0, // sub_dsp22
6756 0, // sub_dsp23
6757 0, // sub_hi
6758 0, // sub_lo
6759 0, // sub_hi_then_sub_32
6760 0, // sub_32_sub_hi_then_sub_32
6761 },
6762 { // MSA128B
6763 0, // sub_32
6764 65, // sub_64 -> MSA128B
6765 0, // sub_dsp16_19
6766 0, // sub_dsp20
6767 0, // sub_dsp21
6768 0, // sub_dsp22
6769 0, // sub_dsp23
6770 65, // sub_hi -> MSA128B
6771 65, // sub_lo -> MSA128B
6772 0, // sub_hi_then_sub_32
6773 0, // sub_32_sub_hi_then_sub_32
6774 },
6775 { // MSA128D
6776 0, // sub_32
6777 66, // sub_64 -> MSA128D
6778 0, // sub_dsp16_19
6779 0, // sub_dsp20
6780 0, // sub_dsp21
6781 0, // sub_dsp22
6782 0, // sub_dsp23
6783 66, // sub_hi -> MSA128D
6784 66, // sub_lo -> MSA128D
6785 0, // sub_hi_then_sub_32
6786 0, // sub_32_sub_hi_then_sub_32
6787 },
6788 { // MSA128H
6789 0, // sub_32
6790 67, // sub_64 -> MSA128H
6791 0, // sub_dsp16_19
6792 0, // sub_dsp20
6793 0, // sub_dsp21
6794 0, // sub_dsp22
6795 0, // sub_dsp23
6796 67, // sub_hi -> MSA128H
6797 67, // sub_lo -> MSA128H
6798 0, // sub_hi_then_sub_32
6799 0, // sub_32_sub_hi_then_sub_32
6800 },
6801 { // MSA128W
6802 0, // sub_32
6803 68, // sub_64 -> MSA128W
6804 0, // sub_dsp16_19
6805 0, // sub_dsp20
6806 0, // sub_dsp21
6807 0, // sub_dsp22
6808 0, // sub_dsp23
6809 68, // sub_hi -> MSA128W
6810 68, // sub_lo -> MSA128W
6811 0, // sub_hi_then_sub_32
6812 0, // sub_32_sub_hi_then_sub_32
6813 },
6814 { // MSA128WEvens
6815 0, // sub_32
6816 69, // sub_64 -> MSA128WEvens
6817 0, // sub_dsp16_19
6818 0, // sub_dsp20
6819 0, // sub_dsp21
6820 0, // sub_dsp22
6821 0, // sub_dsp23
6822 69, // sub_hi -> MSA128WEvens
6823 69, // sub_lo -> MSA128WEvens
6824 0, // sub_hi_then_sub_32
6825 0, // sub_32_sub_hi_then_sub_32
6826 },
6827 { // ACC128
6828 70, // sub_32 -> ACC128
6829 0, // sub_64
6830 0, // sub_dsp16_19
6831 0, // sub_dsp20
6832 0, // sub_dsp21
6833 0, // sub_dsp22
6834 0, // sub_dsp23
6835 70, // sub_hi -> ACC128
6836 70, // sub_lo -> ACC128
6837 70, // sub_hi_then_sub_32 -> ACC128
6838 70, // sub_32_sub_hi_then_sub_32 -> ACC128
6839 },
6840 };
6841 assert(RC && "Missing regclass");
6842 if (!Idx) return RC;
6843 --Idx;
6844 assert(Idx < 11 && "Bad subreg");
6845 unsigned TV = Table[RC->getID()][Idx];
6846 return TV ? getRegClass(TV - 1) : nullptr;
6847}
6848
6849const TargetRegisterClass *MipsGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
6850 static const uint8_t Table[70][11] = {
6851 { // MSA128F16
6852 0, // MSA128F16:sub_32
6853 38, // MSA128F16:sub_64 -> FGR64
6854 0, // MSA128F16:sub_dsp16_19
6855 0, // MSA128F16:sub_dsp20
6856 0, // MSA128F16:sub_dsp21
6857 0, // MSA128F16:sub_dsp22
6858 0, // MSA128F16:sub_dsp23
6859 0, // MSA128F16:sub_hi
6860 7, // MSA128F16:sub_lo -> FGR32
6861 0, // MSA128F16:sub_hi_then_sub_32
6862 0, // MSA128F16:sub_32_sub_hi_then_sub_32
6863 },
6864 { // CCR
6865 0, // CCR:sub_32
6866 0, // CCR:sub_64
6867 0, // CCR:sub_dsp16_19
6868 0, // CCR:sub_dsp20
6869 0, // CCR:sub_dsp21
6870 0, // CCR:sub_dsp22
6871 0, // CCR:sub_dsp23
6872 0, // CCR:sub_hi
6873 0, // CCR:sub_lo
6874 0, // CCR:sub_hi_then_sub_32
6875 0, // CCR:sub_32_sub_hi_then_sub_32
6876 },
6877 { // COP0
6878 0, // COP0:sub_32
6879 0, // COP0:sub_64
6880 0, // COP0:sub_dsp16_19
6881 0, // COP0:sub_dsp20
6882 0, // COP0:sub_dsp21
6883 0, // COP0:sub_dsp22
6884 0, // COP0:sub_dsp23
6885 0, // COP0:sub_hi
6886 0, // COP0:sub_lo
6887 0, // COP0:sub_hi_then_sub_32
6888 0, // COP0:sub_32_sub_hi_then_sub_32
6889 },
6890 { // COP2
6891 0, // COP2:sub_32
6892 0, // COP2:sub_64
6893 0, // COP2:sub_dsp16_19
6894 0, // COP2:sub_dsp20
6895 0, // COP2:sub_dsp21
6896 0, // COP2:sub_dsp22
6897 0, // COP2:sub_dsp23
6898 0, // COP2:sub_hi
6899 0, // COP2:sub_lo
6900 0, // COP2:sub_hi_then_sub_32
6901 0, // COP2:sub_32_sub_hi_then_sub_32
6902 },
6903 { // COP3
6904 0, // COP3:sub_32
6905 0, // COP3:sub_64
6906 0, // COP3:sub_dsp16_19
6907 0, // COP3:sub_dsp20
6908 0, // COP3:sub_dsp21
6909 0, // COP3:sub_dsp22
6910 0, // COP3:sub_dsp23
6911 0, // COP3:sub_hi
6912 0, // COP3:sub_lo
6913 0, // COP3:sub_hi_then_sub_32
6914 0, // COP3:sub_32_sub_hi_then_sub_32
6915 },
6916 { // DSPR
6917 0, // DSPR:sub_32
6918 0, // DSPR:sub_64
6919 0, // DSPR:sub_dsp16_19
6920 0, // DSPR:sub_dsp20
6921 0, // DSPR:sub_dsp21
6922 0, // DSPR:sub_dsp22
6923 0, // DSPR:sub_dsp23
6924 0, // DSPR:sub_hi
6925 0, // DSPR:sub_lo
6926 0, // DSPR:sub_hi_then_sub_32
6927 0, // DSPR:sub_32_sub_hi_then_sub_32
6928 },
6929 { // FGR32
6930 0, // FGR32:sub_32
6931 0, // FGR32:sub_64
6932 0, // FGR32:sub_dsp16_19
6933 0, // FGR32:sub_dsp20
6934 0, // FGR32:sub_dsp21
6935 0, // FGR32:sub_dsp22
6936 0, // FGR32:sub_dsp23
6937 0, // FGR32:sub_hi
6938 0, // FGR32:sub_lo
6939 0, // FGR32:sub_hi_then_sub_32
6940 0, // FGR32:sub_32_sub_hi_then_sub_32
6941 },
6942 { // FGRCC
6943 0, // FGRCC:sub_32
6944 0, // FGRCC:sub_64
6945 0, // FGRCC:sub_dsp16_19
6946 0, // FGRCC:sub_dsp20
6947 0, // FGRCC:sub_dsp21
6948 0, // FGRCC:sub_dsp22
6949 0, // FGRCC:sub_dsp23
6950 0, // FGRCC:sub_hi
6951 0, // FGRCC:sub_lo
6952 0, // FGRCC:sub_hi_then_sub_32
6953 0, // FGRCC:sub_32_sub_hi_then_sub_32
6954 },
6955 { // GPR32
6956 0, // GPR32:sub_32
6957 0, // GPR32:sub_64
6958 0, // GPR32:sub_dsp16_19
6959 0, // GPR32:sub_dsp20
6960 0, // GPR32:sub_dsp21
6961 0, // GPR32:sub_dsp22
6962 0, // GPR32:sub_dsp23
6963 0, // GPR32:sub_hi
6964 0, // GPR32:sub_lo
6965 0, // GPR32:sub_hi_then_sub_32
6966 0, // GPR32:sub_32_sub_hi_then_sub_32
6967 },
6968 { // HWRegs
6969 0, // HWRegs:sub_32
6970 0, // HWRegs:sub_64
6971 0, // HWRegs:sub_dsp16_19
6972 0, // HWRegs:sub_dsp20
6973 0, // HWRegs:sub_dsp21
6974 0, // HWRegs:sub_dsp22
6975 0, // HWRegs:sub_dsp23
6976 0, // HWRegs:sub_hi
6977 0, // HWRegs:sub_lo
6978 0, // HWRegs:sub_hi_then_sub_32
6979 0, // HWRegs:sub_32_sub_hi_then_sub_32
6980 },
6981 { // MSACtrl
6982 0, // MSACtrl:sub_32
6983 0, // MSACtrl:sub_64
6984 0, // MSACtrl:sub_dsp16_19
6985 0, // MSACtrl:sub_dsp20
6986 0, // MSACtrl:sub_dsp21
6987 0, // MSACtrl:sub_dsp22
6988 0, // MSACtrl:sub_dsp23
6989 0, // MSACtrl:sub_hi
6990 0, // MSACtrl:sub_lo
6991 0, // MSACtrl:sub_hi_then_sub_32
6992 0, // MSACtrl:sub_32_sub_hi_then_sub_32
6993 },
6994 { // GPR32NONZERO
6995 0, // GPR32NONZERO:sub_32
6996 0, // GPR32NONZERO:sub_64
6997 0, // GPR32NONZERO:sub_dsp16_19
6998 0, // GPR32NONZERO:sub_dsp20
6999 0, // GPR32NONZERO:sub_dsp21
7000 0, // GPR32NONZERO:sub_dsp22
7001 0, // GPR32NONZERO:sub_dsp23
7002 0, // GPR32NONZERO:sub_hi
7003 0, // GPR32NONZERO:sub_lo
7004 0, // GPR32NONZERO:sub_hi_then_sub_32
7005 0, // GPR32NONZERO:sub_32_sub_hi_then_sub_32
7006 },
7007 { // CPU16RegsPlusSP
7008 0, // CPU16RegsPlusSP:sub_32
7009 0, // CPU16RegsPlusSP:sub_64
7010 0, // CPU16RegsPlusSP:sub_dsp16_19
7011 0, // CPU16RegsPlusSP:sub_dsp20
7012 0, // CPU16RegsPlusSP:sub_dsp21
7013 0, // CPU16RegsPlusSP:sub_dsp22
7014 0, // CPU16RegsPlusSP:sub_dsp23
7015 0, // CPU16RegsPlusSP:sub_hi
7016 0, // CPU16RegsPlusSP:sub_lo
7017 0, // CPU16RegsPlusSP:sub_hi_then_sub_32
7018 0, // CPU16RegsPlusSP:sub_32_sub_hi_then_sub_32
7019 },
7020 { // CPU16Regs
7021 0, // CPU16Regs:sub_32
7022 0, // CPU16Regs:sub_64
7023 0, // CPU16Regs:sub_dsp16_19
7024 0, // CPU16Regs:sub_dsp20
7025 0, // CPU16Regs:sub_dsp21
7026 0, // CPU16Regs:sub_dsp22
7027 0, // CPU16Regs:sub_dsp23
7028 0, // CPU16Regs:sub_hi
7029 0, // CPU16Regs:sub_lo
7030 0, // CPU16Regs:sub_hi_then_sub_32
7031 0, // CPU16Regs:sub_32_sub_hi_then_sub_32
7032 },
7033 { // FCC
7034 0, // FCC:sub_32
7035 0, // FCC:sub_64
7036 0, // FCC:sub_dsp16_19
7037 0, // FCC:sub_dsp20
7038 0, // FCC:sub_dsp21
7039 0, // FCC:sub_dsp22
7040 0, // FCC:sub_dsp23
7041 0, // FCC:sub_hi
7042 0, // FCC:sub_lo
7043 0, // FCC:sub_hi_then_sub_32
7044 0, // FCC:sub_32_sub_hi_then_sub_32
7045 },
7046 { // GPRMM16
7047 0, // GPRMM16:sub_32
7048 0, // GPRMM16:sub_64
7049 0, // GPRMM16:sub_dsp16_19
7050 0, // GPRMM16:sub_dsp20
7051 0, // GPRMM16:sub_dsp21
7052 0, // GPRMM16:sub_dsp22
7053 0, // GPRMM16:sub_dsp23
7054 0, // GPRMM16:sub_hi
7055 0, // GPRMM16:sub_lo
7056 0, // GPRMM16:sub_hi_then_sub_32
7057 0, // GPRMM16:sub_32_sub_hi_then_sub_32
7058 },
7059 { // GPRMM16MoveP
7060 0, // GPRMM16MoveP:sub_32
7061 0, // GPRMM16MoveP:sub_64
7062 0, // GPRMM16MoveP:sub_dsp16_19
7063 0, // GPRMM16MoveP:sub_dsp20
7064 0, // GPRMM16MoveP:sub_dsp21
7065 0, // GPRMM16MoveP:sub_dsp22
7066 0, // GPRMM16MoveP:sub_dsp23
7067 0, // GPRMM16MoveP:sub_hi
7068 0, // GPRMM16MoveP:sub_lo
7069 0, // GPRMM16MoveP:sub_hi_then_sub_32
7070 0, // GPRMM16MoveP:sub_32_sub_hi_then_sub_32
7071 },
7072 { // GPRMM16Zero
7073 0, // GPRMM16Zero:sub_32
7074 0, // GPRMM16Zero:sub_64
7075 0, // GPRMM16Zero:sub_dsp16_19
7076 0, // GPRMM16Zero:sub_dsp20
7077 0, // GPRMM16Zero:sub_dsp21
7078 0, // GPRMM16Zero:sub_dsp22
7079 0, // GPRMM16Zero:sub_dsp23
7080 0, // GPRMM16Zero:sub_hi
7081 0, // GPRMM16Zero:sub_lo
7082 0, // GPRMM16Zero:sub_hi_then_sub_32
7083 0, // GPRMM16Zero:sub_32_sub_hi_then_sub_32
7084 },
7085 { // CPU16Regs_and_GPRMM16Zero
7086 0, // CPU16Regs_and_GPRMM16Zero:sub_32
7087 0, // CPU16Regs_and_GPRMM16Zero:sub_64
7088 0, // CPU16Regs_and_GPRMM16Zero:sub_dsp16_19
7089 0, // CPU16Regs_and_GPRMM16Zero:sub_dsp20
7090 0, // CPU16Regs_and_GPRMM16Zero:sub_dsp21
7091 0, // CPU16Regs_and_GPRMM16Zero:sub_dsp22
7092 0, // CPU16Regs_and_GPRMM16Zero:sub_dsp23
7093 0, // CPU16Regs_and_GPRMM16Zero:sub_hi
7094 0, // CPU16Regs_and_GPRMM16Zero:sub_lo
7095 0, // CPU16Regs_and_GPRMM16Zero:sub_hi_then_sub_32
7096 0, // CPU16Regs_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32
7097 },
7098 { // GPR32NONZERO_and_GPRMM16MoveP
7099 0, // GPR32NONZERO_and_GPRMM16MoveP:sub_32
7100 0, // GPR32NONZERO_and_GPRMM16MoveP:sub_64
7101 0, // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp16_19
7102 0, // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp20
7103 0, // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp21
7104 0, // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp22
7105 0, // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp23
7106 0, // GPR32NONZERO_and_GPRMM16MoveP:sub_hi
7107 0, // GPR32NONZERO_and_GPRMM16MoveP:sub_lo
7108 0, // GPR32NONZERO_and_GPRMM16MoveP:sub_hi_then_sub_32
7109 0, // GPR32NONZERO_and_GPRMM16MoveP:sub_32_sub_hi_then_sub_32
7110 },
7111 { // GPRMM16MovePPairSecond
7112 0, // GPRMM16MovePPairSecond:sub_32
7113 0, // GPRMM16MovePPairSecond:sub_64
7114 0, // GPRMM16MovePPairSecond:sub_dsp16_19
7115 0, // GPRMM16MovePPairSecond:sub_dsp20
7116 0, // GPRMM16MovePPairSecond:sub_dsp21
7117 0, // GPRMM16MovePPairSecond:sub_dsp22
7118 0, // GPRMM16MovePPairSecond:sub_dsp23
7119 0, // GPRMM16MovePPairSecond:sub_hi
7120 0, // GPRMM16MovePPairSecond:sub_lo
7121 0, // GPRMM16MovePPairSecond:sub_hi_then_sub_32
7122 0, // GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32
7123 },
7124 { // CPU16Regs_and_GPRMM16MoveP
7125 0, // CPU16Regs_and_GPRMM16MoveP:sub_32
7126 0, // CPU16Regs_and_GPRMM16MoveP:sub_64
7127 0, // CPU16Regs_and_GPRMM16MoveP:sub_dsp16_19
7128 0, // CPU16Regs_and_GPRMM16MoveP:sub_dsp20
7129 0, // CPU16Regs_and_GPRMM16MoveP:sub_dsp21
7130 0, // CPU16Regs_and_GPRMM16MoveP:sub_dsp22
7131 0, // CPU16Regs_and_GPRMM16MoveP:sub_dsp23
7132 0, // CPU16Regs_and_GPRMM16MoveP:sub_hi
7133 0, // CPU16Regs_and_GPRMM16MoveP:sub_lo
7134 0, // CPU16Regs_and_GPRMM16MoveP:sub_hi_then_sub_32
7135 0, // CPU16Regs_and_GPRMM16MoveP:sub_32_sub_hi_then_sub_32
7136 },
7137 { // GPRMM16MoveP_and_GPRMM16Zero
7138 0, // GPRMM16MoveP_and_GPRMM16Zero:sub_32
7139 0, // GPRMM16MoveP_and_GPRMM16Zero:sub_64
7140 0, // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp16_19
7141 0, // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp20
7142 0, // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp21
7143 0, // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp22
7144 0, // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp23
7145 0, // GPRMM16MoveP_and_GPRMM16Zero:sub_hi
7146 0, // GPRMM16MoveP_and_GPRMM16Zero:sub_lo
7147 0, // GPRMM16MoveP_and_GPRMM16Zero:sub_hi_then_sub_32
7148 0, // GPRMM16MoveP_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32
7149 },
7150 { // HI32DSP
7151 0, // HI32DSP:sub_32
7152 0, // HI32DSP:sub_64
7153 0, // HI32DSP:sub_dsp16_19
7154 0, // HI32DSP:sub_dsp20
7155 0, // HI32DSP:sub_dsp21
7156 0, // HI32DSP:sub_dsp22
7157 0, // HI32DSP:sub_dsp23
7158 0, // HI32DSP:sub_hi
7159 0, // HI32DSP:sub_lo
7160 0, // HI32DSP:sub_hi_then_sub_32
7161 0, // HI32DSP:sub_32_sub_hi_then_sub_32
7162 },
7163 { // LO32DSP
7164 0, // LO32DSP:sub_32
7165 0, // LO32DSP:sub_64
7166 0, // LO32DSP:sub_dsp16_19
7167 0, // LO32DSP:sub_dsp20
7168 0, // LO32DSP:sub_dsp21
7169 0, // LO32DSP:sub_dsp22
7170 0, // LO32DSP:sub_dsp23
7171 0, // LO32DSP:sub_hi
7172 0, // LO32DSP:sub_lo
7173 0, // LO32DSP:sub_hi_then_sub_32
7174 0, // LO32DSP:sub_32_sub_hi_then_sub_32
7175 },
7176 { // CPU16Regs_and_GPRMM16MovePPairSecond
7177 0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_32
7178 0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_64
7179 0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp16_19
7180 0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp20
7181 0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp21
7182 0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp22
7183 0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp23
7184 0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_hi
7185 0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_lo
7186 0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_hi_then_sub_32
7187 0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32
7188 },
7189 { // GPRMM16MovePPairFirst
7190 0, // GPRMM16MovePPairFirst:sub_32
7191 0, // GPRMM16MovePPairFirst:sub_64
7192 0, // GPRMM16MovePPairFirst:sub_dsp16_19
7193 0, // GPRMM16MovePPairFirst:sub_dsp20
7194 0, // GPRMM16MovePPairFirst:sub_dsp21
7195 0, // GPRMM16MovePPairFirst:sub_dsp22
7196 0, // GPRMM16MovePPairFirst:sub_dsp23
7197 0, // GPRMM16MovePPairFirst:sub_hi
7198 0, // GPRMM16MovePPairFirst:sub_lo
7199 0, // GPRMM16MovePPairFirst:sub_hi_then_sub_32
7200 0, // GPRMM16MovePPairFirst:sub_32_sub_hi_then_sub_32
7201 },
7202 { // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
7203 0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_32
7204 0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_64
7205 0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp16_19
7206 0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp20
7207 0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp21
7208 0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp22
7209 0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp23
7210 0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_hi
7211 0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_lo
7212 0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_hi_then_sub_32
7213 0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32
7214 },
7215 { // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
7216 0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_32
7217 0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_64
7218 0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp16_19
7219 0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp20
7220 0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp21
7221 0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp22
7222 0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp23
7223 0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_hi
7224 0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_lo
7225 0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_hi_then_sub_32
7226 0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32
7227 },
7228 { // CPURAReg
7229 0, // CPURAReg:sub_32
7230 0, // CPURAReg:sub_64
7231 0, // CPURAReg:sub_dsp16_19
7232 0, // CPURAReg:sub_dsp20
7233 0, // CPURAReg:sub_dsp21
7234 0, // CPURAReg:sub_dsp22
7235 0, // CPURAReg:sub_dsp23
7236 0, // CPURAReg:sub_hi
7237 0, // CPURAReg:sub_lo
7238 0, // CPURAReg:sub_hi_then_sub_32
7239 0, // CPURAReg:sub_32_sub_hi_then_sub_32
7240 },
7241 { // CPUSPReg
7242 0, // CPUSPReg:sub_32
7243 0, // CPUSPReg:sub_64
7244 0, // CPUSPReg:sub_dsp16_19
7245 0, // CPUSPReg:sub_dsp20
7246 0, // CPUSPReg:sub_dsp21
7247 0, // CPUSPReg:sub_dsp22
7248 0, // CPUSPReg:sub_dsp23
7249 0, // CPUSPReg:sub_hi
7250 0, // CPUSPReg:sub_lo
7251 0, // CPUSPReg:sub_hi_then_sub_32
7252 0, // CPUSPReg:sub_32_sub_hi_then_sub_32
7253 },
7254 { // DSPCC
7255 0, // DSPCC:sub_32
7256 0, // DSPCC:sub_64
7257 0, // DSPCC:sub_dsp16_19
7258 0, // DSPCC:sub_dsp20
7259 0, // DSPCC:sub_dsp21
7260 0, // DSPCC:sub_dsp22
7261 0, // DSPCC:sub_dsp23
7262 0, // DSPCC:sub_hi
7263 0, // DSPCC:sub_lo
7264 0, // DSPCC:sub_hi_then_sub_32
7265 0, // DSPCC:sub_32_sub_hi_then_sub_32
7266 },
7267 { // GP32
7268 0, // GP32:sub_32
7269 0, // GP32:sub_64
7270 0, // GP32:sub_dsp16_19
7271 0, // GP32:sub_dsp20
7272 0, // GP32:sub_dsp21
7273 0, // GP32:sub_dsp22
7274 0, // GP32:sub_dsp23
7275 0, // GP32:sub_hi
7276 0, // GP32:sub_lo
7277 0, // GP32:sub_hi_then_sub_32
7278 0, // GP32:sub_32_sub_hi_then_sub_32
7279 },
7280 { // GPR32ZERO
7281 0, // GPR32ZERO:sub_32
7282 0, // GPR32ZERO:sub_64
7283 0, // GPR32ZERO:sub_dsp16_19
7284 0, // GPR32ZERO:sub_dsp20
7285 0, // GPR32ZERO:sub_dsp21
7286 0, // GPR32ZERO:sub_dsp22
7287 0, // GPR32ZERO:sub_dsp23
7288 0, // GPR32ZERO:sub_hi
7289 0, // GPR32ZERO:sub_lo
7290 0, // GPR32ZERO:sub_hi_then_sub_32
7291 0, // GPR32ZERO:sub_32_sub_hi_then_sub_32
7292 },
7293 { // HI32
7294 0, // HI32:sub_32
7295 0, // HI32:sub_64
7296 0, // HI32:sub_dsp16_19
7297 0, // HI32:sub_dsp20
7298 0, // HI32:sub_dsp21
7299 0, // HI32:sub_dsp22
7300 0, // HI32:sub_dsp23
7301 0, // HI32:sub_hi
7302 0, // HI32:sub_lo
7303 0, // HI32:sub_hi_then_sub_32
7304 0, // HI32:sub_32_sub_hi_then_sub_32
7305 },
7306 { // LO32
7307 0, // LO32:sub_32
7308 0, // LO32:sub_64
7309 0, // LO32:sub_dsp16_19
7310 0, // LO32:sub_dsp20
7311 0, // LO32:sub_dsp21
7312 0, // LO32:sub_dsp22
7313 0, // LO32:sub_dsp23
7314 0, // LO32:sub_hi
7315 0, // LO32:sub_lo
7316 0, // LO32:sub_hi_then_sub_32
7317 0, // LO32:sub_32_sub_hi_then_sub_32
7318 },
7319 { // SP32
7320 0, // SP32:sub_32
7321 0, // SP32:sub_64
7322 0, // SP32:sub_dsp16_19
7323 0, // SP32:sub_dsp20
7324 0, // SP32:sub_dsp21
7325 0, // SP32:sub_dsp22
7326 0, // SP32:sub_dsp23
7327 0, // SP32:sub_hi
7328 0, // SP32:sub_lo
7329 0, // SP32:sub_hi_then_sub_32
7330 0, // SP32:sub_32_sub_hi_then_sub_32
7331 },
7332 { // FGR64
7333 0, // FGR64:sub_32
7334 0, // FGR64:sub_64
7335 0, // FGR64:sub_dsp16_19
7336 0, // FGR64:sub_dsp20
7337 0, // FGR64:sub_dsp21
7338 0, // FGR64:sub_dsp22
7339 0, // FGR64:sub_dsp23
7340 0, // FGR64:sub_hi
7341 7, // FGR64:sub_lo -> FGR32
7342 0, // FGR64:sub_hi_then_sub_32
7343 0, // FGR64:sub_32_sub_hi_then_sub_32
7344 },
7345 { // GPR64
7346 6, // GPR64:sub_32 -> DSPR
7347 0, // GPR64:sub_64
7348 0, // GPR64:sub_dsp16_19
7349 0, // GPR64:sub_dsp20
7350 0, // GPR64:sub_dsp21
7351 0, // GPR64:sub_dsp22
7352 0, // GPR64:sub_dsp23
7353 0, // GPR64:sub_hi
7354 0, // GPR64:sub_lo
7355 0, // GPR64:sub_hi_then_sub_32
7356 0, // GPR64:sub_32_sub_hi_then_sub_32
7357 },
7358 { // GPR64_with_sub_32_in_GPR32NONZERO
7359 12, // GPR64_with_sub_32_in_GPR32NONZERO:sub_32 -> GPR32NONZERO
7360 0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_64
7361 0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp16_19
7362 0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp20
7363 0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp21
7364 0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp22
7365 0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp23
7366 0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_hi
7367 0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_lo
7368 0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_hi_then_sub_32
7369 0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_32_sub_hi_then_sub_32
7370 },
7371 { // AFGR64
7372 0, // AFGR64:sub_32
7373 0, // AFGR64:sub_64
7374 0, // AFGR64:sub_dsp16_19
7375 0, // AFGR64:sub_dsp20
7376 0, // AFGR64:sub_dsp21
7377 0, // AFGR64:sub_dsp22
7378 0, // AFGR64:sub_dsp23
7379 8, // AFGR64:sub_hi -> FGRCC
7380 8, // AFGR64:sub_lo -> FGRCC
7381 0, // AFGR64:sub_hi_then_sub_32
7382 0, // AFGR64:sub_32_sub_hi_then_sub_32
7383 },
7384 { // GPR64_with_sub_32_in_CPU16RegsPlusSP
7385 13, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_32 -> CPU16RegsPlusSP
7386 0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_64
7387 0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp16_19
7388 0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp20
7389 0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp21
7390 0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp22
7391 0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp23
7392 0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_hi
7393 0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_lo
7394 0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_hi_then_sub_32
7395 0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_32_sub_hi_then_sub_32
7396 },
7397 { // GPR64_with_sub_32_in_CPU16Regs
7398 14, // GPR64_with_sub_32_in_CPU16Regs:sub_32 -> CPU16Regs
7399 0, // GPR64_with_sub_32_in_CPU16Regs:sub_64
7400 0, // GPR64_with_sub_32_in_CPU16Regs:sub_dsp16_19
7401 0, // GPR64_with_sub_32_in_CPU16Regs:sub_dsp20
7402 0, // GPR64_with_sub_32_in_CPU16Regs:sub_dsp21
7403 0, // GPR64_with_sub_32_in_CPU16Regs:sub_dsp22
7404 0, // GPR64_with_sub_32_in_CPU16Regs:sub_dsp23
7405 0, // GPR64_with_sub_32_in_CPU16Regs:sub_hi
7406 0, // GPR64_with_sub_32_in_CPU16Regs:sub_lo
7407 0, // GPR64_with_sub_32_in_CPU16Regs:sub_hi_then_sub_32
7408 0, // GPR64_with_sub_32_in_CPU16Regs:sub_32_sub_hi_then_sub_32
7409 },
7410 { // GPR64_with_sub_32_in_GPRMM16MoveP
7411 17, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_32 -> GPRMM16MoveP
7412 0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_64
7413 0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp16_19
7414 0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp20
7415 0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp21
7416 0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp22
7417 0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp23
7418 0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_hi
7419 0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_lo
7420 0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_hi_then_sub_32
7421 0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_32_sub_hi_then_sub_32
7422 },
7423 { // GPR64_with_sub_32_in_GPRMM16Zero
7424 18, // GPR64_with_sub_32_in_GPRMM16Zero:sub_32 -> GPRMM16Zero
7425 0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_64
7426 0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp16_19
7427 0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp20
7428 0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp21
7429 0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp22
7430 0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp23
7431 0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_hi
7432 0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_lo
7433 0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_hi_then_sub_32
7434 0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_32_sub_hi_then_sub_32
7435 },
7436 { // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
7437 19, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_32 -> CPU16Regs_and_GPRMM16Zero
7438 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_64
7439 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp16_19
7440 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp20
7441 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp21
7442 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp22
7443 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp23
7444 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_hi
7445 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_lo
7446 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_hi_then_sub_32
7447 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32
7448 },
7449 { // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
7450 20, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_32 -> GPR32NONZERO_and_GPRMM16MoveP
7451 0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_64
7452 0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp16_19
7453 0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp20
7454 0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp21
7455 0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp22
7456 0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp23
7457 0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_hi
7458 0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_lo
7459 0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_hi_then_sub_32
7460 0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_32_sub_hi_then_sub_32
7461 },
7462 { // GPR64_with_sub_32_in_GPRMM16MovePPairSecond
7463 21, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_32 -> GPRMM16MovePPairSecond
7464 0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_64
7465 0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp16_19
7466 0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp20
7467 0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp21
7468 0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp22
7469 0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp23
7470 0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_hi
7471 0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_lo
7472 0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_hi_then_sub_32
7473 0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32
7474 },
7475 { // ACC64DSP
7476 0, // ACC64DSP:sub_32
7477 0, // ACC64DSP:sub_64
7478 0, // ACC64DSP:sub_dsp16_19
7479 0, // ACC64DSP:sub_dsp20
7480 0, // ACC64DSP:sub_dsp21
7481 0, // ACC64DSP:sub_dsp22
7482 0, // ACC64DSP:sub_dsp23
7483 24, // ACC64DSP:sub_hi -> HI32DSP
7484 25, // ACC64DSP:sub_lo -> LO32DSP
7485 0, // ACC64DSP:sub_hi_then_sub_32
7486 0, // ACC64DSP:sub_32_sub_hi_then_sub_32
7487 },
7488 { // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
7489 22, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_32 -> CPU16Regs_and_GPRMM16MoveP
7490 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_64
7491 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp16_19
7492 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp20
7493 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp21
7494 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp22
7495 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp23
7496 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_hi
7497 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_lo
7498 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_hi_then_sub_32
7499 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_32_sub_hi_then_sub_32
7500 },
7501 { // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
7502 23, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_32 -> GPRMM16MoveP_and_GPRMM16Zero
7503 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_64
7504 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp16_19
7505 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp20
7506 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp21
7507 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp22
7508 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp23
7509 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_hi
7510 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_lo
7511 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_hi_then_sub_32
7512 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32
7513 },
7514 { // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond
7515 26, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_32 -> CPU16Regs_and_GPRMM16MovePPairSecond
7516 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_64
7517 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp16_19
7518 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp20
7519 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp21
7520 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp22
7521 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp23
7522 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_hi
7523 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_lo
7524 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_hi_then_sub_32
7525 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32
7526 },
7527 { // GPR64_with_sub_32_in_GPRMM16MovePPairFirst
7528 27, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_32 -> GPRMM16MovePPairFirst
7529 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_64
7530 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp16_19
7531 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp20
7532 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp21
7533 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp22
7534 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp23
7535 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_hi
7536 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_lo
7537 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_hi_then_sub_32
7538 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_32_sub_hi_then_sub_32
7539 },
7540 { // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
7541 28, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_32 -> GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
7542 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_64
7543 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp16_19
7544 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp20
7545 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp21
7546 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp22
7547 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp23
7548 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_hi
7549 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_lo
7550 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_hi_then_sub_32
7551 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32
7552 },
7553 { // OCTEON_MPL
7554 0, // OCTEON_MPL:sub_32
7555 0, // OCTEON_MPL:sub_64
7556 0, // OCTEON_MPL:sub_dsp16_19
7557 0, // OCTEON_MPL:sub_dsp20
7558 0, // OCTEON_MPL:sub_dsp21
7559 0, // OCTEON_MPL:sub_dsp22
7560 0, // OCTEON_MPL:sub_dsp23
7561 0, // OCTEON_MPL:sub_hi
7562 0, // OCTEON_MPL:sub_lo
7563 0, // OCTEON_MPL:sub_hi_then_sub_32
7564 0, // OCTEON_MPL:sub_32_sub_hi_then_sub_32
7565 },
7566 { // OCTEON_P
7567 0, // OCTEON_P:sub_32
7568 0, // OCTEON_P:sub_64
7569 0, // OCTEON_P:sub_dsp16_19
7570 0, // OCTEON_P:sub_dsp20
7571 0, // OCTEON_P:sub_dsp21
7572 0, // OCTEON_P:sub_dsp22
7573 0, // OCTEON_P:sub_dsp23
7574 0, // OCTEON_P:sub_hi
7575 0, // OCTEON_P:sub_lo
7576 0, // OCTEON_P:sub_hi_then_sub_32
7577 0, // OCTEON_P:sub_32_sub_hi_then_sub_32
7578 },
7579 { // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
7580 29, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_32 -> GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
7581 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_64
7582 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp16_19
7583 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp20
7584 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp21
7585 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp22
7586 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp23
7587 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_hi
7588 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_lo
7589 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_hi_then_sub_32
7590 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32
7591 },
7592 { // ACC64
7593 0, // ACC64:sub_32
7594 0, // ACC64:sub_64
7595 0, // ACC64:sub_dsp16_19
7596 0, // ACC64:sub_dsp20
7597 0, // ACC64:sub_dsp21
7598 0, // ACC64:sub_dsp22
7599 0, // ACC64:sub_dsp23
7600 35, // ACC64:sub_hi -> HI32
7601 36, // ACC64:sub_lo -> LO32
7602 0, // ACC64:sub_hi_then_sub_32
7603 0, // ACC64:sub_32_sub_hi_then_sub_32
7604 },
7605 { // GP64
7606 33, // GP64:sub_32 -> GP32
7607 0, // GP64:sub_64
7608 0, // GP64:sub_dsp16_19
7609 0, // GP64:sub_dsp20
7610 0, // GP64:sub_dsp21
7611 0, // GP64:sub_dsp22
7612 0, // GP64:sub_dsp23
7613 0, // GP64:sub_hi
7614 0, // GP64:sub_lo
7615 0, // GP64:sub_hi_then_sub_32
7616 0, // GP64:sub_32_sub_hi_then_sub_32
7617 },
7618 { // GPR64_with_sub_32_in_CPURAReg
7619 30, // GPR64_with_sub_32_in_CPURAReg:sub_32 -> CPURAReg
7620 0, // GPR64_with_sub_32_in_CPURAReg:sub_64
7621 0, // GPR64_with_sub_32_in_CPURAReg:sub_dsp16_19
7622 0, // GPR64_with_sub_32_in_CPURAReg:sub_dsp20
7623 0, // GPR64_with_sub_32_in_CPURAReg:sub_dsp21
7624 0, // GPR64_with_sub_32_in_CPURAReg:sub_dsp22
7625 0, // GPR64_with_sub_32_in_CPURAReg:sub_dsp23
7626 0, // GPR64_with_sub_32_in_CPURAReg:sub_hi
7627 0, // GPR64_with_sub_32_in_CPURAReg:sub_lo
7628 0, // GPR64_with_sub_32_in_CPURAReg:sub_hi_then_sub_32
7629 0, // GPR64_with_sub_32_in_CPURAReg:sub_32_sub_hi_then_sub_32
7630 },
7631 { // GPR64_with_sub_32_in_GPR32ZERO
7632 34, // GPR64_with_sub_32_in_GPR32ZERO:sub_32 -> GPR32ZERO
7633 0, // GPR64_with_sub_32_in_GPR32ZERO:sub_64
7634 0, // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp16_19
7635 0, // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp20
7636 0, // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp21
7637 0, // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp22
7638 0, // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp23
7639 0, // GPR64_with_sub_32_in_GPR32ZERO:sub_hi
7640 0, // GPR64_with_sub_32_in_GPR32ZERO:sub_lo
7641 0, // GPR64_with_sub_32_in_GPR32ZERO:sub_hi_then_sub_32
7642 0, // GPR64_with_sub_32_in_GPR32ZERO:sub_32_sub_hi_then_sub_32
7643 },
7644 { // HI64
7645 35, // HI64:sub_32 -> HI32
7646 0, // HI64:sub_64
7647 0, // HI64:sub_dsp16_19
7648 0, // HI64:sub_dsp20
7649 0, // HI64:sub_dsp21
7650 0, // HI64:sub_dsp22
7651 0, // HI64:sub_dsp23
7652 0, // HI64:sub_hi
7653 0, // HI64:sub_lo
7654 0, // HI64:sub_hi_then_sub_32
7655 0, // HI64:sub_32_sub_hi_then_sub_32
7656 },
7657 { // LO64
7658 36, // LO64:sub_32 -> LO32
7659 0, // LO64:sub_64
7660 0, // LO64:sub_dsp16_19
7661 0, // LO64:sub_dsp20
7662 0, // LO64:sub_dsp21
7663 0, // LO64:sub_dsp22
7664 0, // LO64:sub_dsp23
7665 0, // LO64:sub_hi
7666 0, // LO64:sub_lo
7667 0, // LO64:sub_hi_then_sub_32
7668 0, // LO64:sub_32_sub_hi_then_sub_32
7669 },
7670 { // SP64
7671 31, // SP64:sub_32 -> CPUSPReg
7672 0, // SP64:sub_64
7673 0, // SP64:sub_dsp16_19
7674 0, // SP64:sub_dsp20
7675 0, // SP64:sub_dsp21
7676 0, // SP64:sub_dsp22
7677 0, // SP64:sub_dsp23
7678 0, // SP64:sub_hi
7679 0, // SP64:sub_lo
7680 0, // SP64:sub_hi_then_sub_32
7681 0, // SP64:sub_32_sub_hi_then_sub_32
7682 },
7683 { // MSA128B
7684 0, // MSA128B:sub_32
7685 38, // MSA128B:sub_64 -> FGR64
7686 0, // MSA128B:sub_dsp16_19
7687 0, // MSA128B:sub_dsp20
7688 0, // MSA128B:sub_dsp21
7689 0, // MSA128B:sub_dsp22
7690 0, // MSA128B:sub_dsp23
7691 0, // MSA128B:sub_hi
7692 7, // MSA128B:sub_lo -> FGR32
7693 0, // MSA128B:sub_hi_then_sub_32
7694 0, // MSA128B:sub_32_sub_hi_then_sub_32
7695 },
7696 { // MSA128D
7697 0, // MSA128D:sub_32
7698 38, // MSA128D:sub_64 -> FGR64
7699 0, // MSA128D:sub_dsp16_19
7700 0, // MSA128D:sub_dsp20
7701 0, // MSA128D:sub_dsp21
7702 0, // MSA128D:sub_dsp22
7703 0, // MSA128D:sub_dsp23
7704 0, // MSA128D:sub_hi
7705 7, // MSA128D:sub_lo -> FGR32
7706 0, // MSA128D:sub_hi_then_sub_32
7707 0, // MSA128D:sub_32_sub_hi_then_sub_32
7708 },
7709 { // MSA128H
7710 0, // MSA128H:sub_32
7711 38, // MSA128H:sub_64 -> FGR64
7712 0, // MSA128H:sub_dsp16_19
7713 0, // MSA128H:sub_dsp20
7714 0, // MSA128H:sub_dsp21
7715 0, // MSA128H:sub_dsp22
7716 0, // MSA128H:sub_dsp23
7717 0, // MSA128H:sub_hi
7718 7, // MSA128H:sub_lo -> FGR32
7719 0, // MSA128H:sub_hi_then_sub_32
7720 0, // MSA128H:sub_32_sub_hi_then_sub_32
7721 },
7722 { // MSA128W
7723 0, // MSA128W:sub_32
7724 38, // MSA128W:sub_64 -> FGR64
7725 0, // MSA128W:sub_dsp16_19
7726 0, // MSA128W:sub_dsp20
7727 0, // MSA128W:sub_dsp21
7728 0, // MSA128W:sub_dsp22
7729 0, // MSA128W:sub_dsp23
7730 0, // MSA128W:sub_hi
7731 7, // MSA128W:sub_lo -> FGR32
7732 0, // MSA128W:sub_hi_then_sub_32
7733 0, // MSA128W:sub_32_sub_hi_then_sub_32
7734 },
7735 { // MSA128WEvens
7736 0, // MSA128WEvens:sub_32
7737 38, // MSA128WEvens:sub_64 -> FGR64
7738 0, // MSA128WEvens:sub_dsp16_19
7739 0, // MSA128WEvens:sub_dsp20
7740 0, // MSA128WEvens:sub_dsp21
7741 0, // MSA128WEvens:sub_dsp22
7742 0, // MSA128WEvens:sub_dsp23
7743 0, // MSA128WEvens:sub_hi
7744 8, // MSA128WEvens:sub_lo -> FGRCC
7745 0, // MSA128WEvens:sub_hi_then_sub_32
7746 0, // MSA128WEvens:sub_32_sub_hi_then_sub_32
7747 },
7748 { // ACC128
7749 36, // ACC128:sub_32 -> LO32
7750 0, // ACC128:sub_64
7751 0, // ACC128:sub_dsp16_19
7752 0, // ACC128:sub_dsp20
7753 0, // ACC128:sub_dsp21
7754 0, // ACC128:sub_dsp22
7755 0, // ACC128:sub_dsp23
7756 62, // ACC128:sub_hi -> HI64
7757 63, // ACC128:sub_lo -> LO64
7758 35, // ACC128:sub_hi_then_sub_32 -> HI32
7759 58, // ACC128:sub_32_sub_hi_then_sub_32 -> ACC64
7760 },
7761 };
7762 assert(RC && "Missing regclass");
7763 if (!Idx) return RC;
7764 --Idx;
7765 assert(Idx < 11 && "Bad subreg");
7766 unsigned TV = Table[RC->getID()][Idx];
7767 return TV ? getRegClass(TV - 1) : nullptr;
7768}
7769
7770/// Get the weight in units of pressure for this register class.
7771const RegClassWeight &MipsGenRegisterInfo::
7772getRegClassWeight(const TargetRegisterClass *RC) const {
7773 static const RegClassWeight RCWeightTable[] = {
7774 {2, 64}, // MSA128F16
7775 {0, 0}, // CCR
7776 {0, 0}, // COP0
7777 {0, 0}, // COP2
7778 {0, 0}, // COP3
7779 {1, 32}, // DSPR
7780 {1, 32}, // FGR32
7781 {1, 32}, // FGRCC
7782 {1, 32}, // GPR32
7783 {0, 0}, // HWRegs
7784 {0, 0}, // MSACtrl
7785 {1, 31}, // GPR32NONZERO
7786 {1, 9}, // CPU16RegsPlusSP
7787 {1, 8}, // CPU16Regs
7788 {0, 0}, // FCC
7789 {1, 8}, // GPRMM16
7790 {1, 8}, // GPRMM16MoveP
7791 {1, 8}, // GPRMM16Zero
7792 {1, 7}, // CPU16Regs_and_GPRMM16Zero
7793 {1, 7}, // GPR32NONZERO_and_GPRMM16MoveP
7794 {1, 5}, // GPRMM16MovePPairSecond
7795 {1, 4}, // CPU16Regs_and_GPRMM16MoveP
7796 {1, 4}, // GPRMM16MoveP_and_GPRMM16Zero
7797 {1, 4}, // HI32DSP
7798 {1, 4}, // LO32DSP
7799 {1, 3}, // CPU16Regs_and_GPRMM16MovePPairSecond
7800 {1, 3}, // GPRMM16MovePPairFirst
7801 {1, 3}, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
7802 {1, 2}, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
7803 {1, 1}, // CPURAReg
7804 {1, 1}, // CPUSPReg
7805 {1, 1}, // DSPCC
7806 {1, 1}, // GP32
7807 {1, 1}, // GPR32ZERO
7808 {1, 1}, // HI32
7809 {1, 1}, // LO32
7810 {1, 1}, // SP32
7811 {2, 64}, // FGR64
7812 {1, 32}, // GPR64
7813 {1, 31}, // GPR64_with_sub_32_in_GPR32NONZERO
7814 {2, 32}, // AFGR64
7815 {1, 9}, // GPR64_with_sub_32_in_CPU16RegsPlusSP
7816 {1, 8}, // GPR64_with_sub_32_in_CPU16Regs
7817 {1, 8}, // GPR64_with_sub_32_in_GPRMM16MoveP
7818 {1, 8}, // GPR64_with_sub_32_in_GPRMM16Zero
7819 {1, 7}, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
7820 {1, 7}, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
7821 {1, 5}, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond
7822 {2, 8}, // ACC64DSP
7823 {1, 4}, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
7824 {1, 4}, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
7825 {1, 3}, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond
7826 {1, 3}, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst
7827 {1, 3}, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
7828 {0, 0}, // OCTEON_MPL
7829 {0, 0}, // OCTEON_P
7830 {1, 2}, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
7831 {2, 2}, // ACC64
7832 {1, 1}, // GP64
7833 {1, 1}, // GPR64_with_sub_32_in_CPURAReg
7834 {1, 1}, // GPR64_with_sub_32_in_GPR32ZERO
7835 {1, 1}, // HI64
7836 {1, 1}, // LO64
7837 {1, 1}, // SP64
7838 {2, 64}, // MSA128B
7839 {2, 64}, // MSA128D
7840 {2, 64}, // MSA128H
7841 {2, 64}, // MSA128W
7842 {2, 32}, // MSA128WEvens
7843 {2, 2}, // ACC128
7844 };
7845 return RCWeightTable[RC->getID()];
7846}
7847
7848/// Get the weight in units of pressure for this register unit.
7849unsigned MipsGenRegisterInfo::
7850getRegUnitWeight(unsigned RegUnit) const {
7851 assert(RegUnit < 321 && "invalid register unit");
7852 // All register units have unit weight.
7853 return 1;
7854}
7855
7856
7857// Get the number of dimensions of register pressure.
7858unsigned MipsGenRegisterInfo::getNumRegPressureSets() const {
7859 return 20;
7860}
7861
7862// Get the name of this register unit pressure set.
7863const char *MipsGenRegisterInfo::
7864getRegPressureSetName(unsigned Idx) const {
7865 static const char *PressureNameTable[] = {
7866 "DSPCC",
7867 "GPR32ZERO",
7868 "GPR64_with_sub_32_in_CPURAReg",
7869 "HI32",
7870 "GPRMM16MovePPairFirst",
7871 "CPU16Regs_and_GPRMM16MoveP",
7872 "HI32DSP",
7873 "LO32DSP",
7874 "GPRMM16MovePPairSecond",
7875 "GPRMM16MoveP",
7876 "ACC64DSP",
7877 "CPU16Regs",
7878 "GPRMM16Zero_with_GPRMM16MovePPairSecond",
7879 "CPU16Regs_with_GPRMM16MovePPairSecond",
7880 "CPU16Regs_with_GPRMM16MoveP",
7881 "DSPR",
7882 "FGR32",
7883 "MSA128WEvens",
7884 "FGR32_with_MSA128WEvens",
7885 "MSA128F16",
7886 };
7887 return PressureNameTable[Idx];
7888}
7889
7890// Get the register unit pressure limit for this dimension.
7891// This limit must be adjusted dynamically for reserved registers.
7892unsigned MipsGenRegisterInfo::
7893getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
7894 static const uint8_t PressureLimitTable[] = {
7895 1, // 0: DSPCC
7896 1, // 1: GPR32ZERO
7897 1, // 2: GPR64_with_sub_32_in_CPURAReg
7898 2, // 3: HI32
7899 3, // 4: GPRMM16MovePPairFirst
7900 5, // 5: CPU16Regs_and_GPRMM16MoveP
7901 5, // 6: HI32DSP
7902 5, // 7: LO32DSP
7903 6, // 8: GPRMM16MovePPairSecond
7904 8, // 9: GPRMM16MoveP
7905 8, // 10: ACC64DSP
7906 10, // 11: CPU16Regs
7907 10, // 12: GPRMM16Zero_with_GPRMM16MovePPairSecond
7908 11, // 13: CPU16Regs_with_GPRMM16MovePPairSecond
7909 13, // 14: CPU16Regs_with_GPRMM16MoveP
7910 32, // 15: DSPR
7911 32, // 16: FGR32
7912 32, // 17: MSA128WEvens
7913 48, // 18: FGR32_with_MSA128WEvens
7914 64, // 19: MSA128F16
7915 };
7916 return PressureLimitTable[Idx];
7917}
7918
7919/// Table of pressure sets per register class or unit.
7920static const int RCSetsTable[] = {
7921 /* 0 */ 0, -1,
7922 /* 2 */ 6, 10, -1,
7923 /* 5 */ 3, 6, 7, 10, -1,
7924 /* 10 */ 2, 15, -1,
7925 /* 13 */ 8, 12, 13, 15, -1,
7926 /* 18 */ 9, 14, 15, -1,
7927 /* 22 */ 1, 5, 9, 11, 12, 14, 15, -1,
7928 /* 30 */ 5, 9, 11, 13, 14, 15, -1,
7929 /* 37 */ 4, 8, 11, 12, 13, 14, 15, -1,
7930 /* 45 */ 5, 9, 11, 12, 13, 14, 15, -1,
7931 /* 53 */ 16, 18, 19, -1,
7932 /* 57 */ 16, 17, 18, 19, -1,
7933};
7934
7935/// Get the dimensions of register pressure impacted by this register class.
7936/// Returns a -1 terminated array of pressure set IDs
7937const int *MipsGenRegisterInfo::
7938getRegClassPressureSets(const TargetRegisterClass *RC) const {
7939 static const uint8_t RCSetStartTable[] = {
7940 55,1,1,1,1,11,53,53,11,1,1,11,32,32,1,32,18,25,39,18,13,30,23,2,7,38,37,45,37,1,1,0,1,22,5,5,1,55,11,11,53,32,32,18,25,39,18,13,3,30,23,38,37,45,1,1,37,5,1,10,22,5,5,1,55,55,55,55,58,5,};
7941 return &RCSetsTable[RCSetStartTable[RC->getID()]];
7942}
7943
7944/// Get the dimensions of register pressure impacted by this register unit.
7945/// Returns a -1 terminated array of pressure set IDs
7946const int *MipsGenRegisterInfo::
7947getRegUnitPressureSets(unsigned RegUnit) const {
7948 assert(RegUnit < 321 && "invalid register unit");
7949 static const uint8_t RUSetStartTable[] = {
7950 11,0,1,1,1,1,1,1,1,1,1,11,11,1,1,1,1,1,1,1,1,1,10,32,22,37,37,37,38,5,5,7,2,7,2,7,2,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,11,11,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,30,45,18,18,18,13,13,11,11,11,11,11,11,11,11,11,11,11,45,45,};
7951 return &RCSetsTable[RUSetStartTable[RegUnit]];
7952}
7953
7954extern const MCRegisterDesc MipsRegDesc[];
7955extern const int16_t MipsRegDiffLists[];
7956extern const LaneBitmask MipsLaneMaskLists[];
7957extern const char MipsRegStrings[];
7958extern const char MipsRegClassStrings[];
7959extern const MCPhysReg MipsRegUnitRoots[][2];
7960extern const uint16_t MipsSubRegIdxLists[];
7961extern const uint16_t MipsRegEncodingTable[];
7962// Mips Dwarf<->LLVM register mappings.
7963extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0Dwarf2L[];
7964extern const unsigned MipsDwarfFlavour0Dwarf2LSize;
7965
7966extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0Dwarf2L[];
7967extern const unsigned MipsEHFlavour0Dwarf2LSize;
7968
7969extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0L2Dwarf[];
7970extern const unsigned MipsDwarfFlavour0L2DwarfSize;
7971
7972extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0L2Dwarf[];
7973extern const unsigned MipsEHFlavour0L2DwarfSize;
7974
7975MipsGenRegisterInfo::
7976MipsGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
7977 unsigned PC, unsigned HwMode)
7978 : TargetRegisterInfo(&MipsRegInfoDesc, RegisterClasses, RegisterClasses+70,
7979 SubRegIndexNameTable, SubRegIdxRangeTable, SubRegIndexLaneMaskTable,
7980 LaneBitmask(0xFFFFFFFFFFFFFF80), RegClassInfos, VTLists, HwMode) {
7981 InitMCRegisterInfo(MipsRegDesc, 442, RA, PC,
7982 MipsMCRegisterClasses, 70,
7983 MipsRegUnitRoots,
7984 321,
7985 MipsRegDiffLists,
7986 MipsLaneMaskLists,
7987 MipsRegStrings,
7988 MipsRegClassStrings,
7989 MipsSubRegIdxLists,
7990 12,
7991 MipsRegEncodingTable);
7992
7993 switch (DwarfFlavour) {
7994 default:
7995 llvm_unreachable("Unknown DWARF flavour");
7996 case 0:
7997 mapDwarfRegsToLLVMRegs(MipsDwarfFlavour0Dwarf2L, MipsDwarfFlavour0Dwarf2LSize, false);
7998 break;
7999 }
8000 switch (EHFlavour) {
8001 default:
8002 llvm_unreachable("Unknown DWARF flavour");
8003 case 0:
8004 mapDwarfRegsToLLVMRegs(MipsEHFlavour0Dwarf2L, MipsEHFlavour0Dwarf2LSize, true);
8005 break;
8006 }
8007 switch (DwarfFlavour) {
8008 default:
8009 llvm_unreachable("Unknown DWARF flavour");
8010 case 0:
8011 mapLLVMRegsToDwarfRegs(MipsDwarfFlavour0L2Dwarf, MipsDwarfFlavour0L2DwarfSize, false);
8012 break;
8013 }
8014 switch (EHFlavour) {
8015 default:
8016 llvm_unreachable("Unknown DWARF flavour");
8017 case 0:
8018 mapLLVMRegsToDwarfRegs(MipsEHFlavour0L2Dwarf, MipsEHFlavour0L2DwarfSize, true);
8019 break;
8020 }
8021}
8022
8023static const MCPhysReg CSR_Interrupt_32_SaveList[] = { Mips::A3, Mips::A2, Mips::A1, Mips::A0, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, Mips::V1, Mips::V0, Mips::T9, Mips::T8, Mips::T7, Mips::T6, Mips::T5, Mips::T4, Mips::T3, Mips::T2, Mips::T1, Mips::T0, Mips::RA, Mips::FP, Mips::GP, Mips::AT, Mips::LO0, Mips::HI0, 0 };
8024static const uint32_t CSR_Interrupt_32_RegMask[] = { 0x07e80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x20000000, 0x00000000, 0x00000008, 0x07ffbfc0, 0x08000000, 0x00000000, 0x00000000, };
8025static const MCPhysReg CSR_Interrupt_32R6_SaveList[] = { Mips::A3, Mips::A2, Mips::A1, Mips::A0, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, Mips::V1, Mips::V0, Mips::T9, Mips::T8, Mips::T7, Mips::T6, Mips::T5, Mips::T4, Mips::T3, Mips::T2, Mips::T1, Mips::T0, Mips::RA, Mips::FP, Mips::GP, Mips::AT, 0 };
8026static const uint32_t CSR_Interrupt_32R6_RegMask[] = { 0x03e80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x07ffbfc0, 0x08000000, 0x00000000, 0x00000000, };
8027static const MCPhysReg CSR_Interrupt_64_SaveList[] = { Mips::A3_64, Mips::A2_64, Mips::A1_64, Mips::A0_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, Mips::T9_64, Mips::T8_64, Mips::T7_64, Mips::T6_64, Mips::T5_64, Mips::T4_64, Mips::T3_64, Mips::T2_64, Mips::T1_64, Mips::T0_64, Mips::V1_64, Mips::V0_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::AT_64, Mips::LO0_64, Mips::HI0_64, 0 };
8028static const uint32_t CSR_Interrupt_64_RegMask[] = { 0x47e80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x30000000, 0x00000000, 0x00000008, 0x07ffbfe0, 0xf8000000, 0x00000001, 0x03ffffe4, };
8029static const MCPhysReg CSR_Interrupt_64R6_SaveList[] = { Mips::A3_64, Mips::A2_64, Mips::A1_64, Mips::A0_64, Mips::V1_64, Mips::V0_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, Mips::T9_64, Mips::T8_64, Mips::T7_64, Mips::T6_64, Mips::T5_64, Mips::T4_64, Mips::T3_64, Mips::T2_64, Mips::T1_64, Mips::T0_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::AT_64, 0 };
8030static const uint32_t CSR_Interrupt_64R6_RegMask[] = { 0x43e80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x10000000, 0x00000000, 0x00000000, 0x07ffbfe0, 0xf8000000, 0x00000000, 0x03ffffc0, };
8031static const MCPhysReg CSR_Mips16RetHelper_SaveList[] = { Mips::V0, Mips::V1, Mips::FP, Mips::A3, Mips::A2, Mips::A1, Mips::A0, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, 0 };
8032static const uint32_t CSR_Mips16RetHelper_RegMask[] = { 0x03e00100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x06003fc0, 0x08000000, 0x00000000, 0x00000000, };
8033static const MCPhysReg CSR_N32_SaveList[] = { Mips::D20_64, Mips::D22_64, Mips::D24_64, Mips::D26_64, Mips::D28_64, Mips::D30_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, 0 };
8034static const uint32_t CSR_N32_RegMask[] = { 0x00280300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0002aa80, 0x08000000, 0x15550000, 0x00000000, 0x00000000, 0x00003fe0, 0x08000000, 0xaaa00000, 0x00003fc0, };
8035static const MCPhysReg CSR_N64_SaveList[] = { Mips::D31_64, Mips::D30_64, Mips::D29_64, Mips::D28_64, Mips::D27_64, Mips::D26_64, Mips::D25_64, Mips::D24_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, 0 };
8036static const uint32_t CSR_N64_RegMask[] = { 0x00280300, 0x00000000, 0x00000000, 0x00000000, 0x00007800, 0x0007f800, 0x08000000, 0x1ff00000, 0x00000000, 0x00000000, 0x00003fe0, 0x08000000, 0xfe000000, 0x00003fc1, };
8037static const MCPhysReg CSR_O32_SaveList[] = { Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };
8038static const uint32_t CSR_O32_RegMask[] = { 0x00280100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00003fc0, 0x08000000, 0x00000000, 0x00000000, };
8039static const MCPhysReg CSR_O32_FP64_SaveList[] = { Mips::D30_64, Mips::D28_64, Mips::D26_64, Mips::D24_64, Mips::D22_64, Mips::D20_64, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };
8040static const uint32_t CSR_O32_FP64_RegMask[] = { 0x00280100, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0002aa80, 0x00000000, 0x05550000, 0x00000000, 0x00000000, 0x00003fc0, 0x08000000, 0xaaa00000, 0x00000000, };
8041static const MCPhysReg CSR_O32_FPXX_SaveList[] = { Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };
8042static const uint32_t CSR_O32_FPXX_RegMask[] = { 0x00280100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00003fc0, 0x08000000, 0x00000000, 0x00000000, };
8043static const MCPhysReg CSR_SingleFloatOnly_SaveList[] = { Mips::F31, Mips::F30, Mips::F29, Mips::F28, Mips::F27, Mips::F26, Mips::F25, Mips::F24, Mips::F23, Mips::F22, Mips::F21, Mips::F20, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };
8044static const uint32_t CSR_SingleFloatOnly_RegMask[] = { 0x00280100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00003fc0, 0x08000000, 0x00000000, 0x00000000, };
8045
8046
8047ArrayRef<const uint32_t *> MipsGenRegisterInfo::getRegMasks() const {
8048 static const uint32_t *const Masks[] = {
8049 CSR_Interrupt_32_RegMask,
8050 CSR_Interrupt_32R6_RegMask,
8051 CSR_Interrupt_64_RegMask,
8052 CSR_Interrupt_64R6_RegMask,
8053 CSR_Mips16RetHelper_RegMask,
8054 CSR_N32_RegMask,
8055 CSR_N64_RegMask,
8056 CSR_O32_RegMask,
8057 CSR_O32_FP64_RegMask,
8058 CSR_O32_FPXX_RegMask,
8059 CSR_SingleFloatOnly_RegMask,
8060 };
8061 return ArrayRef(Masks);
8062}
8063
8064bool MipsGenRegisterInfo::
8065isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
8066 return
8067 false;
8068}
8069
8070bool MipsGenRegisterInfo::
8071isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
8072 return
8073 false;
8074}
8075
8076bool MipsGenRegisterInfo::
8077isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
8078 return
8079 false;
8080}
8081
8082bool MipsGenRegisterInfo::
8083isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
8084 return
8085 false;
8086}
8087
8088bool MipsGenRegisterInfo::
8089isConstantPhysReg(MCRegister PhysReg) const {
8090 return
8091 PhysReg == Mips::ZERO ||
8092 PhysReg == Mips::ZERO_64 ||
8093 false;
8094}
8095
8096ArrayRef<const char *> MipsGenRegisterInfo::getRegMaskNames() const {
8097 static const char *Names[] = {
8098 "CSR_Interrupt_32",
8099 "CSR_Interrupt_32R6",
8100 "CSR_Interrupt_64",
8101 "CSR_Interrupt_64R6",
8102 "CSR_Mips16RetHelper",
8103 "CSR_N32",
8104 "CSR_N64",
8105 "CSR_O32",
8106 "CSR_O32_FP64",
8107 "CSR_O32_FPXX",
8108 "CSR_SingleFloatOnly",
8109 };
8110 return ArrayRef(Names);
8111}
8112
8113const MipsFrameLowering *
8114MipsGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
8115 return static_cast<const MipsFrameLowering *>(
8116 MF.getSubtarget().getFrameLowering());
8117}
8118
8119} // end namespace llvm
8120
8121#endif // GET_REGINFO_TARGET_DESC
8122
8123