1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Machine Code Emitter *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9uint64_t MipsMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
10 SmallVectorImpl<MCFixup> &Fixups,
11 const MCSubtargetInfo &STI) const {
12 static const uint64_t InstBits[] = {
13 UINT64_C(0),
14 UINT64_C(0),
15 UINT64_C(0),
16 UINT64_C(0),
17 UINT64_C(0),
18 UINT64_C(0),
19 UINT64_C(0),
20 UINT64_C(0),
21 UINT64_C(0),
22 UINT64_C(0),
23 UINT64_C(0),
24 UINT64_C(0),
25 UINT64_C(0),
26 UINT64_C(0),
27 UINT64_C(0),
28 UINT64_C(0),
29 UINT64_C(0),
30 UINT64_C(0),
31 UINT64_C(0),
32 UINT64_C(0),
33 UINT64_C(0),
34 UINT64_C(0),
35 UINT64_C(0),
36 UINT64_C(0),
37 UINT64_C(0),
38 UINT64_C(0),
39 UINT64_C(0),
40 UINT64_C(0),
41 UINT64_C(0),
42 UINT64_C(0),
43 UINT64_C(0),
44 UINT64_C(0),
45 UINT64_C(0),
46 UINT64_C(0),
47 UINT64_C(0),
48 UINT64_C(0),
49 UINT64_C(0),
50 UINT64_C(0),
51 UINT64_C(0),
52 UINT64_C(0),
53 UINT64_C(0),
54 UINT64_C(0),
55 UINT64_C(0),
56 UINT64_C(0),
57 UINT64_C(0),
58 UINT64_C(0),
59 UINT64_C(0),
60 UINT64_C(0),
61 UINT64_C(0),
62 UINT64_C(0),
63 UINT64_C(0),
64 UINT64_C(0),
65 UINT64_C(0),
66 UINT64_C(0),
67 UINT64_C(0),
68 UINT64_C(0),
69 UINT64_C(0),
70 UINT64_C(0),
71 UINT64_C(0),
72 UINT64_C(0),
73 UINT64_C(0),
74 UINT64_C(0),
75 UINT64_C(0),
76 UINT64_C(0),
77 UINT64_C(0),
78 UINT64_C(0),
79 UINT64_C(0),
80 UINT64_C(0),
81 UINT64_C(0),
82 UINT64_C(0),
83 UINT64_C(0),
84 UINT64_C(0),
85 UINT64_C(0),
86 UINT64_C(0),
87 UINT64_C(0),
88 UINT64_C(0),
89 UINT64_C(0),
90 UINT64_C(0),
91 UINT64_C(0),
92 UINT64_C(0),
93 UINT64_C(0),
94 UINT64_C(0),
95 UINT64_C(0),
96 UINT64_C(0),
97 UINT64_C(0),
98 UINT64_C(0),
99 UINT64_C(0),
100 UINT64_C(0),
101 UINT64_C(0),
102 UINT64_C(0),
103 UINT64_C(0),
104 UINT64_C(0),
105 UINT64_C(0),
106 UINT64_C(0),
107 UINT64_C(0),
108 UINT64_C(0),
109 UINT64_C(0),
110 UINT64_C(0),
111 UINT64_C(0),
112 UINT64_C(0),
113 UINT64_C(0),
114 UINT64_C(0),
115 UINT64_C(0),
116 UINT64_C(0),
117 UINT64_C(0),
118 UINT64_C(0),
119 UINT64_C(0),
120 UINT64_C(0),
121 UINT64_C(0),
122 UINT64_C(0),
123 UINT64_C(0),
124 UINT64_C(0),
125 UINT64_C(0),
126 UINT64_C(0),
127 UINT64_C(0),
128 UINT64_C(0),
129 UINT64_C(0),
130 UINT64_C(0),
131 UINT64_C(0),
132 UINT64_C(0),
133 UINT64_C(0),
134 UINT64_C(0),
135 UINT64_C(0),
136 UINT64_C(0),
137 UINT64_C(0),
138 UINT64_C(0),
139 UINT64_C(0),
140 UINT64_C(0),
141 UINT64_C(0),
142 UINT64_C(0),
143 UINT64_C(0),
144 UINT64_C(0),
145 UINT64_C(0),
146 UINT64_C(0),
147 UINT64_C(0),
148 UINT64_C(0),
149 UINT64_C(0),
150 UINT64_C(0),
151 UINT64_C(0),
152 UINT64_C(0),
153 UINT64_C(0),
154 UINT64_C(0),
155 UINT64_C(0),
156 UINT64_C(0),
157 UINT64_C(0),
158 UINT64_C(0),
159 UINT64_C(0),
160 UINT64_C(0),
161 UINT64_C(0),
162 UINT64_C(0),
163 UINT64_C(0),
164 UINT64_C(0),
165 UINT64_C(0),
166 UINT64_C(0),
167 UINT64_C(0),
168 UINT64_C(0),
169 UINT64_C(0),
170 UINT64_C(0),
171 UINT64_C(0),
172 UINT64_C(0),
173 UINT64_C(0),
174 UINT64_C(0),
175 UINT64_C(0),
176 UINT64_C(0),
177 UINT64_C(0),
178 UINT64_C(0),
179 UINT64_C(0),
180 UINT64_C(0),
181 UINT64_C(0),
182 UINT64_C(0),
183 UINT64_C(0),
184 UINT64_C(0),
185 UINT64_C(0),
186 UINT64_C(0),
187 UINT64_C(0),
188 UINT64_C(0),
189 UINT64_C(0),
190 UINT64_C(0),
191 UINT64_C(0),
192 UINT64_C(0),
193 UINT64_C(0),
194 UINT64_C(0),
195 UINT64_C(0),
196 UINT64_C(0),
197 UINT64_C(0),
198 UINT64_C(0),
199 UINT64_C(0),
200 UINT64_C(0),
201 UINT64_C(0),
202 UINT64_C(0),
203 UINT64_C(0),
204 UINT64_C(0),
205 UINT64_C(0),
206 UINT64_C(0),
207 UINT64_C(0),
208 UINT64_C(0),
209 UINT64_C(0),
210 UINT64_C(0),
211 UINT64_C(0),
212 UINT64_C(0),
213 UINT64_C(0),
214 UINT64_C(0),
215 UINT64_C(0),
216 UINT64_C(0),
217 UINT64_C(0),
218 UINT64_C(0),
219 UINT64_C(0),
220 UINT64_C(0),
221 UINT64_C(0),
222 UINT64_C(0),
223 UINT64_C(0),
224 UINT64_C(0),
225 UINT64_C(0),
226 UINT64_C(0),
227 UINT64_C(0),
228 UINT64_C(0),
229 UINT64_C(0),
230 UINT64_C(0),
231 UINT64_C(0),
232 UINT64_C(0),
233 UINT64_C(0),
234 UINT64_C(0),
235 UINT64_C(0),
236 UINT64_C(0),
237 UINT64_C(0),
238 UINT64_C(0),
239 UINT64_C(0),
240 UINT64_C(0),
241 UINT64_C(0),
242 UINT64_C(0),
243 UINT64_C(0),
244 UINT64_C(0),
245 UINT64_C(0),
246 UINT64_C(0),
247 UINT64_C(0),
248 UINT64_C(0),
249 UINT64_C(0),
250 UINT64_C(0),
251 UINT64_C(0),
252 UINT64_C(0),
253 UINT64_C(0),
254 UINT64_C(0),
255 UINT64_C(0),
256 UINT64_C(0),
257 UINT64_C(0),
258 UINT64_C(0),
259 UINT64_C(0),
260 UINT64_C(0),
261 UINT64_C(0),
262 UINT64_C(0),
263 UINT64_C(0),
264 UINT64_C(0),
265 UINT64_C(0),
266 UINT64_C(0),
267 UINT64_C(0),
268 UINT64_C(0),
269 UINT64_C(0),
270 UINT64_C(0),
271 UINT64_C(0),
272 UINT64_C(0),
273 UINT64_C(0),
274 UINT64_C(0),
275 UINT64_C(0),
276 UINT64_C(0),
277 UINT64_C(0),
278 UINT64_C(0),
279 UINT64_C(0),
280 UINT64_C(0),
281 UINT64_C(0),
282 UINT64_C(0),
283 UINT64_C(0),
284 UINT64_C(0),
285 UINT64_C(0),
286 UINT64_C(0),
287 UINT64_C(0),
288 UINT64_C(0),
289 UINT64_C(0),
290 UINT64_C(0),
291 UINT64_C(0),
292 UINT64_C(0),
293 UINT64_C(0),
294 UINT64_C(0),
295 UINT64_C(0),
296 UINT64_C(0),
297 UINT64_C(0),
298 UINT64_C(0),
299 UINT64_C(0),
300 UINT64_C(0),
301 UINT64_C(0),
302 UINT64_C(0),
303 UINT64_C(0),
304 UINT64_C(0),
305 UINT64_C(0),
306 UINT64_C(0),
307 UINT64_C(0),
308 UINT64_C(0),
309 UINT64_C(0),
310 UINT64_C(0),
311 UINT64_C(0),
312 UINT64_C(0),
313 UINT64_C(0),
314 UINT64_C(0),
315 UINT64_C(0),
316 UINT64_C(0),
317 UINT64_C(0),
318 UINT64_C(0),
319 UINT64_C(0),
320 UINT64_C(0),
321 UINT64_C(0),
322 UINT64_C(0),
323 UINT64_C(0),
324 UINT64_C(0),
325 UINT64_C(0),
326 UINT64_C(0),
327 UINT64_C(0),
328 UINT64_C(0),
329 UINT64_C(0),
330 UINT64_C(0),
331 UINT64_C(0),
332 UINT64_C(0),
333 UINT64_C(0),
334 UINT64_C(0),
335 UINT64_C(0),
336 UINT64_C(0),
337 UINT64_C(0),
338 UINT64_C(0),
339 UINT64_C(0),
340 UINT64_C(0),
341 UINT64_C(0),
342 UINT64_C(0),
343 UINT64_C(0),
344 UINT64_C(0),
345 UINT64_C(0),
346 UINT64_C(0),
347 UINT64_C(0),
348 UINT64_C(0),
349 UINT64_C(0),
350 UINT64_C(0),
351 UINT64_C(0),
352 UINT64_C(0),
353 UINT64_C(0),
354 UINT64_C(0),
355 UINT64_C(0),
356 UINT64_C(0),
357 UINT64_C(0),
358 UINT64_C(0),
359 UINT64_C(0),
360 UINT64_C(0),
361 UINT64_C(0),
362 UINT64_C(0),
363 UINT64_C(0),
364 UINT64_C(0),
365 UINT64_C(0),
366 UINT64_C(0),
367 UINT64_C(0),
368 UINT64_C(0),
369 UINT64_C(0),
370 UINT64_C(0),
371 UINT64_C(0),
372 UINT64_C(0),
373 UINT64_C(0),
374 UINT64_C(0),
375 UINT64_C(0),
376 UINT64_C(0),
377 UINT64_C(0),
378 UINT64_C(0),
379 UINT64_C(0),
380 UINT64_C(0),
381 UINT64_C(0),
382 UINT64_C(0),
383 UINT64_C(0),
384 UINT64_C(0),
385 UINT64_C(0),
386 UINT64_C(0),
387 UINT64_C(0),
388 UINT64_C(0),
389 UINT64_C(0),
390 UINT64_C(0),
391 UINT64_C(0),
392 UINT64_C(0),
393 UINT64_C(0),
394 UINT64_C(0),
395 UINT64_C(0),
396 UINT64_C(0),
397 UINT64_C(0),
398 UINT64_C(0),
399 UINT64_C(0),
400 UINT64_C(0),
401 UINT64_C(0),
402 UINT64_C(0),
403 UINT64_C(0),
404 UINT64_C(0),
405 UINT64_C(0),
406 UINT64_C(0),
407 UINT64_C(0),
408 UINT64_C(0),
409 UINT64_C(0),
410 UINT64_C(0),
411 UINT64_C(0),
412 UINT64_C(0),
413 UINT64_C(0),
414 UINT64_C(0),
415 UINT64_C(0),
416 UINT64_C(0),
417 UINT64_C(0),
418 UINT64_C(0),
419 UINT64_C(0),
420 UINT64_C(0),
421 UINT64_C(0),
422 UINT64_C(0),
423 UINT64_C(0),
424 UINT64_C(0),
425 UINT64_C(0),
426 UINT64_C(0),
427 UINT64_C(0),
428 UINT64_C(0),
429 UINT64_C(0),
430 UINT64_C(0),
431 UINT64_C(0),
432 UINT64_C(0),
433 UINT64_C(0),
434 UINT64_C(0),
435 UINT64_C(0),
436 UINT64_C(0),
437 UINT64_C(0),
438 UINT64_C(0),
439 UINT64_C(0),
440 UINT64_C(0),
441 UINT64_C(0),
442 UINT64_C(0),
443 UINT64_C(0),
444 UINT64_C(0),
445 UINT64_C(0),
446 UINT64_C(0),
447 UINT64_C(0),
448 UINT64_C(0),
449 UINT64_C(0),
450 UINT64_C(0),
451 UINT64_C(0),
452 UINT64_C(0),
453 UINT64_C(0),
454 UINT64_C(0),
455 UINT64_C(0),
456 UINT64_C(0),
457 UINT64_C(0),
458 UINT64_C(0),
459 UINT64_C(0),
460 UINT64_C(0),
461 UINT64_C(0),
462 UINT64_C(0),
463 UINT64_C(0),
464 UINT64_C(0),
465 UINT64_C(0),
466 UINT64_C(0),
467 UINT64_C(0),
468 UINT64_C(0),
469 UINT64_C(0),
470 UINT64_C(0),
471 UINT64_C(0),
472 UINT64_C(0),
473 UINT64_C(0),
474 UINT64_C(0),
475 UINT64_C(0),
476 UINT64_C(0),
477 UINT64_C(0),
478 UINT64_C(0),
479 UINT64_C(0),
480 UINT64_C(0),
481 UINT64_C(0),
482 UINT64_C(0),
483 UINT64_C(0),
484 UINT64_C(0),
485 UINT64_C(0),
486 UINT64_C(0),
487 UINT64_C(0),
488 UINT64_C(0),
489 UINT64_C(0),
490 UINT64_C(0),
491 UINT64_C(0),
492 UINT64_C(0),
493 UINT64_C(0),
494 UINT64_C(0),
495 UINT64_C(0),
496 UINT64_C(0),
497 UINT64_C(0),
498 UINT64_C(0),
499 UINT64_C(0),
500 UINT64_C(0),
501 UINT64_C(0),
502 UINT64_C(0),
503 UINT64_C(0),
504 UINT64_C(0),
505 UINT64_C(0),
506 UINT64_C(0),
507 UINT64_C(0),
508 UINT64_C(0),
509 UINT64_C(0),
510 UINT64_C(0),
511 UINT64_C(0),
512 UINT64_C(0),
513 UINT64_C(0),
514 UINT64_C(0),
515 UINT64_C(0),
516 UINT64_C(0),
517 UINT64_C(0),
518 UINT64_C(0),
519 UINT64_C(0),
520 UINT64_C(0),
521 UINT64_C(0),
522 UINT64_C(0),
523 UINT64_C(0),
524 UINT64_C(0),
525 UINT64_C(0),
526 UINT64_C(0),
527 UINT64_C(0),
528 UINT64_C(0),
529 UINT64_C(0),
530 UINT64_C(0),
531 UINT64_C(0),
532 UINT64_C(0),
533 UINT64_C(0),
534 UINT64_C(0),
535 UINT64_C(0),
536 UINT64_C(0),
537 UINT64_C(0),
538 UINT64_C(0),
539 UINT64_C(0),
540 UINT64_C(0),
541 UINT64_C(0),
542 UINT64_C(0),
543 UINT64_C(0),
544 UINT64_C(0),
545 UINT64_C(0),
546 UINT64_C(0),
547 UINT64_C(0),
548 UINT64_C(0),
549 UINT64_C(0),
550 UINT64_C(0),
551 UINT64_C(0),
552 UINT64_C(0),
553 UINT64_C(0),
554 UINT64_C(0),
555 UINT64_C(0),
556 UINT64_C(0),
557 UINT64_C(0),
558 UINT64_C(0),
559 UINT64_C(0),
560 UINT64_C(0),
561 UINT64_C(0),
562 UINT64_C(0),
563 UINT64_C(0),
564 UINT64_C(0),
565 UINT64_C(0),
566 UINT64_C(0),
567 UINT64_C(0),
568 UINT64_C(0),
569 UINT64_C(0),
570 UINT64_C(0),
571 UINT64_C(0),
572 UINT64_C(0),
573 UINT64_C(0),
574 UINT64_C(0),
575 UINT64_C(0),
576 UINT64_C(0),
577 UINT64_C(0),
578 UINT64_C(0),
579 UINT64_C(0),
580 UINT64_C(0),
581 UINT64_C(0),
582 UINT64_C(0),
583 UINT64_C(0),
584 UINT64_C(0),
585 UINT64_C(0),
586 UINT64_C(0),
587 UINT64_C(0),
588 UINT64_C(0),
589 UINT64_C(0),
590 UINT64_C(0),
591 UINT64_C(0),
592 UINT64_C(0),
593 UINT64_C(0),
594 UINT64_C(0),
595 UINT64_C(0),
596 UINT64_C(0),
597 UINT64_C(0),
598 UINT64_C(0),
599 UINT64_C(0),
600 UINT64_C(0),
601 UINT64_C(0),
602 UINT64_C(0),
603 UINT64_C(0),
604 UINT64_C(0),
605 UINT64_C(0),
606 UINT64_C(0),
607 UINT64_C(0),
608 UINT64_C(0),
609 UINT64_C(0),
610 UINT64_C(0),
611 UINT64_C(0),
612 UINT64_C(0),
613 UINT64_C(0),
614 UINT64_C(0),
615 UINT64_C(0),
616 UINT64_C(0),
617 UINT64_C(0),
618 UINT64_C(0),
619 UINT64_C(0),
620 UINT64_C(0),
621 UINT64_C(0),
622 UINT64_C(0),
623 UINT64_C(0),
624 UINT64_C(0),
625 UINT64_C(0),
626 UINT64_C(0),
627 UINT64_C(0),
628 UINT64_C(0),
629 UINT64_C(0),
630 UINT64_C(0),
631 UINT64_C(0),
632 UINT64_C(0),
633 UINT64_C(0),
634 UINT64_C(0),
635 UINT64_C(0),
636 UINT64_C(0),
637 UINT64_C(0),
638 UINT64_C(0),
639 UINT64_C(0),
640 UINT64_C(0),
641 UINT64_C(0),
642 UINT64_C(0),
643 UINT64_C(0),
644 UINT64_C(0),
645 UINT64_C(0),
646 UINT64_C(0),
647 UINT64_C(0),
648 UINT64_C(0),
649 UINT64_C(0),
650 UINT64_C(0),
651 UINT64_C(0),
652 UINT64_C(0),
653 UINT64_C(0),
654 UINT64_C(0),
655 UINT64_C(0),
656 UINT64_C(0),
657 UINT64_C(0),
658 UINT64_C(0),
659 UINT64_C(0),
660 UINT64_C(0),
661 UINT64_C(0),
662 UINT64_C(0),
663 UINT64_C(0),
664 UINT64_C(0),
665 UINT64_C(0),
666 UINT64_C(0),
667 UINT64_C(0),
668 UINT64_C(0),
669 UINT64_C(0),
670 UINT64_C(0),
671 UINT64_C(0),
672 UINT64_C(0),
673 UINT64_C(0),
674 UINT64_C(0),
675 UINT64_C(0),
676 UINT64_C(0),
677 UINT64_C(0),
678 UINT64_C(0),
679 UINT64_C(0),
680 UINT64_C(0),
681 UINT64_C(0),
682 UINT64_C(0),
683 UINT64_C(0),
684 UINT64_C(0),
685 UINT64_C(0),
686 UINT64_C(0),
687 UINT64_C(0),
688 UINT64_C(0),
689 UINT64_C(0),
690 UINT64_C(0),
691 UINT64_C(0),
692 UINT64_C(0),
693 UINT64_C(0),
694 UINT64_C(0),
695 UINT64_C(0),
696 UINT64_C(0),
697 UINT64_C(0),
698 UINT64_C(0),
699 UINT64_C(0),
700 UINT64_C(0),
701 UINT64_C(0),
702 UINT64_C(0),
703 UINT64_C(0),
704 UINT64_C(0),
705 UINT64_C(0),
706 UINT64_C(0),
707 UINT64_C(0),
708 UINT64_C(0),
709 UINT64_C(0),
710 UINT64_C(0),
711 UINT64_C(0),
712 UINT64_C(0),
713 UINT64_C(0),
714 UINT64_C(0),
715 UINT64_C(0),
716 UINT64_C(0),
717 UINT64_C(0),
718 UINT64_C(0),
719 UINT64_C(0),
720 UINT64_C(0),
721 UINT64_C(0),
722 UINT64_C(0),
723 UINT64_C(0),
724 UINT64_C(0),
725 UINT64_C(0),
726 UINT64_C(0),
727 UINT64_C(0),
728 UINT64_C(0),
729 UINT64_C(0),
730 UINT64_C(0),
731 UINT64_C(0),
732 UINT64_C(0),
733 UINT64_C(0),
734 UINT64_C(0),
735 UINT64_C(0),
736 UINT64_C(0),
737 UINT64_C(0),
738 UINT64_C(0),
739 UINT64_C(0),
740 UINT64_C(0),
741 UINT64_C(0),
742 UINT64_C(0),
743 UINT64_C(0),
744 UINT64_C(0),
745 UINT64_C(0),
746 UINT64_C(0),
747 UINT64_C(0),
748 UINT64_C(0),
749 UINT64_C(0),
750 UINT64_C(0),
751 UINT64_C(0),
752 UINT64_C(0),
753 UINT64_C(0),
754 UINT64_C(0),
755 UINT64_C(0),
756 UINT64_C(0),
757 UINT64_C(0),
758 UINT64_C(0),
759 UINT64_C(0),
760 UINT64_C(0),
761 UINT64_C(0),
762 UINT64_C(0),
763 UINT64_C(0),
764 UINT64_C(0),
765 UINT64_C(0),
766 UINT64_C(0),
767 UINT64_C(0),
768 UINT64_C(0),
769 UINT64_C(0),
770 UINT64_C(0),
771 UINT64_C(0),
772 UINT64_C(0),
773 UINT64_C(0),
774 UINT64_C(0),
775 UINT64_C(0),
776 UINT64_C(0),
777 UINT64_C(0),
778 UINT64_C(0),
779 UINT64_C(0),
780 UINT64_C(0),
781 UINT64_C(2080375378), // ABSQ_S_PH
782 UINT64_C(4412), // ABSQ_S_PH_MM
783 UINT64_C(2080374866), // ABSQ_S_QB
784 UINT64_C(316), // ABSQ_S_QB_MMR2
785 UINT64_C(2080375890), // ABSQ_S_W
786 UINT64_C(8508), // ABSQ_S_W_MM
787 UINT64_C(32), // ADD
788 UINT64_C(3959422976), // ADDIUPC
789 UINT64_C(2013265920), // ADDIUPC_MM
790 UINT64_C(2013265920), // ADDIUPC_MMR6
791 UINT64_C(27649), // ADDIUR1SP_MM
792 UINT64_C(27648), // ADDIUR2_MM
793 UINT64_C(19456), // ADDIUS5_MM
794 UINT64_C(19457), // ADDIUSP_MM
795 UINT64_C(805306368), // ADDIU_MMR6
796 UINT64_C(2080375320), // ADDQH_PH
797 UINT64_C(77), // ADDQH_PH_MMR2
798 UINT64_C(2080375448), // ADDQH_R_PH
799 UINT64_C(1101), // ADDQH_R_PH_MMR2
800 UINT64_C(2080375960), // ADDQH_R_W
801 UINT64_C(1165), // ADDQH_R_W_MMR2
802 UINT64_C(2080375832), // ADDQH_W
803 UINT64_C(141), // ADDQH_W_MMR2
804 UINT64_C(2080375440), // ADDQ_PH
805 UINT64_C(13), // ADDQ_PH_MM
806 UINT64_C(2080375696), // ADDQ_S_PH
807 UINT64_C(1037), // ADDQ_S_PH_MM
808 UINT64_C(2080376208), // ADDQ_S_W
809 UINT64_C(773), // ADDQ_S_W_MM
810 UINT64_C(1186988056), // ADDR_PS64
811 UINT64_C(2080375824), // ADDSC
812 UINT64_C(901), // ADDSC_MM
813 UINT64_C(2021654544), // ADDS_A_B
814 UINT64_C(2027946000), // ADDS_A_D
815 UINT64_C(2023751696), // ADDS_A_H
816 UINT64_C(2025848848), // ADDS_A_W
817 UINT64_C(2030043152), // ADDS_S_B
818 UINT64_C(2036334608), // ADDS_S_D
819 UINT64_C(2032140304), // ADDS_S_H
820 UINT64_C(2034237456), // ADDS_S_W
821 UINT64_C(2038431760), // ADDS_U_B
822 UINT64_C(2044723216), // ADDS_U_D
823 UINT64_C(2040528912), // ADDS_U_H
824 UINT64_C(2042626064), // ADDS_U_W
825 UINT64_C(1024), // ADDU16_MM
826 UINT64_C(1024), // ADDU16_MMR6
827 UINT64_C(2080374808), // ADDUH_QB
828 UINT64_C(333), // ADDUH_QB_MMR2
829 UINT64_C(2080374936), // ADDUH_R_QB
830 UINT64_C(1357), // ADDUH_R_QB_MMR2
831 UINT64_C(336), // ADDU_MMR6
832 UINT64_C(2080375312), // ADDU_PH
833 UINT64_C(269), // ADDU_PH_MMR2
834 UINT64_C(2080374800), // ADDU_QB
835 UINT64_C(205), // ADDU_QB_MM
836 UINT64_C(2080375568), // ADDU_S_PH
837 UINT64_C(1293), // ADDU_S_PH_MMR2
838 UINT64_C(2080375056), // ADDU_S_QB
839 UINT64_C(1229), // ADDU_S_QB_MM
840 UINT64_C(2013265926), // ADDVI_B
841 UINT64_C(2019557382), // ADDVI_D
842 UINT64_C(2015363078), // ADDVI_H
843 UINT64_C(2017460230), // ADDVI_W
844 UINT64_C(2013265934), // ADDV_B
845 UINT64_C(2019557390), // ADDV_D
846 UINT64_C(2015363086), // ADDV_H
847 UINT64_C(2017460238), // ADDV_W
848 UINT64_C(2080375888), // ADDWC
849 UINT64_C(965), // ADDWC_MM
850 UINT64_C(2013265936), // ADD_A_B
851 UINT64_C(2019557392), // ADD_A_D
852 UINT64_C(2015363088), // ADD_A_H
853 UINT64_C(2017460240), // ADD_A_W
854 UINT64_C(272), // ADD_MM
855 UINT64_C(272), // ADD_MMR6
856 UINT64_C(536870912), // ADDi
857 UINT64_C(268435456), // ADDi_MM
858 UINT64_C(603979776), // ADDiu
859 UINT64_C(805306368), // ADDiu_MM
860 UINT64_C(33), // ADDu
861 UINT64_C(336), // ADDu_MM
862 UINT64_C(2080375328), // ALIGN
863 UINT64_C(31), // ALIGN_MMR6
864 UINT64_C(3961454592), // ALUIPC
865 UINT64_C(2015297536), // ALUIPC_MMR6
866 UINT64_C(36), // AND
867 UINT64_C(17536), // AND16_MM
868 UINT64_C(17409), // AND16_MMR6
869 UINT64_C(36), // AND64
870 UINT64_C(11264), // ANDI16_MM
871 UINT64_C(11264), // ANDI16_MMR6
872 UINT64_C(2013265920), // ANDI_B
873 UINT64_C(3489660928), // ANDI_MMR6
874 UINT64_C(592), // AND_MM
875 UINT64_C(592), // AND_MMR6
876 UINT64_C(2013265950), // AND_V
877 UINT64_C(805306368), // ANDi
878 UINT64_C(805306368), // ANDi64
879 UINT64_C(3489660928), // ANDi_MM
880 UINT64_C(2080374833), // APPEND
881 UINT64_C(533), // APPEND_MMR2
882 UINT64_C(2046820369), // ASUB_S_B
883 UINT64_C(2053111825), // ASUB_S_D
884 UINT64_C(2048917521), // ASUB_S_H
885 UINT64_C(2051014673), // ASUB_S_W
886 UINT64_C(2055208977), // ASUB_U_B
887 UINT64_C(2061500433), // ASUB_U_D
888 UINT64_C(2057306129), // ASUB_U_H
889 UINT64_C(2059403281), // ASUB_U_W
890 UINT64_C(1006632960), // AUI
891 UINT64_C(3961389056), // AUIPC
892 UINT64_C(2015232000), // AUIPC_MMR6
893 UINT64_C(268435456), // AUI_MMR6
894 UINT64_C(2063597584), // AVER_S_B
895 UINT64_C(2069889040), // AVER_S_D
896 UINT64_C(2065694736), // AVER_S_H
897 UINT64_C(2067791888), // AVER_S_W
898 UINT64_C(2071986192), // AVER_U_B
899 UINT64_C(2078277648), // AVER_U_D
900 UINT64_C(2074083344), // AVER_U_H
901 UINT64_C(2076180496), // AVER_U_W
902 UINT64_C(2046820368), // AVE_S_B
903 UINT64_C(2053111824), // AVE_S_D
904 UINT64_C(2048917520), // AVE_S_H
905 UINT64_C(2051014672), // AVE_S_W
906 UINT64_C(2055208976), // AVE_U_B
907 UINT64_C(2061500432), // AVE_U_D
908 UINT64_C(2057306128), // AVE_U_H
909 UINT64_C(2059403280), // AVE_U_W
910 UINT64_C(4026550272), // AddiuRxImmX16
911 UINT64_C(4026533888), // AddiuRxPcImmX16
912 UINT64_C(18432), // AddiuRxRxImm16
913 UINT64_C(4026550272), // AddiuRxRxImmX16
914 UINT64_C(4026548224), // AddiuRxRyOffMemX16
915 UINT64_C(25344), // AddiuSpImm16
916 UINT64_C(4026544896), // AddiuSpImmX16
917 UINT64_C(57345), // AdduRxRyRz16
918 UINT64_C(59404), // AndRxRxRy16
919 UINT64_C(52224), // B16_MM
920 UINT64_C(1879048232), // BADDu
921 UINT64_C(68222976), // BAL
922 UINT64_C(3892314112), // BALC
923 UINT64_C(3019898880), // BALC_MMR6
924 UINT64_C(2080375857), // BALIGN
925 UINT64_C(2236), // BALIGN_MMR2
926 UINT64_C(3355443200), // BBIT0
927 UINT64_C(3623878656), // BBIT032
928 UINT64_C(3892314112), // BBIT1
929 UINT64_C(4160749568), // BBIT132
930 UINT64_C(3355443200), // BC
931 UINT64_C(52224), // BC16_MMR6
932 UINT64_C(1159725056), // BC1EQZ
933 UINT64_C(1090519040), // BC1EQZC_MMR6
934 UINT64_C(1157627904), // BC1F
935 UINT64_C(1157758976), // BC1FL
936 UINT64_C(1132462080), // BC1F_MM
937 UINT64_C(1168113664), // BC1NEZ
938 UINT64_C(1092616192), // BC1NEZC_MMR6
939 UINT64_C(1157693440), // BC1T
940 UINT64_C(1157824512), // BC1TL
941 UINT64_C(1134559232), // BC1T_MM
942 UINT64_C(1226833920), // BC2EQZ
943 UINT64_C(1094713344), // BC2EQZC_MMR6
944 UINT64_C(1235222528), // BC2NEZ
945 UINT64_C(1096810496), // BC2NEZC_MMR6
946 UINT64_C(2045771785), // BCLRI_B
947 UINT64_C(2038431753), // BCLRI_D
948 UINT64_C(2044723209), // BCLRI_H
949 UINT64_C(2042626057), // BCLRI_W
950 UINT64_C(2038431757), // BCLR_B
951 UINT64_C(2044723213), // BCLR_D
952 UINT64_C(2040528909), // BCLR_H
953 UINT64_C(2042626061), // BCLR_W
954 UINT64_C(2483027968), // BC_MMR6
955 UINT64_C(268435456), // BEQ
956 UINT64_C(268435456), // BEQ64
957 UINT64_C(536870912), // BEQC
958 UINT64_C(536870912), // BEQC64
959 UINT64_C(1946157056), // BEQC_MMR6
960 UINT64_C(1342177280), // BEQL
961 UINT64_C(35840), // BEQZ16_MM
962 UINT64_C(536870912), // BEQZALC
963 UINT64_C(1946157056), // BEQZALC_MMR6
964 UINT64_C(3623878656), // BEQZC
965 UINT64_C(35840), // BEQZC16_MMR6
966 UINT64_C(3623878656), // BEQZC64
967 UINT64_C(1088421888), // BEQZC_MM
968 UINT64_C(2147483648), // BEQZC_MMR6
969 UINT64_C(2483027968), // BEQ_MM
970 UINT64_C(1476395008), // BGEC
971 UINT64_C(1476395008), // BGEC64
972 UINT64_C(4093640704), // BGEC_MMR6
973 UINT64_C(402653184), // BGEUC
974 UINT64_C(402653184), // BGEUC64
975 UINT64_C(3221225472), // BGEUC_MMR6
976 UINT64_C(67174400), // BGEZ
977 UINT64_C(67174400), // BGEZ64
978 UINT64_C(68222976), // BGEZAL
979 UINT64_C(402653184), // BGEZALC
980 UINT64_C(3221225472), // BGEZALC_MMR6
981 UINT64_C(68354048), // BGEZALL
982 UINT64_C(1113587712), // BGEZALS_MM
983 UINT64_C(1080033280), // BGEZAL_MM
984 UINT64_C(1476395008), // BGEZC
985 UINT64_C(1476395008), // BGEZC64
986 UINT64_C(4093640704), // BGEZC_MMR6
987 UINT64_C(67305472), // BGEZL
988 UINT64_C(1077936128), // BGEZ_MM
989 UINT64_C(469762048), // BGTZ
990 UINT64_C(469762048), // BGTZ64
991 UINT64_C(469762048), // BGTZALC
992 UINT64_C(3758096384), // BGTZALC_MMR6
993 UINT64_C(1543503872), // BGTZC
994 UINT64_C(1543503872), // BGTZC64
995 UINT64_C(3556769792), // BGTZC_MMR6
996 UINT64_C(1543503872), // BGTZL
997 UINT64_C(1086324736), // BGTZ_MM
998 UINT64_C(2070937609), // BINSLI_B
999 UINT64_C(2063597577), // BINSLI_D
1000 UINT64_C(2069889033), // BINSLI_H
1001 UINT64_C(2067791881), // BINSLI_W
1002 UINT64_C(2063597581), // BINSL_B
1003 UINT64_C(2069889037), // BINSL_D
1004 UINT64_C(2065694733), // BINSL_H
1005 UINT64_C(2067791885), // BINSL_W
1006 UINT64_C(2079326217), // BINSRI_B
1007 UINT64_C(2071986185), // BINSRI_D
1008 UINT64_C(2078277641), // BINSRI_H
1009 UINT64_C(2076180489), // BINSRI_W
1010 UINT64_C(2071986189), // BINSR_B
1011 UINT64_C(2078277645), // BINSR_D
1012 UINT64_C(2074083341), // BINSR_H
1013 UINT64_C(2076180493), // BINSR_W
1014 UINT64_C(2080376530), // BITREV
1015 UINT64_C(12604), // BITREV_MM
1016 UINT64_C(2080374816), // BITSWAP
1017 UINT64_C(2876), // BITSWAP_MMR6
1018 UINT64_C(402653184), // BLEZ
1019 UINT64_C(402653184), // BLEZ64
1020 UINT64_C(402653184), // BLEZALC
1021 UINT64_C(3221225472), // BLEZALC_MMR6
1022 UINT64_C(1476395008), // BLEZC
1023 UINT64_C(1476395008), // BLEZC64
1024 UINT64_C(4093640704), // BLEZC_MMR6
1025 UINT64_C(1476395008), // BLEZL
1026 UINT64_C(1082130432), // BLEZ_MM
1027 UINT64_C(1543503872), // BLTC
1028 UINT64_C(1543503872), // BLTC64
1029 UINT64_C(3556769792), // BLTC_MMR6
1030 UINT64_C(469762048), // BLTUC
1031 UINT64_C(469762048), // BLTUC64
1032 UINT64_C(3758096384), // BLTUC_MMR6
1033 UINT64_C(67108864), // BLTZ
1034 UINT64_C(67108864), // BLTZ64
1035 UINT64_C(68157440), // BLTZAL
1036 UINT64_C(469762048), // BLTZALC
1037 UINT64_C(3758096384), // BLTZALC_MMR6
1038 UINT64_C(68288512), // BLTZALL
1039 UINT64_C(1109393408), // BLTZALS_MM
1040 UINT64_C(1075838976), // BLTZAL_MM
1041 UINT64_C(1543503872), // BLTZC
1042 UINT64_C(1543503872), // BLTZC64
1043 UINT64_C(3556769792), // BLTZC_MMR6
1044 UINT64_C(67239936), // BLTZL
1045 UINT64_C(1073741824), // BLTZ_MM
1046 UINT64_C(2013265921), // BMNZI_B
1047 UINT64_C(2021654558), // BMNZ_V
1048 UINT64_C(2030043137), // BMZI_B
1049 UINT64_C(2023751710), // BMZ_V
1050 UINT64_C(335544320), // BNE
1051 UINT64_C(335544320), // BNE64
1052 UINT64_C(1610612736), // BNEC
1053 UINT64_C(1610612736), // BNEC64
1054 UINT64_C(2080374784), // BNEC_MMR6
1055 UINT64_C(2062549001), // BNEGI_B
1056 UINT64_C(2055208969), // BNEGI_D
1057 UINT64_C(2061500425), // BNEGI_H
1058 UINT64_C(2059403273), // BNEGI_W
1059 UINT64_C(2055208973), // BNEG_B
1060 UINT64_C(2061500429), // BNEG_D
1061 UINT64_C(2057306125), // BNEG_H
1062 UINT64_C(2059403277), // BNEG_W
1063 UINT64_C(1409286144), // BNEL
1064 UINT64_C(44032), // BNEZ16_MM
1065 UINT64_C(1610612736), // BNEZALC
1066 UINT64_C(2080374784), // BNEZALC_MMR6
1067 UINT64_C(4160749568), // BNEZC
1068 UINT64_C(44032), // BNEZC16_MMR6
1069 UINT64_C(4160749568), // BNEZC64
1070 UINT64_C(1084227584), // BNEZC_MM
1071 UINT64_C(2684354560), // BNEZC_MMR6
1072 UINT64_C(3019898880), // BNE_MM
1073 UINT64_C(1610612736), // BNVC
1074 UINT64_C(2080374784), // BNVC_MMR6
1075 UINT64_C(1199570944), // BNZ_B
1076 UINT64_C(1205862400), // BNZ_D
1077 UINT64_C(1201668096), // BNZ_H
1078 UINT64_C(1172307968), // BNZ_V
1079 UINT64_C(1203765248), // BNZ_W
1080 UINT64_C(536870912), // BOVC
1081 UINT64_C(1946157056), // BOVC_MMR6
1082 UINT64_C(68943872), // BPOSGE32
1083 UINT64_C(1126170624), // BPOSGE32C_MMR3
1084 UINT64_C(1130364928), // BPOSGE32_MM
1085 UINT64_C(13), // BREAK
1086 UINT64_C(18048), // BREAK16_MM
1087 UINT64_C(17435), // BREAK16_MMR6
1088 UINT64_C(7), // BREAK_MM
1089 UINT64_C(7), // BREAK_MMR6
1090 UINT64_C(2046820353), // BSELI_B
1091 UINT64_C(2025848862), // BSEL_V
1092 UINT64_C(2054160393), // BSETI_B
1093 UINT64_C(2046820361), // BSETI_D
1094 UINT64_C(2053111817), // BSETI_H
1095 UINT64_C(2051014665), // BSETI_W
1096 UINT64_C(2046820365), // BSET_B
1097 UINT64_C(2053111821), // BSET_D
1098 UINT64_C(2048917517), // BSET_H
1099 UINT64_C(2051014669), // BSET_W
1100 UINT64_C(1191182336), // BZ_B
1101 UINT64_C(1197473792), // BZ_D
1102 UINT64_C(1193279488), // BZ_H
1103 UINT64_C(1163919360), // BZ_V
1104 UINT64_C(1195376640), // BZ_W
1105 UINT64_C(8192), // BeqzRxImm16
1106 UINT64_C(4026540032), // BeqzRxImmX16
1107 UINT64_C(4096), // Bimm16
1108 UINT64_C(4026535936), // BimmX16
1109 UINT64_C(10240), // BnezRxImm16
1110 UINT64_C(4026542080), // BnezRxImmX16
1111 UINT64_C(59397), // Break16
1112 UINT64_C(24576), // Bteqz16
1113 UINT64_C(4026544128), // BteqzX16
1114 UINT64_C(24832), // Btnez16
1115 UINT64_C(4026544384), // BtnezX16
1116 UINT64_C(3154116608), // CACHE
1117 UINT64_C(2080374811), // CACHEE
1118 UINT64_C(1610655232), // CACHEE_MM
1119 UINT64_C(536895488), // CACHE_MM
1120 UINT64_C(536895488), // CACHE_MMR6
1121 UINT64_C(2080374821), // CACHE_R6
1122 UINT64_C(1176502282), // CEIL_L_D64
1123 UINT64_C(1409307451), // CEIL_L_D_MMR6
1124 UINT64_C(1174405130), // CEIL_L_S
1125 UINT64_C(1409291067), // CEIL_L_S_MMR6
1126 UINT64_C(1176502286), // CEIL_W_D32
1127 UINT64_C(1176502286), // CEIL_W_D64
1128 UINT64_C(1409309499), // CEIL_W_D_MMR6
1129 UINT64_C(1409309499), // CEIL_W_MM
1130 UINT64_C(1174405134), // CEIL_W_S
1131 UINT64_C(1409293115), // CEIL_W_S_MM
1132 UINT64_C(1409293115), // CEIL_W_S_MMR6
1133 UINT64_C(2013265927), // CEQI_B
1134 UINT64_C(2019557383), // CEQI_D
1135 UINT64_C(2015363079), // CEQI_H
1136 UINT64_C(2017460231), // CEQI_W
1137 UINT64_C(2013265935), // CEQ_B
1138 UINT64_C(2019557391), // CEQ_D
1139 UINT64_C(2015363087), // CEQ_H
1140 UINT64_C(2017460239), // CEQ_W
1141 UINT64_C(1145044992), // CFC1
1142 UINT64_C(1409290299), // CFC1_MM
1143 UINT64_C(52540), // CFC2_MM
1144 UINT64_C(2021523481), // CFCMSA
1145 UINT64_C(1879048242), // CINS
1146 UINT64_C(1879048243), // CINS32
1147 UINT64_C(1879048242), // CINS64_32
1148 UINT64_C(1879048242), // CINS_i32
1149 UINT64_C(1176502299), // CLASS_D
1150 UINT64_C(1409286752), // CLASS_D_MMR6
1151 UINT64_C(1174405147), // CLASS_S
1152 UINT64_C(1409286240), // CLASS_S_MMR6
1153 UINT64_C(2046820359), // CLEI_S_B
1154 UINT64_C(2053111815), // CLEI_S_D
1155 UINT64_C(2048917511), // CLEI_S_H
1156 UINT64_C(2051014663), // CLEI_S_W
1157 UINT64_C(2055208967), // CLEI_U_B
1158 UINT64_C(2061500423), // CLEI_U_D
1159 UINT64_C(2057306119), // CLEI_U_H
1160 UINT64_C(2059403271), // CLEI_U_W
1161 UINT64_C(2046820367), // CLE_S_B
1162 UINT64_C(2053111823), // CLE_S_D
1163 UINT64_C(2048917519), // CLE_S_H
1164 UINT64_C(2051014671), // CLE_S_W
1165 UINT64_C(2055208975), // CLE_U_B
1166 UINT64_C(2061500431), // CLE_U_D
1167 UINT64_C(2057306127), // CLE_U_H
1168 UINT64_C(2059403279), // CLE_U_W
1169 UINT64_C(1879048225), // CLO
1170 UINT64_C(19260), // CLO_MM
1171 UINT64_C(19260), // CLO_MMR6
1172 UINT64_C(81), // CLO_R6
1173 UINT64_C(2030043143), // CLTI_S_B
1174 UINT64_C(2036334599), // CLTI_S_D
1175 UINT64_C(2032140295), // CLTI_S_H
1176 UINT64_C(2034237447), // CLTI_S_W
1177 UINT64_C(2038431751), // CLTI_U_B
1178 UINT64_C(2044723207), // CLTI_U_D
1179 UINT64_C(2040528903), // CLTI_U_H
1180 UINT64_C(2042626055), // CLTI_U_W
1181 UINT64_C(2030043151), // CLT_S_B
1182 UINT64_C(2036334607), // CLT_S_D
1183 UINT64_C(2032140303), // CLT_S_H
1184 UINT64_C(2034237455), // CLT_S_W
1185 UINT64_C(2038431759), // CLT_U_B
1186 UINT64_C(2044723215), // CLT_U_D
1187 UINT64_C(2040528911), // CLT_U_H
1188 UINT64_C(2042626063), // CLT_U_W
1189 UINT64_C(1879048224), // CLZ
1190 UINT64_C(23356), // CLZ_MM
1191 UINT64_C(80), // CLZ_MMR6
1192 UINT64_C(80), // CLZ_R6
1193 UINT64_C(2080376337), // CMPGDU_EQ_QB
1194 UINT64_C(389), // CMPGDU_EQ_QB_MMR2
1195 UINT64_C(2080376465), // CMPGDU_LE_QB
1196 UINT64_C(517), // CMPGDU_LE_QB_MMR2
1197 UINT64_C(2080376401), // CMPGDU_LT_QB
1198 UINT64_C(453), // CMPGDU_LT_QB_MMR2
1199 UINT64_C(2080375057), // CMPGU_EQ_QB
1200 UINT64_C(1476395205), // CMPGU_EQ_QB_MM
1201 UINT64_C(2080375185), // CMPGU_LE_QB
1202 UINT64_C(1476395333), // CMPGU_LE_QB_MM
1203 UINT64_C(2080375121), // CMPGU_LT_QB
1204 UINT64_C(1476395269), // CMPGU_LT_QB_MM
1205 UINT64_C(2080374801), // CMPU_EQ_QB
1206 UINT64_C(581), // CMPU_EQ_QB_MM
1207 UINT64_C(2080374929), // CMPU_LE_QB
1208 UINT64_C(709), // CMPU_LE_QB_MM
1209 UINT64_C(2080374865), // CMPU_LT_QB
1210 UINT64_C(645), // CMPU_LT_QB_MM
1211 UINT64_C(1409286165), // CMP_AF_D_MMR6
1212 UINT64_C(1409286149), // CMP_AF_S_MMR6
1213 UINT64_C(1184890882), // CMP_EQ_D
1214 UINT64_C(1409286293), // CMP_EQ_D_MMR6
1215 UINT64_C(2080375313), // CMP_EQ_PH
1216 UINT64_C(5), // CMP_EQ_PH_MM
1217 UINT64_C(1182793730), // CMP_EQ_S
1218 UINT64_C(1409286277), // CMP_EQ_S_MMR6
1219 UINT64_C(1184890880), // CMP_F_D
1220 UINT64_C(1182793728), // CMP_F_S
1221 UINT64_C(1184890886), // CMP_LE_D
1222 UINT64_C(1409286549), // CMP_LE_D_MMR6
1223 UINT64_C(2080375441), // CMP_LE_PH
1224 UINT64_C(133), // CMP_LE_PH_MM
1225 UINT64_C(1182793734), // CMP_LE_S
1226 UINT64_C(1409286533), // CMP_LE_S_MMR6
1227 UINT64_C(1184890884), // CMP_LT_D
1228 UINT64_C(1409286421), // CMP_LT_D_MMR6
1229 UINT64_C(2080375377), // CMP_LT_PH
1230 UINT64_C(69), // CMP_LT_PH_MM
1231 UINT64_C(1182793732), // CMP_LT_S
1232 UINT64_C(1409286405), // CMP_LT_S_MMR6
1233 UINT64_C(1184890888), // CMP_SAF_D
1234 UINT64_C(1409286677), // CMP_SAF_D_MMR6
1235 UINT64_C(1182793736), // CMP_SAF_S
1236 UINT64_C(1409286661), // CMP_SAF_S_MMR6
1237 UINT64_C(1184890890), // CMP_SEQ_D
1238 UINT64_C(1409286805), // CMP_SEQ_D_MMR6
1239 UINT64_C(1182793738), // CMP_SEQ_S
1240 UINT64_C(1409286789), // CMP_SEQ_S_MMR6
1241 UINT64_C(1184890894), // CMP_SLE_D
1242 UINT64_C(1409287061), // CMP_SLE_D_MMR6
1243 UINT64_C(1182793742), // CMP_SLE_S
1244 UINT64_C(1409287045), // CMP_SLE_S_MMR6
1245 UINT64_C(1184890892), // CMP_SLT_D
1246 UINT64_C(1409286933), // CMP_SLT_D_MMR6
1247 UINT64_C(1182793740), // CMP_SLT_S
1248 UINT64_C(1409286917), // CMP_SLT_S_MMR6
1249 UINT64_C(1184890891), // CMP_SUEQ_D
1250 UINT64_C(1409286869), // CMP_SUEQ_D_MMR6
1251 UINT64_C(1182793739), // CMP_SUEQ_S
1252 UINT64_C(1409286853), // CMP_SUEQ_S_MMR6
1253 UINT64_C(1184890895), // CMP_SULE_D
1254 UINT64_C(1409287125), // CMP_SULE_D_MMR6
1255 UINT64_C(1182793743), // CMP_SULE_S
1256 UINT64_C(1409287109), // CMP_SULE_S_MMR6
1257 UINT64_C(1184890893), // CMP_SULT_D
1258 UINT64_C(1409286997), // CMP_SULT_D_MMR6
1259 UINT64_C(1182793741), // CMP_SULT_S
1260 UINT64_C(1409286981), // CMP_SULT_S_MMR6
1261 UINT64_C(1184890889), // CMP_SUN_D
1262 UINT64_C(1409286741), // CMP_SUN_D_MMR6
1263 UINT64_C(1182793737), // CMP_SUN_S
1264 UINT64_C(1409286725), // CMP_SUN_S_MMR6
1265 UINT64_C(1184890883), // CMP_UEQ_D
1266 UINT64_C(1409286357), // CMP_UEQ_D_MMR6
1267 UINT64_C(1182793731), // CMP_UEQ_S
1268 UINT64_C(1409286341), // CMP_UEQ_S_MMR6
1269 UINT64_C(1184890887), // CMP_ULE_D
1270 UINT64_C(1409286613), // CMP_ULE_D_MMR6
1271 UINT64_C(1182793735), // CMP_ULE_S
1272 UINT64_C(1409286597), // CMP_ULE_S_MMR6
1273 UINT64_C(1184890885), // CMP_ULT_D
1274 UINT64_C(1409286485), // CMP_ULT_D_MMR6
1275 UINT64_C(1182793733), // CMP_ULT_S
1276 UINT64_C(1409286469), // CMP_ULT_S_MMR6
1277 UINT64_C(1184890881), // CMP_UN_D
1278 UINT64_C(1409286229), // CMP_UN_D_MMR6
1279 UINT64_C(1182793729), // CMP_UN_S
1280 UINT64_C(1409286213), // CMP_UN_S_MMR6
1281 UINT64_C(2021654553), // COPY_S_B
1282 UINT64_C(2025324569), // COPY_S_D
1283 UINT64_C(2023751705), // COPY_S_H
1284 UINT64_C(2024800281), // COPY_S_W
1285 UINT64_C(2025848857), // COPY_U_B
1286 UINT64_C(2027946009), // COPY_U_H
1287 UINT64_C(2028994585), // COPY_U_W
1288 UINT64_C(2080374799), // CRC32B
1289 UINT64_C(2080375055), // CRC32CB
1290 UINT64_C(2080375247), // CRC32CD
1291 UINT64_C(2080375119), // CRC32CH
1292 UINT64_C(2080375183), // CRC32CW
1293 UINT64_C(2080374991), // CRC32D
1294 UINT64_C(2080374863), // CRC32H
1295 UINT64_C(2080374927), // CRC32W
1296 UINT64_C(1153433600), // CTC1
1297 UINT64_C(1409292347), // CTC1_MM
1298 UINT64_C(56636), // CTC2_MM
1299 UINT64_C(2017329177), // CTCMSA
1300 UINT64_C(1174405153), // CVT_D32_S
1301 UINT64_C(1409291131), // CVT_D32_S_MM
1302 UINT64_C(1182793761), // CVT_D32_W
1303 UINT64_C(1409299323), // CVT_D32_W_MM
1304 UINT64_C(1184890913), // CVT_D64_L
1305 UINT64_C(1174405153), // CVT_D64_S
1306 UINT64_C(1409291131), // CVT_D64_S_MM
1307 UINT64_C(1182793761), // CVT_D64_W
1308 UINT64_C(1409299323), // CVT_D64_W_MM
1309 UINT64_C(1409307515), // CVT_D_L_MMR6
1310 UINT64_C(1176502309), // CVT_L_D64
1311 UINT64_C(1409302843), // CVT_L_D64_MM
1312 UINT64_C(1409302843), // CVT_L_D_MMR6
1313 UINT64_C(1174405157), // CVT_L_S
1314 UINT64_C(1409286459), // CVT_L_S_MM
1315 UINT64_C(1409286459), // CVT_L_S_MMR6
1316 UINT64_C(1182793766), // CVT_PS_PW64
1317 UINT64_C(1174405158), // CVT_PS_S64
1318 UINT64_C(1186988068), // CVT_PW_PS64
1319 UINT64_C(1176502304), // CVT_S_D32
1320 UINT64_C(1409293179), // CVT_S_D32_MM
1321 UINT64_C(1176502304), // CVT_S_D64
1322 UINT64_C(1409293179), // CVT_S_D64_MM
1323 UINT64_C(1184890912), // CVT_S_L
1324 UINT64_C(1409309563), // CVT_S_L_MMR6
1325 UINT64_C(1186988072), // CVT_S_PL64
1326 UINT64_C(1186988064), // CVT_S_PU64
1327 UINT64_C(1182793760), // CVT_S_W
1328 UINT64_C(1409301371), // CVT_S_W_MM
1329 UINT64_C(1409301371), // CVT_S_W_MMR6
1330 UINT64_C(1176502308), // CVT_W_D32
1331 UINT64_C(1409304891), // CVT_W_D32_MM
1332 UINT64_C(1176502308), // CVT_W_D64
1333 UINT64_C(1409304891), // CVT_W_D64_MM
1334 UINT64_C(1174405156), // CVT_W_S
1335 UINT64_C(1409288507), // CVT_W_S_MM
1336 UINT64_C(1409288507), // CVT_W_S_MMR6
1337 UINT64_C(1176502322), // C_EQ_D32
1338 UINT64_C(1409287356), // C_EQ_D32_MM
1339 UINT64_C(1176502322), // C_EQ_D64
1340 UINT64_C(1409287356), // C_EQ_D64_MM
1341 UINT64_C(1174405170), // C_EQ_S
1342 UINT64_C(1409286332), // C_EQ_S_MM
1343 UINT64_C(1176502320), // C_F_D32
1344 UINT64_C(1409287228), // C_F_D32_MM
1345 UINT64_C(1176502320), // C_F_D64
1346 UINT64_C(1409287228), // C_F_D64_MM
1347 UINT64_C(1174405168), // C_F_S
1348 UINT64_C(1409286204), // C_F_S_MM
1349 UINT64_C(1176502334), // C_LE_D32
1350 UINT64_C(1409288124), // C_LE_D32_MM
1351 UINT64_C(1176502334), // C_LE_D64
1352 UINT64_C(1409288124), // C_LE_D64_MM
1353 UINT64_C(1174405182), // C_LE_S
1354 UINT64_C(1409287100), // C_LE_S_MM
1355 UINT64_C(1176502332), // C_LT_D32
1356 UINT64_C(1409287996), // C_LT_D32_MM
1357 UINT64_C(1176502332), // C_LT_D64
1358 UINT64_C(1409287996), // C_LT_D64_MM
1359 UINT64_C(1174405180), // C_LT_S
1360 UINT64_C(1409286972), // C_LT_S_MM
1361 UINT64_C(1176502333), // C_NGE_D32
1362 UINT64_C(1409288060), // C_NGE_D32_MM
1363 UINT64_C(1176502333), // C_NGE_D64
1364 UINT64_C(1409288060), // C_NGE_D64_MM
1365 UINT64_C(1174405181), // C_NGE_S
1366 UINT64_C(1409287036), // C_NGE_S_MM
1367 UINT64_C(1176502329), // C_NGLE_D32
1368 UINT64_C(1409287804), // C_NGLE_D32_MM
1369 UINT64_C(1176502329), // C_NGLE_D64
1370 UINT64_C(1409287804), // C_NGLE_D64_MM
1371 UINT64_C(1174405177), // C_NGLE_S
1372 UINT64_C(1409286780), // C_NGLE_S_MM
1373 UINT64_C(1176502331), // C_NGL_D32
1374 UINT64_C(1409287932), // C_NGL_D32_MM
1375 UINT64_C(1176502331), // C_NGL_D64
1376 UINT64_C(1409287932), // C_NGL_D64_MM
1377 UINT64_C(1174405179), // C_NGL_S
1378 UINT64_C(1409286908), // C_NGL_S_MM
1379 UINT64_C(1176502335), // C_NGT_D32
1380 UINT64_C(1409288188), // C_NGT_D32_MM
1381 UINT64_C(1176502335), // C_NGT_D64
1382 UINT64_C(1409288188), // C_NGT_D64_MM
1383 UINT64_C(1174405183), // C_NGT_S
1384 UINT64_C(1409287164), // C_NGT_S_MM
1385 UINT64_C(1176502326), // C_OLE_D32
1386 UINT64_C(1409287612), // C_OLE_D32_MM
1387 UINT64_C(1176502326), // C_OLE_D64
1388 UINT64_C(1409287612), // C_OLE_D64_MM
1389 UINT64_C(1174405174), // C_OLE_S
1390 UINT64_C(1409286588), // C_OLE_S_MM
1391 UINT64_C(1176502324), // C_OLT_D32
1392 UINT64_C(1409287484), // C_OLT_D32_MM
1393 UINT64_C(1176502324), // C_OLT_D64
1394 UINT64_C(1409287484), // C_OLT_D64_MM
1395 UINT64_C(1174405172), // C_OLT_S
1396 UINT64_C(1409286460), // C_OLT_S_MM
1397 UINT64_C(1176502330), // C_SEQ_D32
1398 UINT64_C(1409287868), // C_SEQ_D32_MM
1399 UINT64_C(1176502330), // C_SEQ_D64
1400 UINT64_C(1409287868), // C_SEQ_D64_MM
1401 UINT64_C(1174405178), // C_SEQ_S
1402 UINT64_C(1409286844), // C_SEQ_S_MM
1403 UINT64_C(1176502328), // C_SF_D32
1404 UINT64_C(1409287740), // C_SF_D32_MM
1405 UINT64_C(1176502328), // C_SF_D64
1406 UINT64_C(1409287740), // C_SF_D64_MM
1407 UINT64_C(1174405176), // C_SF_S
1408 UINT64_C(1409286716), // C_SF_S_MM
1409 UINT64_C(1176502323), // C_UEQ_D32
1410 UINT64_C(1409287420), // C_UEQ_D32_MM
1411 UINT64_C(1176502323), // C_UEQ_D64
1412 UINT64_C(1409287420), // C_UEQ_D64_MM
1413 UINT64_C(1174405171), // C_UEQ_S
1414 UINT64_C(1409286396), // C_UEQ_S_MM
1415 UINT64_C(1176502327), // C_ULE_D32
1416 UINT64_C(1409287676), // C_ULE_D32_MM
1417 UINT64_C(1176502327), // C_ULE_D64
1418 UINT64_C(1409287676), // C_ULE_D64_MM
1419 UINT64_C(1174405175), // C_ULE_S
1420 UINT64_C(1409286652), // C_ULE_S_MM
1421 UINT64_C(1176502325), // C_ULT_D32
1422 UINT64_C(1409287548), // C_ULT_D32_MM
1423 UINT64_C(1176502325), // C_ULT_D64
1424 UINT64_C(1409287548), // C_ULT_D64_MM
1425 UINT64_C(1174405173), // C_ULT_S
1426 UINT64_C(1409286524), // C_ULT_S_MM
1427 UINT64_C(1176502321), // C_UN_D32
1428 UINT64_C(1409287292), // C_UN_D32_MM
1429 UINT64_C(1176502321), // C_UN_D64
1430 UINT64_C(1409287292), // C_UN_D64_MM
1431 UINT64_C(1174405169), // C_UN_S
1432 UINT64_C(1409286268), // C_UN_S_MM
1433 UINT64_C(59402), // CmpRxRy16
1434 UINT64_C(28672), // CmpiRxImm16
1435 UINT64_C(4026560512), // CmpiRxImmX16
1436 UINT64_C(44), // DADD
1437 UINT64_C(1610612736), // DADDi
1438 UINT64_C(1677721600), // DADDiu
1439 UINT64_C(45), // DADDu
1440 UINT64_C(67502080), // DAHI
1441 UINT64_C(2080375332), // DALIGN
1442 UINT64_C(69074944), // DATI
1443 UINT64_C(1946157056), // DAUI
1444 UINT64_C(2080374820), // DBITSWAP
1445 UINT64_C(1879048229), // DCLO
1446 UINT64_C(83), // DCLO_R6
1447 UINT64_C(1879048228), // DCLZ
1448 UINT64_C(82), // DCLZ_R6
1449 UINT64_C(158), // DDIV
1450 UINT64_C(159), // DDIVU
1451 UINT64_C(1107296287), // DERET
1452 UINT64_C(58236), // DERET_MM
1453 UINT64_C(58236), // DERET_MMR6
1454 UINT64_C(2080374787), // DEXT
1455 UINT64_C(2080374787), // DEXT64_32
1456 UINT64_C(2080374785), // DEXTM
1457 UINT64_C(2080374786), // DEXTU
1458 UINT64_C(1096835072), // DI
1459 UINT64_C(2080374791), // DINS
1460 UINT64_C(2080374789), // DINSM
1461 UINT64_C(2080374790), // DINSU
1462 UINT64_C(154), // DIV
1463 UINT64_C(155), // DIVU
1464 UINT64_C(408), // DIVU_MMR6
1465 UINT64_C(280), // DIV_MMR6
1466 UINT64_C(2046820370), // DIV_S_B
1467 UINT64_C(2053111826), // DIV_S_D
1468 UINT64_C(2048917522), // DIV_S_H
1469 UINT64_C(2051014674), // DIV_S_W
1470 UINT64_C(2055208978), // DIV_U_B
1471 UINT64_C(2061500434), // DIV_U_D
1472 UINT64_C(2057306130), // DIV_U_H
1473 UINT64_C(2059403282), // DIV_U_W
1474 UINT64_C(18300), // DI_MM
1475 UINT64_C(18300), // DI_MMR6
1476 UINT64_C(21), // DLSA
1477 UINT64_C(21), // DLSA_R6
1478 UINT64_C(1075838976), // DMFC0
1479 UINT64_C(1142947840), // DMFC1
1480 UINT64_C(1210056704), // DMFC2
1481 UINT64_C(1210056704), // DMFC2_OCTEON
1482 UINT64_C(1080033536), // DMFGC0
1483 UINT64_C(222), // DMOD
1484 UINT64_C(223), // DMODU
1485 UINT64_C(1096813505), // DMT
1486 UINT64_C(1084227584), // DMTC0
1487 UINT64_C(1151336448), // DMTC1
1488 UINT64_C(1218445312), // DMTC2
1489 UINT64_C(1218445312), // DMTC2_OCTEON
1490 UINT64_C(1080034048), // DMTGC0
1491 UINT64_C(220), // DMUH
1492 UINT64_C(221), // DMUHU
1493 UINT64_C(1879048195), // DMUL
1494 UINT64_C(28), // DMULT
1495 UINT64_C(29), // DMULTu
1496 UINT64_C(157), // DMULU
1497 UINT64_C(156), // DMUL_R6
1498 UINT64_C(2019557395), // DOTP_S_D
1499 UINT64_C(2015363091), // DOTP_S_H
1500 UINT64_C(2017460243), // DOTP_S_W
1501 UINT64_C(2027946003), // DOTP_U_D
1502 UINT64_C(2023751699), // DOTP_U_H
1503 UINT64_C(2025848851), // DOTP_U_W
1504 UINT64_C(2036334611), // DPADD_S_D
1505 UINT64_C(2032140307), // DPADD_S_H
1506 UINT64_C(2034237459), // DPADD_S_W
1507 UINT64_C(2044723219), // DPADD_U_D
1508 UINT64_C(2040528915), // DPADD_U_H
1509 UINT64_C(2042626067), // DPADD_U_W
1510 UINT64_C(2080376496), // DPAQX_SA_W_PH
1511 UINT64_C(12988), // DPAQX_SA_W_PH_MMR2
1512 UINT64_C(2080376368), // DPAQX_S_W_PH
1513 UINT64_C(8892), // DPAQX_S_W_PH_MMR2
1514 UINT64_C(2080375600), // DPAQ_SA_L_W
1515 UINT64_C(4796), // DPAQ_SA_L_W_MM
1516 UINT64_C(2080375088), // DPAQ_S_W_PH
1517 UINT64_C(700), // DPAQ_S_W_PH_MM
1518 UINT64_C(2080375024), // DPAU_H_QBL
1519 UINT64_C(8380), // DPAU_H_QBL_MM
1520 UINT64_C(2080375280), // DPAU_H_QBR
1521 UINT64_C(12476), // DPAU_H_QBR_MM
1522 UINT64_C(2080375344), // DPAX_W_PH
1523 UINT64_C(4284), // DPAX_W_PH_MMR2
1524 UINT64_C(2080374832), // DPA_W_PH
1525 UINT64_C(188), // DPA_W_PH_MMR2
1526 UINT64_C(1879048237), // DPOP
1527 UINT64_C(2080376560), // DPSQX_SA_W_PH
1528 UINT64_C(14012), // DPSQX_SA_W_PH_MMR2
1529 UINT64_C(2080376432), // DPSQX_S_W_PH
1530 UINT64_C(9916), // DPSQX_S_W_PH_MMR2
1531 UINT64_C(2080375664), // DPSQ_SA_L_W
1532 UINT64_C(5820), // DPSQ_SA_L_W_MM
1533 UINT64_C(2080375152), // DPSQ_S_W_PH
1534 UINT64_C(1724), // DPSQ_S_W_PH_MM
1535 UINT64_C(2053111827), // DPSUB_S_D
1536 UINT64_C(2048917523), // DPSUB_S_H
1537 UINT64_C(2051014675), // DPSUB_S_W
1538 UINT64_C(2061500435), // DPSUB_U_D
1539 UINT64_C(2057306131), // DPSUB_U_H
1540 UINT64_C(2059403283), // DPSUB_U_W
1541 UINT64_C(2080375536), // DPSU_H_QBL
1542 UINT64_C(9404), // DPSU_H_QBL_MM
1543 UINT64_C(2080375792), // DPSU_H_QBR
1544 UINT64_C(13500), // DPSU_H_QBR_MM
1545 UINT64_C(2080375408), // DPSX_W_PH
1546 UINT64_C(5308), // DPSX_W_PH_MMR2
1547 UINT64_C(2080374896), // DPS_W_PH
1548 UINT64_C(1212), // DPS_W_PH_MMR2
1549 UINT64_C(2097210), // DROTR
1550 UINT64_C(2097214), // DROTR32
1551 UINT64_C(86), // DROTRV
1552 UINT64_C(2080374948), // DSBH
1553 UINT64_C(30), // DSDIV
1554 UINT64_C(2080375140), // DSHD
1555 UINT64_C(56), // DSLL
1556 UINT64_C(60), // DSLL32
1557 UINT64_C(60), // DSLL64_32
1558 UINT64_C(20), // DSLLV
1559 UINT64_C(59), // DSRA
1560 UINT64_C(63), // DSRA32
1561 UINT64_C(23), // DSRAV
1562 UINT64_C(58), // DSRL
1563 UINT64_C(62), // DSRL32
1564 UINT64_C(22), // DSRLV
1565 UINT64_C(46), // DSUB
1566 UINT64_C(47), // DSUBu
1567 UINT64_C(31), // DUDIV
1568 UINT64_C(1096810532), // DVP
1569 UINT64_C(1096810497), // DVPE
1570 UINT64_C(6524), // DVP_MMR6
1571 UINT64_C(59418), // DivRxRy16
1572 UINT64_C(59419), // DivuRxRy16
1573 UINT64_C(192), // EHB
1574 UINT64_C(6144), // EHB_MM
1575 UINT64_C(6144), // EHB_MMR6
1576 UINT64_C(1096835104), // EI
1577 UINT64_C(22396), // EI_MM
1578 UINT64_C(22396), // EI_MMR6
1579 UINT64_C(1096813537), // EMT
1580 UINT64_C(1107296280), // ERET
1581 UINT64_C(1107296344), // ERETNC
1582 UINT64_C(127868), // ERETNC_MMR6
1583 UINT64_C(62332), // ERET_MM
1584 UINT64_C(62332), // ERET_MMR6
1585 UINT64_C(1096810500), // EVP
1586 UINT64_C(1096810529), // EVPE
1587 UINT64_C(14716), // EVP_MMR6
1588 UINT64_C(2080374784), // EXT
1589 UINT64_C(2080374968), // EXTP
1590 UINT64_C(2080375480), // EXTPDP
1591 UINT64_C(2080375544), // EXTPDPV
1592 UINT64_C(14524), // EXTPDPV_MM
1593 UINT64_C(13948), // EXTPDP_MM
1594 UINT64_C(2080375032), // EXTPV
1595 UINT64_C(10428), // EXTPV_MM
1596 UINT64_C(9852), // EXTP_MM
1597 UINT64_C(2080375288), // EXTRV_RS_W
1598 UINT64_C(11964), // EXTRV_RS_W_MM
1599 UINT64_C(2080375160), // EXTRV_R_W
1600 UINT64_C(7868), // EXTRV_R_W_MM
1601 UINT64_C(2080375800), // EXTRV_S_H
1602 UINT64_C(16060), // EXTRV_S_H_MM
1603 UINT64_C(2080374904), // EXTRV_W
1604 UINT64_C(3772), // EXTRV_W_MM
1605 UINT64_C(2080375224), // EXTR_RS_W
1606 UINT64_C(11900), // EXTR_RS_W_MM
1607 UINT64_C(2080375096), // EXTR_R_W
1608 UINT64_C(7804), // EXTR_R_W_MM
1609 UINT64_C(2080375736), // EXTR_S_H
1610 UINT64_C(15996), // EXTR_S_H_MM
1611 UINT64_C(2080374840), // EXTR_W
1612 UINT64_C(3708), // EXTR_W_MM
1613 UINT64_C(1879048250), // EXTS
1614 UINT64_C(1879048251), // EXTS32
1615 UINT64_C(44), // EXT_MM
1616 UINT64_C(44), // EXT_MMR6
1617 UINT64_C(1176502277), // FABS_D32
1618 UINT64_C(1409295227), // FABS_D32_MM
1619 UINT64_C(1176502277), // FABS_D64
1620 UINT64_C(1409295227), // FABS_D64_MM
1621 UINT64_C(1174405125), // FABS_S
1622 UINT64_C(1409287035), // FABS_S_MM
1623 UINT64_C(2015363099), // FADD_D
1624 UINT64_C(1176502272), // FADD_D32
1625 UINT64_C(1409286448), // FADD_D32_MM
1626 UINT64_C(1176502272), // FADD_D64
1627 UINT64_C(1409286448), // FADD_D64_MM
1628 UINT64_C(1186988032), // FADD_PS64
1629 UINT64_C(1174405120), // FADD_S
1630 UINT64_C(1409286192), // FADD_S_MM
1631 UINT64_C(1409286192), // FADD_S_MMR6
1632 UINT64_C(2013265947), // FADD_W
1633 UINT64_C(2015363098), // FCAF_D
1634 UINT64_C(2013265946), // FCAF_W
1635 UINT64_C(2023751706), // FCEQ_D
1636 UINT64_C(2021654554), // FCEQ_W
1637 UINT64_C(2065760286), // FCLASS_D
1638 UINT64_C(2065694750), // FCLASS_W
1639 UINT64_C(2040528922), // FCLE_D
1640 UINT64_C(2038431770), // FCLE_W
1641 UINT64_C(2032140314), // FCLT_D
1642 UINT64_C(2030043162), // FCLT_W
1643 UINT64_C(1176502320), // FCMP_D32
1644 UINT64_C(1409287228), // FCMP_D32_MM
1645 UINT64_C(1176502320), // FCMP_D64
1646 UINT64_C(1174405168), // FCMP_S32
1647 UINT64_C(1409286204), // FCMP_S32_MM
1648 UINT64_C(2027946012), // FCNE_D
1649 UINT64_C(2025848860), // FCNE_W
1650 UINT64_C(2019557404), // FCOR_D
1651 UINT64_C(2017460252), // FCOR_W
1652 UINT64_C(2027946010), // FCUEQ_D
1653 UINT64_C(2025848858), // FCUEQ_W
1654 UINT64_C(2044723226), // FCULE_D
1655 UINT64_C(2042626074), // FCULE_W
1656 UINT64_C(2036334618), // FCULT_D
1657 UINT64_C(2034237466), // FCULT_W
1658 UINT64_C(2023751708), // FCUNE_D
1659 UINT64_C(2021654556), // FCUNE_W
1660 UINT64_C(2019557402), // FCUN_D
1661 UINT64_C(2017460250), // FCUN_W
1662 UINT64_C(2027946011), // FDIV_D
1663 UINT64_C(1176502275), // FDIV_D32
1664 UINT64_C(1409286640), // FDIV_D32_MM
1665 UINT64_C(1176502275), // FDIV_D64
1666 UINT64_C(1409286640), // FDIV_D64_MM
1667 UINT64_C(1174405123), // FDIV_S
1668 UINT64_C(1409286384), // FDIV_S_MM
1669 UINT64_C(1409286384), // FDIV_S_MMR6
1670 UINT64_C(2025848859), // FDIV_W
1671 UINT64_C(2046820379), // FEXDO_H
1672 UINT64_C(2048917531), // FEXDO_W
1673 UINT64_C(2044723227), // FEXP2_D
1674 UINT64_C(2042626075), // FEXP2_W
1675 UINT64_C(2066808862), // FEXUPL_D
1676 UINT64_C(2066743326), // FEXUPL_W
1677 UINT64_C(2066939934), // FEXUPR_D
1678 UINT64_C(2066874398), // FEXUPR_W
1679 UINT64_C(2067595294), // FFINT_S_D
1680 UINT64_C(2067529758), // FFINT_S_W
1681 UINT64_C(2067726366), // FFINT_U_D
1682 UINT64_C(2067660830), // FFINT_U_W
1683 UINT64_C(2067071006), // FFQL_D
1684 UINT64_C(2067005470), // FFQL_W
1685 UINT64_C(2067202078), // FFQR_D
1686 UINT64_C(2067136542), // FFQR_W
1687 UINT64_C(2063597598), // FILL_B
1688 UINT64_C(2063794206), // FILL_D
1689 UINT64_C(2063663134), // FILL_H
1690 UINT64_C(2063728670), // FILL_W
1691 UINT64_C(2066677790), // FLOG2_D
1692 UINT64_C(2066612254), // FLOG2_W
1693 UINT64_C(1176502283), // FLOOR_L_D64
1694 UINT64_C(1409303355), // FLOOR_L_D_MMR6
1695 UINT64_C(1174405131), // FLOOR_L_S
1696 UINT64_C(1409286971), // FLOOR_L_S_MMR6
1697 UINT64_C(1176502287), // FLOOR_W_D32
1698 UINT64_C(1176502287), // FLOOR_W_D64
1699 UINT64_C(1409305403), // FLOOR_W_D_MMR6
1700 UINT64_C(1409305403), // FLOOR_W_MM
1701 UINT64_C(1174405135), // FLOOR_W_S
1702 UINT64_C(1409289019), // FLOOR_W_S_MM
1703 UINT64_C(1409289019), // FLOOR_W_S_MMR6
1704 UINT64_C(2032140315), // FMADD_D
1705 UINT64_C(2030043163), // FMADD_W
1706 UINT64_C(2078277659), // FMAX_A_D
1707 UINT64_C(2076180507), // FMAX_A_W
1708 UINT64_C(2074083355), // FMAX_D
1709 UINT64_C(2071986203), // FMAX_W
1710 UINT64_C(2069889051), // FMIN_A_D
1711 UINT64_C(2067791899), // FMIN_A_W
1712 UINT64_C(2065694747), // FMIN_D
1713 UINT64_C(2063597595), // FMIN_W
1714 UINT64_C(1176502278), // FMOV_D32
1715 UINT64_C(1409294459), // FMOV_D32_MM
1716 UINT64_C(1176502278), // FMOV_D64
1717 UINT64_C(1409294459), // FMOV_D64_MM
1718 UINT64_C(1409294459), // FMOV_D_MMR6
1719 UINT64_C(1174405126), // FMOV_S
1720 UINT64_C(1409286267), // FMOV_S_MM
1721 UINT64_C(1409286267), // FMOV_S_MMR6
1722 UINT64_C(2036334619), // FMSUB_D
1723 UINT64_C(2034237467), // FMSUB_W
1724 UINT64_C(2023751707), // FMUL_D
1725 UINT64_C(1176502274), // FMUL_D32
1726 UINT64_C(1409286576), // FMUL_D32_MM
1727 UINT64_C(1176502274), // FMUL_D64
1728 UINT64_C(1409286576), // FMUL_D64_MM
1729 UINT64_C(1186988034), // FMUL_PS64
1730 UINT64_C(1174405122), // FMUL_S
1731 UINT64_C(1409286320), // FMUL_S_MM
1732 UINT64_C(1409286320), // FMUL_S_MMR6
1733 UINT64_C(2021654555), // FMUL_W
1734 UINT64_C(1176502279), // FNEG_D32
1735 UINT64_C(1409297275), // FNEG_D32_MM
1736 UINT64_C(1176502279), // FNEG_D64
1737 UINT64_C(1409297275), // FNEG_D64_MM
1738 UINT64_C(1174405127), // FNEG_S
1739 UINT64_C(1409289083), // FNEG_S_MM
1740 UINT64_C(1409289083), // FNEG_S_MMR6
1741 UINT64_C(2080374792), // FORK
1742 UINT64_C(2066415646), // FRCP_D
1743 UINT64_C(2066350110), // FRCP_W
1744 UINT64_C(2066546718), // FRINT_D
1745 UINT64_C(2066481182), // FRINT_W
1746 UINT64_C(2066284574), // FRSQRT_D
1747 UINT64_C(2066219038), // FRSQRT_W
1748 UINT64_C(2048917530), // FSAF_D
1749 UINT64_C(2046820378), // FSAF_W
1750 UINT64_C(2057306138), // FSEQ_D
1751 UINT64_C(2055208986), // FSEQ_W
1752 UINT64_C(2074083354), // FSLE_D
1753 UINT64_C(2071986202), // FSLE_W
1754 UINT64_C(2065694746), // FSLT_D
1755 UINT64_C(2063597594), // FSLT_W
1756 UINT64_C(2061500444), // FSNE_D
1757 UINT64_C(2059403292), // FSNE_W
1758 UINT64_C(2053111836), // FSOR_D
1759 UINT64_C(2051014684), // FSOR_W
1760 UINT64_C(2066153502), // FSQRT_D
1761 UINT64_C(1176502276), // FSQRT_D32
1762 UINT64_C(1409305147), // FSQRT_D32_MM
1763 UINT64_C(1176502276), // FSQRT_D64
1764 UINT64_C(1409305147), // FSQRT_D64_MM
1765 UINT64_C(1174405124), // FSQRT_S
1766 UINT64_C(1409288763), // FSQRT_S_MM
1767 UINT64_C(2066087966), // FSQRT_W
1768 UINT64_C(2019557403), // FSUB_D
1769 UINT64_C(1176502273), // FSUB_D32
1770 UINT64_C(1409286512), // FSUB_D32_MM
1771 UINT64_C(1176502273), // FSUB_D64
1772 UINT64_C(1409286512), // FSUB_D64_MM
1773 UINT64_C(1186988033), // FSUB_PS64
1774 UINT64_C(1174405121), // FSUB_S
1775 UINT64_C(1409286256), // FSUB_S_MM
1776 UINT64_C(1409286256), // FSUB_S_MMR6
1777 UINT64_C(2017460251), // FSUB_W
1778 UINT64_C(2061500442), // FSUEQ_D
1779 UINT64_C(2059403290), // FSUEQ_W
1780 UINT64_C(2078277658), // FSULE_D
1781 UINT64_C(2076180506), // FSULE_W
1782 UINT64_C(2069889050), // FSULT_D
1783 UINT64_C(2067791898), // FSULT_W
1784 UINT64_C(2057306140), // FSUNE_D
1785 UINT64_C(2055208988), // FSUNE_W
1786 UINT64_C(2053111834), // FSUN_D
1787 UINT64_C(2051014682), // FSUN_W
1788 UINT64_C(2067333150), // FTINT_S_D
1789 UINT64_C(2067267614), // FTINT_S_W
1790 UINT64_C(2067464222), // FTINT_U_D
1791 UINT64_C(2067398686), // FTINT_U_W
1792 UINT64_C(2055208987), // FTQ_H
1793 UINT64_C(2057306139), // FTQ_W
1794 UINT64_C(2065891358), // FTRUNC_S_D
1795 UINT64_C(2065825822), // FTRUNC_S_W
1796 UINT64_C(2066022430), // FTRUNC_U_D
1797 UINT64_C(2065956894), // FTRUNC_U_W
1798 UINT64_C(2080374845), // GINVI
1799 UINT64_C(24956), // GINVI_MMR6
1800 UINT64_C(2080374973), // GINVT
1801 UINT64_C(29052), // GINVT_MMR6
1802 UINT64_C(2053111829), // HADD_S_D
1803 UINT64_C(2048917525), // HADD_S_H
1804 UINT64_C(2051014677), // HADD_S_W
1805 UINT64_C(2061500437), // HADD_U_D
1806 UINT64_C(2057306133), // HADD_U_H
1807 UINT64_C(2059403285), // HADD_U_W
1808 UINT64_C(2069889045), // HSUB_S_D
1809 UINT64_C(2065694741), // HSUB_S_H
1810 UINT64_C(2067791893), // HSUB_S_W
1811 UINT64_C(2078277653), // HSUB_U_D
1812 UINT64_C(2074083349), // HSUB_U_H
1813 UINT64_C(2076180501), // HSUB_U_W
1814 UINT64_C(1107296296), // HYPCALL
1815 UINT64_C(50044), // HYPCALL_MM
1816 UINT64_C(2063597588), // ILVEV_B
1817 UINT64_C(2069889044), // ILVEV_D
1818 UINT64_C(2065694740), // ILVEV_H
1819 UINT64_C(2067791892), // ILVEV_W
1820 UINT64_C(2046820372), // ILVL_B
1821 UINT64_C(2053111828), // ILVL_D
1822 UINT64_C(2048917524), // ILVL_H
1823 UINT64_C(2051014676), // ILVL_W
1824 UINT64_C(2071986196), // ILVOD_B
1825 UINT64_C(2078277652), // ILVOD_D
1826 UINT64_C(2074083348), // ILVOD_H
1827 UINT64_C(2076180500), // ILVOD_W
1828 UINT64_C(2055208980), // ILVR_B
1829 UINT64_C(2061500436), // ILVR_D
1830 UINT64_C(2057306132), // ILVR_H
1831 UINT64_C(2059403284), // ILVR_W
1832 UINT64_C(2080374788), // INS
1833 UINT64_C(2030043161), // INSERT_B
1834 UINT64_C(2033713177), // INSERT_D
1835 UINT64_C(2032140313), // INSERT_H
1836 UINT64_C(2033188889), // INSERT_W
1837 UINT64_C(2080374796), // INSV
1838 UINT64_C(2034237465), // INSVE_B
1839 UINT64_C(2037907481), // INSVE_D
1840 UINT64_C(2036334617), // INSVE_H
1841 UINT64_C(2037383193), // INSVE_W
1842 UINT64_C(16700), // INSV_MM
1843 UINT64_C(12), // INS_MM
1844 UINT64_C(12), // INS_MMR6
1845 UINT64_C(134217728), // J
1846 UINT64_C(201326592), // JAL
1847 UINT64_C(9), // JALR
1848 UINT64_C(17856), // JALR16_MM
1849 UINT64_C(9), // JALR64
1850 UINT64_C(17419), // JALRC16_MMR6
1851 UINT64_C(7996), // JALRC_HB_MMR6
1852 UINT64_C(3900), // JALRC_MMR6
1853 UINT64_C(17888), // JALRS16_MM
1854 UINT64_C(20284), // JALRS_MM
1855 UINT64_C(1033), // JALR_HB
1856 UINT64_C(1033), // JALR_HB64
1857 UINT64_C(3900), // JALR_MM
1858 UINT64_C(1946157056), // JALS_MM
1859 UINT64_C(1946157056), // JALX
1860 UINT64_C(4026531840), // JALX_MM
1861 UINT64_C(4093640704), // JAL_MM
1862 UINT64_C(4160749568), // JIALC
1863 UINT64_C(4160749568), // JIALC64
1864 UINT64_C(2147483648), // JIALC_MMR6
1865 UINT64_C(3623878656), // JIC
1866 UINT64_C(3623878656), // JIC64
1867 UINT64_C(2684354560), // JIC_MMR6
1868 UINT64_C(8), // JR
1869 UINT64_C(17792), // JR16_MM
1870 UINT64_C(8), // JR64
1871 UINT64_C(18176), // JRADDIUSP
1872 UINT64_C(17824), // JRC16_MM
1873 UINT64_C(17411), // JRC16_MMR6
1874 UINT64_C(17427), // JRCADDIUSP_MMR6
1875 UINT64_C(1032), // JR_HB
1876 UINT64_C(1032), // JR_HB64
1877 UINT64_C(1033), // JR_HB64_R6
1878 UINT64_C(1033), // JR_HB_R6
1879 UINT64_C(3900), // JR_MM
1880 UINT64_C(3556769792), // J_MM
1881 UINT64_C(402653184), // Jal16
1882 UINT64_C(402653184), // JalB16
1883 UINT64_C(59424), // JrRa16
1884 UINT64_C(59616), // JrcRa16
1885 UINT64_C(59584), // JrcRx16
1886 UINT64_C(59392), // JumpLinkReg16
1887 UINT64_C(2147483648), // LB
1888 UINT64_C(2147483648), // LB64
1889 UINT64_C(2080374828), // LBE
1890 UINT64_C(1610639360), // LBE_MM
1891 UINT64_C(2048), // LBU16_MM
1892 UINT64_C(2080375178), // LBUX
1893 UINT64_C(549), // LBUX_MM
1894 UINT64_C(335544320), // LBU_MMR6
1895 UINT64_C(469762048), // LB_MM
1896 UINT64_C(469762048), // LB_MMR6
1897 UINT64_C(2415919104), // LBu
1898 UINT64_C(2415919104), // LBu64
1899 UINT64_C(2080374824), // LBuE
1900 UINT64_C(1610637312), // LBuE_MM
1901 UINT64_C(335544320), // LBu_MM
1902 UINT64_C(3690987520), // LD
1903 UINT64_C(3556769792), // LDC1
1904 UINT64_C(3556769792), // LDC164
1905 UINT64_C(3154116608), // LDC1_D64_MMR6
1906 UINT64_C(3154116608), // LDC1_MM_D32
1907 UINT64_C(3154116608), // LDC1_MM_D64
1908 UINT64_C(3623878656), // LDC2
1909 UINT64_C(536879104), // LDC2_MMR6
1910 UINT64_C(1237319680), // LDC2_R6
1911 UINT64_C(3690987520), // LDC3
1912 UINT64_C(2063597575), // LDI_B
1913 UINT64_C(2069889031), // LDI_D
1914 UINT64_C(2065694727), // LDI_H
1915 UINT64_C(2067791879), // LDI_W
1916 UINT64_C(1744830464), // LDL
1917 UINT64_C(3960995840), // LDPC
1918 UINT64_C(1811939328), // LDR
1919 UINT64_C(1275068417), // LDXC1
1920 UINT64_C(1275068417), // LDXC164
1921 UINT64_C(2013265952), // LD_B
1922 UINT64_C(2013265955), // LD_D
1923 UINT64_C(2013265953), // LD_H
1924 UINT64_C(2013265954), // LD_W
1925 UINT64_C(603979776), // LEA_ADDiu
1926 UINT64_C(1677721600), // LEA_ADDiu64
1927 UINT64_C(805306368), // LEA_ADDiu_MM
1928 UINT64_C(2214592512), // LH
1929 UINT64_C(2214592512), // LH64
1930 UINT64_C(2080374829), // LHE
1931 UINT64_C(1610639872), // LHE_MM
1932 UINT64_C(10240), // LHU16_MM
1933 UINT64_C(2080375050), // LHX
1934 UINT64_C(357), // LHX_MM
1935 UINT64_C(1006632960), // LH_MM
1936 UINT64_C(2483027968), // LHu
1937 UINT64_C(2483027968), // LHu64
1938 UINT64_C(2080374825), // LHuE
1939 UINT64_C(1610637824), // LHuE_MM
1940 UINT64_C(872415232), // LHu_MM
1941 UINT64_C(60416), // LI16_MM
1942 UINT64_C(60416), // LI16_MMR6
1943 UINT64_C(3221225472), // LL
1944 UINT64_C(3221225472), // LL64
1945 UINT64_C(2080374838), // LL64_R6
1946 UINT64_C(3489660928), // LLD
1947 UINT64_C(2080374839), // LLD_R6
1948 UINT64_C(2080374830), // LLE
1949 UINT64_C(1610640384), // LLE_MM
1950 UINT64_C(1610625024), // LL_MM
1951 UINT64_C(1610625024), // LL_MMR6
1952 UINT64_C(2080374838), // LL_R6
1953 UINT64_C(5), // LSA
1954 UINT64_C(15), // LSA_MMR6
1955 UINT64_C(5), // LSA_R6
1956 UINT64_C(268435456), // LUI_MMR6
1957 UINT64_C(1275068421), // LUXC1
1958 UINT64_C(1275068421), // LUXC164
1959 UINT64_C(1409286472), // LUXC1_MM
1960 UINT64_C(1006632960), // LUi
1961 UINT64_C(1006632960), // LUi64
1962 UINT64_C(1101004800), // LUi_MM
1963 UINT64_C(2348810240), // LW
1964 UINT64_C(26624), // LW16_MM
1965 UINT64_C(2348810240), // LW64
1966 UINT64_C(3288334336), // LWC1
1967 UINT64_C(2617245696), // LWC1_MM
1968 UINT64_C(3355443200), // LWC2
1969 UINT64_C(536870912), // LWC2_MMR6
1970 UINT64_C(1228931072), // LWC2_R6
1971 UINT64_C(3422552064), // LWC3
1972 UINT64_C(2348810240), // LWDSP
1973 UINT64_C(4227858432), // LWDSP_MM
1974 UINT64_C(2080374831), // LWE
1975 UINT64_C(1610640896), // LWE_MM
1976 UINT64_C(25600), // LWGP_MM
1977 UINT64_C(2281701376), // LWL
1978 UINT64_C(2281701376), // LWL64
1979 UINT64_C(2080374809), // LWLE
1980 UINT64_C(1610638336), // LWLE_MM
1981 UINT64_C(1610612736), // LWL_MM
1982 UINT64_C(17664), // LWM16_MM
1983 UINT64_C(17410), // LWM16_MMR6
1984 UINT64_C(536891392), // LWM32_MM
1985 UINT64_C(3959947264), // LWPC
1986 UINT64_C(2013790208), // LWPC_MMR6
1987 UINT64_C(536875008), // LWP_MM
1988 UINT64_C(2550136832), // LWR
1989 UINT64_C(2550136832), // LWR64
1990 UINT64_C(2080374810), // LWRE
1991 UINT64_C(1610638848), // LWRE_MM
1992 UINT64_C(1610616832), // LWR_MM
1993 UINT64_C(18432), // LWSP_MM
1994 UINT64_C(3960471552), // LWUPC
1995 UINT64_C(1610670080), // LWU_MM
1996 UINT64_C(2080374794), // LWX
1997 UINT64_C(1275068416), // LWXC1
1998 UINT64_C(1409286216), // LWXC1_MM
1999 UINT64_C(280), // LWXS_MM
2000 UINT64_C(421), // LWX_MM
2001 UINT64_C(4227858432), // LW_MM
2002 UINT64_C(4227858432), // LW_MMR6
2003 UINT64_C(2617245696), // LWu
2004 UINT64_C(4026570752), // LbRxRyOffMemX16
2005 UINT64_C(4026572800), // LbuRxRyOffMemX16
2006 UINT64_C(4026572800), // LhRxRyOffMemX16
2007 UINT64_C(4026572800), // LhuRxRyOffMemX16
2008 UINT64_C(26624), // LiRxImm16
2009 UINT64_C(4026558464), // LiRxImmAlignX16
2010 UINT64_C(4026558464), // LiRxImmX16
2011 UINT64_C(45056), // LwRxPcTcp16
2012 UINT64_C(4026576896), // LwRxPcTcpX16
2013 UINT64_C(4026570752), // LwRxRyOffMemX16
2014 UINT64_C(4026568704), // LwRxSpImmX16
2015 UINT64_C(1879048192), // MADD
2016 UINT64_C(1176502296), // MADDF_D
2017 UINT64_C(1409287096), // MADDF_D_MMR6
2018 UINT64_C(1174405144), // MADDF_S
2019 UINT64_C(1409286584), // MADDF_S_MMR6
2020 UINT64_C(2067791900), // MADDR_Q_H
2021 UINT64_C(2069889052), // MADDR_Q_W
2022 UINT64_C(1879048193), // MADDU
2023 UINT64_C(1879048193), // MADDU_DSP
2024 UINT64_C(6844), // MADDU_DSP_MM
2025 UINT64_C(56124), // MADDU_MM
2026 UINT64_C(2021654546), // MADDV_B
2027 UINT64_C(2027946002), // MADDV_D
2028 UINT64_C(2023751698), // MADDV_H
2029 UINT64_C(2025848850), // MADDV_W
2030 UINT64_C(1275068449), // MADD_D32
2031 UINT64_C(1409286153), // MADD_D32_MM
2032 UINT64_C(1275068449), // MADD_D64
2033 UINT64_C(1879048192), // MADD_DSP
2034 UINT64_C(2748), // MADD_DSP_MM
2035 UINT64_C(52028), // MADD_MM
2036 UINT64_C(2034237468), // MADD_Q_H
2037 UINT64_C(2036334620), // MADD_Q_W
2038 UINT64_C(1275068448), // MADD_S
2039 UINT64_C(1409286145), // MADD_S_MM
2040 UINT64_C(2080375856), // MAQ_SA_W_PHL
2041 UINT64_C(14972), // MAQ_SA_W_PHL_MM
2042 UINT64_C(2080375984), // MAQ_SA_W_PHR
2043 UINT64_C(10876), // MAQ_SA_W_PHR_MM
2044 UINT64_C(2080376112), // MAQ_S_W_PHL
2045 UINT64_C(6780), // MAQ_S_W_PHL_MM
2046 UINT64_C(2080376240), // MAQ_S_W_PHR
2047 UINT64_C(2684), // MAQ_S_W_PHR_MM
2048 UINT64_C(1176502303), // MAXA_D
2049 UINT64_C(1409286699), // MAXA_D_MMR6
2050 UINT64_C(1174405151), // MAXA_S
2051 UINT64_C(1409286187), // MAXA_S_MMR6
2052 UINT64_C(2030043142), // MAXI_S_B
2053 UINT64_C(2036334598), // MAXI_S_D
2054 UINT64_C(2032140294), // MAXI_S_H
2055 UINT64_C(2034237446), // MAXI_S_W
2056 UINT64_C(2038431750), // MAXI_U_B
2057 UINT64_C(2044723206), // MAXI_U_D
2058 UINT64_C(2040528902), // MAXI_U_H
2059 UINT64_C(2042626054), // MAXI_U_W
2060 UINT64_C(2063597582), // MAX_A_B
2061 UINT64_C(2069889038), // MAX_A_D
2062 UINT64_C(2065694734), // MAX_A_H
2063 UINT64_C(2067791886), // MAX_A_W
2064 UINT64_C(1176502302), // MAX_D
2065 UINT64_C(1409286667), // MAX_D_MMR6
2066 UINT64_C(1174405150), // MAX_S
2067 UINT64_C(2030043150), // MAX_S_B
2068 UINT64_C(2036334606), // MAX_S_D
2069 UINT64_C(2032140302), // MAX_S_H
2070 UINT64_C(1409286155), // MAX_S_MMR6
2071 UINT64_C(2034237454), // MAX_S_W
2072 UINT64_C(2038431758), // MAX_U_B
2073 UINT64_C(2044723214), // MAX_U_D
2074 UINT64_C(2040528910), // MAX_U_H
2075 UINT64_C(2042626062), // MAX_U_W
2076 UINT64_C(1073741824), // MFC0
2077 UINT64_C(252), // MFC0_MMR6
2078 UINT64_C(1140850688), // MFC1
2079 UINT64_C(1140850688), // MFC1_D64
2080 UINT64_C(1409294395), // MFC1_MM
2081 UINT64_C(1409294395), // MFC1_MMR6
2082 UINT64_C(1207959552), // MFC2
2083 UINT64_C(19772), // MFC2_MMR6
2084 UINT64_C(1080033280), // MFGC0
2085 UINT64_C(1276), // MFGC0_MM
2086 UINT64_C(244), // MFHC0_MMR6
2087 UINT64_C(1147142144), // MFHC1_D32
2088 UINT64_C(1409298491), // MFHC1_D32_MM
2089 UINT64_C(1147142144), // MFHC1_D64
2090 UINT64_C(1409298491), // MFHC1_D64_MM
2091 UINT64_C(36156), // MFHC2_MMR6
2092 UINT64_C(1080034304), // MFHGC0
2093 UINT64_C(1268), // MFHGC0_MM
2094 UINT64_C(16), // MFHI
2095 UINT64_C(17920), // MFHI16_MM
2096 UINT64_C(16), // MFHI64
2097 UINT64_C(16), // MFHI_DSP
2098 UINT64_C(124), // MFHI_DSP_MM
2099 UINT64_C(3452), // MFHI_MM
2100 UINT64_C(18), // MFLO
2101 UINT64_C(17984), // MFLO16_MM
2102 UINT64_C(18), // MFLO64
2103 UINT64_C(18), // MFLO_DSP
2104 UINT64_C(4220), // MFLO_DSP_MM
2105 UINT64_C(7548), // MFLO_MM
2106 UINT64_C(1090519040), // MFTR
2107 UINT64_C(1176502301), // MINA_D
2108 UINT64_C(1409286691), // MINA_D_MMR6
2109 UINT64_C(1174405149), // MINA_S
2110 UINT64_C(1409286179), // MINA_S_MMR6
2111 UINT64_C(2046820358), // MINI_S_B
2112 UINT64_C(2053111814), // MINI_S_D
2113 UINT64_C(2048917510), // MINI_S_H
2114 UINT64_C(2051014662), // MINI_S_W
2115 UINT64_C(2055208966), // MINI_U_B
2116 UINT64_C(2061500422), // MINI_U_D
2117 UINT64_C(2057306118), // MINI_U_H
2118 UINT64_C(2059403270), // MINI_U_W
2119 UINT64_C(2071986190), // MIN_A_B
2120 UINT64_C(2078277646), // MIN_A_D
2121 UINT64_C(2074083342), // MIN_A_H
2122 UINT64_C(2076180494), // MIN_A_W
2123 UINT64_C(1176502300), // MIN_D
2124 UINT64_C(1409286659), // MIN_D_MMR6
2125 UINT64_C(1174405148), // MIN_S
2126 UINT64_C(2046820366), // MIN_S_B
2127 UINT64_C(2053111822), // MIN_S_D
2128 UINT64_C(2048917518), // MIN_S_H
2129 UINT64_C(1409286147), // MIN_S_MMR6
2130 UINT64_C(2051014670), // MIN_S_W
2131 UINT64_C(2055208974), // MIN_U_B
2132 UINT64_C(2061500430), // MIN_U_D
2133 UINT64_C(2057306126), // MIN_U_H
2134 UINT64_C(2059403278), // MIN_U_W
2135 UINT64_C(218), // MOD
2136 UINT64_C(2080375952), // MODSUB
2137 UINT64_C(661), // MODSUB_MM
2138 UINT64_C(219), // MODU
2139 UINT64_C(472), // MODU_MMR6
2140 UINT64_C(344), // MOD_MMR6
2141 UINT64_C(2063597586), // MOD_S_B
2142 UINT64_C(2069889042), // MOD_S_D
2143 UINT64_C(2065694738), // MOD_S_H
2144 UINT64_C(2067791890), // MOD_S_W
2145 UINT64_C(2071986194), // MOD_U_B
2146 UINT64_C(2078277650), // MOD_U_D
2147 UINT64_C(2074083346), // MOD_U_H
2148 UINT64_C(2076180498), // MOD_U_W
2149 UINT64_C(3072), // MOVE16_MM
2150 UINT64_C(3072), // MOVE16_MMR6
2151 UINT64_C(33792), // MOVEP_MM
2152 UINT64_C(17412), // MOVEP_MMR6
2153 UINT64_C(2025717785), // MOVE_V
2154 UINT64_C(1176502289), // MOVF_D32
2155 UINT64_C(1409286688), // MOVF_D32_MM
2156 UINT64_C(1176502289), // MOVF_D64
2157 UINT64_C(1), // MOVF_I
2158 UINT64_C(1), // MOVF_I64
2159 UINT64_C(1409286523), // MOVF_I_MM
2160 UINT64_C(1174405137), // MOVF_S
2161 UINT64_C(1409286176), // MOVF_S_MM
2162 UINT64_C(1176502291), // MOVN_I64_D64
2163 UINT64_C(11), // MOVN_I64_I
2164 UINT64_C(11), // MOVN_I64_I64
2165 UINT64_C(1174405139), // MOVN_I64_S
2166 UINT64_C(1176502291), // MOVN_I_D32
2167 UINT64_C(1409286456), // MOVN_I_D32_MM
2168 UINT64_C(1176502291), // MOVN_I_D64
2169 UINT64_C(11), // MOVN_I_I
2170 UINT64_C(11), // MOVN_I_I64
2171 UINT64_C(24), // MOVN_I_MM
2172 UINT64_C(1174405139), // MOVN_I_S
2173 UINT64_C(1409286200), // MOVN_I_S_MM
2174 UINT64_C(1176567825), // MOVT_D32
2175 UINT64_C(1409286752), // MOVT_D32_MM
2176 UINT64_C(1176567825), // MOVT_D64
2177 UINT64_C(65537), // MOVT_I
2178 UINT64_C(65537), // MOVT_I64
2179 UINT64_C(1409288571), // MOVT_I_MM
2180 UINT64_C(1174470673), // MOVT_S
2181 UINT64_C(1409286240), // MOVT_S_MM
2182 UINT64_C(1176502290), // MOVZ_I64_D64
2183 UINT64_C(10), // MOVZ_I64_I
2184 UINT64_C(10), // MOVZ_I64_I64
2185 UINT64_C(1174405138), // MOVZ_I64_S
2186 UINT64_C(1176502290), // MOVZ_I_D32
2187 UINT64_C(1409286520), // MOVZ_I_D32_MM
2188 UINT64_C(1176502290), // MOVZ_I_D64
2189 UINT64_C(10), // MOVZ_I_I
2190 UINT64_C(10), // MOVZ_I_I64
2191 UINT64_C(88), // MOVZ_I_MM
2192 UINT64_C(1174405138), // MOVZ_I_S
2193 UINT64_C(1409286264), // MOVZ_I_S_MM
2194 UINT64_C(1879048196), // MSUB
2195 UINT64_C(1176502297), // MSUBF_D
2196 UINT64_C(1409287160), // MSUBF_D_MMR6
2197 UINT64_C(1174405145), // MSUBF_S
2198 UINT64_C(1409286648), // MSUBF_S_MMR6
2199 UINT64_C(2071986204), // MSUBR_Q_H
2200 UINT64_C(2074083356), // MSUBR_Q_W
2201 UINT64_C(1879048197), // MSUBU
2202 UINT64_C(1879048197), // MSUBU_DSP
2203 UINT64_C(15036), // MSUBU_DSP_MM
2204 UINT64_C(64316), // MSUBU_MM
2205 UINT64_C(2030043154), // MSUBV_B
2206 UINT64_C(2036334610), // MSUBV_D
2207 UINT64_C(2032140306), // MSUBV_H
2208 UINT64_C(2034237458), // MSUBV_W
2209 UINT64_C(1275068457), // MSUB_D32
2210 UINT64_C(1409286185), // MSUB_D32_MM
2211 UINT64_C(1275068457), // MSUB_D64
2212 UINT64_C(1879048196), // MSUB_DSP
2213 UINT64_C(10940), // MSUB_DSP_MM
2214 UINT64_C(60220), // MSUB_MM
2215 UINT64_C(2038431772), // MSUB_Q_H
2216 UINT64_C(2040528924), // MSUB_Q_W
2217 UINT64_C(1275068456), // MSUB_S
2218 UINT64_C(1409286177), // MSUB_S_MM
2219 UINT64_C(1082130432), // MTC0
2220 UINT64_C(764), // MTC0_MMR6
2221 UINT64_C(1149239296), // MTC1
2222 UINT64_C(1149239296), // MTC1_D64
2223 UINT64_C(1409296443), // MTC1_D64_MM
2224 UINT64_C(1409296443), // MTC1_MM
2225 UINT64_C(1409296443), // MTC1_MMR6
2226 UINT64_C(1216348160), // MTC2
2227 UINT64_C(23868), // MTC2_MMR6
2228 UINT64_C(1080033792), // MTGC0
2229 UINT64_C(1788), // MTGC0_MM
2230 UINT64_C(756), // MTHC0_MMR6
2231 UINT64_C(1155530752), // MTHC1_D32
2232 UINT64_C(1409300539), // MTHC1_D32_MM
2233 UINT64_C(1155530752), // MTHC1_D64
2234 UINT64_C(1409300539), // MTHC1_D64_MM
2235 UINT64_C(40252), // MTHC2_MMR6
2236 UINT64_C(1080034816), // MTHGC0
2237 UINT64_C(1780), // MTHGC0_MM
2238 UINT64_C(17), // MTHI
2239 UINT64_C(17), // MTHI64
2240 UINT64_C(17), // MTHI_DSP
2241 UINT64_C(8316), // MTHI_DSP_MM
2242 UINT64_C(11644), // MTHI_MM
2243 UINT64_C(2080376824), // MTHLIP
2244 UINT64_C(636), // MTHLIP_MM
2245 UINT64_C(19), // MTLO
2246 UINT64_C(19), // MTLO64
2247 UINT64_C(19), // MTLO_DSP
2248 UINT64_C(12412), // MTLO_DSP_MM
2249 UINT64_C(15740), // MTLO_MM
2250 UINT64_C(1879048200), // MTM0
2251 UINT64_C(1879048204), // MTM1
2252 UINT64_C(1879048205), // MTM2
2253 UINT64_C(1879048201), // MTP0
2254 UINT64_C(1879048202), // MTP1
2255 UINT64_C(1879048203), // MTP2
2256 UINT64_C(1098907648), // MTTR
2257 UINT64_C(216), // MUH
2258 UINT64_C(217), // MUHU
2259 UINT64_C(216), // MUHU_MMR6
2260 UINT64_C(88), // MUH_MMR6
2261 UINT64_C(1879048194), // MUL
2262 UINT64_C(2080376592), // MULEQ_S_W_PHL
2263 UINT64_C(37), // MULEQ_S_W_PHL_MM
2264 UINT64_C(2080376656), // MULEQ_S_W_PHR
2265 UINT64_C(101), // MULEQ_S_W_PHR_MM
2266 UINT64_C(2080375184), // MULEU_S_PH_QBL
2267 UINT64_C(149), // MULEU_S_PH_QBL_MM
2268 UINT64_C(2080375248), // MULEU_S_PH_QBR
2269 UINT64_C(213), // MULEU_S_PH_QBR_MM
2270 UINT64_C(2080376784), // MULQ_RS_PH
2271 UINT64_C(277), // MULQ_RS_PH_MM
2272 UINT64_C(2080376280), // MULQ_RS_W
2273 UINT64_C(405), // MULQ_RS_W_MMR2
2274 UINT64_C(2080376720), // MULQ_S_PH
2275 UINT64_C(341), // MULQ_S_PH_MMR2
2276 UINT64_C(2080376216), // MULQ_S_W
2277 UINT64_C(469), // MULQ_S_W_MMR2
2278 UINT64_C(1186988058), // MULR_PS64
2279 UINT64_C(2063597596), // MULR_Q_H
2280 UINT64_C(2065694748), // MULR_Q_W
2281 UINT64_C(2080375216), // MULSAQ_S_W_PH
2282 UINT64_C(15548), // MULSAQ_S_W_PH_MM
2283 UINT64_C(2080374960), // MULSA_W_PH
2284 UINT64_C(11452), // MULSA_W_PH_MMR2
2285 UINT64_C(24), // MULT
2286 UINT64_C(25), // MULTU_DSP
2287 UINT64_C(7356), // MULTU_DSP_MM
2288 UINT64_C(24), // MULT_DSP
2289 UINT64_C(3260), // MULT_DSP_MM
2290 UINT64_C(35644), // MULT_MM
2291 UINT64_C(25), // MULTu
2292 UINT64_C(39740), // MULTu_MM
2293 UINT64_C(153), // MULU
2294 UINT64_C(152), // MULU_MMR6
2295 UINT64_C(2013265938), // MULV_B
2296 UINT64_C(2019557394), // MULV_D
2297 UINT64_C(2015363090), // MULV_H
2298 UINT64_C(2017460242), // MULV_W
2299 UINT64_C(528), // MUL_MM
2300 UINT64_C(24), // MUL_MMR6
2301 UINT64_C(2080375576), // MUL_PH
2302 UINT64_C(45), // MUL_PH_MMR2
2303 UINT64_C(2030043164), // MUL_Q_H
2304 UINT64_C(2032140316), // MUL_Q_W
2305 UINT64_C(152), // MUL_R6
2306 UINT64_C(2080375704), // MUL_S_PH
2307 UINT64_C(1069), // MUL_S_PH_MMR2
2308 UINT64_C(59408), // Mfhi16
2309 UINT64_C(59410), // Mflo16
2310 UINT64_C(25856), // Move32R16
2311 UINT64_C(26368), // MoveR3216
2312 UINT64_C(68157440), // NAL
2313 UINT64_C(2064121886), // NLOC_B
2314 UINT64_C(2064318494), // NLOC_D
2315 UINT64_C(2064187422), // NLOC_H
2316 UINT64_C(2064252958), // NLOC_W
2317 UINT64_C(2064384030), // NLZC_B
2318 UINT64_C(2064580638), // NLZC_D
2319 UINT64_C(2064449566), // NLZC_H
2320 UINT64_C(2064515102), // NLZC_W
2321 UINT64_C(1275068465), // NMADD_D32
2322 UINT64_C(1409286154), // NMADD_D32_MM
2323 UINT64_C(1275068465), // NMADD_D64
2324 UINT64_C(1275068464), // NMADD_S
2325 UINT64_C(1409286146), // NMADD_S_MM
2326 UINT64_C(1275068473), // NMSUB_D32
2327 UINT64_C(1409286186), // NMSUB_D32_MM
2328 UINT64_C(1275068473), // NMSUB_D64
2329 UINT64_C(1275068472), // NMSUB_S
2330 UINT64_C(1409286178), // NMSUB_S_MM
2331 UINT64_C(39), // NOR
2332 UINT64_C(39), // NOR64
2333 UINT64_C(2046820352), // NORI_B
2334 UINT64_C(720), // NOR_MM
2335 UINT64_C(720), // NOR_MMR6
2336 UINT64_C(2017460254), // NOR_V
2337 UINT64_C(17408), // NOT16_MM
2338 UINT64_C(17408), // NOT16_MMR6
2339 UINT64_C(59421), // NegRxRy16
2340 UINT64_C(59407), // NotRxRy16
2341 UINT64_C(37), // OR
2342 UINT64_C(17600), // OR16_MM
2343 UINT64_C(17417), // OR16_MMR6
2344 UINT64_C(37), // OR64
2345 UINT64_C(2030043136), // ORI_B
2346 UINT64_C(1342177280), // ORI_MMR6
2347 UINT64_C(656), // OR_MM
2348 UINT64_C(656), // OR_MMR6
2349 UINT64_C(2015363102), // OR_V
2350 UINT64_C(872415232), // ORi
2351 UINT64_C(872415232), // ORi64
2352 UINT64_C(1342177280), // ORi_MM
2353 UINT64_C(59405), // OrRxRxRy16
2354 UINT64_C(2080375697), // PACKRL_PH
2355 UINT64_C(429), // PACKRL_PH_MM
2356 UINT64_C(320), // PAUSE
2357 UINT64_C(10240), // PAUSE_MM
2358 UINT64_C(10240), // PAUSE_MMR6
2359 UINT64_C(2030043156), // PCKEV_B
2360 UINT64_C(2036334612), // PCKEV_D
2361 UINT64_C(2032140308), // PCKEV_H
2362 UINT64_C(2034237460), // PCKEV_W
2363 UINT64_C(2038431764), // PCKOD_B
2364 UINT64_C(2044723220), // PCKOD_D
2365 UINT64_C(2040528916), // PCKOD_H
2366 UINT64_C(2042626068), // PCKOD_W
2367 UINT64_C(2063859742), // PCNT_B
2368 UINT64_C(2064056350), // PCNT_D
2369 UINT64_C(2063925278), // PCNT_H
2370 UINT64_C(2063990814), // PCNT_W
2371 UINT64_C(2080375505), // PICK_PH
2372 UINT64_C(557), // PICK_PH_MM
2373 UINT64_C(2080374993), // PICK_QB
2374 UINT64_C(493), // PICK_QB_MM
2375 UINT64_C(1186988076), // PLL_PS64
2376 UINT64_C(1186988077), // PLU_PS64
2377 UINT64_C(1879048236), // POP
2378 UINT64_C(2080375058), // PRECEQU_PH_QBL
2379 UINT64_C(2080375186), // PRECEQU_PH_QBLA
2380 UINT64_C(29500), // PRECEQU_PH_QBLA_MM
2381 UINT64_C(28988), // PRECEQU_PH_QBL_MM
2382 UINT64_C(2080375122), // PRECEQU_PH_QBR
2383 UINT64_C(2080375250), // PRECEQU_PH_QBRA
2384 UINT64_C(37692), // PRECEQU_PH_QBRA_MM
2385 UINT64_C(37180), // PRECEQU_PH_QBR_MM
2386 UINT64_C(2080375570), // PRECEQ_W_PHL
2387 UINT64_C(20796), // PRECEQ_W_PHL_MM
2388 UINT64_C(2080375634), // PRECEQ_W_PHR
2389 UINT64_C(24892), // PRECEQ_W_PHR_MM
2390 UINT64_C(2080376594), // PRECEU_PH_QBL
2391 UINT64_C(2080376722), // PRECEU_PH_QBLA
2392 UINT64_C(45884), // PRECEU_PH_QBLA_MM
2393 UINT64_C(45372), // PRECEU_PH_QBL_MM
2394 UINT64_C(2080376658), // PRECEU_PH_QBR
2395 UINT64_C(2080376786), // PRECEU_PH_QBRA
2396 UINT64_C(54076), // PRECEU_PH_QBRA_MM
2397 UINT64_C(53564), // PRECEU_PH_QBR_MM
2398 UINT64_C(2080375761), // PRECRQU_S_QB_PH
2399 UINT64_C(365), // PRECRQU_S_QB_PH_MM
2400 UINT64_C(2080376081), // PRECRQ_PH_W
2401 UINT64_C(237), // PRECRQ_PH_W_MM
2402 UINT64_C(2080375569), // PRECRQ_QB_PH
2403 UINT64_C(173), // PRECRQ_QB_PH_MM
2404 UINT64_C(2080376145), // PRECRQ_RS_PH_W
2405 UINT64_C(301), // PRECRQ_RS_PH_W_MM
2406 UINT64_C(2080375633), // PRECR_QB_PH
2407 UINT64_C(109), // PRECR_QB_PH_MMR2
2408 UINT64_C(2080376721), // PRECR_SRA_PH_W
2409 UINT64_C(973), // PRECR_SRA_PH_W_MMR2
2410 UINT64_C(2080376785), // PRECR_SRA_R_PH_W
2411 UINT64_C(1997), // PRECR_SRA_R_PH_W_MMR2
2412 UINT64_C(3422552064), // PREF
2413 UINT64_C(2080374819), // PREFE
2414 UINT64_C(1610654720), // PREFE_MM
2415 UINT64_C(1409286560), // PREFX_MM
2416 UINT64_C(1610620928), // PREF_MM
2417 UINT64_C(1610620928), // PREF_MMR6
2418 UINT64_C(2080374837), // PREF_R6
2419 UINT64_C(2080374897), // PREPEND
2420 UINT64_C(597), // PREPEND_MMR2
2421 UINT64_C(1186988078), // PUL_PS64
2422 UINT64_C(1186988079), // PUU_PS64
2423 UINT64_C(2080376080), // RADDU_W_QB
2424 UINT64_C(61756), // RADDU_W_QB_MM
2425 UINT64_C(2080375992), // RDDSP
2426 UINT64_C(1660), // RDDSP_MM
2427 UINT64_C(2080374843), // RDHWR
2428 UINT64_C(2080374843), // RDHWR64
2429 UINT64_C(27452), // RDHWR_MM
2430 UINT64_C(448), // RDHWR_MMR6
2431 UINT64_C(57724), // RDPGPR_MMR6
2432 UINT64_C(1176502293), // RECIP_D32
2433 UINT64_C(1409307195), // RECIP_D32_MM
2434 UINT64_C(1176502293), // RECIP_D64
2435 UINT64_C(1409307195), // RECIP_D64_MM
2436 UINT64_C(1174405141), // RECIP_S
2437 UINT64_C(1409290811), // RECIP_S_MM
2438 UINT64_C(2080375506), // REPLV_PH
2439 UINT64_C(828), // REPLV_PH_MM
2440 UINT64_C(2080374994), // REPLV_QB
2441 UINT64_C(4924), // REPLV_QB_MM
2442 UINT64_C(2080375442), // REPL_PH
2443 UINT64_C(61), // REPL_PH_MM
2444 UINT64_C(2080374930), // REPL_QB
2445 UINT64_C(1532), // REPL_QB_MM
2446 UINT64_C(1176502298), // RINT_D
2447 UINT64_C(1409286688), // RINT_D_MMR6
2448 UINT64_C(1174405146), // RINT_S
2449 UINT64_C(1409286176), // RINT_S_MMR6
2450 UINT64_C(2097154), // ROTR
2451 UINT64_C(70), // ROTRV
2452 UINT64_C(208), // ROTRV_MM
2453 UINT64_C(192), // ROTR_MM
2454 UINT64_C(1176502280), // ROUND_L_D64
2455 UINT64_C(1409315643), // ROUND_L_D_MMR6
2456 UINT64_C(1174405128), // ROUND_L_S
2457 UINT64_C(1409299259), // ROUND_L_S_MMR6
2458 UINT64_C(1176502284), // ROUND_W_D32
2459 UINT64_C(1176502284), // ROUND_W_D64
2460 UINT64_C(1409317691), // ROUND_W_D_MMR6
2461 UINT64_C(1409317691), // ROUND_W_MM
2462 UINT64_C(1174405132), // ROUND_W_S
2463 UINT64_C(1409301307), // ROUND_W_S_MM
2464 UINT64_C(1409301307), // ROUND_W_S_MMR6
2465 UINT64_C(1176502294), // RSQRT_D32
2466 UINT64_C(1409303099), // RSQRT_D32_MM
2467 UINT64_C(1176502294), // RSQRT_D64
2468 UINT64_C(1409303099), // RSQRT_D64_MM
2469 UINT64_C(1174405142), // RSQRT_S
2470 UINT64_C(1409286715), // RSQRT_S_MM
2471 UINT64_C(25728), // Restore16
2472 UINT64_C(25728), // RestoreX16
2473 UINT64_C(1879048216), // SAA
2474 UINT64_C(1879048217), // SAAD
2475 UINT64_C(2020605962), // SAT_S_B
2476 UINT64_C(2013265930), // SAT_S_D
2477 UINT64_C(2019557386), // SAT_S_H
2478 UINT64_C(2017460234), // SAT_S_W
2479 UINT64_C(2028994570), // SAT_U_B
2480 UINT64_C(2021654538), // SAT_U_D
2481 UINT64_C(2027945994), // SAT_U_H
2482 UINT64_C(2025848842), // SAT_U_W
2483 UINT64_C(2684354560), // SB
2484 UINT64_C(34816), // SB16_MM
2485 UINT64_C(34816), // SB16_MMR6
2486 UINT64_C(2684354560), // SB64
2487 UINT64_C(2080374812), // SBE
2488 UINT64_C(1610655744), // SBE_MM
2489 UINT64_C(402653184), // SB_MM
2490 UINT64_C(402653184), // SB_MMR6
2491 UINT64_C(3758096384), // SC
2492 UINT64_C(3758096384), // SC64
2493 UINT64_C(2080374822), // SC64_R6
2494 UINT64_C(4026531840), // SCD
2495 UINT64_C(2080374823), // SCD_R6
2496 UINT64_C(2080374814), // SCE
2497 UINT64_C(1610656768), // SCE_MM
2498 UINT64_C(1610657792), // SC_MM
2499 UINT64_C(1610657792), // SC_MMR6
2500 UINT64_C(2080374822), // SC_R6
2501 UINT64_C(4227858432), // SD
2502 UINT64_C(1879048255), // SDBBP
2503 UINT64_C(18112), // SDBBP16_MM
2504 UINT64_C(17467), // SDBBP16_MMR6
2505 UINT64_C(56188), // SDBBP_MM
2506 UINT64_C(56188), // SDBBP_MMR6
2507 UINT64_C(14), // SDBBP_R6
2508 UINT64_C(4093640704), // SDC1
2509 UINT64_C(4093640704), // SDC164
2510 UINT64_C(3087007744), // SDC1_D64_MMR6
2511 UINT64_C(3087007744), // SDC1_MM_D32
2512 UINT64_C(3087007744), // SDC1_MM_D64
2513 UINT64_C(4160749568), // SDC2
2514 UINT64_C(536911872), // SDC2_MMR6
2515 UINT64_C(1239416832), // SDC2_R6
2516 UINT64_C(4227858432), // SDC3
2517 UINT64_C(26), // SDIV
2518 UINT64_C(43836), // SDIV_MM
2519 UINT64_C(2952790016), // SDL
2520 UINT64_C(3019898880), // SDR
2521 UINT64_C(1275068425), // SDXC1
2522 UINT64_C(1275068425), // SDXC164
2523 UINT64_C(2080375840), // SEB
2524 UINT64_C(2080375840), // SEB64
2525 UINT64_C(11068), // SEB_MM
2526 UINT64_C(2080376352), // SEH
2527 UINT64_C(2080376352), // SEH64
2528 UINT64_C(15164), // SEH_MM
2529 UINT64_C(53), // SELEQZ
2530 UINT64_C(53), // SELEQZ64
2531 UINT64_C(1176502292), // SELEQZ_D
2532 UINT64_C(1409286712), // SELEQZ_D_MMR6
2533 UINT64_C(320), // SELEQZ_MMR6
2534 UINT64_C(1174405140), // SELEQZ_S
2535 UINT64_C(1409286200), // SELEQZ_S_MMR6
2536 UINT64_C(55), // SELNEZ
2537 UINT64_C(55), // SELNEZ64
2538 UINT64_C(1176502295), // SELNEZ_D
2539 UINT64_C(1409286776), // SELNEZ_D_MMR6
2540 UINT64_C(384), // SELNEZ_MMR6
2541 UINT64_C(1174405143), // SELNEZ_S
2542 UINT64_C(1409286264), // SELNEZ_S_MMR6
2543 UINT64_C(1176502288), // SEL_D
2544 UINT64_C(1409286840), // SEL_D_MMR6
2545 UINT64_C(1174405136), // SEL_S
2546 UINT64_C(1409286328), // SEL_S_MMR6
2547 UINT64_C(1879048234), // SEQ
2548 UINT64_C(1879048238), // SEQi
2549 UINT64_C(2751463424), // SH
2550 UINT64_C(43008), // SH16_MM
2551 UINT64_C(43008), // SH16_MMR6
2552 UINT64_C(2751463424), // SH64
2553 UINT64_C(2080374813), // SHE
2554 UINT64_C(1610656256), // SHE_MM
2555 UINT64_C(2013265922), // SHF_B
2556 UINT64_C(2030043138), // SHF_H
2557 UINT64_C(2046820354), // SHF_W
2558 UINT64_C(2080376504), // SHILO
2559 UINT64_C(2080376568), // SHILOV
2560 UINT64_C(4732), // SHILOV_MM
2561 UINT64_C(29), // SHILO_MM
2562 UINT64_C(2080375443), // SHLLV_PH
2563 UINT64_C(14), // SHLLV_PH_MM
2564 UINT64_C(2080374931), // SHLLV_QB
2565 UINT64_C(917), // SHLLV_QB_MM
2566 UINT64_C(2080375699), // SHLLV_S_PH
2567 UINT64_C(1038), // SHLLV_S_PH_MM
2568 UINT64_C(2080376211), // SHLLV_S_W
2569 UINT64_C(981), // SHLLV_S_W_MM
2570 UINT64_C(2080375315), // SHLL_PH
2571 UINT64_C(949), // SHLL_PH_MM
2572 UINT64_C(2080374803), // SHLL_QB
2573 UINT64_C(2172), // SHLL_QB_MM
2574 UINT64_C(2080375571), // SHLL_S_PH
2575 UINT64_C(2997), // SHLL_S_PH_MM
2576 UINT64_C(2080376083), // SHLL_S_W
2577 UINT64_C(1013), // SHLL_S_W_MM
2578 UINT64_C(2080375507), // SHRAV_PH
2579 UINT64_C(397), // SHRAV_PH_MM
2580 UINT64_C(2080375187), // SHRAV_QB
2581 UINT64_C(461), // SHRAV_QB_MMR2
2582 UINT64_C(2080375763), // SHRAV_R_PH
2583 UINT64_C(1421), // SHRAV_R_PH_MM
2584 UINT64_C(2080375251), // SHRAV_R_QB
2585 UINT64_C(1485), // SHRAV_R_QB_MMR2
2586 UINT64_C(2080376275), // SHRAV_R_W
2587 UINT64_C(725), // SHRAV_R_W_MM
2588 UINT64_C(2080375379), // SHRA_PH
2589 UINT64_C(821), // SHRA_PH_MM
2590 UINT64_C(2080375059), // SHRA_QB
2591 UINT64_C(508), // SHRA_QB_MMR2
2592 UINT64_C(2080375635), // SHRA_R_PH
2593 UINT64_C(1845), // SHRA_R_PH_MM
2594 UINT64_C(2080375123), // SHRA_R_QB
2595 UINT64_C(4604), // SHRA_R_QB_MMR2
2596 UINT64_C(2080376147), // SHRA_R_W
2597 UINT64_C(757), // SHRA_R_W_MM
2598 UINT64_C(2080376531), // SHRLV_PH
2599 UINT64_C(789), // SHRLV_PH_MMR2
2600 UINT64_C(2080374995), // SHRLV_QB
2601 UINT64_C(853), // SHRLV_QB_MM
2602 UINT64_C(2080376403), // SHRL_PH
2603 UINT64_C(1020), // SHRL_PH_MMR2
2604 UINT64_C(2080374867), // SHRL_QB
2605 UINT64_C(6268), // SHRL_QB_MM
2606 UINT64_C(939524096), // SH_MM
2607 UINT64_C(939524096), // SH_MMR6
2608 UINT64_C(68616192), // SIGRIE
2609 UINT64_C(63), // SIGRIE_MMR6
2610 UINT64_C(2013265945), // SLDI_B
2611 UINT64_C(2016935961), // SLDI_D
2612 UINT64_C(2015363097), // SLDI_H
2613 UINT64_C(2016411673), // SLDI_W
2614 UINT64_C(2013265940), // SLD_B
2615 UINT64_C(2019557396), // SLD_D
2616 UINT64_C(2015363092), // SLD_H
2617 UINT64_C(2017460244), // SLD_W
2618 UINT64_C(0), // SLL
2619 UINT64_C(9216), // SLL16_MM
2620 UINT64_C(9216), // SLL16_MMR6
2621 UINT64_C(0), // SLL64_32
2622 UINT64_C(0), // SLL64_64
2623 UINT64_C(2020605961), // SLLI_B
2624 UINT64_C(2013265929), // SLLI_D
2625 UINT64_C(2019557385), // SLLI_H
2626 UINT64_C(2017460233), // SLLI_W
2627 UINT64_C(4), // SLLV
2628 UINT64_C(16), // SLLV_MM
2629 UINT64_C(2013265933), // SLL_B
2630 UINT64_C(2019557389), // SLL_D
2631 UINT64_C(2015363085), // SLL_H
2632 UINT64_C(0), // SLL_MM
2633 UINT64_C(0), // SLL_MMR6
2634 UINT64_C(2017460237), // SLL_W
2635 UINT64_C(42), // SLT
2636 UINT64_C(42), // SLT64
2637 UINT64_C(848), // SLT_MM
2638 UINT64_C(671088640), // SLTi
2639 UINT64_C(671088640), // SLTi64
2640 UINT64_C(2415919104), // SLTi_MM
2641 UINT64_C(738197504), // SLTiu
2642 UINT64_C(738197504), // SLTiu64
2643 UINT64_C(2952790016), // SLTiu_MM
2644 UINT64_C(43), // SLTu
2645 UINT64_C(43), // SLTu64
2646 UINT64_C(912), // SLTu_MM
2647 UINT64_C(1879048235), // SNE
2648 UINT64_C(1879048239), // SNEi
2649 UINT64_C(2017460249), // SPLATI_B
2650 UINT64_C(2021130265), // SPLATI_D
2651 UINT64_C(2019557401), // SPLATI_H
2652 UINT64_C(2020605977), // SPLATI_W
2653 UINT64_C(2021654548), // SPLAT_B
2654 UINT64_C(2027946004), // SPLAT_D
2655 UINT64_C(2023751700), // SPLAT_H
2656 UINT64_C(2025848852), // SPLAT_W
2657 UINT64_C(3), // SRA
2658 UINT64_C(2028994569), // SRAI_B
2659 UINT64_C(2021654537), // SRAI_D
2660 UINT64_C(2027945993), // SRAI_H
2661 UINT64_C(2025848841), // SRAI_W
2662 UINT64_C(2037383178), // SRARI_B
2663 UINT64_C(2030043146), // SRARI_D
2664 UINT64_C(2036334602), // SRARI_H
2665 UINT64_C(2034237450), // SRARI_W
2666 UINT64_C(2021654549), // SRAR_B
2667 UINT64_C(2027946005), // SRAR_D
2668 UINT64_C(2023751701), // SRAR_H
2669 UINT64_C(2025848853), // SRAR_W
2670 UINT64_C(7), // SRAV
2671 UINT64_C(144), // SRAV_MM
2672 UINT64_C(2021654541), // SRA_B
2673 UINT64_C(2027945997), // SRA_D
2674 UINT64_C(2023751693), // SRA_H
2675 UINT64_C(128), // SRA_MM
2676 UINT64_C(2025848845), // SRA_W
2677 UINT64_C(2), // SRL
2678 UINT64_C(9217), // SRL16_MM
2679 UINT64_C(9217), // SRL16_MMR6
2680 UINT64_C(2037383177), // SRLI_B
2681 UINT64_C(2030043145), // SRLI_D
2682 UINT64_C(2036334601), // SRLI_H
2683 UINT64_C(2034237449), // SRLI_W
2684 UINT64_C(2045771786), // SRLRI_B
2685 UINT64_C(2038431754), // SRLRI_D
2686 UINT64_C(2044723210), // SRLRI_H
2687 UINT64_C(2042626058), // SRLRI_W
2688 UINT64_C(2030043157), // SRLR_B
2689 UINT64_C(2036334613), // SRLR_D
2690 UINT64_C(2032140309), // SRLR_H
2691 UINT64_C(2034237461), // SRLR_W
2692 UINT64_C(6), // SRLV
2693 UINT64_C(80), // SRLV_MM
2694 UINT64_C(2030043149), // SRL_B
2695 UINT64_C(2036334605), // SRL_D
2696 UINT64_C(2032140301), // SRL_H
2697 UINT64_C(64), // SRL_MM
2698 UINT64_C(2034237453), // SRL_W
2699 UINT64_C(64), // SSNOP
2700 UINT64_C(2048), // SSNOP_MM
2701 UINT64_C(2048), // SSNOP_MMR6
2702 UINT64_C(2013265956), // ST_B
2703 UINT64_C(2013265959), // ST_D
2704 UINT64_C(2013265957), // ST_H
2705 UINT64_C(2013265958), // ST_W
2706 UINT64_C(34), // SUB
2707 UINT64_C(2080375384), // SUBQH_PH
2708 UINT64_C(589), // SUBQH_PH_MMR2
2709 UINT64_C(2080375512), // SUBQH_R_PH
2710 UINT64_C(1613), // SUBQH_R_PH_MMR2
2711 UINT64_C(2080376024), // SUBQH_R_W
2712 UINT64_C(1677), // SUBQH_R_W_MMR2
2713 UINT64_C(2080375896), // SUBQH_W
2714 UINT64_C(653), // SUBQH_W_MMR2
2715 UINT64_C(2080375504), // SUBQ_PH
2716 UINT64_C(525), // SUBQ_PH_MM
2717 UINT64_C(2080375760), // SUBQ_S_PH
2718 UINT64_C(1549), // SUBQ_S_PH_MM
2719 UINT64_C(2080376272), // SUBQ_S_W
2720 UINT64_C(837), // SUBQ_S_W_MM
2721 UINT64_C(2030043153), // SUBSUS_U_B
2722 UINT64_C(2036334609), // SUBSUS_U_D
2723 UINT64_C(2032140305), // SUBSUS_U_H
2724 UINT64_C(2034237457), // SUBSUS_U_W
2725 UINT64_C(2038431761), // SUBSUU_S_B
2726 UINT64_C(2044723217), // SUBSUU_S_D
2727 UINT64_C(2040528913), // SUBSUU_S_H
2728 UINT64_C(2042626065), // SUBSUU_S_W
2729 UINT64_C(2013265937), // SUBS_S_B
2730 UINT64_C(2019557393), // SUBS_S_D
2731 UINT64_C(2015363089), // SUBS_S_H
2732 UINT64_C(2017460241), // SUBS_S_W
2733 UINT64_C(2021654545), // SUBS_U_B
2734 UINT64_C(2027946001), // SUBS_U_D
2735 UINT64_C(2023751697), // SUBS_U_H
2736 UINT64_C(2025848849), // SUBS_U_W
2737 UINT64_C(1025), // SUBU16_MM
2738 UINT64_C(1025), // SUBU16_MMR6
2739 UINT64_C(2080374872), // SUBUH_QB
2740 UINT64_C(845), // SUBUH_QB_MMR2
2741 UINT64_C(2080375000), // SUBUH_R_QB
2742 UINT64_C(1869), // SUBUH_R_QB_MMR2
2743 UINT64_C(464), // SUBU_MMR6
2744 UINT64_C(2080375376), // SUBU_PH
2745 UINT64_C(781), // SUBU_PH_MMR2
2746 UINT64_C(2080374864), // SUBU_QB
2747 UINT64_C(717), // SUBU_QB_MM
2748 UINT64_C(2080375632), // SUBU_S_PH
2749 UINT64_C(1805), // SUBU_S_PH_MMR2
2750 UINT64_C(2080375120), // SUBU_S_QB
2751 UINT64_C(1741), // SUBU_S_QB_MM
2752 UINT64_C(2021654534), // SUBVI_B
2753 UINT64_C(2027945990), // SUBVI_D
2754 UINT64_C(2023751686), // SUBVI_H
2755 UINT64_C(2025848838), // SUBVI_W
2756 UINT64_C(2021654542), // SUBV_B
2757 UINT64_C(2027945998), // SUBV_D
2758 UINT64_C(2023751694), // SUBV_H
2759 UINT64_C(2025848846), // SUBV_W
2760 UINT64_C(400), // SUB_MM
2761 UINT64_C(400), // SUB_MMR6
2762 UINT64_C(35), // SUBu
2763 UINT64_C(464), // SUBu_MM
2764 UINT64_C(1275068429), // SUXC1
2765 UINT64_C(1275068429), // SUXC164
2766 UINT64_C(1409286536), // SUXC1_MM
2767 UINT64_C(2885681152), // SW
2768 UINT64_C(59392), // SW16_MM
2769 UINT64_C(59392), // SW16_MMR6
2770 UINT64_C(2885681152), // SW64
2771 UINT64_C(3825205248), // SWC1
2772 UINT64_C(2550136832), // SWC1_MM
2773 UINT64_C(3892314112), // SWC2
2774 UINT64_C(536903680), // SWC2_MMR6
2775 UINT64_C(1231028224), // SWC2_R6
2776 UINT64_C(3959422976), // SWC3
2777 UINT64_C(2885681152), // SWDSP
2778 UINT64_C(4160749568), // SWDSP_MM
2779 UINT64_C(2080374815), // SWE
2780 UINT64_C(1610657280), // SWE_MM
2781 UINT64_C(2818572288), // SWL
2782 UINT64_C(2818572288), // SWL64
2783 UINT64_C(2080374817), // SWLE
2784 UINT64_C(1610653696), // SWLE_MM
2785 UINT64_C(1610645504), // SWL_MM
2786 UINT64_C(17728), // SWM16_MM
2787 UINT64_C(17418), // SWM16_MMR6
2788 UINT64_C(536924160), // SWM32_MM
2789 UINT64_C(536907776), // SWP_MM
2790 UINT64_C(3087007744), // SWR
2791 UINT64_C(3087007744), // SWR64
2792 UINT64_C(2080374818), // SWRE
2793 UINT64_C(1610654208), // SWRE_MM
2794 UINT64_C(1610649600), // SWR_MM
2795 UINT64_C(51200), // SWSP_MM
2796 UINT64_C(51200), // SWSP_MMR6
2797 UINT64_C(1275068424), // SWXC1
2798 UINT64_C(1409286280), // SWXC1_MM
2799 UINT64_C(4160749568), // SW_MM
2800 UINT64_C(4160749568), // SW_MMR6
2801 UINT64_C(15), // SYNC
2802 UINT64_C(69140480), // SYNCI
2803 UINT64_C(1107296256), // SYNCI_MM
2804 UINT64_C(1098907648), // SYNCI_MMR6
2805 UINT64_C(27516), // SYNC_MM
2806 UINT64_C(27516), // SYNC_MMR6
2807 UINT64_C(12), // SYSCALL
2808 UINT64_C(35708), // SYSCALL_MM
2809 UINT64_C(25728), // Save16
2810 UINT64_C(25728), // SaveX16
2811 UINT64_C(4026580992), // SbRxRyOffMemX16
2812 UINT64_C(59537), // SebRx16
2813 UINT64_C(59569), // SehRx16
2814 UINT64_C(4026583040), // ShRxRyOffMemX16
2815 UINT64_C(4026544128), // SllX16
2816 UINT64_C(59396), // SllvRxRy16
2817 UINT64_C(59394), // SltRxRy16
2818 UINT64_C(20480), // SltiRxImm16
2819 UINT64_C(4026552320), // SltiRxImmX16
2820 UINT64_C(22528), // SltiuRxImm16
2821 UINT64_C(4026554368), // SltiuRxImmX16
2822 UINT64_C(59395), // SltuRxRy16
2823 UINT64_C(4026544131), // SraX16
2824 UINT64_C(59399), // SravRxRy16
2825 UINT64_C(4026544130), // SrlX16
2826 UINT64_C(59398), // SrlvRxRy16
2827 UINT64_C(57347), // SubuRxRyRz16
2828 UINT64_C(4026587136), // SwRxRyOffMemX16
2829 UINT64_C(4026585088), // SwRxSpImmX16
2830 UINT64_C(52), // TEQ
2831 UINT64_C(67895296), // TEQI
2832 UINT64_C(1103101952), // TEQI_MM
2833 UINT64_C(60), // TEQ_MM
2834 UINT64_C(48), // TGE
2835 UINT64_C(67633152), // TGEI
2836 UINT64_C(67698688), // TGEIU
2837 UINT64_C(1096810496), // TGEIU_MM
2838 UINT64_C(1092616192), // TGEI_MM
2839 UINT64_C(49), // TGEU
2840 UINT64_C(1084), // TGEU_MM
2841 UINT64_C(572), // TGE_MM
2842 UINT64_C(1107296267), // TLBGINV
2843 UINT64_C(1107296268), // TLBGINVF
2844 UINT64_C(20860), // TLBGINVF_MM
2845 UINT64_C(16764), // TLBGINV_MM
2846 UINT64_C(1107296272), // TLBGP
2847 UINT64_C(380), // TLBGP_MM
2848 UINT64_C(1107296265), // TLBGR
2849 UINT64_C(4476), // TLBGR_MM
2850 UINT64_C(1107296266), // TLBGWI
2851 UINT64_C(8572), // TLBGWI_MM
2852 UINT64_C(1107296270), // TLBGWR
2853 UINT64_C(12668), // TLBGWR_MM
2854 UINT64_C(1107296259), // TLBINV
2855 UINT64_C(1107296260), // TLBINVF
2856 UINT64_C(21372), // TLBINVF_MMR6
2857 UINT64_C(17276), // TLBINV_MMR6
2858 UINT64_C(1107296264), // TLBP
2859 UINT64_C(892), // TLBP_MM
2860 UINT64_C(1107296257), // TLBR
2861 UINT64_C(4988), // TLBR_MM
2862 UINT64_C(1107296258), // TLBWI
2863 UINT64_C(9084), // TLBWI_MM
2864 UINT64_C(1107296262), // TLBWR
2865 UINT64_C(13180), // TLBWR_MM
2866 UINT64_C(50), // TLT
2867 UINT64_C(67764224), // TLTI
2868 UINT64_C(1094713344), // TLTIU_MM
2869 UINT64_C(1090519040), // TLTI_MM
2870 UINT64_C(51), // TLTU
2871 UINT64_C(2620), // TLTU_MM
2872 UINT64_C(2108), // TLT_MM
2873 UINT64_C(54), // TNE
2874 UINT64_C(68026368), // TNEI
2875 UINT64_C(1098907648), // TNEI_MM
2876 UINT64_C(3132), // TNE_MM
2877 UINT64_C(1176502281), // TRUNC_L_D64
2878 UINT64_C(1409311547), // TRUNC_L_D_MMR6
2879 UINT64_C(1174405129), // TRUNC_L_S
2880 UINT64_C(1409295163), // TRUNC_L_S_MMR6
2881 UINT64_C(1176502285), // TRUNC_W_D32
2882 UINT64_C(1176502285), // TRUNC_W_D64
2883 UINT64_C(1409313595), // TRUNC_W_D_MMR6
2884 UINT64_C(1409313595), // TRUNC_W_MM
2885 UINT64_C(1174405133), // TRUNC_W_S
2886 UINT64_C(1409297211), // TRUNC_W_S_MM
2887 UINT64_C(1409297211), // TRUNC_W_S_MMR6
2888 UINT64_C(67829760), // TTLTIU
2889 UINT64_C(27), // UDIV
2890 UINT64_C(47932), // UDIV_MM
2891 UINT64_C(1879048209), // V3MULU
2892 UINT64_C(1879048208), // VMM0
2893 UINT64_C(1879048207), // VMULU
2894 UINT64_C(2013265941), // VSHF_B
2895 UINT64_C(2019557397), // VSHF_D
2896 UINT64_C(2015363093), // VSHF_H
2897 UINT64_C(2017460245), // VSHF_W
2898 UINT64_C(1107296288), // WAIT
2899 UINT64_C(37756), // WAIT_MM
2900 UINT64_C(37756), // WAIT_MMR6
2901 UINT64_C(2080376056), // WRDSP
2902 UINT64_C(5756), // WRDSP_MM
2903 UINT64_C(61820), // WRPGPR_MMR6
2904 UINT64_C(2080374944), // WSBH
2905 UINT64_C(31548), // WSBH_MM
2906 UINT64_C(31548), // WSBH_MMR6
2907 UINT64_C(38), // XOR
2908 UINT64_C(17472), // XOR16_MM
2909 UINT64_C(17416), // XOR16_MMR6
2910 UINT64_C(38), // XOR64
2911 UINT64_C(2063597568), // XORI_B
2912 UINT64_C(1879048192), // XORI_MMR6
2913 UINT64_C(784), // XOR_MM
2914 UINT64_C(784), // XOR_MMR6
2915 UINT64_C(2019557406), // XOR_V
2916 UINT64_C(939524096), // XORi
2917 UINT64_C(939524096), // XORi64
2918 UINT64_C(1879048192), // XORi_MM
2919 UINT64_C(59406), // XorRxRxRy16
2920 UINT64_C(2080374793), // YIELD
2921 UINT64_C(0)
2922 };
2923 const unsigned opcode = MI.getOpcode();
2924 uint64_t Value = InstBits[opcode];
2925 uint64_t op = 0;
2926 (void)op; // suppress warning
2927 switch (opcode) {
2928 case Mips::Break16:
2929 case Mips::DERET:
2930 case Mips::DERET_MM:
2931 case Mips::DERET_MMR6:
2932 case Mips::EHB:
2933 case Mips::EHB_MM:
2934 case Mips::EHB_MMR6:
2935 case Mips::ERET:
2936 case Mips::ERETNC:
2937 case Mips::ERETNC_MMR6:
2938 case Mips::ERET_MM:
2939 case Mips::ERET_MMR6:
2940 case Mips::JrRa16:
2941 case Mips::JrcRa16:
2942 case Mips::JrcRx16:
2943 case Mips::NAL:
2944 case Mips::PAUSE:
2945 case Mips::PAUSE_MM:
2946 case Mips::PAUSE_MMR6:
2947 case Mips::Restore16:
2948 case Mips::RestoreX16:
2949 case Mips::SSNOP:
2950 case Mips::SSNOP_MM:
2951 case Mips::SSNOP_MMR6:
2952 case Mips::Save16:
2953 case Mips::SaveX16:
2954 case Mips::TLBGINV:
2955 case Mips::TLBGINVF:
2956 case Mips::TLBGINVF_MM:
2957 case Mips::TLBGINV_MM:
2958 case Mips::TLBGP:
2959 case Mips::TLBGP_MM:
2960 case Mips::TLBGR:
2961 case Mips::TLBGR_MM:
2962 case Mips::TLBGWI:
2963 case Mips::TLBGWI_MM:
2964 case Mips::TLBGWR:
2965 case Mips::TLBGWR_MM:
2966 case Mips::TLBINV:
2967 case Mips::TLBINVF:
2968 case Mips::TLBINVF_MMR6:
2969 case Mips::TLBINV_MMR6:
2970 case Mips::TLBP:
2971 case Mips::TLBP_MM:
2972 case Mips::TLBR:
2973 case Mips::TLBR_MM:
2974 case Mips::TLBWI:
2975 case Mips::TLBWI_MM:
2976 case Mips::TLBWR:
2977 case Mips::TLBWR_MM:
2978 case Mips::WAIT: {
2979 break;
2980 }
2981 case Mips::MTHLIP:
2982 case Mips::SHILOV: {
2983 // op: ac
2984 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
2985 op &= UINT64_C(3);
2986 op <<= 11;
2987 Value |= op;
2988 // op: rs
2989 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
2990 op &= UINT64_C(31);
2991 op <<= 21;
2992 Value |= op;
2993 break;
2994 }
2995 case Mips::DPAQX_SA_W_PH:
2996 case Mips::DPAQX_S_W_PH:
2997 case Mips::DPAQ_SA_L_W:
2998 case Mips::DPAQ_S_W_PH:
2999 case Mips::DPAU_H_QBL:
3000 case Mips::DPAU_H_QBR:
3001 case Mips::DPAX_W_PH:
3002 case Mips::DPA_W_PH:
3003 case Mips::DPSQX_SA_W_PH:
3004 case Mips::DPSQX_S_W_PH:
3005 case Mips::DPSQ_SA_L_W:
3006 case Mips::DPSQ_S_W_PH:
3007 case Mips::DPSU_H_QBL:
3008 case Mips::DPSU_H_QBR:
3009 case Mips::DPSX_W_PH:
3010 case Mips::DPS_W_PH:
3011 case Mips::MADDU_DSP:
3012 case Mips::MADD_DSP:
3013 case Mips::MAQ_SA_W_PHL:
3014 case Mips::MAQ_SA_W_PHR:
3015 case Mips::MAQ_S_W_PHL:
3016 case Mips::MAQ_S_W_PHR:
3017 case Mips::MSUBU_DSP:
3018 case Mips::MSUB_DSP:
3019 case Mips::MULSAQ_S_W_PH:
3020 case Mips::MULSA_W_PH:
3021 case Mips::MULTU_DSP:
3022 case Mips::MULT_DSP: {
3023 // op: ac
3024 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3025 op &= UINT64_C(3);
3026 op <<= 11;
3027 Value |= op;
3028 // op: rs
3029 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3030 op &= UINT64_C(31);
3031 op <<= 21;
3032 Value |= op;
3033 // op: rt
3034 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3035 op &= UINT64_C(31);
3036 op <<= 16;
3037 Value |= op;
3038 break;
3039 }
3040 case Mips::SHILO: {
3041 // op: ac
3042 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3043 op &= UINT64_C(3);
3044 op <<= 11;
3045 Value |= op;
3046 // op: shift
3047 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3048 op &= UINT64_C(63);
3049 op <<= 20;
3050 Value |= op;
3051 break;
3052 }
3053 case Mips::CACHEE:
3054 case Mips::CACHE_R6:
3055 case Mips::PREFE:
3056 case Mips::PREF_R6: {
3057 // op: addr
3058 op = getMemEncoding(MI, OpNo: 0, Fixups, STI);
3059 Value |= (op & UINT64_C(2031616)) << 5;
3060 Value |= (op & UINT64_C(511)) << 7;
3061 // op: hint
3062 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3063 op &= UINT64_C(31);
3064 op <<= 16;
3065 Value |= op;
3066 break;
3067 }
3068 case Mips::SYNCI: {
3069 // op: addr
3070 op = getMemEncoding(MI, OpNo: 0, Fixups, STI);
3071 Value |= (op & UINT64_C(2031616)) << 5;
3072 Value |= (op & UINT64_C(65535));
3073 break;
3074 }
3075 case Mips::CACHE:
3076 case Mips::PREF: {
3077 // op: addr
3078 op = getMemEncoding(MI, OpNo: 0, Fixups, STI);
3079 Value |= (op & UINT64_C(2031616)) << 5;
3080 Value |= (op & UINT64_C(65535));
3081 // op: hint
3082 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3083 op &= UINT64_C(31);
3084 op <<= 16;
3085 Value |= op;
3086 break;
3087 }
3088 case Mips::LD_B:
3089 case Mips::ST_B: {
3090 // op: addr
3091 op = getMemEncoding(MI, OpNo: 1, Fixups, STI);
3092 Value |= (op & UINT64_C(1023)) << 16;
3093 Value |= (op & UINT64_C(2031616)) >> 5;
3094 // op: wd
3095 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3096 op &= UINT64_C(31);
3097 op <<= 6;
3098 Value |= op;
3099 break;
3100 }
3101 case Mips::LBE:
3102 case Mips::LBuE:
3103 case Mips::LHE:
3104 case Mips::LHuE:
3105 case Mips::LLE:
3106 case Mips::LWE:
3107 case Mips::LWLE:
3108 case Mips::LWRE:
3109 case Mips::SBE:
3110 case Mips::SHE:
3111 case Mips::SWE:
3112 case Mips::SWLE:
3113 case Mips::SWRE: {
3114 // op: addr
3115 op = getMemEncoding(MI, OpNo: 1, Fixups, STI);
3116 Value |= (op & UINT64_C(2031616)) << 5;
3117 Value |= (op & UINT64_C(511)) << 7;
3118 // op: rt
3119 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3120 op &= UINT64_C(31);
3121 op <<= 16;
3122 Value |= op;
3123 break;
3124 }
3125 case Mips::SCE: {
3126 // op: addr
3127 op = getMemEncoding(MI, OpNo: 2, Fixups, STI);
3128 Value |= (op & UINT64_C(2031616)) << 5;
3129 Value |= (op & UINT64_C(511)) << 7;
3130 // op: rt
3131 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3132 op &= UINT64_C(31);
3133 op <<= 16;
3134 Value |= op;
3135 break;
3136 }
3137 case Mips::LD_H:
3138 case Mips::ST_H: {
3139 // op: addr
3140 op = getMemEncoding<1>(MI, OpNo: 1, Fixups, STI);
3141 Value |= (op & UINT64_C(1023)) << 16;
3142 Value |= (op & UINT64_C(2031616)) >> 5;
3143 // op: wd
3144 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3145 op &= UINT64_C(31);
3146 op <<= 6;
3147 Value |= op;
3148 break;
3149 }
3150 case Mips::LD_W:
3151 case Mips::ST_W: {
3152 // op: addr
3153 op = getMemEncoding<2>(MI, OpNo: 1, Fixups, STI);
3154 Value |= (op & UINT64_C(1023)) << 16;
3155 Value |= (op & UINT64_C(2031616)) >> 5;
3156 // op: wd
3157 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3158 op &= UINT64_C(31);
3159 op <<= 6;
3160 Value |= op;
3161 break;
3162 }
3163 case Mips::LD_D:
3164 case Mips::ST_D: {
3165 // op: addr
3166 op = getMemEncoding<3>(MI, OpNo: 1, Fixups, STI);
3167 Value |= (op & UINT64_C(1023)) << 16;
3168 Value |= (op & UINT64_C(2031616)) >> 5;
3169 // op: wd
3170 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3171 op &= UINT64_C(31);
3172 op <<= 6;
3173 Value |= op;
3174 break;
3175 }
3176 case Mips::CACHE_MM:
3177 case Mips::CACHE_MMR6:
3178 case Mips::PREF_MM:
3179 case Mips::PREF_MMR6: {
3180 // op: addr
3181 op = getMemEncodingMMImm12(MI, OpNo: 0, Fixups, STI);
3182 Value |= (op & UINT64_C(2031616));
3183 Value |= (op & UINT64_C(4095));
3184 // op: hint
3185 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3186 op &= UINT64_C(31);
3187 op <<= 21;
3188 Value |= op;
3189 break;
3190 }
3191 case Mips::SYNCI_MM:
3192 case Mips::SYNCI_MMR6: {
3193 // op: addr
3194 op = getMemEncodingMMImm16(MI, OpNo: 0, Fixups, STI);
3195 op &= UINT64_C(2097151);
3196 Value |= op;
3197 break;
3198 }
3199 case Mips::LBU_MMR6:
3200 case Mips::LB_MMR6: {
3201 // op: addr
3202 op = getMemEncodingMMImm16(MI, OpNo: 1, Fixups, STI);
3203 op &= UINT64_C(2097151);
3204 Value |= op;
3205 // op: rt
3206 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3207 op &= UINT64_C(31);
3208 op <<= 21;
3209 Value |= op;
3210 break;
3211 }
3212 case Mips::CACHEE_MM:
3213 case Mips::PREFE_MM: {
3214 // op: addr
3215 op = getMemEncodingMMImm9(MI, OpNo: 0, Fixups, STI);
3216 Value |= (op & UINT64_C(2031616));
3217 Value |= (op & UINT64_C(511));
3218 // op: hint
3219 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3220 op &= UINT64_C(31);
3221 op <<= 21;
3222 Value |= op;
3223 break;
3224 }
3225 case Mips::HYPCALL: {
3226 // op: code_
3227 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3228 op &= UINT64_C(1023);
3229 op <<= 11;
3230 Value |= op;
3231 break;
3232 }
3233 case Mips::HYPCALL_MM:
3234 case Mips::SDBBP_MM:
3235 case Mips::SDBBP_MMR6:
3236 case Mips::SYSCALL_MM:
3237 case Mips::WAIT_MM:
3238 case Mips::WAIT_MMR6: {
3239 // op: code_
3240 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3241 op &= UINT64_C(1023);
3242 op <<= 16;
3243 Value |= op;
3244 break;
3245 }
3246 case Mips::SDBBP:
3247 case Mips::SDBBP_R6:
3248 case Mips::SYSCALL: {
3249 // op: code_
3250 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3251 op &= UINT64_C(1048575);
3252 op <<= 6;
3253 Value |= op;
3254 break;
3255 }
3256 case Mips::BREAK16_MM:
3257 case Mips::SDBBP16_MM: {
3258 // op: code_
3259 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3260 op &= UINT64_C(15);
3261 Value |= op;
3262 break;
3263 }
3264 case Mips::BREAK16_MMR6:
3265 case Mips::SDBBP16_MMR6: {
3266 // op: code_
3267 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3268 op &= UINT64_C(15);
3269 op <<= 6;
3270 Value |= op;
3271 break;
3272 }
3273 case Mips::SIGRIE: {
3274 // op: code_
3275 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3276 op &= UINT64_C(65535);
3277 Value |= op;
3278 break;
3279 }
3280 case Mips::SIGRIE_MMR6: {
3281 // op: code_
3282 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3283 op &= UINT64_C(65535);
3284 op <<= 6;
3285 Value |= op;
3286 break;
3287 }
3288 case Mips::BREAK:
3289 case Mips::BREAK_MM:
3290 case Mips::BREAK_MMR6: {
3291 // op: code_1
3292 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3293 op &= UINT64_C(1023);
3294 op <<= 16;
3295 Value |= op;
3296 // op: code_2
3297 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3298 op &= UINT64_C(1023);
3299 op <<= 6;
3300 Value |= op;
3301 break;
3302 }
3303 case Mips::BC2EQZ:
3304 case Mips::BC2NEZ: {
3305 // op: ct
3306 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3307 op &= UINT64_C(31);
3308 op <<= 16;
3309 Value |= op;
3310 // op: offset
3311 op = getBranchTargetOpValue(MI, OpNo: 1, Fixups, STI);
3312 op &= UINT64_C(65535);
3313 Value |= op;
3314 break;
3315 }
3316 case Mips::BC1F:
3317 case Mips::BC1FL:
3318 case Mips::BC1T:
3319 case Mips::BC1TL: {
3320 // op: fcc
3321 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3322 op &= UINT64_C(7);
3323 op <<= 18;
3324 Value |= op;
3325 // op: offset
3326 op = getBranchTargetOpValue(MI, OpNo: 1, Fixups, STI);
3327 op &= UINT64_C(65535);
3328 Value |= op;
3329 break;
3330 }
3331 case Mips::BC1F_MM:
3332 case Mips::BC1T_MM: {
3333 // op: fcc
3334 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3335 op &= UINT64_C(7);
3336 op <<= 18;
3337 Value |= op;
3338 // op: offset
3339 op = getBranchTargetOpValueMM(MI, OpNo: 1, Fixups, STI);
3340 op &= UINT64_C(65535);
3341 Value |= op;
3342 break;
3343 }
3344 case Mips::LUXC1_MM:
3345 case Mips::LWXC1_MM: {
3346 // op: fd
3347 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3348 op &= UINT64_C(31);
3349 op <<= 11;
3350 Value |= op;
3351 // op: base
3352 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3353 op &= UINT64_C(31);
3354 op <<= 16;
3355 Value |= op;
3356 // op: index
3357 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3358 op &= UINT64_C(31);
3359 op <<= 21;
3360 Value |= op;
3361 break;
3362 }
3363 case Mips::MOVN_I_D32_MM:
3364 case Mips::MOVN_I_S_MM:
3365 case Mips::MOVZ_I_D32_MM:
3366 case Mips::MOVZ_I_S_MM: {
3367 // op: fd
3368 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3369 op &= UINT64_C(31);
3370 op <<= 11;
3371 Value |= op;
3372 // op: fs
3373 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3374 op &= UINT64_C(31);
3375 op <<= 16;
3376 Value |= op;
3377 // op: rt
3378 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3379 op &= UINT64_C(31);
3380 op <<= 21;
3381 Value |= op;
3382 break;
3383 }
3384 case Mips::CEIL_W_MM:
3385 case Mips::CEIL_W_S_MM:
3386 case Mips::CVT_D32_S_MM:
3387 case Mips::CVT_D32_W_MM:
3388 case Mips::CVT_D64_S_MM:
3389 case Mips::CVT_D64_W_MM:
3390 case Mips::CVT_L_D64_MM:
3391 case Mips::CVT_L_S_MM:
3392 case Mips::CVT_S_D32_MM:
3393 case Mips::CVT_S_D64_MM:
3394 case Mips::CVT_S_W_MM:
3395 case Mips::CVT_W_D32_MM:
3396 case Mips::CVT_W_D64_MM:
3397 case Mips::CVT_W_S_MM:
3398 case Mips::FABS_D32_MM:
3399 case Mips::FABS_D64_MM:
3400 case Mips::FABS_S_MM:
3401 case Mips::FLOOR_W_MM:
3402 case Mips::FLOOR_W_S_MM:
3403 case Mips::FMOV_D32_MM:
3404 case Mips::FMOV_D64_MM:
3405 case Mips::FMOV_S_MM:
3406 case Mips::FNEG_D32_MM:
3407 case Mips::FNEG_D64_MM:
3408 case Mips::FNEG_S_MM:
3409 case Mips::FSQRT_D32_MM:
3410 case Mips::FSQRT_D64_MM:
3411 case Mips::FSQRT_S_MM:
3412 case Mips::RECIP_D32_MM:
3413 case Mips::RECIP_D64_MM:
3414 case Mips::RECIP_S_MM:
3415 case Mips::ROUND_W_MM:
3416 case Mips::ROUND_W_S_MM:
3417 case Mips::RSQRT_D32_MM:
3418 case Mips::RSQRT_D64_MM:
3419 case Mips::RSQRT_S_MM:
3420 case Mips::TRUNC_W_MM:
3421 case Mips::TRUNC_W_S_MM: {
3422 // op: fd
3423 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3424 op &= UINT64_C(31);
3425 op <<= 21;
3426 Value |= op;
3427 // op: fs
3428 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3429 op &= UINT64_C(31);
3430 op <<= 16;
3431 Value |= op;
3432 break;
3433 }
3434 case Mips::MOVF_D32_MM:
3435 case Mips::MOVF_S_MM:
3436 case Mips::MOVT_D32_MM:
3437 case Mips::MOVT_S_MM: {
3438 // op: fd
3439 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3440 op &= UINT64_C(31);
3441 op <<= 21;
3442 Value |= op;
3443 // op: fs
3444 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3445 op &= UINT64_C(31);
3446 op <<= 16;
3447 Value |= op;
3448 // op: fcc
3449 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3450 op &= UINT64_C(7);
3451 op <<= 13;
3452 Value |= op;
3453 break;
3454 }
3455 case Mips::LDXC1:
3456 case Mips::LDXC164:
3457 case Mips::LUXC1:
3458 case Mips::LUXC164:
3459 case Mips::LWXC1: {
3460 // op: fd
3461 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3462 op &= UINT64_C(31);
3463 op <<= 6;
3464 Value |= op;
3465 // op: base
3466 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3467 op &= UINT64_C(31);
3468 op <<= 21;
3469 Value |= op;
3470 // op: index
3471 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3472 op &= UINT64_C(31);
3473 op <<= 16;
3474 Value |= op;
3475 break;
3476 }
3477 case Mips::MADD_D32:
3478 case Mips::MADD_D64:
3479 case Mips::MADD_S:
3480 case Mips::MSUB_D32:
3481 case Mips::MSUB_D64:
3482 case Mips::MSUB_S:
3483 case Mips::NMADD_D32:
3484 case Mips::NMADD_D64:
3485 case Mips::NMADD_S:
3486 case Mips::NMSUB_D32:
3487 case Mips::NMSUB_D64:
3488 case Mips::NMSUB_S: {
3489 // op: fd
3490 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3491 op &= UINT64_C(31);
3492 op <<= 6;
3493 Value |= op;
3494 // op: fr
3495 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3496 op &= UINT64_C(31);
3497 op <<= 21;
3498 Value |= op;
3499 // op: fs
3500 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3501 op &= UINT64_C(31);
3502 op <<= 11;
3503 Value |= op;
3504 // op: ft
3505 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
3506 op &= UINT64_C(31);
3507 op <<= 16;
3508 Value |= op;
3509 break;
3510 }
3511 case Mips::CEIL_L_D64:
3512 case Mips::CEIL_L_S:
3513 case Mips::CEIL_W_D32:
3514 case Mips::CEIL_W_D64:
3515 case Mips::CEIL_W_S:
3516 case Mips::CVT_D32_S:
3517 case Mips::CVT_D32_W:
3518 case Mips::CVT_D64_L:
3519 case Mips::CVT_D64_S:
3520 case Mips::CVT_D64_W:
3521 case Mips::CVT_L_D64:
3522 case Mips::CVT_L_S:
3523 case Mips::CVT_PS_PW64:
3524 case Mips::CVT_PW_PS64:
3525 case Mips::CVT_S_D32:
3526 case Mips::CVT_S_D64:
3527 case Mips::CVT_S_L:
3528 case Mips::CVT_S_PL64:
3529 case Mips::CVT_S_PU64:
3530 case Mips::CVT_S_W:
3531 case Mips::CVT_W_D32:
3532 case Mips::CVT_W_D64:
3533 case Mips::CVT_W_S:
3534 case Mips::FABS_D32:
3535 case Mips::FABS_D64:
3536 case Mips::FABS_S:
3537 case Mips::FLOOR_L_D64:
3538 case Mips::FLOOR_L_S:
3539 case Mips::FLOOR_W_D32:
3540 case Mips::FLOOR_W_D64:
3541 case Mips::FLOOR_W_S:
3542 case Mips::FMOV_D32:
3543 case Mips::FMOV_D64:
3544 case Mips::FMOV_S:
3545 case Mips::FNEG_D32:
3546 case Mips::FNEG_D64:
3547 case Mips::FNEG_S:
3548 case Mips::FSQRT_D32:
3549 case Mips::FSQRT_D64:
3550 case Mips::FSQRT_S:
3551 case Mips::RECIP_D32:
3552 case Mips::RECIP_D64:
3553 case Mips::RECIP_S:
3554 case Mips::ROUND_L_D64:
3555 case Mips::ROUND_L_S:
3556 case Mips::ROUND_W_D32:
3557 case Mips::ROUND_W_D64:
3558 case Mips::ROUND_W_S:
3559 case Mips::RSQRT_D32:
3560 case Mips::RSQRT_D64:
3561 case Mips::RSQRT_S:
3562 case Mips::TRUNC_L_D64:
3563 case Mips::TRUNC_L_S:
3564 case Mips::TRUNC_W_D32:
3565 case Mips::TRUNC_W_D64:
3566 case Mips::TRUNC_W_S: {
3567 // op: fd
3568 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3569 op &= UINT64_C(31);
3570 op <<= 6;
3571 Value |= op;
3572 // op: fs
3573 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3574 op &= UINT64_C(31);
3575 op <<= 11;
3576 Value |= op;
3577 break;
3578 }
3579 case Mips::MOVF_D32:
3580 case Mips::MOVF_D64:
3581 case Mips::MOVF_S:
3582 case Mips::MOVT_D32:
3583 case Mips::MOVT_D64:
3584 case Mips::MOVT_S: {
3585 // op: fd
3586 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3587 op &= UINT64_C(31);
3588 op <<= 6;
3589 Value |= op;
3590 // op: fs
3591 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3592 op &= UINT64_C(31);
3593 op <<= 11;
3594 Value |= op;
3595 // op: fcc
3596 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3597 op &= UINT64_C(7);
3598 op <<= 18;
3599 Value |= op;
3600 break;
3601 }
3602 case Mips::ADDR_PS64:
3603 case Mips::CMP_EQ_D:
3604 case Mips::CMP_EQ_S:
3605 case Mips::CMP_F_D:
3606 case Mips::CMP_F_S:
3607 case Mips::CMP_LE_D:
3608 case Mips::CMP_LE_S:
3609 case Mips::CMP_LT_D:
3610 case Mips::CMP_LT_S:
3611 case Mips::CMP_SAF_D:
3612 case Mips::CMP_SAF_S:
3613 case Mips::CMP_SEQ_D:
3614 case Mips::CMP_SEQ_S:
3615 case Mips::CMP_SLE_D:
3616 case Mips::CMP_SLE_S:
3617 case Mips::CMP_SLT_D:
3618 case Mips::CMP_SLT_S:
3619 case Mips::CMP_SUEQ_D:
3620 case Mips::CMP_SUEQ_S:
3621 case Mips::CMP_SULE_D:
3622 case Mips::CMP_SULE_S:
3623 case Mips::CMP_SULT_D:
3624 case Mips::CMP_SULT_S:
3625 case Mips::CMP_SUN_D:
3626 case Mips::CMP_SUN_S:
3627 case Mips::CMP_UEQ_D:
3628 case Mips::CMP_UEQ_S:
3629 case Mips::CMP_ULE_D:
3630 case Mips::CMP_ULE_S:
3631 case Mips::CMP_ULT_D:
3632 case Mips::CMP_ULT_S:
3633 case Mips::CMP_UN_D:
3634 case Mips::CMP_UN_S:
3635 case Mips::CVT_PS_S64:
3636 case Mips::FADD_D32:
3637 case Mips::FADD_D64:
3638 case Mips::FADD_PS64:
3639 case Mips::FADD_S:
3640 case Mips::FDIV_D32:
3641 case Mips::FDIV_D64:
3642 case Mips::FDIV_S:
3643 case Mips::FMUL_D32:
3644 case Mips::FMUL_D64:
3645 case Mips::FMUL_PS64:
3646 case Mips::FMUL_S:
3647 case Mips::FSUB_D32:
3648 case Mips::FSUB_D64:
3649 case Mips::FSUB_PS64:
3650 case Mips::FSUB_S:
3651 case Mips::MULR_PS64:
3652 case Mips::PLL_PS64:
3653 case Mips::PLU_PS64:
3654 case Mips::PUL_PS64:
3655 case Mips::PUU_PS64: {
3656 // op: fd
3657 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3658 op &= UINT64_C(31);
3659 op <<= 6;
3660 Value |= op;
3661 // op: fs
3662 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3663 op &= UINT64_C(31);
3664 op <<= 11;
3665 Value |= op;
3666 // op: ft
3667 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3668 op &= UINT64_C(31);
3669 op <<= 16;
3670 Value |= op;
3671 break;
3672 }
3673 case Mips::MOVN_I64_D64:
3674 case Mips::MOVN_I64_S:
3675 case Mips::MOVN_I_D32:
3676 case Mips::MOVN_I_D64:
3677 case Mips::MOVN_I_S:
3678 case Mips::MOVZ_I64_D64:
3679 case Mips::MOVZ_I64_S:
3680 case Mips::MOVZ_I_D32:
3681 case Mips::MOVZ_I_D64:
3682 case Mips::MOVZ_I_S: {
3683 // op: fd
3684 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3685 op &= UINT64_C(31);
3686 op <<= 6;
3687 Value |= op;
3688 // op: fs
3689 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3690 op &= UINT64_C(31);
3691 op <<= 11;
3692 Value |= op;
3693 // op: rt
3694 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3695 op &= UINT64_C(31);
3696 op <<= 16;
3697 Value |= op;
3698 break;
3699 }
3700 case Mips::SUXC1_MM:
3701 case Mips::SWXC1_MM: {
3702 // op: fs
3703 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3704 op &= UINT64_C(31);
3705 op <<= 11;
3706 Value |= op;
3707 // op: base
3708 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3709 op &= UINT64_C(31);
3710 op <<= 16;
3711 Value |= op;
3712 // op: index
3713 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3714 op &= UINT64_C(31);
3715 op <<= 21;
3716 Value |= op;
3717 break;
3718 }
3719 case Mips::SDXC1:
3720 case Mips::SDXC164:
3721 case Mips::SUXC1:
3722 case Mips::SUXC164:
3723 case Mips::SWXC1: {
3724 // op: fs
3725 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3726 op &= UINT64_C(31);
3727 op <<= 11;
3728 Value |= op;
3729 // op: base
3730 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3731 op &= UINT64_C(31);
3732 op <<= 21;
3733 Value |= op;
3734 // op: index
3735 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3736 op &= UINT64_C(31);
3737 op <<= 16;
3738 Value |= op;
3739 break;
3740 }
3741 case Mips::FCMP_D32:
3742 case Mips::FCMP_D64:
3743 case Mips::FCMP_S32: {
3744 // op: fs
3745 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3746 op &= UINT64_C(31);
3747 op <<= 11;
3748 Value |= op;
3749 // op: ft
3750 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3751 op &= UINT64_C(31);
3752 op <<= 16;
3753 Value |= op;
3754 // op: cond
3755 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3756 op &= UINT64_C(15);
3757 Value |= op;
3758 break;
3759 }
3760 case Mips::FCMP_D32_MM:
3761 case Mips::FCMP_S32_MM: {
3762 // op: fs
3763 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3764 op &= UINT64_C(31);
3765 op <<= 16;
3766 Value |= op;
3767 // op: ft
3768 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3769 op &= UINT64_C(31);
3770 op <<= 21;
3771 Value |= op;
3772 // op: cond
3773 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3774 op &= UINT64_C(15);
3775 op <<= 6;
3776 Value |= op;
3777 break;
3778 }
3779 case Mips::CLASS_D:
3780 case Mips::CLASS_S:
3781 case Mips::RINT_D:
3782 case Mips::RINT_S: {
3783 // op: fs
3784 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3785 op &= UINT64_C(31);
3786 op <<= 11;
3787 Value |= op;
3788 // op: fd
3789 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3790 op &= UINT64_C(31);
3791 op <<= 6;
3792 Value |= op;
3793 break;
3794 }
3795 case Mips::C_EQ_D32:
3796 case Mips::C_EQ_D64:
3797 case Mips::C_EQ_S:
3798 case Mips::C_F_D32:
3799 case Mips::C_F_D64:
3800 case Mips::C_F_S:
3801 case Mips::C_LE_D32:
3802 case Mips::C_LE_D64:
3803 case Mips::C_LE_S:
3804 case Mips::C_LT_D32:
3805 case Mips::C_LT_D64:
3806 case Mips::C_LT_S:
3807 case Mips::C_NGE_D32:
3808 case Mips::C_NGE_D64:
3809 case Mips::C_NGE_S:
3810 case Mips::C_NGLE_D32:
3811 case Mips::C_NGLE_D64:
3812 case Mips::C_NGLE_S:
3813 case Mips::C_NGL_D32:
3814 case Mips::C_NGL_D64:
3815 case Mips::C_NGL_S:
3816 case Mips::C_NGT_D32:
3817 case Mips::C_NGT_D64:
3818 case Mips::C_NGT_S:
3819 case Mips::C_OLE_D32:
3820 case Mips::C_OLE_D64:
3821 case Mips::C_OLE_S:
3822 case Mips::C_OLT_D32:
3823 case Mips::C_OLT_D64:
3824 case Mips::C_OLT_S:
3825 case Mips::C_SEQ_D32:
3826 case Mips::C_SEQ_D64:
3827 case Mips::C_SEQ_S:
3828 case Mips::C_SF_D32:
3829 case Mips::C_SF_D64:
3830 case Mips::C_SF_S:
3831 case Mips::C_UEQ_D32:
3832 case Mips::C_UEQ_D64:
3833 case Mips::C_UEQ_S:
3834 case Mips::C_ULE_D32:
3835 case Mips::C_ULE_D64:
3836 case Mips::C_ULE_S:
3837 case Mips::C_ULT_D32:
3838 case Mips::C_ULT_D64:
3839 case Mips::C_ULT_S:
3840 case Mips::C_UN_D32:
3841 case Mips::C_UN_D64:
3842 case Mips::C_UN_S: {
3843 // op: fs
3844 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3845 op &= UINT64_C(31);
3846 op <<= 11;
3847 Value |= op;
3848 // op: ft
3849 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3850 op &= UINT64_C(31);
3851 op <<= 16;
3852 Value |= op;
3853 // op: fcc
3854 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3855 op &= UINT64_C(7);
3856 op <<= 8;
3857 Value |= op;
3858 break;
3859 }
3860 case Mips::C_EQ_D32_MM:
3861 case Mips::C_EQ_D64_MM:
3862 case Mips::C_EQ_S_MM:
3863 case Mips::C_F_D32_MM:
3864 case Mips::C_F_D64_MM:
3865 case Mips::C_F_S_MM:
3866 case Mips::C_LE_D32_MM:
3867 case Mips::C_LE_D64_MM:
3868 case Mips::C_LE_S_MM:
3869 case Mips::C_LT_D32_MM:
3870 case Mips::C_LT_D64_MM:
3871 case Mips::C_LT_S_MM:
3872 case Mips::C_NGE_D32_MM:
3873 case Mips::C_NGE_D64_MM:
3874 case Mips::C_NGE_S_MM:
3875 case Mips::C_NGLE_D32_MM:
3876 case Mips::C_NGLE_D64_MM:
3877 case Mips::C_NGLE_S_MM:
3878 case Mips::C_NGL_D32_MM:
3879 case Mips::C_NGL_D64_MM:
3880 case Mips::C_NGL_S_MM:
3881 case Mips::C_NGT_D32_MM:
3882 case Mips::C_NGT_D64_MM:
3883 case Mips::C_NGT_S_MM:
3884 case Mips::C_OLE_D32_MM:
3885 case Mips::C_OLE_D64_MM:
3886 case Mips::C_OLE_S_MM:
3887 case Mips::C_OLT_D32_MM:
3888 case Mips::C_OLT_D64_MM:
3889 case Mips::C_OLT_S_MM:
3890 case Mips::C_SEQ_D32_MM:
3891 case Mips::C_SEQ_D64_MM:
3892 case Mips::C_SEQ_S_MM:
3893 case Mips::C_SF_D32_MM:
3894 case Mips::C_SF_D64_MM:
3895 case Mips::C_SF_S_MM:
3896 case Mips::C_UEQ_D32_MM:
3897 case Mips::C_UEQ_D64_MM:
3898 case Mips::C_UEQ_S_MM:
3899 case Mips::C_ULE_D32_MM:
3900 case Mips::C_ULE_D64_MM:
3901 case Mips::C_ULE_S_MM:
3902 case Mips::C_ULT_D32_MM:
3903 case Mips::C_ULT_D64_MM:
3904 case Mips::C_ULT_S_MM:
3905 case Mips::C_UN_D32_MM:
3906 case Mips::C_UN_D64_MM:
3907 case Mips::C_UN_S_MM: {
3908 // op: fs
3909 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3910 op &= UINT64_C(31);
3911 op <<= 16;
3912 Value |= op;
3913 // op: ft
3914 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3915 op &= UINT64_C(31);
3916 op <<= 21;
3917 Value |= op;
3918 // op: fcc
3919 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3920 op &= UINT64_C(7);
3921 op <<= 13;
3922 Value |= op;
3923 break;
3924 }
3925 case Mips::CLASS_D_MMR6:
3926 case Mips::CLASS_S_MMR6:
3927 case Mips::RINT_D_MMR6:
3928 case Mips::RINT_S_MMR6: {
3929 // op: fs
3930 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3931 op &= UINT64_C(31);
3932 op <<= 21;
3933 Value |= op;
3934 // op: fd
3935 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3936 op &= UINT64_C(31);
3937 op <<= 16;
3938 Value |= op;
3939 break;
3940 }
3941 case Mips::BC1EQZ:
3942 case Mips::BC1NEZ: {
3943 // op: ft
3944 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3945 op &= UINT64_C(31);
3946 op <<= 16;
3947 Value |= op;
3948 // op: offset
3949 op = getBranchTargetOpValue(MI, OpNo: 1, Fixups, STI);
3950 op &= UINT64_C(65535);
3951 Value |= op;
3952 break;
3953 }
3954 case Mips::LDC1_D64_MMR6:
3955 case Mips::SDC1_D64_MMR6: {
3956 // op: ft
3957 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3958 op &= UINT64_C(31);
3959 op <<= 21;
3960 Value |= op;
3961 // op: addr
3962 op = getMemEncodingMMImm16(MI, OpNo: 1, Fixups, STI);
3963 op &= UINT64_C(2097151);
3964 Value |= op;
3965 break;
3966 }
3967 case Mips::CEIL_L_D_MMR6:
3968 case Mips::CEIL_L_S_MMR6:
3969 case Mips::CEIL_W_D_MMR6:
3970 case Mips::CEIL_W_S_MMR6:
3971 case Mips::CVT_D_L_MMR6:
3972 case Mips::CVT_L_D_MMR6:
3973 case Mips::CVT_L_S_MMR6:
3974 case Mips::CVT_S_L_MMR6:
3975 case Mips::CVT_S_W_MMR6:
3976 case Mips::CVT_W_S_MMR6:
3977 case Mips::FLOOR_L_D_MMR6:
3978 case Mips::FLOOR_L_S_MMR6:
3979 case Mips::FLOOR_W_D_MMR6:
3980 case Mips::FLOOR_W_S_MMR6:
3981 case Mips::FMOV_D_MMR6:
3982 case Mips::FMOV_S_MMR6:
3983 case Mips::FNEG_S_MMR6:
3984 case Mips::ROUND_L_D_MMR6:
3985 case Mips::ROUND_L_S_MMR6:
3986 case Mips::ROUND_W_D_MMR6:
3987 case Mips::ROUND_W_S_MMR6:
3988 case Mips::TRUNC_L_D_MMR6:
3989 case Mips::TRUNC_L_S_MMR6:
3990 case Mips::TRUNC_W_D_MMR6:
3991 case Mips::TRUNC_W_S_MMR6: {
3992 // op: ft
3993 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3994 op &= UINT64_C(31);
3995 op <<= 21;
3996 Value |= op;
3997 // op: fs
3998 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3999 op &= UINT64_C(31);
4000 op <<= 16;
4001 Value |= op;
4002 break;
4003 }
4004 case Mips::FADD_S_MMR6:
4005 case Mips::FDIV_S_MMR6:
4006 case Mips::FMUL_S_MMR6:
4007 case Mips::FSUB_S_MMR6: {
4008 // op: ft
4009 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4010 op &= UINT64_C(31);
4011 op <<= 21;
4012 Value |= op;
4013 // op: fs
4014 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4015 op &= UINT64_C(31);
4016 op <<= 16;
4017 Value |= op;
4018 // op: fd
4019 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4020 op &= UINT64_C(31);
4021 op <<= 11;
4022 Value |= op;
4023 break;
4024 }
4025 case Mips::MAXA_D:
4026 case Mips::MAXA_S:
4027 case Mips::MAX_D:
4028 case Mips::MAX_S:
4029 case Mips::MINA_D:
4030 case Mips::MINA_S:
4031 case Mips::MIN_D:
4032 case Mips::MIN_S:
4033 case Mips::SELEQZ_D:
4034 case Mips::SELEQZ_S:
4035 case Mips::SELNEZ_D:
4036 case Mips::SELNEZ_S: {
4037 // op: ft
4038 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4039 op &= UINT64_C(31);
4040 op <<= 16;
4041 Value |= op;
4042 // op: fs
4043 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4044 op &= UINT64_C(31);
4045 op <<= 11;
4046 Value |= op;
4047 // op: fd
4048 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4049 op &= UINT64_C(31);
4050 op <<= 6;
4051 Value |= op;
4052 break;
4053 }
4054 case Mips::CMP_AF_D_MMR6:
4055 case Mips::CMP_AF_S_MMR6:
4056 case Mips::CMP_EQ_D_MMR6:
4057 case Mips::CMP_EQ_S_MMR6:
4058 case Mips::CMP_LE_D_MMR6:
4059 case Mips::CMP_LE_S_MMR6:
4060 case Mips::CMP_LT_D_MMR6:
4061 case Mips::CMP_LT_S_MMR6:
4062 case Mips::CMP_SAF_D_MMR6:
4063 case Mips::CMP_SAF_S_MMR6:
4064 case Mips::CMP_SEQ_D_MMR6:
4065 case Mips::CMP_SEQ_S_MMR6:
4066 case Mips::CMP_SLE_D_MMR6:
4067 case Mips::CMP_SLE_S_MMR6:
4068 case Mips::CMP_SLT_D_MMR6:
4069 case Mips::CMP_SLT_S_MMR6:
4070 case Mips::CMP_SUEQ_D_MMR6:
4071 case Mips::CMP_SUEQ_S_MMR6:
4072 case Mips::CMP_SULE_D_MMR6:
4073 case Mips::CMP_SULE_S_MMR6:
4074 case Mips::CMP_SULT_D_MMR6:
4075 case Mips::CMP_SULT_S_MMR6:
4076 case Mips::CMP_SUN_D_MMR6:
4077 case Mips::CMP_SUN_S_MMR6:
4078 case Mips::CMP_UEQ_D_MMR6:
4079 case Mips::CMP_UEQ_S_MMR6:
4080 case Mips::CMP_ULE_D_MMR6:
4081 case Mips::CMP_ULE_S_MMR6:
4082 case Mips::CMP_ULT_D_MMR6:
4083 case Mips::CMP_ULT_S_MMR6:
4084 case Mips::CMP_UN_D_MMR6:
4085 case Mips::CMP_UN_S_MMR6:
4086 case Mips::FADD_D32_MM:
4087 case Mips::FADD_D64_MM:
4088 case Mips::FADD_S_MM:
4089 case Mips::FDIV_D32_MM:
4090 case Mips::FDIV_D64_MM:
4091 case Mips::FDIV_S_MM:
4092 case Mips::FMUL_D32_MM:
4093 case Mips::FMUL_D64_MM:
4094 case Mips::FMUL_S_MM:
4095 case Mips::FSUB_D32_MM:
4096 case Mips::FSUB_D64_MM:
4097 case Mips::FSUB_S_MM:
4098 case Mips::MAXA_D_MMR6:
4099 case Mips::MAXA_S_MMR6:
4100 case Mips::MAX_D_MMR6:
4101 case Mips::MAX_S_MMR6:
4102 case Mips::MINA_D_MMR6:
4103 case Mips::MINA_S_MMR6:
4104 case Mips::MIN_D_MMR6:
4105 case Mips::MIN_S_MMR6:
4106 case Mips::SELEQZ_D_MMR6:
4107 case Mips::SELEQZ_S_MMR6:
4108 case Mips::SELNEZ_D_MMR6:
4109 case Mips::SELNEZ_S_MMR6: {
4110 // op: ft
4111 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4112 op &= UINT64_C(31);
4113 op <<= 21;
4114 Value |= op;
4115 // op: fs
4116 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4117 op &= UINT64_C(31);
4118 op <<= 16;
4119 Value |= op;
4120 // op: fd
4121 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4122 op &= UINT64_C(31);
4123 op <<= 11;
4124 Value |= op;
4125 break;
4126 }
4127 case Mips::MADDF_D:
4128 case Mips::MADDF_S:
4129 case Mips::MSUBF_D:
4130 case Mips::MSUBF_S:
4131 case Mips::SEL_D:
4132 case Mips::SEL_S: {
4133 // op: ft
4134 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4135 op &= UINT64_C(31);
4136 op <<= 16;
4137 Value |= op;
4138 // op: fs
4139 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4140 op &= UINT64_C(31);
4141 op <<= 11;
4142 Value |= op;
4143 // op: fd
4144 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4145 op &= UINT64_C(31);
4146 op <<= 6;
4147 Value |= op;
4148 break;
4149 }
4150 case Mips::MADDF_D_MMR6:
4151 case Mips::MADDF_S_MMR6:
4152 case Mips::MSUBF_D_MMR6:
4153 case Mips::MSUBF_S_MMR6:
4154 case Mips::SEL_D_MMR6:
4155 case Mips::SEL_S_MMR6: {
4156 // op: ft
4157 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4158 op &= UINT64_C(31);
4159 op <<= 21;
4160 Value |= op;
4161 // op: fs
4162 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4163 op &= UINT64_C(31);
4164 op <<= 16;
4165 Value |= op;
4166 // op: fd
4167 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4168 op &= UINT64_C(31);
4169 op <<= 11;
4170 Value |= op;
4171 break;
4172 }
4173 case Mips::MADD_D32_MM:
4174 case Mips::MADD_S_MM:
4175 case Mips::MSUB_D32_MM:
4176 case Mips::MSUB_S_MM:
4177 case Mips::NMADD_D32_MM:
4178 case Mips::NMADD_S_MM:
4179 case Mips::NMSUB_D32_MM:
4180 case Mips::NMSUB_S_MM: {
4181 // op: ft
4182 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4183 op &= UINT64_C(31);
4184 op <<= 21;
4185 Value |= op;
4186 // op: fs
4187 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4188 op &= UINT64_C(31);
4189 op <<= 16;
4190 Value |= op;
4191 // op: fd
4192 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4193 op &= UINT64_C(31);
4194 op <<= 11;
4195 Value |= op;
4196 // op: fr
4197 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4198 op &= UINT64_C(31);
4199 op <<= 6;
4200 Value |= op;
4201 break;
4202 }
4203 case Mips::ADDVI_B:
4204 case Mips::ADDVI_D:
4205 case Mips::ADDVI_H:
4206 case Mips::ADDVI_W:
4207 case Mips::CEQI_B:
4208 case Mips::CEQI_D:
4209 case Mips::CEQI_H:
4210 case Mips::CEQI_W:
4211 case Mips::CLEI_S_B:
4212 case Mips::CLEI_S_D:
4213 case Mips::CLEI_S_H:
4214 case Mips::CLEI_S_W:
4215 case Mips::CLEI_U_B:
4216 case Mips::CLEI_U_D:
4217 case Mips::CLEI_U_H:
4218 case Mips::CLEI_U_W:
4219 case Mips::CLTI_S_B:
4220 case Mips::CLTI_S_D:
4221 case Mips::CLTI_S_H:
4222 case Mips::CLTI_S_W:
4223 case Mips::CLTI_U_B:
4224 case Mips::CLTI_U_D:
4225 case Mips::CLTI_U_H:
4226 case Mips::CLTI_U_W:
4227 case Mips::MAXI_S_B:
4228 case Mips::MAXI_S_D:
4229 case Mips::MAXI_S_H:
4230 case Mips::MAXI_S_W:
4231 case Mips::MAXI_U_B:
4232 case Mips::MAXI_U_D:
4233 case Mips::MAXI_U_H:
4234 case Mips::MAXI_U_W:
4235 case Mips::MINI_S_B:
4236 case Mips::MINI_S_D:
4237 case Mips::MINI_S_H:
4238 case Mips::MINI_S_W:
4239 case Mips::MINI_U_B:
4240 case Mips::MINI_U_D:
4241 case Mips::MINI_U_H:
4242 case Mips::MINI_U_W:
4243 case Mips::SUBVI_B:
4244 case Mips::SUBVI_D:
4245 case Mips::SUBVI_H:
4246 case Mips::SUBVI_W: {
4247 // op: imm
4248 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4249 op &= UINT64_C(31);
4250 op <<= 16;
4251 Value |= op;
4252 // op: ws
4253 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4254 op &= UINT64_C(31);
4255 op <<= 11;
4256 Value |= op;
4257 // op: wd
4258 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4259 op &= UINT64_C(31);
4260 op <<= 6;
4261 Value |= op;
4262 break;
4263 }
4264 case Mips::ADDIUSP_MM: {
4265 // op: imm
4266 op = getSImm9AddiuspValue(MI, OpNo: 0, Fixups, STI);
4267 op &= UINT64_C(511);
4268 op <<= 1;
4269 Value |= op;
4270 break;
4271 }
4272 case Mips::JRADDIUSP: {
4273 // op: imm
4274 op = getUImm5Lsl2Encoding(MI, OpNo: 0, Fixups, STI);
4275 op &= UINT64_C(31);
4276 Value |= op;
4277 break;
4278 }
4279 case Mips::JRCADDIUSP_MMR6: {
4280 // op: imm
4281 op = getUImm5Lsl2Encoding(MI, OpNo: 0, Fixups, STI);
4282 op &= UINT64_C(31);
4283 op <<= 5;
4284 Value |= op;
4285 break;
4286 }
4287 case Mips::Bimm16: {
4288 // op: imm11
4289 op = getBranchTargetOpValue(MI, OpNo: 0, Fixups, STI);
4290 op &= UINT64_C(2047);
4291 Value |= op;
4292 break;
4293 }
4294 case Mips::AddiuRxRyOffMemX16: {
4295 // op: imm15
4296 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4297 Value |= (op & UINT64_C(2032)) << 16;
4298 Value |= (op & UINT64_C(30720)) << 5;
4299 Value |= (op & UINT64_C(15));
4300 // op: rx
4301 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4302 op &= UINT64_C(7);
4303 op <<= 8;
4304 Value |= op;
4305 // op: ry
4306 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4307 op &= UINT64_C(7);
4308 op <<= 5;
4309 Value |= op;
4310 break;
4311 }
4312 case Mips::BimmX16: {
4313 // op: imm16
4314 op = getBranchTargetOpValue(MI, OpNo: 0, Fixups, STI);
4315 Value |= (op & UINT64_C(2016)) << 16;
4316 Value |= (op & UINT64_C(63488)) << 5;
4317 Value |= (op & UINT64_C(31));
4318 break;
4319 }
4320 case Mips::BeqzRxImmX16:
4321 case Mips::BnezRxImmX16: {
4322 // op: imm16
4323 op = getBranchTargetOpValue(MI, OpNo: 1, Fixups, STI);
4324 Value |= (op & UINT64_C(2016)) << 16;
4325 Value |= (op & UINT64_C(63488)) << 5;
4326 Value |= (op & UINT64_C(31));
4327 // op: rx
4328 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4329 op &= UINT64_C(7);
4330 op <<= 8;
4331 Value |= op;
4332 break;
4333 }
4334 case Mips::AddiuSpImmX16:
4335 case Mips::BteqzX16:
4336 case Mips::BtnezX16: {
4337 // op: imm16
4338 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4339 Value |= (op & UINT64_C(2016)) << 16;
4340 Value |= (op & UINT64_C(63488)) << 5;
4341 Value |= (op & UINT64_C(31));
4342 break;
4343 }
4344 case Mips::AddiuRxImmX16:
4345 case Mips::AddiuRxPcImmX16:
4346 case Mips::CmpiRxImmX16:
4347 case Mips::LiRxImmAlignX16:
4348 case Mips::LiRxImmX16:
4349 case Mips::LwRxPcTcpX16:
4350 case Mips::SltiRxImmX16:
4351 case Mips::SltiuRxImmX16: {
4352 // op: imm16
4353 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4354 Value |= (op & UINT64_C(2016)) << 16;
4355 Value |= (op & UINT64_C(63488)) << 5;
4356 Value |= (op & UINT64_C(31));
4357 // op: rx
4358 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4359 op &= UINT64_C(7);
4360 op <<= 8;
4361 Value |= op;
4362 break;
4363 }
4364 case Mips::AddiuRxRxImmX16: {
4365 // op: imm16
4366 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4367 Value |= (op & UINT64_C(2016)) << 16;
4368 Value |= (op & UINT64_C(63488)) << 5;
4369 Value |= (op & UINT64_C(31));
4370 // op: rx
4371 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4372 op &= UINT64_C(7);
4373 op <<= 8;
4374 Value |= op;
4375 break;
4376 }
4377 case Mips::LbRxRyOffMemX16:
4378 case Mips::LbuRxRyOffMemX16:
4379 case Mips::LhRxRyOffMemX16:
4380 case Mips::LhuRxRyOffMemX16:
4381 case Mips::LwRxRyOffMemX16:
4382 case Mips::LwRxSpImmX16:
4383 case Mips::SbRxRyOffMemX16:
4384 case Mips::ShRxRyOffMemX16:
4385 case Mips::SwRxRyOffMemX16:
4386 case Mips::SwRxSpImmX16: {
4387 // op: imm16
4388 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4389 Value |= (op & UINT64_C(2016)) << 16;
4390 Value |= (op & UINT64_C(63488)) << 5;
4391 Value |= (op & UINT64_C(31));
4392 // op: rx
4393 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4394 op &= UINT64_C(7);
4395 op <<= 8;
4396 Value |= op;
4397 // op: ry
4398 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4399 op &= UINT64_C(7);
4400 op <<= 5;
4401 Value |= op;
4402 break;
4403 }
4404 case Mips::Jal16:
4405 case Mips::JalB16: {
4406 // op: imm26
4407 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4408 Value |= (op & UINT64_C(2031616)) << 5;
4409 Value |= (op & UINT64_C(65011712)) >> 5;
4410 Value |= (op & UINT64_C(65535));
4411 break;
4412 }
4413 case Mips::AddiuSpImm16:
4414 case Mips::Bteqz16:
4415 case Mips::Btnez16: {
4416 // op: imm8
4417 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4418 op &= UINT64_C(255);
4419 Value |= op;
4420 break;
4421 }
4422 case Mips::PREFX_MM: {
4423 // op: index
4424 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4425 op &= UINT64_C(31);
4426 op <<= 21;
4427 Value |= op;
4428 // op: base
4429 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4430 op &= UINT64_C(31);
4431 op <<= 16;
4432 Value |= op;
4433 // op: hint
4434 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4435 op &= UINT64_C(31);
4436 op <<= 11;
4437 Value |= op;
4438 break;
4439 }
4440 case Mips::LBUX_MM:
4441 case Mips::LHX_MM:
4442 case Mips::LWX_MM: {
4443 // op: index
4444 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4445 op &= UINT64_C(31);
4446 op <<= 21;
4447 Value |= op;
4448 // op: base
4449 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4450 op &= UINT64_C(31);
4451 op <<= 16;
4452 Value |= op;
4453 // op: rd
4454 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4455 op &= UINT64_C(31);
4456 op <<= 11;
4457 Value |= op;
4458 break;
4459 }
4460 case Mips::COPY_S_D: {
4461 // op: n
4462 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4463 op &= UINT64_C(1);
4464 op <<= 16;
4465 Value |= op;
4466 // op: ws
4467 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4468 op &= UINT64_C(31);
4469 op <<= 11;
4470 Value |= op;
4471 // op: rd
4472 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4473 op &= UINT64_C(31);
4474 op <<= 6;
4475 Value |= op;
4476 break;
4477 }
4478 case Mips::SPLATI_D: {
4479 // op: n
4480 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4481 op &= UINT64_C(1);
4482 op <<= 16;
4483 Value |= op;
4484 // op: ws
4485 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4486 op &= UINT64_C(31);
4487 op <<= 11;
4488 Value |= op;
4489 // op: wd
4490 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4491 op &= UINT64_C(31);
4492 op <<= 6;
4493 Value |= op;
4494 break;
4495 }
4496 case Mips::INSVE_D: {
4497 // op: n
4498 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4499 op &= UINT64_C(1);
4500 op <<= 16;
4501 Value |= op;
4502 // op: ws
4503 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4504 op &= UINT64_C(31);
4505 op <<= 11;
4506 Value |= op;
4507 // op: wd
4508 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4509 op &= UINT64_C(31);
4510 op <<= 6;
4511 Value |= op;
4512 break;
4513 }
4514 case Mips::COPY_S_B:
4515 case Mips::COPY_U_B: {
4516 // op: n
4517 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4518 op &= UINT64_C(15);
4519 op <<= 16;
4520 Value |= op;
4521 // op: ws
4522 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4523 op &= UINT64_C(31);
4524 op <<= 11;
4525 Value |= op;
4526 // op: rd
4527 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4528 op &= UINT64_C(31);
4529 op <<= 6;
4530 Value |= op;
4531 break;
4532 }
4533 case Mips::SPLATI_B: {
4534 // op: n
4535 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4536 op &= UINT64_C(15);
4537 op <<= 16;
4538 Value |= op;
4539 // op: ws
4540 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4541 op &= UINT64_C(31);
4542 op <<= 11;
4543 Value |= op;
4544 // op: wd
4545 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4546 op &= UINT64_C(31);
4547 op <<= 6;
4548 Value |= op;
4549 break;
4550 }
4551 case Mips::INSVE_B: {
4552 // op: n
4553 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4554 op &= UINT64_C(15);
4555 op <<= 16;
4556 Value |= op;
4557 // op: ws
4558 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4559 op &= UINT64_C(31);
4560 op <<= 11;
4561 Value |= op;
4562 // op: wd
4563 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4564 op &= UINT64_C(31);
4565 op <<= 6;
4566 Value |= op;
4567 break;
4568 }
4569 case Mips::COPY_S_W:
4570 case Mips::COPY_U_W: {
4571 // op: n
4572 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4573 op &= UINT64_C(3);
4574 op <<= 16;
4575 Value |= op;
4576 // op: ws
4577 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4578 op &= UINT64_C(31);
4579 op <<= 11;
4580 Value |= op;
4581 // op: rd
4582 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4583 op &= UINT64_C(31);
4584 op <<= 6;
4585 Value |= op;
4586 break;
4587 }
4588 case Mips::SPLATI_W: {
4589 // op: n
4590 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4591 op &= UINT64_C(3);
4592 op <<= 16;
4593 Value |= op;
4594 // op: ws
4595 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4596 op &= UINT64_C(31);
4597 op <<= 11;
4598 Value |= op;
4599 // op: wd
4600 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4601 op &= UINT64_C(31);
4602 op <<= 6;
4603 Value |= op;
4604 break;
4605 }
4606 case Mips::INSVE_W: {
4607 // op: n
4608 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4609 op &= UINT64_C(3);
4610 op <<= 16;
4611 Value |= op;
4612 // op: ws
4613 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4614 op &= UINT64_C(31);
4615 op <<= 11;
4616 Value |= op;
4617 // op: wd
4618 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4619 op &= UINT64_C(31);
4620 op <<= 6;
4621 Value |= op;
4622 break;
4623 }
4624 case Mips::COPY_S_H:
4625 case Mips::COPY_U_H: {
4626 // op: n
4627 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4628 op &= UINT64_C(7);
4629 op <<= 16;
4630 Value |= op;
4631 // op: ws
4632 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4633 op &= UINT64_C(31);
4634 op <<= 11;
4635 Value |= op;
4636 // op: rd
4637 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4638 op &= UINT64_C(31);
4639 op <<= 6;
4640 Value |= op;
4641 break;
4642 }
4643 case Mips::SPLATI_H: {
4644 // op: n
4645 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4646 op &= UINT64_C(7);
4647 op <<= 16;
4648 Value |= op;
4649 // op: ws
4650 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4651 op &= UINT64_C(31);
4652 op <<= 11;
4653 Value |= op;
4654 // op: wd
4655 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4656 op &= UINT64_C(31);
4657 op <<= 6;
4658 Value |= op;
4659 break;
4660 }
4661 case Mips::INSVE_H: {
4662 // op: n
4663 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4664 op &= UINT64_C(7);
4665 op <<= 16;
4666 Value |= op;
4667 // op: ws
4668 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4669 op &= UINT64_C(31);
4670 op <<= 11;
4671 Value |= op;
4672 // op: wd
4673 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4674 op &= UINT64_C(31);
4675 op <<= 6;
4676 Value |= op;
4677 break;
4678 }
4679 case Mips::INSERT_D: {
4680 // op: n
4681 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4682 op &= UINT64_C(1);
4683 op <<= 16;
4684 Value |= op;
4685 // op: rs
4686 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4687 op &= UINT64_C(31);
4688 op <<= 11;
4689 Value |= op;
4690 // op: wd
4691 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4692 op &= UINT64_C(31);
4693 op <<= 6;
4694 Value |= op;
4695 break;
4696 }
4697 case Mips::SLDI_D: {
4698 // op: n
4699 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4700 op &= UINT64_C(1);
4701 op <<= 16;
4702 Value |= op;
4703 // op: ws
4704 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4705 op &= UINT64_C(31);
4706 op <<= 11;
4707 Value |= op;
4708 // op: wd
4709 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4710 op &= UINT64_C(31);
4711 op <<= 6;
4712 Value |= op;
4713 break;
4714 }
4715 case Mips::INSERT_B: {
4716 // op: n
4717 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4718 op &= UINT64_C(15);
4719 op <<= 16;
4720 Value |= op;
4721 // op: rs
4722 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4723 op &= UINT64_C(31);
4724 op <<= 11;
4725 Value |= op;
4726 // op: wd
4727 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4728 op &= UINT64_C(31);
4729 op <<= 6;
4730 Value |= op;
4731 break;
4732 }
4733 case Mips::SLDI_B: {
4734 // op: n
4735 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4736 op &= UINT64_C(15);
4737 op <<= 16;
4738 Value |= op;
4739 // op: ws
4740 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4741 op &= UINT64_C(31);
4742 op <<= 11;
4743 Value |= op;
4744 // op: wd
4745 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4746 op &= UINT64_C(31);
4747 op <<= 6;
4748 Value |= op;
4749 break;
4750 }
4751 case Mips::INSERT_W: {
4752 // op: n
4753 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4754 op &= UINT64_C(3);
4755 op <<= 16;
4756 Value |= op;
4757 // op: rs
4758 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4759 op &= UINT64_C(31);
4760 op <<= 11;
4761 Value |= op;
4762 // op: wd
4763 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4764 op &= UINT64_C(31);
4765 op <<= 6;
4766 Value |= op;
4767 break;
4768 }
4769 case Mips::SLDI_W: {
4770 // op: n
4771 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4772 op &= UINT64_C(3);
4773 op <<= 16;
4774 Value |= op;
4775 // op: ws
4776 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4777 op &= UINT64_C(31);
4778 op <<= 11;
4779 Value |= op;
4780 // op: wd
4781 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4782 op &= UINT64_C(31);
4783 op <<= 6;
4784 Value |= op;
4785 break;
4786 }
4787 case Mips::INSERT_H: {
4788 // op: n
4789 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4790 op &= UINT64_C(7);
4791 op <<= 16;
4792 Value |= op;
4793 // op: rs
4794 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4795 op &= UINT64_C(31);
4796 op <<= 11;
4797 Value |= op;
4798 // op: wd
4799 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4800 op &= UINT64_C(31);
4801 op <<= 6;
4802 Value |= op;
4803 break;
4804 }
4805 case Mips::SLDI_H: {
4806 // op: n
4807 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4808 op &= UINT64_C(7);
4809 op <<= 16;
4810 Value |= op;
4811 // op: ws
4812 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4813 op &= UINT64_C(31);
4814 op <<= 11;
4815 Value |= op;
4816 // op: wd
4817 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4818 op &= UINT64_C(31);
4819 op <<= 6;
4820 Value |= op;
4821 break;
4822 }
4823 case Mips::BALC:
4824 case Mips::BC: {
4825 // op: offset
4826 op = getBranchTarget26OpValue(MI, OpNo: 0, Fixups, STI);
4827 op &= UINT64_C(67108863);
4828 Value |= op;
4829 break;
4830 }
4831 case Mips::BALC_MMR6:
4832 case Mips::BC_MMR6: {
4833 // op: offset
4834 op = getBranchTarget26OpValueMM(MI, OpNo: 0, Fixups, STI);
4835 op &= UINT64_C(67108863);
4836 Value |= op;
4837 break;
4838 }
4839 case Mips::BAL:
4840 case Mips::BPOSGE32: {
4841 // op: offset
4842 op = getBranchTargetOpValue(MI, OpNo: 0, Fixups, STI);
4843 op &= UINT64_C(65535);
4844 Value |= op;
4845 break;
4846 }
4847 case Mips::BNZ_B:
4848 case Mips::BNZ_D:
4849 case Mips::BNZ_H:
4850 case Mips::BNZ_V:
4851 case Mips::BNZ_W:
4852 case Mips::BZ_B:
4853 case Mips::BZ_D:
4854 case Mips::BZ_H:
4855 case Mips::BZ_V:
4856 case Mips::BZ_W: {
4857 // op: offset
4858 op = getBranchTargetOpValue(MI, OpNo: 1, Fixups, STI);
4859 op &= UINT64_C(65535);
4860 Value |= op;
4861 // op: wt
4862 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4863 op &= UINT64_C(31);
4864 op <<= 16;
4865 Value |= op;
4866 break;
4867 }
4868 case Mips::BPOSGE32C_MMR3: {
4869 // op: offset
4870 op = getBranchTargetOpValue1SImm16(MI, OpNo: 0, Fixups, STI);
4871 op &= UINT64_C(65535);
4872 Value |= op;
4873 break;
4874 }
4875 case Mips::BPOSGE32_MM: {
4876 // op: offset
4877 op = getBranchTargetOpValueMM(MI, OpNo: 0, Fixups, STI);
4878 op &= UINT64_C(65535);
4879 Value |= op;
4880 break;
4881 }
4882 case Mips::B16_MM:
4883 case Mips::BC16_MMR6: {
4884 // op: offset
4885 op = getBranchTargetOpValueMMPC10(MI, OpNo: 0, Fixups, STI);
4886 op &= UINT64_C(1023);
4887 Value |= op;
4888 break;
4889 }
4890 case Mips::Move32R16: {
4891 // op: r32
4892 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4893 Value |= (op & UINT64_C(7)) << 5;
4894 Value |= (op & UINT64_C(24));
4895 // op: rz
4896 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4897 op &= UINT64_C(7);
4898 Value |= op;
4899 break;
4900 }
4901 case Mips::CLO:
4902 case Mips::CLZ:
4903 case Mips::DCLO:
4904 case Mips::DCLZ: {
4905 // op: rd
4906 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4907 Value |= (op & UINT64_C(31)) << 16;
4908 Value |= (op & UINT64_C(31)) << 11;
4909 // op: rs
4910 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4911 op &= UINT64_C(31);
4912 op <<= 21;
4913 Value |= op;
4914 break;
4915 }
4916 case Mips::MFHI16_MM:
4917 case Mips::MFLO16_MM: {
4918 // op: rd
4919 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4920 op &= UINT64_C(31);
4921 Value |= op;
4922 break;
4923 }
4924 case Mips::MFHI:
4925 case Mips::MFHI64:
4926 case Mips::MFLO:
4927 case Mips::MFLO64: {
4928 // op: rd
4929 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4930 op &= UINT64_C(31);
4931 op <<= 11;
4932 Value |= op;
4933 break;
4934 }
4935 case Mips::MFHI_DSP:
4936 case Mips::MFLO_DSP: {
4937 // op: rd
4938 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4939 op &= UINT64_C(31);
4940 op <<= 11;
4941 Value |= op;
4942 // op: ac
4943 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4944 op &= UINT64_C(3);
4945 op <<= 21;
4946 Value |= op;
4947 break;
4948 }
4949 case Mips::LWXS_MM: {
4950 // op: rd
4951 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4952 op &= UINT64_C(31);
4953 op <<= 11;
4954 Value |= op;
4955 // op: base
4956 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4957 op &= UINT64_C(31);
4958 op <<= 16;
4959 Value |= op;
4960 // op: index
4961 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4962 op &= UINT64_C(31);
4963 op <<= 21;
4964 Value |= op;
4965 break;
4966 }
4967 case Mips::LBUX:
4968 case Mips::LHX:
4969 case Mips::LWX: {
4970 // op: rd
4971 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4972 op &= UINT64_C(31);
4973 op <<= 11;
4974 Value |= op;
4975 // op: base
4976 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4977 op &= UINT64_C(31);
4978 op <<= 21;
4979 Value |= op;
4980 // op: index
4981 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4982 op &= UINT64_C(31);
4983 op <<= 16;
4984 Value |= op;
4985 break;
4986 }
4987 case Mips::REPL_PH:
4988 case Mips::REPL_PH_MM:
4989 case Mips::REPL_QB: {
4990 // op: rd
4991 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4992 op &= UINT64_C(31);
4993 op <<= 11;
4994 Value |= op;
4995 // op: imm
4996 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4997 op &= UINT64_C(1023);
4998 op <<= 16;
4999 Value |= op;
5000 break;
5001 }
5002 case Mips::RDDSP: {
5003 // op: rd
5004 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5005 op &= UINT64_C(31);
5006 op <<= 11;
5007 Value |= op;
5008 // op: mask
5009 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5010 op &= UINT64_C(1023);
5011 op <<= 16;
5012 Value |= op;
5013 break;
5014 }
5015 case Mips::ADDQH_PH_MMR2:
5016 case Mips::ADDQH_R_PH_MMR2:
5017 case Mips::ADDQH_R_W_MMR2:
5018 case Mips::ADDQH_W_MMR2:
5019 case Mips::ADDQ_PH_MM:
5020 case Mips::ADDQ_S_PH_MM:
5021 case Mips::ADDQ_S_W_MM:
5022 case Mips::ADDSC_MM:
5023 case Mips::ADDUH_QB_MMR2:
5024 case Mips::ADDUH_R_QB_MMR2:
5025 case Mips::ADDU_PH_MMR2:
5026 case Mips::ADDU_QB_MM:
5027 case Mips::ADDU_S_PH_MMR2:
5028 case Mips::ADDU_S_QB_MM:
5029 case Mips::ADDWC_MM:
5030 case Mips::CMPGDU_EQ_QB_MMR2:
5031 case Mips::CMPGDU_LE_QB_MMR2:
5032 case Mips::CMPGDU_LT_QB_MMR2:
5033 case Mips::MODSUB_MM:
5034 case Mips::MULEQ_S_W_PHL_MM:
5035 case Mips::MULEQ_S_W_PHR_MM:
5036 case Mips::MULEU_S_PH_QBL_MM:
5037 case Mips::MULEU_S_PH_QBR_MM:
5038 case Mips::MULQ_RS_PH_MM:
5039 case Mips::MULQ_RS_W_MMR2:
5040 case Mips::MULQ_S_PH_MMR2:
5041 case Mips::MULQ_S_W_MMR2:
5042 case Mips::MUL_PH_MMR2:
5043 case Mips::MUL_S_PH_MMR2:
5044 case Mips::PACKRL_PH_MM:
5045 case Mips::PICK_PH_MM:
5046 case Mips::PICK_QB_MM:
5047 case Mips::PRECRQU_S_QB_PH_MM:
5048 case Mips::PRECRQ_PH_W_MM:
5049 case Mips::PRECRQ_QB_PH_MM:
5050 case Mips::PRECRQ_RS_PH_W_MM:
5051 case Mips::PRECR_QB_PH_MMR2:
5052 case Mips::SELEQZ_MMR6:
5053 case Mips::SELNEZ_MMR6:
5054 case Mips::SUBQH_PH_MMR2:
5055 case Mips::SUBQH_R_PH_MMR2:
5056 case Mips::SUBQH_R_W_MMR2:
5057 case Mips::SUBQH_W_MMR2:
5058 case Mips::SUBQ_PH_MM:
5059 case Mips::SUBQ_S_PH_MM:
5060 case Mips::SUBQ_S_W_MM:
5061 case Mips::SUBUH_QB_MMR2:
5062 case Mips::SUBUH_R_QB_MMR2:
5063 case Mips::SUBU_PH_MMR2:
5064 case Mips::SUBU_QB_MM:
5065 case Mips::SUBU_S_PH_MMR2:
5066 case Mips::SUBU_S_QB_MM: {
5067 // op: rd
5068 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5069 op &= UINT64_C(31);
5070 op <<= 11;
5071 Value |= op;
5072 // op: rs
5073 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5074 op &= UINT64_C(31);
5075 op <<= 16;
5076 Value |= op;
5077 // op: rt
5078 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5079 op &= UINT64_C(31);
5080 op <<= 21;
5081 Value |= op;
5082 break;
5083 }
5084 case Mips::LSA_MMR6: {
5085 // op: rd
5086 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5087 op &= UINT64_C(31);
5088 op <<= 11;
5089 Value |= op;
5090 // op: rs
5091 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5092 op &= UINT64_C(31);
5093 op <<= 16;
5094 Value |= op;
5095 // op: rt
5096 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5097 op &= UINT64_C(31);
5098 op <<= 21;
5099 Value |= op;
5100 // op: imm2
5101 op = getUImmWithOffsetEncoding<2, 1>(MI, OpNo: 3, Fixups, STI);
5102 op &= UINT64_C(3);
5103 op <<= 9;
5104 Value |= op;
5105 break;
5106 }
5107 case Mips::CLO_R6:
5108 case Mips::CLZ_R6:
5109 case Mips::DCLO_R6:
5110 case Mips::DCLZ_R6:
5111 case Mips::DPOP:
5112 case Mips::JALR:
5113 case Mips::JALR64:
5114 case Mips::JALR_HB:
5115 case Mips::JALR_HB64:
5116 case Mips::POP:
5117 case Mips::RADDU_W_QB: {
5118 // op: rd
5119 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5120 op &= UINT64_C(31);
5121 op <<= 11;
5122 Value |= op;
5123 // op: rs
5124 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5125 op &= UINT64_C(31);
5126 op <<= 21;
5127 Value |= op;
5128 break;
5129 }
5130 case Mips::MOVF_I:
5131 case Mips::MOVF_I64:
5132 case Mips::MOVT_I:
5133 case Mips::MOVT_I64: {
5134 // op: rd
5135 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5136 op &= UINT64_C(31);
5137 op <<= 11;
5138 Value |= op;
5139 // op: rs
5140 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5141 op &= UINT64_C(31);
5142 op <<= 21;
5143 Value |= op;
5144 // op: fcc
5145 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5146 op &= UINT64_C(7);
5147 op <<= 18;
5148 Value |= op;
5149 break;
5150 }
5151 case Mips::ADD:
5152 case Mips::ADDQH_PH:
5153 case Mips::ADDQH_R_PH:
5154 case Mips::ADDQH_R_W:
5155 case Mips::ADDQH_W:
5156 case Mips::ADDQ_PH:
5157 case Mips::ADDQ_S_PH:
5158 case Mips::ADDQ_S_W:
5159 case Mips::ADDSC:
5160 case Mips::ADDUH_QB:
5161 case Mips::ADDUH_R_QB:
5162 case Mips::ADDU_PH:
5163 case Mips::ADDU_QB:
5164 case Mips::ADDU_S_PH:
5165 case Mips::ADDU_S_QB:
5166 case Mips::ADDWC:
5167 case Mips::ADDu:
5168 case Mips::AND:
5169 case Mips::AND64:
5170 case Mips::BADDu:
5171 case Mips::DADD:
5172 case Mips::DADDu:
5173 case Mips::DDIV:
5174 case Mips::DDIVU:
5175 case Mips::DIV:
5176 case Mips::DIVU:
5177 case Mips::DMOD:
5178 case Mips::DMODU:
5179 case Mips::DMUH:
5180 case Mips::DMUHU:
5181 case Mips::DMUL:
5182 case Mips::DMULU:
5183 case Mips::DMUL_R6:
5184 case Mips::DSUB:
5185 case Mips::DSUBu:
5186 case Mips::MOD:
5187 case Mips::MODSUB:
5188 case Mips::MODU:
5189 case Mips::MOVN_I64_I:
5190 case Mips::MOVN_I64_I64:
5191 case Mips::MOVN_I_I:
5192 case Mips::MOVN_I_I64:
5193 case Mips::MOVZ_I64_I:
5194 case Mips::MOVZ_I64_I64:
5195 case Mips::MOVZ_I_I:
5196 case Mips::MOVZ_I_I64:
5197 case Mips::MUH:
5198 case Mips::MUHU:
5199 case Mips::MUL:
5200 case Mips::MULEQ_S_W_PHL:
5201 case Mips::MULEQ_S_W_PHR:
5202 case Mips::MULEU_S_PH_QBL:
5203 case Mips::MULEU_S_PH_QBR:
5204 case Mips::MULQ_RS_PH:
5205 case Mips::MULQ_RS_W:
5206 case Mips::MULQ_S_PH:
5207 case Mips::MULQ_S_W:
5208 case Mips::MULU:
5209 case Mips::MUL_PH:
5210 case Mips::MUL_R6:
5211 case Mips::MUL_S_PH:
5212 case Mips::NOR:
5213 case Mips::NOR64:
5214 case Mips::OR:
5215 case Mips::OR64:
5216 case Mips::SELEQZ:
5217 case Mips::SELEQZ64:
5218 case Mips::SELNEZ:
5219 case Mips::SELNEZ64:
5220 case Mips::SEQ:
5221 case Mips::SLT:
5222 case Mips::SLT64:
5223 case Mips::SLTu:
5224 case Mips::SLTu64:
5225 case Mips::SNE:
5226 case Mips::SUB:
5227 case Mips::SUBQH_PH:
5228 case Mips::SUBQH_R_PH:
5229 case Mips::SUBQH_R_W:
5230 case Mips::SUBQH_W:
5231 case Mips::SUBQ_PH:
5232 case Mips::SUBQ_S_PH:
5233 case Mips::SUBQ_S_W:
5234 case Mips::SUBUH_QB:
5235 case Mips::SUBUH_R_QB:
5236 case Mips::SUBU_PH:
5237 case Mips::SUBU_QB:
5238 case Mips::SUBU_S_PH:
5239 case Mips::SUBU_S_QB:
5240 case Mips::SUBu:
5241 case Mips::V3MULU:
5242 case Mips::VMM0:
5243 case Mips::VMULU:
5244 case Mips::XOR:
5245 case Mips::XOR64: {
5246 // op: rd
5247 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5248 op &= UINT64_C(31);
5249 op <<= 11;
5250 Value |= op;
5251 // op: rs
5252 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5253 op &= UINT64_C(31);
5254 op <<= 21;
5255 Value |= op;
5256 // op: rt
5257 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5258 op &= UINT64_C(31);
5259 op <<= 16;
5260 Value |= op;
5261 break;
5262 }
5263 case Mips::ALIGN: {
5264 // op: rd
5265 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5266 op &= UINT64_C(31);
5267 op <<= 11;
5268 Value |= op;
5269 // op: rs
5270 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5271 op &= UINT64_C(31);
5272 op <<= 21;
5273 Value |= op;
5274 // op: rt
5275 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5276 op &= UINT64_C(31);
5277 op <<= 16;
5278 Value |= op;
5279 // op: bp
5280 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
5281 op &= UINT64_C(3);
5282 op <<= 6;
5283 Value |= op;
5284 break;
5285 }
5286 case Mips::ALIGN_MMR6: {
5287 // op: rd
5288 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5289 op &= UINT64_C(31);
5290 op <<= 11;
5291 Value |= op;
5292 // op: rs
5293 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5294 op &= UINT64_C(31);
5295 op <<= 21;
5296 Value |= op;
5297 // op: rt
5298 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5299 op &= UINT64_C(31);
5300 op <<= 16;
5301 Value |= op;
5302 // op: bp
5303 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
5304 op &= UINT64_C(3);
5305 op <<= 9;
5306 Value |= op;
5307 break;
5308 }
5309 case Mips::DALIGN: {
5310 // op: rd
5311 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5312 op &= UINT64_C(31);
5313 op <<= 11;
5314 Value |= op;
5315 // op: rs
5316 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5317 op &= UINT64_C(31);
5318 op <<= 21;
5319 Value |= op;
5320 // op: rt
5321 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5322 op &= UINT64_C(31);
5323 op <<= 16;
5324 Value |= op;
5325 // op: bp
5326 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
5327 op &= UINT64_C(7);
5328 op <<= 6;
5329 Value |= op;
5330 break;
5331 }
5332 case Mips::DLSA_R6:
5333 case Mips::LSA_R6: {
5334 // op: rd
5335 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5336 op &= UINT64_C(31);
5337 op <<= 11;
5338 Value |= op;
5339 // op: rs
5340 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5341 op &= UINT64_C(31);
5342 op <<= 21;
5343 Value |= op;
5344 // op: rt
5345 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5346 op &= UINT64_C(31);
5347 op <<= 16;
5348 Value |= op;
5349 // op: imm2
5350 op = getUImmWithOffsetEncoding<2, 1>(MI, OpNo: 3, Fixups, STI);
5351 op &= UINT64_C(3);
5352 op <<= 6;
5353 Value |= op;
5354 break;
5355 }
5356 case Mips::SHLLV_PH_MM:
5357 case Mips::SHLLV_QB_MM:
5358 case Mips::SHLLV_S_PH_MM:
5359 case Mips::SHLLV_S_W_MM:
5360 case Mips::SHRAV_PH_MM:
5361 case Mips::SHRAV_QB_MMR2:
5362 case Mips::SHRAV_R_PH_MM:
5363 case Mips::SHRAV_R_QB_MMR2:
5364 case Mips::SHRAV_R_W_MM:
5365 case Mips::SHRLV_PH_MMR2:
5366 case Mips::SHRLV_QB_MM: {
5367 // op: rd
5368 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5369 op &= UINT64_C(31);
5370 op <<= 11;
5371 Value |= op;
5372 // op: rs
5373 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5374 op &= UINT64_C(31);
5375 op <<= 16;
5376 Value |= op;
5377 // op: rt
5378 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5379 op &= UINT64_C(31);
5380 op <<= 21;
5381 Value |= op;
5382 break;
5383 }
5384 case Mips::ABSQ_S_PH:
5385 case Mips::ABSQ_S_QB:
5386 case Mips::ABSQ_S_W:
5387 case Mips::BITREV:
5388 case Mips::BITSWAP:
5389 case Mips::DBITSWAP:
5390 case Mips::DSBH:
5391 case Mips::DSHD:
5392 case Mips::DSLL64_32:
5393 case Mips::PRECEQU_PH_QBL:
5394 case Mips::PRECEQU_PH_QBLA:
5395 case Mips::PRECEQU_PH_QBR:
5396 case Mips::PRECEQU_PH_QBRA:
5397 case Mips::PRECEQ_W_PHL:
5398 case Mips::PRECEQ_W_PHR:
5399 case Mips::PRECEU_PH_QBL:
5400 case Mips::PRECEU_PH_QBLA:
5401 case Mips::PRECEU_PH_QBR:
5402 case Mips::PRECEU_PH_QBRA:
5403 case Mips::REPLV_PH:
5404 case Mips::REPLV_QB:
5405 case Mips::SEB:
5406 case Mips::SEB64:
5407 case Mips::SEH:
5408 case Mips::SEH64:
5409 case Mips::SLL64_32:
5410 case Mips::SLL64_64:
5411 case Mips::WSBH: {
5412 // op: rd
5413 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5414 op &= UINT64_C(31);
5415 op <<= 11;
5416 Value |= op;
5417 // op: rt
5418 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5419 op &= UINT64_C(31);
5420 op <<= 16;
5421 Value |= op;
5422 break;
5423 }
5424 case Mips::DROTRV:
5425 case Mips::DSLLV:
5426 case Mips::DSRAV:
5427 case Mips::DSRLV:
5428 case Mips::ROTRV:
5429 case Mips::SLLV:
5430 case Mips::SRAV:
5431 case Mips::SRLV: {
5432 // op: rd
5433 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5434 op &= UINT64_C(31);
5435 op <<= 11;
5436 Value |= op;
5437 // op: rt
5438 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5439 op &= UINT64_C(31);
5440 op <<= 16;
5441 Value |= op;
5442 // op: rs
5443 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5444 op &= UINT64_C(31);
5445 op <<= 21;
5446 Value |= op;
5447 break;
5448 }
5449 case Mips::SHLLV_PH:
5450 case Mips::SHLLV_QB:
5451 case Mips::SHLLV_S_PH:
5452 case Mips::SHLLV_S_W:
5453 case Mips::SHLL_PH:
5454 case Mips::SHLL_QB:
5455 case Mips::SHLL_S_PH:
5456 case Mips::SHLL_S_W:
5457 case Mips::SHRAV_PH:
5458 case Mips::SHRAV_QB:
5459 case Mips::SHRAV_R_PH:
5460 case Mips::SHRAV_R_QB:
5461 case Mips::SHRAV_R_W:
5462 case Mips::SHRA_PH:
5463 case Mips::SHRA_QB:
5464 case Mips::SHRA_R_PH:
5465 case Mips::SHRA_R_QB:
5466 case Mips::SHRA_R_W:
5467 case Mips::SHRLV_PH:
5468 case Mips::SHRLV_QB:
5469 case Mips::SHRL_PH:
5470 case Mips::SHRL_QB: {
5471 // op: rd
5472 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5473 op &= UINT64_C(31);
5474 op <<= 11;
5475 Value |= op;
5476 // op: rt
5477 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5478 op &= UINT64_C(31);
5479 op <<= 16;
5480 Value |= op;
5481 // op: rs_sa
5482 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5483 op &= UINT64_C(31);
5484 op <<= 21;
5485 Value |= op;
5486 break;
5487 }
5488 case Mips::DROTR:
5489 case Mips::DROTR32:
5490 case Mips::DSLL:
5491 case Mips::DSLL32:
5492 case Mips::DSRA:
5493 case Mips::DSRA32:
5494 case Mips::DSRL:
5495 case Mips::DSRL32:
5496 case Mips::ROTR:
5497 case Mips::SLL:
5498 case Mips::SRA:
5499 case Mips::SRL: {
5500 // op: rd
5501 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5502 op &= UINT64_C(31);
5503 op <<= 11;
5504 Value |= op;
5505 // op: rt
5506 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5507 op &= UINT64_C(31);
5508 op <<= 16;
5509 Value |= op;
5510 // op: shamt
5511 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5512 op &= UINT64_C(31);
5513 op <<= 6;
5514 Value |= op;
5515 break;
5516 }
5517 case Mips::ROTRV_MM:
5518 case Mips::SLLV_MM:
5519 case Mips::SRAV_MM:
5520 case Mips::SRLV_MM: {
5521 // op: rd
5522 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5523 op &= UINT64_C(31);
5524 op <<= 11;
5525 Value |= op;
5526 // op: rt
5527 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5528 op &= UINT64_C(31);
5529 op <<= 21;
5530 Value |= op;
5531 // op: rs
5532 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5533 op &= UINT64_C(31);
5534 op <<= 16;
5535 Value |= op;
5536 break;
5537 }
5538 case Mips::ADDU_MMR6:
5539 case Mips::ADD_MMR6:
5540 case Mips::AND_MMR6:
5541 case Mips::DIVU_MMR6:
5542 case Mips::DIV_MMR6:
5543 case Mips::MODU_MMR6:
5544 case Mips::MOD_MMR6:
5545 case Mips::MUHU_MMR6:
5546 case Mips::MUH_MMR6:
5547 case Mips::MULU_MMR6:
5548 case Mips::MUL_MMR6:
5549 case Mips::NOR_MMR6:
5550 case Mips::OR_MMR6:
5551 case Mips::SUBU_MMR6:
5552 case Mips::SUB_MMR6:
5553 case Mips::XOR_MMR6: {
5554 // op: rd
5555 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5556 op &= UINT64_C(31);
5557 op <<= 11;
5558 Value |= op;
5559 // op: rt
5560 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5561 op &= UINT64_C(31);
5562 op <<= 21;
5563 Value |= op;
5564 // op: rs
5565 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5566 op &= UINT64_C(31);
5567 op <<= 16;
5568 Value |= op;
5569 break;
5570 }
5571 case Mips::MFHI_MM:
5572 case Mips::MFLO_MM: {
5573 // op: rd
5574 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5575 op &= UINT64_C(31);
5576 op <<= 16;
5577 Value |= op;
5578 break;
5579 }
5580 case Mips::BITSWAP_MMR6: {
5581 // op: rd
5582 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5583 op &= UINT64_C(31);
5584 op <<= 16;
5585 Value |= op;
5586 // op: rt
5587 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5588 op &= UINT64_C(31);
5589 op <<= 21;
5590 Value |= op;
5591 break;
5592 }
5593 case Mips::CLO_MM:
5594 case Mips::CLZ_MM: {
5595 // op: rd
5596 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5597 op &= UINT64_C(31);
5598 op <<= 21;
5599 Value |= op;
5600 // op: rs
5601 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5602 op &= UINT64_C(31);
5603 op <<= 16;
5604 Value |= op;
5605 break;
5606 }
5607 case Mips::MOVF_I_MM:
5608 case Mips::MOVT_I_MM: {
5609 // op: rd
5610 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5611 op &= UINT64_C(31);
5612 op <<= 21;
5613 Value |= op;
5614 // op: rs
5615 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5616 op &= UINT64_C(31);
5617 op <<= 16;
5618 Value |= op;
5619 // op: fcc
5620 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5621 op &= UINT64_C(7);
5622 op <<= 13;
5623 Value |= op;
5624 break;
5625 }
5626 case Mips::SEB_MM:
5627 case Mips::SEH_MM:
5628 case Mips::WSBH_MM: {
5629 // op: rd
5630 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5631 op &= UINT64_C(31);
5632 op <<= 21;
5633 Value |= op;
5634 // op: rt
5635 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5636 op &= UINT64_C(31);
5637 op <<= 16;
5638 Value |= op;
5639 break;
5640 }
5641 case Mips::ROTR_MM:
5642 case Mips::SLL_MM:
5643 case Mips::SLL_MMR6:
5644 case Mips::SRA_MM:
5645 case Mips::SRL_MM: {
5646 // op: rd
5647 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5648 op &= UINT64_C(31);
5649 op <<= 21;
5650 Value |= op;
5651 // op: rt
5652 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5653 op &= UINT64_C(31);
5654 op <<= 16;
5655 Value |= op;
5656 // op: shamt
5657 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5658 op &= UINT64_C(31);
5659 op <<= 11;
5660 Value |= op;
5661 break;
5662 }
5663 case Mips::CFCMSA: {
5664 // op: rd
5665 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5666 op &= UINT64_C(31);
5667 op <<= 6;
5668 Value |= op;
5669 // op: cs
5670 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5671 op &= UINT64_C(31);
5672 op <<= 11;
5673 Value |= op;
5674 break;
5675 }
5676 case Mips::LI16_MM:
5677 case Mips::LI16_MMR6: {
5678 // op: rd
5679 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5680 op &= UINT64_C(7);
5681 op <<= 7;
5682 Value |= op;
5683 // op: imm
5684 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5685 op &= UINT64_C(127);
5686 Value |= op;
5687 break;
5688 }
5689 case Mips::ADDIUR1SP_MM: {
5690 // op: rd
5691 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5692 op &= UINT64_C(7);
5693 op <<= 7;
5694 Value |= op;
5695 // op: imm
5696 op = getUImm6Lsl2Encoding(MI, OpNo: 1, Fixups, STI);
5697 op &= UINT64_C(63);
5698 op <<= 1;
5699 Value |= op;
5700 break;
5701 }
5702 case Mips::ADDIUR2_MM: {
5703 // op: rd
5704 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5705 op &= UINT64_C(7);
5706 op <<= 7;
5707 Value |= op;
5708 // op: rs
5709 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5710 op &= UINT64_C(7);
5711 op <<= 4;
5712 Value |= op;
5713 // op: imm
5714 op = getSImm3Lsa2Value(MI, OpNo: 2, Fixups, STI);
5715 op &= UINT64_C(7);
5716 op <<= 1;
5717 Value |= op;
5718 break;
5719 }
5720 case Mips::ANDI16_MM:
5721 case Mips::ANDI16_MMR6: {
5722 // op: rd
5723 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5724 op &= UINT64_C(7);
5725 op <<= 7;
5726 Value |= op;
5727 // op: rs
5728 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5729 op &= UINT64_C(7);
5730 op <<= 4;
5731 Value |= op;
5732 // op: imm
5733 op = getUImm4AndValue(MI, OpNo: 2, Fixups, STI);
5734 op &= UINT64_C(15);
5735 Value |= op;
5736 break;
5737 }
5738 case Mips::SLL16_MM:
5739 case Mips::SLL16_MMR6:
5740 case Mips::SRL16_MM:
5741 case Mips::SRL16_MMR6: {
5742 // op: rd
5743 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5744 op &= UINT64_C(7);
5745 op <<= 7;
5746 Value |= op;
5747 // op: rt
5748 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5749 op &= UINT64_C(7);
5750 op <<= 4;
5751 Value |= op;
5752 // op: shamt
5753 op = getUImm3Mod8Encoding(MI, OpNo: 2, Fixups, STI);
5754 op &= UINT64_C(7);
5755 op <<= 1;
5756 Value |= op;
5757 break;
5758 }
5759 case Mips::ADDU16_MM:
5760 case Mips::SUBU16_MM: {
5761 // op: rd
5762 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5763 op &= UINT64_C(7);
5764 op <<= 7;
5765 Value |= op;
5766 // op: rt
5767 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5768 op &= UINT64_C(7);
5769 op <<= 4;
5770 Value |= op;
5771 // op: rs
5772 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5773 op &= UINT64_C(7);
5774 op <<= 1;
5775 Value |= op;
5776 break;
5777 }
5778 case Mips::ADDIUS5_MM: {
5779 // op: rd
5780 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5781 op &= UINT64_C(31);
5782 op <<= 5;
5783 Value |= op;
5784 // op: imm
5785 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5786 op &= UINT64_C(15);
5787 op <<= 1;
5788 Value |= op;
5789 break;
5790 }
5791 case Mips::JALR16_MM:
5792 case Mips::JALRS16_MM:
5793 case Mips::JR16_MM:
5794 case Mips::JRC16_MM: {
5795 // op: rs
5796 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5797 op &= UINT64_C(31);
5798 Value |= op;
5799 break;
5800 }
5801 case Mips::DVP_MMR6:
5802 case Mips::EVP_MMR6:
5803 case Mips::GINVI_MMR6:
5804 case Mips::JR_MM:
5805 case Mips::MTHI_MM:
5806 case Mips::MTLO_MM: {
5807 // op: rs
5808 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5809 op &= UINT64_C(31);
5810 op <<= 16;
5811 Value |= op;
5812 break;
5813 }
5814 case Mips::MFHI_DSP_MM:
5815 case Mips::MFLO_DSP_MM: {
5816 // op: rs
5817 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5818 op &= UINT64_C(31);
5819 op <<= 16;
5820 Value |= op;
5821 // op: ac
5822 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5823 op &= UINT64_C(3);
5824 op <<= 14;
5825 Value |= op;
5826 break;
5827 }
5828 case Mips::TEQI_MM:
5829 case Mips::TGEIU_MM:
5830 case Mips::TGEI_MM:
5831 case Mips::TLTIU_MM:
5832 case Mips::TLTI_MM:
5833 case Mips::TNEI_MM: {
5834 // op: rs
5835 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5836 op &= UINT64_C(31);
5837 op <<= 16;
5838 Value |= op;
5839 // op: imm16
5840 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5841 op &= UINT64_C(65535);
5842 Value |= op;
5843 break;
5844 }
5845 case Mips::BEQZC_MM:
5846 case Mips::BGEZALS_MM:
5847 case Mips::BGEZAL_MM:
5848 case Mips::BGEZ_MM:
5849 case Mips::BGTZ_MM:
5850 case Mips::BLEZ_MM:
5851 case Mips::BLTZALS_MM:
5852 case Mips::BLTZAL_MM:
5853 case Mips::BLTZ_MM:
5854 case Mips::BNEZC_MM: {
5855 // op: rs
5856 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5857 op &= UINT64_C(31);
5858 op <<= 16;
5859 Value |= op;
5860 // op: offset
5861 op = getBranchTargetOpValueMM(MI, OpNo: 1, Fixups, STI);
5862 op &= UINT64_C(65535);
5863 Value |= op;
5864 break;
5865 }
5866 case Mips::MADDU_MM:
5867 case Mips::MADD_MM:
5868 case Mips::MSUBU_MM:
5869 case Mips::MSUB_MM:
5870 case Mips::MULT_MM:
5871 case Mips::MULTu_MM:
5872 case Mips::SDIV_MM:
5873 case Mips::UDIV_MM: {
5874 // op: rs
5875 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5876 op &= UINT64_C(31);
5877 op <<= 16;
5878 Value |= op;
5879 // op: rt
5880 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5881 op &= UINT64_C(31);
5882 op <<= 21;
5883 Value |= op;
5884 break;
5885 }
5886 case Mips::TEQ_MM:
5887 case Mips::TGEU_MM:
5888 case Mips::TGE_MM:
5889 case Mips::TLTU_MM:
5890 case Mips::TLT_MM:
5891 case Mips::TNE_MM: {
5892 // op: rs
5893 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5894 op &= UINT64_C(31);
5895 op <<= 16;
5896 Value |= op;
5897 // op: rt
5898 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5899 op &= UINT64_C(31);
5900 op <<= 21;
5901 Value |= op;
5902 // op: code_
5903 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5904 op &= UINT64_C(15);
5905 op <<= 12;
5906 Value |= op;
5907 break;
5908 }
5909 case Mips::BEQ_MM:
5910 case Mips::BNE_MM: {
5911 // op: rs
5912 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5913 op &= UINT64_C(31);
5914 op <<= 16;
5915 Value |= op;
5916 // op: rt
5917 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5918 op &= UINT64_C(31);
5919 op <<= 21;
5920 Value |= op;
5921 // op: offset
5922 op = getBranchTargetOpValueMM(MI, OpNo: 2, Fixups, STI);
5923 op &= UINT64_C(65535);
5924 Value |= op;
5925 break;
5926 }
5927 case Mips::GINVT_MMR6: {
5928 // op: rs
5929 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5930 op &= UINT64_C(31);
5931 op <<= 16;
5932 Value |= op;
5933 // op: type
5934 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5935 op &= UINT64_C(3);
5936 op <<= 9;
5937 Value |= op;
5938 break;
5939 }
5940 case Mips::GINVI:
5941 case Mips::JR:
5942 case Mips::JR64:
5943 case Mips::JR_HB:
5944 case Mips::JR_HB64:
5945 case Mips::JR_HB64_R6:
5946 case Mips::JR_HB_R6:
5947 case Mips::MTHI:
5948 case Mips::MTHI64:
5949 case Mips::MTLO:
5950 case Mips::MTLO64:
5951 case Mips::MTM0:
5952 case Mips::MTM1:
5953 case Mips::MTM2:
5954 case Mips::MTP0:
5955 case Mips::MTP1:
5956 case Mips::MTP2: {
5957 // op: rs
5958 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5959 op &= UINT64_C(31);
5960 op <<= 21;
5961 Value |= op;
5962 break;
5963 }
5964 case Mips::ALUIPC:
5965 case Mips::AUIPC: {
5966 // op: rs
5967 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5968 op &= UINT64_C(31);
5969 op <<= 21;
5970 Value |= op;
5971 // op: imm
5972 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5973 op &= UINT64_C(65535);
5974 Value |= op;
5975 break;
5976 }
5977 case Mips::DAHI:
5978 case Mips::DATI: {
5979 // op: rs
5980 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5981 op &= UINT64_C(31);
5982 op <<= 21;
5983 Value |= op;
5984 // op: imm
5985 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5986 op &= UINT64_C(65535);
5987 Value |= op;
5988 break;
5989 }
5990 case Mips::LDPC: {
5991 // op: rs
5992 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5993 op &= UINT64_C(31);
5994 op <<= 21;
5995 Value |= op;
5996 // op: imm
5997 op = getSimm18Lsl3Encoding(MI, OpNo: 1, Fixups, STI);
5998 op &= UINT64_C(262143);
5999 Value |= op;
6000 break;
6001 }
6002 case Mips::ADDIUPC:
6003 case Mips::LWPC:
6004 case Mips::LWUPC: {
6005 // op: rs
6006 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6007 op &= UINT64_C(31);
6008 op <<= 21;
6009 Value |= op;
6010 // op: imm
6011 op = getSimm19Lsl2Encoding(MI, OpNo: 1, Fixups, STI);
6012 op &= UINT64_C(524287);
6013 Value |= op;
6014 break;
6015 }
6016 case Mips::TEQI:
6017 case Mips::TGEI:
6018 case Mips::TGEIU:
6019 case Mips::TLTI:
6020 case Mips::TNEI:
6021 case Mips::TTLTIU: {
6022 // op: rs
6023 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6024 op &= UINT64_C(31);
6025 op <<= 21;
6026 Value |= op;
6027 // op: imm16
6028 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6029 op &= UINT64_C(65535);
6030 Value |= op;
6031 break;
6032 }
6033 case Mips::WRDSP: {
6034 // op: rs
6035 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6036 op &= UINT64_C(31);
6037 op <<= 21;
6038 Value |= op;
6039 // op: mask
6040 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6041 op &= UINT64_C(1023);
6042 op <<= 11;
6043 Value |= op;
6044 break;
6045 }
6046 case Mips::BEQZC:
6047 case Mips::BEQZC64:
6048 case Mips::BNEZC:
6049 case Mips::BNEZC64: {
6050 // op: rs
6051 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6052 op &= UINT64_C(31);
6053 op <<= 21;
6054 Value |= op;
6055 // op: offset
6056 op = getBranchTarget21OpValue(MI, OpNo: 1, Fixups, STI);
6057 op &= UINT64_C(2097151);
6058 Value |= op;
6059 break;
6060 }
6061 case Mips::BEQZC_MMR6:
6062 case Mips::BNEZC_MMR6: {
6063 // op: rs
6064 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6065 op &= UINT64_C(31);
6066 op <<= 21;
6067 Value |= op;
6068 // op: offset
6069 op = getBranchTarget21OpValueMM(MI, OpNo: 1, Fixups, STI);
6070 op &= UINT64_C(2097151);
6071 Value |= op;
6072 break;
6073 }
6074 case Mips::BGEZ:
6075 case Mips::BGEZ64:
6076 case Mips::BGEZAL:
6077 case Mips::BGEZALL:
6078 case Mips::BGEZL:
6079 case Mips::BGTZ:
6080 case Mips::BGTZ64:
6081 case Mips::BGTZL:
6082 case Mips::BLEZ:
6083 case Mips::BLEZ64:
6084 case Mips::BLEZL:
6085 case Mips::BLTZ:
6086 case Mips::BLTZ64:
6087 case Mips::BLTZAL:
6088 case Mips::BLTZALL:
6089 case Mips::BLTZL: {
6090 // op: rs
6091 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6092 op &= UINT64_C(31);
6093 op <<= 21;
6094 Value |= op;
6095 // op: offset
6096 op = getBranchTargetOpValue(MI, OpNo: 1, Fixups, STI);
6097 op &= UINT64_C(65535);
6098 Value |= op;
6099 break;
6100 }
6101 case Mips::BBIT0:
6102 case Mips::BBIT1:
6103 case Mips::BBIT032:
6104 case Mips::BBIT132: {
6105 // op: rs
6106 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6107 op &= UINT64_C(31);
6108 op <<= 21;
6109 Value |= op;
6110 // op: p
6111 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6112 op &= UINT64_C(31);
6113 op <<= 16;
6114 Value |= op;
6115 // op: offset
6116 op = getBranchTargetOpValue(MI, OpNo: 2, Fixups, STI);
6117 op &= UINT64_C(65535);
6118 Value |= op;
6119 break;
6120 }
6121 case Mips::CMPU_EQ_QB:
6122 case Mips::CMPU_LE_QB:
6123 case Mips::CMPU_LT_QB:
6124 case Mips::CMP_EQ_PH:
6125 case Mips::CMP_LE_PH:
6126 case Mips::CMP_LT_PH:
6127 case Mips::DMULT:
6128 case Mips::DMULTu:
6129 case Mips::DSDIV:
6130 case Mips::DUDIV:
6131 case Mips::MADD:
6132 case Mips::MADDU:
6133 case Mips::MSUB:
6134 case Mips::MSUBU:
6135 case Mips::MULT:
6136 case Mips::MULTu:
6137 case Mips::SDIV:
6138 case Mips::UDIV: {
6139 // op: rs
6140 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6141 op &= UINT64_C(31);
6142 op <<= 21;
6143 Value |= op;
6144 // op: rt
6145 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6146 op &= UINT64_C(31);
6147 op <<= 16;
6148 Value |= op;
6149 break;
6150 }
6151 case Mips::TEQ:
6152 case Mips::TGE:
6153 case Mips::TGEU:
6154 case Mips::TLT:
6155 case Mips::TLTU:
6156 case Mips::TNE: {
6157 // op: rs
6158 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6159 op &= UINT64_C(31);
6160 op <<= 21;
6161 Value |= op;
6162 // op: rt
6163 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6164 op &= UINT64_C(31);
6165 op <<= 16;
6166 Value |= op;
6167 // op: code_
6168 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6169 op &= UINT64_C(1023);
6170 op <<= 6;
6171 Value |= op;
6172 break;
6173 }
6174 case Mips::BEQ:
6175 case Mips::BEQ64:
6176 case Mips::BEQC:
6177 case Mips::BEQC64:
6178 case Mips::BEQL:
6179 case Mips::BGEC:
6180 case Mips::BGEC64:
6181 case Mips::BGEUC:
6182 case Mips::BGEUC64:
6183 case Mips::BLTC:
6184 case Mips::BLTC64:
6185 case Mips::BLTUC:
6186 case Mips::BLTUC64:
6187 case Mips::BNE:
6188 case Mips::BNE64:
6189 case Mips::BNEC:
6190 case Mips::BNEC64:
6191 case Mips::BNEL:
6192 case Mips::BNVC:
6193 case Mips::BOVC: {
6194 // op: rs
6195 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6196 op &= UINT64_C(31);
6197 op <<= 21;
6198 Value |= op;
6199 // op: rt
6200 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6201 op &= UINT64_C(31);
6202 op <<= 16;
6203 Value |= op;
6204 // op: offset
6205 op = getBranchTargetOpValue(MI, OpNo: 2, Fixups, STI);
6206 op &= UINT64_C(65535);
6207 Value |= op;
6208 break;
6209 }
6210 case Mips::FORK: {
6211 // op: rs
6212 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6213 op &= UINT64_C(31);
6214 op <<= 21;
6215 Value |= op;
6216 // op: rt
6217 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6218 op &= UINT64_C(31);
6219 op <<= 16;
6220 Value |= op;
6221 // op: rd
6222 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6223 op &= UINT64_C(31);
6224 op <<= 11;
6225 Value |= op;
6226 break;
6227 }
6228 case Mips::GINVT: {
6229 // op: rs
6230 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6231 op &= UINT64_C(31);
6232 op <<= 21;
6233 Value |= op;
6234 // op: type_
6235 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6236 op &= UINT64_C(3);
6237 op <<= 8;
6238 Value |= op;
6239 break;
6240 }
6241 case Mips::JALRC16_MMR6:
6242 case Mips::JRC16_MMR6: {
6243 // op: rs
6244 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6245 op &= UINT64_C(31);
6246 op <<= 5;
6247 Value |= op;
6248 break;
6249 }
6250 case Mips::ADDIUPC_MM: {
6251 // op: rs
6252 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6253 op &= UINT64_C(7);
6254 op <<= 23;
6255 Value |= op;
6256 // op: imm
6257 op = getSimm23Lsl2Encoding(MI, OpNo: 1, Fixups, STI);
6258 op &= UINT64_C(8388607);
6259 Value |= op;
6260 break;
6261 }
6262 case Mips::BEQZ16_MM:
6263 case Mips::BEQZC16_MMR6:
6264 case Mips::BNEZ16_MM:
6265 case Mips::BNEZC16_MMR6: {
6266 // op: rs
6267 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6268 op &= UINT64_C(7);
6269 op <<= 7;
6270 Value |= op;
6271 // op: offset
6272 op = getBranchTarget7OpValueMM(MI, OpNo: 1, Fixups, STI);
6273 op &= UINT64_C(127);
6274 Value |= op;
6275 break;
6276 }
6277 case Mips::MOVE16_MM:
6278 case Mips::MOVE16_MMR6: {
6279 // op: rs
6280 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6281 op &= UINT64_C(31);
6282 Value |= op;
6283 // op: rd
6284 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6285 op &= UINT64_C(31);
6286 op <<= 5;
6287 Value |= op;
6288 break;
6289 }
6290 case Mips::CTCMSA: {
6291 // op: rs
6292 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6293 op &= UINT64_C(31);
6294 op <<= 11;
6295 Value |= op;
6296 // op: cd
6297 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6298 op &= UINT64_C(31);
6299 op <<= 6;
6300 Value |= op;
6301 break;
6302 }
6303 case Mips::FILL_B:
6304 case Mips::FILL_D:
6305 case Mips::FILL_H:
6306 case Mips::FILL_W: {
6307 // op: rs
6308 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6309 op &= UINT64_C(31);
6310 op <<= 11;
6311 Value |= op;
6312 // op: wd
6313 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6314 op &= UINT64_C(31);
6315 op <<= 6;
6316 Value |= op;
6317 break;
6318 }
6319 case Mips::MTHI_DSP_MM:
6320 case Mips::MTHLIP_MM:
6321 case Mips::MTLO_DSP_MM:
6322 case Mips::SHILOV_MM: {
6323 // op: rs
6324 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6325 op &= UINT64_C(31);
6326 op <<= 16;
6327 Value |= op;
6328 // op: ac
6329 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6330 op &= UINT64_C(3);
6331 op <<= 14;
6332 Value |= op;
6333 break;
6334 }
6335 case Mips::JALRS_MM:
6336 case Mips::JALR_MM: {
6337 // op: rs
6338 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6339 op &= UINT64_C(31);
6340 op <<= 16;
6341 Value |= op;
6342 // op: rd
6343 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6344 op &= UINT64_C(31);
6345 op <<= 21;
6346 Value |= op;
6347 break;
6348 }
6349 case Mips::CLO_MMR6: {
6350 // op: rs
6351 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6352 op &= UINT64_C(31);
6353 op <<= 16;
6354 Value |= op;
6355 // op: rt
6356 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6357 op &= UINT64_C(31);
6358 op <<= 21;
6359 Value |= op;
6360 break;
6361 }
6362 case Mips::AUI_MMR6: {
6363 // op: rs
6364 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6365 op &= UINT64_C(31);
6366 op <<= 16;
6367 Value |= op;
6368 // op: rt
6369 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6370 op &= UINT64_C(31);
6371 op <<= 21;
6372 Value |= op;
6373 // op: imm
6374 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6375 op &= UINT64_C(65535);
6376 Value |= op;
6377 break;
6378 }
6379 case Mips::ADDi_MM:
6380 case Mips::ADDiu_MM:
6381 case Mips::ANDi_MM:
6382 case Mips::ORi_MM:
6383 case Mips::XORi_MM: {
6384 // op: rs
6385 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6386 op &= UINT64_C(31);
6387 op <<= 16;
6388 Value |= op;
6389 // op: rt
6390 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6391 op &= UINT64_C(31);
6392 op <<= 21;
6393 Value |= op;
6394 // op: imm16
6395 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6396 op &= UINT64_C(65535);
6397 Value |= op;
6398 break;
6399 }
6400 case Mips::MTHI_DSP:
6401 case Mips::MTLO_DSP: {
6402 // op: rs
6403 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6404 op &= UINT64_C(31);
6405 op <<= 21;
6406 Value |= op;
6407 // op: ac
6408 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6409 op &= UINT64_C(3);
6410 op <<= 11;
6411 Value |= op;
6412 break;
6413 }
6414 case Mips::YIELD: {
6415 // op: rs
6416 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6417 op &= UINT64_C(31);
6418 op <<= 21;
6419 Value |= op;
6420 // op: rd
6421 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6422 op &= UINT64_C(31);
6423 op <<= 11;
6424 Value |= op;
6425 break;
6426 }
6427 case Mips::CLZ_MMR6: {
6428 // op: rs
6429 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6430 op &= UINT64_C(31);
6431 op <<= 21;
6432 Value |= op;
6433 // op: rt
6434 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6435 op &= UINT64_C(31);
6436 op <<= 11;
6437 Value |= op;
6438 break;
6439 }
6440 case Mips::AUI:
6441 case Mips::DAUI: {
6442 // op: rs
6443 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6444 op &= UINT64_C(31);
6445 op <<= 21;
6446 Value |= op;
6447 // op: rt
6448 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6449 op &= UINT64_C(31);
6450 op <<= 16;
6451 Value |= op;
6452 // op: imm
6453 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6454 op &= UINT64_C(65535);
6455 Value |= op;
6456 break;
6457 }
6458 case Mips::SEQi:
6459 case Mips::SNEi: {
6460 // op: rs
6461 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6462 op &= UINT64_C(31);
6463 op <<= 21;
6464 Value |= op;
6465 // op: rt
6466 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6467 op &= UINT64_C(31);
6468 op <<= 16;
6469 Value |= op;
6470 // op: imm10
6471 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6472 op &= UINT64_C(1023);
6473 op <<= 6;
6474 Value |= op;
6475 break;
6476 }
6477 case Mips::ADDi:
6478 case Mips::ADDiu:
6479 case Mips::ANDi:
6480 case Mips::ANDi64:
6481 case Mips::DADDi:
6482 case Mips::DADDiu:
6483 case Mips::ORi:
6484 case Mips::ORi64:
6485 case Mips::XORi:
6486 case Mips::XORi64: {
6487 // op: rs
6488 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6489 op &= UINT64_C(31);
6490 op <<= 21;
6491 Value |= op;
6492 // op: rt
6493 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6494 op &= UINT64_C(31);
6495 op <<= 16;
6496 Value |= op;
6497 // op: imm16
6498 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6499 op &= UINT64_C(65535);
6500 Value |= op;
6501 break;
6502 }
6503 case Mips::PRECR_SRA_PH_W:
6504 case Mips::PRECR_SRA_R_PH_W: {
6505 // op: rs
6506 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6507 op &= UINT64_C(31);
6508 op <<= 21;
6509 Value |= op;
6510 // op: rt
6511 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6512 op &= UINT64_C(31);
6513 op <<= 16;
6514 Value |= op;
6515 // op: sa
6516 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6517 op &= UINT64_C(31);
6518 op <<= 11;
6519 Value |= op;
6520 break;
6521 }
6522 case Mips::CRC32B:
6523 case Mips::CRC32CB:
6524 case Mips::CRC32CD:
6525 case Mips::CRC32CH:
6526 case Mips::CRC32CW:
6527 case Mips::CRC32D:
6528 case Mips::CRC32H:
6529 case Mips::CRC32W: {
6530 // op: rs
6531 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6532 op &= UINT64_C(31);
6533 op <<= 21;
6534 Value |= op;
6535 // op: rt
6536 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6537 op &= UINT64_C(31);
6538 op <<= 16;
6539 Value |= op;
6540 break;
6541 }
6542 case Mips::CMPGDU_EQ_QB:
6543 case Mips::CMPGDU_LE_QB:
6544 case Mips::CMPGDU_LT_QB:
6545 case Mips::CMPGU_EQ_QB:
6546 case Mips::CMPGU_LE_QB:
6547 case Mips::CMPGU_LT_QB:
6548 case Mips::PACKRL_PH:
6549 case Mips::PICK_PH:
6550 case Mips::PICK_QB:
6551 case Mips::PRECRQU_S_QB_PH:
6552 case Mips::PRECRQ_PH_W:
6553 case Mips::PRECRQ_QB_PH:
6554 case Mips::PRECRQ_RS_PH_W:
6555 case Mips::PRECR_QB_PH: {
6556 // op: rs
6557 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6558 op &= UINT64_C(31);
6559 op <<= 21;
6560 Value |= op;
6561 // op: rt
6562 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6563 op &= UINT64_C(31);
6564 op <<= 16;
6565 Value |= op;
6566 // op: rd
6567 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6568 op &= UINT64_C(31);
6569 op <<= 11;
6570 Value |= op;
6571 break;
6572 }
6573 case Mips::DLSA:
6574 case Mips::LSA: {
6575 // op: rs
6576 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6577 op &= UINT64_C(31);
6578 op <<= 21;
6579 Value |= op;
6580 // op: rt
6581 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6582 op &= UINT64_C(31);
6583 op <<= 16;
6584 Value |= op;
6585 // op: rd
6586 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6587 op &= UINT64_C(31);
6588 op <<= 11;
6589 Value |= op;
6590 // op: sa
6591 op = getUImmWithOffsetEncoding<2, 1>(MI, OpNo: 3, Fixups, STI);
6592 op &= UINT64_C(3);
6593 op <<= 6;
6594 Value |= op;
6595 break;
6596 }
6597 case Mips::ADDU16_MMR6:
6598 case Mips::SUBU16_MMR6: {
6599 // op: rs
6600 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6601 op &= UINT64_C(7);
6602 op <<= 7;
6603 Value |= op;
6604 // op: rt
6605 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6606 op &= UINT64_C(7);
6607 op <<= 4;
6608 Value |= op;
6609 // op: rd
6610 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6611 op &= UINT64_C(7);
6612 op <<= 1;
6613 Value |= op;
6614 break;
6615 }
6616 case Mips::BGEZALC:
6617 case Mips::BGEZC:
6618 case Mips::BGEZC64:
6619 case Mips::BLTZALC:
6620 case Mips::BLTZC:
6621 case Mips::BLTZC64: {
6622 // op: rt
6623 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6624 Value |= (op & UINT64_C(31)) << 21;
6625 Value |= (op & UINT64_C(31)) << 16;
6626 // op: offset
6627 op = getBranchTargetOpValue(MI, OpNo: 1, Fixups, STI);
6628 op &= UINT64_C(65535);
6629 Value |= op;
6630 break;
6631 }
6632 case Mips::BGEZC_MMR6:
6633 case Mips::BLTZC_MMR6: {
6634 // op: rt
6635 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6636 Value |= (op & UINT64_C(31)) << 21;
6637 Value |= (op & UINT64_C(31)) << 16;
6638 // op: offset
6639 op = getBranchTargetOpValueLsl2MMR6(MI, OpNo: 1, Fixups, STI);
6640 op &= UINT64_C(65535);
6641 Value |= op;
6642 break;
6643 }
6644 case Mips::BGEZALC_MMR6:
6645 case Mips::BLTZALC_MMR6: {
6646 // op: rt
6647 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6648 Value |= (op & UINT64_C(31)) << 21;
6649 Value |= (op & UINT64_C(31)) << 16;
6650 // op: offset
6651 op = getBranchTargetOpValueMM(MI, OpNo: 1, Fixups, STI);
6652 op &= UINT64_C(65535);
6653 Value |= op;
6654 break;
6655 }
6656 case Mips::DI:
6657 case Mips::DI_MM:
6658 case Mips::DI_MMR6:
6659 case Mips::DMT:
6660 case Mips::DVP:
6661 case Mips::DVPE:
6662 case Mips::EI:
6663 case Mips::EI_MM:
6664 case Mips::EI_MMR6:
6665 case Mips::EMT:
6666 case Mips::EVP:
6667 case Mips::EVPE: {
6668 // op: rt
6669 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6670 op &= UINT64_C(31);
6671 op <<= 16;
6672 Value |= op;
6673 break;
6674 }
6675 case Mips::EXTP:
6676 case Mips::EXTPDP:
6677 case Mips::EXTPDPV:
6678 case Mips::EXTPV:
6679 case Mips::EXTRV_RS_W:
6680 case Mips::EXTRV_R_W:
6681 case Mips::EXTRV_S_H:
6682 case Mips::EXTRV_W:
6683 case Mips::EXTR_RS_W:
6684 case Mips::EXTR_R_W:
6685 case Mips::EXTR_S_H:
6686 case Mips::EXTR_W: {
6687 // op: rt
6688 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6689 op &= UINT64_C(31);
6690 op <<= 16;
6691 Value |= op;
6692 // op: ac
6693 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6694 op &= UINT64_C(3);
6695 op <<= 11;
6696 Value |= op;
6697 // op: shift_rs
6698 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6699 op &= UINT64_C(31);
6700 op <<= 21;
6701 Value |= op;
6702 break;
6703 }
6704 case Mips::LL64_R6:
6705 case Mips::LLD_R6:
6706 case Mips::LL_R6: {
6707 // op: rt
6708 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6709 op &= UINT64_C(31);
6710 op <<= 16;
6711 Value |= op;
6712 // op: addr
6713 op = getMemEncoding(MI, OpNo: 1, Fixups, STI);
6714 Value |= (op & UINT64_C(2031616)) << 5;
6715 Value |= (op & UINT64_C(511)) << 7;
6716 break;
6717 }
6718 case Mips::LB:
6719 case Mips::LB64:
6720 case Mips::LBu:
6721 case Mips::LBu64:
6722 case Mips::LD:
6723 case Mips::LDC1:
6724 case Mips::LDC2:
6725 case Mips::LDC3:
6726 case Mips::LDC164:
6727 case Mips::LDL:
6728 case Mips::LDR:
6729 case Mips::LEA_ADDiu:
6730 case Mips::LEA_ADDiu64:
6731 case Mips::LH:
6732 case Mips::LH64:
6733 case Mips::LHu:
6734 case Mips::LHu64:
6735 case Mips::LL:
6736 case Mips::LL64:
6737 case Mips::LLD:
6738 case Mips::LW:
6739 case Mips::LW64:
6740 case Mips::LWC1:
6741 case Mips::LWC2:
6742 case Mips::LWC3:
6743 case Mips::LWDSP:
6744 case Mips::LWL:
6745 case Mips::LWL64:
6746 case Mips::LWR:
6747 case Mips::LWR64:
6748 case Mips::LWu:
6749 case Mips::SB:
6750 case Mips::SB64:
6751 case Mips::SD:
6752 case Mips::SDC1:
6753 case Mips::SDC2:
6754 case Mips::SDC3:
6755 case Mips::SDC164:
6756 case Mips::SDL:
6757 case Mips::SDR:
6758 case Mips::SH:
6759 case Mips::SH64:
6760 case Mips::SW:
6761 case Mips::SW64:
6762 case Mips::SWC1:
6763 case Mips::SWC2:
6764 case Mips::SWC3:
6765 case Mips::SWDSP:
6766 case Mips::SWL:
6767 case Mips::SWL64:
6768 case Mips::SWR:
6769 case Mips::SWR64: {
6770 // op: rt
6771 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6772 op &= UINT64_C(31);
6773 op <<= 16;
6774 Value |= op;
6775 // op: addr
6776 op = getMemEncoding(MI, OpNo: 1, Fixups, STI);
6777 Value |= (op & UINT64_C(2031616)) << 5;
6778 Value |= (op & UINT64_C(65535));
6779 break;
6780 }
6781 case Mips::LDC2_R6:
6782 case Mips::LWC2_R6:
6783 case Mips::SDC2_R6:
6784 case Mips::SWC2_R6: {
6785 // op: rt
6786 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6787 op &= UINT64_C(31);
6788 op <<= 16;
6789 Value |= op;
6790 // op: addr
6791 op = getMemEncoding(MI, OpNo: 1, Fixups, STI);
6792 Value |= (op & UINT64_C(2031616)) >> 5;
6793 Value |= (op & UINT64_C(2047));
6794 break;
6795 }
6796 case Mips::CFC1:
6797 case Mips::DMFC1:
6798 case Mips::MFC1:
6799 case Mips::MFC1_D64:
6800 case Mips::MFHC1_D32:
6801 case Mips::MFHC1_D64: {
6802 // op: rt
6803 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6804 op &= UINT64_C(31);
6805 op <<= 16;
6806 Value |= op;
6807 // op: fs
6808 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6809 op &= UINT64_C(31);
6810 op <<= 11;
6811 Value |= op;
6812 break;
6813 }
6814 case Mips::DMFC2_OCTEON:
6815 case Mips::DMTC2_OCTEON:
6816 case Mips::LUi:
6817 case Mips::LUi64:
6818 case Mips::LUi_MM: {
6819 // op: rt
6820 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6821 op &= UINT64_C(31);
6822 op <<= 16;
6823 Value |= op;
6824 // op: imm16
6825 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6826 op &= UINT64_C(65535);
6827 Value |= op;
6828 break;
6829 }
6830 case Mips::BEQZALC:
6831 case Mips::BGTZALC:
6832 case Mips::BGTZC:
6833 case Mips::BGTZC64:
6834 case Mips::BLEZALC:
6835 case Mips::BLEZC:
6836 case Mips::BLEZC64:
6837 case Mips::BNEZALC: {
6838 // op: rt
6839 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6840 op &= UINT64_C(31);
6841 op <<= 16;
6842 Value |= op;
6843 // op: offset
6844 op = getBranchTargetOpValue(MI, OpNo: 1, Fixups, STI);
6845 op &= UINT64_C(65535);
6846 Value |= op;
6847 break;
6848 }
6849 case Mips::BC1EQZC_MMR6:
6850 case Mips::BC1NEZC_MMR6:
6851 case Mips::BC2EQZC_MMR6:
6852 case Mips::BC2NEZC_MMR6: {
6853 // op: rt
6854 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6855 op &= UINT64_C(31);
6856 op <<= 16;
6857 Value |= op;
6858 // op: offset
6859 op = getBranchTargetOpValueMM(MI, OpNo: 1, Fixups, STI);
6860 op &= UINT64_C(65535);
6861 Value |= op;
6862 break;
6863 }
6864 case Mips::JIALC:
6865 case Mips::JIALC64:
6866 case Mips::JIALC_MMR6:
6867 case Mips::JIC:
6868 case Mips::JIC64:
6869 case Mips::JIC_MMR6: {
6870 // op: rt
6871 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6872 op &= UINT64_C(31);
6873 op <<= 16;
6874 Value |= op;
6875 // op: offset
6876 op = getJumpOffset16OpValue(MI, OpNo: 1, Fixups, STI);
6877 op &= UINT64_C(65535);
6878 Value |= op;
6879 break;
6880 }
6881 case Mips::DMFC0:
6882 case Mips::DMFC2:
6883 case Mips::DMFGC0:
6884 case Mips::MFC0:
6885 case Mips::MFC2:
6886 case Mips::MFGC0:
6887 case Mips::MFHGC0: {
6888 // op: rt
6889 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6890 op &= UINT64_C(31);
6891 op <<= 16;
6892 Value |= op;
6893 // op: rd
6894 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6895 op &= UINT64_C(31);
6896 op <<= 11;
6897 Value |= op;
6898 // op: sel
6899 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6900 op &= UINT64_C(7);
6901 Value |= op;
6902 break;
6903 }
6904 case Mips::RDHWR:
6905 case Mips::RDHWR64: {
6906 // op: rt
6907 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6908 op &= UINT64_C(31);
6909 op <<= 16;
6910 Value |= op;
6911 // op: rd
6912 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6913 op &= UINT64_C(31);
6914 op <<= 11;
6915 Value |= op;
6916 // op: sel
6917 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6918 op &= UINT64_C(7);
6919 op <<= 6;
6920 Value |= op;
6921 break;
6922 }
6923 case Mips::SAA:
6924 case Mips::SAAD: {
6925 // op: rt
6926 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6927 op &= UINT64_C(31);
6928 op <<= 16;
6929 Value |= op;
6930 // op: rs
6931 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6932 op &= UINT64_C(31);
6933 op <<= 21;
6934 Value |= op;
6935 break;
6936 }
6937 case Mips::SLTi:
6938 case Mips::SLTi64:
6939 case Mips::SLTiu:
6940 case Mips::SLTiu64: {
6941 // op: rt
6942 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6943 op &= UINT64_C(31);
6944 op <<= 16;
6945 Value |= op;
6946 // op: rs
6947 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6948 op &= UINT64_C(31);
6949 op <<= 21;
6950 Value |= op;
6951 // op: imm16
6952 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6953 op &= UINT64_C(65535);
6954 Value |= op;
6955 break;
6956 }
6957 case Mips::CINS:
6958 case Mips::CINS32:
6959 case Mips::CINS64_32:
6960 case Mips::CINS_i32:
6961 case Mips::EXTS:
6962 case Mips::EXTS32: {
6963 // op: rt
6964 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6965 op &= UINT64_C(31);
6966 op <<= 16;
6967 Value |= op;
6968 // op: rs
6969 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6970 op &= UINT64_C(31);
6971 op <<= 21;
6972 Value |= op;
6973 // op: pos
6974 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6975 op &= UINT64_C(31);
6976 op <<= 6;
6977 Value |= op;
6978 // op: lenm1
6979 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
6980 op &= UINT64_C(31);
6981 op <<= 11;
6982 Value |= op;
6983 break;
6984 }
6985 case Mips::DINS:
6986 case Mips::DINSM:
6987 case Mips::DINSU:
6988 case Mips::INS: {
6989 // op: rt
6990 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6991 op &= UINT64_C(31);
6992 op <<= 16;
6993 Value |= op;
6994 // op: rs
6995 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6996 op &= UINT64_C(31);
6997 op <<= 21;
6998 Value |= op;
6999 // op: pos
7000 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7001 op &= UINT64_C(31);
7002 op <<= 6;
7003 Value |= op;
7004 // op: size
7005 op = getSizeInsEncoding(MI, OpNo: 3, Fixups, STI);
7006 op &= UINT64_C(31);
7007 op <<= 11;
7008 Value |= op;
7009 break;
7010 }
7011 case Mips::DEXT:
7012 case Mips::DEXT64_32:
7013 case Mips::DEXTM:
7014 case Mips::DEXTU:
7015 case Mips::EXT: {
7016 // op: rt
7017 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7018 op &= UINT64_C(31);
7019 op <<= 16;
7020 Value |= op;
7021 // op: rs
7022 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7023 op &= UINT64_C(31);
7024 op <<= 21;
7025 Value |= op;
7026 // op: pos
7027 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7028 op &= UINT64_C(31);
7029 op <<= 6;
7030 Value |= op;
7031 // op: size
7032 op = getUImmWithOffsetEncoding<5, 1>(MI, OpNo: 3, Fixups, STI);
7033 op &= UINT64_C(31);
7034 op <<= 11;
7035 Value |= op;
7036 break;
7037 }
7038 case Mips::APPEND:
7039 case Mips::BALIGN:
7040 case Mips::PREPEND: {
7041 // op: rt
7042 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7043 op &= UINT64_C(31);
7044 op <<= 16;
7045 Value |= op;
7046 // op: rs
7047 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7048 op &= UINT64_C(31);
7049 op <<= 21;
7050 Value |= op;
7051 // op: sa
7052 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7053 op &= UINT64_C(31);
7054 op <<= 11;
7055 Value |= op;
7056 break;
7057 }
7058 case Mips::INSV: {
7059 // op: rt
7060 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7061 op &= UINT64_C(31);
7062 op <<= 16;
7063 Value |= op;
7064 // op: rs
7065 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7066 op &= UINT64_C(31);
7067 op <<= 21;
7068 Value |= op;
7069 break;
7070 }
7071 case Mips::LWU_MM: {
7072 // op: rt
7073 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7074 op &= UINT64_C(31);
7075 op <<= 21;
7076 Value |= op;
7077 // op: addr
7078 op = getMemEncoding(MI, OpNo: 1, Fixups, STI);
7079 Value |= (op & UINT64_C(2031616));
7080 Value |= (op & UINT64_C(4095));
7081 break;
7082 }
7083 case Mips::LBE_MM:
7084 case Mips::LBuE_MM:
7085 case Mips::LHE_MM:
7086 case Mips::LHuE_MM:
7087 case Mips::LLE_MM:
7088 case Mips::LWE_MM:
7089 case Mips::SBE_MM:
7090 case Mips::SHE_MM:
7091 case Mips::SWE_MM: {
7092 // op: rt
7093 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7094 op &= UINT64_C(31);
7095 op <<= 21;
7096 Value |= op;
7097 // op: addr
7098 op = getMemEncoding(MI, OpNo: 1, Fixups, STI);
7099 Value |= (op & UINT64_C(2031616));
7100 Value |= (op & UINT64_C(511));
7101 break;
7102 }
7103 case Mips::LEA_ADDiu_MM:
7104 case Mips::LH_MM:
7105 case Mips::LHu_MM:
7106 case Mips::LWDSP_MM:
7107 case Mips::LW_MM:
7108 case Mips::LW_MMR6:
7109 case Mips::SB_MM:
7110 case Mips::SB_MMR6:
7111 case Mips::SH_MM:
7112 case Mips::SH_MMR6:
7113 case Mips::SWDSP_MM:
7114 case Mips::SW_MM:
7115 case Mips::SW_MMR6: {
7116 // op: rt
7117 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7118 op &= UINT64_C(31);
7119 op <<= 21;
7120 Value |= op;
7121 // op: addr
7122 op = getMemEncoding(MI, OpNo: 1, Fixups, STI);
7123 op &= UINT64_C(2097151);
7124 Value |= op;
7125 break;
7126 }
7127 case Mips::LWP_MM:
7128 case Mips::SWP_MM: {
7129 // op: rt
7130 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7131 op &= UINT64_C(31);
7132 op <<= 21;
7133 Value |= op;
7134 // op: addr
7135 op = getMemEncoding(MI, OpNo: 2, Fixups, STI);
7136 Value |= (op & UINT64_C(2031616));
7137 Value |= (op & UINT64_C(4095));
7138 break;
7139 }
7140 case Mips::LDC2_MMR6:
7141 case Mips::LWC2_MMR6:
7142 case Mips::SDC2_MMR6:
7143 case Mips::SWC2_MMR6: {
7144 // op: rt
7145 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7146 op &= UINT64_C(31);
7147 op <<= 21;
7148 Value |= op;
7149 // op: addr
7150 op = getMemEncodingMMImm11(MI, OpNo: 1, Fixups, STI);
7151 Value |= (op & UINT64_C(2031616));
7152 Value |= (op & UINT64_C(2047));
7153 break;
7154 }
7155 case Mips::LL_MM:
7156 case Mips::LWL_MM:
7157 case Mips::LWR_MM:
7158 case Mips::SWL_MM:
7159 case Mips::SWR_MM: {
7160 // op: rt
7161 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7162 op &= UINT64_C(31);
7163 op <<= 21;
7164 Value |= op;
7165 // op: addr
7166 op = getMemEncodingMMImm12(MI, OpNo: 1, Fixups, STI);
7167 Value |= (op & UINT64_C(2031616));
7168 Value |= (op & UINT64_C(4095));
7169 break;
7170 }
7171 case Mips::LB_MM:
7172 case Mips::LBu_MM:
7173 case Mips::LDC1_MM_D32:
7174 case Mips::LDC1_MM_D64:
7175 case Mips::LWC1_MM:
7176 case Mips::SDC1_MM_D32:
7177 case Mips::SDC1_MM_D64:
7178 case Mips::SWC1_MM: {
7179 // op: rt
7180 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7181 op &= UINT64_C(31);
7182 op <<= 21;
7183 Value |= op;
7184 // op: addr
7185 op = getMemEncodingMMImm16(MI, OpNo: 1, Fixups, STI);
7186 op &= UINT64_C(2097151);
7187 Value |= op;
7188 break;
7189 }
7190 case Mips::LL_MMR6:
7191 case Mips::LWLE_MM:
7192 case Mips::LWRE_MM:
7193 case Mips::SWLE_MM:
7194 case Mips::SWRE_MM: {
7195 // op: rt
7196 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7197 op &= UINT64_C(31);
7198 op <<= 21;
7199 Value |= op;
7200 // op: addr
7201 op = getMemEncodingMMImm9(MI, OpNo: 1, Fixups, STI);
7202 Value |= (op & UINT64_C(2031616));
7203 Value |= (op & UINT64_C(511));
7204 break;
7205 }
7206 case Mips::CFC1_MM:
7207 case Mips::MFC1_MM:
7208 case Mips::MFC1_MMR6:
7209 case Mips::MFHC1_D32_MM:
7210 case Mips::MFHC1_D64_MM: {
7211 // op: rt
7212 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7213 op &= UINT64_C(31);
7214 op <<= 21;
7215 Value |= op;
7216 // op: fs
7217 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7218 op &= UINT64_C(31);
7219 op <<= 16;
7220 Value |= op;
7221 break;
7222 }
7223 case Mips::REPL_QB_MM: {
7224 // op: rt
7225 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7226 op &= UINT64_C(31);
7227 op <<= 21;
7228 Value |= op;
7229 // op: imm
7230 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7231 op &= UINT64_C(255);
7232 op <<= 13;
7233 Value |= op;
7234 break;
7235 }
7236 case Mips::ALUIPC_MMR6:
7237 case Mips::AUIPC_MMR6: {
7238 // op: rt
7239 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7240 op &= UINT64_C(31);
7241 op <<= 21;
7242 Value |= op;
7243 // op: imm
7244 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7245 op &= UINT64_C(65535);
7246 Value |= op;
7247 break;
7248 }
7249 case Mips::EXTPDP_MM:
7250 case Mips::EXTP_MM:
7251 case Mips::EXTR_RS_W_MM:
7252 case Mips::EXTR_R_W_MM:
7253 case Mips::EXTR_S_H_MM:
7254 case Mips::EXTR_W_MM: {
7255 // op: rt
7256 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7257 op &= UINT64_C(31);
7258 op <<= 21;
7259 Value |= op;
7260 // op: imm
7261 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7262 op &= UINT64_C(31);
7263 op <<= 16;
7264 Value |= op;
7265 // op: ac
7266 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7267 op &= UINT64_C(3);
7268 op <<= 14;
7269 Value |= op;
7270 break;
7271 }
7272 case Mips::ADDIUPC_MMR6:
7273 case Mips::LWPC_MMR6: {
7274 // op: rt
7275 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7276 op &= UINT64_C(31);
7277 op <<= 21;
7278 Value |= op;
7279 // op: imm
7280 op = getSimm19Lsl2Encoding(MI, OpNo: 1, Fixups, STI);
7281 op &= UINT64_C(524287);
7282 Value |= op;
7283 break;
7284 }
7285 case Mips::LUI_MMR6: {
7286 // op: rt
7287 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7288 op &= UINT64_C(31);
7289 op <<= 21;
7290 Value |= op;
7291 // op: imm16
7292 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7293 op &= UINT64_C(65535);
7294 Value |= op;
7295 break;
7296 }
7297 case Mips::CFC2_MM:
7298 case Mips::MFC2_MMR6:
7299 case Mips::MFHC2_MMR6: {
7300 // op: rt
7301 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7302 op &= UINT64_C(31);
7303 op <<= 21;
7304 Value |= op;
7305 // op: impl
7306 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7307 op &= UINT64_C(31);
7308 op <<= 16;
7309 Value |= op;
7310 break;
7311 }
7312 case Mips::RDDSP_MM:
7313 case Mips::WRDSP_MM: {
7314 // op: rt
7315 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7316 op &= UINT64_C(31);
7317 op <<= 21;
7318 Value |= op;
7319 // op: mask
7320 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7321 op &= UINT64_C(127);
7322 op <<= 14;
7323 Value |= op;
7324 break;
7325 }
7326 case Mips::BGTZC_MMR6:
7327 case Mips::BLEZC_MMR6: {
7328 // op: rt
7329 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7330 op &= UINT64_C(31);
7331 op <<= 21;
7332 Value |= op;
7333 // op: offset
7334 op = getBranchTargetOpValueLsl2MMR6(MI, OpNo: 1, Fixups, STI);
7335 op &= UINT64_C(65535);
7336 Value |= op;
7337 break;
7338 }
7339 case Mips::BEQZALC_MMR6:
7340 case Mips::BGTZALC_MMR6:
7341 case Mips::BLEZALC_MMR6:
7342 case Mips::BNEZALC_MMR6: {
7343 // op: rt
7344 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7345 op &= UINT64_C(31);
7346 op <<= 21;
7347 Value |= op;
7348 // op: offset
7349 op = getBranchTargetOpValueMM(MI, OpNo: 1, Fixups, STI);
7350 op &= UINT64_C(65535);
7351 Value |= op;
7352 break;
7353 }
7354 case Mips::RDHWR_MM:
7355 case Mips::RDPGPR_MMR6: {
7356 // op: rt
7357 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7358 op &= UINT64_C(31);
7359 op <<= 21;
7360 Value |= op;
7361 // op: rd
7362 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7363 op &= UINT64_C(31);
7364 op <<= 16;
7365 Value |= op;
7366 break;
7367 }
7368 case Mips::ABSQ_S_PH_MM:
7369 case Mips::ABSQ_S_QB_MMR2:
7370 case Mips::ABSQ_S_W_MM:
7371 case Mips::BITREV_MM:
7372 case Mips::JALRC_HB_MMR6:
7373 case Mips::JALRC_MMR6:
7374 case Mips::PRECEQU_PH_QBLA_MM:
7375 case Mips::PRECEQU_PH_QBL_MM:
7376 case Mips::PRECEQU_PH_QBRA_MM:
7377 case Mips::PRECEQU_PH_QBR_MM:
7378 case Mips::PRECEQ_W_PHL_MM:
7379 case Mips::PRECEQ_W_PHR_MM:
7380 case Mips::PRECEU_PH_QBLA_MM:
7381 case Mips::PRECEU_PH_QBL_MM:
7382 case Mips::PRECEU_PH_QBRA_MM:
7383 case Mips::PRECEU_PH_QBR_MM:
7384 case Mips::RADDU_W_QB_MM:
7385 case Mips::REPLV_PH_MM:
7386 case Mips::REPLV_QB_MM:
7387 case Mips::WRPGPR_MMR6:
7388 case Mips::WSBH_MMR6: {
7389 // op: rt
7390 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7391 op &= UINT64_C(31);
7392 op <<= 21;
7393 Value |= op;
7394 // op: rs
7395 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7396 op &= UINT64_C(31);
7397 op <<= 16;
7398 Value |= op;
7399 break;
7400 }
7401 case Mips::BALIGN_MMR2: {
7402 // op: rt
7403 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7404 op &= UINT64_C(31);
7405 op <<= 21;
7406 Value |= op;
7407 // op: rs
7408 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7409 op &= UINT64_C(31);
7410 op <<= 16;
7411 Value |= op;
7412 // op: bp
7413 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7414 op &= UINT64_C(3);
7415 op <<= 14;
7416 Value |= op;
7417 break;
7418 }
7419 case Mips::ADDIU_MMR6:
7420 case Mips::ANDI_MMR6:
7421 case Mips::ORI_MMR6:
7422 case Mips::SLTi_MM:
7423 case Mips::SLTiu_MM:
7424 case Mips::XORI_MMR6: {
7425 // op: rt
7426 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7427 op &= UINT64_C(31);
7428 op <<= 21;
7429 Value |= op;
7430 // op: rs
7431 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7432 op &= UINT64_C(31);
7433 op <<= 16;
7434 Value |= op;
7435 // op: imm16
7436 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7437 op &= UINT64_C(65535);
7438 Value |= op;
7439 break;
7440 }
7441 case Mips::BNVC_MMR6:
7442 case Mips::BOVC_MMR6: {
7443 // op: rt
7444 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7445 op &= UINT64_C(31);
7446 op <<= 21;
7447 Value |= op;
7448 // op: rs
7449 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7450 op &= UINT64_C(31);
7451 op <<= 16;
7452 Value |= op;
7453 // op: offset
7454 op = getBranchTargetOpValueMMR6(MI, OpNo: 2, Fixups, STI);
7455 op &= UINT64_C(65535);
7456 Value |= op;
7457 break;
7458 }
7459 case Mips::INS_MM: {
7460 // op: rt
7461 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7462 op &= UINT64_C(31);
7463 op <<= 21;
7464 Value |= op;
7465 // op: rs
7466 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7467 op &= UINT64_C(31);
7468 op <<= 16;
7469 Value |= op;
7470 // op: pos
7471 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7472 op &= UINT64_C(31);
7473 op <<= 6;
7474 Value |= op;
7475 // op: size
7476 op = getSizeInsEncoding(MI, OpNo: 3, Fixups, STI);
7477 op &= UINT64_C(31);
7478 op <<= 11;
7479 Value |= op;
7480 break;
7481 }
7482 case Mips::EXT_MM: {
7483 // op: rt
7484 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7485 op &= UINT64_C(31);
7486 op <<= 21;
7487 Value |= op;
7488 // op: rs
7489 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7490 op &= UINT64_C(31);
7491 op <<= 16;
7492 Value |= op;
7493 // op: pos
7494 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7495 op &= UINT64_C(31);
7496 op <<= 6;
7497 Value |= op;
7498 // op: size
7499 op = getUImmWithOffsetEncoding<5, 1>(MI, OpNo: 3, Fixups, STI);
7500 op &= UINT64_C(31);
7501 op <<= 11;
7502 Value |= op;
7503 break;
7504 }
7505 case Mips::SHLL_PH_MM:
7506 case Mips::SHLL_S_PH_MM:
7507 case Mips::SHRA_PH_MM:
7508 case Mips::SHRA_R_PH_MM:
7509 case Mips::SHRL_PH_MMR2: {
7510 // op: rt
7511 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7512 op &= UINT64_C(31);
7513 op <<= 21;
7514 Value |= op;
7515 // op: rs
7516 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7517 op &= UINT64_C(31);
7518 op <<= 16;
7519 Value |= op;
7520 // op: sa
7521 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7522 op &= UINT64_C(15);
7523 op <<= 12;
7524 Value |= op;
7525 break;
7526 }
7527 case Mips::APPEND_MMR2:
7528 case Mips::PRECR_SRA_PH_W_MMR2:
7529 case Mips::PRECR_SRA_R_PH_W_MMR2:
7530 case Mips::PREPEND_MMR2:
7531 case Mips::SHLL_S_W_MM:
7532 case Mips::SHRA_R_W_MM: {
7533 // op: rt
7534 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7535 op &= UINT64_C(31);
7536 op <<= 21;
7537 Value |= op;
7538 // op: rs
7539 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7540 op &= UINT64_C(31);
7541 op <<= 16;
7542 Value |= op;
7543 // op: sa
7544 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7545 op &= UINT64_C(31);
7546 op <<= 11;
7547 Value |= op;
7548 break;
7549 }
7550 case Mips::SHLL_QB_MM:
7551 case Mips::SHRA_QB_MMR2:
7552 case Mips::SHRA_R_QB_MMR2:
7553 case Mips::SHRL_QB_MM: {
7554 // op: rt
7555 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7556 op &= UINT64_C(31);
7557 op <<= 21;
7558 Value |= op;
7559 // op: rs
7560 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7561 op &= UINT64_C(31);
7562 op <<= 16;
7563 Value |= op;
7564 // op: sa
7565 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7566 op &= UINT64_C(7);
7567 op <<= 13;
7568 Value |= op;
7569 break;
7570 }
7571 case Mips::MFC0_MMR6:
7572 case Mips::MFGC0_MM:
7573 case Mips::MFHC0_MMR6:
7574 case Mips::MFHGC0_MM:
7575 case Mips::RDHWR_MMR6: {
7576 // op: rt
7577 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7578 op &= UINT64_C(31);
7579 op <<= 21;
7580 Value |= op;
7581 // op: rs
7582 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7583 op &= UINT64_C(31);
7584 op <<= 16;
7585 Value |= op;
7586 // op: sel
7587 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7588 op &= UINT64_C(7);
7589 op <<= 11;
7590 Value |= op;
7591 break;
7592 }
7593 case Mips::INS_MMR6: {
7594 // op: rt
7595 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7596 op &= UINT64_C(31);
7597 op <<= 21;
7598 Value |= op;
7599 // op: rs
7600 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7601 op &= UINT64_C(31);
7602 op <<= 16;
7603 Value |= op;
7604 // op: size
7605 op = getSizeInsEncoding(MI, OpNo: 3, Fixups, STI);
7606 op &= UINT64_C(31);
7607 op <<= 11;
7608 Value |= op;
7609 // op: pos
7610 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7611 op &= UINT64_C(31);
7612 op <<= 6;
7613 Value |= op;
7614 break;
7615 }
7616 case Mips::EXT_MMR6: {
7617 // op: rt
7618 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7619 op &= UINT64_C(31);
7620 op <<= 21;
7621 Value |= op;
7622 // op: rs
7623 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7624 op &= UINT64_C(31);
7625 op <<= 16;
7626 Value |= op;
7627 // op: size
7628 op = getUImmWithOffsetEncoding<5, 1>(MI, OpNo: 3, Fixups, STI);
7629 op &= UINT64_C(31);
7630 op <<= 11;
7631 Value |= op;
7632 // op: pos
7633 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7634 op &= UINT64_C(31);
7635 op <<= 6;
7636 Value |= op;
7637 break;
7638 }
7639 case Mips::INSV_MM: {
7640 // op: rt
7641 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7642 op &= UINT64_C(31);
7643 op <<= 21;
7644 Value |= op;
7645 // op: rs
7646 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7647 op &= UINT64_C(31);
7648 op <<= 16;
7649 Value |= op;
7650 break;
7651 }
7652 case Mips::EXTPDPV_MM:
7653 case Mips::EXTPV_MM:
7654 case Mips::EXTRV_RS_W_MM:
7655 case Mips::EXTRV_R_W_MM:
7656 case Mips::EXTRV_S_H_MM:
7657 case Mips::EXTRV_W_MM: {
7658 // op: rt
7659 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7660 op &= UINT64_C(31);
7661 op <<= 21;
7662 Value |= op;
7663 // op: rs
7664 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7665 op &= UINT64_C(31);
7666 op <<= 16;
7667 Value |= op;
7668 // op: ac
7669 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7670 op &= UINT64_C(3);
7671 op <<= 14;
7672 Value |= op;
7673 break;
7674 }
7675 case Mips::LWSP_MM:
7676 case Mips::SWSP_MM:
7677 case Mips::SWSP_MMR6: {
7678 // op: rt
7679 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7680 op &= UINT64_C(31);
7681 op <<= 5;
7682 Value |= op;
7683 // op: offset
7684 op = getMemEncodingMMSPImm5Lsl2(MI, OpNo: 1, Fixups, STI);
7685 op &= UINT64_C(31);
7686 Value |= op;
7687 break;
7688 }
7689 case Mips::NOT16_MM: {
7690 // op: rt
7691 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7692 op &= UINT64_C(7);
7693 op <<= 3;
7694 Value |= op;
7695 // op: rs
7696 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7697 op &= UINT64_C(7);
7698 Value |= op;
7699 break;
7700 }
7701 case Mips::LBU16_MM:
7702 case Mips::SB16_MM:
7703 case Mips::SB16_MMR6: {
7704 // op: rt
7705 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7706 op &= UINT64_C(7);
7707 op <<= 7;
7708 Value |= op;
7709 // op: addr
7710 op = getMemEncodingMMImm4(MI, OpNo: 1, Fixups, STI);
7711 op &= UINT64_C(127);
7712 Value |= op;
7713 break;
7714 }
7715 case Mips::LHU16_MM:
7716 case Mips::SH16_MM:
7717 case Mips::SH16_MMR6: {
7718 // op: rt
7719 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7720 op &= UINT64_C(7);
7721 op <<= 7;
7722 Value |= op;
7723 // op: addr
7724 op = getMemEncodingMMImm4Lsl1(MI, OpNo: 1, Fixups, STI);
7725 op &= UINT64_C(127);
7726 Value |= op;
7727 break;
7728 }
7729 case Mips::LW16_MM:
7730 case Mips::SW16_MM:
7731 case Mips::SW16_MMR6: {
7732 // op: rt
7733 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7734 op &= UINT64_C(7);
7735 op <<= 7;
7736 Value |= op;
7737 // op: addr
7738 op = getMemEncodingMMImm4Lsl2(MI, OpNo: 1, Fixups, STI);
7739 op &= UINT64_C(127);
7740 Value |= op;
7741 break;
7742 }
7743 case Mips::LWGP_MM: {
7744 // op: rt
7745 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7746 op &= UINT64_C(7);
7747 op <<= 7;
7748 Value |= op;
7749 // op: offset
7750 op = getMemEncodingMMGPImm7Lsl2(MI, OpNo: 1, Fixups, STI);
7751 op &= UINT64_C(127);
7752 Value |= op;
7753 break;
7754 }
7755 case Mips::NOT16_MMR6: {
7756 // op: rt
7757 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7758 op &= UINT64_C(7);
7759 op <<= 7;
7760 Value |= op;
7761 // op: rs
7762 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7763 op &= UINT64_C(7);
7764 op <<= 4;
7765 Value |= op;
7766 break;
7767 }
7768 case Mips::SC64_R6:
7769 case Mips::SCD_R6:
7770 case Mips::SC_R6: {
7771 // op: rt
7772 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7773 op &= UINT64_C(31);
7774 op <<= 16;
7775 Value |= op;
7776 // op: addr
7777 op = getMemEncoding(MI, OpNo: 2, Fixups, STI);
7778 Value |= (op & UINT64_C(2031616)) << 5;
7779 Value |= (op & UINT64_C(511)) << 7;
7780 break;
7781 }
7782 case Mips::SC:
7783 case Mips::SC64:
7784 case Mips::SCD: {
7785 // op: rt
7786 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7787 op &= UINT64_C(31);
7788 op <<= 16;
7789 Value |= op;
7790 // op: addr
7791 op = getMemEncoding(MI, OpNo: 2, Fixups, STI);
7792 Value |= (op & UINT64_C(2031616)) << 5;
7793 Value |= (op & UINT64_C(65535));
7794 break;
7795 }
7796 case Mips::CTC1:
7797 case Mips::DMTC1:
7798 case Mips::MTC1:
7799 case Mips::MTC1_D64: {
7800 // op: rt
7801 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7802 op &= UINT64_C(31);
7803 op <<= 16;
7804 Value |= op;
7805 // op: fs
7806 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7807 op &= UINT64_C(31);
7808 op <<= 11;
7809 Value |= op;
7810 break;
7811 }
7812 case Mips::DMTC0:
7813 case Mips::DMTC2:
7814 case Mips::DMTGC0:
7815 case Mips::MTC0:
7816 case Mips::MTC2:
7817 case Mips::MTGC0:
7818 case Mips::MTHGC0: {
7819 // op: rt
7820 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7821 op &= UINT64_C(31);
7822 op <<= 16;
7823 Value |= op;
7824 // op: rd
7825 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7826 op &= UINT64_C(31);
7827 op <<= 11;
7828 Value |= op;
7829 // op: sel
7830 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7831 op &= UINT64_C(7);
7832 Value |= op;
7833 break;
7834 }
7835 case Mips::MFTR:
7836 case Mips::MTTR: {
7837 // op: rt
7838 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7839 op &= UINT64_C(31);
7840 op <<= 16;
7841 Value |= op;
7842 // op: rd
7843 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7844 op &= UINT64_C(31);
7845 op <<= 11;
7846 Value |= op;
7847 // op: u
7848 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7849 op &= UINT64_C(1);
7850 op <<= 5;
7851 Value |= op;
7852 // op: h
7853 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
7854 op &= UINT64_C(1);
7855 op <<= 4;
7856 Value |= op;
7857 // op: sel
7858 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
7859 op &= UINT64_C(7);
7860 Value |= op;
7861 break;
7862 }
7863 case Mips::SCE_MM: {
7864 // op: rt
7865 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7866 op &= UINT64_C(31);
7867 op <<= 21;
7868 Value |= op;
7869 // op: addr
7870 op = getMemEncoding(MI, OpNo: 2, Fixups, STI);
7871 Value |= (op & UINT64_C(2031616));
7872 Value |= (op & UINT64_C(511));
7873 break;
7874 }
7875 case Mips::SC_MM: {
7876 // op: rt
7877 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7878 op &= UINT64_C(31);
7879 op <<= 21;
7880 Value |= op;
7881 // op: addr
7882 op = getMemEncodingMMImm12(MI, OpNo: 2, Fixups, STI);
7883 Value |= (op & UINT64_C(2031616));
7884 Value |= (op & UINT64_C(4095));
7885 break;
7886 }
7887 case Mips::SC_MMR6: {
7888 // op: rt
7889 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7890 op &= UINT64_C(31);
7891 op <<= 21;
7892 Value |= op;
7893 // op: addr
7894 op = getMemEncodingMMImm9(MI, OpNo: 2, Fixups, STI);
7895 Value |= (op & UINT64_C(2031616));
7896 Value |= (op & UINT64_C(511));
7897 break;
7898 }
7899 case Mips::CTC1_MM:
7900 case Mips::MTC1_D64_MM:
7901 case Mips::MTC1_MM:
7902 case Mips::MTC1_MMR6: {
7903 // op: rt
7904 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7905 op &= UINT64_C(31);
7906 op <<= 21;
7907 Value |= op;
7908 // op: fs
7909 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7910 op &= UINT64_C(31);
7911 op <<= 16;
7912 Value |= op;
7913 break;
7914 }
7915 case Mips::CTC2_MM:
7916 case Mips::MTC2_MMR6:
7917 case Mips::MTHC2_MMR6: {
7918 // op: rt
7919 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7920 op &= UINT64_C(31);
7921 op <<= 21;
7922 Value |= op;
7923 // op: impl
7924 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7925 op &= UINT64_C(31);
7926 op <<= 16;
7927 Value |= op;
7928 break;
7929 }
7930 case Mips::CMPU_EQ_QB_MM:
7931 case Mips::CMPU_LE_QB_MM:
7932 case Mips::CMPU_LT_QB_MM:
7933 case Mips::CMP_EQ_PH_MM:
7934 case Mips::CMP_LE_PH_MM:
7935 case Mips::CMP_LT_PH_MM: {
7936 // op: rt
7937 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7938 op &= UINT64_C(31);
7939 op <<= 21;
7940 Value |= op;
7941 // op: rs
7942 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7943 op &= UINT64_C(31);
7944 op <<= 16;
7945 Value |= op;
7946 break;
7947 }
7948 case Mips::BEQC_MMR6:
7949 case Mips::BGEC_MMR6:
7950 case Mips::BGEUC_MMR6:
7951 case Mips::BLTC_MMR6:
7952 case Mips::BLTUC_MMR6:
7953 case Mips::BNEC_MMR6: {
7954 // op: rt
7955 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7956 op &= UINT64_C(31);
7957 op <<= 21;
7958 Value |= op;
7959 // op: rs
7960 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7961 op &= UINT64_C(31);
7962 op <<= 16;
7963 Value |= op;
7964 // op: offset
7965 op = getBranchTargetOpValueLsl2MMR6(MI, OpNo: 2, Fixups, STI);
7966 op &= UINT64_C(65535);
7967 Value |= op;
7968 break;
7969 }
7970 case Mips::MTC0_MMR6:
7971 case Mips::MTGC0_MM:
7972 case Mips::MTHC0_MMR6:
7973 case Mips::MTHGC0_MM: {
7974 // op: rt
7975 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7976 op &= UINT64_C(31);
7977 op <<= 21;
7978 Value |= op;
7979 // op: rs
7980 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7981 op &= UINT64_C(31);
7982 op <<= 16;
7983 Value |= op;
7984 // op: sel
7985 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7986 op &= UINT64_C(7);
7987 op <<= 11;
7988 Value |= op;
7989 break;
7990 }
7991 case Mips::MTHC1_D32:
7992 case Mips::MTHC1_D64: {
7993 // op: rt
7994 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7995 op &= UINT64_C(31);
7996 op <<= 16;
7997 Value |= op;
7998 // op: fs
7999 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8000 op &= UINT64_C(31);
8001 op <<= 11;
8002 Value |= op;
8003 break;
8004 }
8005 case Mips::SPLAT_B:
8006 case Mips::SPLAT_D:
8007 case Mips::SPLAT_H:
8008 case Mips::SPLAT_W: {
8009 // op: rt
8010 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8011 op &= UINT64_C(31);
8012 op <<= 16;
8013 Value |= op;
8014 // op: ws
8015 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8016 op &= UINT64_C(31);
8017 op <<= 11;
8018 Value |= op;
8019 // op: wd
8020 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8021 op &= UINT64_C(31);
8022 op <<= 6;
8023 Value |= op;
8024 break;
8025 }
8026 case Mips::MTHC1_D32_MM:
8027 case Mips::MTHC1_D64_MM: {
8028 // op: rt
8029 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8030 op &= UINT64_C(31);
8031 op <<= 21;
8032 Value |= op;
8033 // op: fs
8034 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8035 op &= UINT64_C(31);
8036 op <<= 16;
8037 Value |= op;
8038 break;
8039 }
8040 case Mips::DPAQX_SA_W_PH_MMR2:
8041 case Mips::DPAQX_S_W_PH_MMR2:
8042 case Mips::DPAQ_SA_L_W_MM:
8043 case Mips::DPAQ_S_W_PH_MM:
8044 case Mips::DPAU_H_QBL_MM:
8045 case Mips::DPAU_H_QBR_MM:
8046 case Mips::DPAX_W_PH_MMR2:
8047 case Mips::DPA_W_PH_MMR2:
8048 case Mips::DPSQX_SA_W_PH_MMR2:
8049 case Mips::DPSQX_S_W_PH_MMR2:
8050 case Mips::DPSQ_SA_L_W_MM:
8051 case Mips::DPSQ_S_W_PH_MM:
8052 case Mips::DPSU_H_QBL_MM:
8053 case Mips::DPSU_H_QBR_MM:
8054 case Mips::DPSX_W_PH_MMR2:
8055 case Mips::DPS_W_PH_MMR2:
8056 case Mips::MADDU_DSP_MM:
8057 case Mips::MADD_DSP_MM:
8058 case Mips::MAQ_SA_W_PHL_MM:
8059 case Mips::MAQ_SA_W_PHR_MM:
8060 case Mips::MAQ_S_W_PHL_MM:
8061 case Mips::MAQ_S_W_PHR_MM:
8062 case Mips::MSUBU_DSP_MM:
8063 case Mips::MSUB_DSP_MM:
8064 case Mips::MULSAQ_S_W_PH_MM:
8065 case Mips::MULSA_W_PH_MMR2:
8066 case Mips::MULTU_DSP_MM:
8067 case Mips::MULT_DSP_MM: {
8068 // op: rt
8069 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8070 op &= UINT64_C(31);
8071 op <<= 21;
8072 Value |= op;
8073 // op: rs
8074 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8075 op &= UINT64_C(31);
8076 op <<= 16;
8077 Value |= op;
8078 // op: ac
8079 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8080 op &= UINT64_C(3);
8081 op <<= 14;
8082 Value |= op;
8083 break;
8084 }
8085 case Mips::ADD_MM:
8086 case Mips::ADDu_MM:
8087 case Mips::AND_MM:
8088 case Mips::CMPGU_EQ_QB_MM:
8089 case Mips::CMPGU_LE_QB_MM:
8090 case Mips::CMPGU_LT_QB_MM:
8091 case Mips::MOVN_I_MM:
8092 case Mips::MOVZ_I_MM:
8093 case Mips::MUL_MM:
8094 case Mips::NOR_MM:
8095 case Mips::OR_MM:
8096 case Mips::SLT_MM:
8097 case Mips::SLTu_MM:
8098 case Mips::SUB_MM:
8099 case Mips::SUBu_MM:
8100 case Mips::XOR_MM: {
8101 // op: rt
8102 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8103 op &= UINT64_C(31);
8104 op <<= 21;
8105 Value |= op;
8106 // op: rs
8107 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8108 op &= UINT64_C(31);
8109 op <<= 16;
8110 Value |= op;
8111 // op: rd
8112 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8113 op &= UINT64_C(31);
8114 op <<= 11;
8115 Value |= op;
8116 break;
8117 }
8118 case Mips::AND16_MM:
8119 case Mips::OR16_MM:
8120 case Mips::XOR16_MM: {
8121 // op: rt
8122 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8123 op &= UINT64_C(7);
8124 op <<= 3;
8125 Value |= op;
8126 // op: rs
8127 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8128 op &= UINT64_C(7);
8129 Value |= op;
8130 break;
8131 }
8132 case Mips::AND16_MMR6:
8133 case Mips::OR16_MMR6:
8134 case Mips::XOR16_MMR6: {
8135 // op: rt
8136 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8137 op &= UINT64_C(7);
8138 op <<= 7;
8139 Value |= op;
8140 // op: rs
8141 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8142 op &= UINT64_C(7);
8143 op <<= 4;
8144 Value |= op;
8145 break;
8146 }
8147 case Mips::SLD_B:
8148 case Mips::SLD_D:
8149 case Mips::SLD_H:
8150 case Mips::SLD_W: {
8151 // op: rt
8152 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
8153 op &= UINT64_C(31);
8154 op <<= 16;
8155 Value |= op;
8156 // op: ws
8157 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8158 op &= UINT64_C(31);
8159 op <<= 11;
8160 Value |= op;
8161 // op: wd
8162 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8163 op &= UINT64_C(31);
8164 op <<= 6;
8165 Value |= op;
8166 break;
8167 }
8168 case Mips::MOVEP_MMR6: {
8169 // op: rt
8170 op = getMovePRegSingleOpValue(MI, OpNo: 3, Fixups, STI);
8171 op &= UINT64_C(7);
8172 op <<= 4;
8173 Value |= op;
8174 // op: rs
8175 op = getMovePRegSingleOpValue(MI, OpNo: 2, Fixups, STI);
8176 Value |= (op & UINT64_C(4)) << 1;
8177 Value |= (op & UINT64_C(3));
8178 break;
8179 }
8180 case Mips::MOVEP_MM: {
8181 // op: rt
8182 op = getMovePRegSingleOpValue(MI, OpNo: 3, Fixups, STI);
8183 op &= UINT64_C(7);
8184 op <<= 4;
8185 Value |= op;
8186 // op: rs
8187 op = getMovePRegSingleOpValue(MI, OpNo: 2, Fixups, STI);
8188 op &= UINT64_C(7);
8189 op <<= 1;
8190 Value |= op;
8191 break;
8192 }
8193 case Mips::LWM32_MM:
8194 case Mips::SWM32_MM: {
8195 // op: rt
8196 op = getRegisterListOpValue(MI, OpNo: 0, Fixups, STI);
8197 op &= UINT64_C(31);
8198 op <<= 21;
8199 Value |= op;
8200 // op: addr
8201 op = getMemEncodingMMImm12(MI, OpNo: 1, Fixups, STI);
8202 Value |= (op & UINT64_C(2031616));
8203 Value |= (op & UINT64_C(4095));
8204 break;
8205 }
8206 case Mips::LWM16_MM:
8207 case Mips::SWM16_MM: {
8208 // op: rt
8209 op = getRegisterListOpValue16(MI, OpNo: 0, Fixups, STI);
8210 op &= UINT64_C(3);
8211 op <<= 4;
8212 Value |= op;
8213 // op: addr
8214 op = getMemEncodingMMImm4sp(MI, OpNo: 1, Fixups, STI);
8215 op &= UINT64_C(15);
8216 Value |= op;
8217 break;
8218 }
8219 case Mips::LWM16_MMR6:
8220 case Mips::SWM16_MMR6: {
8221 // op: rt
8222 op = getRegisterListOpValue16(MI, OpNo: 0, Fixups, STI);
8223 op &= UINT64_C(3);
8224 op <<= 8;
8225 Value |= op;
8226 // op: addr
8227 op = getMemEncodingMMImm4sp(MI, OpNo: 1, Fixups, STI);
8228 op &= UINT64_C(15);
8229 op <<= 4;
8230 Value |= op;
8231 break;
8232 }
8233 case Mips::JumpLinkReg16:
8234 case Mips::Mfhi16:
8235 case Mips::Mflo16:
8236 case Mips::SebRx16:
8237 case Mips::SehRx16: {
8238 // op: rx
8239 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8240 op &= UINT64_C(7);
8241 op <<= 8;
8242 Value |= op;
8243 break;
8244 }
8245 case Mips::BeqzRxImm16:
8246 case Mips::BnezRxImm16: {
8247 // op: rx
8248 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8249 op &= UINT64_C(7);
8250 op <<= 8;
8251 Value |= op;
8252 // op: imm8
8253 op = getBranchTargetOpValue(MI, OpNo: 1, Fixups, STI);
8254 op &= UINT64_C(255);
8255 Value |= op;
8256 break;
8257 }
8258 case Mips::CmpiRxImm16:
8259 case Mips::LiRxImm16:
8260 case Mips::LwRxPcTcp16:
8261 case Mips::SltiRxImm16:
8262 case Mips::SltiuRxImm16: {
8263 // op: rx
8264 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8265 op &= UINT64_C(7);
8266 op <<= 8;
8267 Value |= op;
8268 // op: imm8
8269 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8270 op &= UINT64_C(255);
8271 Value |= op;
8272 break;
8273 }
8274 case Mips::AddiuRxRxImm16: {
8275 // op: rx
8276 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8277 op &= UINT64_C(7);
8278 op <<= 8;
8279 Value |= op;
8280 // op: imm8
8281 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8282 op &= UINT64_C(255);
8283 Value |= op;
8284 break;
8285 }
8286 case Mips::CmpRxRy16:
8287 case Mips::DivRxRy16:
8288 case Mips::DivuRxRy16:
8289 case Mips::NegRxRy16:
8290 case Mips::NotRxRy16:
8291 case Mips::SltRxRy16:
8292 case Mips::SltuRxRy16: {
8293 // op: rx
8294 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8295 op &= UINT64_C(7);
8296 op <<= 8;
8297 Value |= op;
8298 // op: ry
8299 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8300 op &= UINT64_C(7);
8301 op <<= 5;
8302 Value |= op;
8303 break;
8304 }
8305 case Mips::AndRxRxRy16:
8306 case Mips::OrRxRxRy16:
8307 case Mips::SllvRxRy16:
8308 case Mips::SravRxRy16:
8309 case Mips::SrlvRxRy16:
8310 case Mips::XorRxRxRy16: {
8311 // op: rx
8312 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8313 op &= UINT64_C(7);
8314 op <<= 8;
8315 Value |= op;
8316 // op: ry
8317 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8318 op &= UINT64_C(7);
8319 op <<= 5;
8320 Value |= op;
8321 break;
8322 }
8323 case Mips::AdduRxRyRz16:
8324 case Mips::SubuRxRyRz16: {
8325 // op: rx
8326 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8327 op &= UINT64_C(7);
8328 op <<= 8;
8329 Value |= op;
8330 // op: ry
8331 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8332 op &= UINT64_C(7);
8333 op <<= 5;
8334 Value |= op;
8335 // op: rz
8336 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8337 op &= UINT64_C(7);
8338 op <<= 2;
8339 Value |= op;
8340 break;
8341 }
8342 case Mips::MoveR3216: {
8343 // op: ry
8344 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8345 op &= UINT64_C(15);
8346 op <<= 4;
8347 Value |= op;
8348 // op: r32
8349 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8350 op &= UINT64_C(15);
8351 Value |= op;
8352 break;
8353 }
8354 case Mips::LDI_B:
8355 case Mips::LDI_D:
8356 case Mips::LDI_H:
8357 case Mips::LDI_W: {
8358 // op: s10
8359 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8360 op &= UINT64_C(1023);
8361 op <<= 11;
8362 Value |= op;
8363 // op: wd
8364 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8365 op &= UINT64_C(31);
8366 op <<= 6;
8367 Value |= op;
8368 break;
8369 }
8370 case Mips::SllX16:
8371 case Mips::SraX16:
8372 case Mips::SrlX16: {
8373 // op: sa6
8374 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8375 Value |= (op & UINT64_C(31)) << 22;
8376 Value |= (op & UINT64_C(32)) << 16;
8377 // op: rx
8378 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8379 op &= UINT64_C(7);
8380 op <<= 8;
8381 Value |= op;
8382 // op: ry
8383 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8384 op &= UINT64_C(7);
8385 op <<= 5;
8386 Value |= op;
8387 break;
8388 }
8389 case Mips::SHILO_MM: {
8390 // op: shift
8391 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8392 op &= UINT64_C(63);
8393 op <<= 16;
8394 Value |= op;
8395 // op: ac
8396 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8397 op &= UINT64_C(3);
8398 op <<= 14;
8399 Value |= op;
8400 break;
8401 }
8402 case Mips::SYNC_MM:
8403 case Mips::SYNC_MMR6: {
8404 // op: stype
8405 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8406 op &= UINT64_C(31);
8407 op <<= 16;
8408 Value |= op;
8409 break;
8410 }
8411 case Mips::SYNC: {
8412 // op: stype
8413 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8414 op &= UINT64_C(31);
8415 op <<= 6;
8416 Value |= op;
8417 break;
8418 }
8419 case Mips::J:
8420 case Mips::JAL:
8421 case Mips::JALX:
8422 case Mips::JALX_MM: {
8423 // op: target
8424 op = getJumpTargetOpValue(MI, OpNo: 0, Fixups, STI);
8425 op &= UINT64_C(67108863);
8426 Value |= op;
8427 break;
8428 }
8429 case Mips::JALS_MM:
8430 case Mips::JAL_MM:
8431 case Mips::J_MM: {
8432 // op: target
8433 op = getJumpTargetOpValueMM(MI, OpNo: 0, Fixups, STI);
8434 op &= UINT64_C(67108863);
8435 Value |= op;
8436 break;
8437 }
8438 case Mips::ANDI_B:
8439 case Mips::NORI_B:
8440 case Mips::ORI_B:
8441 case Mips::SHF_B:
8442 case Mips::SHF_H:
8443 case Mips::SHF_W:
8444 case Mips::XORI_B: {
8445 // op: u8
8446 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8447 op &= UINT64_C(255);
8448 op <<= 16;
8449 Value |= op;
8450 // op: ws
8451 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8452 op &= UINT64_C(31);
8453 op <<= 11;
8454 Value |= op;
8455 // op: wd
8456 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8457 op &= UINT64_C(31);
8458 op <<= 6;
8459 Value |= op;
8460 break;
8461 }
8462 case Mips::BMNZI_B:
8463 case Mips::BMZI_B:
8464 case Mips::BSELI_B: {
8465 // op: u8
8466 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
8467 op &= UINT64_C(255);
8468 op <<= 16;
8469 Value |= op;
8470 // op: ws
8471 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8472 op &= UINT64_C(31);
8473 op <<= 11;
8474 Value |= op;
8475 // op: wd
8476 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8477 op &= UINT64_C(31);
8478 op <<= 6;
8479 Value |= op;
8480 break;
8481 }
8482 case Mips::FCLASS_D:
8483 case Mips::FCLASS_W:
8484 case Mips::FEXUPL_D:
8485 case Mips::FEXUPL_W:
8486 case Mips::FEXUPR_D:
8487 case Mips::FEXUPR_W:
8488 case Mips::FFINT_S_D:
8489 case Mips::FFINT_S_W:
8490 case Mips::FFINT_U_D:
8491 case Mips::FFINT_U_W:
8492 case Mips::FFQL_D:
8493 case Mips::FFQL_W:
8494 case Mips::FFQR_D:
8495 case Mips::FFQR_W:
8496 case Mips::FLOG2_D:
8497 case Mips::FLOG2_W:
8498 case Mips::FRCP_D:
8499 case Mips::FRCP_W:
8500 case Mips::FRINT_D:
8501 case Mips::FRINT_W:
8502 case Mips::FRSQRT_D:
8503 case Mips::FRSQRT_W:
8504 case Mips::FSQRT_D:
8505 case Mips::FSQRT_W:
8506 case Mips::FTINT_S_D:
8507 case Mips::FTINT_S_W:
8508 case Mips::FTINT_U_D:
8509 case Mips::FTINT_U_W:
8510 case Mips::FTRUNC_S_D:
8511 case Mips::FTRUNC_S_W:
8512 case Mips::FTRUNC_U_D:
8513 case Mips::FTRUNC_U_W:
8514 case Mips::MOVE_V:
8515 case Mips::NLOC_B:
8516 case Mips::NLOC_D:
8517 case Mips::NLOC_H:
8518 case Mips::NLOC_W:
8519 case Mips::NLZC_B:
8520 case Mips::NLZC_D:
8521 case Mips::NLZC_H:
8522 case Mips::NLZC_W:
8523 case Mips::PCNT_B:
8524 case Mips::PCNT_D:
8525 case Mips::PCNT_H:
8526 case Mips::PCNT_W: {
8527 // op: ws
8528 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8529 op &= UINT64_C(31);
8530 op <<= 11;
8531 Value |= op;
8532 // op: wd
8533 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8534 op &= UINT64_C(31);
8535 op <<= 6;
8536 Value |= op;
8537 break;
8538 }
8539 case Mips::BCLRI_H:
8540 case Mips::BNEGI_H:
8541 case Mips::BSETI_H:
8542 case Mips::SAT_S_H:
8543 case Mips::SAT_U_H:
8544 case Mips::SLLI_H:
8545 case Mips::SRAI_H:
8546 case Mips::SRARI_H:
8547 case Mips::SRLI_H:
8548 case Mips::SRLRI_H: {
8549 // op: ws
8550 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8551 op &= UINT64_C(31);
8552 op <<= 11;
8553 Value |= op;
8554 // op: wd
8555 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8556 op &= UINT64_C(31);
8557 op <<= 6;
8558 Value |= op;
8559 // op: m
8560 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8561 op &= UINT64_C(15);
8562 op <<= 16;
8563 Value |= op;
8564 break;
8565 }
8566 case Mips::BCLRI_W:
8567 case Mips::BNEGI_W:
8568 case Mips::BSETI_W:
8569 case Mips::SAT_S_W:
8570 case Mips::SAT_U_W:
8571 case Mips::SLLI_W:
8572 case Mips::SRAI_W:
8573 case Mips::SRARI_W:
8574 case Mips::SRLI_W:
8575 case Mips::SRLRI_W: {
8576 // op: ws
8577 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8578 op &= UINT64_C(31);
8579 op <<= 11;
8580 Value |= op;
8581 // op: wd
8582 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8583 op &= UINT64_C(31);
8584 op <<= 6;
8585 Value |= op;
8586 // op: m
8587 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8588 op &= UINT64_C(31);
8589 op <<= 16;
8590 Value |= op;
8591 break;
8592 }
8593 case Mips::BCLRI_D:
8594 case Mips::BNEGI_D:
8595 case Mips::BSETI_D:
8596 case Mips::SAT_S_D:
8597 case Mips::SAT_U_D:
8598 case Mips::SLLI_D:
8599 case Mips::SRAI_D:
8600 case Mips::SRARI_D:
8601 case Mips::SRLI_D:
8602 case Mips::SRLRI_D: {
8603 // op: ws
8604 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8605 op &= UINT64_C(31);
8606 op <<= 11;
8607 Value |= op;
8608 // op: wd
8609 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8610 op &= UINT64_C(31);
8611 op <<= 6;
8612 Value |= op;
8613 // op: m
8614 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8615 op &= UINT64_C(63);
8616 op <<= 16;
8617 Value |= op;
8618 break;
8619 }
8620 case Mips::BCLRI_B:
8621 case Mips::BNEGI_B:
8622 case Mips::BSETI_B:
8623 case Mips::SAT_S_B:
8624 case Mips::SAT_U_B:
8625 case Mips::SLLI_B:
8626 case Mips::SRAI_B:
8627 case Mips::SRARI_B:
8628 case Mips::SRLI_B:
8629 case Mips::SRLRI_B: {
8630 // op: ws
8631 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8632 op &= UINT64_C(31);
8633 op <<= 11;
8634 Value |= op;
8635 // op: wd
8636 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8637 op &= UINT64_C(31);
8638 op <<= 6;
8639 Value |= op;
8640 // op: m
8641 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8642 op &= UINT64_C(7);
8643 op <<= 16;
8644 Value |= op;
8645 break;
8646 }
8647 case Mips::BINSLI_H:
8648 case Mips::BINSRI_H: {
8649 // op: ws
8650 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8651 op &= UINT64_C(31);
8652 op <<= 11;
8653 Value |= op;
8654 // op: wd
8655 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8656 op &= UINT64_C(31);
8657 op <<= 6;
8658 Value |= op;
8659 // op: m
8660 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
8661 op &= UINT64_C(15);
8662 op <<= 16;
8663 Value |= op;
8664 break;
8665 }
8666 case Mips::BINSLI_W:
8667 case Mips::BINSRI_W: {
8668 // op: ws
8669 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8670 op &= UINT64_C(31);
8671 op <<= 11;
8672 Value |= op;
8673 // op: wd
8674 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8675 op &= UINT64_C(31);
8676 op <<= 6;
8677 Value |= op;
8678 // op: m
8679 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
8680 op &= UINT64_C(31);
8681 op <<= 16;
8682 Value |= op;
8683 break;
8684 }
8685 case Mips::BINSLI_D:
8686 case Mips::BINSRI_D: {
8687 // op: ws
8688 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8689 op &= UINT64_C(31);
8690 op <<= 11;
8691 Value |= op;
8692 // op: wd
8693 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8694 op &= UINT64_C(31);
8695 op <<= 6;
8696 Value |= op;
8697 // op: m
8698 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
8699 op &= UINT64_C(63);
8700 op <<= 16;
8701 Value |= op;
8702 break;
8703 }
8704 case Mips::BINSLI_B:
8705 case Mips::BINSRI_B: {
8706 // op: ws
8707 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8708 op &= UINT64_C(31);
8709 op <<= 11;
8710 Value |= op;
8711 // op: wd
8712 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8713 op &= UINT64_C(31);
8714 op <<= 6;
8715 Value |= op;
8716 // op: m
8717 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
8718 op &= UINT64_C(7);
8719 op <<= 16;
8720 Value |= op;
8721 break;
8722 }
8723 case Mips::ADDS_A_B:
8724 case Mips::ADDS_A_D:
8725 case Mips::ADDS_A_H:
8726 case Mips::ADDS_A_W:
8727 case Mips::ADDS_S_B:
8728 case Mips::ADDS_S_D:
8729 case Mips::ADDS_S_H:
8730 case Mips::ADDS_S_W:
8731 case Mips::ADDS_U_B:
8732 case Mips::ADDS_U_D:
8733 case Mips::ADDS_U_H:
8734 case Mips::ADDS_U_W:
8735 case Mips::ADDV_B:
8736 case Mips::ADDV_D:
8737 case Mips::ADDV_H:
8738 case Mips::ADDV_W:
8739 case Mips::ADD_A_B:
8740 case Mips::ADD_A_D:
8741 case Mips::ADD_A_H:
8742 case Mips::ADD_A_W:
8743 case Mips::AND_V:
8744 case Mips::ASUB_S_B:
8745 case Mips::ASUB_S_D:
8746 case Mips::ASUB_S_H:
8747 case Mips::ASUB_S_W:
8748 case Mips::ASUB_U_B:
8749 case Mips::ASUB_U_D:
8750 case Mips::ASUB_U_H:
8751 case Mips::ASUB_U_W:
8752 case Mips::AVER_S_B:
8753 case Mips::AVER_S_D:
8754 case Mips::AVER_S_H:
8755 case Mips::AVER_S_W:
8756 case Mips::AVER_U_B:
8757 case Mips::AVER_U_D:
8758 case Mips::AVER_U_H:
8759 case Mips::AVER_U_W:
8760 case Mips::AVE_S_B:
8761 case Mips::AVE_S_D:
8762 case Mips::AVE_S_H:
8763 case Mips::AVE_S_W:
8764 case Mips::AVE_U_B:
8765 case Mips::AVE_U_D:
8766 case Mips::AVE_U_H:
8767 case Mips::AVE_U_W:
8768 case Mips::BCLR_B:
8769 case Mips::BCLR_D:
8770 case Mips::BCLR_H:
8771 case Mips::BCLR_W:
8772 case Mips::BNEG_B:
8773 case Mips::BNEG_D:
8774 case Mips::BNEG_H:
8775 case Mips::BNEG_W:
8776 case Mips::BSET_B:
8777 case Mips::BSET_D:
8778 case Mips::BSET_H:
8779 case Mips::BSET_W:
8780 case Mips::CEQ_B:
8781 case Mips::CEQ_D:
8782 case Mips::CEQ_H:
8783 case Mips::CEQ_W:
8784 case Mips::CLE_S_B:
8785 case Mips::CLE_S_D:
8786 case Mips::CLE_S_H:
8787 case Mips::CLE_S_W:
8788 case Mips::CLE_U_B:
8789 case Mips::CLE_U_D:
8790 case Mips::CLE_U_H:
8791 case Mips::CLE_U_W:
8792 case Mips::CLT_S_B:
8793 case Mips::CLT_S_D:
8794 case Mips::CLT_S_H:
8795 case Mips::CLT_S_W:
8796 case Mips::CLT_U_B:
8797 case Mips::CLT_U_D:
8798 case Mips::CLT_U_H:
8799 case Mips::CLT_U_W:
8800 case Mips::DIV_S_B:
8801 case Mips::DIV_S_D:
8802 case Mips::DIV_S_H:
8803 case Mips::DIV_S_W:
8804 case Mips::DIV_U_B:
8805 case Mips::DIV_U_D:
8806 case Mips::DIV_U_H:
8807 case Mips::DIV_U_W:
8808 case Mips::DOTP_S_D:
8809 case Mips::DOTP_S_H:
8810 case Mips::DOTP_S_W:
8811 case Mips::DOTP_U_D:
8812 case Mips::DOTP_U_H:
8813 case Mips::DOTP_U_W:
8814 case Mips::FADD_D:
8815 case Mips::FADD_W:
8816 case Mips::FCAF_D:
8817 case Mips::FCAF_W:
8818 case Mips::FCEQ_D:
8819 case Mips::FCEQ_W:
8820 case Mips::FCLE_D:
8821 case Mips::FCLE_W:
8822 case Mips::FCLT_D:
8823 case Mips::FCLT_W:
8824 case Mips::FCNE_D:
8825 case Mips::FCNE_W:
8826 case Mips::FCOR_D:
8827 case Mips::FCOR_W:
8828 case Mips::FCUEQ_D:
8829 case Mips::FCUEQ_W:
8830 case Mips::FCULE_D:
8831 case Mips::FCULE_W:
8832 case Mips::FCULT_D:
8833 case Mips::FCULT_W:
8834 case Mips::FCUNE_D:
8835 case Mips::FCUNE_W:
8836 case Mips::FCUN_D:
8837 case Mips::FCUN_W:
8838 case Mips::FDIV_D:
8839 case Mips::FDIV_W:
8840 case Mips::FEXDO_H:
8841 case Mips::FEXDO_W:
8842 case Mips::FEXP2_D:
8843 case Mips::FEXP2_W:
8844 case Mips::FMAX_A_D:
8845 case Mips::FMAX_A_W:
8846 case Mips::FMAX_D:
8847 case Mips::FMAX_W:
8848 case Mips::FMIN_A_D:
8849 case Mips::FMIN_A_W:
8850 case Mips::FMIN_D:
8851 case Mips::FMIN_W:
8852 case Mips::FMUL_D:
8853 case Mips::FMUL_W:
8854 case Mips::FSAF_D:
8855 case Mips::FSAF_W:
8856 case Mips::FSEQ_D:
8857 case Mips::FSEQ_W:
8858 case Mips::FSLE_D:
8859 case Mips::FSLE_W:
8860 case Mips::FSLT_D:
8861 case Mips::FSLT_W:
8862 case Mips::FSNE_D:
8863 case Mips::FSNE_W:
8864 case Mips::FSOR_D:
8865 case Mips::FSOR_W:
8866 case Mips::FSUB_D:
8867 case Mips::FSUB_W:
8868 case Mips::FSUEQ_D:
8869 case Mips::FSUEQ_W:
8870 case Mips::FSULE_D:
8871 case Mips::FSULE_W:
8872 case Mips::FSULT_D:
8873 case Mips::FSULT_W:
8874 case Mips::FSUNE_D:
8875 case Mips::FSUNE_W:
8876 case Mips::FSUN_D:
8877 case Mips::FSUN_W:
8878 case Mips::FTQ_H:
8879 case Mips::FTQ_W:
8880 case Mips::HADD_S_D:
8881 case Mips::HADD_S_H:
8882 case Mips::HADD_S_W:
8883 case Mips::HADD_U_D:
8884 case Mips::HADD_U_H:
8885 case Mips::HADD_U_W:
8886 case Mips::HSUB_S_D:
8887 case Mips::HSUB_S_H:
8888 case Mips::HSUB_S_W:
8889 case Mips::HSUB_U_D:
8890 case Mips::HSUB_U_H:
8891 case Mips::HSUB_U_W:
8892 case Mips::ILVEV_B:
8893 case Mips::ILVEV_D:
8894 case Mips::ILVEV_H:
8895 case Mips::ILVEV_W:
8896 case Mips::ILVL_B:
8897 case Mips::ILVL_D:
8898 case Mips::ILVL_H:
8899 case Mips::ILVL_W:
8900 case Mips::ILVOD_B:
8901 case Mips::ILVOD_D:
8902 case Mips::ILVOD_H:
8903 case Mips::ILVOD_W:
8904 case Mips::ILVR_B:
8905 case Mips::ILVR_D:
8906 case Mips::ILVR_H:
8907 case Mips::ILVR_W:
8908 case Mips::MAX_A_B:
8909 case Mips::MAX_A_D:
8910 case Mips::MAX_A_H:
8911 case Mips::MAX_A_W:
8912 case Mips::MAX_S_B:
8913 case Mips::MAX_S_D:
8914 case Mips::MAX_S_H:
8915 case Mips::MAX_S_W:
8916 case Mips::MAX_U_B:
8917 case Mips::MAX_U_D:
8918 case Mips::MAX_U_H:
8919 case Mips::MAX_U_W:
8920 case Mips::MIN_A_B:
8921 case Mips::MIN_A_D:
8922 case Mips::MIN_A_H:
8923 case Mips::MIN_A_W:
8924 case Mips::MIN_S_B:
8925 case Mips::MIN_S_D:
8926 case Mips::MIN_S_H:
8927 case Mips::MIN_S_W:
8928 case Mips::MIN_U_B:
8929 case Mips::MIN_U_D:
8930 case Mips::MIN_U_H:
8931 case Mips::MIN_U_W:
8932 case Mips::MOD_S_B:
8933 case Mips::MOD_S_D:
8934 case Mips::MOD_S_H:
8935 case Mips::MOD_S_W:
8936 case Mips::MOD_U_B:
8937 case Mips::MOD_U_D:
8938 case Mips::MOD_U_H:
8939 case Mips::MOD_U_W:
8940 case Mips::MULR_Q_H:
8941 case Mips::MULR_Q_W:
8942 case Mips::MULV_B:
8943 case Mips::MULV_D:
8944 case Mips::MULV_H:
8945 case Mips::MULV_W:
8946 case Mips::MUL_Q_H:
8947 case Mips::MUL_Q_W:
8948 case Mips::NOR_V:
8949 case Mips::OR_V:
8950 case Mips::PCKEV_B:
8951 case Mips::PCKEV_D:
8952 case Mips::PCKEV_H:
8953 case Mips::PCKEV_W:
8954 case Mips::PCKOD_B:
8955 case Mips::PCKOD_D:
8956 case Mips::PCKOD_H:
8957 case Mips::PCKOD_W:
8958 case Mips::SLL_B:
8959 case Mips::SLL_D:
8960 case Mips::SLL_H:
8961 case Mips::SLL_W:
8962 case Mips::SRAR_B:
8963 case Mips::SRAR_D:
8964 case Mips::SRAR_H:
8965 case Mips::SRAR_W:
8966 case Mips::SRA_B:
8967 case Mips::SRA_D:
8968 case Mips::SRA_H:
8969 case Mips::SRA_W:
8970 case Mips::SRLR_B:
8971 case Mips::SRLR_D:
8972 case Mips::SRLR_H:
8973 case Mips::SRLR_W:
8974 case Mips::SRL_B:
8975 case Mips::SRL_D:
8976 case Mips::SRL_H:
8977 case Mips::SRL_W:
8978 case Mips::SUBSUS_U_B:
8979 case Mips::SUBSUS_U_D:
8980 case Mips::SUBSUS_U_H:
8981 case Mips::SUBSUS_U_W:
8982 case Mips::SUBSUU_S_B:
8983 case Mips::SUBSUU_S_D:
8984 case Mips::SUBSUU_S_H:
8985 case Mips::SUBSUU_S_W:
8986 case Mips::SUBS_S_B:
8987 case Mips::SUBS_S_D:
8988 case Mips::SUBS_S_H:
8989 case Mips::SUBS_S_W:
8990 case Mips::SUBS_U_B:
8991 case Mips::SUBS_U_D:
8992 case Mips::SUBS_U_H:
8993 case Mips::SUBS_U_W:
8994 case Mips::SUBV_B:
8995 case Mips::SUBV_D:
8996 case Mips::SUBV_H:
8997 case Mips::SUBV_W:
8998 case Mips::XOR_V: {
8999 // op: wt
9000 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9001 op &= UINT64_C(31);
9002 op <<= 16;
9003 Value |= op;
9004 // op: ws
9005 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9006 op &= UINT64_C(31);
9007 op <<= 11;
9008 Value |= op;
9009 // op: wd
9010 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9011 op &= UINT64_C(31);
9012 op <<= 6;
9013 Value |= op;
9014 break;
9015 }
9016 case Mips::BINSL_B:
9017 case Mips::BINSL_D:
9018 case Mips::BINSL_H:
9019 case Mips::BINSL_W:
9020 case Mips::BINSR_B:
9021 case Mips::BINSR_D:
9022 case Mips::BINSR_H:
9023 case Mips::BINSR_W:
9024 case Mips::BMNZ_V:
9025 case Mips::BMZ_V:
9026 case Mips::BSEL_V:
9027 case Mips::DPADD_S_D:
9028 case Mips::DPADD_S_H:
9029 case Mips::DPADD_S_W:
9030 case Mips::DPADD_U_D:
9031 case Mips::DPADD_U_H:
9032 case Mips::DPADD_U_W:
9033 case Mips::DPSUB_S_D:
9034 case Mips::DPSUB_S_H:
9035 case Mips::DPSUB_S_W:
9036 case Mips::DPSUB_U_D:
9037 case Mips::DPSUB_U_H:
9038 case Mips::DPSUB_U_W:
9039 case Mips::FMADD_D:
9040 case Mips::FMADD_W:
9041 case Mips::FMSUB_D:
9042 case Mips::FMSUB_W:
9043 case Mips::MADDR_Q_H:
9044 case Mips::MADDR_Q_W:
9045 case Mips::MADDV_B:
9046 case Mips::MADDV_D:
9047 case Mips::MADDV_H:
9048 case Mips::MADDV_W:
9049 case Mips::MADD_Q_H:
9050 case Mips::MADD_Q_W:
9051 case Mips::MSUBR_Q_H:
9052 case Mips::MSUBR_Q_W:
9053 case Mips::MSUBV_B:
9054 case Mips::MSUBV_D:
9055 case Mips::MSUBV_H:
9056 case Mips::MSUBV_W:
9057 case Mips::MSUB_Q_H:
9058 case Mips::MSUB_Q_W:
9059 case Mips::VSHF_B:
9060 case Mips::VSHF_D:
9061 case Mips::VSHF_H:
9062 case Mips::VSHF_W: {
9063 // op: wt
9064 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
9065 op &= UINT64_C(31);
9066 op <<= 16;
9067 Value |= op;
9068 // op: ws
9069 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9070 op &= UINT64_C(31);
9071 op <<= 11;
9072 Value |= op;
9073 // op: wd
9074 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9075 op &= UINT64_C(31);
9076 op <<= 6;
9077 Value |= op;
9078 break;
9079 }
9080 default:
9081 std::string msg;
9082 raw_string_ostream Msg(msg);
9083 Msg << "Not supported instr: " << MI;
9084 report_fatal_error(reason: Msg.str().c_str());
9085 }
9086 return Value;
9087}
9088
9089#ifdef GET_OPERAND_BIT_OFFSET
9090#undef GET_OPERAND_BIT_OFFSET
9091
9092uint32_t MipsMCCodeEmitter::getOperandBitOffset(const MCInst &MI,
9093 unsigned OpNum,
9094 const MCSubtargetInfo &STI) const {
9095 switch (MI.getOpcode()) {
9096 case Mips::Break16:
9097 case Mips::DERET:
9098 case Mips::DERET_MM:
9099 case Mips::DERET_MMR6:
9100 case Mips::EHB:
9101 case Mips::EHB_MM:
9102 case Mips::EHB_MMR6:
9103 case Mips::ERET:
9104 case Mips::ERETNC:
9105 case Mips::ERETNC_MMR6:
9106 case Mips::ERET_MM:
9107 case Mips::ERET_MMR6:
9108 case Mips::JrRa16:
9109 case Mips::JrcRa16:
9110 case Mips::JrcRx16:
9111 case Mips::NAL:
9112 case Mips::PAUSE:
9113 case Mips::PAUSE_MM:
9114 case Mips::PAUSE_MMR6:
9115 case Mips::Restore16:
9116 case Mips::RestoreX16:
9117 case Mips::SSNOP:
9118 case Mips::SSNOP_MM:
9119 case Mips::SSNOP_MMR6:
9120 case Mips::Save16:
9121 case Mips::SaveX16:
9122 case Mips::TLBGINV:
9123 case Mips::TLBGINVF:
9124 case Mips::TLBGINVF_MM:
9125 case Mips::TLBGINV_MM:
9126 case Mips::TLBGP:
9127 case Mips::TLBGP_MM:
9128 case Mips::TLBGR:
9129 case Mips::TLBGR_MM:
9130 case Mips::TLBGWI:
9131 case Mips::TLBGWI_MM:
9132 case Mips::TLBGWR:
9133 case Mips::TLBGWR_MM:
9134 case Mips::TLBINV:
9135 case Mips::TLBINVF:
9136 case Mips::TLBINVF_MMR6:
9137 case Mips::TLBINV_MMR6:
9138 case Mips::TLBP:
9139 case Mips::TLBP_MM:
9140 case Mips::TLBR:
9141 case Mips::TLBR_MM:
9142 case Mips::TLBWI:
9143 case Mips::TLBWI_MM:
9144 case Mips::TLBWR:
9145 case Mips::TLBWR_MM:
9146 case Mips::WAIT: {
9147 break;
9148 }
9149 case Mips::DPAQX_SA_W_PH:
9150 case Mips::DPAQX_S_W_PH:
9151 case Mips::DPAQ_SA_L_W:
9152 case Mips::DPAQ_S_W_PH:
9153 case Mips::DPAU_H_QBL:
9154 case Mips::DPAU_H_QBR:
9155 case Mips::DPAX_W_PH:
9156 case Mips::DPA_W_PH:
9157 case Mips::DPSQX_SA_W_PH:
9158 case Mips::DPSQX_S_W_PH:
9159 case Mips::DPSQ_SA_L_W:
9160 case Mips::DPSQ_S_W_PH:
9161 case Mips::DPSU_H_QBL:
9162 case Mips::DPSU_H_QBR:
9163 case Mips::DPSX_W_PH:
9164 case Mips::DPS_W_PH:
9165 case Mips::MADDU_DSP:
9166 case Mips::MADD_DSP:
9167 case Mips::MAQ_SA_W_PHL:
9168 case Mips::MAQ_SA_W_PHR:
9169 case Mips::MAQ_S_W_PHL:
9170 case Mips::MAQ_S_W_PHR:
9171 case Mips::MSUBU_DSP:
9172 case Mips::MSUB_DSP:
9173 case Mips::MULSAQ_S_W_PH:
9174 case Mips::MULSA_W_PH:
9175 case Mips::MULTU_DSP:
9176 case Mips::MULT_DSP: {
9177 switch (OpNum) {
9178 case 0:
9179 // op: ac
9180 return 11;
9181 case 1:
9182 // op: rs
9183 return 21;
9184 case 2:
9185 // op: rt
9186 return 16;
9187 }
9188 break;
9189 }
9190 case Mips::MTHLIP:
9191 case Mips::SHILOV: {
9192 switch (OpNum) {
9193 case 0:
9194 // op: ac
9195 return 11;
9196 case 1:
9197 // op: rs
9198 return 21;
9199 }
9200 break;
9201 }
9202 case Mips::SHILO: {
9203 switch (OpNum) {
9204 case 0:
9205 // op: ac
9206 return 11;
9207 case 1:
9208 // op: shift
9209 return 20;
9210 }
9211 break;
9212 }
9213 case Mips::CACHE:
9214 case Mips::PREF: {
9215 switch (OpNum) {
9216 case 0:
9217 // op: addr
9218 return 0;
9219 case 2:
9220 // op: hint
9221 return 16;
9222 }
9223 break;
9224 }
9225 case Mips::CACHEE_MM:
9226 case Mips::CACHE_MM:
9227 case Mips::CACHE_MMR6:
9228 case Mips::PREFE_MM:
9229 case Mips::PREF_MM:
9230 case Mips::PREF_MMR6: {
9231 switch (OpNum) {
9232 case 0:
9233 // op: addr
9234 return 0;
9235 case 2:
9236 // op: hint
9237 return 21;
9238 }
9239 break;
9240 }
9241 case Mips::SYNCI:
9242 case Mips::SYNCI_MM:
9243 case Mips::SYNCI_MMR6: {
9244 switch (OpNum) {
9245 case 0:
9246 // op: addr
9247 return 0;
9248 }
9249 break;
9250 }
9251 case Mips::CACHEE:
9252 case Mips::CACHE_R6:
9253 case Mips::PREFE:
9254 case Mips::PREF_R6: {
9255 switch (OpNum) {
9256 case 0:
9257 // op: addr
9258 return 7;
9259 case 2:
9260 // op: hint
9261 return 16;
9262 }
9263 break;
9264 }
9265 case Mips::BREAK16_MM:
9266 case Mips::SDBBP16_MM:
9267 case Mips::SIGRIE: {
9268 switch (OpNum) {
9269 case 0:
9270 // op: code_
9271 return 0;
9272 }
9273 break;
9274 }
9275 case Mips::HYPCALL: {
9276 switch (OpNum) {
9277 case 0:
9278 // op: code_
9279 return 11;
9280 }
9281 break;
9282 }
9283 case Mips::HYPCALL_MM:
9284 case Mips::SDBBP_MM:
9285 case Mips::SDBBP_MMR6:
9286 case Mips::SYSCALL_MM:
9287 case Mips::WAIT_MM:
9288 case Mips::WAIT_MMR6: {
9289 switch (OpNum) {
9290 case 0:
9291 // op: code_
9292 return 16;
9293 }
9294 break;
9295 }
9296 case Mips::BREAK16_MMR6:
9297 case Mips::SDBBP:
9298 case Mips::SDBBP16_MMR6:
9299 case Mips::SDBBP_R6:
9300 case Mips::SIGRIE_MMR6:
9301 case Mips::SYSCALL: {
9302 switch (OpNum) {
9303 case 0:
9304 // op: code_
9305 return 6;
9306 }
9307 break;
9308 }
9309 case Mips::BREAK:
9310 case Mips::BREAK_MM:
9311 case Mips::BREAK_MMR6: {
9312 switch (OpNum) {
9313 case 0:
9314 // op: code_1
9315 return 16;
9316 case 1:
9317 // op: code_2
9318 return 6;
9319 }
9320 break;
9321 }
9322 case Mips::BC2EQZ:
9323 case Mips::BC2NEZ: {
9324 switch (OpNum) {
9325 case 0:
9326 // op: ct
9327 return 16;
9328 case 1:
9329 // op: offset
9330 return 0;
9331 }
9332 break;
9333 }
9334 case Mips::BC1F:
9335 case Mips::BC1FL:
9336 case Mips::BC1F_MM:
9337 case Mips::BC1T:
9338 case Mips::BC1TL:
9339 case Mips::BC1T_MM: {
9340 switch (OpNum) {
9341 case 0:
9342 // op: fcc
9343 return 18;
9344 case 1:
9345 // op: offset
9346 return 0;
9347 }
9348 break;
9349 }
9350 case Mips::LUXC1_MM:
9351 case Mips::LWXC1_MM: {
9352 switch (OpNum) {
9353 case 0:
9354 // op: fd
9355 return 11;
9356 case 1:
9357 // op: base
9358 return 16;
9359 case 2:
9360 // op: index
9361 return 21;
9362 }
9363 break;
9364 }
9365 case Mips::MOVN_I_D32_MM:
9366 case Mips::MOVN_I_S_MM:
9367 case Mips::MOVZ_I_D32_MM:
9368 case Mips::MOVZ_I_S_MM: {
9369 switch (OpNum) {
9370 case 0:
9371 // op: fd
9372 return 11;
9373 case 1:
9374 // op: fs
9375 return 16;
9376 case 2:
9377 // op: rt
9378 return 21;
9379 }
9380 break;
9381 }
9382 case Mips::MOVF_D32_MM:
9383 case Mips::MOVF_S_MM:
9384 case Mips::MOVT_D32_MM:
9385 case Mips::MOVT_S_MM: {
9386 switch (OpNum) {
9387 case 0:
9388 // op: fd
9389 return 21;
9390 case 1:
9391 // op: fs
9392 return 16;
9393 case 2:
9394 // op: fcc
9395 return 13;
9396 }
9397 break;
9398 }
9399 case Mips::CEIL_W_MM:
9400 case Mips::CEIL_W_S_MM:
9401 case Mips::CVT_D32_S_MM:
9402 case Mips::CVT_D32_W_MM:
9403 case Mips::CVT_D64_S_MM:
9404 case Mips::CVT_D64_W_MM:
9405 case Mips::CVT_L_D64_MM:
9406 case Mips::CVT_L_S_MM:
9407 case Mips::CVT_S_D32_MM:
9408 case Mips::CVT_S_D64_MM:
9409 case Mips::CVT_S_W_MM:
9410 case Mips::CVT_W_D32_MM:
9411 case Mips::CVT_W_D64_MM:
9412 case Mips::CVT_W_S_MM:
9413 case Mips::FABS_D32_MM:
9414 case Mips::FABS_D64_MM:
9415 case Mips::FABS_S_MM:
9416 case Mips::FLOOR_W_MM:
9417 case Mips::FLOOR_W_S_MM:
9418 case Mips::FMOV_D32_MM:
9419 case Mips::FMOV_D64_MM:
9420 case Mips::FMOV_S_MM:
9421 case Mips::FNEG_D32_MM:
9422 case Mips::FNEG_D64_MM:
9423 case Mips::FNEG_S_MM:
9424 case Mips::FSQRT_D32_MM:
9425 case Mips::FSQRT_D64_MM:
9426 case Mips::FSQRT_S_MM:
9427 case Mips::RECIP_D32_MM:
9428 case Mips::RECIP_D64_MM:
9429 case Mips::RECIP_S_MM:
9430 case Mips::ROUND_W_MM:
9431 case Mips::ROUND_W_S_MM:
9432 case Mips::RSQRT_D32_MM:
9433 case Mips::RSQRT_D64_MM:
9434 case Mips::RSQRT_S_MM:
9435 case Mips::TRUNC_W_MM:
9436 case Mips::TRUNC_W_S_MM: {
9437 switch (OpNum) {
9438 case 0:
9439 // op: fd
9440 return 21;
9441 case 1:
9442 // op: fs
9443 return 16;
9444 }
9445 break;
9446 }
9447 case Mips::LDXC1:
9448 case Mips::LDXC164:
9449 case Mips::LUXC1:
9450 case Mips::LUXC164:
9451 case Mips::LWXC1: {
9452 switch (OpNum) {
9453 case 0:
9454 // op: fd
9455 return 6;
9456 case 1:
9457 // op: base
9458 return 21;
9459 case 2:
9460 // op: index
9461 return 16;
9462 }
9463 break;
9464 }
9465 case Mips::MADD_D32:
9466 case Mips::MADD_D64:
9467 case Mips::MADD_S:
9468 case Mips::MSUB_D32:
9469 case Mips::MSUB_D64:
9470 case Mips::MSUB_S:
9471 case Mips::NMADD_D32:
9472 case Mips::NMADD_D64:
9473 case Mips::NMADD_S:
9474 case Mips::NMSUB_D32:
9475 case Mips::NMSUB_D64:
9476 case Mips::NMSUB_S: {
9477 switch (OpNum) {
9478 case 0:
9479 // op: fd
9480 return 6;
9481 case 1:
9482 // op: fr
9483 return 21;
9484 case 2:
9485 // op: fs
9486 return 11;
9487 case 3:
9488 // op: ft
9489 return 16;
9490 }
9491 break;
9492 }
9493 case Mips::MOVF_D32:
9494 case Mips::MOVF_D64:
9495 case Mips::MOVF_S:
9496 case Mips::MOVT_D32:
9497 case Mips::MOVT_D64:
9498 case Mips::MOVT_S: {
9499 switch (OpNum) {
9500 case 0:
9501 // op: fd
9502 return 6;
9503 case 1:
9504 // op: fs
9505 return 11;
9506 case 2:
9507 // op: fcc
9508 return 18;
9509 }
9510 break;
9511 }
9512 case Mips::ADDR_PS64:
9513 case Mips::CMP_EQ_D:
9514 case Mips::CMP_EQ_S:
9515 case Mips::CMP_F_D:
9516 case Mips::CMP_F_S:
9517 case Mips::CMP_LE_D:
9518 case Mips::CMP_LE_S:
9519 case Mips::CMP_LT_D:
9520 case Mips::CMP_LT_S:
9521 case Mips::CMP_SAF_D:
9522 case Mips::CMP_SAF_S:
9523 case Mips::CMP_SEQ_D:
9524 case Mips::CMP_SEQ_S:
9525 case Mips::CMP_SLE_D:
9526 case Mips::CMP_SLE_S:
9527 case Mips::CMP_SLT_D:
9528 case Mips::CMP_SLT_S:
9529 case Mips::CMP_SUEQ_D:
9530 case Mips::CMP_SUEQ_S:
9531 case Mips::CMP_SULE_D:
9532 case Mips::CMP_SULE_S:
9533 case Mips::CMP_SULT_D:
9534 case Mips::CMP_SULT_S:
9535 case Mips::CMP_SUN_D:
9536 case Mips::CMP_SUN_S:
9537 case Mips::CMP_UEQ_D:
9538 case Mips::CMP_UEQ_S:
9539 case Mips::CMP_ULE_D:
9540 case Mips::CMP_ULE_S:
9541 case Mips::CMP_ULT_D:
9542 case Mips::CMP_ULT_S:
9543 case Mips::CMP_UN_D:
9544 case Mips::CMP_UN_S:
9545 case Mips::CVT_PS_S64:
9546 case Mips::FADD_D32:
9547 case Mips::FADD_D64:
9548 case Mips::FADD_PS64:
9549 case Mips::FADD_S:
9550 case Mips::FDIV_D32:
9551 case Mips::FDIV_D64:
9552 case Mips::FDIV_S:
9553 case Mips::FMUL_D32:
9554 case Mips::FMUL_D64:
9555 case Mips::FMUL_PS64:
9556 case Mips::FMUL_S:
9557 case Mips::FSUB_D32:
9558 case Mips::FSUB_D64:
9559 case Mips::FSUB_PS64:
9560 case Mips::FSUB_S:
9561 case Mips::MULR_PS64:
9562 case Mips::PLL_PS64:
9563 case Mips::PLU_PS64:
9564 case Mips::PUL_PS64:
9565 case Mips::PUU_PS64: {
9566 switch (OpNum) {
9567 case 0:
9568 // op: fd
9569 return 6;
9570 case 1:
9571 // op: fs
9572 return 11;
9573 case 2:
9574 // op: ft
9575 return 16;
9576 }
9577 break;
9578 }
9579 case Mips::MOVN_I64_D64:
9580 case Mips::MOVN_I64_S:
9581 case Mips::MOVN_I_D32:
9582 case Mips::MOVN_I_D64:
9583 case Mips::MOVN_I_S:
9584 case Mips::MOVZ_I64_D64:
9585 case Mips::MOVZ_I64_S:
9586 case Mips::MOVZ_I_D32:
9587 case Mips::MOVZ_I_D64:
9588 case Mips::MOVZ_I_S: {
9589 switch (OpNum) {
9590 case 0:
9591 // op: fd
9592 return 6;
9593 case 1:
9594 // op: fs
9595 return 11;
9596 case 2:
9597 // op: rt
9598 return 16;
9599 }
9600 break;
9601 }
9602 case Mips::CEIL_L_D64:
9603 case Mips::CEIL_L_S:
9604 case Mips::CEIL_W_D32:
9605 case Mips::CEIL_W_D64:
9606 case Mips::CEIL_W_S:
9607 case Mips::CVT_D32_S:
9608 case Mips::CVT_D32_W:
9609 case Mips::CVT_D64_L:
9610 case Mips::CVT_D64_S:
9611 case Mips::CVT_D64_W:
9612 case Mips::CVT_L_D64:
9613 case Mips::CVT_L_S:
9614 case Mips::CVT_PS_PW64:
9615 case Mips::CVT_PW_PS64:
9616 case Mips::CVT_S_D32:
9617 case Mips::CVT_S_D64:
9618 case Mips::CVT_S_L:
9619 case Mips::CVT_S_PL64:
9620 case Mips::CVT_S_PU64:
9621 case Mips::CVT_S_W:
9622 case Mips::CVT_W_D32:
9623 case Mips::CVT_W_D64:
9624 case Mips::CVT_W_S:
9625 case Mips::FABS_D32:
9626 case Mips::FABS_D64:
9627 case Mips::FABS_S:
9628 case Mips::FLOOR_L_D64:
9629 case Mips::FLOOR_L_S:
9630 case Mips::FLOOR_W_D32:
9631 case Mips::FLOOR_W_D64:
9632 case Mips::FLOOR_W_S:
9633 case Mips::FMOV_D32:
9634 case Mips::FMOV_D64:
9635 case Mips::FMOV_S:
9636 case Mips::FNEG_D32:
9637 case Mips::FNEG_D64:
9638 case Mips::FNEG_S:
9639 case Mips::FSQRT_D32:
9640 case Mips::FSQRT_D64:
9641 case Mips::FSQRT_S:
9642 case Mips::RECIP_D32:
9643 case Mips::RECIP_D64:
9644 case Mips::RECIP_S:
9645 case Mips::ROUND_L_D64:
9646 case Mips::ROUND_L_S:
9647 case Mips::ROUND_W_D32:
9648 case Mips::ROUND_W_D64:
9649 case Mips::ROUND_W_S:
9650 case Mips::RSQRT_D32:
9651 case Mips::RSQRT_D64:
9652 case Mips::RSQRT_S:
9653 case Mips::TRUNC_L_D64:
9654 case Mips::TRUNC_L_S:
9655 case Mips::TRUNC_W_D32:
9656 case Mips::TRUNC_W_D64:
9657 case Mips::TRUNC_W_S: {
9658 switch (OpNum) {
9659 case 0:
9660 // op: fd
9661 return 6;
9662 case 1:
9663 // op: fs
9664 return 11;
9665 }
9666 break;
9667 }
9668 case Mips::SUXC1_MM:
9669 case Mips::SWXC1_MM: {
9670 switch (OpNum) {
9671 case 0:
9672 // op: fs
9673 return 11;
9674 case 1:
9675 // op: base
9676 return 16;
9677 case 2:
9678 // op: index
9679 return 21;
9680 }
9681 break;
9682 }
9683 case Mips::SDXC1:
9684 case Mips::SDXC164:
9685 case Mips::SUXC1:
9686 case Mips::SUXC164:
9687 case Mips::SWXC1: {
9688 switch (OpNum) {
9689 case 0:
9690 // op: fs
9691 return 11;
9692 case 1:
9693 // op: base
9694 return 21;
9695 case 2:
9696 // op: index
9697 return 16;
9698 }
9699 break;
9700 }
9701 case Mips::FCMP_D32:
9702 case Mips::FCMP_D64:
9703 case Mips::FCMP_S32: {
9704 switch (OpNum) {
9705 case 0:
9706 // op: fs
9707 return 11;
9708 case 1:
9709 // op: ft
9710 return 16;
9711 case 2:
9712 // op: cond
9713 return 0;
9714 }
9715 break;
9716 }
9717 case Mips::FCMP_D32_MM:
9718 case Mips::FCMP_S32_MM: {
9719 switch (OpNum) {
9720 case 0:
9721 // op: fs
9722 return 16;
9723 case 1:
9724 // op: ft
9725 return 21;
9726 case 2:
9727 // op: cond
9728 return 6;
9729 }
9730 break;
9731 }
9732 case Mips::BC1EQZ:
9733 case Mips::BC1NEZ: {
9734 switch (OpNum) {
9735 case 0:
9736 // op: ft
9737 return 16;
9738 case 1:
9739 // op: offset
9740 return 0;
9741 }
9742 break;
9743 }
9744 case Mips::LDC1_D64_MMR6:
9745 case Mips::SDC1_D64_MMR6: {
9746 switch (OpNum) {
9747 case 0:
9748 // op: ft
9749 return 21;
9750 case 1:
9751 // op: addr
9752 return 0;
9753 }
9754 break;
9755 }
9756 case Mips::CEIL_L_D_MMR6:
9757 case Mips::CEIL_L_S_MMR6:
9758 case Mips::CEIL_W_D_MMR6:
9759 case Mips::CEIL_W_S_MMR6:
9760 case Mips::CVT_D_L_MMR6:
9761 case Mips::CVT_L_D_MMR6:
9762 case Mips::CVT_L_S_MMR6:
9763 case Mips::CVT_S_L_MMR6:
9764 case Mips::CVT_S_W_MMR6:
9765 case Mips::CVT_W_S_MMR6:
9766 case Mips::FLOOR_L_D_MMR6:
9767 case Mips::FLOOR_L_S_MMR6:
9768 case Mips::FLOOR_W_D_MMR6:
9769 case Mips::FLOOR_W_S_MMR6:
9770 case Mips::FMOV_D_MMR6:
9771 case Mips::FMOV_S_MMR6:
9772 case Mips::FNEG_S_MMR6:
9773 case Mips::ROUND_L_D_MMR6:
9774 case Mips::ROUND_L_S_MMR6:
9775 case Mips::ROUND_W_D_MMR6:
9776 case Mips::ROUND_W_S_MMR6:
9777 case Mips::TRUNC_L_D_MMR6:
9778 case Mips::TRUNC_L_S_MMR6:
9779 case Mips::TRUNC_W_D_MMR6:
9780 case Mips::TRUNC_W_S_MMR6: {
9781 switch (OpNum) {
9782 case 0:
9783 // op: ft
9784 return 21;
9785 case 1:
9786 // op: fs
9787 return 16;
9788 }
9789 break;
9790 }
9791 case Mips::JRADDIUSP: {
9792 switch (OpNum) {
9793 case 0:
9794 // op: imm
9795 return 0;
9796 }
9797 break;
9798 }
9799 case Mips::ADDIUSP_MM: {
9800 switch (OpNum) {
9801 case 0:
9802 // op: imm
9803 return 1;
9804 }
9805 break;
9806 }
9807 case Mips::JRCADDIUSP_MMR6: {
9808 switch (OpNum) {
9809 case 0:
9810 // op: imm
9811 return 5;
9812 }
9813 break;
9814 }
9815 case Mips::Bimm16: {
9816 switch (OpNum) {
9817 case 0:
9818 // op: imm11
9819 return 0;
9820 }
9821 break;
9822 }
9823 case Mips::AddiuSpImmX16:
9824 case Mips::BimmX16:
9825 case Mips::BteqzX16:
9826 case Mips::BtnezX16: {
9827 switch (OpNum) {
9828 case 0:
9829 // op: imm16
9830 return 0;
9831 }
9832 break;
9833 }
9834 case Mips::Jal16:
9835 case Mips::JalB16: {
9836 switch (OpNum) {
9837 case 0:
9838 // op: imm26
9839 return 0;
9840 }
9841 break;
9842 }
9843 case Mips::AddiuSpImm16:
9844 case Mips::Bteqz16:
9845 case Mips::Btnez16: {
9846 switch (OpNum) {
9847 case 0:
9848 // op: imm8
9849 return 0;
9850 }
9851 break;
9852 }
9853 case Mips::B16_MM:
9854 case Mips::BAL:
9855 case Mips::BALC:
9856 case Mips::BALC_MMR6:
9857 case Mips::BC:
9858 case Mips::BC16_MMR6:
9859 case Mips::BC_MMR6:
9860 case Mips::BPOSGE32:
9861 case Mips::BPOSGE32C_MMR3:
9862 case Mips::BPOSGE32_MM: {
9863 switch (OpNum) {
9864 case 0:
9865 // op: offset
9866 return 0;
9867 }
9868 break;
9869 }
9870 case Mips::Move32R16: {
9871 switch (OpNum) {
9872 case 0:
9873 // op: r32
9874 return 3;
9875 case 1:
9876 // op: rz
9877 return 0;
9878 }
9879 break;
9880 }
9881 case Mips::MFHI16_MM:
9882 case Mips::MFLO16_MM: {
9883 switch (OpNum) {
9884 case 0:
9885 // op: rd
9886 return 0;
9887 }
9888 break;
9889 }
9890 case Mips::MFHI_DSP:
9891 case Mips::MFLO_DSP: {
9892 switch (OpNum) {
9893 case 0:
9894 // op: rd
9895 return 11;
9896 case 1:
9897 // op: ac
9898 return 21;
9899 }
9900 break;
9901 }
9902 case Mips::LWXS_MM: {
9903 switch (OpNum) {
9904 case 0:
9905 // op: rd
9906 return 11;
9907 case 1:
9908 // op: base
9909 return 16;
9910 case 2:
9911 // op: index
9912 return 21;
9913 }
9914 break;
9915 }
9916 case Mips::LBUX:
9917 case Mips::LHX:
9918 case Mips::LWX: {
9919 switch (OpNum) {
9920 case 0:
9921 // op: rd
9922 return 11;
9923 case 1:
9924 // op: base
9925 return 21;
9926 case 2:
9927 // op: index
9928 return 16;
9929 }
9930 break;
9931 }
9932 case Mips::REPL_PH:
9933 case Mips::REPL_PH_MM:
9934 case Mips::REPL_QB: {
9935 switch (OpNum) {
9936 case 0:
9937 // op: rd
9938 return 11;
9939 case 1:
9940 // op: imm
9941 return 16;
9942 }
9943 break;
9944 }
9945 case Mips::RDDSP: {
9946 switch (OpNum) {
9947 case 0:
9948 // op: rd
9949 return 11;
9950 case 1:
9951 // op: mask
9952 return 16;
9953 }
9954 break;
9955 }
9956 case Mips::LSA_MMR6: {
9957 switch (OpNum) {
9958 case 0:
9959 // op: rd
9960 return 11;
9961 case 1:
9962 // op: rs
9963 return 16;
9964 case 2:
9965 // op: rt
9966 return 21;
9967 case 3:
9968 // op: imm2
9969 return 9;
9970 }
9971 break;
9972 }
9973 case Mips::ADDQH_PH_MMR2:
9974 case Mips::ADDQH_R_PH_MMR2:
9975 case Mips::ADDQH_R_W_MMR2:
9976 case Mips::ADDQH_W_MMR2:
9977 case Mips::ADDQ_PH_MM:
9978 case Mips::ADDQ_S_PH_MM:
9979 case Mips::ADDQ_S_W_MM:
9980 case Mips::ADDSC_MM:
9981 case Mips::ADDUH_QB_MMR2:
9982 case Mips::ADDUH_R_QB_MMR2:
9983 case Mips::ADDU_PH_MMR2:
9984 case Mips::ADDU_QB_MM:
9985 case Mips::ADDU_S_PH_MMR2:
9986 case Mips::ADDU_S_QB_MM:
9987 case Mips::ADDWC_MM:
9988 case Mips::CMPGDU_EQ_QB_MMR2:
9989 case Mips::CMPGDU_LE_QB_MMR2:
9990 case Mips::CMPGDU_LT_QB_MMR2:
9991 case Mips::MODSUB_MM:
9992 case Mips::MULEQ_S_W_PHL_MM:
9993 case Mips::MULEQ_S_W_PHR_MM:
9994 case Mips::MULEU_S_PH_QBL_MM:
9995 case Mips::MULEU_S_PH_QBR_MM:
9996 case Mips::MULQ_RS_PH_MM:
9997 case Mips::MULQ_RS_W_MMR2:
9998 case Mips::MULQ_S_PH_MMR2:
9999 case Mips::MULQ_S_W_MMR2:
10000 case Mips::MUL_PH_MMR2:
10001 case Mips::MUL_S_PH_MMR2:
10002 case Mips::PACKRL_PH_MM:
10003 case Mips::PICK_PH_MM:
10004 case Mips::PICK_QB_MM:
10005 case Mips::PRECRQU_S_QB_PH_MM:
10006 case Mips::PRECRQ_PH_W_MM:
10007 case Mips::PRECRQ_QB_PH_MM:
10008 case Mips::PRECRQ_RS_PH_W_MM:
10009 case Mips::PRECR_QB_PH_MMR2:
10010 case Mips::SELEQZ_MMR6:
10011 case Mips::SELNEZ_MMR6:
10012 case Mips::SUBQH_PH_MMR2:
10013 case Mips::SUBQH_R_PH_MMR2:
10014 case Mips::SUBQH_R_W_MMR2:
10015 case Mips::SUBQH_W_MMR2:
10016 case Mips::SUBQ_PH_MM:
10017 case Mips::SUBQ_S_PH_MM:
10018 case Mips::SUBQ_S_W_MM:
10019 case Mips::SUBUH_QB_MMR2:
10020 case Mips::SUBUH_R_QB_MMR2:
10021 case Mips::SUBU_PH_MMR2:
10022 case Mips::SUBU_QB_MM:
10023 case Mips::SUBU_S_PH_MMR2:
10024 case Mips::SUBU_S_QB_MM: {
10025 switch (OpNum) {
10026 case 0:
10027 // op: rd
10028 return 11;
10029 case 1:
10030 // op: rs
10031 return 16;
10032 case 2:
10033 // op: rt
10034 return 21;
10035 }
10036 break;
10037 }
10038 case Mips::MOVF_I:
10039 case Mips::MOVF_I64:
10040 case Mips::MOVT_I:
10041 case Mips::MOVT_I64: {
10042 switch (OpNum) {
10043 case 0:
10044 // op: rd
10045 return 11;
10046 case 1:
10047 // op: rs
10048 return 21;
10049 case 2:
10050 // op: fcc
10051 return 18;
10052 }
10053 break;
10054 }
10055 case Mips::ALIGN:
10056 case Mips::DALIGN: {
10057 switch (OpNum) {
10058 case 0:
10059 // op: rd
10060 return 11;
10061 case 1:
10062 // op: rs
10063 return 21;
10064 case 2:
10065 // op: rt
10066 return 16;
10067 case 3:
10068 // op: bp
10069 return 6;
10070 }
10071 break;
10072 }
10073 case Mips::ALIGN_MMR6: {
10074 switch (OpNum) {
10075 case 0:
10076 // op: rd
10077 return 11;
10078 case 1:
10079 // op: rs
10080 return 21;
10081 case 2:
10082 // op: rt
10083 return 16;
10084 case 3:
10085 // op: bp
10086 return 9;
10087 }
10088 break;
10089 }
10090 case Mips::DLSA_R6:
10091 case Mips::LSA_R6: {
10092 switch (OpNum) {
10093 case 0:
10094 // op: rd
10095 return 11;
10096 case 1:
10097 // op: rs
10098 return 21;
10099 case 2:
10100 // op: rt
10101 return 16;
10102 case 3:
10103 // op: imm2
10104 return 6;
10105 }
10106 break;
10107 }
10108 case Mips::ADD:
10109 case Mips::ADDQH_PH:
10110 case Mips::ADDQH_R_PH:
10111 case Mips::ADDQH_R_W:
10112 case Mips::ADDQH_W:
10113 case Mips::ADDQ_PH:
10114 case Mips::ADDQ_S_PH:
10115 case Mips::ADDQ_S_W:
10116 case Mips::ADDSC:
10117 case Mips::ADDUH_QB:
10118 case Mips::ADDUH_R_QB:
10119 case Mips::ADDU_PH:
10120 case Mips::ADDU_QB:
10121 case Mips::ADDU_S_PH:
10122 case Mips::ADDU_S_QB:
10123 case Mips::ADDWC:
10124 case Mips::ADDu:
10125 case Mips::AND:
10126 case Mips::AND64:
10127 case Mips::BADDu:
10128 case Mips::DADD:
10129 case Mips::DADDu:
10130 case Mips::DDIV:
10131 case Mips::DDIVU:
10132 case Mips::DIV:
10133 case Mips::DIVU:
10134 case Mips::DMOD:
10135 case Mips::DMODU:
10136 case Mips::DMUH:
10137 case Mips::DMUHU:
10138 case Mips::DMUL:
10139 case Mips::DMULU:
10140 case Mips::DMUL_R6:
10141 case Mips::DSUB:
10142 case Mips::DSUBu:
10143 case Mips::MOD:
10144 case Mips::MODSUB:
10145 case Mips::MODU:
10146 case Mips::MOVN_I64_I:
10147 case Mips::MOVN_I64_I64:
10148 case Mips::MOVN_I_I:
10149 case Mips::MOVN_I_I64:
10150 case Mips::MOVZ_I64_I:
10151 case Mips::MOVZ_I64_I64:
10152 case Mips::MOVZ_I_I:
10153 case Mips::MOVZ_I_I64:
10154 case Mips::MUH:
10155 case Mips::MUHU:
10156 case Mips::MUL:
10157 case Mips::MULEQ_S_W_PHL:
10158 case Mips::MULEQ_S_W_PHR:
10159 case Mips::MULEU_S_PH_QBL:
10160 case Mips::MULEU_S_PH_QBR:
10161 case Mips::MULQ_RS_PH:
10162 case Mips::MULQ_RS_W:
10163 case Mips::MULQ_S_PH:
10164 case Mips::MULQ_S_W:
10165 case Mips::MULU:
10166 case Mips::MUL_PH:
10167 case Mips::MUL_R6:
10168 case Mips::MUL_S_PH:
10169 case Mips::NOR:
10170 case Mips::NOR64:
10171 case Mips::OR:
10172 case Mips::OR64:
10173 case Mips::SELEQZ:
10174 case Mips::SELEQZ64:
10175 case Mips::SELNEZ:
10176 case Mips::SELNEZ64:
10177 case Mips::SEQ:
10178 case Mips::SLT:
10179 case Mips::SLT64:
10180 case Mips::SLTu:
10181 case Mips::SLTu64:
10182 case Mips::SNE:
10183 case Mips::SUB:
10184 case Mips::SUBQH_PH:
10185 case Mips::SUBQH_R_PH:
10186 case Mips::SUBQH_R_W:
10187 case Mips::SUBQH_W:
10188 case Mips::SUBQ_PH:
10189 case Mips::SUBQ_S_PH:
10190 case Mips::SUBQ_S_W:
10191 case Mips::SUBUH_QB:
10192 case Mips::SUBUH_R_QB:
10193 case Mips::SUBU_PH:
10194 case Mips::SUBU_QB:
10195 case Mips::SUBU_S_PH:
10196 case Mips::SUBU_S_QB:
10197 case Mips::SUBu:
10198 case Mips::V3MULU:
10199 case Mips::VMM0:
10200 case Mips::VMULU:
10201 case Mips::XOR:
10202 case Mips::XOR64: {
10203 switch (OpNum) {
10204 case 0:
10205 // op: rd
10206 return 11;
10207 case 1:
10208 // op: rs
10209 return 21;
10210 case 2:
10211 // op: rt
10212 return 16;
10213 }
10214 break;
10215 }
10216 case Mips::CLO:
10217 case Mips::CLO_R6:
10218 case Mips::CLZ:
10219 case Mips::CLZ_R6:
10220 case Mips::DCLO:
10221 case Mips::DCLO_R6:
10222 case Mips::DCLZ:
10223 case Mips::DCLZ_R6:
10224 case Mips::DPOP:
10225 case Mips::JALR:
10226 case Mips::JALR64:
10227 case Mips::JALR_HB:
10228 case Mips::JALR_HB64:
10229 case Mips::POP:
10230 case Mips::RADDU_W_QB: {
10231 switch (OpNum) {
10232 case 0:
10233 // op: rd
10234 return 11;
10235 case 1:
10236 // op: rs
10237 return 21;
10238 }
10239 break;
10240 }
10241 case Mips::DROTRV:
10242 case Mips::DSLLV:
10243 case Mips::DSRAV:
10244 case Mips::DSRLV:
10245 case Mips::ROTRV:
10246 case Mips::SLLV:
10247 case Mips::SRAV:
10248 case Mips::SRLV: {
10249 switch (OpNum) {
10250 case 0:
10251 // op: rd
10252 return 11;
10253 case 1:
10254 // op: rt
10255 return 16;
10256 case 2:
10257 // op: rs
10258 return 21;
10259 }
10260 break;
10261 }
10262 case Mips::SHLLV_PH:
10263 case Mips::SHLLV_QB:
10264 case Mips::SHLLV_S_PH:
10265 case Mips::SHLLV_S_W:
10266 case Mips::SHLL_PH:
10267 case Mips::SHLL_QB:
10268 case Mips::SHLL_S_PH:
10269 case Mips::SHLL_S_W:
10270 case Mips::SHRAV_PH:
10271 case Mips::SHRAV_QB:
10272 case Mips::SHRAV_R_PH:
10273 case Mips::SHRAV_R_QB:
10274 case Mips::SHRAV_R_W:
10275 case Mips::SHRA_PH:
10276 case Mips::SHRA_QB:
10277 case Mips::SHRA_R_PH:
10278 case Mips::SHRA_R_QB:
10279 case Mips::SHRA_R_W:
10280 case Mips::SHRLV_PH:
10281 case Mips::SHRLV_QB:
10282 case Mips::SHRL_PH:
10283 case Mips::SHRL_QB: {
10284 switch (OpNum) {
10285 case 0:
10286 // op: rd
10287 return 11;
10288 case 1:
10289 // op: rt
10290 return 16;
10291 case 2:
10292 // op: rs_sa
10293 return 21;
10294 }
10295 break;
10296 }
10297 case Mips::DROTR:
10298 case Mips::DROTR32:
10299 case Mips::DSLL:
10300 case Mips::DSLL32:
10301 case Mips::DSRA:
10302 case Mips::DSRA32:
10303 case Mips::DSRL:
10304 case Mips::DSRL32:
10305 case Mips::ROTR:
10306 case Mips::SLL:
10307 case Mips::SRA:
10308 case Mips::SRL: {
10309 switch (OpNum) {
10310 case 0:
10311 // op: rd
10312 return 11;
10313 case 1:
10314 // op: rt
10315 return 16;
10316 case 2:
10317 // op: shamt
10318 return 6;
10319 }
10320 break;
10321 }
10322 case Mips::ABSQ_S_PH:
10323 case Mips::ABSQ_S_QB:
10324 case Mips::ABSQ_S_W:
10325 case Mips::BITREV:
10326 case Mips::BITSWAP:
10327 case Mips::DBITSWAP:
10328 case Mips::DSBH:
10329 case Mips::DSHD:
10330 case Mips::DSLL64_32:
10331 case Mips::PRECEQU_PH_QBL:
10332 case Mips::PRECEQU_PH_QBLA:
10333 case Mips::PRECEQU_PH_QBR:
10334 case Mips::PRECEQU_PH_QBRA:
10335 case Mips::PRECEQ_W_PHL:
10336 case Mips::PRECEQ_W_PHR:
10337 case Mips::PRECEU_PH_QBL:
10338 case Mips::PRECEU_PH_QBLA:
10339 case Mips::PRECEU_PH_QBR:
10340 case Mips::PRECEU_PH_QBRA:
10341 case Mips::REPLV_PH:
10342 case Mips::REPLV_QB:
10343 case Mips::SEB:
10344 case Mips::SEB64:
10345 case Mips::SEH:
10346 case Mips::SEH64:
10347 case Mips::SLL64_32:
10348 case Mips::SLL64_64:
10349 case Mips::WSBH: {
10350 switch (OpNum) {
10351 case 0:
10352 // op: rd
10353 return 11;
10354 case 1:
10355 // op: rt
10356 return 16;
10357 }
10358 break;
10359 }
10360 case Mips::ROTRV_MM:
10361 case Mips::SLLV_MM:
10362 case Mips::SRAV_MM:
10363 case Mips::SRLV_MM: {
10364 switch (OpNum) {
10365 case 0:
10366 // op: rd
10367 return 11;
10368 case 1:
10369 // op: rt
10370 return 21;
10371 case 2:
10372 // op: rs
10373 return 16;
10374 }
10375 break;
10376 }
10377 case Mips::SHLLV_PH_MM:
10378 case Mips::SHLLV_QB_MM:
10379 case Mips::SHLLV_S_PH_MM:
10380 case Mips::SHLLV_S_W_MM:
10381 case Mips::SHRAV_PH_MM:
10382 case Mips::SHRAV_QB_MMR2:
10383 case Mips::SHRAV_R_PH_MM:
10384 case Mips::SHRAV_R_QB_MMR2:
10385 case Mips::SHRAV_R_W_MM:
10386 case Mips::SHRLV_PH_MMR2:
10387 case Mips::SHRLV_QB_MM: {
10388 switch (OpNum) {
10389 case 0:
10390 // op: rd
10391 return 11;
10392 case 2:
10393 // op: rs
10394 return 16;
10395 case 1:
10396 // op: rt
10397 return 21;
10398 }
10399 break;
10400 }
10401 case Mips::ADDU_MMR6:
10402 case Mips::ADD_MMR6:
10403 case Mips::AND_MMR6:
10404 case Mips::DIVU_MMR6:
10405 case Mips::DIV_MMR6:
10406 case Mips::MODU_MMR6:
10407 case Mips::MOD_MMR6:
10408 case Mips::MUHU_MMR6:
10409 case Mips::MUH_MMR6:
10410 case Mips::MULU_MMR6:
10411 case Mips::MUL_MMR6:
10412 case Mips::NOR_MMR6:
10413 case Mips::OR_MMR6:
10414 case Mips::SUBU_MMR6:
10415 case Mips::SUB_MMR6:
10416 case Mips::XOR_MMR6: {
10417 switch (OpNum) {
10418 case 0:
10419 // op: rd
10420 return 11;
10421 case 2:
10422 // op: rt
10423 return 21;
10424 case 1:
10425 // op: rs
10426 return 16;
10427 }
10428 break;
10429 }
10430 case Mips::MFHI:
10431 case Mips::MFHI64:
10432 case Mips::MFLO:
10433 case Mips::MFLO64: {
10434 switch (OpNum) {
10435 case 0:
10436 // op: rd
10437 return 11;
10438 }
10439 break;
10440 }
10441 case Mips::BITSWAP_MMR6: {
10442 switch (OpNum) {
10443 case 0:
10444 // op: rd
10445 return 16;
10446 case 1:
10447 // op: rt
10448 return 21;
10449 }
10450 break;
10451 }
10452 case Mips::MFHI_MM:
10453 case Mips::MFLO_MM: {
10454 switch (OpNum) {
10455 case 0:
10456 // op: rd
10457 return 16;
10458 }
10459 break;
10460 }
10461 case Mips::MOVF_I_MM:
10462 case Mips::MOVT_I_MM: {
10463 switch (OpNum) {
10464 case 0:
10465 // op: rd
10466 return 21;
10467 case 1:
10468 // op: rs
10469 return 16;
10470 case 2:
10471 // op: fcc
10472 return 13;
10473 }
10474 break;
10475 }
10476 case Mips::CLO_MM:
10477 case Mips::CLZ_MM: {
10478 switch (OpNum) {
10479 case 0:
10480 // op: rd
10481 return 21;
10482 case 1:
10483 // op: rs
10484 return 16;
10485 }
10486 break;
10487 }
10488 case Mips::ROTR_MM:
10489 case Mips::SLL_MM:
10490 case Mips::SLL_MMR6:
10491 case Mips::SRA_MM:
10492 case Mips::SRL_MM: {
10493 switch (OpNum) {
10494 case 0:
10495 // op: rd
10496 return 21;
10497 case 1:
10498 // op: rt
10499 return 16;
10500 case 2:
10501 // op: shamt
10502 return 11;
10503 }
10504 break;
10505 }
10506 case Mips::SEB_MM:
10507 case Mips::SEH_MM:
10508 case Mips::WSBH_MM: {
10509 switch (OpNum) {
10510 case 0:
10511 // op: rd
10512 return 21;
10513 case 1:
10514 // op: rt
10515 return 16;
10516 }
10517 break;
10518 }
10519 case Mips::CFCMSA: {
10520 switch (OpNum) {
10521 case 0:
10522 // op: rd
10523 return 6;
10524 case 1:
10525 // op: cs
10526 return 11;
10527 }
10528 break;
10529 }
10530 case Mips::LI16_MM:
10531 case Mips::LI16_MMR6: {
10532 switch (OpNum) {
10533 case 0:
10534 // op: rd
10535 return 7;
10536 case 1:
10537 // op: imm
10538 return 0;
10539 }
10540 break;
10541 }
10542 case Mips::ADDIUR1SP_MM: {
10543 switch (OpNum) {
10544 case 0:
10545 // op: rd
10546 return 7;
10547 case 1:
10548 // op: imm
10549 return 1;
10550 }
10551 break;
10552 }
10553 case Mips::ANDI16_MM:
10554 case Mips::ANDI16_MMR6: {
10555 switch (OpNum) {
10556 case 0:
10557 // op: rd
10558 return 7;
10559 case 1:
10560 // op: rs
10561 return 4;
10562 case 2:
10563 // op: imm
10564 return 0;
10565 }
10566 break;
10567 }
10568 case Mips::ADDIUR2_MM: {
10569 switch (OpNum) {
10570 case 0:
10571 // op: rd
10572 return 7;
10573 case 1:
10574 // op: rs
10575 return 4;
10576 case 2:
10577 // op: imm
10578 return 1;
10579 }
10580 break;
10581 }
10582 case Mips::SLL16_MM:
10583 case Mips::SLL16_MMR6:
10584 case Mips::SRL16_MM:
10585 case Mips::SRL16_MMR6: {
10586 switch (OpNum) {
10587 case 0:
10588 // op: rd
10589 return 7;
10590 case 1:
10591 // op: rt
10592 return 4;
10593 case 2:
10594 // op: shamt
10595 return 1;
10596 }
10597 break;
10598 }
10599 case Mips::ADDU16_MM:
10600 case Mips::SUBU16_MM: {
10601 switch (OpNum) {
10602 case 0:
10603 // op: rd
10604 return 7;
10605 case 2:
10606 // op: rt
10607 return 4;
10608 case 1:
10609 // op: rs
10610 return 1;
10611 }
10612 break;
10613 }
10614 case Mips::JALR16_MM:
10615 case Mips::JALRS16_MM:
10616 case Mips::JR16_MM:
10617 case Mips::JRC16_MM: {
10618 switch (OpNum) {
10619 case 0:
10620 // op: rs
10621 return 0;
10622 }
10623 break;
10624 }
10625 case Mips::MFHI_DSP_MM:
10626 case Mips::MFLO_DSP_MM: {
10627 switch (OpNum) {
10628 case 0:
10629 // op: rs
10630 return 16;
10631 case 1:
10632 // op: ac
10633 return 14;
10634 }
10635 break;
10636 }
10637 case Mips::TEQI_MM:
10638 case Mips::TGEIU_MM:
10639 case Mips::TGEI_MM:
10640 case Mips::TLTIU_MM:
10641 case Mips::TLTI_MM:
10642 case Mips::TNEI_MM: {
10643 switch (OpNum) {
10644 case 0:
10645 // op: rs
10646 return 16;
10647 case 1:
10648 // op: imm16
10649 return 0;
10650 }
10651 break;
10652 }
10653 case Mips::BEQZC_MM:
10654 case Mips::BGEZALS_MM:
10655 case Mips::BGEZAL_MM:
10656 case Mips::BGEZ_MM:
10657 case Mips::BGTZ_MM:
10658 case Mips::BLEZ_MM:
10659 case Mips::BLTZALS_MM:
10660 case Mips::BLTZAL_MM:
10661 case Mips::BLTZ_MM:
10662 case Mips::BNEZC_MM: {
10663 switch (OpNum) {
10664 case 0:
10665 // op: rs
10666 return 16;
10667 case 1:
10668 // op: offset
10669 return 0;
10670 }
10671 break;
10672 }
10673 case Mips::TEQ_MM:
10674 case Mips::TGEU_MM:
10675 case Mips::TGE_MM:
10676 case Mips::TLTU_MM:
10677 case Mips::TLT_MM:
10678 case Mips::TNE_MM: {
10679 switch (OpNum) {
10680 case 0:
10681 // op: rs
10682 return 16;
10683 case 1:
10684 // op: rt
10685 return 21;
10686 case 2:
10687 // op: code_
10688 return 12;
10689 }
10690 break;
10691 }
10692 case Mips::BEQ_MM:
10693 case Mips::BNE_MM: {
10694 switch (OpNum) {
10695 case 0:
10696 // op: rs
10697 return 16;
10698 case 1:
10699 // op: rt
10700 return 21;
10701 case 2:
10702 // op: offset
10703 return 0;
10704 }
10705 break;
10706 }
10707 case Mips::MADDU_MM:
10708 case Mips::MADD_MM:
10709 case Mips::MSUBU_MM:
10710 case Mips::MSUB_MM:
10711 case Mips::MULT_MM:
10712 case Mips::MULTu_MM:
10713 case Mips::SDIV_MM:
10714 case Mips::UDIV_MM: {
10715 switch (OpNum) {
10716 case 0:
10717 // op: rs
10718 return 16;
10719 case 1:
10720 // op: rt
10721 return 21;
10722 }
10723 break;
10724 }
10725 case Mips::GINVT_MMR6: {
10726 switch (OpNum) {
10727 case 0:
10728 // op: rs
10729 return 16;
10730 case 1:
10731 // op: type
10732 return 9;
10733 }
10734 break;
10735 }
10736 case Mips::DVP_MMR6:
10737 case Mips::EVP_MMR6:
10738 case Mips::GINVI_MMR6:
10739 case Mips::JR_MM:
10740 case Mips::MTHI_MM:
10741 case Mips::MTLO_MM: {
10742 switch (OpNum) {
10743 case 0:
10744 // op: rs
10745 return 16;
10746 }
10747 break;
10748 }
10749 case Mips::ADDIUPC:
10750 case Mips::ALUIPC:
10751 case Mips::AUIPC:
10752 case Mips::LDPC:
10753 case Mips::LWPC:
10754 case Mips::LWUPC: {
10755 switch (OpNum) {
10756 case 0:
10757 // op: rs
10758 return 21;
10759 case 1:
10760 // op: imm
10761 return 0;
10762 }
10763 break;
10764 }
10765 case Mips::TEQI:
10766 case Mips::TGEI:
10767 case Mips::TGEIU:
10768 case Mips::TLTI:
10769 case Mips::TNEI:
10770 case Mips::TTLTIU: {
10771 switch (OpNum) {
10772 case 0:
10773 // op: rs
10774 return 21;
10775 case 1:
10776 // op: imm16
10777 return 0;
10778 }
10779 break;
10780 }
10781 case Mips::WRDSP: {
10782 switch (OpNum) {
10783 case 0:
10784 // op: rs
10785 return 21;
10786 case 1:
10787 // op: mask
10788 return 11;
10789 }
10790 break;
10791 }
10792 case Mips::BEQZC:
10793 case Mips::BEQZC64:
10794 case Mips::BEQZC_MMR6:
10795 case Mips::BGEZ:
10796 case Mips::BGEZ64:
10797 case Mips::BGEZAL:
10798 case Mips::BGEZALL:
10799 case Mips::BGEZL:
10800 case Mips::BGTZ:
10801 case Mips::BGTZ64:
10802 case Mips::BGTZL:
10803 case Mips::BLEZ:
10804 case Mips::BLEZ64:
10805 case Mips::BLEZL:
10806 case Mips::BLTZ:
10807 case Mips::BLTZ64:
10808 case Mips::BLTZAL:
10809 case Mips::BLTZALL:
10810 case Mips::BLTZL:
10811 case Mips::BNEZC:
10812 case Mips::BNEZC64:
10813 case Mips::BNEZC_MMR6: {
10814 switch (OpNum) {
10815 case 0:
10816 // op: rs
10817 return 21;
10818 case 1:
10819 // op: offset
10820 return 0;
10821 }
10822 break;
10823 }
10824 case Mips::BBIT0:
10825 case Mips::BBIT1:
10826 case Mips::BBIT032:
10827 case Mips::BBIT132: {
10828 switch (OpNum) {
10829 case 0:
10830 // op: rs
10831 return 21;
10832 case 1:
10833 // op: p
10834 return 16;
10835 case 2:
10836 // op: offset
10837 return 0;
10838 }
10839 break;
10840 }
10841 case Mips::TEQ:
10842 case Mips::TGE:
10843 case Mips::TGEU:
10844 case Mips::TLT:
10845 case Mips::TLTU:
10846 case Mips::TNE: {
10847 switch (OpNum) {
10848 case 0:
10849 // op: rs
10850 return 21;
10851 case 1:
10852 // op: rt
10853 return 16;
10854 case 2:
10855 // op: code_
10856 return 6;
10857 }
10858 break;
10859 }
10860 case Mips::BEQ:
10861 case Mips::BEQ64:
10862 case Mips::BEQC:
10863 case Mips::BEQC64:
10864 case Mips::BEQL:
10865 case Mips::BGEC:
10866 case Mips::BGEC64:
10867 case Mips::BGEUC:
10868 case Mips::BGEUC64:
10869 case Mips::BLTC:
10870 case Mips::BLTC64:
10871 case Mips::BLTUC:
10872 case Mips::BLTUC64:
10873 case Mips::BNE:
10874 case Mips::BNE64:
10875 case Mips::BNEC:
10876 case Mips::BNEC64:
10877 case Mips::BNEL:
10878 case Mips::BNVC:
10879 case Mips::BOVC: {
10880 switch (OpNum) {
10881 case 0:
10882 // op: rs
10883 return 21;
10884 case 1:
10885 // op: rt
10886 return 16;
10887 case 2:
10888 // op: offset
10889 return 0;
10890 }
10891 break;
10892 }
10893 case Mips::CMPU_EQ_QB:
10894 case Mips::CMPU_LE_QB:
10895 case Mips::CMPU_LT_QB:
10896 case Mips::CMP_EQ_PH:
10897 case Mips::CMP_LE_PH:
10898 case Mips::CMP_LT_PH:
10899 case Mips::DMULT:
10900 case Mips::DMULTu:
10901 case Mips::DSDIV:
10902 case Mips::DUDIV:
10903 case Mips::MADD:
10904 case Mips::MADDU:
10905 case Mips::MSUB:
10906 case Mips::MSUBU:
10907 case Mips::MULT:
10908 case Mips::MULTu:
10909 case Mips::SDIV:
10910 case Mips::UDIV: {
10911 switch (OpNum) {
10912 case 0:
10913 // op: rs
10914 return 21;
10915 case 1:
10916 // op: rt
10917 return 16;
10918 }
10919 break;
10920 }
10921 case Mips::GINVT: {
10922 switch (OpNum) {
10923 case 0:
10924 // op: rs
10925 return 21;
10926 case 1:
10927 // op: type_
10928 return 8;
10929 }
10930 break;
10931 }
10932 case Mips::DAHI:
10933 case Mips::DATI: {
10934 switch (OpNum) {
10935 case 0:
10936 // op: rs
10937 return 21;
10938 case 2:
10939 // op: imm
10940 return 0;
10941 }
10942 break;
10943 }
10944 case Mips::FORK: {
10945 switch (OpNum) {
10946 case 0:
10947 // op: rs
10948 return 21;
10949 case 2:
10950 // op: rt
10951 return 16;
10952 case 1:
10953 // op: rd
10954 return 11;
10955 }
10956 break;
10957 }
10958 case Mips::GINVI:
10959 case Mips::JR:
10960 case Mips::JR64:
10961 case Mips::JR_HB:
10962 case Mips::JR_HB64:
10963 case Mips::JR_HB64_R6:
10964 case Mips::JR_HB_R6:
10965 case Mips::MTHI:
10966 case Mips::MTHI64:
10967 case Mips::MTLO:
10968 case Mips::MTLO64:
10969 case Mips::MTM0:
10970 case Mips::MTM1:
10971 case Mips::MTM2:
10972 case Mips::MTP0:
10973 case Mips::MTP1:
10974 case Mips::MTP2: {
10975 switch (OpNum) {
10976 case 0:
10977 // op: rs
10978 return 21;
10979 }
10980 break;
10981 }
10982 case Mips::ADDIUPC_MM: {
10983 switch (OpNum) {
10984 case 0:
10985 // op: rs
10986 return 23;
10987 case 1:
10988 // op: imm
10989 return 0;
10990 }
10991 break;
10992 }
10993 case Mips::JALRC16_MMR6:
10994 case Mips::JRC16_MMR6: {
10995 switch (OpNum) {
10996 case 0:
10997 // op: rs
10998 return 5;
10999 }
11000 break;
11001 }
11002 case Mips::BEQZ16_MM:
11003 case Mips::BEQZC16_MMR6:
11004 case Mips::BNEZ16_MM:
11005 case Mips::BNEZC16_MMR6: {
11006 switch (OpNum) {
11007 case 0:
11008 // op: rs
11009 return 7;
11010 case 1:
11011 // op: offset
11012 return 0;
11013 }
11014 break;
11015 }
11016 case Mips::EXTP:
11017 case Mips::EXTPDP:
11018 case Mips::EXTPDPV:
11019 case Mips::EXTPV:
11020 case Mips::EXTRV_RS_W:
11021 case Mips::EXTRV_R_W:
11022 case Mips::EXTRV_S_H:
11023 case Mips::EXTRV_W:
11024 case Mips::EXTR_RS_W:
11025 case Mips::EXTR_R_W:
11026 case Mips::EXTR_S_H:
11027 case Mips::EXTR_W: {
11028 switch (OpNum) {
11029 case 0:
11030 // op: rt
11031 return 16;
11032 case 1:
11033 // op: ac
11034 return 11;
11035 case 2:
11036 // op: shift_rs
11037 return 21;
11038 }
11039 break;
11040 }
11041 case Mips::LB:
11042 case Mips::LB64:
11043 case Mips::LBu:
11044 case Mips::LBu64:
11045 case Mips::LD:
11046 case Mips::LDC1:
11047 case Mips::LDC2:
11048 case Mips::LDC2_R6:
11049 case Mips::LDC3:
11050 case Mips::LDC164:
11051 case Mips::LDL:
11052 case Mips::LDR:
11053 case Mips::LEA_ADDiu:
11054 case Mips::LEA_ADDiu64:
11055 case Mips::LH:
11056 case Mips::LH64:
11057 case Mips::LHu:
11058 case Mips::LHu64:
11059 case Mips::LL:
11060 case Mips::LL64:
11061 case Mips::LLD:
11062 case Mips::LW:
11063 case Mips::LW64:
11064 case Mips::LWC1:
11065 case Mips::LWC2:
11066 case Mips::LWC2_R6:
11067 case Mips::LWC3:
11068 case Mips::LWDSP:
11069 case Mips::LWL:
11070 case Mips::LWL64:
11071 case Mips::LWR:
11072 case Mips::LWR64:
11073 case Mips::LWu:
11074 case Mips::SB:
11075 case Mips::SB64:
11076 case Mips::SD:
11077 case Mips::SDC1:
11078 case Mips::SDC2:
11079 case Mips::SDC2_R6:
11080 case Mips::SDC3:
11081 case Mips::SDC164:
11082 case Mips::SDL:
11083 case Mips::SDR:
11084 case Mips::SH:
11085 case Mips::SH64:
11086 case Mips::SW:
11087 case Mips::SW64:
11088 case Mips::SWC1:
11089 case Mips::SWC2:
11090 case Mips::SWC2_R6:
11091 case Mips::SWC3:
11092 case Mips::SWDSP:
11093 case Mips::SWL:
11094 case Mips::SWL64:
11095 case Mips::SWR:
11096 case Mips::SWR64: {
11097 switch (OpNum) {
11098 case 0:
11099 // op: rt
11100 return 16;
11101 case 1:
11102 // op: addr
11103 return 0;
11104 }
11105 break;
11106 }
11107 case Mips::LL64_R6:
11108 case Mips::LLD_R6:
11109 case Mips::LL_R6: {
11110 switch (OpNum) {
11111 case 0:
11112 // op: rt
11113 return 16;
11114 case 1:
11115 // op: addr
11116 return 7;
11117 }
11118 break;
11119 }
11120 case Mips::CFC1:
11121 case Mips::DMFC1:
11122 case Mips::MFC1:
11123 case Mips::MFC1_D64:
11124 case Mips::MFHC1_D32:
11125 case Mips::MFHC1_D64: {
11126 switch (OpNum) {
11127 case 0:
11128 // op: rt
11129 return 16;
11130 case 1:
11131 // op: fs
11132 return 11;
11133 }
11134 break;
11135 }
11136 case Mips::DMFC2_OCTEON:
11137 case Mips::DMTC2_OCTEON:
11138 case Mips::LUi:
11139 case Mips::LUi64:
11140 case Mips::LUi_MM: {
11141 switch (OpNum) {
11142 case 0:
11143 // op: rt
11144 return 16;
11145 case 1:
11146 // op: imm16
11147 return 0;
11148 }
11149 break;
11150 }
11151 case Mips::BC1EQZC_MMR6:
11152 case Mips::BC1NEZC_MMR6:
11153 case Mips::BC2EQZC_MMR6:
11154 case Mips::BC2NEZC_MMR6:
11155 case Mips::BEQZALC:
11156 case Mips::BGEZALC:
11157 case Mips::BGEZALC_MMR6:
11158 case Mips::BGEZC:
11159 case Mips::BGEZC64:
11160 case Mips::BGEZC_MMR6:
11161 case Mips::BGTZALC:
11162 case Mips::BGTZC:
11163 case Mips::BGTZC64:
11164 case Mips::BLEZALC:
11165 case Mips::BLEZC:
11166 case Mips::BLEZC64:
11167 case Mips::BLTZALC:
11168 case Mips::BLTZALC_MMR6:
11169 case Mips::BLTZC:
11170 case Mips::BLTZC64:
11171 case Mips::BLTZC_MMR6:
11172 case Mips::BNEZALC:
11173 case Mips::JIALC:
11174 case Mips::JIALC64:
11175 case Mips::JIALC_MMR6:
11176 case Mips::JIC:
11177 case Mips::JIC64:
11178 case Mips::JIC_MMR6: {
11179 switch (OpNum) {
11180 case 0:
11181 // op: rt
11182 return 16;
11183 case 1:
11184 // op: offset
11185 return 0;
11186 }
11187 break;
11188 }
11189 case Mips::DMFC0:
11190 case Mips::DMFC2:
11191 case Mips::DMFGC0:
11192 case Mips::MFC0:
11193 case Mips::MFC2:
11194 case Mips::MFGC0:
11195 case Mips::MFHGC0: {
11196 switch (OpNum) {
11197 case 0:
11198 // op: rt
11199 return 16;
11200 case 1:
11201 // op: rd
11202 return 11;
11203 case 2:
11204 // op: sel
11205 return 0;
11206 }
11207 break;
11208 }
11209 case Mips::RDHWR:
11210 case Mips::RDHWR64: {
11211 switch (OpNum) {
11212 case 0:
11213 // op: rt
11214 return 16;
11215 case 1:
11216 // op: rd
11217 return 11;
11218 case 2:
11219 // op: sel
11220 return 6;
11221 }
11222 break;
11223 }
11224 case Mips::SLTi:
11225 case Mips::SLTi64:
11226 case Mips::SLTiu:
11227 case Mips::SLTiu64: {
11228 switch (OpNum) {
11229 case 0:
11230 // op: rt
11231 return 16;
11232 case 1:
11233 // op: rs
11234 return 21;
11235 case 2:
11236 // op: imm16
11237 return 0;
11238 }
11239 break;
11240 }
11241 case Mips::CINS:
11242 case Mips::CINS32:
11243 case Mips::CINS64_32:
11244 case Mips::CINS_i32:
11245 case Mips::EXTS:
11246 case Mips::EXTS32: {
11247 switch (OpNum) {
11248 case 0:
11249 // op: rt
11250 return 16;
11251 case 1:
11252 // op: rs
11253 return 21;
11254 case 2:
11255 // op: pos
11256 return 6;
11257 case 3:
11258 // op: lenm1
11259 return 11;
11260 }
11261 break;
11262 }
11263 case Mips::DEXT:
11264 case Mips::DEXT64_32:
11265 case Mips::DEXTM:
11266 case Mips::DEXTU:
11267 case Mips::DINS:
11268 case Mips::DINSM:
11269 case Mips::DINSU:
11270 case Mips::EXT:
11271 case Mips::INS: {
11272 switch (OpNum) {
11273 case 0:
11274 // op: rt
11275 return 16;
11276 case 1:
11277 // op: rs
11278 return 21;
11279 case 2:
11280 // op: pos
11281 return 6;
11282 case 3:
11283 // op: size
11284 return 11;
11285 }
11286 break;
11287 }
11288 case Mips::APPEND:
11289 case Mips::BALIGN:
11290 case Mips::PREPEND: {
11291 switch (OpNum) {
11292 case 0:
11293 // op: rt
11294 return 16;
11295 case 1:
11296 // op: rs
11297 return 21;
11298 case 2:
11299 // op: sa
11300 return 11;
11301 }
11302 break;
11303 }
11304 case Mips::SAA:
11305 case Mips::SAAD: {
11306 switch (OpNum) {
11307 case 0:
11308 // op: rt
11309 return 16;
11310 case 1:
11311 // op: rs
11312 return 21;
11313 }
11314 break;
11315 }
11316 case Mips::INSV: {
11317 switch (OpNum) {
11318 case 0:
11319 // op: rt
11320 return 16;
11321 case 2:
11322 // op: rs
11323 return 21;
11324 }
11325 break;
11326 }
11327 case Mips::DI:
11328 case Mips::DI_MM:
11329 case Mips::DI_MMR6:
11330 case Mips::DMT:
11331 case Mips::DVP:
11332 case Mips::DVPE:
11333 case Mips::EI:
11334 case Mips::EI_MM:
11335 case Mips::EI_MMR6:
11336 case Mips::EMT:
11337 case Mips::EVP:
11338 case Mips::EVPE: {
11339 switch (OpNum) {
11340 case 0:
11341 // op: rt
11342 return 16;
11343 }
11344 break;
11345 }
11346 case Mips::LBE_MM:
11347 case Mips::LB_MM:
11348 case Mips::LBuE_MM:
11349 case Mips::LBu_MM:
11350 case Mips::LDC1_MM_D32:
11351 case Mips::LDC1_MM_D64:
11352 case Mips::LDC2_MMR6:
11353 case Mips::LEA_ADDiu_MM:
11354 case Mips::LHE_MM:
11355 case Mips::LH_MM:
11356 case Mips::LHuE_MM:
11357 case Mips::LHu_MM:
11358 case Mips::LLE_MM:
11359 case Mips::LL_MM:
11360 case Mips::LL_MMR6:
11361 case Mips::LWC1_MM:
11362 case Mips::LWC2_MMR6:
11363 case Mips::LWDSP_MM:
11364 case Mips::LWE_MM:
11365 case Mips::LWLE_MM:
11366 case Mips::LWL_MM:
11367 case Mips::LWM32_MM:
11368 case Mips::LWRE_MM:
11369 case Mips::LWR_MM:
11370 case Mips::LWU_MM:
11371 case Mips::LW_MM:
11372 case Mips::LW_MMR6:
11373 case Mips::SBE_MM:
11374 case Mips::SB_MM:
11375 case Mips::SB_MMR6:
11376 case Mips::SDC1_MM_D32:
11377 case Mips::SDC1_MM_D64:
11378 case Mips::SDC2_MMR6:
11379 case Mips::SHE_MM:
11380 case Mips::SH_MM:
11381 case Mips::SH_MMR6:
11382 case Mips::SWC1_MM:
11383 case Mips::SWC2_MMR6:
11384 case Mips::SWDSP_MM:
11385 case Mips::SWE_MM:
11386 case Mips::SWLE_MM:
11387 case Mips::SWL_MM:
11388 case Mips::SWM32_MM:
11389 case Mips::SWRE_MM:
11390 case Mips::SWR_MM:
11391 case Mips::SW_MM:
11392 case Mips::SW_MMR6: {
11393 switch (OpNum) {
11394 case 0:
11395 // op: rt
11396 return 21;
11397 case 1:
11398 // op: addr
11399 return 0;
11400 }
11401 break;
11402 }
11403 case Mips::CFC1_MM:
11404 case Mips::MFC1_MM:
11405 case Mips::MFC1_MMR6:
11406 case Mips::MFHC1_D32_MM:
11407 case Mips::MFHC1_D64_MM: {
11408 switch (OpNum) {
11409 case 0:
11410 // op: rt
11411 return 21;
11412 case 1:
11413 // op: fs
11414 return 16;
11415 }
11416 break;
11417 }
11418 case Mips::ADDIUPC_MMR6:
11419 case Mips::ALUIPC_MMR6:
11420 case Mips::AUIPC_MMR6:
11421 case Mips::LWPC_MMR6: {
11422 switch (OpNum) {
11423 case 0:
11424 // op: rt
11425 return 21;
11426 case 1:
11427 // op: imm
11428 return 0;
11429 }
11430 break;
11431 }
11432 case Mips::REPL_QB_MM: {
11433 switch (OpNum) {
11434 case 0:
11435 // op: rt
11436 return 21;
11437 case 1:
11438 // op: imm
11439 return 13;
11440 }
11441 break;
11442 }
11443 case Mips::LUI_MMR6: {
11444 switch (OpNum) {
11445 case 0:
11446 // op: rt
11447 return 21;
11448 case 1:
11449 // op: imm16
11450 return 0;
11451 }
11452 break;
11453 }
11454 case Mips::CFC2_MM:
11455 case Mips::MFC2_MMR6:
11456 case Mips::MFHC2_MMR6: {
11457 switch (OpNum) {
11458 case 0:
11459 // op: rt
11460 return 21;
11461 case 1:
11462 // op: impl
11463 return 16;
11464 }
11465 break;
11466 }
11467 case Mips::RDDSP_MM:
11468 case Mips::WRDSP_MM: {
11469 switch (OpNum) {
11470 case 0:
11471 // op: rt
11472 return 21;
11473 case 1:
11474 // op: mask
11475 return 14;
11476 }
11477 break;
11478 }
11479 case Mips::BEQZALC_MMR6:
11480 case Mips::BGTZALC_MMR6:
11481 case Mips::BGTZC_MMR6:
11482 case Mips::BLEZALC_MMR6:
11483 case Mips::BLEZC_MMR6:
11484 case Mips::BNEZALC_MMR6: {
11485 switch (OpNum) {
11486 case 0:
11487 // op: rt
11488 return 21;
11489 case 1:
11490 // op: offset
11491 return 0;
11492 }
11493 break;
11494 }
11495 case Mips::RDHWR_MM:
11496 case Mips::RDPGPR_MMR6: {
11497 switch (OpNum) {
11498 case 0:
11499 // op: rt
11500 return 21;
11501 case 1:
11502 // op: rd
11503 return 16;
11504 }
11505 break;
11506 }
11507 case Mips::BALIGN_MMR2: {
11508 switch (OpNum) {
11509 case 0:
11510 // op: rt
11511 return 21;
11512 case 1:
11513 // op: rs
11514 return 16;
11515 case 2:
11516 // op: bp
11517 return 14;
11518 }
11519 break;
11520 }
11521 case Mips::ADDIU_MMR6:
11522 case Mips::ANDI_MMR6:
11523 case Mips::ORI_MMR6:
11524 case Mips::SLTi_MM:
11525 case Mips::SLTiu_MM:
11526 case Mips::XORI_MMR6: {
11527 switch (OpNum) {
11528 case 0:
11529 // op: rt
11530 return 21;
11531 case 1:
11532 // op: rs
11533 return 16;
11534 case 2:
11535 // op: imm16
11536 return 0;
11537 }
11538 break;
11539 }
11540 case Mips::BNVC_MMR6:
11541 case Mips::BOVC_MMR6: {
11542 switch (OpNum) {
11543 case 0:
11544 // op: rt
11545 return 21;
11546 case 1:
11547 // op: rs
11548 return 16;
11549 case 2:
11550 // op: offset
11551 return 0;
11552 }
11553 break;
11554 }
11555 case Mips::EXT_MM:
11556 case Mips::INS_MM: {
11557 switch (OpNum) {
11558 case 0:
11559 // op: rt
11560 return 21;
11561 case 1:
11562 // op: rs
11563 return 16;
11564 case 2:
11565 // op: pos
11566 return 6;
11567 case 3:
11568 // op: size
11569 return 11;
11570 }
11571 break;
11572 }
11573 case Mips::APPEND_MMR2:
11574 case Mips::PRECR_SRA_PH_W_MMR2:
11575 case Mips::PRECR_SRA_R_PH_W_MMR2:
11576 case Mips::PREPEND_MMR2:
11577 case Mips::SHLL_S_W_MM:
11578 case Mips::SHRA_R_W_MM: {
11579 switch (OpNum) {
11580 case 0:
11581 // op: rt
11582 return 21;
11583 case 1:
11584 // op: rs
11585 return 16;
11586 case 2:
11587 // op: sa
11588 return 11;
11589 }
11590 break;
11591 }
11592 case Mips::SHLL_PH_MM:
11593 case Mips::SHLL_S_PH_MM:
11594 case Mips::SHRA_PH_MM:
11595 case Mips::SHRA_R_PH_MM:
11596 case Mips::SHRL_PH_MMR2: {
11597 switch (OpNum) {
11598 case 0:
11599 // op: rt
11600 return 21;
11601 case 1:
11602 // op: rs
11603 return 16;
11604 case 2:
11605 // op: sa
11606 return 12;
11607 }
11608 break;
11609 }
11610 case Mips::SHLL_QB_MM:
11611 case Mips::SHRA_QB_MMR2:
11612 case Mips::SHRA_R_QB_MMR2:
11613 case Mips::SHRL_QB_MM: {
11614 switch (OpNum) {
11615 case 0:
11616 // op: rt
11617 return 21;
11618 case 1:
11619 // op: rs
11620 return 16;
11621 case 2:
11622 // op: sa
11623 return 13;
11624 }
11625 break;
11626 }
11627 case Mips::MFC0_MMR6:
11628 case Mips::MFGC0_MM:
11629 case Mips::MFHC0_MMR6:
11630 case Mips::MFHGC0_MM:
11631 case Mips::RDHWR_MMR6: {
11632 switch (OpNum) {
11633 case 0:
11634 // op: rt
11635 return 21;
11636 case 1:
11637 // op: rs
11638 return 16;
11639 case 2:
11640 // op: sel
11641 return 11;
11642 }
11643 break;
11644 }
11645 case Mips::EXT_MMR6:
11646 case Mips::INS_MMR6: {
11647 switch (OpNum) {
11648 case 0:
11649 // op: rt
11650 return 21;
11651 case 1:
11652 // op: rs
11653 return 16;
11654 case 3:
11655 // op: size
11656 return 11;
11657 case 2:
11658 // op: pos
11659 return 6;
11660 }
11661 break;
11662 }
11663 case Mips::ABSQ_S_PH_MM:
11664 case Mips::ABSQ_S_QB_MMR2:
11665 case Mips::ABSQ_S_W_MM:
11666 case Mips::BITREV_MM:
11667 case Mips::JALRC_HB_MMR6:
11668 case Mips::JALRC_MMR6:
11669 case Mips::PRECEQU_PH_QBLA_MM:
11670 case Mips::PRECEQU_PH_QBL_MM:
11671 case Mips::PRECEQU_PH_QBRA_MM:
11672 case Mips::PRECEQU_PH_QBR_MM:
11673 case Mips::PRECEQ_W_PHL_MM:
11674 case Mips::PRECEQ_W_PHR_MM:
11675 case Mips::PRECEU_PH_QBLA_MM:
11676 case Mips::PRECEU_PH_QBL_MM:
11677 case Mips::PRECEU_PH_QBRA_MM:
11678 case Mips::PRECEU_PH_QBR_MM:
11679 case Mips::RADDU_W_QB_MM:
11680 case Mips::REPLV_PH_MM:
11681 case Mips::REPLV_QB_MM:
11682 case Mips::WRPGPR_MMR6:
11683 case Mips::WSBH_MMR6: {
11684 switch (OpNum) {
11685 case 0:
11686 // op: rt
11687 return 21;
11688 case 1:
11689 // op: rs
11690 return 16;
11691 }
11692 break;
11693 }
11694 case Mips::LWP_MM:
11695 case Mips::SWP_MM: {
11696 switch (OpNum) {
11697 case 0:
11698 // op: rt
11699 return 21;
11700 case 2:
11701 // op: addr
11702 return 0;
11703 }
11704 break;
11705 }
11706 case Mips::EXTPDP_MM:
11707 case Mips::EXTP_MM:
11708 case Mips::EXTR_RS_W_MM:
11709 case Mips::EXTR_R_W_MM:
11710 case Mips::EXTR_S_H_MM:
11711 case Mips::EXTR_W_MM: {
11712 switch (OpNum) {
11713 case 0:
11714 // op: rt
11715 return 21;
11716 case 2:
11717 // op: imm
11718 return 16;
11719 case 1:
11720 // op: ac
11721 return 14;
11722 }
11723 break;
11724 }
11725 case Mips::EXTPDPV_MM:
11726 case Mips::EXTPV_MM:
11727 case Mips::EXTRV_RS_W_MM:
11728 case Mips::EXTRV_R_W_MM:
11729 case Mips::EXTRV_S_H_MM:
11730 case Mips::EXTRV_W_MM: {
11731 switch (OpNum) {
11732 case 0:
11733 // op: rt
11734 return 21;
11735 case 2:
11736 // op: rs
11737 return 16;
11738 case 1:
11739 // op: ac
11740 return 14;
11741 }
11742 break;
11743 }
11744 case Mips::INSV_MM: {
11745 switch (OpNum) {
11746 case 0:
11747 // op: rt
11748 return 21;
11749 case 2:
11750 // op: rs
11751 return 16;
11752 }
11753 break;
11754 }
11755 case Mips::NOT16_MM: {
11756 switch (OpNum) {
11757 case 0:
11758 // op: rt
11759 return 3;
11760 case 1:
11761 // op: rs
11762 return 0;
11763 }
11764 break;
11765 }
11766 case Mips::LWM16_MM:
11767 case Mips::SWM16_MM: {
11768 switch (OpNum) {
11769 case 0:
11770 // op: rt
11771 return 4;
11772 case 1:
11773 // op: addr
11774 return 0;
11775 }
11776 break;
11777 }
11778 case Mips::LWSP_MM:
11779 case Mips::SWSP_MM:
11780 case Mips::SWSP_MMR6: {
11781 switch (OpNum) {
11782 case 0:
11783 // op: rt
11784 return 5;
11785 case 1:
11786 // op: offset
11787 return 0;
11788 }
11789 break;
11790 }
11791 case Mips::LBU16_MM:
11792 case Mips::LHU16_MM:
11793 case Mips::LW16_MM:
11794 case Mips::SB16_MM:
11795 case Mips::SB16_MMR6:
11796 case Mips::SH16_MM:
11797 case Mips::SH16_MMR6:
11798 case Mips::SW16_MM:
11799 case Mips::SW16_MMR6: {
11800 switch (OpNum) {
11801 case 0:
11802 // op: rt
11803 return 7;
11804 case 1:
11805 // op: addr
11806 return 0;
11807 }
11808 break;
11809 }
11810 case Mips::LWGP_MM: {
11811 switch (OpNum) {
11812 case 0:
11813 // op: rt
11814 return 7;
11815 case 1:
11816 // op: offset
11817 return 0;
11818 }
11819 break;
11820 }
11821 case Mips::NOT16_MMR6: {
11822 switch (OpNum) {
11823 case 0:
11824 // op: rt
11825 return 7;
11826 case 1:
11827 // op: rs
11828 return 4;
11829 }
11830 break;
11831 }
11832 case Mips::LWM16_MMR6:
11833 case Mips::SWM16_MMR6: {
11834 switch (OpNum) {
11835 case 0:
11836 // op: rt
11837 return 8;
11838 case 1:
11839 // op: addr
11840 return 4;
11841 }
11842 break;
11843 }
11844 case Mips::BeqzRxImm16:
11845 case Mips::BnezRxImm16:
11846 case Mips::CmpiRxImm16:
11847 case Mips::LiRxImm16:
11848 case Mips::LwRxPcTcp16:
11849 case Mips::SltiRxImm16:
11850 case Mips::SltiuRxImm16: {
11851 switch (OpNum) {
11852 case 0:
11853 // op: rx
11854 return 8;
11855 case 1:
11856 // op: imm8
11857 return 0;
11858 }
11859 break;
11860 }
11861 case Mips::CmpRxRy16:
11862 case Mips::DivRxRy16:
11863 case Mips::DivuRxRy16:
11864 case Mips::NegRxRy16:
11865 case Mips::NotRxRy16:
11866 case Mips::SltRxRy16:
11867 case Mips::SltuRxRy16: {
11868 switch (OpNum) {
11869 case 0:
11870 // op: rx
11871 return 8;
11872 case 1:
11873 // op: ry
11874 return 5;
11875 }
11876 break;
11877 }
11878 case Mips::AddiuRxRxImm16: {
11879 switch (OpNum) {
11880 case 0:
11881 // op: rx
11882 return 8;
11883 case 2:
11884 // op: imm8
11885 return 0;
11886 }
11887 break;
11888 }
11889 case Mips::JumpLinkReg16:
11890 case Mips::Mfhi16:
11891 case Mips::Mflo16:
11892 case Mips::SebRx16:
11893 case Mips::SehRx16: {
11894 switch (OpNum) {
11895 case 0:
11896 // op: rx
11897 return 8;
11898 }
11899 break;
11900 }
11901 case Mips::MoveR3216: {
11902 switch (OpNum) {
11903 case 0:
11904 // op: ry
11905 return 4;
11906 case 1:
11907 // op: r32
11908 return 0;
11909 }
11910 break;
11911 }
11912 case Mips::SYNC_MM:
11913 case Mips::SYNC_MMR6: {
11914 switch (OpNum) {
11915 case 0:
11916 // op: stype
11917 return 16;
11918 }
11919 break;
11920 }
11921 case Mips::SYNC: {
11922 switch (OpNum) {
11923 case 0:
11924 // op: stype
11925 return 6;
11926 }
11927 break;
11928 }
11929 case Mips::J:
11930 case Mips::JAL:
11931 case Mips::JALS_MM:
11932 case Mips::JALX:
11933 case Mips::JALX_MM:
11934 case Mips::JAL_MM:
11935 case Mips::J_MM: {
11936 switch (OpNum) {
11937 case 0:
11938 // op: target
11939 return 0;
11940 }
11941 break;
11942 }
11943 case Mips::LBU_MMR6:
11944 case Mips::LB_MMR6: {
11945 switch (OpNum) {
11946 case 1:
11947 // op: addr
11948 return 0;
11949 case 0:
11950 // op: rt
11951 return 21;
11952 }
11953 break;
11954 }
11955 case Mips::LD_B:
11956 case Mips::LD_D:
11957 case Mips::LD_H:
11958 case Mips::LD_W:
11959 case Mips::ST_B:
11960 case Mips::ST_D:
11961 case Mips::ST_H:
11962 case Mips::ST_W: {
11963 switch (OpNum) {
11964 case 1:
11965 // op: addr
11966 return 11;
11967 case 0:
11968 // op: wd
11969 return 6;
11970 }
11971 break;
11972 }
11973 case Mips::LBE:
11974 case Mips::LBuE:
11975 case Mips::LHE:
11976 case Mips::LHuE:
11977 case Mips::LLE:
11978 case Mips::LWE:
11979 case Mips::LWLE:
11980 case Mips::LWRE:
11981 case Mips::SBE:
11982 case Mips::SHE:
11983 case Mips::SWE:
11984 case Mips::SWLE:
11985 case Mips::SWRE: {
11986 switch (OpNum) {
11987 case 1:
11988 // op: addr
11989 return 7;
11990 case 0:
11991 // op: rt
11992 return 16;
11993 }
11994 break;
11995 }
11996 case Mips::CLASS_D:
11997 case Mips::CLASS_S:
11998 case Mips::RINT_D:
11999 case Mips::RINT_S: {
12000 switch (OpNum) {
12001 case 1:
12002 // op: fs
12003 return 11;
12004 case 0:
12005 // op: fd
12006 return 6;
12007 }
12008 break;
12009 }
12010 case Mips::C_EQ_D32:
12011 case Mips::C_EQ_D64:
12012 case Mips::C_EQ_S:
12013 case Mips::C_F_D32:
12014 case Mips::C_F_D64:
12015 case Mips::C_F_S:
12016 case Mips::C_LE_D32:
12017 case Mips::C_LE_D64:
12018 case Mips::C_LE_S:
12019 case Mips::C_LT_D32:
12020 case Mips::C_LT_D64:
12021 case Mips::C_LT_S:
12022 case Mips::C_NGE_D32:
12023 case Mips::C_NGE_D64:
12024 case Mips::C_NGE_S:
12025 case Mips::C_NGLE_D32:
12026 case Mips::C_NGLE_D64:
12027 case Mips::C_NGLE_S:
12028 case Mips::C_NGL_D32:
12029 case Mips::C_NGL_D64:
12030 case Mips::C_NGL_S:
12031 case Mips::C_NGT_D32:
12032 case Mips::C_NGT_D64:
12033 case Mips::C_NGT_S:
12034 case Mips::C_OLE_D32:
12035 case Mips::C_OLE_D64:
12036 case Mips::C_OLE_S:
12037 case Mips::C_OLT_D32:
12038 case Mips::C_OLT_D64:
12039 case Mips::C_OLT_S:
12040 case Mips::C_SEQ_D32:
12041 case Mips::C_SEQ_D64:
12042 case Mips::C_SEQ_S:
12043 case Mips::C_SF_D32:
12044 case Mips::C_SF_D64:
12045 case Mips::C_SF_S:
12046 case Mips::C_UEQ_D32:
12047 case Mips::C_UEQ_D64:
12048 case Mips::C_UEQ_S:
12049 case Mips::C_ULE_D32:
12050 case Mips::C_ULE_D64:
12051 case Mips::C_ULE_S:
12052 case Mips::C_ULT_D32:
12053 case Mips::C_ULT_D64:
12054 case Mips::C_ULT_S:
12055 case Mips::C_UN_D32:
12056 case Mips::C_UN_D64:
12057 case Mips::C_UN_S: {
12058 switch (OpNum) {
12059 case 1:
12060 // op: fs
12061 return 11;
12062 case 2:
12063 // op: ft
12064 return 16;
12065 case 0:
12066 // op: fcc
12067 return 8;
12068 }
12069 break;
12070 }
12071 case Mips::C_EQ_D32_MM:
12072 case Mips::C_EQ_D64_MM:
12073 case Mips::C_EQ_S_MM:
12074 case Mips::C_F_D32_MM:
12075 case Mips::C_F_D64_MM:
12076 case Mips::C_F_S_MM:
12077 case Mips::C_LE_D32_MM:
12078 case Mips::C_LE_D64_MM:
12079 case Mips::C_LE_S_MM:
12080 case Mips::C_LT_D32_MM:
12081 case Mips::C_LT_D64_MM:
12082 case Mips::C_LT_S_MM:
12083 case Mips::C_NGE_D32_MM:
12084 case Mips::C_NGE_D64_MM:
12085 case Mips::C_NGE_S_MM:
12086 case Mips::C_NGLE_D32_MM:
12087 case Mips::C_NGLE_D64_MM:
12088 case Mips::C_NGLE_S_MM:
12089 case Mips::C_NGL_D32_MM:
12090 case Mips::C_NGL_D64_MM:
12091 case Mips::C_NGL_S_MM:
12092 case Mips::C_NGT_D32_MM:
12093 case Mips::C_NGT_D64_MM:
12094 case Mips::C_NGT_S_MM:
12095 case Mips::C_OLE_D32_MM:
12096 case Mips::C_OLE_D64_MM:
12097 case Mips::C_OLE_S_MM:
12098 case Mips::C_OLT_D32_MM:
12099 case Mips::C_OLT_D64_MM:
12100 case Mips::C_OLT_S_MM:
12101 case Mips::C_SEQ_D32_MM:
12102 case Mips::C_SEQ_D64_MM:
12103 case Mips::C_SEQ_S_MM:
12104 case Mips::C_SF_D32_MM:
12105 case Mips::C_SF_D64_MM:
12106 case Mips::C_SF_S_MM:
12107 case Mips::C_UEQ_D32_MM:
12108 case Mips::C_UEQ_D64_MM:
12109 case Mips::C_UEQ_S_MM:
12110 case Mips::C_ULE_D32_MM:
12111 case Mips::C_ULE_D64_MM:
12112 case Mips::C_ULE_S_MM:
12113 case Mips::C_ULT_D32_MM:
12114 case Mips::C_ULT_D64_MM:
12115 case Mips::C_ULT_S_MM:
12116 case Mips::C_UN_D32_MM:
12117 case Mips::C_UN_D64_MM:
12118 case Mips::C_UN_S_MM: {
12119 switch (OpNum) {
12120 case 1:
12121 // op: fs
12122 return 16;
12123 case 2:
12124 // op: ft
12125 return 21;
12126 case 0:
12127 // op: fcc
12128 return 13;
12129 }
12130 break;
12131 }
12132 case Mips::CLASS_D_MMR6:
12133 case Mips::CLASS_S_MMR6:
12134 case Mips::RINT_D_MMR6:
12135 case Mips::RINT_S_MMR6: {
12136 switch (OpNum) {
12137 case 1:
12138 // op: fs
12139 return 21;
12140 case 0:
12141 // op: fd
12142 return 16;
12143 }
12144 break;
12145 }
12146 case Mips::FADD_S_MMR6:
12147 case Mips::FDIV_S_MMR6:
12148 case Mips::FMUL_S_MMR6:
12149 case Mips::FSUB_S_MMR6: {
12150 switch (OpNum) {
12151 case 1:
12152 // op: ft
12153 return 21;
12154 case 2:
12155 // op: fs
12156 return 16;
12157 case 0:
12158 // op: fd
12159 return 11;
12160 }
12161 break;
12162 }
12163 case Mips::AddiuRxImmX16:
12164 case Mips::AddiuRxPcImmX16:
12165 case Mips::BeqzRxImmX16:
12166 case Mips::BnezRxImmX16:
12167 case Mips::CmpiRxImmX16:
12168 case Mips::LiRxImmAlignX16:
12169 case Mips::LiRxImmX16:
12170 case Mips::LwRxPcTcpX16:
12171 case Mips::SltiRxImmX16:
12172 case Mips::SltiuRxImmX16: {
12173 switch (OpNum) {
12174 case 1:
12175 // op: imm16
12176 return 0;
12177 case 0:
12178 // op: rx
12179 return 8;
12180 }
12181 break;
12182 }
12183 case Mips::PREFX_MM: {
12184 switch (OpNum) {
12185 case 1:
12186 // op: index
12187 return 21;
12188 case 0:
12189 // op: base
12190 return 16;
12191 case 2:
12192 // op: hint
12193 return 11;
12194 }
12195 break;
12196 }
12197 case Mips::BNZ_B:
12198 case Mips::BNZ_D:
12199 case Mips::BNZ_H:
12200 case Mips::BNZ_V:
12201 case Mips::BNZ_W:
12202 case Mips::BZ_B:
12203 case Mips::BZ_D:
12204 case Mips::BZ_H:
12205 case Mips::BZ_V:
12206 case Mips::BZ_W: {
12207 switch (OpNum) {
12208 case 1:
12209 // op: offset
12210 return 0;
12211 case 0:
12212 // op: wt
12213 return 16;
12214 }
12215 break;
12216 }
12217 case Mips::ADDIUS5_MM: {
12218 switch (OpNum) {
12219 case 1:
12220 // op: rd
12221 return 5;
12222 case 2:
12223 // op: imm
12224 return 1;
12225 }
12226 break;
12227 }
12228 case Mips::MOVE16_MM:
12229 case Mips::MOVE16_MMR6: {
12230 switch (OpNum) {
12231 case 1:
12232 // op: rs
12233 return 0;
12234 case 0:
12235 // op: rd
12236 return 5;
12237 }
12238 break;
12239 }
12240 case Mips::CTCMSA: {
12241 switch (OpNum) {
12242 case 1:
12243 // op: rs
12244 return 11;
12245 case 0:
12246 // op: cd
12247 return 6;
12248 }
12249 break;
12250 }
12251 case Mips::FILL_B:
12252 case Mips::FILL_D:
12253 case Mips::FILL_H:
12254 case Mips::FILL_W: {
12255 switch (OpNum) {
12256 case 1:
12257 // op: rs
12258 return 11;
12259 case 0:
12260 // op: wd
12261 return 6;
12262 }
12263 break;
12264 }
12265 case Mips::MTHI_DSP_MM:
12266 case Mips::MTHLIP_MM:
12267 case Mips::MTLO_DSP_MM:
12268 case Mips::SHILOV_MM: {
12269 switch (OpNum) {
12270 case 1:
12271 // op: rs
12272 return 16;
12273 case 0:
12274 // op: ac
12275 return 14;
12276 }
12277 break;
12278 }
12279 case Mips::JALRS_MM:
12280 case Mips::JALR_MM: {
12281 switch (OpNum) {
12282 case 1:
12283 // op: rs
12284 return 16;
12285 case 0:
12286 // op: rd
12287 return 21;
12288 }
12289 break;
12290 }
12291 case Mips::AUI_MMR6: {
12292 switch (OpNum) {
12293 case 1:
12294 // op: rs
12295 return 16;
12296 case 0:
12297 // op: rt
12298 return 21;
12299 case 2:
12300 // op: imm
12301 return 0;
12302 }
12303 break;
12304 }
12305 case Mips::ADDi_MM:
12306 case Mips::ADDiu_MM:
12307 case Mips::ANDi_MM:
12308 case Mips::ORi_MM:
12309 case Mips::XORi_MM: {
12310 switch (OpNum) {
12311 case 1:
12312 // op: rs
12313 return 16;
12314 case 0:
12315 // op: rt
12316 return 21;
12317 case 2:
12318 // op: imm16
12319 return 0;
12320 }
12321 break;
12322 }
12323 case Mips::CLO_MMR6: {
12324 switch (OpNum) {
12325 case 1:
12326 // op: rs
12327 return 16;
12328 case 0:
12329 // op: rt
12330 return 21;
12331 }
12332 break;
12333 }
12334 case Mips::MTHI_DSP:
12335 case Mips::MTLO_DSP: {
12336 switch (OpNum) {
12337 case 1:
12338 // op: rs
12339 return 21;
12340 case 0:
12341 // op: ac
12342 return 11;
12343 }
12344 break;
12345 }
12346 case Mips::YIELD: {
12347 switch (OpNum) {
12348 case 1:
12349 // op: rs
12350 return 21;
12351 case 0:
12352 // op: rd
12353 return 11;
12354 }
12355 break;
12356 }
12357 case Mips::CLZ_MMR6: {
12358 switch (OpNum) {
12359 case 1:
12360 // op: rs
12361 return 21;
12362 case 0:
12363 // op: rt
12364 return 11;
12365 }
12366 break;
12367 }
12368 case Mips::AUI:
12369 case Mips::DAUI: {
12370 switch (OpNum) {
12371 case 1:
12372 // op: rs
12373 return 21;
12374 case 0:
12375 // op: rt
12376 return 16;
12377 case 2:
12378 // op: imm
12379 return 0;
12380 }
12381 break;
12382 }
12383 case Mips::SEQi:
12384 case Mips::SNEi: {
12385 switch (OpNum) {
12386 case 1:
12387 // op: rs
12388 return 21;
12389 case 0:
12390 // op: rt
12391 return 16;
12392 case 2:
12393 // op: imm10
12394 return 6;
12395 }
12396 break;
12397 }
12398 case Mips::ADDi:
12399 case Mips::ADDiu:
12400 case Mips::ANDi:
12401 case Mips::ANDi64:
12402 case Mips::DADDi:
12403 case Mips::DADDiu:
12404 case Mips::ORi:
12405 case Mips::ORi64:
12406 case Mips::XORi:
12407 case Mips::XORi64: {
12408 switch (OpNum) {
12409 case 1:
12410 // op: rs
12411 return 21;
12412 case 0:
12413 // op: rt
12414 return 16;
12415 case 2:
12416 // op: imm16
12417 return 0;
12418 }
12419 break;
12420 }
12421 case Mips::PRECR_SRA_PH_W:
12422 case Mips::PRECR_SRA_R_PH_W: {
12423 switch (OpNum) {
12424 case 1:
12425 // op: rs
12426 return 21;
12427 case 0:
12428 // op: rt
12429 return 16;
12430 case 2:
12431 // op: sa
12432 return 11;
12433 }
12434 break;
12435 }
12436 case Mips::DLSA:
12437 case Mips::LSA: {
12438 switch (OpNum) {
12439 case 1:
12440 // op: rs
12441 return 21;
12442 case 2:
12443 // op: rt
12444 return 16;
12445 case 0:
12446 // op: rd
12447 return 11;
12448 case 3:
12449 // op: sa
12450 return 6;
12451 }
12452 break;
12453 }
12454 case Mips::CMPGDU_EQ_QB:
12455 case Mips::CMPGDU_LE_QB:
12456 case Mips::CMPGDU_LT_QB:
12457 case Mips::CMPGU_EQ_QB:
12458 case Mips::CMPGU_LE_QB:
12459 case Mips::CMPGU_LT_QB:
12460 case Mips::PACKRL_PH:
12461 case Mips::PICK_PH:
12462 case Mips::PICK_QB:
12463 case Mips::PRECRQU_S_QB_PH:
12464 case Mips::PRECRQ_PH_W:
12465 case Mips::PRECRQ_QB_PH:
12466 case Mips::PRECRQ_RS_PH_W:
12467 case Mips::PRECR_QB_PH: {
12468 switch (OpNum) {
12469 case 1:
12470 // op: rs
12471 return 21;
12472 case 2:
12473 // op: rt
12474 return 16;
12475 case 0:
12476 // op: rd
12477 return 11;
12478 }
12479 break;
12480 }
12481 case Mips::CRC32B:
12482 case Mips::CRC32CB:
12483 case Mips::CRC32CD:
12484 case Mips::CRC32CH:
12485 case Mips::CRC32CW:
12486 case Mips::CRC32D:
12487 case Mips::CRC32H:
12488 case Mips::CRC32W: {
12489 switch (OpNum) {
12490 case 1:
12491 // op: rs
12492 return 21;
12493 case 2:
12494 // op: rt
12495 return 16;
12496 }
12497 break;
12498 }
12499 case Mips::ADDU16_MMR6:
12500 case Mips::SUBU16_MMR6: {
12501 switch (OpNum) {
12502 case 1:
12503 // op: rs
12504 return 7;
12505 case 2:
12506 // op: rt
12507 return 4;
12508 case 0:
12509 // op: rd
12510 return 1;
12511 }
12512 break;
12513 }
12514 case Mips::CTC1:
12515 case Mips::DMTC1:
12516 case Mips::MTC1:
12517 case Mips::MTC1_D64: {
12518 switch (OpNum) {
12519 case 1:
12520 // op: rt
12521 return 16;
12522 case 0:
12523 // op: fs
12524 return 11;
12525 }
12526 break;
12527 }
12528 case Mips::DMTC0:
12529 case Mips::DMTC2:
12530 case Mips::DMTGC0:
12531 case Mips::MTC0:
12532 case Mips::MTC2:
12533 case Mips::MTGC0:
12534 case Mips::MTHGC0: {
12535 switch (OpNum) {
12536 case 1:
12537 // op: rt
12538 return 16;
12539 case 0:
12540 // op: rd
12541 return 11;
12542 case 2:
12543 // op: sel
12544 return 0;
12545 }
12546 break;
12547 }
12548 case Mips::MFTR:
12549 case Mips::MTTR: {
12550 switch (OpNum) {
12551 case 1:
12552 // op: rt
12553 return 16;
12554 case 0:
12555 // op: rd
12556 return 11;
12557 case 2:
12558 // op: u
12559 return 5;
12560 case 4:
12561 // op: h
12562 return 4;
12563 case 3:
12564 // op: sel
12565 return 0;
12566 }
12567 break;
12568 }
12569 case Mips::SC:
12570 case Mips::SC64:
12571 case Mips::SCD: {
12572 switch (OpNum) {
12573 case 1:
12574 // op: rt
12575 return 16;
12576 case 2:
12577 // op: addr
12578 return 0;
12579 }
12580 break;
12581 }
12582 case Mips::SC64_R6:
12583 case Mips::SCD_R6:
12584 case Mips::SC_R6: {
12585 switch (OpNum) {
12586 case 1:
12587 // op: rt
12588 return 16;
12589 case 2:
12590 // op: addr
12591 return 7;
12592 }
12593 break;
12594 }
12595 case Mips::CTC1_MM:
12596 case Mips::MTC1_D64_MM:
12597 case Mips::MTC1_MM:
12598 case Mips::MTC1_MMR6: {
12599 switch (OpNum) {
12600 case 1:
12601 // op: rt
12602 return 21;
12603 case 0:
12604 // op: fs
12605 return 16;
12606 }
12607 break;
12608 }
12609 case Mips::CTC2_MM:
12610 case Mips::MTC2_MMR6:
12611 case Mips::MTHC2_MMR6: {
12612 switch (OpNum) {
12613 case 1:
12614 // op: rt
12615 return 21;
12616 case 0:
12617 // op: impl
12618 return 16;
12619 }
12620 break;
12621 }
12622 case Mips::BEQC_MMR6:
12623 case Mips::BGEC_MMR6:
12624 case Mips::BGEUC_MMR6:
12625 case Mips::BLTC_MMR6:
12626 case Mips::BLTUC_MMR6:
12627 case Mips::BNEC_MMR6: {
12628 switch (OpNum) {
12629 case 1:
12630 // op: rt
12631 return 21;
12632 case 0:
12633 // op: rs
12634 return 16;
12635 case 2:
12636 // op: offset
12637 return 0;
12638 }
12639 break;
12640 }
12641 case Mips::MTC0_MMR6:
12642 case Mips::MTGC0_MM:
12643 case Mips::MTHC0_MMR6:
12644 case Mips::MTHGC0_MM: {
12645 switch (OpNum) {
12646 case 1:
12647 // op: rt
12648 return 21;
12649 case 0:
12650 // op: rs
12651 return 16;
12652 case 2:
12653 // op: sel
12654 return 11;
12655 }
12656 break;
12657 }
12658 case Mips::CMPU_EQ_QB_MM:
12659 case Mips::CMPU_LE_QB_MM:
12660 case Mips::CMPU_LT_QB_MM:
12661 case Mips::CMP_EQ_PH_MM:
12662 case Mips::CMP_LE_PH_MM:
12663 case Mips::CMP_LT_PH_MM: {
12664 switch (OpNum) {
12665 case 1:
12666 // op: rt
12667 return 21;
12668 case 0:
12669 // op: rs
12670 return 16;
12671 }
12672 break;
12673 }
12674 case Mips::SCE_MM:
12675 case Mips::SC_MM:
12676 case Mips::SC_MMR6: {
12677 switch (OpNum) {
12678 case 1:
12679 // op: rt
12680 return 21;
12681 case 2:
12682 // op: addr
12683 return 0;
12684 }
12685 break;
12686 }
12687 case Mips::AdduRxRyRz16:
12688 case Mips::SubuRxRyRz16: {
12689 switch (OpNum) {
12690 case 1:
12691 // op: rx
12692 return 8;
12693 case 2:
12694 // op: ry
12695 return 5;
12696 case 0:
12697 // op: rz
12698 return 2;
12699 }
12700 break;
12701 }
12702 case Mips::AndRxRxRy16:
12703 case Mips::OrRxRxRy16:
12704 case Mips::SllvRxRy16:
12705 case Mips::SravRxRy16:
12706 case Mips::SrlvRxRy16:
12707 case Mips::XorRxRxRy16: {
12708 switch (OpNum) {
12709 case 1:
12710 // op: rx
12711 return 8;
12712 case 2:
12713 // op: ry
12714 return 5;
12715 }
12716 break;
12717 }
12718 case Mips::LDI_B:
12719 case Mips::LDI_D:
12720 case Mips::LDI_H:
12721 case Mips::LDI_W: {
12722 switch (OpNum) {
12723 case 1:
12724 // op: s10
12725 return 11;
12726 case 0:
12727 // op: wd
12728 return 6;
12729 }
12730 break;
12731 }
12732 case Mips::SHILO_MM: {
12733 switch (OpNum) {
12734 case 1:
12735 // op: shift
12736 return 16;
12737 case 0:
12738 // op: ac
12739 return 14;
12740 }
12741 break;
12742 }
12743 case Mips::BCLRI_B:
12744 case Mips::BCLRI_D:
12745 case Mips::BCLRI_H:
12746 case Mips::BCLRI_W:
12747 case Mips::BNEGI_B:
12748 case Mips::BNEGI_D:
12749 case Mips::BNEGI_H:
12750 case Mips::BNEGI_W:
12751 case Mips::BSETI_B:
12752 case Mips::BSETI_D:
12753 case Mips::BSETI_H:
12754 case Mips::BSETI_W:
12755 case Mips::SAT_S_B:
12756 case Mips::SAT_S_D:
12757 case Mips::SAT_S_H:
12758 case Mips::SAT_S_W:
12759 case Mips::SAT_U_B:
12760 case Mips::SAT_U_D:
12761 case Mips::SAT_U_H:
12762 case Mips::SAT_U_W:
12763 case Mips::SLLI_B:
12764 case Mips::SLLI_D:
12765 case Mips::SLLI_H:
12766 case Mips::SLLI_W:
12767 case Mips::SRAI_B:
12768 case Mips::SRAI_D:
12769 case Mips::SRAI_H:
12770 case Mips::SRAI_W:
12771 case Mips::SRARI_B:
12772 case Mips::SRARI_D:
12773 case Mips::SRARI_H:
12774 case Mips::SRARI_W:
12775 case Mips::SRLI_B:
12776 case Mips::SRLI_D:
12777 case Mips::SRLI_H:
12778 case Mips::SRLI_W:
12779 case Mips::SRLRI_B:
12780 case Mips::SRLRI_D:
12781 case Mips::SRLRI_H:
12782 case Mips::SRLRI_W: {
12783 switch (OpNum) {
12784 case 1:
12785 // op: ws
12786 return 11;
12787 case 0:
12788 // op: wd
12789 return 6;
12790 case 2:
12791 // op: m
12792 return 16;
12793 }
12794 break;
12795 }
12796 case Mips::FCLASS_D:
12797 case Mips::FCLASS_W:
12798 case Mips::FEXUPL_D:
12799 case Mips::FEXUPL_W:
12800 case Mips::FEXUPR_D:
12801 case Mips::FEXUPR_W:
12802 case Mips::FFINT_S_D:
12803 case Mips::FFINT_S_W:
12804 case Mips::FFINT_U_D:
12805 case Mips::FFINT_U_W:
12806 case Mips::FFQL_D:
12807 case Mips::FFQL_W:
12808 case Mips::FFQR_D:
12809 case Mips::FFQR_W:
12810 case Mips::FLOG2_D:
12811 case Mips::FLOG2_W:
12812 case Mips::FRCP_D:
12813 case Mips::FRCP_W:
12814 case Mips::FRINT_D:
12815 case Mips::FRINT_W:
12816 case Mips::FRSQRT_D:
12817 case Mips::FRSQRT_W:
12818 case Mips::FSQRT_D:
12819 case Mips::FSQRT_W:
12820 case Mips::FTINT_S_D:
12821 case Mips::FTINT_S_W:
12822 case Mips::FTINT_U_D:
12823 case Mips::FTINT_U_W:
12824 case Mips::FTRUNC_S_D:
12825 case Mips::FTRUNC_S_W:
12826 case Mips::FTRUNC_U_D:
12827 case Mips::FTRUNC_U_W:
12828 case Mips::MOVE_V:
12829 case Mips::NLOC_B:
12830 case Mips::NLOC_D:
12831 case Mips::NLOC_H:
12832 case Mips::NLOC_W:
12833 case Mips::NLZC_B:
12834 case Mips::NLZC_D:
12835 case Mips::NLZC_H:
12836 case Mips::NLZC_W:
12837 case Mips::PCNT_B:
12838 case Mips::PCNT_D:
12839 case Mips::PCNT_H:
12840 case Mips::PCNT_W: {
12841 switch (OpNum) {
12842 case 1:
12843 // op: ws
12844 return 11;
12845 case 0:
12846 // op: wd
12847 return 6;
12848 }
12849 break;
12850 }
12851 case Mips::SCE: {
12852 switch (OpNum) {
12853 case 2:
12854 // op: addr
12855 return 7;
12856 case 1:
12857 // op: rt
12858 return 16;
12859 }
12860 break;
12861 }
12862 case Mips::MAXA_D:
12863 case Mips::MAXA_S:
12864 case Mips::MAX_D:
12865 case Mips::MAX_S:
12866 case Mips::MINA_D:
12867 case Mips::MINA_S:
12868 case Mips::MIN_D:
12869 case Mips::MIN_S:
12870 case Mips::SELEQZ_D:
12871 case Mips::SELEQZ_S:
12872 case Mips::SELNEZ_D:
12873 case Mips::SELNEZ_S: {
12874 switch (OpNum) {
12875 case 2:
12876 // op: ft
12877 return 16;
12878 case 1:
12879 // op: fs
12880 return 11;
12881 case 0:
12882 // op: fd
12883 return 6;
12884 }
12885 break;
12886 }
12887 case Mips::CMP_AF_D_MMR6:
12888 case Mips::CMP_AF_S_MMR6:
12889 case Mips::CMP_EQ_D_MMR6:
12890 case Mips::CMP_EQ_S_MMR6:
12891 case Mips::CMP_LE_D_MMR6:
12892 case Mips::CMP_LE_S_MMR6:
12893 case Mips::CMP_LT_D_MMR6:
12894 case Mips::CMP_LT_S_MMR6:
12895 case Mips::CMP_SAF_D_MMR6:
12896 case Mips::CMP_SAF_S_MMR6:
12897 case Mips::CMP_SEQ_D_MMR6:
12898 case Mips::CMP_SEQ_S_MMR6:
12899 case Mips::CMP_SLE_D_MMR6:
12900 case Mips::CMP_SLE_S_MMR6:
12901 case Mips::CMP_SLT_D_MMR6:
12902 case Mips::CMP_SLT_S_MMR6:
12903 case Mips::CMP_SUEQ_D_MMR6:
12904 case Mips::CMP_SUEQ_S_MMR6:
12905 case Mips::CMP_SULE_D_MMR6:
12906 case Mips::CMP_SULE_S_MMR6:
12907 case Mips::CMP_SULT_D_MMR6:
12908 case Mips::CMP_SULT_S_MMR6:
12909 case Mips::CMP_SUN_D_MMR6:
12910 case Mips::CMP_SUN_S_MMR6:
12911 case Mips::CMP_UEQ_D_MMR6:
12912 case Mips::CMP_UEQ_S_MMR6:
12913 case Mips::CMP_ULE_D_MMR6:
12914 case Mips::CMP_ULE_S_MMR6:
12915 case Mips::CMP_ULT_D_MMR6:
12916 case Mips::CMP_ULT_S_MMR6:
12917 case Mips::CMP_UN_D_MMR6:
12918 case Mips::CMP_UN_S_MMR6:
12919 case Mips::FADD_D32_MM:
12920 case Mips::FADD_D64_MM:
12921 case Mips::FADD_S_MM:
12922 case Mips::FDIV_D32_MM:
12923 case Mips::FDIV_D64_MM:
12924 case Mips::FDIV_S_MM:
12925 case Mips::FMUL_D32_MM:
12926 case Mips::FMUL_D64_MM:
12927 case Mips::FMUL_S_MM:
12928 case Mips::FSUB_D32_MM:
12929 case Mips::FSUB_D64_MM:
12930 case Mips::FSUB_S_MM:
12931 case Mips::MAXA_D_MMR6:
12932 case Mips::MAXA_S_MMR6:
12933 case Mips::MAX_D_MMR6:
12934 case Mips::MAX_S_MMR6:
12935 case Mips::MINA_D_MMR6:
12936 case Mips::MINA_S_MMR6:
12937 case Mips::MIN_D_MMR6:
12938 case Mips::MIN_S_MMR6:
12939 case Mips::SELEQZ_D_MMR6:
12940 case Mips::SELEQZ_S_MMR6:
12941 case Mips::SELNEZ_D_MMR6:
12942 case Mips::SELNEZ_S_MMR6: {
12943 switch (OpNum) {
12944 case 2:
12945 // op: ft
12946 return 21;
12947 case 1:
12948 // op: fs
12949 return 16;
12950 case 0:
12951 // op: fd
12952 return 11;
12953 }
12954 break;
12955 }
12956 case Mips::ADDVI_B:
12957 case Mips::ADDVI_D:
12958 case Mips::ADDVI_H:
12959 case Mips::ADDVI_W:
12960 case Mips::CEQI_B:
12961 case Mips::CEQI_D:
12962 case Mips::CEQI_H:
12963 case Mips::CEQI_W:
12964 case Mips::CLEI_S_B:
12965 case Mips::CLEI_S_D:
12966 case Mips::CLEI_S_H:
12967 case Mips::CLEI_S_W:
12968 case Mips::CLEI_U_B:
12969 case Mips::CLEI_U_D:
12970 case Mips::CLEI_U_H:
12971 case Mips::CLEI_U_W:
12972 case Mips::CLTI_S_B:
12973 case Mips::CLTI_S_D:
12974 case Mips::CLTI_S_H:
12975 case Mips::CLTI_S_W:
12976 case Mips::CLTI_U_B:
12977 case Mips::CLTI_U_D:
12978 case Mips::CLTI_U_H:
12979 case Mips::CLTI_U_W:
12980 case Mips::MAXI_S_B:
12981 case Mips::MAXI_S_D:
12982 case Mips::MAXI_S_H:
12983 case Mips::MAXI_S_W:
12984 case Mips::MAXI_U_B:
12985 case Mips::MAXI_U_D:
12986 case Mips::MAXI_U_H:
12987 case Mips::MAXI_U_W:
12988 case Mips::MINI_S_B:
12989 case Mips::MINI_S_D:
12990 case Mips::MINI_S_H:
12991 case Mips::MINI_S_W:
12992 case Mips::MINI_U_B:
12993 case Mips::MINI_U_D:
12994 case Mips::MINI_U_H:
12995 case Mips::MINI_U_W:
12996 case Mips::SUBVI_B:
12997 case Mips::SUBVI_D:
12998 case Mips::SUBVI_H:
12999 case Mips::SUBVI_W: {
13000 switch (OpNum) {
13001 case 2:
13002 // op: imm
13003 return 16;
13004 case 1:
13005 // op: ws
13006 return 11;
13007 case 0:
13008 // op: wd
13009 return 6;
13010 }
13011 break;
13012 }
13013 case Mips::AddiuRxRyOffMemX16: {
13014 switch (OpNum) {
13015 case 2:
13016 // op: imm15
13017 return 0;
13018 case 1:
13019 // op: rx
13020 return 8;
13021 case 0:
13022 // op: ry
13023 return 5;
13024 }
13025 break;
13026 }
13027 case Mips::AddiuRxRxImmX16: {
13028 switch (OpNum) {
13029 case 2:
13030 // op: imm16
13031 return 0;
13032 case 0:
13033 // op: rx
13034 return 8;
13035 }
13036 break;
13037 }
13038 case Mips::LbRxRyOffMemX16:
13039 case Mips::LbuRxRyOffMemX16:
13040 case Mips::LhRxRyOffMemX16:
13041 case Mips::LhuRxRyOffMemX16:
13042 case Mips::LwRxRyOffMemX16:
13043 case Mips::LwRxSpImmX16:
13044 case Mips::SbRxRyOffMemX16:
13045 case Mips::ShRxRyOffMemX16:
13046 case Mips::SwRxRyOffMemX16:
13047 case Mips::SwRxSpImmX16: {
13048 switch (OpNum) {
13049 case 2:
13050 // op: imm16
13051 return 0;
13052 case 1:
13053 // op: rx
13054 return 8;
13055 case 0:
13056 // op: ry
13057 return 5;
13058 }
13059 break;
13060 }
13061 case Mips::LBUX_MM:
13062 case Mips::LHX_MM:
13063 case Mips::LWX_MM: {
13064 switch (OpNum) {
13065 case 2:
13066 // op: index
13067 return 21;
13068 case 1:
13069 // op: base
13070 return 16;
13071 case 0:
13072 // op: rd
13073 return 11;
13074 }
13075 break;
13076 }
13077 case Mips::COPY_S_B:
13078 case Mips::COPY_S_D:
13079 case Mips::COPY_S_H:
13080 case Mips::COPY_S_W:
13081 case Mips::COPY_U_B:
13082 case Mips::COPY_U_H:
13083 case Mips::COPY_U_W: {
13084 switch (OpNum) {
13085 case 2:
13086 // op: n
13087 return 16;
13088 case 1:
13089 // op: ws
13090 return 11;
13091 case 0:
13092 // op: rd
13093 return 6;
13094 }
13095 break;
13096 }
13097 case Mips::SPLATI_B:
13098 case Mips::SPLATI_D:
13099 case Mips::SPLATI_H:
13100 case Mips::SPLATI_W: {
13101 switch (OpNum) {
13102 case 2:
13103 // op: n
13104 return 16;
13105 case 1:
13106 // op: ws
13107 return 11;
13108 case 0:
13109 // op: wd
13110 return 6;
13111 }
13112 break;
13113 }
13114 case Mips::INSVE_B:
13115 case Mips::INSVE_D:
13116 case Mips::INSVE_H:
13117 case Mips::INSVE_W: {
13118 switch (OpNum) {
13119 case 2:
13120 // op: n
13121 return 16;
13122 case 3:
13123 // op: ws
13124 return 11;
13125 case 0:
13126 // op: wd
13127 return 6;
13128 }
13129 break;
13130 }
13131 case Mips::MTHC1_D32:
13132 case Mips::MTHC1_D64: {
13133 switch (OpNum) {
13134 case 2:
13135 // op: rt
13136 return 16;
13137 case 0:
13138 // op: fs
13139 return 11;
13140 }
13141 break;
13142 }
13143 case Mips::SPLAT_B:
13144 case Mips::SPLAT_D:
13145 case Mips::SPLAT_H:
13146 case Mips::SPLAT_W: {
13147 switch (OpNum) {
13148 case 2:
13149 // op: rt
13150 return 16;
13151 case 1:
13152 // op: ws
13153 return 11;
13154 case 0:
13155 // op: wd
13156 return 6;
13157 }
13158 break;
13159 }
13160 case Mips::MTHC1_D32_MM:
13161 case Mips::MTHC1_D64_MM: {
13162 switch (OpNum) {
13163 case 2:
13164 // op: rt
13165 return 21;
13166 case 0:
13167 // op: fs
13168 return 16;
13169 }
13170 break;
13171 }
13172 case Mips::DPAQX_SA_W_PH_MMR2:
13173 case Mips::DPAQX_S_W_PH_MMR2:
13174 case Mips::DPAQ_SA_L_W_MM:
13175 case Mips::DPAQ_S_W_PH_MM:
13176 case Mips::DPAU_H_QBL_MM:
13177 case Mips::DPAU_H_QBR_MM:
13178 case Mips::DPAX_W_PH_MMR2:
13179 case Mips::DPA_W_PH_MMR2:
13180 case Mips::DPSQX_SA_W_PH_MMR2:
13181 case Mips::DPSQX_S_W_PH_MMR2:
13182 case Mips::DPSQ_SA_L_W_MM:
13183 case Mips::DPSQ_S_W_PH_MM:
13184 case Mips::DPSU_H_QBL_MM:
13185 case Mips::DPSU_H_QBR_MM:
13186 case Mips::DPSX_W_PH_MMR2:
13187 case Mips::DPS_W_PH_MMR2:
13188 case Mips::MADDU_DSP_MM:
13189 case Mips::MADD_DSP_MM:
13190 case Mips::MAQ_SA_W_PHL_MM:
13191 case Mips::MAQ_SA_W_PHR_MM:
13192 case Mips::MAQ_S_W_PHL_MM:
13193 case Mips::MAQ_S_W_PHR_MM:
13194 case Mips::MSUBU_DSP_MM:
13195 case Mips::MSUB_DSP_MM:
13196 case Mips::MULSAQ_S_W_PH_MM:
13197 case Mips::MULSA_W_PH_MMR2:
13198 case Mips::MULTU_DSP_MM:
13199 case Mips::MULT_DSP_MM: {
13200 switch (OpNum) {
13201 case 2:
13202 // op: rt
13203 return 21;
13204 case 1:
13205 // op: rs
13206 return 16;
13207 case 0:
13208 // op: ac
13209 return 14;
13210 }
13211 break;
13212 }
13213 case Mips::ADD_MM:
13214 case Mips::ADDu_MM:
13215 case Mips::AND_MM:
13216 case Mips::CMPGU_EQ_QB_MM:
13217 case Mips::CMPGU_LE_QB_MM:
13218 case Mips::CMPGU_LT_QB_MM:
13219 case Mips::MOVN_I_MM:
13220 case Mips::MOVZ_I_MM:
13221 case Mips::MUL_MM:
13222 case Mips::NOR_MM:
13223 case Mips::OR_MM:
13224 case Mips::SLT_MM:
13225 case Mips::SLTu_MM:
13226 case Mips::SUB_MM:
13227 case Mips::SUBu_MM:
13228 case Mips::XOR_MM: {
13229 switch (OpNum) {
13230 case 2:
13231 // op: rt
13232 return 21;
13233 case 1:
13234 // op: rs
13235 return 16;
13236 case 0:
13237 // op: rd
13238 return 11;
13239 }
13240 break;
13241 }
13242 case Mips::AND16_MM:
13243 case Mips::OR16_MM:
13244 case Mips::XOR16_MM: {
13245 switch (OpNum) {
13246 case 2:
13247 // op: rt
13248 return 3;
13249 case 1:
13250 // op: rs
13251 return 0;
13252 }
13253 break;
13254 }
13255 case Mips::AND16_MMR6:
13256 case Mips::OR16_MMR6:
13257 case Mips::XOR16_MMR6: {
13258 switch (OpNum) {
13259 case 2:
13260 // op: rt
13261 return 7;
13262 case 1:
13263 // op: rs
13264 return 4;
13265 }
13266 break;
13267 }
13268 case Mips::SllX16:
13269 case Mips::SraX16:
13270 case Mips::SrlX16: {
13271 switch (OpNum) {
13272 case 2:
13273 // op: sa6
13274 return 21;
13275 case 0:
13276 // op: rx
13277 return 8;
13278 case 1:
13279 // op: ry
13280 return 5;
13281 }
13282 break;
13283 }
13284 case Mips::ANDI_B:
13285 case Mips::NORI_B:
13286 case Mips::ORI_B:
13287 case Mips::SHF_B:
13288 case Mips::SHF_H:
13289 case Mips::SHF_W:
13290 case Mips::XORI_B: {
13291 switch (OpNum) {
13292 case 2:
13293 // op: u8
13294 return 16;
13295 case 1:
13296 // op: ws
13297 return 11;
13298 case 0:
13299 // op: wd
13300 return 6;
13301 }
13302 break;
13303 }
13304 case Mips::BINSLI_B:
13305 case Mips::BINSLI_D:
13306 case Mips::BINSLI_H:
13307 case Mips::BINSLI_W:
13308 case Mips::BINSRI_B:
13309 case Mips::BINSRI_D:
13310 case Mips::BINSRI_H:
13311 case Mips::BINSRI_W: {
13312 switch (OpNum) {
13313 case 2:
13314 // op: ws
13315 return 11;
13316 case 0:
13317 // op: wd
13318 return 6;
13319 case 3:
13320 // op: m
13321 return 16;
13322 }
13323 break;
13324 }
13325 case Mips::ADDS_A_B:
13326 case Mips::ADDS_A_D:
13327 case Mips::ADDS_A_H:
13328 case Mips::ADDS_A_W:
13329 case Mips::ADDS_S_B:
13330 case Mips::ADDS_S_D:
13331 case Mips::ADDS_S_H:
13332 case Mips::ADDS_S_W:
13333 case Mips::ADDS_U_B:
13334 case Mips::ADDS_U_D:
13335 case Mips::ADDS_U_H:
13336 case Mips::ADDS_U_W:
13337 case Mips::ADDV_B:
13338 case Mips::ADDV_D:
13339 case Mips::ADDV_H:
13340 case Mips::ADDV_W:
13341 case Mips::ADD_A_B:
13342 case Mips::ADD_A_D:
13343 case Mips::ADD_A_H:
13344 case Mips::ADD_A_W:
13345 case Mips::AND_V:
13346 case Mips::ASUB_S_B:
13347 case Mips::ASUB_S_D:
13348 case Mips::ASUB_S_H:
13349 case Mips::ASUB_S_W:
13350 case Mips::ASUB_U_B:
13351 case Mips::ASUB_U_D:
13352 case Mips::ASUB_U_H:
13353 case Mips::ASUB_U_W:
13354 case Mips::AVER_S_B:
13355 case Mips::AVER_S_D:
13356 case Mips::AVER_S_H:
13357 case Mips::AVER_S_W:
13358 case Mips::AVER_U_B:
13359 case Mips::AVER_U_D:
13360 case Mips::AVER_U_H:
13361 case Mips::AVER_U_W:
13362 case Mips::AVE_S_B:
13363 case Mips::AVE_S_D:
13364 case Mips::AVE_S_H:
13365 case Mips::AVE_S_W:
13366 case Mips::AVE_U_B:
13367 case Mips::AVE_U_D:
13368 case Mips::AVE_U_H:
13369 case Mips::AVE_U_W:
13370 case Mips::BCLR_B:
13371 case Mips::BCLR_D:
13372 case Mips::BCLR_H:
13373 case Mips::BCLR_W:
13374 case Mips::BNEG_B:
13375 case Mips::BNEG_D:
13376 case Mips::BNEG_H:
13377 case Mips::BNEG_W:
13378 case Mips::BSET_B:
13379 case Mips::BSET_D:
13380 case Mips::BSET_H:
13381 case Mips::BSET_W:
13382 case Mips::CEQ_B:
13383 case Mips::CEQ_D:
13384 case Mips::CEQ_H:
13385 case Mips::CEQ_W:
13386 case Mips::CLE_S_B:
13387 case Mips::CLE_S_D:
13388 case Mips::CLE_S_H:
13389 case Mips::CLE_S_W:
13390 case Mips::CLE_U_B:
13391 case Mips::CLE_U_D:
13392 case Mips::CLE_U_H:
13393 case Mips::CLE_U_W:
13394 case Mips::CLT_S_B:
13395 case Mips::CLT_S_D:
13396 case Mips::CLT_S_H:
13397 case Mips::CLT_S_W:
13398 case Mips::CLT_U_B:
13399 case Mips::CLT_U_D:
13400 case Mips::CLT_U_H:
13401 case Mips::CLT_U_W:
13402 case Mips::DIV_S_B:
13403 case Mips::DIV_S_D:
13404 case Mips::DIV_S_H:
13405 case Mips::DIV_S_W:
13406 case Mips::DIV_U_B:
13407 case Mips::DIV_U_D:
13408 case Mips::DIV_U_H:
13409 case Mips::DIV_U_W:
13410 case Mips::DOTP_S_D:
13411 case Mips::DOTP_S_H:
13412 case Mips::DOTP_S_W:
13413 case Mips::DOTP_U_D:
13414 case Mips::DOTP_U_H:
13415 case Mips::DOTP_U_W:
13416 case Mips::FADD_D:
13417 case Mips::FADD_W:
13418 case Mips::FCAF_D:
13419 case Mips::FCAF_W:
13420 case Mips::FCEQ_D:
13421 case Mips::FCEQ_W:
13422 case Mips::FCLE_D:
13423 case Mips::FCLE_W:
13424 case Mips::FCLT_D:
13425 case Mips::FCLT_W:
13426 case Mips::FCNE_D:
13427 case Mips::FCNE_W:
13428 case Mips::FCOR_D:
13429 case Mips::FCOR_W:
13430 case Mips::FCUEQ_D:
13431 case Mips::FCUEQ_W:
13432 case Mips::FCULE_D:
13433 case Mips::FCULE_W:
13434 case Mips::FCULT_D:
13435 case Mips::FCULT_W:
13436 case Mips::FCUNE_D:
13437 case Mips::FCUNE_W:
13438 case Mips::FCUN_D:
13439 case Mips::FCUN_W:
13440 case Mips::FDIV_D:
13441 case Mips::FDIV_W:
13442 case Mips::FEXDO_H:
13443 case Mips::FEXDO_W:
13444 case Mips::FEXP2_D:
13445 case Mips::FEXP2_W:
13446 case Mips::FMAX_A_D:
13447 case Mips::FMAX_A_W:
13448 case Mips::FMAX_D:
13449 case Mips::FMAX_W:
13450 case Mips::FMIN_A_D:
13451 case Mips::FMIN_A_W:
13452 case Mips::FMIN_D:
13453 case Mips::FMIN_W:
13454 case Mips::FMUL_D:
13455 case Mips::FMUL_W:
13456 case Mips::FSAF_D:
13457 case Mips::FSAF_W:
13458 case Mips::FSEQ_D:
13459 case Mips::FSEQ_W:
13460 case Mips::FSLE_D:
13461 case Mips::FSLE_W:
13462 case Mips::FSLT_D:
13463 case Mips::FSLT_W:
13464 case Mips::FSNE_D:
13465 case Mips::FSNE_W:
13466 case Mips::FSOR_D:
13467 case Mips::FSOR_W:
13468 case Mips::FSUB_D:
13469 case Mips::FSUB_W:
13470 case Mips::FSUEQ_D:
13471 case Mips::FSUEQ_W:
13472 case Mips::FSULE_D:
13473 case Mips::FSULE_W:
13474 case Mips::FSULT_D:
13475 case Mips::FSULT_W:
13476 case Mips::FSUNE_D:
13477 case Mips::FSUNE_W:
13478 case Mips::FSUN_D:
13479 case Mips::FSUN_W:
13480 case Mips::FTQ_H:
13481 case Mips::FTQ_W:
13482 case Mips::HADD_S_D:
13483 case Mips::HADD_S_H:
13484 case Mips::HADD_S_W:
13485 case Mips::HADD_U_D:
13486 case Mips::HADD_U_H:
13487 case Mips::HADD_U_W:
13488 case Mips::HSUB_S_D:
13489 case Mips::HSUB_S_H:
13490 case Mips::HSUB_S_W:
13491 case Mips::HSUB_U_D:
13492 case Mips::HSUB_U_H:
13493 case Mips::HSUB_U_W:
13494 case Mips::ILVEV_B:
13495 case Mips::ILVEV_D:
13496 case Mips::ILVEV_H:
13497 case Mips::ILVEV_W:
13498 case Mips::ILVL_B:
13499 case Mips::ILVL_D:
13500 case Mips::ILVL_H:
13501 case Mips::ILVL_W:
13502 case Mips::ILVOD_B:
13503 case Mips::ILVOD_D:
13504 case Mips::ILVOD_H:
13505 case Mips::ILVOD_W:
13506 case Mips::ILVR_B:
13507 case Mips::ILVR_D:
13508 case Mips::ILVR_H:
13509 case Mips::ILVR_W:
13510 case Mips::MAX_A_B:
13511 case Mips::MAX_A_D:
13512 case Mips::MAX_A_H:
13513 case Mips::MAX_A_W:
13514 case Mips::MAX_S_B:
13515 case Mips::MAX_S_D:
13516 case Mips::MAX_S_H:
13517 case Mips::MAX_S_W:
13518 case Mips::MAX_U_B:
13519 case Mips::MAX_U_D:
13520 case Mips::MAX_U_H:
13521 case Mips::MAX_U_W:
13522 case Mips::MIN_A_B:
13523 case Mips::MIN_A_D:
13524 case Mips::MIN_A_H:
13525 case Mips::MIN_A_W:
13526 case Mips::MIN_S_B:
13527 case Mips::MIN_S_D:
13528 case Mips::MIN_S_H:
13529 case Mips::MIN_S_W:
13530 case Mips::MIN_U_B:
13531 case Mips::MIN_U_D:
13532 case Mips::MIN_U_H:
13533 case Mips::MIN_U_W:
13534 case Mips::MOD_S_B:
13535 case Mips::MOD_S_D:
13536 case Mips::MOD_S_H:
13537 case Mips::MOD_S_W:
13538 case Mips::MOD_U_B:
13539 case Mips::MOD_U_D:
13540 case Mips::MOD_U_H:
13541 case Mips::MOD_U_W:
13542 case Mips::MULR_Q_H:
13543 case Mips::MULR_Q_W:
13544 case Mips::MULV_B:
13545 case Mips::MULV_D:
13546 case Mips::MULV_H:
13547 case Mips::MULV_W:
13548 case Mips::MUL_Q_H:
13549 case Mips::MUL_Q_W:
13550 case Mips::NOR_V:
13551 case Mips::OR_V:
13552 case Mips::PCKEV_B:
13553 case Mips::PCKEV_D:
13554 case Mips::PCKEV_H:
13555 case Mips::PCKEV_W:
13556 case Mips::PCKOD_B:
13557 case Mips::PCKOD_D:
13558 case Mips::PCKOD_H:
13559 case Mips::PCKOD_W:
13560 case Mips::SLL_B:
13561 case Mips::SLL_D:
13562 case Mips::SLL_H:
13563 case Mips::SLL_W:
13564 case Mips::SRAR_B:
13565 case Mips::SRAR_D:
13566 case Mips::SRAR_H:
13567 case Mips::SRAR_W:
13568 case Mips::SRA_B:
13569 case Mips::SRA_D:
13570 case Mips::SRA_H:
13571 case Mips::SRA_W:
13572 case Mips::SRLR_B:
13573 case Mips::SRLR_D:
13574 case Mips::SRLR_H:
13575 case Mips::SRLR_W:
13576 case Mips::SRL_B:
13577 case Mips::SRL_D:
13578 case Mips::SRL_H:
13579 case Mips::SRL_W:
13580 case Mips::SUBSUS_U_B:
13581 case Mips::SUBSUS_U_D:
13582 case Mips::SUBSUS_U_H:
13583 case Mips::SUBSUS_U_W:
13584 case Mips::SUBSUU_S_B:
13585 case Mips::SUBSUU_S_D:
13586 case Mips::SUBSUU_S_H:
13587 case Mips::SUBSUU_S_W:
13588 case Mips::SUBS_S_B:
13589 case Mips::SUBS_S_D:
13590 case Mips::SUBS_S_H:
13591 case Mips::SUBS_S_W:
13592 case Mips::SUBS_U_B:
13593 case Mips::SUBS_U_D:
13594 case Mips::SUBS_U_H:
13595 case Mips::SUBS_U_W:
13596 case Mips::SUBV_B:
13597 case Mips::SUBV_D:
13598 case Mips::SUBV_H:
13599 case Mips::SUBV_W:
13600 case Mips::XOR_V: {
13601 switch (OpNum) {
13602 case 2:
13603 // op: wt
13604 return 16;
13605 case 1:
13606 // op: ws
13607 return 11;
13608 case 0:
13609 // op: wd
13610 return 6;
13611 }
13612 break;
13613 }
13614 case Mips::MADDF_D:
13615 case Mips::MADDF_S:
13616 case Mips::MSUBF_D:
13617 case Mips::MSUBF_S:
13618 case Mips::SEL_D:
13619 case Mips::SEL_S: {
13620 switch (OpNum) {
13621 case 3:
13622 // op: ft
13623 return 16;
13624 case 2:
13625 // op: fs
13626 return 11;
13627 case 0:
13628 // op: fd
13629 return 6;
13630 }
13631 break;
13632 }
13633 case Mips::MADD_D32_MM:
13634 case Mips::MADD_S_MM:
13635 case Mips::MSUB_D32_MM:
13636 case Mips::MSUB_S_MM:
13637 case Mips::NMADD_D32_MM:
13638 case Mips::NMADD_S_MM:
13639 case Mips::NMSUB_D32_MM:
13640 case Mips::NMSUB_S_MM: {
13641 switch (OpNum) {
13642 case 3:
13643 // op: ft
13644 return 21;
13645 case 2:
13646 // op: fs
13647 return 16;
13648 case 0:
13649 // op: fd
13650 return 11;
13651 case 1:
13652 // op: fr
13653 return 6;
13654 }
13655 break;
13656 }
13657 case Mips::MADDF_D_MMR6:
13658 case Mips::MADDF_S_MMR6:
13659 case Mips::MSUBF_D_MMR6:
13660 case Mips::MSUBF_S_MMR6:
13661 case Mips::SEL_D_MMR6:
13662 case Mips::SEL_S_MMR6: {
13663 switch (OpNum) {
13664 case 3:
13665 // op: ft
13666 return 21;
13667 case 2:
13668 // op: fs
13669 return 16;
13670 case 0:
13671 // op: fd
13672 return 11;
13673 }
13674 break;
13675 }
13676 case Mips::INSERT_B:
13677 case Mips::INSERT_D:
13678 case Mips::INSERT_H:
13679 case Mips::INSERT_W: {
13680 switch (OpNum) {
13681 case 3:
13682 // op: n
13683 return 16;
13684 case 2:
13685 // op: rs
13686 return 11;
13687 case 0:
13688 // op: wd
13689 return 6;
13690 }
13691 break;
13692 }
13693 case Mips::SLDI_B:
13694 case Mips::SLDI_D:
13695 case Mips::SLDI_H:
13696 case Mips::SLDI_W: {
13697 switch (OpNum) {
13698 case 3:
13699 // op: n
13700 return 16;
13701 case 2:
13702 // op: ws
13703 return 11;
13704 case 0:
13705 // op: wd
13706 return 6;
13707 }
13708 break;
13709 }
13710 case Mips::SLD_B:
13711 case Mips::SLD_D:
13712 case Mips::SLD_H:
13713 case Mips::SLD_W: {
13714 switch (OpNum) {
13715 case 3:
13716 // op: rt
13717 return 16;
13718 case 2:
13719 // op: ws
13720 return 11;
13721 case 0:
13722 // op: wd
13723 return 6;
13724 }
13725 break;
13726 }
13727 case Mips::MOVEP_MMR6: {
13728 switch (OpNum) {
13729 case 3:
13730 // op: rt
13731 return 4;
13732 case 2:
13733 // op: rs
13734 return 0;
13735 }
13736 break;
13737 }
13738 case Mips::MOVEP_MM: {
13739 switch (OpNum) {
13740 case 3:
13741 // op: rt
13742 return 4;
13743 case 2:
13744 // op: rs
13745 return 1;
13746 }
13747 break;
13748 }
13749 case Mips::BMNZI_B:
13750 case Mips::BMZI_B:
13751 case Mips::BSELI_B: {
13752 switch (OpNum) {
13753 case 3:
13754 // op: u8
13755 return 16;
13756 case 2:
13757 // op: ws
13758 return 11;
13759 case 0:
13760 // op: wd
13761 return 6;
13762 }
13763 break;
13764 }
13765 case Mips::BINSL_B:
13766 case Mips::BINSL_D:
13767 case Mips::BINSL_H:
13768 case Mips::BINSL_W:
13769 case Mips::BINSR_B:
13770 case Mips::BINSR_D:
13771 case Mips::BINSR_H:
13772 case Mips::BINSR_W:
13773 case Mips::BMNZ_V:
13774 case Mips::BMZ_V:
13775 case Mips::BSEL_V:
13776 case Mips::DPADD_S_D:
13777 case Mips::DPADD_S_H:
13778 case Mips::DPADD_S_W:
13779 case Mips::DPADD_U_D:
13780 case Mips::DPADD_U_H:
13781 case Mips::DPADD_U_W:
13782 case Mips::DPSUB_S_D:
13783 case Mips::DPSUB_S_H:
13784 case Mips::DPSUB_S_W:
13785 case Mips::DPSUB_U_D:
13786 case Mips::DPSUB_U_H:
13787 case Mips::DPSUB_U_W:
13788 case Mips::FMADD_D:
13789 case Mips::FMADD_W:
13790 case Mips::FMSUB_D:
13791 case Mips::FMSUB_W:
13792 case Mips::MADDR_Q_H:
13793 case Mips::MADDR_Q_W:
13794 case Mips::MADDV_B:
13795 case Mips::MADDV_D:
13796 case Mips::MADDV_H:
13797 case Mips::MADDV_W:
13798 case Mips::MADD_Q_H:
13799 case Mips::MADD_Q_W:
13800 case Mips::MSUBR_Q_H:
13801 case Mips::MSUBR_Q_W:
13802 case Mips::MSUBV_B:
13803 case Mips::MSUBV_D:
13804 case Mips::MSUBV_H:
13805 case Mips::MSUBV_W:
13806 case Mips::MSUB_Q_H:
13807 case Mips::MSUB_Q_W:
13808 case Mips::VSHF_B:
13809 case Mips::VSHF_D:
13810 case Mips::VSHF_H:
13811 case Mips::VSHF_W: {
13812 switch (OpNum) {
13813 case 3:
13814 // op: wt
13815 return 16;
13816 case 2:
13817 // op: ws
13818 return 11;
13819 case 0:
13820 // op: wd
13821 return 6;
13822 }
13823 break;
13824 }
13825 }
13826 std::string msg;
13827 raw_string_ostream Msg(msg);
13828 Msg << "Not supported instr[opcode]: " << MI << "[" << OpNum << "]";
13829 report_fatal_error(Msg.str().c_str());
13830}
13831
13832#endif // GET_OPERAND_BIT_OFFSET
13833
13834