1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register Enum Values *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_REGINFO_ENUM
11#undef GET_REGINFO_ENUM
12
13namespace llvm {
14
15class MCRegisterClass;
16extern const MCRegisterClass NVPTXMCRegisterClasses[];
17
18namespace NVPTX {
19enum : unsigned {
20 NoRegister,
21 VRDepot = 1,
22 ENVREG0 = 2,
23 ENVREG1 = 3,
24 ENVREG2 = 4,
25 ENVREG3 = 5,
26 ENVREG4 = 6,
27 ENVREG5 = 7,
28 ENVREG6 = 8,
29 ENVREG7 = 9,
30 ENVREG8 = 10,
31 ENVREG9 = 11,
32 ENVREG10 = 12,
33 ENVREG11 = 13,
34 ENVREG12 = 14,
35 ENVREG13 = 15,
36 ENVREG14 = 16,
37 ENVREG15 = 17,
38 ENVREG16 = 18,
39 ENVREG17 = 19,
40 ENVREG18 = 20,
41 ENVREG19 = 21,
42 ENVREG20 = 22,
43 ENVREG21 = 23,
44 ENVREG22 = 24,
45 ENVREG23 = 25,
46 ENVREG24 = 26,
47 ENVREG25 = 27,
48 ENVREG26 = 28,
49 ENVREG27 = 29,
50 ENVREG28 = 30,
51 ENVREG29 = 31,
52 ENVREG30 = 32,
53 ENVREG31 = 33,
54 H0 = 34,
55 H1 = 35,
56 H2 = 36,
57 H3 = 37,
58 H4 = 38,
59 HH0 = 39,
60 HH1 = 40,
61 HH2 = 41,
62 HH3 = 42,
63 HH4 = 43,
64 P0 = 44,
65 P1 = 45,
66 P2 = 46,
67 P3 = 47,
68 P4 = 48,
69 R0 = 49,
70 R1 = 50,
71 R2 = 51,
72 R3 = 52,
73 R4 = 53,
74 RL0 = 54,
75 RL1 = 55,
76 RL2 = 56,
77 RL3 = 57,
78 RL4 = 58,
79 RQ0 = 59,
80 RQ1 = 60,
81 RQ2 = 61,
82 RQ3 = 62,
83 RQ4 = 63,
84 RS0 = 64,
85 RS1 = 65,
86 RS2 = 66,
87 RS3 = 67,
88 RS4 = 68,
89 VRFrame32 = 69,
90 VRFrame64 = 70,
91 VRFrameLocal32 = 71,
92 VRFrameLocal64 = 72,
93 da0 = 73,
94 da1 = 74,
95 da2 = 75,
96 da3 = 76,
97 da4 = 77,
98 fa0 = 78,
99 fa1 = 79,
100 fa2 = 80,
101 fa3 = 81,
102 fa4 = 82,
103 ia0 = 83,
104 ia1 = 84,
105 ia2 = 85,
106 ia3 = 86,
107 ia4 = 87,
108 la0 = 88,
109 la1 = 89,
110 la2 = 90,
111 la3 = 91,
112 la4 = 92,
113 NUM_TARGET_REGS // 93
114};
115} // end namespace NVPTX
116
117// Register classes
118
119namespace NVPTX {
120enum {
121 B1RegClassID = 0,
122 B16RegClassID = 1,
123 SpecialRegsRegClassID = 2,
124 B32RegClassID = 3,
125 B32_and_SpecialRegsRegClassID = 4,
126 B64RegClassID = 5,
127 B128RegClassID = 6,
128
129};
130} // end namespace NVPTX
131
132// Register pressure sets enum.
133namespace NVPTX {
134enum RegisterPressureSets {
135 B32_and_SpecialRegs = 0,
136 B1 = 1,
137 B16 = 2,
138 B128 = 3,
139 B32 = 4,
140 B64 = 5,
141 SpecialRegs = 6,
142 SpecialRegs_with_B32 = 7,
143};
144} // end namespace NVPTX
145
146} // end namespace llvm
147
148#endif // GET_REGINFO_ENUM
149
150/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
151|* *|
152|* MC Register Information *|
153|* *|
154|* Automatically generated file, do not edit! *|
155|* *|
156\*===----------------------------------------------------------------------===*/
157
158
159#ifdef GET_REGINFO_MC_DESC
160#undef GET_REGINFO_MC_DESC
161
162namespace llvm {
163
164extern const int16_t NVPTXRegDiffLists[] = {
165 /* 0 */ 0,
166};
167
168extern const LaneBitmask NVPTXLaneMaskLists[] = {
169 /* 0 */ LaneBitmask(0xFFFFFFFFFFFFFFFF),
170};
171
172extern const uint16_t NVPTXSubRegIdxLists[] = {
173 /* 0 */
174 /* dummy */ 0
175};
176
177
178#ifdef __GNUC__
179#pragma GCC diagnostic push
180#pragma GCC diagnostic ignored "-Woverlength-strings"
181#endif
182extern const char NVPTXRegStrings[] = {
183 /* 0 */ "ENVREG10\000"
184 /* 9 */ "ENVREG20\000"
185 /* 18 */ "ENVREG30\000"
186 /* 27 */ "ENVREG0\000"
187 /* 35 */ "HH0\000"
188 /* 39 */ "RL0\000"
189 /* 43 */ "P0\000"
190 /* 46 */ "RQ0\000"
191 /* 50 */ "R0\000"
192 /* 53 */ "RS0\000"
193 /* 57 */ "da0\000"
194 /* 61 */ "fa0\000"
195 /* 65 */ "ia0\000"
196 /* 69 */ "la0\000"
197 /* 73 */ "ENVREG11\000"
198 /* 82 */ "ENVREG21\000"
199 /* 91 */ "ENVREG31\000"
200 /* 100 */ "ENVREG1\000"
201 /* 108 */ "HH1\000"
202 /* 112 */ "RL1\000"
203 /* 116 */ "P1\000"
204 /* 119 */ "RQ1\000"
205 /* 123 */ "R1\000"
206 /* 126 */ "RS1\000"
207 /* 130 */ "da1\000"
208 /* 134 */ "fa1\000"
209 /* 138 */ "ia1\000"
210 /* 142 */ "la1\000"
211 /* 146 */ "ENVREG12\000"
212 /* 155 */ "ENVREG22\000"
213 /* 164 */ "VRFrame32\000"
214 /* 174 */ "VRFrameLocal32\000"
215 /* 189 */ "ENVREG2\000"
216 /* 197 */ "HH2\000"
217 /* 201 */ "RL2\000"
218 /* 205 */ "P2\000"
219 /* 208 */ "RQ2\000"
220 /* 212 */ "R2\000"
221 /* 215 */ "RS2\000"
222 /* 219 */ "da2\000"
223 /* 223 */ "fa2\000"
224 /* 227 */ "ia2\000"
225 /* 231 */ "la2\000"
226 /* 235 */ "ENVREG13\000"
227 /* 244 */ "ENVREG23\000"
228 /* 253 */ "ENVREG3\000"
229 /* 261 */ "HH3\000"
230 /* 265 */ "RL3\000"
231 /* 269 */ "P3\000"
232 /* 272 */ "RQ3\000"
233 /* 276 */ "R3\000"
234 /* 279 */ "RS3\000"
235 /* 283 */ "da3\000"
236 /* 287 */ "fa3\000"
237 /* 291 */ "ia3\000"
238 /* 295 */ "la3\000"
239 /* 299 */ "ENVREG14\000"
240 /* 308 */ "ENVREG24\000"
241 /* 317 */ "VRFrame64\000"
242 /* 327 */ "VRFrameLocal64\000"
243 /* 342 */ "ENVREG4\000"
244 /* 350 */ "HH4\000"
245 /* 354 */ "RL4\000"
246 /* 358 */ "P4\000"
247 /* 361 */ "RQ4\000"
248 /* 365 */ "R4\000"
249 /* 368 */ "RS4\000"
250 /* 372 */ "da4\000"
251 /* 376 */ "fa4\000"
252 /* 380 */ "ia4\000"
253 /* 384 */ "la4\000"
254 /* 388 */ "ENVREG15\000"
255 /* 397 */ "ENVREG25\000"
256 /* 406 */ "ENVREG5\000"
257 /* 414 */ "ENVREG16\000"
258 /* 423 */ "ENVREG26\000"
259 /* 432 */ "ENVREG6\000"
260 /* 440 */ "ENVREG17\000"
261 /* 449 */ "ENVREG27\000"
262 /* 458 */ "ENVREG7\000"
263 /* 466 */ "ENVREG18\000"
264 /* 475 */ "ENVREG28\000"
265 /* 484 */ "ENVREG8\000"
266 /* 492 */ "ENVREG19\000"
267 /* 501 */ "ENVREG29\000"
268 /* 510 */ "ENVREG9\000"
269 /* 518 */ "VRDepot\000"
270};
271#ifdef __GNUC__
272#pragma GCC diagnostic pop
273#endif
274
275extern const MCRegisterDesc NVPTXRegDesc[] = { // Descriptors
276 { 8, 0, 0, 0, 0, 0, 0, 0 },
277 { 518, 0, 0, 0, 0, 0, 0, 0 },
278 { 27, 0, 0, 0, 1, 0, 0, 0 },
279 { 100, 0, 0, 0, 2, 0, 0, 0 },
280 { 189, 0, 0, 0, 3, 0, 0, 0 },
281 { 253, 0, 0, 0, 4, 0, 0, 0 },
282 { 342, 0, 0, 0, 5, 0, 0, 0 },
283 { 406, 0, 0, 0, 6, 0, 0, 0 },
284 { 432, 0, 0, 0, 7, 0, 0, 0 },
285 { 458, 0, 0, 0, 8, 0, 0, 0 },
286 { 484, 0, 0, 0, 9, 0, 0, 0 },
287 { 510, 0, 0, 0, 10, 0, 0, 0 },
288 { 0, 0, 0, 0, 11, 0, 0, 0 },
289 { 73, 0, 0, 0, 12, 0, 0, 0 },
290 { 146, 0, 0, 0, 13, 0, 0, 0 },
291 { 235, 0, 0, 0, 14, 0, 0, 0 },
292 { 299, 0, 0, 0, 15, 0, 0, 0 },
293 { 388, 0, 0, 0, 16, 0, 0, 0 },
294 { 414, 0, 0, 0, 17, 0, 0, 0 },
295 { 440, 0, 0, 0, 18, 0, 0, 0 },
296 { 466, 0, 0, 0, 19, 0, 0, 0 },
297 { 492, 0, 0, 0, 20, 0, 0, 0 },
298 { 9, 0, 0, 0, 21, 0, 0, 0 },
299 { 82, 0, 0, 0, 22, 0, 0, 0 },
300 { 155, 0, 0, 0, 23, 0, 0, 0 },
301 { 244, 0, 0, 0, 24, 0, 0, 0 },
302 { 308, 0, 0, 0, 25, 0, 0, 0 },
303 { 397, 0, 0, 0, 26, 0, 0, 0 },
304 { 423, 0, 0, 0, 27, 0, 0, 0 },
305 { 449, 0, 0, 0, 28, 0, 0, 0 },
306 { 475, 0, 0, 0, 29, 0, 0, 0 },
307 { 501, 0, 0, 0, 30, 0, 0, 0 },
308 { 18, 0, 0, 0, 31, 0, 0, 0 },
309 { 91, 0, 0, 0, 32, 0, 0, 0 },
310 { 36, 0, 0, 0, 33, 0, 0, 0 },
311 { 109, 0, 0, 0, 34, 0, 0, 0 },
312 { 198, 0, 0, 0, 35, 0, 0, 0 },
313 { 262, 0, 0, 0, 36, 0, 0, 0 },
314 { 351, 0, 0, 0, 37, 0, 0, 0 },
315 { 35, 0, 0, 0, 38, 0, 0, 0 },
316 { 108, 0, 0, 0, 39, 0, 0, 0 },
317 { 197, 0, 0, 0, 40, 0, 0, 0 },
318 { 261, 0, 0, 0, 41, 0, 0, 0 },
319 { 350, 0, 0, 0, 42, 0, 0, 0 },
320 { 43, 0, 0, 0, 43, 0, 0, 0 },
321 { 116, 0, 0, 0, 44, 0, 0, 0 },
322 { 205, 0, 0, 0, 45, 0, 0, 0 },
323 { 269, 0, 0, 0, 46, 0, 0, 0 },
324 { 358, 0, 0, 0, 47, 0, 0, 0 },
325 { 50, 0, 0, 0, 48, 0, 0, 0 },
326 { 123, 0, 0, 0, 49, 0, 0, 0 },
327 { 212, 0, 0, 0, 50, 0, 0, 0 },
328 { 276, 0, 0, 0, 51, 0, 0, 0 },
329 { 365, 0, 0, 0, 52, 0, 0, 0 },
330 { 39, 0, 0, 0, 53, 0, 0, 0 },
331 { 112, 0, 0, 0, 54, 0, 0, 0 },
332 { 201, 0, 0, 0, 55, 0, 0, 0 },
333 { 265, 0, 0, 0, 56, 0, 0, 0 },
334 { 354, 0, 0, 0, 57, 0, 0, 0 },
335 { 46, 0, 0, 0, 58, 0, 0, 0 },
336 { 119, 0, 0, 0, 59, 0, 0, 0 },
337 { 208, 0, 0, 0, 60, 0, 0, 0 },
338 { 272, 0, 0, 0, 61, 0, 0, 0 },
339 { 361, 0, 0, 0, 62, 0, 0, 0 },
340 { 53, 0, 0, 0, 63, 0, 0, 0 },
341 { 126, 0, 0, 0, 64, 0, 0, 0 },
342 { 215, 0, 0, 0, 65, 0, 0, 0 },
343 { 279, 0, 0, 0, 66, 0, 0, 0 },
344 { 368, 0, 0, 0, 67, 0, 0, 0 },
345 { 164, 0, 0, 0, 68, 0, 0, 0 },
346 { 317, 0, 0, 0, 69, 0, 0, 0 },
347 { 174, 0, 0, 0, 70, 0, 0, 0 },
348 { 327, 0, 0, 0, 71, 0, 0, 0 },
349 { 57, 0, 0, 0, 72, 0, 0, 0 },
350 { 130, 0, 0, 0, 73, 0, 0, 0 },
351 { 219, 0, 0, 0, 74, 0, 0, 0 },
352 { 283, 0, 0, 0, 75, 0, 0, 0 },
353 { 372, 0, 0, 0, 76, 0, 0, 0 },
354 { 61, 0, 0, 0, 77, 0, 0, 0 },
355 { 134, 0, 0, 0, 78, 0, 0, 0 },
356 { 223, 0, 0, 0, 79, 0, 0, 0 },
357 { 287, 0, 0, 0, 80, 0, 0, 0 },
358 { 376, 0, 0, 0, 81, 0, 0, 0 },
359 { 65, 0, 0, 0, 82, 0, 0, 0 },
360 { 138, 0, 0, 0, 83, 0, 0, 0 },
361 { 227, 0, 0, 0, 84, 0, 0, 0 },
362 { 291, 0, 0, 0, 85, 0, 0, 0 },
363 { 380, 0, 0, 0, 86, 0, 0, 0 },
364 { 69, 0, 0, 0, 87, 0, 0, 0 },
365 { 142, 0, 0, 0, 88, 0, 0, 0 },
366 { 231, 0, 0, 0, 89, 0, 0, 0 },
367 { 295, 0, 0, 0, 90, 0, 0, 0 },
368 { 384, 0, 0, 0, 91, 0, 0, 0 },
369};
370
371extern const MCPhysReg NVPTXRegUnitRoots[][2] = {
372 { NVPTX::VRDepot },
373 { NVPTX::ENVREG0 },
374 { NVPTX::ENVREG1 },
375 { NVPTX::ENVREG2 },
376 { NVPTX::ENVREG3 },
377 { NVPTX::ENVREG4 },
378 { NVPTX::ENVREG5 },
379 { NVPTX::ENVREG6 },
380 { NVPTX::ENVREG7 },
381 { NVPTX::ENVREG8 },
382 { NVPTX::ENVREG9 },
383 { NVPTX::ENVREG10 },
384 { NVPTX::ENVREG11 },
385 { NVPTX::ENVREG12 },
386 { NVPTX::ENVREG13 },
387 { NVPTX::ENVREG14 },
388 { NVPTX::ENVREG15 },
389 { NVPTX::ENVREG16 },
390 { NVPTX::ENVREG17 },
391 { NVPTX::ENVREG18 },
392 { NVPTX::ENVREG19 },
393 { NVPTX::ENVREG20 },
394 { NVPTX::ENVREG21 },
395 { NVPTX::ENVREG22 },
396 { NVPTX::ENVREG23 },
397 { NVPTX::ENVREG24 },
398 { NVPTX::ENVREG25 },
399 { NVPTX::ENVREG26 },
400 { NVPTX::ENVREG27 },
401 { NVPTX::ENVREG28 },
402 { NVPTX::ENVREG29 },
403 { NVPTX::ENVREG30 },
404 { NVPTX::ENVREG31 },
405 { NVPTX::H0 },
406 { NVPTX::H1 },
407 { NVPTX::H2 },
408 { NVPTX::H3 },
409 { NVPTX::H4 },
410 { NVPTX::HH0 },
411 { NVPTX::HH1 },
412 { NVPTX::HH2 },
413 { NVPTX::HH3 },
414 { NVPTX::HH4 },
415 { NVPTX::P0 },
416 { NVPTX::P1 },
417 { NVPTX::P2 },
418 { NVPTX::P3 },
419 { NVPTX::P4 },
420 { NVPTX::R0 },
421 { NVPTX::R1 },
422 { NVPTX::R2 },
423 { NVPTX::R3 },
424 { NVPTX::R4 },
425 { NVPTX::RL0 },
426 { NVPTX::RL1 },
427 { NVPTX::RL2 },
428 { NVPTX::RL3 },
429 { NVPTX::RL4 },
430 { NVPTX::RQ0 },
431 { NVPTX::RQ1 },
432 { NVPTX::RQ2 },
433 { NVPTX::RQ3 },
434 { NVPTX::RQ4 },
435 { NVPTX::RS0 },
436 { NVPTX::RS1 },
437 { NVPTX::RS2 },
438 { NVPTX::RS3 },
439 { NVPTX::RS4 },
440 { NVPTX::VRFrame32 },
441 { NVPTX::VRFrame64 },
442 { NVPTX::VRFrameLocal32 },
443 { NVPTX::VRFrameLocal64 },
444 { NVPTX::da0 },
445 { NVPTX::da1 },
446 { NVPTX::da2 },
447 { NVPTX::da3 },
448 { NVPTX::da4 },
449 { NVPTX::fa0 },
450 { NVPTX::fa1 },
451 { NVPTX::fa2 },
452 { NVPTX::fa3 },
453 { NVPTX::fa4 },
454 { NVPTX::ia0 },
455 { NVPTX::ia1 },
456 { NVPTX::ia2 },
457 { NVPTX::ia3 },
458 { NVPTX::ia4 },
459 { NVPTX::la0 },
460 { NVPTX::la1 },
461 { NVPTX::la2 },
462 { NVPTX::la3 },
463 { NVPTX::la4 },
464};
465
466namespace { // Register classes...
467 // B1 Register Class...
468 const MCPhysReg B1[] = {
469 NVPTX::P0, NVPTX::P1, NVPTX::P2, NVPTX::P3, NVPTX::P4,
470 };
471
472 // B1 Bit set.
473 const uint8_t B1Bits[] = {
474 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x01,
475 };
476
477 // B16 Register Class...
478 const MCPhysReg B16[] = {
479 NVPTX::RS0, NVPTX::RS1, NVPTX::RS2, NVPTX::RS3, NVPTX::RS4,
480 };
481
482 // B16 Bit set.
483 const uint8_t B16Bits[] = {
484 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1f,
485 };
486
487 // SpecialRegs Register Class...
488 const MCPhysReg SpecialRegs[] = {
489 NVPTX::VRFrame32, NVPTX::VRFrameLocal32, NVPTX::VRDepot, NVPTX::ENVREG0, NVPTX::ENVREG1, NVPTX::ENVREG2, NVPTX::ENVREG3, NVPTX::ENVREG4, NVPTX::ENVREG5, NVPTX::ENVREG6, NVPTX::ENVREG7, NVPTX::ENVREG8, NVPTX::ENVREG9, NVPTX::ENVREG10, NVPTX::ENVREG11, NVPTX::ENVREG12, NVPTX::ENVREG13, NVPTX::ENVREG14, NVPTX::ENVREG15, NVPTX::ENVREG16, NVPTX::ENVREG17, NVPTX::ENVREG18, NVPTX::ENVREG19, NVPTX::ENVREG20, NVPTX::ENVREG21, NVPTX::ENVREG22, NVPTX::ENVREG23, NVPTX::ENVREG24, NVPTX::ENVREG25, NVPTX::ENVREG26, NVPTX::ENVREG27, NVPTX::ENVREG28, NVPTX::ENVREG29, NVPTX::ENVREG30, NVPTX::ENVREG31,
490 };
491
492 // SpecialRegs Bit set.
493 const uint8_t SpecialRegsBits[] = {
494 0xfe, 0xff, 0xff, 0xff, 0x03, 0x00, 0x00, 0x00, 0xa0,
495 };
496
497 // B32 Register Class...
498 const MCPhysReg B32[] = {
499 NVPTX::R0, NVPTX::R1, NVPTX::R2, NVPTX::R3, NVPTX::R4, NVPTX::VRFrame32, NVPTX::VRFrameLocal32,
500 };
501
502 // B32 Bit set.
503 const uint8_t B32Bits[] = {
504 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3e, 0x00, 0xa0,
505 };
506
507 // B32_and_SpecialRegs Register Class...
508 const MCPhysReg B32_and_SpecialRegs[] = {
509 NVPTX::VRFrame32, NVPTX::VRFrameLocal32,
510 };
511
512 // B32_and_SpecialRegs Bit set.
513 const uint8_t B32_and_SpecialRegsBits[] = {
514 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0,
515 };
516
517 // B64 Register Class...
518 const MCPhysReg B64[] = {
519 NVPTX::RL0, NVPTX::RL1, NVPTX::RL2, NVPTX::RL3, NVPTX::RL4, NVPTX::VRFrame64, NVPTX::VRFrameLocal64,
520 };
521
522 // B64 Bit set.
523 const uint8_t B64Bits[] = {
524 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x40, 0x01,
525 };
526
527 // B128 Register Class...
528 const MCPhysReg B128[] = {
529 NVPTX::RQ0, NVPTX::RQ1, NVPTX::RQ2, NVPTX::RQ3, NVPTX::RQ4,
530 };
531
532 // B128 Bit set.
533 const uint8_t B128Bits[] = {
534 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8,
535 };
536
537} // end anonymous namespace
538
539
540#ifdef __GNUC__
541#pragma GCC diagnostic push
542#pragma GCC diagnostic ignored "-Woverlength-strings"
543#endif
544extern const char NVPTXRegClassStrings[] = {
545 /* 0 */ "B1\000"
546 /* 3 */ "B32\000"
547 /* 7 */ "B64\000"
548 /* 11 */ "B16\000"
549 /* 15 */ "B128\000"
550 /* 20 */ "B32_and_SpecialRegs\000"
551};
552#ifdef __GNUC__
553#pragma GCC diagnostic pop
554#endif
555
556extern const MCRegisterClass NVPTXMCRegisterClasses[] = {
557 { B1, B1Bits, 0, 5, sizeof(B1Bits), NVPTX::B1RegClassID, 1, 1, true, false },
558 { B16, B16Bits, 11, 5, sizeof(B16Bits), NVPTX::B16RegClassID, 16, 1, true, false },
559 { SpecialRegs, SpecialRegsBits, 28, 35, sizeof(SpecialRegsBits), NVPTX::SpecialRegsRegClassID, 32, 1, true, false },
560 { B32, B32Bits, 3, 7, sizeof(B32Bits), NVPTX::B32RegClassID, 32, 1, true, false },
561 { B32_and_SpecialRegs, B32_and_SpecialRegsBits, 20, 2, sizeof(B32_and_SpecialRegsBits), NVPTX::B32_and_SpecialRegsRegClassID, 32, 1, true, false },
562 { B64, B64Bits, 7, 7, sizeof(B64Bits), NVPTX::B64RegClassID, 64, 1, true, false },
563 { B128, B128Bits, 15, 5, sizeof(B128Bits), NVPTX::B128RegClassID, 128, 1, true, false },
564};
565
566extern const uint16_t NVPTXRegEncodingTable[] = {
567 0,
568 0,
569 0,
570 0,
571 0,
572 0,
573 0,
574 0,
575 0,
576 0,
577 0,
578 0,
579 0,
580 0,
581 0,
582 0,
583 0,
584 0,
585 0,
586 0,
587 0,
588 0,
589 0,
590 0,
591 0,
592 0,
593 0,
594 0,
595 0,
596 0,
597 0,
598 0,
599 0,
600 0,
601 0,
602 0,
603 0,
604 0,
605 0,
606 0,
607 0,
608 0,
609 0,
610 0,
611 0,
612 0,
613 0,
614 0,
615 0,
616 0,
617 0,
618 0,
619 0,
620 0,
621 0,
622 0,
623 0,
624 0,
625 0,
626 0,
627 0,
628 0,
629 0,
630 0,
631 0,
632 0,
633 0,
634 0,
635 0,
636 0,
637 0,
638 0,
639 0,
640 0,
641 0,
642 0,
643 0,
644 0,
645 0,
646 0,
647 0,
648 0,
649 0,
650 0,
651 0,
652 0,
653 0,
654 0,
655 0,
656 0,
657 0,
658 0,
659 0,
660};
661static inline void InitNVPTXMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
662 RI->InitMCRegisterInfo(NVPTXRegDesc, 93, RA, PC, NVPTXMCRegisterClasses, 7, NVPTXRegUnitRoots, 92, NVPTXRegDiffLists, NVPTXLaneMaskLists, NVPTXRegStrings, NVPTXRegClassStrings, NVPTXSubRegIdxLists, 1,
663NVPTXRegEncodingTable);
664
665}
666
667} // end namespace llvm
668
669#endif // GET_REGINFO_MC_DESC
670
671/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
672|* *|
673|* Register Information Header Fragment *|
674|* *|
675|* Automatically generated file, do not edit! *|
676|* *|
677\*===----------------------------------------------------------------------===*/
678
679
680#ifdef GET_REGINFO_HEADER
681#undef GET_REGINFO_HEADER
682
683#include "llvm/CodeGen/TargetRegisterInfo.h"
684
685namespace llvm {
686
687class NVPTXFrameLowering;
688
689struct NVPTXGenRegisterInfo : public TargetRegisterInfo {
690 explicit NVPTXGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
691 unsigned PC = 0, unsigned HwMode = 0);
692 const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
693 unsigned getRegUnitWeight(unsigned RegUnit) const override;
694 unsigned getNumRegPressureSets() const override;
695 const char *getRegPressureSetName(unsigned Idx) const override;
696 unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
697 const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
698 const int *getRegUnitPressureSets(unsigned RegUnit) const override;
699 ArrayRef<const char *> getRegMaskNames() const override;
700 ArrayRef<const uint32_t *> getRegMasks() const override;
701 bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override;
702 bool isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const override;
703 bool isFixedRegister(const MachineFunction &, MCRegister) const override;
704 bool isArgumentRegister(const MachineFunction &, MCRegister) const override;
705 bool isConstantPhysReg(MCRegister PhysReg) const override final;
706 /// Devirtualized TargetFrameLowering.
707 static const NVPTXFrameLowering *getFrameLowering(
708 const MachineFunction &MF);
709};
710
711namespace NVPTX { // Register classes
712 extern const TargetRegisterClass B1RegClass;
713 extern const TargetRegisterClass B16RegClass;
714 extern const TargetRegisterClass SpecialRegsRegClass;
715 extern const TargetRegisterClass B32RegClass;
716 extern const TargetRegisterClass B32_and_SpecialRegsRegClass;
717 extern const TargetRegisterClass B64RegClass;
718 extern const TargetRegisterClass B128RegClass;
719} // end namespace NVPTX
720
721} // end namespace llvm
722
723#endif // GET_REGINFO_HEADER
724
725/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
726|* *|
727|* Target Register and Register Classes Information *|
728|* *|
729|* Automatically generated file, do not edit! *|
730|* *|
731\*===----------------------------------------------------------------------===*/
732
733
734#ifdef GET_REGINFO_TARGET_DESC
735#undef GET_REGINFO_TARGET_DESC
736
737namespace llvm {
738
739extern const MCRegisterClass NVPTXMCRegisterClasses[];
740
741static const MVT::SimpleValueType VTLists[] = {
742 /* 0 */ MVT::i1, MVT::Other,
743 /* 2 */ MVT::i32, MVT::Other,
744 /* 4 */ MVT::i128, MVT::Other,
745 /* 6 */ MVT::i16, MVT::f16, MVT::bf16, MVT::Other,
746 /* 10 */ MVT::i32, MVT::v2f16, MVT::v2bf16, MVT::v2i16, MVT::v4i8, MVT::f32, MVT::Other,
747 /* 17 */ MVT::i64, MVT::f64, MVT::Other,
748};
749
750static const char *SubRegIndexNameTable[] = { "" };
751
752static const TargetRegisterInfo::SubRegCoveredBits SubRegIdxRangeTable[] = {
753 { 65535, 65535 },
754};
755
756
757static const LaneBitmask SubRegIndexLaneMaskTable[] = {
758 LaneBitmask::getAll(),
759 };
760
761
762
763static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
764 // Mode = 0 (Default)
765 { 1, 1, 8, /*VTLists+*/0 }, // B1
766 { 16, 16, 16, /*VTLists+*/6 }, // B16
767 { 32, 32, 32, /*VTLists+*/2 }, // SpecialRegs
768 { 32, 32, 32, /*VTLists+*/10 }, // B32
769 { 32, 32, 32, /*VTLists+*/10 }, // B32_and_SpecialRegs
770 { 64, 64, 64, /*VTLists+*/17 }, // B64
771 { 128, 128, 128, /*VTLists+*/4 }, // B128
772};
773static const uint32_t B1SubClassMask[] = {
774 0x00000001,
775};
776
777static const uint32_t B16SubClassMask[] = {
778 0x00000002,
779};
780
781static const uint32_t SpecialRegsSubClassMask[] = {
782 0x00000014,
783};
784
785static const uint32_t B32SubClassMask[] = {
786 0x00000018,
787};
788
789static const uint32_t B32_and_SpecialRegsSubClassMask[] = {
790 0x00000010,
791};
792
793static const uint32_t B64SubClassMask[] = {
794 0x00000020,
795};
796
797static const uint32_t B128SubClassMask[] = {
798 0x00000040,
799};
800
801static const uint16_t SuperRegIdxSeqs[] = {
802 /* 0 */ 0,
803};
804
805static unsigned const B32_and_SpecialRegsSuperclasses[] = {
806 NVPTX::SpecialRegsRegClassID,
807 NVPTX::B32RegClassID,
808};
809
810
811namespace NVPTX { // Register class instances
812 extern const TargetRegisterClass B1RegClass = {
813 &NVPTXMCRegisterClasses[B1RegClassID],
814 B1SubClassMask,
815 SuperRegIdxSeqs + 0,
816 LaneBitmask(0x0000000000000001),
817 0,
818 false,
819 0x00, /* TSFlags */
820 false, /* HasDisjunctSubRegs */
821 false, /* CoveredBySubRegs */
822 nullptr, 0,
823 nullptr
824 };
825
826 extern const TargetRegisterClass B16RegClass = {
827 &NVPTXMCRegisterClasses[B16RegClassID],
828 B16SubClassMask,
829 SuperRegIdxSeqs + 0,
830 LaneBitmask(0x0000000000000001),
831 0,
832 false,
833 0x00, /* TSFlags */
834 false, /* HasDisjunctSubRegs */
835 false, /* CoveredBySubRegs */
836 nullptr, 0,
837 nullptr
838 };
839
840 extern const TargetRegisterClass SpecialRegsRegClass = {
841 &NVPTXMCRegisterClasses[SpecialRegsRegClassID],
842 SpecialRegsSubClassMask,
843 SuperRegIdxSeqs + 0,
844 LaneBitmask(0x0000000000000001),
845 0,
846 false,
847 0x00, /* TSFlags */
848 false, /* HasDisjunctSubRegs */
849 false, /* CoveredBySubRegs */
850 nullptr, 0,
851 nullptr
852 };
853
854 extern const TargetRegisterClass B32RegClass = {
855 &NVPTXMCRegisterClasses[B32RegClassID],
856 B32SubClassMask,
857 SuperRegIdxSeqs + 0,
858 LaneBitmask(0x0000000000000001),
859 0,
860 false,
861 0x00, /* TSFlags */
862 false, /* HasDisjunctSubRegs */
863 false, /* CoveredBySubRegs */
864 nullptr, 0,
865 nullptr
866 };
867
868 extern const TargetRegisterClass B32_and_SpecialRegsRegClass = {
869 &NVPTXMCRegisterClasses[B32_and_SpecialRegsRegClassID],
870 B32_and_SpecialRegsSubClassMask,
871 SuperRegIdxSeqs + 0,
872 LaneBitmask(0x0000000000000001),
873 0,
874 false,
875 0x00, /* TSFlags */
876 false, /* HasDisjunctSubRegs */
877 false, /* CoveredBySubRegs */
878 B32_and_SpecialRegsSuperclasses, 2,
879 nullptr
880 };
881
882 extern const TargetRegisterClass B64RegClass = {
883 &NVPTXMCRegisterClasses[B64RegClassID],
884 B64SubClassMask,
885 SuperRegIdxSeqs + 0,
886 LaneBitmask(0x0000000000000001),
887 0,
888 false,
889 0x00, /* TSFlags */
890 false, /* HasDisjunctSubRegs */
891 false, /* CoveredBySubRegs */
892 nullptr, 0,
893 nullptr
894 };
895
896 extern const TargetRegisterClass B128RegClass = {
897 &NVPTXMCRegisterClasses[B128RegClassID],
898 B128SubClassMask,
899 SuperRegIdxSeqs + 0,
900 LaneBitmask(0x0000000000000001),
901 0,
902 false,
903 0x00, /* TSFlags */
904 false, /* HasDisjunctSubRegs */
905 false, /* CoveredBySubRegs */
906 nullptr, 0,
907 nullptr
908 };
909
910} // end namespace NVPTX
911
912namespace {
913 const TargetRegisterClass *const RegisterClasses[] = {
914 &NVPTX::B1RegClass,
915 &NVPTX::B16RegClass,
916 &NVPTX::SpecialRegsRegClass,
917 &NVPTX::B32RegClass,
918 &NVPTX::B32_and_SpecialRegsRegClass,
919 &NVPTX::B64RegClass,
920 &NVPTX::B128RegClass,
921 };
922} // end anonymous namespace
923
924static const uint8_t CostPerUseTable[] = {
9250, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
926
927
928static const bool InAllocatableClassTable[] = {
929false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, };
930
931
932static const TargetRegisterInfoDesc NVPTXRegInfoDesc = { // Extra Descriptors
933CostPerUseTable, 1, InAllocatableClassTable};
934
935/// Get the weight in units of pressure for this register class.
936const RegClassWeight &NVPTXGenRegisterInfo::
937getRegClassWeight(const TargetRegisterClass *RC) const {
938 static const RegClassWeight RCWeightTable[] = {
939 {1, 5}, // B1
940 {1, 5}, // B16
941 {1, 35}, // SpecialRegs
942 {1, 7}, // B32
943 {1, 2}, // B32_and_SpecialRegs
944 {1, 7}, // B64
945 {1, 5}, // B128
946 };
947 return RCWeightTable[RC->getID()];
948}
949
950/// Get the weight in units of pressure for this register unit.
951unsigned NVPTXGenRegisterInfo::
952getRegUnitWeight(unsigned RegUnit) const {
953 assert(RegUnit < 92 && "invalid register unit");
954 // All register units have unit weight.
955 return 1;
956}
957
958
959// Get the number of dimensions of register pressure.
960unsigned NVPTXGenRegisterInfo::getNumRegPressureSets() const {
961 return 8;
962}
963
964// Get the name of this register unit pressure set.
965const char *NVPTXGenRegisterInfo::
966getRegPressureSetName(unsigned Idx) const {
967 static const char *PressureNameTable[] = {
968 "B32_and_SpecialRegs",
969 "B1",
970 "B16",
971 "B128",
972 "B32",
973 "B64",
974 "SpecialRegs",
975 "SpecialRegs_with_B32",
976 };
977 return PressureNameTable[Idx];
978}
979
980// Get the register unit pressure limit for this dimension.
981// This limit must be adjusted dynamically for reserved registers.
982unsigned NVPTXGenRegisterInfo::
983getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
984 static const uint8_t PressureLimitTable[] = {
985 2, // 0: B32_and_SpecialRegs
986 5, // 1: B1
987 5, // 2: B16
988 5, // 3: B128
989 7, // 4: B32
990 7, // 5: B64
991 35, // 6: SpecialRegs
992 40, // 7: SpecialRegs_with_B32
993 };
994 return PressureLimitTable[Idx];
995}
996
997/// Table of pressure sets per register class or unit.
998static const int RCSetsTable[] = {
999 /* 0 */ 1, -1,
1000 /* 2 */ 2, -1,
1001 /* 4 */ 3, -1,
1002 /* 6 */ 5, -1,
1003 /* 8 */ 4, 7, -1,
1004 /* 11 */ 0, 4, 6, 7, -1,
1005};
1006
1007/// Get the dimensions of register pressure impacted by this register class.
1008/// Returns a -1 terminated array of pressure set IDs
1009const int *NVPTXGenRegisterInfo::
1010getRegClassPressureSets(const TargetRegisterClass *RC) const {
1011 static const uint8_t RCSetStartTable[] = {
1012 0,2,13,8,11,6,4,};
1013 return &RCSetsTable[RCSetStartTable[RC->getID()]];
1014}
1015
1016/// Get the dimensions of register pressure impacted by this register unit.
1017/// Returns a -1 terminated array of pressure set IDs
1018const int *NVPTXGenRegisterInfo::
1019getRegUnitPressureSets(unsigned RegUnit) const {
1020 assert(RegUnit < 92 && "invalid register unit");
1021 static const uint8_t RUSetStartTable[] = {
1022 13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,8,8,8,8,8,6,6,6,6,6,4,4,4,4,4,2,2,2,2,2,11,6,11,6,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,};
1023 return &RCSetsTable[RUSetStartTable[RegUnit]];
1024}
1025
1026extern const MCRegisterDesc NVPTXRegDesc[];
1027extern const int16_t NVPTXRegDiffLists[];
1028extern const LaneBitmask NVPTXLaneMaskLists[];
1029extern const char NVPTXRegStrings[];
1030extern const char NVPTXRegClassStrings[];
1031extern const MCPhysReg NVPTXRegUnitRoots[][2];
1032extern const uint16_t NVPTXSubRegIdxLists[];
1033extern const uint16_t NVPTXRegEncodingTable[];
1034NVPTXGenRegisterInfo::
1035NVPTXGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
1036 unsigned PC, unsigned HwMode)
1037 : TargetRegisterInfo(&NVPTXRegInfoDesc, RegisterClasses, RegisterClasses+7,
1038 SubRegIndexNameTable, SubRegIdxRangeTable, SubRegIndexLaneMaskTable,
1039 LaneBitmask(0xFFFFFFFFFFFFFFFF), RegClassInfos, VTLists, HwMode) {
1040 InitMCRegisterInfo(NVPTXRegDesc, 93, RA, PC,
1041 NVPTXMCRegisterClasses, 7,
1042 NVPTXRegUnitRoots,
1043 92,
1044 NVPTXRegDiffLists,
1045 NVPTXLaneMaskLists,
1046 NVPTXRegStrings,
1047 NVPTXRegClassStrings,
1048 NVPTXSubRegIdxLists,
1049 1,
1050 NVPTXRegEncodingTable);
1051
1052}
1053
1054
1055
1056ArrayRef<const uint32_t *> NVPTXGenRegisterInfo::getRegMasks() const {
1057 return {};
1058}
1059
1060bool NVPTXGenRegisterInfo::
1061isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
1062 return
1063 false;
1064}
1065
1066bool NVPTXGenRegisterInfo::
1067isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
1068 return
1069 false;
1070}
1071
1072bool NVPTXGenRegisterInfo::
1073isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
1074 return
1075 false;
1076}
1077
1078bool NVPTXGenRegisterInfo::
1079isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
1080 return
1081 false;
1082}
1083
1084bool NVPTXGenRegisterInfo::
1085isConstantPhysReg(MCRegister PhysReg) const {
1086 return
1087 false;
1088}
1089
1090ArrayRef<const char *> NVPTXGenRegisterInfo::getRegMaskNames() const {
1091 return {};
1092}
1093
1094const NVPTXFrameLowering *
1095NVPTXGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
1096 return static_cast<const NVPTXFrameLowering *>(
1097 MF.getSubtarget().getFrameLowering());
1098}
1099
1100} // end namespace llvm
1101
1102#endif // GET_REGINFO_TARGET_DESC
1103
1104