1//===-- NVPTX.h - Top-level interface for NVPTX representation --*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the entry points for global functions defined in
10// the LLVM NVPTX back-end.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_NVPTX_NVPTX_H
15#define LLVM_LIB_TARGET_NVPTX_NVPTX_H
16
17#include "llvm/IR/PassManager.h"
18#include "llvm/Pass.h"
19#include "llvm/Support/AtomicOrdering.h"
20#include "llvm/Support/CodeGen.h"
21#include "llvm/Target/TargetMachine.h"
22
23namespace llvm {
24class FunctionPass;
25class MachineFunctionPass;
26class NVPTXTargetMachine;
27class PassRegistry;
28
29namespace NVPTXCC {
30enum CondCodes {
31 EQ,
32 NE,
33 LT,
34 LE,
35 GT,
36 GE
37};
38}
39
40FunctionPass *createNVPTXISelDag(NVPTXTargetMachine &TM,
41 llvm::CodeGenOptLevel OptLevel);
42ModulePass *createNVPTXAssignValidGlobalNamesPass();
43ModulePass *createGenericToNVVMLegacyPass();
44ModulePass *createNVPTXCtorDtorLoweringLegacyPass();
45FunctionPass *createNVVMIntrRangePass();
46ModulePass *createNVVMReflectPass(unsigned int SmVersion);
47MachineFunctionPass *createNVPTXPrologEpilogPass();
48MachineFunctionPass *createNVPTXReplaceImageHandlesPass();
49FunctionPass *createNVPTXImageOptimizerPass();
50FunctionPass *createNVPTXLowerArgsPass();
51FunctionPass *createNVPTXLowerAllocaPass();
52FunctionPass *createNVPTXLowerUnreachablePass(bool TrapUnreachable,
53 bool NoTrapAfterNoreturn);
54FunctionPass *createNVPTXTagInvariantLoadsPass();
55MachineFunctionPass *createNVPTXPeephole();
56MachineFunctionPass *createNVPTXProxyRegErasurePass();
57MachineFunctionPass *createNVPTXForwardParamsPass();
58
59void initializeNVVMReflectLegacyPassPass(PassRegistry &);
60void initializeGenericToNVVMLegacyPassPass(PassRegistry &);
61void initializeNVPTXAllocaHoistingPass(PassRegistry &);
62void initializeNVPTXAsmPrinterPass(PassRegistry &);
63void initializeNVPTXAssignValidGlobalNamesPass(PassRegistry &);
64void initializeNVPTXAtomicLowerPass(PassRegistry &);
65void initializeNVPTXCtorDtorLoweringLegacyPass(PassRegistry &);
66void initializeNVPTXLowerAggrCopiesPass(PassRegistry &);
67void initializeNVPTXLowerAllocaPass(PassRegistry &);
68void initializeNVPTXLowerUnreachablePass(PassRegistry &);
69void initializeNVPTXCtorDtorLoweringLegacyPass(PassRegistry &);
70void initializeNVPTXLowerArgsLegacyPassPass(PassRegistry &);
71void initializeNVPTXProxyRegErasurePass(PassRegistry &);
72void initializeNVPTXForwardParamsPassPass(PassRegistry &);
73void initializeNVVMIntrRangePass(PassRegistry &);
74void initializeNVVMReflectPass(PassRegistry &);
75void initializeNVPTXAAWrapperPassPass(PassRegistry &);
76void initializeNVPTXExternalAAWrapperPass(PassRegistry &);
77void initializeNVPTXPeepholePass(PassRegistry &);
78void initializeNVPTXTagInvariantLoadLegacyPassPass(PassRegistry &);
79void initializeNVPTXPrologEpilogPassPass(PassRegistry &);
80
81struct NVVMIntrRangePass : PassInfoMixin<NVVMIntrRangePass> {
82 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
83};
84
85struct NVVMReflectPass : PassInfoMixin<NVVMReflectPass> {
86 NVVMReflectPass() : SmVersion(0) {}
87 NVVMReflectPass(unsigned SmVersion) : SmVersion(SmVersion) {}
88 PreservedAnalyses run(Module &F, ModuleAnalysisManager &AM);
89
90private:
91 unsigned SmVersion;
92};
93
94struct GenericToNVVMPass : PassInfoMixin<GenericToNVVMPass> {
95 PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
96};
97
98struct NVPTXCopyByValArgsPass : PassInfoMixin<NVPTXCopyByValArgsPass> {
99 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
100};
101
102struct NVPTXLowerArgsPass : PassInfoMixin<NVPTXLowerArgsPass> {
103private:
104 TargetMachine &TM;
105
106public:
107 NVPTXLowerArgsPass(TargetMachine &TM) : TM(TM) {};
108 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
109};
110
111struct NVPTXTagInvariantLoadsPass : PassInfoMixin<NVPTXTagInvariantLoadsPass> {
112 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
113};
114
115namespace NVPTX {
116enum DrvInterface {
117 NVCL,
118 CUDA
119};
120
121// A field inside TSFlags needs a shift and a mask. The usage is
122// always as follows :
123// ((TSFlags & fieldMask) >> fieldShift)
124// The enum keeps the mask, the shift, and all valid values of the
125// field in one place.
126enum VecInstType {
127 VecInstTypeShift = 0,
128 VecInstTypeMask = 0xF,
129
130 VecNOP = 0,
131 VecLoad = 1,
132 VecStore = 2,
133 VecBuild = 3,
134 VecShuffle = 4,
135 VecExtract = 5,
136 VecInsert = 6,
137 VecDest = 7,
138 VecOther = 15
139};
140
141enum SimpleMove {
142 SimpleMoveMask = 0x10,
143 SimpleMoveShift = 4
144};
145enum LoadStore {
146 isLoadMask = 0x20,
147 isLoadShift = 5,
148 isStoreMask = 0x40,
149 isStoreShift = 6
150};
151
152// Extends LLVM AtomicOrdering with PTX Orderings:
153using OrderingUnderlyingType = unsigned int;
154enum Ordering : OrderingUnderlyingType {
155 NotAtomic = (OrderingUnderlyingType)
156 AtomicOrdering::NotAtomic, // PTX calls these: "Weak"
157 // Unordered = 1, // NVPTX maps LLVM Unorderd to Relaxed
158 Relaxed = (OrderingUnderlyingType)AtomicOrdering::Monotonic,
159 // Consume = 3, // Unimplemented in LLVM; NVPTX would map to "Acquire"
160 Acquire = (OrderingUnderlyingType)AtomicOrdering::Acquire,
161 Release = (OrderingUnderlyingType)AtomicOrdering::Release,
162 AcquireRelease = (OrderingUnderlyingType)AtomicOrdering::AcquireRelease,
163 SequentiallyConsistent =
164 (OrderingUnderlyingType)AtomicOrdering::SequentiallyConsistent,
165 Volatile = SequentiallyConsistent + 1,
166 RelaxedMMIO = Volatile + 1,
167 LASTORDERING = RelaxedMMIO
168};
169
170using ScopeUnderlyingType = unsigned int;
171enum Scope : ScopeUnderlyingType {
172 Thread = 0,
173 Block = 1,
174 Cluster = 2,
175 Device = 3,
176 System = 4,
177 LASTSCOPE = System
178};
179
180using AddressSpaceUnderlyingType = unsigned int;
181enum AddressSpace : AddressSpaceUnderlyingType {
182 Generic = 0,
183 Global = 1,
184 Shared = 3,
185 Const = 4,
186 Local = 5,
187 SharedCluster = 7,
188
189 // NVPTX Backend Private:
190 Param = 101
191};
192
193namespace PTXLdStInstCode {
194enum FromType { Unsigned = 0, Signed, Float, Untyped };
195} // namespace PTXLdStInstCode
196
197/// PTXCvtMode - Conversion code enumeration
198namespace PTXCvtMode {
199enum CvtMode {
200 NONE = 0,
201 RNI,
202 RZI,
203 RMI,
204 RPI,
205 RN,
206 RZ,
207 RM,
208 RP,
209 RNA,
210
211 BASE_MASK = 0x0F,
212 FTZ_FLAG = 0x10,
213 SAT_FLAG = 0x20,
214 RELU_FLAG = 0x40
215};
216}
217
218/// PTXCmpMode - Comparison mode enumeration
219namespace PTXCmpMode {
220enum CmpMode {
221 EQ = 0,
222 NE,
223 LT,
224 LE,
225 GT,
226 GE,
227 LO,
228 LS,
229 HI,
230 HS,
231 EQU,
232 NEU,
233 LTU,
234 LEU,
235 GTU,
236 GEU,
237 NUM,
238 // NAN is a MACRO
239 NotANumber,
240
241 BASE_MASK = 0xFF,
242 FTZ_FLAG = 0x100
243};
244}
245
246namespace PTXPrmtMode {
247enum PrmtMode {
248 NONE,
249 F4E,
250 B4E,
251 RC8,
252 ECL,
253 ECR,
254 RC16,
255};
256}
257
258enum class DivPrecisionLevel : unsigned {
259 Approx = 0,
260 Full = 1,
261 IEEE754 = 2,
262 IEEE754_NoFTZ = 3,
263};
264
265} // namespace NVPTX
266void initializeNVPTXDAGToDAGISelLegacyPass(PassRegistry &);
267} // namespace llvm
268
269// Defines symbolic names for NVPTX registers. This defines a mapping from
270// register name to register number.
271#define GET_REGINFO_ENUM
272#include "NVPTXGenRegisterInfo.inc"
273
274// Defines symbolic names for the NVPTX instructions.
275#define GET_INSTRINFO_ENUM
276#define GET_INSTRINFO_MC_HELPER_DECLS
277#include "NVPTXGenInstrInfo.inc"
278
279#endif
280