1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Subtarget Enumeration Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_SUBTARGETINFO_ENUM
11#undef GET_SUBTARGETINFO_ENUM
12
13namespace llvm {
14namespace NVPTX {
15enum {
16 PTX32 = 0,
17 PTX40 = 1,
18 PTX41 = 2,
19 PTX42 = 3,
20 PTX43 = 4,
21 PTX50 = 5,
22 PTX60 = 6,
23 PTX61 = 7,
24 PTX62 = 8,
25 PTX63 = 9,
26 PTX64 = 10,
27 PTX65 = 11,
28 PTX70 = 12,
29 PTX71 = 13,
30 PTX72 = 14,
31 PTX73 = 15,
32 PTX74 = 16,
33 PTX75 = 17,
34 PTX76 = 18,
35 PTX77 = 19,
36 PTX78 = 20,
37 PTX80 = 21,
38 PTX81 = 22,
39 PTX82 = 23,
40 PTX83 = 24,
41 PTX84 = 25,
42 PTX85 = 26,
43 PTX86 = 27,
44 PTX87 = 28,
45 PTX88 = 29,
46 SM20 = 30,
47 SM21 = 31,
48 SM30 = 32,
49 SM32 = 33,
50 SM35 = 34,
51 SM37 = 35,
52 SM50 = 36,
53 SM52 = 37,
54 SM53 = 38,
55 SM60 = 39,
56 SM61 = 40,
57 SM62 = 41,
58 SM70 = 42,
59 SM72 = 43,
60 SM75 = 44,
61 SM80 = 45,
62 SM86 = 46,
63 SM87 = 47,
64 SM89 = 48,
65 SM90 = 49,
66 SM90a = 50,
67 SM100 = 51,
68 SM100a = 52,
69 SM100f = 53,
70 SM101 = 54,
71 SM101a = 55,
72 SM101f = 56,
73 SM103 = 57,
74 SM103a = 58,
75 SM103f = 59,
76 SM120 = 60,
77 SM120a = 61,
78 SM120f = 62,
79 SM121 = 63,
80 SM121a = 64,
81 SM121f = 65,
82 NumSubtargetFeatures = 66
83};
84} // end namespace NVPTX
85} // end namespace llvm
86
87#endif // GET_SUBTARGETINFO_ENUM
88
89
90#ifdef GET_SUBTARGETINFO_MACRO
91#undef GET_SUBTARGETINFO_MACRO
92#endif // GET_SUBTARGETINFO_MACRO
93
94
95#ifdef GET_SUBTARGETINFO_MC_DESC
96#undef GET_SUBTARGETINFO_MC_DESC
97
98namespace llvm {
99// Sorted (by key) array of values for CPU features.
100extern const llvm::SubtargetFeatureKV NVPTXFeatureKV[] = {
101 { "ptx32", "Use PTX version 32", NVPTX::PTX32, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
102 { "ptx40", "Use PTX version 40", NVPTX::PTX40, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
103 { "ptx41", "Use PTX version 41", NVPTX::PTX41, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
104 { "ptx42", "Use PTX version 42", NVPTX::PTX42, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
105 { "ptx43", "Use PTX version 43", NVPTX::PTX43, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
106 { "ptx50", "Use PTX version 50", NVPTX::PTX50, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
107 { "ptx60", "Use PTX version 60", NVPTX::PTX60, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
108 { "ptx61", "Use PTX version 61", NVPTX::PTX61, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
109 { "ptx62", "Use PTX version 62", NVPTX::PTX62, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
110 { "ptx63", "Use PTX version 63", NVPTX::PTX63, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
111 { "ptx64", "Use PTX version 64", NVPTX::PTX64, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
112 { "ptx65", "Use PTX version 65", NVPTX::PTX65, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
113 { "ptx70", "Use PTX version 70", NVPTX::PTX70, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
114 { "ptx71", "Use PTX version 71", NVPTX::PTX71, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
115 { "ptx72", "Use PTX version 72", NVPTX::PTX72, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
116 { "ptx73", "Use PTX version 73", NVPTX::PTX73, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
117 { "ptx74", "Use PTX version 74", NVPTX::PTX74, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
118 { "ptx75", "Use PTX version 75", NVPTX::PTX75, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
119 { "ptx76", "Use PTX version 76", NVPTX::PTX76, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
120 { "ptx77", "Use PTX version 77", NVPTX::PTX77, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
121 { "ptx78", "Use PTX version 78", NVPTX::PTX78, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
122 { "ptx80", "Use PTX version 80", NVPTX::PTX80, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
123 { "ptx81", "Use PTX version 81", NVPTX::PTX81, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
124 { "ptx82", "Use PTX version 82", NVPTX::PTX82, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
125 { "ptx83", "Use PTX version 83", NVPTX::PTX83, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
126 { "ptx84", "Use PTX version 84", NVPTX::PTX84, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
127 { "ptx85", "Use PTX version 85", NVPTX::PTX85, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
128 { "ptx86", "Use PTX version 86", NVPTX::PTX86, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
129 { "ptx87", "Use PTX version 87", NVPTX::PTX87, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
130 { "ptx88", "Use PTX version 88", NVPTX::PTX88, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
131 { "sm_100", "Target SM 100", NVPTX::SM100, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
132 { "sm_100a", "Target SM 100a", NVPTX::SM100a, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
133 { "sm_100f", "Target SM 100f", NVPTX::SM100f, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
134 { "sm_101", "Target SM 101", NVPTX::SM101, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
135 { "sm_101a", "Target SM 101a", NVPTX::SM101a, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
136 { "sm_101f", "Target SM 101f", NVPTX::SM101f, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
137 { "sm_103", "Target SM 103", NVPTX::SM103, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
138 { "sm_103a", "Target SM 103a", NVPTX::SM103a, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
139 { "sm_103f", "Target SM 103f", NVPTX::SM103f, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
140 { "sm_120", "Target SM 120", NVPTX::SM120, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
141 { "sm_120a", "Target SM 120a", NVPTX::SM120a, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
142 { "sm_120f", "Target SM 120f", NVPTX::SM120f, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
143 { "sm_121", "Target SM 121", NVPTX::SM121, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
144 { "sm_121a", "Target SM 121a", NVPTX::SM121a, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
145 { "sm_121f", "Target SM 121f", NVPTX::SM121f, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
146 { "sm_20", "Target SM 20", NVPTX::SM20, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
147 { "sm_21", "Target SM 21", NVPTX::SM21, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
148 { "sm_30", "Target SM 30", NVPTX::SM30, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
149 { "sm_32", "Target SM 32", NVPTX::SM32, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
150 { "sm_35", "Target SM 35", NVPTX::SM35, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
151 { "sm_37", "Target SM 37", NVPTX::SM37, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
152 { "sm_50", "Target SM 50", NVPTX::SM50, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
153 { "sm_52", "Target SM 52", NVPTX::SM52, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
154 { "sm_53", "Target SM 53", NVPTX::SM53, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
155 { "sm_60", "Target SM 60", NVPTX::SM60, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
156 { "sm_61", "Target SM 61", NVPTX::SM61, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
157 { "sm_62", "Target SM 62", NVPTX::SM62, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
158 { "sm_70", "Target SM 70", NVPTX::SM70, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
159 { "sm_72", "Target SM 72", NVPTX::SM72, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
160 { "sm_75", "Target SM 75", NVPTX::SM75, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
161 { "sm_80", "Target SM 80", NVPTX::SM80, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
162 { "sm_86", "Target SM 86", NVPTX::SM86, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
163 { "sm_87", "Target SM 87", NVPTX::SM87, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
164 { "sm_89", "Target SM 89", NVPTX::SM89, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
165 { "sm_90", "Target SM 90", NVPTX::SM90, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
166 { "sm_90a", "Target SM 90a", NVPTX::SM90a, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
167};
168
169#ifdef DBGFIELD
170#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
171#endif
172#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
173#define DBGFIELD(x) x,
174#define DBGVAL_OR_NULLPTR(x) x
175#else
176#define DBGFIELD(x)
177#define DBGVAL_OR_NULLPTR(x) nullptr
178#endif
179
180// ===============================================================
181// Data tables for the new per-operand machine model.
182
183// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}
184extern const llvm::MCWriteProcResEntry NVPTXWriteProcResTable[] = {
185 { 0, 0, 0 }, // Invalid
186}; // NVPTXWriteProcResTable
187
188// {Cycles, WriteResourceID}
189extern const llvm::MCWriteLatencyEntry NVPTXWriteLatencyTable[] = {
190 { 0, 0}, // Invalid
191}; // NVPTXWriteLatencyTable
192
193// {UseIdx, WriteResourceID, Cycles}
194extern const llvm::MCReadAdvanceEntry NVPTXReadAdvanceTable[] = {
195 {0, 0, 0}, // Invalid
196}; // NVPTXReadAdvanceTable
197
198#ifdef __GNUC__
199#pragma GCC diagnostic push
200#pragma GCC diagnostic ignored "-Woverlength-strings"
201#endif
202static constexpr char NVPTXSchedClassNamesStorage[] =
203 "\0"
204 "InvalidSchedClass\0"
205 ;
206#ifdef __GNUC__
207#pragma GCC diagnostic pop
208#endif
209
210static constexpr llvm::StringTable NVPTXSchedClassNames =
211 NVPTXSchedClassNamesStorage;
212
213static const llvm::MCSchedModel NoSchedModel = {
214 MCSchedModel::DefaultIssueWidth,
215 MCSchedModel::DefaultMicroOpBufferSize,
216 MCSchedModel::DefaultLoopMicroOpBufferSize,
217 MCSchedModel::DefaultLoadLatency,
218 MCSchedModel::DefaultHighLatency,
219 MCSchedModel::DefaultMispredictPenalty,
220 false, // PostRAScheduler
221 false, // CompleteModel
222 false, // EnableIntervals
223 0, // Processor ID
224 nullptr, nullptr, 0, 0, // No instruction-level machine model.
225 DBGVAL_OR_NULLPTR(&NVPTXSchedClassNames), // SchedClassNames
226 nullptr, // No Itinerary
227 nullptr // No extra processor descriptor
228};
229
230#undef DBGFIELD
231
232#undef DBGVAL_OR_NULLPTR
233
234// Sorted (by key) array of values for CPU subtype.
235extern const llvm::SubtargetSubTypeKV NVPTXSubTypeKV[] = {
236 { "sm_100", { { { 0x8000008000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
237 { "sm_100a", { { { 0x10000008000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
238 { "sm_100f", { { { 0x20000020000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
239 { "sm_101", { { { 0x40000008000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
240 { "sm_101a", { { { 0x80000008000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
241 { "sm_101f", { { { 0x100000020000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
242 { "sm_103", { { { 0x200000020000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
243 { "sm_103a", { { { 0x400000020000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
244 { "sm_103f", { { { 0x800000020000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
245 { "sm_120", { { { 0x1000000010000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
246 { "sm_120a", { { { 0x2000000010000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
247 { "sm_120f", { { { 0x4000000020000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
248 { "sm_121", { { { 0x8000000020000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
249 { "sm_121a", { { { 0x20000000ULL, 0x1ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
250 { "sm_121f", { { { 0x20000000ULL, 0x2ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
251 { "sm_20", { { { 0x40000001ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
252 { "sm_21", { { { 0x80000001ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
253 { "sm_30", { { { 0x100000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
254 { "sm_32", { { { 0x200000002ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
255 { "sm_35", { { { 0x400000001ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
256 { "sm_37", { { { 0x800000004ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
257 { "sm_50", { { { 0x1000000002ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
258 { "sm_52", { { { 0x2000000004ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
259 { "sm_53", { { { 0x4000000008ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
260 { "sm_60", { { { 0x8000000020ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
261 { "sm_61", { { { 0x10000000020ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
262 { "sm_62", { { { 0x20000000020ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
263 { "sm_70", { { { 0x40000000040ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
264 { "sm_72", { { { 0x80000000080ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
265 { "sm_75", { { { 0x100000000200ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
266 { "sm_80", { { { 0x200000001000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
267 { "sm_86", { { { 0x400000002000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
268 { "sm_87", { { { 0x800000010000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
269 { "sm_89", { { { 0x1000000100000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
270 { "sm_90", { { { 0x2000000100000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
271 { "sm_90a", { { { 0x4000000200000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
272};
273
274// Sorted array of names of CPU subtypes, including aliases.
275extern const llvm::StringRef NVPTXNames[] = {
276"sm_100",
277"sm_100a",
278"sm_100f",
279"sm_101",
280"sm_101a",
281"sm_101f",
282"sm_103",
283"sm_103a",
284"sm_103f",
285"sm_120",
286"sm_120a",
287"sm_120f",
288"sm_121",
289"sm_121a",
290"sm_121f",
291"sm_20",
292"sm_21",
293"sm_30",
294"sm_32",
295"sm_35",
296"sm_37",
297"sm_50",
298"sm_52",
299"sm_53",
300"sm_60",
301"sm_61",
302"sm_62",
303"sm_70",
304"sm_72",
305"sm_75",
306"sm_80",
307"sm_86",
308"sm_87",
309"sm_89",
310"sm_90",
311"sm_90a"};
312
313namespace NVPTX_MC {
314unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
315 const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) {
316 // Don't know how to resolve this scheduling class.
317 return 0;
318}
319} // end namespace NVPTX_MC
320
321struct NVPTXGenMCSubtargetInfo : public MCSubtargetInfo {
322 NVPTXGenMCSubtargetInfo(const Triple &TT,
323 StringRef CPU, StringRef TuneCPU, StringRef FS,
324 ArrayRef<StringRef> PN,
325 ArrayRef<SubtargetFeatureKV> PF,
326 ArrayRef<SubtargetSubTypeKV> PD,
327 const MCWriteProcResEntry *WPR,
328 const MCWriteLatencyEntry *WL,
329 const MCReadAdvanceEntry *RA, const InstrStage *IS,
330 const unsigned *OC, const unsigned *FP) :
331 MCSubtargetInfo(TT, CPU, TuneCPU, FS, PN, PF, PD,
332 WPR, WL, RA, IS, OC, FP) { }
333
334 unsigned resolveVariantSchedClass(unsigned SchedClass,
335 const MCInst *MI, const MCInstrInfo *MCII,
336 unsigned CPUID) const override {
337 return NVPTX_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);
338 }
339};
340
341static inline MCSubtargetInfo *createNVPTXMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
342 return new NVPTXGenMCSubtargetInfo(TT, CPU, TuneCPU, FS, NVPTXNames, NVPTXFeatureKV, NVPTXSubTypeKV,
343 NVPTXWriteProcResTable, NVPTXWriteLatencyTable, NVPTXReadAdvanceTable,
344 nullptr, nullptr, nullptr);
345}
346
347} // end namespace llvm
348
349#endif // GET_SUBTARGETINFO_MC_DESC
350
351
352#ifdef GET_SUBTARGETINFO_TARGET_DESC
353#undef GET_SUBTARGETINFO_TARGET_DESC
354
355#include "llvm/ADT/BitmaskEnum.h"
356#include "llvm/Support/Debug.h"
357#include "llvm/Support/raw_ostream.h"
358
359// ParseSubtargetFeatures - Parses features string setting specified
360// subtarget options.
361void llvm::NVPTXSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
362 LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
363 LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
364 LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
365 InitMCProcessorInfo(CPU, TuneCPU, FS);
366 const FeatureBitset &Bits = getFeatureBits();
367 if (Bits[NVPTX::PTX32] && PTXVersion < 32) PTXVersion = 32;
368 if (Bits[NVPTX::PTX40] && PTXVersion < 40) PTXVersion = 40;
369 if (Bits[NVPTX::PTX41] && PTXVersion < 41) PTXVersion = 41;
370 if (Bits[NVPTX::PTX42] && PTXVersion < 42) PTXVersion = 42;
371 if (Bits[NVPTX::PTX43] && PTXVersion < 43) PTXVersion = 43;
372 if (Bits[NVPTX::PTX50] && PTXVersion < 50) PTXVersion = 50;
373 if (Bits[NVPTX::PTX60] && PTXVersion < 60) PTXVersion = 60;
374 if (Bits[NVPTX::PTX61] && PTXVersion < 61) PTXVersion = 61;
375 if (Bits[NVPTX::PTX62] && PTXVersion < 62) PTXVersion = 62;
376 if (Bits[NVPTX::PTX63] && PTXVersion < 63) PTXVersion = 63;
377 if (Bits[NVPTX::PTX64] && PTXVersion < 64) PTXVersion = 64;
378 if (Bits[NVPTX::PTX65] && PTXVersion < 65) PTXVersion = 65;
379 if (Bits[NVPTX::PTX70] && PTXVersion < 70) PTXVersion = 70;
380 if (Bits[NVPTX::PTX71] && PTXVersion < 71) PTXVersion = 71;
381 if (Bits[NVPTX::PTX72] && PTXVersion < 72) PTXVersion = 72;
382 if (Bits[NVPTX::PTX73] && PTXVersion < 73) PTXVersion = 73;
383 if (Bits[NVPTX::PTX74] && PTXVersion < 74) PTXVersion = 74;
384 if (Bits[NVPTX::PTX75] && PTXVersion < 75) PTXVersion = 75;
385 if (Bits[NVPTX::PTX76] && PTXVersion < 76) PTXVersion = 76;
386 if (Bits[NVPTX::PTX77] && PTXVersion < 77) PTXVersion = 77;
387 if (Bits[NVPTX::PTX78] && PTXVersion < 78) PTXVersion = 78;
388 if (Bits[NVPTX::PTX80] && PTXVersion < 80) PTXVersion = 80;
389 if (Bits[NVPTX::PTX81] && PTXVersion < 81) PTXVersion = 81;
390 if (Bits[NVPTX::PTX82] && PTXVersion < 82) PTXVersion = 82;
391 if (Bits[NVPTX::PTX83] && PTXVersion < 83) PTXVersion = 83;
392 if (Bits[NVPTX::PTX84] && PTXVersion < 84) PTXVersion = 84;
393 if (Bits[NVPTX::PTX85] && PTXVersion < 85) PTXVersion = 85;
394 if (Bits[NVPTX::PTX86] && PTXVersion < 86) PTXVersion = 86;
395 if (Bits[NVPTX::PTX87] && PTXVersion < 87) PTXVersion = 87;
396 if (Bits[NVPTX::PTX88] && PTXVersion < 88) PTXVersion = 88;
397 if (Bits[NVPTX::SM20] && FullSmVersion < 200) FullSmVersion = 200;
398 if (Bits[NVPTX::SM21] && FullSmVersion < 210) FullSmVersion = 210;
399 if (Bits[NVPTX::SM30] && FullSmVersion < 300) FullSmVersion = 300;
400 if (Bits[NVPTX::SM32] && FullSmVersion < 320) FullSmVersion = 320;
401 if (Bits[NVPTX::SM35] && FullSmVersion < 350) FullSmVersion = 350;
402 if (Bits[NVPTX::SM37] && FullSmVersion < 370) FullSmVersion = 370;
403 if (Bits[NVPTX::SM50] && FullSmVersion < 500) FullSmVersion = 500;
404 if (Bits[NVPTX::SM52] && FullSmVersion < 520) FullSmVersion = 520;
405 if (Bits[NVPTX::SM53] && FullSmVersion < 530) FullSmVersion = 530;
406 if (Bits[NVPTX::SM60] && FullSmVersion < 600) FullSmVersion = 600;
407 if (Bits[NVPTX::SM61] && FullSmVersion < 610) FullSmVersion = 610;
408 if (Bits[NVPTX::SM62] && FullSmVersion < 620) FullSmVersion = 620;
409 if (Bits[NVPTX::SM70] && FullSmVersion < 700) FullSmVersion = 700;
410 if (Bits[NVPTX::SM72] && FullSmVersion < 720) FullSmVersion = 720;
411 if (Bits[NVPTX::SM75] && FullSmVersion < 750) FullSmVersion = 750;
412 if (Bits[NVPTX::SM80] && FullSmVersion < 800) FullSmVersion = 800;
413 if (Bits[NVPTX::SM86] && FullSmVersion < 860) FullSmVersion = 860;
414 if (Bits[NVPTX::SM87] && FullSmVersion < 870) FullSmVersion = 870;
415 if (Bits[NVPTX::SM89] && FullSmVersion < 890) FullSmVersion = 890;
416 if (Bits[NVPTX::SM90] && FullSmVersion < 900) FullSmVersion = 900;
417 if (Bits[NVPTX::SM90a] && FullSmVersion < 903) FullSmVersion = 903;
418 if (Bits[NVPTX::SM100] && FullSmVersion < 1000) FullSmVersion = 1000;
419 if (Bits[NVPTX::SM100a] && FullSmVersion < 1003) FullSmVersion = 1003;
420 if (Bits[NVPTX::SM100f] && FullSmVersion < 1002) FullSmVersion = 1002;
421 if (Bits[NVPTX::SM101] && FullSmVersion < 1010) FullSmVersion = 1010;
422 if (Bits[NVPTX::SM101a] && FullSmVersion < 1013) FullSmVersion = 1013;
423 if (Bits[NVPTX::SM101f] && FullSmVersion < 1012) FullSmVersion = 1012;
424 if (Bits[NVPTX::SM103] && FullSmVersion < 1030) FullSmVersion = 1030;
425 if (Bits[NVPTX::SM103a] && FullSmVersion < 1033) FullSmVersion = 1033;
426 if (Bits[NVPTX::SM103f] && FullSmVersion < 1032) FullSmVersion = 1032;
427 if (Bits[NVPTX::SM120] && FullSmVersion < 1200) FullSmVersion = 1200;
428 if (Bits[NVPTX::SM120a] && FullSmVersion < 1203) FullSmVersion = 1203;
429 if (Bits[NVPTX::SM120f] && FullSmVersion < 1202) FullSmVersion = 1202;
430 if (Bits[NVPTX::SM121] && FullSmVersion < 1210) FullSmVersion = 1210;
431 if (Bits[NVPTX::SM121a] && FullSmVersion < 1213) FullSmVersion = 1213;
432 if (Bits[NVPTX::SM121f] && FullSmVersion < 1212) FullSmVersion = 1212;
433}
434#endif // GET_SUBTARGETINFO_TARGET_DESC
435
436
437#ifdef GET_SUBTARGETINFO_HEADER
438#undef GET_SUBTARGETINFO_HEADER
439
440namespace llvm {
441class DFAPacketizer;
442namespace NVPTX_MC {
443unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID);
444} // end namespace NVPTX_MC
445
446struct NVPTXGenSubtargetInfo : public TargetSubtargetInfo {
447 explicit NVPTXGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
448public:
449 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
450 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const override;
451 DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
452};
453} // end namespace llvm
454
455#endif // GET_SUBTARGETINFO_HEADER
456
457
458#ifdef GET_SUBTARGETINFO_CTOR
459#undef GET_SUBTARGETINFO_CTOR
460
461#include "llvm/CodeGen/TargetSchedule.h"
462
463namespace llvm {
464extern const llvm::StringRef NVPTXNames[];
465extern const llvm::SubtargetFeatureKV NVPTXFeatureKV[];
466extern const llvm::SubtargetSubTypeKV NVPTXSubTypeKV[];
467extern const llvm::MCWriteProcResEntry NVPTXWriteProcResTable[];
468extern const llvm::MCWriteLatencyEntry NVPTXWriteLatencyTable[];
469extern const llvm::MCReadAdvanceEntry NVPTXReadAdvanceTable[];
470NVPTXGenSubtargetInfo::NVPTXGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
471 : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, ArrayRef(NVPTXNames, 36), ArrayRef(NVPTXFeatureKV, 66), ArrayRef(NVPTXSubTypeKV, 36),
472 NVPTXWriteProcResTable, NVPTXWriteLatencyTable, NVPTXReadAdvanceTable,
473 nullptr, nullptr, nullptr) {}
474
475unsigned NVPTXGenSubtargetInfo
476::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
477 report_fatal_error("Expected a variant SchedClass");
478} // NVPTXGenSubtargetInfo::resolveSchedClass
479
480unsigned NVPTXGenSubtargetInfo
481::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {
482 return NVPTX_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);
483} // NVPTXGenSubtargetInfo::resolveVariantSchedClass
484
485} // end namespace llvm
486
487#endif // GET_SUBTARGETINFO_CTOR
488
489
490#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
491#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
492
493#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
494
495
496#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
497#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
498
499#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
500
501