| 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
| 2 | |* *| |
| 3 | |* Machine Code Emitter *| |
| 4 | |* *| |
| 5 | |* Automatically generated file, do not edit! *| |
| 6 | |* *| |
| 7 | \*===----------------------------------------------------------------------===*/ |
| 8 | |
| 9 | uint64_t PPCMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI, |
| 10 | SmallVectorImpl<MCFixup> &Fixups, |
| 11 | const MCSubtargetInfo &STI) const { |
| 12 | static const uint64_t InstBits[] = { |
| 13 | UINT64_C(0), |
| 14 | UINT64_C(0), |
| 15 | UINT64_C(0), |
| 16 | UINT64_C(0), |
| 17 | UINT64_C(0), |
| 18 | UINT64_C(0), |
| 19 | UINT64_C(0), |
| 20 | UINT64_C(0), |
| 21 | UINT64_C(0), |
| 22 | UINT64_C(0), |
| 23 | UINT64_C(0), |
| 24 | UINT64_C(0), |
| 25 | UINT64_C(0), |
| 26 | UINT64_C(0), |
| 27 | UINT64_C(0), |
| 28 | UINT64_C(0), |
| 29 | UINT64_C(0), |
| 30 | UINT64_C(0), |
| 31 | UINT64_C(0), |
| 32 | UINT64_C(0), |
| 33 | UINT64_C(0), |
| 34 | UINT64_C(0), |
| 35 | UINT64_C(0), |
| 36 | UINT64_C(0), |
| 37 | UINT64_C(0), |
| 38 | UINT64_C(0), |
| 39 | UINT64_C(0), |
| 40 | UINT64_C(0), |
| 41 | UINT64_C(0), |
| 42 | UINT64_C(0), |
| 43 | UINT64_C(0), |
| 44 | UINT64_C(0), |
| 45 | UINT64_C(0), |
| 46 | UINT64_C(0), |
| 47 | UINT64_C(0), |
| 48 | UINT64_C(0), |
| 49 | UINT64_C(0), |
| 50 | UINT64_C(0), |
| 51 | UINT64_C(0), |
| 52 | UINT64_C(0), |
| 53 | UINT64_C(0), |
| 54 | UINT64_C(0), |
| 55 | UINT64_C(0), |
| 56 | UINT64_C(0), |
| 57 | UINT64_C(0), |
| 58 | UINT64_C(0), |
| 59 | UINT64_C(0), |
| 60 | UINT64_C(0), |
| 61 | UINT64_C(0), |
| 62 | UINT64_C(0), |
| 63 | UINT64_C(0), |
| 64 | UINT64_C(0), |
| 65 | UINT64_C(0), |
| 66 | UINT64_C(0), |
| 67 | UINT64_C(0), |
| 68 | UINT64_C(0), |
| 69 | UINT64_C(0), |
| 70 | UINT64_C(0), |
| 71 | UINT64_C(0), |
| 72 | UINT64_C(0), |
| 73 | UINT64_C(0), |
| 74 | UINT64_C(0), |
| 75 | UINT64_C(0), |
| 76 | UINT64_C(0), |
| 77 | UINT64_C(0), |
| 78 | UINT64_C(0), |
| 79 | UINT64_C(0), |
| 80 | UINT64_C(0), |
| 81 | UINT64_C(0), |
| 82 | UINT64_C(0), |
| 83 | UINT64_C(0), |
| 84 | UINT64_C(0), |
| 85 | UINT64_C(0), |
| 86 | UINT64_C(0), |
| 87 | UINT64_C(0), |
| 88 | UINT64_C(0), |
| 89 | UINT64_C(0), |
| 90 | UINT64_C(0), |
| 91 | UINT64_C(0), |
| 92 | UINT64_C(0), |
| 93 | UINT64_C(0), |
| 94 | UINT64_C(0), |
| 95 | UINT64_C(0), |
| 96 | UINT64_C(0), |
| 97 | UINT64_C(0), |
| 98 | UINT64_C(0), |
| 99 | UINT64_C(0), |
| 100 | UINT64_C(0), |
| 101 | UINT64_C(0), |
| 102 | UINT64_C(0), |
| 103 | UINT64_C(0), |
| 104 | UINT64_C(0), |
| 105 | UINT64_C(0), |
| 106 | UINT64_C(0), |
| 107 | UINT64_C(0), |
| 108 | UINT64_C(0), |
| 109 | UINT64_C(0), |
| 110 | UINT64_C(0), |
| 111 | UINT64_C(0), |
| 112 | UINT64_C(0), |
| 113 | UINT64_C(0), |
| 114 | UINT64_C(0), |
| 115 | UINT64_C(0), |
| 116 | UINT64_C(0), |
| 117 | UINT64_C(0), |
| 118 | UINT64_C(0), |
| 119 | UINT64_C(0), |
| 120 | UINT64_C(0), |
| 121 | UINT64_C(0), |
| 122 | UINT64_C(0), |
| 123 | UINT64_C(0), |
| 124 | UINT64_C(0), |
| 125 | UINT64_C(0), |
| 126 | UINT64_C(0), |
| 127 | UINT64_C(0), |
| 128 | UINT64_C(0), |
| 129 | UINT64_C(0), |
| 130 | UINT64_C(0), |
| 131 | UINT64_C(0), |
| 132 | UINT64_C(0), |
| 133 | UINT64_C(0), |
| 134 | UINT64_C(0), |
| 135 | UINT64_C(0), |
| 136 | UINT64_C(0), |
| 137 | UINT64_C(0), |
| 138 | UINT64_C(0), |
| 139 | UINT64_C(0), |
| 140 | UINT64_C(0), |
| 141 | UINT64_C(0), |
| 142 | UINT64_C(0), |
| 143 | UINT64_C(0), |
| 144 | UINT64_C(0), |
| 145 | UINT64_C(0), |
| 146 | UINT64_C(0), |
| 147 | UINT64_C(0), |
| 148 | UINT64_C(0), |
| 149 | UINT64_C(0), |
| 150 | UINT64_C(0), |
| 151 | UINT64_C(0), |
| 152 | UINT64_C(0), |
| 153 | UINT64_C(0), |
| 154 | UINT64_C(0), |
| 155 | UINT64_C(0), |
| 156 | UINT64_C(0), |
| 157 | UINT64_C(0), |
| 158 | UINT64_C(0), |
| 159 | UINT64_C(0), |
| 160 | UINT64_C(0), |
| 161 | UINT64_C(0), |
| 162 | UINT64_C(0), |
| 163 | UINT64_C(0), |
| 164 | UINT64_C(0), |
| 165 | UINT64_C(0), |
| 166 | UINT64_C(0), |
| 167 | UINT64_C(0), |
| 168 | UINT64_C(0), |
| 169 | UINT64_C(0), |
| 170 | UINT64_C(0), |
| 171 | UINT64_C(0), |
| 172 | UINT64_C(0), |
| 173 | UINT64_C(0), |
| 174 | UINT64_C(0), |
| 175 | UINT64_C(0), |
| 176 | UINT64_C(0), |
| 177 | UINT64_C(0), |
| 178 | UINT64_C(0), |
| 179 | UINT64_C(0), |
| 180 | UINT64_C(0), |
| 181 | UINT64_C(0), |
| 182 | UINT64_C(0), |
| 183 | UINT64_C(0), |
| 184 | UINT64_C(0), |
| 185 | UINT64_C(0), |
| 186 | UINT64_C(0), |
| 187 | UINT64_C(0), |
| 188 | UINT64_C(0), |
| 189 | UINT64_C(0), |
| 190 | UINT64_C(0), |
| 191 | UINT64_C(0), |
| 192 | UINT64_C(0), |
| 193 | UINT64_C(0), |
| 194 | UINT64_C(0), |
| 195 | UINT64_C(0), |
| 196 | UINT64_C(0), |
| 197 | UINT64_C(0), |
| 198 | UINT64_C(0), |
| 199 | UINT64_C(0), |
| 200 | UINT64_C(0), |
| 201 | UINT64_C(0), |
| 202 | UINT64_C(0), |
| 203 | UINT64_C(0), |
| 204 | UINT64_C(0), |
| 205 | UINT64_C(0), |
| 206 | UINT64_C(0), |
| 207 | UINT64_C(0), |
| 208 | UINT64_C(0), |
| 209 | UINT64_C(0), |
| 210 | UINT64_C(0), |
| 211 | UINT64_C(0), |
| 212 | UINT64_C(0), |
| 213 | UINT64_C(0), |
| 214 | UINT64_C(0), |
| 215 | UINT64_C(0), |
| 216 | UINT64_C(0), |
| 217 | UINT64_C(0), |
| 218 | UINT64_C(0), |
| 219 | UINT64_C(0), |
| 220 | UINT64_C(0), |
| 221 | UINT64_C(0), |
| 222 | UINT64_C(0), |
| 223 | UINT64_C(0), |
| 224 | UINT64_C(0), |
| 225 | UINT64_C(0), |
| 226 | UINT64_C(0), |
| 227 | UINT64_C(0), |
| 228 | UINT64_C(0), |
| 229 | UINT64_C(0), |
| 230 | UINT64_C(0), |
| 231 | UINT64_C(0), |
| 232 | UINT64_C(0), |
| 233 | UINT64_C(0), |
| 234 | UINT64_C(0), |
| 235 | UINT64_C(0), |
| 236 | UINT64_C(0), |
| 237 | UINT64_C(0), |
| 238 | UINT64_C(0), |
| 239 | UINT64_C(0), |
| 240 | UINT64_C(0), |
| 241 | UINT64_C(0), |
| 242 | UINT64_C(0), |
| 243 | UINT64_C(0), |
| 244 | UINT64_C(0), |
| 245 | UINT64_C(0), |
| 246 | UINT64_C(0), |
| 247 | UINT64_C(0), |
| 248 | UINT64_C(0), |
| 249 | UINT64_C(0), |
| 250 | UINT64_C(0), |
| 251 | UINT64_C(0), |
| 252 | UINT64_C(0), |
| 253 | UINT64_C(0), |
| 254 | UINT64_C(0), |
| 255 | UINT64_C(0), |
| 256 | UINT64_C(0), |
| 257 | UINT64_C(0), |
| 258 | UINT64_C(0), |
| 259 | UINT64_C(0), |
| 260 | UINT64_C(0), |
| 261 | UINT64_C(0), |
| 262 | UINT64_C(0), |
| 263 | UINT64_C(0), |
| 264 | UINT64_C(0), |
| 265 | UINT64_C(0), |
| 266 | UINT64_C(0), |
| 267 | UINT64_C(0), |
| 268 | UINT64_C(0), |
| 269 | UINT64_C(0), |
| 270 | UINT64_C(0), |
| 271 | UINT64_C(0), |
| 272 | UINT64_C(0), |
| 273 | UINT64_C(0), |
| 274 | UINT64_C(0), |
| 275 | UINT64_C(0), |
| 276 | UINT64_C(0), |
| 277 | UINT64_C(0), |
| 278 | UINT64_C(0), |
| 279 | UINT64_C(0), |
| 280 | UINT64_C(0), |
| 281 | UINT64_C(0), |
| 282 | UINT64_C(0), |
| 283 | UINT64_C(0), |
| 284 | UINT64_C(0), |
| 285 | UINT64_C(0), |
| 286 | UINT64_C(0), |
| 287 | UINT64_C(0), |
| 288 | UINT64_C(0), |
| 289 | UINT64_C(0), |
| 290 | UINT64_C(0), |
| 291 | UINT64_C(0), |
| 292 | UINT64_C(0), |
| 293 | UINT64_C(0), |
| 294 | UINT64_C(0), |
| 295 | UINT64_C(0), |
| 296 | UINT64_C(0), |
| 297 | UINT64_C(0), |
| 298 | UINT64_C(0), |
| 299 | UINT64_C(0), |
| 300 | UINT64_C(0), |
| 301 | UINT64_C(0), |
| 302 | UINT64_C(0), |
| 303 | UINT64_C(0), |
| 304 | UINT64_C(0), |
| 305 | UINT64_C(0), |
| 306 | UINT64_C(0), |
| 307 | UINT64_C(0), |
| 308 | UINT64_C(0), |
| 309 | UINT64_C(0), |
| 310 | UINT64_C(0), |
| 311 | UINT64_C(0), |
| 312 | UINT64_C(0), |
| 313 | UINT64_C(0), |
| 314 | UINT64_C(0), |
| 315 | UINT64_C(0), |
| 316 | UINT64_C(0), |
| 317 | UINT64_C(0), |
| 318 | UINT64_C(0), |
| 319 | UINT64_C(0), |
| 320 | UINT64_C(0), |
| 321 | UINT64_C(0), |
| 322 | UINT64_C(0), |
| 323 | UINT64_C(0), |
| 324 | UINT64_C(0), |
| 325 | UINT64_C(0), |
| 326 | UINT64_C(0), |
| 327 | UINT64_C(0), |
| 328 | UINT64_C(0), |
| 329 | UINT64_C(0), |
| 330 | UINT64_C(0), |
| 331 | UINT64_C(0), |
| 332 | UINT64_C(0), |
| 333 | UINT64_C(0), |
| 334 | UINT64_C(0), |
| 335 | UINT64_C(0), |
| 336 | UINT64_C(0), |
| 337 | UINT64_C(0), |
| 338 | UINT64_C(0), |
| 339 | UINT64_C(0), |
| 340 | UINT64_C(0), |
| 341 | UINT64_C(0), |
| 342 | UINT64_C(0), |
| 343 | UINT64_C(0), |
| 344 | UINT64_C(0), |
| 345 | UINT64_C(0), |
| 346 | UINT64_C(0), |
| 347 | UINT64_C(0), |
| 348 | UINT64_C(0), |
| 349 | UINT64_C(0), |
| 350 | UINT64_C(0), |
| 351 | UINT64_C(0), |
| 352 | UINT64_C(0), |
| 353 | UINT64_C(0), |
| 354 | UINT64_C(0), |
| 355 | UINT64_C(0), |
| 356 | UINT64_C(0), |
| 357 | UINT64_C(0), |
| 358 | UINT64_C(0), |
| 359 | UINT64_C(0), |
| 360 | UINT64_C(0), |
| 361 | UINT64_C(0), |
| 362 | UINT64_C(0), |
| 363 | UINT64_C(0), |
| 364 | UINT64_C(0), |
| 365 | UINT64_C(0), |
| 366 | UINT64_C(0), |
| 367 | UINT64_C(0), |
| 368 | UINT64_C(0), |
| 369 | UINT64_C(0), |
| 370 | UINT64_C(0), |
| 371 | UINT64_C(0), |
| 372 | UINT64_C(0), |
| 373 | UINT64_C(0), |
| 374 | UINT64_C(0), |
| 375 | UINT64_C(0), |
| 376 | UINT64_C(0), |
| 377 | UINT64_C(0), |
| 378 | UINT64_C(0), |
| 379 | UINT64_C(0), |
| 380 | UINT64_C(0), |
| 381 | UINT64_C(0), |
| 382 | UINT64_C(0), |
| 383 | UINT64_C(0), |
| 384 | UINT64_C(0), |
| 385 | UINT64_C(0), |
| 386 | UINT64_C(0), |
| 387 | UINT64_C(0), |
| 388 | UINT64_C(0), |
| 389 | UINT64_C(0), |
| 390 | UINT64_C(0), |
| 391 | UINT64_C(0), |
| 392 | UINT64_C(0), |
| 393 | UINT64_C(0), |
| 394 | UINT64_C(0), |
| 395 | UINT64_C(0), |
| 396 | UINT64_C(0), |
| 397 | UINT64_C(0), |
| 398 | UINT64_C(0), |
| 399 | UINT64_C(0), |
| 400 | UINT64_C(0), |
| 401 | UINT64_C(0), |
| 402 | UINT64_C(0), |
| 403 | UINT64_C(0), |
| 404 | UINT64_C(0), |
| 405 | UINT64_C(0), |
| 406 | UINT64_C(0), |
| 407 | UINT64_C(0), |
| 408 | UINT64_C(0), |
| 409 | UINT64_C(0), |
| 410 | UINT64_C(0), |
| 411 | UINT64_C(0), |
| 412 | UINT64_C(2080375316), // ADD4 |
| 413 | UINT64_C(2080376340), // ADD4O |
| 414 | UINT64_C(2080376341), // ADD4O_rec |
| 415 | UINT64_C(2080375316), // ADD4TLS |
| 416 | UINT64_C(2080375317), // ADD4_rec |
| 417 | UINT64_C(2080375316), // ADD8 |
| 418 | UINT64_C(2080376340), // ADD8O |
| 419 | UINT64_C(2080376341), // ADD8O_rec |
| 420 | UINT64_C(2080375316), // ADD8TLS |
| 421 | UINT64_C(2080375316), // ADD8TLS_ |
| 422 | UINT64_C(2080375317), // ADD8_rec |
| 423 | UINT64_C(2080374804), // ADDC |
| 424 | UINT64_C(2080374804), // ADDC8 |
| 425 | UINT64_C(2080375828), // ADDC8O |
| 426 | UINT64_C(2080375829), // ADDC8O_rec |
| 427 | UINT64_C(2080374805), // ADDC8_rec |
| 428 | UINT64_C(2080375828), // ADDCO |
| 429 | UINT64_C(2080375829), // ADDCO_rec |
| 430 | UINT64_C(2080374805), // ADDC_rec |
| 431 | UINT64_C(2080375060), // ADDE |
| 432 | UINT64_C(2080375060), // ADDE8 |
| 433 | UINT64_C(2080376084), // ADDE8O |
| 434 | UINT64_C(2080376085), // ADDE8O_rec |
| 435 | UINT64_C(2080375061), // ADDE8_rec |
| 436 | UINT64_C(2080376084), // ADDEO |
| 437 | UINT64_C(2080376085), // ADDEO_rec |
| 438 | UINT64_C(2080375124), // ADDEX |
| 439 | UINT64_C(2080375124), // ADDEX8 |
| 440 | UINT64_C(2080375061), // ADDE_rec |
| 441 | UINT64_C(2080374932), // ADDG6S |
| 442 | UINT64_C(2080374932), // ADDG6S8 |
| 443 | UINT64_C(939524096), // ADDI |
| 444 | UINT64_C(939524096), // ADDI8 |
| 445 | UINT64_C(805306368), // ADDIC |
| 446 | UINT64_C(805306368), // ADDIC8 |
| 447 | UINT64_C(872415232), // ADDIC_rec |
| 448 | UINT64_C(1006632960), // ADDIS |
| 449 | UINT64_C(1006632960), // ADDIS8 |
| 450 | UINT64_C(0), // ADDISdtprelHA |
| 451 | UINT64_C(0), // ADDISdtprelHA32 |
| 452 | UINT64_C(0), // ADDISgotTprelHA |
| 453 | UINT64_C(0), // ADDIStlsgdHA |
| 454 | UINT64_C(0), // ADDIStlsldHA |
| 455 | UINT64_C(0), // ADDIStocHA |
| 456 | UINT64_C(0), // ADDIStocHA8 |
| 457 | UINT64_C(0), // ADDIdtprelL |
| 458 | UINT64_C(0), // ADDIdtprelL32 |
| 459 | UINT64_C(0), // ADDItlsgdL |
| 460 | UINT64_C(0), // ADDItlsgdL32 |
| 461 | UINT64_C(0), // ADDItlsgdLADDR |
| 462 | UINT64_C(0), // ADDItlsgdLADDR32 |
| 463 | UINT64_C(0), // ADDItlsldL |
| 464 | UINT64_C(0), // ADDItlsldL32 |
| 465 | UINT64_C(0), // ADDItlsldLADDR |
| 466 | UINT64_C(0), // ADDItlsldLADDR32 |
| 467 | UINT64_C(0), // ADDItoc |
| 468 | UINT64_C(0), // ADDItoc8 |
| 469 | UINT64_C(0), // ADDItocL |
| 470 | UINT64_C(0), // ADDItocL8 |
| 471 | UINT64_C(2080375252), // ADDME |
| 472 | UINT64_C(2080375252), // ADDME8 |
| 473 | UINT64_C(2080376276), // ADDME8O |
| 474 | UINT64_C(2080376277), // ADDME8O_rec |
| 475 | UINT64_C(2080375253), // ADDME8_rec |
| 476 | UINT64_C(2080376276), // ADDMEO |
| 477 | UINT64_C(2080376277), // ADDMEO_rec |
| 478 | UINT64_C(2080375253), // ADDME_rec |
| 479 | UINT64_C(1275068420), // ADDPCIS |
| 480 | UINT64_C(2080375188), // ADDZE |
| 481 | UINT64_C(2080375188), // ADDZE8 |
| 482 | UINT64_C(2080376212), // ADDZE8O |
| 483 | UINT64_C(2080376213), // ADDZE8O_rec |
| 484 | UINT64_C(2080375189), // ADDZE8_rec |
| 485 | UINT64_C(2080376212), // ADDZEO |
| 486 | UINT64_C(2080376213), // ADDZEO_rec |
| 487 | UINT64_C(2080375189), // ADDZE_rec |
| 488 | UINT64_C(0), // ADJCALLSTACKDOWN |
| 489 | UINT64_C(0), // ADJCALLSTACKUP |
| 490 | UINT64_C(2080374840), // AND |
| 491 | UINT64_C(2080374840), // AND8 |
| 492 | UINT64_C(2080374841), // AND8_rec |
| 493 | UINT64_C(2080374904), // ANDC |
| 494 | UINT64_C(2080374904), // ANDC8 |
| 495 | UINT64_C(2080374905), // ANDC8_rec |
| 496 | UINT64_C(2080374905), // ANDC_rec |
| 497 | UINT64_C(1879048192), // ANDI8_rec |
| 498 | UINT64_C(1946157056), // ANDIS8_rec |
| 499 | UINT64_C(1946157056), // ANDIS_rec |
| 500 | UINT64_C(1879048192), // ANDI_rec |
| 501 | UINT64_C(0), // ANDI_rec_1_EQ_BIT |
| 502 | UINT64_C(0), // ANDI_rec_1_EQ_BIT8 |
| 503 | UINT64_C(0), // ANDI_rec_1_GT_BIT |
| 504 | UINT64_C(0), // ANDI_rec_1_GT_BIT8 |
| 505 | UINT64_C(2080374841), // AND_rec |
| 506 | UINT64_C(0), // ATOMIC_CMP_SWAP_I16 |
| 507 | UINT64_C(0), // ATOMIC_CMP_SWAP_I32 |
| 508 | UINT64_C(0), // ATOMIC_CMP_SWAP_I64 |
| 509 | UINT64_C(0), // ATOMIC_CMP_SWAP_I8 |
| 510 | UINT64_C(0), // ATOMIC_LOAD_ADD_I16 |
| 511 | UINT64_C(0), // ATOMIC_LOAD_ADD_I32 |
| 512 | UINT64_C(0), // ATOMIC_LOAD_ADD_I64 |
| 513 | UINT64_C(0), // ATOMIC_LOAD_ADD_I8 |
| 514 | UINT64_C(0), // ATOMIC_LOAD_AND_I16 |
| 515 | UINT64_C(0), // ATOMIC_LOAD_AND_I32 |
| 516 | UINT64_C(0), // ATOMIC_LOAD_AND_I64 |
| 517 | UINT64_C(0), // ATOMIC_LOAD_AND_I8 |
| 518 | UINT64_C(0), // ATOMIC_LOAD_MAX_I16 |
| 519 | UINT64_C(0), // ATOMIC_LOAD_MAX_I32 |
| 520 | UINT64_C(0), // ATOMIC_LOAD_MAX_I64 |
| 521 | UINT64_C(0), // ATOMIC_LOAD_MAX_I8 |
| 522 | UINT64_C(0), // ATOMIC_LOAD_MIN_I16 |
| 523 | UINT64_C(0), // ATOMIC_LOAD_MIN_I32 |
| 524 | UINT64_C(0), // ATOMIC_LOAD_MIN_I64 |
| 525 | UINT64_C(0), // ATOMIC_LOAD_MIN_I8 |
| 526 | UINT64_C(0), // ATOMIC_LOAD_NAND_I16 |
| 527 | UINT64_C(0), // ATOMIC_LOAD_NAND_I32 |
| 528 | UINT64_C(0), // ATOMIC_LOAD_NAND_I64 |
| 529 | UINT64_C(0), // ATOMIC_LOAD_NAND_I8 |
| 530 | UINT64_C(0), // ATOMIC_LOAD_OR_I16 |
| 531 | UINT64_C(0), // ATOMIC_LOAD_OR_I32 |
| 532 | UINT64_C(0), // ATOMIC_LOAD_OR_I64 |
| 533 | UINT64_C(0), // ATOMIC_LOAD_OR_I8 |
| 534 | UINT64_C(0), // ATOMIC_LOAD_SUB_I16 |
| 535 | UINT64_C(0), // ATOMIC_LOAD_SUB_I32 |
| 536 | UINT64_C(0), // ATOMIC_LOAD_SUB_I64 |
| 537 | UINT64_C(0), // ATOMIC_LOAD_SUB_I8 |
| 538 | UINT64_C(0), // ATOMIC_LOAD_UMAX_I16 |
| 539 | UINT64_C(0), // ATOMIC_LOAD_UMAX_I32 |
| 540 | UINT64_C(0), // ATOMIC_LOAD_UMAX_I64 |
| 541 | UINT64_C(0), // ATOMIC_LOAD_UMAX_I8 |
| 542 | UINT64_C(0), // ATOMIC_LOAD_UMIN_I16 |
| 543 | UINT64_C(0), // ATOMIC_LOAD_UMIN_I32 |
| 544 | UINT64_C(0), // ATOMIC_LOAD_UMIN_I64 |
| 545 | UINT64_C(0), // ATOMIC_LOAD_UMIN_I8 |
| 546 | UINT64_C(0), // ATOMIC_LOAD_XOR_I16 |
| 547 | UINT64_C(0), // ATOMIC_LOAD_XOR_I32 |
| 548 | UINT64_C(0), // ATOMIC_LOAD_XOR_I64 |
| 549 | UINT64_C(0), // ATOMIC_LOAD_XOR_I8 |
| 550 | UINT64_C(0), // ATOMIC_SWAP_I16 |
| 551 | UINT64_C(0), // ATOMIC_SWAP_I32 |
| 552 | UINT64_C(0), // ATOMIC_SWAP_I64 |
| 553 | UINT64_C(0), // ATOMIC_SWAP_I8 |
| 554 | UINT64_C(512), // ATTN |
| 555 | UINT64_C(1207959552), // B |
| 556 | UINT64_C(1207959554), // BA |
| 557 | UINT64_C(1098907648), // BC |
| 558 | UINT64_C(1073741824), // BCC |
| 559 | UINT64_C(1073741826), // BCCA |
| 560 | UINT64_C(1275069472), // BCCCTR |
| 561 | UINT64_C(1275069472), // BCCCTR8 |
| 562 | UINT64_C(1275069473), // BCCCTRL |
| 563 | UINT64_C(1275069473), // BCCCTRL8 |
| 564 | UINT64_C(1073741825), // BCCL |
| 565 | UINT64_C(1073741827), // BCCLA |
| 566 | UINT64_C(1275068448), // BCCLR |
| 567 | UINT64_C(1275068449), // BCCLRL |
| 568 | UINT64_C(1300235296), // BCCTR |
| 569 | UINT64_C(1300235296), // BCCTR8 |
| 570 | UINT64_C(1283458080), // BCCTR8n |
| 571 | UINT64_C(1300235297), // BCCTRL |
| 572 | UINT64_C(1300235297), // BCCTRL8 |
| 573 | UINT64_C(1283458081), // BCCTRL8n |
| 574 | UINT64_C(1283458081), // BCCTRLn |
| 575 | UINT64_C(1283458080), // BCCTRn |
| 576 | UINT64_C(268436481), // BCDADD_rec |
| 577 | UINT64_C(268895617), // BCDCFN_rec |
| 578 | UINT64_C(268567937), // BCDCFSQ_rec |
| 579 | UINT64_C(268830081), // BCDCFZ_rec |
| 580 | UINT64_C(268436289), // BCDCPSGN_rec |
| 581 | UINT64_C(268764545), // BCDCTN_rec |
| 582 | UINT64_C(268436865), // BCDCTSQ_rec |
| 583 | UINT64_C(268699009), // BCDCTZ_rec |
| 584 | UINT64_C(270468481), // BCDSETSGN_rec |
| 585 | UINT64_C(268436929), // BCDSR_rec |
| 586 | UINT64_C(268436545), // BCDSUB_rec |
| 587 | UINT64_C(268436673), // BCDS_rec |
| 588 | UINT64_C(268436737), // BCDTRUNC_rec |
| 589 | UINT64_C(268436609), // BCDUS_rec |
| 590 | UINT64_C(268436801), // BCDUTRUNC_rec |
| 591 | UINT64_C(1098907649), // BCL |
| 592 | UINT64_C(1300234272), // BCLR |
| 593 | UINT64_C(1300234273), // BCLRL |
| 594 | UINT64_C(1283457057), // BCLRLn |
| 595 | UINT64_C(1283457056), // BCLRn |
| 596 | UINT64_C(1117716481), // BCLalways |
| 597 | UINT64_C(1082130433), // BCLn |
| 598 | UINT64_C(1317012512), // BCTR |
| 599 | UINT64_C(1317012512), // BCTR8 |
| 600 | UINT64_C(1317012513), // BCTRL |
| 601 | UINT64_C(1317012513), // BCTRL8 |
| 602 | UINT64_C(5656525675654283264), // BCTRL8_LDinto_toc |
| 603 | UINT64_C(5656525675654283264), // BCTRL8_LDinto_toc_RM |
| 604 | UINT64_C(1317012513), // BCTRL8_RM |
| 605 | UINT64_C(5656525673909452800), // BCTRL_LWZinto_toc |
| 606 | UINT64_C(5656525673909452800), // BCTRL_LWZinto_toc_RM |
| 607 | UINT64_C(1317012513), // BCTRL_RM |
| 608 | UINT64_C(1082130432), // BCn |
| 609 | UINT64_C(1107296256), // BDNZ |
| 610 | UINT64_C(1107296256), // BDNZ8 |
| 611 | UINT64_C(1107296258), // BDNZA |
| 612 | UINT64_C(1124073474), // BDNZAm |
| 613 | UINT64_C(1126170626), // BDNZAp |
| 614 | UINT64_C(1107296257), // BDNZL |
| 615 | UINT64_C(1107296259), // BDNZLA |
| 616 | UINT64_C(1124073475), // BDNZLAm |
| 617 | UINT64_C(1126170627), // BDNZLAp |
| 618 | UINT64_C(1308622880), // BDNZLR |
| 619 | UINT64_C(1308622880), // BDNZLR8 |
| 620 | UINT64_C(1308622881), // BDNZLRL |
| 621 | UINT64_C(1325400097), // BDNZLRLm |
| 622 | UINT64_C(1327497249), // BDNZLRLp |
| 623 | UINT64_C(1325400096), // BDNZLRm |
| 624 | UINT64_C(1327497248), // BDNZLRp |
| 625 | UINT64_C(1124073473), // BDNZLm |
| 626 | UINT64_C(1126170625), // BDNZLp |
| 627 | UINT64_C(1124073472), // BDNZm |
| 628 | UINT64_C(1126170624), // BDNZp |
| 629 | UINT64_C(1111490560), // BDZ |
| 630 | UINT64_C(1111490560), // BDZ8 |
| 631 | UINT64_C(1111490562), // BDZA |
| 632 | UINT64_C(1128267778), // BDZAm |
| 633 | UINT64_C(1130364930), // BDZAp |
| 634 | UINT64_C(1111490561), // BDZL |
| 635 | UINT64_C(1111490563), // BDZLA |
| 636 | UINT64_C(1128267779), // BDZLAm |
| 637 | UINT64_C(1130364931), // BDZLAp |
| 638 | UINT64_C(1312817184), // BDZLR |
| 639 | UINT64_C(1312817184), // BDZLR8 |
| 640 | UINT64_C(1312817185), // BDZLRL |
| 641 | UINT64_C(1329594401), // BDZLRLm |
| 642 | UINT64_C(1331691553), // BDZLRLp |
| 643 | UINT64_C(1329594400), // BDZLRm |
| 644 | UINT64_C(1331691552), // BDZLRp |
| 645 | UINT64_C(1128267777), // BDZLm |
| 646 | UINT64_C(1130364929), // BDZLp |
| 647 | UINT64_C(1128267776), // BDZm |
| 648 | UINT64_C(1130364928), // BDZp |
| 649 | UINT64_C(1207959553), // BL |
| 650 | UINT64_C(1207959553), // BL8 |
| 651 | UINT64_C(5188146776636391424), // BL8_NOP |
| 652 | UINT64_C(5188146776636391424), // BL8_NOP_RM |
| 653 | UINT64_C(5188146776636391424), // BL8_NOP_TLS |
| 654 | UINT64_C(1207959553), // BL8_NOTOC |
| 655 | UINT64_C(1207959553), // BL8_NOTOC_RM |
| 656 | UINT64_C(1207959553), // BL8_NOTOC_TLS |
| 657 | UINT64_C(1207959553), // BL8_RM |
| 658 | UINT64_C(1207959553), // BL8_TLS |
| 659 | UINT64_C(1207959553), // BL8_TLS_ |
| 660 | UINT64_C(1207959555), // BLA |
| 661 | UINT64_C(1207959555), // BLA8 |
| 662 | UINT64_C(5188146785226326016), // BLA8_NOP |
| 663 | UINT64_C(5188146785226326016), // BLA8_NOP_RM |
| 664 | UINT64_C(1207959555), // BLA8_RM |
| 665 | UINT64_C(1207959555), // BLA_RM |
| 666 | UINT64_C(1317011488), // BLR |
| 667 | UINT64_C(1317011488), // BLR8 |
| 668 | UINT64_C(1317011489), // BLRL |
| 669 | UINT64_C(5188146776636391424), // BL_NOP |
| 670 | UINT64_C(5188146776636391424), // BL_NOP_RM |
| 671 | UINT64_C(1207959553), // BL_RM |
| 672 | UINT64_C(1207959553), // BL_TLS |
| 673 | UINT64_C(2080375288), // BPERMD |
| 674 | UINT64_C(2080375158), // BRD |
| 675 | UINT64_C(2080375222), // BRH |
| 676 | UINT64_C(2080375222), // BRH8 |
| 677 | UINT64_C(268435983), // BRINC |
| 678 | UINT64_C(2080375094), // BRW |
| 679 | UINT64_C(2080375094), // BRW8 |
| 680 | UINT64_C(2080375412), // CBCDTD |
| 681 | UINT64_C(2080375412), // CBCDTD8 |
| 682 | UINT64_C(2080375348), // CDTBCD |
| 683 | UINT64_C(2080375348), // CDTBCD8 |
| 684 | UINT64_C(2080375224), // CFUGED |
| 685 | UINT64_C(2080375644), // CLRBHRB |
| 686 | UINT64_C(2080375800), // CMPB |
| 687 | UINT64_C(2080375800), // CMPB8 |
| 688 | UINT64_C(2082471936), // CMPD |
| 689 | UINT64_C(740294656), // CMPDI |
| 690 | UINT64_C(2080375232), // CMPEQB |
| 691 | UINT64_C(2082472000), // CMPLD |
| 692 | UINT64_C(673185792), // CMPLDI |
| 693 | UINT64_C(2080374848), // CMPLW |
| 694 | UINT64_C(671088640), // CMPLWI |
| 695 | UINT64_C(2080375168), // CMPRB |
| 696 | UINT64_C(2080375168), // CMPRB8 |
| 697 | UINT64_C(2080374784), // CMPW |
| 698 | UINT64_C(738197504), // CMPWI |
| 699 | UINT64_C(2080374900), // CNTLZD |
| 700 | UINT64_C(2080374902), // CNTLZDM |
| 701 | UINT64_C(2080374901), // CNTLZD_rec |
| 702 | UINT64_C(2080374836), // CNTLZW |
| 703 | UINT64_C(2080374836), // CNTLZW8 |
| 704 | UINT64_C(2080374837), // CNTLZW8_rec |
| 705 | UINT64_C(2080374837), // CNTLZW_rec |
| 706 | UINT64_C(2080375924), // CNTTZD |
| 707 | UINT64_C(2080375926), // CNTTZDM |
| 708 | UINT64_C(2080375925), // CNTTZD_rec |
| 709 | UINT64_C(2080375860), // CNTTZW |
| 710 | UINT64_C(2080375860), // CNTTZW8 |
| 711 | UINT64_C(2080375861), // CNTTZW8_rec |
| 712 | UINT64_C(2080375861), // CNTTZW_rec |
| 713 | UINT64_C(2080376460), // CP_ABORT |
| 714 | UINT64_C(2082473484), // CP_COPY |
| 715 | UINT64_C(2082473484), // CP_COPY8 |
| 716 | UINT64_C(2080376589), // CP_PASTE8_rec |
| 717 | UINT64_C(2080376589), // CP_PASTE_rec |
| 718 | UINT64_C(1288057410), // CR6SET |
| 719 | UINT64_C(1288057218), // CR6UNSET |
| 720 | UINT64_C(1275068930), // CRAND |
| 721 | UINT64_C(1275068674), // CRANDC |
| 722 | UINT64_C(1275068994), // CREQV |
| 723 | UINT64_C(1275068866), // CRNAND |
| 724 | UINT64_C(1275068482), // CRNOR |
| 725 | UINT64_C(1275068482), // CRNOT |
| 726 | UINT64_C(1275069314), // CROR |
| 727 | UINT64_C(1275069250), // CRORC |
| 728 | UINT64_C(1275068994), // CRSET |
| 729 | UINT64_C(1275068802), // CRUNSET |
| 730 | UINT64_C(1275068802), // CRXOR |
| 731 | UINT64_C(1073741824), // CTRL_DEP |
| 732 | UINT64_C(3959422980), // DADD |
| 733 | UINT64_C(4227858436), // DADDQ |
| 734 | UINT64_C(4227858437), // DADDQ_rec |
| 735 | UINT64_C(3959422981), // DADD_rec |
| 736 | UINT64_C(2080376294), // DARN |
| 737 | UINT64_C(2080376300), // DCBA |
| 738 | UINT64_C(2080374956), // DCBF |
| 739 | UINT64_C(2080375038), // DCBFEP |
| 740 | UINT64_C(2080375724), // DCBI |
| 741 | UINT64_C(2080374892), // DCBST |
| 742 | UINT64_C(2080374910), // DCBSTEP |
| 743 | UINT64_C(2080375340), // DCBT |
| 744 | UINT64_C(2080375422), // DCBTEP |
| 745 | UINT64_C(2080375276), // DCBTST |
| 746 | UINT64_C(2080375294), // DCBTSTEP |
| 747 | UINT64_C(2080376812), // DCBZ |
| 748 | UINT64_C(2080376830), // DCBZEP |
| 749 | UINT64_C(2082473964), // DCBZL |
| 750 | UINT64_C(2082473982), // DCBZLEP |
| 751 | UINT64_C(2080375692), // DCCCI |
| 752 | UINT64_C(3959424580), // DCFFIX |
| 753 | UINT64_C(4227860036), // DCFFIXQ |
| 754 | UINT64_C(4227860420), // DCFFIXQQ |
| 755 | UINT64_C(4227860037), // DCFFIXQ_rec |
| 756 | UINT64_C(3959424581), // DCFFIX_rec |
| 757 | UINT64_C(3959423236), // DCMPO |
| 758 | UINT64_C(4227858692), // DCMPOQ |
| 759 | UINT64_C(3959424260), // DCMPU |
| 760 | UINT64_C(4227859716), // DCMPUQ |
| 761 | UINT64_C(3959423492), // DCTDP |
| 762 | UINT64_C(3959423493), // DCTDP_rec |
| 763 | UINT64_C(3959423556), // DCTFIX |
| 764 | UINT64_C(4227859012), // DCTFIXQ |
| 765 | UINT64_C(4227925956), // DCTFIXQQ |
| 766 | UINT64_C(4227859013), // DCTFIXQ_rec |
| 767 | UINT64_C(3959423557), // DCTFIX_rec |
| 768 | UINT64_C(4227858948), // DCTQPQ |
| 769 | UINT64_C(4227858949), // DCTQPQ_rec |
| 770 | UINT64_C(3959423620), // DDEDPD |
| 771 | UINT64_C(4227859076), // DDEDPDQ |
| 772 | UINT64_C(4227859077), // DDEDPDQ_rec |
| 773 | UINT64_C(3959423621), // DDEDPD_rec |
| 774 | UINT64_C(3959424068), // DDIV |
| 775 | UINT64_C(4227859524), // DDIVQ |
| 776 | UINT64_C(4227859525), // DDIVQ_rec |
| 777 | UINT64_C(3959424069), // DDIV_rec |
| 778 | UINT64_C(3959424644), // DENBCD |
| 779 | UINT64_C(4227860100), // DENBCDQ |
| 780 | UINT64_C(4227860101), // DENBCDQ_rec |
| 781 | UINT64_C(3959424645), // DENBCD_rec |
| 782 | UINT64_C(3959424708), // DIEX |
| 783 | UINT64_C(4227860164), // DIEXQ |
| 784 | UINT64_C(4227860165), // DIEXQ_rec |
| 785 | UINT64_C(3959424709), // DIEX_rec |
| 786 | UINT64_C(2080375762), // DIVD |
| 787 | UINT64_C(2080375634), // DIVDE |
| 788 | UINT64_C(2080376658), // DIVDEO |
| 789 | UINT64_C(2080376659), // DIVDEO_rec |
| 790 | UINT64_C(2080375570), // DIVDEU |
| 791 | UINT64_C(2080376594), // DIVDEUO |
| 792 | UINT64_C(2080376595), // DIVDEUO_rec |
| 793 | UINT64_C(2080375571), // DIVDEU_rec |
| 794 | UINT64_C(2080375635), // DIVDE_rec |
| 795 | UINT64_C(2080376786), // DIVDO |
| 796 | UINT64_C(2080376787), // DIVDO_rec |
| 797 | UINT64_C(2080375698), // DIVDU |
| 798 | UINT64_C(2080376722), // DIVDUO |
| 799 | UINT64_C(2080376723), // DIVDUO_rec |
| 800 | UINT64_C(2080375699), // DIVDU_rec |
| 801 | UINT64_C(2080375763), // DIVD_rec |
| 802 | UINT64_C(2080375766), // DIVW |
| 803 | UINT64_C(2080375638), // DIVWE |
| 804 | UINT64_C(2080376662), // DIVWEO |
| 805 | UINT64_C(2080376663), // DIVWEO_rec |
| 806 | UINT64_C(2080375574), // DIVWEU |
| 807 | UINT64_C(2080376598), // DIVWEUO |
| 808 | UINT64_C(2080376599), // DIVWEUO_rec |
| 809 | UINT64_C(2080375575), // DIVWEU_rec |
| 810 | UINT64_C(2080375639), // DIVWE_rec |
| 811 | UINT64_C(2080376790), // DIVWO |
| 812 | UINT64_C(2080376791), // DIVWO_rec |
| 813 | UINT64_C(2080375702), // DIVWU |
| 814 | UINT64_C(2080376726), // DIVWUO |
| 815 | UINT64_C(2080376727), // DIVWUO_rec |
| 816 | UINT64_C(2080375703), // DIVWU_rec |
| 817 | UINT64_C(2080375767), // DIVW_rec |
| 818 | UINT64_C(2080768354), // DMMR |
| 819 | UINT64_C(2080506210), // DMSETDMRZ |
| 820 | UINT64_C(2081292642), // DMSHA2HASH |
| 821 | UINT64_C(2081358178), // DMSHA3HASH |
| 822 | UINT64_C(3959423044), // DMUL |
| 823 | UINT64_C(4227858500), // DMULQ |
| 824 | UINT64_C(4227858501), // DMULQ_rec |
| 825 | UINT64_C(3959423045), // DMUL_rec |
| 826 | UINT64_C(2080833890), // DMXOR |
| 827 | UINT64_C(3959423704), // DMXVBF16GERX2 |
| 828 | UINT64_C(3959424848), // DMXVBF16GERX2NN |
| 829 | UINT64_C(3959423896), // DMXVBF16GERX2NP |
| 830 | UINT64_C(3959424408), // DMXVBF16GERX2PN |
| 831 | UINT64_C(3959423568), // DMXVBF16GERX2PP |
| 832 | UINT64_C(3959423512), // DMXVF16GERX2 |
| 833 | UINT64_C(3959424592), // DMXVF16GERX2NN |
| 834 | UINT64_C(3959423640), // DMXVF16GERX2NP |
| 835 | UINT64_C(3959424152), // DMXVF16GERX2PN |
| 836 | UINT64_C(3959423504), // DMXVF16GERX2PP |
| 837 | UINT64_C(3959423064), // DMXVI8GERX4 |
| 838 | UINT64_C(3959423056), // DMXVI8GERX4PP |
| 839 | UINT64_C(3959423760), // DMXVI8GERX4SPP |
| 840 | UINT64_C(4026533776), // DMXXEXTFDMR256 |
| 841 | UINT64_C(4026533648), // DMXXEXTFDMR512 |
| 842 | UINT64_C(4026599184), // DMXXEXTFDMR512_HI |
| 843 | UINT64_C(4026533780), // DMXXINSTDMR256 |
| 844 | UINT64_C(4026533712), // DMXXINSTDMR512 |
| 845 | UINT64_C(4026599248), // DMXXINSTDMR512_HI |
| 846 | UINT64_C(2080571746), // DMXXSETACCZ |
| 847 | UINT64_C(4026533524), // DMXXSHAPAD |
| 848 | UINT64_C(3959422982), // DQUA |
| 849 | UINT64_C(3959423110), // DQUAI |
| 850 | UINT64_C(4227858566), // DQUAIQ |
| 851 | UINT64_C(4227858567), // DQUAIQ_rec |
| 852 | UINT64_C(3959423111), // DQUAI_rec |
| 853 | UINT64_C(4227858438), // DQUAQ |
| 854 | UINT64_C(4227858439), // DQUAQ_rec |
| 855 | UINT64_C(3959422983), // DQUA_rec |
| 856 | UINT64_C(4227859972), // DRDPQ |
| 857 | UINT64_C(4227859973), // DRDPQ_rec |
| 858 | UINT64_C(3959423430), // DRINTN |
| 859 | UINT64_C(4227858886), // DRINTNQ |
| 860 | UINT64_C(4227858887), // DRINTNQ_rec |
| 861 | UINT64_C(3959423431), // DRINTN_rec |
| 862 | UINT64_C(3959423174), // DRINTX |
| 863 | UINT64_C(4227858630), // DRINTXQ |
| 864 | UINT64_C(4227858631), // DRINTXQ_rec |
| 865 | UINT64_C(3959423175), // DRINTX_rec |
| 866 | UINT64_C(3959423046), // DRRND |
| 867 | UINT64_C(4227858502), // DRRNDQ |
| 868 | UINT64_C(4227858503), // DRRNDQ_rec |
| 869 | UINT64_C(3959423047), // DRRND_rec |
| 870 | UINT64_C(3959424516), // DRSP |
| 871 | UINT64_C(3959424517), // DRSP_rec |
| 872 | UINT64_C(3959423108), // DSCLI |
| 873 | UINT64_C(4227858564), // DSCLIQ |
| 874 | UINT64_C(4227858565), // DSCLIQ_rec |
| 875 | UINT64_C(3959423109), // DSCLI_rec |
| 876 | UINT64_C(3959423172), // DSCRI |
| 877 | UINT64_C(4227858628), // DSCRIQ |
| 878 | UINT64_C(4227858629), // DSCRIQ_rec |
| 879 | UINT64_C(3959423173), // DSCRI_rec |
| 880 | UINT64_C(2080376428), // DSS |
| 881 | UINT64_C(2113930860), // DSSALL |
| 882 | UINT64_C(2080375468), // DST |
| 883 | UINT64_C(2080375468), // DST64 |
| 884 | UINT64_C(2080375532), // DSTST |
| 885 | UINT64_C(2080375532), // DSTST64 |
| 886 | UINT64_C(2113929964), // DSTSTT |
| 887 | UINT64_C(2113929964), // DSTSTT64 |
| 888 | UINT64_C(2113929900), // DSTT |
| 889 | UINT64_C(2113929900), // DSTT64 |
| 890 | UINT64_C(3959424004), // DSUB |
| 891 | UINT64_C(4227859460), // DSUBQ |
| 892 | UINT64_C(4227859461), // DSUBQ_rec |
| 893 | UINT64_C(3959424005), // DSUB_rec |
| 894 | UINT64_C(3959423364), // DTSTDC |
| 895 | UINT64_C(4227858820), // DTSTDCQ |
| 896 | UINT64_C(3959423428), // DTSTDG |
| 897 | UINT64_C(4227858884), // DTSTDGQ |
| 898 | UINT64_C(3959423300), // DTSTEX |
| 899 | UINT64_C(4227858756), // DTSTEXQ |
| 900 | UINT64_C(3959424324), // DTSTSF |
| 901 | UINT64_C(3959424326), // DTSTSFI |
| 902 | UINT64_C(4227859782), // DTSTSFIQ |
| 903 | UINT64_C(4227859780), // DTSTSFQ |
| 904 | UINT64_C(3959423684), // DXEX |
| 905 | UINT64_C(4227859140), // DXEXQ |
| 906 | UINT64_C(4227859141), // DXEXQ_rec |
| 907 | UINT64_C(3959423685), // DXEX_rec |
| 908 | UINT64_C(0), // DYNALLOC |
| 909 | UINT64_C(0), // DYNALLOC8 |
| 910 | UINT64_C(0), // DYNAREAOFFSET |
| 911 | UINT64_C(0), // DYNAREAOFFSET8 |
| 912 | UINT64_C(0), // DecreaseCTR8loop |
| 913 | UINT64_C(0), // DecreaseCTRloop |
| 914 | UINT64_C(268436196), // EFDABS |
| 915 | UINT64_C(268436192), // EFDADD |
| 916 | UINT64_C(268436207), // EFDCFS |
| 917 | UINT64_C(268436211), // EFDCFSF |
| 918 | UINT64_C(268436209), // EFDCFSI |
| 919 | UINT64_C(268436195), // EFDCFSID |
| 920 | UINT64_C(268436210), // EFDCFUF |
| 921 | UINT64_C(268436208), // EFDCFUI |
| 922 | UINT64_C(268436194), // EFDCFUID |
| 923 | UINT64_C(268436206), // EFDCMPEQ |
| 924 | UINT64_C(268436204), // EFDCMPGT |
| 925 | UINT64_C(268436205), // EFDCMPLT |
| 926 | UINT64_C(268436215), // EFDCTSF |
| 927 | UINT64_C(268436213), // EFDCTSI |
| 928 | UINT64_C(268436203), // EFDCTSIDZ |
| 929 | UINT64_C(268436218), // EFDCTSIZ |
| 930 | UINT64_C(268436214), // EFDCTUF |
| 931 | UINT64_C(268436212), // EFDCTUI |
| 932 | UINT64_C(268436202), // EFDCTUIDZ |
| 933 | UINT64_C(268436216), // EFDCTUIZ |
| 934 | UINT64_C(268436201), // EFDDIV |
| 935 | UINT64_C(268436200), // EFDMUL |
| 936 | UINT64_C(268436197), // EFDNABS |
| 937 | UINT64_C(268436198), // EFDNEG |
| 938 | UINT64_C(268436193), // EFDSUB |
| 939 | UINT64_C(268436222), // EFDTSTEQ |
| 940 | UINT64_C(268436220), // EFDTSTGT |
| 941 | UINT64_C(268436221), // EFDTSTLT |
| 942 | UINT64_C(268436164), // EFSABS |
| 943 | UINT64_C(268436160), // EFSADD |
| 944 | UINT64_C(268436175), // EFSCFD |
| 945 | UINT64_C(268436179), // EFSCFSF |
| 946 | UINT64_C(268436177), // EFSCFSI |
| 947 | UINT64_C(268436178), // EFSCFUF |
| 948 | UINT64_C(268436176), // EFSCFUI |
| 949 | UINT64_C(268436174), // EFSCMPEQ |
| 950 | UINT64_C(268436172), // EFSCMPGT |
| 951 | UINT64_C(268436173), // EFSCMPLT |
| 952 | UINT64_C(268436183), // EFSCTSF |
| 953 | UINT64_C(268436181), // EFSCTSI |
| 954 | UINT64_C(268436186), // EFSCTSIZ |
| 955 | UINT64_C(268436182), // EFSCTUF |
| 956 | UINT64_C(268436180), // EFSCTUI |
| 957 | UINT64_C(268436184), // EFSCTUIZ |
| 958 | UINT64_C(268436169), // EFSDIV |
| 959 | UINT64_C(268436168), // EFSMUL |
| 960 | UINT64_C(268436165), // EFSNABS |
| 961 | UINT64_C(268436166), // EFSNEG |
| 962 | UINT64_C(268436161), // EFSSUB |
| 963 | UINT64_C(268436190), // EFSTSTEQ |
| 964 | UINT64_C(268436188), // EFSTSTGT |
| 965 | UINT64_C(268436189), // EFSTSTLT |
| 966 | UINT64_C(0), // EH_SjLj_LongJmp32 |
| 967 | UINT64_C(0), // EH_SjLj_LongJmp64 |
| 968 | UINT64_C(0), // EH_SjLj_SetJmp32 |
| 969 | UINT64_C(0), // EH_SjLj_SetJmp64 |
| 970 | UINT64_C(0), // EH_SjLj_Setup |
| 971 | UINT64_C(2080375352), // EQV |
| 972 | UINT64_C(2080375352), // EQV8 |
| 973 | UINT64_C(2080375353), // EQV8_rec |
| 974 | UINT64_C(2080375353), // EQV_rec |
| 975 | UINT64_C(268435976), // EVABS |
| 976 | UINT64_C(268435970), // EVADDIW |
| 977 | UINT64_C(268436681), // EVADDSMIAAW |
| 978 | UINT64_C(268436673), // EVADDSSIAAW |
| 979 | UINT64_C(268436680), // EVADDUMIAAW |
| 980 | UINT64_C(268436672), // EVADDUSIAAW |
| 981 | UINT64_C(268435968), // EVADDW |
| 982 | UINT64_C(268435985), // EVAND |
| 983 | UINT64_C(268435986), // EVANDC |
| 984 | UINT64_C(268436020), // EVCMPEQ |
| 985 | UINT64_C(268436017), // EVCMPGTS |
| 986 | UINT64_C(268436016), // EVCMPGTU |
| 987 | UINT64_C(268436019), // EVCMPLTS |
| 988 | UINT64_C(268436018), // EVCMPLTU |
| 989 | UINT64_C(268435982), // EVCNTLSW |
| 990 | UINT64_C(268435981), // EVCNTLZW |
| 991 | UINT64_C(268436678), // EVDIVWS |
| 992 | UINT64_C(268436679), // EVDIVWU |
| 993 | UINT64_C(268435993), // EVEQV |
| 994 | UINT64_C(268435978), // EVEXTSB |
| 995 | UINT64_C(268435979), // EVEXTSH |
| 996 | UINT64_C(268436100), // EVFSABS |
| 997 | UINT64_C(268436096), // EVFSADD |
| 998 | UINT64_C(268436115), // EVFSCFSF |
| 999 | UINT64_C(268436113), // EVFSCFSI |
| 1000 | UINT64_C(268436114), // EVFSCFUF |
| 1001 | UINT64_C(268436106), // EVFSCFUI |
| 1002 | UINT64_C(268436110), // EVFSCMPEQ |
| 1003 | UINT64_C(268436108), // EVFSCMPGT |
| 1004 | UINT64_C(268436109), // EVFSCMPLT |
| 1005 | UINT64_C(268436119), // EVFSCTSF |
| 1006 | UINT64_C(268436117), // EVFSCTSI |
| 1007 | UINT64_C(268436122), // EVFSCTSIZ |
| 1008 | UINT64_C(268436118), // EVFSCTUF |
| 1009 | UINT64_C(268436116), // EVFSCTUI |
| 1010 | UINT64_C(268436120), // EVFSCTUIZ |
| 1011 | UINT64_C(268436105), // EVFSDIV |
| 1012 | UINT64_C(268436104), // EVFSMUL |
| 1013 | UINT64_C(268436101), // EVFSNABS |
| 1014 | UINT64_C(268436102), // EVFSNEG |
| 1015 | UINT64_C(268436097), // EVFSSUB |
| 1016 | UINT64_C(268436126), // EVFSTSTEQ |
| 1017 | UINT64_C(268436124), // EVFSTSTGT |
| 1018 | UINT64_C(268436125), // EVFSTSTLT |
| 1019 | UINT64_C(268436225), // EVLDD |
| 1020 | UINT64_C(268436224), // EVLDDX |
| 1021 | UINT64_C(268436229), // EVLDH |
| 1022 | UINT64_C(268436228), // EVLDHX |
| 1023 | UINT64_C(268436227), // EVLDW |
| 1024 | UINT64_C(268436226), // EVLDWX |
| 1025 | UINT64_C(268436233), // EVLHHESPLAT |
| 1026 | UINT64_C(268436232), // EVLHHESPLATX |
| 1027 | UINT64_C(268436239), // EVLHHOSSPLAT |
| 1028 | UINT64_C(268436238), // EVLHHOSSPLATX |
| 1029 | UINT64_C(268436237), // EVLHHOUSPLAT |
| 1030 | UINT64_C(268436236), // EVLHHOUSPLATX |
| 1031 | UINT64_C(268436241), // EVLWHE |
| 1032 | UINT64_C(268436240), // EVLWHEX |
| 1033 | UINT64_C(268436247), // EVLWHOS |
| 1034 | UINT64_C(268436246), // EVLWHOSX |
| 1035 | UINT64_C(268436245), // EVLWHOU |
| 1036 | UINT64_C(268436244), // EVLWHOUX |
| 1037 | UINT64_C(268436253), // EVLWHSPLAT |
| 1038 | UINT64_C(268436252), // EVLWHSPLATX |
| 1039 | UINT64_C(268436249), // EVLWWSPLAT |
| 1040 | UINT64_C(268436248), // EVLWWSPLATX |
| 1041 | UINT64_C(268436012), // EVMERGEHI |
| 1042 | UINT64_C(268436014), // EVMERGEHILO |
| 1043 | UINT64_C(268436013), // EVMERGELO |
| 1044 | UINT64_C(268436015), // EVMERGELOHI |
| 1045 | UINT64_C(268436779), // EVMHEGSMFAA |
| 1046 | UINT64_C(268436907), // EVMHEGSMFAN |
| 1047 | UINT64_C(268436777), // EVMHEGSMIAA |
| 1048 | UINT64_C(268436905), // EVMHEGSMIAN |
| 1049 | UINT64_C(268436776), // EVMHEGUMIAA |
| 1050 | UINT64_C(268436904), // EVMHEGUMIAN |
| 1051 | UINT64_C(268436491), // EVMHESMF |
| 1052 | UINT64_C(268436523), // EVMHESMFA |
| 1053 | UINT64_C(268436747), // EVMHESMFAAW |
| 1054 | UINT64_C(268436875), // EVMHESMFANW |
| 1055 | UINT64_C(268436489), // EVMHESMI |
| 1056 | UINT64_C(268436521), // EVMHESMIA |
| 1057 | UINT64_C(268436745), // EVMHESMIAAW |
| 1058 | UINT64_C(268436873), // EVMHESMIANW |
| 1059 | UINT64_C(268436483), // EVMHESSF |
| 1060 | UINT64_C(268436515), // EVMHESSFA |
| 1061 | UINT64_C(268436739), // EVMHESSFAAW |
| 1062 | UINT64_C(268436867), // EVMHESSFANW |
| 1063 | UINT64_C(268436737), // EVMHESSIAAW |
| 1064 | UINT64_C(268436865), // EVMHESSIANW |
| 1065 | UINT64_C(268436488), // EVMHEUMI |
| 1066 | UINT64_C(268436520), // EVMHEUMIA |
| 1067 | UINT64_C(268436744), // EVMHEUMIAAW |
| 1068 | UINT64_C(268436872), // EVMHEUMIANW |
| 1069 | UINT64_C(268436736), // EVMHEUSIAAW |
| 1070 | UINT64_C(268436864), // EVMHEUSIANW |
| 1071 | UINT64_C(268436783), // EVMHOGSMFAA |
| 1072 | UINT64_C(268436911), // EVMHOGSMFAN |
| 1073 | UINT64_C(268436781), // EVMHOGSMIAA |
| 1074 | UINT64_C(268436909), // EVMHOGSMIAN |
| 1075 | UINT64_C(268436780), // EVMHOGUMIAA |
| 1076 | UINT64_C(268436908), // EVMHOGUMIAN |
| 1077 | UINT64_C(268436495), // EVMHOSMF |
| 1078 | UINT64_C(268436527), // EVMHOSMFA |
| 1079 | UINT64_C(268436751), // EVMHOSMFAAW |
| 1080 | UINT64_C(268436879), // EVMHOSMFANW |
| 1081 | UINT64_C(268436493), // EVMHOSMI |
| 1082 | UINT64_C(268436525), // EVMHOSMIA |
| 1083 | UINT64_C(268436749), // EVMHOSMIAAW |
| 1084 | UINT64_C(268436877), // EVMHOSMIANW |
| 1085 | UINT64_C(268436487), // EVMHOSSF |
| 1086 | UINT64_C(268436519), // EVMHOSSFA |
| 1087 | UINT64_C(268436743), // EVMHOSSFAAW |
| 1088 | UINT64_C(268436871), // EVMHOSSFANW |
| 1089 | UINT64_C(268436741), // EVMHOSSIAAW |
| 1090 | UINT64_C(268436869), // EVMHOSSIANW |
| 1091 | UINT64_C(268436492), // EVMHOUMI |
| 1092 | UINT64_C(268436524), // EVMHOUMIA |
| 1093 | UINT64_C(268436748), // EVMHOUMIAAW |
| 1094 | UINT64_C(268436876), // EVMHOUMIANW |
| 1095 | UINT64_C(268436740), // EVMHOUSIAAW |
| 1096 | UINT64_C(268436868), // EVMHOUSIANW |
| 1097 | UINT64_C(268436676), // EVMRA |
| 1098 | UINT64_C(268436559), // EVMWHSMF |
| 1099 | UINT64_C(268436591), // EVMWHSMFA |
| 1100 | UINT64_C(268436557), // EVMWHSMI |
| 1101 | UINT64_C(268436589), // EVMWHSMIA |
| 1102 | UINT64_C(268436551), // EVMWHSSF |
| 1103 | UINT64_C(268436583), // EVMWHSSFA |
| 1104 | UINT64_C(268436556), // EVMWHUMI |
| 1105 | UINT64_C(268436588), // EVMWHUMIA |
| 1106 | UINT64_C(268436809), // EVMWLSMIAAW |
| 1107 | UINT64_C(268436937), // EVMWLSMIANW |
| 1108 | UINT64_C(268436801), // EVMWLSSIAAW |
| 1109 | UINT64_C(268436929), // EVMWLSSIANW |
| 1110 | UINT64_C(268436552), // EVMWLUMI |
| 1111 | UINT64_C(268436584), // EVMWLUMIA |
| 1112 | UINT64_C(268436808), // EVMWLUMIAAW |
| 1113 | UINT64_C(268436936), // EVMWLUMIANW |
| 1114 | UINT64_C(268436800), // EVMWLUSIAAW |
| 1115 | UINT64_C(268436928), // EVMWLUSIANW |
| 1116 | UINT64_C(268436571), // EVMWSMF |
| 1117 | UINT64_C(268436603), // EVMWSMFA |
| 1118 | UINT64_C(268436827), // EVMWSMFAA |
| 1119 | UINT64_C(268436955), // EVMWSMFAN |
| 1120 | UINT64_C(268436569), // EVMWSMI |
| 1121 | UINT64_C(268436601), // EVMWSMIA |
| 1122 | UINT64_C(268436825), // EVMWSMIAA |
| 1123 | UINT64_C(268436953), // EVMWSMIAN |
| 1124 | UINT64_C(268436563), // EVMWSSF |
| 1125 | UINT64_C(268436595), // EVMWSSFA |
| 1126 | UINT64_C(268436819), // EVMWSSFAA |
| 1127 | UINT64_C(268436947), // EVMWSSFAN |
| 1128 | UINT64_C(268436568), // EVMWUMI |
| 1129 | UINT64_C(268436600), // EVMWUMIA |
| 1130 | UINT64_C(268436824), // EVMWUMIAA |
| 1131 | UINT64_C(268436952), // EVMWUMIAN |
| 1132 | UINT64_C(268435998), // EVNAND |
| 1133 | UINT64_C(268435977), // EVNEG |
| 1134 | UINT64_C(268435992), // EVNOR |
| 1135 | UINT64_C(268435991), // EVOR |
| 1136 | UINT64_C(268435995), // EVORC |
| 1137 | UINT64_C(268436008), // EVRLW |
| 1138 | UINT64_C(268436010), // EVRLWI |
| 1139 | UINT64_C(268435980), // EVRNDW |
| 1140 | UINT64_C(268436088), // EVSEL |
| 1141 | UINT64_C(268436004), // EVSLW |
| 1142 | UINT64_C(268436006), // EVSLWI |
| 1143 | UINT64_C(268436011), // EVSPLATFI |
| 1144 | UINT64_C(268436009), // EVSPLATI |
| 1145 | UINT64_C(268436003), // EVSRWIS |
| 1146 | UINT64_C(268436002), // EVSRWIU |
| 1147 | UINT64_C(268436001), // EVSRWS |
| 1148 | UINT64_C(268436000), // EVSRWU |
| 1149 | UINT64_C(268436257), // EVSTDD |
| 1150 | UINT64_C(268436256), // EVSTDDX |
| 1151 | UINT64_C(268436261), // EVSTDH |
| 1152 | UINT64_C(268436260), // EVSTDHX |
| 1153 | UINT64_C(268436259), // EVSTDW |
| 1154 | UINT64_C(268436258), // EVSTDWX |
| 1155 | UINT64_C(268436273), // EVSTWHE |
| 1156 | UINT64_C(268436272), // EVSTWHEX |
| 1157 | UINT64_C(268436277), // EVSTWHO |
| 1158 | UINT64_C(268436276), // EVSTWHOX |
| 1159 | UINT64_C(268436281), // EVSTWWE |
| 1160 | UINT64_C(268436280), // EVSTWWEX |
| 1161 | UINT64_C(268436285), // EVSTWWO |
| 1162 | UINT64_C(268436284), // EVSTWWOX |
| 1163 | UINT64_C(268436683), // EVSUBFSMIAAW |
| 1164 | UINT64_C(268436675), // EVSUBFSSIAAW |
| 1165 | UINT64_C(268436682), // EVSUBFUMIAAW |
| 1166 | UINT64_C(268436674), // EVSUBFUSIAAW |
| 1167 | UINT64_C(268435972), // EVSUBFW |
| 1168 | UINT64_C(268435974), // EVSUBIFW |
| 1169 | UINT64_C(268435990), // EVXOR |
| 1170 | UINT64_C(2080376692), // EXTSB |
| 1171 | UINT64_C(2080376692), // EXTSB8 |
| 1172 | UINT64_C(2080376692), // EXTSB8_32_64 |
| 1173 | UINT64_C(2080376693), // EXTSB8_rec |
| 1174 | UINT64_C(2080376693), // EXTSB_rec |
| 1175 | UINT64_C(2080376628), // EXTSH |
| 1176 | UINT64_C(2080376628), // EXTSH8 |
| 1177 | UINT64_C(2080376628), // EXTSH8_32_64 |
| 1178 | UINT64_C(2080376629), // EXTSH8_rec |
| 1179 | UINT64_C(2080376629), // EXTSH_rec |
| 1180 | UINT64_C(2080376756), // EXTSW |
| 1181 | UINT64_C(2080376564), // EXTSWSLI |
| 1182 | UINT64_C(2080376564), // EXTSWSLI_32_64 |
| 1183 | UINT64_C(2080376565), // EXTSWSLI_32_64_rec |
| 1184 | UINT64_C(2080376565), // EXTSWSLI_rec |
| 1185 | UINT64_C(2080376756), // EXTSW_32 |
| 1186 | UINT64_C(2080376756), // EXTSW_32_64 |
| 1187 | UINT64_C(2080376757), // EXTSW_32_64_rec |
| 1188 | UINT64_C(2080376757), // EXTSW_rec |
| 1189 | UINT64_C(2080376492), // EnforceIEIO |
| 1190 | UINT64_C(4227858960), // FABSD |
| 1191 | UINT64_C(4227858961), // FABSD_rec |
| 1192 | UINT64_C(4227858960), // FABSS |
| 1193 | UINT64_C(4227858961), // FABSS_rec |
| 1194 | UINT64_C(4227858474), // FADD |
| 1195 | UINT64_C(3959423018), // FADDS |
| 1196 | UINT64_C(3959423019), // FADDS_rec |
| 1197 | UINT64_C(4227858475), // FADD_rec |
| 1198 | UINT64_C(0), // FADDrtz |
| 1199 | UINT64_C(4227860124), // FCFID |
| 1200 | UINT64_C(3959424668), // FCFIDS |
| 1201 | UINT64_C(3959424669), // FCFIDS_rec |
| 1202 | UINT64_C(4227860380), // FCFIDU |
| 1203 | UINT64_C(3959424924), // FCFIDUS |
| 1204 | UINT64_C(3959424925), // FCFIDUS_rec |
| 1205 | UINT64_C(4227860381), // FCFIDU_rec |
| 1206 | UINT64_C(4227860125), // FCFID_rec |
| 1207 | UINT64_C(4227858496), // FCMPOD |
| 1208 | UINT64_C(4227858496), // FCMPOS |
| 1209 | UINT64_C(4227858432), // FCMPUD |
| 1210 | UINT64_C(4227858432), // FCMPUS |
| 1211 | UINT64_C(4227858448), // FCPSGND |
| 1212 | UINT64_C(4227858449), // FCPSGND_rec |
| 1213 | UINT64_C(4227858448), // FCPSGNS |
| 1214 | UINT64_C(4227858449), // FCPSGNS_rec |
| 1215 | UINT64_C(4227860060), // FCTID |
| 1216 | UINT64_C(4227860316), // FCTIDU |
| 1217 | UINT64_C(4227860318), // FCTIDUZ |
| 1218 | UINT64_C(4227860319), // FCTIDUZ_rec |
| 1219 | UINT64_C(4227860317), // FCTIDU_rec |
| 1220 | UINT64_C(4227860062), // FCTIDZ |
| 1221 | UINT64_C(4227860063), // FCTIDZ_rec |
| 1222 | UINT64_C(4227860061), // FCTID_rec |
| 1223 | UINT64_C(4227858460), // FCTIW |
| 1224 | UINT64_C(4227858716), // FCTIWU |
| 1225 | UINT64_C(4227858718), // FCTIWUZ |
| 1226 | UINT64_C(4227858719), // FCTIWUZ_rec |
| 1227 | UINT64_C(4227858717), // FCTIWU_rec |
| 1228 | UINT64_C(4227858462), // FCTIWZ |
| 1229 | UINT64_C(4227858463), // FCTIWZ_rec |
| 1230 | UINT64_C(4227858461), // FCTIW_rec |
| 1231 | UINT64_C(4227858468), // FDIV |
| 1232 | UINT64_C(3959423012), // FDIVS |
| 1233 | UINT64_C(3959423013), // FDIVS_rec |
| 1234 | UINT64_C(4227858469), // FDIV_rec |
| 1235 | UINT64_C(0), // FENCE |
| 1236 | UINT64_C(4227858490), // FMADD |
| 1237 | UINT64_C(3959423034), // FMADDS |
| 1238 | UINT64_C(3959423035), // FMADDS_rec |
| 1239 | UINT64_C(4227858491), // FMADD_rec |
| 1240 | UINT64_C(4227858576), // FMR |
| 1241 | UINT64_C(4227858577), // FMR_rec |
| 1242 | UINT64_C(4227858488), // FMSUB |
| 1243 | UINT64_C(3959423032), // FMSUBS |
| 1244 | UINT64_C(3959423033), // FMSUBS_rec |
| 1245 | UINT64_C(4227858489), // FMSUB_rec |
| 1246 | UINT64_C(4227858482), // FMUL |
| 1247 | UINT64_C(3959423026), // FMULS |
| 1248 | UINT64_C(3959423027), // FMULS_rec |
| 1249 | UINT64_C(4227858483), // FMUL_rec |
| 1250 | UINT64_C(4227858704), // FNABSD |
| 1251 | UINT64_C(4227858705), // FNABSD_rec |
| 1252 | UINT64_C(4227858704), // FNABSS |
| 1253 | UINT64_C(4227858705), // FNABSS_rec |
| 1254 | UINT64_C(4227858512), // FNEGD |
| 1255 | UINT64_C(4227858513), // FNEGD_rec |
| 1256 | UINT64_C(4227858512), // FNEGS |
| 1257 | UINT64_C(4227858513), // FNEGS_rec |
| 1258 | UINT64_C(4227858494), // FNMADD |
| 1259 | UINT64_C(3959423038), // FNMADDS |
| 1260 | UINT64_C(3959423039), // FNMADDS_rec |
| 1261 | UINT64_C(4227858495), // FNMADD_rec |
| 1262 | UINT64_C(4227858492), // FNMSUB |
| 1263 | UINT64_C(3959423036), // FNMSUBS |
| 1264 | UINT64_C(3959423037), // FNMSUBS_rec |
| 1265 | UINT64_C(4227858493), // FNMSUB_rec |
| 1266 | UINT64_C(4227858480), // FRE |
| 1267 | UINT64_C(3959423024), // FRES |
| 1268 | UINT64_C(3959423025), // FRES_rec |
| 1269 | UINT64_C(4227858481), // FRE_rec |
| 1270 | UINT64_C(4227859408), // FRIMD |
| 1271 | UINT64_C(4227859409), // FRIMD_rec |
| 1272 | UINT64_C(4227859408), // FRIMS |
| 1273 | UINT64_C(4227859409), // FRIMS_rec |
| 1274 | UINT64_C(4227859216), // FRIND |
| 1275 | UINT64_C(4227859217), // FRIND_rec |
| 1276 | UINT64_C(4227859216), // FRINS |
| 1277 | UINT64_C(4227859217), // FRINS_rec |
| 1278 | UINT64_C(4227859344), // FRIPD |
| 1279 | UINT64_C(4227859345), // FRIPD_rec |
| 1280 | UINT64_C(4227859344), // FRIPS |
| 1281 | UINT64_C(4227859345), // FRIPS_rec |
| 1282 | UINT64_C(4227859280), // FRIZD |
| 1283 | UINT64_C(4227859281), // FRIZD_rec |
| 1284 | UINT64_C(4227859280), // FRIZS |
| 1285 | UINT64_C(4227859281), // FRIZS_rec |
| 1286 | UINT64_C(4227858456), // FRSP |
| 1287 | UINT64_C(4227858457), // FRSP_rec |
| 1288 | UINT64_C(4227858484), // FRSQRTE |
| 1289 | UINT64_C(3959423028), // FRSQRTES |
| 1290 | UINT64_C(3959423029), // FRSQRTES_rec |
| 1291 | UINT64_C(4227858485), // FRSQRTE_rec |
| 1292 | UINT64_C(4227858478), // FSELD |
| 1293 | UINT64_C(4227858479), // FSELD_rec |
| 1294 | UINT64_C(4227858478), // FSELS |
| 1295 | UINT64_C(4227858479), // FSELS_rec |
| 1296 | UINT64_C(4227858476), // FSQRT |
| 1297 | UINT64_C(3959423020), // FSQRTS |
| 1298 | UINT64_C(3959423021), // FSQRTS_rec |
| 1299 | UINT64_C(4227858477), // FSQRT_rec |
| 1300 | UINT64_C(4227858472), // FSUB |
| 1301 | UINT64_C(3959423016), // FSUBS |
| 1302 | UINT64_C(3959423017), // FSUBS_rec |
| 1303 | UINT64_C(4227858473), // FSUB_rec |
| 1304 | UINT64_C(4227858688), // FTDIV |
| 1305 | UINT64_C(4227858752), // FTSQRT |
| 1306 | UINT64_C(0), // GETtlsADDR |
| 1307 | UINT64_C(0), // GETtlsADDR32 |
| 1308 | UINT64_C(0), // GETtlsADDR32AIX |
| 1309 | UINT64_C(0), // GETtlsADDR64AIX |
| 1310 | UINT64_C(0), // GETtlsADDRPCREL |
| 1311 | UINT64_C(0), // GETtlsMOD32AIX |
| 1312 | UINT64_C(0), // GETtlsMOD64AIX |
| 1313 | UINT64_C(0), // GETtlsTpointer32AIX |
| 1314 | UINT64_C(0), // GETtlsldADDR |
| 1315 | UINT64_C(0), // GETtlsldADDR32 |
| 1316 | UINT64_C(0), // GETtlsldADDRPCREL |
| 1317 | UINT64_C(2080376292), // HASHCHK |
| 1318 | UINT64_C(2080376292), // HASHCHK8 |
| 1319 | UINT64_C(2080376164), // HASHCHKP |
| 1320 | UINT64_C(2080376164), // HASHCHKP8 |
| 1321 | UINT64_C(2080376228), // HASHST |
| 1322 | UINT64_C(2080376228), // HASHST8 |
| 1323 | UINT64_C(2080376100), // HASHSTP |
| 1324 | UINT64_C(2080376100), // HASHSTP8 |
| 1325 | UINT64_C(1275068964), // HRFID |
| 1326 | UINT64_C(2080376748), // ICBI |
| 1327 | UINT64_C(2080376766), // ICBIEP |
| 1328 | UINT64_C(2080375244), // ICBLC |
| 1329 | UINT64_C(2080375180), // ICBLQ |
| 1330 | UINT64_C(2080374828), // ICBT |
| 1331 | UINT64_C(2080375756), // ICBTLS |
| 1332 | UINT64_C(2080376716), // ICCCI |
| 1333 | UINT64_C(2080374814), // ISEL |
| 1334 | UINT64_C(2080374814), // ISEL8 |
| 1335 | UINT64_C(1275068716), // ISYNC |
| 1336 | UINT64_C(939524096), // LA |
| 1337 | UINT64_C(939524096), // LA8 |
| 1338 | UINT64_C(2080374888), // LBARX |
| 1339 | UINT64_C(2080374889), // LBARXL |
| 1340 | UINT64_C(2080374974), // LBEPX |
| 1341 | UINT64_C(2281701376), // LBZ |
| 1342 | UINT64_C(2281701376), // LBZ8 |
| 1343 | UINT64_C(2080376490), // LBZCIX |
| 1344 | UINT64_C(2348810240), // LBZU |
| 1345 | UINT64_C(2348810240), // LBZU8 |
| 1346 | UINT64_C(2080375022), // LBZUX |
| 1347 | UINT64_C(2080375022), // LBZUX8 |
| 1348 | UINT64_C(2080374958), // LBZX |
| 1349 | UINT64_C(2080374958), // LBZX8 |
| 1350 | UINT64_C(2080374958), // LBZXTLS |
| 1351 | UINT64_C(2080374958), // LBZXTLS_ |
| 1352 | UINT64_C(2080374958), // LBZXTLS_32 |
| 1353 | UINT64_C(3892314112), // LD |
| 1354 | UINT64_C(2080374952), // LDARX |
| 1355 | UINT64_C(2080374953), // LDARXL |
| 1356 | UINT64_C(2080376012), // LDAT |
| 1357 | UINT64_C(2080375848), // LDBRX |
| 1358 | UINT64_C(2080376554), // LDCIX |
| 1359 | UINT64_C(3892314113), // LDU |
| 1360 | UINT64_C(2080374890), // LDUX |
| 1361 | UINT64_C(2080374826), // LDX |
| 1362 | UINT64_C(2080374826), // LDXTLS |
| 1363 | UINT64_C(2080374826), // LDXTLS_ |
| 1364 | UINT64_C(0), // LDgotTprelL |
| 1365 | UINT64_C(0), // LDgotTprelL32 |
| 1366 | UINT64_C(0), // LDtoc |
| 1367 | UINT64_C(0), // LDtocBA |
| 1368 | UINT64_C(0), // LDtocCPT |
| 1369 | UINT64_C(0), // LDtocJTI |
| 1370 | UINT64_C(0), // LDtocL |
| 1371 | UINT64_C(3355443200), // LFD |
| 1372 | UINT64_C(2080375998), // LFDEPX |
| 1373 | UINT64_C(3422552064), // LFDU |
| 1374 | UINT64_C(2080376046), // LFDUX |
| 1375 | UINT64_C(2080375982), // LFDX |
| 1376 | UINT64_C(2080375982), // LFDXTLS |
| 1377 | UINT64_C(2080375982), // LFDXTLS_ |
| 1378 | UINT64_C(2080376494), // LFIWAX |
| 1379 | UINT64_C(2080376558), // LFIWZX |
| 1380 | UINT64_C(3221225472), // LFS |
| 1381 | UINT64_C(3288334336), // LFSU |
| 1382 | UINT64_C(2080375918), // LFSUX |
| 1383 | UINT64_C(2080375854), // LFSX |
| 1384 | UINT64_C(2080375854), // LFSXTLS |
| 1385 | UINT64_C(2080375854), // LFSXTLS_ |
| 1386 | UINT64_C(2818572288), // LHA |
| 1387 | UINT64_C(2818572288), // LHA8 |
| 1388 | UINT64_C(2080375016), // LHARX |
| 1389 | UINT64_C(2080375017), // LHARXL |
| 1390 | UINT64_C(2885681152), // LHAU |
| 1391 | UINT64_C(2885681152), // LHAU8 |
| 1392 | UINT64_C(2080375534), // LHAUX |
| 1393 | UINT64_C(2080375534), // LHAUX8 |
| 1394 | UINT64_C(2080375470), // LHAX |
| 1395 | UINT64_C(2080375470), // LHAX8 |
| 1396 | UINT64_C(2080375470), // LHAXTLS |
| 1397 | UINT64_C(2080375470), // LHAXTLS_ |
| 1398 | UINT64_C(2080375470), // LHAXTLS_32 |
| 1399 | UINT64_C(2080376364), // LHBRX |
| 1400 | UINT64_C(2080376364), // LHBRX8 |
| 1401 | UINT64_C(2080375358), // LHEPX |
| 1402 | UINT64_C(2684354560), // LHZ |
| 1403 | UINT64_C(2684354560), // LHZ8 |
| 1404 | UINT64_C(2080376426), // LHZCIX |
| 1405 | UINT64_C(2751463424), // LHZU |
| 1406 | UINT64_C(2751463424), // LHZU8 |
| 1407 | UINT64_C(2080375406), // LHZUX |
| 1408 | UINT64_C(2080375406), // LHZUX8 |
| 1409 | UINT64_C(2080375342), // LHZX |
| 1410 | UINT64_C(2080375342), // LHZX8 |
| 1411 | UINT64_C(2080375342), // LHZXTLS |
| 1412 | UINT64_C(2080375342), // LHZXTLS_ |
| 1413 | UINT64_C(2080375342), // LHZXTLS_32 |
| 1414 | UINT64_C(939524096), // LI |
| 1415 | UINT64_C(939524096), // LI8 |
| 1416 | UINT64_C(1006632960), // LIS |
| 1417 | UINT64_C(1006632960), // LIS8 |
| 1418 | UINT64_C(3087007744), // LMW |
| 1419 | UINT64_C(3758096384), // LQ |
| 1420 | UINT64_C(2080375336), // LQARX |
| 1421 | UINT64_C(2080375337), // LQARXL |
| 1422 | UINT64_C(0), // LQX_PSEUDO |
| 1423 | UINT64_C(2080375978), // LSWI |
| 1424 | UINT64_C(2080374798), // LVEBX |
| 1425 | UINT64_C(2080374862), // LVEHX |
| 1426 | UINT64_C(2080374926), // LVEWX |
| 1427 | UINT64_C(2080374796), // LVSL |
| 1428 | UINT64_C(2080374860), // LVSR |
| 1429 | UINT64_C(2080374990), // LVX |
| 1430 | UINT64_C(2080375502), // LVXL |
| 1431 | UINT64_C(3892314114), // LWA |
| 1432 | UINT64_C(2080374824), // LWARX |
| 1433 | UINT64_C(2080374825), // LWARXL |
| 1434 | UINT64_C(2080375948), // LWAT |
| 1435 | UINT64_C(2080375530), // LWAUX |
| 1436 | UINT64_C(2080375466), // LWAX |
| 1437 | UINT64_C(2080375466), // LWAXTLS |
| 1438 | UINT64_C(2080375466), // LWAXTLS_ |
| 1439 | UINT64_C(2080375466), // LWAXTLS_32 |
| 1440 | UINT64_C(2080375466), // LWAX_32 |
| 1441 | UINT64_C(3892314114), // LWA_32 |
| 1442 | UINT64_C(2080375852), // LWBRX |
| 1443 | UINT64_C(2080375852), // LWBRX8 |
| 1444 | UINT64_C(2080374846), // LWEPX |
| 1445 | UINT64_C(2147483648), // LWZ |
| 1446 | UINT64_C(2147483648), // LWZ8 |
| 1447 | UINT64_C(2080376362), // LWZCIX |
| 1448 | UINT64_C(2214592512), // LWZU |
| 1449 | UINT64_C(2214592512), // LWZU8 |
| 1450 | UINT64_C(2080374894), // LWZUX |
| 1451 | UINT64_C(2080374894), // LWZUX8 |
| 1452 | UINT64_C(2080374830), // LWZX |
| 1453 | UINT64_C(2080374830), // LWZX8 |
| 1454 | UINT64_C(2080374830), // LWZXTLS |
| 1455 | UINT64_C(2080374830), // LWZXTLS_ |
| 1456 | UINT64_C(2080374830), // LWZXTLS_32 |
| 1457 | UINT64_C(0), // LWZtoc |
| 1458 | UINT64_C(0), // LWZtocL |
| 1459 | UINT64_C(3825205250), // LXSD |
| 1460 | UINT64_C(2080375960), // LXSDX |
| 1461 | UINT64_C(2080376346), // LXSIBZX |
| 1462 | UINT64_C(2080376410), // LXSIHZX |
| 1463 | UINT64_C(2080374936), // LXSIWAX |
| 1464 | UINT64_C(2080374808), // LXSIWZX |
| 1465 | UINT64_C(3825205251), // LXSSP |
| 1466 | UINT64_C(2080375832), // LXSSPX |
| 1467 | UINT64_C(4093640705), // LXV |
| 1468 | UINT64_C(2080376536), // LXVB16X |
| 1469 | UINT64_C(2080376472), // LXVD2X |
| 1470 | UINT64_C(2080375448), // LXVDSX |
| 1471 | UINT64_C(2080376408), // LXVH8X |
| 1472 | UINT64_C(4028564176), // LXVKQ |
| 1473 | UINT64_C(2080375322), // LXVL |
| 1474 | UINT64_C(2080375386), // LXVLL |
| 1475 | UINT64_C(402653184), // LXVP |
| 1476 | UINT64_C(2080375962), // LXVPRL |
| 1477 | UINT64_C(2080376026), // LXVPRLL |
| 1478 | UINT64_C(2080375450), // LXVPX |
| 1479 | UINT64_C(2080374810), // LXVRBX |
| 1480 | UINT64_C(2080375002), // LXVRDX |
| 1481 | UINT64_C(2080374874), // LXVRHX |
| 1482 | UINT64_C(2080375834), // LXVRL |
| 1483 | UINT64_C(2080375898), // LXVRLL |
| 1484 | UINT64_C(2080374938), // LXVRWX |
| 1485 | UINT64_C(2080376344), // LXVW4X |
| 1486 | UINT64_C(2080375512), // LXVWSX |
| 1487 | UINT64_C(2080375320), // LXVX |
| 1488 | UINT64_C(268435504), // MADDHD |
| 1489 | UINT64_C(268435505), // MADDHDU |
| 1490 | UINT64_C(268435507), // MADDLD |
| 1491 | UINT64_C(268435507), // MADDLD8 |
| 1492 | UINT64_C(2080376492), // MBAR |
| 1493 | UINT64_C(1275068416), // MCRF |
| 1494 | UINT64_C(4227858560), // MCRFS |
| 1495 | UINT64_C(2080375936), // MCRXRX |
| 1496 | UINT64_C(2080375388), // MFBHRBE |
| 1497 | UINT64_C(2080374822), // MFCR |
| 1498 | UINT64_C(2080374822), // MFCR8 |
| 1499 | UINT64_C(2080965286), // MFCTR |
| 1500 | UINT64_C(2080965286), // MFCTR8 |
| 1501 | UINT64_C(2080375430), // MFDCR |
| 1502 | UINT64_C(4227859598), // MFFS |
| 1503 | UINT64_C(4229170318), // MFFSCDRN |
| 1504 | UINT64_C(4229235854), // MFFSCDRNI |
| 1505 | UINT64_C(4227925134), // MFFSCE |
| 1506 | UINT64_C(4229301390), // MFFSCRN |
| 1507 | UINT64_C(4229366926), // MFFSCRNI |
| 1508 | UINT64_C(4229432462), // MFFSL |
| 1509 | UINT64_C(4227859599), // MFFS_rec |
| 1510 | UINT64_C(2080899750), // MFLR |
| 1511 | UINT64_C(2080899750), // MFLR8 |
| 1512 | UINT64_C(2080374950), // MFMSR |
| 1513 | UINT64_C(2081423398), // MFOCRF |
| 1514 | UINT64_C(2081423398), // MFOCRF8 |
| 1515 | UINT64_C(2080375452), // MFPMR |
| 1516 | UINT64_C(2080375462), // MFSPR |
| 1517 | UINT64_C(2080375462), // MFSPR8 |
| 1518 | UINT64_C(2080375974), // MFSR |
| 1519 | UINT64_C(2080376102), // MFSRIN |
| 1520 | UINT64_C(2080375526), // MFTB |
| 1521 | UINT64_C(2081178278), // MFTB8 |
| 1522 | UINT64_C(2080572070), // MFUDSCR |
| 1523 | UINT64_C(2080374886), // MFVRD |
| 1524 | UINT64_C(2080391846), // MFVRSAVE |
| 1525 | UINT64_C(2080391846), // MFVRSAVEv |
| 1526 | UINT64_C(2080375014), // MFVRWZ |
| 1527 | UINT64_C(268436996), // MFVSCR |
| 1528 | UINT64_C(2080374886), // MFVSRD |
| 1529 | UINT64_C(2080375398), // MFVSRLD |
| 1530 | UINT64_C(2080375014), // MFVSRWZ |
| 1531 | UINT64_C(2080376338), // MODSD |
| 1532 | UINT64_C(2080376342), // MODSW |
| 1533 | UINT64_C(2080375314), // MODUD |
| 1534 | UINT64_C(2080375318), // MODUW |
| 1535 | UINT64_C(2080376556), // MSGSYNC |
| 1536 | UINT64_C(2080375980), // MSYNC |
| 1537 | UINT64_C(2080375072), // MTCRF |
| 1538 | UINT64_C(2080375072), // MTCRF8 |
| 1539 | UINT64_C(2080965542), // MTCTR |
| 1540 | UINT64_C(2080965542), // MTCTR8 |
| 1541 | UINT64_C(2080965542), // MTCTR8loop |
| 1542 | UINT64_C(2080965542), // MTCTRloop |
| 1543 | UINT64_C(2080375686), // MTDCR |
| 1544 | UINT64_C(4227858572), // MTFSB0 |
| 1545 | UINT64_C(4227858508), // MTFSB1 |
| 1546 | UINT64_C(4227859854), // MTFSF |
| 1547 | UINT64_C(4227858700), // MTFSFI |
| 1548 | UINT64_C(4227858701), // MTFSFI_rec |
| 1549 | UINT64_C(4227858700), // MTFSFIb |
| 1550 | UINT64_C(4227859855), // MTFSF_rec |
| 1551 | UINT64_C(4227859854), // MTFSFb |
| 1552 | UINT64_C(2080900006), // MTLR |
| 1553 | UINT64_C(2080900006), // MTLR8 |
| 1554 | UINT64_C(2080375076), // MTMSR |
| 1555 | UINT64_C(2080375140), // MTMSRD |
| 1556 | UINT64_C(2081423648), // MTOCRF |
| 1557 | UINT64_C(2081423648), // MTOCRF8 |
| 1558 | UINT64_C(2080375708), // MTPMR |
| 1559 | UINT64_C(2080375718), // MTSPR |
| 1560 | UINT64_C(2080375718), // MTSPR8 |
| 1561 | UINT64_C(2080375204), // MTSR |
| 1562 | UINT64_C(2080375268), // MTSRIN |
| 1563 | UINT64_C(2080572326), // MTUDSCR |
| 1564 | UINT64_C(2080375142), // MTVRD |
| 1565 | UINT64_C(2080392102), // MTVRSAVE |
| 1566 | UINT64_C(2080392102), // MTVRSAVEv |
| 1567 | UINT64_C(2080375206), // MTVRWA |
| 1568 | UINT64_C(2080375270), // MTVRWZ |
| 1569 | UINT64_C(268437060), // MTVSCR |
| 1570 | UINT64_C(269485634), // MTVSRBM |
| 1571 | UINT64_C(268435476), // MTVSRBMI |
| 1572 | UINT64_C(2080375142), // MTVSRD |
| 1573 | UINT64_C(2080375654), // MTVSRDD |
| 1574 | UINT64_C(269682242), // MTVSRDM |
| 1575 | UINT64_C(269551170), // MTVSRHM |
| 1576 | UINT64_C(269747778), // MTVSRQM |
| 1577 | UINT64_C(2080375206), // MTVSRWA |
| 1578 | UINT64_C(269616706), // MTVSRWM |
| 1579 | UINT64_C(2080375590), // MTVSRWS |
| 1580 | UINT64_C(2080375270), // MTVSRWZ |
| 1581 | UINT64_C(2080374930), // MULHD |
| 1582 | UINT64_C(2080374802), // MULHDU |
| 1583 | UINT64_C(2080374803), // MULHDU_rec |
| 1584 | UINT64_C(2080374931), // MULHD_rec |
| 1585 | UINT64_C(2080374934), // MULHW |
| 1586 | UINT64_C(2080374806), // MULHWU |
| 1587 | UINT64_C(2080374807), // MULHWU_rec |
| 1588 | UINT64_C(2080374935), // MULHW_rec |
| 1589 | UINT64_C(2080375250), // MULLD |
| 1590 | UINT64_C(2080376274), // MULLDO |
| 1591 | UINT64_C(2080376275), // MULLDO_rec |
| 1592 | UINT64_C(2080375251), // MULLD_rec |
| 1593 | UINT64_C(469762048), // MULLI |
| 1594 | UINT64_C(469762048), // MULLI8 |
| 1595 | UINT64_C(2080375254), // MULLW |
| 1596 | UINT64_C(2080376278), // MULLWO |
| 1597 | UINT64_C(2080376279), // MULLWO_rec |
| 1598 | UINT64_C(2080375255), // MULLW_rec |
| 1599 | UINT64_C(0), // MoveGOTtoLR |
| 1600 | UINT64_C(0), // MovePCtoLR |
| 1601 | UINT64_C(0), // MovePCtoLR8 |
| 1602 | UINT64_C(2080375736), // NAND |
| 1603 | UINT64_C(2080375736), // NAND8 |
| 1604 | UINT64_C(2080375737), // NAND8_rec |
| 1605 | UINT64_C(2080375737), // NAND_rec |
| 1606 | UINT64_C(1275069284), // NAP |
| 1607 | UINT64_C(2080374992), // NEG |
| 1608 | UINT64_C(2080374992), // NEG8 |
| 1609 | UINT64_C(2080376016), // NEG8O |
| 1610 | UINT64_C(2080376017), // NEG8O_rec |
| 1611 | UINT64_C(2080374993), // NEG8_rec |
| 1612 | UINT64_C(2080376016), // NEGO |
| 1613 | UINT64_C(2080376017), // NEGO_rec |
| 1614 | UINT64_C(2080374993), // NEG_rec |
| 1615 | UINT64_C(1610612736), // NOP |
| 1616 | UINT64_C(1612775424), // NOP_GT_PWR6 |
| 1617 | UINT64_C(1614938112), // NOP_GT_PWR7 |
| 1618 | UINT64_C(2080375032), // NOR |
| 1619 | UINT64_C(2080375032), // NOR8 |
| 1620 | UINT64_C(2080375033), // NOR8_rec |
| 1621 | UINT64_C(2080375033), // NOR_rec |
| 1622 | UINT64_C(2080375672), // OR |
| 1623 | UINT64_C(2080375672), // OR8 |
| 1624 | UINT64_C(2080375673), // OR8_rec |
| 1625 | UINT64_C(2080375608), // ORC |
| 1626 | UINT64_C(2080375608), // ORC8 |
| 1627 | UINT64_C(2080375609), // ORC8_rec |
| 1628 | UINT64_C(2080375609), // ORC_rec |
| 1629 | UINT64_C(1610612736), // ORI |
| 1630 | UINT64_C(1610612736), // ORI8 |
| 1631 | UINT64_C(1677721600), // ORIS |
| 1632 | UINT64_C(1677721600), // ORIS8 |
| 1633 | UINT64_C(2080375673), // OR_rec |
| 1634 | UINT64_C(432345565167091712), // PADDI |
| 1635 | UINT64_C(432345565167091712), // PADDI8 |
| 1636 | UINT64_C(436849164794462208), // PADDI8pc |
| 1637 | UINT64_C(0), // PADDIdtprel |
| 1638 | UINT64_C(436849164794462208), // PADDIpc |
| 1639 | UINT64_C(2080375096), // PDEPD |
| 1640 | UINT64_C(2080375160), // PEXTD |
| 1641 | UINT64_C(432345565167091712), // PLA |
| 1642 | UINT64_C(432345565167091712), // PLA8 |
| 1643 | UINT64_C(432345565167091712), // PLA8pc |
| 1644 | UINT64_C(432345565167091712), // PLApc |
| 1645 | UINT64_C(432345566509268992), // PLBZ |
| 1646 | UINT64_C(432345566509268992), // PLBZ8 |
| 1647 | UINT64_C(432345566509268992), // PLBZ8nopc |
| 1648 | UINT64_C(436849166136639488), // PLBZ8onlypc |
| 1649 | UINT64_C(436849166136639488), // PLBZ8pc |
| 1650 | UINT64_C(432345566509268992), // PLBZnopc |
| 1651 | UINT64_C(436849166136639488), // PLBZonlypc |
| 1652 | UINT64_C(436849166136639488), // PLBZpc |
| 1653 | UINT64_C(288230379976916992), // PLD |
| 1654 | UINT64_C(288230379976916992), // PLDnopc |
| 1655 | UINT64_C(292733979604287488), // PLDonlypc |
| 1656 | UINT64_C(292733979604287488), // PLDpc |
| 1657 | UINT64_C(432345567583010816), // PLFD |
| 1658 | UINT64_C(432345567583010816), // PLFDnopc |
| 1659 | UINT64_C(436849167210381312), // PLFDonlypc |
| 1660 | UINT64_C(436849167210381312), // PLFDpc |
| 1661 | UINT64_C(432345567448793088), // PLFS |
| 1662 | UINT64_C(432345567448793088), // PLFSnopc |
| 1663 | UINT64_C(436849167076163584), // PLFSonlypc |
| 1664 | UINT64_C(436849167076163584), // PLFSpc |
| 1665 | UINT64_C(432345567046139904), // PLHA |
| 1666 | UINT64_C(432345567046139904), // PLHA8 |
| 1667 | UINT64_C(432345567046139904), // PLHA8nopc |
| 1668 | UINT64_C(436849166673510400), // PLHA8onlypc |
| 1669 | UINT64_C(436849166673510400), // PLHA8pc |
| 1670 | UINT64_C(432345567046139904), // PLHAnopc |
| 1671 | UINT64_C(436849166673510400), // PLHAonlypc |
| 1672 | UINT64_C(436849166673510400), // PLHApc |
| 1673 | UINT64_C(432345566911922176), // PLHZ |
| 1674 | UINT64_C(432345566911922176), // PLHZ8 |
| 1675 | UINT64_C(432345566911922176), // PLHZ8nopc |
| 1676 | UINT64_C(436849166539292672), // PLHZ8onlypc |
| 1677 | UINT64_C(436849166539292672), // PLHZ8pc |
| 1678 | UINT64_C(432345566911922176), // PLHZnopc |
| 1679 | UINT64_C(436849166539292672), // PLHZonlypc |
| 1680 | UINT64_C(436849166539292672), // PLHZpc |
| 1681 | UINT64_C(432345565167091712), // PLI |
| 1682 | UINT64_C(432345565167091712), // PLI8 |
| 1683 | UINT64_C(288230378903175168), // PLWA |
| 1684 | UINT64_C(288230378903175168), // PLWA8 |
| 1685 | UINT64_C(288230378903175168), // PLWA8nopc |
| 1686 | UINT64_C(292733978530545664), // PLWA8onlypc |
| 1687 | UINT64_C(292733978530545664), // PLWA8pc |
| 1688 | UINT64_C(288230378903175168), // PLWAnopc |
| 1689 | UINT64_C(292733978530545664), // PLWAonlypc |
| 1690 | UINT64_C(292733978530545664), // PLWApc |
| 1691 | UINT64_C(432345566375051264), // PLWZ |
| 1692 | UINT64_C(432345566375051264), // PLWZ8 |
| 1693 | UINT64_C(432345566375051264), // PLWZ8nopc |
| 1694 | UINT64_C(436849166002421760), // PLWZ8onlypc |
| 1695 | UINT64_C(436849166002421760), // PLWZ8pc |
| 1696 | UINT64_C(432345566375051264), // PLWZnopc |
| 1697 | UINT64_C(436849166002421760), // PLWZonlypc |
| 1698 | UINT64_C(436849166002421760), // PLWZpc |
| 1699 | UINT64_C(288230378970284032), // PLXSD |
| 1700 | UINT64_C(288230378970284032), // PLXSDnopc |
| 1701 | UINT64_C(292733978597654528), // PLXSDonlypc |
| 1702 | UINT64_C(292733978597654528), // PLXSDpc |
| 1703 | UINT64_C(288230379037392896), // PLXSSP |
| 1704 | UINT64_C(288230379037392896), // PLXSSPnopc |
| 1705 | UINT64_C(292733978664763392), // PLXSSPonlypc |
| 1706 | UINT64_C(292733978664763392), // PLXSSPpc |
| 1707 | UINT64_C(288230379507154944), // PLXV |
| 1708 | UINT64_C(288230380044025856), // PLXVP |
| 1709 | UINT64_C(288230380044025856), // PLXVPnopc |
| 1710 | UINT64_C(292733979671396352), // PLXVPonlypc |
| 1711 | UINT64_C(292733979671396352), // PLXVPpc |
| 1712 | UINT64_C(288230379507154944), // PLXVnopc |
| 1713 | UINT64_C(292733979134525440), // PLXVonlypc |
| 1714 | UINT64_C(292733979134525440), // PLXVpc |
| 1715 | UINT64_C(544935558871253720), // PMDMXVBF16GERX2 |
| 1716 | UINT64_C(544935558871254864), // PMDMXVBF16GERX2NN |
| 1717 | UINT64_C(544935558871253912), // PMDMXVBF16GERX2NP |
| 1718 | UINT64_C(544935558871254424), // PMDMXVBF16GERX2PN |
| 1719 | UINT64_C(544935558871253584), // PMDMXVBF16GERX2PP |
| 1720 | UINT64_C(544935558871253528), // PMDMXVF16GERX2 |
| 1721 | UINT64_C(544935558871254608), // PMDMXVF16GERX2NN |
| 1722 | UINT64_C(544935558871253656), // PMDMXVF16GERX2NP |
| 1723 | UINT64_C(544935558871254168), // PMDMXVF16GERX2PN |
| 1724 | UINT64_C(544935558871253520), // PMDMXVF16GERX2PP |
| 1725 | UINT64_C(544935558871253080), // PMDMXVI8GERX4 |
| 1726 | UINT64_C(544935558871253072), // PMDMXVI8GERX4PP |
| 1727 | UINT64_C(544935558871253776), // PMDMXVI8GERX4SPP |
| 1728 | UINT64_C(544935558871253400), // PMXVBF16GER2 |
| 1729 | UINT64_C(544935558871254928), // PMXVBF16GER2NN |
| 1730 | UINT64_C(544935558871253904), // PMXVBF16GER2NP |
| 1731 | UINT64_C(544935558871254416), // PMXVBF16GER2PN |
| 1732 | UINT64_C(544935558871253392), // PMXVBF16GER2PP |
| 1733 | UINT64_C(544935558871253400), // PMXVBF16GER2W |
| 1734 | UINT64_C(544935558871254928), // PMXVBF16GER2WNN |
| 1735 | UINT64_C(544935558871253904), // PMXVBF16GER2WNP |
| 1736 | UINT64_C(544935558871254416), // PMXVBF16GER2WPN |
| 1737 | UINT64_C(544935558871253392), // PMXVBF16GER2WPP |
| 1738 | UINT64_C(544935558871253144), // PMXVF16GER2 |
| 1739 | UINT64_C(544935558871254672), // PMXVF16GER2NN |
| 1740 | UINT64_C(544935558871253648), // PMXVF16GER2NP |
| 1741 | UINT64_C(544935558871254160), // PMXVF16GER2PN |
| 1742 | UINT64_C(544935558871253136), // PMXVF16GER2PP |
| 1743 | UINT64_C(544935558871253144), // PMXVF16GER2W |
| 1744 | UINT64_C(544935558871254672), // PMXVF16GER2WNN |
| 1745 | UINT64_C(544935558871253648), // PMXVF16GER2WNP |
| 1746 | UINT64_C(544935558871254160), // PMXVF16GER2WPN |
| 1747 | UINT64_C(544935558871253136), // PMXVF16GER2WPP |
| 1748 | UINT64_C(544935558871253208), // PMXVF32GER |
| 1749 | UINT64_C(544935558871254736), // PMXVF32GERNN |
| 1750 | UINT64_C(544935558871253712), // PMXVF32GERNP |
| 1751 | UINT64_C(544935558871254224), // PMXVF32GERPN |
| 1752 | UINT64_C(544935558871253200), // PMXVF32GERPP |
| 1753 | UINT64_C(544935558871253208), // PMXVF32GERW |
| 1754 | UINT64_C(544935558871254736), // PMXVF32GERWNN |
| 1755 | UINT64_C(544935558871253712), // PMXVF32GERWNP |
| 1756 | UINT64_C(544935558871254224), // PMXVF32GERWPN |
| 1757 | UINT64_C(544935558871253200), // PMXVF32GERWPP |
| 1758 | UINT64_C(544935558871253464), // PMXVF64GER |
| 1759 | UINT64_C(544935558871254992), // PMXVF64GERNN |
| 1760 | UINT64_C(544935558871253968), // PMXVF64GERNP |
| 1761 | UINT64_C(544935558871254480), // PMXVF64GERPN |
| 1762 | UINT64_C(544935558871253456), // PMXVF64GERPP |
| 1763 | UINT64_C(544935558871253464), // PMXVF64GERW |
| 1764 | UINT64_C(544935558871254992), // PMXVF64GERWNN |
| 1765 | UINT64_C(544935558871253968), // PMXVF64GERWNP |
| 1766 | UINT64_C(544935558871254480), // PMXVF64GERWPN |
| 1767 | UINT64_C(544935558871253456), // PMXVF64GERWPP |
| 1768 | UINT64_C(544935558871253592), // PMXVI16GER2 |
| 1769 | UINT64_C(544935558871253848), // PMXVI16GER2PP |
| 1770 | UINT64_C(544935558871253336), // PMXVI16GER2S |
| 1771 | UINT64_C(544935558871253328), // PMXVI16GER2SPP |
| 1772 | UINT64_C(544935558871253336), // PMXVI16GER2SW |
| 1773 | UINT64_C(544935558871253328), // PMXVI16GER2SWPP |
| 1774 | UINT64_C(544935558871253592), // PMXVI16GER2W |
| 1775 | UINT64_C(544935558871253848), // PMXVI16GER2WPP |
| 1776 | UINT64_C(544935558871253272), // PMXVI4GER8 |
| 1777 | UINT64_C(544935558871253264), // PMXVI4GER8PP |
| 1778 | UINT64_C(544935558871253272), // PMXVI4GER8W |
| 1779 | UINT64_C(544935558871253264), // PMXVI4GER8WPP |
| 1780 | UINT64_C(544935558871253016), // PMXVI8GER4 |
| 1781 | UINT64_C(544935558871253008), // PMXVI8GER4PP |
| 1782 | UINT64_C(544935558871253784), // PMXVI8GER4SPP |
| 1783 | UINT64_C(544935558871253016), // PMXVI8GER4W |
| 1784 | UINT64_C(544935558871253008), // PMXVI8GER4WPP |
| 1785 | UINT64_C(544935558871253784), // PMXVI8GER4WSPP |
| 1786 | UINT64_C(2080375028), // POPCNTB |
| 1787 | UINT64_C(2080375028), // POPCNTB8 |
| 1788 | UINT64_C(2080375796), // POPCNTD |
| 1789 | UINT64_C(2080375540), // POPCNTW |
| 1790 | UINT64_C(0), // PPC32GOT |
| 1791 | UINT64_C(0), // PPC32PICGOT |
| 1792 | UINT64_C(0), // PREPARE_PROBED_ALLOCA_32 |
| 1793 | UINT64_C(0), // PREPARE_PROBED_ALLOCA_64 |
| 1794 | UINT64_C(0), // PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32 |
| 1795 | UINT64_C(0), // PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64 |
| 1796 | UINT64_C(0), // PROBED_ALLOCA_32 |
| 1797 | UINT64_C(0), // PROBED_ALLOCA_64 |
| 1798 | UINT64_C(0), // PROBED_STACKALLOC_32 |
| 1799 | UINT64_C(0), // PROBED_STACKALLOC_64 |
| 1800 | UINT64_C(432345566777704448), // PSTB |
| 1801 | UINT64_C(432345566777704448), // PSTB8 |
| 1802 | UINT64_C(432345566777704448), // PSTB8nopc |
| 1803 | UINT64_C(436849166405074944), // PSTB8onlypc |
| 1804 | UINT64_C(436849166405074944), // PSTB8pc |
| 1805 | UINT64_C(432345566777704448), // PSTBnopc |
| 1806 | UINT64_C(436849166405074944), // PSTBonlypc |
| 1807 | UINT64_C(436849166405074944), // PSTBpc |
| 1808 | UINT64_C(288230380245352448), // PSTD |
| 1809 | UINT64_C(288230380245352448), // PSTDnopc |
| 1810 | UINT64_C(292733979872722944), // PSTDonlypc |
| 1811 | UINT64_C(292733979872722944), // PSTDpc |
| 1812 | UINT64_C(432345567851446272), // PSTFD |
| 1813 | UINT64_C(432345567851446272), // PSTFDnopc |
| 1814 | UINT64_C(436849167478816768), // PSTFDonlypc |
| 1815 | UINT64_C(436849167478816768), // PSTFDpc |
| 1816 | UINT64_C(432345567717228544), // PSTFS |
| 1817 | UINT64_C(432345567717228544), // PSTFSnopc |
| 1818 | UINT64_C(436849167344599040), // PSTFSonlypc |
| 1819 | UINT64_C(436849167344599040), // PSTFSpc |
| 1820 | UINT64_C(432345567180357632), // PSTH |
| 1821 | UINT64_C(432345567180357632), // PSTH8 |
| 1822 | UINT64_C(432345567180357632), // PSTH8nopc |
| 1823 | UINT64_C(436849166807728128), // PSTH8onlypc |
| 1824 | UINT64_C(436849166807728128), // PSTH8pc |
| 1825 | UINT64_C(432345567180357632), // PSTHnopc |
| 1826 | UINT64_C(436849166807728128), // PSTHonlypc |
| 1827 | UINT64_C(436849166807728128), // PSTHpc |
| 1828 | UINT64_C(432345566643486720), // PSTW |
| 1829 | UINT64_C(432345566643486720), // PSTW8 |
| 1830 | UINT64_C(432345566643486720), // PSTW8nopc |
| 1831 | UINT64_C(436849166270857216), // PSTW8onlypc |
| 1832 | UINT64_C(436849166270857216), // PSTW8pc |
| 1833 | UINT64_C(432345566643486720), // PSTWnopc |
| 1834 | UINT64_C(436849166270857216), // PSTWonlypc |
| 1835 | UINT64_C(436849166270857216), // PSTWpc |
| 1836 | UINT64_C(288230379238719488), // PSTXSD |
| 1837 | UINT64_C(288230379238719488), // PSTXSDnopc |
| 1838 | UINT64_C(292733978866089984), // PSTXSDonlypc |
| 1839 | UINT64_C(292733978866089984), // PSTXSDpc |
| 1840 | UINT64_C(288230379305828352), // PSTXSSP |
| 1841 | UINT64_C(288230379305828352), // PSTXSSPnopc |
| 1842 | UINT64_C(292733978933198848), // PSTXSSPonlypc |
| 1843 | UINT64_C(292733978933198848), // PSTXSSPpc |
| 1844 | UINT64_C(288230379775590400), // PSTXV |
| 1845 | UINT64_C(288230380312461312), // PSTXVP |
| 1846 | UINT64_C(288230380312461312), // PSTXVPnopc |
| 1847 | UINT64_C(292733979939831808), // PSTXVPonlypc |
| 1848 | UINT64_C(292733979939831808), // PSTXVPpc |
| 1849 | UINT64_C(288230379775590400), // PSTXVnopc |
| 1850 | UINT64_C(292733979402960896), // PSTXVonlypc |
| 1851 | UINT64_C(292733979402960896), // PSTXVpc |
| 1852 | UINT64_C(0), // PseudoEIEIO |
| 1853 | UINT64_C(0), // RESTORE_ACC |
| 1854 | UINT64_C(0), // RESTORE_CR |
| 1855 | UINT64_C(0), // RESTORE_CRBIT |
| 1856 | UINT64_C(0), // RESTORE_DMR |
| 1857 | UINT64_C(0), // RESTORE_DMRP |
| 1858 | UINT64_C(0), // RESTORE_QUADWORD |
| 1859 | UINT64_C(0), // RESTORE_UACC |
| 1860 | UINT64_C(0), // RESTORE_WACC |
| 1861 | UINT64_C(1275068518), // RFCI |
| 1862 | UINT64_C(1275068494), // RFDI |
| 1863 | UINT64_C(1275068708), // RFEBB |
| 1864 | UINT64_C(1275068516), // RFI |
| 1865 | UINT64_C(1275068452), // RFID |
| 1866 | UINT64_C(1275068492), // RFMCI |
| 1867 | UINT64_C(2013265936), // RLDCL |
| 1868 | UINT64_C(2013265937), // RLDCL_rec |
| 1869 | UINT64_C(2013265938), // RLDCR |
| 1870 | UINT64_C(2013265939), // RLDCR_rec |
| 1871 | UINT64_C(2013265928), // RLDIC |
| 1872 | UINT64_C(2013265920), // RLDICL |
| 1873 | UINT64_C(2013265920), // RLDICL_32 |
| 1874 | UINT64_C(2013265920), // RLDICL_32_64 |
| 1875 | UINT64_C(2013265921), // RLDICL_32_rec |
| 1876 | UINT64_C(2013265921), // RLDICL_rec |
| 1877 | UINT64_C(2013265924), // RLDICR |
| 1878 | UINT64_C(2013265924), // RLDICR_32 |
| 1879 | UINT64_C(2013265925), // RLDICR_rec |
| 1880 | UINT64_C(2013265929), // RLDIC_rec |
| 1881 | UINT64_C(2013265932), // RLDIMI |
| 1882 | UINT64_C(2013265933), // RLDIMI_rec |
| 1883 | UINT64_C(1342177280), // RLWIMI |
| 1884 | UINT64_C(1342177280), // RLWIMI8 |
| 1885 | UINT64_C(1342177281), // RLWIMI8_rec |
| 1886 | UINT64_C(1342177281), // RLWIMI_rec |
| 1887 | UINT64_C(1409286144), // RLWINM |
| 1888 | UINT64_C(1409286144), // RLWINM8 |
| 1889 | UINT64_C(1409286145), // RLWINM8_rec |
| 1890 | UINT64_C(1409286145), // RLWINM_rec |
| 1891 | UINT64_C(1543503872), // RLWNM |
| 1892 | UINT64_C(1543503872), // RLWNM8 |
| 1893 | UINT64_C(1543503873), // RLWNM8_rec |
| 1894 | UINT64_C(1543503873), // RLWNM_rec |
| 1895 | UINT64_C(0), // ReadTB |
| 1896 | UINT64_C(1140850690), // SC |
| 1897 | UINT64_C(1140850689), // SCV |
| 1898 | UINT64_C(0), // SELECT_CC_F16 |
| 1899 | UINT64_C(0), // SELECT_CC_F4 |
| 1900 | UINT64_C(0), // SELECT_CC_F8 |
| 1901 | UINT64_C(0), // SELECT_CC_I4 |
| 1902 | UINT64_C(0), // SELECT_CC_I8 |
| 1903 | UINT64_C(0), // SELECT_CC_SPE |
| 1904 | UINT64_C(0), // SELECT_CC_SPE4 |
| 1905 | UINT64_C(0), // SELECT_CC_VRRC |
| 1906 | UINT64_C(0), // SELECT_CC_VSFRC |
| 1907 | UINT64_C(0), // SELECT_CC_VSRC |
| 1908 | UINT64_C(0), // SELECT_CC_VSSRC |
| 1909 | UINT64_C(0), // SELECT_F16 |
| 1910 | UINT64_C(0), // SELECT_F4 |
| 1911 | UINT64_C(0), // SELECT_F8 |
| 1912 | UINT64_C(0), // SELECT_I4 |
| 1913 | UINT64_C(0), // SELECT_I8 |
| 1914 | UINT64_C(0), // SELECT_SPE |
| 1915 | UINT64_C(0), // SELECT_SPE4 |
| 1916 | UINT64_C(0), // SELECT_VRRC |
| 1917 | UINT64_C(0), // SELECT_VSFRC |
| 1918 | UINT64_C(0), // SELECT_VSRC |
| 1919 | UINT64_C(0), // SELECT_VSSRC |
| 1920 | UINT64_C(2080375040), // SETB |
| 1921 | UINT64_C(2080375040), // SETB8 |
| 1922 | UINT64_C(2080375552), // SETBC |
| 1923 | UINT64_C(2080375552), // SETBC8 |
| 1924 | UINT64_C(2080375616), // SETBCR |
| 1925 | UINT64_C(2080375616), // SETBCR8 |
| 1926 | UINT64_C(0), // SETFLM |
| 1927 | UINT64_C(2080375680), // SETNBC |
| 1928 | UINT64_C(2080375680), // SETNBC8 |
| 1929 | UINT64_C(2080375744), // SETNBCR |
| 1930 | UINT64_C(2080375744), // SETNBCR8 |
| 1931 | UINT64_C(0), // SETRND |
| 1932 | UINT64_C(0), // SETRNDi |
| 1933 | UINT64_C(2080376743), // SLBFEE_rec |
| 1934 | UINT64_C(2080375780), // SLBIA |
| 1935 | UINT64_C(2080375652), // SLBIE |
| 1936 | UINT64_C(2080375716), // SLBIEG |
| 1937 | UINT64_C(2080376614), // SLBMFEE |
| 1938 | UINT64_C(2080376486), // SLBMFEV |
| 1939 | UINT64_C(2080375588), // SLBMTE |
| 1940 | UINT64_C(2080375460), // SLBSYNC |
| 1941 | UINT64_C(2080374838), // SLD |
| 1942 | UINT64_C(2080374839), // SLD_rec |
| 1943 | UINT64_C(2080374832), // SLW |
| 1944 | UINT64_C(2080374832), // SLW8 |
| 1945 | UINT64_C(2080374833), // SLW8_rec |
| 1946 | UINT64_C(2080374833), // SLW_rec |
| 1947 | UINT64_C(2147483648), // SPELWZ |
| 1948 | UINT64_C(2080374830), // SPELWZX |
| 1949 | UINT64_C(2415919104), // SPESTW |
| 1950 | UINT64_C(2080375086), // SPESTWX |
| 1951 | UINT64_C(0), // SPILL_ACC |
| 1952 | UINT64_C(0), // SPILL_CR |
| 1953 | UINT64_C(0), // SPILL_CRBIT |
| 1954 | UINT64_C(0), // SPILL_DMR |
| 1955 | UINT64_C(0), // SPILL_DMRP |
| 1956 | UINT64_C(0), // SPILL_QUADWORD |
| 1957 | UINT64_C(0), // SPILL_UACC |
| 1958 | UINT64_C(0), // SPILL_WACC |
| 1959 | UINT64_C(0), // SPLIT_QUADWORD |
| 1960 | UINT64_C(2080376372), // SRAD |
| 1961 | UINT64_C(2080376436), // SRADI |
| 1962 | UINT64_C(2080376436), // SRADI_32 |
| 1963 | UINT64_C(2080376437), // SRADI_rec |
| 1964 | UINT64_C(2080376373), // SRAD_rec |
| 1965 | UINT64_C(2080376368), // SRAW |
| 1966 | UINT64_C(2080376368), // SRAW8 |
| 1967 | UINT64_C(2080376369), // SRAW8_rec |
| 1968 | UINT64_C(2080376432), // SRAWI |
| 1969 | UINT64_C(2080376432), // SRAWI8 |
| 1970 | UINT64_C(2080376433), // SRAWI8_rec |
| 1971 | UINT64_C(2080376433), // SRAWI_rec |
| 1972 | UINT64_C(2080376369), // SRAW_rec |
| 1973 | UINT64_C(2080375862), // SRD |
| 1974 | UINT64_C(2080375863), // SRD_rec |
| 1975 | UINT64_C(2080375856), // SRW |
| 1976 | UINT64_C(2080375856), // SRW8 |
| 1977 | UINT64_C(2080375857), // SRW8_rec |
| 1978 | UINT64_C(2080375857), // SRW_rec |
| 1979 | UINT64_C(2550136832), // STB |
| 1980 | UINT64_C(2550136832), // STB8 |
| 1981 | UINT64_C(2080376746), // STBCIX |
| 1982 | UINT64_C(2080376173), // STBCX |
| 1983 | UINT64_C(2080375230), // STBEPX |
| 1984 | UINT64_C(2617245696), // STBU |
| 1985 | UINT64_C(2617245696), // STBU8 |
| 1986 | UINT64_C(2080375278), // STBUX |
| 1987 | UINT64_C(2080375278), // STBUX8 |
| 1988 | UINT64_C(2080375214), // STBX |
| 1989 | UINT64_C(2080375214), // STBX8 |
| 1990 | UINT64_C(2080375214), // STBXTLS |
| 1991 | UINT64_C(2080375214), // STBXTLS_ |
| 1992 | UINT64_C(2080375214), // STBXTLS_32 |
| 1993 | UINT64_C(4160749568), // STD |
| 1994 | UINT64_C(2080376268), // STDAT |
| 1995 | UINT64_C(2080376104), // STDBRX |
| 1996 | UINT64_C(2080376810), // STDCIX |
| 1997 | UINT64_C(2080375213), // STDCX |
| 1998 | UINT64_C(4160749569), // STDU |
| 1999 | UINT64_C(2080375146), // STDUX |
| 2000 | UINT64_C(2080375082), // STDX |
| 2001 | UINT64_C(2080375082), // STDXTLS |
| 2002 | UINT64_C(2080375082), // STDXTLS_ |
| 2003 | UINT64_C(3623878656), // STFD |
| 2004 | UINT64_C(2080376254), // STFDEPX |
| 2005 | UINT64_C(3690987520), // STFDU |
| 2006 | UINT64_C(2080376302), // STFDUX |
| 2007 | UINT64_C(2080376238), // STFDX |
| 2008 | UINT64_C(2080376238), // STFDXTLS |
| 2009 | UINT64_C(2080376238), // STFDXTLS_ |
| 2010 | UINT64_C(2080376750), // STFIWX |
| 2011 | UINT64_C(3489660928), // STFS |
| 2012 | UINT64_C(3556769792), // STFSU |
| 2013 | UINT64_C(2080376174), // STFSUX |
| 2014 | UINT64_C(2080376110), // STFSX |
| 2015 | UINT64_C(2080376110), // STFSXTLS |
| 2016 | UINT64_C(2080376110), // STFSXTLS_ |
| 2017 | UINT64_C(2952790016), // STH |
| 2018 | UINT64_C(2952790016), // STH8 |
| 2019 | UINT64_C(2080376620), // STHBRX |
| 2020 | UINT64_C(2080376682), // STHCIX |
| 2021 | UINT64_C(2080376237), // STHCX |
| 2022 | UINT64_C(2080375614), // STHEPX |
| 2023 | UINT64_C(3019898880), // STHU |
| 2024 | UINT64_C(3019898880), // STHU8 |
| 2025 | UINT64_C(2080375662), // STHUX |
| 2026 | UINT64_C(2080375662), // STHUX8 |
| 2027 | UINT64_C(2080375598), // STHX |
| 2028 | UINT64_C(2080375598), // STHX8 |
| 2029 | UINT64_C(2080375598), // STHXTLS |
| 2030 | UINT64_C(2080375598), // STHXTLS_ |
| 2031 | UINT64_C(2080375598), // STHXTLS_32 |
| 2032 | UINT64_C(3154116608), // STMW |
| 2033 | UINT64_C(1275069156), // STOP |
| 2034 | UINT64_C(4160749570), // STQ |
| 2035 | UINT64_C(2080375149), // STQCX |
| 2036 | UINT64_C(0), // STQX_PSEUDO |
| 2037 | UINT64_C(2080376234), // STSWI |
| 2038 | UINT64_C(2080375054), // STVEBX |
| 2039 | UINT64_C(2080375118), // STVEHX |
| 2040 | UINT64_C(2080375182), // STVEWX |
| 2041 | UINT64_C(2080375246), // STVX |
| 2042 | UINT64_C(2080375758), // STVXL |
| 2043 | UINT64_C(2415919104), // STW |
| 2044 | UINT64_C(2415919104), // STW8 |
| 2045 | UINT64_C(2080376204), // STWAT |
| 2046 | UINT64_C(2080376108), // STWBRX |
| 2047 | UINT64_C(2080376618), // STWCIX |
| 2048 | UINT64_C(2080375085), // STWCX |
| 2049 | UINT64_C(2080375102), // STWEPX |
| 2050 | UINT64_C(2483027968), // STWU |
| 2051 | UINT64_C(2483027968), // STWU8 |
| 2052 | UINT64_C(2080375150), // STWUX |
| 2053 | UINT64_C(2080375150), // STWUX8 |
| 2054 | UINT64_C(2080375086), // STWX |
| 2055 | UINT64_C(2080375086), // STWX8 |
| 2056 | UINT64_C(2080375086), // STWXTLS |
| 2057 | UINT64_C(2080375086), // STWXTLS_ |
| 2058 | UINT64_C(2080375086), // STWXTLS_32 |
| 2059 | UINT64_C(4093640706), // STXSD |
| 2060 | UINT64_C(2080376216), // STXSDX |
| 2061 | UINT64_C(2080376602), // STXSIBX |
| 2062 | UINT64_C(2080376602), // STXSIBXv |
| 2063 | UINT64_C(2080376666), // STXSIHX |
| 2064 | UINT64_C(2080376666), // STXSIHXv |
| 2065 | UINT64_C(2080375064), // STXSIWX |
| 2066 | UINT64_C(4093640707), // STXSSP |
| 2067 | UINT64_C(2080376088), // STXSSPX |
| 2068 | UINT64_C(4093640709), // STXV |
| 2069 | UINT64_C(2080376792), // STXVB16X |
| 2070 | UINT64_C(2080376728), // STXVD2X |
| 2071 | UINT64_C(2080376664), // STXVH8X |
| 2072 | UINT64_C(2080375578), // STXVL |
| 2073 | UINT64_C(2080375642), // STXVLL |
| 2074 | UINT64_C(402653185), // STXVP |
| 2075 | UINT64_C(2080376218), // STXVPRL |
| 2076 | UINT64_C(2080376282), // STXVPRLL |
| 2077 | UINT64_C(2080375706), // STXVPX |
| 2078 | UINT64_C(2080375066), // STXVRBX |
| 2079 | UINT64_C(2080375258), // STXVRDX |
| 2080 | UINT64_C(2080375130), // STXVRHX |
| 2081 | UINT64_C(2080376090), // STXVRL |
| 2082 | UINT64_C(2080376154), // STXVRLL |
| 2083 | UINT64_C(2080375194), // STXVRWX |
| 2084 | UINT64_C(2080376600), // STXVW4X |
| 2085 | UINT64_C(2080375576), // STXVX |
| 2086 | UINT64_C(2080374864), // SUBF |
| 2087 | UINT64_C(2080374864), // SUBF8 |
| 2088 | UINT64_C(2080375888), // SUBF8O |
| 2089 | UINT64_C(2080375889), // SUBF8O_rec |
| 2090 | UINT64_C(2080374865), // SUBF8_rec |
| 2091 | UINT64_C(2080374800), // SUBFC |
| 2092 | UINT64_C(2080374800), // SUBFC8 |
| 2093 | UINT64_C(2080375824), // SUBFC8O |
| 2094 | UINT64_C(2080375825), // SUBFC8O_rec |
| 2095 | UINT64_C(2080374801), // SUBFC8_rec |
| 2096 | UINT64_C(2080375824), // SUBFCO |
| 2097 | UINT64_C(2080375825), // SUBFCO_rec |
| 2098 | UINT64_C(2080374801), // SUBFC_rec |
| 2099 | UINT64_C(2080375056), // SUBFE |
| 2100 | UINT64_C(2080375056), // SUBFE8 |
| 2101 | UINT64_C(2080376080), // SUBFE8O |
| 2102 | UINT64_C(2080376081), // SUBFE8O_rec |
| 2103 | UINT64_C(2080375057), // SUBFE8_rec |
| 2104 | UINT64_C(2080376080), // SUBFEO |
| 2105 | UINT64_C(2080376081), // SUBFEO_rec |
| 2106 | UINT64_C(2080375057), // SUBFE_rec |
| 2107 | UINT64_C(536870912), // SUBFIC |
| 2108 | UINT64_C(536870912), // SUBFIC8 |
| 2109 | UINT64_C(2080375248), // SUBFME |
| 2110 | UINT64_C(2080375248), // SUBFME8 |
| 2111 | UINT64_C(2080376272), // SUBFME8O |
| 2112 | UINT64_C(2080376273), // SUBFME8O_rec |
| 2113 | UINT64_C(2080375249), // SUBFME8_rec |
| 2114 | UINT64_C(2080376272), // SUBFMEO |
| 2115 | UINT64_C(2080376273), // SUBFMEO_rec |
| 2116 | UINT64_C(2080375249), // SUBFME_rec |
| 2117 | UINT64_C(2080375888), // SUBFO |
| 2118 | UINT64_C(2080375889), // SUBFO_rec |
| 2119 | UINT64_C(2080374928), // SUBFUS |
| 2120 | UINT64_C(2080374929), // SUBFUS_rec |
| 2121 | UINT64_C(2080375184), // SUBFZE |
| 2122 | UINT64_C(2080375184), // SUBFZE8 |
| 2123 | UINT64_C(2080376208), // SUBFZE8O |
| 2124 | UINT64_C(2080376209), // SUBFZE8O_rec |
| 2125 | UINT64_C(2080375185), // SUBFZE8_rec |
| 2126 | UINT64_C(2080376208), // SUBFZEO |
| 2127 | UINT64_C(2080376209), // SUBFZEO_rec |
| 2128 | UINT64_C(2080375185), // SUBFZE_rec |
| 2129 | UINT64_C(2080374865), // SUBF_rec |
| 2130 | UINT64_C(2080375980), // SYNC |
| 2131 | UINT64_C(2080375980), // SYNCP10 |
| 2132 | UINT64_C(2080376605), // TABORT |
| 2133 | UINT64_C(2080376413), // TABORTDC |
| 2134 | UINT64_C(2080376541), // TABORTDCI |
| 2135 | UINT64_C(2080376349), // TABORTWC |
| 2136 | UINT64_C(2080376477), // TABORTWCI |
| 2137 | UINT64_C(1207959552), // TAILB |
| 2138 | UINT64_C(1207959552), // TAILB8 |
| 2139 | UINT64_C(1207959552), // TAILBA |
| 2140 | UINT64_C(1207959552), // TAILBA8 |
| 2141 | UINT64_C(1317012512), // TAILBCTR |
| 2142 | UINT64_C(1317012512), // TAILBCTR8 |
| 2143 | UINT64_C(2080376093), // TBEGIN |
| 2144 | UINT64_C(0), // TBEGIN_RET |
| 2145 | UINT64_C(2080376220), // TCHECK |
| 2146 | UINT64_C(0), // TCHECK_RET |
| 2147 | UINT64_C(0), // TCRETURNai |
| 2148 | UINT64_C(0), // TCRETURNai8 |
| 2149 | UINT64_C(0), // TCRETURNdi |
| 2150 | UINT64_C(0), // TCRETURNdi8 |
| 2151 | UINT64_C(0), // TCRETURNri |
| 2152 | UINT64_C(0), // TCRETURNri8 |
| 2153 | UINT64_C(2080374920), // TD |
| 2154 | UINT64_C(134217728), // TDI |
| 2155 | UINT64_C(2080376157), // TEND |
| 2156 | UINT64_C(2080375524), // TLBIA |
| 2157 | UINT64_C(2080375396), // TLBIE |
| 2158 | UINT64_C(2080375332), // TLBIEL |
| 2159 | UINT64_C(2080374820), // TLBILX |
| 2160 | UINT64_C(2080376356), // TLBIVAX |
| 2161 | UINT64_C(2080376740), // TLBLD |
| 2162 | UINT64_C(2080376804), // TLBLI |
| 2163 | UINT64_C(2080376676), // TLBRE |
| 2164 | UINT64_C(2080376676), // TLBRE2 |
| 2165 | UINT64_C(2080376612), // TLBSX |
| 2166 | UINT64_C(2080376612), // TLBSX2 |
| 2167 | UINT64_C(2080376613), // TLBSX2D |
| 2168 | UINT64_C(2080375916), // TLBSYNC |
| 2169 | UINT64_C(2080376740), // TLBWE |
| 2170 | UINT64_C(2080376740), // TLBWE2 |
| 2171 | UINT64_C(0), // TLSGDAIX |
| 2172 | UINT64_C(0), // TLSGDAIX8 |
| 2173 | UINT64_C(0), // TLSLDAIX |
| 2174 | UINT64_C(0), // TLSLDAIX8 |
| 2175 | UINT64_C(2145386504), // TRAP |
| 2176 | UINT64_C(2080376797), // TRECHKPT |
| 2177 | UINT64_C(2080376669), // TRECLAIM |
| 2178 | UINT64_C(2080376285), // TSR |
| 2179 | UINT64_C(2080374792), // TW |
| 2180 | UINT64_C(201326592), // TWI |
| 2181 | UINT64_C(0), // UNENCODED_NOP |
| 2182 | UINT64_C(0), // UpdateGBR |
| 2183 | UINT64_C(268436483), // VABSDUB |
| 2184 | UINT64_C(268436547), // VABSDUH |
| 2185 | UINT64_C(268436611), // VABSDUW |
| 2186 | UINT64_C(268435776), // VADDCUQ |
| 2187 | UINT64_C(268435840), // VADDCUW |
| 2188 | UINT64_C(268435517), // VADDECUQ |
| 2189 | UINT64_C(268435516), // VADDEUQM |
| 2190 | UINT64_C(268435466), // VADDFP |
| 2191 | UINT64_C(268436224), // VADDSBS |
| 2192 | UINT64_C(268436288), // VADDSHS |
| 2193 | UINT64_C(268436352), // VADDSWS |
| 2194 | UINT64_C(268435456), // VADDUBM |
| 2195 | UINT64_C(268435968), // VADDUBS |
| 2196 | UINT64_C(268435648), // VADDUDM |
| 2197 | UINT64_C(268435520), // VADDUHM |
| 2198 | UINT64_C(268436032), // VADDUHS |
| 2199 | UINT64_C(268435712), // VADDUQM |
| 2200 | UINT64_C(268435584), // VADDUWM |
| 2201 | UINT64_C(268436096), // VADDUWS |
| 2202 | UINT64_C(268436484), // VAND |
| 2203 | UINT64_C(268436548), // VANDC |
| 2204 | UINT64_C(268436738), // VAVGSB |
| 2205 | UINT64_C(268436802), // VAVGSH |
| 2206 | UINT64_C(268436866), // VAVGSW |
| 2207 | UINT64_C(268436482), // VAVGUB |
| 2208 | UINT64_C(268436546), // VAVGUH |
| 2209 | UINT64_C(268436610), // VAVGUW |
| 2210 | UINT64_C(268436940), // VBPERMD |
| 2211 | UINT64_C(268436812), // VBPERMQ |
| 2212 | UINT64_C(268436298), // VCFSX |
| 2213 | UINT64_C(268436298), // VCFSX_0 |
| 2214 | UINT64_C(268436813), // VCFUGED |
| 2215 | UINT64_C(268436234), // VCFUX |
| 2216 | UINT64_C(268436234), // VCFUX_0 |
| 2217 | UINT64_C(268436744), // VCIPHER |
| 2218 | UINT64_C(268436745), // VCIPHERLAST |
| 2219 | UINT64_C(268435853), // VCLRLB |
| 2220 | UINT64_C(268435917), // VCLRRB |
| 2221 | UINT64_C(268437250), // VCLZB |
| 2222 | UINT64_C(268437442), // VCLZD |
| 2223 | UINT64_C(268437380), // VCLZDM |
| 2224 | UINT64_C(268437314), // VCLZH |
| 2225 | UINT64_C(268436994), // VCLZLSBB |
| 2226 | UINT64_C(268437378), // VCLZW |
| 2227 | UINT64_C(268436422), // VCMPBFP |
| 2228 | UINT64_C(268437446), // VCMPBFP_rec |
| 2229 | UINT64_C(268435654), // VCMPEQFP |
| 2230 | UINT64_C(268436678), // VCMPEQFP_rec |
| 2231 | UINT64_C(268435462), // VCMPEQUB |
| 2232 | UINT64_C(268436486), // VCMPEQUB_rec |
| 2233 | UINT64_C(268435655), // VCMPEQUD |
| 2234 | UINT64_C(268436679), // VCMPEQUD_rec |
| 2235 | UINT64_C(268435526), // VCMPEQUH |
| 2236 | UINT64_C(268436550), // VCMPEQUH_rec |
| 2237 | UINT64_C(268435911), // VCMPEQUQ |
| 2238 | UINT64_C(268436935), // VCMPEQUQ_rec |
| 2239 | UINT64_C(268435590), // VCMPEQUW |
| 2240 | UINT64_C(268436614), // VCMPEQUW_rec |
| 2241 | UINT64_C(268435910), // VCMPGEFP |
| 2242 | UINT64_C(268436934), // VCMPGEFP_rec |
| 2243 | UINT64_C(268436166), // VCMPGTFP |
| 2244 | UINT64_C(268437190), // VCMPGTFP_rec |
| 2245 | UINT64_C(268436230), // VCMPGTSB |
| 2246 | UINT64_C(268437254), // VCMPGTSB_rec |
| 2247 | UINT64_C(268436423), // VCMPGTSD |
| 2248 | UINT64_C(268437447), // VCMPGTSD_rec |
| 2249 | UINT64_C(268436294), // VCMPGTSH |
| 2250 | UINT64_C(268437318), // VCMPGTSH_rec |
| 2251 | UINT64_C(268436359), // VCMPGTSQ |
| 2252 | UINT64_C(268437383), // VCMPGTSQ_rec |
| 2253 | UINT64_C(268436358), // VCMPGTSW |
| 2254 | UINT64_C(268437382), // VCMPGTSW_rec |
| 2255 | UINT64_C(268435974), // VCMPGTUB |
| 2256 | UINT64_C(268436998), // VCMPGTUB_rec |
| 2257 | UINT64_C(268436167), // VCMPGTUD |
| 2258 | UINT64_C(268437191), // VCMPGTUD_rec |
| 2259 | UINT64_C(268436038), // VCMPGTUH |
| 2260 | UINT64_C(268437062), // VCMPGTUH_rec |
| 2261 | UINT64_C(268436103), // VCMPGTUQ |
| 2262 | UINT64_C(268437127), // VCMPGTUQ_rec |
| 2263 | UINT64_C(268436102), // VCMPGTUW |
| 2264 | UINT64_C(268437126), // VCMPGTUW_rec |
| 2265 | UINT64_C(268435463), // VCMPNEB |
| 2266 | UINT64_C(268436487), // VCMPNEB_rec |
| 2267 | UINT64_C(268435527), // VCMPNEH |
| 2268 | UINT64_C(268436551), // VCMPNEH_rec |
| 2269 | UINT64_C(268435591), // VCMPNEW |
| 2270 | UINT64_C(268436615), // VCMPNEW_rec |
| 2271 | UINT64_C(268435719), // VCMPNEZB |
| 2272 | UINT64_C(268436743), // VCMPNEZB_rec |
| 2273 | UINT64_C(268435783), // VCMPNEZH |
| 2274 | UINT64_C(268436807), // VCMPNEZH_rec |
| 2275 | UINT64_C(268435847), // VCMPNEZW |
| 2276 | UINT64_C(268436871), // VCMPNEZW_rec |
| 2277 | UINT64_C(268435777), // VCMPSQ |
| 2278 | UINT64_C(268435713), // VCMPUQ |
| 2279 | UINT64_C(270009922), // VCNTMBB |
| 2280 | UINT64_C(270403138), // VCNTMBD |
| 2281 | UINT64_C(270140994), // VCNTMBH |
| 2282 | UINT64_C(270272066), // VCNTMBW |
| 2283 | UINT64_C(268436426), // VCTSXS |
| 2284 | UINT64_C(268436426), // VCTSXS_0 |
| 2285 | UINT64_C(268436362), // VCTUXS |
| 2286 | UINT64_C(268436362), // VCTUXS_0 |
| 2287 | UINT64_C(270272002), // VCTZB |
| 2288 | UINT64_C(270468610), // VCTZD |
| 2289 | UINT64_C(268437444), // VCTZDM |
| 2290 | UINT64_C(270337538), // VCTZH |
| 2291 | UINT64_C(268502530), // VCTZLSBB |
| 2292 | UINT64_C(270403074), // VCTZW |
| 2293 | UINT64_C(268436427), // VDIVESD |
| 2294 | UINT64_C(268436235), // VDIVESQ |
| 2295 | UINT64_C(268436363), // VDIVESW |
| 2296 | UINT64_C(268436171), // VDIVEUD |
| 2297 | UINT64_C(268435979), // VDIVEUQ |
| 2298 | UINT64_C(268436107), // VDIVEUW |
| 2299 | UINT64_C(268435915), // VDIVSD |
| 2300 | UINT64_C(268435723), // VDIVSQ |
| 2301 | UINT64_C(268435851), // VDIVSW |
| 2302 | UINT64_C(268435659), // VDIVUD |
| 2303 | UINT64_C(268435467), // VDIVUQ |
| 2304 | UINT64_C(268435595), // VDIVUW |
| 2305 | UINT64_C(268437124), // VEQV |
| 2306 | UINT64_C(268437058), // VEXPANDBM |
| 2307 | UINT64_C(268633666), // VEXPANDDM |
| 2308 | UINT64_C(268502594), // VEXPANDHM |
| 2309 | UINT64_C(268699202), // VEXPANDQM |
| 2310 | UINT64_C(268568130), // VEXPANDWM |
| 2311 | UINT64_C(268435850), // VEXPTEFP |
| 2312 | UINT64_C(268435486), // VEXTDDVLX |
| 2313 | UINT64_C(268435487), // VEXTDDVRX |
| 2314 | UINT64_C(268435480), // VEXTDUBVLX |
| 2315 | UINT64_C(268435481), // VEXTDUBVRX |
| 2316 | UINT64_C(268435482), // VEXTDUHVLX |
| 2317 | UINT64_C(268435483), // VEXTDUHVRX |
| 2318 | UINT64_C(268435484), // VEXTDUWVLX |
| 2319 | UINT64_C(268435485), // VEXTDUWVRX |
| 2320 | UINT64_C(268961346), // VEXTRACTBM |
| 2321 | UINT64_C(268436173), // VEXTRACTD |
| 2322 | UINT64_C(269157954), // VEXTRACTDM |
| 2323 | UINT64_C(269026882), // VEXTRACTHM |
| 2324 | UINT64_C(269223490), // VEXTRACTQM |
| 2325 | UINT64_C(268435981), // VEXTRACTUB |
| 2326 | UINT64_C(268436045), // VEXTRACTUH |
| 2327 | UINT64_C(268436109), // VEXTRACTUW |
| 2328 | UINT64_C(269092418), // VEXTRACTWM |
| 2329 | UINT64_C(270009858), // VEXTSB2D |
| 2330 | UINT64_C(270009858), // VEXTSB2Ds |
| 2331 | UINT64_C(269485570), // VEXTSB2W |
| 2332 | UINT64_C(269485570), // VEXTSB2Ws |
| 2333 | UINT64_C(270206466), // VEXTSD2Q |
| 2334 | UINT64_C(270075394), // VEXTSH2D |
| 2335 | UINT64_C(270075394), // VEXTSH2Ds |
| 2336 | UINT64_C(269551106), // VEXTSH2W |
| 2337 | UINT64_C(269551106), // VEXTSH2Ws |
| 2338 | UINT64_C(270140930), // VEXTSW2D |
| 2339 | UINT64_C(270140930), // VEXTSW2Ds |
| 2340 | UINT64_C(268437005), // VEXTUBLX |
| 2341 | UINT64_C(268437261), // VEXTUBRX |
| 2342 | UINT64_C(268437069), // VEXTUHLX |
| 2343 | UINT64_C(268437325), // VEXTUHRX |
| 2344 | UINT64_C(268437133), // VEXTUWLX |
| 2345 | UINT64_C(268437389), // VEXTUWRX |
| 2346 | UINT64_C(268436748), // VGBBD |
| 2347 | UINT64_C(268436684), // VGNB |
| 2348 | UINT64_C(268435983), // VINSBLX |
| 2349 | UINT64_C(268436239), // VINSBRX |
| 2350 | UINT64_C(268435471), // VINSBVLX |
| 2351 | UINT64_C(268435727), // VINSBVRX |
| 2352 | UINT64_C(268435919), // VINSD |
| 2353 | UINT64_C(268436175), // VINSDLX |
| 2354 | UINT64_C(268436431), // VINSDRX |
| 2355 | UINT64_C(268436237), // VINSERTB |
| 2356 | UINT64_C(268436429), // VINSERTD |
| 2357 | UINT64_C(268436301), // VINSERTH |
| 2358 | UINT64_C(268436365), // VINSERTW |
| 2359 | UINT64_C(268436047), // VINSHLX |
| 2360 | UINT64_C(268436303), // VINSHRX |
| 2361 | UINT64_C(268435535), // VINSHVLX |
| 2362 | UINT64_C(268435791), // VINSHVRX |
| 2363 | UINT64_C(268435663), // VINSW |
| 2364 | UINT64_C(268436111), // VINSWLX |
| 2365 | UINT64_C(268436367), // VINSWRX |
| 2366 | UINT64_C(268435599), // VINSWVLX |
| 2367 | UINT64_C(268435855), // VINSWVRX |
| 2368 | UINT64_C(268435914), // VLOGEFP |
| 2369 | UINT64_C(268435502), // VMADDFP |
| 2370 | UINT64_C(268436490), // VMAXFP |
| 2371 | UINT64_C(268435714), // VMAXSB |
| 2372 | UINT64_C(268435906), // VMAXSD |
| 2373 | UINT64_C(268435778), // VMAXSH |
| 2374 | UINT64_C(268435842), // VMAXSW |
| 2375 | UINT64_C(268435458), // VMAXUB |
| 2376 | UINT64_C(268435650), // VMAXUD |
| 2377 | UINT64_C(268435522), // VMAXUH |
| 2378 | UINT64_C(268435586), // VMAXUW |
| 2379 | UINT64_C(268435488), // VMHADDSHS |
| 2380 | UINT64_C(268435489), // VMHRADDSHS |
| 2381 | UINT64_C(268436554), // VMINFP |
| 2382 | UINT64_C(268436226), // VMINSB |
| 2383 | UINT64_C(268436418), // VMINSD |
| 2384 | UINT64_C(268436290), // VMINSH |
| 2385 | UINT64_C(268436354), // VMINSW |
| 2386 | UINT64_C(268435970), // VMINUB |
| 2387 | UINT64_C(268436162), // VMINUD |
| 2388 | UINT64_C(268436034), // VMINUH |
| 2389 | UINT64_C(268436098), // VMINUW |
| 2390 | UINT64_C(268435490), // VMLADDUHM |
| 2391 | UINT64_C(268437451), // VMODSD |
| 2392 | UINT64_C(268437259), // VMODSQ |
| 2393 | UINT64_C(268437387), // VMODSW |
| 2394 | UINT64_C(268437195), // VMODUD |
| 2395 | UINT64_C(268437003), // VMODUQ |
| 2396 | UINT64_C(268437131), // VMODUW |
| 2397 | UINT64_C(268437388), // VMRGEW |
| 2398 | UINT64_C(268435468), // VMRGHB |
| 2399 | UINT64_C(268435532), // VMRGHH |
| 2400 | UINT64_C(268435596), // VMRGHW |
| 2401 | UINT64_C(268435724), // VMRGLB |
| 2402 | UINT64_C(268435788), // VMRGLH |
| 2403 | UINT64_C(268435852), // VMRGLW |
| 2404 | UINT64_C(268437132), // VMRGOW |
| 2405 | UINT64_C(268435479), // VMSUMCUD |
| 2406 | UINT64_C(268435493), // VMSUMMBM |
| 2407 | UINT64_C(268435496), // VMSUMSHM |
| 2408 | UINT64_C(268435497), // VMSUMSHS |
| 2409 | UINT64_C(268435492), // VMSUMUBM |
| 2410 | UINT64_C(268435491), // VMSUMUDM |
| 2411 | UINT64_C(268435494), // VMSUMUHM |
| 2412 | UINT64_C(268435495), // VMSUMUHS |
| 2413 | UINT64_C(268435457), // VMUL10CUQ |
| 2414 | UINT64_C(268435521), // VMUL10ECUQ |
| 2415 | UINT64_C(268436033), // VMUL10EUQ |
| 2416 | UINT64_C(268435969), // VMUL10UQ |
| 2417 | UINT64_C(268436232), // VMULESB |
| 2418 | UINT64_C(268436424), // VMULESD |
| 2419 | UINT64_C(268436296), // VMULESH |
| 2420 | UINT64_C(268436360), // VMULESW |
| 2421 | UINT64_C(268435976), // VMULEUB |
| 2422 | UINT64_C(268436168), // VMULEUD |
| 2423 | UINT64_C(268436040), // VMULEUH |
| 2424 | UINT64_C(268436104), // VMULEUW |
| 2425 | UINT64_C(268436425), // VMULHSD |
| 2426 | UINT64_C(268436361), // VMULHSW |
| 2427 | UINT64_C(268436169), // VMULHUD |
| 2428 | UINT64_C(268436105), // VMULHUW |
| 2429 | UINT64_C(268435913), // VMULLD |
| 2430 | UINT64_C(268435720), // VMULOSB |
| 2431 | UINT64_C(268435912), // VMULOSD |
| 2432 | UINT64_C(268435784), // VMULOSH |
| 2433 | UINT64_C(268435848), // VMULOSW |
| 2434 | UINT64_C(268435464), // VMULOUB |
| 2435 | UINT64_C(268435656), // VMULOUD |
| 2436 | UINT64_C(268435528), // VMULOUH |
| 2437 | UINT64_C(268435592), // VMULOUW |
| 2438 | UINT64_C(268435593), // VMULUWM |
| 2439 | UINT64_C(268436868), // VNAND |
| 2440 | UINT64_C(268436808), // VNCIPHER |
| 2441 | UINT64_C(268436809), // VNCIPHERLAST |
| 2442 | UINT64_C(268895746), // VNEGD |
| 2443 | UINT64_C(268830210), // VNEGW |
| 2444 | UINT64_C(268435503), // VNMSUBFP |
| 2445 | UINT64_C(268436740), // VNOR |
| 2446 | UINT64_C(268436612), // VOR |
| 2447 | UINT64_C(268436804), // VORC |
| 2448 | UINT64_C(268436941), // VPDEPD |
| 2449 | UINT64_C(268435499), // VPERM |
| 2450 | UINT64_C(268435515), // VPERMR |
| 2451 | UINT64_C(268435501), // VPERMXOR |
| 2452 | UINT64_C(268436877), // VPEXTD |
| 2453 | UINT64_C(268436238), // VPKPX |
| 2454 | UINT64_C(268436942), // VPKSDSS |
| 2455 | UINT64_C(268436814), // VPKSDUS |
| 2456 | UINT64_C(268435854), // VPKSHSS |
| 2457 | UINT64_C(268435726), // VPKSHUS |
| 2458 | UINT64_C(268435918), // VPKSWSS |
| 2459 | UINT64_C(268435790), // VPKSWUS |
| 2460 | UINT64_C(268436558), // VPKUDUM |
| 2461 | UINT64_C(268436686), // VPKUDUS |
| 2462 | UINT64_C(268435470), // VPKUHUM |
| 2463 | UINT64_C(268435598), // VPKUHUS |
| 2464 | UINT64_C(268435534), // VPKUWUM |
| 2465 | UINT64_C(268435662), // VPKUWUS |
| 2466 | UINT64_C(268436488), // VPMSUMB |
| 2467 | UINT64_C(268436680), // VPMSUMD |
| 2468 | UINT64_C(268436552), // VPMSUMH |
| 2469 | UINT64_C(268436616), // VPMSUMW |
| 2470 | UINT64_C(268437251), // VPOPCNTB |
| 2471 | UINT64_C(268437443), // VPOPCNTD |
| 2472 | UINT64_C(268437315), // VPOPCNTH |
| 2473 | UINT64_C(268437379), // VPOPCNTW |
| 2474 | UINT64_C(269026818), // VPRTYBD |
| 2475 | UINT64_C(269092354), // VPRTYBQ |
| 2476 | UINT64_C(268961282), // VPRTYBW |
| 2477 | UINT64_C(268435722), // VREFP |
| 2478 | UINT64_C(268436170), // VRFIM |
| 2479 | UINT64_C(268435978), // VRFIN |
| 2480 | UINT64_C(268436106), // VRFIP |
| 2481 | UINT64_C(268436042), // VRFIZ |
| 2482 | UINT64_C(268435460), // VRLB |
| 2483 | UINT64_C(268435652), // VRLD |
| 2484 | UINT64_C(268435653), // VRLDMI |
| 2485 | UINT64_C(268435909), // VRLDNM |
| 2486 | UINT64_C(268435524), // VRLH |
| 2487 | UINT64_C(268435461), // VRLQ |
| 2488 | UINT64_C(268435525), // VRLQMI |
| 2489 | UINT64_C(268435781), // VRLQNM |
| 2490 | UINT64_C(268435588), // VRLW |
| 2491 | UINT64_C(268435589), // VRLWMI |
| 2492 | UINT64_C(268435845), // VRLWNM |
| 2493 | UINT64_C(268435786), // VRSQRTEFP |
| 2494 | UINT64_C(268436936), // VSBOX |
| 2495 | UINT64_C(268435498), // VSEL |
| 2496 | UINT64_C(268437186), // VSHASIGMAD |
| 2497 | UINT64_C(268437122), // VSHASIGMAW |
| 2498 | UINT64_C(268435908), // VSL |
| 2499 | UINT64_C(268435716), // VSLB |
| 2500 | UINT64_C(268436932), // VSLD |
| 2501 | UINT64_C(268435478), // VSLDBI |
| 2502 | UINT64_C(268435500), // VSLDOI |
| 2503 | UINT64_C(268435780), // VSLH |
| 2504 | UINT64_C(268436492), // VSLO |
| 2505 | UINT64_C(268435717), // VSLQ |
| 2506 | UINT64_C(268437316), // VSLV |
| 2507 | UINT64_C(268435844), // VSLW |
| 2508 | UINT64_C(268435980), // VSPLTB |
| 2509 | UINT64_C(268435980), // VSPLTBs |
| 2510 | UINT64_C(268436044), // VSPLTH |
| 2511 | UINT64_C(268436044), // VSPLTHs |
| 2512 | UINT64_C(268436236), // VSPLTISB |
| 2513 | UINT64_C(268436300), // VSPLTISH |
| 2514 | UINT64_C(268436364), // VSPLTISW |
| 2515 | UINT64_C(268436108), // VSPLTW |
| 2516 | UINT64_C(268436164), // VSR |
| 2517 | UINT64_C(268436228), // VSRAB |
| 2518 | UINT64_C(268436420), // VSRAD |
| 2519 | UINT64_C(268436292), // VSRAH |
| 2520 | UINT64_C(268436229), // VSRAQ |
| 2521 | UINT64_C(268436356), // VSRAW |
| 2522 | UINT64_C(268435972), // VSRB |
| 2523 | UINT64_C(268437188), // VSRD |
| 2524 | UINT64_C(268435990), // VSRDBI |
| 2525 | UINT64_C(268436036), // VSRH |
| 2526 | UINT64_C(268436556), // VSRO |
| 2527 | UINT64_C(268435973), // VSRQ |
| 2528 | UINT64_C(268437252), // VSRV |
| 2529 | UINT64_C(268436100), // VSRW |
| 2530 | UINT64_C(268435469), // VSTRIBL |
| 2531 | UINT64_C(268436493), // VSTRIBL_rec |
| 2532 | UINT64_C(268501005), // VSTRIBR |
| 2533 | UINT64_C(268502029), // VSTRIBR_rec |
| 2534 | UINT64_C(268566541), // VSTRIHL |
| 2535 | UINT64_C(268567565), // VSTRIHL_rec |
| 2536 | UINT64_C(268632077), // VSTRIHR |
| 2537 | UINT64_C(268633101), // VSTRIHR_rec |
| 2538 | UINT64_C(268436800), // VSUBCUQ |
| 2539 | UINT64_C(268436864), // VSUBCUW |
| 2540 | UINT64_C(268435519), // VSUBECUQ |
| 2541 | UINT64_C(268435518), // VSUBEUQM |
| 2542 | UINT64_C(268435530), // VSUBFP |
| 2543 | UINT64_C(268437248), // VSUBSBS |
| 2544 | UINT64_C(268437312), // VSUBSHS |
| 2545 | UINT64_C(268437376), // VSUBSWS |
| 2546 | UINT64_C(268436480), // VSUBUBM |
| 2547 | UINT64_C(268436992), // VSUBUBS |
| 2548 | UINT64_C(268436672), // VSUBUDM |
| 2549 | UINT64_C(268436544), // VSUBUHM |
| 2550 | UINT64_C(268437056), // VSUBUHS |
| 2551 | UINT64_C(268436736), // VSUBUQM |
| 2552 | UINT64_C(268436608), // VSUBUWM |
| 2553 | UINT64_C(268437120), // VSUBUWS |
| 2554 | UINT64_C(268437128), // VSUM2SWS |
| 2555 | UINT64_C(268437256), // VSUM4SBS |
| 2556 | UINT64_C(268437064), // VSUM4SHS |
| 2557 | UINT64_C(268437000), // VSUM4UBS |
| 2558 | UINT64_C(268437384), // VSUMSWS |
| 2559 | UINT64_C(268436302), // VUPKHPX |
| 2560 | UINT64_C(268435982), // VUPKHSB |
| 2561 | UINT64_C(268436046), // VUPKHSH |
| 2562 | UINT64_C(268437070), // VUPKHSW |
| 2563 | UINT64_C(268436430), // VUPKLPX |
| 2564 | UINT64_C(268436110), // VUPKLSB |
| 2565 | UINT64_C(268436174), // VUPKLSH |
| 2566 | UINT64_C(268437198), // VUPKLSW |
| 2567 | UINT64_C(268436676), // VXOR |
| 2568 | UINT64_C(268436676), // V_SET0 |
| 2569 | UINT64_C(268436676), // V_SET0B |
| 2570 | UINT64_C(268436676), // V_SET0H |
| 2571 | UINT64_C(270467980), // V_SETALLONES |
| 2572 | UINT64_C(270467980), // V_SETALLONESB |
| 2573 | UINT64_C(270467980), // V_SETALLONESH |
| 2574 | UINT64_C(2080374844), // WAIT |
| 2575 | UINT64_C(2080374844), // WAITP10 |
| 2576 | UINT64_C(2080375046), // WRTEE |
| 2577 | UINT64_C(2080375110), // WRTEEI |
| 2578 | UINT64_C(2080375416), // XOR |
| 2579 | UINT64_C(2080375416), // XOR8 |
| 2580 | UINT64_C(2080375417), // XOR8_rec |
| 2581 | UINT64_C(1744830464), // XORI |
| 2582 | UINT64_C(1744830464), // XORI8 |
| 2583 | UINT64_C(1811939328), // XORIS |
| 2584 | UINT64_C(1811939328), // XORIS8 |
| 2585 | UINT64_C(2080375417), // XOR_rec |
| 2586 | UINT64_C(4026533220), // XSABSDP |
| 2587 | UINT64_C(4227860040), // XSABSQP |
| 2588 | UINT64_C(4026532096), // XSADDDP |
| 2589 | UINT64_C(4227858440), // XSADDQP |
| 2590 | UINT64_C(4227858441), // XSADDQPO |
| 2591 | UINT64_C(4026531840), // XSADDSP |
| 2592 | UINT64_C(4026531864), // XSCMPEQDP |
| 2593 | UINT64_C(4227858568), // XSCMPEQQP |
| 2594 | UINT64_C(4026532312), // XSCMPEXPDP |
| 2595 | UINT64_C(4227858760), // XSCMPEXPQP |
| 2596 | UINT64_C(4026531992), // XSCMPGEDP |
| 2597 | UINT64_C(4227858824), // XSCMPGEQP |
| 2598 | UINT64_C(4026531928), // XSCMPGTDP |
| 2599 | UINT64_C(4227858888), // XSCMPGTQP |
| 2600 | UINT64_C(4026532184), // XSCMPODP |
| 2601 | UINT64_C(4227858696), // XSCMPOQP |
| 2602 | UINT64_C(4026532120), // XSCMPUDP |
| 2603 | UINT64_C(4227859720), // XSCMPUQP |
| 2604 | UINT64_C(4026533248), // XSCPSGNDP |
| 2605 | UINT64_C(4227858632), // XSCPSGNQP |
| 2606 | UINT64_C(4027647340), // XSCVDPHP |
| 2607 | UINT64_C(4229301896), // XSCVDPQP |
| 2608 | UINT64_C(4026532900), // XSCVDPSP |
| 2609 | UINT64_C(4026532908), // XSCVDPSPN |
| 2610 | UINT64_C(4026533216), // XSCVDPSXDS |
| 2611 | UINT64_C(4026533216), // XSCVDPSXDSs |
| 2612 | UINT64_C(4026532192), // XSCVDPSXWS |
| 2613 | UINT64_C(4026532192), // XSCVDPSXWSs |
| 2614 | UINT64_C(4026533152), // XSCVDPUXDS |
| 2615 | UINT64_C(4026533152), // XSCVDPUXDSs |
| 2616 | UINT64_C(4026532128), // XSCVDPUXWS |
| 2617 | UINT64_C(4026532128), // XSCVDPUXWSs |
| 2618 | UINT64_C(4027581804), // XSCVHPDP |
| 2619 | UINT64_C(4229170824), // XSCVQPDP |
| 2620 | UINT64_C(4229170825), // XSCVQPDPO |
| 2621 | UINT64_C(4229498504), // XSCVQPSDZ |
| 2622 | UINT64_C(4228384392), // XSCVQPSQZ |
| 2623 | UINT64_C(4228449928), // XSCVQPSWZ |
| 2624 | UINT64_C(4228974216), // XSCVQPUDZ |
| 2625 | UINT64_C(4227860104), // XSCVQPUQZ |
| 2626 | UINT64_C(4227925640), // XSCVQPUWZ |
| 2627 | UINT64_C(4228515464), // XSCVSDQP |
| 2628 | UINT64_C(4026533156), // XSCVSPDP |
| 2629 | UINT64_C(4026533164), // XSCVSPDPN |
| 2630 | UINT64_C(4228581000), // XSCVSQQP |
| 2631 | UINT64_C(4026533344), // XSCVSXDDP |
| 2632 | UINT64_C(4026533088), // XSCVSXDSP |
| 2633 | UINT64_C(4227991176), // XSCVUDQP |
| 2634 | UINT64_C(4228056712), // XSCVUQQP |
| 2635 | UINT64_C(4026533280), // XSCVUXDDP |
| 2636 | UINT64_C(4026533024), // XSCVUXDSP |
| 2637 | UINT64_C(4026532288), // XSDIVDP |
| 2638 | UINT64_C(4227859528), // XSDIVQP |
| 2639 | UINT64_C(4227859529), // XSDIVQPO |
| 2640 | UINT64_C(4026532032), // XSDIVSP |
| 2641 | UINT64_C(4026533676), // XSIEXPDP |
| 2642 | UINT64_C(4227860168), // XSIEXPQP |
| 2643 | UINT64_C(4026532104), // XSMADDADP |
| 2644 | UINT64_C(4026531848), // XSMADDASP |
| 2645 | UINT64_C(4026532168), // XSMADDMDP |
| 2646 | UINT64_C(4026531912), // XSMADDMSP |
| 2647 | UINT64_C(4227859208), // XSMADDQP |
| 2648 | UINT64_C(4227859209), // XSMADDQPO |
| 2649 | UINT64_C(4026532864), // XSMAXCDP |
| 2650 | UINT64_C(4227859784), // XSMAXCQP |
| 2651 | UINT64_C(4026533120), // XSMAXDP |
| 2652 | UINT64_C(4026532992), // XSMAXJDP |
| 2653 | UINT64_C(4026532928), // XSMINCDP |
| 2654 | UINT64_C(4227859912), // XSMINCQP |
| 2655 | UINT64_C(4026533184), // XSMINDP |
| 2656 | UINT64_C(4026533056), // XSMINJDP |
| 2657 | UINT64_C(4026532232), // XSMSUBADP |
| 2658 | UINT64_C(4026531976), // XSMSUBASP |
| 2659 | UINT64_C(4026532296), // XSMSUBMDP |
| 2660 | UINT64_C(4026532040), // XSMSUBMSP |
| 2661 | UINT64_C(4227859272), // XSMSUBQP |
| 2662 | UINT64_C(4227859273), // XSMSUBQPO |
| 2663 | UINT64_C(4026532224), // XSMULDP |
| 2664 | UINT64_C(4227858504), // XSMULQP |
| 2665 | UINT64_C(4227858505), // XSMULQPO |
| 2666 | UINT64_C(4026531968), // XSMULSP |
| 2667 | UINT64_C(4026533284), // XSNABSDP |
| 2668 | UINT64_C(4026533284), // XSNABSDPs |
| 2669 | UINT64_C(4228384328), // XSNABSQP |
| 2670 | UINT64_C(4026533348), // XSNEGDP |
| 2671 | UINT64_C(4228908616), // XSNEGQP |
| 2672 | UINT64_C(4026533128), // XSNMADDADP |
| 2673 | UINT64_C(4026532872), // XSNMADDASP |
| 2674 | UINT64_C(4026533192), // XSNMADDMDP |
| 2675 | UINT64_C(4026532936), // XSNMADDMSP |
| 2676 | UINT64_C(4227859336), // XSNMADDQP |
| 2677 | UINT64_C(4227859337), // XSNMADDQPO |
| 2678 | UINT64_C(4026533256), // XSNMSUBADP |
| 2679 | UINT64_C(4026533000), // XSNMSUBASP |
| 2680 | UINT64_C(4026533320), // XSNMSUBMDP |
| 2681 | UINT64_C(4026533064), // XSNMSUBMSP |
| 2682 | UINT64_C(4227859400), // XSNMSUBQP |
| 2683 | UINT64_C(4227859401), // XSNMSUBQPO |
| 2684 | UINT64_C(4026532132), // XSRDPI |
| 2685 | UINT64_C(4026532268), // XSRDPIC |
| 2686 | UINT64_C(4026532324), // XSRDPIM |
| 2687 | UINT64_C(4026532260), // XSRDPIP |
| 2688 | UINT64_C(4026532196), // XSRDPIZ |
| 2689 | UINT64_C(4026532200), // XSREDP |
| 2690 | UINT64_C(4026531944), // XSRESP |
| 2691 | UINT64_C(4227858442), // XSRQPI |
| 2692 | UINT64_C(4227858443), // XSRQPIX |
| 2693 | UINT64_C(4227858506), // XSRQPXP |
| 2694 | UINT64_C(4026532964), // XSRSP |
| 2695 | UINT64_C(4026532136), // XSRSQRTEDP |
| 2696 | UINT64_C(4026531880), // XSRSQRTESP |
| 2697 | UINT64_C(4026532140), // XSSQRTDP |
| 2698 | UINT64_C(4229629512), // XSSQRTQP |
| 2699 | UINT64_C(4229629513), // XSSQRTQPO |
| 2700 | UINT64_C(4026531884), // XSSQRTSP |
| 2701 | UINT64_C(4026532160), // XSSUBDP |
| 2702 | UINT64_C(4227859464), // XSSUBQP |
| 2703 | UINT64_C(4227859465), // XSSUBQPO |
| 2704 | UINT64_C(4026531904), // XSSUBSP |
| 2705 | UINT64_C(4026532328), // XSTDIVDP |
| 2706 | UINT64_C(4026532264), // XSTSQRTDP |
| 2707 | UINT64_C(4026533288), // XSTSTDCDP |
| 2708 | UINT64_C(4227859848), // XSTSTDCQP |
| 2709 | UINT64_C(4026533032), // XSTSTDCSP |
| 2710 | UINT64_C(4026533228), // XSXEXPDP |
| 2711 | UINT64_C(4227991112), // XSXEXPQP |
| 2712 | UINT64_C(4026598764), // XSXSIGDP |
| 2713 | UINT64_C(4229039688), // XSXSIGQP |
| 2714 | UINT64_C(4026533732), // XVABSDP |
| 2715 | UINT64_C(4026533476), // XVABSSP |
| 2716 | UINT64_C(4026532608), // XVADDDP |
| 2717 | UINT64_C(4026532352), // XVADDSP |
| 2718 | UINT64_C(3959423384), // XVBF16GER2 |
| 2719 | UINT64_C(3959424912), // XVBF16GER2NN |
| 2720 | UINT64_C(3959423888), // XVBF16GER2NP |
| 2721 | UINT64_C(3959424400), // XVBF16GER2PN |
| 2722 | UINT64_C(3959423376), // XVBF16GER2PP |
| 2723 | UINT64_C(3959423384), // XVBF16GER2W |
| 2724 | UINT64_C(3959424912), // XVBF16GER2WNN |
| 2725 | UINT64_C(3959423888), // XVBF16GER2WNP |
| 2726 | UINT64_C(3959424400), // XVBF16GER2WPN |
| 2727 | UINT64_C(3959423376), // XVBF16GER2WPP |
| 2728 | UINT64_C(4026532632), // XVCMPEQDP |
| 2729 | UINT64_C(4026533656), // XVCMPEQDP_rec |
| 2730 | UINT64_C(4026532376), // XVCMPEQSP |
| 2731 | UINT64_C(4026533400), // XVCMPEQSP_rec |
| 2732 | UINT64_C(4026532760), // XVCMPGEDP |
| 2733 | UINT64_C(4026533784), // XVCMPGEDP_rec |
| 2734 | UINT64_C(4026532504), // XVCMPGESP |
| 2735 | UINT64_C(4026533528), // XVCMPGESP_rec |
| 2736 | UINT64_C(4026532696), // XVCMPGTDP |
| 2737 | UINT64_C(4026533720), // XVCMPGTDP_rec |
| 2738 | UINT64_C(4026532440), // XVCMPGTSP |
| 2739 | UINT64_C(4026533464), // XVCMPGTSP_rec |
| 2740 | UINT64_C(4026533760), // XVCPSGNDP |
| 2741 | UINT64_C(4026533504), // XVCPSGNSP |
| 2742 | UINT64_C(4027582316), // XVCVBF16SPN |
| 2743 | UINT64_C(4026533412), // XVCVDPSP |
| 2744 | UINT64_C(4026533728), // XVCVDPSXDS |
| 2745 | UINT64_C(4026532704), // XVCVDPSXWS |
| 2746 | UINT64_C(4026533664), // XVCVDPUXDS |
| 2747 | UINT64_C(4026532640), // XVCVDPUXWS |
| 2748 | UINT64_C(4028106604), // XVCVHPSP |
| 2749 | UINT64_C(4027647852), // XVCVSPBF16 |
| 2750 | UINT64_C(4026533668), // XVCVSPDP |
| 2751 | UINT64_C(4028172140), // XVCVSPHP |
| 2752 | UINT64_C(4026533472), // XVCVSPSXDS |
| 2753 | UINT64_C(4026532448), // XVCVSPSXWS |
| 2754 | UINT64_C(4026533408), // XVCVSPUXDS |
| 2755 | UINT64_C(4026532384), // XVCVSPUXWS |
| 2756 | UINT64_C(4026533856), // XVCVSXDDP |
| 2757 | UINT64_C(4026533600), // XVCVSXDSP |
| 2758 | UINT64_C(4026532832), // XVCVSXWDP |
| 2759 | UINT64_C(4026532576), // XVCVSXWSP |
| 2760 | UINT64_C(4026533792), // XVCVUXDDP |
| 2761 | UINT64_C(4026533536), // XVCVUXDSP |
| 2762 | UINT64_C(4026532768), // XVCVUXWDP |
| 2763 | UINT64_C(4026532512), // XVCVUXWSP |
| 2764 | UINT64_C(4026532800), // XVDIVDP |
| 2765 | UINT64_C(4026532544), // XVDIVSP |
| 2766 | UINT64_C(3959423128), // XVF16GER2 |
| 2767 | UINT64_C(3959424656), // XVF16GER2NN |
| 2768 | UINT64_C(3959423632), // XVF16GER2NP |
| 2769 | UINT64_C(3959424144), // XVF16GER2PN |
| 2770 | UINT64_C(3959423120), // XVF16GER2PP |
| 2771 | UINT64_C(3959423128), // XVF16GER2W |
| 2772 | UINT64_C(3959424656), // XVF16GER2WNN |
| 2773 | UINT64_C(3959423632), // XVF16GER2WNP |
| 2774 | UINT64_C(3959424144), // XVF16GER2WPN |
| 2775 | UINT64_C(3959423120), // XVF16GER2WPP |
| 2776 | UINT64_C(3959423192), // XVF32GER |
| 2777 | UINT64_C(3959424720), // XVF32GERNN |
| 2778 | UINT64_C(3959423696), // XVF32GERNP |
| 2779 | UINT64_C(3959424208), // XVF32GERPN |
| 2780 | UINT64_C(3959423184), // XVF32GERPP |
| 2781 | UINT64_C(3959423192), // XVF32GERW |
| 2782 | UINT64_C(3959424720), // XVF32GERWNN |
| 2783 | UINT64_C(3959423696), // XVF32GERWNP |
| 2784 | UINT64_C(3959424208), // XVF32GERWPN |
| 2785 | UINT64_C(3959423184), // XVF32GERWPP |
| 2786 | UINT64_C(3959423448), // XVF64GER |
| 2787 | UINT64_C(3959424976), // XVF64GERNN |
| 2788 | UINT64_C(3959423952), // XVF64GERNP |
| 2789 | UINT64_C(3959424464), // XVF64GERPN |
| 2790 | UINT64_C(3959423440), // XVF64GERPP |
| 2791 | UINT64_C(3959423448), // XVF64GERW |
| 2792 | UINT64_C(3959424976), // XVF64GERWNN |
| 2793 | UINT64_C(3959423952), // XVF64GERWNP |
| 2794 | UINT64_C(3959424464), // XVF64GERWPN |
| 2795 | UINT64_C(3959423440), // XVF64GERWPP |
| 2796 | UINT64_C(3959423576), // XVI16GER2 |
| 2797 | UINT64_C(3959423832), // XVI16GER2PP |
| 2798 | UINT64_C(3959423320), // XVI16GER2S |
| 2799 | UINT64_C(3959423312), // XVI16GER2SPP |
| 2800 | UINT64_C(3959423320), // XVI16GER2SW |
| 2801 | UINT64_C(3959423312), // XVI16GER2SWPP |
| 2802 | UINT64_C(3959423576), // XVI16GER2W |
| 2803 | UINT64_C(3959423832), // XVI16GER2WPP |
| 2804 | UINT64_C(3959423256), // XVI4GER8 |
| 2805 | UINT64_C(3959423248), // XVI4GER8PP |
| 2806 | UINT64_C(3959423256), // XVI4GER8W |
| 2807 | UINT64_C(3959423248), // XVI4GER8WPP |
| 2808 | UINT64_C(3959423000), // XVI8GER4 |
| 2809 | UINT64_C(3959422992), // XVI8GER4PP |
| 2810 | UINT64_C(3959423768), // XVI8GER4SPP |
| 2811 | UINT64_C(3959423000), // XVI8GER4W |
| 2812 | UINT64_C(3959422992), // XVI8GER4WPP |
| 2813 | UINT64_C(3959423768), // XVI8GER4WSPP |
| 2814 | UINT64_C(4026533824), // XVIEXPDP |
| 2815 | UINT64_C(4026533568), // XVIEXPSP |
| 2816 | UINT64_C(4026532616), // XVMADDADP |
| 2817 | UINT64_C(4026532360), // XVMADDASP |
| 2818 | UINT64_C(4026532680), // XVMADDMDP |
| 2819 | UINT64_C(4026532424), // XVMADDMSP |
| 2820 | UINT64_C(4026533632), // XVMAXDP |
| 2821 | UINT64_C(4026533376), // XVMAXSP |
| 2822 | UINT64_C(4026533696), // XVMINDP |
| 2823 | UINT64_C(4026533440), // XVMINSP |
| 2824 | UINT64_C(4026532744), // XVMSUBADP |
| 2825 | UINT64_C(4026532488), // XVMSUBASP |
| 2826 | UINT64_C(4026532808), // XVMSUBMDP |
| 2827 | UINT64_C(4026532552), // XVMSUBMSP |
| 2828 | UINT64_C(4026532736), // XVMULDP |
| 2829 | UINT64_C(4026532480), // XVMULSP |
| 2830 | UINT64_C(4026533796), // XVNABSDP |
| 2831 | UINT64_C(4026533540), // XVNABSSP |
| 2832 | UINT64_C(4026533860), // XVNEGDP |
| 2833 | UINT64_C(4026533604), // XVNEGSP |
| 2834 | UINT64_C(4026533640), // XVNMADDADP |
| 2835 | UINT64_C(4026533384), // XVNMADDASP |
| 2836 | UINT64_C(4026533704), // XVNMADDMDP |
| 2837 | UINT64_C(4026533448), // XVNMADDMSP |
| 2838 | UINT64_C(4026533768), // XVNMSUBADP |
| 2839 | UINT64_C(4026533512), // XVNMSUBASP |
| 2840 | UINT64_C(4026533832), // XVNMSUBMDP |
| 2841 | UINT64_C(4026533576), // XVNMSUBMSP |
| 2842 | UINT64_C(4026532644), // XVRDPI |
| 2843 | UINT64_C(4026532780), // XVRDPIC |
| 2844 | UINT64_C(4026532836), // XVRDPIM |
| 2845 | UINT64_C(4026532772), // XVRDPIP |
| 2846 | UINT64_C(4026532708), // XVRDPIZ |
| 2847 | UINT64_C(4026532712), // XVREDP |
| 2848 | UINT64_C(4026532456), // XVRESP |
| 2849 | UINT64_C(4026532388), // XVRSPI |
| 2850 | UINT64_C(4026532524), // XVRSPIC |
| 2851 | UINT64_C(4026532580), // XVRSPIM |
| 2852 | UINT64_C(4026532516), // XVRSPIP |
| 2853 | UINT64_C(4026532452), // XVRSPIZ |
| 2854 | UINT64_C(4026532648), // XVRSQRTEDP |
| 2855 | UINT64_C(4026532392), // XVRSQRTESP |
| 2856 | UINT64_C(4026532652), // XVSQRTDP |
| 2857 | UINT64_C(4026532396), // XVSQRTSP |
| 2858 | UINT64_C(4026532672), // XVSUBDP |
| 2859 | UINT64_C(4026532416), // XVSUBSP |
| 2860 | UINT64_C(4026532840), // XVTDIVDP |
| 2861 | UINT64_C(4026532584), // XVTDIVSP |
| 2862 | UINT64_C(4026664812), // XVTLSBB |
| 2863 | UINT64_C(4026532776), // XVTSQRTDP |
| 2864 | UINT64_C(4026532520), // XVTSQRTSP |
| 2865 | UINT64_C(4026533800), // XVTSTDCDP |
| 2866 | UINT64_C(4026533544), // XVTSTDCSP |
| 2867 | UINT64_C(4026533740), // XVXEXPDP |
| 2868 | UINT64_C(4027058028), // XVXEXPSP |
| 2869 | UINT64_C(4026599276), // XVXSIGDP |
| 2870 | UINT64_C(4027123564), // XVXSIGSP |
| 2871 | UINT64_C(360287972404232192), // XXBLENDVB |
| 2872 | UINT64_C(360287972404232240), // XXBLENDVD |
| 2873 | UINT64_C(360287972404232208), // XXBLENDVH |
| 2874 | UINT64_C(360287972404232224), // XXBLENDVW |
| 2875 | UINT64_C(4028041068), // XXBRD |
| 2876 | UINT64_C(4026992492), // XXBRH |
| 2877 | UINT64_C(4028565356), // XXBRQ |
| 2878 | UINT64_C(4027516780), // XXBRW |
| 2879 | UINT64_C(360287972471341072), // XXEVAL |
| 2880 | UINT64_C(4026532500), // XXEXTRACTUW |
| 2881 | UINT64_C(4026533672), // XXGENPCVBM |
| 2882 | UINT64_C(4026533738), // XXGENPCVDM |
| 2883 | UINT64_C(4026533674), // XXGENPCVHM |
| 2884 | UINT64_C(4026533736), // XXGENPCVWM |
| 2885 | UINT64_C(4026532564), // XXINSERTW |
| 2886 | UINT64_C(4026532880), // XXLAND |
| 2887 | UINT64_C(4026532944), // XXLANDC |
| 2888 | UINT64_C(4026533328), // XXLEQV |
| 2889 | UINT64_C(4026533328), // XXLEQVOnes |
| 2890 | UINT64_C(4026533264), // XXLNAND |
| 2891 | UINT64_C(4026533136), // XXLNOR |
| 2892 | UINT64_C(4026533008), // XXLOR |
| 2893 | UINT64_C(4026533200), // XXLORC |
| 2894 | UINT64_C(4026533008), // XXLORf |
| 2895 | UINT64_C(4026533072), // XXLXOR |
| 2896 | UINT64_C(4026533072), // XXLXORdpz |
| 2897 | UINT64_C(4026533072), // XXLXORspz |
| 2898 | UINT64_C(4026533072), // XXLXORz |
| 2899 | UINT64_C(2080375138), // XXMFACC |
| 2900 | UINT64_C(2080375138), // XXMFACCW |
| 2901 | UINT64_C(4026531984), // XXMRGHW |
| 2902 | UINT64_C(4026532240), // XXMRGLW |
| 2903 | UINT64_C(2080440674), // XXMTACC |
| 2904 | UINT64_C(2080440674), // XXMTACCW |
| 2905 | UINT64_C(4026532048), // XXPERM |
| 2906 | UINT64_C(4026531920), // XXPERMDI |
| 2907 | UINT64_C(4026531920), // XXPERMDIs |
| 2908 | UINT64_C(4026532304), // XXPERMR |
| 2909 | UINT64_C(360287972471341056), // XXPERMX |
| 2910 | UINT64_C(4026531888), // XXSEL |
| 2911 | UINT64_C(2080571746), // XXSETACCZ |
| 2912 | UINT64_C(4026531856), // XXSLDWI |
| 2913 | UINT64_C(4026531856), // XXSLDWIs |
| 2914 | UINT64_C(360287972337123328), // XXSPLTI32DX |
| 2915 | UINT64_C(4026532560), // XXSPLTIB |
| 2916 | UINT64_C(360287972337385472), // XXSPLTIDP |
| 2917 | UINT64_C(360287972337516544), // XXSPLTIW |
| 2918 | UINT64_C(4026532496), // XXSPLTW |
| 2919 | UINT64_C(4026532496), // XXSPLTWs |
| 2920 | UINT64_C(1073741824), // gBC |
| 2921 | UINT64_C(1073741826), // gBCA |
| 2922 | UINT64_C(1073741826), // gBCAat |
| 2923 | UINT64_C(1275069472), // gBCCTR |
| 2924 | UINT64_C(1275069473), // gBCCTRL |
| 2925 | UINT64_C(1073741825), // gBCL |
| 2926 | UINT64_C(1073741827), // gBCLA |
| 2927 | UINT64_C(1073741827), // gBCLAat |
| 2928 | UINT64_C(1275068448), // gBCLR |
| 2929 | UINT64_C(1275068449), // gBCLRL |
| 2930 | UINT64_C(1073741825), // gBCLat |
| 2931 | UINT64_C(1073741824), // gBCat |
| 2932 | UINT64_C(0) |
| 2933 | }; |
| 2934 | const unsigned opcode = MI.getOpcode(); |
| 2935 | uint64_t Value = InstBits[opcode]; |
| 2936 | uint64_t op = 0; |
| 2937 | (void)op; // suppress warning |
| 2938 | switch (opcode) { |
| 2939 | case PPC::ADDISdtprelHA: |
| 2940 | case PPC::ADDISdtprelHA32: |
| 2941 | case PPC::ADDISgotTprelHA: |
| 2942 | case PPC::ADDIStlsgdHA: |
| 2943 | case PPC::ADDIStlsldHA: |
| 2944 | case PPC::ADDIStocHA: |
| 2945 | case PPC::ADDIStocHA8: |
| 2946 | case PPC::ADDIdtprelL: |
| 2947 | case PPC::ADDIdtprelL32: |
| 2948 | case PPC::ADDItlsgdL: |
| 2949 | case PPC::ADDItlsgdL32: |
| 2950 | case PPC::ADDItlsgdLADDR: |
| 2951 | case PPC::ADDItlsgdLADDR32: |
| 2952 | case PPC::ADDItlsldL: |
| 2953 | case PPC::ADDItlsldL32: |
| 2954 | case PPC::ADDItlsldLADDR: |
| 2955 | case PPC::ADDItlsldLADDR32: |
| 2956 | case PPC::ADDItoc: |
| 2957 | case PPC::ADDItoc8: |
| 2958 | case PPC::ADDItocL: |
| 2959 | case PPC::ADDItocL8: |
| 2960 | case PPC::ADJCALLSTACKDOWN: |
| 2961 | case PPC::ADJCALLSTACKUP: |
| 2962 | case PPC::ANDI_rec_1_EQ_BIT: |
| 2963 | case PPC::ANDI_rec_1_EQ_BIT8: |
| 2964 | case PPC::ANDI_rec_1_GT_BIT: |
| 2965 | case PPC::ANDI_rec_1_GT_BIT8: |
| 2966 | case PPC::ATOMIC_CMP_SWAP_I8: |
| 2967 | case PPC::ATOMIC_CMP_SWAP_I16: |
| 2968 | case PPC::ATOMIC_CMP_SWAP_I32: |
| 2969 | case PPC::ATOMIC_CMP_SWAP_I64: |
| 2970 | case PPC::ATOMIC_LOAD_ADD_I8: |
| 2971 | case PPC::ATOMIC_LOAD_ADD_I16: |
| 2972 | case PPC::ATOMIC_LOAD_ADD_I32: |
| 2973 | case PPC::ATOMIC_LOAD_ADD_I64: |
| 2974 | case PPC::ATOMIC_LOAD_AND_I8: |
| 2975 | case PPC::ATOMIC_LOAD_AND_I16: |
| 2976 | case PPC::ATOMIC_LOAD_AND_I32: |
| 2977 | case PPC::ATOMIC_LOAD_AND_I64: |
| 2978 | case PPC::ATOMIC_LOAD_MAX_I8: |
| 2979 | case PPC::ATOMIC_LOAD_MAX_I16: |
| 2980 | case PPC::ATOMIC_LOAD_MAX_I32: |
| 2981 | case PPC::ATOMIC_LOAD_MAX_I64: |
| 2982 | case PPC::ATOMIC_LOAD_MIN_I8: |
| 2983 | case PPC::ATOMIC_LOAD_MIN_I16: |
| 2984 | case PPC::ATOMIC_LOAD_MIN_I32: |
| 2985 | case PPC::ATOMIC_LOAD_MIN_I64: |
| 2986 | case PPC::ATOMIC_LOAD_NAND_I8: |
| 2987 | case PPC::ATOMIC_LOAD_NAND_I16: |
| 2988 | case PPC::ATOMIC_LOAD_NAND_I32: |
| 2989 | case PPC::ATOMIC_LOAD_NAND_I64: |
| 2990 | case PPC::ATOMIC_LOAD_OR_I8: |
| 2991 | case PPC::ATOMIC_LOAD_OR_I16: |
| 2992 | case PPC::ATOMIC_LOAD_OR_I32: |
| 2993 | case PPC::ATOMIC_LOAD_OR_I64: |
| 2994 | case PPC::ATOMIC_LOAD_SUB_I8: |
| 2995 | case PPC::ATOMIC_LOAD_SUB_I16: |
| 2996 | case PPC::ATOMIC_LOAD_SUB_I32: |
| 2997 | case PPC::ATOMIC_LOAD_SUB_I64: |
| 2998 | case PPC::ATOMIC_LOAD_UMAX_I8: |
| 2999 | case PPC::ATOMIC_LOAD_UMAX_I16: |
| 3000 | case PPC::ATOMIC_LOAD_UMAX_I32: |
| 3001 | case PPC::ATOMIC_LOAD_UMAX_I64: |
| 3002 | case PPC::ATOMIC_LOAD_UMIN_I8: |
| 3003 | case PPC::ATOMIC_LOAD_UMIN_I16: |
| 3004 | case PPC::ATOMIC_LOAD_UMIN_I32: |
| 3005 | case PPC::ATOMIC_LOAD_UMIN_I64: |
| 3006 | case PPC::ATOMIC_LOAD_XOR_I8: |
| 3007 | case PPC::ATOMIC_LOAD_XOR_I16: |
| 3008 | case PPC::ATOMIC_LOAD_XOR_I32: |
| 3009 | case PPC::ATOMIC_LOAD_XOR_I64: |
| 3010 | case PPC::ATOMIC_SWAP_I8: |
| 3011 | case PPC::ATOMIC_SWAP_I16: |
| 3012 | case PPC::ATOMIC_SWAP_I32: |
| 3013 | case PPC::ATOMIC_SWAP_I64: |
| 3014 | case PPC::ATTN: |
| 3015 | case PPC::BCTR: |
| 3016 | case PPC::BCTR8: |
| 3017 | case PPC::BCTRL: |
| 3018 | case PPC::BCTRL8: |
| 3019 | case PPC::BCTRL8_RM: |
| 3020 | case PPC::BCTRL_RM: |
| 3021 | case PPC::BDNZLR: |
| 3022 | case PPC::BDNZLR8: |
| 3023 | case PPC::BDNZLRL: |
| 3024 | case PPC::BDNZLRLm: |
| 3025 | case PPC::BDNZLRLp: |
| 3026 | case PPC::BDNZLRm: |
| 3027 | case PPC::BDNZLRp: |
| 3028 | case PPC::BDZLR: |
| 3029 | case PPC::BDZLR8: |
| 3030 | case PPC::BDZLRL: |
| 3031 | case PPC::BDZLRLm: |
| 3032 | case PPC::BDZLRLp: |
| 3033 | case PPC::BDZLRm: |
| 3034 | case PPC::BDZLRp: |
| 3035 | case PPC::BLR: |
| 3036 | case PPC::BLR8: |
| 3037 | case PPC::BLRL: |
| 3038 | case PPC::CLRBHRB: |
| 3039 | case PPC::CP_ABORT: |
| 3040 | case PPC::CR6SET: |
| 3041 | case PPC::CR6UNSET: |
| 3042 | case PPC::DSSALL: |
| 3043 | case PPC::DYNALLOC: |
| 3044 | case PPC::DYNALLOC8: |
| 3045 | case PPC::DYNAREAOFFSET: |
| 3046 | case PPC::DYNAREAOFFSET8: |
| 3047 | case PPC::DecreaseCTR8loop: |
| 3048 | case PPC::DecreaseCTRloop: |
| 3049 | case PPC::EH_SjLj_LongJmp32: |
| 3050 | case PPC::EH_SjLj_LongJmp64: |
| 3051 | case PPC::EH_SjLj_SetJmp32: |
| 3052 | case PPC::EH_SjLj_SetJmp64: |
| 3053 | case PPC::EH_SjLj_Setup: |
| 3054 | case PPC::EnforceIEIO: |
| 3055 | case PPC::FADDrtz: |
| 3056 | case PPC::FENCE: |
| 3057 | case PPC::GETtlsADDR: |
| 3058 | case PPC::GETtlsADDR32: |
| 3059 | case PPC::GETtlsADDR32AIX: |
| 3060 | case PPC::GETtlsADDR64AIX: |
| 3061 | case PPC::GETtlsADDRPCREL: |
| 3062 | case PPC::GETtlsMOD32AIX: |
| 3063 | case PPC::GETtlsMOD64AIX: |
| 3064 | case PPC::GETtlsTpointer32AIX: |
| 3065 | case PPC::GETtlsldADDR: |
| 3066 | case PPC::GETtlsldADDR32: |
| 3067 | case PPC::GETtlsldADDRPCREL: |
| 3068 | case PPC::HRFID: |
| 3069 | case PPC::ISYNC: |
| 3070 | case PPC::LDgotTprelL: |
| 3071 | case PPC::LDgotTprelL32: |
| 3072 | case PPC::LDtoc: |
| 3073 | case PPC::LDtocBA: |
| 3074 | case PPC::LDtocCPT: |
| 3075 | case PPC::LDtocJTI: |
| 3076 | case PPC::LDtocL: |
| 3077 | case PPC::LQX_PSEUDO: |
| 3078 | case PPC::LWZtoc: |
| 3079 | case PPC::LWZtocL: |
| 3080 | case PPC::MSGSYNC: |
| 3081 | case PPC::MSYNC: |
| 3082 | case PPC::MoveGOTtoLR: |
| 3083 | case PPC::MovePCtoLR: |
| 3084 | case PPC::MovePCtoLR8: |
| 3085 | case PPC::NAP: |
| 3086 | case PPC::NOP: |
| 3087 | case PPC::NOP_GT_PWR6: |
| 3088 | case PPC::NOP_GT_PWR7: |
| 3089 | case PPC::PADDIdtprel: |
| 3090 | case PPC::PPC32GOT: |
| 3091 | case PPC::PPC32PICGOT: |
| 3092 | case PPC::PREPARE_PROBED_ALLOCA_32: |
| 3093 | case PPC::PREPARE_PROBED_ALLOCA_64: |
| 3094 | case PPC::PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32: |
| 3095 | case PPC::PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64: |
| 3096 | case PPC::PROBED_ALLOCA_32: |
| 3097 | case PPC::PROBED_ALLOCA_64: |
| 3098 | case PPC::PROBED_STACKALLOC_32: |
| 3099 | case PPC::PROBED_STACKALLOC_64: |
| 3100 | case PPC::PseudoEIEIO: |
| 3101 | case PPC::RESTORE_ACC: |
| 3102 | case PPC::RESTORE_CR: |
| 3103 | case PPC::RESTORE_CRBIT: |
| 3104 | case PPC::RESTORE_DMR: |
| 3105 | case PPC::RESTORE_DMRP: |
| 3106 | case PPC::RESTORE_QUADWORD: |
| 3107 | case PPC::RESTORE_UACC: |
| 3108 | case PPC::RESTORE_WACC: |
| 3109 | case PPC::RFCI: |
| 3110 | case PPC::RFDI: |
| 3111 | case PPC::RFI: |
| 3112 | case PPC::RFID: |
| 3113 | case PPC::RFMCI: |
| 3114 | case PPC::ReadTB: |
| 3115 | case PPC::SELECT_CC_F4: |
| 3116 | case PPC::SELECT_CC_F8: |
| 3117 | case PPC::SELECT_CC_F16: |
| 3118 | case PPC::SELECT_CC_I4: |
| 3119 | case PPC::SELECT_CC_I8: |
| 3120 | case PPC::SELECT_CC_SPE: |
| 3121 | case PPC::SELECT_CC_SPE4: |
| 3122 | case PPC::SELECT_CC_VRRC: |
| 3123 | case PPC::SELECT_CC_VSFRC: |
| 3124 | case PPC::SELECT_CC_VSRC: |
| 3125 | case PPC::SELECT_CC_VSSRC: |
| 3126 | case PPC::SELECT_F4: |
| 3127 | case PPC::SELECT_F8: |
| 3128 | case PPC::SELECT_F16: |
| 3129 | case PPC::SELECT_I4: |
| 3130 | case PPC::SELECT_I8: |
| 3131 | case PPC::SELECT_SPE: |
| 3132 | case PPC::SELECT_SPE4: |
| 3133 | case PPC::SELECT_VRRC: |
| 3134 | case PPC::SELECT_VSFRC: |
| 3135 | case PPC::SELECT_VSRC: |
| 3136 | case PPC::SELECT_VSSRC: |
| 3137 | case PPC::SETFLM: |
| 3138 | case PPC::SETRND: |
| 3139 | case PPC::SETRNDi: |
| 3140 | case PPC::SLBIA: |
| 3141 | case PPC::SLBSYNC: |
| 3142 | case PPC::SPILL_ACC: |
| 3143 | case PPC::SPILL_CR: |
| 3144 | case PPC::SPILL_CRBIT: |
| 3145 | case PPC::SPILL_DMR: |
| 3146 | case PPC::SPILL_DMRP: |
| 3147 | case PPC::SPILL_QUADWORD: |
| 3148 | case PPC::SPILL_UACC: |
| 3149 | case PPC::SPILL_WACC: |
| 3150 | case PPC::SPLIT_QUADWORD: |
| 3151 | case PPC::STOP: |
| 3152 | case PPC::STQX_PSEUDO: |
| 3153 | case PPC::TAILBCTR: |
| 3154 | case PPC::TAILBCTR8: |
| 3155 | case PPC::TBEGIN_RET: |
| 3156 | case PPC::TCHECK_RET: |
| 3157 | case PPC::TCRETURNai: |
| 3158 | case PPC::TCRETURNai8: |
| 3159 | case PPC::TCRETURNdi: |
| 3160 | case PPC::TCRETURNdi8: |
| 3161 | case PPC::TCRETURNri: |
| 3162 | case PPC::TCRETURNri8: |
| 3163 | case PPC::TLBIA: |
| 3164 | case PPC::TLBRE: |
| 3165 | case PPC::TLBSYNC: |
| 3166 | case PPC::TLBWE: |
| 3167 | case PPC::TLSGDAIX: |
| 3168 | case PPC::TLSGDAIX8: |
| 3169 | case PPC::TLSLDAIX: |
| 3170 | case PPC::TLSLDAIX8: |
| 3171 | case PPC::TRAP: |
| 3172 | case PPC::TRECHKPT: |
| 3173 | case PPC::UNENCODED_NOP: |
| 3174 | case PPC::UpdateGBR: { |
| 3175 | break; |
| 3176 | } |
| 3177 | case PPC::TEND: { |
| 3178 | // op: A |
| 3179 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3180 | op &= UINT64_C(1); |
| 3181 | op <<= 25; |
| 3182 | Value |= op; |
| 3183 | break; |
| 3184 | } |
| 3185 | case PPC::DMSETDMRZ: |
| 3186 | case PPC::DMXXSETACCZ: |
| 3187 | case PPC::XXMTACC: |
| 3188 | case PPC::XXMTACCW: |
| 3189 | case PPC::XXSETACCZ: { |
| 3190 | // op: AT |
| 3191 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3192 | op &= UINT64_C(7); |
| 3193 | op <<= 23; |
| 3194 | Value |= op; |
| 3195 | break; |
| 3196 | } |
| 3197 | case PPC::DMMR: { |
| 3198 | // op: AT |
| 3199 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3200 | op &= UINT64_C(7); |
| 3201 | op <<= 23; |
| 3202 | Value |= op; |
| 3203 | // op: AB |
| 3204 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3205 | op &= UINT64_C(7); |
| 3206 | op <<= 13; |
| 3207 | Value |= op; |
| 3208 | break; |
| 3209 | } |
| 3210 | case PPC::DMXOR: { |
| 3211 | // op: AT |
| 3212 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3213 | op &= UINT64_C(7); |
| 3214 | op <<= 23; |
| 3215 | Value |= op; |
| 3216 | // op: AB |
| 3217 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3218 | op &= UINT64_C(7); |
| 3219 | op <<= 13; |
| 3220 | Value |= op; |
| 3221 | break; |
| 3222 | } |
| 3223 | case PPC::DMSHA2HASH: { |
| 3224 | // op: AT |
| 3225 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3226 | op &= UINT64_C(7); |
| 3227 | op <<= 23; |
| 3228 | Value |= op; |
| 3229 | // op: AB |
| 3230 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3231 | op &= UINT64_C(7); |
| 3232 | op <<= 13; |
| 3233 | Value |= op; |
| 3234 | // op: T |
| 3235 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3236 | op &= UINT64_C(1); |
| 3237 | op <<= 21; |
| 3238 | Value |= op; |
| 3239 | break; |
| 3240 | } |
| 3241 | case PPC::XVBF16GER2: |
| 3242 | case PPC::XVBF16GER2W: |
| 3243 | case PPC::XVF16GER2: |
| 3244 | case PPC::XVF16GER2W: |
| 3245 | case PPC::XVF32GER: |
| 3246 | case PPC::XVF32GERW: |
| 3247 | case PPC::XVI4GER8: |
| 3248 | case PPC::XVI4GER8W: |
| 3249 | case PPC::XVI8GER4: |
| 3250 | case PPC::XVI8GER4W: |
| 3251 | case PPC::XVI16GER2: |
| 3252 | case PPC::XVI16GER2S: |
| 3253 | case PPC::XVI16GER2SW: |
| 3254 | case PPC::XVI16GER2W: { |
| 3255 | // op: AT |
| 3256 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3257 | op &= UINT64_C(7); |
| 3258 | op <<= 23; |
| 3259 | Value |= op; |
| 3260 | // op: XA |
| 3261 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3262 | Value |= (op & UINT64_C(31)) << 16; |
| 3263 | Value |= (op & UINT64_C(32)) >> 3; |
| 3264 | // op: XB |
| 3265 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3266 | Value |= (op & UINT64_C(31)) << 11; |
| 3267 | Value |= (op & UINT64_C(32)) >> 4; |
| 3268 | break; |
| 3269 | } |
| 3270 | case PPC::PMXVF32GER: |
| 3271 | case PPC::PMXVF32GERW: { |
| 3272 | // op: AT |
| 3273 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3274 | op &= UINT64_C(7); |
| 3275 | op <<= 23; |
| 3276 | Value |= op; |
| 3277 | // op: XA |
| 3278 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3279 | Value |= (op & UINT64_C(31)) << 16; |
| 3280 | Value |= (op & UINT64_C(32)) >> 3; |
| 3281 | // op: XB |
| 3282 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3283 | Value |= (op & UINT64_C(31)) << 11; |
| 3284 | Value |= (op & UINT64_C(32)) >> 4; |
| 3285 | // op: XMSK |
| 3286 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3287 | op &= UINT64_C(15); |
| 3288 | op <<= 36; |
| 3289 | Value |= op; |
| 3290 | // op: YMSK |
| 3291 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 3292 | op &= UINT64_C(15); |
| 3293 | op <<= 32; |
| 3294 | Value |= op; |
| 3295 | break; |
| 3296 | } |
| 3297 | case PPC::PMXVI8GER4: |
| 3298 | case PPC::PMXVI8GER4W: { |
| 3299 | // op: AT |
| 3300 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3301 | op &= UINT64_C(7); |
| 3302 | op <<= 23; |
| 3303 | Value |= op; |
| 3304 | // op: XA |
| 3305 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3306 | Value |= (op & UINT64_C(31)) << 16; |
| 3307 | Value |= (op & UINT64_C(32)) >> 3; |
| 3308 | // op: XB |
| 3309 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3310 | Value |= (op & UINT64_C(31)) << 11; |
| 3311 | Value |= (op & UINT64_C(32)) >> 4; |
| 3312 | // op: XMSK |
| 3313 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3314 | op &= UINT64_C(15); |
| 3315 | op <<= 36; |
| 3316 | Value |= op; |
| 3317 | // op: YMSK |
| 3318 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 3319 | op &= UINT64_C(15); |
| 3320 | op <<= 32; |
| 3321 | Value |= op; |
| 3322 | // op: PMSK |
| 3323 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 3324 | op &= UINT64_C(15); |
| 3325 | op <<= 44; |
| 3326 | Value |= op; |
| 3327 | break; |
| 3328 | } |
| 3329 | case PPC::PMXVI4GER8: |
| 3330 | case PPC::PMXVI4GER8W: { |
| 3331 | // op: AT |
| 3332 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3333 | op &= UINT64_C(7); |
| 3334 | op <<= 23; |
| 3335 | Value |= op; |
| 3336 | // op: XA |
| 3337 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3338 | Value |= (op & UINT64_C(31)) << 16; |
| 3339 | Value |= (op & UINT64_C(32)) >> 3; |
| 3340 | // op: XB |
| 3341 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3342 | Value |= (op & UINT64_C(31)) << 11; |
| 3343 | Value |= (op & UINT64_C(32)) >> 4; |
| 3344 | // op: XMSK |
| 3345 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3346 | op &= UINT64_C(15); |
| 3347 | op <<= 36; |
| 3348 | Value |= op; |
| 3349 | // op: YMSK |
| 3350 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 3351 | op &= UINT64_C(15); |
| 3352 | op <<= 32; |
| 3353 | Value |= op; |
| 3354 | // op: PMSK |
| 3355 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 3356 | op &= UINT64_C(255); |
| 3357 | op <<= 40; |
| 3358 | Value |= op; |
| 3359 | break; |
| 3360 | } |
| 3361 | case PPC::PMXVBF16GER2: |
| 3362 | case PPC::PMXVBF16GER2W: |
| 3363 | case PPC::PMXVF16GER2: |
| 3364 | case PPC::PMXVF16GER2W: |
| 3365 | case PPC::PMXVI16GER2: |
| 3366 | case PPC::PMXVI16GER2S: |
| 3367 | case PPC::PMXVI16GER2SW: |
| 3368 | case PPC::PMXVI16GER2W: { |
| 3369 | // op: AT |
| 3370 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3371 | op &= UINT64_C(7); |
| 3372 | op <<= 23; |
| 3373 | Value |= op; |
| 3374 | // op: XA |
| 3375 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3376 | Value |= (op & UINT64_C(31)) << 16; |
| 3377 | Value |= (op & UINT64_C(32)) >> 3; |
| 3378 | // op: XB |
| 3379 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3380 | Value |= (op & UINT64_C(31)) << 11; |
| 3381 | Value |= (op & UINT64_C(32)) >> 4; |
| 3382 | // op: XMSK |
| 3383 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3384 | op &= UINT64_C(15); |
| 3385 | op <<= 36; |
| 3386 | Value |= op; |
| 3387 | // op: YMSK |
| 3388 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 3389 | op &= UINT64_C(15); |
| 3390 | op <<= 32; |
| 3391 | Value |= op; |
| 3392 | // op: PMSK |
| 3393 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 3394 | op &= UINT64_C(3); |
| 3395 | op <<= 46; |
| 3396 | Value |= op; |
| 3397 | break; |
| 3398 | } |
| 3399 | case PPC::XVBF16GER2NN: |
| 3400 | case PPC::XVBF16GER2NP: |
| 3401 | case PPC::XVBF16GER2PN: |
| 3402 | case PPC::XVBF16GER2PP: |
| 3403 | case PPC::XVBF16GER2WNN: |
| 3404 | case PPC::XVBF16GER2WNP: |
| 3405 | case PPC::XVBF16GER2WPN: |
| 3406 | case PPC::XVBF16GER2WPP: |
| 3407 | case PPC::XVF16GER2NN: |
| 3408 | case PPC::XVF16GER2NP: |
| 3409 | case PPC::XVF16GER2PN: |
| 3410 | case PPC::XVF16GER2PP: |
| 3411 | case PPC::XVF16GER2WNN: |
| 3412 | case PPC::XVF16GER2WNP: |
| 3413 | case PPC::XVF16GER2WPN: |
| 3414 | case PPC::XVF16GER2WPP: |
| 3415 | case PPC::XVF32GERNN: |
| 3416 | case PPC::XVF32GERNP: |
| 3417 | case PPC::XVF32GERPN: |
| 3418 | case PPC::XVF32GERPP: |
| 3419 | case PPC::XVF32GERWNN: |
| 3420 | case PPC::XVF32GERWNP: |
| 3421 | case PPC::XVF32GERWPN: |
| 3422 | case PPC::XVF32GERWPP: |
| 3423 | case PPC::XVI4GER8PP: |
| 3424 | case PPC::XVI4GER8WPP: |
| 3425 | case PPC::XVI8GER4PP: |
| 3426 | case PPC::XVI8GER4SPP: |
| 3427 | case PPC::XVI8GER4WPP: |
| 3428 | case PPC::XVI8GER4WSPP: |
| 3429 | case PPC::XVI16GER2PP: |
| 3430 | case PPC::XVI16GER2SPP: |
| 3431 | case PPC::XVI16GER2SWPP: |
| 3432 | case PPC::XVI16GER2WPP: { |
| 3433 | // op: AT |
| 3434 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3435 | op &= UINT64_C(7); |
| 3436 | op <<= 23; |
| 3437 | Value |= op; |
| 3438 | // op: XA |
| 3439 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3440 | Value |= (op & UINT64_C(31)) << 16; |
| 3441 | Value |= (op & UINT64_C(32)) >> 3; |
| 3442 | // op: XB |
| 3443 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3444 | Value |= (op & UINT64_C(31)) << 11; |
| 3445 | Value |= (op & UINT64_C(32)) >> 4; |
| 3446 | break; |
| 3447 | } |
| 3448 | case PPC::PMXVF32GERNN: |
| 3449 | case PPC::PMXVF32GERNP: |
| 3450 | case PPC::PMXVF32GERPN: |
| 3451 | case PPC::PMXVF32GERPP: |
| 3452 | case PPC::PMXVF32GERWNN: |
| 3453 | case PPC::PMXVF32GERWNP: |
| 3454 | case PPC::PMXVF32GERWPN: |
| 3455 | case PPC::PMXVF32GERWPP: { |
| 3456 | // op: AT |
| 3457 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3458 | op &= UINT64_C(7); |
| 3459 | op <<= 23; |
| 3460 | Value |= op; |
| 3461 | // op: XA |
| 3462 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3463 | Value |= (op & UINT64_C(31)) << 16; |
| 3464 | Value |= (op & UINT64_C(32)) >> 3; |
| 3465 | // op: XB |
| 3466 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3467 | Value |= (op & UINT64_C(31)) << 11; |
| 3468 | Value |= (op & UINT64_C(32)) >> 4; |
| 3469 | // op: XMSK |
| 3470 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 3471 | op &= UINT64_C(15); |
| 3472 | op <<= 36; |
| 3473 | Value |= op; |
| 3474 | // op: YMSK |
| 3475 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 3476 | op &= UINT64_C(15); |
| 3477 | op <<= 32; |
| 3478 | Value |= op; |
| 3479 | break; |
| 3480 | } |
| 3481 | case PPC::PMXVI8GER4PP: |
| 3482 | case PPC::PMXVI8GER4SPP: |
| 3483 | case PPC::PMXVI8GER4WPP: |
| 3484 | case PPC::PMXVI8GER4WSPP: { |
| 3485 | // op: AT |
| 3486 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3487 | op &= UINT64_C(7); |
| 3488 | op <<= 23; |
| 3489 | Value |= op; |
| 3490 | // op: XA |
| 3491 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3492 | Value |= (op & UINT64_C(31)) << 16; |
| 3493 | Value |= (op & UINT64_C(32)) >> 3; |
| 3494 | // op: XB |
| 3495 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3496 | Value |= (op & UINT64_C(31)) << 11; |
| 3497 | Value |= (op & UINT64_C(32)) >> 4; |
| 3498 | // op: XMSK |
| 3499 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 3500 | op &= UINT64_C(15); |
| 3501 | op <<= 36; |
| 3502 | Value |= op; |
| 3503 | // op: YMSK |
| 3504 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 3505 | op &= UINT64_C(15); |
| 3506 | op <<= 32; |
| 3507 | Value |= op; |
| 3508 | // op: PMSK |
| 3509 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI); |
| 3510 | op &= UINT64_C(15); |
| 3511 | op <<= 44; |
| 3512 | Value |= op; |
| 3513 | break; |
| 3514 | } |
| 3515 | case PPC::PMXVI4GER8PP: |
| 3516 | case PPC::PMXVI4GER8WPP: { |
| 3517 | // op: AT |
| 3518 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3519 | op &= UINT64_C(7); |
| 3520 | op <<= 23; |
| 3521 | Value |= op; |
| 3522 | // op: XA |
| 3523 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3524 | Value |= (op & UINT64_C(31)) << 16; |
| 3525 | Value |= (op & UINT64_C(32)) >> 3; |
| 3526 | // op: XB |
| 3527 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3528 | Value |= (op & UINT64_C(31)) << 11; |
| 3529 | Value |= (op & UINT64_C(32)) >> 4; |
| 3530 | // op: XMSK |
| 3531 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 3532 | op &= UINT64_C(15); |
| 3533 | op <<= 36; |
| 3534 | Value |= op; |
| 3535 | // op: YMSK |
| 3536 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 3537 | op &= UINT64_C(15); |
| 3538 | op <<= 32; |
| 3539 | Value |= op; |
| 3540 | // op: PMSK |
| 3541 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI); |
| 3542 | op &= UINT64_C(255); |
| 3543 | op <<= 40; |
| 3544 | Value |= op; |
| 3545 | break; |
| 3546 | } |
| 3547 | case PPC::PMXVBF16GER2NN: |
| 3548 | case PPC::PMXVBF16GER2NP: |
| 3549 | case PPC::PMXVBF16GER2PN: |
| 3550 | case PPC::PMXVBF16GER2PP: |
| 3551 | case PPC::PMXVBF16GER2WNN: |
| 3552 | case PPC::PMXVBF16GER2WNP: |
| 3553 | case PPC::PMXVBF16GER2WPN: |
| 3554 | case PPC::PMXVBF16GER2WPP: |
| 3555 | case PPC::PMXVF16GER2NN: |
| 3556 | case PPC::PMXVF16GER2NP: |
| 3557 | case PPC::PMXVF16GER2PN: |
| 3558 | case PPC::PMXVF16GER2PP: |
| 3559 | case PPC::PMXVF16GER2WNN: |
| 3560 | case PPC::PMXVF16GER2WNP: |
| 3561 | case PPC::PMXVF16GER2WPN: |
| 3562 | case PPC::PMXVF16GER2WPP: |
| 3563 | case PPC::PMXVI16GER2PP: |
| 3564 | case PPC::PMXVI16GER2SPP: |
| 3565 | case PPC::PMXVI16GER2SWPP: |
| 3566 | case PPC::PMXVI16GER2WPP: { |
| 3567 | // op: AT |
| 3568 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3569 | op &= UINT64_C(7); |
| 3570 | op <<= 23; |
| 3571 | Value |= op; |
| 3572 | // op: XA |
| 3573 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3574 | Value |= (op & UINT64_C(31)) << 16; |
| 3575 | Value |= (op & UINT64_C(32)) >> 3; |
| 3576 | // op: XB |
| 3577 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3578 | Value |= (op & UINT64_C(31)) << 11; |
| 3579 | Value |= (op & UINT64_C(32)) >> 4; |
| 3580 | // op: XMSK |
| 3581 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 3582 | op &= UINT64_C(15); |
| 3583 | op <<= 36; |
| 3584 | Value |= op; |
| 3585 | // op: YMSK |
| 3586 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 3587 | op &= UINT64_C(15); |
| 3588 | op <<= 32; |
| 3589 | Value |= op; |
| 3590 | // op: PMSK |
| 3591 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI); |
| 3592 | op &= UINT64_C(3); |
| 3593 | op <<= 46; |
| 3594 | Value |= op; |
| 3595 | break; |
| 3596 | } |
| 3597 | case PPC::XVF64GER: |
| 3598 | case PPC::XVF64GERW: { |
| 3599 | // op: AT |
| 3600 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3601 | op &= UINT64_C(7); |
| 3602 | op <<= 23; |
| 3603 | Value |= op; |
| 3604 | // op: XA |
| 3605 | op = getVSRpEvenEncoding(MI, OpNo: 1, Fixups, STI); |
| 3606 | Value |= (op & UINT64_C(31)) << 16; |
| 3607 | Value |= (op & UINT64_C(32)) >> 3; |
| 3608 | // op: XB |
| 3609 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3610 | Value |= (op & UINT64_C(31)) << 11; |
| 3611 | Value |= (op & UINT64_C(32)) >> 4; |
| 3612 | break; |
| 3613 | } |
| 3614 | case PPC::PMXVF64GER: |
| 3615 | case PPC::PMXVF64GERW: { |
| 3616 | // op: AT |
| 3617 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3618 | op &= UINT64_C(7); |
| 3619 | op <<= 23; |
| 3620 | Value |= op; |
| 3621 | // op: XA |
| 3622 | op = getVSRpEvenEncoding(MI, OpNo: 1, Fixups, STI); |
| 3623 | Value |= (op & UINT64_C(31)) << 16; |
| 3624 | Value |= (op & UINT64_C(32)) >> 3; |
| 3625 | // op: XB |
| 3626 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3627 | Value |= (op & UINT64_C(31)) << 11; |
| 3628 | Value |= (op & UINT64_C(32)) >> 4; |
| 3629 | // op: XMSK |
| 3630 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3631 | op &= UINT64_C(15); |
| 3632 | op <<= 36; |
| 3633 | Value |= op; |
| 3634 | // op: YMSK |
| 3635 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 3636 | op &= UINT64_C(3); |
| 3637 | op <<= 34; |
| 3638 | Value |= op; |
| 3639 | break; |
| 3640 | } |
| 3641 | case PPC::XVF64GERNN: |
| 3642 | case PPC::XVF64GERNP: |
| 3643 | case PPC::XVF64GERPN: |
| 3644 | case PPC::XVF64GERPP: |
| 3645 | case PPC::XVF64GERWNN: |
| 3646 | case PPC::XVF64GERWNP: |
| 3647 | case PPC::XVF64GERWPN: |
| 3648 | case PPC::XVF64GERWPP: { |
| 3649 | // op: AT |
| 3650 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3651 | op &= UINT64_C(7); |
| 3652 | op <<= 23; |
| 3653 | Value |= op; |
| 3654 | // op: XA |
| 3655 | op = getVSRpEvenEncoding(MI, OpNo: 2, Fixups, STI); |
| 3656 | Value |= (op & UINT64_C(31)) << 16; |
| 3657 | Value |= (op & UINT64_C(32)) >> 3; |
| 3658 | // op: XB |
| 3659 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3660 | Value |= (op & UINT64_C(31)) << 11; |
| 3661 | Value |= (op & UINT64_C(32)) >> 4; |
| 3662 | break; |
| 3663 | } |
| 3664 | case PPC::PMXVF64GERNN: |
| 3665 | case PPC::PMXVF64GERNP: |
| 3666 | case PPC::PMXVF64GERPN: |
| 3667 | case PPC::PMXVF64GERPP: |
| 3668 | case PPC::PMXVF64GERWNN: |
| 3669 | case PPC::PMXVF64GERWNP: |
| 3670 | case PPC::PMXVF64GERWPN: |
| 3671 | case PPC::PMXVF64GERWPP: { |
| 3672 | // op: AT |
| 3673 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3674 | op &= UINT64_C(7); |
| 3675 | op <<= 23; |
| 3676 | Value |= op; |
| 3677 | // op: XA |
| 3678 | op = getVSRpEvenEncoding(MI, OpNo: 2, Fixups, STI); |
| 3679 | Value |= (op & UINT64_C(31)) << 16; |
| 3680 | Value |= (op & UINT64_C(32)) >> 3; |
| 3681 | // op: XB |
| 3682 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3683 | Value |= (op & UINT64_C(31)) << 11; |
| 3684 | Value |= (op & UINT64_C(32)) >> 4; |
| 3685 | // op: XMSK |
| 3686 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 3687 | op &= UINT64_C(15); |
| 3688 | op <<= 36; |
| 3689 | Value |= op; |
| 3690 | // op: YMSK |
| 3691 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 3692 | op &= UINT64_C(3); |
| 3693 | op <<= 34; |
| 3694 | Value |= op; |
| 3695 | break; |
| 3696 | } |
| 3697 | case PPC::DMXVBF16GERX2: |
| 3698 | case PPC::DMXVF16GERX2: |
| 3699 | case PPC::DMXVI8GERX4: { |
| 3700 | // op: AT |
| 3701 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3702 | op &= UINT64_C(7); |
| 3703 | op <<= 23; |
| 3704 | Value |= op; |
| 3705 | // op: XAp |
| 3706 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3707 | Value |= (op & UINT64_C(15)) << 17; |
| 3708 | Value |= (op & UINT64_C(16)) >> 2; |
| 3709 | // op: XB |
| 3710 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3711 | Value |= (op & UINT64_C(31)) << 11; |
| 3712 | Value |= (op & UINT64_C(32)) >> 4; |
| 3713 | break; |
| 3714 | } |
| 3715 | case PPC::PMDMXVI8GERX4: { |
| 3716 | // op: AT |
| 3717 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3718 | op &= UINT64_C(7); |
| 3719 | op <<= 23; |
| 3720 | Value |= op; |
| 3721 | // op: XAp |
| 3722 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3723 | Value |= (op & UINT64_C(15)) << 17; |
| 3724 | Value |= (op & UINT64_C(16)) >> 2; |
| 3725 | // op: XB |
| 3726 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3727 | Value |= (op & UINT64_C(31)) << 11; |
| 3728 | Value |= (op & UINT64_C(32)) >> 4; |
| 3729 | // op: XMSK |
| 3730 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3731 | op &= UINT64_C(255); |
| 3732 | op <<= 36; |
| 3733 | Value |= op; |
| 3734 | // op: YMSK |
| 3735 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 3736 | op &= UINT64_C(15); |
| 3737 | op <<= 32; |
| 3738 | Value |= op; |
| 3739 | // op: PMSK |
| 3740 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 3741 | op &= UINT64_C(15); |
| 3742 | op <<= 44; |
| 3743 | Value |= op; |
| 3744 | break; |
| 3745 | } |
| 3746 | case PPC::PMDMXVBF16GERX2: |
| 3747 | case PPC::PMDMXVF16GERX2: { |
| 3748 | // op: AT |
| 3749 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3750 | op &= UINT64_C(7); |
| 3751 | op <<= 23; |
| 3752 | Value |= op; |
| 3753 | // op: XAp |
| 3754 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3755 | Value |= (op & UINT64_C(15)) << 17; |
| 3756 | Value |= (op & UINT64_C(16)) >> 2; |
| 3757 | // op: XB |
| 3758 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3759 | Value |= (op & UINT64_C(31)) << 11; |
| 3760 | Value |= (op & UINT64_C(32)) >> 4; |
| 3761 | // op: XMSK |
| 3762 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3763 | op &= UINT64_C(255); |
| 3764 | op <<= 36; |
| 3765 | Value |= op; |
| 3766 | // op: YMSK |
| 3767 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 3768 | op &= UINT64_C(15); |
| 3769 | op <<= 32; |
| 3770 | Value |= op; |
| 3771 | // op: PMSK |
| 3772 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 3773 | op &= UINT64_C(3); |
| 3774 | op <<= 46; |
| 3775 | Value |= op; |
| 3776 | break; |
| 3777 | } |
| 3778 | case PPC::DMXXINSTDMR512: |
| 3779 | case PPC::DMXXINSTDMR512_HI: { |
| 3780 | // op: AT |
| 3781 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3782 | op &= UINT64_C(7); |
| 3783 | op <<= 23; |
| 3784 | Value |= op; |
| 3785 | // op: XAp |
| 3786 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3787 | Value |= (op & UINT64_C(15)) << 17; |
| 3788 | Value |= (op & UINT64_C(16)) >> 2; |
| 3789 | // op: XBp |
| 3790 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3791 | Value |= (op & UINT64_C(15)) << 12; |
| 3792 | Value |= (op & UINT64_C(16)) >> 3; |
| 3793 | break; |
| 3794 | } |
| 3795 | case PPC::DMXVBF16GERX2NN: |
| 3796 | case PPC::DMXVBF16GERX2NP: |
| 3797 | case PPC::DMXVBF16GERX2PN: |
| 3798 | case PPC::DMXVBF16GERX2PP: |
| 3799 | case PPC::DMXVF16GERX2NN: |
| 3800 | case PPC::DMXVF16GERX2NP: |
| 3801 | case PPC::DMXVF16GERX2PN: |
| 3802 | case PPC::DMXVF16GERX2PP: |
| 3803 | case PPC::DMXVI8GERX4PP: |
| 3804 | case PPC::DMXVI8GERX4SPP: { |
| 3805 | // op: AT |
| 3806 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3807 | op &= UINT64_C(7); |
| 3808 | op <<= 23; |
| 3809 | Value |= op; |
| 3810 | // op: XAp |
| 3811 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3812 | Value |= (op & UINT64_C(15)) << 17; |
| 3813 | Value |= (op & UINT64_C(16)) >> 2; |
| 3814 | // op: XB |
| 3815 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3816 | Value |= (op & UINT64_C(31)) << 11; |
| 3817 | Value |= (op & UINT64_C(32)) >> 4; |
| 3818 | break; |
| 3819 | } |
| 3820 | case PPC::PMDMXVI8GERX4PP: |
| 3821 | case PPC::PMDMXVI8GERX4SPP: { |
| 3822 | // op: AT |
| 3823 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3824 | op &= UINT64_C(7); |
| 3825 | op <<= 23; |
| 3826 | Value |= op; |
| 3827 | // op: XAp |
| 3828 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3829 | Value |= (op & UINT64_C(15)) << 17; |
| 3830 | Value |= (op & UINT64_C(16)) >> 2; |
| 3831 | // op: XB |
| 3832 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3833 | Value |= (op & UINT64_C(31)) << 11; |
| 3834 | Value |= (op & UINT64_C(32)) >> 4; |
| 3835 | // op: XMSK |
| 3836 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 3837 | op &= UINT64_C(255); |
| 3838 | op <<= 36; |
| 3839 | Value |= op; |
| 3840 | // op: YMSK |
| 3841 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 3842 | op &= UINT64_C(15); |
| 3843 | op <<= 32; |
| 3844 | Value |= op; |
| 3845 | // op: PMSK |
| 3846 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI); |
| 3847 | op &= UINT64_C(15); |
| 3848 | op <<= 44; |
| 3849 | Value |= op; |
| 3850 | break; |
| 3851 | } |
| 3852 | case PPC::PMDMXVBF16GERX2NN: |
| 3853 | case PPC::PMDMXVBF16GERX2NP: |
| 3854 | case PPC::PMDMXVBF16GERX2PN: |
| 3855 | case PPC::PMDMXVBF16GERX2PP: |
| 3856 | case PPC::PMDMXVF16GERX2NN: |
| 3857 | case PPC::PMDMXVF16GERX2NP: |
| 3858 | case PPC::PMDMXVF16GERX2PN: |
| 3859 | case PPC::PMDMXVF16GERX2PP: { |
| 3860 | // op: AT |
| 3861 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3862 | op &= UINT64_C(7); |
| 3863 | op <<= 23; |
| 3864 | Value |= op; |
| 3865 | // op: XAp |
| 3866 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3867 | Value |= (op & UINT64_C(15)) << 17; |
| 3868 | Value |= (op & UINT64_C(16)) >> 2; |
| 3869 | // op: XB |
| 3870 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3871 | Value |= (op & UINT64_C(31)) << 11; |
| 3872 | Value |= (op & UINT64_C(32)) >> 4; |
| 3873 | // op: XMSK |
| 3874 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 3875 | op &= UINT64_C(255); |
| 3876 | op <<= 36; |
| 3877 | Value |= op; |
| 3878 | // op: YMSK |
| 3879 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 3880 | op &= UINT64_C(15); |
| 3881 | op <<= 32; |
| 3882 | Value |= op; |
| 3883 | // op: PMSK |
| 3884 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI); |
| 3885 | op &= UINT64_C(3); |
| 3886 | op <<= 46; |
| 3887 | Value |= op; |
| 3888 | break; |
| 3889 | } |
| 3890 | case PPC::DMXXSHAPAD: { |
| 3891 | // op: AT |
| 3892 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3893 | op &= UINT64_C(7); |
| 3894 | op <<= 23; |
| 3895 | Value |= op; |
| 3896 | // op: XB |
| 3897 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3898 | Value |= (op & UINT64_C(31)) << 11; |
| 3899 | Value |= (op & UINT64_C(32)) >> 4; |
| 3900 | // op: ID |
| 3901 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3902 | op &= UINT64_C(3); |
| 3903 | op <<= 19; |
| 3904 | Value |= op; |
| 3905 | // op: E |
| 3906 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 3907 | op &= UINT64_C(1); |
| 3908 | op <<= 18; |
| 3909 | Value |= op; |
| 3910 | // op: BL |
| 3911 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 3912 | op &= UINT64_C(3); |
| 3913 | op <<= 16; |
| 3914 | Value |= op; |
| 3915 | break; |
| 3916 | } |
| 3917 | case PPC::DMXXINSTDMR256: { |
| 3918 | // op: AT |
| 3919 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3920 | op &= UINT64_C(7); |
| 3921 | op <<= 23; |
| 3922 | Value |= op; |
| 3923 | // op: XBp |
| 3924 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3925 | Value |= (op & UINT64_C(15)) << 12; |
| 3926 | Value |= (op & UINT64_C(16)) >> 3; |
| 3927 | // op: P |
| 3928 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3929 | Value |= (op & UINT64_C(1)) << 16; |
| 3930 | Value |= (op & UINT64_C(2)) << 10; |
| 3931 | break; |
| 3932 | } |
| 3933 | case PPC::XXMFACC: |
| 3934 | case PPC::XXMFACCW: { |
| 3935 | // op: AT |
| 3936 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3937 | op &= UINT64_C(7); |
| 3938 | op <<= 23; |
| 3939 | Value |= op; |
| 3940 | break; |
| 3941 | } |
| 3942 | case PPC::DMXXEXTFDMR256: { |
| 3943 | // op: AT |
| 3944 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3945 | op &= UINT64_C(7); |
| 3946 | op <<= 23; |
| 3947 | Value |= op; |
| 3948 | // op: XBp |
| 3949 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3950 | Value |= (op & UINT64_C(15)) << 12; |
| 3951 | Value |= (op & UINT64_C(16)) >> 3; |
| 3952 | // op: P |
| 3953 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3954 | Value |= (op & UINT64_C(1)) << 16; |
| 3955 | Value |= (op & UINT64_C(2)) << 10; |
| 3956 | break; |
| 3957 | } |
| 3958 | case PPC::DMXXEXTFDMR512: |
| 3959 | case PPC::DMXXEXTFDMR512_HI: { |
| 3960 | // op: AT |
| 3961 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3962 | op &= UINT64_C(7); |
| 3963 | op <<= 23; |
| 3964 | Value |= op; |
| 3965 | // op: XAp |
| 3966 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3967 | Value |= (op & UINT64_C(15)) << 17; |
| 3968 | Value |= (op & UINT64_C(16)) >> 2; |
| 3969 | // op: XBp |
| 3970 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3971 | Value |= (op & UINT64_C(15)) << 12; |
| 3972 | Value |= (op & UINT64_C(16)) >> 3; |
| 3973 | break; |
| 3974 | } |
| 3975 | case PPC::DMSHA3HASH: { |
| 3976 | // op: ATp |
| 3977 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3978 | op &= UINT64_C(3); |
| 3979 | op <<= 24; |
| 3980 | Value |= op; |
| 3981 | // op: SR |
| 3982 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3983 | op &= UINT64_C(31); |
| 3984 | op <<= 11; |
| 3985 | Value |= op; |
| 3986 | break; |
| 3987 | } |
| 3988 | case PPC::BDNZA: |
| 3989 | case PPC::BDNZAm: |
| 3990 | case PPC::BDNZAp: |
| 3991 | case PPC::BDNZLA: |
| 3992 | case PPC::BDNZLAm: |
| 3993 | case PPC::BDNZLAp: |
| 3994 | case PPC::BDZA: |
| 3995 | case PPC::BDZAm: |
| 3996 | case PPC::BDZAp: |
| 3997 | case PPC::BDZLA: |
| 3998 | case PPC::BDZLAm: |
| 3999 | case PPC::BDZLAp: { |
| 4000 | // op: BD |
| 4001 | op = getAbsCondBrEncoding(MI, OpNo: 0, Fixups, STI); |
| 4002 | op &= UINT64_C(16383); |
| 4003 | op <<= 2; |
| 4004 | Value |= op; |
| 4005 | break; |
| 4006 | } |
| 4007 | case PPC::BCLalways: |
| 4008 | case PPC::BDNZ: |
| 4009 | case PPC::BDNZ8: |
| 4010 | case PPC::BDNZL: |
| 4011 | case PPC::BDNZLm: |
| 4012 | case PPC::BDNZLp: |
| 4013 | case PPC::BDNZm: |
| 4014 | case PPC::BDNZp: |
| 4015 | case PPC::BDZ: |
| 4016 | case PPC::BDZ8: |
| 4017 | case PPC::BDZL: |
| 4018 | case PPC::BDZLm: |
| 4019 | case PPC::BDZLp: |
| 4020 | case PPC::BDZm: |
| 4021 | case PPC::BDZp: { |
| 4022 | // op: BD |
| 4023 | op = getCondBrEncoding(MI, OpNo: 0, Fixups, STI); |
| 4024 | op &= UINT64_C(16383); |
| 4025 | op <<= 2; |
| 4026 | Value |= op; |
| 4027 | break; |
| 4028 | } |
| 4029 | case PPC::MCRXRX: |
| 4030 | case PPC::TCHECK: { |
| 4031 | // op: BF |
| 4032 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4033 | op &= UINT64_C(7); |
| 4034 | op <<= 23; |
| 4035 | Value |= op; |
| 4036 | break; |
| 4037 | } |
| 4038 | case PPC::MCRF: |
| 4039 | case PPC::MCRFS: { |
| 4040 | // op: BF |
| 4041 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4042 | op &= UINT64_C(7); |
| 4043 | op <<= 23; |
| 4044 | Value |= op; |
| 4045 | // op: BFA |
| 4046 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4047 | op &= UINT64_C(7); |
| 4048 | op <<= 18; |
| 4049 | Value |= op; |
| 4050 | break; |
| 4051 | } |
| 4052 | case PPC::XSTSTDCQP: { |
| 4053 | // op: BF |
| 4054 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4055 | op &= UINT64_C(7); |
| 4056 | op <<= 23; |
| 4057 | Value |= op; |
| 4058 | // op: DCMX |
| 4059 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4060 | op &= UINT64_C(127); |
| 4061 | op <<= 16; |
| 4062 | Value |= op; |
| 4063 | // op: VB |
| 4064 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4065 | op &= UINT64_C(31); |
| 4066 | op <<= 11; |
| 4067 | Value |= op; |
| 4068 | break; |
| 4069 | } |
| 4070 | case PPC::XSTSTDCDP: |
| 4071 | case PPC::XSTSTDCSP: { |
| 4072 | // op: BF |
| 4073 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4074 | op &= UINT64_C(7); |
| 4075 | op <<= 23; |
| 4076 | Value |= op; |
| 4077 | // op: DCMX |
| 4078 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4079 | op &= UINT64_C(127); |
| 4080 | op <<= 16; |
| 4081 | Value |= op; |
| 4082 | // op: XB |
| 4083 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4084 | Value |= (op & UINT64_C(31)) << 11; |
| 4085 | Value |= (op & UINT64_C(32)) >> 4; |
| 4086 | break; |
| 4087 | } |
| 4088 | case PPC::DTSTDC: |
| 4089 | case PPC::DTSTDCQ: |
| 4090 | case PPC::DTSTDG: |
| 4091 | case PPC::DTSTDGQ: { |
| 4092 | // op: BF |
| 4093 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4094 | op &= UINT64_C(7); |
| 4095 | op <<= 23; |
| 4096 | Value |= op; |
| 4097 | // op: FRA |
| 4098 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4099 | op &= UINT64_C(31); |
| 4100 | op <<= 16; |
| 4101 | Value |= op; |
| 4102 | // op: DCM |
| 4103 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4104 | op &= UINT64_C(63); |
| 4105 | op <<= 10; |
| 4106 | Value |= op; |
| 4107 | break; |
| 4108 | } |
| 4109 | case PPC::CMPRB: |
| 4110 | case PPC::CMPRB8: { |
| 4111 | // op: BF |
| 4112 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4113 | op &= UINT64_C(7); |
| 4114 | op <<= 23; |
| 4115 | Value |= op; |
| 4116 | // op: L |
| 4117 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4118 | op &= UINT64_C(1); |
| 4119 | op <<= 21; |
| 4120 | Value |= op; |
| 4121 | // op: RA |
| 4122 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4123 | op &= UINT64_C(31); |
| 4124 | op <<= 16; |
| 4125 | Value |= op; |
| 4126 | // op: RB |
| 4127 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4128 | op &= UINT64_C(31); |
| 4129 | op <<= 11; |
| 4130 | Value |= op; |
| 4131 | break; |
| 4132 | } |
| 4133 | case PPC::CMPDI: |
| 4134 | case PPC::CMPLDI: |
| 4135 | case PPC::CMPLWI: |
| 4136 | case PPC::CMPWI: { |
| 4137 | // op: BF |
| 4138 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4139 | op &= UINT64_C(7); |
| 4140 | op <<= 23; |
| 4141 | Value |= op; |
| 4142 | // op: RA |
| 4143 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4144 | op &= UINT64_C(31); |
| 4145 | op <<= 16; |
| 4146 | Value |= op; |
| 4147 | // op: D |
| 4148 | op = getImm16Encoding(MI, OpNo: 2, Fixups, STI); |
| 4149 | op &= UINT64_C(65535); |
| 4150 | Value |= op; |
| 4151 | break; |
| 4152 | } |
| 4153 | case PPC::CMPD: |
| 4154 | case PPC::CMPEQB: |
| 4155 | case PPC::CMPLD: |
| 4156 | case PPC::CMPLW: |
| 4157 | case PPC::CMPW: |
| 4158 | case PPC::DCMPO: |
| 4159 | case PPC::DCMPOQ: |
| 4160 | case PPC::DCMPU: |
| 4161 | case PPC::DCMPUQ: |
| 4162 | case PPC::DTSTEX: |
| 4163 | case PPC::DTSTEXQ: |
| 4164 | case PPC::DTSTSF: |
| 4165 | case PPC::DTSTSFQ: |
| 4166 | case PPC::FCMPOD: |
| 4167 | case PPC::FCMPOS: |
| 4168 | case PPC::FCMPUD: |
| 4169 | case PPC::FCMPUS: |
| 4170 | case PPC::FTDIV: |
| 4171 | case PPC::XSCMPEXPQP: |
| 4172 | case PPC::XSCMPOQP: |
| 4173 | case PPC::XSCMPUQP: { |
| 4174 | // op: BF |
| 4175 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4176 | op &= UINT64_C(7); |
| 4177 | op <<= 23; |
| 4178 | Value |= op; |
| 4179 | // op: RA |
| 4180 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4181 | op &= UINT64_C(31); |
| 4182 | op <<= 16; |
| 4183 | Value |= op; |
| 4184 | // op: RB |
| 4185 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4186 | op &= UINT64_C(31); |
| 4187 | op <<= 11; |
| 4188 | Value |= op; |
| 4189 | break; |
| 4190 | } |
| 4191 | case PPC::FTSQRT: { |
| 4192 | // op: BF |
| 4193 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4194 | op &= UINT64_C(7); |
| 4195 | op <<= 23; |
| 4196 | Value |= op; |
| 4197 | // op: RB |
| 4198 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4199 | op &= UINT64_C(31); |
| 4200 | op <<= 11; |
| 4201 | Value |= op; |
| 4202 | break; |
| 4203 | } |
| 4204 | case PPC::MTFSFIb: { |
| 4205 | // op: BF |
| 4206 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4207 | op &= UINT64_C(7); |
| 4208 | op <<= 23; |
| 4209 | Value |= op; |
| 4210 | // op: U |
| 4211 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4212 | op &= UINT64_C(15); |
| 4213 | op <<= 12; |
| 4214 | Value |= op; |
| 4215 | break; |
| 4216 | } |
| 4217 | case PPC::DTSTSFI: |
| 4218 | case PPC::DTSTSFIQ: { |
| 4219 | // op: BF |
| 4220 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4221 | op &= UINT64_C(7); |
| 4222 | op <<= 23; |
| 4223 | Value |= op; |
| 4224 | // op: UIM |
| 4225 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4226 | op &= UINT64_C(63); |
| 4227 | op <<= 16; |
| 4228 | Value |= op; |
| 4229 | // op: FRB |
| 4230 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4231 | op &= UINT64_C(31); |
| 4232 | op <<= 11; |
| 4233 | Value |= op; |
| 4234 | break; |
| 4235 | } |
| 4236 | case PPC::VCMPSQ: |
| 4237 | case PPC::VCMPUQ: { |
| 4238 | // op: BF |
| 4239 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4240 | op &= UINT64_C(7); |
| 4241 | op <<= 23; |
| 4242 | Value |= op; |
| 4243 | // op: VA |
| 4244 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4245 | op &= UINT64_C(31); |
| 4246 | op <<= 16; |
| 4247 | Value |= op; |
| 4248 | // op: VB |
| 4249 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4250 | op &= UINT64_C(31); |
| 4251 | op <<= 11; |
| 4252 | Value |= op; |
| 4253 | break; |
| 4254 | } |
| 4255 | case PPC::MTFSFI: |
| 4256 | case PPC::MTFSFI_rec: { |
| 4257 | // op: BF |
| 4258 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4259 | op &= UINT64_C(7); |
| 4260 | op <<= 23; |
| 4261 | Value |= op; |
| 4262 | // op: W |
| 4263 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4264 | op &= UINT64_C(1); |
| 4265 | op <<= 16; |
| 4266 | Value |= op; |
| 4267 | // op: U |
| 4268 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4269 | op &= UINT64_C(15); |
| 4270 | op <<= 12; |
| 4271 | Value |= op; |
| 4272 | break; |
| 4273 | } |
| 4274 | case PPC::XVTLSBB: { |
| 4275 | // op: BF |
| 4276 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4277 | op &= UINT64_C(7); |
| 4278 | op <<= 23; |
| 4279 | Value |= op; |
| 4280 | // op: XB |
| 4281 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4282 | Value |= (op & UINT64_C(31)) << 11; |
| 4283 | Value |= (op & UINT64_C(32)) >> 4; |
| 4284 | break; |
| 4285 | } |
| 4286 | case PPC::BCCTR: |
| 4287 | case PPC::BCCTR8: |
| 4288 | case PPC::BCCTR8n: |
| 4289 | case PPC::BCCTRL: |
| 4290 | case PPC::BCCTRL8: |
| 4291 | case PPC::BCCTRL8n: |
| 4292 | case PPC::BCCTRLn: |
| 4293 | case PPC::BCCTRn: |
| 4294 | case PPC::BCLR: |
| 4295 | case PPC::BCLRL: |
| 4296 | case PPC::BCLRLn: |
| 4297 | case PPC::BCLRn: { |
| 4298 | // op: BI |
| 4299 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4300 | op &= UINT64_C(31); |
| 4301 | op <<= 16; |
| 4302 | Value |= op; |
| 4303 | break; |
| 4304 | } |
| 4305 | case PPC::BC: |
| 4306 | case PPC::BCL: |
| 4307 | case PPC::BCLn: |
| 4308 | case PPC::BCn: { |
| 4309 | // op: BI |
| 4310 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4311 | op &= UINT64_C(31); |
| 4312 | op <<= 16; |
| 4313 | Value |= op; |
| 4314 | // op: BD |
| 4315 | op = getCondBrEncoding(MI, OpNo: 1, Fixups, STI); |
| 4316 | op &= UINT64_C(16383); |
| 4317 | op <<= 2; |
| 4318 | Value |= op; |
| 4319 | break; |
| 4320 | } |
| 4321 | case PPC::BCCCTR: |
| 4322 | case PPC::BCCCTR8: |
| 4323 | case PPC::BCCCTRL: |
| 4324 | case PPC::BCCCTRL8: |
| 4325 | case PPC::BCCLR: |
| 4326 | case PPC::BCCLRL: { |
| 4327 | // op: BIBO |
| 4328 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4329 | Value |= (op & UINT64_C(31)) << 21; |
| 4330 | Value |= (op & UINT64_C(96)) << 11; |
| 4331 | // op: CR |
| 4332 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4333 | op &= UINT64_C(7); |
| 4334 | op <<= 18; |
| 4335 | Value |= op; |
| 4336 | break; |
| 4337 | } |
| 4338 | case PPC::BCCA: |
| 4339 | case PPC::BCCLA: { |
| 4340 | // op: BIBO |
| 4341 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4342 | Value |= (op & UINT64_C(31)) << 21; |
| 4343 | Value |= (op & UINT64_C(96)) << 11; |
| 4344 | // op: CR |
| 4345 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4346 | op &= UINT64_C(7); |
| 4347 | op <<= 18; |
| 4348 | Value |= op; |
| 4349 | // op: BD |
| 4350 | op = getAbsCondBrEncoding(MI, OpNo: 2, Fixups, STI); |
| 4351 | op &= UINT64_C(16383); |
| 4352 | op <<= 2; |
| 4353 | Value |= op; |
| 4354 | break; |
| 4355 | } |
| 4356 | case PPC::BCC: |
| 4357 | case PPC::BCCL: |
| 4358 | case PPC::CTRL_DEP: { |
| 4359 | // op: BIBO |
| 4360 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4361 | Value |= (op & UINT64_C(31)) << 21; |
| 4362 | Value |= (op & UINT64_C(96)) << 11; |
| 4363 | // op: CR |
| 4364 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4365 | op &= UINT64_C(7); |
| 4366 | op <<= 18; |
| 4367 | Value |= op; |
| 4368 | // op: BD |
| 4369 | op = getCondBrEncoding(MI, OpNo: 2, Fixups, STI); |
| 4370 | op &= UINT64_C(16383); |
| 4371 | op <<= 2; |
| 4372 | Value |= op; |
| 4373 | break; |
| 4374 | } |
| 4375 | case PPC::gBCAat: |
| 4376 | case PPC::gBCLAat: { |
| 4377 | // op: BO |
| 4378 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4379 | op &= UINT64_C(28); |
| 4380 | op <<= 21; |
| 4381 | Value |= op; |
| 4382 | // op: at |
| 4383 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4384 | op &= UINT64_C(3); |
| 4385 | op <<= 21; |
| 4386 | Value |= op; |
| 4387 | // op: BI |
| 4388 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4389 | op &= UINT64_C(31); |
| 4390 | op <<= 16; |
| 4391 | Value |= op; |
| 4392 | // op: BD |
| 4393 | op = getAbsCondBrEncoding(MI, OpNo: 3, Fixups, STI); |
| 4394 | op &= UINT64_C(16383); |
| 4395 | op <<= 2; |
| 4396 | Value |= op; |
| 4397 | break; |
| 4398 | } |
| 4399 | case PPC::gBCLat: |
| 4400 | case PPC::gBCat: { |
| 4401 | // op: BO |
| 4402 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4403 | op &= UINT64_C(28); |
| 4404 | op <<= 21; |
| 4405 | Value |= op; |
| 4406 | // op: at |
| 4407 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4408 | op &= UINT64_C(3); |
| 4409 | op <<= 21; |
| 4410 | Value |= op; |
| 4411 | // op: BI |
| 4412 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4413 | op &= UINT64_C(31); |
| 4414 | op <<= 16; |
| 4415 | Value |= op; |
| 4416 | // op: BD |
| 4417 | op = getCondBrEncoding(MI, OpNo: 3, Fixups, STI); |
| 4418 | op &= UINT64_C(16383); |
| 4419 | op <<= 2; |
| 4420 | Value |= op; |
| 4421 | break; |
| 4422 | } |
| 4423 | case PPC::gBCA: |
| 4424 | case PPC::gBCLA: { |
| 4425 | // op: BO |
| 4426 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4427 | op &= UINT64_C(31); |
| 4428 | op <<= 21; |
| 4429 | Value |= op; |
| 4430 | // op: BI |
| 4431 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4432 | op &= UINT64_C(31); |
| 4433 | op <<= 16; |
| 4434 | Value |= op; |
| 4435 | // op: BD |
| 4436 | op = getAbsCondBrEncoding(MI, OpNo: 2, Fixups, STI); |
| 4437 | op &= UINT64_C(16383); |
| 4438 | op <<= 2; |
| 4439 | Value |= op; |
| 4440 | break; |
| 4441 | } |
| 4442 | case PPC::gBC: |
| 4443 | case PPC::gBCL: { |
| 4444 | // op: BO |
| 4445 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4446 | op &= UINT64_C(31); |
| 4447 | op <<= 21; |
| 4448 | Value |= op; |
| 4449 | // op: BI |
| 4450 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4451 | op &= UINT64_C(31); |
| 4452 | op <<= 16; |
| 4453 | Value |= op; |
| 4454 | // op: BD |
| 4455 | op = getCondBrEncoding(MI, OpNo: 2, Fixups, STI); |
| 4456 | op &= UINT64_C(16383); |
| 4457 | op <<= 2; |
| 4458 | Value |= op; |
| 4459 | break; |
| 4460 | } |
| 4461 | case PPC::gBCCTR: |
| 4462 | case PPC::gBCCTRL: |
| 4463 | case PPC::gBCLR: |
| 4464 | case PPC::gBCLRL: { |
| 4465 | // op: BO |
| 4466 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4467 | op &= UINT64_C(31); |
| 4468 | op <<= 21; |
| 4469 | Value |= op; |
| 4470 | // op: BI |
| 4471 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4472 | op &= UINT64_C(31); |
| 4473 | op <<= 16; |
| 4474 | Value |= op; |
| 4475 | // op: BH |
| 4476 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4477 | op &= UINT64_C(3); |
| 4478 | op <<= 11; |
| 4479 | Value |= op; |
| 4480 | break; |
| 4481 | } |
| 4482 | case PPC::XSCMPEXPDP: |
| 4483 | case PPC::XSCMPODP: |
| 4484 | case PPC::XSCMPUDP: |
| 4485 | case PPC::XSTDIVDP: |
| 4486 | case PPC::XVTDIVDP: |
| 4487 | case PPC::XVTDIVSP: { |
| 4488 | // op: CR |
| 4489 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4490 | op &= UINT64_C(7); |
| 4491 | op <<= 23; |
| 4492 | Value |= op; |
| 4493 | // op: XA |
| 4494 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4495 | Value |= (op & UINT64_C(31)) << 16; |
| 4496 | Value |= (op & UINT64_C(32)) >> 3; |
| 4497 | // op: XB |
| 4498 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4499 | Value |= (op & UINT64_C(31)) << 11; |
| 4500 | Value |= (op & UINT64_C(32)) >> 4; |
| 4501 | break; |
| 4502 | } |
| 4503 | case PPC::XSTSQRTDP: |
| 4504 | case PPC::XVTSQRTDP: |
| 4505 | case PPC::XVTSQRTSP: { |
| 4506 | // op: CR |
| 4507 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4508 | op &= UINT64_C(7); |
| 4509 | op <<= 23; |
| 4510 | Value |= op; |
| 4511 | // op: XB |
| 4512 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4513 | Value |= (op & UINT64_C(31)) << 11; |
| 4514 | Value |= (op & UINT64_C(32)) >> 4; |
| 4515 | break; |
| 4516 | } |
| 4517 | case PPC::CRSET: |
| 4518 | case PPC::CRUNSET: { |
| 4519 | // op: CRD |
| 4520 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4521 | Value |= (op & UINT64_C(31)) << 21; |
| 4522 | Value |= (op & UINT64_C(31)) << 16; |
| 4523 | Value |= (op & UINT64_C(31)) << 11; |
| 4524 | break; |
| 4525 | } |
| 4526 | case PPC::CRNOT: { |
| 4527 | // op: CRD |
| 4528 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4529 | op &= UINT64_C(31); |
| 4530 | op <<= 21; |
| 4531 | Value |= op; |
| 4532 | // op: CRA |
| 4533 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4534 | Value |= (op & UINT64_C(31)) << 16; |
| 4535 | Value |= (op & UINT64_C(31)) << 11; |
| 4536 | break; |
| 4537 | } |
| 4538 | case PPC::CRAND: |
| 4539 | case PPC::CRANDC: |
| 4540 | case PPC::CREQV: |
| 4541 | case PPC::CRNAND: |
| 4542 | case PPC::CRNOR: |
| 4543 | case PPC::CROR: |
| 4544 | case PPC::CRORC: |
| 4545 | case PPC::CRXOR: { |
| 4546 | // op: CRD |
| 4547 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4548 | op &= UINT64_C(31); |
| 4549 | op <<= 21; |
| 4550 | Value |= op; |
| 4551 | // op: CRA |
| 4552 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4553 | op &= UINT64_C(31); |
| 4554 | op <<= 16; |
| 4555 | Value |= op; |
| 4556 | // op: CRB |
| 4557 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4558 | op &= UINT64_C(31); |
| 4559 | op <<= 11; |
| 4560 | Value |= op; |
| 4561 | break; |
| 4562 | } |
| 4563 | case PPC::ICBLC: |
| 4564 | case PPC::ICBLQ: |
| 4565 | case PPC::ICBT: |
| 4566 | case PPC::ICBTLS: { |
| 4567 | // op: CT |
| 4568 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4569 | op &= UINT64_C(15); |
| 4570 | op <<= 21; |
| 4571 | Value |= op; |
| 4572 | // op: RA |
| 4573 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4574 | op &= UINT64_C(31); |
| 4575 | op <<= 16; |
| 4576 | Value |= op; |
| 4577 | // op: RB |
| 4578 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4579 | op &= UINT64_C(31); |
| 4580 | op <<= 11; |
| 4581 | Value |= op; |
| 4582 | break; |
| 4583 | } |
| 4584 | case PPC::WRTEEI: { |
| 4585 | // op: E |
| 4586 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4587 | op &= UINT64_C(1); |
| 4588 | op <<= 15; |
| 4589 | Value |= op; |
| 4590 | break; |
| 4591 | } |
| 4592 | case PPC::MTFSFb: { |
| 4593 | // op: FM |
| 4594 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4595 | op &= UINT64_C(255); |
| 4596 | op <<= 17; |
| 4597 | Value |= op; |
| 4598 | // op: RT |
| 4599 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4600 | op &= UINT64_C(31); |
| 4601 | op <<= 11; |
| 4602 | Value |= op; |
| 4603 | break; |
| 4604 | } |
| 4605 | case PPC::MTFSB0: |
| 4606 | case PPC::MTFSB1: { |
| 4607 | // op: FM |
| 4608 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4609 | op &= UINT64_C(31); |
| 4610 | op <<= 21; |
| 4611 | Value |= op; |
| 4612 | break; |
| 4613 | } |
| 4614 | case PPC::FADD: |
| 4615 | case PPC::FADDS: |
| 4616 | case PPC::FADDS_rec: |
| 4617 | case PPC::FADD_rec: |
| 4618 | case PPC::FDIV: |
| 4619 | case PPC::FDIVS: |
| 4620 | case PPC::FDIVS_rec: |
| 4621 | case PPC::FDIV_rec: |
| 4622 | case PPC::FSUB: |
| 4623 | case PPC::FSUBS: |
| 4624 | case PPC::FSUBS_rec: |
| 4625 | case PPC::FSUB_rec: |
| 4626 | case PPC::XSIEXPQP: { |
| 4627 | // op: FRT |
| 4628 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4629 | op &= UINT64_C(31); |
| 4630 | op <<= 21; |
| 4631 | Value |= op; |
| 4632 | // op: FRA |
| 4633 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4634 | op &= UINT64_C(31); |
| 4635 | op <<= 16; |
| 4636 | Value |= op; |
| 4637 | // op: FRB |
| 4638 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4639 | op &= UINT64_C(31); |
| 4640 | op <<= 11; |
| 4641 | Value |= op; |
| 4642 | break; |
| 4643 | } |
| 4644 | case PPC::DQUA: |
| 4645 | case PPC::DQUAQ: |
| 4646 | case PPC::DQUAQ_rec: |
| 4647 | case PPC::DQUA_rec: |
| 4648 | case PPC::DRRND: |
| 4649 | case PPC::DRRNDQ: |
| 4650 | case PPC::DRRNDQ_rec: |
| 4651 | case PPC::DRRND_rec: { |
| 4652 | // op: FRT |
| 4653 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4654 | op &= UINT64_C(31); |
| 4655 | op <<= 21; |
| 4656 | Value |= op; |
| 4657 | // op: FRA |
| 4658 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4659 | op &= UINT64_C(31); |
| 4660 | op <<= 16; |
| 4661 | Value |= op; |
| 4662 | // op: FRB |
| 4663 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4664 | op &= UINT64_C(31); |
| 4665 | op <<= 11; |
| 4666 | Value |= op; |
| 4667 | // op: RMC |
| 4668 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4669 | op &= UINT64_C(3); |
| 4670 | op <<= 9; |
| 4671 | Value |= op; |
| 4672 | break; |
| 4673 | } |
| 4674 | case PPC::FMUL: |
| 4675 | case PPC::FMULS: |
| 4676 | case PPC::FMULS_rec: |
| 4677 | case PPC::FMUL_rec: { |
| 4678 | // op: FRT |
| 4679 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4680 | op &= UINT64_C(31); |
| 4681 | op <<= 21; |
| 4682 | Value |= op; |
| 4683 | // op: FRA |
| 4684 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4685 | op &= UINT64_C(31); |
| 4686 | op <<= 16; |
| 4687 | Value |= op; |
| 4688 | // op: FRC |
| 4689 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4690 | op &= UINT64_C(31); |
| 4691 | op <<= 6; |
| 4692 | Value |= op; |
| 4693 | break; |
| 4694 | } |
| 4695 | case PPC::FMADD: |
| 4696 | case PPC::FMADDS: |
| 4697 | case PPC::FMADDS_rec: |
| 4698 | case PPC::FMADD_rec: |
| 4699 | case PPC::FMSUB: |
| 4700 | case PPC::FMSUBS: |
| 4701 | case PPC::FMSUBS_rec: |
| 4702 | case PPC::FMSUB_rec: |
| 4703 | case PPC::FNMADD: |
| 4704 | case PPC::FNMADDS: |
| 4705 | case PPC::FNMADDS_rec: |
| 4706 | case PPC::FNMADD_rec: |
| 4707 | case PPC::FNMSUB: |
| 4708 | case PPC::FNMSUBS: |
| 4709 | case PPC::FNMSUBS_rec: |
| 4710 | case PPC::FNMSUB_rec: |
| 4711 | case PPC::FSELD: |
| 4712 | case PPC::FSELD_rec: |
| 4713 | case PPC::FSELS: |
| 4714 | case PPC::FSELS_rec: { |
| 4715 | // op: FRT |
| 4716 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4717 | op &= UINT64_C(31); |
| 4718 | op <<= 21; |
| 4719 | Value |= op; |
| 4720 | // op: FRA |
| 4721 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4722 | op &= UINT64_C(31); |
| 4723 | op <<= 16; |
| 4724 | Value |= op; |
| 4725 | // op: FRC |
| 4726 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4727 | op &= UINT64_C(31); |
| 4728 | op <<= 6; |
| 4729 | Value |= op; |
| 4730 | // op: FRB |
| 4731 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4732 | op &= UINT64_C(31); |
| 4733 | op <<= 11; |
| 4734 | Value |= op; |
| 4735 | break; |
| 4736 | } |
| 4737 | case PPC::DSCLI: |
| 4738 | case PPC::DSCLIQ: |
| 4739 | case PPC::DSCLIQ_rec: |
| 4740 | case PPC::DSCLI_rec: |
| 4741 | case PPC::DSCRI: |
| 4742 | case PPC::DSCRIQ: |
| 4743 | case PPC::DSCRIQ_rec: |
| 4744 | case PPC::DSCRI_rec: { |
| 4745 | // op: FRT |
| 4746 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4747 | op &= UINT64_C(31); |
| 4748 | op <<= 21; |
| 4749 | Value |= op; |
| 4750 | // op: FRA |
| 4751 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4752 | op &= UINT64_C(31); |
| 4753 | op <<= 16; |
| 4754 | Value |= op; |
| 4755 | // op: SH |
| 4756 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4757 | op &= UINT64_C(63); |
| 4758 | op <<= 10; |
| 4759 | Value |= op; |
| 4760 | break; |
| 4761 | } |
| 4762 | case PPC::DQUAI: |
| 4763 | case PPC::DQUAIQ: |
| 4764 | case PPC::DQUAIQ_rec: |
| 4765 | case PPC::DQUAI_rec: { |
| 4766 | // op: FRT |
| 4767 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4768 | op &= UINT64_C(31); |
| 4769 | op <<= 21; |
| 4770 | Value |= op; |
| 4771 | // op: FRB |
| 4772 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4773 | op &= UINT64_C(31); |
| 4774 | op <<= 11; |
| 4775 | Value |= op; |
| 4776 | // op: RMC |
| 4777 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4778 | op &= UINT64_C(3); |
| 4779 | op <<= 9; |
| 4780 | Value |= op; |
| 4781 | // op: TE |
| 4782 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4783 | op &= UINT64_C(31); |
| 4784 | op <<= 16; |
| 4785 | Value |= op; |
| 4786 | break; |
| 4787 | } |
| 4788 | case PPC::DRINTN: |
| 4789 | case PPC::DRINTNQ: |
| 4790 | case PPC::DRINTNQ_rec: |
| 4791 | case PPC::DRINTN_rec: |
| 4792 | case PPC::DRINTX: |
| 4793 | case PPC::DRINTXQ: |
| 4794 | case PPC::DRINTXQ_rec: |
| 4795 | case PPC::DRINTX_rec: { |
| 4796 | // op: FRT |
| 4797 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4798 | op &= UINT64_C(31); |
| 4799 | op <<= 21; |
| 4800 | Value |= op; |
| 4801 | // op: R |
| 4802 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4803 | op &= UINT64_C(1); |
| 4804 | op <<= 16; |
| 4805 | Value |= op; |
| 4806 | // op: FRB |
| 4807 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4808 | op &= UINT64_C(31); |
| 4809 | op <<= 11; |
| 4810 | Value |= op; |
| 4811 | // op: RMC |
| 4812 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4813 | op &= UINT64_C(3); |
| 4814 | op <<= 9; |
| 4815 | Value |= op; |
| 4816 | break; |
| 4817 | } |
| 4818 | case PPC::MTCRF: |
| 4819 | case PPC::MTCRF8: { |
| 4820 | // op: FXM |
| 4821 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4822 | op &= UINT64_C(255); |
| 4823 | op <<= 12; |
| 4824 | Value |= op; |
| 4825 | // op: RST |
| 4826 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4827 | op &= UINT64_C(31); |
| 4828 | op <<= 21; |
| 4829 | Value |= op; |
| 4830 | break; |
| 4831 | } |
| 4832 | case PPC::TSR: { |
| 4833 | // op: L |
| 4834 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4835 | op &= UINT64_C(1); |
| 4836 | op <<= 21; |
| 4837 | Value |= op; |
| 4838 | break; |
| 4839 | } |
| 4840 | case PPC::SYNC: |
| 4841 | case PPC::WAIT: { |
| 4842 | // op: L |
| 4843 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4844 | op &= UINT64_C(3); |
| 4845 | op <<= 21; |
| 4846 | Value |= op; |
| 4847 | break; |
| 4848 | } |
| 4849 | case PPC::WAITP10: { |
| 4850 | // op: L |
| 4851 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4852 | op &= UINT64_C(3); |
| 4853 | op <<= 21; |
| 4854 | Value |= op; |
| 4855 | // op: PL |
| 4856 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4857 | op &= UINT64_C(3); |
| 4858 | op <<= 16; |
| 4859 | Value |= op; |
| 4860 | break; |
| 4861 | } |
| 4862 | case PPC::SYNCP10: { |
| 4863 | // op: L |
| 4864 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4865 | op &= UINT64_C(7); |
| 4866 | op <<= 21; |
| 4867 | Value |= op; |
| 4868 | // op: SC |
| 4869 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4870 | op &= UINT64_C(3); |
| 4871 | op <<= 16; |
| 4872 | Value |= op; |
| 4873 | break; |
| 4874 | } |
| 4875 | case PPC::CP_PASTE8_rec: |
| 4876 | case PPC::CP_PASTE_rec: { |
| 4877 | // op: L |
| 4878 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4879 | op &= UINT64_C(1); |
| 4880 | op <<= 21; |
| 4881 | Value |= op; |
| 4882 | // op: RA |
| 4883 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4884 | op &= UINT64_C(31); |
| 4885 | op <<= 16; |
| 4886 | Value |= op; |
| 4887 | // op: RB |
| 4888 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4889 | op &= UINT64_C(31); |
| 4890 | op <<= 11; |
| 4891 | Value |= op; |
| 4892 | break; |
| 4893 | } |
| 4894 | case PPC::MTFSF: |
| 4895 | case PPC::MTFSF_rec: { |
| 4896 | // op: L |
| 4897 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4898 | op &= UINT64_C(1); |
| 4899 | op <<= 25; |
| 4900 | Value |= op; |
| 4901 | // op: FLM |
| 4902 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4903 | op &= UINT64_C(255); |
| 4904 | op <<= 17; |
| 4905 | Value |= op; |
| 4906 | // op: W |
| 4907 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4908 | op &= UINT64_C(1); |
| 4909 | op <<= 16; |
| 4910 | Value |= op; |
| 4911 | // op: FRB |
| 4912 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4913 | op &= UINT64_C(31); |
| 4914 | op <<= 11; |
| 4915 | Value |= op; |
| 4916 | break; |
| 4917 | } |
| 4918 | case PPC::SC: |
| 4919 | case PPC::SCV: { |
| 4920 | // op: LEV |
| 4921 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4922 | op &= UINT64_C(127); |
| 4923 | op <<= 5; |
| 4924 | Value |= op; |
| 4925 | break; |
| 4926 | } |
| 4927 | case PPC::BA: |
| 4928 | case PPC::BLA: |
| 4929 | case PPC::BLA8: |
| 4930 | case PPC::BLA8_RM: |
| 4931 | case PPC::BLA_RM: |
| 4932 | case PPC::TAILBA: |
| 4933 | case PPC::TAILBA8: { |
| 4934 | // op: LI |
| 4935 | op = getAbsDirectBrEncoding(MI, OpNo: 0, Fixups, STI); |
| 4936 | op &= UINT64_C(16777215); |
| 4937 | op <<= 2; |
| 4938 | Value |= op; |
| 4939 | break; |
| 4940 | } |
| 4941 | case PPC::BLA8_NOP: |
| 4942 | case PPC::BLA8_NOP_RM: { |
| 4943 | // op: LI |
| 4944 | op = getAbsDirectBrEncoding(MI, OpNo: 0, Fixups, STI); |
| 4945 | op &= UINT64_C(16777215); |
| 4946 | op <<= 34; |
| 4947 | Value |= op; |
| 4948 | break; |
| 4949 | } |
| 4950 | case PPC::B: |
| 4951 | case PPC::BL: |
| 4952 | case PPC::BL8: |
| 4953 | case PPC::BL8_NOTOC: |
| 4954 | case PPC::BL8_NOTOC_RM: |
| 4955 | case PPC::BL8_RM: |
| 4956 | case PPC::BL_RM: |
| 4957 | case PPC::TAILB: |
| 4958 | case PPC::TAILB8: { |
| 4959 | // op: LI |
| 4960 | op = getDirectBrEncoding(MI, OpNo: 0, Fixups, STI); |
| 4961 | op &= UINT64_C(16777215); |
| 4962 | op <<= 2; |
| 4963 | Value |= op; |
| 4964 | break; |
| 4965 | } |
| 4966 | case PPC::BL8_NOP: |
| 4967 | case PPC::BL8_NOP_RM: |
| 4968 | case PPC::BL_NOP: |
| 4969 | case PPC::BL_NOP_RM: { |
| 4970 | // op: LI |
| 4971 | op = getDirectBrEncoding(MI, OpNo: 0, Fixups, STI); |
| 4972 | op &= UINT64_C(16777215); |
| 4973 | op <<= 34; |
| 4974 | Value |= op; |
| 4975 | break; |
| 4976 | } |
| 4977 | case PPC::BL8_NOTOC_TLS: |
| 4978 | case PPC::BL8_TLS: |
| 4979 | case PPC::BL8_TLS_: |
| 4980 | case PPC::BL_TLS: { |
| 4981 | // op: LI |
| 4982 | op = getTLSCallEncoding(MI, OpNo: 0, Fixups, STI); |
| 4983 | op &= UINT64_C(16777215); |
| 4984 | op <<= 2; |
| 4985 | Value |= op; |
| 4986 | break; |
| 4987 | } |
| 4988 | case PPC::BL8_NOP_TLS: { |
| 4989 | // op: LI |
| 4990 | op = getTLSCallEncoding(MI, OpNo: 0, Fixups, STI); |
| 4991 | op &= UINT64_C(16777215); |
| 4992 | op <<= 34; |
| 4993 | Value |= op; |
| 4994 | break; |
| 4995 | } |
| 4996 | case PPC::MBAR: { |
| 4997 | // op: MO |
| 4998 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4999 | op &= UINT64_C(31); |
| 5000 | op <<= 21; |
| 5001 | Value |= op; |
| 5002 | break; |
| 5003 | } |
| 5004 | case PPC::TBEGIN: { |
| 5005 | // op: R |
| 5006 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5007 | op &= UINT64_C(1); |
| 5008 | op <<= 21; |
| 5009 | Value |= op; |
| 5010 | break; |
| 5011 | } |
| 5012 | case PPC::TABORT: |
| 5013 | case PPC::TRECLAIM: { |
| 5014 | // op: RA |
| 5015 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5016 | op &= UINT64_C(31); |
| 5017 | op <<= 16; |
| 5018 | Value |= op; |
| 5019 | break; |
| 5020 | } |
| 5021 | case PPC::CP_COPY: |
| 5022 | case PPC::CP_COPY8: |
| 5023 | case PPC::DCBA: |
| 5024 | case PPC::DCBFEP: |
| 5025 | case PPC::DCBI: |
| 5026 | case PPC::DCBST: |
| 5027 | case PPC::DCBSTEP: |
| 5028 | case PPC::DCBZ: |
| 5029 | case PPC::DCBZEP: |
| 5030 | case PPC::DCBZL: |
| 5031 | case PPC::DCBZLEP: |
| 5032 | case PPC::DCCCI: |
| 5033 | case PPC::ICBI: |
| 5034 | case PPC::ICBIEP: |
| 5035 | case PPC::ICCCI: |
| 5036 | case PPC::TLBIVAX: |
| 5037 | case PPC::TLBSX: { |
| 5038 | // op: RA |
| 5039 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5040 | op &= UINT64_C(31); |
| 5041 | op <<= 16; |
| 5042 | Value |= op; |
| 5043 | // op: RB |
| 5044 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5045 | op &= UINT64_C(31); |
| 5046 | op <<= 11; |
| 5047 | Value |= op; |
| 5048 | break; |
| 5049 | } |
| 5050 | case PPC::RLWNM: |
| 5051 | case PPC::RLWNM8: |
| 5052 | case PPC::RLWNM8_rec: |
| 5053 | case PPC::RLWNM_rec: { |
| 5054 | // op: RA |
| 5055 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5056 | op &= UINT64_C(31); |
| 5057 | op <<= 16; |
| 5058 | Value |= op; |
| 5059 | // op: RS |
| 5060 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5061 | op &= UINT64_C(31); |
| 5062 | op <<= 21; |
| 5063 | Value |= op; |
| 5064 | // op: RB |
| 5065 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5066 | op &= UINT64_C(31); |
| 5067 | op <<= 11; |
| 5068 | Value |= op; |
| 5069 | // op: MB |
| 5070 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5071 | op &= UINT64_C(31); |
| 5072 | op <<= 6; |
| 5073 | Value |= op; |
| 5074 | // op: ME |
| 5075 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 5076 | op &= UINT64_C(31); |
| 5077 | op <<= 1; |
| 5078 | Value |= op; |
| 5079 | break; |
| 5080 | } |
| 5081 | case PPC::RLDCL: |
| 5082 | case PPC::RLDCL_rec: |
| 5083 | case PPC::RLDCR: |
| 5084 | case PPC::RLDCR_rec: { |
| 5085 | // op: RA |
| 5086 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5087 | op &= UINT64_C(31); |
| 5088 | op <<= 16; |
| 5089 | Value |= op; |
| 5090 | // op: RS |
| 5091 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5092 | op &= UINT64_C(31); |
| 5093 | op <<= 21; |
| 5094 | Value |= op; |
| 5095 | // op: RB |
| 5096 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5097 | op &= UINT64_C(31); |
| 5098 | op <<= 11; |
| 5099 | Value |= op; |
| 5100 | // op: MBE |
| 5101 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5102 | Value |= (op & UINT64_C(31)) << 6; |
| 5103 | Value |= (op & UINT64_C(32)); |
| 5104 | break; |
| 5105 | } |
| 5106 | case PPC::EXTSWSLI: |
| 5107 | case PPC::EXTSWSLI_32_64: |
| 5108 | case PPC::EXTSWSLI_32_64_rec: |
| 5109 | case PPC::EXTSWSLI_rec: |
| 5110 | case PPC::SRADI: |
| 5111 | case PPC::SRADI_32: |
| 5112 | case PPC::SRADI_rec: { |
| 5113 | // op: RA |
| 5114 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5115 | op &= UINT64_C(31); |
| 5116 | op <<= 16; |
| 5117 | Value |= op; |
| 5118 | // op: RS |
| 5119 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5120 | op &= UINT64_C(31); |
| 5121 | op <<= 21; |
| 5122 | Value |= op; |
| 5123 | // op: SH |
| 5124 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5125 | Value |= (op & UINT64_C(31)) << 11; |
| 5126 | Value |= (op & UINT64_C(32)) >> 4; |
| 5127 | break; |
| 5128 | } |
| 5129 | case PPC::RLDIC: |
| 5130 | case PPC::RLDICL: |
| 5131 | case PPC::RLDICL_32: |
| 5132 | case PPC::RLDICL_32_64: |
| 5133 | case PPC::RLDICL_32_rec: |
| 5134 | case PPC::RLDICL_rec: |
| 5135 | case PPC::RLDICR: |
| 5136 | case PPC::RLDICR_32: |
| 5137 | case PPC::RLDICR_rec: |
| 5138 | case PPC::RLDIC_rec: { |
| 5139 | // op: RA |
| 5140 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5141 | op &= UINT64_C(31); |
| 5142 | op <<= 16; |
| 5143 | Value |= op; |
| 5144 | // op: RS |
| 5145 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5146 | op &= UINT64_C(31); |
| 5147 | op <<= 21; |
| 5148 | Value |= op; |
| 5149 | // op: SH |
| 5150 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5151 | Value |= (op & UINT64_C(31)) << 11; |
| 5152 | Value |= (op & UINT64_C(32)) >> 4; |
| 5153 | // op: MBE |
| 5154 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5155 | Value |= (op & UINT64_C(31)) << 6; |
| 5156 | Value |= (op & UINT64_C(32)); |
| 5157 | break; |
| 5158 | } |
| 5159 | case PPC::RLWINM: |
| 5160 | case PPC::RLWINM8: |
| 5161 | case PPC::RLWINM8_rec: |
| 5162 | case PPC::RLWINM_rec: { |
| 5163 | // op: RA |
| 5164 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5165 | op &= UINT64_C(31); |
| 5166 | op <<= 16; |
| 5167 | Value |= op; |
| 5168 | // op: RS |
| 5169 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5170 | op &= UINT64_C(31); |
| 5171 | op <<= 21; |
| 5172 | Value |= op; |
| 5173 | // op: SH |
| 5174 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5175 | op &= UINT64_C(31); |
| 5176 | op <<= 11; |
| 5177 | Value |= op; |
| 5178 | // op: MB |
| 5179 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5180 | op &= UINT64_C(31); |
| 5181 | op <<= 6; |
| 5182 | Value |= op; |
| 5183 | // op: ME |
| 5184 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 5185 | op &= UINT64_C(31); |
| 5186 | op <<= 1; |
| 5187 | Value |= op; |
| 5188 | break; |
| 5189 | } |
| 5190 | case PPC::RLDIMI: |
| 5191 | case PPC::RLDIMI_rec: { |
| 5192 | // op: RA |
| 5193 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5194 | op &= UINT64_C(31); |
| 5195 | op <<= 16; |
| 5196 | Value |= op; |
| 5197 | // op: RS |
| 5198 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5199 | op &= UINT64_C(31); |
| 5200 | op <<= 21; |
| 5201 | Value |= op; |
| 5202 | // op: SH |
| 5203 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5204 | Value |= (op & UINT64_C(31)) << 11; |
| 5205 | Value |= (op & UINT64_C(32)) >> 4; |
| 5206 | // op: MBE |
| 5207 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 5208 | Value |= (op & UINT64_C(31)) << 6; |
| 5209 | Value |= (op & UINT64_C(32)); |
| 5210 | break; |
| 5211 | } |
| 5212 | case PPC::RLWIMI: |
| 5213 | case PPC::RLWIMI8: |
| 5214 | case PPC::RLWIMI8_rec: |
| 5215 | case PPC::RLWIMI_rec: { |
| 5216 | // op: RA |
| 5217 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5218 | op &= UINT64_C(31); |
| 5219 | op <<= 16; |
| 5220 | Value |= op; |
| 5221 | // op: RS |
| 5222 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5223 | op &= UINT64_C(31); |
| 5224 | op <<= 21; |
| 5225 | Value |= op; |
| 5226 | // op: SH |
| 5227 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5228 | op &= UINT64_C(31); |
| 5229 | op <<= 11; |
| 5230 | Value |= op; |
| 5231 | // op: MB |
| 5232 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 5233 | op &= UINT64_C(31); |
| 5234 | op <<= 6; |
| 5235 | Value |= op; |
| 5236 | // op: ME |
| 5237 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 5238 | op &= UINT64_C(31); |
| 5239 | op <<= 1; |
| 5240 | Value |= op; |
| 5241 | break; |
| 5242 | } |
| 5243 | case PPC::BRD: |
| 5244 | case PPC::BRH: |
| 5245 | case PPC::BRH8: |
| 5246 | case PPC::BRW: |
| 5247 | case PPC::BRW8: |
| 5248 | case PPC::CBCDTD: |
| 5249 | case PPC::CBCDTD8: |
| 5250 | case PPC::CDTBCD: |
| 5251 | case PPC::CDTBCD8: |
| 5252 | case PPC::CNTLZD: |
| 5253 | case PPC::CNTLZD_rec: |
| 5254 | case PPC::CNTLZW: |
| 5255 | case PPC::CNTLZW8: |
| 5256 | case PPC::CNTLZW8_rec: |
| 5257 | case PPC::CNTLZW_rec: |
| 5258 | case PPC::CNTTZD: |
| 5259 | case PPC::CNTTZD_rec: |
| 5260 | case PPC::CNTTZW: |
| 5261 | case PPC::CNTTZW8: |
| 5262 | case PPC::CNTTZW8_rec: |
| 5263 | case PPC::CNTTZW_rec: |
| 5264 | case PPC::EXTSB: |
| 5265 | case PPC::EXTSB8: |
| 5266 | case PPC::EXTSB8_32_64: |
| 5267 | case PPC::EXTSB8_rec: |
| 5268 | case PPC::EXTSB_rec: |
| 5269 | case PPC::EXTSH: |
| 5270 | case PPC::EXTSH8: |
| 5271 | case PPC::EXTSH8_32_64: |
| 5272 | case PPC::EXTSH8_rec: |
| 5273 | case PPC::EXTSH_rec: |
| 5274 | case PPC::EXTSW: |
| 5275 | case PPC::EXTSW_32: |
| 5276 | case PPC::EXTSW_32_64: |
| 5277 | case PPC::EXTSW_32_64_rec: |
| 5278 | case PPC::EXTSW_rec: |
| 5279 | case PPC::POPCNTB: |
| 5280 | case PPC::POPCNTB8: |
| 5281 | case PPC::POPCNTD: |
| 5282 | case PPC::POPCNTW: { |
| 5283 | // op: RA |
| 5284 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5285 | op &= UINT64_C(31); |
| 5286 | op <<= 16; |
| 5287 | Value |= op; |
| 5288 | // op: RST |
| 5289 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5290 | op &= UINT64_C(31); |
| 5291 | op <<= 21; |
| 5292 | Value |= op; |
| 5293 | break; |
| 5294 | } |
| 5295 | case PPC::ANDI8_rec: |
| 5296 | case PPC::ANDIS8_rec: |
| 5297 | case PPC::ANDIS_rec: |
| 5298 | case PPC::ANDI_rec: |
| 5299 | case PPC::ORI: |
| 5300 | case PPC::ORI8: |
| 5301 | case PPC::ORIS: |
| 5302 | case PPC::ORIS8: |
| 5303 | case PPC::XORI: |
| 5304 | case PPC::XORI8: |
| 5305 | case PPC::XORIS: |
| 5306 | case PPC::XORIS8: { |
| 5307 | // op: RA |
| 5308 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5309 | op &= UINT64_C(31); |
| 5310 | op <<= 16; |
| 5311 | Value |= op; |
| 5312 | // op: RST |
| 5313 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5314 | op &= UINT64_C(31); |
| 5315 | op <<= 21; |
| 5316 | Value |= op; |
| 5317 | // op: D |
| 5318 | op = getImm16Encoding(MI, OpNo: 2, Fixups, STI); |
| 5319 | op &= UINT64_C(65535); |
| 5320 | Value |= op; |
| 5321 | break; |
| 5322 | } |
| 5323 | case PPC::AND: |
| 5324 | case PPC::AND8: |
| 5325 | case PPC::AND8_rec: |
| 5326 | case PPC::ANDC: |
| 5327 | case PPC::ANDC8: |
| 5328 | case PPC::ANDC8_rec: |
| 5329 | case PPC::ANDC_rec: |
| 5330 | case PPC::AND_rec: |
| 5331 | case PPC::BPERMD: |
| 5332 | case PPC::CFUGED: |
| 5333 | case PPC::CMPB: |
| 5334 | case PPC::CMPB8: |
| 5335 | case PPC::CNTLZDM: |
| 5336 | case PPC::CNTTZDM: |
| 5337 | case PPC::EQV: |
| 5338 | case PPC::EQV8: |
| 5339 | case PPC::EQV8_rec: |
| 5340 | case PPC::EQV_rec: |
| 5341 | case PPC::NAND: |
| 5342 | case PPC::NAND8: |
| 5343 | case PPC::NAND8_rec: |
| 5344 | case PPC::NAND_rec: |
| 5345 | case PPC::NOR: |
| 5346 | case PPC::NOR8: |
| 5347 | case PPC::NOR8_rec: |
| 5348 | case PPC::NOR_rec: |
| 5349 | case PPC::OR: |
| 5350 | case PPC::OR8: |
| 5351 | case PPC::OR8_rec: |
| 5352 | case PPC::ORC: |
| 5353 | case PPC::ORC8: |
| 5354 | case PPC::ORC8_rec: |
| 5355 | case PPC::ORC_rec: |
| 5356 | case PPC::OR_rec: |
| 5357 | case PPC::PDEPD: |
| 5358 | case PPC::PEXTD: |
| 5359 | case PPC::SLD: |
| 5360 | case PPC::SLD_rec: |
| 5361 | case PPC::SLW: |
| 5362 | case PPC::SLW8: |
| 5363 | case PPC::SLW8_rec: |
| 5364 | case PPC::SLW_rec: |
| 5365 | case PPC::SRAD: |
| 5366 | case PPC::SRAD_rec: |
| 5367 | case PPC::SRAW: |
| 5368 | case PPC::SRAW8: |
| 5369 | case PPC::SRAW8_rec: |
| 5370 | case PPC::SRAWI: |
| 5371 | case PPC::SRAWI8: |
| 5372 | case PPC::SRAWI8_rec: |
| 5373 | case PPC::SRAWI_rec: |
| 5374 | case PPC::SRAW_rec: |
| 5375 | case PPC::SRD: |
| 5376 | case PPC::SRD_rec: |
| 5377 | case PPC::SRW: |
| 5378 | case PPC::SRW8: |
| 5379 | case PPC::SRW8_rec: |
| 5380 | case PPC::SRW_rec: |
| 5381 | case PPC::XOR: |
| 5382 | case PPC::XOR8: |
| 5383 | case PPC::XOR8_rec: |
| 5384 | case PPC::XOR_rec: { |
| 5385 | // op: RA |
| 5386 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5387 | op &= UINT64_C(31); |
| 5388 | op <<= 16; |
| 5389 | Value |= op; |
| 5390 | // op: RST |
| 5391 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5392 | op &= UINT64_C(31); |
| 5393 | op <<= 21; |
| 5394 | Value |= op; |
| 5395 | // op: RB |
| 5396 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5397 | op &= UINT64_C(31); |
| 5398 | op <<= 11; |
| 5399 | Value |= op; |
| 5400 | break; |
| 5401 | } |
| 5402 | case PPC::BCTRL_LWZinto_toc: |
| 5403 | case PPC::BCTRL_LWZinto_toc_RM: { |
| 5404 | // op: RA |
| 5405 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5406 | op &= UINT64_C(31); |
| 5407 | op <<= 16; |
| 5408 | Value |= op; |
| 5409 | // op: D |
| 5410 | op = getDispRIEncoding(MI, OpNo: 0, Fixups, STI); |
| 5411 | op &= UINT64_C(65535); |
| 5412 | Value |= op; |
| 5413 | break; |
| 5414 | } |
| 5415 | case PPC::BCTRL8_LDinto_toc: |
| 5416 | case PPC::BCTRL8_LDinto_toc_RM: { |
| 5417 | // op: RA |
| 5418 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5419 | op &= UINT64_C(31); |
| 5420 | op <<= 16; |
| 5421 | Value |= op; |
| 5422 | // op: D |
| 5423 | op = getDispRIXEncoding(MI, OpNo: 0, Fixups, STI); |
| 5424 | op &= UINT64_C(16383); |
| 5425 | op <<= 2; |
| 5426 | Value |= op; |
| 5427 | break; |
| 5428 | } |
| 5429 | case PPC::TLBILX: { |
| 5430 | // op: RA |
| 5431 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5432 | op &= UINT64_C(31); |
| 5433 | op <<= 16; |
| 5434 | Value |= op; |
| 5435 | // op: RB |
| 5436 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5437 | op &= UINT64_C(31); |
| 5438 | op <<= 11; |
| 5439 | Value |= op; |
| 5440 | // op: T |
| 5441 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5442 | op &= UINT64_C(31); |
| 5443 | op <<= 21; |
| 5444 | Value |= op; |
| 5445 | break; |
| 5446 | } |
| 5447 | case PPC::HASHCHK: |
| 5448 | case PPC::HASHCHK8: |
| 5449 | case PPC::HASHCHKP: |
| 5450 | case PPC::HASHCHKP8: |
| 5451 | case PPC::HASHST: |
| 5452 | case PPC::HASHST8: |
| 5453 | case PPC::HASHSTP: |
| 5454 | case PPC::HASHSTP8: { |
| 5455 | // op: RA |
| 5456 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5457 | op &= UINT64_C(31); |
| 5458 | op <<= 16; |
| 5459 | Value |= op; |
| 5460 | // op: D |
| 5461 | op = getDispRIHashEncoding(MI, OpNo: 1, Fixups, STI); |
| 5462 | Value |= (op & UINT64_C(31)) << 21; |
| 5463 | Value |= (op & UINT64_C(32)) >> 5; |
| 5464 | // op: RB |
| 5465 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5466 | op &= UINT64_C(31); |
| 5467 | op <<= 11; |
| 5468 | Value |= op; |
| 5469 | break; |
| 5470 | } |
| 5471 | case PPC::SLBIE: |
| 5472 | case PPC::TLBIEL: |
| 5473 | case PPC::TLBLD: |
| 5474 | case PPC::TLBLI: { |
| 5475 | // op: RB |
| 5476 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5477 | op &= UINT64_C(31); |
| 5478 | op <<= 11; |
| 5479 | Value |= op; |
| 5480 | break; |
| 5481 | } |
| 5482 | case PPC::VCNTMBB: |
| 5483 | case PPC::VCNTMBD: |
| 5484 | case PPC::VCNTMBH: |
| 5485 | case PPC::VCNTMBW: { |
| 5486 | // op: RD |
| 5487 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5488 | op &= UINT64_C(31); |
| 5489 | op <<= 21; |
| 5490 | Value |= op; |
| 5491 | // op: VB |
| 5492 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5493 | op &= UINT64_C(31); |
| 5494 | op <<= 11; |
| 5495 | Value |= op; |
| 5496 | // op: MP |
| 5497 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5498 | op &= UINT64_C(1); |
| 5499 | op <<= 16; |
| 5500 | Value |= op; |
| 5501 | break; |
| 5502 | } |
| 5503 | case PPC::VGNB: { |
| 5504 | // op: RD |
| 5505 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5506 | op &= UINT64_C(31); |
| 5507 | op <<= 21; |
| 5508 | Value |= op; |
| 5509 | // op: VB |
| 5510 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5511 | op &= UINT64_C(31); |
| 5512 | op <<= 11; |
| 5513 | Value |= op; |
| 5514 | // op: N |
| 5515 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5516 | op &= UINT64_C(7); |
| 5517 | op <<= 16; |
| 5518 | Value |= op; |
| 5519 | break; |
| 5520 | } |
| 5521 | case PPC::WRTEE: { |
| 5522 | // op: RS |
| 5523 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5524 | op &= UINT64_C(31); |
| 5525 | op <<= 21; |
| 5526 | Value |= op; |
| 5527 | break; |
| 5528 | } |
| 5529 | case PPC::MTMSR: |
| 5530 | case PPC::MTMSRD: { |
| 5531 | // op: RS |
| 5532 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5533 | op &= UINT64_C(31); |
| 5534 | op <<= 21; |
| 5535 | Value |= op; |
| 5536 | // op: L |
| 5537 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5538 | op &= UINT64_C(1); |
| 5539 | op <<= 16; |
| 5540 | Value |= op; |
| 5541 | break; |
| 5542 | } |
| 5543 | case PPC::MFSRIN: |
| 5544 | case PPC::MTSRIN: { |
| 5545 | // op: RS |
| 5546 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5547 | op &= UINT64_C(31); |
| 5548 | op <<= 21; |
| 5549 | Value |= op; |
| 5550 | // op: RB |
| 5551 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5552 | op &= UINT64_C(31); |
| 5553 | op <<= 11; |
| 5554 | Value |= op; |
| 5555 | break; |
| 5556 | } |
| 5557 | case PPC::MFSR: |
| 5558 | case PPC::MTSR: { |
| 5559 | // op: RS |
| 5560 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5561 | op &= UINT64_C(31); |
| 5562 | op <<= 21; |
| 5563 | Value |= op; |
| 5564 | // op: SR |
| 5565 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5566 | op &= UINT64_C(15); |
| 5567 | op <<= 16; |
| 5568 | Value |= op; |
| 5569 | break; |
| 5570 | } |
| 5571 | case PPC::MFCTR: |
| 5572 | case PPC::MFCTR8: |
| 5573 | case PPC::MFFS: |
| 5574 | case PPC::MFFSCE: |
| 5575 | case PPC::MFFSL: |
| 5576 | case PPC::MFFS_rec: |
| 5577 | case PPC::MFLR: |
| 5578 | case PPC::MFLR8: |
| 5579 | case PPC::MFMSR: |
| 5580 | case PPC::MFTB8: |
| 5581 | case PPC::MFUDSCR: |
| 5582 | case PPC::MFVRSAVE: |
| 5583 | case PPC::MFVRSAVEv: |
| 5584 | case PPC::MTCTR: |
| 5585 | case PPC::MTCTR8: |
| 5586 | case PPC::MTCTR8loop: |
| 5587 | case PPC::MTCTRloop: |
| 5588 | case PPC::MTLR: |
| 5589 | case PPC::MTLR8: |
| 5590 | case PPC::MTUDSCR: |
| 5591 | case PPC::MTVRSAVE: { |
| 5592 | // op: RST |
| 5593 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5594 | op &= UINT64_C(31); |
| 5595 | op <<= 21; |
| 5596 | Value |= op; |
| 5597 | break; |
| 5598 | } |
| 5599 | case PPC::SETBC: |
| 5600 | case PPC::SETBC8: |
| 5601 | case PPC::SETBCR: |
| 5602 | case PPC::SETBCR8: |
| 5603 | case PPC::SETNBC: |
| 5604 | case PPC::SETNBC8: |
| 5605 | case PPC::SETNBCR: |
| 5606 | case PPC::SETNBCR8: { |
| 5607 | // op: RST |
| 5608 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5609 | op &= UINT64_C(31); |
| 5610 | op <<= 21; |
| 5611 | Value |= op; |
| 5612 | // op: BI |
| 5613 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5614 | op &= UINT64_C(31); |
| 5615 | op <<= 16; |
| 5616 | Value |= op; |
| 5617 | break; |
| 5618 | } |
| 5619 | case PPC::LI: |
| 5620 | case PPC::LI8: |
| 5621 | case PPC::LIS: |
| 5622 | case PPC::LIS8: { |
| 5623 | // op: RST |
| 5624 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5625 | op &= UINT64_C(31); |
| 5626 | op <<= 21; |
| 5627 | Value |= op; |
| 5628 | // op: D |
| 5629 | op = getImm16Encoding(MI, OpNo: 1, Fixups, STI); |
| 5630 | op &= UINT64_C(65535); |
| 5631 | Value |= op; |
| 5632 | break; |
| 5633 | } |
| 5634 | case PPC::PLBZ8onlypc: |
| 5635 | case PPC::PLBZonlypc: |
| 5636 | case PPC::PLDonlypc: |
| 5637 | case PPC::PLFDonlypc: |
| 5638 | case PPC::PLFSonlypc: |
| 5639 | case PPC::PLHA8onlypc: |
| 5640 | case PPC::PLHAonlypc: |
| 5641 | case PPC::PLHZ8onlypc: |
| 5642 | case PPC::PLHZonlypc: |
| 5643 | case PPC::PLWA8onlypc: |
| 5644 | case PPC::PLWAonlypc: |
| 5645 | case PPC::PLWZ8onlypc: |
| 5646 | case PPC::PLWZonlypc: |
| 5647 | case PPC::PLXSDonlypc: |
| 5648 | case PPC::PLXSSPonlypc: |
| 5649 | case PPC::PSTB8onlypc: |
| 5650 | case PPC::PSTBonlypc: |
| 5651 | case PPC::PSTDonlypc: |
| 5652 | case PPC::PSTFDonlypc: |
| 5653 | case PPC::PSTFSonlypc: |
| 5654 | case PPC::PSTH8onlypc: |
| 5655 | case PPC::PSTHonlypc: |
| 5656 | case PPC::PSTW8onlypc: |
| 5657 | case PPC::PSTWonlypc: |
| 5658 | case PPC::PSTXSDonlypc: |
| 5659 | case PPC::PSTXSSPonlypc: { |
| 5660 | // op: RST |
| 5661 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5662 | op &= UINT64_C(31); |
| 5663 | op <<= 21; |
| 5664 | Value |= op; |
| 5665 | // op: D |
| 5666 | op = getImm34EncodingPCRel(MI, OpNo: 1, Fixups, STI); |
| 5667 | Value |= (op & UINT64_C(17179803648)) << 16; |
| 5668 | Value |= (op & UINT64_C(65535)); |
| 5669 | break; |
| 5670 | } |
| 5671 | case PPC::MFFSCDRNI: { |
| 5672 | // op: RST |
| 5673 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5674 | op &= UINT64_C(31); |
| 5675 | op <<= 21; |
| 5676 | Value |= op; |
| 5677 | // op: DRM |
| 5678 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5679 | op &= UINT64_C(7); |
| 5680 | op <<= 11; |
| 5681 | Value |= op; |
| 5682 | break; |
| 5683 | } |
| 5684 | case PPC::MFFSCDRN: |
| 5685 | case PPC::MFFSCRN: { |
| 5686 | // op: RST |
| 5687 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5688 | op &= UINT64_C(31); |
| 5689 | op <<= 21; |
| 5690 | Value |= op; |
| 5691 | // op: FRB |
| 5692 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5693 | op &= UINT64_C(31); |
| 5694 | op <<= 11; |
| 5695 | Value |= op; |
| 5696 | break; |
| 5697 | } |
| 5698 | case PPC::MFOCRF: |
| 5699 | case PPC::MFOCRF8: { |
| 5700 | // op: RST |
| 5701 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5702 | op &= UINT64_C(31); |
| 5703 | op <<= 21; |
| 5704 | Value |= op; |
| 5705 | // op: FXM |
| 5706 | op = get_crbitm_encoding(MI, OpNo: 1, Fixups, STI); |
| 5707 | op &= UINT64_C(255); |
| 5708 | op <<= 12; |
| 5709 | Value |= op; |
| 5710 | break; |
| 5711 | } |
| 5712 | case PPC::ADDI: |
| 5713 | case PPC::ADDI8: |
| 5714 | case PPC::ADDIC: |
| 5715 | case PPC::ADDIC8: |
| 5716 | case PPC::ADDIC_rec: |
| 5717 | case PPC::ADDIS: |
| 5718 | case PPC::ADDIS8: |
| 5719 | case PPC::LA: |
| 5720 | case PPC::LA8: |
| 5721 | case PPC::MULLI: |
| 5722 | case PPC::MULLI8: |
| 5723 | case PPC::SUBFIC: |
| 5724 | case PPC::SUBFIC8: |
| 5725 | case PPC::TDI: |
| 5726 | case PPC::TWI: { |
| 5727 | // op: RST |
| 5728 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5729 | op &= UINT64_C(31); |
| 5730 | op <<= 21; |
| 5731 | Value |= op; |
| 5732 | // op: RA |
| 5733 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5734 | op &= UINT64_C(31); |
| 5735 | op <<= 16; |
| 5736 | Value |= op; |
| 5737 | // op: D |
| 5738 | op = getImm16Encoding(MI, OpNo: 2, Fixups, STI); |
| 5739 | op &= UINT64_C(65535); |
| 5740 | Value |= op; |
| 5741 | break; |
| 5742 | } |
| 5743 | case PPC::DADD: |
| 5744 | case PPC::DADDQ: |
| 5745 | case PPC::DADDQ_rec: |
| 5746 | case PPC::DADD_rec: |
| 5747 | case PPC::DDIV: |
| 5748 | case PPC::DDIVQ: |
| 5749 | case PPC::DDIVQ_rec: |
| 5750 | case PPC::DDIV_rec: |
| 5751 | case PPC::DIEX: |
| 5752 | case PPC::DIEXQ: |
| 5753 | case PPC::DIEXQ_rec: |
| 5754 | case PPC::DIEX_rec: |
| 5755 | case PPC::DMUL: |
| 5756 | case PPC::DMULQ: |
| 5757 | case PPC::DMULQ_rec: |
| 5758 | case PPC::DMUL_rec: |
| 5759 | case PPC::DSUB: |
| 5760 | case PPC::DSUBQ: |
| 5761 | case PPC::DSUBQ_rec: |
| 5762 | case PPC::DSUB_rec: |
| 5763 | case PPC::FCPSGND: |
| 5764 | case PPC::FCPSGND_rec: |
| 5765 | case PPC::FCPSGNS: |
| 5766 | case PPC::FCPSGNS_rec: |
| 5767 | case PPC::LBARX: |
| 5768 | case PPC::LBARXL: |
| 5769 | case PPC::LBEPX: |
| 5770 | case PPC::LBZCIX: |
| 5771 | case PPC::LBZX: |
| 5772 | case PPC::LBZX8: |
| 5773 | case PPC::LDARX: |
| 5774 | case PPC::LDARXL: |
| 5775 | case PPC::LDAT: |
| 5776 | case PPC::LDBRX: |
| 5777 | case PPC::LDCIX: |
| 5778 | case PPC::LDX: |
| 5779 | case PPC::LFDEPX: |
| 5780 | case PPC::LFDX: |
| 5781 | case PPC::LFIWAX: |
| 5782 | case PPC::LFIWZX: |
| 5783 | case PPC::LFSX: |
| 5784 | case PPC::LHARX: |
| 5785 | case PPC::LHARXL: |
| 5786 | case PPC::LHAX: |
| 5787 | case PPC::LHAX8: |
| 5788 | case PPC::LHBRX: |
| 5789 | case PPC::LHBRX8: |
| 5790 | case PPC::LHEPX: |
| 5791 | case PPC::LHZCIX: |
| 5792 | case PPC::LHZX: |
| 5793 | case PPC::LHZX8: |
| 5794 | case PPC::LQARX: |
| 5795 | case PPC::LQARXL: |
| 5796 | case PPC::LSWI: |
| 5797 | case PPC::LVEBX: |
| 5798 | case PPC::LVEHX: |
| 5799 | case PPC::LVEWX: |
| 5800 | case PPC::LVSL: |
| 5801 | case PPC::LVSR: |
| 5802 | case PPC::LVX: |
| 5803 | case PPC::LVXL: |
| 5804 | case PPC::LWARX: |
| 5805 | case PPC::LWARXL: |
| 5806 | case PPC::LWAT: |
| 5807 | case PPC::LWAX: |
| 5808 | case PPC::LWAX_32: |
| 5809 | case PPC::LWBRX: |
| 5810 | case PPC::LWBRX8: |
| 5811 | case PPC::LWEPX: |
| 5812 | case PPC::LWZCIX: |
| 5813 | case PPC::LWZX: |
| 5814 | case PPC::LWZX8: |
| 5815 | case PPC::MODSD: |
| 5816 | case PPC::MODSW: |
| 5817 | case PPC::MODUD: |
| 5818 | case PPC::MODUW: |
| 5819 | case PPC::SPELWZX: |
| 5820 | case PPC::SPESTWX: |
| 5821 | case PPC::STBCIX: |
| 5822 | case PPC::STBCX: |
| 5823 | case PPC::STBEPX: |
| 5824 | case PPC::STBX: |
| 5825 | case PPC::STBX8: |
| 5826 | case PPC::STDAT: |
| 5827 | case PPC::STDBRX: |
| 5828 | case PPC::STDCIX: |
| 5829 | case PPC::STDCX: |
| 5830 | case PPC::STDX: |
| 5831 | case PPC::STFDEPX: |
| 5832 | case PPC::STFDX: |
| 5833 | case PPC::STFIWX: |
| 5834 | case PPC::STFSX: |
| 5835 | case PPC::STHBRX: |
| 5836 | case PPC::STHCIX: |
| 5837 | case PPC::STHCX: |
| 5838 | case PPC::STHEPX: |
| 5839 | case PPC::STHX: |
| 5840 | case PPC::STHX8: |
| 5841 | case PPC::STQCX: |
| 5842 | case PPC::STSWI: |
| 5843 | case PPC::STVEBX: |
| 5844 | case PPC::STVEHX: |
| 5845 | case PPC::STVEWX: |
| 5846 | case PPC::STVX: |
| 5847 | case PPC::STVXL: |
| 5848 | case PPC::STWAT: |
| 5849 | case PPC::STWBRX: |
| 5850 | case PPC::STWCIX: |
| 5851 | case PPC::STWCX: |
| 5852 | case PPC::STWEPX: |
| 5853 | case PPC::STWX: |
| 5854 | case PPC::STWX8: |
| 5855 | case PPC::TABORTDC: |
| 5856 | case PPC::TABORTDCI: |
| 5857 | case PPC::TABORTWC: |
| 5858 | case PPC::TABORTWCI: |
| 5859 | case PPC::TD: |
| 5860 | case PPC::TLBSX2: |
| 5861 | case PPC::TLBSX2D: |
| 5862 | case PPC::TW: |
| 5863 | case PPC::XSADDQP: |
| 5864 | case PPC::XSADDQPO: |
| 5865 | case PPC::XSCMPEQQP: |
| 5866 | case PPC::XSCMPGEQP: |
| 5867 | case PPC::XSCMPGTQP: |
| 5868 | case PPC::XSCPSGNQP: |
| 5869 | case PPC::XSDIVQP: |
| 5870 | case PPC::XSDIVQPO: |
| 5871 | case PPC::XSMAXCQP: |
| 5872 | case PPC::XSMINCQP: |
| 5873 | case PPC::XSMULQP: |
| 5874 | case PPC::XSMULQPO: |
| 5875 | case PPC::XSSUBQP: |
| 5876 | case PPC::XSSUBQPO: { |
| 5877 | // op: RST |
| 5878 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5879 | op &= UINT64_C(31); |
| 5880 | op <<= 21; |
| 5881 | Value |= op; |
| 5882 | // op: RA |
| 5883 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5884 | op &= UINT64_C(31); |
| 5885 | op <<= 16; |
| 5886 | Value |= op; |
| 5887 | // op: RB |
| 5888 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5889 | op &= UINT64_C(31); |
| 5890 | op <<= 11; |
| 5891 | Value |= op; |
| 5892 | break; |
| 5893 | } |
| 5894 | case PPC::LBZXTLS: |
| 5895 | case PPC::LBZXTLS_: |
| 5896 | case PPC::LBZXTLS_32: |
| 5897 | case PPC::LDXTLS: |
| 5898 | case PPC::LDXTLS_: |
| 5899 | case PPC::LFDXTLS: |
| 5900 | case PPC::LFDXTLS_: |
| 5901 | case PPC::LFSXTLS: |
| 5902 | case PPC::LFSXTLS_: |
| 5903 | case PPC::LHAXTLS: |
| 5904 | case PPC::LHAXTLS_: |
| 5905 | case PPC::LHAXTLS_32: |
| 5906 | case PPC::LHZXTLS: |
| 5907 | case PPC::LHZXTLS_: |
| 5908 | case PPC::LHZXTLS_32: |
| 5909 | case PPC::LWAXTLS: |
| 5910 | case PPC::LWAXTLS_: |
| 5911 | case PPC::LWAXTLS_32: |
| 5912 | case PPC::LWZXTLS: |
| 5913 | case PPC::LWZXTLS_: |
| 5914 | case PPC::LWZXTLS_32: |
| 5915 | case PPC::STBXTLS: |
| 5916 | case PPC::STBXTLS_: |
| 5917 | case PPC::STBXTLS_32: |
| 5918 | case PPC::STDXTLS: |
| 5919 | case PPC::STDXTLS_: |
| 5920 | case PPC::STFDXTLS: |
| 5921 | case PPC::STFDXTLS_: |
| 5922 | case PPC::STFSXTLS: |
| 5923 | case PPC::STFSXTLS_: |
| 5924 | case PPC::STHXTLS: |
| 5925 | case PPC::STHXTLS_: |
| 5926 | case PPC::STHXTLS_32: |
| 5927 | case PPC::STWXTLS: |
| 5928 | case PPC::STWXTLS_: |
| 5929 | case PPC::STWXTLS_32: { |
| 5930 | // op: RST |
| 5931 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5932 | op &= UINT64_C(31); |
| 5933 | op <<= 21; |
| 5934 | Value |= op; |
| 5935 | // op: RA |
| 5936 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5937 | op &= UINT64_C(31); |
| 5938 | op <<= 16; |
| 5939 | Value |= op; |
| 5940 | // op: RB |
| 5941 | op = getTLSRegEncoding(MI, OpNo: 2, Fixups, STI); |
| 5942 | op &= UINT64_C(31); |
| 5943 | op <<= 11; |
| 5944 | Value |= op; |
| 5945 | break; |
| 5946 | } |
| 5947 | case PPC::TLBRE2: |
| 5948 | case PPC::TLBWE2: { |
| 5949 | // op: RST |
| 5950 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5951 | op &= UINT64_C(31); |
| 5952 | op <<= 21; |
| 5953 | Value |= op; |
| 5954 | // op: RA |
| 5955 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5956 | op &= UINT64_C(31); |
| 5957 | op <<= 16; |
| 5958 | Value |= op; |
| 5959 | // op: WS |
| 5960 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5961 | op &= UINT64_C(1); |
| 5962 | op <<= 11; |
| 5963 | Value |= op; |
| 5964 | break; |
| 5965 | } |
| 5966 | case PPC::PLBZ: |
| 5967 | case PPC::PLBZ8: |
| 5968 | case PPC::PLBZ8nopc: |
| 5969 | case PPC::PLBZnopc: |
| 5970 | case PPC::PLD: |
| 5971 | case PPC::PLDnopc: |
| 5972 | case PPC::PLFD: |
| 5973 | case PPC::PLFDnopc: |
| 5974 | case PPC::PLFS: |
| 5975 | case PPC::PLFSnopc: |
| 5976 | case PPC::PLHA: |
| 5977 | case PPC::PLHA8: |
| 5978 | case PPC::PLHA8nopc: |
| 5979 | case PPC::PLHAnopc: |
| 5980 | case PPC::PLHZ: |
| 5981 | case PPC::PLHZ8: |
| 5982 | case PPC::PLHZ8nopc: |
| 5983 | case PPC::PLHZnopc: |
| 5984 | case PPC::PLWA: |
| 5985 | case PPC::PLWA8: |
| 5986 | case PPC::PLWA8nopc: |
| 5987 | case PPC::PLWAnopc: |
| 5988 | case PPC::PLWZ: |
| 5989 | case PPC::PLWZ8: |
| 5990 | case PPC::PLWZ8nopc: |
| 5991 | case PPC::PLWZnopc: |
| 5992 | case PPC::PLXSD: |
| 5993 | case PPC::PLXSDnopc: |
| 5994 | case PPC::PLXSSP: |
| 5995 | case PPC::PLXSSPnopc: |
| 5996 | case PPC::PSTB: |
| 5997 | case PPC::PSTB8: |
| 5998 | case PPC::PSTB8nopc: |
| 5999 | case PPC::PSTBnopc: |
| 6000 | case PPC::PSTD: |
| 6001 | case PPC::PSTDnopc: |
| 6002 | case PPC::PSTFD: |
| 6003 | case PPC::PSTFDnopc: |
| 6004 | case PPC::PSTFS: |
| 6005 | case PPC::PSTFSnopc: |
| 6006 | case PPC::PSTH: |
| 6007 | case PPC::PSTH8: |
| 6008 | case PPC::PSTH8nopc: |
| 6009 | case PPC::PSTHnopc: |
| 6010 | case PPC::PSTW: |
| 6011 | case PPC::PSTW8: |
| 6012 | case PPC::PSTW8nopc: |
| 6013 | case PPC::PSTWnopc: |
| 6014 | case PPC::PSTXSD: |
| 6015 | case PPC::PSTXSDnopc: |
| 6016 | case PPC::PSTXSSP: |
| 6017 | case PPC::PSTXSSPnopc: { |
| 6018 | // op: RST |
| 6019 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6020 | op &= UINT64_C(31); |
| 6021 | op <<= 21; |
| 6022 | Value |= op; |
| 6023 | // op: RA |
| 6024 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6025 | op &= UINT64_C(31); |
| 6026 | op <<= 16; |
| 6027 | Value |= op; |
| 6028 | // op: D |
| 6029 | op = getDispRI34Encoding(MI, OpNo: 1, Fixups, STI); |
| 6030 | Value |= (op & UINT64_C(17179803648)) << 16; |
| 6031 | Value |= (op & UINT64_C(65535)); |
| 6032 | break; |
| 6033 | } |
| 6034 | case PPC::PLBZ8pc: |
| 6035 | case PPC::PLBZpc: |
| 6036 | case PPC::PLDpc: |
| 6037 | case PPC::PLFDpc: |
| 6038 | case PPC::PLFSpc: |
| 6039 | case PPC::PLHA8pc: |
| 6040 | case PPC::PLHApc: |
| 6041 | case PPC::PLHZ8pc: |
| 6042 | case PPC::PLHZpc: |
| 6043 | case PPC::PLWA8pc: |
| 6044 | case PPC::PLWApc: |
| 6045 | case PPC::PLWZ8pc: |
| 6046 | case PPC::PLWZpc: |
| 6047 | case PPC::PLXSDpc: |
| 6048 | case PPC::PLXSSPpc: |
| 6049 | case PPC::PSTB8pc: |
| 6050 | case PPC::PSTBpc: |
| 6051 | case PPC::PSTDpc: |
| 6052 | case PPC::PSTFDpc: |
| 6053 | case PPC::PSTFSpc: |
| 6054 | case PPC::PSTH8pc: |
| 6055 | case PPC::PSTHpc: |
| 6056 | case PPC::PSTW8pc: |
| 6057 | case PPC::PSTWpc: |
| 6058 | case PPC::PSTXSDpc: |
| 6059 | case PPC::PSTXSSPpc: { |
| 6060 | // op: RST |
| 6061 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6062 | op &= UINT64_C(31); |
| 6063 | op <<= 21; |
| 6064 | Value |= op; |
| 6065 | // op: RA |
| 6066 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6067 | op &= UINT64_C(31); |
| 6068 | op <<= 16; |
| 6069 | Value |= op; |
| 6070 | // op: D |
| 6071 | op = getDispRI34PCRelEncoding(MI, OpNo: 1, Fixups, STI); |
| 6072 | Value |= (op & UINT64_C(17179803648)) << 16; |
| 6073 | Value |= (op & UINT64_C(65535)); |
| 6074 | break; |
| 6075 | } |
| 6076 | case PPC::LBZ: |
| 6077 | case PPC::LBZ8: |
| 6078 | case PPC::LFD: |
| 6079 | case PPC::LFS: |
| 6080 | case PPC::LHA: |
| 6081 | case PPC::LHA8: |
| 6082 | case PPC::LHZ: |
| 6083 | case PPC::LHZ8: |
| 6084 | case PPC::LMW: |
| 6085 | case PPC::LWZ: |
| 6086 | case PPC::LWZ8: |
| 6087 | case PPC::SPELWZ: |
| 6088 | case PPC::SPESTW: |
| 6089 | case PPC::STB: |
| 6090 | case PPC::STB8: |
| 6091 | case PPC::STFD: |
| 6092 | case PPC::STFS: |
| 6093 | case PPC::STH: |
| 6094 | case PPC::STH8: |
| 6095 | case PPC::STMW: |
| 6096 | case PPC::STW: |
| 6097 | case PPC::STW8: { |
| 6098 | // op: RST |
| 6099 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6100 | op &= UINT64_C(31); |
| 6101 | op <<= 21; |
| 6102 | Value |= op; |
| 6103 | // op: RA |
| 6104 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6105 | op &= UINT64_C(31); |
| 6106 | op <<= 16; |
| 6107 | Value |= op; |
| 6108 | // op: D |
| 6109 | op = getDispRIEncoding(MI, OpNo: 1, Fixups, STI); |
| 6110 | op &= UINT64_C(65535); |
| 6111 | Value |= op; |
| 6112 | break; |
| 6113 | } |
| 6114 | case PPC::LD: |
| 6115 | case PPC::LWA: |
| 6116 | case PPC::LWA_32: |
| 6117 | case PPC::LXSD: |
| 6118 | case PPC::LXSSP: |
| 6119 | case PPC::STD: |
| 6120 | case PPC::STQ: |
| 6121 | case PPC::STXSD: |
| 6122 | case PPC::STXSSP: { |
| 6123 | // op: RST |
| 6124 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6125 | op &= UINT64_C(31); |
| 6126 | op <<= 21; |
| 6127 | Value |= op; |
| 6128 | // op: RA |
| 6129 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6130 | op &= UINT64_C(31); |
| 6131 | op <<= 16; |
| 6132 | Value |= op; |
| 6133 | // op: D |
| 6134 | op = getDispRIXEncoding(MI, OpNo: 1, Fixups, STI); |
| 6135 | op &= UINT64_C(16383); |
| 6136 | op <<= 2; |
| 6137 | Value |= op; |
| 6138 | break; |
| 6139 | } |
| 6140 | case PPC::LBZUX: |
| 6141 | case PPC::LBZUX8: |
| 6142 | case PPC::LDUX: |
| 6143 | case PPC::LFDUX: |
| 6144 | case PPC::LFSUX: |
| 6145 | case PPC::LHAUX: |
| 6146 | case PPC::LHAUX8: |
| 6147 | case PPC::LHZUX: |
| 6148 | case PPC::LHZUX8: |
| 6149 | case PPC::LWAUX: |
| 6150 | case PPC::LWZUX: |
| 6151 | case PPC::LWZUX8: |
| 6152 | case PPC::XSMADDQP: |
| 6153 | case PPC::XSMADDQPO: |
| 6154 | case PPC::XSMSUBQP: |
| 6155 | case PPC::XSMSUBQPO: |
| 6156 | case PPC::XSNMADDQP: |
| 6157 | case PPC::XSNMADDQPO: |
| 6158 | case PPC::XSNMSUBQP: |
| 6159 | case PPC::XSNMSUBQPO: { |
| 6160 | // op: RST |
| 6161 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6162 | op &= UINT64_C(31); |
| 6163 | op <<= 21; |
| 6164 | Value |= op; |
| 6165 | // op: RA |
| 6166 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6167 | op &= UINT64_C(31); |
| 6168 | op <<= 16; |
| 6169 | Value |= op; |
| 6170 | // op: RB |
| 6171 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6172 | op &= UINT64_C(31); |
| 6173 | op <<= 11; |
| 6174 | Value |= op; |
| 6175 | break; |
| 6176 | } |
| 6177 | case PPC::LBZU: |
| 6178 | case PPC::LBZU8: |
| 6179 | case PPC::LFDU: |
| 6180 | case PPC::LFSU: |
| 6181 | case PPC::LHAU: |
| 6182 | case PPC::LHAU8: |
| 6183 | case PPC::LHZU: |
| 6184 | case PPC::LHZU8: |
| 6185 | case PPC::LWZU: |
| 6186 | case PPC::LWZU8: { |
| 6187 | // op: RST |
| 6188 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6189 | op &= UINT64_C(31); |
| 6190 | op <<= 21; |
| 6191 | Value |= op; |
| 6192 | // op: RA |
| 6193 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6194 | op &= UINT64_C(31); |
| 6195 | op <<= 16; |
| 6196 | Value |= op; |
| 6197 | // op: D |
| 6198 | op = getDispRIEncoding(MI, OpNo: 2, Fixups, STI); |
| 6199 | op &= UINT64_C(65535); |
| 6200 | Value |= op; |
| 6201 | break; |
| 6202 | } |
| 6203 | case PPC::LDU: { |
| 6204 | // op: RST |
| 6205 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6206 | op &= UINT64_C(31); |
| 6207 | op <<= 21; |
| 6208 | Value |= op; |
| 6209 | // op: RA |
| 6210 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6211 | op &= UINT64_C(31); |
| 6212 | op <<= 16; |
| 6213 | Value |= op; |
| 6214 | // op: D |
| 6215 | op = getDispRIXEncoding(MI, OpNo: 2, Fixups, STI); |
| 6216 | op &= UINT64_C(16383); |
| 6217 | op <<= 2; |
| 6218 | Value |= op; |
| 6219 | break; |
| 6220 | } |
| 6221 | case PPC::DCFFIX: |
| 6222 | case PPC::DCFFIXQ: |
| 6223 | case PPC::DCFFIXQQ: |
| 6224 | case PPC::DCFFIXQ_rec: |
| 6225 | case PPC::DCFFIX_rec: |
| 6226 | case PPC::DCTDP: |
| 6227 | case PPC::DCTDP_rec: |
| 6228 | case PPC::DCTFIX: |
| 6229 | case PPC::DCTFIXQ: |
| 6230 | case PPC::DCTFIXQQ: |
| 6231 | case PPC::DCTFIXQ_rec: |
| 6232 | case PPC::DCTFIX_rec: |
| 6233 | case PPC::DCTQPQ: |
| 6234 | case PPC::DCTQPQ_rec: |
| 6235 | case PPC::DRDPQ: |
| 6236 | case PPC::DRDPQ_rec: |
| 6237 | case PPC::DRSP: |
| 6238 | case PPC::DRSP_rec: |
| 6239 | case PPC::DXEX: |
| 6240 | case PPC::DXEXQ: |
| 6241 | case PPC::DXEXQ_rec: |
| 6242 | case PPC::DXEX_rec: |
| 6243 | case PPC::FABSD: |
| 6244 | case PPC::FABSD_rec: |
| 6245 | case PPC::FABSS: |
| 6246 | case PPC::FABSS_rec: |
| 6247 | case PPC::FCFID: |
| 6248 | case PPC::FCFIDS: |
| 6249 | case PPC::FCFIDS_rec: |
| 6250 | case PPC::FCFIDU: |
| 6251 | case PPC::FCFIDUS: |
| 6252 | case PPC::FCFIDUS_rec: |
| 6253 | case PPC::FCFIDU_rec: |
| 6254 | case PPC::FCFID_rec: |
| 6255 | case PPC::FCTID: |
| 6256 | case PPC::FCTIDU: |
| 6257 | case PPC::FCTIDUZ: |
| 6258 | case PPC::FCTIDUZ_rec: |
| 6259 | case PPC::FCTIDU_rec: |
| 6260 | case PPC::FCTIDZ: |
| 6261 | case PPC::FCTIDZ_rec: |
| 6262 | case PPC::FCTID_rec: |
| 6263 | case PPC::FCTIW: |
| 6264 | case PPC::FCTIWU: |
| 6265 | case PPC::FCTIWUZ: |
| 6266 | case PPC::FCTIWUZ_rec: |
| 6267 | case PPC::FCTIWU_rec: |
| 6268 | case PPC::FCTIWZ: |
| 6269 | case PPC::FCTIWZ_rec: |
| 6270 | case PPC::FCTIW_rec: |
| 6271 | case PPC::FMR: |
| 6272 | case PPC::FMR_rec: |
| 6273 | case PPC::FNABSD: |
| 6274 | case PPC::FNABSD_rec: |
| 6275 | case PPC::FNABSS: |
| 6276 | case PPC::FNABSS_rec: |
| 6277 | case PPC::FNEGD: |
| 6278 | case PPC::FNEGD_rec: |
| 6279 | case PPC::FNEGS: |
| 6280 | case PPC::FNEGS_rec: |
| 6281 | case PPC::FRE: |
| 6282 | case PPC::FRES: |
| 6283 | case PPC::FRES_rec: |
| 6284 | case PPC::FRE_rec: |
| 6285 | case PPC::FRIMD: |
| 6286 | case PPC::FRIMD_rec: |
| 6287 | case PPC::FRIMS: |
| 6288 | case PPC::FRIMS_rec: |
| 6289 | case PPC::FRIND: |
| 6290 | case PPC::FRIND_rec: |
| 6291 | case PPC::FRINS: |
| 6292 | case PPC::FRINS_rec: |
| 6293 | case PPC::FRIPD: |
| 6294 | case PPC::FRIPD_rec: |
| 6295 | case PPC::FRIPS: |
| 6296 | case PPC::FRIPS_rec: |
| 6297 | case PPC::FRIZD: |
| 6298 | case PPC::FRIZD_rec: |
| 6299 | case PPC::FRIZS: |
| 6300 | case PPC::FRIZS_rec: |
| 6301 | case PPC::FRSP: |
| 6302 | case PPC::FRSP_rec: |
| 6303 | case PPC::FRSQRTE: |
| 6304 | case PPC::FRSQRTES: |
| 6305 | case PPC::FRSQRTES_rec: |
| 6306 | case PPC::FRSQRTE_rec: |
| 6307 | case PPC::FSQRT: |
| 6308 | case PPC::FSQRTS: |
| 6309 | case PPC::FSQRTS_rec: |
| 6310 | case PPC::FSQRT_rec: |
| 6311 | case PPC::SLBFEE_rec: |
| 6312 | case PPC::SLBIEG: |
| 6313 | case PPC::SLBMFEE: |
| 6314 | case PPC::SLBMTE: |
| 6315 | case PPC::TLBIE: |
| 6316 | case PPC::XSABSQP: |
| 6317 | case PPC::XSCVDPQP: |
| 6318 | case PPC::XSCVQPDP: |
| 6319 | case PPC::XSCVQPDPO: |
| 6320 | case PPC::XSCVQPSDZ: |
| 6321 | case PPC::XSCVQPSQZ: |
| 6322 | case PPC::XSCVQPSWZ: |
| 6323 | case PPC::XSCVQPUDZ: |
| 6324 | case PPC::XSCVQPUQZ: |
| 6325 | case PPC::XSCVQPUWZ: |
| 6326 | case PPC::XSCVSDQP: |
| 6327 | case PPC::XSCVSQQP: |
| 6328 | case PPC::XSCVUDQP: |
| 6329 | case PPC::XSCVUQQP: |
| 6330 | case PPC::XSNABSQP: |
| 6331 | case PPC::XSNEGQP: |
| 6332 | case PPC::XSSQRTQP: |
| 6333 | case PPC::XSSQRTQPO: |
| 6334 | case PPC::XSXEXPQP: |
| 6335 | case PPC::XSXSIGQP: { |
| 6336 | // op: RST |
| 6337 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6338 | op &= UINT64_C(31); |
| 6339 | op <<= 21; |
| 6340 | Value |= op; |
| 6341 | // op: RB |
| 6342 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6343 | op &= UINT64_C(31); |
| 6344 | op <<= 11; |
| 6345 | Value |= op; |
| 6346 | break; |
| 6347 | } |
| 6348 | case PPC::MFFSCRNI: { |
| 6349 | // op: RST |
| 6350 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6351 | op &= UINT64_C(31); |
| 6352 | op <<= 21; |
| 6353 | Value |= op; |
| 6354 | // op: RM |
| 6355 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6356 | op &= UINT64_C(3); |
| 6357 | op <<= 11; |
| 6358 | Value |= op; |
| 6359 | break; |
| 6360 | } |
| 6361 | case PPC::MFDCR: |
| 6362 | case PPC::MFPMR: |
| 6363 | case PPC::MFSPR: |
| 6364 | case PPC::MFSPR8: |
| 6365 | case PPC::MFTB: |
| 6366 | case PPC::MTDCR: { |
| 6367 | // op: RST |
| 6368 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6369 | op &= UINT64_C(31); |
| 6370 | op <<= 21; |
| 6371 | Value |= op; |
| 6372 | // op: SPR |
| 6373 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6374 | Value |= (op & UINT64_C(31)) << 16; |
| 6375 | Value |= (op & UINT64_C(992)) << 6; |
| 6376 | break; |
| 6377 | } |
| 6378 | case PPC::MTVRSAVEv: { |
| 6379 | // op: RST |
| 6380 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6381 | op &= UINT64_C(31); |
| 6382 | op <<= 21; |
| 6383 | Value |= op; |
| 6384 | break; |
| 6385 | } |
| 6386 | case PPC::MTOCRF: |
| 6387 | case PPC::MTOCRF8: { |
| 6388 | // op: RST |
| 6389 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6390 | op &= UINT64_C(31); |
| 6391 | op <<= 21; |
| 6392 | Value |= op; |
| 6393 | // op: FXM |
| 6394 | op = get_crbitm_encoding(MI, OpNo: 0, Fixups, STI); |
| 6395 | op &= UINT64_C(255); |
| 6396 | op <<= 12; |
| 6397 | Value |= op; |
| 6398 | break; |
| 6399 | } |
| 6400 | case PPC::STBUX: |
| 6401 | case PPC::STBUX8: |
| 6402 | case PPC::STDUX: |
| 6403 | case PPC::STFDUX: |
| 6404 | case PPC::STFSUX: |
| 6405 | case PPC::STHUX: |
| 6406 | case PPC::STHUX8: |
| 6407 | case PPC::STWUX: |
| 6408 | case PPC::STWUX8: { |
| 6409 | // op: RST |
| 6410 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6411 | op &= UINT64_C(31); |
| 6412 | op <<= 21; |
| 6413 | Value |= op; |
| 6414 | // op: RA |
| 6415 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6416 | op &= UINT64_C(31); |
| 6417 | op <<= 16; |
| 6418 | Value |= op; |
| 6419 | // op: RB |
| 6420 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6421 | op &= UINT64_C(31); |
| 6422 | op <<= 11; |
| 6423 | Value |= op; |
| 6424 | break; |
| 6425 | } |
| 6426 | case PPC::STBU: |
| 6427 | case PPC::STBU8: |
| 6428 | case PPC::STFDU: |
| 6429 | case PPC::STFSU: |
| 6430 | case PPC::STHU: |
| 6431 | case PPC::STHU8: |
| 6432 | case PPC::STWU: |
| 6433 | case PPC::STWU8: { |
| 6434 | // op: RST |
| 6435 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6436 | op &= UINT64_C(31); |
| 6437 | op <<= 21; |
| 6438 | Value |= op; |
| 6439 | // op: RA |
| 6440 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6441 | op &= UINT64_C(31); |
| 6442 | op <<= 16; |
| 6443 | Value |= op; |
| 6444 | // op: D |
| 6445 | op = getDispRIEncoding(MI, OpNo: 2, Fixups, STI); |
| 6446 | op &= UINT64_C(65535); |
| 6447 | Value |= op; |
| 6448 | break; |
| 6449 | } |
| 6450 | case PPC::STDU: { |
| 6451 | // op: RST |
| 6452 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6453 | op &= UINT64_C(31); |
| 6454 | op <<= 21; |
| 6455 | Value |= op; |
| 6456 | // op: RA |
| 6457 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6458 | op &= UINT64_C(31); |
| 6459 | op <<= 16; |
| 6460 | Value |= op; |
| 6461 | // op: D |
| 6462 | op = getDispRIXEncoding(MI, OpNo: 2, Fixups, STI); |
| 6463 | op &= UINT64_C(16383); |
| 6464 | op <<= 2; |
| 6465 | Value |= op; |
| 6466 | break; |
| 6467 | } |
| 6468 | case PPC::MTPMR: |
| 6469 | case PPC::MTSPR: |
| 6470 | case PPC::MTSPR8: { |
| 6471 | // op: RST |
| 6472 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6473 | op &= UINT64_C(31); |
| 6474 | op <<= 21; |
| 6475 | Value |= op; |
| 6476 | // op: SPR |
| 6477 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6478 | Value |= (op & UINT64_C(31)) << 16; |
| 6479 | Value |= (op & UINT64_C(992)) << 6; |
| 6480 | break; |
| 6481 | } |
| 6482 | case PPC::MFCR: |
| 6483 | case PPC::MFCR8: { |
| 6484 | // op: RT |
| 6485 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6486 | op &= UINT64_C(31); |
| 6487 | op <<= 21; |
| 6488 | Value |= op; |
| 6489 | break; |
| 6490 | } |
| 6491 | case PPC::SETB: |
| 6492 | case PPC::SETB8: { |
| 6493 | // op: RT |
| 6494 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6495 | op &= UINT64_C(31); |
| 6496 | op <<= 21; |
| 6497 | Value |= op; |
| 6498 | // op: BFA |
| 6499 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6500 | op &= UINT64_C(7); |
| 6501 | op <<= 18; |
| 6502 | Value |= op; |
| 6503 | break; |
| 6504 | } |
| 6505 | case PPC::MTVSRBMI: { |
| 6506 | // op: RT |
| 6507 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6508 | op &= UINT64_C(31); |
| 6509 | op <<= 21; |
| 6510 | Value |= op; |
| 6511 | // op: D |
| 6512 | op = getImm16Encoding(MI, OpNo: 1, Fixups, STI); |
| 6513 | Value |= (op & UINT64_C(62)) << 15; |
| 6514 | Value |= (op & UINT64_C(65472)); |
| 6515 | Value |= (op & UINT64_C(1)); |
| 6516 | break; |
| 6517 | } |
| 6518 | case PPC::ADDPCIS: { |
| 6519 | // op: RT |
| 6520 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6521 | op &= UINT64_C(31); |
| 6522 | op <<= 21; |
| 6523 | Value |= op; |
| 6524 | // op: D |
| 6525 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6526 | Value |= (op & UINT64_C(62)) << 15; |
| 6527 | Value |= (op & UINT64_C(65472)); |
| 6528 | Value |= (op & UINT64_C(1)); |
| 6529 | break; |
| 6530 | } |
| 6531 | case PPC::DARN: { |
| 6532 | // op: RT |
| 6533 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6534 | op &= UINT64_C(31); |
| 6535 | op <<= 21; |
| 6536 | Value |= op; |
| 6537 | // op: L |
| 6538 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6539 | op &= UINT64_C(3); |
| 6540 | op <<= 16; |
| 6541 | Value |= op; |
| 6542 | break; |
| 6543 | } |
| 6544 | case PPC::ADDME: |
| 6545 | case PPC::ADDME8: |
| 6546 | case PPC::ADDME8O: |
| 6547 | case PPC::ADDME8O_rec: |
| 6548 | case PPC::ADDME8_rec: |
| 6549 | case PPC::ADDMEO: |
| 6550 | case PPC::ADDMEO_rec: |
| 6551 | case PPC::ADDME_rec: |
| 6552 | case PPC::ADDZE: |
| 6553 | case PPC::ADDZE8: |
| 6554 | case PPC::ADDZE8O: |
| 6555 | case PPC::ADDZE8O_rec: |
| 6556 | case PPC::ADDZE8_rec: |
| 6557 | case PPC::ADDZEO: |
| 6558 | case PPC::ADDZEO_rec: |
| 6559 | case PPC::ADDZE_rec: |
| 6560 | case PPC::EFDABS: |
| 6561 | case PPC::EFDNABS: |
| 6562 | case PPC::EFDNEG: |
| 6563 | case PPC::EFSABS: |
| 6564 | case PPC::EFSNABS: |
| 6565 | case PPC::EFSNEG: |
| 6566 | case PPC::EVABS: |
| 6567 | case PPC::EVADDSMIAAW: |
| 6568 | case PPC::EVADDSSIAAW: |
| 6569 | case PPC::EVADDUMIAAW: |
| 6570 | case PPC::EVADDUSIAAW: |
| 6571 | case PPC::EVCNTLSW: |
| 6572 | case PPC::EVCNTLZW: |
| 6573 | case PPC::EVEXTSB: |
| 6574 | case PPC::EVEXTSH: |
| 6575 | case PPC::EVFSABS: |
| 6576 | case PPC::EVFSNABS: |
| 6577 | case PPC::EVFSNEG: |
| 6578 | case PPC::EVMRA: |
| 6579 | case PPC::EVNEG: |
| 6580 | case PPC::EVRNDW: |
| 6581 | case PPC::EVSPLATFI: |
| 6582 | case PPC::EVSPLATI: |
| 6583 | case PPC::EVSUBFSMIAAW: |
| 6584 | case PPC::EVSUBFSSIAAW: |
| 6585 | case PPC::EVSUBFUMIAAW: |
| 6586 | case PPC::EVSUBFUSIAAW: |
| 6587 | case PPC::NEG: |
| 6588 | case PPC::NEG8: |
| 6589 | case PPC::NEG8O: |
| 6590 | case PPC::NEG8O_rec: |
| 6591 | case PPC::NEG8_rec: |
| 6592 | case PPC::NEGO: |
| 6593 | case PPC::NEGO_rec: |
| 6594 | case PPC::NEG_rec: |
| 6595 | case PPC::SUBFME: |
| 6596 | case PPC::SUBFME8: |
| 6597 | case PPC::SUBFME8O: |
| 6598 | case PPC::SUBFME8O_rec: |
| 6599 | case PPC::SUBFME8_rec: |
| 6600 | case PPC::SUBFMEO: |
| 6601 | case PPC::SUBFMEO_rec: |
| 6602 | case PPC::SUBFME_rec: |
| 6603 | case PPC::SUBFZE: |
| 6604 | case PPC::SUBFZE8: |
| 6605 | case PPC::SUBFZE8O: |
| 6606 | case PPC::SUBFZE8O_rec: |
| 6607 | case PPC::SUBFZE8_rec: |
| 6608 | case PPC::SUBFZEO: |
| 6609 | case PPC::SUBFZEO_rec: |
| 6610 | case PPC::SUBFZE_rec: { |
| 6611 | // op: RT |
| 6612 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6613 | op &= UINT64_C(31); |
| 6614 | op <<= 21; |
| 6615 | Value |= op; |
| 6616 | // op: RA |
| 6617 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6618 | op &= UINT64_C(31); |
| 6619 | op <<= 16; |
| 6620 | Value |= op; |
| 6621 | break; |
| 6622 | } |
| 6623 | case PPC::ADD4: |
| 6624 | case PPC::ADD4O: |
| 6625 | case PPC::ADD4O_rec: |
| 6626 | case PPC::ADD4_rec: |
| 6627 | case PPC::ADD8: |
| 6628 | case PPC::ADD8O: |
| 6629 | case PPC::ADD8O_rec: |
| 6630 | case PPC::ADD8_rec: |
| 6631 | case PPC::ADDC: |
| 6632 | case PPC::ADDC8: |
| 6633 | case PPC::ADDC8O: |
| 6634 | case PPC::ADDC8O_rec: |
| 6635 | case PPC::ADDC8_rec: |
| 6636 | case PPC::ADDCO: |
| 6637 | case PPC::ADDCO_rec: |
| 6638 | case PPC::ADDC_rec: |
| 6639 | case PPC::ADDE: |
| 6640 | case PPC::ADDE8: |
| 6641 | case PPC::ADDE8O: |
| 6642 | case PPC::ADDE8O_rec: |
| 6643 | case PPC::ADDE8_rec: |
| 6644 | case PPC::ADDEO: |
| 6645 | case PPC::ADDEO_rec: |
| 6646 | case PPC::ADDE_rec: |
| 6647 | case PPC::ADDG6S: |
| 6648 | case PPC::ADDG6S8: |
| 6649 | case PPC::BRINC: |
| 6650 | case PPC::DIVD: |
| 6651 | case PPC::DIVDE: |
| 6652 | case PPC::DIVDEO: |
| 6653 | case PPC::DIVDEO_rec: |
| 6654 | case PPC::DIVDEU: |
| 6655 | case PPC::DIVDEUO: |
| 6656 | case PPC::DIVDEUO_rec: |
| 6657 | case PPC::DIVDEU_rec: |
| 6658 | case PPC::DIVDE_rec: |
| 6659 | case PPC::DIVDO: |
| 6660 | case PPC::DIVDO_rec: |
| 6661 | case PPC::DIVDU: |
| 6662 | case PPC::DIVDUO: |
| 6663 | case PPC::DIVDUO_rec: |
| 6664 | case PPC::DIVDU_rec: |
| 6665 | case PPC::DIVD_rec: |
| 6666 | case PPC::DIVW: |
| 6667 | case PPC::DIVWE: |
| 6668 | case PPC::DIVWEO: |
| 6669 | case PPC::DIVWEO_rec: |
| 6670 | case PPC::DIVWEU: |
| 6671 | case PPC::DIVWEUO: |
| 6672 | case PPC::DIVWEUO_rec: |
| 6673 | case PPC::DIVWEU_rec: |
| 6674 | case PPC::DIVWE_rec: |
| 6675 | case PPC::DIVWO: |
| 6676 | case PPC::DIVWO_rec: |
| 6677 | case PPC::DIVWU: |
| 6678 | case PPC::DIVWUO: |
| 6679 | case PPC::DIVWUO_rec: |
| 6680 | case PPC::DIVWU_rec: |
| 6681 | case PPC::DIVW_rec: |
| 6682 | case PPC::EFDADD: |
| 6683 | case PPC::EFDDIV: |
| 6684 | case PPC::EFDMUL: |
| 6685 | case PPC::EFDSUB: |
| 6686 | case PPC::EFSADD: |
| 6687 | case PPC::EFSDIV: |
| 6688 | case PPC::EFSMUL: |
| 6689 | case PPC::EFSSUB: |
| 6690 | case PPC::EVADDIW: |
| 6691 | case PPC::EVADDW: |
| 6692 | case PPC::EVAND: |
| 6693 | case PPC::EVANDC: |
| 6694 | case PPC::EVDIVWS: |
| 6695 | case PPC::EVDIVWU: |
| 6696 | case PPC::EVEQV: |
| 6697 | case PPC::EVFSADD: |
| 6698 | case PPC::EVFSDIV: |
| 6699 | case PPC::EVFSMUL: |
| 6700 | case PPC::EVFSSUB: |
| 6701 | case PPC::EVLDDX: |
| 6702 | case PPC::EVLDHX: |
| 6703 | case PPC::EVLDWX: |
| 6704 | case PPC::EVLHHESPLATX: |
| 6705 | case PPC::EVLHHOSSPLATX: |
| 6706 | case PPC::EVLHHOUSPLATX: |
| 6707 | case PPC::EVLWHEX: |
| 6708 | case PPC::EVLWHOSX: |
| 6709 | case PPC::EVLWHOUX: |
| 6710 | case PPC::EVLWHSPLATX: |
| 6711 | case PPC::EVLWWSPLATX: |
| 6712 | case PPC::EVMERGEHI: |
| 6713 | case PPC::EVMERGEHILO: |
| 6714 | case PPC::EVMERGELO: |
| 6715 | case PPC::EVMERGELOHI: |
| 6716 | case PPC::EVMHEGSMFAA: |
| 6717 | case PPC::EVMHEGSMFAN: |
| 6718 | case PPC::EVMHEGSMIAA: |
| 6719 | case PPC::EVMHEGSMIAN: |
| 6720 | case PPC::EVMHEGUMIAA: |
| 6721 | case PPC::EVMHEGUMIAN: |
| 6722 | case PPC::EVMHESMF: |
| 6723 | case PPC::EVMHESMFA: |
| 6724 | case PPC::EVMHESMFAAW: |
| 6725 | case PPC::EVMHESMFANW: |
| 6726 | case PPC::EVMHESMI: |
| 6727 | case PPC::EVMHESMIA: |
| 6728 | case PPC::EVMHESMIAAW: |
| 6729 | case PPC::EVMHESMIANW: |
| 6730 | case PPC::EVMHESSF: |
| 6731 | case PPC::EVMHESSFA: |
| 6732 | case PPC::EVMHESSFAAW: |
| 6733 | case PPC::EVMHESSFANW: |
| 6734 | case PPC::EVMHESSIAAW: |
| 6735 | case PPC::EVMHESSIANW: |
| 6736 | case PPC::EVMHEUMI: |
| 6737 | case PPC::EVMHEUMIA: |
| 6738 | case PPC::EVMHEUMIAAW: |
| 6739 | case PPC::EVMHEUMIANW: |
| 6740 | case PPC::EVMHEUSIAAW: |
| 6741 | case PPC::EVMHEUSIANW: |
| 6742 | case PPC::EVMHOGSMFAA: |
| 6743 | case PPC::EVMHOGSMFAN: |
| 6744 | case PPC::EVMHOGSMIAA: |
| 6745 | case PPC::EVMHOGSMIAN: |
| 6746 | case PPC::EVMHOGUMIAA: |
| 6747 | case PPC::EVMHOGUMIAN: |
| 6748 | case PPC::EVMHOSMF: |
| 6749 | case PPC::EVMHOSMFA: |
| 6750 | case PPC::EVMHOSMFAAW: |
| 6751 | case PPC::EVMHOSMFANW: |
| 6752 | case PPC::EVMHOSMI: |
| 6753 | case PPC::EVMHOSMIA: |
| 6754 | case PPC::EVMHOSMIAAW: |
| 6755 | case PPC::EVMHOSMIANW: |
| 6756 | case PPC::EVMHOSSF: |
| 6757 | case PPC::EVMHOSSFA: |
| 6758 | case PPC::EVMHOSSFAAW: |
| 6759 | case PPC::EVMHOSSFANW: |
| 6760 | case PPC::EVMHOSSIAAW: |
| 6761 | case PPC::EVMHOSSIANW: |
| 6762 | case PPC::EVMHOUMI: |
| 6763 | case PPC::EVMHOUMIA: |
| 6764 | case PPC::EVMHOUMIAAW: |
| 6765 | case PPC::EVMHOUMIANW: |
| 6766 | case PPC::EVMHOUSIAAW: |
| 6767 | case PPC::EVMHOUSIANW: |
| 6768 | case PPC::EVMWHSMF: |
| 6769 | case PPC::EVMWHSMFA: |
| 6770 | case PPC::EVMWHSMI: |
| 6771 | case PPC::EVMWHSMIA: |
| 6772 | case PPC::EVMWHSSF: |
| 6773 | case PPC::EVMWHSSFA: |
| 6774 | case PPC::EVMWHUMI: |
| 6775 | case PPC::EVMWHUMIA: |
| 6776 | case PPC::EVMWLSMIAAW: |
| 6777 | case PPC::EVMWLSMIANW: |
| 6778 | case PPC::EVMWLSSIAAW: |
| 6779 | case PPC::EVMWLSSIANW: |
| 6780 | case PPC::EVMWLUMI: |
| 6781 | case PPC::EVMWLUMIA: |
| 6782 | case PPC::EVMWLUMIAAW: |
| 6783 | case PPC::EVMWLUMIANW: |
| 6784 | case PPC::EVMWLUSIAAW: |
| 6785 | case PPC::EVMWLUSIANW: |
| 6786 | case PPC::EVMWSMF: |
| 6787 | case PPC::EVMWSMFA: |
| 6788 | case PPC::EVMWSMFAA: |
| 6789 | case PPC::EVMWSMFAN: |
| 6790 | case PPC::EVMWSMI: |
| 6791 | case PPC::EVMWSMIA: |
| 6792 | case PPC::EVMWSMIAA: |
| 6793 | case PPC::EVMWSMIAN: |
| 6794 | case PPC::EVMWSSF: |
| 6795 | case PPC::EVMWSSFA: |
| 6796 | case PPC::EVMWSSFAA: |
| 6797 | case PPC::EVMWSSFAN: |
| 6798 | case PPC::EVMWUMI: |
| 6799 | case PPC::EVMWUMIA: |
| 6800 | case PPC::EVMWUMIAA: |
| 6801 | case PPC::EVMWUMIAN: |
| 6802 | case PPC::EVNAND: |
| 6803 | case PPC::EVNOR: |
| 6804 | case PPC::EVOR: |
| 6805 | case PPC::EVORC: |
| 6806 | case PPC::EVRLW: |
| 6807 | case PPC::EVRLWI: |
| 6808 | case PPC::EVSLW: |
| 6809 | case PPC::EVSLWI: |
| 6810 | case PPC::EVSRWIS: |
| 6811 | case PPC::EVSRWIU: |
| 6812 | case PPC::EVSRWS: |
| 6813 | case PPC::EVSRWU: |
| 6814 | case PPC::EVSTDDX: |
| 6815 | case PPC::EVSTDHX: |
| 6816 | case PPC::EVSTDWX: |
| 6817 | case PPC::EVSTWHEX: |
| 6818 | case PPC::EVSTWHOX: |
| 6819 | case PPC::EVSTWWEX: |
| 6820 | case PPC::EVSTWWOX: |
| 6821 | case PPC::EVSUBFW: |
| 6822 | case PPC::EVSUBIFW: |
| 6823 | case PPC::EVXOR: |
| 6824 | case PPC::MULHD: |
| 6825 | case PPC::MULHDU: |
| 6826 | case PPC::MULHDU_rec: |
| 6827 | case PPC::MULHD_rec: |
| 6828 | case PPC::MULHW: |
| 6829 | case PPC::MULHWU: |
| 6830 | case PPC::MULHWU_rec: |
| 6831 | case PPC::MULHW_rec: |
| 6832 | case PPC::MULLD: |
| 6833 | case PPC::MULLDO: |
| 6834 | case PPC::MULLDO_rec: |
| 6835 | case PPC::MULLD_rec: |
| 6836 | case PPC::MULLW: |
| 6837 | case PPC::MULLWO: |
| 6838 | case PPC::MULLWO_rec: |
| 6839 | case PPC::MULLW_rec: |
| 6840 | case PPC::SUBF: |
| 6841 | case PPC::SUBF8: |
| 6842 | case PPC::SUBF8O: |
| 6843 | case PPC::SUBF8O_rec: |
| 6844 | case PPC::SUBF8_rec: |
| 6845 | case PPC::SUBFC: |
| 6846 | case PPC::SUBFC8: |
| 6847 | case PPC::SUBFC8O: |
| 6848 | case PPC::SUBFC8O_rec: |
| 6849 | case PPC::SUBFC8_rec: |
| 6850 | case PPC::SUBFCO: |
| 6851 | case PPC::SUBFCO_rec: |
| 6852 | case PPC::SUBFC_rec: |
| 6853 | case PPC::SUBFE: |
| 6854 | case PPC::SUBFE8: |
| 6855 | case PPC::SUBFE8O: |
| 6856 | case PPC::SUBFE8O_rec: |
| 6857 | case PPC::SUBFE8_rec: |
| 6858 | case PPC::SUBFEO: |
| 6859 | case PPC::SUBFEO_rec: |
| 6860 | case PPC::SUBFE_rec: |
| 6861 | case PPC::SUBFO: |
| 6862 | case PPC::SUBFO_rec: |
| 6863 | case PPC::SUBF_rec: { |
| 6864 | // op: RT |
| 6865 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6866 | op &= UINT64_C(31); |
| 6867 | op <<= 21; |
| 6868 | Value |= op; |
| 6869 | // op: RA |
| 6870 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6871 | op &= UINT64_C(31); |
| 6872 | op <<= 16; |
| 6873 | Value |= op; |
| 6874 | // op: RB |
| 6875 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6876 | op &= UINT64_C(31); |
| 6877 | op <<= 11; |
| 6878 | Value |= op; |
| 6879 | break; |
| 6880 | } |
| 6881 | case PPC::ISEL: |
| 6882 | case PPC::ISEL8: { |
| 6883 | // op: RT |
| 6884 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6885 | op &= UINT64_C(31); |
| 6886 | op <<= 21; |
| 6887 | Value |= op; |
| 6888 | // op: RA |
| 6889 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6890 | op &= UINT64_C(31); |
| 6891 | op <<= 16; |
| 6892 | Value |= op; |
| 6893 | // op: RB |
| 6894 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6895 | op &= UINT64_C(31); |
| 6896 | op <<= 11; |
| 6897 | Value |= op; |
| 6898 | // op: COND |
| 6899 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6900 | op &= UINT64_C(31); |
| 6901 | op <<= 6; |
| 6902 | Value |= op; |
| 6903 | break; |
| 6904 | } |
| 6905 | case PPC::ADDEX: |
| 6906 | case PPC::ADDEX8: { |
| 6907 | // op: RT |
| 6908 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6909 | op &= UINT64_C(31); |
| 6910 | op <<= 21; |
| 6911 | Value |= op; |
| 6912 | // op: RA |
| 6913 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6914 | op &= UINT64_C(31); |
| 6915 | op <<= 16; |
| 6916 | Value |= op; |
| 6917 | // op: RB |
| 6918 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6919 | op &= UINT64_C(31); |
| 6920 | op <<= 11; |
| 6921 | Value |= op; |
| 6922 | // op: CY |
| 6923 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6924 | op &= UINT64_C(3); |
| 6925 | op <<= 9; |
| 6926 | Value |= op; |
| 6927 | break; |
| 6928 | } |
| 6929 | case PPC::SUBFUS: |
| 6930 | case PPC::SUBFUS_rec: { |
| 6931 | // op: RT |
| 6932 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6933 | op &= UINT64_C(31); |
| 6934 | op <<= 21; |
| 6935 | Value |= op; |
| 6936 | // op: RA |
| 6937 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6938 | op &= UINT64_C(31); |
| 6939 | op <<= 16; |
| 6940 | Value |= op; |
| 6941 | // op: RB |
| 6942 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6943 | op &= UINT64_C(31); |
| 6944 | op <<= 11; |
| 6945 | Value |= op; |
| 6946 | // op: L |
| 6947 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6948 | op &= UINT64_C(1); |
| 6949 | op <<= 10; |
| 6950 | Value |= op; |
| 6951 | break; |
| 6952 | } |
| 6953 | case PPC::MADDHD: |
| 6954 | case PPC::MADDHDU: |
| 6955 | case PPC::MADDLD: |
| 6956 | case PPC::MADDLD8: |
| 6957 | case PPC::VADDECUQ: |
| 6958 | case PPC::VADDEUQM: |
| 6959 | case PPC::VEXTDDVLX: |
| 6960 | case PPC::VEXTDDVRX: |
| 6961 | case PPC::VEXTDUBVLX: |
| 6962 | case PPC::VEXTDUBVRX: |
| 6963 | case PPC::VEXTDUHVLX: |
| 6964 | case PPC::VEXTDUHVRX: |
| 6965 | case PPC::VEXTDUWVLX: |
| 6966 | case PPC::VEXTDUWVRX: |
| 6967 | case PPC::VMHADDSHS: |
| 6968 | case PPC::VMHRADDSHS: |
| 6969 | case PPC::VMLADDUHM: |
| 6970 | case PPC::VMSUMCUD: |
| 6971 | case PPC::VMSUMMBM: |
| 6972 | case PPC::VMSUMSHM: |
| 6973 | case PPC::VMSUMSHS: |
| 6974 | case PPC::VMSUMUBM: |
| 6975 | case PPC::VMSUMUDM: |
| 6976 | case PPC::VMSUMUHM: |
| 6977 | case PPC::VMSUMUHS: |
| 6978 | case PPC::VPERM: |
| 6979 | case PPC::VPERMR: |
| 6980 | case PPC::VSEL: |
| 6981 | case PPC::VSUBECUQ: |
| 6982 | case PPC::VSUBEUQM: { |
| 6983 | // op: RT |
| 6984 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6985 | op &= UINT64_C(31); |
| 6986 | op <<= 21; |
| 6987 | Value |= op; |
| 6988 | // op: RA |
| 6989 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6990 | op &= UINT64_C(31); |
| 6991 | op <<= 16; |
| 6992 | Value |= op; |
| 6993 | // op: RB |
| 6994 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6995 | op &= UINT64_C(31); |
| 6996 | op <<= 11; |
| 6997 | Value |= op; |
| 6998 | // op: RC |
| 6999 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 7000 | op &= UINT64_C(31); |
| 7001 | op <<= 6; |
| 7002 | Value |= op; |
| 7003 | break; |
| 7004 | } |
| 7005 | case PPC::VSLDOI: { |
| 7006 | // op: RT |
| 7007 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7008 | op &= UINT64_C(31); |
| 7009 | op <<= 21; |
| 7010 | Value |= op; |
| 7011 | // op: RA |
| 7012 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7013 | op &= UINT64_C(31); |
| 7014 | op <<= 16; |
| 7015 | Value |= op; |
| 7016 | // op: RB |
| 7017 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7018 | op &= UINT64_C(31); |
| 7019 | op <<= 11; |
| 7020 | Value |= op; |
| 7021 | // op: SH |
| 7022 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 7023 | op &= UINT64_C(15); |
| 7024 | op <<= 6; |
| 7025 | Value |= op; |
| 7026 | break; |
| 7027 | } |
| 7028 | case PPC::ADD4TLS: |
| 7029 | case PPC::ADD8TLS: |
| 7030 | case PPC::ADD8TLS_: { |
| 7031 | // op: RT |
| 7032 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7033 | op &= UINT64_C(31); |
| 7034 | op <<= 21; |
| 7035 | Value |= op; |
| 7036 | // op: RA |
| 7037 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7038 | op &= UINT64_C(31); |
| 7039 | op <<= 16; |
| 7040 | Value |= op; |
| 7041 | // op: RB |
| 7042 | op = getTLSRegEncoding(MI, OpNo: 2, Fixups, STI); |
| 7043 | op &= UINT64_C(31); |
| 7044 | op <<= 11; |
| 7045 | Value |= op; |
| 7046 | break; |
| 7047 | } |
| 7048 | case PPC::VMADDFP: |
| 7049 | case PPC::VNMSUBFP: { |
| 7050 | // op: RT |
| 7051 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7052 | op &= UINT64_C(31); |
| 7053 | op <<= 21; |
| 7054 | Value |= op; |
| 7055 | // op: RA |
| 7056 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7057 | op &= UINT64_C(31); |
| 7058 | op <<= 16; |
| 7059 | Value |= op; |
| 7060 | // op: RC |
| 7061 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7062 | op &= UINT64_C(31); |
| 7063 | op <<= 6; |
| 7064 | Value |= op; |
| 7065 | // op: RB |
| 7066 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 7067 | op &= UINT64_C(31); |
| 7068 | op <<= 11; |
| 7069 | Value |= op; |
| 7070 | break; |
| 7071 | } |
| 7072 | case PPC::VPERMXOR: { |
| 7073 | // op: RT |
| 7074 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7075 | op &= UINT64_C(31); |
| 7076 | op <<= 21; |
| 7077 | Value |= op; |
| 7078 | // op: RA |
| 7079 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7080 | op &= UINT64_C(31); |
| 7081 | op <<= 16; |
| 7082 | Value |= op; |
| 7083 | // op: RC |
| 7084 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 7085 | op &= UINT64_C(31); |
| 7086 | op <<= 6; |
| 7087 | Value |= op; |
| 7088 | // op: RB |
| 7089 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7090 | op &= UINT64_C(31); |
| 7091 | op <<= 11; |
| 7092 | Value |= op; |
| 7093 | break; |
| 7094 | } |
| 7095 | case PPC::PADDI: |
| 7096 | case PPC::PADDI8: { |
| 7097 | // op: RT |
| 7098 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7099 | op &= UINT64_C(31); |
| 7100 | op <<= 21; |
| 7101 | Value |= op; |
| 7102 | // op: RA |
| 7103 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7104 | op &= UINT64_C(31); |
| 7105 | op <<= 16; |
| 7106 | Value |= op; |
| 7107 | // op: SI |
| 7108 | op = getImm34EncodingNoPCRel(MI, OpNo: 2, Fixups, STI); |
| 7109 | Value |= (op & UINT64_C(17179803648)) << 16; |
| 7110 | Value |= (op & UINT64_C(65535)); |
| 7111 | break; |
| 7112 | } |
| 7113 | case PPC::PADDI8pc: |
| 7114 | case PPC::PADDIpc: { |
| 7115 | // op: RT |
| 7116 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7117 | op &= UINT64_C(31); |
| 7118 | op <<= 21; |
| 7119 | Value |= op; |
| 7120 | // op: RA |
| 7121 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7122 | op &= UINT64_C(31); |
| 7123 | op <<= 16; |
| 7124 | Value |= op; |
| 7125 | // op: SI |
| 7126 | op = getImm34EncodingPCRel(MI, OpNo: 2, Fixups, STI); |
| 7127 | Value |= (op & UINT64_C(17179803648)) << 16; |
| 7128 | Value |= (op & UINT64_C(65535)); |
| 7129 | break; |
| 7130 | } |
| 7131 | case PPC::EVLHHESPLAT: |
| 7132 | case PPC::EVLHHOSSPLAT: |
| 7133 | case PPC::EVLHHOUSPLAT: { |
| 7134 | // op: RT |
| 7135 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7136 | op &= UINT64_C(31); |
| 7137 | op <<= 21; |
| 7138 | Value |= op; |
| 7139 | // op: RA |
| 7140 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7141 | op &= UINT64_C(31); |
| 7142 | op <<= 16; |
| 7143 | Value |= op; |
| 7144 | // op: D |
| 7145 | op = getDispSPE2Encoding(MI, OpNo: 1, Fixups, STI); |
| 7146 | op &= UINT64_C(31); |
| 7147 | op <<= 11; |
| 7148 | Value |= op; |
| 7149 | break; |
| 7150 | } |
| 7151 | case PPC::EVLWHE: |
| 7152 | case PPC::EVLWHOS: |
| 7153 | case PPC::EVLWHOU: |
| 7154 | case PPC::EVLWHSPLAT: |
| 7155 | case PPC::EVLWWSPLAT: |
| 7156 | case PPC::EVSTWHE: |
| 7157 | case PPC::EVSTWHO: |
| 7158 | case PPC::EVSTWWE: |
| 7159 | case PPC::EVSTWWO: { |
| 7160 | // op: RT |
| 7161 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7162 | op &= UINT64_C(31); |
| 7163 | op <<= 21; |
| 7164 | Value |= op; |
| 7165 | // op: RA |
| 7166 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7167 | op &= UINT64_C(31); |
| 7168 | op <<= 16; |
| 7169 | Value |= op; |
| 7170 | // op: D |
| 7171 | op = getDispSPE4Encoding(MI, OpNo: 1, Fixups, STI); |
| 7172 | op &= UINT64_C(31); |
| 7173 | op <<= 11; |
| 7174 | Value |= op; |
| 7175 | break; |
| 7176 | } |
| 7177 | case PPC::EVLDD: |
| 7178 | case PPC::EVLDH: |
| 7179 | case PPC::EVLDW: |
| 7180 | case PPC::EVSTDD: |
| 7181 | case PPC::EVSTDH: |
| 7182 | case PPC::EVSTDW: { |
| 7183 | // op: RT |
| 7184 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7185 | op &= UINT64_C(31); |
| 7186 | op <<= 21; |
| 7187 | Value |= op; |
| 7188 | // op: RA |
| 7189 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7190 | op &= UINT64_C(31); |
| 7191 | op <<= 16; |
| 7192 | Value |= op; |
| 7193 | // op: D |
| 7194 | op = getDispSPE8Encoding(MI, OpNo: 1, Fixups, STI); |
| 7195 | op &= UINT64_C(31); |
| 7196 | op <<= 11; |
| 7197 | Value |= op; |
| 7198 | break; |
| 7199 | } |
| 7200 | case PPC::EFDCFS: |
| 7201 | case PPC::EFDCFSF: |
| 7202 | case PPC::EFDCFSI: |
| 7203 | case PPC::EFDCFSID: |
| 7204 | case PPC::EFDCFUF: |
| 7205 | case PPC::EFDCFUI: |
| 7206 | case PPC::EFDCFUID: |
| 7207 | case PPC::EFDCTSF: |
| 7208 | case PPC::EFDCTSI: |
| 7209 | case PPC::EFDCTSIDZ: |
| 7210 | case PPC::EFDCTSIZ: |
| 7211 | case PPC::EFDCTUF: |
| 7212 | case PPC::EFDCTUI: |
| 7213 | case PPC::EFDCTUIDZ: |
| 7214 | case PPC::EFDCTUIZ: |
| 7215 | case PPC::EFSCFD: |
| 7216 | case PPC::EFSCFSF: |
| 7217 | case PPC::EFSCFSI: |
| 7218 | case PPC::EFSCFUF: |
| 7219 | case PPC::EFSCFUI: |
| 7220 | case PPC::EFSCTSF: |
| 7221 | case PPC::EFSCTSI: |
| 7222 | case PPC::EFSCTSIZ: |
| 7223 | case PPC::EFSCTUF: |
| 7224 | case PPC::EFSCTUI: |
| 7225 | case PPC::EFSCTUIZ: |
| 7226 | case PPC::EVFSCFSF: |
| 7227 | case PPC::EVFSCFSI: |
| 7228 | case PPC::EVFSCFUF: |
| 7229 | case PPC::EVFSCFUI: |
| 7230 | case PPC::EVFSCTSF: |
| 7231 | case PPC::EVFSCTSI: |
| 7232 | case PPC::EVFSCTSIZ: |
| 7233 | case PPC::EVFSCTUF: |
| 7234 | case PPC::EVFSCTUI: |
| 7235 | case PPC::EVFSCTUIZ: |
| 7236 | case PPC::SLBMFEV: { |
| 7237 | // op: RT |
| 7238 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7239 | op &= UINT64_C(31); |
| 7240 | op <<= 21; |
| 7241 | Value |= op; |
| 7242 | // op: RB |
| 7243 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7244 | op &= UINT64_C(31); |
| 7245 | op <<= 11; |
| 7246 | Value |= op; |
| 7247 | break; |
| 7248 | } |
| 7249 | case PPC::PLI: |
| 7250 | case PPC::PLI8: { |
| 7251 | // op: RT |
| 7252 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7253 | op &= UINT64_C(31); |
| 7254 | op <<= 21; |
| 7255 | Value |= op; |
| 7256 | // op: SI |
| 7257 | op = getImm34EncodingNoPCRel(MI, OpNo: 1, Fixups, STI); |
| 7258 | Value |= (op & UINT64_C(17179803648)) << 16; |
| 7259 | Value |= (op & UINT64_C(65535)); |
| 7260 | break; |
| 7261 | } |
| 7262 | case PPC::PLA: |
| 7263 | case PPC::PLA8: { |
| 7264 | // op: RT |
| 7265 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7266 | op &= UINT64_C(31); |
| 7267 | op <<= 21; |
| 7268 | Value |= op; |
| 7269 | // op: SI |
| 7270 | op = getImm34EncodingNoPCRel(MI, OpNo: 2, Fixups, STI); |
| 7271 | Value |= (op & UINT64_C(17179803648)) << 16; |
| 7272 | Value |= (op & UINT64_C(65535)); |
| 7273 | break; |
| 7274 | } |
| 7275 | case PPC::PLA8pc: |
| 7276 | case PPC::PLApc: { |
| 7277 | // op: RT |
| 7278 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7279 | op &= UINT64_C(31); |
| 7280 | op <<= 21; |
| 7281 | Value |= op; |
| 7282 | // op: SI |
| 7283 | op = getImm34EncodingPCRel(MI, OpNo: 1, Fixups, STI); |
| 7284 | Value |= (op & UINT64_C(17179803648)) << 16; |
| 7285 | Value |= (op & UINT64_C(65535)); |
| 7286 | break; |
| 7287 | } |
| 7288 | case PPC::XSXEXPDP: |
| 7289 | case PPC::XSXSIGDP: { |
| 7290 | // op: RT |
| 7291 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7292 | op &= UINT64_C(31); |
| 7293 | op <<= 21; |
| 7294 | Value |= op; |
| 7295 | // op: XB |
| 7296 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7297 | Value |= (op & UINT64_C(31)) << 11; |
| 7298 | Value |= (op & UINT64_C(32)) >> 4; |
| 7299 | break; |
| 7300 | } |
| 7301 | case PPC::MFBHRBE: { |
| 7302 | // op: RT |
| 7303 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7304 | op &= UINT64_C(31); |
| 7305 | op <<= 21; |
| 7306 | Value |= op; |
| 7307 | // op: imm |
| 7308 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7309 | op &= UINT64_C(1023); |
| 7310 | op <<= 11; |
| 7311 | Value |= op; |
| 7312 | break; |
| 7313 | } |
| 7314 | case PPC::LQ: { |
| 7315 | // op: RTp |
| 7316 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7317 | op &= UINT64_C(31); |
| 7318 | op <<= 21; |
| 7319 | Value |= op; |
| 7320 | // op: RA |
| 7321 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7322 | op &= UINT64_C(31); |
| 7323 | op <<= 16; |
| 7324 | Value |= op; |
| 7325 | // op: DQ |
| 7326 | op = getDispRIX16Encoding(MI, OpNo: 1, Fixups, STI); |
| 7327 | op &= UINT64_C(4095); |
| 7328 | op <<= 4; |
| 7329 | Value |= op; |
| 7330 | break; |
| 7331 | } |
| 7332 | case PPC::RFEBB: { |
| 7333 | // op: S |
| 7334 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7335 | op &= UINT64_C(1); |
| 7336 | op <<= 11; |
| 7337 | Value |= op; |
| 7338 | break; |
| 7339 | } |
| 7340 | case PPC::DENBCD: |
| 7341 | case PPC::DENBCDQ: |
| 7342 | case PPC::DENBCDQ_rec: |
| 7343 | case PPC::DENBCD_rec: { |
| 7344 | // op: S |
| 7345 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7346 | op &= UINT64_C(1); |
| 7347 | op <<= 20; |
| 7348 | Value |= op; |
| 7349 | // op: FRT |
| 7350 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7351 | op &= UINT64_C(31); |
| 7352 | op <<= 21; |
| 7353 | Value |= op; |
| 7354 | // op: FRB |
| 7355 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7356 | op &= UINT64_C(31); |
| 7357 | op <<= 11; |
| 7358 | Value |= op; |
| 7359 | break; |
| 7360 | } |
| 7361 | case PPC::DDEDPD: |
| 7362 | case PPC::DDEDPDQ: |
| 7363 | case PPC::DDEDPDQ_rec: |
| 7364 | case PPC::DDEDPD_rec: { |
| 7365 | // op: SP |
| 7366 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7367 | op &= UINT64_C(3); |
| 7368 | op <<= 19; |
| 7369 | Value |= op; |
| 7370 | // op: FRT |
| 7371 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7372 | op &= UINT64_C(31); |
| 7373 | op <<= 21; |
| 7374 | Value |= op; |
| 7375 | // op: FRB |
| 7376 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7377 | op &= UINT64_C(31); |
| 7378 | op <<= 11; |
| 7379 | Value |= op; |
| 7380 | break; |
| 7381 | } |
| 7382 | case PPC::DSS: { |
| 7383 | // op: STRM |
| 7384 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7385 | op &= UINT64_C(3); |
| 7386 | op <<= 21; |
| 7387 | Value |= op; |
| 7388 | break; |
| 7389 | } |
| 7390 | case PPC::DST: |
| 7391 | case PPC::DST64: |
| 7392 | case PPC::DSTST: |
| 7393 | case PPC::DSTST64: |
| 7394 | case PPC::DSTSTT: |
| 7395 | case PPC::DSTSTT64: |
| 7396 | case PPC::DSTT: |
| 7397 | case PPC::DSTT64: { |
| 7398 | // op: STRM |
| 7399 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7400 | op &= UINT64_C(3); |
| 7401 | op <<= 21; |
| 7402 | Value |= op; |
| 7403 | // op: RA |
| 7404 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7405 | op &= UINT64_C(31); |
| 7406 | op <<= 16; |
| 7407 | Value |= op; |
| 7408 | // op: RB |
| 7409 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7410 | op &= UINT64_C(31); |
| 7411 | op <<= 11; |
| 7412 | Value |= op; |
| 7413 | break; |
| 7414 | } |
| 7415 | case PPC::DCBF: |
| 7416 | case PPC::DCBT: |
| 7417 | case PPC::DCBTST: { |
| 7418 | // op: TH |
| 7419 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7420 | op &= UINT64_C(31); |
| 7421 | op <<= 21; |
| 7422 | Value |= op; |
| 7423 | // op: RA |
| 7424 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7425 | op &= UINT64_C(31); |
| 7426 | op <<= 16; |
| 7427 | Value |= op; |
| 7428 | // op: RB |
| 7429 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7430 | op &= UINT64_C(31); |
| 7431 | op <<= 11; |
| 7432 | Value |= op; |
| 7433 | break; |
| 7434 | } |
| 7435 | case PPC::DCBTEP: |
| 7436 | case PPC::DCBTSTEP: { |
| 7437 | // op: TH |
| 7438 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7439 | op &= UINT64_C(31); |
| 7440 | op <<= 21; |
| 7441 | Value |= op; |
| 7442 | // op: RA |
| 7443 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7444 | op &= UINT64_C(31); |
| 7445 | op <<= 16; |
| 7446 | Value |= op; |
| 7447 | // op: RB |
| 7448 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7449 | op &= UINT64_C(31); |
| 7450 | op <<= 11; |
| 7451 | Value |= op; |
| 7452 | break; |
| 7453 | } |
| 7454 | case PPC::MTVSCR: { |
| 7455 | // op: VB |
| 7456 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7457 | op &= UINT64_C(31); |
| 7458 | op <<= 11; |
| 7459 | Value |= op; |
| 7460 | break; |
| 7461 | } |
| 7462 | case PPC::V_SET0: |
| 7463 | case PPC::V_SET0B: |
| 7464 | case PPC::V_SET0H: { |
| 7465 | // op: VD |
| 7466 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7467 | Value |= (op & UINT64_C(31)) << 21; |
| 7468 | Value |= (op & UINT64_C(31)) << 16; |
| 7469 | Value |= (op & UINT64_C(31)) << 11; |
| 7470 | break; |
| 7471 | } |
| 7472 | case PPC::MFVSCR: |
| 7473 | case PPC::V_SETALLONES: |
| 7474 | case PPC::V_SETALLONESB: |
| 7475 | case PPC::V_SETALLONESH: { |
| 7476 | // op: VD |
| 7477 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7478 | op &= UINT64_C(31); |
| 7479 | op <<= 21; |
| 7480 | Value |= op; |
| 7481 | break; |
| 7482 | } |
| 7483 | case PPC::VSPLTISB: |
| 7484 | case PPC::VSPLTISH: |
| 7485 | case PPC::VSPLTISW: { |
| 7486 | // op: VD |
| 7487 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7488 | op &= UINT64_C(31); |
| 7489 | op <<= 21; |
| 7490 | Value |= op; |
| 7491 | // op: IMM |
| 7492 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7493 | op &= UINT64_C(31); |
| 7494 | op <<= 16; |
| 7495 | Value |= op; |
| 7496 | break; |
| 7497 | } |
| 7498 | case PPC::VMUL10CUQ: |
| 7499 | case PPC::VMUL10UQ: |
| 7500 | case PPC::VSBOX: { |
| 7501 | // op: VD |
| 7502 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7503 | op &= UINT64_C(31); |
| 7504 | op <<= 21; |
| 7505 | Value |= op; |
| 7506 | // op: VA |
| 7507 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7508 | op &= UINT64_C(31); |
| 7509 | op <<= 16; |
| 7510 | Value |= op; |
| 7511 | break; |
| 7512 | } |
| 7513 | case PPC::VSHASIGMAD: |
| 7514 | case PPC::VSHASIGMAW: { |
| 7515 | // op: VD |
| 7516 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7517 | op &= UINT64_C(31); |
| 7518 | op <<= 21; |
| 7519 | Value |= op; |
| 7520 | // op: VA |
| 7521 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7522 | op &= UINT64_C(31); |
| 7523 | op <<= 16; |
| 7524 | Value |= op; |
| 7525 | // op: ST |
| 7526 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7527 | op &= UINT64_C(1); |
| 7528 | op <<= 15; |
| 7529 | Value |= op; |
| 7530 | // op: SIX |
| 7531 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 7532 | op &= UINT64_C(15); |
| 7533 | op <<= 11; |
| 7534 | Value |= op; |
| 7535 | break; |
| 7536 | } |
| 7537 | case PPC::BCDCPSGN_rec: |
| 7538 | case PPC::BCDUS_rec: |
| 7539 | case PPC::BCDUTRUNC_rec: |
| 7540 | case PPC::VABSDUB: |
| 7541 | case PPC::VABSDUH: |
| 7542 | case PPC::VABSDUW: |
| 7543 | case PPC::VADDCUQ: |
| 7544 | case PPC::VADDCUW: |
| 7545 | case PPC::VADDFP: |
| 7546 | case PPC::VADDSBS: |
| 7547 | case PPC::VADDSHS: |
| 7548 | case PPC::VADDSWS: |
| 7549 | case PPC::VADDUBM: |
| 7550 | case PPC::VADDUBS: |
| 7551 | case PPC::VADDUDM: |
| 7552 | case PPC::VADDUHM: |
| 7553 | case PPC::VADDUHS: |
| 7554 | case PPC::VADDUQM: |
| 7555 | case PPC::VADDUWM: |
| 7556 | case PPC::VADDUWS: |
| 7557 | case PPC::VAND: |
| 7558 | case PPC::VANDC: |
| 7559 | case PPC::VAVGSB: |
| 7560 | case PPC::VAVGSH: |
| 7561 | case PPC::VAVGSW: |
| 7562 | case PPC::VAVGUB: |
| 7563 | case PPC::VAVGUH: |
| 7564 | case PPC::VAVGUW: |
| 7565 | case PPC::VBPERMD: |
| 7566 | case PPC::VBPERMQ: |
| 7567 | case PPC::VCFSX: |
| 7568 | case PPC::VCFUGED: |
| 7569 | case PPC::VCFUX: |
| 7570 | case PPC::VCIPHER: |
| 7571 | case PPC::VCIPHERLAST: |
| 7572 | case PPC::VCLRLB: |
| 7573 | case PPC::VCLRRB: |
| 7574 | case PPC::VCLZDM: |
| 7575 | case PPC::VCMPBFP: |
| 7576 | case PPC::VCMPBFP_rec: |
| 7577 | case PPC::VCMPEQFP: |
| 7578 | case PPC::VCMPEQFP_rec: |
| 7579 | case PPC::VCMPEQUB: |
| 7580 | case PPC::VCMPEQUB_rec: |
| 7581 | case PPC::VCMPEQUD: |
| 7582 | case PPC::VCMPEQUD_rec: |
| 7583 | case PPC::VCMPEQUH: |
| 7584 | case PPC::VCMPEQUH_rec: |
| 7585 | case PPC::VCMPEQUQ: |
| 7586 | case PPC::VCMPEQUQ_rec: |
| 7587 | case PPC::VCMPEQUW: |
| 7588 | case PPC::VCMPEQUW_rec: |
| 7589 | case PPC::VCMPGEFP: |
| 7590 | case PPC::VCMPGEFP_rec: |
| 7591 | case PPC::VCMPGTFP: |
| 7592 | case PPC::VCMPGTFP_rec: |
| 7593 | case PPC::VCMPGTSB: |
| 7594 | case PPC::VCMPGTSB_rec: |
| 7595 | case PPC::VCMPGTSD: |
| 7596 | case PPC::VCMPGTSD_rec: |
| 7597 | case PPC::VCMPGTSH: |
| 7598 | case PPC::VCMPGTSH_rec: |
| 7599 | case PPC::VCMPGTSQ: |
| 7600 | case PPC::VCMPGTSQ_rec: |
| 7601 | case PPC::VCMPGTSW: |
| 7602 | case PPC::VCMPGTSW_rec: |
| 7603 | case PPC::VCMPGTUB: |
| 7604 | case PPC::VCMPGTUB_rec: |
| 7605 | case PPC::VCMPGTUD: |
| 7606 | case PPC::VCMPGTUD_rec: |
| 7607 | case PPC::VCMPGTUH: |
| 7608 | case PPC::VCMPGTUH_rec: |
| 7609 | case PPC::VCMPGTUQ: |
| 7610 | case PPC::VCMPGTUQ_rec: |
| 7611 | case PPC::VCMPGTUW: |
| 7612 | case PPC::VCMPGTUW_rec: |
| 7613 | case PPC::VCMPNEB: |
| 7614 | case PPC::VCMPNEB_rec: |
| 7615 | case PPC::VCMPNEH: |
| 7616 | case PPC::VCMPNEH_rec: |
| 7617 | case PPC::VCMPNEW: |
| 7618 | case PPC::VCMPNEW_rec: |
| 7619 | case PPC::VCMPNEZB: |
| 7620 | case PPC::VCMPNEZB_rec: |
| 7621 | case PPC::VCMPNEZH: |
| 7622 | case PPC::VCMPNEZH_rec: |
| 7623 | case PPC::VCMPNEZW: |
| 7624 | case PPC::VCMPNEZW_rec: |
| 7625 | case PPC::VCTSXS: |
| 7626 | case PPC::VCTUXS: |
| 7627 | case PPC::VCTZDM: |
| 7628 | case PPC::VDIVESD: |
| 7629 | case PPC::VDIVESQ: |
| 7630 | case PPC::VDIVESW: |
| 7631 | case PPC::VDIVEUD: |
| 7632 | case PPC::VDIVEUQ: |
| 7633 | case PPC::VDIVEUW: |
| 7634 | case PPC::VDIVSD: |
| 7635 | case PPC::VDIVSQ: |
| 7636 | case PPC::VDIVSW: |
| 7637 | case PPC::VDIVUD: |
| 7638 | case PPC::VDIVUQ: |
| 7639 | case PPC::VDIVUW: |
| 7640 | case PPC::VEQV: |
| 7641 | case PPC::VEXTRACTD: |
| 7642 | case PPC::VEXTRACTUB: |
| 7643 | case PPC::VEXTRACTUH: |
| 7644 | case PPC::VEXTRACTUW: |
| 7645 | case PPC::VEXTUBLX: |
| 7646 | case PPC::VEXTUBRX: |
| 7647 | case PPC::VEXTUHLX: |
| 7648 | case PPC::VEXTUHRX: |
| 7649 | case PPC::VEXTUWLX: |
| 7650 | case PPC::VEXTUWRX: |
| 7651 | case PPC::VINSERTD: |
| 7652 | case PPC::VINSERTW: |
| 7653 | case PPC::VMAXFP: |
| 7654 | case PPC::VMAXSB: |
| 7655 | case PPC::VMAXSD: |
| 7656 | case PPC::VMAXSH: |
| 7657 | case PPC::VMAXSW: |
| 7658 | case PPC::VMAXUB: |
| 7659 | case PPC::VMAXUD: |
| 7660 | case PPC::VMAXUH: |
| 7661 | case PPC::VMAXUW: |
| 7662 | case PPC::VMINFP: |
| 7663 | case PPC::VMINSB: |
| 7664 | case PPC::VMINSD: |
| 7665 | case PPC::VMINSH: |
| 7666 | case PPC::VMINSW: |
| 7667 | case PPC::VMINUB: |
| 7668 | case PPC::VMINUD: |
| 7669 | case PPC::VMINUH: |
| 7670 | case PPC::VMINUW: |
| 7671 | case PPC::VMODSD: |
| 7672 | case PPC::VMODSQ: |
| 7673 | case PPC::VMODSW: |
| 7674 | case PPC::VMODUD: |
| 7675 | case PPC::VMODUQ: |
| 7676 | case PPC::VMODUW: |
| 7677 | case PPC::VMRGEW: |
| 7678 | case PPC::VMRGHB: |
| 7679 | case PPC::VMRGHH: |
| 7680 | case PPC::VMRGHW: |
| 7681 | case PPC::VMRGLB: |
| 7682 | case PPC::VMRGLH: |
| 7683 | case PPC::VMRGLW: |
| 7684 | case PPC::VMRGOW: |
| 7685 | case PPC::VMUL10ECUQ: |
| 7686 | case PPC::VMUL10EUQ: |
| 7687 | case PPC::VMULESB: |
| 7688 | case PPC::VMULESD: |
| 7689 | case PPC::VMULESH: |
| 7690 | case PPC::VMULESW: |
| 7691 | case PPC::VMULEUB: |
| 7692 | case PPC::VMULEUD: |
| 7693 | case PPC::VMULEUH: |
| 7694 | case PPC::VMULEUW: |
| 7695 | case PPC::VMULHSD: |
| 7696 | case PPC::VMULHSW: |
| 7697 | case PPC::VMULHUD: |
| 7698 | case PPC::VMULHUW: |
| 7699 | case PPC::VMULLD: |
| 7700 | case PPC::VMULOSB: |
| 7701 | case PPC::VMULOSD: |
| 7702 | case PPC::VMULOSH: |
| 7703 | case PPC::VMULOSW: |
| 7704 | case PPC::VMULOUB: |
| 7705 | case PPC::VMULOUD: |
| 7706 | case PPC::VMULOUH: |
| 7707 | case PPC::VMULOUW: |
| 7708 | case PPC::VMULUWM: |
| 7709 | case PPC::VNAND: |
| 7710 | case PPC::VNCIPHER: |
| 7711 | case PPC::VNCIPHERLAST: |
| 7712 | case PPC::VNOR: |
| 7713 | case PPC::VOR: |
| 7714 | case PPC::VORC: |
| 7715 | case PPC::VPDEPD: |
| 7716 | case PPC::VPEXTD: |
| 7717 | case PPC::VPKPX: |
| 7718 | case PPC::VPKSDSS: |
| 7719 | case PPC::VPKSDUS: |
| 7720 | case PPC::VPKSHSS: |
| 7721 | case PPC::VPKSHUS: |
| 7722 | case PPC::VPKSWSS: |
| 7723 | case PPC::VPKSWUS: |
| 7724 | case PPC::VPKUDUM: |
| 7725 | case PPC::VPKUDUS: |
| 7726 | case PPC::VPKUHUM: |
| 7727 | case PPC::VPKUHUS: |
| 7728 | case PPC::VPKUWUM: |
| 7729 | case PPC::VPKUWUS: |
| 7730 | case PPC::VPMSUMB: |
| 7731 | case PPC::VPMSUMD: |
| 7732 | case PPC::VPMSUMH: |
| 7733 | case PPC::VPMSUMW: |
| 7734 | case PPC::VRLB: |
| 7735 | case PPC::VRLD: |
| 7736 | case PPC::VRLDMI: |
| 7737 | case PPC::VRLDNM: |
| 7738 | case PPC::VRLH: |
| 7739 | case PPC::VRLQ: |
| 7740 | case PPC::VRLQMI: |
| 7741 | case PPC::VRLQNM: |
| 7742 | case PPC::VRLW: |
| 7743 | case PPC::VRLWMI: |
| 7744 | case PPC::VRLWNM: |
| 7745 | case PPC::VSL: |
| 7746 | case PPC::VSLB: |
| 7747 | case PPC::VSLD: |
| 7748 | case PPC::VSLH: |
| 7749 | case PPC::VSLO: |
| 7750 | case PPC::VSLQ: |
| 7751 | case PPC::VSLV: |
| 7752 | case PPC::VSLW: |
| 7753 | case PPC::VSPLTB: |
| 7754 | case PPC::VSPLTBs: |
| 7755 | case PPC::VSPLTH: |
| 7756 | case PPC::VSPLTHs: |
| 7757 | case PPC::VSPLTW: |
| 7758 | case PPC::VSR: |
| 7759 | case PPC::VSRAB: |
| 7760 | case PPC::VSRAD: |
| 7761 | case PPC::VSRAH: |
| 7762 | case PPC::VSRAQ: |
| 7763 | case PPC::VSRAW: |
| 7764 | case PPC::VSRB: |
| 7765 | case PPC::VSRD: |
| 7766 | case PPC::VSRH: |
| 7767 | case PPC::VSRO: |
| 7768 | case PPC::VSRQ: |
| 7769 | case PPC::VSRV: |
| 7770 | case PPC::VSRW: |
| 7771 | case PPC::VSUBCUQ: |
| 7772 | case PPC::VSUBCUW: |
| 7773 | case PPC::VSUBFP: |
| 7774 | case PPC::VSUBSBS: |
| 7775 | case PPC::VSUBSHS: |
| 7776 | case PPC::VSUBSWS: |
| 7777 | case PPC::VSUBUBM: |
| 7778 | case PPC::VSUBUBS: |
| 7779 | case PPC::VSUBUDM: |
| 7780 | case PPC::VSUBUHM: |
| 7781 | case PPC::VSUBUHS: |
| 7782 | case PPC::VSUBUQM: |
| 7783 | case PPC::VSUBUWM: |
| 7784 | case PPC::VSUBUWS: |
| 7785 | case PPC::VSUM2SWS: |
| 7786 | case PPC::VSUM4SBS: |
| 7787 | case PPC::VSUM4SHS: |
| 7788 | case PPC::VSUM4UBS: |
| 7789 | case PPC::VSUMSWS: |
| 7790 | case PPC::VXOR: { |
| 7791 | // op: VD |
| 7792 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7793 | op &= UINT64_C(31); |
| 7794 | op <<= 21; |
| 7795 | Value |= op; |
| 7796 | // op: VA |
| 7797 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7798 | op &= UINT64_C(31); |
| 7799 | op <<= 16; |
| 7800 | Value |= op; |
| 7801 | // op: VB |
| 7802 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7803 | op &= UINT64_C(31); |
| 7804 | op <<= 11; |
| 7805 | Value |= op; |
| 7806 | break; |
| 7807 | } |
| 7808 | case PPC::BCDADD_rec: |
| 7809 | case PPC::BCDSR_rec: |
| 7810 | case PPC::BCDSUB_rec: |
| 7811 | case PPC::BCDS_rec: |
| 7812 | case PPC::BCDTRUNC_rec: { |
| 7813 | // op: VD |
| 7814 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7815 | op &= UINT64_C(31); |
| 7816 | op <<= 21; |
| 7817 | Value |= op; |
| 7818 | // op: VA |
| 7819 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7820 | op &= UINT64_C(31); |
| 7821 | op <<= 16; |
| 7822 | Value |= op; |
| 7823 | // op: VB |
| 7824 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7825 | op &= UINT64_C(31); |
| 7826 | op <<= 11; |
| 7827 | Value |= op; |
| 7828 | // op: PS |
| 7829 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 7830 | op &= UINT64_C(1); |
| 7831 | op <<= 9; |
| 7832 | Value |= op; |
| 7833 | break; |
| 7834 | } |
| 7835 | case PPC::VINSBLX: |
| 7836 | case PPC::VINSBRX: |
| 7837 | case PPC::VINSBVLX: |
| 7838 | case PPC::VINSBVRX: |
| 7839 | case PPC::VINSD: |
| 7840 | case PPC::VINSDLX: |
| 7841 | case PPC::VINSDRX: |
| 7842 | case PPC::VINSERTB: |
| 7843 | case PPC::VINSERTH: |
| 7844 | case PPC::VINSHLX: |
| 7845 | case PPC::VINSHRX: |
| 7846 | case PPC::VINSHVLX: |
| 7847 | case PPC::VINSHVRX: |
| 7848 | case PPC::VINSW: |
| 7849 | case PPC::VINSWLX: |
| 7850 | case PPC::VINSWRX: |
| 7851 | case PPC::VINSWVLX: |
| 7852 | case PPC::VINSWVRX: { |
| 7853 | // op: VD |
| 7854 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7855 | op &= UINT64_C(31); |
| 7856 | op <<= 21; |
| 7857 | Value |= op; |
| 7858 | // op: VA |
| 7859 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7860 | op &= UINT64_C(31); |
| 7861 | op <<= 16; |
| 7862 | Value |= op; |
| 7863 | // op: VB |
| 7864 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 7865 | op &= UINT64_C(31); |
| 7866 | op <<= 11; |
| 7867 | Value |= op; |
| 7868 | break; |
| 7869 | } |
| 7870 | case PPC::BCDCTN_rec: |
| 7871 | case PPC::BCDCTSQ_rec: |
| 7872 | case PPC::MTVSRBM: |
| 7873 | case PPC::MTVSRDM: |
| 7874 | case PPC::MTVSRHM: |
| 7875 | case PPC::MTVSRQM: |
| 7876 | case PPC::MTVSRWM: |
| 7877 | case PPC::VCFSX_0: |
| 7878 | case PPC::VCFUX_0: |
| 7879 | case PPC::VCLZB: |
| 7880 | case PPC::VCLZD: |
| 7881 | case PPC::VCLZH: |
| 7882 | case PPC::VCLZLSBB: |
| 7883 | case PPC::VCLZW: |
| 7884 | case PPC::VCTSXS_0: |
| 7885 | case PPC::VCTUXS_0: |
| 7886 | case PPC::VCTZB: |
| 7887 | case PPC::VCTZD: |
| 7888 | case PPC::VCTZH: |
| 7889 | case PPC::VCTZLSBB: |
| 7890 | case PPC::VCTZW: |
| 7891 | case PPC::VEXPANDBM: |
| 7892 | case PPC::VEXPANDDM: |
| 7893 | case PPC::VEXPANDHM: |
| 7894 | case PPC::VEXPANDQM: |
| 7895 | case PPC::VEXPANDWM: |
| 7896 | case PPC::VEXPTEFP: |
| 7897 | case PPC::VEXTRACTBM: |
| 7898 | case PPC::VEXTRACTDM: |
| 7899 | case PPC::VEXTRACTHM: |
| 7900 | case PPC::VEXTRACTQM: |
| 7901 | case PPC::VEXTRACTWM: |
| 7902 | case PPC::VEXTSB2D: |
| 7903 | case PPC::VEXTSB2Ds: |
| 7904 | case PPC::VEXTSB2W: |
| 7905 | case PPC::VEXTSB2Ws: |
| 7906 | case PPC::VEXTSD2Q: |
| 7907 | case PPC::VEXTSH2D: |
| 7908 | case PPC::VEXTSH2Ds: |
| 7909 | case PPC::VEXTSH2W: |
| 7910 | case PPC::VEXTSH2Ws: |
| 7911 | case PPC::VEXTSW2D: |
| 7912 | case PPC::VEXTSW2Ds: |
| 7913 | case PPC::VGBBD: |
| 7914 | case PPC::VLOGEFP: |
| 7915 | case PPC::VNEGD: |
| 7916 | case PPC::VNEGW: |
| 7917 | case PPC::VPOPCNTB: |
| 7918 | case PPC::VPOPCNTD: |
| 7919 | case PPC::VPOPCNTH: |
| 7920 | case PPC::VPOPCNTW: |
| 7921 | case PPC::VPRTYBD: |
| 7922 | case PPC::VPRTYBQ: |
| 7923 | case PPC::VPRTYBW: |
| 7924 | case PPC::VREFP: |
| 7925 | case PPC::VRFIM: |
| 7926 | case PPC::VRFIN: |
| 7927 | case PPC::VRFIP: |
| 7928 | case PPC::VRFIZ: |
| 7929 | case PPC::VRSQRTEFP: |
| 7930 | case PPC::VUPKHPX: |
| 7931 | case PPC::VUPKHSB: |
| 7932 | case PPC::VUPKHSH: |
| 7933 | case PPC::VUPKHSW: |
| 7934 | case PPC::VUPKLPX: |
| 7935 | case PPC::VUPKLSB: |
| 7936 | case PPC::VUPKLSH: |
| 7937 | case PPC::VUPKLSW: { |
| 7938 | // op: VD |
| 7939 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7940 | op &= UINT64_C(31); |
| 7941 | op <<= 21; |
| 7942 | Value |= op; |
| 7943 | // op: VB |
| 7944 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7945 | op &= UINT64_C(31); |
| 7946 | op <<= 11; |
| 7947 | Value |= op; |
| 7948 | break; |
| 7949 | } |
| 7950 | case PPC::BCDCFN_rec: |
| 7951 | case PPC::BCDCFSQ_rec: |
| 7952 | case PPC::BCDCFZ_rec: |
| 7953 | case PPC::BCDCTZ_rec: |
| 7954 | case PPC::BCDSETSGN_rec: { |
| 7955 | // op: VD |
| 7956 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7957 | op &= UINT64_C(31); |
| 7958 | op <<= 21; |
| 7959 | Value |= op; |
| 7960 | // op: VB |
| 7961 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7962 | op &= UINT64_C(31); |
| 7963 | op <<= 11; |
| 7964 | Value |= op; |
| 7965 | // op: PS |
| 7966 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7967 | op &= UINT64_C(1); |
| 7968 | op <<= 9; |
| 7969 | Value |= op; |
| 7970 | break; |
| 7971 | } |
| 7972 | case PPC::XSRQPI: |
| 7973 | case PPC::XSRQPIX: |
| 7974 | case PPC::XSRQPXP: { |
| 7975 | // op: VRT |
| 7976 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7977 | op &= UINT64_C(31); |
| 7978 | op <<= 21; |
| 7979 | Value |= op; |
| 7980 | // op: R |
| 7981 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7982 | op &= UINT64_C(1); |
| 7983 | op <<= 16; |
| 7984 | Value |= op; |
| 7985 | // op: VRB |
| 7986 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7987 | op &= UINT64_C(31); |
| 7988 | op <<= 11; |
| 7989 | Value |= op; |
| 7990 | // op: idx |
| 7991 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 7992 | op &= UINT64_C(3); |
| 7993 | op <<= 9; |
| 7994 | Value |= op; |
| 7995 | break; |
| 7996 | } |
| 7997 | case PPC::VSLDBI: |
| 7998 | case PPC::VSRDBI: { |
| 7999 | // op: VRT |
| 8000 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8001 | op &= UINT64_C(31); |
| 8002 | op <<= 21; |
| 8003 | Value |= op; |
| 8004 | // op: VRA |
| 8005 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8006 | op &= UINT64_C(31); |
| 8007 | op <<= 16; |
| 8008 | Value |= op; |
| 8009 | // op: VRB |
| 8010 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8011 | op &= UINT64_C(31); |
| 8012 | op <<= 11; |
| 8013 | Value |= op; |
| 8014 | // op: SD |
| 8015 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8016 | op &= UINT64_C(7); |
| 8017 | op <<= 6; |
| 8018 | Value |= op; |
| 8019 | break; |
| 8020 | } |
| 8021 | case PPC::VSTRIBL: |
| 8022 | case PPC::VSTRIBL_rec: |
| 8023 | case PPC::VSTRIBR: |
| 8024 | case PPC::VSTRIBR_rec: |
| 8025 | case PPC::VSTRIHL: |
| 8026 | case PPC::VSTRIHL_rec: |
| 8027 | case PPC::VSTRIHR: |
| 8028 | case PPC::VSTRIHR_rec: { |
| 8029 | // op: VT |
| 8030 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8031 | op &= UINT64_C(31); |
| 8032 | op <<= 21; |
| 8033 | Value |= op; |
| 8034 | // op: VB |
| 8035 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8036 | op &= UINT64_C(31); |
| 8037 | op <<= 11; |
| 8038 | Value |= op; |
| 8039 | break; |
| 8040 | } |
| 8041 | case PPC::PLXVonlypc: |
| 8042 | case PPC::PSTXVonlypc: { |
| 8043 | // op: XST |
| 8044 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8045 | op &= UINT64_C(63); |
| 8046 | op <<= 21; |
| 8047 | Value |= op; |
| 8048 | // op: D |
| 8049 | op = getImm34EncodingPCRel(MI, OpNo: 1, Fixups, STI); |
| 8050 | Value |= (op & UINT64_C(17179803648)) << 16; |
| 8051 | Value |= (op & UINT64_C(65535)); |
| 8052 | break; |
| 8053 | } |
| 8054 | case PPC::PLXV: |
| 8055 | case PPC::PLXVnopc: |
| 8056 | case PPC::PSTXV: |
| 8057 | case PPC::PSTXVnopc: { |
| 8058 | // op: XST |
| 8059 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8060 | op &= UINT64_C(63); |
| 8061 | op <<= 21; |
| 8062 | Value |= op; |
| 8063 | // op: RA |
| 8064 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8065 | op &= UINT64_C(31); |
| 8066 | op <<= 16; |
| 8067 | Value |= op; |
| 8068 | // op: D |
| 8069 | op = getDispRI34Encoding(MI, OpNo: 1, Fixups, STI); |
| 8070 | Value |= (op & UINT64_C(17179803648)) << 16; |
| 8071 | Value |= (op & UINT64_C(65535)); |
| 8072 | break; |
| 8073 | } |
| 8074 | case PPC::PLXVpc: |
| 8075 | case PPC::PSTXVpc: { |
| 8076 | // op: XST |
| 8077 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8078 | op &= UINT64_C(63); |
| 8079 | op <<= 21; |
| 8080 | Value |= op; |
| 8081 | // op: RA |
| 8082 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8083 | op &= UINT64_C(31); |
| 8084 | op <<= 16; |
| 8085 | Value |= op; |
| 8086 | // op: D |
| 8087 | op = getDispRI34PCRelEncoding(MI, OpNo: 1, Fixups, STI); |
| 8088 | Value |= (op & UINT64_C(17179803648)) << 16; |
| 8089 | Value |= (op & UINT64_C(65535)); |
| 8090 | break; |
| 8091 | } |
| 8092 | case PPC::XXLEQVOnes: |
| 8093 | case PPC::XXLXORdpz: |
| 8094 | case PPC::XXLXORspz: |
| 8095 | case PPC::XXLXORz: { |
| 8096 | // op: XT |
| 8097 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8098 | Value |= (op & UINT64_C(31)) << 21; |
| 8099 | Value |= (op & UINT64_C(31)) << 16; |
| 8100 | Value |= (op & UINT64_C(31)) << 11; |
| 8101 | Value |= (op & UINT64_C(32)) >> 3; |
| 8102 | Value |= (op & UINT64_C(32)) >> 4; |
| 8103 | Value |= (op & UINT64_C(32)) >> 5; |
| 8104 | break; |
| 8105 | } |
| 8106 | case PPC::XXSPLTIDP: |
| 8107 | case PPC::XXSPLTIW: { |
| 8108 | // op: XT |
| 8109 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8110 | Value |= (op & UINT64_C(31)) << 21; |
| 8111 | Value |= (op & UINT64_C(32)) << 11; |
| 8112 | // op: IMM32 |
| 8113 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8114 | Value |= (op & UINT64_C(4294901760)) << 16; |
| 8115 | Value |= (op & UINT64_C(65535)); |
| 8116 | break; |
| 8117 | } |
| 8118 | case PPC::XXSPLTI32DX: { |
| 8119 | // op: XT |
| 8120 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8121 | Value |= (op & UINT64_C(31)) << 21; |
| 8122 | Value |= (op & UINT64_C(32)) << 11; |
| 8123 | // op: IX |
| 8124 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8125 | op &= UINT64_C(1); |
| 8126 | op <<= 17; |
| 8127 | Value |= op; |
| 8128 | // op: IMM32 |
| 8129 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8130 | Value |= (op & UINT64_C(4294901760)) << 16; |
| 8131 | Value |= (op & UINT64_C(65535)); |
| 8132 | break; |
| 8133 | } |
| 8134 | case PPC::LXV: |
| 8135 | case PPC::STXV: { |
| 8136 | // op: XT |
| 8137 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8138 | Value |= (op & UINT64_C(31)) << 21; |
| 8139 | Value |= (op & UINT64_C(32)) >> 2; |
| 8140 | // op: RA |
| 8141 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8142 | op &= UINT64_C(31); |
| 8143 | op <<= 16; |
| 8144 | Value |= op; |
| 8145 | // op: DQ |
| 8146 | op = getDispRIX16Encoding(MI, OpNo: 1, Fixups, STI); |
| 8147 | op &= UINT64_C(4095); |
| 8148 | op <<= 4; |
| 8149 | Value |= op; |
| 8150 | break; |
| 8151 | } |
| 8152 | case PPC::XVTSTDCDP: |
| 8153 | case PPC::XVTSTDCSP: { |
| 8154 | // op: XT |
| 8155 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8156 | Value |= (op & UINT64_C(31)) << 21; |
| 8157 | Value |= (op & UINT64_C(32)) >> 5; |
| 8158 | // op: DCMX |
| 8159 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8160 | Value |= (op & UINT64_C(31)) << 16; |
| 8161 | Value |= (op & UINT64_C(64)); |
| 8162 | Value |= (op & UINT64_C(32)) >> 3; |
| 8163 | // op: XB |
| 8164 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8165 | Value |= (op & UINT64_C(31)) << 11; |
| 8166 | Value |= (op & UINT64_C(32)) >> 4; |
| 8167 | break; |
| 8168 | } |
| 8169 | case PPC::XXSPLTIB: { |
| 8170 | // op: XT |
| 8171 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8172 | Value |= (op & UINT64_C(31)) << 21; |
| 8173 | Value |= (op & UINT64_C(32)) >> 5; |
| 8174 | // op: IMM8 |
| 8175 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8176 | op &= UINT64_C(255); |
| 8177 | op <<= 11; |
| 8178 | Value |= op; |
| 8179 | break; |
| 8180 | } |
| 8181 | case PPC::MTVRD: |
| 8182 | case PPC::MTVRWA: |
| 8183 | case PPC::MTVRWZ: |
| 8184 | case PPC::MTVSRD: |
| 8185 | case PPC::MTVSRWA: |
| 8186 | case PPC::MTVSRWS: |
| 8187 | case PPC::MTVSRWZ: { |
| 8188 | // op: XT |
| 8189 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8190 | Value |= (op & UINT64_C(31)) << 21; |
| 8191 | Value |= (op & UINT64_C(32)) >> 5; |
| 8192 | // op: RA |
| 8193 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8194 | op &= UINT64_C(31); |
| 8195 | op <<= 16; |
| 8196 | Value |= op; |
| 8197 | break; |
| 8198 | } |
| 8199 | case PPC::LXSDX: |
| 8200 | case PPC::LXSIBZX: |
| 8201 | case PPC::LXSIHZX: |
| 8202 | case PPC::LXSIWAX: |
| 8203 | case PPC::LXSIWZX: |
| 8204 | case PPC::LXSSPX: |
| 8205 | case PPC::LXVB16X: |
| 8206 | case PPC::LXVD2X: |
| 8207 | case PPC::LXVDSX: |
| 8208 | case PPC::LXVH8X: |
| 8209 | case PPC::LXVL: |
| 8210 | case PPC::LXVLL: |
| 8211 | case PPC::LXVRBX: |
| 8212 | case PPC::LXVRDX: |
| 8213 | case PPC::LXVRHX: |
| 8214 | case PPC::LXVRL: |
| 8215 | case PPC::LXVRLL: |
| 8216 | case PPC::LXVRWX: |
| 8217 | case PPC::LXVW4X: |
| 8218 | case PPC::LXVWSX: |
| 8219 | case PPC::LXVX: |
| 8220 | case PPC::MTVSRDD: |
| 8221 | case PPC::STXSDX: |
| 8222 | case PPC::STXSIBX: |
| 8223 | case PPC::STXSIBXv: |
| 8224 | case PPC::STXSIHX: |
| 8225 | case PPC::STXSIHXv: |
| 8226 | case PPC::STXSIWX: |
| 8227 | case PPC::STXSSPX: |
| 8228 | case PPC::STXVB16X: |
| 8229 | case PPC::STXVD2X: |
| 8230 | case PPC::STXVH8X: |
| 8231 | case PPC::STXVL: |
| 8232 | case PPC::STXVLL: |
| 8233 | case PPC::STXVRBX: |
| 8234 | case PPC::STXVRDX: |
| 8235 | case PPC::STXVRHX: |
| 8236 | case PPC::STXVRL: |
| 8237 | case PPC::STXVRLL: |
| 8238 | case PPC::STXVRWX: |
| 8239 | case PPC::STXVW4X: |
| 8240 | case PPC::STXVX: |
| 8241 | case PPC::XSIEXPDP: { |
| 8242 | // op: XT |
| 8243 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8244 | Value |= (op & UINT64_C(31)) << 21; |
| 8245 | Value |= (op & UINT64_C(32)) >> 5; |
| 8246 | // op: RA |
| 8247 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8248 | op &= UINT64_C(31); |
| 8249 | op <<= 16; |
| 8250 | Value |= op; |
| 8251 | // op: RB |
| 8252 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8253 | op &= UINT64_C(31); |
| 8254 | op <<= 11; |
| 8255 | Value |= op; |
| 8256 | break; |
| 8257 | } |
| 8258 | case PPC::LXVKQ: { |
| 8259 | // op: XT |
| 8260 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8261 | Value |= (op & UINT64_C(31)) << 21; |
| 8262 | Value |= (op & UINT64_C(32)) >> 5; |
| 8263 | // op: UIM |
| 8264 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8265 | op &= UINT64_C(31); |
| 8266 | op <<= 11; |
| 8267 | Value |= op; |
| 8268 | break; |
| 8269 | } |
| 8270 | case PPC::XXGENPCVBM: |
| 8271 | case PPC::XXGENPCVDM: |
| 8272 | case PPC::XXGENPCVHM: |
| 8273 | case PPC::XXGENPCVWM: { |
| 8274 | // op: XT |
| 8275 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8276 | Value |= (op & UINT64_C(31)) << 21; |
| 8277 | Value |= (op & UINT64_C(32)) >> 5; |
| 8278 | // op: VRB |
| 8279 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8280 | op &= UINT64_C(31); |
| 8281 | op <<= 11; |
| 8282 | Value |= op; |
| 8283 | // op: IMM |
| 8284 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8285 | op &= UINT64_C(31); |
| 8286 | op <<= 16; |
| 8287 | Value |= op; |
| 8288 | break; |
| 8289 | } |
| 8290 | case PPC::XXPERMDIs: |
| 8291 | case PPC::XXSLDWIs: { |
| 8292 | // op: XT |
| 8293 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8294 | Value |= (op & UINT64_C(31)) << 21; |
| 8295 | Value |= (op & UINT64_C(32)) >> 5; |
| 8296 | // op: XA |
| 8297 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8298 | Value |= (op & UINT64_C(31)) << 16; |
| 8299 | Value |= (op & UINT64_C(31)) << 11; |
| 8300 | Value |= (op & UINT64_C(32)) >> 3; |
| 8301 | Value |= (op & UINT64_C(32)) >> 4; |
| 8302 | // op: D |
| 8303 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8304 | op &= UINT64_C(3); |
| 8305 | op <<= 8; |
| 8306 | Value |= op; |
| 8307 | break; |
| 8308 | } |
| 8309 | case PPC::XSADDDP: |
| 8310 | case PPC::XSADDSP: |
| 8311 | case PPC::XSCMPEQDP: |
| 8312 | case PPC::XSCMPGEDP: |
| 8313 | case PPC::XSCMPGTDP: |
| 8314 | case PPC::XSCPSGNDP: |
| 8315 | case PPC::XSDIVDP: |
| 8316 | case PPC::XSDIVSP: |
| 8317 | case PPC::XSMAXCDP: |
| 8318 | case PPC::XSMAXDP: |
| 8319 | case PPC::XSMAXJDP: |
| 8320 | case PPC::XSMINCDP: |
| 8321 | case PPC::XSMINDP: |
| 8322 | case PPC::XSMINJDP: |
| 8323 | case PPC::XSMULDP: |
| 8324 | case PPC::XSMULSP: |
| 8325 | case PPC::XSSUBDP: |
| 8326 | case PPC::XSSUBSP: |
| 8327 | case PPC::XVADDDP: |
| 8328 | case PPC::XVADDSP: |
| 8329 | case PPC::XVCMPEQDP: |
| 8330 | case PPC::XVCMPEQDP_rec: |
| 8331 | case PPC::XVCMPEQSP: |
| 8332 | case PPC::XVCMPEQSP_rec: |
| 8333 | case PPC::XVCMPGEDP: |
| 8334 | case PPC::XVCMPGEDP_rec: |
| 8335 | case PPC::XVCMPGESP: |
| 8336 | case PPC::XVCMPGESP_rec: |
| 8337 | case PPC::XVCMPGTDP: |
| 8338 | case PPC::XVCMPGTDP_rec: |
| 8339 | case PPC::XVCMPGTSP: |
| 8340 | case PPC::XVCMPGTSP_rec: |
| 8341 | case PPC::XVCPSGNDP: |
| 8342 | case PPC::XVCPSGNSP: |
| 8343 | case PPC::XVDIVDP: |
| 8344 | case PPC::XVDIVSP: |
| 8345 | case PPC::XVIEXPDP: |
| 8346 | case PPC::XVIEXPSP: |
| 8347 | case PPC::XVMAXDP: |
| 8348 | case PPC::XVMAXSP: |
| 8349 | case PPC::XVMINDP: |
| 8350 | case PPC::XVMINSP: |
| 8351 | case PPC::XVMULDP: |
| 8352 | case PPC::XVMULSP: |
| 8353 | case PPC::XVSUBDP: |
| 8354 | case PPC::XVSUBSP: |
| 8355 | case PPC::XXLAND: |
| 8356 | case PPC::XXLANDC: |
| 8357 | case PPC::XXLEQV: |
| 8358 | case PPC::XXLNAND: |
| 8359 | case PPC::XXLNOR: |
| 8360 | case PPC::XXLOR: |
| 8361 | case PPC::XXLORC: |
| 8362 | case PPC::XXLORf: |
| 8363 | case PPC::XXLXOR: |
| 8364 | case PPC::XXMRGHW: |
| 8365 | case PPC::XXMRGLW: { |
| 8366 | // op: XT |
| 8367 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8368 | Value |= (op & UINT64_C(31)) << 21; |
| 8369 | Value |= (op & UINT64_C(32)) >> 5; |
| 8370 | // op: XA |
| 8371 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8372 | Value |= (op & UINT64_C(31)) << 16; |
| 8373 | Value |= (op & UINT64_C(32)) >> 3; |
| 8374 | // op: XB |
| 8375 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8376 | Value |= (op & UINT64_C(31)) << 11; |
| 8377 | Value |= (op & UINT64_C(32)) >> 4; |
| 8378 | break; |
| 8379 | } |
| 8380 | case PPC::XXPERMDI: |
| 8381 | case PPC::XXSLDWI: { |
| 8382 | // op: XT |
| 8383 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8384 | Value |= (op & UINT64_C(31)) << 21; |
| 8385 | Value |= (op & UINT64_C(32)) >> 5; |
| 8386 | // op: XA |
| 8387 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8388 | Value |= (op & UINT64_C(31)) << 16; |
| 8389 | Value |= (op & UINT64_C(32)) >> 3; |
| 8390 | // op: XB |
| 8391 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8392 | Value |= (op & UINT64_C(31)) << 11; |
| 8393 | Value |= (op & UINT64_C(32)) >> 4; |
| 8394 | // op: D |
| 8395 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8396 | op &= UINT64_C(3); |
| 8397 | op <<= 8; |
| 8398 | Value |= op; |
| 8399 | break; |
| 8400 | } |
| 8401 | case PPC::XXBLENDVB: |
| 8402 | case PPC::XXBLENDVD: |
| 8403 | case PPC::XXBLENDVH: |
| 8404 | case PPC::XXBLENDVW: |
| 8405 | case PPC::XXSEL: { |
| 8406 | // op: XT |
| 8407 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8408 | Value |= (op & UINT64_C(31)) << 21; |
| 8409 | Value |= (op & UINT64_C(32)) >> 5; |
| 8410 | // op: XA |
| 8411 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8412 | Value |= (op & UINT64_C(31)) << 16; |
| 8413 | Value |= (op & UINT64_C(32)) >> 3; |
| 8414 | // op: XB |
| 8415 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8416 | Value |= (op & UINT64_C(31)) << 11; |
| 8417 | Value |= (op & UINT64_C(32)) >> 4; |
| 8418 | // op: XC |
| 8419 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8420 | Value |= (op & UINT64_C(31)) << 6; |
| 8421 | Value |= (op & UINT64_C(32)) >> 2; |
| 8422 | break; |
| 8423 | } |
| 8424 | case PPC::XXEVAL: { |
| 8425 | // op: XT |
| 8426 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8427 | Value |= (op & UINT64_C(31)) << 21; |
| 8428 | Value |= (op & UINT64_C(32)) >> 5; |
| 8429 | // op: XA |
| 8430 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8431 | Value |= (op & UINT64_C(31)) << 16; |
| 8432 | Value |= (op & UINT64_C(32)) >> 3; |
| 8433 | // op: XB |
| 8434 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8435 | Value |= (op & UINT64_C(31)) << 11; |
| 8436 | Value |= (op & UINT64_C(32)) >> 4; |
| 8437 | // op: XC |
| 8438 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8439 | Value |= (op & UINT64_C(31)) << 6; |
| 8440 | Value |= (op & UINT64_C(32)) >> 2; |
| 8441 | // op: IMM |
| 8442 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 8443 | op &= UINT64_C(255); |
| 8444 | op <<= 32; |
| 8445 | Value |= op; |
| 8446 | break; |
| 8447 | } |
| 8448 | case PPC::XXPERMX: { |
| 8449 | // op: XT |
| 8450 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8451 | Value |= (op & UINT64_C(31)) << 21; |
| 8452 | Value |= (op & UINT64_C(32)) >> 5; |
| 8453 | // op: XA |
| 8454 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8455 | Value |= (op & UINT64_C(31)) << 16; |
| 8456 | Value |= (op & UINT64_C(32)) >> 3; |
| 8457 | // op: XB |
| 8458 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8459 | Value |= (op & UINT64_C(31)) << 11; |
| 8460 | Value |= (op & UINT64_C(32)) >> 4; |
| 8461 | // op: XC |
| 8462 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8463 | Value |= (op & UINT64_C(31)) << 6; |
| 8464 | Value |= (op & UINT64_C(32)) >> 2; |
| 8465 | // op: IMM |
| 8466 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 8467 | op &= UINT64_C(7); |
| 8468 | op <<= 32; |
| 8469 | Value |= op; |
| 8470 | break; |
| 8471 | } |
| 8472 | case PPC::XXPERM: |
| 8473 | case PPC::XXPERMR: { |
| 8474 | // op: XT |
| 8475 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8476 | Value |= (op & UINT64_C(31)) << 21; |
| 8477 | Value |= (op & UINT64_C(32)) >> 5; |
| 8478 | // op: XA |
| 8479 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8480 | Value |= (op & UINT64_C(31)) << 16; |
| 8481 | Value |= (op & UINT64_C(32)) >> 3; |
| 8482 | // op: XB |
| 8483 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8484 | Value |= (op & UINT64_C(31)) << 11; |
| 8485 | Value |= (op & UINT64_C(32)) >> 4; |
| 8486 | break; |
| 8487 | } |
| 8488 | case PPC::XSMADDADP: |
| 8489 | case PPC::XSMADDASP: |
| 8490 | case PPC::XSMADDMDP: |
| 8491 | case PPC::XSMADDMSP: |
| 8492 | case PPC::XSMSUBADP: |
| 8493 | case PPC::XSMSUBASP: |
| 8494 | case PPC::XSMSUBMDP: |
| 8495 | case PPC::XSMSUBMSP: |
| 8496 | case PPC::XSNMADDADP: |
| 8497 | case PPC::XSNMADDASP: |
| 8498 | case PPC::XSNMADDMDP: |
| 8499 | case PPC::XSNMADDMSP: |
| 8500 | case PPC::XSNMSUBADP: |
| 8501 | case PPC::XSNMSUBASP: |
| 8502 | case PPC::XSNMSUBMDP: |
| 8503 | case PPC::XSNMSUBMSP: |
| 8504 | case PPC::XVMADDADP: |
| 8505 | case PPC::XVMADDASP: |
| 8506 | case PPC::XVMADDMDP: |
| 8507 | case PPC::XVMADDMSP: |
| 8508 | case PPC::XVMSUBADP: |
| 8509 | case PPC::XVMSUBASP: |
| 8510 | case PPC::XVMSUBMDP: |
| 8511 | case PPC::XVMSUBMSP: |
| 8512 | case PPC::XVNMADDADP: |
| 8513 | case PPC::XVNMADDASP: |
| 8514 | case PPC::XVNMADDMDP: |
| 8515 | case PPC::XVNMADDMSP: |
| 8516 | case PPC::XVNMSUBADP: |
| 8517 | case PPC::XVNMSUBASP: |
| 8518 | case PPC::XVNMSUBMDP: |
| 8519 | case PPC::XVNMSUBMSP: { |
| 8520 | // op: XT |
| 8521 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8522 | Value |= (op & UINT64_C(31)) << 21; |
| 8523 | Value |= (op & UINT64_C(32)) >> 5; |
| 8524 | // op: XA |
| 8525 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8526 | Value |= (op & UINT64_C(31)) << 16; |
| 8527 | Value |= (op & UINT64_C(32)) >> 3; |
| 8528 | // op: XB |
| 8529 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8530 | Value |= (op & UINT64_C(31)) << 11; |
| 8531 | Value |= (op & UINT64_C(32)) >> 4; |
| 8532 | break; |
| 8533 | } |
| 8534 | case PPC::XSABSDP: |
| 8535 | case PPC::XSCVDPHP: |
| 8536 | case PPC::XSCVDPSP: |
| 8537 | case PPC::XSCVDPSPN: |
| 8538 | case PPC::XSCVDPSXDS: |
| 8539 | case PPC::XSCVDPSXDSs: |
| 8540 | case PPC::XSCVDPSXWS: |
| 8541 | case PPC::XSCVDPSXWSs: |
| 8542 | case PPC::XSCVDPUXDS: |
| 8543 | case PPC::XSCVDPUXDSs: |
| 8544 | case PPC::XSCVDPUXWS: |
| 8545 | case PPC::XSCVDPUXWSs: |
| 8546 | case PPC::XSCVHPDP: |
| 8547 | case PPC::XSCVSPDP: |
| 8548 | case PPC::XSCVSPDPN: |
| 8549 | case PPC::XSCVSXDDP: |
| 8550 | case PPC::XSCVSXDSP: |
| 8551 | case PPC::XSCVUXDDP: |
| 8552 | case PPC::XSCVUXDSP: |
| 8553 | case PPC::XSNABSDP: |
| 8554 | case PPC::XSNABSDPs: |
| 8555 | case PPC::XSNEGDP: |
| 8556 | case PPC::XSRDPI: |
| 8557 | case PPC::XSRDPIC: |
| 8558 | case PPC::XSRDPIM: |
| 8559 | case PPC::XSRDPIP: |
| 8560 | case PPC::XSRDPIZ: |
| 8561 | case PPC::XSREDP: |
| 8562 | case PPC::XSRESP: |
| 8563 | case PPC::XSRSP: |
| 8564 | case PPC::XSRSQRTEDP: |
| 8565 | case PPC::XSRSQRTESP: |
| 8566 | case PPC::XSSQRTDP: |
| 8567 | case PPC::XSSQRTSP: |
| 8568 | case PPC::XVABSDP: |
| 8569 | case PPC::XVABSSP: |
| 8570 | case PPC::XVCVBF16SPN: |
| 8571 | case PPC::XVCVDPSP: |
| 8572 | case PPC::XVCVDPSXDS: |
| 8573 | case PPC::XVCVDPSXWS: |
| 8574 | case PPC::XVCVDPUXDS: |
| 8575 | case PPC::XVCVDPUXWS: |
| 8576 | case PPC::XVCVHPSP: |
| 8577 | case PPC::XVCVSPBF16: |
| 8578 | case PPC::XVCVSPDP: |
| 8579 | case PPC::XVCVSPHP: |
| 8580 | case PPC::XVCVSPSXDS: |
| 8581 | case PPC::XVCVSPSXWS: |
| 8582 | case PPC::XVCVSPUXDS: |
| 8583 | case PPC::XVCVSPUXWS: |
| 8584 | case PPC::XVCVSXDDP: |
| 8585 | case PPC::XVCVSXDSP: |
| 8586 | case PPC::XVCVSXWDP: |
| 8587 | case PPC::XVCVSXWSP: |
| 8588 | case PPC::XVCVUXDDP: |
| 8589 | case PPC::XVCVUXDSP: |
| 8590 | case PPC::XVCVUXWDP: |
| 8591 | case PPC::XVCVUXWSP: |
| 8592 | case PPC::XVNABSDP: |
| 8593 | case PPC::XVNABSSP: |
| 8594 | case PPC::XVNEGDP: |
| 8595 | case PPC::XVNEGSP: |
| 8596 | case PPC::XVRDPI: |
| 8597 | case PPC::XVRDPIC: |
| 8598 | case PPC::XVRDPIM: |
| 8599 | case PPC::XVRDPIP: |
| 8600 | case PPC::XVRDPIZ: |
| 8601 | case PPC::XVREDP: |
| 8602 | case PPC::XVRESP: |
| 8603 | case PPC::XVRSPI: |
| 8604 | case PPC::XVRSPIC: |
| 8605 | case PPC::XVRSPIM: |
| 8606 | case PPC::XVRSPIP: |
| 8607 | case PPC::XVRSPIZ: |
| 8608 | case PPC::XVRSQRTEDP: |
| 8609 | case PPC::XVRSQRTESP: |
| 8610 | case PPC::XVSQRTDP: |
| 8611 | case PPC::XVSQRTSP: |
| 8612 | case PPC::XVXEXPDP: |
| 8613 | case PPC::XVXEXPSP: |
| 8614 | case PPC::XVXSIGDP: |
| 8615 | case PPC::XVXSIGSP: |
| 8616 | case PPC::XXBRD: |
| 8617 | case PPC::XXBRH: |
| 8618 | case PPC::XXBRQ: |
| 8619 | case PPC::XXBRW: { |
| 8620 | // op: XT |
| 8621 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8622 | Value |= (op & UINT64_C(31)) << 21; |
| 8623 | Value |= (op & UINT64_C(32)) >> 5; |
| 8624 | // op: XB |
| 8625 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8626 | Value |= (op & UINT64_C(31)) << 11; |
| 8627 | Value |= (op & UINT64_C(32)) >> 4; |
| 8628 | break; |
| 8629 | } |
| 8630 | case PPC::XXSPLTW: |
| 8631 | case PPC::XXSPLTWs: { |
| 8632 | // op: XT |
| 8633 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8634 | Value |= (op & UINT64_C(31)) << 21; |
| 8635 | Value |= (op & UINT64_C(32)) >> 5; |
| 8636 | // op: XB |
| 8637 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8638 | Value |= (op & UINT64_C(31)) << 11; |
| 8639 | Value |= (op & UINT64_C(32)) >> 4; |
| 8640 | // op: D |
| 8641 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8642 | op &= UINT64_C(3); |
| 8643 | op <<= 16; |
| 8644 | Value |= op; |
| 8645 | break; |
| 8646 | } |
| 8647 | case PPC::XXEXTRACTUW: { |
| 8648 | // op: XT |
| 8649 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8650 | Value |= (op & UINT64_C(31)) << 21; |
| 8651 | Value |= (op & UINT64_C(32)) >> 5; |
| 8652 | // op: XB |
| 8653 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8654 | Value |= (op & UINT64_C(31)) << 11; |
| 8655 | Value |= (op & UINT64_C(32)) >> 4; |
| 8656 | // op: UIM5 |
| 8657 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8658 | op &= UINT64_C(31); |
| 8659 | op <<= 16; |
| 8660 | Value |= op; |
| 8661 | break; |
| 8662 | } |
| 8663 | case PPC::XXINSERTW: { |
| 8664 | // op: XT |
| 8665 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8666 | Value |= (op & UINT64_C(31)) << 21; |
| 8667 | Value |= (op & UINT64_C(32)) >> 5; |
| 8668 | // op: XB |
| 8669 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8670 | Value |= (op & UINT64_C(31)) << 11; |
| 8671 | Value |= (op & UINT64_C(32)) >> 4; |
| 8672 | // op: UIM5 |
| 8673 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8674 | op &= UINT64_C(31); |
| 8675 | op <<= 16; |
| 8676 | Value |= op; |
| 8677 | break; |
| 8678 | } |
| 8679 | case PPC::MFVRD: |
| 8680 | case PPC::MFVRWZ: |
| 8681 | case PPC::MFVSRD: |
| 8682 | case PPC::MFVSRLD: |
| 8683 | case PPC::MFVSRWZ: { |
| 8684 | // op: XT |
| 8685 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8686 | Value |= (op & UINT64_C(31)) << 21; |
| 8687 | Value |= (op & UINT64_C(32)) >> 5; |
| 8688 | // op: RA |
| 8689 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8690 | op &= UINT64_C(31); |
| 8691 | op <<= 16; |
| 8692 | Value |= op; |
| 8693 | break; |
| 8694 | } |
| 8695 | case PPC::PLXVPonlypc: |
| 8696 | case PPC::PSTXVPonlypc: { |
| 8697 | // op: XTp |
| 8698 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8699 | Value |= (op & UINT64_C(15)) << 22; |
| 8700 | Value |= (op & UINT64_C(16)) << 17; |
| 8701 | // op: D |
| 8702 | op = getImm34EncodingPCRel(MI, OpNo: 1, Fixups, STI); |
| 8703 | Value |= (op & UINT64_C(17179803648)) << 16; |
| 8704 | Value |= (op & UINT64_C(65535)); |
| 8705 | break; |
| 8706 | } |
| 8707 | case PPC::LXVPRL: |
| 8708 | case PPC::LXVPRLL: |
| 8709 | case PPC::LXVPX: |
| 8710 | case PPC::STXVPRL: |
| 8711 | case PPC::STXVPRLL: |
| 8712 | case PPC::STXVPX: { |
| 8713 | // op: XTp |
| 8714 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8715 | Value |= (op & UINT64_C(15)) << 22; |
| 8716 | Value |= (op & UINT64_C(16)) << 17; |
| 8717 | // op: RA |
| 8718 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8719 | op &= UINT64_C(31); |
| 8720 | op <<= 16; |
| 8721 | Value |= op; |
| 8722 | // op: RB |
| 8723 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8724 | op &= UINT64_C(31); |
| 8725 | op <<= 11; |
| 8726 | Value |= op; |
| 8727 | break; |
| 8728 | } |
| 8729 | case PPC::PLXVP: |
| 8730 | case PPC::PLXVPnopc: |
| 8731 | case PPC::PSTXVP: |
| 8732 | case PPC::PSTXVPnopc: { |
| 8733 | // op: XTp |
| 8734 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8735 | Value |= (op & UINT64_C(15)) << 22; |
| 8736 | Value |= (op & UINT64_C(16)) << 17; |
| 8737 | // op: RA |
| 8738 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8739 | op &= UINT64_C(31); |
| 8740 | op <<= 16; |
| 8741 | Value |= op; |
| 8742 | // op: D |
| 8743 | op = getDispRI34Encoding(MI, OpNo: 1, Fixups, STI); |
| 8744 | Value |= (op & UINT64_C(17179803648)) << 16; |
| 8745 | Value |= (op & UINT64_C(65535)); |
| 8746 | break; |
| 8747 | } |
| 8748 | case PPC::PLXVPpc: |
| 8749 | case PPC::PSTXVPpc: { |
| 8750 | // op: XTp |
| 8751 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8752 | Value |= (op & UINT64_C(15)) << 22; |
| 8753 | Value |= (op & UINT64_C(16)) << 17; |
| 8754 | // op: RA |
| 8755 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8756 | op &= UINT64_C(31); |
| 8757 | op <<= 16; |
| 8758 | Value |= op; |
| 8759 | // op: D |
| 8760 | op = getDispRI34PCRelEncoding(MI, OpNo: 1, Fixups, STI); |
| 8761 | Value |= (op & UINT64_C(17179803648)) << 16; |
| 8762 | Value |= (op & UINT64_C(65535)); |
| 8763 | break; |
| 8764 | } |
| 8765 | case PPC::LXVP: |
| 8766 | case PPC::STXVP: { |
| 8767 | // op: XTp |
| 8768 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8769 | Value |= (op & UINT64_C(15)) << 22; |
| 8770 | Value |= (op & UINT64_C(16)) << 17; |
| 8771 | // op: RA |
| 8772 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8773 | op &= UINT64_C(31); |
| 8774 | op <<= 16; |
| 8775 | Value |= op; |
| 8776 | // op: DQ |
| 8777 | op = getDispRIX16Encoding(MI, OpNo: 1, Fixups, STI); |
| 8778 | op &= UINT64_C(4095); |
| 8779 | op <<= 4; |
| 8780 | Value |= op; |
| 8781 | break; |
| 8782 | } |
| 8783 | case PPC::EFDCMPEQ: |
| 8784 | case PPC::EFDCMPGT: |
| 8785 | case PPC::EFDCMPLT: |
| 8786 | case PPC::EFDTSTEQ: |
| 8787 | case PPC::EFDTSTGT: |
| 8788 | case PPC::EFDTSTLT: |
| 8789 | case PPC::EFSCMPEQ: |
| 8790 | case PPC::EFSCMPGT: |
| 8791 | case PPC::EFSCMPLT: |
| 8792 | case PPC::EFSTSTEQ: |
| 8793 | case PPC::EFSTSTGT: |
| 8794 | case PPC::EFSTSTLT: |
| 8795 | case PPC::EVCMPEQ: |
| 8796 | case PPC::EVCMPGTS: |
| 8797 | case PPC::EVCMPGTU: |
| 8798 | case PPC::EVCMPLTS: |
| 8799 | case PPC::EVCMPLTU: |
| 8800 | case PPC::EVFSCMPEQ: |
| 8801 | case PPC::EVFSCMPGT: |
| 8802 | case PPC::EVFSCMPLT: |
| 8803 | case PPC::EVFSTSTEQ: |
| 8804 | case PPC::EVFSTSTGT: |
| 8805 | case PPC::EVFSTSTLT: { |
| 8806 | // op: crD |
| 8807 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8808 | op &= UINT64_C(7); |
| 8809 | op <<= 23; |
| 8810 | Value |= op; |
| 8811 | // op: RA |
| 8812 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8813 | op &= UINT64_C(31); |
| 8814 | op <<= 16; |
| 8815 | Value |= op; |
| 8816 | // op: RB |
| 8817 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8818 | op &= UINT64_C(31); |
| 8819 | op <<= 11; |
| 8820 | Value |= op; |
| 8821 | break; |
| 8822 | } |
| 8823 | case PPC::EVSEL: { |
| 8824 | // op: crD |
| 8825 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8826 | op &= UINT64_C(7); |
| 8827 | Value |= op; |
| 8828 | // op: RA |
| 8829 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8830 | op &= UINT64_C(31); |
| 8831 | op <<= 16; |
| 8832 | Value |= op; |
| 8833 | // op: RB |
| 8834 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8835 | op &= UINT64_C(31); |
| 8836 | op <<= 11; |
| 8837 | Value |= op; |
| 8838 | // op: RT |
| 8839 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8840 | op &= UINT64_C(31); |
| 8841 | op <<= 21; |
| 8842 | Value |= op; |
| 8843 | break; |
| 8844 | } |
| 8845 | default: |
| 8846 | std::string msg; |
| 8847 | raw_string_ostream Msg(msg); |
| 8848 | Msg << "Not supported instr: " << MI; |
| 8849 | report_fatal_error(reason: Msg.str().c_str()); |
| 8850 | } |
| 8851 | return Value; |
| 8852 | } |
| 8853 | |
| 8854 | #ifdef GET_OPERAND_BIT_OFFSET |
| 8855 | #undef GET_OPERAND_BIT_OFFSET |
| 8856 | |
| 8857 | uint32_t PPCMCCodeEmitter::getOperandBitOffset(const MCInst &MI, |
| 8858 | unsigned OpNum, |
| 8859 | const MCSubtargetInfo &STI) const { |
| 8860 | switch (MI.getOpcode()) { |
| 8861 | case PPC::ADDISdtprelHA: |
| 8862 | case PPC::ADDISdtprelHA32: |
| 8863 | case PPC::ADDISgotTprelHA: |
| 8864 | case PPC::ADDIStlsgdHA: |
| 8865 | case PPC::ADDIStlsldHA: |
| 8866 | case PPC::ADDIStocHA: |
| 8867 | case PPC::ADDIStocHA8: |
| 8868 | case PPC::ADDIdtprelL: |
| 8869 | case PPC::ADDIdtprelL32: |
| 8870 | case PPC::ADDItlsgdL: |
| 8871 | case PPC::ADDItlsgdL32: |
| 8872 | case PPC::ADDItlsgdLADDR: |
| 8873 | case PPC::ADDItlsgdLADDR32: |
| 8874 | case PPC::ADDItlsldL: |
| 8875 | case PPC::ADDItlsldL32: |
| 8876 | case PPC::ADDItlsldLADDR: |
| 8877 | case PPC::ADDItlsldLADDR32: |
| 8878 | case PPC::ADDItoc: |
| 8879 | case PPC::ADDItoc8: |
| 8880 | case PPC::ADDItocL: |
| 8881 | case PPC::ADDItocL8: |
| 8882 | case PPC::ADJCALLSTACKDOWN: |
| 8883 | case PPC::ADJCALLSTACKUP: |
| 8884 | case PPC::ANDI_rec_1_EQ_BIT: |
| 8885 | case PPC::ANDI_rec_1_EQ_BIT8: |
| 8886 | case PPC::ANDI_rec_1_GT_BIT: |
| 8887 | case PPC::ANDI_rec_1_GT_BIT8: |
| 8888 | case PPC::ATOMIC_CMP_SWAP_I8: |
| 8889 | case PPC::ATOMIC_CMP_SWAP_I16: |
| 8890 | case PPC::ATOMIC_CMP_SWAP_I32: |
| 8891 | case PPC::ATOMIC_CMP_SWAP_I64: |
| 8892 | case PPC::ATOMIC_LOAD_ADD_I8: |
| 8893 | case PPC::ATOMIC_LOAD_ADD_I16: |
| 8894 | case PPC::ATOMIC_LOAD_ADD_I32: |
| 8895 | case PPC::ATOMIC_LOAD_ADD_I64: |
| 8896 | case PPC::ATOMIC_LOAD_AND_I8: |
| 8897 | case PPC::ATOMIC_LOAD_AND_I16: |
| 8898 | case PPC::ATOMIC_LOAD_AND_I32: |
| 8899 | case PPC::ATOMIC_LOAD_AND_I64: |
| 8900 | case PPC::ATOMIC_LOAD_MAX_I8: |
| 8901 | case PPC::ATOMIC_LOAD_MAX_I16: |
| 8902 | case PPC::ATOMIC_LOAD_MAX_I32: |
| 8903 | case PPC::ATOMIC_LOAD_MAX_I64: |
| 8904 | case PPC::ATOMIC_LOAD_MIN_I8: |
| 8905 | case PPC::ATOMIC_LOAD_MIN_I16: |
| 8906 | case PPC::ATOMIC_LOAD_MIN_I32: |
| 8907 | case PPC::ATOMIC_LOAD_MIN_I64: |
| 8908 | case PPC::ATOMIC_LOAD_NAND_I8: |
| 8909 | case PPC::ATOMIC_LOAD_NAND_I16: |
| 8910 | case PPC::ATOMIC_LOAD_NAND_I32: |
| 8911 | case PPC::ATOMIC_LOAD_NAND_I64: |
| 8912 | case PPC::ATOMIC_LOAD_OR_I8: |
| 8913 | case PPC::ATOMIC_LOAD_OR_I16: |
| 8914 | case PPC::ATOMIC_LOAD_OR_I32: |
| 8915 | case PPC::ATOMIC_LOAD_OR_I64: |
| 8916 | case PPC::ATOMIC_LOAD_SUB_I8: |
| 8917 | case PPC::ATOMIC_LOAD_SUB_I16: |
| 8918 | case PPC::ATOMIC_LOAD_SUB_I32: |
| 8919 | case PPC::ATOMIC_LOAD_SUB_I64: |
| 8920 | case PPC::ATOMIC_LOAD_UMAX_I8: |
| 8921 | case PPC::ATOMIC_LOAD_UMAX_I16: |
| 8922 | case PPC::ATOMIC_LOAD_UMAX_I32: |
| 8923 | case PPC::ATOMIC_LOAD_UMAX_I64: |
| 8924 | case PPC::ATOMIC_LOAD_UMIN_I8: |
| 8925 | case PPC::ATOMIC_LOAD_UMIN_I16: |
| 8926 | case PPC::ATOMIC_LOAD_UMIN_I32: |
| 8927 | case PPC::ATOMIC_LOAD_UMIN_I64: |
| 8928 | case PPC::ATOMIC_LOAD_XOR_I8: |
| 8929 | case PPC::ATOMIC_LOAD_XOR_I16: |
| 8930 | case PPC::ATOMIC_LOAD_XOR_I32: |
| 8931 | case PPC::ATOMIC_LOAD_XOR_I64: |
| 8932 | case PPC::ATOMIC_SWAP_I8: |
| 8933 | case PPC::ATOMIC_SWAP_I16: |
| 8934 | case PPC::ATOMIC_SWAP_I32: |
| 8935 | case PPC::ATOMIC_SWAP_I64: |
| 8936 | case PPC::ATTN: |
| 8937 | case PPC::BCTR: |
| 8938 | case PPC::BCTR8: |
| 8939 | case PPC::BCTRL: |
| 8940 | case PPC::BCTRL8: |
| 8941 | case PPC::BCTRL8_RM: |
| 8942 | case PPC::BCTRL_RM: |
| 8943 | case PPC::BDNZLR: |
| 8944 | case PPC::BDNZLR8: |
| 8945 | case PPC::BDNZLRL: |
| 8946 | case PPC::BDNZLRLm: |
| 8947 | case PPC::BDNZLRLp: |
| 8948 | case PPC::BDNZLRm: |
| 8949 | case PPC::BDNZLRp: |
| 8950 | case PPC::BDZLR: |
| 8951 | case PPC::BDZLR8: |
| 8952 | case PPC::BDZLRL: |
| 8953 | case PPC::BDZLRLm: |
| 8954 | case PPC::BDZLRLp: |
| 8955 | case PPC::BDZLRm: |
| 8956 | case PPC::BDZLRp: |
| 8957 | case PPC::BLR: |
| 8958 | case PPC::BLR8: |
| 8959 | case PPC::BLRL: |
| 8960 | case PPC::CLRBHRB: |
| 8961 | case PPC::CP_ABORT: |
| 8962 | case PPC::CR6SET: |
| 8963 | case PPC::CR6UNSET: |
| 8964 | case PPC::DSSALL: |
| 8965 | case PPC::DYNALLOC: |
| 8966 | case PPC::DYNALLOC8: |
| 8967 | case PPC::DYNAREAOFFSET: |
| 8968 | case PPC::DYNAREAOFFSET8: |
| 8969 | case PPC::DecreaseCTR8loop: |
| 8970 | case PPC::DecreaseCTRloop: |
| 8971 | case PPC::EH_SjLj_LongJmp32: |
| 8972 | case PPC::EH_SjLj_LongJmp64: |
| 8973 | case PPC::EH_SjLj_SetJmp32: |
| 8974 | case PPC::EH_SjLj_SetJmp64: |
| 8975 | case PPC::EH_SjLj_Setup: |
| 8976 | case PPC::EnforceIEIO: |
| 8977 | case PPC::FADDrtz: |
| 8978 | case PPC::FENCE: |
| 8979 | case PPC::GETtlsADDR: |
| 8980 | case PPC::GETtlsADDR32: |
| 8981 | case PPC::GETtlsADDR32AIX: |
| 8982 | case PPC::GETtlsADDR64AIX: |
| 8983 | case PPC::GETtlsADDRPCREL: |
| 8984 | case PPC::GETtlsMOD32AIX: |
| 8985 | case PPC::GETtlsMOD64AIX: |
| 8986 | case PPC::GETtlsTpointer32AIX: |
| 8987 | case PPC::GETtlsldADDR: |
| 8988 | case PPC::GETtlsldADDR32: |
| 8989 | case PPC::GETtlsldADDRPCREL: |
| 8990 | case PPC::HRFID: |
| 8991 | case PPC::ISYNC: |
| 8992 | case PPC::LDgotTprelL: |
| 8993 | case PPC::LDgotTprelL32: |
| 8994 | case PPC::LDtoc: |
| 8995 | case PPC::LDtocBA: |
| 8996 | case PPC::LDtocCPT: |
| 8997 | case PPC::LDtocJTI: |
| 8998 | case PPC::LDtocL: |
| 8999 | case PPC::LQX_PSEUDO: |
| 9000 | case PPC::LWZtoc: |
| 9001 | case PPC::LWZtocL: |
| 9002 | case PPC::MSGSYNC: |
| 9003 | case PPC::MSYNC: |
| 9004 | case PPC::MoveGOTtoLR: |
| 9005 | case PPC::MovePCtoLR: |
| 9006 | case PPC::MovePCtoLR8: |
| 9007 | case PPC::NAP: |
| 9008 | case PPC::NOP: |
| 9009 | case PPC::NOP_GT_PWR6: |
| 9010 | case PPC::NOP_GT_PWR7: |
| 9011 | case PPC::PADDIdtprel: |
| 9012 | case PPC::PPC32GOT: |
| 9013 | case PPC::PPC32PICGOT: |
| 9014 | case PPC::PREPARE_PROBED_ALLOCA_32: |
| 9015 | case PPC::PREPARE_PROBED_ALLOCA_64: |
| 9016 | case PPC::PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32: |
| 9017 | case PPC::PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64: |
| 9018 | case PPC::PROBED_ALLOCA_32: |
| 9019 | case PPC::PROBED_ALLOCA_64: |
| 9020 | case PPC::PROBED_STACKALLOC_32: |
| 9021 | case PPC::PROBED_STACKALLOC_64: |
| 9022 | case PPC::PseudoEIEIO: |
| 9023 | case PPC::RESTORE_ACC: |
| 9024 | case PPC::RESTORE_CR: |
| 9025 | case PPC::RESTORE_CRBIT: |
| 9026 | case PPC::RESTORE_DMR: |
| 9027 | case PPC::RESTORE_DMRP: |
| 9028 | case PPC::RESTORE_QUADWORD: |
| 9029 | case PPC::RESTORE_UACC: |
| 9030 | case PPC::RESTORE_WACC: |
| 9031 | case PPC::RFCI: |
| 9032 | case PPC::RFDI: |
| 9033 | case PPC::RFI: |
| 9034 | case PPC::RFID: |
| 9035 | case PPC::RFMCI: |
| 9036 | case PPC::ReadTB: |
| 9037 | case PPC::SELECT_CC_F4: |
| 9038 | case PPC::SELECT_CC_F8: |
| 9039 | case PPC::SELECT_CC_F16: |
| 9040 | case PPC::SELECT_CC_I4: |
| 9041 | case PPC::SELECT_CC_I8: |
| 9042 | case PPC::SELECT_CC_SPE: |
| 9043 | case PPC::SELECT_CC_SPE4: |
| 9044 | case PPC::SELECT_CC_VRRC: |
| 9045 | case PPC::SELECT_CC_VSFRC: |
| 9046 | case PPC::SELECT_CC_VSRC: |
| 9047 | case PPC::SELECT_CC_VSSRC: |
| 9048 | case PPC::SELECT_F4: |
| 9049 | case PPC::SELECT_F8: |
| 9050 | case PPC::SELECT_F16: |
| 9051 | case PPC::SELECT_I4: |
| 9052 | case PPC::SELECT_I8: |
| 9053 | case PPC::SELECT_SPE: |
| 9054 | case PPC::SELECT_SPE4: |
| 9055 | case PPC::SELECT_VRRC: |
| 9056 | case PPC::SELECT_VSFRC: |
| 9057 | case PPC::SELECT_VSRC: |
| 9058 | case PPC::SELECT_VSSRC: |
| 9059 | case PPC::SETFLM: |
| 9060 | case PPC::SETRND: |
| 9061 | case PPC::SETRNDi: |
| 9062 | case PPC::SLBIA: |
| 9063 | case PPC::SLBSYNC: |
| 9064 | case PPC::SPILL_ACC: |
| 9065 | case PPC::SPILL_CR: |
| 9066 | case PPC::SPILL_CRBIT: |
| 9067 | case PPC::SPILL_DMR: |
| 9068 | case PPC::SPILL_DMRP: |
| 9069 | case PPC::SPILL_QUADWORD: |
| 9070 | case PPC::SPILL_UACC: |
| 9071 | case PPC::SPILL_WACC: |
| 9072 | case PPC::SPLIT_QUADWORD: |
| 9073 | case PPC::STOP: |
| 9074 | case PPC::STQX_PSEUDO: |
| 9075 | case PPC::TAILBCTR: |
| 9076 | case PPC::TAILBCTR8: |
| 9077 | case PPC::TBEGIN_RET: |
| 9078 | case PPC::TCHECK_RET: |
| 9079 | case PPC::TCRETURNai: |
| 9080 | case PPC::TCRETURNai8: |
| 9081 | case PPC::TCRETURNdi: |
| 9082 | case PPC::TCRETURNdi8: |
| 9083 | case PPC::TCRETURNri: |
| 9084 | case PPC::TCRETURNri8: |
| 9085 | case PPC::TLBIA: |
| 9086 | case PPC::TLBRE: |
| 9087 | case PPC::TLBSYNC: |
| 9088 | case PPC::TLBWE: |
| 9089 | case PPC::TLSGDAIX: |
| 9090 | case PPC::TLSGDAIX8: |
| 9091 | case PPC::TLSLDAIX: |
| 9092 | case PPC::TLSLDAIX8: |
| 9093 | case PPC::TRAP: |
| 9094 | case PPC::TRECHKPT: |
| 9095 | case PPC::UNENCODED_NOP: |
| 9096 | case PPC::UpdateGBR: { |
| 9097 | break; |
| 9098 | } |
| 9099 | case PPC::TEND: { |
| 9100 | switch (OpNum) { |
| 9101 | case 0: |
| 9102 | // op: A |
| 9103 | return 25; |
| 9104 | } |
| 9105 | break; |
| 9106 | } |
| 9107 | case PPC::DMMR: { |
| 9108 | switch (OpNum) { |
| 9109 | case 0: |
| 9110 | // op: AT |
| 9111 | return 23; |
| 9112 | case 1: |
| 9113 | // op: AB |
| 9114 | return 13; |
| 9115 | } |
| 9116 | break; |
| 9117 | } |
| 9118 | case PPC::PMXVI4GER8: |
| 9119 | case PPC::PMXVI4GER8W: { |
| 9120 | switch (OpNum) { |
| 9121 | case 0: |
| 9122 | // op: AT |
| 9123 | return 23; |
| 9124 | case 1: |
| 9125 | // op: XA |
| 9126 | return 2; |
| 9127 | case 2: |
| 9128 | // op: XB |
| 9129 | return 1; |
| 9130 | case 3: |
| 9131 | // op: XMSK |
| 9132 | return 36; |
| 9133 | case 4: |
| 9134 | // op: YMSK |
| 9135 | return 32; |
| 9136 | case 5: |
| 9137 | // op: PMSK |
| 9138 | return 40; |
| 9139 | } |
| 9140 | break; |
| 9141 | } |
| 9142 | case PPC::PMXVI8GER4: |
| 9143 | case PPC::PMXVI8GER4W: { |
| 9144 | switch (OpNum) { |
| 9145 | case 0: |
| 9146 | // op: AT |
| 9147 | return 23; |
| 9148 | case 1: |
| 9149 | // op: XA |
| 9150 | return 2; |
| 9151 | case 2: |
| 9152 | // op: XB |
| 9153 | return 1; |
| 9154 | case 3: |
| 9155 | // op: XMSK |
| 9156 | return 36; |
| 9157 | case 4: |
| 9158 | // op: YMSK |
| 9159 | return 32; |
| 9160 | case 5: |
| 9161 | // op: PMSK |
| 9162 | return 44; |
| 9163 | } |
| 9164 | break; |
| 9165 | } |
| 9166 | case PPC::PMXVBF16GER2: |
| 9167 | case PPC::PMXVBF16GER2W: |
| 9168 | case PPC::PMXVF16GER2: |
| 9169 | case PPC::PMXVF16GER2W: |
| 9170 | case PPC::PMXVI16GER2: |
| 9171 | case PPC::PMXVI16GER2S: |
| 9172 | case PPC::PMXVI16GER2SW: |
| 9173 | case PPC::PMXVI16GER2W: { |
| 9174 | switch (OpNum) { |
| 9175 | case 0: |
| 9176 | // op: AT |
| 9177 | return 23; |
| 9178 | case 1: |
| 9179 | // op: XA |
| 9180 | return 2; |
| 9181 | case 2: |
| 9182 | // op: XB |
| 9183 | return 1; |
| 9184 | case 3: |
| 9185 | // op: XMSK |
| 9186 | return 36; |
| 9187 | case 4: |
| 9188 | // op: YMSK |
| 9189 | return 32; |
| 9190 | case 5: |
| 9191 | // op: PMSK |
| 9192 | return 46; |
| 9193 | } |
| 9194 | break; |
| 9195 | } |
| 9196 | case PPC::PMXVF32GER: |
| 9197 | case PPC::PMXVF32GERW: { |
| 9198 | switch (OpNum) { |
| 9199 | case 0: |
| 9200 | // op: AT |
| 9201 | return 23; |
| 9202 | case 1: |
| 9203 | // op: XA |
| 9204 | return 2; |
| 9205 | case 2: |
| 9206 | // op: XB |
| 9207 | return 1; |
| 9208 | case 3: |
| 9209 | // op: XMSK |
| 9210 | return 36; |
| 9211 | case 4: |
| 9212 | // op: YMSK |
| 9213 | return 32; |
| 9214 | } |
| 9215 | break; |
| 9216 | } |
| 9217 | case PPC::PMXVF64GER: |
| 9218 | case PPC::PMXVF64GERW: { |
| 9219 | switch (OpNum) { |
| 9220 | case 0: |
| 9221 | // op: AT |
| 9222 | return 23; |
| 9223 | case 1: |
| 9224 | // op: XA |
| 9225 | return 2; |
| 9226 | case 2: |
| 9227 | // op: XB |
| 9228 | return 1; |
| 9229 | case 3: |
| 9230 | // op: XMSK |
| 9231 | return 36; |
| 9232 | case 4: |
| 9233 | // op: YMSK |
| 9234 | return 34; |
| 9235 | } |
| 9236 | break; |
| 9237 | } |
| 9238 | case PPC::XVBF16GER2: |
| 9239 | case PPC::XVBF16GER2W: |
| 9240 | case PPC::XVF16GER2: |
| 9241 | case PPC::XVF16GER2W: |
| 9242 | case PPC::XVF32GER: |
| 9243 | case PPC::XVF32GERW: |
| 9244 | case PPC::XVF64GER: |
| 9245 | case PPC::XVF64GERW: |
| 9246 | case PPC::XVI4GER8: |
| 9247 | case PPC::XVI4GER8W: |
| 9248 | case PPC::XVI8GER4: |
| 9249 | case PPC::XVI8GER4W: |
| 9250 | case PPC::XVI16GER2: |
| 9251 | case PPC::XVI16GER2S: |
| 9252 | case PPC::XVI16GER2SW: |
| 9253 | case PPC::XVI16GER2W: { |
| 9254 | switch (OpNum) { |
| 9255 | case 0: |
| 9256 | // op: AT |
| 9257 | return 23; |
| 9258 | case 1: |
| 9259 | // op: XA |
| 9260 | return 2; |
| 9261 | case 2: |
| 9262 | // op: XB |
| 9263 | return 1; |
| 9264 | } |
| 9265 | break; |
| 9266 | } |
| 9267 | case PPC::PMDMXVI8GERX4: { |
| 9268 | switch (OpNum) { |
| 9269 | case 0: |
| 9270 | // op: AT |
| 9271 | return 23; |
| 9272 | case 1: |
| 9273 | // op: XAp |
| 9274 | return 2; |
| 9275 | case 2: |
| 9276 | // op: XB |
| 9277 | return 1; |
| 9278 | case 3: |
| 9279 | // op: XMSK |
| 9280 | return 36; |
| 9281 | case 4: |
| 9282 | // op: YMSK |
| 9283 | return 32; |
| 9284 | case 5: |
| 9285 | // op: PMSK |
| 9286 | return 44; |
| 9287 | } |
| 9288 | break; |
| 9289 | } |
| 9290 | case PPC::PMDMXVBF16GERX2: |
| 9291 | case PPC::PMDMXVF16GERX2: { |
| 9292 | switch (OpNum) { |
| 9293 | case 0: |
| 9294 | // op: AT |
| 9295 | return 23; |
| 9296 | case 1: |
| 9297 | // op: XAp |
| 9298 | return 2; |
| 9299 | case 2: |
| 9300 | // op: XB |
| 9301 | return 1; |
| 9302 | case 3: |
| 9303 | // op: XMSK |
| 9304 | return 36; |
| 9305 | case 4: |
| 9306 | // op: YMSK |
| 9307 | return 32; |
| 9308 | case 5: |
| 9309 | // op: PMSK |
| 9310 | return 46; |
| 9311 | } |
| 9312 | break; |
| 9313 | } |
| 9314 | case PPC::DMXVBF16GERX2: |
| 9315 | case PPC::DMXVF16GERX2: |
| 9316 | case PPC::DMXVI8GERX4: { |
| 9317 | switch (OpNum) { |
| 9318 | case 0: |
| 9319 | // op: AT |
| 9320 | return 23; |
| 9321 | case 1: |
| 9322 | // op: XAp |
| 9323 | return 2; |
| 9324 | case 2: |
| 9325 | // op: XB |
| 9326 | return 1; |
| 9327 | } |
| 9328 | break; |
| 9329 | } |
| 9330 | case PPC::DMXXINSTDMR512: |
| 9331 | case PPC::DMXXINSTDMR512_HI: { |
| 9332 | switch (OpNum) { |
| 9333 | case 0: |
| 9334 | // op: AT |
| 9335 | return 23; |
| 9336 | case 1: |
| 9337 | // op: XAp |
| 9338 | return 2; |
| 9339 | case 2: |
| 9340 | // op: XBp |
| 9341 | return 1; |
| 9342 | } |
| 9343 | break; |
| 9344 | } |
| 9345 | case PPC::DMXXINSTDMR256: { |
| 9346 | switch (OpNum) { |
| 9347 | case 0: |
| 9348 | // op: AT |
| 9349 | return 23; |
| 9350 | case 1: |
| 9351 | // op: XBp |
| 9352 | return 1; |
| 9353 | case 2: |
| 9354 | // op: P |
| 9355 | return 11; |
| 9356 | } |
| 9357 | break; |
| 9358 | } |
| 9359 | case PPC::DMSHA2HASH: { |
| 9360 | switch (OpNum) { |
| 9361 | case 0: |
| 9362 | // op: AT |
| 9363 | return 23; |
| 9364 | case 2: |
| 9365 | // op: AB |
| 9366 | return 13; |
| 9367 | case 3: |
| 9368 | // op: T |
| 9369 | return 21; |
| 9370 | } |
| 9371 | break; |
| 9372 | } |
| 9373 | case PPC::DMXOR: { |
| 9374 | switch (OpNum) { |
| 9375 | case 0: |
| 9376 | // op: AT |
| 9377 | return 23; |
| 9378 | case 2: |
| 9379 | // op: AB |
| 9380 | return 13; |
| 9381 | } |
| 9382 | break; |
| 9383 | } |
| 9384 | case PPC::PMXVI4GER8PP: |
| 9385 | case PPC::PMXVI4GER8WPP: { |
| 9386 | switch (OpNum) { |
| 9387 | case 0: |
| 9388 | // op: AT |
| 9389 | return 23; |
| 9390 | case 2: |
| 9391 | // op: XA |
| 9392 | return 2; |
| 9393 | case 3: |
| 9394 | // op: XB |
| 9395 | return 1; |
| 9396 | case 4: |
| 9397 | // op: XMSK |
| 9398 | return 36; |
| 9399 | case 5: |
| 9400 | // op: YMSK |
| 9401 | return 32; |
| 9402 | case 6: |
| 9403 | // op: PMSK |
| 9404 | return 40; |
| 9405 | } |
| 9406 | break; |
| 9407 | } |
| 9408 | case PPC::PMXVI8GER4PP: |
| 9409 | case PPC::PMXVI8GER4SPP: |
| 9410 | case PPC::PMXVI8GER4WPP: |
| 9411 | case PPC::PMXVI8GER4WSPP: { |
| 9412 | switch (OpNum) { |
| 9413 | case 0: |
| 9414 | // op: AT |
| 9415 | return 23; |
| 9416 | case 2: |
| 9417 | // op: XA |
| 9418 | return 2; |
| 9419 | case 3: |
| 9420 | // op: XB |
| 9421 | return 1; |
| 9422 | case 4: |
| 9423 | // op: XMSK |
| 9424 | return 36; |
| 9425 | case 5: |
| 9426 | // op: YMSK |
| 9427 | return 32; |
| 9428 | case 6: |
| 9429 | // op: PMSK |
| 9430 | return 44; |
| 9431 | } |
| 9432 | break; |
| 9433 | } |
| 9434 | case PPC::PMXVBF16GER2NN: |
| 9435 | case PPC::PMXVBF16GER2NP: |
| 9436 | case PPC::PMXVBF16GER2PN: |
| 9437 | case PPC::PMXVBF16GER2PP: |
| 9438 | case PPC::PMXVBF16GER2WNN: |
| 9439 | case PPC::PMXVBF16GER2WNP: |
| 9440 | case PPC::PMXVBF16GER2WPN: |
| 9441 | case PPC::PMXVBF16GER2WPP: |
| 9442 | case PPC::PMXVF16GER2NN: |
| 9443 | case PPC::PMXVF16GER2NP: |
| 9444 | case PPC::PMXVF16GER2PN: |
| 9445 | case PPC::PMXVF16GER2PP: |
| 9446 | case PPC::PMXVF16GER2WNN: |
| 9447 | case PPC::PMXVF16GER2WNP: |
| 9448 | case PPC::PMXVF16GER2WPN: |
| 9449 | case PPC::PMXVF16GER2WPP: |
| 9450 | case PPC::PMXVI16GER2PP: |
| 9451 | case PPC::PMXVI16GER2SPP: |
| 9452 | case PPC::PMXVI16GER2SWPP: |
| 9453 | case PPC::PMXVI16GER2WPP: { |
| 9454 | switch (OpNum) { |
| 9455 | case 0: |
| 9456 | // op: AT |
| 9457 | return 23; |
| 9458 | case 2: |
| 9459 | // op: XA |
| 9460 | return 2; |
| 9461 | case 3: |
| 9462 | // op: XB |
| 9463 | return 1; |
| 9464 | case 4: |
| 9465 | // op: XMSK |
| 9466 | return 36; |
| 9467 | case 5: |
| 9468 | // op: YMSK |
| 9469 | return 32; |
| 9470 | case 6: |
| 9471 | // op: PMSK |
| 9472 | return 46; |
| 9473 | } |
| 9474 | break; |
| 9475 | } |
| 9476 | case PPC::PMXVF32GERNN: |
| 9477 | case PPC::PMXVF32GERNP: |
| 9478 | case PPC::PMXVF32GERPN: |
| 9479 | case PPC::PMXVF32GERPP: |
| 9480 | case PPC::PMXVF32GERWNN: |
| 9481 | case PPC::PMXVF32GERWNP: |
| 9482 | case PPC::PMXVF32GERWPN: |
| 9483 | case PPC::PMXVF32GERWPP: { |
| 9484 | switch (OpNum) { |
| 9485 | case 0: |
| 9486 | // op: AT |
| 9487 | return 23; |
| 9488 | case 2: |
| 9489 | // op: XA |
| 9490 | return 2; |
| 9491 | case 3: |
| 9492 | // op: XB |
| 9493 | return 1; |
| 9494 | case 4: |
| 9495 | // op: XMSK |
| 9496 | return 36; |
| 9497 | case 5: |
| 9498 | // op: YMSK |
| 9499 | return 32; |
| 9500 | } |
| 9501 | break; |
| 9502 | } |
| 9503 | case PPC::PMXVF64GERNN: |
| 9504 | case PPC::PMXVF64GERNP: |
| 9505 | case PPC::PMXVF64GERPN: |
| 9506 | case PPC::PMXVF64GERPP: |
| 9507 | case PPC::PMXVF64GERWNN: |
| 9508 | case PPC::PMXVF64GERWNP: |
| 9509 | case PPC::PMXVF64GERWPN: |
| 9510 | case PPC::PMXVF64GERWPP: { |
| 9511 | switch (OpNum) { |
| 9512 | case 0: |
| 9513 | // op: AT |
| 9514 | return 23; |
| 9515 | case 2: |
| 9516 | // op: XA |
| 9517 | return 2; |
| 9518 | case 3: |
| 9519 | // op: XB |
| 9520 | return 1; |
| 9521 | case 4: |
| 9522 | // op: XMSK |
| 9523 | return 36; |
| 9524 | case 5: |
| 9525 | // op: YMSK |
| 9526 | return 34; |
| 9527 | } |
| 9528 | break; |
| 9529 | } |
| 9530 | case PPC::XVBF16GER2NN: |
| 9531 | case PPC::XVBF16GER2NP: |
| 9532 | case PPC::XVBF16GER2PN: |
| 9533 | case PPC::XVBF16GER2PP: |
| 9534 | case PPC::XVBF16GER2WNN: |
| 9535 | case PPC::XVBF16GER2WNP: |
| 9536 | case PPC::XVBF16GER2WPN: |
| 9537 | case PPC::XVBF16GER2WPP: |
| 9538 | case PPC::XVF16GER2NN: |
| 9539 | case PPC::XVF16GER2NP: |
| 9540 | case PPC::XVF16GER2PN: |
| 9541 | case PPC::XVF16GER2PP: |
| 9542 | case PPC::XVF16GER2WNN: |
| 9543 | case PPC::XVF16GER2WNP: |
| 9544 | case PPC::XVF16GER2WPN: |
| 9545 | case PPC::XVF16GER2WPP: |
| 9546 | case PPC::XVF32GERNN: |
| 9547 | case PPC::XVF32GERNP: |
| 9548 | case PPC::XVF32GERPN: |
| 9549 | case PPC::XVF32GERPP: |
| 9550 | case PPC::XVF32GERWNN: |
| 9551 | case PPC::XVF32GERWNP: |
| 9552 | case PPC::XVF32GERWPN: |
| 9553 | case PPC::XVF32GERWPP: |
| 9554 | case PPC::XVF64GERNN: |
| 9555 | case PPC::XVF64GERNP: |
| 9556 | case PPC::XVF64GERPN: |
| 9557 | case PPC::XVF64GERPP: |
| 9558 | case PPC::XVF64GERWNN: |
| 9559 | case PPC::XVF64GERWNP: |
| 9560 | case PPC::XVF64GERWPN: |
| 9561 | case PPC::XVF64GERWPP: |
| 9562 | case PPC::XVI4GER8PP: |
| 9563 | case PPC::XVI4GER8WPP: |
| 9564 | case PPC::XVI8GER4PP: |
| 9565 | case PPC::XVI8GER4SPP: |
| 9566 | case PPC::XVI8GER4WPP: |
| 9567 | case PPC::XVI8GER4WSPP: |
| 9568 | case PPC::XVI16GER2PP: |
| 9569 | case PPC::XVI16GER2SPP: |
| 9570 | case PPC::XVI16GER2SWPP: |
| 9571 | case PPC::XVI16GER2WPP: { |
| 9572 | switch (OpNum) { |
| 9573 | case 0: |
| 9574 | // op: AT |
| 9575 | return 23; |
| 9576 | case 2: |
| 9577 | // op: XA |
| 9578 | return 2; |
| 9579 | case 3: |
| 9580 | // op: XB |
| 9581 | return 1; |
| 9582 | } |
| 9583 | break; |
| 9584 | } |
| 9585 | case PPC::PMDMXVI8GERX4PP: |
| 9586 | case PPC::PMDMXVI8GERX4SPP: { |
| 9587 | switch (OpNum) { |
| 9588 | case 0: |
| 9589 | // op: AT |
| 9590 | return 23; |
| 9591 | case 2: |
| 9592 | // op: XAp |
| 9593 | return 2; |
| 9594 | case 3: |
| 9595 | // op: XB |
| 9596 | return 1; |
| 9597 | case 4: |
| 9598 | // op: XMSK |
| 9599 | return 36; |
| 9600 | case 5: |
| 9601 | // op: YMSK |
| 9602 | return 32; |
| 9603 | case 6: |
| 9604 | // op: PMSK |
| 9605 | return 44; |
| 9606 | } |
| 9607 | break; |
| 9608 | } |
| 9609 | case PPC::PMDMXVBF16GERX2NN: |
| 9610 | case PPC::PMDMXVBF16GERX2NP: |
| 9611 | case PPC::PMDMXVBF16GERX2PN: |
| 9612 | case PPC::PMDMXVBF16GERX2PP: |
| 9613 | case PPC::PMDMXVF16GERX2NN: |
| 9614 | case PPC::PMDMXVF16GERX2NP: |
| 9615 | case PPC::PMDMXVF16GERX2PN: |
| 9616 | case PPC::PMDMXVF16GERX2PP: { |
| 9617 | switch (OpNum) { |
| 9618 | case 0: |
| 9619 | // op: AT |
| 9620 | return 23; |
| 9621 | case 2: |
| 9622 | // op: XAp |
| 9623 | return 2; |
| 9624 | case 3: |
| 9625 | // op: XB |
| 9626 | return 1; |
| 9627 | case 4: |
| 9628 | // op: XMSK |
| 9629 | return 36; |
| 9630 | case 5: |
| 9631 | // op: YMSK |
| 9632 | return 32; |
| 9633 | case 6: |
| 9634 | // op: PMSK |
| 9635 | return 46; |
| 9636 | } |
| 9637 | break; |
| 9638 | } |
| 9639 | case PPC::DMXVBF16GERX2NN: |
| 9640 | case PPC::DMXVBF16GERX2NP: |
| 9641 | case PPC::DMXVBF16GERX2PN: |
| 9642 | case PPC::DMXVBF16GERX2PP: |
| 9643 | case PPC::DMXVF16GERX2NN: |
| 9644 | case PPC::DMXVF16GERX2NP: |
| 9645 | case PPC::DMXVF16GERX2PN: |
| 9646 | case PPC::DMXVF16GERX2PP: |
| 9647 | case PPC::DMXVI8GERX4PP: |
| 9648 | case PPC::DMXVI8GERX4SPP: { |
| 9649 | switch (OpNum) { |
| 9650 | case 0: |
| 9651 | // op: AT |
| 9652 | return 23; |
| 9653 | case 2: |
| 9654 | // op: XAp |
| 9655 | return 2; |
| 9656 | case 3: |
| 9657 | // op: XB |
| 9658 | return 1; |
| 9659 | } |
| 9660 | break; |
| 9661 | } |
| 9662 | case PPC::DMXXSHAPAD: { |
| 9663 | switch (OpNum) { |
| 9664 | case 0: |
| 9665 | // op: AT |
| 9666 | return 23; |
| 9667 | case 2: |
| 9668 | // op: XB |
| 9669 | return 1; |
| 9670 | case 3: |
| 9671 | // op: ID |
| 9672 | return 19; |
| 9673 | case 4: |
| 9674 | // op: E |
| 9675 | return 18; |
| 9676 | case 5: |
| 9677 | // op: BL |
| 9678 | return 16; |
| 9679 | } |
| 9680 | break; |
| 9681 | } |
| 9682 | case PPC::DMSETDMRZ: |
| 9683 | case PPC::DMXXSETACCZ: |
| 9684 | case PPC::XXMTACC: |
| 9685 | case PPC::XXMTACCW: |
| 9686 | case PPC::XXSETACCZ: { |
| 9687 | switch (OpNum) { |
| 9688 | case 0: |
| 9689 | // op: AT |
| 9690 | return 23; |
| 9691 | } |
| 9692 | break; |
| 9693 | } |
| 9694 | case PPC::DMSHA3HASH: { |
| 9695 | switch (OpNum) { |
| 9696 | case 0: |
| 9697 | // op: ATp |
| 9698 | return 24; |
| 9699 | case 2: |
| 9700 | // op: SR |
| 9701 | return 11; |
| 9702 | } |
| 9703 | break; |
| 9704 | } |
| 9705 | case PPC::BCLalways: |
| 9706 | case PPC::BDNZ: |
| 9707 | case PPC::BDNZ8: |
| 9708 | case PPC::BDNZA: |
| 9709 | case PPC::BDNZAm: |
| 9710 | case PPC::BDNZAp: |
| 9711 | case PPC::BDNZL: |
| 9712 | case PPC::BDNZLA: |
| 9713 | case PPC::BDNZLAm: |
| 9714 | case PPC::BDNZLAp: |
| 9715 | case PPC::BDNZLm: |
| 9716 | case PPC::BDNZLp: |
| 9717 | case PPC::BDNZm: |
| 9718 | case PPC::BDNZp: |
| 9719 | case PPC::BDZ: |
| 9720 | case PPC::BDZ8: |
| 9721 | case PPC::BDZA: |
| 9722 | case PPC::BDZAm: |
| 9723 | case PPC::BDZAp: |
| 9724 | case PPC::BDZL: |
| 9725 | case PPC::BDZLA: |
| 9726 | case PPC::BDZLAm: |
| 9727 | case PPC::BDZLAp: |
| 9728 | case PPC::BDZLm: |
| 9729 | case PPC::BDZLp: |
| 9730 | case PPC::BDZm: |
| 9731 | case PPC::BDZp: { |
| 9732 | switch (OpNum) { |
| 9733 | case 0: |
| 9734 | // op: BD |
| 9735 | return 2; |
| 9736 | } |
| 9737 | break; |
| 9738 | } |
| 9739 | case PPC::MCRF: |
| 9740 | case PPC::MCRFS: { |
| 9741 | switch (OpNum) { |
| 9742 | case 0: |
| 9743 | // op: BF |
| 9744 | return 23; |
| 9745 | case 1: |
| 9746 | // op: BFA |
| 9747 | return 18; |
| 9748 | } |
| 9749 | break; |
| 9750 | } |
| 9751 | case PPC::XSTSTDCQP: { |
| 9752 | switch (OpNum) { |
| 9753 | case 0: |
| 9754 | // op: BF |
| 9755 | return 23; |
| 9756 | case 1: |
| 9757 | // op: DCMX |
| 9758 | return 16; |
| 9759 | case 2: |
| 9760 | // op: VB |
| 9761 | return 11; |
| 9762 | } |
| 9763 | break; |
| 9764 | } |
| 9765 | case PPC::XSTSTDCDP: |
| 9766 | case PPC::XSTSTDCSP: { |
| 9767 | switch (OpNum) { |
| 9768 | case 0: |
| 9769 | // op: BF |
| 9770 | return 23; |
| 9771 | case 1: |
| 9772 | // op: DCMX |
| 9773 | return 16; |
| 9774 | case 2: |
| 9775 | // op: XB |
| 9776 | return 1; |
| 9777 | } |
| 9778 | break; |
| 9779 | } |
| 9780 | case PPC::DTSTDC: |
| 9781 | case PPC::DTSTDCQ: |
| 9782 | case PPC::DTSTDG: |
| 9783 | case PPC::DTSTDGQ: { |
| 9784 | switch (OpNum) { |
| 9785 | case 0: |
| 9786 | // op: BF |
| 9787 | return 23; |
| 9788 | case 1: |
| 9789 | // op: FRA |
| 9790 | return 16; |
| 9791 | case 2: |
| 9792 | // op: DCM |
| 9793 | return 10; |
| 9794 | } |
| 9795 | break; |
| 9796 | } |
| 9797 | case PPC::CMPRB: |
| 9798 | case PPC::CMPRB8: { |
| 9799 | switch (OpNum) { |
| 9800 | case 0: |
| 9801 | // op: BF |
| 9802 | return 23; |
| 9803 | case 1: |
| 9804 | // op: L |
| 9805 | return 21; |
| 9806 | case 2: |
| 9807 | // op: RA |
| 9808 | return 16; |
| 9809 | case 3: |
| 9810 | // op: RB |
| 9811 | return 11; |
| 9812 | } |
| 9813 | break; |
| 9814 | } |
| 9815 | case PPC::CMPDI: |
| 9816 | case PPC::CMPLDI: |
| 9817 | case PPC::CMPLWI: |
| 9818 | case PPC::CMPWI: { |
| 9819 | switch (OpNum) { |
| 9820 | case 0: |
| 9821 | // op: BF |
| 9822 | return 23; |
| 9823 | case 1: |
| 9824 | // op: RA |
| 9825 | return 16; |
| 9826 | case 2: |
| 9827 | // op: D |
| 9828 | return 0; |
| 9829 | } |
| 9830 | break; |
| 9831 | } |
| 9832 | case PPC::CMPD: |
| 9833 | case PPC::CMPEQB: |
| 9834 | case PPC::CMPLD: |
| 9835 | case PPC::CMPLW: |
| 9836 | case PPC::CMPW: |
| 9837 | case PPC::DCMPO: |
| 9838 | case PPC::DCMPOQ: |
| 9839 | case PPC::DCMPU: |
| 9840 | case PPC::DCMPUQ: |
| 9841 | case PPC::DTSTEX: |
| 9842 | case PPC::DTSTEXQ: |
| 9843 | case PPC::DTSTSF: |
| 9844 | case PPC::DTSTSFQ: |
| 9845 | case PPC::FCMPOD: |
| 9846 | case PPC::FCMPOS: |
| 9847 | case PPC::FCMPUD: |
| 9848 | case PPC::FCMPUS: |
| 9849 | case PPC::FTDIV: |
| 9850 | case PPC::XSCMPEXPQP: |
| 9851 | case PPC::XSCMPOQP: |
| 9852 | case PPC::XSCMPUQP: { |
| 9853 | switch (OpNum) { |
| 9854 | case 0: |
| 9855 | // op: BF |
| 9856 | return 23; |
| 9857 | case 1: |
| 9858 | // op: RA |
| 9859 | return 16; |
| 9860 | case 2: |
| 9861 | // op: RB |
| 9862 | return 11; |
| 9863 | } |
| 9864 | break; |
| 9865 | } |
| 9866 | case PPC::FTSQRT: { |
| 9867 | switch (OpNum) { |
| 9868 | case 0: |
| 9869 | // op: BF |
| 9870 | return 23; |
| 9871 | case 1: |
| 9872 | // op: RB |
| 9873 | return 11; |
| 9874 | } |
| 9875 | break; |
| 9876 | } |
| 9877 | case PPC::MTFSFIb: { |
| 9878 | switch (OpNum) { |
| 9879 | case 0: |
| 9880 | // op: BF |
| 9881 | return 23; |
| 9882 | case 1: |
| 9883 | // op: U |
| 9884 | return 12; |
| 9885 | } |
| 9886 | break; |
| 9887 | } |
| 9888 | case PPC::DTSTSFI: |
| 9889 | case PPC::DTSTSFIQ: { |
| 9890 | switch (OpNum) { |
| 9891 | case 0: |
| 9892 | // op: BF |
| 9893 | return 23; |
| 9894 | case 1: |
| 9895 | // op: UIM |
| 9896 | return 16; |
| 9897 | case 2: |
| 9898 | // op: FRB |
| 9899 | return 11; |
| 9900 | } |
| 9901 | break; |
| 9902 | } |
| 9903 | case PPC::VCMPSQ: |
| 9904 | case PPC::VCMPUQ: { |
| 9905 | switch (OpNum) { |
| 9906 | case 0: |
| 9907 | // op: BF |
| 9908 | return 23; |
| 9909 | case 1: |
| 9910 | // op: VA |
| 9911 | return 16; |
| 9912 | case 2: |
| 9913 | // op: VB |
| 9914 | return 11; |
| 9915 | } |
| 9916 | break; |
| 9917 | } |
| 9918 | case PPC::XVTLSBB: { |
| 9919 | switch (OpNum) { |
| 9920 | case 0: |
| 9921 | // op: BF |
| 9922 | return 23; |
| 9923 | case 1: |
| 9924 | // op: XB |
| 9925 | return 1; |
| 9926 | } |
| 9927 | break; |
| 9928 | } |
| 9929 | case PPC::MTFSFI: |
| 9930 | case PPC::MTFSFI_rec: { |
| 9931 | switch (OpNum) { |
| 9932 | case 0: |
| 9933 | // op: BF |
| 9934 | return 23; |
| 9935 | case 2: |
| 9936 | // op: W |
| 9937 | return 16; |
| 9938 | case 1: |
| 9939 | // op: U |
| 9940 | return 12; |
| 9941 | } |
| 9942 | break; |
| 9943 | } |
| 9944 | case PPC::MCRXRX: |
| 9945 | case PPC::TCHECK: { |
| 9946 | switch (OpNum) { |
| 9947 | case 0: |
| 9948 | // op: BF |
| 9949 | return 23; |
| 9950 | } |
| 9951 | break; |
| 9952 | } |
| 9953 | case PPC::BC: |
| 9954 | case PPC::BCL: |
| 9955 | case PPC::BCLn: |
| 9956 | case PPC::BCn: { |
| 9957 | switch (OpNum) { |
| 9958 | case 0: |
| 9959 | // op: BI |
| 9960 | return 16; |
| 9961 | case 1: |
| 9962 | // op: BD |
| 9963 | return 2; |
| 9964 | } |
| 9965 | break; |
| 9966 | } |
| 9967 | case PPC::BCCTR: |
| 9968 | case PPC::BCCTR8: |
| 9969 | case PPC::BCCTR8n: |
| 9970 | case PPC::BCCTRL: |
| 9971 | case PPC::BCCTRL8: |
| 9972 | case PPC::BCCTRL8n: |
| 9973 | case PPC::BCCTRLn: |
| 9974 | case PPC::BCCTRn: |
| 9975 | case PPC::BCLR: |
| 9976 | case PPC::BCLRL: |
| 9977 | case PPC::BCLRLn: |
| 9978 | case PPC::BCLRn: { |
| 9979 | switch (OpNum) { |
| 9980 | case 0: |
| 9981 | // op: BI |
| 9982 | return 16; |
| 9983 | } |
| 9984 | break; |
| 9985 | } |
| 9986 | case PPC::BCC: |
| 9987 | case PPC::BCCA: |
| 9988 | case PPC::BCCL: |
| 9989 | case PPC::BCCLA: |
| 9990 | case PPC::CTRL_DEP: { |
| 9991 | switch (OpNum) { |
| 9992 | case 0: |
| 9993 | // op: BIBO |
| 9994 | return 16; |
| 9995 | case 1: |
| 9996 | // op: CR |
| 9997 | return 18; |
| 9998 | case 2: |
| 9999 | // op: BD |
| 10000 | return 2; |
| 10001 | } |
| 10002 | break; |
| 10003 | } |
| 10004 | case PPC::BCCCTR: |
| 10005 | case PPC::BCCCTR8: |
| 10006 | case PPC::BCCCTRL: |
| 10007 | case PPC::BCCCTRL8: |
| 10008 | case PPC::BCCLR: |
| 10009 | case PPC::BCCLRL: { |
| 10010 | switch (OpNum) { |
| 10011 | case 0: |
| 10012 | // op: BIBO |
| 10013 | return 16; |
| 10014 | case 1: |
| 10015 | // op: CR |
| 10016 | return 18; |
| 10017 | } |
| 10018 | break; |
| 10019 | } |
| 10020 | case PPC::gBC: |
| 10021 | case PPC::gBCA: |
| 10022 | case PPC::gBCL: |
| 10023 | case PPC::gBCLA: { |
| 10024 | switch (OpNum) { |
| 10025 | case 0: |
| 10026 | // op: BO |
| 10027 | return 21; |
| 10028 | case 1: |
| 10029 | // op: BI |
| 10030 | return 16; |
| 10031 | case 2: |
| 10032 | // op: BD |
| 10033 | return 2; |
| 10034 | } |
| 10035 | break; |
| 10036 | } |
| 10037 | case PPC::gBCCTR: |
| 10038 | case PPC::gBCCTRL: |
| 10039 | case PPC::gBCLR: |
| 10040 | case PPC::gBCLRL: { |
| 10041 | switch (OpNum) { |
| 10042 | case 0: |
| 10043 | // op: BO |
| 10044 | return 21; |
| 10045 | case 1: |
| 10046 | // op: BI |
| 10047 | return 16; |
| 10048 | case 2: |
| 10049 | // op: BH |
| 10050 | return 11; |
| 10051 | } |
| 10052 | break; |
| 10053 | } |
| 10054 | case PPC::gBCAat: |
| 10055 | case PPC::gBCLAat: |
| 10056 | case PPC::gBCLat: |
| 10057 | case PPC::gBCat: { |
| 10058 | switch (OpNum) { |
| 10059 | case 0: |
| 10060 | // op: BO |
| 10061 | return 23; |
| 10062 | case 1: |
| 10063 | // op: at |
| 10064 | return 21; |
| 10065 | case 2: |
| 10066 | // op: BI |
| 10067 | return 16; |
| 10068 | case 3: |
| 10069 | // op: BD |
| 10070 | return 2; |
| 10071 | } |
| 10072 | break; |
| 10073 | } |
| 10074 | case PPC::XSCMPEXPDP: |
| 10075 | case PPC::XSCMPODP: |
| 10076 | case PPC::XSCMPUDP: |
| 10077 | case PPC::XSTDIVDP: |
| 10078 | case PPC::XVTDIVDP: |
| 10079 | case PPC::XVTDIVSP: { |
| 10080 | switch (OpNum) { |
| 10081 | case 0: |
| 10082 | // op: CR |
| 10083 | return 23; |
| 10084 | case 1: |
| 10085 | // op: XA |
| 10086 | return 2; |
| 10087 | case 2: |
| 10088 | // op: XB |
| 10089 | return 1; |
| 10090 | } |
| 10091 | break; |
| 10092 | } |
| 10093 | case PPC::XSTSQRTDP: |
| 10094 | case PPC::XVTSQRTDP: |
| 10095 | case PPC::XVTSQRTSP: { |
| 10096 | switch (OpNum) { |
| 10097 | case 0: |
| 10098 | // op: CR |
| 10099 | return 23; |
| 10100 | case 1: |
| 10101 | // op: XB |
| 10102 | return 1; |
| 10103 | } |
| 10104 | break; |
| 10105 | } |
| 10106 | case PPC::CRSET: |
| 10107 | case PPC::CRUNSET: { |
| 10108 | switch (OpNum) { |
| 10109 | case 0: |
| 10110 | // op: CRD |
| 10111 | return 11; |
| 10112 | } |
| 10113 | break; |
| 10114 | } |
| 10115 | case PPC::CRNOT: { |
| 10116 | switch (OpNum) { |
| 10117 | case 0: |
| 10118 | // op: CRD |
| 10119 | return 21; |
| 10120 | case 1: |
| 10121 | // op: CRA |
| 10122 | return 11; |
| 10123 | } |
| 10124 | break; |
| 10125 | } |
| 10126 | case PPC::CRAND: |
| 10127 | case PPC::CRANDC: |
| 10128 | case PPC::CREQV: |
| 10129 | case PPC::CRNAND: |
| 10130 | case PPC::CRNOR: |
| 10131 | case PPC::CROR: |
| 10132 | case PPC::CRORC: |
| 10133 | case PPC::CRXOR: { |
| 10134 | switch (OpNum) { |
| 10135 | case 0: |
| 10136 | // op: CRD |
| 10137 | return 21; |
| 10138 | case 1: |
| 10139 | // op: CRA |
| 10140 | return 16; |
| 10141 | case 2: |
| 10142 | // op: CRB |
| 10143 | return 11; |
| 10144 | } |
| 10145 | break; |
| 10146 | } |
| 10147 | case PPC::ICBLC: |
| 10148 | case PPC::ICBLQ: |
| 10149 | case PPC::ICBT: |
| 10150 | case PPC::ICBTLS: { |
| 10151 | switch (OpNum) { |
| 10152 | case 0: |
| 10153 | // op: CT |
| 10154 | return 21; |
| 10155 | case 1: |
| 10156 | // op: RA |
| 10157 | return 16; |
| 10158 | case 2: |
| 10159 | // op: RB |
| 10160 | return 11; |
| 10161 | } |
| 10162 | break; |
| 10163 | } |
| 10164 | case PPC::WRTEEI: { |
| 10165 | switch (OpNum) { |
| 10166 | case 0: |
| 10167 | // op: E |
| 10168 | return 15; |
| 10169 | } |
| 10170 | break; |
| 10171 | } |
| 10172 | case PPC::MTFSFb: { |
| 10173 | switch (OpNum) { |
| 10174 | case 0: |
| 10175 | // op: FM |
| 10176 | return 17; |
| 10177 | case 1: |
| 10178 | // op: RT |
| 10179 | return 11; |
| 10180 | } |
| 10181 | break; |
| 10182 | } |
| 10183 | case PPC::MTFSB0: |
| 10184 | case PPC::MTFSB1: { |
| 10185 | switch (OpNum) { |
| 10186 | case 0: |
| 10187 | // op: FM |
| 10188 | return 21; |
| 10189 | } |
| 10190 | break; |
| 10191 | } |
| 10192 | case PPC::DQUA: |
| 10193 | case PPC::DQUAQ: |
| 10194 | case PPC::DQUAQ_rec: |
| 10195 | case PPC::DQUA_rec: |
| 10196 | case PPC::DRRND: |
| 10197 | case PPC::DRRNDQ: |
| 10198 | case PPC::DRRNDQ_rec: |
| 10199 | case PPC::DRRND_rec: { |
| 10200 | switch (OpNum) { |
| 10201 | case 0: |
| 10202 | // op: FRT |
| 10203 | return 21; |
| 10204 | case 1: |
| 10205 | // op: FRA |
| 10206 | return 16; |
| 10207 | case 2: |
| 10208 | // op: FRB |
| 10209 | return 11; |
| 10210 | case 3: |
| 10211 | // op: RMC |
| 10212 | return 9; |
| 10213 | } |
| 10214 | break; |
| 10215 | } |
| 10216 | case PPC::FADD: |
| 10217 | case PPC::FADDS: |
| 10218 | case PPC::FADDS_rec: |
| 10219 | case PPC::FADD_rec: |
| 10220 | case PPC::FDIV: |
| 10221 | case PPC::FDIVS: |
| 10222 | case PPC::FDIVS_rec: |
| 10223 | case PPC::FDIV_rec: |
| 10224 | case PPC::FSUB: |
| 10225 | case PPC::FSUBS: |
| 10226 | case PPC::FSUBS_rec: |
| 10227 | case PPC::FSUB_rec: |
| 10228 | case PPC::XSIEXPQP: { |
| 10229 | switch (OpNum) { |
| 10230 | case 0: |
| 10231 | // op: FRT |
| 10232 | return 21; |
| 10233 | case 1: |
| 10234 | // op: FRA |
| 10235 | return 16; |
| 10236 | case 2: |
| 10237 | // op: FRB |
| 10238 | return 11; |
| 10239 | } |
| 10240 | break; |
| 10241 | } |
| 10242 | case PPC::FMADD: |
| 10243 | case PPC::FMADDS: |
| 10244 | case PPC::FMADDS_rec: |
| 10245 | case PPC::FMADD_rec: |
| 10246 | case PPC::FMSUB: |
| 10247 | case PPC::FMSUBS: |
| 10248 | case PPC::FMSUBS_rec: |
| 10249 | case PPC::FMSUB_rec: |
| 10250 | case PPC::FNMADD: |
| 10251 | case PPC::FNMADDS: |
| 10252 | case PPC::FNMADDS_rec: |
| 10253 | case PPC::FNMADD_rec: |
| 10254 | case PPC::FNMSUB: |
| 10255 | case PPC::FNMSUBS: |
| 10256 | case PPC::FNMSUBS_rec: |
| 10257 | case PPC::FNMSUB_rec: |
| 10258 | case PPC::FSELD: |
| 10259 | case PPC::FSELD_rec: |
| 10260 | case PPC::FSELS: |
| 10261 | case PPC::FSELS_rec: { |
| 10262 | switch (OpNum) { |
| 10263 | case 0: |
| 10264 | // op: FRT |
| 10265 | return 21; |
| 10266 | case 1: |
| 10267 | // op: FRA |
| 10268 | return 16; |
| 10269 | case 2: |
| 10270 | // op: FRC |
| 10271 | return 6; |
| 10272 | case 3: |
| 10273 | // op: FRB |
| 10274 | return 11; |
| 10275 | } |
| 10276 | break; |
| 10277 | } |
| 10278 | case PPC::FMUL: |
| 10279 | case PPC::FMULS: |
| 10280 | case PPC::FMULS_rec: |
| 10281 | case PPC::FMUL_rec: { |
| 10282 | switch (OpNum) { |
| 10283 | case 0: |
| 10284 | // op: FRT |
| 10285 | return 21; |
| 10286 | case 1: |
| 10287 | // op: FRA |
| 10288 | return 16; |
| 10289 | case 2: |
| 10290 | // op: FRC |
| 10291 | return 6; |
| 10292 | } |
| 10293 | break; |
| 10294 | } |
| 10295 | case PPC::DSCLI: |
| 10296 | case PPC::DSCLIQ: |
| 10297 | case PPC::DSCLIQ_rec: |
| 10298 | case PPC::DSCLI_rec: |
| 10299 | case PPC::DSCRI: |
| 10300 | case PPC::DSCRIQ: |
| 10301 | case PPC::DSCRIQ_rec: |
| 10302 | case PPC::DSCRI_rec: { |
| 10303 | switch (OpNum) { |
| 10304 | case 0: |
| 10305 | // op: FRT |
| 10306 | return 21; |
| 10307 | case 1: |
| 10308 | // op: FRA |
| 10309 | return 16; |
| 10310 | case 2: |
| 10311 | // op: SH |
| 10312 | return 10; |
| 10313 | } |
| 10314 | break; |
| 10315 | } |
| 10316 | case PPC::DRINTN: |
| 10317 | case PPC::DRINTNQ: |
| 10318 | case PPC::DRINTNQ_rec: |
| 10319 | case PPC::DRINTN_rec: |
| 10320 | case PPC::DRINTX: |
| 10321 | case PPC::DRINTXQ: |
| 10322 | case PPC::DRINTXQ_rec: |
| 10323 | case PPC::DRINTX_rec: { |
| 10324 | switch (OpNum) { |
| 10325 | case 0: |
| 10326 | // op: FRT |
| 10327 | return 21; |
| 10328 | case 1: |
| 10329 | // op: R |
| 10330 | return 16; |
| 10331 | case 2: |
| 10332 | // op: FRB |
| 10333 | return 11; |
| 10334 | case 3: |
| 10335 | // op: RMC |
| 10336 | return 9; |
| 10337 | } |
| 10338 | break; |
| 10339 | } |
| 10340 | case PPC::DQUAI: |
| 10341 | case PPC::DQUAIQ: |
| 10342 | case PPC::DQUAIQ_rec: |
| 10343 | case PPC::DQUAI_rec: { |
| 10344 | switch (OpNum) { |
| 10345 | case 0: |
| 10346 | // op: FRT |
| 10347 | return 21; |
| 10348 | case 2: |
| 10349 | // op: FRB |
| 10350 | return 11; |
| 10351 | case 3: |
| 10352 | // op: RMC |
| 10353 | return 9; |
| 10354 | case 1: |
| 10355 | // op: TE |
| 10356 | return 16; |
| 10357 | } |
| 10358 | break; |
| 10359 | } |
| 10360 | case PPC::MTCRF: |
| 10361 | case PPC::MTCRF8: { |
| 10362 | switch (OpNum) { |
| 10363 | case 0: |
| 10364 | // op: FXM |
| 10365 | return 12; |
| 10366 | case 1: |
| 10367 | // op: RST |
| 10368 | return 21; |
| 10369 | } |
| 10370 | break; |
| 10371 | } |
| 10372 | case PPC::WAITP10: { |
| 10373 | switch (OpNum) { |
| 10374 | case 0: |
| 10375 | // op: L |
| 10376 | return 21; |
| 10377 | case 1: |
| 10378 | // op: PL |
| 10379 | return 16; |
| 10380 | } |
| 10381 | break; |
| 10382 | } |
| 10383 | case PPC::SYNCP10: { |
| 10384 | switch (OpNum) { |
| 10385 | case 0: |
| 10386 | // op: L |
| 10387 | return 21; |
| 10388 | case 1: |
| 10389 | // op: SC |
| 10390 | return 16; |
| 10391 | } |
| 10392 | break; |
| 10393 | } |
| 10394 | case PPC::SYNC: |
| 10395 | case PPC::TSR: |
| 10396 | case PPC::WAIT: { |
| 10397 | switch (OpNum) { |
| 10398 | case 0: |
| 10399 | // op: L |
| 10400 | return 21; |
| 10401 | } |
| 10402 | break; |
| 10403 | } |
| 10404 | case PPC::SC: |
| 10405 | case PPC::SCV: { |
| 10406 | switch (OpNum) { |
| 10407 | case 0: |
| 10408 | // op: LEV |
| 10409 | return 5; |
| 10410 | } |
| 10411 | break; |
| 10412 | } |
| 10413 | case PPC::B: |
| 10414 | case PPC::BA: |
| 10415 | case PPC::BL: |
| 10416 | case PPC::BL8: |
| 10417 | case PPC::BL8_NOTOC: |
| 10418 | case PPC::BL8_NOTOC_RM: |
| 10419 | case PPC::BL8_NOTOC_TLS: |
| 10420 | case PPC::BL8_RM: |
| 10421 | case PPC::BL8_TLS: |
| 10422 | case PPC::BL8_TLS_: |
| 10423 | case PPC::BLA: |
| 10424 | case PPC::BLA8: |
| 10425 | case PPC::BLA8_RM: |
| 10426 | case PPC::BLA_RM: |
| 10427 | case PPC::BL_RM: |
| 10428 | case PPC::BL_TLS: |
| 10429 | case PPC::TAILB: |
| 10430 | case PPC::TAILB8: |
| 10431 | case PPC::TAILBA: |
| 10432 | case PPC::TAILBA8: { |
| 10433 | switch (OpNum) { |
| 10434 | case 0: |
| 10435 | // op: LI |
| 10436 | return 2; |
| 10437 | } |
| 10438 | break; |
| 10439 | } |
| 10440 | case PPC::BL8_NOP: |
| 10441 | case PPC::BL8_NOP_RM: |
| 10442 | case PPC::BL8_NOP_TLS: |
| 10443 | case PPC::BLA8_NOP: |
| 10444 | case PPC::BLA8_NOP_RM: |
| 10445 | case PPC::BL_NOP: |
| 10446 | case PPC::BL_NOP_RM: { |
| 10447 | switch (OpNum) { |
| 10448 | case 0: |
| 10449 | // op: LI |
| 10450 | return 34; |
| 10451 | } |
| 10452 | break; |
| 10453 | } |
| 10454 | case PPC::MBAR: { |
| 10455 | switch (OpNum) { |
| 10456 | case 0: |
| 10457 | // op: MO |
| 10458 | return 21; |
| 10459 | } |
| 10460 | break; |
| 10461 | } |
| 10462 | case PPC::TBEGIN: { |
| 10463 | switch (OpNum) { |
| 10464 | case 0: |
| 10465 | // op: R |
| 10466 | return 21; |
| 10467 | } |
| 10468 | break; |
| 10469 | } |
| 10470 | case PPC::CP_COPY: |
| 10471 | case PPC::CP_COPY8: |
| 10472 | case PPC::DCBA: |
| 10473 | case PPC::DCBFEP: |
| 10474 | case PPC::DCBI: |
| 10475 | case PPC::DCBST: |
| 10476 | case PPC::DCBSTEP: |
| 10477 | case PPC::DCBZ: |
| 10478 | case PPC::DCBZEP: |
| 10479 | case PPC::DCBZL: |
| 10480 | case PPC::DCBZLEP: |
| 10481 | case PPC::DCCCI: |
| 10482 | case PPC::ICBI: |
| 10483 | case PPC::ICBIEP: |
| 10484 | case PPC::ICCCI: |
| 10485 | case PPC::TLBIVAX: |
| 10486 | case PPC::TLBSX: { |
| 10487 | switch (OpNum) { |
| 10488 | case 0: |
| 10489 | // op: RA |
| 10490 | return 16; |
| 10491 | case 1: |
| 10492 | // op: RB |
| 10493 | return 11; |
| 10494 | } |
| 10495 | break; |
| 10496 | } |
| 10497 | case PPC::RLWNM: |
| 10498 | case PPC::RLWNM8: |
| 10499 | case PPC::RLWNM8_rec: |
| 10500 | case PPC::RLWNM_rec: { |
| 10501 | switch (OpNum) { |
| 10502 | case 0: |
| 10503 | // op: RA |
| 10504 | return 16; |
| 10505 | case 1: |
| 10506 | // op: RS |
| 10507 | return 21; |
| 10508 | case 2: |
| 10509 | // op: RB |
| 10510 | return 11; |
| 10511 | case 3: |
| 10512 | // op: MB |
| 10513 | return 6; |
| 10514 | case 4: |
| 10515 | // op: ME |
| 10516 | return 1; |
| 10517 | } |
| 10518 | break; |
| 10519 | } |
| 10520 | case PPC::RLDCL: |
| 10521 | case PPC::RLDCL_rec: |
| 10522 | case PPC::RLDCR: |
| 10523 | case PPC::RLDCR_rec: { |
| 10524 | switch (OpNum) { |
| 10525 | case 0: |
| 10526 | // op: RA |
| 10527 | return 16; |
| 10528 | case 1: |
| 10529 | // op: RS |
| 10530 | return 21; |
| 10531 | case 2: |
| 10532 | // op: RB |
| 10533 | return 11; |
| 10534 | case 3: |
| 10535 | // op: MBE |
| 10536 | return 5; |
| 10537 | } |
| 10538 | break; |
| 10539 | } |
| 10540 | case PPC::RLWINM: |
| 10541 | case PPC::RLWINM8: |
| 10542 | case PPC::RLWINM8_rec: |
| 10543 | case PPC::RLWINM_rec: { |
| 10544 | switch (OpNum) { |
| 10545 | case 0: |
| 10546 | // op: RA |
| 10547 | return 16; |
| 10548 | case 1: |
| 10549 | // op: RS |
| 10550 | return 21; |
| 10551 | case 2: |
| 10552 | // op: SH |
| 10553 | return 11; |
| 10554 | case 3: |
| 10555 | // op: MB |
| 10556 | return 6; |
| 10557 | case 4: |
| 10558 | // op: ME |
| 10559 | return 1; |
| 10560 | } |
| 10561 | break; |
| 10562 | } |
| 10563 | case PPC::RLDIC: |
| 10564 | case PPC::RLDICL: |
| 10565 | case PPC::RLDICL_32: |
| 10566 | case PPC::RLDICL_32_64: |
| 10567 | case PPC::RLDICL_32_rec: |
| 10568 | case PPC::RLDICL_rec: |
| 10569 | case PPC::RLDICR: |
| 10570 | case PPC::RLDICR_32: |
| 10571 | case PPC::RLDICR_rec: |
| 10572 | case PPC::RLDIC_rec: { |
| 10573 | switch (OpNum) { |
| 10574 | case 0: |
| 10575 | // op: RA |
| 10576 | return 16; |
| 10577 | case 1: |
| 10578 | // op: RS |
| 10579 | return 21; |
| 10580 | case 2: |
| 10581 | // op: SH |
| 10582 | return 1; |
| 10583 | case 3: |
| 10584 | // op: MBE |
| 10585 | return 5; |
| 10586 | } |
| 10587 | break; |
| 10588 | } |
| 10589 | case PPC::EXTSWSLI: |
| 10590 | case PPC::EXTSWSLI_32_64: |
| 10591 | case PPC::EXTSWSLI_32_64_rec: |
| 10592 | case PPC::EXTSWSLI_rec: |
| 10593 | case PPC::SRADI: |
| 10594 | case PPC::SRADI_32: |
| 10595 | case PPC::SRADI_rec: { |
| 10596 | switch (OpNum) { |
| 10597 | case 0: |
| 10598 | // op: RA |
| 10599 | return 16; |
| 10600 | case 1: |
| 10601 | // op: RS |
| 10602 | return 21; |
| 10603 | case 2: |
| 10604 | // op: SH |
| 10605 | return 1; |
| 10606 | } |
| 10607 | break; |
| 10608 | } |
| 10609 | case PPC::ANDI8_rec: |
| 10610 | case PPC::ANDIS8_rec: |
| 10611 | case PPC::ANDIS_rec: |
| 10612 | case PPC::ANDI_rec: |
| 10613 | case PPC::ORI: |
| 10614 | case PPC::ORI8: |
| 10615 | case PPC::ORIS: |
| 10616 | case PPC::ORIS8: |
| 10617 | case PPC::XORI: |
| 10618 | case PPC::XORI8: |
| 10619 | case PPC::XORIS: |
| 10620 | case PPC::XORIS8: { |
| 10621 | switch (OpNum) { |
| 10622 | case 0: |
| 10623 | // op: RA |
| 10624 | return 16; |
| 10625 | case 1: |
| 10626 | // op: RST |
| 10627 | return 21; |
| 10628 | case 2: |
| 10629 | // op: D |
| 10630 | return 0; |
| 10631 | } |
| 10632 | break; |
| 10633 | } |
| 10634 | case PPC::AND: |
| 10635 | case PPC::AND8: |
| 10636 | case PPC::AND8_rec: |
| 10637 | case PPC::ANDC: |
| 10638 | case PPC::ANDC8: |
| 10639 | case PPC::ANDC8_rec: |
| 10640 | case PPC::ANDC_rec: |
| 10641 | case PPC::AND_rec: |
| 10642 | case PPC::BPERMD: |
| 10643 | case PPC::CFUGED: |
| 10644 | case PPC::CMPB: |
| 10645 | case PPC::CMPB8: |
| 10646 | case PPC::CNTLZDM: |
| 10647 | case PPC::CNTTZDM: |
| 10648 | case PPC::EQV: |
| 10649 | case PPC::EQV8: |
| 10650 | case PPC::EQV8_rec: |
| 10651 | case PPC::EQV_rec: |
| 10652 | case PPC::NAND: |
| 10653 | case PPC::NAND8: |
| 10654 | case PPC::NAND8_rec: |
| 10655 | case PPC::NAND_rec: |
| 10656 | case PPC::NOR: |
| 10657 | case PPC::NOR8: |
| 10658 | case PPC::NOR8_rec: |
| 10659 | case PPC::NOR_rec: |
| 10660 | case PPC::OR: |
| 10661 | case PPC::OR8: |
| 10662 | case PPC::OR8_rec: |
| 10663 | case PPC::ORC: |
| 10664 | case PPC::ORC8: |
| 10665 | case PPC::ORC8_rec: |
| 10666 | case PPC::ORC_rec: |
| 10667 | case PPC::OR_rec: |
| 10668 | case PPC::PDEPD: |
| 10669 | case PPC::PEXTD: |
| 10670 | case PPC::SLD: |
| 10671 | case PPC::SLD_rec: |
| 10672 | case PPC::SLW: |
| 10673 | case PPC::SLW8: |
| 10674 | case PPC::SLW8_rec: |
| 10675 | case PPC::SLW_rec: |
| 10676 | case PPC::SRAD: |
| 10677 | case PPC::SRAD_rec: |
| 10678 | case PPC::SRAW: |
| 10679 | case PPC::SRAW8: |
| 10680 | case PPC::SRAW8_rec: |
| 10681 | case PPC::SRAWI: |
| 10682 | case PPC::SRAWI8: |
| 10683 | case PPC::SRAWI8_rec: |
| 10684 | case PPC::SRAWI_rec: |
| 10685 | case PPC::SRAW_rec: |
| 10686 | case PPC::SRD: |
| 10687 | case PPC::SRD_rec: |
| 10688 | case PPC::SRW: |
| 10689 | case PPC::SRW8: |
| 10690 | case PPC::SRW8_rec: |
| 10691 | case PPC::SRW_rec: |
| 10692 | case PPC::XOR: |
| 10693 | case PPC::XOR8: |
| 10694 | case PPC::XOR8_rec: |
| 10695 | case PPC::XOR_rec: { |
| 10696 | switch (OpNum) { |
| 10697 | case 0: |
| 10698 | // op: RA |
| 10699 | return 16; |
| 10700 | case 1: |
| 10701 | // op: RST |
| 10702 | return 21; |
| 10703 | case 2: |
| 10704 | // op: RB |
| 10705 | return 11; |
| 10706 | } |
| 10707 | break; |
| 10708 | } |
| 10709 | case PPC::BRD: |
| 10710 | case PPC::BRH: |
| 10711 | case PPC::BRH8: |
| 10712 | case PPC::BRW: |
| 10713 | case PPC::BRW8: |
| 10714 | case PPC::CBCDTD: |
| 10715 | case PPC::CBCDTD8: |
| 10716 | case PPC::CDTBCD: |
| 10717 | case PPC::CDTBCD8: |
| 10718 | case PPC::CNTLZD: |
| 10719 | case PPC::CNTLZD_rec: |
| 10720 | case PPC::CNTLZW: |
| 10721 | case PPC::CNTLZW8: |
| 10722 | case PPC::CNTLZW8_rec: |
| 10723 | case PPC::CNTLZW_rec: |
| 10724 | case PPC::CNTTZD: |
| 10725 | case PPC::CNTTZD_rec: |
| 10726 | case PPC::CNTTZW: |
| 10727 | case PPC::CNTTZW8: |
| 10728 | case PPC::CNTTZW8_rec: |
| 10729 | case PPC::CNTTZW_rec: |
| 10730 | case PPC::EXTSB: |
| 10731 | case PPC::EXTSB8: |
| 10732 | case PPC::EXTSB8_32_64: |
| 10733 | case PPC::EXTSB8_rec: |
| 10734 | case PPC::EXTSB_rec: |
| 10735 | case PPC::EXTSH: |
| 10736 | case PPC::EXTSH8: |
| 10737 | case PPC::EXTSH8_32_64: |
| 10738 | case PPC::EXTSH8_rec: |
| 10739 | case PPC::EXTSH_rec: |
| 10740 | case PPC::EXTSW: |
| 10741 | case PPC::EXTSW_32: |
| 10742 | case PPC::EXTSW_32_64: |
| 10743 | case PPC::EXTSW_32_64_rec: |
| 10744 | case PPC::EXTSW_rec: |
| 10745 | case PPC::POPCNTB: |
| 10746 | case PPC::POPCNTB8: |
| 10747 | case PPC::POPCNTD: |
| 10748 | case PPC::POPCNTW: { |
| 10749 | switch (OpNum) { |
| 10750 | case 0: |
| 10751 | // op: RA |
| 10752 | return 16; |
| 10753 | case 1: |
| 10754 | // op: RST |
| 10755 | return 21; |
| 10756 | } |
| 10757 | break; |
| 10758 | } |
| 10759 | case PPC::RLWIMI: |
| 10760 | case PPC::RLWIMI8: |
| 10761 | case PPC::RLWIMI8_rec: |
| 10762 | case PPC::RLWIMI_rec: { |
| 10763 | switch (OpNum) { |
| 10764 | case 0: |
| 10765 | // op: RA |
| 10766 | return 16; |
| 10767 | case 2: |
| 10768 | // op: RS |
| 10769 | return 21; |
| 10770 | case 3: |
| 10771 | // op: SH |
| 10772 | return 11; |
| 10773 | case 4: |
| 10774 | // op: MB |
| 10775 | return 6; |
| 10776 | case 5: |
| 10777 | // op: ME |
| 10778 | return 1; |
| 10779 | } |
| 10780 | break; |
| 10781 | } |
| 10782 | case PPC::RLDIMI: |
| 10783 | case PPC::RLDIMI_rec: { |
| 10784 | switch (OpNum) { |
| 10785 | case 0: |
| 10786 | // op: RA |
| 10787 | return 16; |
| 10788 | case 2: |
| 10789 | // op: RS |
| 10790 | return 21; |
| 10791 | case 3: |
| 10792 | // op: SH |
| 10793 | return 1; |
| 10794 | case 4: |
| 10795 | // op: MBE |
| 10796 | return 5; |
| 10797 | } |
| 10798 | break; |
| 10799 | } |
| 10800 | case PPC::TABORT: |
| 10801 | case PPC::TRECLAIM: { |
| 10802 | switch (OpNum) { |
| 10803 | case 0: |
| 10804 | // op: RA |
| 10805 | return 16; |
| 10806 | } |
| 10807 | break; |
| 10808 | } |
| 10809 | case PPC::SLBIE: |
| 10810 | case PPC::TLBIEL: |
| 10811 | case PPC::TLBLD: |
| 10812 | case PPC::TLBLI: { |
| 10813 | switch (OpNum) { |
| 10814 | case 0: |
| 10815 | // op: RB |
| 10816 | return 11; |
| 10817 | } |
| 10818 | break; |
| 10819 | } |
| 10820 | case PPC::VCNTMBB: |
| 10821 | case PPC::VCNTMBD: |
| 10822 | case PPC::VCNTMBH: |
| 10823 | case PPC::VCNTMBW: { |
| 10824 | switch (OpNum) { |
| 10825 | case 0: |
| 10826 | // op: RD |
| 10827 | return 21; |
| 10828 | case 1: |
| 10829 | // op: VB |
| 10830 | return 11; |
| 10831 | case 2: |
| 10832 | // op: MP |
| 10833 | return 16; |
| 10834 | } |
| 10835 | break; |
| 10836 | } |
| 10837 | case PPC::VGNB: { |
| 10838 | switch (OpNum) { |
| 10839 | case 0: |
| 10840 | // op: RD |
| 10841 | return 21; |
| 10842 | case 1: |
| 10843 | // op: VB |
| 10844 | return 11; |
| 10845 | case 2: |
| 10846 | // op: N |
| 10847 | return 16; |
| 10848 | } |
| 10849 | break; |
| 10850 | } |
| 10851 | case PPC::MTMSR: |
| 10852 | case PPC::MTMSRD: { |
| 10853 | switch (OpNum) { |
| 10854 | case 0: |
| 10855 | // op: RS |
| 10856 | return 21; |
| 10857 | case 1: |
| 10858 | // op: L |
| 10859 | return 16; |
| 10860 | } |
| 10861 | break; |
| 10862 | } |
| 10863 | case PPC::MFSRIN: |
| 10864 | case PPC::MTSRIN: { |
| 10865 | switch (OpNum) { |
| 10866 | case 0: |
| 10867 | // op: RS |
| 10868 | return 21; |
| 10869 | case 1: |
| 10870 | // op: RB |
| 10871 | return 11; |
| 10872 | } |
| 10873 | break; |
| 10874 | } |
| 10875 | case PPC::MFSR: |
| 10876 | case PPC::MTSR: { |
| 10877 | switch (OpNum) { |
| 10878 | case 0: |
| 10879 | // op: RS |
| 10880 | return 21; |
| 10881 | case 1: |
| 10882 | // op: SR |
| 10883 | return 16; |
| 10884 | } |
| 10885 | break; |
| 10886 | } |
| 10887 | case PPC::WRTEE: { |
| 10888 | switch (OpNum) { |
| 10889 | case 0: |
| 10890 | // op: RS |
| 10891 | return 21; |
| 10892 | } |
| 10893 | break; |
| 10894 | } |
| 10895 | case PPC::SETBC: |
| 10896 | case PPC::SETBC8: |
| 10897 | case PPC::SETBCR: |
| 10898 | case PPC::SETBCR8: |
| 10899 | case PPC::SETNBC: |
| 10900 | case PPC::SETNBC8: |
| 10901 | case PPC::SETNBCR: |
| 10902 | case PPC::SETNBCR8: { |
| 10903 | switch (OpNum) { |
| 10904 | case 0: |
| 10905 | // op: RST |
| 10906 | return 21; |
| 10907 | case 1: |
| 10908 | // op: BI |
| 10909 | return 16; |
| 10910 | } |
| 10911 | break; |
| 10912 | } |
| 10913 | case PPC::LI: |
| 10914 | case PPC::LI8: |
| 10915 | case PPC::LIS: |
| 10916 | case PPC::LIS8: |
| 10917 | case PPC::PLBZ8onlypc: |
| 10918 | case PPC::PLBZonlypc: |
| 10919 | case PPC::PLDonlypc: |
| 10920 | case PPC::PLFDonlypc: |
| 10921 | case PPC::PLFSonlypc: |
| 10922 | case PPC::PLHA8onlypc: |
| 10923 | case PPC::PLHAonlypc: |
| 10924 | case PPC::PLHZ8onlypc: |
| 10925 | case PPC::PLHZonlypc: |
| 10926 | case PPC::PLWA8onlypc: |
| 10927 | case PPC::PLWAonlypc: |
| 10928 | case PPC::PLWZ8onlypc: |
| 10929 | case PPC::PLWZonlypc: |
| 10930 | case PPC::PLXSDonlypc: |
| 10931 | case PPC::PLXSSPonlypc: |
| 10932 | case PPC::PSTB8onlypc: |
| 10933 | case PPC::PSTBonlypc: |
| 10934 | case PPC::PSTDonlypc: |
| 10935 | case PPC::PSTFDonlypc: |
| 10936 | case PPC::PSTFSonlypc: |
| 10937 | case PPC::PSTH8onlypc: |
| 10938 | case PPC::PSTHonlypc: |
| 10939 | case PPC::PSTW8onlypc: |
| 10940 | case PPC::PSTWonlypc: |
| 10941 | case PPC::PSTXSDonlypc: |
| 10942 | case PPC::PSTXSSPonlypc: { |
| 10943 | switch (OpNum) { |
| 10944 | case 0: |
| 10945 | // op: RST |
| 10946 | return 21; |
| 10947 | case 1: |
| 10948 | // op: D |
| 10949 | return 0; |
| 10950 | } |
| 10951 | break; |
| 10952 | } |
| 10953 | case PPC::MFFSCDRNI: { |
| 10954 | switch (OpNum) { |
| 10955 | case 0: |
| 10956 | // op: RST |
| 10957 | return 21; |
| 10958 | case 1: |
| 10959 | // op: DRM |
| 10960 | return 11; |
| 10961 | } |
| 10962 | break; |
| 10963 | } |
| 10964 | case PPC::MFFSCDRN: |
| 10965 | case PPC::MFFSCRN: { |
| 10966 | switch (OpNum) { |
| 10967 | case 0: |
| 10968 | // op: RST |
| 10969 | return 21; |
| 10970 | case 1: |
| 10971 | // op: FRB |
| 10972 | return 11; |
| 10973 | } |
| 10974 | break; |
| 10975 | } |
| 10976 | case PPC::MFOCRF: |
| 10977 | case PPC::MFOCRF8: { |
| 10978 | switch (OpNum) { |
| 10979 | case 0: |
| 10980 | // op: RST |
| 10981 | return 21; |
| 10982 | case 1: |
| 10983 | // op: FXM |
| 10984 | return 12; |
| 10985 | } |
| 10986 | break; |
| 10987 | } |
| 10988 | case PPC::ADDI: |
| 10989 | case PPC::ADDI8: |
| 10990 | case PPC::ADDIC: |
| 10991 | case PPC::ADDIC8: |
| 10992 | case PPC::ADDIC_rec: |
| 10993 | case PPC::ADDIS: |
| 10994 | case PPC::ADDIS8: |
| 10995 | case PPC::LA: |
| 10996 | case PPC::LA8: |
| 10997 | case PPC::MULLI: |
| 10998 | case PPC::MULLI8: |
| 10999 | case PPC::SUBFIC: |
| 11000 | case PPC::SUBFIC8: |
| 11001 | case PPC::TDI: |
| 11002 | case PPC::TWI: { |
| 11003 | switch (OpNum) { |
| 11004 | case 0: |
| 11005 | // op: RST |
| 11006 | return 21; |
| 11007 | case 1: |
| 11008 | // op: RA |
| 11009 | return 16; |
| 11010 | case 2: |
| 11011 | // op: D |
| 11012 | return 0; |
| 11013 | } |
| 11014 | break; |
| 11015 | } |
| 11016 | case PPC::DADD: |
| 11017 | case PPC::DADDQ: |
| 11018 | case PPC::DADDQ_rec: |
| 11019 | case PPC::DADD_rec: |
| 11020 | case PPC::DDIV: |
| 11021 | case PPC::DDIVQ: |
| 11022 | case PPC::DDIVQ_rec: |
| 11023 | case PPC::DDIV_rec: |
| 11024 | case PPC::DIEX: |
| 11025 | case PPC::DIEXQ: |
| 11026 | case PPC::DIEXQ_rec: |
| 11027 | case PPC::DIEX_rec: |
| 11028 | case PPC::DMUL: |
| 11029 | case PPC::DMULQ: |
| 11030 | case PPC::DMULQ_rec: |
| 11031 | case PPC::DMUL_rec: |
| 11032 | case PPC::DSUB: |
| 11033 | case PPC::DSUBQ: |
| 11034 | case PPC::DSUBQ_rec: |
| 11035 | case PPC::DSUB_rec: |
| 11036 | case PPC::FCPSGND: |
| 11037 | case PPC::FCPSGND_rec: |
| 11038 | case PPC::FCPSGNS: |
| 11039 | case PPC::FCPSGNS_rec: |
| 11040 | case PPC::LBARX: |
| 11041 | case PPC::LBARXL: |
| 11042 | case PPC::LBEPX: |
| 11043 | case PPC::LBZCIX: |
| 11044 | case PPC::LBZX: |
| 11045 | case PPC::LBZX8: |
| 11046 | case PPC::LBZXTLS: |
| 11047 | case PPC::LBZXTLS_: |
| 11048 | case PPC::LBZXTLS_32: |
| 11049 | case PPC::LDARX: |
| 11050 | case PPC::LDARXL: |
| 11051 | case PPC::LDAT: |
| 11052 | case PPC::LDBRX: |
| 11053 | case PPC::LDCIX: |
| 11054 | case PPC::LDX: |
| 11055 | case PPC::LDXTLS: |
| 11056 | case PPC::LDXTLS_: |
| 11057 | case PPC::LFDEPX: |
| 11058 | case PPC::LFDX: |
| 11059 | case PPC::LFDXTLS: |
| 11060 | case PPC::LFDXTLS_: |
| 11061 | case PPC::LFIWAX: |
| 11062 | case PPC::LFIWZX: |
| 11063 | case PPC::LFSX: |
| 11064 | case PPC::LFSXTLS: |
| 11065 | case PPC::LFSXTLS_: |
| 11066 | case PPC::LHARX: |
| 11067 | case PPC::LHARXL: |
| 11068 | case PPC::LHAX: |
| 11069 | case PPC::LHAX8: |
| 11070 | case PPC::LHAXTLS: |
| 11071 | case PPC::LHAXTLS_: |
| 11072 | case PPC::LHAXTLS_32: |
| 11073 | case PPC::LHBRX: |
| 11074 | case PPC::LHBRX8: |
| 11075 | case PPC::LHEPX: |
| 11076 | case PPC::LHZCIX: |
| 11077 | case PPC::LHZX: |
| 11078 | case PPC::LHZX8: |
| 11079 | case PPC::LHZXTLS: |
| 11080 | case PPC::LHZXTLS_: |
| 11081 | case PPC::LHZXTLS_32: |
| 11082 | case PPC::LQARX: |
| 11083 | case PPC::LQARXL: |
| 11084 | case PPC::LSWI: |
| 11085 | case PPC::LVEBX: |
| 11086 | case PPC::LVEHX: |
| 11087 | case PPC::LVEWX: |
| 11088 | case PPC::LVSL: |
| 11089 | case PPC::LVSR: |
| 11090 | case PPC::LVX: |
| 11091 | case PPC::LVXL: |
| 11092 | case PPC::LWARX: |
| 11093 | case PPC::LWARXL: |
| 11094 | case PPC::LWAT: |
| 11095 | case PPC::LWAX: |
| 11096 | case PPC::LWAXTLS: |
| 11097 | case PPC::LWAXTLS_: |
| 11098 | case PPC::LWAXTLS_32: |
| 11099 | case PPC::LWAX_32: |
| 11100 | case PPC::LWBRX: |
| 11101 | case PPC::LWBRX8: |
| 11102 | case PPC::LWEPX: |
| 11103 | case PPC::LWZCIX: |
| 11104 | case PPC::LWZX: |
| 11105 | case PPC::LWZX8: |
| 11106 | case PPC::LWZXTLS: |
| 11107 | case PPC::LWZXTLS_: |
| 11108 | case PPC::LWZXTLS_32: |
| 11109 | case PPC::MODSD: |
| 11110 | case PPC::MODSW: |
| 11111 | case PPC::MODUD: |
| 11112 | case PPC::MODUW: |
| 11113 | case PPC::SPELWZX: |
| 11114 | case PPC::SPESTWX: |
| 11115 | case PPC::STBCIX: |
| 11116 | case PPC::STBCX: |
| 11117 | case PPC::STBEPX: |
| 11118 | case PPC::STBX: |
| 11119 | case PPC::STBX8: |
| 11120 | case PPC::STBXTLS: |
| 11121 | case PPC::STBXTLS_: |
| 11122 | case PPC::STBXTLS_32: |
| 11123 | case PPC::STDAT: |
| 11124 | case PPC::STDBRX: |
| 11125 | case PPC::STDCIX: |
| 11126 | case PPC::STDCX: |
| 11127 | case PPC::STDX: |
| 11128 | case PPC::STDXTLS: |
| 11129 | case PPC::STDXTLS_: |
| 11130 | case PPC::STFDEPX: |
| 11131 | case PPC::STFDX: |
| 11132 | case PPC::STFDXTLS: |
| 11133 | case PPC::STFDXTLS_: |
| 11134 | case PPC::STFIWX: |
| 11135 | case PPC::STFSX: |
| 11136 | case PPC::STFSXTLS: |
| 11137 | case PPC::STFSXTLS_: |
| 11138 | case PPC::STHBRX: |
| 11139 | case PPC::STHCIX: |
| 11140 | case PPC::STHCX: |
| 11141 | case PPC::STHEPX: |
| 11142 | case PPC::STHX: |
| 11143 | case PPC::STHX8: |
| 11144 | case PPC::STHXTLS: |
| 11145 | case PPC::STHXTLS_: |
| 11146 | case PPC::STHXTLS_32: |
| 11147 | case PPC::STQCX: |
| 11148 | case PPC::STSWI: |
| 11149 | case PPC::STVEBX: |
| 11150 | case PPC::STVEHX: |
| 11151 | case PPC::STVEWX: |
| 11152 | case PPC::STVX: |
| 11153 | case PPC::STVXL: |
| 11154 | case PPC::STWAT: |
| 11155 | case PPC::STWBRX: |
| 11156 | case PPC::STWCIX: |
| 11157 | case PPC::STWCX: |
| 11158 | case PPC::STWEPX: |
| 11159 | case PPC::STWX: |
| 11160 | case PPC::STWX8: |
| 11161 | case PPC::STWXTLS: |
| 11162 | case PPC::STWXTLS_: |
| 11163 | case PPC::STWXTLS_32: |
| 11164 | case PPC::TABORTDC: |
| 11165 | case PPC::TABORTDCI: |
| 11166 | case PPC::TABORTWC: |
| 11167 | case PPC::TABORTWCI: |
| 11168 | case PPC::TD: |
| 11169 | case PPC::TLBSX2: |
| 11170 | case PPC::TLBSX2D: |
| 11171 | case PPC::TW: |
| 11172 | case PPC::XSADDQP: |
| 11173 | case PPC::XSADDQPO: |
| 11174 | case PPC::XSCMPEQQP: |
| 11175 | case PPC::XSCMPGEQP: |
| 11176 | case PPC::XSCMPGTQP: |
| 11177 | case PPC::XSCPSGNQP: |
| 11178 | case PPC::XSDIVQP: |
| 11179 | case PPC::XSDIVQPO: |
| 11180 | case PPC::XSMAXCQP: |
| 11181 | case PPC::XSMINCQP: |
| 11182 | case PPC::XSMULQP: |
| 11183 | case PPC::XSMULQPO: |
| 11184 | case PPC::XSSUBQP: |
| 11185 | case PPC::XSSUBQPO: { |
| 11186 | switch (OpNum) { |
| 11187 | case 0: |
| 11188 | // op: RST |
| 11189 | return 21; |
| 11190 | case 1: |
| 11191 | // op: RA |
| 11192 | return 16; |
| 11193 | case 2: |
| 11194 | // op: RB |
| 11195 | return 11; |
| 11196 | } |
| 11197 | break; |
| 11198 | } |
| 11199 | case PPC::TLBRE2: |
| 11200 | case PPC::TLBWE2: { |
| 11201 | switch (OpNum) { |
| 11202 | case 0: |
| 11203 | // op: RST |
| 11204 | return 21; |
| 11205 | case 1: |
| 11206 | // op: RA |
| 11207 | return 16; |
| 11208 | case 2: |
| 11209 | // op: WS |
| 11210 | return 11; |
| 11211 | } |
| 11212 | break; |
| 11213 | } |
| 11214 | case PPC::DCFFIX: |
| 11215 | case PPC::DCFFIXQ: |
| 11216 | case PPC::DCFFIXQQ: |
| 11217 | case PPC::DCFFIXQ_rec: |
| 11218 | case PPC::DCFFIX_rec: |
| 11219 | case PPC::DCTDP: |
| 11220 | case PPC::DCTDP_rec: |
| 11221 | case PPC::DCTFIX: |
| 11222 | case PPC::DCTFIXQ: |
| 11223 | case PPC::DCTFIXQQ: |
| 11224 | case PPC::DCTFIXQ_rec: |
| 11225 | case PPC::DCTFIX_rec: |
| 11226 | case PPC::DCTQPQ: |
| 11227 | case PPC::DCTQPQ_rec: |
| 11228 | case PPC::DRDPQ: |
| 11229 | case PPC::DRDPQ_rec: |
| 11230 | case PPC::DRSP: |
| 11231 | case PPC::DRSP_rec: |
| 11232 | case PPC::DXEX: |
| 11233 | case PPC::DXEXQ: |
| 11234 | case PPC::DXEXQ_rec: |
| 11235 | case PPC::DXEX_rec: |
| 11236 | case PPC::FABSD: |
| 11237 | case PPC::FABSD_rec: |
| 11238 | case PPC::FABSS: |
| 11239 | case PPC::FABSS_rec: |
| 11240 | case PPC::FCFID: |
| 11241 | case PPC::FCFIDS: |
| 11242 | case PPC::FCFIDS_rec: |
| 11243 | case PPC::FCFIDU: |
| 11244 | case PPC::FCFIDUS: |
| 11245 | case PPC::FCFIDUS_rec: |
| 11246 | case PPC::FCFIDU_rec: |
| 11247 | case PPC::FCFID_rec: |
| 11248 | case PPC::FCTID: |
| 11249 | case PPC::FCTIDU: |
| 11250 | case PPC::FCTIDUZ: |
| 11251 | case PPC::FCTIDUZ_rec: |
| 11252 | case PPC::FCTIDU_rec: |
| 11253 | case PPC::FCTIDZ: |
| 11254 | case PPC::FCTIDZ_rec: |
| 11255 | case PPC::FCTID_rec: |
| 11256 | case PPC::FCTIW: |
| 11257 | case PPC::FCTIWU: |
| 11258 | case PPC::FCTIWUZ: |
| 11259 | case PPC::FCTIWUZ_rec: |
| 11260 | case PPC::FCTIWU_rec: |
| 11261 | case PPC::FCTIWZ: |
| 11262 | case PPC::FCTIWZ_rec: |
| 11263 | case PPC::FCTIW_rec: |
| 11264 | case PPC::FMR: |
| 11265 | case PPC::FMR_rec: |
| 11266 | case PPC::FNABSD: |
| 11267 | case PPC::FNABSD_rec: |
| 11268 | case PPC::FNABSS: |
| 11269 | case PPC::FNABSS_rec: |
| 11270 | case PPC::FNEGD: |
| 11271 | case PPC::FNEGD_rec: |
| 11272 | case PPC::FNEGS: |
| 11273 | case PPC::FNEGS_rec: |
| 11274 | case PPC::FRE: |
| 11275 | case PPC::FRES: |
| 11276 | case PPC::FRES_rec: |
| 11277 | case PPC::FRE_rec: |
| 11278 | case PPC::FRIMD: |
| 11279 | case PPC::FRIMD_rec: |
| 11280 | case PPC::FRIMS: |
| 11281 | case PPC::FRIMS_rec: |
| 11282 | case PPC::FRIND: |
| 11283 | case PPC::FRIND_rec: |
| 11284 | case PPC::FRINS: |
| 11285 | case PPC::FRINS_rec: |
| 11286 | case PPC::FRIPD: |
| 11287 | case PPC::FRIPD_rec: |
| 11288 | case PPC::FRIPS: |
| 11289 | case PPC::FRIPS_rec: |
| 11290 | case PPC::FRIZD: |
| 11291 | case PPC::FRIZD_rec: |
| 11292 | case PPC::FRIZS: |
| 11293 | case PPC::FRIZS_rec: |
| 11294 | case PPC::FRSP: |
| 11295 | case PPC::FRSP_rec: |
| 11296 | case PPC::FRSQRTE: |
| 11297 | case PPC::FRSQRTES: |
| 11298 | case PPC::FRSQRTES_rec: |
| 11299 | case PPC::FRSQRTE_rec: |
| 11300 | case PPC::FSQRT: |
| 11301 | case PPC::FSQRTS: |
| 11302 | case PPC::FSQRTS_rec: |
| 11303 | case PPC::FSQRT_rec: |
| 11304 | case PPC::SLBFEE_rec: |
| 11305 | case PPC::SLBIEG: |
| 11306 | case PPC::SLBMFEE: |
| 11307 | case PPC::SLBMTE: |
| 11308 | case PPC::TLBIE: |
| 11309 | case PPC::XSABSQP: |
| 11310 | case PPC::XSCVDPQP: |
| 11311 | case PPC::XSCVQPDP: |
| 11312 | case PPC::XSCVQPDPO: |
| 11313 | case PPC::XSCVQPSDZ: |
| 11314 | case PPC::XSCVQPSQZ: |
| 11315 | case PPC::XSCVQPSWZ: |
| 11316 | case PPC::XSCVQPUDZ: |
| 11317 | case PPC::XSCVQPUQZ: |
| 11318 | case PPC::XSCVQPUWZ: |
| 11319 | case PPC::XSCVSDQP: |
| 11320 | case PPC::XSCVSQQP: |
| 11321 | case PPC::XSCVUDQP: |
| 11322 | case PPC::XSCVUQQP: |
| 11323 | case PPC::XSNABSQP: |
| 11324 | case PPC::XSNEGQP: |
| 11325 | case PPC::XSSQRTQP: |
| 11326 | case PPC::XSSQRTQPO: |
| 11327 | case PPC::XSXEXPQP: |
| 11328 | case PPC::XSXSIGQP: { |
| 11329 | switch (OpNum) { |
| 11330 | case 0: |
| 11331 | // op: RST |
| 11332 | return 21; |
| 11333 | case 1: |
| 11334 | // op: RB |
| 11335 | return 11; |
| 11336 | } |
| 11337 | break; |
| 11338 | } |
| 11339 | case PPC::MFFSCRNI: { |
| 11340 | switch (OpNum) { |
| 11341 | case 0: |
| 11342 | // op: RST |
| 11343 | return 21; |
| 11344 | case 1: |
| 11345 | // op: RM |
| 11346 | return 11; |
| 11347 | } |
| 11348 | break; |
| 11349 | } |
| 11350 | case PPC::MFDCR: |
| 11351 | case PPC::MFPMR: |
| 11352 | case PPC::MFSPR: |
| 11353 | case PPC::MFSPR8: |
| 11354 | case PPC::MFTB: |
| 11355 | case PPC::MTDCR: { |
| 11356 | switch (OpNum) { |
| 11357 | case 0: |
| 11358 | // op: RST |
| 11359 | return 21; |
| 11360 | case 1: |
| 11361 | // op: SPR |
| 11362 | return 11; |
| 11363 | } |
| 11364 | break; |
| 11365 | } |
| 11366 | case PPC::LBZ: |
| 11367 | case PPC::LBZ8: |
| 11368 | case PPC::LFD: |
| 11369 | case PPC::LFS: |
| 11370 | case PPC::LHA: |
| 11371 | case PPC::LHA8: |
| 11372 | case PPC::LHZ: |
| 11373 | case PPC::LHZ8: |
| 11374 | case PPC::LMW: |
| 11375 | case PPC::LWZ: |
| 11376 | case PPC::LWZ8: |
| 11377 | case PPC::PLBZ: |
| 11378 | case PPC::PLBZ8: |
| 11379 | case PPC::PLBZ8nopc: |
| 11380 | case PPC::PLBZ8pc: |
| 11381 | case PPC::PLBZnopc: |
| 11382 | case PPC::PLBZpc: |
| 11383 | case PPC::PLD: |
| 11384 | case PPC::PLDnopc: |
| 11385 | case PPC::PLDpc: |
| 11386 | case PPC::PLFD: |
| 11387 | case PPC::PLFDnopc: |
| 11388 | case PPC::PLFDpc: |
| 11389 | case PPC::PLFS: |
| 11390 | case PPC::PLFSnopc: |
| 11391 | case PPC::PLFSpc: |
| 11392 | case PPC::PLHA: |
| 11393 | case PPC::PLHA8: |
| 11394 | case PPC::PLHA8nopc: |
| 11395 | case PPC::PLHA8pc: |
| 11396 | case PPC::PLHAnopc: |
| 11397 | case PPC::PLHApc: |
| 11398 | case PPC::PLHZ: |
| 11399 | case PPC::PLHZ8: |
| 11400 | case PPC::PLHZ8nopc: |
| 11401 | case PPC::PLHZ8pc: |
| 11402 | case PPC::PLHZnopc: |
| 11403 | case PPC::PLHZpc: |
| 11404 | case PPC::PLWA: |
| 11405 | case PPC::PLWA8: |
| 11406 | case PPC::PLWA8nopc: |
| 11407 | case PPC::PLWA8pc: |
| 11408 | case PPC::PLWAnopc: |
| 11409 | case PPC::PLWApc: |
| 11410 | case PPC::PLWZ: |
| 11411 | case PPC::PLWZ8: |
| 11412 | case PPC::PLWZ8nopc: |
| 11413 | case PPC::PLWZ8pc: |
| 11414 | case PPC::PLWZnopc: |
| 11415 | case PPC::PLWZpc: |
| 11416 | case PPC::PLXSD: |
| 11417 | case PPC::PLXSDnopc: |
| 11418 | case PPC::PLXSDpc: |
| 11419 | case PPC::PLXSSP: |
| 11420 | case PPC::PLXSSPnopc: |
| 11421 | case PPC::PLXSSPpc: |
| 11422 | case PPC::PSTB: |
| 11423 | case PPC::PSTB8: |
| 11424 | case PPC::PSTB8nopc: |
| 11425 | case PPC::PSTB8pc: |
| 11426 | case PPC::PSTBnopc: |
| 11427 | case PPC::PSTBpc: |
| 11428 | case PPC::PSTD: |
| 11429 | case PPC::PSTDnopc: |
| 11430 | case PPC::PSTDpc: |
| 11431 | case PPC::PSTFD: |
| 11432 | case PPC::PSTFDnopc: |
| 11433 | case PPC::PSTFDpc: |
| 11434 | case PPC::PSTFS: |
| 11435 | case PPC::PSTFSnopc: |
| 11436 | case PPC::PSTFSpc: |
| 11437 | case PPC::PSTH: |
| 11438 | case PPC::PSTH8: |
| 11439 | case PPC::PSTH8nopc: |
| 11440 | case PPC::PSTH8pc: |
| 11441 | case PPC::PSTHnopc: |
| 11442 | case PPC::PSTHpc: |
| 11443 | case PPC::PSTW: |
| 11444 | case PPC::PSTW8: |
| 11445 | case PPC::PSTW8nopc: |
| 11446 | case PPC::PSTW8pc: |
| 11447 | case PPC::PSTWnopc: |
| 11448 | case PPC::PSTWpc: |
| 11449 | case PPC::PSTXSD: |
| 11450 | case PPC::PSTXSDnopc: |
| 11451 | case PPC::PSTXSDpc: |
| 11452 | case PPC::PSTXSSP: |
| 11453 | case PPC::PSTXSSPnopc: |
| 11454 | case PPC::PSTXSSPpc: |
| 11455 | case PPC::SPELWZ: |
| 11456 | case PPC::SPESTW: |
| 11457 | case PPC::STB: |
| 11458 | case PPC::STB8: |
| 11459 | case PPC::STFD: |
| 11460 | case PPC::STFS: |
| 11461 | case PPC::STH: |
| 11462 | case PPC::STH8: |
| 11463 | case PPC::STMW: |
| 11464 | case PPC::STW: |
| 11465 | case PPC::STW8: { |
| 11466 | switch (OpNum) { |
| 11467 | case 0: |
| 11468 | // op: RST |
| 11469 | return 21; |
| 11470 | case 2: |
| 11471 | // op: RA |
| 11472 | return 16; |
| 11473 | case 1: |
| 11474 | // op: D |
| 11475 | return 0; |
| 11476 | } |
| 11477 | break; |
| 11478 | } |
| 11479 | case PPC::LD: |
| 11480 | case PPC::LWA: |
| 11481 | case PPC::LWA_32: |
| 11482 | case PPC::LXSD: |
| 11483 | case PPC::LXSSP: |
| 11484 | case PPC::STD: |
| 11485 | case PPC::STQ: |
| 11486 | case PPC::STXSD: |
| 11487 | case PPC::STXSSP: { |
| 11488 | switch (OpNum) { |
| 11489 | case 0: |
| 11490 | // op: RST |
| 11491 | return 21; |
| 11492 | case 2: |
| 11493 | // op: RA |
| 11494 | return 16; |
| 11495 | case 1: |
| 11496 | // op: D |
| 11497 | return 2; |
| 11498 | } |
| 11499 | break; |
| 11500 | } |
| 11501 | case PPC::LBZUX: |
| 11502 | case PPC::LBZUX8: |
| 11503 | case PPC::LDUX: |
| 11504 | case PPC::LFDUX: |
| 11505 | case PPC::LFSUX: |
| 11506 | case PPC::LHAUX: |
| 11507 | case PPC::LHAUX8: |
| 11508 | case PPC::LHZUX: |
| 11509 | case PPC::LHZUX8: |
| 11510 | case PPC::LWAUX: |
| 11511 | case PPC::LWZUX: |
| 11512 | case PPC::LWZUX8: |
| 11513 | case PPC::XSMADDQP: |
| 11514 | case PPC::XSMADDQPO: |
| 11515 | case PPC::XSMSUBQP: |
| 11516 | case PPC::XSMSUBQPO: |
| 11517 | case PPC::XSNMADDQP: |
| 11518 | case PPC::XSNMADDQPO: |
| 11519 | case PPC::XSNMSUBQP: |
| 11520 | case PPC::XSNMSUBQPO: { |
| 11521 | switch (OpNum) { |
| 11522 | case 0: |
| 11523 | // op: RST |
| 11524 | return 21; |
| 11525 | case 2: |
| 11526 | // op: RA |
| 11527 | return 16; |
| 11528 | case 3: |
| 11529 | // op: RB |
| 11530 | return 11; |
| 11531 | } |
| 11532 | break; |
| 11533 | } |
| 11534 | case PPC::LBZU: |
| 11535 | case PPC::LBZU8: |
| 11536 | case PPC::LFDU: |
| 11537 | case PPC::LFSU: |
| 11538 | case PPC::LHAU: |
| 11539 | case PPC::LHAU8: |
| 11540 | case PPC::LHZU: |
| 11541 | case PPC::LHZU8: |
| 11542 | case PPC::LWZU: |
| 11543 | case PPC::LWZU8: { |
| 11544 | switch (OpNum) { |
| 11545 | case 0: |
| 11546 | // op: RST |
| 11547 | return 21; |
| 11548 | case 3: |
| 11549 | // op: RA |
| 11550 | return 16; |
| 11551 | case 2: |
| 11552 | // op: D |
| 11553 | return 0; |
| 11554 | } |
| 11555 | break; |
| 11556 | } |
| 11557 | case PPC::LDU: { |
| 11558 | switch (OpNum) { |
| 11559 | case 0: |
| 11560 | // op: RST |
| 11561 | return 21; |
| 11562 | case 3: |
| 11563 | // op: RA |
| 11564 | return 16; |
| 11565 | case 2: |
| 11566 | // op: D |
| 11567 | return 2; |
| 11568 | } |
| 11569 | break; |
| 11570 | } |
| 11571 | case PPC::MFCTR: |
| 11572 | case PPC::MFCTR8: |
| 11573 | case PPC::MFFS: |
| 11574 | case PPC::MFFSCE: |
| 11575 | case PPC::MFFSL: |
| 11576 | case PPC::MFFS_rec: |
| 11577 | case PPC::MFLR: |
| 11578 | case PPC::MFLR8: |
| 11579 | case PPC::MFMSR: |
| 11580 | case PPC::MFTB8: |
| 11581 | case PPC::MFUDSCR: |
| 11582 | case PPC::MFVRSAVE: |
| 11583 | case PPC::MFVRSAVEv: |
| 11584 | case PPC::MTCTR: |
| 11585 | case PPC::MTCTR8: |
| 11586 | case PPC::MTCTR8loop: |
| 11587 | case PPC::MTCTRloop: |
| 11588 | case PPC::MTLR: |
| 11589 | case PPC::MTLR8: |
| 11590 | case PPC::MTUDSCR: |
| 11591 | case PPC::MTVRSAVE: { |
| 11592 | switch (OpNum) { |
| 11593 | case 0: |
| 11594 | // op: RST |
| 11595 | return 21; |
| 11596 | } |
| 11597 | break; |
| 11598 | } |
| 11599 | case PPC::SETB: |
| 11600 | case PPC::SETB8: { |
| 11601 | switch (OpNum) { |
| 11602 | case 0: |
| 11603 | // op: RT |
| 11604 | return 21; |
| 11605 | case 1: |
| 11606 | // op: BFA |
| 11607 | return 18; |
| 11608 | } |
| 11609 | break; |
| 11610 | } |
| 11611 | case PPC::ADDPCIS: |
| 11612 | case PPC::MTVSRBMI: { |
| 11613 | switch (OpNum) { |
| 11614 | case 0: |
| 11615 | // op: RT |
| 11616 | return 21; |
| 11617 | case 1: |
| 11618 | // op: D |
| 11619 | return 0; |
| 11620 | } |
| 11621 | break; |
| 11622 | } |
| 11623 | case PPC::DARN: { |
| 11624 | switch (OpNum) { |
| 11625 | case 0: |
| 11626 | // op: RT |
| 11627 | return 21; |
| 11628 | case 1: |
| 11629 | // op: L |
| 11630 | return 16; |
| 11631 | } |
| 11632 | break; |
| 11633 | } |
| 11634 | case PPC::ISEL: |
| 11635 | case PPC::ISEL8: { |
| 11636 | switch (OpNum) { |
| 11637 | case 0: |
| 11638 | // op: RT |
| 11639 | return 21; |
| 11640 | case 1: |
| 11641 | // op: RA |
| 11642 | return 16; |
| 11643 | case 2: |
| 11644 | // op: RB |
| 11645 | return 11; |
| 11646 | case 3: |
| 11647 | // op: COND |
| 11648 | return 6; |
| 11649 | } |
| 11650 | break; |
| 11651 | } |
| 11652 | case PPC::ADDEX: |
| 11653 | case PPC::ADDEX8: { |
| 11654 | switch (OpNum) { |
| 11655 | case 0: |
| 11656 | // op: RT |
| 11657 | return 21; |
| 11658 | case 1: |
| 11659 | // op: RA |
| 11660 | return 16; |
| 11661 | case 2: |
| 11662 | // op: RB |
| 11663 | return 11; |
| 11664 | case 3: |
| 11665 | // op: CY |
| 11666 | return 9; |
| 11667 | } |
| 11668 | break; |
| 11669 | } |
| 11670 | case PPC::SUBFUS: |
| 11671 | case PPC::SUBFUS_rec: { |
| 11672 | switch (OpNum) { |
| 11673 | case 0: |
| 11674 | // op: RT |
| 11675 | return 21; |
| 11676 | case 1: |
| 11677 | // op: RA |
| 11678 | return 16; |
| 11679 | case 2: |
| 11680 | // op: RB |
| 11681 | return 11; |
| 11682 | case 3: |
| 11683 | // op: L |
| 11684 | return 10; |
| 11685 | } |
| 11686 | break; |
| 11687 | } |
| 11688 | case PPC::MADDHD: |
| 11689 | case PPC::MADDHDU: |
| 11690 | case PPC::MADDLD: |
| 11691 | case PPC::MADDLD8: |
| 11692 | case PPC::VADDECUQ: |
| 11693 | case PPC::VADDEUQM: |
| 11694 | case PPC::VEXTDDVLX: |
| 11695 | case PPC::VEXTDDVRX: |
| 11696 | case PPC::VEXTDUBVLX: |
| 11697 | case PPC::VEXTDUBVRX: |
| 11698 | case PPC::VEXTDUHVLX: |
| 11699 | case PPC::VEXTDUHVRX: |
| 11700 | case PPC::VEXTDUWVLX: |
| 11701 | case PPC::VEXTDUWVRX: |
| 11702 | case PPC::VMHADDSHS: |
| 11703 | case PPC::VMHRADDSHS: |
| 11704 | case PPC::VMLADDUHM: |
| 11705 | case PPC::VMSUMCUD: |
| 11706 | case PPC::VMSUMMBM: |
| 11707 | case PPC::VMSUMSHM: |
| 11708 | case PPC::VMSUMSHS: |
| 11709 | case PPC::VMSUMUBM: |
| 11710 | case PPC::VMSUMUDM: |
| 11711 | case PPC::VMSUMUHM: |
| 11712 | case PPC::VMSUMUHS: |
| 11713 | case PPC::VPERM: |
| 11714 | case PPC::VPERMR: |
| 11715 | case PPC::VSEL: |
| 11716 | case PPC::VSUBECUQ: |
| 11717 | case PPC::VSUBEUQM: { |
| 11718 | switch (OpNum) { |
| 11719 | case 0: |
| 11720 | // op: RT |
| 11721 | return 21; |
| 11722 | case 1: |
| 11723 | // op: RA |
| 11724 | return 16; |
| 11725 | case 2: |
| 11726 | // op: RB |
| 11727 | return 11; |
| 11728 | case 3: |
| 11729 | // op: RC |
| 11730 | return 6; |
| 11731 | } |
| 11732 | break; |
| 11733 | } |
| 11734 | case PPC::VSLDOI: { |
| 11735 | switch (OpNum) { |
| 11736 | case 0: |
| 11737 | // op: RT |
| 11738 | return 21; |
| 11739 | case 1: |
| 11740 | // op: RA |
| 11741 | return 16; |
| 11742 | case 2: |
| 11743 | // op: RB |
| 11744 | return 11; |
| 11745 | case 3: |
| 11746 | // op: SH |
| 11747 | return 6; |
| 11748 | } |
| 11749 | break; |
| 11750 | } |
| 11751 | case PPC::ADD4: |
| 11752 | case PPC::ADD4O: |
| 11753 | case PPC::ADD4O_rec: |
| 11754 | case PPC::ADD4TLS: |
| 11755 | case PPC::ADD4_rec: |
| 11756 | case PPC::ADD8: |
| 11757 | case PPC::ADD8O: |
| 11758 | case PPC::ADD8O_rec: |
| 11759 | case PPC::ADD8TLS: |
| 11760 | case PPC::ADD8TLS_: |
| 11761 | case PPC::ADD8_rec: |
| 11762 | case PPC::ADDC: |
| 11763 | case PPC::ADDC8: |
| 11764 | case PPC::ADDC8O: |
| 11765 | case PPC::ADDC8O_rec: |
| 11766 | case PPC::ADDC8_rec: |
| 11767 | case PPC::ADDCO: |
| 11768 | case PPC::ADDCO_rec: |
| 11769 | case PPC::ADDC_rec: |
| 11770 | case PPC::ADDE: |
| 11771 | case PPC::ADDE8: |
| 11772 | case PPC::ADDE8O: |
| 11773 | case PPC::ADDE8O_rec: |
| 11774 | case PPC::ADDE8_rec: |
| 11775 | case PPC::ADDEO: |
| 11776 | case PPC::ADDEO_rec: |
| 11777 | case PPC::ADDE_rec: |
| 11778 | case PPC::ADDG6S: |
| 11779 | case PPC::ADDG6S8: |
| 11780 | case PPC::BRINC: |
| 11781 | case PPC::DIVD: |
| 11782 | case PPC::DIVDE: |
| 11783 | case PPC::DIVDEO: |
| 11784 | case PPC::DIVDEO_rec: |
| 11785 | case PPC::DIVDEU: |
| 11786 | case PPC::DIVDEUO: |
| 11787 | case PPC::DIVDEUO_rec: |
| 11788 | case PPC::DIVDEU_rec: |
| 11789 | case PPC::DIVDE_rec: |
| 11790 | case PPC::DIVDO: |
| 11791 | case PPC::DIVDO_rec: |
| 11792 | case PPC::DIVDU: |
| 11793 | case PPC::DIVDUO: |
| 11794 | case PPC::DIVDUO_rec: |
| 11795 | case PPC::DIVDU_rec: |
| 11796 | case PPC::DIVD_rec: |
| 11797 | case PPC::DIVW: |
| 11798 | case PPC::DIVWE: |
| 11799 | case PPC::DIVWEO: |
| 11800 | case PPC::DIVWEO_rec: |
| 11801 | case PPC::DIVWEU: |
| 11802 | case PPC::DIVWEUO: |
| 11803 | case PPC::DIVWEUO_rec: |
| 11804 | case PPC::DIVWEU_rec: |
| 11805 | case PPC::DIVWE_rec: |
| 11806 | case PPC::DIVWO: |
| 11807 | case PPC::DIVWO_rec: |
| 11808 | case PPC::DIVWU: |
| 11809 | case PPC::DIVWUO: |
| 11810 | case PPC::DIVWUO_rec: |
| 11811 | case PPC::DIVWU_rec: |
| 11812 | case PPC::DIVW_rec: |
| 11813 | case PPC::EFDADD: |
| 11814 | case PPC::EFDDIV: |
| 11815 | case PPC::EFDMUL: |
| 11816 | case PPC::EFDSUB: |
| 11817 | case PPC::EFSADD: |
| 11818 | case PPC::EFSDIV: |
| 11819 | case PPC::EFSMUL: |
| 11820 | case PPC::EFSSUB: |
| 11821 | case PPC::EVADDIW: |
| 11822 | case PPC::EVADDW: |
| 11823 | case PPC::EVAND: |
| 11824 | case PPC::EVANDC: |
| 11825 | case PPC::EVDIVWS: |
| 11826 | case PPC::EVDIVWU: |
| 11827 | case PPC::EVEQV: |
| 11828 | case PPC::EVFSADD: |
| 11829 | case PPC::EVFSDIV: |
| 11830 | case PPC::EVFSMUL: |
| 11831 | case PPC::EVFSSUB: |
| 11832 | case PPC::EVLDDX: |
| 11833 | case PPC::EVLDHX: |
| 11834 | case PPC::EVLDWX: |
| 11835 | case PPC::EVLHHESPLATX: |
| 11836 | case PPC::EVLHHOSSPLATX: |
| 11837 | case PPC::EVLHHOUSPLATX: |
| 11838 | case PPC::EVLWHEX: |
| 11839 | case PPC::EVLWHOSX: |
| 11840 | case PPC::EVLWHOUX: |
| 11841 | case PPC::EVLWHSPLATX: |
| 11842 | case PPC::EVLWWSPLATX: |
| 11843 | case PPC::EVMERGEHI: |
| 11844 | case PPC::EVMERGEHILO: |
| 11845 | case PPC::EVMERGELO: |
| 11846 | case PPC::EVMERGELOHI: |
| 11847 | case PPC::EVMHEGSMFAA: |
| 11848 | case PPC::EVMHEGSMFAN: |
| 11849 | case PPC::EVMHEGSMIAA: |
| 11850 | case PPC::EVMHEGSMIAN: |
| 11851 | case PPC::EVMHEGUMIAA: |
| 11852 | case PPC::EVMHEGUMIAN: |
| 11853 | case PPC::EVMHESMF: |
| 11854 | case PPC::EVMHESMFA: |
| 11855 | case PPC::EVMHESMFAAW: |
| 11856 | case PPC::EVMHESMFANW: |
| 11857 | case PPC::EVMHESMI: |
| 11858 | case PPC::EVMHESMIA: |
| 11859 | case PPC::EVMHESMIAAW: |
| 11860 | case PPC::EVMHESMIANW: |
| 11861 | case PPC::EVMHESSF: |
| 11862 | case PPC::EVMHESSFA: |
| 11863 | case PPC::EVMHESSFAAW: |
| 11864 | case PPC::EVMHESSFANW: |
| 11865 | case PPC::EVMHESSIAAW: |
| 11866 | case PPC::EVMHESSIANW: |
| 11867 | case PPC::EVMHEUMI: |
| 11868 | case PPC::EVMHEUMIA: |
| 11869 | case PPC::EVMHEUMIAAW: |
| 11870 | case PPC::EVMHEUMIANW: |
| 11871 | case PPC::EVMHEUSIAAW: |
| 11872 | case PPC::EVMHEUSIANW: |
| 11873 | case PPC::EVMHOGSMFAA: |
| 11874 | case PPC::EVMHOGSMFAN: |
| 11875 | case PPC::EVMHOGSMIAA: |
| 11876 | case PPC::EVMHOGSMIAN: |
| 11877 | case PPC::EVMHOGUMIAA: |
| 11878 | case PPC::EVMHOGUMIAN: |
| 11879 | case PPC::EVMHOSMF: |
| 11880 | case PPC::EVMHOSMFA: |
| 11881 | case PPC::EVMHOSMFAAW: |
| 11882 | case PPC::EVMHOSMFANW: |
| 11883 | case PPC::EVMHOSMI: |
| 11884 | case PPC::EVMHOSMIA: |
| 11885 | case PPC::EVMHOSMIAAW: |
| 11886 | case PPC::EVMHOSMIANW: |
| 11887 | case PPC::EVMHOSSF: |
| 11888 | case PPC::EVMHOSSFA: |
| 11889 | case PPC::EVMHOSSFAAW: |
| 11890 | case PPC::EVMHOSSFANW: |
| 11891 | case PPC::EVMHOSSIAAW: |
| 11892 | case PPC::EVMHOSSIANW: |
| 11893 | case PPC::EVMHOUMI: |
| 11894 | case PPC::EVMHOUMIA: |
| 11895 | case PPC::EVMHOUMIAAW: |
| 11896 | case PPC::EVMHOUMIANW: |
| 11897 | case PPC::EVMHOUSIAAW: |
| 11898 | case PPC::EVMHOUSIANW: |
| 11899 | case PPC::EVMWHSMF: |
| 11900 | case PPC::EVMWHSMFA: |
| 11901 | case PPC::EVMWHSMI: |
| 11902 | case PPC::EVMWHSMIA: |
| 11903 | case PPC::EVMWHSSF: |
| 11904 | case PPC::EVMWHSSFA: |
| 11905 | case PPC::EVMWHUMI: |
| 11906 | case PPC::EVMWHUMIA: |
| 11907 | case PPC::EVMWLSMIAAW: |
| 11908 | case PPC::EVMWLSMIANW: |
| 11909 | case PPC::EVMWLSSIAAW: |
| 11910 | case PPC::EVMWLSSIANW: |
| 11911 | case PPC::EVMWLUMI: |
| 11912 | case PPC::EVMWLUMIA: |
| 11913 | case PPC::EVMWLUMIAAW: |
| 11914 | case PPC::EVMWLUMIANW: |
| 11915 | case PPC::EVMWLUSIAAW: |
| 11916 | case PPC::EVMWLUSIANW: |
| 11917 | case PPC::EVMWSMF: |
| 11918 | case PPC::EVMWSMFA: |
| 11919 | case PPC::EVMWSMFAA: |
| 11920 | case PPC::EVMWSMFAN: |
| 11921 | case PPC::EVMWSMI: |
| 11922 | case PPC::EVMWSMIA: |
| 11923 | case PPC::EVMWSMIAA: |
| 11924 | case PPC::EVMWSMIAN: |
| 11925 | case PPC::EVMWSSF: |
| 11926 | case PPC::EVMWSSFA: |
| 11927 | case PPC::EVMWSSFAA: |
| 11928 | case PPC::EVMWSSFAN: |
| 11929 | case PPC::EVMWUMI: |
| 11930 | case PPC::EVMWUMIA: |
| 11931 | case PPC::EVMWUMIAA: |
| 11932 | case PPC::EVMWUMIAN: |
| 11933 | case PPC::EVNAND: |
| 11934 | case PPC::EVNOR: |
| 11935 | case PPC::EVOR: |
| 11936 | case PPC::EVORC: |
| 11937 | case PPC::EVRLW: |
| 11938 | case PPC::EVRLWI: |
| 11939 | case PPC::EVSLW: |
| 11940 | case PPC::EVSLWI: |
| 11941 | case PPC::EVSRWIS: |
| 11942 | case PPC::EVSRWIU: |
| 11943 | case PPC::EVSRWS: |
| 11944 | case PPC::EVSRWU: |
| 11945 | case PPC::EVSTDDX: |
| 11946 | case PPC::EVSTDHX: |
| 11947 | case PPC::EVSTDWX: |
| 11948 | case PPC::EVSTWHEX: |
| 11949 | case PPC::EVSTWHOX: |
| 11950 | case PPC::EVSTWWEX: |
| 11951 | case PPC::EVSTWWOX: |
| 11952 | case PPC::EVSUBFW: |
| 11953 | case PPC::EVSUBIFW: |
| 11954 | case PPC::EVXOR: |
| 11955 | case PPC::MULHD: |
| 11956 | case PPC::MULHDU: |
| 11957 | case PPC::MULHDU_rec: |
| 11958 | case PPC::MULHD_rec: |
| 11959 | case PPC::MULHW: |
| 11960 | case PPC::MULHWU: |
| 11961 | case PPC::MULHWU_rec: |
| 11962 | case PPC::MULHW_rec: |
| 11963 | case PPC::MULLD: |
| 11964 | case PPC::MULLDO: |
| 11965 | case PPC::MULLDO_rec: |
| 11966 | case PPC::MULLD_rec: |
| 11967 | case PPC::MULLW: |
| 11968 | case PPC::MULLWO: |
| 11969 | case PPC::MULLWO_rec: |
| 11970 | case PPC::MULLW_rec: |
| 11971 | case PPC::SUBF: |
| 11972 | case PPC::SUBF8: |
| 11973 | case PPC::SUBF8O: |
| 11974 | case PPC::SUBF8O_rec: |
| 11975 | case PPC::SUBF8_rec: |
| 11976 | case PPC::SUBFC: |
| 11977 | case PPC::SUBFC8: |
| 11978 | case PPC::SUBFC8O: |
| 11979 | case PPC::SUBFC8O_rec: |
| 11980 | case PPC::SUBFC8_rec: |
| 11981 | case PPC::SUBFCO: |
| 11982 | case PPC::SUBFCO_rec: |
| 11983 | case PPC::SUBFC_rec: |
| 11984 | case PPC::SUBFE: |
| 11985 | case PPC::SUBFE8: |
| 11986 | case PPC::SUBFE8O: |
| 11987 | case PPC::SUBFE8O_rec: |
| 11988 | case PPC::SUBFE8_rec: |
| 11989 | case PPC::SUBFEO: |
| 11990 | case PPC::SUBFEO_rec: |
| 11991 | case PPC::SUBFE_rec: |
| 11992 | case PPC::SUBFO: |
| 11993 | case PPC::SUBFO_rec: |
| 11994 | case PPC::SUBF_rec: { |
| 11995 | switch (OpNum) { |
| 11996 | case 0: |
| 11997 | // op: RT |
| 11998 | return 21; |
| 11999 | case 1: |
| 12000 | // op: RA |
| 12001 | return 16; |
| 12002 | case 2: |
| 12003 | // op: RB |
| 12004 | return 11; |
| 12005 | } |
| 12006 | break; |
| 12007 | } |
| 12008 | case PPC::VMADDFP: |
| 12009 | case PPC::VNMSUBFP: { |
| 12010 | switch (OpNum) { |
| 12011 | case 0: |
| 12012 | // op: RT |
| 12013 | return 21; |
| 12014 | case 1: |
| 12015 | // op: RA |
| 12016 | return 16; |
| 12017 | case 2: |
| 12018 | // op: RC |
| 12019 | return 6; |
| 12020 | case 3: |
| 12021 | // op: RB |
| 12022 | return 11; |
| 12023 | } |
| 12024 | break; |
| 12025 | } |
| 12026 | case PPC::PADDI: |
| 12027 | case PPC::PADDI8: |
| 12028 | case PPC::PADDI8pc: |
| 12029 | case PPC::PADDIpc: { |
| 12030 | switch (OpNum) { |
| 12031 | case 0: |
| 12032 | // op: RT |
| 12033 | return 21; |
| 12034 | case 1: |
| 12035 | // op: RA |
| 12036 | return 16; |
| 12037 | case 2: |
| 12038 | // op: SI |
| 12039 | return 0; |
| 12040 | } |
| 12041 | break; |
| 12042 | } |
| 12043 | case PPC::VPERMXOR: { |
| 12044 | switch (OpNum) { |
| 12045 | case 0: |
| 12046 | // op: RT |
| 12047 | return 21; |
| 12048 | case 1: |
| 12049 | // op: RA |
| 12050 | return 16; |
| 12051 | case 3: |
| 12052 | // op: RC |
| 12053 | return 6; |
| 12054 | case 2: |
| 12055 | // op: RB |
| 12056 | return 11; |
| 12057 | } |
| 12058 | break; |
| 12059 | } |
| 12060 | case PPC::ADDME: |
| 12061 | case PPC::ADDME8: |
| 12062 | case PPC::ADDME8O: |
| 12063 | case PPC::ADDME8O_rec: |
| 12064 | case PPC::ADDME8_rec: |
| 12065 | case PPC::ADDMEO: |
| 12066 | case PPC::ADDMEO_rec: |
| 12067 | case PPC::ADDME_rec: |
| 12068 | case PPC::ADDZE: |
| 12069 | case PPC::ADDZE8: |
| 12070 | case PPC::ADDZE8O: |
| 12071 | case PPC::ADDZE8O_rec: |
| 12072 | case PPC::ADDZE8_rec: |
| 12073 | case PPC::ADDZEO: |
| 12074 | case PPC::ADDZEO_rec: |
| 12075 | case PPC::ADDZE_rec: |
| 12076 | case PPC::EFDABS: |
| 12077 | case PPC::EFDNABS: |
| 12078 | case PPC::EFDNEG: |
| 12079 | case PPC::EFSABS: |
| 12080 | case PPC::EFSNABS: |
| 12081 | case PPC::EFSNEG: |
| 12082 | case PPC::EVABS: |
| 12083 | case PPC::EVADDSMIAAW: |
| 12084 | case PPC::EVADDSSIAAW: |
| 12085 | case PPC::EVADDUMIAAW: |
| 12086 | case PPC::EVADDUSIAAW: |
| 12087 | case PPC::EVCNTLSW: |
| 12088 | case PPC::EVCNTLZW: |
| 12089 | case PPC::EVEXTSB: |
| 12090 | case PPC::EVEXTSH: |
| 12091 | case PPC::EVFSABS: |
| 12092 | case PPC::EVFSNABS: |
| 12093 | case PPC::EVFSNEG: |
| 12094 | case PPC::EVMRA: |
| 12095 | case PPC::EVNEG: |
| 12096 | case PPC::EVRNDW: |
| 12097 | case PPC::EVSPLATFI: |
| 12098 | case PPC::EVSPLATI: |
| 12099 | case PPC::EVSUBFSMIAAW: |
| 12100 | case PPC::EVSUBFSSIAAW: |
| 12101 | case PPC::EVSUBFUMIAAW: |
| 12102 | case PPC::EVSUBFUSIAAW: |
| 12103 | case PPC::NEG: |
| 12104 | case PPC::NEG8: |
| 12105 | case PPC::NEG8O: |
| 12106 | case PPC::NEG8O_rec: |
| 12107 | case PPC::NEG8_rec: |
| 12108 | case PPC::NEGO: |
| 12109 | case PPC::NEGO_rec: |
| 12110 | case PPC::NEG_rec: |
| 12111 | case PPC::SUBFME: |
| 12112 | case PPC::SUBFME8: |
| 12113 | case PPC::SUBFME8O: |
| 12114 | case PPC::SUBFME8O_rec: |
| 12115 | case PPC::SUBFME8_rec: |
| 12116 | case PPC::SUBFMEO: |
| 12117 | case PPC::SUBFMEO_rec: |
| 12118 | case PPC::SUBFME_rec: |
| 12119 | case PPC::SUBFZE: |
| 12120 | case PPC::SUBFZE8: |
| 12121 | case PPC::SUBFZE8O: |
| 12122 | case PPC::SUBFZE8O_rec: |
| 12123 | case PPC::SUBFZE8_rec: |
| 12124 | case PPC::SUBFZEO: |
| 12125 | case PPC::SUBFZEO_rec: |
| 12126 | case PPC::SUBFZE_rec: { |
| 12127 | switch (OpNum) { |
| 12128 | case 0: |
| 12129 | // op: RT |
| 12130 | return 21; |
| 12131 | case 1: |
| 12132 | // op: RA |
| 12133 | return 16; |
| 12134 | } |
| 12135 | break; |
| 12136 | } |
| 12137 | case PPC::EFDCFS: |
| 12138 | case PPC::EFDCFSF: |
| 12139 | case PPC::EFDCFSI: |
| 12140 | case PPC::EFDCFSID: |
| 12141 | case PPC::EFDCFUF: |
| 12142 | case PPC::EFDCFUI: |
| 12143 | case PPC::EFDCFUID: |
| 12144 | case PPC::EFDCTSF: |
| 12145 | case PPC::EFDCTSI: |
| 12146 | case PPC::EFDCTSIDZ: |
| 12147 | case PPC::EFDCTSIZ: |
| 12148 | case PPC::EFDCTUF: |
| 12149 | case PPC::EFDCTUI: |
| 12150 | case PPC::EFDCTUIDZ: |
| 12151 | case PPC::EFDCTUIZ: |
| 12152 | case PPC::EFSCFD: |
| 12153 | case PPC::EFSCFSF: |
| 12154 | case PPC::EFSCFSI: |
| 12155 | case PPC::EFSCFUF: |
| 12156 | case PPC::EFSCFUI: |
| 12157 | case PPC::EFSCTSF: |
| 12158 | case PPC::EFSCTSI: |
| 12159 | case PPC::EFSCTSIZ: |
| 12160 | case PPC::EFSCTUF: |
| 12161 | case PPC::EFSCTUI: |
| 12162 | case PPC::EFSCTUIZ: |
| 12163 | case PPC::EVFSCFSF: |
| 12164 | case PPC::EVFSCFSI: |
| 12165 | case PPC::EVFSCFUF: |
| 12166 | case PPC::EVFSCFUI: |
| 12167 | case PPC::EVFSCTSF: |
| 12168 | case PPC::EVFSCTSI: |
| 12169 | case PPC::EVFSCTSIZ: |
| 12170 | case PPC::EVFSCTUF: |
| 12171 | case PPC::EVFSCTUI: |
| 12172 | case PPC::EVFSCTUIZ: |
| 12173 | case PPC::SLBMFEV: { |
| 12174 | switch (OpNum) { |
| 12175 | case 0: |
| 12176 | // op: RT |
| 12177 | return 21; |
| 12178 | case 1: |
| 12179 | // op: RB |
| 12180 | return 11; |
| 12181 | } |
| 12182 | break; |
| 12183 | } |
| 12184 | case PPC::PLA8pc: |
| 12185 | case PPC::PLApc: |
| 12186 | case PPC::PLI: |
| 12187 | case PPC::PLI8: { |
| 12188 | switch (OpNum) { |
| 12189 | case 0: |
| 12190 | // op: RT |
| 12191 | return 21; |
| 12192 | case 1: |
| 12193 | // op: SI |
| 12194 | return 0; |
| 12195 | } |
| 12196 | break; |
| 12197 | } |
| 12198 | case PPC::XSXEXPDP: |
| 12199 | case PPC::XSXSIGDP: { |
| 12200 | switch (OpNum) { |
| 12201 | case 0: |
| 12202 | // op: RT |
| 12203 | return 21; |
| 12204 | case 1: |
| 12205 | // op: XB |
| 12206 | return 1; |
| 12207 | } |
| 12208 | break; |
| 12209 | } |
| 12210 | case PPC::MFBHRBE: { |
| 12211 | switch (OpNum) { |
| 12212 | case 0: |
| 12213 | // op: RT |
| 12214 | return 21; |
| 12215 | case 1: |
| 12216 | // op: imm |
| 12217 | return 11; |
| 12218 | } |
| 12219 | break; |
| 12220 | } |
| 12221 | case PPC::EVLDD: |
| 12222 | case PPC::EVLDH: |
| 12223 | case PPC::EVLDW: |
| 12224 | case PPC::EVLHHESPLAT: |
| 12225 | case PPC::EVLHHOSSPLAT: |
| 12226 | case PPC::EVLHHOUSPLAT: |
| 12227 | case PPC::EVLWHE: |
| 12228 | case PPC::EVLWHOS: |
| 12229 | case PPC::EVLWHOU: |
| 12230 | case PPC::EVLWHSPLAT: |
| 12231 | case PPC::EVLWWSPLAT: |
| 12232 | case PPC::EVSTDD: |
| 12233 | case PPC::EVSTDH: |
| 12234 | case PPC::EVSTDW: |
| 12235 | case PPC::EVSTWHE: |
| 12236 | case PPC::EVSTWHO: |
| 12237 | case PPC::EVSTWWE: |
| 12238 | case PPC::EVSTWWO: { |
| 12239 | switch (OpNum) { |
| 12240 | case 0: |
| 12241 | // op: RT |
| 12242 | return 21; |
| 12243 | case 2: |
| 12244 | // op: RA |
| 12245 | return 16; |
| 12246 | case 1: |
| 12247 | // op: D |
| 12248 | return 11; |
| 12249 | } |
| 12250 | break; |
| 12251 | } |
| 12252 | case PPC::PLA: |
| 12253 | case PPC::PLA8: { |
| 12254 | switch (OpNum) { |
| 12255 | case 0: |
| 12256 | // op: RT |
| 12257 | return 21; |
| 12258 | case 2: |
| 12259 | // op: SI |
| 12260 | return 0; |
| 12261 | } |
| 12262 | break; |
| 12263 | } |
| 12264 | case PPC::MFCR: |
| 12265 | case PPC::MFCR8: { |
| 12266 | switch (OpNum) { |
| 12267 | case 0: |
| 12268 | // op: RT |
| 12269 | return 21; |
| 12270 | } |
| 12271 | break; |
| 12272 | } |
| 12273 | case PPC::LQ: { |
| 12274 | switch (OpNum) { |
| 12275 | case 0: |
| 12276 | // op: RTp |
| 12277 | return 21; |
| 12278 | case 2: |
| 12279 | // op: RA |
| 12280 | return 16; |
| 12281 | case 1: |
| 12282 | // op: DQ |
| 12283 | return 4; |
| 12284 | } |
| 12285 | break; |
| 12286 | } |
| 12287 | case PPC::RFEBB: { |
| 12288 | switch (OpNum) { |
| 12289 | case 0: |
| 12290 | // op: S |
| 12291 | return 11; |
| 12292 | } |
| 12293 | break; |
| 12294 | } |
| 12295 | case PPC::DST: |
| 12296 | case PPC::DST64: |
| 12297 | case PPC::DSTST: |
| 12298 | case PPC::DSTST64: |
| 12299 | case PPC::DSTSTT: |
| 12300 | case PPC::DSTSTT64: |
| 12301 | case PPC::DSTT: |
| 12302 | case PPC::DSTT64: { |
| 12303 | switch (OpNum) { |
| 12304 | case 0: |
| 12305 | // op: STRM |
| 12306 | return 21; |
| 12307 | case 1: |
| 12308 | // op: RA |
| 12309 | return 16; |
| 12310 | case 2: |
| 12311 | // op: RB |
| 12312 | return 11; |
| 12313 | } |
| 12314 | break; |
| 12315 | } |
| 12316 | case PPC::DSS: { |
| 12317 | switch (OpNum) { |
| 12318 | case 0: |
| 12319 | // op: STRM |
| 12320 | return 21; |
| 12321 | } |
| 12322 | break; |
| 12323 | } |
| 12324 | case PPC::DCBF: |
| 12325 | case PPC::DCBT: |
| 12326 | case PPC::DCBTST: { |
| 12327 | switch (OpNum) { |
| 12328 | case 0: |
| 12329 | // op: TH |
| 12330 | return 21; |
| 12331 | case 1: |
| 12332 | // op: RA |
| 12333 | return 16; |
| 12334 | case 2: |
| 12335 | // op: RB |
| 12336 | return 11; |
| 12337 | } |
| 12338 | break; |
| 12339 | } |
| 12340 | case PPC::MTVSCR: { |
| 12341 | switch (OpNum) { |
| 12342 | case 0: |
| 12343 | // op: VB |
| 12344 | return 11; |
| 12345 | } |
| 12346 | break; |
| 12347 | } |
| 12348 | case PPC::V_SET0: |
| 12349 | case PPC::V_SET0B: |
| 12350 | case PPC::V_SET0H: { |
| 12351 | switch (OpNum) { |
| 12352 | case 0: |
| 12353 | // op: VD |
| 12354 | return 11; |
| 12355 | } |
| 12356 | break; |
| 12357 | } |
| 12358 | case PPC::VSPLTISB: |
| 12359 | case PPC::VSPLTISH: |
| 12360 | case PPC::VSPLTISW: { |
| 12361 | switch (OpNum) { |
| 12362 | case 0: |
| 12363 | // op: VD |
| 12364 | return 21; |
| 12365 | case 1: |
| 12366 | // op: IMM |
| 12367 | return 16; |
| 12368 | } |
| 12369 | break; |
| 12370 | } |
| 12371 | case PPC::VSHASIGMAD: |
| 12372 | case PPC::VSHASIGMAW: { |
| 12373 | switch (OpNum) { |
| 12374 | case 0: |
| 12375 | // op: VD |
| 12376 | return 21; |
| 12377 | case 1: |
| 12378 | // op: VA |
| 12379 | return 16; |
| 12380 | case 2: |
| 12381 | // op: ST |
| 12382 | return 15; |
| 12383 | case 3: |
| 12384 | // op: SIX |
| 12385 | return 11; |
| 12386 | } |
| 12387 | break; |
| 12388 | } |
| 12389 | case PPC::BCDADD_rec: |
| 12390 | case PPC::BCDSR_rec: |
| 12391 | case PPC::BCDSUB_rec: |
| 12392 | case PPC::BCDS_rec: |
| 12393 | case PPC::BCDTRUNC_rec: { |
| 12394 | switch (OpNum) { |
| 12395 | case 0: |
| 12396 | // op: VD |
| 12397 | return 21; |
| 12398 | case 1: |
| 12399 | // op: VA |
| 12400 | return 16; |
| 12401 | case 2: |
| 12402 | // op: VB |
| 12403 | return 11; |
| 12404 | case 3: |
| 12405 | // op: PS |
| 12406 | return 9; |
| 12407 | } |
| 12408 | break; |
| 12409 | } |
| 12410 | case PPC::BCDCPSGN_rec: |
| 12411 | case PPC::BCDUS_rec: |
| 12412 | case PPC::BCDUTRUNC_rec: |
| 12413 | case PPC::VABSDUB: |
| 12414 | case PPC::VABSDUH: |
| 12415 | case PPC::VABSDUW: |
| 12416 | case PPC::VADDCUQ: |
| 12417 | case PPC::VADDCUW: |
| 12418 | case PPC::VADDFP: |
| 12419 | case PPC::VADDSBS: |
| 12420 | case PPC::VADDSHS: |
| 12421 | case PPC::VADDSWS: |
| 12422 | case PPC::VADDUBM: |
| 12423 | case PPC::VADDUBS: |
| 12424 | case PPC::VADDUDM: |
| 12425 | case PPC::VADDUHM: |
| 12426 | case PPC::VADDUHS: |
| 12427 | case PPC::VADDUQM: |
| 12428 | case PPC::VADDUWM: |
| 12429 | case PPC::VADDUWS: |
| 12430 | case PPC::VAND: |
| 12431 | case PPC::VANDC: |
| 12432 | case PPC::VAVGSB: |
| 12433 | case PPC::VAVGSH: |
| 12434 | case PPC::VAVGSW: |
| 12435 | case PPC::VAVGUB: |
| 12436 | case PPC::VAVGUH: |
| 12437 | case PPC::VAVGUW: |
| 12438 | case PPC::VBPERMD: |
| 12439 | case PPC::VBPERMQ: |
| 12440 | case PPC::VCFSX: |
| 12441 | case PPC::VCFUGED: |
| 12442 | case PPC::VCFUX: |
| 12443 | case PPC::VCIPHER: |
| 12444 | case PPC::VCIPHERLAST: |
| 12445 | case PPC::VCLRLB: |
| 12446 | case PPC::VCLRRB: |
| 12447 | case PPC::VCLZDM: |
| 12448 | case PPC::VCMPBFP: |
| 12449 | case PPC::VCMPBFP_rec: |
| 12450 | case PPC::VCMPEQFP: |
| 12451 | case PPC::VCMPEQFP_rec: |
| 12452 | case PPC::VCMPEQUB: |
| 12453 | case PPC::VCMPEQUB_rec: |
| 12454 | case PPC::VCMPEQUD: |
| 12455 | case PPC::VCMPEQUD_rec: |
| 12456 | case PPC::VCMPEQUH: |
| 12457 | case PPC::VCMPEQUH_rec: |
| 12458 | case PPC::VCMPEQUQ: |
| 12459 | case PPC::VCMPEQUQ_rec: |
| 12460 | case PPC::VCMPEQUW: |
| 12461 | case PPC::VCMPEQUW_rec: |
| 12462 | case PPC::VCMPGEFP: |
| 12463 | case PPC::VCMPGEFP_rec: |
| 12464 | case PPC::VCMPGTFP: |
| 12465 | case PPC::VCMPGTFP_rec: |
| 12466 | case PPC::VCMPGTSB: |
| 12467 | case PPC::VCMPGTSB_rec: |
| 12468 | case PPC::VCMPGTSD: |
| 12469 | case PPC::VCMPGTSD_rec: |
| 12470 | case PPC::VCMPGTSH: |
| 12471 | case PPC::VCMPGTSH_rec: |
| 12472 | case PPC::VCMPGTSQ: |
| 12473 | case PPC::VCMPGTSQ_rec: |
| 12474 | case PPC::VCMPGTSW: |
| 12475 | case PPC::VCMPGTSW_rec: |
| 12476 | case PPC::VCMPGTUB: |
| 12477 | case PPC::VCMPGTUB_rec: |
| 12478 | case PPC::VCMPGTUD: |
| 12479 | case PPC::VCMPGTUD_rec: |
| 12480 | case PPC::VCMPGTUH: |
| 12481 | case PPC::VCMPGTUH_rec: |
| 12482 | case PPC::VCMPGTUQ: |
| 12483 | case PPC::VCMPGTUQ_rec: |
| 12484 | case PPC::VCMPGTUW: |
| 12485 | case PPC::VCMPGTUW_rec: |
| 12486 | case PPC::VCMPNEB: |
| 12487 | case PPC::VCMPNEB_rec: |
| 12488 | case PPC::VCMPNEH: |
| 12489 | case PPC::VCMPNEH_rec: |
| 12490 | case PPC::VCMPNEW: |
| 12491 | case PPC::VCMPNEW_rec: |
| 12492 | case PPC::VCMPNEZB: |
| 12493 | case PPC::VCMPNEZB_rec: |
| 12494 | case PPC::VCMPNEZH: |
| 12495 | case PPC::VCMPNEZH_rec: |
| 12496 | case PPC::VCMPNEZW: |
| 12497 | case PPC::VCMPNEZW_rec: |
| 12498 | case PPC::VCTSXS: |
| 12499 | case PPC::VCTUXS: |
| 12500 | case PPC::VCTZDM: |
| 12501 | case PPC::VDIVESD: |
| 12502 | case PPC::VDIVESQ: |
| 12503 | case PPC::VDIVESW: |
| 12504 | case PPC::VDIVEUD: |
| 12505 | case PPC::VDIVEUQ: |
| 12506 | case PPC::VDIVEUW: |
| 12507 | case PPC::VDIVSD: |
| 12508 | case PPC::VDIVSQ: |
| 12509 | case PPC::VDIVSW: |
| 12510 | case PPC::VDIVUD: |
| 12511 | case PPC::VDIVUQ: |
| 12512 | case PPC::VDIVUW: |
| 12513 | case PPC::VEQV: |
| 12514 | case PPC::VEXTRACTD: |
| 12515 | case PPC::VEXTRACTUB: |
| 12516 | case PPC::VEXTRACTUH: |
| 12517 | case PPC::VEXTRACTUW: |
| 12518 | case PPC::VEXTUBLX: |
| 12519 | case PPC::VEXTUBRX: |
| 12520 | case PPC::VEXTUHLX: |
| 12521 | case PPC::VEXTUHRX: |
| 12522 | case PPC::VEXTUWLX: |
| 12523 | case PPC::VEXTUWRX: |
| 12524 | case PPC::VINSERTD: |
| 12525 | case PPC::VINSERTW: |
| 12526 | case PPC::VMAXFP: |
| 12527 | case PPC::VMAXSB: |
| 12528 | case PPC::VMAXSD: |
| 12529 | case PPC::VMAXSH: |
| 12530 | case PPC::VMAXSW: |
| 12531 | case PPC::VMAXUB: |
| 12532 | case PPC::VMAXUD: |
| 12533 | case PPC::VMAXUH: |
| 12534 | case PPC::VMAXUW: |
| 12535 | case PPC::VMINFP: |
| 12536 | case PPC::VMINSB: |
| 12537 | case PPC::VMINSD: |
| 12538 | case PPC::VMINSH: |
| 12539 | case PPC::VMINSW: |
| 12540 | case PPC::VMINUB: |
| 12541 | case PPC::VMINUD: |
| 12542 | case PPC::VMINUH: |
| 12543 | case PPC::VMINUW: |
| 12544 | case PPC::VMODSD: |
| 12545 | case PPC::VMODSQ: |
| 12546 | case PPC::VMODSW: |
| 12547 | case PPC::VMODUD: |
| 12548 | case PPC::VMODUQ: |
| 12549 | case PPC::VMODUW: |
| 12550 | case PPC::VMRGEW: |
| 12551 | case PPC::VMRGHB: |
| 12552 | case PPC::VMRGHH: |
| 12553 | case PPC::VMRGHW: |
| 12554 | case PPC::VMRGLB: |
| 12555 | case PPC::VMRGLH: |
| 12556 | case PPC::VMRGLW: |
| 12557 | case PPC::VMRGOW: |
| 12558 | case PPC::VMUL10ECUQ: |
| 12559 | case PPC::VMUL10EUQ: |
| 12560 | case PPC::VMULESB: |
| 12561 | case PPC::VMULESD: |
| 12562 | case PPC::VMULESH: |
| 12563 | case PPC::VMULESW: |
| 12564 | case PPC::VMULEUB: |
| 12565 | case PPC::VMULEUD: |
| 12566 | case PPC::VMULEUH: |
| 12567 | case PPC::VMULEUW: |
| 12568 | case PPC::VMULHSD: |
| 12569 | case PPC::VMULHSW: |
| 12570 | case PPC::VMULHUD: |
| 12571 | case PPC::VMULHUW: |
| 12572 | case PPC::VMULLD: |
| 12573 | case PPC::VMULOSB: |
| 12574 | case PPC::VMULOSD: |
| 12575 | case PPC::VMULOSH: |
| 12576 | case PPC::VMULOSW: |
| 12577 | case PPC::VMULOUB: |
| 12578 | case PPC::VMULOUD: |
| 12579 | case PPC::VMULOUH: |
| 12580 | case PPC::VMULOUW: |
| 12581 | case PPC::VMULUWM: |
| 12582 | case PPC::VNAND: |
| 12583 | case PPC::VNCIPHER: |
| 12584 | case PPC::VNCIPHERLAST: |
| 12585 | case PPC::VNOR: |
| 12586 | case PPC::VOR: |
| 12587 | case PPC::VORC: |
| 12588 | case PPC::VPDEPD: |
| 12589 | case PPC::VPEXTD: |
| 12590 | case PPC::VPKPX: |
| 12591 | case PPC::VPKSDSS: |
| 12592 | case PPC::VPKSDUS: |
| 12593 | case PPC::VPKSHSS: |
| 12594 | case PPC::VPKSHUS: |
| 12595 | case PPC::VPKSWSS: |
| 12596 | case PPC::VPKSWUS: |
| 12597 | case PPC::VPKUDUM: |
| 12598 | case PPC::VPKUDUS: |
| 12599 | case PPC::VPKUHUM: |
| 12600 | case PPC::VPKUHUS: |
| 12601 | case PPC::VPKUWUM: |
| 12602 | case PPC::VPKUWUS: |
| 12603 | case PPC::VPMSUMB: |
| 12604 | case PPC::VPMSUMD: |
| 12605 | case PPC::VPMSUMH: |
| 12606 | case PPC::VPMSUMW: |
| 12607 | case PPC::VRLB: |
| 12608 | case PPC::VRLD: |
| 12609 | case PPC::VRLDMI: |
| 12610 | case PPC::VRLDNM: |
| 12611 | case PPC::VRLH: |
| 12612 | case PPC::VRLQ: |
| 12613 | case PPC::VRLQMI: |
| 12614 | case PPC::VRLQNM: |
| 12615 | case PPC::VRLW: |
| 12616 | case PPC::VRLWMI: |
| 12617 | case PPC::VRLWNM: |
| 12618 | case PPC::VSL: |
| 12619 | case PPC::VSLB: |
| 12620 | case PPC::VSLD: |
| 12621 | case PPC::VSLH: |
| 12622 | case PPC::VSLO: |
| 12623 | case PPC::VSLQ: |
| 12624 | case PPC::VSLV: |
| 12625 | case PPC::VSLW: |
| 12626 | case PPC::VSPLTB: |
| 12627 | case PPC::VSPLTBs: |
| 12628 | case PPC::VSPLTH: |
| 12629 | case PPC::VSPLTHs: |
| 12630 | case PPC::VSPLTW: |
| 12631 | case PPC::VSR: |
| 12632 | case PPC::VSRAB: |
| 12633 | case PPC::VSRAD: |
| 12634 | case PPC::VSRAH: |
| 12635 | case PPC::VSRAQ: |
| 12636 | case PPC::VSRAW: |
| 12637 | case PPC::VSRB: |
| 12638 | case PPC::VSRD: |
| 12639 | case PPC::VSRH: |
| 12640 | case PPC::VSRO: |
| 12641 | case PPC::VSRQ: |
| 12642 | case PPC::VSRV: |
| 12643 | case PPC::VSRW: |
| 12644 | case PPC::VSUBCUQ: |
| 12645 | case PPC::VSUBCUW: |
| 12646 | case PPC::VSUBFP: |
| 12647 | case PPC::VSUBSBS: |
| 12648 | case PPC::VSUBSHS: |
| 12649 | case PPC::VSUBSWS: |
| 12650 | case PPC::VSUBUBM: |
| 12651 | case PPC::VSUBUBS: |
| 12652 | case PPC::VSUBUDM: |
| 12653 | case PPC::VSUBUHM: |
| 12654 | case PPC::VSUBUHS: |
| 12655 | case PPC::VSUBUQM: |
| 12656 | case PPC::VSUBUWM: |
| 12657 | case PPC::VSUBUWS: |
| 12658 | case PPC::VSUM2SWS: |
| 12659 | case PPC::VSUM4SBS: |
| 12660 | case PPC::VSUM4SHS: |
| 12661 | case PPC::VSUM4UBS: |
| 12662 | case PPC::VSUMSWS: |
| 12663 | case PPC::VXOR: { |
| 12664 | switch (OpNum) { |
| 12665 | case 0: |
| 12666 | // op: VD |
| 12667 | return 21; |
| 12668 | case 1: |
| 12669 | // op: VA |
| 12670 | return 16; |
| 12671 | case 2: |
| 12672 | // op: VB |
| 12673 | return 11; |
| 12674 | } |
| 12675 | break; |
| 12676 | } |
| 12677 | case PPC::VMUL10CUQ: |
| 12678 | case PPC::VMUL10UQ: |
| 12679 | case PPC::VSBOX: { |
| 12680 | switch (OpNum) { |
| 12681 | case 0: |
| 12682 | // op: VD |
| 12683 | return 21; |
| 12684 | case 1: |
| 12685 | // op: VA |
| 12686 | return 16; |
| 12687 | } |
| 12688 | break; |
| 12689 | } |
| 12690 | case PPC::BCDCFN_rec: |
| 12691 | case PPC::BCDCFSQ_rec: |
| 12692 | case PPC::BCDCFZ_rec: |
| 12693 | case PPC::BCDCTZ_rec: |
| 12694 | case PPC::BCDSETSGN_rec: { |
| 12695 | switch (OpNum) { |
| 12696 | case 0: |
| 12697 | // op: VD |
| 12698 | return 21; |
| 12699 | case 1: |
| 12700 | // op: VB |
| 12701 | return 11; |
| 12702 | case 2: |
| 12703 | // op: PS |
| 12704 | return 9; |
| 12705 | } |
| 12706 | break; |
| 12707 | } |
| 12708 | case PPC::BCDCTN_rec: |
| 12709 | case PPC::BCDCTSQ_rec: |
| 12710 | case PPC::MTVSRBM: |
| 12711 | case PPC::MTVSRDM: |
| 12712 | case PPC::MTVSRHM: |
| 12713 | case PPC::MTVSRQM: |
| 12714 | case PPC::MTVSRWM: |
| 12715 | case PPC::VCFSX_0: |
| 12716 | case PPC::VCFUX_0: |
| 12717 | case PPC::VCLZB: |
| 12718 | case PPC::VCLZD: |
| 12719 | case PPC::VCLZH: |
| 12720 | case PPC::VCLZLSBB: |
| 12721 | case PPC::VCLZW: |
| 12722 | case PPC::VCTSXS_0: |
| 12723 | case PPC::VCTUXS_0: |
| 12724 | case PPC::VCTZB: |
| 12725 | case PPC::VCTZD: |
| 12726 | case PPC::VCTZH: |
| 12727 | case PPC::VCTZLSBB: |
| 12728 | case PPC::VCTZW: |
| 12729 | case PPC::VEXPANDBM: |
| 12730 | case PPC::VEXPANDDM: |
| 12731 | case PPC::VEXPANDHM: |
| 12732 | case PPC::VEXPANDQM: |
| 12733 | case PPC::VEXPANDWM: |
| 12734 | case PPC::VEXPTEFP: |
| 12735 | case PPC::VEXTRACTBM: |
| 12736 | case PPC::VEXTRACTDM: |
| 12737 | case PPC::VEXTRACTHM: |
| 12738 | case PPC::VEXTRACTQM: |
| 12739 | case PPC::VEXTRACTWM: |
| 12740 | case PPC::VEXTSB2D: |
| 12741 | case PPC::VEXTSB2Ds: |
| 12742 | case PPC::VEXTSB2W: |
| 12743 | case PPC::VEXTSB2Ws: |
| 12744 | case PPC::VEXTSD2Q: |
| 12745 | case PPC::VEXTSH2D: |
| 12746 | case PPC::VEXTSH2Ds: |
| 12747 | case PPC::VEXTSH2W: |
| 12748 | case PPC::VEXTSH2Ws: |
| 12749 | case PPC::VEXTSW2D: |
| 12750 | case PPC::VEXTSW2Ds: |
| 12751 | case PPC::VGBBD: |
| 12752 | case PPC::VLOGEFP: |
| 12753 | case PPC::VNEGD: |
| 12754 | case PPC::VNEGW: |
| 12755 | case PPC::VPOPCNTB: |
| 12756 | case PPC::VPOPCNTD: |
| 12757 | case PPC::VPOPCNTH: |
| 12758 | case PPC::VPOPCNTW: |
| 12759 | case PPC::VPRTYBD: |
| 12760 | case PPC::VPRTYBQ: |
| 12761 | case PPC::VPRTYBW: |
| 12762 | case PPC::VREFP: |
| 12763 | case PPC::VRFIM: |
| 12764 | case PPC::VRFIN: |
| 12765 | case PPC::VRFIP: |
| 12766 | case PPC::VRFIZ: |
| 12767 | case PPC::VRSQRTEFP: |
| 12768 | case PPC::VUPKHPX: |
| 12769 | case PPC::VUPKHSB: |
| 12770 | case PPC::VUPKHSH: |
| 12771 | case PPC::VUPKHSW: |
| 12772 | case PPC::VUPKLPX: |
| 12773 | case PPC::VUPKLSB: |
| 12774 | case PPC::VUPKLSH: |
| 12775 | case PPC::VUPKLSW: { |
| 12776 | switch (OpNum) { |
| 12777 | case 0: |
| 12778 | // op: VD |
| 12779 | return 21; |
| 12780 | case 1: |
| 12781 | // op: VB |
| 12782 | return 11; |
| 12783 | } |
| 12784 | break; |
| 12785 | } |
| 12786 | case PPC::VINSBLX: |
| 12787 | case PPC::VINSBRX: |
| 12788 | case PPC::VINSBVLX: |
| 12789 | case PPC::VINSBVRX: |
| 12790 | case PPC::VINSD: |
| 12791 | case PPC::VINSDLX: |
| 12792 | case PPC::VINSDRX: |
| 12793 | case PPC::VINSERTB: |
| 12794 | case PPC::VINSERTH: |
| 12795 | case PPC::VINSHLX: |
| 12796 | case PPC::VINSHRX: |
| 12797 | case PPC::VINSHVLX: |
| 12798 | case PPC::VINSHVRX: |
| 12799 | case PPC::VINSW: |
| 12800 | case PPC::VINSWLX: |
| 12801 | case PPC::VINSWRX: |
| 12802 | case PPC::VINSWVLX: |
| 12803 | case PPC::VINSWVRX: { |
| 12804 | switch (OpNum) { |
| 12805 | case 0: |
| 12806 | // op: VD |
| 12807 | return 21; |
| 12808 | case 2: |
| 12809 | // op: VA |
| 12810 | return 16; |
| 12811 | case 3: |
| 12812 | // op: VB |
| 12813 | return 11; |
| 12814 | } |
| 12815 | break; |
| 12816 | } |
| 12817 | case PPC::MFVSCR: |
| 12818 | case PPC::V_SETALLONES: |
| 12819 | case PPC::V_SETALLONESB: |
| 12820 | case PPC::V_SETALLONESH: { |
| 12821 | switch (OpNum) { |
| 12822 | case 0: |
| 12823 | // op: VD |
| 12824 | return 21; |
| 12825 | } |
| 12826 | break; |
| 12827 | } |
| 12828 | case PPC::XSRQPI: |
| 12829 | case PPC::XSRQPIX: |
| 12830 | case PPC::XSRQPXP: { |
| 12831 | switch (OpNum) { |
| 12832 | case 0: |
| 12833 | // op: VRT |
| 12834 | return 21; |
| 12835 | case 1: |
| 12836 | // op: R |
| 12837 | return 16; |
| 12838 | case 2: |
| 12839 | // op: VRB |
| 12840 | return 11; |
| 12841 | case 3: |
| 12842 | // op: idx |
| 12843 | return 9; |
| 12844 | } |
| 12845 | break; |
| 12846 | } |
| 12847 | case PPC::VSLDBI: |
| 12848 | case PPC::VSRDBI: { |
| 12849 | switch (OpNum) { |
| 12850 | case 0: |
| 12851 | // op: VRT |
| 12852 | return 21; |
| 12853 | case 1: |
| 12854 | // op: VRA |
| 12855 | return 16; |
| 12856 | case 2: |
| 12857 | // op: VRB |
| 12858 | return 11; |
| 12859 | case 3: |
| 12860 | // op: SD |
| 12861 | return 6; |
| 12862 | } |
| 12863 | break; |
| 12864 | } |
| 12865 | case PPC::VSTRIBL: |
| 12866 | case PPC::VSTRIBL_rec: |
| 12867 | case PPC::VSTRIBR: |
| 12868 | case PPC::VSTRIBR_rec: |
| 12869 | case PPC::VSTRIHL: |
| 12870 | case PPC::VSTRIHL_rec: |
| 12871 | case PPC::VSTRIHR: |
| 12872 | case PPC::VSTRIHR_rec: { |
| 12873 | switch (OpNum) { |
| 12874 | case 0: |
| 12875 | // op: VT |
| 12876 | return 21; |
| 12877 | case 1: |
| 12878 | // op: VB |
| 12879 | return 11; |
| 12880 | } |
| 12881 | break; |
| 12882 | } |
| 12883 | case PPC::PLXVonlypc: |
| 12884 | case PPC::PSTXVonlypc: { |
| 12885 | switch (OpNum) { |
| 12886 | case 0: |
| 12887 | // op: XST |
| 12888 | return 21; |
| 12889 | case 1: |
| 12890 | // op: D |
| 12891 | return 0; |
| 12892 | } |
| 12893 | break; |
| 12894 | } |
| 12895 | case PPC::PLXV: |
| 12896 | case PPC::PLXVnopc: |
| 12897 | case PPC::PLXVpc: |
| 12898 | case PPC::PSTXV: |
| 12899 | case PPC::PSTXVnopc: |
| 12900 | case PPC::PSTXVpc: { |
| 12901 | switch (OpNum) { |
| 12902 | case 0: |
| 12903 | // op: XST |
| 12904 | return 21; |
| 12905 | case 2: |
| 12906 | // op: RA |
| 12907 | return 16; |
| 12908 | case 1: |
| 12909 | // op: D |
| 12910 | return 0; |
| 12911 | } |
| 12912 | break; |
| 12913 | } |
| 12914 | case PPC::XVTSTDCDP: |
| 12915 | case PPC::XVTSTDCSP: { |
| 12916 | switch (OpNum) { |
| 12917 | case 0: |
| 12918 | // op: XT |
| 12919 | return 0; |
| 12920 | case 1: |
| 12921 | // op: DCMX |
| 12922 | return 2; |
| 12923 | case 2: |
| 12924 | // op: XB |
| 12925 | return 1; |
| 12926 | } |
| 12927 | break; |
| 12928 | } |
| 12929 | case PPC::XXSPLTIB: { |
| 12930 | switch (OpNum) { |
| 12931 | case 0: |
| 12932 | // op: XT |
| 12933 | return 0; |
| 12934 | case 1: |
| 12935 | // op: IMM8 |
| 12936 | return 11; |
| 12937 | } |
| 12938 | break; |
| 12939 | } |
| 12940 | case PPC::LXSDX: |
| 12941 | case PPC::LXSIBZX: |
| 12942 | case PPC::LXSIHZX: |
| 12943 | case PPC::LXSIWAX: |
| 12944 | case PPC::LXSIWZX: |
| 12945 | case PPC::LXSSPX: |
| 12946 | case PPC::LXVB16X: |
| 12947 | case PPC::LXVD2X: |
| 12948 | case PPC::LXVDSX: |
| 12949 | case PPC::LXVH8X: |
| 12950 | case PPC::LXVL: |
| 12951 | case PPC::LXVLL: |
| 12952 | case PPC::LXVRBX: |
| 12953 | case PPC::LXVRDX: |
| 12954 | case PPC::LXVRHX: |
| 12955 | case PPC::LXVRL: |
| 12956 | case PPC::LXVRLL: |
| 12957 | case PPC::LXVRWX: |
| 12958 | case PPC::LXVW4X: |
| 12959 | case PPC::LXVWSX: |
| 12960 | case PPC::LXVX: |
| 12961 | case PPC::MTVSRDD: |
| 12962 | case PPC::STXSDX: |
| 12963 | case PPC::STXSIBX: |
| 12964 | case PPC::STXSIBXv: |
| 12965 | case PPC::STXSIHX: |
| 12966 | case PPC::STXSIHXv: |
| 12967 | case PPC::STXSIWX: |
| 12968 | case PPC::STXSSPX: |
| 12969 | case PPC::STXVB16X: |
| 12970 | case PPC::STXVD2X: |
| 12971 | case PPC::STXVH8X: |
| 12972 | case PPC::STXVL: |
| 12973 | case PPC::STXVLL: |
| 12974 | case PPC::STXVRBX: |
| 12975 | case PPC::STXVRDX: |
| 12976 | case PPC::STXVRHX: |
| 12977 | case PPC::STXVRL: |
| 12978 | case PPC::STXVRLL: |
| 12979 | case PPC::STXVRWX: |
| 12980 | case PPC::STXVW4X: |
| 12981 | case PPC::STXVX: |
| 12982 | case PPC::XSIEXPDP: { |
| 12983 | switch (OpNum) { |
| 12984 | case 0: |
| 12985 | // op: XT |
| 12986 | return 0; |
| 12987 | case 1: |
| 12988 | // op: RA |
| 12989 | return 16; |
| 12990 | case 2: |
| 12991 | // op: RB |
| 12992 | return 11; |
| 12993 | } |
| 12994 | break; |
| 12995 | } |
| 12996 | case PPC::MTVRD: |
| 12997 | case PPC::MTVRWA: |
| 12998 | case PPC::MTVRWZ: |
| 12999 | case PPC::MTVSRD: |
| 13000 | case PPC::MTVSRWA: |
| 13001 | case PPC::MTVSRWS: |
| 13002 | case PPC::MTVSRWZ: { |
| 13003 | switch (OpNum) { |
| 13004 | case 0: |
| 13005 | // op: XT |
| 13006 | return 0; |
| 13007 | case 1: |
| 13008 | // op: RA |
| 13009 | return 16; |
| 13010 | } |
| 13011 | break; |
| 13012 | } |
| 13013 | case PPC::LXVKQ: { |
| 13014 | switch (OpNum) { |
| 13015 | case 0: |
| 13016 | // op: XT |
| 13017 | return 0; |
| 13018 | case 1: |
| 13019 | // op: UIM |
| 13020 | return 11; |
| 13021 | } |
| 13022 | break; |
| 13023 | } |
| 13024 | case PPC::XXGENPCVBM: |
| 13025 | case PPC::XXGENPCVDM: |
| 13026 | case PPC::XXGENPCVHM: |
| 13027 | case PPC::XXGENPCVWM: { |
| 13028 | switch (OpNum) { |
| 13029 | case 0: |
| 13030 | // op: XT |
| 13031 | return 0; |
| 13032 | case 1: |
| 13033 | // op: VRB |
| 13034 | return 11; |
| 13035 | case 2: |
| 13036 | // op: IMM |
| 13037 | return 16; |
| 13038 | } |
| 13039 | break; |
| 13040 | } |
| 13041 | case PPC::XXPERMDIs: |
| 13042 | case PPC::XXSLDWIs: { |
| 13043 | switch (OpNum) { |
| 13044 | case 0: |
| 13045 | // op: XT |
| 13046 | return 0; |
| 13047 | case 1: |
| 13048 | // op: XA |
| 13049 | return 1; |
| 13050 | case 2: |
| 13051 | // op: D |
| 13052 | return 8; |
| 13053 | } |
| 13054 | break; |
| 13055 | } |
| 13056 | case PPC::XXPERMDI: |
| 13057 | case PPC::XXSLDWI: { |
| 13058 | switch (OpNum) { |
| 13059 | case 0: |
| 13060 | // op: XT |
| 13061 | return 0; |
| 13062 | case 1: |
| 13063 | // op: XA |
| 13064 | return 2; |
| 13065 | case 2: |
| 13066 | // op: XB |
| 13067 | return 1; |
| 13068 | case 3: |
| 13069 | // op: D |
| 13070 | return 8; |
| 13071 | } |
| 13072 | break; |
| 13073 | } |
| 13074 | case PPC::XXEVAL: |
| 13075 | case PPC::XXPERMX: { |
| 13076 | switch (OpNum) { |
| 13077 | case 0: |
| 13078 | // op: XT |
| 13079 | return 0; |
| 13080 | case 1: |
| 13081 | // op: XA |
| 13082 | return 2; |
| 13083 | case 2: |
| 13084 | // op: XB |
| 13085 | return 1; |
| 13086 | case 3: |
| 13087 | // op: XC |
| 13088 | return 3; |
| 13089 | case 4: |
| 13090 | // op: IMM |
| 13091 | return 32; |
| 13092 | } |
| 13093 | break; |
| 13094 | } |
| 13095 | case PPC::XXBLENDVB: |
| 13096 | case PPC::XXBLENDVD: |
| 13097 | case PPC::XXBLENDVH: |
| 13098 | case PPC::XXBLENDVW: |
| 13099 | case PPC::XXSEL: { |
| 13100 | switch (OpNum) { |
| 13101 | case 0: |
| 13102 | // op: XT |
| 13103 | return 0; |
| 13104 | case 1: |
| 13105 | // op: XA |
| 13106 | return 2; |
| 13107 | case 2: |
| 13108 | // op: XB |
| 13109 | return 1; |
| 13110 | case 3: |
| 13111 | // op: XC |
| 13112 | return 3; |
| 13113 | } |
| 13114 | break; |
| 13115 | } |
| 13116 | case PPC::XSADDDP: |
| 13117 | case PPC::XSADDSP: |
| 13118 | case PPC::XSCMPEQDP: |
| 13119 | case PPC::XSCMPGEDP: |
| 13120 | case PPC::XSCMPGTDP: |
| 13121 | case PPC::XSCPSGNDP: |
| 13122 | case PPC::XSDIVDP: |
| 13123 | case PPC::XSDIVSP: |
| 13124 | case PPC::XSMAXCDP: |
| 13125 | case PPC::XSMAXDP: |
| 13126 | case PPC::XSMAXJDP: |
| 13127 | case PPC::XSMINCDP: |
| 13128 | case PPC::XSMINDP: |
| 13129 | case PPC::XSMINJDP: |
| 13130 | case PPC::XSMULDP: |
| 13131 | case PPC::XSMULSP: |
| 13132 | case PPC::XSSUBDP: |
| 13133 | case PPC::XSSUBSP: |
| 13134 | case PPC::XVADDDP: |
| 13135 | case PPC::XVADDSP: |
| 13136 | case PPC::XVCMPEQDP: |
| 13137 | case PPC::XVCMPEQDP_rec: |
| 13138 | case PPC::XVCMPEQSP: |
| 13139 | case PPC::XVCMPEQSP_rec: |
| 13140 | case PPC::XVCMPGEDP: |
| 13141 | case PPC::XVCMPGEDP_rec: |
| 13142 | case PPC::XVCMPGESP: |
| 13143 | case PPC::XVCMPGESP_rec: |
| 13144 | case PPC::XVCMPGTDP: |
| 13145 | case PPC::XVCMPGTDP_rec: |
| 13146 | case PPC::XVCMPGTSP: |
| 13147 | case PPC::XVCMPGTSP_rec: |
| 13148 | case PPC::XVCPSGNDP: |
| 13149 | case PPC::XVCPSGNSP: |
| 13150 | case PPC::XVDIVDP: |
| 13151 | case PPC::XVDIVSP: |
| 13152 | case PPC::XVIEXPDP: |
| 13153 | case PPC::XVIEXPSP: |
| 13154 | case PPC::XVMAXDP: |
| 13155 | case PPC::XVMAXSP: |
| 13156 | case PPC::XVMINDP: |
| 13157 | case PPC::XVMINSP: |
| 13158 | case PPC::XVMULDP: |
| 13159 | case PPC::XVMULSP: |
| 13160 | case PPC::XVSUBDP: |
| 13161 | case PPC::XVSUBSP: |
| 13162 | case PPC::XXLAND: |
| 13163 | case PPC::XXLANDC: |
| 13164 | case PPC::XXLEQV: |
| 13165 | case PPC::XXLNAND: |
| 13166 | case PPC::XXLNOR: |
| 13167 | case PPC::XXLOR: |
| 13168 | case PPC::XXLORC: |
| 13169 | case PPC::XXLORf: |
| 13170 | case PPC::XXLXOR: |
| 13171 | case PPC::XXMRGHW: |
| 13172 | case PPC::XXMRGLW: { |
| 13173 | switch (OpNum) { |
| 13174 | case 0: |
| 13175 | // op: XT |
| 13176 | return 0; |
| 13177 | case 1: |
| 13178 | // op: XA |
| 13179 | return 2; |
| 13180 | case 2: |
| 13181 | // op: XB |
| 13182 | return 1; |
| 13183 | } |
| 13184 | break; |
| 13185 | } |
| 13186 | case PPC::XXPERM: |
| 13187 | case PPC::XXPERMR: { |
| 13188 | switch (OpNum) { |
| 13189 | case 0: |
| 13190 | // op: XT |
| 13191 | return 0; |
| 13192 | case 1: |
| 13193 | // op: XA |
| 13194 | return 2; |
| 13195 | case 3: |
| 13196 | // op: XB |
| 13197 | return 1; |
| 13198 | } |
| 13199 | break; |
| 13200 | } |
| 13201 | case PPC::XXSPLTW: |
| 13202 | case PPC::XXSPLTWs: { |
| 13203 | switch (OpNum) { |
| 13204 | case 0: |
| 13205 | // op: XT |
| 13206 | return 0; |
| 13207 | case 1: |
| 13208 | // op: XB |
| 13209 | return 1; |
| 13210 | case 2: |
| 13211 | // op: D |
| 13212 | return 16; |
| 13213 | } |
| 13214 | break; |
| 13215 | } |
| 13216 | case PPC::XXEXTRACTUW: { |
| 13217 | switch (OpNum) { |
| 13218 | case 0: |
| 13219 | // op: XT |
| 13220 | return 0; |
| 13221 | case 1: |
| 13222 | // op: XB |
| 13223 | return 1; |
| 13224 | case 2: |
| 13225 | // op: UIM5 |
| 13226 | return 16; |
| 13227 | } |
| 13228 | break; |
| 13229 | } |
| 13230 | case PPC::XSABSDP: |
| 13231 | case PPC::XSCVDPHP: |
| 13232 | case PPC::XSCVDPSP: |
| 13233 | case PPC::XSCVDPSPN: |
| 13234 | case PPC::XSCVDPSXDS: |
| 13235 | case PPC::XSCVDPSXDSs: |
| 13236 | case PPC::XSCVDPSXWS: |
| 13237 | case PPC::XSCVDPSXWSs: |
| 13238 | case PPC::XSCVDPUXDS: |
| 13239 | case PPC::XSCVDPUXDSs: |
| 13240 | case PPC::XSCVDPUXWS: |
| 13241 | case PPC::XSCVDPUXWSs: |
| 13242 | case PPC::XSCVHPDP: |
| 13243 | case PPC::XSCVSPDP: |
| 13244 | case PPC::XSCVSPDPN: |
| 13245 | case PPC::XSCVSXDDP: |
| 13246 | case PPC::XSCVSXDSP: |
| 13247 | case PPC::XSCVUXDDP: |
| 13248 | case PPC::XSCVUXDSP: |
| 13249 | case PPC::XSNABSDP: |
| 13250 | case PPC::XSNABSDPs: |
| 13251 | case PPC::XSNEGDP: |
| 13252 | case PPC::XSRDPI: |
| 13253 | case PPC::XSRDPIC: |
| 13254 | case PPC::XSRDPIM: |
| 13255 | case PPC::XSRDPIP: |
| 13256 | case PPC::XSRDPIZ: |
| 13257 | case PPC::XSREDP: |
| 13258 | case PPC::XSRESP: |
| 13259 | case PPC::XSRSP: |
| 13260 | case PPC::XSRSQRTEDP: |
| 13261 | case PPC::XSRSQRTESP: |
| 13262 | case PPC::XSSQRTDP: |
| 13263 | case PPC::XSSQRTSP: |
| 13264 | case PPC::XVABSDP: |
| 13265 | case PPC::XVABSSP: |
| 13266 | case PPC::XVCVBF16SPN: |
| 13267 | case PPC::XVCVDPSP: |
| 13268 | case PPC::XVCVDPSXDS: |
| 13269 | case PPC::XVCVDPSXWS: |
| 13270 | case PPC::XVCVDPUXDS: |
| 13271 | case PPC::XVCVDPUXWS: |
| 13272 | case PPC::XVCVHPSP: |
| 13273 | case PPC::XVCVSPBF16: |
| 13274 | case PPC::XVCVSPDP: |
| 13275 | case PPC::XVCVSPHP: |
| 13276 | case PPC::XVCVSPSXDS: |
| 13277 | case PPC::XVCVSPSXWS: |
| 13278 | case PPC::XVCVSPUXDS: |
| 13279 | case PPC::XVCVSPUXWS: |
| 13280 | case PPC::XVCVSXDDP: |
| 13281 | case PPC::XVCVSXDSP: |
| 13282 | case PPC::XVCVSXWDP: |
| 13283 | case PPC::XVCVSXWSP: |
| 13284 | case PPC::XVCVUXDDP: |
| 13285 | case PPC::XVCVUXDSP: |
| 13286 | case PPC::XVCVUXWDP: |
| 13287 | case PPC::XVCVUXWSP: |
| 13288 | case PPC::XVNABSDP: |
| 13289 | case PPC::XVNABSSP: |
| 13290 | case PPC::XVNEGDP: |
| 13291 | case PPC::XVNEGSP: |
| 13292 | case PPC::XVRDPI: |
| 13293 | case PPC::XVRDPIC: |
| 13294 | case PPC::XVRDPIM: |
| 13295 | case PPC::XVRDPIP: |
| 13296 | case PPC::XVRDPIZ: |
| 13297 | case PPC::XVREDP: |
| 13298 | case PPC::XVRESP: |
| 13299 | case PPC::XVRSPI: |
| 13300 | case PPC::XVRSPIC: |
| 13301 | case PPC::XVRSPIM: |
| 13302 | case PPC::XVRSPIP: |
| 13303 | case PPC::XVRSPIZ: |
| 13304 | case PPC::XVRSQRTEDP: |
| 13305 | case PPC::XVRSQRTESP: |
| 13306 | case PPC::XVSQRTDP: |
| 13307 | case PPC::XVSQRTSP: |
| 13308 | case PPC::XVXEXPDP: |
| 13309 | case PPC::XVXEXPSP: |
| 13310 | case PPC::XVXSIGDP: |
| 13311 | case PPC::XVXSIGSP: |
| 13312 | case PPC::XXBRD: |
| 13313 | case PPC::XXBRH: |
| 13314 | case PPC::XXBRQ: |
| 13315 | case PPC::XXBRW: { |
| 13316 | switch (OpNum) { |
| 13317 | case 0: |
| 13318 | // op: XT |
| 13319 | return 0; |
| 13320 | case 1: |
| 13321 | // op: XB |
| 13322 | return 1; |
| 13323 | } |
| 13324 | break; |
| 13325 | } |
| 13326 | case PPC::XSMADDADP: |
| 13327 | case PPC::XSMADDASP: |
| 13328 | case PPC::XSMADDMDP: |
| 13329 | case PPC::XSMADDMSP: |
| 13330 | case PPC::XSMSUBADP: |
| 13331 | case PPC::XSMSUBASP: |
| 13332 | case PPC::XSMSUBMDP: |
| 13333 | case PPC::XSMSUBMSP: |
| 13334 | case PPC::XSNMADDADP: |
| 13335 | case PPC::XSNMADDASP: |
| 13336 | case PPC::XSNMADDMDP: |
| 13337 | case PPC::XSNMADDMSP: |
| 13338 | case PPC::XSNMSUBADP: |
| 13339 | case PPC::XSNMSUBASP: |
| 13340 | case PPC::XSNMSUBMDP: |
| 13341 | case PPC::XSNMSUBMSP: |
| 13342 | case PPC::XVMADDADP: |
| 13343 | case PPC::XVMADDASP: |
| 13344 | case PPC::XVMADDMDP: |
| 13345 | case PPC::XVMADDMSP: |
| 13346 | case PPC::XVMSUBADP: |
| 13347 | case PPC::XVMSUBASP: |
| 13348 | case PPC::XVMSUBMDP: |
| 13349 | case PPC::XVMSUBMSP: |
| 13350 | case PPC::XVNMADDADP: |
| 13351 | case PPC::XVNMADDASP: |
| 13352 | case PPC::XVNMADDMDP: |
| 13353 | case PPC::XVNMADDMSP: |
| 13354 | case PPC::XVNMSUBADP: |
| 13355 | case PPC::XVNMSUBASP: |
| 13356 | case PPC::XVNMSUBMDP: |
| 13357 | case PPC::XVNMSUBMSP: { |
| 13358 | switch (OpNum) { |
| 13359 | case 0: |
| 13360 | // op: XT |
| 13361 | return 0; |
| 13362 | case 2: |
| 13363 | // op: XA |
| 13364 | return 2; |
| 13365 | case 3: |
| 13366 | // op: XB |
| 13367 | return 1; |
| 13368 | } |
| 13369 | break; |
| 13370 | } |
| 13371 | case PPC::XXINSERTW: { |
| 13372 | switch (OpNum) { |
| 13373 | case 0: |
| 13374 | // op: XT |
| 13375 | return 0; |
| 13376 | case 2: |
| 13377 | // op: XB |
| 13378 | return 1; |
| 13379 | case 3: |
| 13380 | // op: UIM5 |
| 13381 | return 16; |
| 13382 | } |
| 13383 | break; |
| 13384 | } |
| 13385 | case PPC::XXLEQVOnes: |
| 13386 | case PPC::XXLXORdpz: |
| 13387 | case PPC::XXLXORspz: |
| 13388 | case PPC::XXLXORz: { |
| 13389 | switch (OpNum) { |
| 13390 | case 0: |
| 13391 | // op: XT |
| 13392 | return 0; |
| 13393 | } |
| 13394 | break; |
| 13395 | } |
| 13396 | case PPC::XXSPLTIDP: |
| 13397 | case PPC::XXSPLTIW: { |
| 13398 | switch (OpNum) { |
| 13399 | case 0: |
| 13400 | // op: XT |
| 13401 | return 16; |
| 13402 | case 1: |
| 13403 | // op: IMM32 |
| 13404 | return 0; |
| 13405 | } |
| 13406 | break; |
| 13407 | } |
| 13408 | case PPC::XXSPLTI32DX: { |
| 13409 | switch (OpNum) { |
| 13410 | case 0: |
| 13411 | // op: XT |
| 13412 | return 16; |
| 13413 | case 2: |
| 13414 | // op: IX |
| 13415 | return 17; |
| 13416 | case 3: |
| 13417 | // op: IMM32 |
| 13418 | return 0; |
| 13419 | } |
| 13420 | break; |
| 13421 | } |
| 13422 | case PPC::LXV: |
| 13423 | case PPC::STXV: { |
| 13424 | switch (OpNum) { |
| 13425 | case 0: |
| 13426 | // op: XT |
| 13427 | return 3; |
| 13428 | case 2: |
| 13429 | // op: RA |
| 13430 | return 16; |
| 13431 | case 1: |
| 13432 | // op: DQ |
| 13433 | return 4; |
| 13434 | } |
| 13435 | break; |
| 13436 | } |
| 13437 | case PPC::PLXVPonlypc: |
| 13438 | case PPC::PSTXVPonlypc: { |
| 13439 | switch (OpNum) { |
| 13440 | case 0: |
| 13441 | // op: XTp |
| 13442 | return 21; |
| 13443 | case 1: |
| 13444 | // op: D |
| 13445 | return 0; |
| 13446 | } |
| 13447 | break; |
| 13448 | } |
| 13449 | case PPC::LXVPRL: |
| 13450 | case PPC::LXVPRLL: |
| 13451 | case PPC::LXVPX: |
| 13452 | case PPC::STXVPRL: |
| 13453 | case PPC::STXVPRLL: |
| 13454 | case PPC::STXVPX: { |
| 13455 | switch (OpNum) { |
| 13456 | case 0: |
| 13457 | // op: XTp |
| 13458 | return 21; |
| 13459 | case 1: |
| 13460 | // op: RA |
| 13461 | return 16; |
| 13462 | case 2: |
| 13463 | // op: RB |
| 13464 | return 11; |
| 13465 | } |
| 13466 | break; |
| 13467 | } |
| 13468 | case PPC::PLXVP: |
| 13469 | case PPC::PLXVPnopc: |
| 13470 | case PPC::PLXVPpc: |
| 13471 | case PPC::PSTXVP: |
| 13472 | case PPC::PSTXVPnopc: |
| 13473 | case PPC::PSTXVPpc: { |
| 13474 | switch (OpNum) { |
| 13475 | case 0: |
| 13476 | // op: XTp |
| 13477 | return 21; |
| 13478 | case 2: |
| 13479 | // op: RA |
| 13480 | return 16; |
| 13481 | case 1: |
| 13482 | // op: D |
| 13483 | return 0; |
| 13484 | } |
| 13485 | break; |
| 13486 | } |
| 13487 | case PPC::LXVP: |
| 13488 | case PPC::STXVP: { |
| 13489 | switch (OpNum) { |
| 13490 | case 0: |
| 13491 | // op: XTp |
| 13492 | return 21; |
| 13493 | case 2: |
| 13494 | // op: RA |
| 13495 | return 16; |
| 13496 | case 1: |
| 13497 | // op: DQ |
| 13498 | return 4; |
| 13499 | } |
| 13500 | break; |
| 13501 | } |
| 13502 | case PPC::EFDCMPEQ: |
| 13503 | case PPC::EFDCMPGT: |
| 13504 | case PPC::EFDCMPLT: |
| 13505 | case PPC::EFDTSTEQ: |
| 13506 | case PPC::EFDTSTGT: |
| 13507 | case PPC::EFDTSTLT: |
| 13508 | case PPC::EFSCMPEQ: |
| 13509 | case PPC::EFSCMPGT: |
| 13510 | case PPC::EFSCMPLT: |
| 13511 | case PPC::EFSTSTEQ: |
| 13512 | case PPC::EFSTSTGT: |
| 13513 | case PPC::EFSTSTLT: |
| 13514 | case PPC::EVCMPEQ: |
| 13515 | case PPC::EVCMPGTS: |
| 13516 | case PPC::EVCMPGTU: |
| 13517 | case PPC::EVCMPLTS: |
| 13518 | case PPC::EVCMPLTU: |
| 13519 | case PPC::EVFSCMPEQ: |
| 13520 | case PPC::EVFSCMPGT: |
| 13521 | case PPC::EVFSCMPLT: |
| 13522 | case PPC::EVFSTSTEQ: |
| 13523 | case PPC::EVFSTSTGT: |
| 13524 | case PPC::EVFSTSTLT: { |
| 13525 | switch (OpNum) { |
| 13526 | case 0: |
| 13527 | // op: crD |
| 13528 | return 23; |
| 13529 | case 1: |
| 13530 | // op: RA |
| 13531 | return 16; |
| 13532 | case 2: |
| 13533 | // op: RB |
| 13534 | return 11; |
| 13535 | } |
| 13536 | break; |
| 13537 | } |
| 13538 | case PPC::DMXXEXTFDMR256: { |
| 13539 | switch (OpNum) { |
| 13540 | case 1: |
| 13541 | // op: AT |
| 13542 | return 23; |
| 13543 | case 0: |
| 13544 | // op: XBp |
| 13545 | return 1; |
| 13546 | case 2: |
| 13547 | // op: P |
| 13548 | return 11; |
| 13549 | } |
| 13550 | break; |
| 13551 | } |
| 13552 | case PPC::XXMFACC: |
| 13553 | case PPC::XXMFACCW: { |
| 13554 | switch (OpNum) { |
| 13555 | case 1: |
| 13556 | // op: AT |
| 13557 | return 23; |
| 13558 | } |
| 13559 | break; |
| 13560 | } |
| 13561 | case PPC::BCTRL_LWZinto_toc: |
| 13562 | case PPC::BCTRL_LWZinto_toc_RM: { |
| 13563 | switch (OpNum) { |
| 13564 | case 1: |
| 13565 | // op: RA |
| 13566 | return 16; |
| 13567 | case 0: |
| 13568 | // op: D |
| 13569 | return 0; |
| 13570 | } |
| 13571 | break; |
| 13572 | } |
| 13573 | case PPC::BCTRL8_LDinto_toc: |
| 13574 | case PPC::BCTRL8_LDinto_toc_RM: { |
| 13575 | switch (OpNum) { |
| 13576 | case 1: |
| 13577 | // op: RA |
| 13578 | return 16; |
| 13579 | case 0: |
| 13580 | // op: D |
| 13581 | return 2; |
| 13582 | } |
| 13583 | break; |
| 13584 | } |
| 13585 | case PPC::TLBILX: { |
| 13586 | switch (OpNum) { |
| 13587 | case 1: |
| 13588 | // op: RA |
| 13589 | return 16; |
| 13590 | case 2: |
| 13591 | // op: RB |
| 13592 | return 11; |
| 13593 | case 0: |
| 13594 | // op: T |
| 13595 | return 21; |
| 13596 | } |
| 13597 | break; |
| 13598 | } |
| 13599 | case PPC::MTOCRF: |
| 13600 | case PPC::MTOCRF8: { |
| 13601 | switch (OpNum) { |
| 13602 | case 1: |
| 13603 | // op: RST |
| 13604 | return 21; |
| 13605 | case 0: |
| 13606 | // op: FXM |
| 13607 | return 12; |
| 13608 | } |
| 13609 | break; |
| 13610 | } |
| 13611 | case PPC::MTPMR: |
| 13612 | case PPC::MTSPR: |
| 13613 | case PPC::MTSPR8: { |
| 13614 | switch (OpNum) { |
| 13615 | case 1: |
| 13616 | // op: RST |
| 13617 | return 21; |
| 13618 | case 0: |
| 13619 | // op: SPR |
| 13620 | return 11; |
| 13621 | } |
| 13622 | break; |
| 13623 | } |
| 13624 | case PPC::STBUX: |
| 13625 | case PPC::STBUX8: |
| 13626 | case PPC::STDUX: |
| 13627 | case PPC::STFDUX: |
| 13628 | case PPC::STFSUX: |
| 13629 | case PPC::STHUX: |
| 13630 | case PPC::STHUX8: |
| 13631 | case PPC::STWUX: |
| 13632 | case PPC::STWUX8: { |
| 13633 | switch (OpNum) { |
| 13634 | case 1: |
| 13635 | // op: RST |
| 13636 | return 21; |
| 13637 | case 2: |
| 13638 | // op: RA |
| 13639 | return 16; |
| 13640 | case 3: |
| 13641 | // op: RB |
| 13642 | return 11; |
| 13643 | } |
| 13644 | break; |
| 13645 | } |
| 13646 | case PPC::STBU: |
| 13647 | case PPC::STBU8: |
| 13648 | case PPC::STFDU: |
| 13649 | case PPC::STFSU: |
| 13650 | case PPC::STHU: |
| 13651 | case PPC::STHU8: |
| 13652 | case PPC::STWU: |
| 13653 | case PPC::STWU8: { |
| 13654 | switch (OpNum) { |
| 13655 | case 1: |
| 13656 | // op: RST |
| 13657 | return 21; |
| 13658 | case 3: |
| 13659 | // op: RA |
| 13660 | return 16; |
| 13661 | case 2: |
| 13662 | // op: D |
| 13663 | return 0; |
| 13664 | } |
| 13665 | break; |
| 13666 | } |
| 13667 | case PPC::STDU: { |
| 13668 | switch (OpNum) { |
| 13669 | case 1: |
| 13670 | // op: RST |
| 13671 | return 21; |
| 13672 | case 3: |
| 13673 | // op: RA |
| 13674 | return 16; |
| 13675 | case 2: |
| 13676 | // op: D |
| 13677 | return 2; |
| 13678 | } |
| 13679 | break; |
| 13680 | } |
| 13681 | case PPC::MTVRSAVEv: { |
| 13682 | switch (OpNum) { |
| 13683 | case 1: |
| 13684 | // op: RST |
| 13685 | return 21; |
| 13686 | } |
| 13687 | break; |
| 13688 | } |
| 13689 | case PPC::DENBCD: |
| 13690 | case PPC::DENBCDQ: |
| 13691 | case PPC::DENBCDQ_rec: |
| 13692 | case PPC::DENBCD_rec: { |
| 13693 | switch (OpNum) { |
| 13694 | case 1: |
| 13695 | // op: S |
| 13696 | return 20; |
| 13697 | case 0: |
| 13698 | // op: FRT |
| 13699 | return 21; |
| 13700 | case 2: |
| 13701 | // op: FRB |
| 13702 | return 11; |
| 13703 | } |
| 13704 | break; |
| 13705 | } |
| 13706 | case PPC::DDEDPD: |
| 13707 | case PPC::DDEDPDQ: |
| 13708 | case PPC::DDEDPDQ_rec: |
| 13709 | case PPC::DDEDPD_rec: { |
| 13710 | switch (OpNum) { |
| 13711 | case 1: |
| 13712 | // op: SP |
| 13713 | return 19; |
| 13714 | case 0: |
| 13715 | // op: FRT |
| 13716 | return 21; |
| 13717 | case 2: |
| 13718 | // op: FRB |
| 13719 | return 11; |
| 13720 | } |
| 13721 | break; |
| 13722 | } |
| 13723 | case PPC::MFVRD: |
| 13724 | case PPC::MFVRWZ: |
| 13725 | case PPC::MFVSRD: |
| 13726 | case PPC::MFVSRLD: |
| 13727 | case PPC::MFVSRWZ: { |
| 13728 | switch (OpNum) { |
| 13729 | case 1: |
| 13730 | // op: XT |
| 13731 | return 0; |
| 13732 | case 0: |
| 13733 | // op: RA |
| 13734 | return 16; |
| 13735 | } |
| 13736 | break; |
| 13737 | } |
| 13738 | case PPC::DMXXEXTFDMR512: |
| 13739 | case PPC::DMXXEXTFDMR512_HI: { |
| 13740 | switch (OpNum) { |
| 13741 | case 2: |
| 13742 | // op: AT |
| 13743 | return 23; |
| 13744 | case 0: |
| 13745 | // op: XAp |
| 13746 | return 2; |
| 13747 | case 1: |
| 13748 | // op: XBp |
| 13749 | return 1; |
| 13750 | } |
| 13751 | break; |
| 13752 | } |
| 13753 | case PPC::CP_PASTE8_rec: |
| 13754 | case PPC::CP_PASTE_rec: { |
| 13755 | switch (OpNum) { |
| 13756 | case 2: |
| 13757 | // op: L |
| 13758 | return 21; |
| 13759 | case 0: |
| 13760 | // op: RA |
| 13761 | return 16; |
| 13762 | case 1: |
| 13763 | // op: RB |
| 13764 | return 11; |
| 13765 | } |
| 13766 | break; |
| 13767 | } |
| 13768 | case PPC::MTFSF: |
| 13769 | case PPC::MTFSF_rec: { |
| 13770 | switch (OpNum) { |
| 13771 | case 2: |
| 13772 | // op: L |
| 13773 | return 25; |
| 13774 | case 0: |
| 13775 | // op: FLM |
| 13776 | return 17; |
| 13777 | case 3: |
| 13778 | // op: W |
| 13779 | return 16; |
| 13780 | case 1: |
| 13781 | // op: FRB |
| 13782 | return 11; |
| 13783 | } |
| 13784 | break; |
| 13785 | } |
| 13786 | case PPC::HASHCHK: |
| 13787 | case PPC::HASHCHK8: |
| 13788 | case PPC::HASHCHKP: |
| 13789 | case PPC::HASHCHKP8: |
| 13790 | case PPC::HASHST: |
| 13791 | case PPC::HASHST8: |
| 13792 | case PPC::HASHSTP: |
| 13793 | case PPC::HASHSTP8: { |
| 13794 | switch (OpNum) { |
| 13795 | case 2: |
| 13796 | // op: RA |
| 13797 | return 16; |
| 13798 | case 1: |
| 13799 | // op: D |
| 13800 | return 0; |
| 13801 | case 0: |
| 13802 | // op: RB |
| 13803 | return 11; |
| 13804 | } |
| 13805 | break; |
| 13806 | } |
| 13807 | case PPC::DCBTEP: |
| 13808 | case PPC::DCBTSTEP: { |
| 13809 | switch (OpNum) { |
| 13810 | case 2: |
| 13811 | // op: TH |
| 13812 | return 21; |
| 13813 | case 0: |
| 13814 | // op: RA |
| 13815 | return 16; |
| 13816 | case 1: |
| 13817 | // op: RB |
| 13818 | return 11; |
| 13819 | } |
| 13820 | break; |
| 13821 | } |
| 13822 | case PPC::EVSEL: { |
| 13823 | switch (OpNum) { |
| 13824 | case 3: |
| 13825 | // op: crD |
| 13826 | return 0; |
| 13827 | case 1: |
| 13828 | // op: RA |
| 13829 | return 16; |
| 13830 | case 2: |
| 13831 | // op: RB |
| 13832 | return 11; |
| 13833 | case 0: |
| 13834 | // op: RT |
| 13835 | return 21; |
| 13836 | } |
| 13837 | break; |
| 13838 | } |
| 13839 | } |
| 13840 | std::string msg; |
| 13841 | raw_string_ostream Msg(msg); |
| 13842 | Msg << "Not supported instr[opcode]: " << MI << "[" << OpNum << "]" ; |
| 13843 | report_fatal_error(Msg.str().c_str()); |
| 13844 | } |
| 13845 | |
| 13846 | #endif // GET_OPERAND_BIT_OFFSET |
| 13847 | |
| 13848 | |