1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Register Bank Source Fragments *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_REGBANK_DECLARATIONS
10#undef GET_REGBANK_DECLARATIONS
11namespace llvm {
12namespace PPC {
13enum : unsigned {
14 InvalidRegBankID = ~0u,
15 CRRegBankID = 0,
16 FPRRegBankID = 1,
17 GPRRegBankID = 2,
18 VECRegBankID = 3,
19 NumRegisterBanks,
20};
21} // end namespace PPC
22} // end namespace llvm
23#endif // GET_REGBANK_DECLARATIONS
24
25#ifdef GET_TARGET_REGBANK_CLASS
26#undef GET_TARGET_REGBANK_CLASS
27private:
28 static const RegisterBank *RegBanks[];
29 static const unsigned Sizes[];
30
31public:
32 const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC, LLT Ty) const override;
33protected:
34 PPCGenRegisterBankInfo(unsigned HwMode = 0);
35
36#endif // GET_TARGET_REGBANK_CLASS
37
38#ifdef GET_TARGET_REGBANK_IMPL
39#undef GET_TARGET_REGBANK_IMPL
40namespace llvm {
41namespace PPC {
42const uint32_t CRRegBankCoverageData[] = {
43 // 0-31
44 (1u << (PPC::CRRCRegClassID - 0)) |
45 (1u << (PPC::CRBITRCRegClassID - 0)) |
46 0,
47 // 32-63
48 0,
49};
50const uint32_t FPRRegBankCoverageData[] = {
51 // 0-31
52 (1u << (PPC::VSSRCRegClassID - 0)) |
53 (1u << (PPC::F4RCRegClassID - 0)) |
54 (1u << (PPC::F8RCRegClassID - 0)) |
55 (1u << (PPC::SPILLTOVSRRC_and_F4RCRegClassID - 0)) |
56 (1u << (PPC::VSFRCRegClassID - 0)) |
57 (1u << (PPC::SPILLTOVSRRC_and_VSFRCRegClassID - 0)) |
58 (1u << (PPC::SPILLTOVSRRC_and_VFRCRegClassID - 0)) |
59 (1u << (PPC::VFRCRegClassID - 0)) |
60 0,
61 // 32-63
62 0,
63};
64const uint32_t GPRRegBankCoverageData[] = {
65 // 0-31
66 (1u << (PPC::G8RCRegClassID - 0)) |
67 (1u << (PPC::GPRCRegClassID - 0)) |
68 (1u << (PPC::G8RC_and_G8RC_NOX0RegClassID - 0)) |
69 (1u << (PPC::GPRC_NOR0RegClassID - 0)) |
70 (1u << (PPC::GPRC_and_GPRC_NOR0RegClassID - 0)) |
71 (1u << (PPC::G8RC_NOX0RegClassID - 0)) |
72 0,
73 // 32-63
74 0,
75};
76const uint32_t VECRegBankCoverageData[] = {
77 // 0-31
78 (1u << (PPC::VSRCRegClassID - 0)) |
79 (1u << (PPC::VSSRCRegClassID - 0)) |
80 (1u << (PPC::VSFRCRegClassID - 0)) |
81 (1u << (PPC::VSRC_with_sub_64_in_SPILLTOVSRRCRegClassID - 0)) |
82 (1u << (PPC::SPILLTOVSRRCRegClassID - 0)) |
83 (1u << (PPC::SPILLTOVSRRC_and_VSFRCRegClassID - 0)) |
84 (1u << (PPC::VFRCRegClassID - 0)) |
85 (1u << (PPC::SPILLTOVSRRC_and_VFRCRegClassID - 0)) |
86 (1u << (PPC::F4RCRegClassID - 0)) |
87 (1u << (PPC::F8RCRegClassID - 0)) |
88 (1u << (PPC::SPILLTOVSRRC_and_F4RCRegClassID - 0)) |
89 (1u << (PPC::VRRCRegClassID - 0)) |
90 0,
91 // 32-63
92 (1u << (PPC::VRRC_with_sub_64_in_SPILLTOVSRRCRegClassID - 32)) |
93 (1u << (PPC::VSLRC_with_sub_64_in_SPILLTOVSRRCRegClassID - 32)) |
94 (1u << (PPC::VSLRCRegClassID - 32)) |
95 0,
96};
97
98constexpr RegisterBank CRRegBank(/* ID */ PPC::CRRegBankID, /* Name */ "CR", /* CoveredRegClasses */ CRRegBankCoverageData, /* NumRegClasses */ 56);
99constexpr RegisterBank FPRRegBank(/* ID */ PPC::FPRRegBankID, /* Name */ "FPR", /* CoveredRegClasses */ FPRRegBankCoverageData, /* NumRegClasses */ 56);
100constexpr RegisterBank GPRRegBank(/* ID */ PPC::GPRRegBankID, /* Name */ "GPR", /* CoveredRegClasses */ GPRRegBankCoverageData, /* NumRegClasses */ 56);
101constexpr RegisterBank VECRegBank(/* ID */ PPC::VECRegBankID, /* Name */ "VEC", /* CoveredRegClasses */ VECRegBankCoverageData, /* NumRegClasses */ 56);
102} // end namespace PPC
103
104const RegisterBank *PPCGenRegisterBankInfo::RegBanks[] = {
105 &PPC::CRRegBank,
106 &PPC::FPRRegBank,
107 &PPC::GPRRegBank,
108 &PPC::VECRegBank,
109};
110
111const unsigned PPCGenRegisterBankInfo::Sizes[] = {
112 // Mode = 0 (Default)
113 32,
114 64,
115 64,
116 128,
117};
118
119PPCGenRegisterBankInfo::PPCGenRegisterBankInfo(unsigned HwMode)
120 : RegisterBankInfo(RegBanks, PPC::NumRegisterBanks, Sizes, HwMode) {
121 // Assert that RegBank indices match their ID's
122#ifndef NDEBUG
123 for (auto RB : enumerate(RegBanks))
124 assert(RB.index() == RB.value()->getID() && "Index != ID");
125#endif // NDEBUG
126}
127const RegisterBank &
128PPCGenRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC, LLT) const {
129 constexpr uint32_t InvalidRegBankID = uint32_t(PPC::InvalidRegBankID) & 15;
130 static const uint32_t RegClass2RegBank[5] = {
131 (uint32_t(InvalidRegBankID) << 0) | // VSSRCRegClassID
132 (uint32_t(PPC::GPRRegBankID) << 4) | // GPRCRegClassID
133 (uint32_t(PPC::GPRRegBankID) << 8) | // GPRC_NOR0RegClassID
134 (uint32_t(PPC::GPRRegBankID) << 12) | // GPRC_and_GPRC_NOR0RegClassID
135 (uint32_t(PPC::CRRegBankID) << 16) | // CRBITRCRegClassID
136 (uint32_t(InvalidRegBankID) << 20) | // F4RCRegClassID
137 (uint32_t(InvalidRegBankID) << 24) |
138 (uint32_t(PPC::CRRegBankID) << 28), // CRRCRegClassID
139 (uint32_t(InvalidRegBankID) << 0) |
140 (uint32_t(InvalidRegBankID) << 4) |
141 (uint32_t(InvalidRegBankID) << 8) |
142 (uint32_t(InvalidRegBankID) << 12) |
143 (uint32_t(PPC::VECRegBankID) << 16) | // SPILLTOVSRRCRegClassID
144 (uint32_t(InvalidRegBankID) << 20) | // VSFRCRegClassID
145 (uint32_t(PPC::GPRRegBankID) << 24) | // G8RCRegClassID
146 (uint32_t(PPC::GPRRegBankID) << 28), // G8RC_NOX0RegClassID
147 (uint32_t(InvalidRegBankID) << 0) | // SPILLTOVSRRC_and_VSFRCRegClassID
148 (uint32_t(PPC::GPRRegBankID) << 4) | // G8RC_and_G8RC_NOX0RegClassID
149 (uint32_t(InvalidRegBankID) << 8) | // F8RCRegClassID
150 (uint32_t(InvalidRegBankID) << 12) |
151 (uint32_t(InvalidRegBankID) << 16) |
152 (uint32_t(InvalidRegBankID) << 20) |
153 (uint32_t(InvalidRegBankID) << 24) | // VFRCRegClassID
154 (uint32_t(InvalidRegBankID) << 28),
155 (uint32_t(InvalidRegBankID) << 0) | // SPILLTOVSRRC_and_VFRCRegClassID
156 (uint32_t(InvalidRegBankID) << 4) | // SPILLTOVSRRC_and_F4RCRegClassID
157 (uint32_t(InvalidRegBankID) << 8) |
158 (uint32_t(InvalidRegBankID) << 12) |
159 (uint32_t(InvalidRegBankID) << 16) |
160 (uint32_t(PPC::VECRegBankID) << 20) | // VSRCRegClassID
161 (uint32_t(PPC::VECRegBankID) << 24) | // VSRC_with_sub_64_in_SPILLTOVSRRCRegClassID
162 (uint32_t(PPC::VECRegBankID) << 28), // VRRCRegClassID
163 (uint32_t(PPC::VECRegBankID) << 0) | // VSLRCRegClassID
164 (uint32_t(PPC::VECRegBankID) << 4) | // VRRC_with_sub_64_in_SPILLTOVSRRCRegClassID
165 (uint32_t(InvalidRegBankID) << 8) |
166 (uint32_t(InvalidRegBankID) << 12) |
167 (uint32_t(InvalidRegBankID) << 16) |
168 (uint32_t(PPC::VECRegBankID) << 20) // VSLRC_with_sub_64_in_SPILLTOVSRRCRegClassID
169 };
170 const unsigned RegClassID = RC.getID();
171 if (LLVM_LIKELY(RegClassID < 38)) {
172 unsigned RegBankID = (RegClass2RegBank[RegClassID / 8] >> ((RegClassID % 8) * 4)) & 15;
173 if (RegBankID != InvalidRegBankID)
174 return getRegBank(RegBankID);
175 }
176 llvm_unreachable(llvm::Twine("Target needs to handle register class ID 0x").concat(llvm::Twine::utohexstr(RegClassID)).str().c_str());
177}
178} // end namespace llvm
179#endif // GET_TARGET_REGBANK_IMPL
180