RISCVGenCompressInstEmitter.inc source code [llvm_projects/build/lib/Target/RISCV/RISCVGenCompressInstEmitter.inc]

1	/===- TableGen'erated file -------------------------------------- C++ --===\
2	\| \|
3	\| Compress instruction Source Fragment \|
4	\| \|
5	\| Automatically generated file, do not edit! \|
6	\| From: RISCV.td \|
7	\| \|
8	\===----------------------------------------------------------------------===/
9
10
11	#ifdef GEN_COMPRESS_INSTR
12	#undef GEN_COMPRESS_INSTR
13
14	static bool RISCVValidateMCOperandForCompress(const MCOperand &MCOp,
15	const MCSubtargetInfo &STI,
16	unsigned PredicateIndex) {
17	switch (PredicateIndex) {
18	default:
19	llvm_unreachable("Unknown MCOperandPredicate kind");
20	break;
21	case `1`: {
22	// uimm10_lsb00nonzero
23	int64_t Imm;
24	if (!MCOp.evaluateAsConstantImm(Imm))
25	return false;
26	return isShiftedUInt<`8`, `2`>(x: Imm) && (Imm != `0`);
27	}
28	case `2`: {
29	// simm6nonzero
30	int64_t Imm;
31	if (MCOp.evaluateAsConstantImm(Imm))
32	return (Imm != `0`) && isInt<`6`>(x: Imm);
33	return MCOp.isBareSymbolRef();
34	}
35	case `3`: {
36	// simm6
37	int64_t Imm;
38	if (MCOp.evaluateAsConstantImm(Imm))
39	return isInt<`6`>(x: Imm);
40	return MCOp.isBareSymbolRef();
41	}
42	case `4`: {
43	// simm10_lsb0000nonzero
44	int64_t Imm;
45	if (!MCOp.evaluateAsConstantImm(Imm))
46	return false;
47	return isShiftedInt<`6`, `4`>(x: Imm) && (Imm != `0`);
48	}
49	case `5`: {
50	// bare_simm9_lsb0
51	int64_t Imm;
52	if (MCOp.evaluateAsConstantImm(Imm))
53	return isShiftedInt<`8`, `1`>(x: Imm);
54	return MCOp.isBareSymbolRef();
55	}
56	case `6`: {
57	// uimmlog2xlennonzero
58	int64_t Imm;
59	if (!MCOp.evaluateAsConstantImm(Imm))
60	return false;
61	if (STI.getTargetTriple().isArch64Bit())
62	return isUInt<`6`>(x: Imm) && (Imm != `0`);
63	return isUInt<`5`>(x: Imm) && (Imm != `0`);
64	}
65	case `7`: {
66	// uimm8_lsb000
67	int64_t Imm;
68	if (!MCOp.evaluateAsConstantImm(Imm))
69	return false;
70	return isShiftedUInt<`5`, `3`>(x: Imm);
71	}
72	case `8`: {
73	// uimm9_lsb000
74	int64_t Imm;
75	if (!MCOp.evaluateAsConstantImm(Imm))
76	return false;
77	return isShiftedUInt<`6`, `3`>(x: Imm);
78	}
79	case `9`: {
80	// uimm7_lsb00
81	int64_t Imm;
82	if (!MCOp.evaluateAsConstantImm(Imm))
83	return false;
84	return isShiftedUInt<`5`, `2`>(x: Imm);
85	}
86	case `10`: {
87	// uimm8_lsb00
88	int64_t Imm;
89	if (!MCOp.evaluateAsConstantImm(Imm))
90	return false;
91	return isShiftedUInt<`6`, `2`>(x: Imm);
92	}
93	case `11`: {
94	// bare_simm12_lsb0
95	int64_t Imm;
96	if (MCOp.evaluateAsConstantImm(Imm))
97	return isShiftedInt<`11`, `1`>(x: Imm);
98	return MCOp.isBareSymbolRef();
99	}
100	case `12`: {
101	// uimm2
102	int64_t Imm;
103	if (!MCOp.evaluateAsConstantImm(Imm))
104	return false;
105	return isUInt<`2`>(x: Imm);
106	}
107	case `13`: {
108	// uimm5
109	int64_t Imm;
110	if (!MCOp.evaluateAsConstantImm(Imm))
111	return false;
112	return isUInt<`5`>(x: Imm);
113	}
114	case `14`: {
115	// uimm4
116	int64_t Imm;
117	if (!MCOp.evaluateAsConstantImm(Imm))
118	return false;
119	return isUInt<`4`>(x: Imm);
120	}
121	case `15`: {
122	// uimm2_lsb0
123	int64_t Imm;
124	if (!MCOp.evaluateAsConstantImm(Imm))
125	return false;
126	return isShiftedUInt<`1`, `1`>(x: Imm);
127	}
128	case `16`: {
129	// uimm6_lsb0
130	int64_t Imm;
131	if (!MCOp.evaluateAsConstantImm(Imm))
132	return false;
133	return isShiftedUInt<`5`, `1`>(x: Imm);
134	}
135	case `17`: {
136	// uimm5_lsb0
137	int64_t Imm;
138	if (!MCOp.evaluateAsConstantImm(Imm))
139	return false;
140	return isShiftedUInt<`4`, `1`>(x: Imm);
141	}
142	case `18`: {
143	// c_lui_imm
144	int64_t Imm;
145	if (!MCOp.evaluateAsConstantImm(Imm))
146	return false;
147	return (Imm != `0`) && (isUInt<`5`>(x: Imm) \|\|
148	(Imm >= `0xfffe0` && Imm <= `0xfffff`));
149	}
150	case `19`: {
151	// uimm5ge6_plus1
152	int64_t Imm;
153	if (!MCOp.evaluateAsConstantImm(Imm))
154	return false;
155	return (Imm >= `6`) && (isUInt<`5`>(x: Imm) \|\| (Imm == `32`));
156	}
157	case `20`: {
158	// simm5nonzero
159	int64_t Imm;
160	if (!MCOp.evaluateAsConstantImm(Imm))
161	return false;
162	return (Imm != `0`) && isInt<`5`>(x: Imm);
163	}
164	case `21`: {
165	// bare_simm13_lsb0
166	int64_t Imm;
167	if (MCOp.evaluateAsConstantImm(Imm))
168	return isShiftedInt<`12`, `1`>(x: Imm);
169	return MCOp.isBareSymbolRef();
170	}
171	case `22`: {
172	// uimm5nonzero
173	int64_t Imm;
174	if (!MCOp.evaluateAsConstantImm(Imm))
175	return false;
176	return (Imm != `0`) && isUInt<`5`>(x: Imm);;
177	}
178	case `23`: {
179	// simm21_lsb0_jal
180	int64_t Imm;
181	if (MCOp.evaluateAsConstantImm(Imm))
182	return isShiftedInt<`20`, `1`>(x: Imm);
183	return MCOp.isBareSymbolRef();
184	}
185	case `24`: {
186	// simm12
187	int64_t Imm;
188	if (MCOp.evaluateAsConstantImm(Imm))
189	return isInt<`12`>(x: Imm);
190	return MCOp.isBareSymbolRef();
191	}
192	case `25`: {
193	// simm20_li
194	int64_t Imm;
195	if (MCOp.evaluateAsConstantImm(Imm))
196	return isInt<`20`>(x: Imm);
197	return MCOp.isBareSymbolRef();
198	}
199	case `26`: {
200	// uimm5slist
201	int64_t Imm;
202	if (!MCOp.evaluateAsConstantImm(Imm))
203	return false;
204	return ((Imm == `0`) \|\| (Imm == `1`) \|\|
205	(Imm == `2`) \|\| (Imm == `4`) \|\|
206	(Imm == `8`) \|\| (Imm == `16`) \|\|
207	(Imm == `15`) \|\| (Imm == `31`));
208	}
209	}
210	}
211
212	static bool compressInst(MCInst &OutInst,
213	const MCInst &MI,
214	const MCSubtargetInfo &STI) {
215	switch (MI.getOpcode()) {
216	default: return false;
217	case RISCV::ADD: {
218	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
219	(MI.getOperand(i: `1`).isReg()) &&
220	(MI.getOperand(i: `1`).getReg() == RISCV::X0) &&
221	MI.getOperand(i: `0`).isReg() &&
222	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
223	MI.getOperand(i: `2`).isReg() &&
224	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `2`).getReg())) {
225	// c.mv $rs1, $rs2
226	OutInst.setOpcode(RISCV::C_MV);
227	// Operand: rs1
228	OutInst.addOperand(Op: MI.getOperand(i: `0`));
229	// Operand: rs2
230	OutInst.addOperand(Op: MI.getOperand(i: `2`));
231	OutInst.setLoc(MI.getLoc());
232	return true;
233	} // if
234	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
235	(MI.getOperand(i: `2`).isReg()) &&
236	(MI.getOperand(i: `2`).getReg() == RISCV::X0) &&
237	MI.getOperand(i: `0`).isReg() &&
238	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
239	MI.getOperand(i: `1`).isReg() &&
240	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `1`).getReg())) {
241	// c.mv $rs1, $rs2
242	OutInst.setOpcode(RISCV::C_MV);
243	// Operand: rs1
244	OutInst.addOperand(Op: MI.getOperand(i: `0`));
245	// Operand: rs2
246	OutInst.addOperand(Op: MI.getOperand(i: `1`));
247	OutInst.setLoc(MI.getLoc());
248	return true;
249	} // if
250	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
251	(MI.getOperand(i: `1`).isReg()) && (MI.getOperand(i: `0`).isReg()) &&
252	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
253	MI.getOperand(i: `1`).isReg() &&
254	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
255	MI.getOperand(i: `2`).isReg() &&
256	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `2`).getReg())) {
257	// c.add $rs1, $rs2
258	OutInst.setOpcode(RISCV::C_ADD);
259	// Operand: rd
260	OutInst.addOperand(Op: MI.getOperand(i: `1`));
261	// Operand: rs1
262	OutInst.addOperand(Op: MI.getOperand(i: `1`));
263	// Operand: rs2
264	OutInst.addOperand(Op: MI.getOperand(i: `2`));
265	OutInst.setLoc(MI.getLoc());
266	return true;
267	} // if
268	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
269	(MI.getOperand(i: `2`).isReg()) && (MI.getOperand(i: `0`).isReg()) &&
270	(MI.getOperand(i: `2`).getReg() == MI.getOperand(i: `0`).getReg()) &&
271	MI.getOperand(i: `2`).isReg() &&
272	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `2`).getReg()) &&
273	MI.getOperand(i: `1`).isReg() &&
274	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `1`).getReg())) {
275	// c.add $rs1, $rs2
276	OutInst.setOpcode(RISCV::C_ADD);
277	// Operand: rd
278	OutInst.addOperand(Op: MI.getOperand(i: `2`));
279	// Operand: rs1
280	OutInst.addOperand(Op: MI.getOperand(i: `2`));
281	// Operand: rs2
282	OutInst.addOperand(Op: MI.getOperand(i: `1`));
283	OutInst.setLoc(MI.getLoc());
284	return true;
285	} // if
286	break;
287	} // case ADD
288	case RISCV::ADDI: {
289	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
290	MI.getOperand(i: `0`).isReg() &&
291	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
292	MI.getOperand(i: `1`).isReg() &&
293	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
294	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `1`)) {
295	// c.addi4spn $rd, $rs1, $imm
296	OutInst.setOpcode(RISCV::C_ADDI4SPN);
297	// Operand: rd
298	OutInst.addOperand(Op: MI.getOperand(i: `0`));
299	// Operand: rs1
300	OutInst.addOperand(Op: MI.getOperand(i: `1`));
301	// Operand: imm
302	OutInst.addOperand(Op: MI.getOperand(i: `2`));
303	OutInst.setLoc(MI.getLoc());
304	return true;
305	} // if
306	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
307	(MI.getOperand(i: `0`).isReg()) &&
308	(MI.getOperand(i: `0`).getReg() == RISCV::X0) &&
309	(MI.getOperand(i: `1`).isReg()) &&
310	(MI.getOperand(i: `1`).getReg() == RISCV::X0) &&
311	(MI.getOperand(i: `2`).isImm()) &&
312	(MI.getOperand(i: `2`).getImm() == `0`)) {
313	// c.nop
314	OutInst.setOpcode(RISCV::C_NOP);
315	OutInst.setLoc(MI.getLoc());
316	return true;
317	} // if
318	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
319	(MI.getOperand(i: `1`).isReg()) && (MI.getOperand(i: `0`).isReg()) &&
320	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
321	MI.getOperand(i: `1`).isReg() &&
322	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
323	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `2`)) {
324	// c.addi $rd, $imm
325	OutInst.setOpcode(RISCV::C_ADDI);
326	// Operand: rd_wb
327	OutInst.addOperand(Op: MI.getOperand(i: `1`));
328	// Operand: rd
329	OutInst.addOperand(Op: MI.getOperand(i: `1`));
330	// Operand: imm
331	OutInst.addOperand(Op: MI.getOperand(i: `2`));
332	OutInst.setLoc(MI.getLoc());
333	return true;
334	} // if
335	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
336	(MI.getOperand(i: `1`).isReg()) &&
337	(MI.getOperand(i: `1`).getReg() == RISCV::X0) &&
338	MI.getOperand(i: `0`).isReg() &&
339	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
340	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `3`)) {
341	// c.li $rd, $imm
342	OutInst.setOpcode(RISCV::C_LI);
343	// Operand: rd
344	OutInst.addOperand(Op: MI.getOperand(i: `0`));
345	// Operand: imm
346	OutInst.addOperand(Op: MI.getOperand(i: `2`));
347	OutInst.setLoc(MI.getLoc());
348	return true;
349	} // if
350	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
351	(MI.getOperand(i: `0`).isReg()) &&
352	(MI.getOperand(i: `0`).getReg() == RISCV::X2) &&
353	(MI.getOperand(i: `1`).isReg()) &&
354	(MI.getOperand(i: `1`).getReg() == RISCV::X2) &&
355	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `4`)) {
356	// c.addi16sp $rd, $imm
357	OutInst.setOpcode(RISCV::C_ADDI16SP);
358	// Operand: rd_wb
359	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X2));
360	// Operand: rd
361	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X2));
362	// Operand: imm
363	OutInst.addOperand(Op: MI.getOperand(i: `2`));
364	OutInst.setLoc(MI.getLoc());
365	return true;
366	} // if
367	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
368	(MI.getOperand(i: `2`).isImm()) &&
369	(MI.getOperand(i: `2`).getImm() == `0`) &&
370	MI.getOperand(i: `0`).isReg() &&
371	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
372	MI.getOperand(i: `1`).isReg() &&
373	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `1`).getReg())) {
374	// c.mv $rs1, $rs2
375	OutInst.setOpcode(RISCV::C_MV);
376	// Operand: rs1
377	OutInst.addOperand(Op: MI.getOperand(i: `0`));
378	// Operand: rs2
379	OutInst.addOperand(Op: MI.getOperand(i: `1`));
380	OutInst.setLoc(MI.getLoc());
381	return true;
382	} // if
383	break;
384	} // case ADDI
385	case RISCV::ADDIW: {
386	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
387	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
388	(MI.getOperand(i: `1`).isReg()) && (MI.getOperand(i: `0`).isReg()) &&
389	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
390	MI.getOperand(i: `1`).isReg() &&
391	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
392	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `3`)) {
393	// c.addiw $rd, $imm
394	OutInst.setOpcode(RISCV::C_ADDIW);
395	// Operand: rd_wb
396	OutInst.addOperand(Op: MI.getOperand(i: `1`));
397	// Operand: rd
398	OutInst.addOperand(Op: MI.getOperand(i: `1`));
399	// Operand: imm
400	OutInst.addOperand(Op: MI.getOperand(i: `2`));
401	OutInst.setLoc(MI.getLoc());
402	return true;
403	} // if
404	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
405	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
406	(MI.getOperand(i: `1`).isReg()) &&
407	(MI.getOperand(i: `1`).getReg() == RISCV::X0) &&
408	MI.getOperand(i: `0`).isReg() &&
409	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
410	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `3`)) {
411	// c.li $rd, $imm
412	OutInst.setOpcode(RISCV::C_LI);
413	// Operand: rd
414	OutInst.addOperand(Op: MI.getOperand(i: `0`));
415	// Operand: imm
416	OutInst.addOperand(Op: MI.getOperand(i: `2`));
417	OutInst.setLoc(MI.getLoc());
418	return true;
419	} // if
420	break;
421	} // case ADDIW
422	case RISCV::ADDW: {
423	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
424	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
425	(MI.getOperand(i: `1`).isReg()) && (MI.getOperand(i: `0`).isReg()) &&
426	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
427	MI.getOperand(i: `1`).isReg() &&
428	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
429	MI.getOperand(i: `2`).isReg() &&
430	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `2`).getReg())) {
431	// c.addw $rd, $rs2
432	OutInst.setOpcode(RISCV::C_ADDW);
433	// Operand: rd_wb
434	OutInst.addOperand(Op: MI.getOperand(i: `1`));
435	// Operand: rd
436	OutInst.addOperand(Op: MI.getOperand(i: `1`));
437	// Operand: rs2
438	OutInst.addOperand(Op: MI.getOperand(i: `2`));
439	OutInst.setLoc(MI.getLoc());
440	return true;
441	} // if
442	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
443	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
444	(MI.getOperand(i: `2`).isReg()) && (MI.getOperand(i: `0`).isReg()) &&
445	(MI.getOperand(i: `2`).getReg() == MI.getOperand(i: `0`).getReg()) &&
446	MI.getOperand(i: `2`).isReg() &&
447	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `2`).getReg()) &&
448	MI.getOperand(i: `1`).isReg() &&
449	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg())) {
450	// c.addw $rd, $rs2
451	OutInst.setOpcode(RISCV::C_ADDW);
452	// Operand: rd_wb
453	OutInst.addOperand(Op: MI.getOperand(i: `2`));
454	// Operand: rd
455	OutInst.addOperand(Op: MI.getOperand(i: `2`));
456	// Operand: rs2
457	OutInst.addOperand(Op: MI.getOperand(i: `1`));
458	OutInst.setLoc(MI.getLoc());
459	return true;
460	} // if
461	break;
462	} // case ADDW
463	case RISCV::ADD_UW: {
464	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
465	STI.getFeatureBits()[RISCV::FeatureStdExtZba] &&
466	STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
467	(MI.getOperand(i: `1`).isReg()) && (MI.getOperand(i: `0`).isReg()) &&
468	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
469	(MI.getOperand(i: `2`).isReg()) &&
470	(MI.getOperand(i: `2`).getReg() == RISCV::X0) &&
471	MI.getOperand(i: `1`).isReg() &&
472	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg())) {
473	// c.zext.w $rd
474	OutInst.setOpcode(RISCV::C_ZEXT_W);
475	// Operand: rd_wb
476	OutInst.addOperand(Op: MI.getOperand(i: `1`));
477	// Operand: rd
478	OutInst.addOperand(Op: MI.getOperand(i: `1`));
479	OutInst.setLoc(MI.getLoc());
480	return true;
481	} // if
482	break;
483	} // case ADD_UW
484	case RISCV::AND: {
485	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
486	(MI.getOperand(i: `1`).isReg()) && (MI.getOperand(i: `0`).isReg()) &&
487	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
488	MI.getOperand(i: `1`).isReg() &&
489	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
490	MI.getOperand(i: `2`).isReg() &&
491	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `2`).getReg())) {
492	// c.and $rd, $rs2
493	OutInst.setOpcode(RISCV::C_AND);
494	// Operand: rd_wb
495	OutInst.addOperand(Op: MI.getOperand(i: `1`));
496	// Operand: rd
497	OutInst.addOperand(Op: MI.getOperand(i: `1`));
498	// Operand: rs2
499	OutInst.addOperand(Op: MI.getOperand(i: `2`));
500	OutInst.setLoc(MI.getLoc());
501	return true;
502	} // if
503	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
504	(MI.getOperand(i: `2`).isReg()) && (MI.getOperand(i: `0`).isReg()) &&
505	(MI.getOperand(i: `2`).getReg() == MI.getOperand(i: `0`).getReg()) &&
506	MI.getOperand(i: `2`).isReg() &&
507	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `2`).getReg()) &&
508	MI.getOperand(i: `1`).isReg() &&
509	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg())) {
510	// c.and $rd, $rs2
511	OutInst.setOpcode(RISCV::C_AND);
512	// Operand: rd_wb
513	OutInst.addOperand(Op: MI.getOperand(i: `2`));
514	// Operand: rd
515	OutInst.addOperand(Op: MI.getOperand(i: `2`));
516	// Operand: rs2
517	OutInst.addOperand(Op: MI.getOperand(i: `1`));
518	OutInst.setLoc(MI.getLoc());
519	return true;
520	} // if
521	break;
522	} // case AND
523	case RISCV::ANDI: {
524	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
525	(MI.getOperand(i: `1`).isReg()) && (MI.getOperand(i: `0`).isReg()) &&
526	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
527	MI.getOperand(i: `1`).isReg() &&
528	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
529	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `3`)) {
530	// c.andi $rs1, $imm
531	OutInst.setOpcode(RISCV::C_ANDI);
532	// Operand: rd
533	OutInst.addOperand(Op: MI.getOperand(i: `1`));
534	// Operand: rs1
535	OutInst.addOperand(Op: MI.getOperand(i: `1`));
536	// Operand: imm
537	OutInst.addOperand(Op: MI.getOperand(i: `2`));
538	OutInst.setLoc(MI.getLoc());
539	return true;
540	} // if
541	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
542	(MI.getOperand(i: `1`).isReg()) && (MI.getOperand(i: `0`).isReg()) &&
543	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
544	(MI.getOperand(i: `2`).isImm()) &&
545	(MI.getOperand(i: `2`).getImm() == `255`) &&
546	MI.getOperand(i: `1`).isReg() &&
547	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg())) {
548	// c.zext.b $rd
549	OutInst.setOpcode(RISCV::C_ZEXT_B);
550	// Operand: rd_wb
551	OutInst.addOperand(Op: MI.getOperand(i: `1`));
552	// Operand: rd
553	OutInst.addOperand(Op: MI.getOperand(i: `1`));
554	OutInst.setLoc(MI.getLoc());
555	return true;
556	} // if
557	break;
558	} // case ANDI
559	case RISCV::BEQ: {
560	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
561	(MI.getOperand(i: `1`).isReg()) &&
562	(MI.getOperand(i: `1`).getReg() == RISCV::X0) &&
563	MI.getOperand(i: `0`).isReg() &&
564	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
565	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `5`)) {
566	// c.beqz $rs1, $imm
567	OutInst.setOpcode(RISCV::C_BEQZ);
568	// Operand: rs1
569	OutInst.addOperand(Op: MI.getOperand(i: `0`));
570	// Operand: imm
571	OutInst.addOperand(Op: MI.getOperand(i: `2`));
572	OutInst.setLoc(MI.getLoc());
573	return true;
574	} // if
575	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
576	(MI.getOperand(i: `0`).isReg()) &&
577	(MI.getOperand(i: `0`).getReg() == RISCV::X0) &&
578	MI.getOperand(i: `1`).isReg() &&
579	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
580	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `5`)) {
581	// c.beqz $rs1, $imm
582	OutInst.setOpcode(RISCV::C_BEQZ);
583	// Operand: rs1
584	OutInst.addOperand(Op: MI.getOperand(i: `1`));
585	// Operand: imm
586	OutInst.addOperand(Op: MI.getOperand(i: `2`));
587	OutInst.setLoc(MI.getLoc());
588	return true;
589	} // if
590	break;
591	} // case BEQ
592	case RISCV::BEXTI: {
593	if (STI.getFeatureBits()[RISCV::FeatureStdExtZbs] &&
594	STI.getFeatureBits()[RISCV::FeatureVendorXqcibm] &&
595	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
596	(MI.getOperand(i: `1`).isReg()) && (MI.getOperand(i: `0`).isReg()) &&
597	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
598	MI.getOperand(i: `1`).isReg() &&
599	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
600	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `6`)) {
601	// qc.c.bexti $rs1, $shamt
602	OutInst.setOpcode(RISCV::QC_C_BEXTI);
603	// Operand: rd
604	OutInst.addOperand(Op: MI.getOperand(i: `1`));
605	// Operand: rs1
606	OutInst.addOperand(Op: MI.getOperand(i: `1`));
607	// Operand: shamt
608	OutInst.addOperand(Op: MI.getOperand(i: `2`));
609	OutInst.setLoc(MI.getLoc());
610	return true;
611	} // if
612	break;
613	} // case BEXTI
614	case RISCV::BNE: {
615	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
616	(MI.getOperand(i: `1`).isReg()) &&
617	(MI.getOperand(i: `1`).getReg() == RISCV::X0) &&
618	MI.getOperand(i: `0`).isReg() &&
619	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
620	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `5`)) {
621	// c.bnez $rs1, $imm
622	OutInst.setOpcode(RISCV::C_BNEZ);
623	// Operand: rs1
624	OutInst.addOperand(Op: MI.getOperand(i: `0`));
625	// Operand: imm
626	OutInst.addOperand(Op: MI.getOperand(i: `2`));
627	OutInst.setLoc(MI.getLoc());
628	return true;
629	} // if
630	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
631	(MI.getOperand(i: `0`).isReg()) &&
632	(MI.getOperand(i: `0`).getReg() == RISCV::X0) &&
633	MI.getOperand(i: `1`).isReg() &&
634	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
635	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `5`)) {
636	// c.bnez $rs1, $imm
637	OutInst.setOpcode(RISCV::C_BNEZ);
638	// Operand: rs1
639	OutInst.addOperand(Op: MI.getOperand(i: `1`));
640	// Operand: imm
641	OutInst.addOperand(Op: MI.getOperand(i: `2`));
642	OutInst.setLoc(MI.getLoc());
643	return true;
644	} // if
645	break;
646	} // case BNE
647	case RISCV::BSETI: {
648	if (STI.getFeatureBits()[RISCV::FeatureStdExtZbs] &&
649	STI.getFeatureBits()[RISCV::FeatureVendorXqcibm] &&
650	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
651	(MI.getOperand(i: `1`).isReg()) && (MI.getOperand(i: `0`).isReg()) &&
652	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
653	MI.getOperand(i: `1`).isReg() &&
654	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
655	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `6`)) {
656	// qc.c.bseti $rs1, $shamt
657	OutInst.setOpcode(RISCV::QC_C_BSETI);
658	// Operand: rd
659	OutInst.addOperand(Op: MI.getOperand(i: `1`));
660	// Operand: rs1
661	OutInst.addOperand(Op: MI.getOperand(i: `1`));
662	// Operand: shamt
663	OutInst.addOperand(Op: MI.getOperand(i: `2`));
664	OutInst.setLoc(MI.getLoc());
665	return true;
666	} // if
667	break;
668	} // case BSETI
669	case RISCV::EBREAK: {
670	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca])) {
671	// c.ebreak
672	OutInst.setOpcode(RISCV::C_EBREAK);
673	OutInst.setLoc(MI.getLoc());
674	return true;
675	} // if
676	break;
677	} // case EBREAK
678	case RISCV::FLD: {
679	if (STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
680	(STI.getFeatureBits()[RISCV::FeatureStdExtC] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZcd]) &&
681	MI.getOperand(i: `0`).isReg() &&
682	RISCVMCRegisterClasses[RISCV::FPR64CRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
683	MI.getOperand(i: `1`).isReg() &&
684	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
685	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `7`)) {
686	// c.fld $rd, ${imm}(${rs1})
687	OutInst.setOpcode(RISCV::C_FLD);
688	// Operand: rd
689	OutInst.addOperand(Op: MI.getOperand(i: `0`));
690	// Operand: rs1
691	OutInst.addOperand(Op: MI.getOperand(i: `1`));
692	// Operand: imm
693	OutInst.addOperand(Op: MI.getOperand(i: `2`));
694	OutInst.setLoc(MI.getLoc());
695	return true;
696	} // if
697	if (STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
698	(STI.getFeatureBits()[RISCV::FeatureStdExtC] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZcd]) &&
699	MI.getOperand(i: `0`).isReg() &&
700	RISCVMCRegisterClasses[RISCV::FPR64RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
701	MI.getOperand(i: `1`).isReg() &&
702	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
703	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `8`)) {
704	// c.fldsp $rd, ${imm}(${rs1})
705	OutInst.setOpcode(RISCV::C_FLDSP);
706	// Operand: rd
707	OutInst.addOperand(Op: MI.getOperand(i: `0`));
708	// Operand: rs1
709	OutInst.addOperand(Op: MI.getOperand(i: `1`));
710	// Operand: imm
711	OutInst.addOperand(Op: MI.getOperand(i: `2`));
712	OutInst.setLoc(MI.getLoc());
713	return true;
714	} // if
715	break;
716	} // case FLD
717	case RISCV::FLW: {
718	if (STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
719	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
720	(STI.getFeatureBits()[RISCV::FeatureStdExtC] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZce] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZcf]) &&
721	MI.getOperand(i: `0`).isReg() &&
722	RISCVMCRegisterClasses[RISCV::FPR32CRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
723	MI.getOperand(i: `1`).isReg() &&
724	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
725	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `9`)) {
726	// c.flw $rd, ${imm}(${rs1})
727	OutInst.setOpcode(RISCV::C_FLW);
728	// Operand: rd
729	OutInst.addOperand(Op: MI.getOperand(i: `0`));
730	// Operand: rs1
731	OutInst.addOperand(Op: MI.getOperand(i: `1`));
732	// Operand: imm
733	OutInst.addOperand(Op: MI.getOperand(i: `2`));
734	OutInst.setLoc(MI.getLoc());
735	return true;
736	} // if
737	if (STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
738	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
739	(STI.getFeatureBits()[RISCV::FeatureStdExtC] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZce] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZcf]) &&
740	MI.getOperand(i: `0`).isReg() &&
741	RISCVMCRegisterClasses[RISCV::FPR32RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
742	MI.getOperand(i: `1`).isReg() &&
743	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
744	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `10`)) {
745	// c.flwsp $rd, ${imm}(${rs1})
746	OutInst.setOpcode(RISCV::C_FLWSP);
747	// Operand: rd
748	OutInst.addOperand(Op: MI.getOperand(i: `0`));
749	// Operand: rs1
750	OutInst.addOperand(Op: MI.getOperand(i: `1`));
751	// Operand: imm
752	OutInst.addOperand(Op: MI.getOperand(i: `2`));
753	OutInst.setLoc(MI.getLoc());
754	return true;
755	} // if
756	break;
757	} // case FLW
758	case RISCV::FSD: {
759	if (STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
760	(STI.getFeatureBits()[RISCV::FeatureStdExtC] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZcd]) &&
761	MI.getOperand(i: `0`).isReg() &&
762	RISCVMCRegisterClasses[RISCV::FPR64CRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
763	MI.getOperand(i: `1`).isReg() &&
764	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
765	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `7`)) {
766	// c.fsd $rs2, ${imm}(${rs1})
767	OutInst.setOpcode(RISCV::C_FSD);
768	// Operand: rs2
769	OutInst.addOperand(Op: MI.getOperand(i: `0`));
770	// Operand: rs1
771	OutInst.addOperand(Op: MI.getOperand(i: `1`));
772	// Operand: imm
773	OutInst.addOperand(Op: MI.getOperand(i: `2`));
774	OutInst.setLoc(MI.getLoc());
775	return true;
776	} // if
777	if (STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
778	(STI.getFeatureBits()[RISCV::FeatureStdExtC] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZcd]) &&
779	MI.getOperand(i: `0`).isReg() &&
780	RISCVMCRegisterClasses[RISCV::FPR64RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
781	MI.getOperand(i: `1`).isReg() &&
782	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
783	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `8`)) {
784	// c.fsdsp $rs2, ${imm}(${rs1})
785	OutInst.setOpcode(RISCV::C_FSDSP);
786	// Operand: rs2
787	OutInst.addOperand(Op: MI.getOperand(i: `0`));
788	// Operand: rs1
789	OutInst.addOperand(Op: MI.getOperand(i: `1`));
790	// Operand: imm
791	OutInst.addOperand(Op: MI.getOperand(i: `2`));
792	OutInst.setLoc(MI.getLoc());
793	return true;
794	} // if
795	break;
796	} // case FSD
797	case RISCV::FSW: {
798	if (STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
799	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
800	(STI.getFeatureBits()[RISCV::FeatureStdExtC] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZce] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZcf]) &&
801	MI.getOperand(i: `0`).isReg() &&
802	RISCVMCRegisterClasses[RISCV::FPR32CRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
803	MI.getOperand(i: `1`).isReg() &&
804	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
805	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `9`)) {
806	// c.fsw $rs2, ${imm}(${rs1})
807	OutInst.setOpcode(RISCV::C_FSW);
808	// Operand: rs2
809	OutInst.addOperand(Op: MI.getOperand(i: `0`));
810	// Operand: rs1
811	OutInst.addOperand(Op: MI.getOperand(i: `1`));
812	// Operand: imm
813	OutInst.addOperand(Op: MI.getOperand(i: `2`));
814	OutInst.setLoc(MI.getLoc());
815	return true;
816	} // if
817	if (STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
818	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
819	(STI.getFeatureBits()[RISCV::FeatureStdExtC] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZce] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZcf]) &&
820	MI.getOperand(i: `0`).isReg() &&
821	RISCVMCRegisterClasses[RISCV::FPR32RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
822	MI.getOperand(i: `1`).isReg() &&
823	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
824	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `10`)) {
825	// c.fswsp $rs2, ${imm}(${rs1})
826	OutInst.setOpcode(RISCV::C_FSWSP);
827	// Operand: rs2
828	OutInst.addOperand(Op: MI.getOperand(i: `0`));
829	// Operand: rs1
830	OutInst.addOperand(Op: MI.getOperand(i: `1`));
831	// Operand: imm
832	OutInst.addOperand(Op: MI.getOperand(i: `2`));
833	OutInst.setLoc(MI.getLoc());
834	return true;
835	} // if
836	break;
837	} // case FSW
838	case RISCV::JAL: {
839	if (!STI.getFeatureBits()[RISCV::Feature64Bit] &&
840	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
841	(MI.getOperand(i: `0`).isReg()) &&
842	(MI.getOperand(i: `0`).getReg() == RISCV::X1) &&
843	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `1`), STI, PredicateIndex: `11`)) {
844	// c.jal $offset
845	OutInst.setOpcode(RISCV::C_JAL);
846	// Operand: offset
847	OutInst.addOperand(Op: MI.getOperand(i: `1`));
848	OutInst.setLoc(MI.getLoc());
849	return true;
850	} // if
851	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
852	(MI.getOperand(i: `0`).isReg()) &&
853	(MI.getOperand(i: `0`).getReg() == RISCV::X0) &&
854	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `1`), STI, PredicateIndex: `11`)) {
855	// c.j $offset
856	OutInst.setOpcode(RISCV::C_J);
857	// Operand: offset
858	OutInst.addOperand(Op: MI.getOperand(i: `1`));
859	OutInst.setLoc(MI.getLoc());
860	return true;
861	} // if
862	break;
863	} // case JAL
864	case RISCV::JALR: {
865	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
866	(MI.getOperand(i: `0`).isReg()) &&
867	(MI.getOperand(i: `0`).getReg() == RISCV::X0) &&
868	(MI.getOperand(i: `2`).isImm()) &&
869	(MI.getOperand(i: `2`).getImm() == `0`) &&
870	MI.getOperand(i: `1`).isReg() &&
871	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `1`).getReg())) {
872	// c.jr $rs1
873	OutInst.setOpcode(RISCV::C_JR);
874	// Operand: rs1
875	OutInst.addOperand(Op: MI.getOperand(i: `1`));
876	OutInst.setLoc(MI.getLoc());
877	return true;
878	} // if
879	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
880	(MI.getOperand(i: `0`).isReg()) &&
881	(MI.getOperand(i: `0`).getReg() == RISCV::X1) &&
882	(MI.getOperand(i: `2`).isImm()) &&
883	(MI.getOperand(i: `2`).getImm() == `0`) &&
884	MI.getOperand(i: `1`).isReg() &&
885	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `1`).getReg())) {
886	// c.jalr $rs1
887	OutInst.setOpcode(RISCV::C_JALR);
888	// Operand: rs1
889	OutInst.addOperand(Op: MI.getOperand(i: `1`));
890	OutInst.setLoc(MI.getLoc());
891	return true;
892	} // if
893	break;
894	} // case JALR
895	case RISCV::LBU: {
896	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
897	MI.getOperand(i: `0`).isReg() &&
898	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
899	MI.getOperand(i: `1`).isReg() &&
900	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
901	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `12`)) {
902	// c.lbu $rd, ${imm}(${rs1})
903	OutInst.setOpcode(RISCV::C_LBU);
904	// Operand: rd
905	OutInst.addOperand(Op: MI.getOperand(i: `0`));
906	// Operand: rs1
907	OutInst.addOperand(Op: MI.getOperand(i: `1`));
908	// Operand: imm
909	OutInst.addOperand(Op: MI.getOperand(i: `2`));
910	OutInst.setLoc(MI.getLoc());
911	return true;
912	} // if
913	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
914	MI.getOperand(i: `0`).isReg() &&
915	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
916	MI.getOperand(i: `1`).isReg() &&
917	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
918	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `13`)) {
919	// qk.c.lbu $rd, ${imm}(${rs1})
920	OutInst.setOpcode(RISCV::QK_C_LBU);
921	// Operand: rd
922	OutInst.addOperand(Op: MI.getOperand(i: `0`));
923	// Operand: rs1
924	OutInst.addOperand(Op: MI.getOperand(i: `1`));
925	// Operand: imm
926	OutInst.addOperand(Op: MI.getOperand(i: `2`));
927	OutInst.setLoc(MI.getLoc());
928	return true;
929	} // if
930	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
931	MI.getOperand(i: `0`).isReg() &&
932	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
933	MI.getOperand(i: `1`).isReg() &&
934	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
935	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `14`)) {
936	// qk.c.lbusp $rd_rs2, ${imm}(${rs1})
937	OutInst.setOpcode(RISCV::QK_C_LBUSP);
938	// Operand: rd_rs2
939	OutInst.addOperand(Op: MI.getOperand(i: `0`));
940	// Operand: rs1
941	OutInst.addOperand(Op: MI.getOperand(i: `1`));
942	// Operand: imm
943	OutInst.addOperand(Op: MI.getOperand(i: `2`));
944	OutInst.setLoc(MI.getLoc());
945	return true;
946	} // if
947	break;
948	} // case LBU
949	case RISCV::LD: {
950	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
951	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
952	MI.getOperand(i: `0`).isReg() &&
953	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
954	MI.getOperand(i: `1`).isReg() &&
955	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
956	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `7`)) {
957	// c.ld $rd, ${imm}(${rs1})
958	OutInst.setOpcode(RISCV::C_LD);
959	// Operand: rd
960	OutInst.addOperand(Op: MI.getOperand(i: `0`));
961	// Operand: rs1
962	OutInst.addOperand(Op: MI.getOperand(i: `1`));
963	// Operand: imm
964	OutInst.addOperand(Op: MI.getOperand(i: `2`));
965	OutInst.setLoc(MI.getLoc());
966	return true;
967	} // if
968	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
969	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
970	MI.getOperand(i: `0`).isReg() &&
971	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
972	MI.getOperand(i: `1`).isReg() &&
973	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
974	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `8`)) {
975	// c.ldsp $rd, ${imm}(${rs1})
976	OutInst.setOpcode(RISCV::C_LDSP);
977	// Operand: rd
978	OutInst.addOperand(Op: MI.getOperand(i: `0`));
979	// Operand: rs1
980	OutInst.addOperand(Op: MI.getOperand(i: `1`));
981	// Operand: imm
982	OutInst.addOperand(Op: MI.getOperand(i: `2`));
983	OutInst.setLoc(MI.getLoc());
984	return true;
985	} // if
986	break;
987	} // case LD
988	case RISCV::LD_RV32: {
989	if (STI.getFeatureBits()[RISCV::FeatureStdExtZclsd] &&
990	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
991	MI.getOperand(i: `0`).isReg() &&
992	RISCVMCRegisterClasses[RISCV::GPRPairNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
993	MI.getOperand(i: `1`).isReg() &&
994	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
995	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `8`)) {
996	// c.ldsp $rd, ${imm}(${rs1})
997	OutInst.setOpcode(RISCV::C_LDSP_RV32);
998	// Operand: rd
999	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1000	// Operand: rs1
1001	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1002	// Operand: imm
1003	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1004	OutInst.setLoc(MI.getLoc());
1005	return true;
1006	} // if
1007	if (STI.getFeatureBits()[RISCV::FeatureStdExtZclsd] &&
1008	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1009	MI.getOperand(i: `0`).isReg() &&
1010	RISCVMCRegisterClasses[RISCV::GPRPairCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1011	MI.getOperand(i: `1`).isReg() &&
1012	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1013	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `7`)) {
1014	// c.ld $rd, ${imm}(${rs1})
1015	OutInst.setOpcode(RISCV::C_LD_RV32);
1016	// Operand: rd
1017	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1018	// Operand: rs1
1019	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1020	// Operand: imm
1021	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1022	OutInst.setLoc(MI.getLoc());
1023	return true;
1024	} // if
1025	break;
1026	} // case LD_RV32
1027	case RISCV::LH: {
1028	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
1029	MI.getOperand(i: `0`).isReg() &&
1030	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1031	MI.getOperand(i: `1`).isReg() &&
1032	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1033	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `15`)) {
1034	// c.lh $rd, ${imm}(${rs1})
1035	OutInst.setOpcode(RISCV::C_LH);
1036	// Operand: rd
1037	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1038	// Operand: rs1
1039	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1040	// Operand: imm
1041	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1042	OutInst.setLoc(MI.getLoc());
1043	return true;
1044	} // if
1045	break;
1046	} // case LH
1047	case RISCV::LHU: {
1048	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
1049	MI.getOperand(i: `0`).isReg() &&
1050	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1051	MI.getOperand(i: `1`).isReg() &&
1052	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1053	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `15`)) {
1054	// c.lhu $rd, ${imm}(${rs1})
1055	OutInst.setOpcode(RISCV::C_LHU);
1056	// Operand: rd
1057	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1058	// Operand: rs1
1059	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1060	// Operand: imm
1061	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1062	OutInst.setLoc(MI.getLoc());
1063	return true;
1064	} // if
1065	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
1066	MI.getOperand(i: `0`).isReg() &&
1067	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1068	MI.getOperand(i: `1`).isReg() &&
1069	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1070	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `16`)) {
1071	// qk.c.lhu $rd, ${imm}(${rs1})
1072	OutInst.setOpcode(RISCV::QK_C_LHU);
1073	// Operand: rd
1074	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1075	// Operand: rs1
1076	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1077	// Operand: imm
1078	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1079	OutInst.setLoc(MI.getLoc());
1080	return true;
1081	} // if
1082	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
1083	MI.getOperand(i: `0`).isReg() &&
1084	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1085	MI.getOperand(i: `1`).isReg() &&
1086	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1087	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `17`)) {
1088	// qk.c.lhusp $rd_rs2, ${imm}(${rs1})
1089	OutInst.setOpcode(RISCV::QK_C_LHUSP);
1090	// Operand: rd_rs2
1091	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1092	// Operand: rs1
1093	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1094	// Operand: imm
1095	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1096	OutInst.setLoc(MI.getLoc());
1097	return true;
1098	} // if
1099	break;
1100	} // case LHU
1101	case RISCV::LH_INX: {
1102	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
1103	MI.getOperand(i: `0`).isReg() &&
1104	RISCVMCRegisterClasses[RISCV::GPRF16CRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1105	MI.getOperand(i: `1`).isReg() &&
1106	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1107	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `15`)) {
1108	// c.lh $rd, ${imm}(${rs1})
1109	OutInst.setOpcode(RISCV::C_LH_INX);
1110	// Operand: rd
1111	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1112	// Operand: rs1
1113	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1114	// Operand: imm
1115	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1116	OutInst.setLoc(MI.getLoc());
1117	return true;
1118	} // if
1119	break;
1120	} // case LH_INX
1121	case RISCV::LUI: {
1122	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1123	MI.getOperand(i: `0`).isReg() &&
1124	RISCVMCRegisterClasses[RISCV::GPRNoX0X2RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1125	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `1`), STI, PredicateIndex: `18`)) {
1126	// c.lui $rd, $imm
1127	OutInst.setOpcode(RISCV::C_LUI);
1128	// Operand: rd
1129	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1130	// Operand: imm
1131	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1132	OutInst.setLoc(MI.getLoc());
1133	return true;
1134	} // if
1135	break;
1136	} // case LUI
1137	case RISCV::LW: {
1138	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1139	MI.getOperand(i: `0`).isReg() &&
1140	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1141	MI.getOperand(i: `1`).isReg() &&
1142	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1143	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `9`)) {
1144	// c.lw $rd, ${imm}(${rs1})
1145	OutInst.setOpcode(RISCV::C_LW);
1146	// Operand: rd
1147	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1148	// Operand: rs1
1149	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1150	// Operand: imm
1151	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1152	OutInst.setLoc(MI.getLoc());
1153	return true;
1154	} // if
1155	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1156	MI.getOperand(i: `0`).isReg() &&
1157	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1158	MI.getOperand(i: `1`).isReg() &&
1159	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1160	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `10`)) {
1161	// c.lwsp $rd, ${imm}(${rs1})
1162	OutInst.setOpcode(RISCV::C_LWSP);
1163	// Operand: rd
1164	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1165	// Operand: rs1
1166	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1167	// Operand: imm
1168	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1169	OutInst.setLoc(MI.getLoc());
1170	return true;
1171	} // if
1172	break;
1173	} // case LW
1174	case RISCV::LW_INX: {
1175	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1176	MI.getOperand(i: `0`).isReg() &&
1177	RISCVMCRegisterClasses[RISCV::GPRF32CRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1178	MI.getOperand(i: `1`).isReg() &&
1179	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1180	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `9`)) {
1181	// c.lw $rd, ${imm}(${rs1})
1182	OutInst.setOpcode(RISCV::C_LW_INX);
1183	// Operand: rd
1184	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1185	// Operand: rs1
1186	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1187	// Operand: imm
1188	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1189	OutInst.setLoc(MI.getLoc());
1190	return true;
1191	} // if
1192	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1193	MI.getOperand(i: `0`).isReg() &&
1194	RISCVMCRegisterClasses[RISCV::GPRF32NoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1195	MI.getOperand(i: `1`).isReg() &&
1196	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1197	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `10`)) {
1198	// c.lwsp $rd, ${imm}(${rs1})
1199	OutInst.setOpcode(RISCV::C_LWSP_INX);
1200	// Operand: rd
1201	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1202	// Operand: rs1
1203	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1204	// Operand: imm
1205	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1206	OutInst.setLoc(MI.getLoc());
1207	return true;
1208	} // if
1209	break;
1210	} // case LW_INX
1211	case RISCV::MUL: {
1212	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
1213	STI.getFeatureBits()[RISCV::FeatureStdExtZmmul] &&
1214	(MI.getOperand(i: `1`).isReg()) && (MI.getOperand(i: `0`).isReg()) &&
1215	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
1216	MI.getOperand(i: `1`).isReg() &&
1217	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1218	MI.getOperand(i: `2`).isReg() &&
1219	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `2`).getReg())) {
1220	// c.mul $rd, $rs2
1221	OutInst.setOpcode(RISCV::C_MUL);
1222	// Operand: rd_wb
1223	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1224	// Operand: rd
1225	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1226	// Operand: rs2
1227	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1228	OutInst.setLoc(MI.getLoc());
1229	return true;
1230	} // if
1231	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
1232	STI.getFeatureBits()[RISCV::FeatureStdExtZmmul] &&
1233	(MI.getOperand(i: `2`).isReg()) && (MI.getOperand(i: `0`).isReg()) &&
1234	(MI.getOperand(i: `2`).getReg() == MI.getOperand(i: `0`).getReg()) &&
1235	MI.getOperand(i: `2`).isReg() &&
1236	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `2`).getReg()) &&
1237	MI.getOperand(i: `1`).isReg() &&
1238	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg())) {
1239	// c.mul $rd, $rs2
1240	OutInst.setOpcode(RISCV::C_MUL);
1241	// Operand: rd_wb
1242	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1243	// Operand: rd
1244	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1245	// Operand: rs2
1246	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1247	OutInst.setLoc(MI.getLoc());
1248	return true;
1249	} // if
1250	break;
1251	} // case MUL
1252	case RISCV::OR: {
1253	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1254	(MI.getOperand(i: `1`).isReg()) && (MI.getOperand(i: `0`).isReg()) &&
1255	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
1256	MI.getOperand(i: `1`).isReg() &&
1257	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1258	MI.getOperand(i: `2`).isReg() &&
1259	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `2`).getReg())) {
1260	// c.or $rd, $rs2
1261	OutInst.setOpcode(RISCV::C_OR);
1262	// Operand: rd_wb
1263	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1264	// Operand: rd
1265	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1266	// Operand: rs2
1267	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1268	OutInst.setLoc(MI.getLoc());
1269	return true;
1270	} // if
1271	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1272	(MI.getOperand(i: `2`).isReg()) && (MI.getOperand(i: `0`).isReg()) &&
1273	(MI.getOperand(i: `2`).getReg() == MI.getOperand(i: `0`).getReg()) &&
1274	MI.getOperand(i: `2`).isReg() &&
1275	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `2`).getReg()) &&
1276	MI.getOperand(i: `1`).isReg() &&
1277	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg())) {
1278	// c.or $rd, $rs2
1279	OutInst.setOpcode(RISCV::C_OR);
1280	// Operand: rd_wb
1281	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1282	// Operand: rd
1283	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1284	// Operand: rs2
1285	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1286	OutInst.setLoc(MI.getLoc());
1287	return true;
1288	} // if
1289	break;
1290	} // case OR
1291	case RISCV::QC_EXTU: {
1292	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcibm] &&
1293	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1294	(MI.getOperand(i: `1`).isReg()) && (MI.getOperand(i: `0`).isReg()) &&
1295	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
1296	(MI.getOperand(i: `3`).isImm()) &&
1297	(MI.getOperand(i: `3`).getImm() == `0`) &&
1298	MI.getOperand(i: `1`).isReg() &&
1299	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1300	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `19`)) {
1301	// qc.c.extu $rd, $width
1302	OutInst.setOpcode(RISCV::QC_C_EXTU);
1303	// Operand: rd_wb
1304	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1305	// Operand: rd
1306	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1307	// Operand: width
1308	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1309	OutInst.setLoc(MI.getLoc());
1310	return true;
1311	} // if
1312	if (STI.getFeatureBits()[RISCV::FeatureStdExtZbs] &&
1313	STI.getFeatureBits()[RISCV::FeatureVendorXqcibm] &&
1314	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1315	(MI.getOperand(i: `1`).isReg()) && (MI.getOperand(i: `0`).isReg()) &&
1316	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
1317	(MI.getOperand(i: `2`).isImm()) &&
1318	(MI.getOperand(i: `2`).getImm() == `1`) &&
1319	MI.getOperand(i: `1`).isReg() &&
1320	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1321	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `3`), STI, PredicateIndex: `6`)) {
1322	// qc.c.bexti $rs1, $shamt
1323	OutInst.setOpcode(RISCV::QC_C_BEXTI);
1324	// Operand: rd
1325	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1326	// Operand: rs1
1327	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1328	// Operand: shamt
1329	OutInst.addOperand(Op: MI.getOperand(i: `3`));
1330	OutInst.setLoc(MI.getLoc());
1331	return true;
1332	} // if
1333	break;
1334	} // case QC_EXTU
1335	case RISCV::QC_E_ADDI: {
1336	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
1337	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1338	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1339	(MI.getOperand(i: `1`).isReg()) && (MI.getOperand(i: `0`).isReg()) &&
1340	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
1341	MI.getOperand(i: `1`).isReg() &&
1342	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1343	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `2`)) {
1344	// c.addi $rd, $imm
1345	OutInst.setOpcode(RISCV::C_ADDI);
1346	// Operand: rd_wb
1347	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1348	// Operand: rd
1349	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1350	// Operand: imm
1351	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1352	OutInst.setLoc(MI.getLoc());
1353	return true;
1354	} // if
1355	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
1356	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1357	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1358	(MI.getOperand(i: `2`).isImm()) &&
1359	(MI.getOperand(i: `2`).getImm() == `0`) &&
1360	MI.getOperand(i: `0`).isReg() &&
1361	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1362	MI.getOperand(i: `1`).isReg() &&
1363	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `1`).getReg())) {
1364	// c.mv $rs1, $rs2
1365	OutInst.setOpcode(RISCV::C_MV);
1366	// Operand: rs1
1367	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1368	// Operand: rs2
1369	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1370	OutInst.setLoc(MI.getLoc());
1371	return true;
1372	} // if
1373	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
1374	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1375	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1376	(MI.getOperand(i: `0`).isReg()) &&
1377	(MI.getOperand(i: `0`).getReg() == RISCV::X2) &&
1378	(MI.getOperand(i: `1`).isReg()) &&
1379	(MI.getOperand(i: `1`).getReg() == RISCV::X2) &&
1380	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `4`)) {
1381	// c.addi16sp $rd, $imm
1382	OutInst.setOpcode(RISCV::C_ADDI16SP);
1383	// Operand: rd_wb
1384	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X2));
1385	// Operand: rd
1386	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X2));
1387	// Operand: imm
1388	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1389	OutInst.setLoc(MI.getLoc());
1390	return true;
1391	} // if
1392	break;
1393	} // case QC_E_ADDI
1394	case RISCV::QC_E_ANDI: {
1395	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
1396	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1397	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1398	(MI.getOperand(i: `1`).isReg()) && (MI.getOperand(i: `0`).isReg()) &&
1399	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
1400	MI.getOperand(i: `1`).isReg() &&
1401	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1402	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `3`)) {
1403	// c.andi $rs1, $imm
1404	OutInst.setOpcode(RISCV::C_ANDI);
1405	// Operand: rd
1406	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1407	// Operand: rs1
1408	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1409	// Operand: imm
1410	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1411	OutInst.setLoc(MI.getLoc());
1412	return true;
1413	} // if
1414	break;
1415	} // case QC_E_ANDI
1416	case RISCV::QC_E_BEQI: {
1417	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcibi] &&
1418	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1419	MI.getOperand(i: `0`).isReg() &&
1420	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1421	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `1`), STI, PredicateIndex: `20`) &&
1422	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `21`)) {
1423	// qc.beqi $rs1, $rs2, $imm12
1424	OutInst.setOpcode(RISCV::QC_BEQI);
1425	// Operand: rs1
1426	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1427	// Operand: rs2
1428	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1429	// Operand: imm12
1430	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1431	OutInst.setLoc(MI.getLoc());
1432	return true;
1433	} // if
1434	break;
1435	} // case QC_E_BEQI
1436	case RISCV::QC_E_BGEI: {
1437	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcibi] &&
1438	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1439	MI.getOperand(i: `0`).isReg() &&
1440	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1441	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `1`), STI, PredicateIndex: `20`) &&
1442	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `21`)) {
1443	// qc.bgei $rs1, $rs2, $imm12
1444	OutInst.setOpcode(RISCV::QC_BGEI);
1445	// Operand: rs1
1446	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1447	// Operand: rs2
1448	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1449	// Operand: imm12
1450	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1451	OutInst.setLoc(MI.getLoc());
1452	return true;
1453	} // if
1454	break;
1455	} // case QC_E_BGEI
1456	case RISCV::QC_E_BGEUI: {
1457	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcibi] &&
1458	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1459	MI.getOperand(i: `0`).isReg() &&
1460	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1461	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `1`), STI, PredicateIndex: `22`) &&
1462	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `21`)) {
1463	// qc.bgeui $rs1, $rs2, $imm12
1464	OutInst.setOpcode(RISCV::QC_BGEUI);
1465	// Operand: rs1
1466	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1467	// Operand: rs2
1468	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1469	// Operand: imm12
1470	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1471	OutInst.setLoc(MI.getLoc());
1472	return true;
1473	} // if
1474	break;
1475	} // case QC_E_BGEUI
1476	case RISCV::QC_E_BLTI: {
1477	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcibi] &&
1478	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1479	MI.getOperand(i: `0`).isReg() &&
1480	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1481	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `1`), STI, PredicateIndex: `20`) &&
1482	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `21`)) {
1483	// qc.blti $rs1, $rs2, $imm12
1484	OutInst.setOpcode(RISCV::QC_BLTI);
1485	// Operand: rs1
1486	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1487	// Operand: rs2
1488	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1489	// Operand: imm12
1490	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1491	OutInst.setLoc(MI.getLoc());
1492	return true;
1493	} // if
1494	break;
1495	} // case QC_E_BLTI
1496	case RISCV::QC_E_BLTUI: {
1497	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcibi] &&
1498	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1499	MI.getOperand(i: `0`).isReg() &&
1500	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1501	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `1`), STI, PredicateIndex: `22`) &&
1502	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `21`)) {
1503	// qc.bltui $rs1, $rs2, $imm12
1504	OutInst.setOpcode(RISCV::QC_BLTUI);
1505	// Operand: rs1
1506	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1507	// Operand: rs2
1508	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1509	// Operand: imm12
1510	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1511	OutInst.setLoc(MI.getLoc());
1512	return true;
1513	} // if
1514	break;
1515	} // case QC_E_BLTUI
1516	case RISCV::QC_E_BNEI: {
1517	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcibi] &&
1518	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1519	MI.getOperand(i: `0`).isReg() &&
1520	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1521	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `1`), STI, PredicateIndex: `20`) &&
1522	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `21`)) {
1523	// qc.bnei $rs1, $rs2, $imm12
1524	OutInst.setOpcode(RISCV::QC_BNEI);
1525	// Operand: rs1
1526	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1527	// Operand: rs2
1528	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1529	// Operand: imm12
1530	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1531	OutInst.setLoc(MI.getLoc());
1532	return true;
1533	} // if
1534	break;
1535	} // case QC_E_BNEI
1536	case RISCV::QC_E_J: {
1537	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilb] &&
1538	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1539	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1540	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `0`), STI, PredicateIndex: `11`)) {
1541	// c.j $offset
1542	OutInst.setOpcode(RISCV::C_J);
1543	// Operand: offset
1544	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1545	OutInst.setLoc(MI.getLoc());
1546	return true;
1547	} // if
1548	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilb] &&
1549	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1550	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `0`), STI, PredicateIndex: `23`)) {
1551	// jal $rd, $imm20
1552	OutInst.setOpcode(RISCV::JAL);
1553	// Operand: rd
1554	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X0));
1555	// Operand: imm20
1556	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1557	OutInst.setLoc(MI.getLoc());
1558	return true;
1559	} // if
1560	break;
1561	} // case QC_E_J
1562	case RISCV::QC_E_JAL: {
1563	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilb] &&
1564	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1565	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1566	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `0`), STI, PredicateIndex: `11`)) {
1567	// c.jal $offset
1568	OutInst.setOpcode(RISCV::C_JAL);
1569	// Operand: offset
1570	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1571	OutInst.setLoc(MI.getLoc());
1572	return true;
1573	} // if
1574	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilb] &&
1575	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1576	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `0`), STI, PredicateIndex: `23`)) {
1577	// jal $rd, $imm20
1578	OutInst.setOpcode(RISCV::JAL);
1579	// Operand: rd
1580	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X1));
1581	// Operand: imm20
1582	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1583	OutInst.setLoc(MI.getLoc());
1584	return true;
1585	} // if
1586	break;
1587	} // case QC_E_JAL
1588	case RISCV::QC_E_LB: {
1589	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
1590	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1591	MI.getOperand(i: `0`).isReg() &&
1592	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1593	MI.getOperand(i: `1`).isReg() &&
1594	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1595	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `24`)) {
1596	// lb $rd, ${imm12}(${rs1})
1597	OutInst.setOpcode(RISCV::LB);
1598	// Operand: rd
1599	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1600	// Operand: rs1
1601	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1602	// Operand: imm12
1603	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1604	OutInst.setLoc(MI.getLoc());
1605	return true;
1606	} // if
1607	break;
1608	} // case QC_E_LB
1609	case RISCV::QC_E_LBU: {
1610	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
1611	STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
1612	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1613	MI.getOperand(i: `0`).isReg() &&
1614	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1615	MI.getOperand(i: `1`).isReg() &&
1616	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1617	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `12`)) {
1618	// c.lbu $rd, ${imm}(${rs1})
1619	OutInst.setOpcode(RISCV::C_LBU);
1620	// Operand: rd
1621	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1622	// Operand: rs1
1623	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1624	// Operand: imm
1625	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1626	OutInst.setLoc(MI.getLoc());
1627	return true;
1628	} // if
1629	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
1630	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1631	MI.getOperand(i: `0`).isReg() &&
1632	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1633	MI.getOperand(i: `1`).isReg() &&
1634	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1635	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `24`)) {
1636	// lbu $rd, ${imm12}(${rs1})
1637	OutInst.setOpcode(RISCV::LBU);
1638	// Operand: rd
1639	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1640	// Operand: rs1
1641	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1642	// Operand: imm12
1643	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1644	OutInst.setLoc(MI.getLoc());
1645	return true;
1646	} // if
1647	break;
1648	} // case QC_E_LBU
1649	case RISCV::QC_E_LH: {
1650	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
1651	STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
1652	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1653	MI.getOperand(i: `0`).isReg() &&
1654	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1655	MI.getOperand(i: `1`).isReg() &&
1656	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1657	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `15`)) {
1658	// c.lh $rd, ${imm}(${rs1})
1659	OutInst.setOpcode(RISCV::C_LH);
1660	// Operand: rd
1661	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1662	// Operand: rs1
1663	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1664	// Operand: imm
1665	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1666	OutInst.setLoc(MI.getLoc());
1667	return true;
1668	} // if
1669	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
1670	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1671	MI.getOperand(i: `0`).isReg() &&
1672	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1673	MI.getOperand(i: `1`).isReg() &&
1674	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1675	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `24`)) {
1676	// lh $rd, ${imm12}(${rs1})
1677	OutInst.setOpcode(RISCV::LH);
1678	// Operand: rd
1679	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1680	// Operand: rs1
1681	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1682	// Operand: imm12
1683	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1684	OutInst.setLoc(MI.getLoc());
1685	return true;
1686	} // if
1687	break;
1688	} // case QC_E_LH
1689	case RISCV::QC_E_LHU: {
1690	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
1691	STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
1692	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1693	MI.getOperand(i: `0`).isReg() &&
1694	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1695	MI.getOperand(i: `1`).isReg() &&
1696	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1697	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `15`)) {
1698	// c.lhu $rd, ${imm}(${rs1})
1699	OutInst.setOpcode(RISCV::C_LHU);
1700	// Operand: rd
1701	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1702	// Operand: rs1
1703	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1704	// Operand: imm
1705	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1706	OutInst.setLoc(MI.getLoc());
1707	return true;
1708	} // if
1709	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
1710	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1711	MI.getOperand(i: `0`).isReg() &&
1712	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1713	MI.getOperand(i: `1`).isReg() &&
1714	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1715	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `24`)) {
1716	// lhu $rd, ${imm12}(${rs1})
1717	OutInst.setOpcode(RISCV::LHU);
1718	// Operand: rd
1719	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1720	// Operand: rs1
1721	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1722	// Operand: imm12
1723	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1724	OutInst.setLoc(MI.getLoc());
1725	return true;
1726	} // if
1727	break;
1728	} // case QC_E_LHU
1729	case RISCV::QC_E_LI: {
1730	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcili] &&
1731	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1732	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1733	MI.getOperand(i: `0`).isReg() &&
1734	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1735	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `1`), STI, PredicateIndex: `3`)) {
1736	// c.li $rd, $imm
1737	OutInst.setOpcode(RISCV::C_LI);
1738	// Operand: rd
1739	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1740	// Operand: imm
1741	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1742	OutInst.setLoc(MI.getLoc());
1743	return true;
1744	} // if
1745	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcili] &&
1746	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1747	MI.getOperand(i: `0`).isReg() &&
1748	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1749	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `1`), STI, PredicateIndex: `25`)) {
1750	// qc.li $rd, $imm20
1751	OutInst.setOpcode(RISCV::QC_LI);
1752	// Operand: rd
1753	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1754	// Operand: imm20
1755	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1756	OutInst.setLoc(MI.getLoc());
1757	return true;
1758	} // if
1759	break;
1760	} // case QC_E_LI
1761	case RISCV::QC_E_LW: {
1762	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
1763	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1764	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1765	MI.getOperand(i: `0`).isReg() &&
1766	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1767	MI.getOperand(i: `1`).isReg() &&
1768	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1769	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `9`)) {
1770	// c.lw $rd, ${imm}(${rs1})
1771	OutInst.setOpcode(RISCV::C_LW);
1772	// Operand: rd
1773	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1774	// Operand: rs1
1775	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1776	// Operand: imm
1777	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1778	OutInst.setLoc(MI.getLoc());
1779	return true;
1780	} // if
1781	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
1782	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1783	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1784	MI.getOperand(i: `0`).isReg() &&
1785	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1786	MI.getOperand(i: `1`).isReg() &&
1787	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1788	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `10`)) {
1789	// c.lwsp $rd, ${imm}(${rs1})
1790	OutInst.setOpcode(RISCV::C_LWSP);
1791	// Operand: rd
1792	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1793	// Operand: rs1
1794	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1795	// Operand: imm
1796	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1797	OutInst.setLoc(MI.getLoc());
1798	return true;
1799	} // if
1800	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
1801	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1802	MI.getOperand(i: `0`).isReg() &&
1803	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1804	MI.getOperand(i: `1`).isReg() &&
1805	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1806	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `24`)) {
1807	// lw $rd, ${imm12}(${rs1})
1808	OutInst.setOpcode(RISCV::LW);
1809	// Operand: rd
1810	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1811	// Operand: rs1
1812	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1813	// Operand: imm12
1814	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1815	OutInst.setLoc(MI.getLoc());
1816	return true;
1817	} // if
1818	break;
1819	} // case QC_E_LW
1820	case RISCV::QC_E_SB: {
1821	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
1822	STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
1823	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1824	MI.getOperand(i: `0`).isReg() &&
1825	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1826	MI.getOperand(i: `1`).isReg() &&
1827	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1828	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `12`)) {
1829	// c.sb $rs2, ${imm}(${rs1})
1830	OutInst.setOpcode(RISCV::C_SB);
1831	// Operand: rs2
1832	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1833	// Operand: rs1
1834	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1835	// Operand: imm
1836	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1837	OutInst.setLoc(MI.getLoc());
1838	return true;
1839	} // if
1840	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
1841	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1842	MI.getOperand(i: `0`).isReg() &&
1843	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1844	MI.getOperand(i: `1`).isReg() &&
1845	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1846	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `24`)) {
1847	// sb $rs2, ${imm12}(${rs1})
1848	OutInst.setOpcode(RISCV::SB);
1849	// Operand: rs2
1850	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1851	// Operand: rs1
1852	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1853	// Operand: imm12
1854	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1855	OutInst.setLoc(MI.getLoc());
1856	return true;
1857	} // if
1858	break;
1859	} // case QC_E_SB
1860	case RISCV::QC_E_SH: {
1861	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
1862	STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
1863	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1864	MI.getOperand(i: `0`).isReg() &&
1865	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1866	MI.getOperand(i: `1`).isReg() &&
1867	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1868	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `15`)) {
1869	// c.sh $rs2, ${imm}(${rs1})
1870	OutInst.setOpcode(RISCV::C_SH);
1871	// Operand: rs2
1872	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1873	// Operand: rs1
1874	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1875	// Operand: imm
1876	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1877	OutInst.setLoc(MI.getLoc());
1878	return true;
1879	} // if
1880	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
1881	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1882	MI.getOperand(i: `0`).isReg() &&
1883	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1884	MI.getOperand(i: `1`).isReg() &&
1885	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1886	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `24`)) {
1887	// sh $rs2, ${imm12}(${rs1})
1888	OutInst.setOpcode(RISCV::SH);
1889	// Operand: rs2
1890	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1891	// Operand: rs1
1892	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1893	// Operand: imm12
1894	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1895	OutInst.setLoc(MI.getLoc());
1896	return true;
1897	} // if
1898	break;
1899	} // case QC_E_SH
1900	case RISCV::QC_E_SW: {
1901	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
1902	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1903	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1904	MI.getOperand(i: `0`).isReg() &&
1905	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1906	MI.getOperand(i: `1`).isReg() &&
1907	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1908	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `9`)) {
1909	// c.sw $rs2, ${imm}(${rs1})
1910	OutInst.setOpcode(RISCV::C_SW);
1911	// Operand: rs2
1912	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1913	// Operand: rs1
1914	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1915	// Operand: imm
1916	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1917	OutInst.setLoc(MI.getLoc());
1918	return true;
1919	} // if
1920	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
1921	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1922	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1923	MI.getOperand(i: `0`).isReg() &&
1924	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1925	MI.getOperand(i: `1`).isReg() &&
1926	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1927	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `10`)) {
1928	// c.swsp $rs2, ${imm}(${rs1})
1929	OutInst.setOpcode(RISCV::C_SWSP);
1930	// Operand: rs2
1931	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1932	// Operand: rs1
1933	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1934	// Operand: imm
1935	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1936	OutInst.setLoc(MI.getLoc());
1937	return true;
1938	} // if
1939	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
1940	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1941	MI.getOperand(i: `0`).isReg() &&
1942	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1943	MI.getOperand(i: `1`).isReg() &&
1944	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
1945	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `24`)) {
1946	// sw $rs2, ${imm12}(${rs1})
1947	OutInst.setOpcode(RISCV::SW);
1948	// Operand: rs2
1949	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1950	// Operand: rs1
1951	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1952	// Operand: imm12
1953	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1954	OutInst.setLoc(MI.getLoc());
1955	return true;
1956	} // if
1957	break;
1958	} // case QC_E_SW
1959	case RISCV::QC_LI: {
1960	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcili] &&
1961	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1962	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1963	MI.getOperand(i: `0`).isReg() &&
1964	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1965	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `1`), STI, PredicateIndex: `3`)) {
1966	// c.li $rd, $imm
1967	OutInst.setOpcode(RISCV::C_LI);
1968	// Operand: rd
1969	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1970	// Operand: imm
1971	OutInst.addOperand(Op: MI.getOperand(i: `1`));
1972	OutInst.setLoc(MI.getLoc());
1973	return true;
1974	} // if
1975	break;
1976	} // case QC_LI
1977	case RISCV::QC_MULIADD: {
1978	if (STI.getFeatureBits()[RISCV::FeatureVendorXqciac] &&
1979	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1980	MI.getOperand(i: `0`).isReg() &&
1981	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
1982	MI.getOperand(i: `2`).isReg() &&
1983	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `2`).getReg()) &&
1984	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `3`), STI, PredicateIndex: `13`)) {
1985	// qc.c.muliadd $rd, $rs1, $uimm
1986	OutInst.setOpcode(RISCV::QC_C_MULIADD);
1987	// Operand: rd_wb
1988	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1989	// Operand: rd
1990	OutInst.addOperand(Op: MI.getOperand(i: `0`));
1991	// Operand: rs1
1992	OutInst.addOperand(Op: MI.getOperand(i: `2`));
1993	// Operand: uimm
1994	OutInst.addOperand(Op: MI.getOperand(i: `3`));
1995	OutInst.setLoc(MI.getLoc());
1996	return true;
1997	} // if
1998	break;
1999	} // case QC_MULIADD
2000	case RISCV::QC_MVEQI: {
2001	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcicm] &&
2002	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
2003	(MI.getOperand(i: `2`).isReg()) && (MI.getOperand(i: `0`).isReg()) &&
2004	(MI.getOperand(i: `2`).getReg() == MI.getOperand(i: `0`).getReg()) &&
2005	(MI.getOperand(i: `3`).isImm()) &&
2006	(MI.getOperand(i: `3`).getImm() == `0`) &&
2007	MI.getOperand(i: `2`).isReg() &&
2008	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `2`).getReg()) &&
2009	MI.getOperand(i: `4`).isReg() &&
2010	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `4`).getReg())) {
2011	// qc.c.mveqz $rd, $rs1
2012	OutInst.setOpcode(RISCV::QC_C_MVEQZ);
2013	// Operand: rd_wb
2014	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2015	// Operand: rd
2016	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2017	// Operand: rs1
2018	OutInst.addOperand(Op: MI.getOperand(i: `4`));
2019	OutInst.setLoc(MI.getLoc());
2020	return true;
2021	} // if
2022	break;
2023	} // case QC_MVEQI
2024	case RISCV::QC_MVLTUI: {
2025	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcicm] &&
2026	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
2027	(MI.getOperand(i: `2`).isReg()) && (MI.getOperand(i: `0`).isReg()) &&
2028	(MI.getOperand(i: `2`).getReg() == MI.getOperand(i: `0`).getReg()) &&
2029	(MI.getOperand(i: `3`).isImm()) &&
2030	(MI.getOperand(i: `3`).getImm() == `1`) &&
2031	MI.getOperand(i: `2`).isReg() &&
2032	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `2`).getReg()) &&
2033	MI.getOperand(i: `4`).isReg() &&
2034	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `4`).getReg())) {
2035	// qc.c.mveqz $rd, $rs1
2036	OutInst.setOpcode(RISCV::QC_C_MVEQZ);
2037	// Operand: rd_wb
2038	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2039	// Operand: rd
2040	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2041	// Operand: rs1
2042	OutInst.addOperand(Op: MI.getOperand(i: `4`));
2043	OutInst.setLoc(MI.getLoc());
2044	return true;
2045	} // if
2046	break;
2047	} // case QC_MVLTUI
2048	case RISCV::QC_SYNC: {
2049	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcisync] &&
2050	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
2051	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `0`), STI, PredicateIndex: `26`)) {
2052	// qc.c.sync $slist
2053	OutInst.setOpcode(RISCV::QC_C_SYNC);
2054	// Operand: slist
2055	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2056	OutInst.setLoc(MI.getLoc());
2057	return true;
2058	} // if
2059	break;
2060	} // case QC_SYNC
2061	case RISCV::QC_SYNCR: {
2062	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcisync] &&
2063	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
2064	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `0`), STI, PredicateIndex: `26`)) {
2065	// qc.c.syncr $slist
2066	OutInst.setOpcode(RISCV::QC_C_SYNCR);
2067	// Operand: slist
2068	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2069	OutInst.setLoc(MI.getLoc());
2070	return true;
2071	} // if
2072	break;
2073	} // case QC_SYNCR
2074	case RISCV::QC_SYNCWF: {
2075	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcisync] &&
2076	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
2077	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `0`), STI, PredicateIndex: `26`)) {
2078	// qc.c.syncwf $slist
2079	OutInst.setOpcode(RISCV::QC_C_SYNCWF);
2080	// Operand: slist
2081	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2082	OutInst.setLoc(MI.getLoc());
2083	return true;
2084	} // if
2085	break;
2086	} // case QC_SYNCWF
2087	case RISCV::QC_SYNCWL: {
2088	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcisync] &&
2089	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
2090	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `0`), STI, PredicateIndex: `26`)) {
2091	// qc.c.syncwl $slist
2092	OutInst.setOpcode(RISCV::QC_C_SYNCWL);
2093	// Operand: slist
2094	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2095	OutInst.setLoc(MI.getLoc());
2096	return true;
2097	} // if
2098	break;
2099	} // case QC_SYNCWL
2100	case RISCV::SB: {
2101	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
2102	MI.getOperand(i: `0`).isReg() &&
2103	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2104	MI.getOperand(i: `1`).isReg() &&
2105	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2106	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `12`)) {
2107	// c.sb $rs2, ${imm}(${rs1})
2108	OutInst.setOpcode(RISCV::C_SB);
2109	// Operand: rs2
2110	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2111	// Operand: rs1
2112	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2113	// Operand: imm
2114	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2115	OutInst.setLoc(MI.getLoc());
2116	return true;
2117	} // if
2118	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
2119	MI.getOperand(i: `0`).isReg() &&
2120	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2121	MI.getOperand(i: `1`).isReg() &&
2122	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2123	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `13`)) {
2124	// qk.c.sb $rs2, ${imm}(${rs1})
2125	OutInst.setOpcode(RISCV::QK_C_SB);
2126	// Operand: rs2
2127	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2128	// Operand: rs1
2129	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2130	// Operand: imm
2131	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2132	OutInst.setLoc(MI.getLoc());
2133	return true;
2134	} // if
2135	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
2136	MI.getOperand(i: `0`).isReg() &&
2137	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2138	MI.getOperand(i: `1`).isReg() &&
2139	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2140	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `14`)) {
2141	// qk.c.sbsp $rd_rs2, ${imm}(${rs1})
2142	OutInst.setOpcode(RISCV::QK_C_SBSP);
2143	// Operand: rd_rs2
2144	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2145	// Operand: rs1
2146	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2147	// Operand: imm
2148	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2149	OutInst.setLoc(MI.getLoc());
2150	return true;
2151	} // if
2152	break;
2153	} // case SB
2154	case RISCV::SD: {
2155	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
2156	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2157	MI.getOperand(i: `0`).isReg() &&
2158	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2159	MI.getOperand(i: `1`).isReg() &&
2160	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2161	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `7`)) {
2162	// c.sd $rs2, ${imm}(${rs1})
2163	OutInst.setOpcode(RISCV::C_SD);
2164	// Operand: rs2
2165	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2166	// Operand: rs1
2167	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2168	// Operand: imm
2169	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2170	OutInst.setLoc(MI.getLoc());
2171	return true;
2172	} // if
2173	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
2174	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2175	MI.getOperand(i: `0`).isReg() &&
2176	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2177	MI.getOperand(i: `1`).isReg() &&
2178	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2179	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `8`)) {
2180	// c.sdsp $rs2, ${imm}(${rs1})
2181	OutInst.setOpcode(RISCV::C_SDSP);
2182	// Operand: rs2
2183	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2184	// Operand: rs1
2185	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2186	// Operand: imm
2187	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2188	OutInst.setLoc(MI.getLoc());
2189	return true;
2190	} // if
2191	break;
2192	} // case SD
2193	case RISCV::SD_RV32: {
2194	if (STI.getFeatureBits()[RISCV::FeatureStdExtZclsd] &&
2195	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
2196	MI.getOperand(i: `0`).isReg() &&
2197	RISCVMCRegisterClasses[RISCV::GPRPairRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2198	MI.getOperand(i: `1`).isReg() &&
2199	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2200	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `8`)) {
2201	// c.sdsp $rs2, ${imm}(${rs1})
2202	OutInst.setOpcode(RISCV::C_SDSP_RV32);
2203	// Operand: rs2
2204	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2205	// Operand: rs1
2206	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2207	// Operand: imm
2208	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2209	OutInst.setLoc(MI.getLoc());
2210	return true;
2211	} // if
2212	if (STI.getFeatureBits()[RISCV::FeatureStdExtZclsd] &&
2213	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
2214	MI.getOperand(i: `0`).isReg() &&
2215	RISCVMCRegisterClasses[RISCV::GPRPairCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2216	MI.getOperand(i: `1`).isReg() &&
2217	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2218	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `7`)) {
2219	// c.sd $rs2, ${imm}(${rs1})
2220	OutInst.setOpcode(RISCV::C_SD_RV32);
2221	// Operand: rs2
2222	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2223	// Operand: rs1
2224	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2225	// Operand: imm
2226	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2227	OutInst.setLoc(MI.getLoc());
2228	return true;
2229	} // if
2230	break;
2231	} // case SD_RV32
2232	case RISCV::SEXT_B: {
2233	if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] &&
2234	STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
2235	(MI.getOperand(i: `1`).isReg()) && (MI.getOperand(i: `0`).isReg()) &&
2236	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
2237	MI.getOperand(i: `1`).isReg() &&
2238	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg())) {
2239	// c.sext.b $rd
2240	OutInst.setOpcode(RISCV::C_SEXT_B);
2241	// Operand: rd_wb
2242	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2243	// Operand: rd
2244	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2245	OutInst.setLoc(MI.getLoc());
2246	return true;
2247	} // if
2248	break;
2249	} // case SEXT_B
2250	case RISCV::SEXT_H: {
2251	if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] &&
2252	STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
2253	(MI.getOperand(i: `1`).isReg()) && (MI.getOperand(i: `0`).isReg()) &&
2254	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
2255	MI.getOperand(i: `1`).isReg() &&
2256	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg())) {
2257	// c.sext.h $rd
2258	OutInst.setOpcode(RISCV::C_SEXT_H);
2259	// Operand: rd_wb
2260	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2261	// Operand: rd
2262	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2263	OutInst.setLoc(MI.getLoc());
2264	return true;
2265	} // if
2266	break;
2267	} // case SEXT_H
2268	case RISCV::SH: {
2269	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
2270	MI.getOperand(i: `0`).isReg() &&
2271	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2272	MI.getOperand(i: `1`).isReg() &&
2273	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2274	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `15`)) {
2275	// c.sh $rs2, ${imm}(${rs1})
2276	OutInst.setOpcode(RISCV::C_SH);
2277	// Operand: rs2
2278	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2279	// Operand: rs1
2280	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2281	// Operand: imm
2282	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2283	OutInst.setLoc(MI.getLoc());
2284	return true;
2285	} // if
2286	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
2287	MI.getOperand(i: `0`).isReg() &&
2288	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2289	MI.getOperand(i: `1`).isReg() &&
2290	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2291	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `16`)) {
2292	// qk.c.sh $rs2, ${imm}(${rs1})
2293	OutInst.setOpcode(RISCV::QK_C_SH);
2294	// Operand: rs2
2295	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2296	// Operand: rs1
2297	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2298	// Operand: imm
2299	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2300	OutInst.setLoc(MI.getLoc());
2301	return true;
2302	} // if
2303	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
2304	MI.getOperand(i: `0`).isReg() &&
2305	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2306	MI.getOperand(i: `1`).isReg() &&
2307	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2308	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `17`)) {
2309	// qk.c.shsp $rd_rs2, ${imm}(${rs1})
2310	OutInst.setOpcode(RISCV::QK_C_SHSP);
2311	// Operand: rd_rs2
2312	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2313	// Operand: rs1
2314	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2315	// Operand: imm
2316	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2317	OutInst.setLoc(MI.getLoc());
2318	return true;
2319	} // if
2320	break;
2321	} // case SH
2322	case RISCV::SH_INX: {
2323	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
2324	MI.getOperand(i: `0`).isReg() &&
2325	RISCVMCRegisterClasses[RISCV::GPRF16CRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2326	MI.getOperand(i: `1`).isReg() &&
2327	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2328	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `15`)) {
2329	// c.sh $rs2, ${imm}(${rs1})
2330	OutInst.setOpcode(RISCV::C_SH_INX);
2331	// Operand: rs2
2332	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2333	// Operand: rs1
2334	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2335	// Operand: imm
2336	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2337	OutInst.setLoc(MI.getLoc());
2338	return true;
2339	} // if
2340	break;
2341	} // case SH_INX
2342	case RISCV::SLLI: {
2343	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2344	(MI.getOperand(i: `1`).isReg()) && (MI.getOperand(i: `0`).isReg()) &&
2345	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
2346	MI.getOperand(i: `1`).isReg() &&
2347	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2348	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `6`)) {
2349	// c.slli $rd, $imm
2350	OutInst.setOpcode(RISCV::C_SLLI);
2351	// Operand: rd_wb
2352	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2353	// Operand: rd
2354	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2355	// Operand: imm
2356	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2357	OutInst.setLoc(MI.getLoc());
2358	return true;
2359	} // if
2360	break;
2361	} // case SLLI
2362	case RISCV::SRAI: {
2363	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2364	(MI.getOperand(i: `1`).isReg()) && (MI.getOperand(i: `0`).isReg()) &&
2365	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
2366	MI.getOperand(i: `1`).isReg() &&
2367	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2368	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `6`)) {
2369	// c.srai $rs1, $imm
2370	OutInst.setOpcode(RISCV::C_SRAI);
2371	// Operand: rd
2372	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2373	// Operand: rs1
2374	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2375	// Operand: imm
2376	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2377	OutInst.setLoc(MI.getLoc());
2378	return true;
2379	} // if
2380	break;
2381	} // case SRAI
2382	case RISCV::SRLI: {
2383	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2384	(MI.getOperand(i: `1`).isReg()) && (MI.getOperand(i: `0`).isReg()) &&
2385	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
2386	MI.getOperand(i: `1`).isReg() &&
2387	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2388	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `6`)) {
2389	// c.srli $rs1, $imm
2390	OutInst.setOpcode(RISCV::C_SRLI);
2391	// Operand: rd
2392	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2393	// Operand: rs1
2394	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2395	// Operand: imm
2396	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2397	OutInst.setLoc(MI.getLoc());
2398	return true;
2399	} // if
2400	break;
2401	} // case SRLI
2402	case RISCV::SSPOPCHK: {
2403	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcmop] &&
2404	STI.getFeatureBits()[RISCV::FeatureStdExtZicfiss] &&
2405	(MI.getOperand(i: `0`).isReg()) &&
2406	(MI.getOperand(i: `0`).getReg() == RISCV::X5)) {
2407	// c.sspopchk $rs1
2408	OutInst.setOpcode(RISCV::C_SSPOPCHK);
2409	// Operand: rs1
2410	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X5));
2411	OutInst.setLoc(MI.getLoc());
2412	return true;
2413	} // if
2414	break;
2415	} // case SSPOPCHK
2416	case RISCV::SSPUSH: {
2417	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcmop] &&
2418	STI.getFeatureBits()[RISCV::FeatureStdExtZicfiss] &&
2419	(MI.getOperand(i: `0`).isReg()) &&
2420	(MI.getOperand(i: `0`).getReg() == RISCV::X1)) {
2421	// c.sspush $rs1
2422	OutInst.setOpcode(RISCV::C_SSPUSH);
2423	// Operand: rs1
2424	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X1));
2425	OutInst.setLoc(MI.getLoc());
2426	return true;
2427	} // if
2428	break;
2429	} // case SSPUSH
2430	case RISCV::SUB: {
2431	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2432	(MI.getOperand(i: `1`).isReg()) && (MI.getOperand(i: `0`).isReg()) &&
2433	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
2434	MI.getOperand(i: `1`).isReg() &&
2435	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2436	MI.getOperand(i: `2`).isReg() &&
2437	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `2`).getReg())) {
2438	// c.sub $rd, $rs2
2439	OutInst.setOpcode(RISCV::C_SUB);
2440	// Operand: rd_wb
2441	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2442	// Operand: rd
2443	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2444	// Operand: rs2
2445	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2446	OutInst.setLoc(MI.getLoc());
2447	return true;
2448	} // if
2449	break;
2450	} // case SUB
2451	case RISCV::SUBW: {
2452	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
2453	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2454	(MI.getOperand(i: `1`).isReg()) && (MI.getOperand(i: `0`).isReg()) &&
2455	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
2456	MI.getOperand(i: `1`).isReg() &&
2457	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2458	MI.getOperand(i: `2`).isReg() &&
2459	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `2`).getReg())) {
2460	// c.subw $rd, $rs2
2461	OutInst.setOpcode(RISCV::C_SUBW);
2462	// Operand: rd_wb
2463	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2464	// Operand: rd
2465	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2466	// Operand: rs2
2467	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2468	OutInst.setLoc(MI.getLoc());
2469	return true;
2470	} // if
2471	break;
2472	} // case SUBW
2473	case RISCV::SW: {
2474	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2475	MI.getOperand(i: `0`).isReg() &&
2476	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2477	MI.getOperand(i: `1`).isReg() &&
2478	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2479	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `9`)) {
2480	// c.sw $rs2, ${imm}(${rs1})
2481	OutInst.setOpcode(RISCV::C_SW);
2482	// Operand: rs2
2483	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2484	// Operand: rs1
2485	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2486	// Operand: imm
2487	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2488	OutInst.setLoc(MI.getLoc());
2489	return true;
2490	} // if
2491	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2492	MI.getOperand(i: `0`).isReg() &&
2493	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2494	MI.getOperand(i: `1`).isReg() &&
2495	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2496	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `10`)) {
2497	// c.swsp $rs2, ${imm}(${rs1})
2498	OutInst.setOpcode(RISCV::C_SWSP);
2499	// Operand: rs2
2500	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2501	// Operand: rs1
2502	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2503	// Operand: imm
2504	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2505	OutInst.setLoc(MI.getLoc());
2506	return true;
2507	} // if
2508	break;
2509	} // case SW
2510	case RISCV::SW_INX: {
2511	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2512	MI.getOperand(i: `0`).isReg() &&
2513	RISCVMCRegisterClasses[RISCV::GPRF32CRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2514	MI.getOperand(i: `1`).isReg() &&
2515	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2516	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `9`)) {
2517	// c.sw $rs2, ${imm}(${rs1})
2518	OutInst.setOpcode(RISCV::C_SW_INX);
2519	// Operand: rs2
2520	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2521	// Operand: rs1
2522	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2523	// Operand: imm
2524	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2525	OutInst.setLoc(MI.getLoc());
2526	return true;
2527	} // if
2528	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2529	MI.getOperand(i: `0`).isReg() &&
2530	RISCVMCRegisterClasses[RISCV::GPRF32RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2531	MI.getOperand(i: `1`).isReg() &&
2532	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2533	RISCVValidateMCOperandForCompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `10`)) {
2534	// c.swsp $rs2, ${imm}(${rs1})
2535	OutInst.setOpcode(RISCV::C_SWSP_INX);
2536	// Operand: rs2
2537	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2538	// Operand: rs1
2539	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2540	// Operand: imm
2541	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2542	OutInst.setLoc(MI.getLoc());
2543	return true;
2544	} // if
2545	break;
2546	} // case SW_INX
2547	case RISCV::UNIMP: {
2548	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca])) {
2549	// c.unimp
2550	OutInst.setOpcode(RISCV::C_UNIMP);
2551	OutInst.setLoc(MI.getLoc());
2552	return true;
2553	} // if
2554	break;
2555	} // case UNIMP
2556	case RISCV::XOR: {
2557	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2558	(MI.getOperand(i: `1`).isReg()) && (MI.getOperand(i: `0`).isReg()) &&
2559	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
2560	MI.getOperand(i: `1`).isReg() &&
2561	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2562	MI.getOperand(i: `2`).isReg() &&
2563	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `2`).getReg())) {
2564	// c.xor $rd, $rs2
2565	OutInst.setOpcode(RISCV::C_XOR);
2566	// Operand: rd_wb
2567	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2568	// Operand: rd
2569	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2570	// Operand: rs2
2571	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2572	OutInst.setLoc(MI.getLoc());
2573	return true;
2574	} // if
2575	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2576	(MI.getOperand(i: `2`).isReg()) && (MI.getOperand(i: `0`).isReg()) &&
2577	(MI.getOperand(i: `2`).getReg() == MI.getOperand(i: `0`).getReg()) &&
2578	MI.getOperand(i: `2`).isReg() &&
2579	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `2`).getReg()) &&
2580	MI.getOperand(i: `1`).isReg() &&
2581	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg())) {
2582	// c.xor $rd, $rs2
2583	OutInst.setOpcode(RISCV::C_XOR);
2584	// Operand: rd_wb
2585	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2586	// Operand: rd
2587	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2588	// Operand: rs2
2589	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2590	OutInst.setLoc(MI.getLoc());
2591	return true;
2592	} // if
2593	break;
2594	} // case XOR
2595	case RISCV::XORI: {
2596	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
2597	(MI.getOperand(i: `1`).isReg()) && (MI.getOperand(i: `0`).isReg()) &&
2598	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
2599	(MI.getOperand(i: `2`).isImm()) &&
2600	(MI.getOperand(i: `2`).getImm() == -`1`) &&
2601	MI.getOperand(i: `1`).isReg() &&
2602	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg())) {
2603	// c.not $rd
2604	OutInst.setOpcode(RISCV::C_NOT);
2605	// Operand: rd_wb
2606	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2607	// Operand: rd
2608	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2609	OutInst.setLoc(MI.getLoc());
2610	return true;
2611	} // if
2612	break;
2613	} // case XORI
2614	case RISCV::ZEXT_H_RV32: {
2615	if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] &&
2616	STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
2617	(MI.getOperand(i: `1`).isReg()) && (MI.getOperand(i: `0`).isReg()) &&
2618	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
2619	MI.getOperand(i: `1`).isReg() &&
2620	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg())) {
2621	// c.zext.h $rd
2622	OutInst.setOpcode(RISCV::C_ZEXT_H);
2623	// Operand: rd_wb
2624	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2625	// Operand: rd
2626	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2627	OutInst.setLoc(MI.getLoc());
2628	return true;
2629	} // if
2630	break;
2631	} // case ZEXT_H_RV32
2632	case RISCV::ZEXT_H_RV64: {
2633	if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] &&
2634	STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
2635	(MI.getOperand(i: `1`).isReg()) && (MI.getOperand(i: `0`).isReg()) &&
2636	(MI.getOperand(i: `1`).getReg() == MI.getOperand(i: `0`).getReg()) &&
2637	MI.getOperand(i: `1`).isReg() &&
2638	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg())) {
2639	// c.zext.h $rd
2640	OutInst.setOpcode(RISCV::C_ZEXT_H);
2641	// Operand: rd_wb
2642	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2643	// Operand: rd
2644	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2645	OutInst.setLoc(MI.getLoc());
2646	return true;
2647	} // if
2648
2649	} // case ZEXT_H_RV64
2650	} // switch
2651	return false;
2652	}
2653
2654	#endif //GEN_COMPRESS_INSTR
2655
2656	#ifdef GEN_UNCOMPRESS_INSTR
2657	#undef GEN_UNCOMPRESS_INSTR
2658
2659	static bool RISCVValidateMCOperandForUncompress(const MCOperand &MCOp,
2660	const MCSubtargetInfo &STI,
2661	unsigned PredicateIndex) {
2662	switch (PredicateIndex) {
2663	default:
2664	llvm_unreachable("Unknown MCOperandPredicate kind");
2665	break;
2666	case `1`: {
2667	// simm12
2668	int64_t Imm;
2669	if (MCOp.evaluateAsConstantImm(Imm))
2670	return isInt<`12`>(x: Imm);
2671	return MCOp.isBareSymbolRef();
2672	}
2673	case `2`: {
2674	// bare_simm13_lsb0
2675	int64_t Imm;
2676	if (MCOp.evaluateAsConstantImm(Imm))
2677	return isShiftedInt<`12`, `1`>(x: Imm);
2678	return MCOp.isBareSymbolRef();
2679	}
2680	case `3`: {
2681	// simm21_lsb0_jal
2682	int64_t Imm;
2683	if (MCOp.evaluateAsConstantImm(Imm))
2684	return isShiftedInt<`20`, `1`>(x: Imm);
2685	return MCOp.isBareSymbolRef();
2686	}
2687	case `4`: {
2688	// simm20_li
2689	int64_t Imm;
2690	if (MCOp.evaluateAsConstantImm(Imm))
2691	return isInt<`20`>(x: Imm);
2692	return MCOp.isBareSymbolRef();
2693	}
2694	case `5`: {
2695	// uimm20_lui
2696	int64_t Imm;
2697	if (MCOp.evaluateAsConstantImm(Imm))
2698	return isUInt<`20`>(x: Imm);
2699	return MCOp.isBareSymbolRef();
2700	}
2701	case `6`: {
2702	// uimmlog2xlen
2703	int64_t Imm;
2704	if (!MCOp.evaluateAsConstantImm(Imm))
2705	return false;
2706	if (STI.getTargetTriple().isArch64Bit())
2707	return isUInt<`6`>(x: Imm);
2708	return isUInt<`5`>(x: Imm);
2709	}
2710	case `7`: {
2711	// uimm5_plus1
2712	int64_t Imm;
2713	if (!MCOp.evaluateAsConstantImm(Imm))
2714	return false;
2715	return (isUInt<`5`>(x: Imm) && (Imm != `0`)) \|\| (Imm == `32`);
2716	}
2717	case `8`: {
2718	// uimm5
2719	int64_t Imm;
2720	if (!MCOp.evaluateAsConstantImm(Imm))
2721	return false;
2722	return isUInt<`5`>(x: Imm);
2723	}
2724	case `9`: {
2725	// simm5
2726	int64_t Imm;
2727	if (MCOp.evaluateAsConstantImm(Imm))
2728	return isInt<`5`>(x: Imm);
2729	return MCOp.isBareSymbolRef();
2730	}
2731	}
2732	}
2733
2734	static bool uncompressInst(MCInst &OutInst,
2735	const MCInst &MI,
2736	const MCSubtargetInfo &STI) {
2737	switch (MI.getOpcode()) {
2738	default: return false;
2739	case RISCV::C_ADD: {
2740	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2741	MI.getOperand(i: `0`).isReg() &&
2742	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2743	MI.getOperand(i: `0`).isReg() &&
2744	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2745	MI.getOperand(i: `2`).isReg() &&
2746	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `2`).getReg())) {
2747	// add $rd, $rs1, $rs2
2748	OutInst.setOpcode(RISCV::ADD);
2749	// Operand: rd
2750	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2751	// Operand: rs1
2752	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2753	// Operand: rs2
2754	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2755	OutInst.setLoc(MI.getLoc());
2756	return true;
2757	} // if
2758	break;
2759	} // case C_ADD
2760	case RISCV::C_ADDI: {
2761	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2762	MI.getOperand(i: `0`).isReg() &&
2763	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2764	MI.getOperand(i: `0`).isReg() &&
2765	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2766	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `1`)) {
2767	// addi $rd, $rs1, $imm12
2768	OutInst.setOpcode(RISCV::ADDI);
2769	// Operand: rd
2770	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2771	// Operand: rs1
2772	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2773	// Operand: imm12
2774	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2775	OutInst.setLoc(MI.getLoc());
2776	return true;
2777	} // if
2778	break;
2779	} // case C_ADDI
2780	case RISCV::C_ADDI16SP: {
2781	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2782	(MI.getOperand(i: `0`).isReg()) &&
2783	(MI.getOperand(i: `0`).getReg() == RISCV::X2) &&
2784	(MI.getOperand(i: `1`).isReg()) &&
2785	(MI.getOperand(i: `1`).getReg() == RISCV::X2) &&
2786	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `1`)) {
2787	// addi $rd, $rs1, $imm12
2788	OutInst.setOpcode(RISCV::ADDI);
2789	// Operand: rd
2790	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X2));
2791	// Operand: rs1
2792	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X2));
2793	// Operand: imm12
2794	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2795	OutInst.setLoc(MI.getLoc());
2796	return true;
2797	} // if
2798	break;
2799	} // case C_ADDI16SP
2800	case RISCV::C_ADDI4SPN: {
2801	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2802	MI.getOperand(i: `0`).isReg() &&
2803	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2804	MI.getOperand(i: `1`).isReg() &&
2805	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2806	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `1`)) {
2807	// addi $rd, $rs1, $imm12
2808	OutInst.setOpcode(RISCV::ADDI);
2809	// Operand: rd
2810	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2811	// Operand: rs1
2812	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2813	// Operand: imm12
2814	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2815	OutInst.setLoc(MI.getLoc());
2816	return true;
2817	} // if
2818	break;
2819	} // case C_ADDI4SPN
2820	case RISCV::C_ADDIW: {
2821	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
2822	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2823	MI.getOperand(i: `0`).isReg() &&
2824	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2825	MI.getOperand(i: `0`).isReg() &&
2826	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2827	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `1`)) {
2828	// addiw $rd, $rs1, $imm12
2829	OutInst.setOpcode(RISCV::ADDIW);
2830	// Operand: rd
2831	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2832	// Operand: rs1
2833	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2834	// Operand: imm12
2835	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2836	OutInst.setLoc(MI.getLoc());
2837	return true;
2838	} // if
2839	break;
2840	} // case C_ADDIW
2841	case RISCV::C_ADDW: {
2842	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
2843	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2844	MI.getOperand(i: `0`).isReg() &&
2845	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2846	MI.getOperand(i: `0`).isReg() &&
2847	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2848	MI.getOperand(i: `2`).isReg() &&
2849	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `2`).getReg())) {
2850	// addw $rd, $rs1, $rs2
2851	OutInst.setOpcode(RISCV::ADDW);
2852	// Operand: rd
2853	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2854	// Operand: rs1
2855	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2856	// Operand: rs2
2857	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2858	OutInst.setLoc(MI.getLoc());
2859	return true;
2860	} // if
2861	break;
2862	} // case C_ADDW
2863	case RISCV::C_AND: {
2864	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2865	MI.getOperand(i: `0`).isReg() &&
2866	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2867	MI.getOperand(i: `0`).isReg() &&
2868	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2869	MI.getOperand(i: `2`).isReg() &&
2870	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `2`).getReg())) {
2871	// and $rd, $rs1, $rs2
2872	OutInst.setOpcode(RISCV::AND);
2873	// Operand: rd
2874	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2875	// Operand: rs1
2876	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2877	// Operand: rs2
2878	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2879	OutInst.setLoc(MI.getLoc());
2880	return true;
2881	} // if
2882	break;
2883	} // case C_AND
2884	case RISCV::C_ANDI: {
2885	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2886	MI.getOperand(i: `0`).isReg() &&
2887	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2888	MI.getOperand(i: `0`).isReg() &&
2889	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2890	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `1`)) {
2891	// andi $rd, $rs1, $imm12
2892	OutInst.setOpcode(RISCV::ANDI);
2893	// Operand: rd
2894	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2895	// Operand: rs1
2896	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2897	// Operand: imm12
2898	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2899	OutInst.setLoc(MI.getLoc());
2900	return true;
2901	} // if
2902	break;
2903	} // case C_ANDI
2904	case RISCV::C_BEQZ: {
2905	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2906	MI.getOperand(i: `0`).isReg() &&
2907	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2908	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `1`), STI, PredicateIndex: `2`)) {
2909	// beq $rs1, $rs2, $imm12
2910	OutInst.setOpcode(RISCV::BEQ);
2911	// Operand: rs1
2912	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2913	// Operand: rs2
2914	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X0));
2915	// Operand: imm12
2916	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2917	OutInst.setLoc(MI.getLoc());
2918	return true;
2919	} // if
2920	break;
2921	} // case C_BEQZ
2922	case RISCV::C_BNEZ: {
2923	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2924	MI.getOperand(i: `0`).isReg() &&
2925	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2926	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `1`), STI, PredicateIndex: `2`)) {
2927	// bne $rs1, $rs2, $imm12
2928	OutInst.setOpcode(RISCV::BNE);
2929	// Operand: rs1
2930	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2931	// Operand: rs2
2932	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X0));
2933	// Operand: imm12
2934	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2935	OutInst.setLoc(MI.getLoc());
2936	return true;
2937	} // if
2938	break;
2939	} // case C_BNEZ
2940	case RISCV::C_EBREAK: {
2941	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca])) {
2942	// ebreak
2943	OutInst.setOpcode(RISCV::EBREAK);
2944	OutInst.setLoc(MI.getLoc());
2945	return true;
2946	} // if
2947	break;
2948	} // case C_EBREAK
2949	case RISCV::C_FLD: {
2950	if (STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
2951	(STI.getFeatureBits()[RISCV::FeatureStdExtC] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZcd]) &&
2952	MI.getOperand(i: `0`).isReg() &&
2953	RISCVMCRegisterClasses[RISCV::FPR64RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2954	MI.getOperand(i: `1`).isReg() &&
2955	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2956	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `1`)) {
2957	// fld $rd, ${imm12}(${rs1})
2958	OutInst.setOpcode(RISCV::FLD);
2959	// Operand: rd
2960	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2961	// Operand: rs1
2962	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2963	// Operand: imm12
2964	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2965	OutInst.setLoc(MI.getLoc());
2966	return true;
2967	} // if
2968	break;
2969	} // case C_FLD
2970	case RISCV::C_FLDSP: {
2971	if (STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
2972	(STI.getFeatureBits()[RISCV::FeatureStdExtC] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZcd]) &&
2973	MI.getOperand(i: `0`).isReg() &&
2974	RISCVMCRegisterClasses[RISCV::FPR64RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2975	MI.getOperand(i: `1`).isReg() &&
2976	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2977	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `1`)) {
2978	// fld $rd, ${imm12}(${rs1})
2979	OutInst.setOpcode(RISCV::FLD);
2980	// Operand: rd
2981	OutInst.addOperand(Op: MI.getOperand(i: `0`));
2982	// Operand: rs1
2983	OutInst.addOperand(Op: MI.getOperand(i: `1`));
2984	// Operand: imm12
2985	OutInst.addOperand(Op: MI.getOperand(i: `2`));
2986	OutInst.setLoc(MI.getLoc());
2987	return true;
2988	} // if
2989	break;
2990	} // case C_FLDSP
2991	case RISCV::C_FLW: {
2992	if (STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
2993	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
2994	(STI.getFeatureBits()[RISCV::FeatureStdExtC] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZce] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZcf]) &&
2995	MI.getOperand(i: `0`).isReg() &&
2996	RISCVMCRegisterClasses[RISCV::FPR32RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
2997	MI.getOperand(i: `1`).isReg() &&
2998	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
2999	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `1`)) {
3000	// flw $rd, ${imm12}(${rs1})
3001	OutInst.setOpcode(RISCV::FLW);
3002	// Operand: rd
3003	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3004	// Operand: rs1
3005	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3006	// Operand: imm12
3007	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3008	OutInst.setLoc(MI.getLoc());
3009	return true;
3010	} // if
3011	break;
3012	} // case C_FLW
3013	case RISCV::C_FLWSP: {
3014	if (STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
3015	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
3016	(STI.getFeatureBits()[RISCV::FeatureStdExtC] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZce] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZcf]) &&
3017	MI.getOperand(i: `0`).isReg() &&
3018	RISCVMCRegisterClasses[RISCV::FPR32RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3019	MI.getOperand(i: `1`).isReg() &&
3020	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
3021	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `1`)) {
3022	// flw $rd, ${imm12}(${rs1})
3023	OutInst.setOpcode(RISCV::FLW);
3024	// Operand: rd
3025	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3026	// Operand: rs1
3027	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3028	// Operand: imm12
3029	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3030	OutInst.setLoc(MI.getLoc());
3031	return true;
3032	} // if
3033	break;
3034	} // case C_FLWSP
3035	case RISCV::C_FSD: {
3036	if (STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
3037	(STI.getFeatureBits()[RISCV::FeatureStdExtC] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZcd]) &&
3038	MI.getOperand(i: `0`).isReg() &&
3039	RISCVMCRegisterClasses[RISCV::FPR64RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3040	MI.getOperand(i: `1`).isReg() &&
3041	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
3042	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `1`)) {
3043	// fsd $rs2, ${imm12}(${rs1})
3044	OutInst.setOpcode(RISCV::FSD);
3045	// Operand: rs2
3046	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3047	// Operand: rs1
3048	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3049	// Operand: imm12
3050	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3051	OutInst.setLoc(MI.getLoc());
3052	return true;
3053	} // if
3054	break;
3055	} // case C_FSD
3056	case RISCV::C_FSDSP: {
3057	if (STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
3058	(STI.getFeatureBits()[RISCV::FeatureStdExtC] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZcd]) &&
3059	MI.getOperand(i: `0`).isReg() &&
3060	RISCVMCRegisterClasses[RISCV::FPR64RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3061	MI.getOperand(i: `1`).isReg() &&
3062	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
3063	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `1`)) {
3064	// fsd $rs2, ${imm12}(${rs1})
3065	OutInst.setOpcode(RISCV::FSD);
3066	// Operand: rs2
3067	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3068	// Operand: rs1
3069	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3070	// Operand: imm12
3071	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3072	OutInst.setLoc(MI.getLoc());
3073	return true;
3074	} // if
3075	break;
3076	} // case C_FSDSP
3077	case RISCV::C_FSW: {
3078	if (STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
3079	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
3080	(STI.getFeatureBits()[RISCV::FeatureStdExtC] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZce] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZcf]) &&
3081	MI.getOperand(i: `0`).isReg() &&
3082	RISCVMCRegisterClasses[RISCV::FPR32RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3083	MI.getOperand(i: `1`).isReg() &&
3084	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
3085	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `1`)) {
3086	// fsw $rs2, ${imm12}(${rs1})
3087	OutInst.setOpcode(RISCV::FSW);
3088	// Operand: rs2
3089	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3090	// Operand: rs1
3091	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3092	// Operand: imm12
3093	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3094	OutInst.setLoc(MI.getLoc());
3095	return true;
3096	} // if
3097	break;
3098	} // case C_FSW
3099	case RISCV::C_FSWSP: {
3100	if (STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
3101	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
3102	(STI.getFeatureBits()[RISCV::FeatureStdExtC] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZce] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZcf]) &&
3103	MI.getOperand(i: `0`).isReg() &&
3104	RISCVMCRegisterClasses[RISCV::FPR32RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3105	MI.getOperand(i: `1`).isReg() &&
3106	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
3107	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `1`)) {
3108	// fsw $rs2, ${imm12}(${rs1})
3109	OutInst.setOpcode(RISCV::FSW);
3110	// Operand: rs2
3111	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3112	// Operand: rs1
3113	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3114	// Operand: imm12
3115	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3116	OutInst.setLoc(MI.getLoc());
3117	return true;
3118	} // if
3119	break;
3120	} // case C_FSWSP
3121	case RISCV::C_J: {
3122	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3123	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `0`), STI, PredicateIndex: `3`)) {
3124	// jal $rd, $imm20
3125	OutInst.setOpcode(RISCV::JAL);
3126	// Operand: rd
3127	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X0));
3128	// Operand: imm20
3129	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3130	OutInst.setLoc(MI.getLoc());
3131	return true;
3132	} // if
3133	break;
3134	} // case C_J
3135	case RISCV::C_JAL: {
3136	if (!STI.getFeatureBits()[RISCV::Feature64Bit] &&
3137	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3138	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `0`), STI, PredicateIndex: `3`)) {
3139	// jal $rd, $imm20
3140	OutInst.setOpcode(RISCV::JAL);
3141	// Operand: rd
3142	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X1));
3143	// Operand: imm20
3144	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3145	OutInst.setLoc(MI.getLoc());
3146	return true;
3147	} // if
3148	break;
3149	} // case C_JAL
3150	case RISCV::C_JALR: {
3151	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3152	MI.getOperand(i: `0`).isReg() &&
3153	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3154	RISCVValidateMCOperandForUncompress(MCOp: MCOperand::createImm(Val: `0`), STI, PredicateIndex: `1`)) {
3155	// jalr $rd, ${imm12}(${rs1})
3156	OutInst.setOpcode(RISCV::JALR);
3157	// Operand: rd
3158	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X1));
3159	// Operand: rs1
3160	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3161	// Operand: imm12
3162	OutInst.addOperand(Op: MCOperand::createImm(Val: `0`));
3163	OutInst.setLoc(MI.getLoc());
3164	return true;
3165	} // if
3166	break;
3167	} // case C_JALR
3168	case RISCV::C_JR: {
3169	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3170	MI.getOperand(i: `0`).isReg() &&
3171	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3172	RISCVValidateMCOperandForUncompress(MCOp: MCOperand::createImm(Val: `0`), STI, PredicateIndex: `1`)) {
3173	// jalr $rd, ${imm12}(${rs1})
3174	OutInst.setOpcode(RISCV::JALR);
3175	// Operand: rd
3176	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X0));
3177	// Operand: rs1
3178	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3179	// Operand: imm12
3180	OutInst.addOperand(Op: MCOperand::createImm(Val: `0`));
3181	OutInst.setLoc(MI.getLoc());
3182	return true;
3183	} // if
3184	break;
3185	} // case C_JR
3186	case RISCV::C_LBU: {
3187	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
3188	MI.getOperand(i: `0`).isReg() &&
3189	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3190	MI.getOperand(i: `1`).isReg() &&
3191	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
3192	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `1`)) {
3193	// lbu $rd, ${imm12}(${rs1})
3194	OutInst.setOpcode(RISCV::LBU);
3195	// Operand: rd
3196	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3197	// Operand: rs1
3198	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3199	// Operand: imm12
3200	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3201	OutInst.setLoc(MI.getLoc());
3202	return true;
3203	} // if
3204	break;
3205	} // case C_LBU
3206	case RISCV::C_LD: {
3207	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
3208	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3209	MI.getOperand(i: `0`).isReg() &&
3210	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3211	MI.getOperand(i: `1`).isReg() &&
3212	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
3213	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `1`)) {
3214	// ld $rd, ${imm12}(${rs1})
3215	OutInst.setOpcode(RISCV::LD);
3216	// Operand: rd
3217	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3218	// Operand: rs1
3219	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3220	// Operand: imm12
3221	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3222	OutInst.setLoc(MI.getLoc());
3223	return true;
3224	} // if
3225	break;
3226	} // case C_LD
3227	case RISCV::C_LDSP: {
3228	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
3229	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3230	MI.getOperand(i: `0`).isReg() &&
3231	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3232	MI.getOperand(i: `1`).isReg() &&
3233	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
3234	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `1`)) {
3235	// ld $rd, ${imm12}(${rs1})
3236	OutInst.setOpcode(RISCV::LD);
3237	// Operand: rd
3238	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3239	// Operand: rs1
3240	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3241	// Operand: imm12
3242	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3243	OutInst.setLoc(MI.getLoc());
3244	return true;
3245	} // if
3246	break;
3247	} // case C_LDSP
3248	case RISCV::C_LDSP_RV32: {
3249	if (STI.getFeatureBits()[RISCV::FeatureStdExtZclsd] &&
3250	STI.getFeatureBits()[RISCV::FeatureStdExtZilsd] &&
3251	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
3252	MI.getOperand(i: `0`).isReg() &&
3253	RISCVMCRegisterClasses[RISCV::GPRPairRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3254	MI.getOperand(i: `1`).isReg() &&
3255	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
3256	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `1`)) {
3257	// ld $rd, ${imm12}(${rs1})
3258	OutInst.setOpcode(RISCV::LD_RV32);
3259	// Operand: rd
3260	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3261	// Operand: rs1
3262	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3263	// Operand: imm12
3264	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3265	OutInst.setLoc(MI.getLoc());
3266	return true;
3267	} // if
3268	break;
3269	} // case C_LDSP_RV32
3270	case RISCV::C_LD_RV32: {
3271	if (STI.getFeatureBits()[RISCV::FeatureStdExtZclsd] &&
3272	STI.getFeatureBits()[RISCV::FeatureStdExtZilsd] &&
3273	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
3274	MI.getOperand(i: `0`).isReg() &&
3275	RISCVMCRegisterClasses[RISCV::GPRPairRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3276	MI.getOperand(i: `1`).isReg() &&
3277	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
3278	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `1`)) {
3279	// ld $rd, ${imm12}(${rs1})
3280	OutInst.setOpcode(RISCV::LD_RV32);
3281	// Operand: rd
3282	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3283	// Operand: rs1
3284	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3285	// Operand: imm12
3286	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3287	OutInst.setLoc(MI.getLoc());
3288	return true;
3289	} // if
3290	break;
3291	} // case C_LD_RV32
3292	case RISCV::C_LH: {
3293	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
3294	MI.getOperand(i: `0`).isReg() &&
3295	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3296	MI.getOperand(i: `1`).isReg() &&
3297	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
3298	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `1`)) {
3299	// lh $rd, ${imm12}(${rs1})
3300	OutInst.setOpcode(RISCV::LH);
3301	// Operand: rd
3302	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3303	// Operand: rs1
3304	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3305	// Operand: imm12
3306	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3307	OutInst.setLoc(MI.getLoc());
3308	return true;
3309	} // if
3310	break;
3311	} // case C_LH
3312	case RISCV::C_LHU: {
3313	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
3314	MI.getOperand(i: `0`).isReg() &&
3315	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3316	MI.getOperand(i: `1`).isReg() &&
3317	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
3318	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `1`)) {
3319	// lhu $rd, ${imm12}(${rs1})
3320	OutInst.setOpcode(RISCV::LHU);
3321	// Operand: rd
3322	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3323	// Operand: rs1
3324	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3325	// Operand: imm12
3326	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3327	OutInst.setLoc(MI.getLoc());
3328	return true;
3329	} // if
3330	break;
3331	} // case C_LHU
3332	case RISCV::C_LI: {
3333	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3334	MI.getOperand(i: `0`).isReg() &&
3335	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3336	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `1`), STI, PredicateIndex: `1`)) {
3337	// addi $rd, $rs1, $imm12
3338	OutInst.setOpcode(RISCV::ADDI);
3339	// Operand: rd
3340	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3341	// Operand: rs1
3342	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X0));
3343	// Operand: imm12
3344	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3345	OutInst.setLoc(MI.getLoc());
3346	return true;
3347	} // if
3348	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcili] &&
3349	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
3350	MI.getOperand(i: `0`).isReg() &&
3351	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3352	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `1`), STI, PredicateIndex: `4`)) {
3353	// qc.li $rd, $imm20
3354	OutInst.setOpcode(RISCV::QC_LI);
3355	// Operand: rd
3356	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3357	// Operand: imm20
3358	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3359	OutInst.setLoc(MI.getLoc());
3360	return true;
3361	} // if
3362	break;
3363	} // case C_LI
3364	case RISCV::C_LUI: {
3365	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3366	MI.getOperand(i: `0`).isReg() &&
3367	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3368	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `1`), STI, PredicateIndex: `5`)) {
3369	// lui $rd, $imm20
3370	OutInst.setOpcode(RISCV::LUI);
3371	// Operand: rd
3372	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3373	// Operand: imm20
3374	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3375	OutInst.setLoc(MI.getLoc());
3376	return true;
3377	} // if
3378	break;
3379	} // case C_LUI
3380	case RISCV::C_LW: {
3381	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3382	MI.getOperand(i: `0`).isReg() &&
3383	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3384	MI.getOperand(i: `1`).isReg() &&
3385	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
3386	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `1`)) {
3387	// lw $rd, ${imm12}(${rs1})
3388	OutInst.setOpcode(RISCV::LW);
3389	// Operand: rd
3390	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3391	// Operand: rs1
3392	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3393	// Operand: imm12
3394	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3395	OutInst.setLoc(MI.getLoc());
3396	return true;
3397	} // if
3398	break;
3399	} // case C_LW
3400	case RISCV::C_LWSP: {
3401	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3402	MI.getOperand(i: `0`).isReg() &&
3403	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3404	MI.getOperand(i: `1`).isReg() &&
3405	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
3406	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `1`)) {
3407	// lw $rd, ${imm12}(${rs1})
3408	OutInst.setOpcode(RISCV::LW);
3409	// Operand: rd
3410	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3411	// Operand: rs1
3412	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3413	// Operand: imm12
3414	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3415	OutInst.setLoc(MI.getLoc());
3416	return true;
3417	} // if
3418	break;
3419	} // case C_LWSP
3420	case RISCV::C_MUL: {
3421	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
3422	STI.getFeatureBits()[RISCV::FeatureStdExtZmmul] &&
3423	MI.getOperand(i: `0`).isReg() &&
3424	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3425	MI.getOperand(i: `0`).isReg() &&
3426	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3427	MI.getOperand(i: `2`).isReg() &&
3428	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `2`).getReg())) {
3429	// mul $rd, $rs1, $rs2
3430	OutInst.setOpcode(RISCV::MUL);
3431	// Operand: rd
3432	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3433	// Operand: rs1
3434	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3435	// Operand: rs2
3436	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3437	OutInst.setLoc(MI.getLoc());
3438	return true;
3439	} // if
3440	break;
3441	} // case C_MUL
3442	case RISCV::C_MV: {
3443	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3444	MI.getOperand(i: `0`).isReg() &&
3445	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3446	MI.getOperand(i: `1`).isReg() &&
3447	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
3448	RISCVValidateMCOperandForUncompress(MCOp: MCOperand::createImm(Val: `0`), STI, PredicateIndex: `1`)) {
3449	// addi $rd, $rs1, $imm12
3450	OutInst.setOpcode(RISCV::ADDI);
3451	// Operand: rd
3452	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3453	// Operand: rs1
3454	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3455	// Operand: imm12
3456	OutInst.addOperand(Op: MCOperand::createImm(Val: `0`));
3457	OutInst.setLoc(MI.getLoc());
3458	return true;
3459	} // if
3460	break;
3461	} // case C_MV
3462	case RISCV::C_NOP: {
3463	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3464	RISCVValidateMCOperandForUncompress(MCOp: MCOperand::createImm(Val: `0`), STI, PredicateIndex: `1`)) {
3465	// addi $rd, $rs1, $imm12
3466	OutInst.setOpcode(RISCV::ADDI);
3467	// Operand: rd
3468	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X0));
3469	// Operand: rs1
3470	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X0));
3471	// Operand: imm12
3472	OutInst.addOperand(Op: MCOperand::createImm(Val: `0`));
3473	OutInst.setLoc(MI.getLoc());
3474	return true;
3475	} // if
3476	break;
3477	} // case C_NOP
3478	case RISCV::C_NOT: {
3479	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
3480	MI.getOperand(i: `0`).isReg() &&
3481	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3482	MI.getOperand(i: `0`).isReg() &&
3483	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3484	RISCVValidateMCOperandForUncompress(MCOp: MCOperand::createImm(Val: -`1`), STI, PredicateIndex: `1`)) {
3485	// xori $rd, $rs1, $imm12
3486	OutInst.setOpcode(RISCV::XORI);
3487	// Operand: rd
3488	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3489	// Operand: rs1
3490	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3491	// Operand: imm12
3492	OutInst.addOperand(Op: MCOperand::createImm(Val: -`1`));
3493	OutInst.setLoc(MI.getLoc());
3494	return true;
3495	} // if
3496	break;
3497	} // case C_NOT
3498	case RISCV::C_OR: {
3499	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3500	MI.getOperand(i: `0`).isReg() &&
3501	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3502	MI.getOperand(i: `0`).isReg() &&
3503	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3504	MI.getOperand(i: `2`).isReg() &&
3505	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `2`).getReg())) {
3506	// or $rd, $rs1, $rs2
3507	OutInst.setOpcode(RISCV::OR);
3508	// Operand: rd
3509	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3510	// Operand: rs1
3511	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3512	// Operand: rs2
3513	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3514	OutInst.setLoc(MI.getLoc());
3515	return true;
3516	} // if
3517	break;
3518	} // case C_OR
3519	case RISCV::C_SB: {
3520	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
3521	MI.getOperand(i: `0`).isReg() &&
3522	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3523	MI.getOperand(i: `1`).isReg() &&
3524	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
3525	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `1`)) {
3526	// sb $rs2, ${imm12}(${rs1})
3527	OutInst.setOpcode(RISCV::SB);
3528	// Operand: rs2
3529	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3530	// Operand: rs1
3531	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3532	// Operand: imm12
3533	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3534	OutInst.setLoc(MI.getLoc());
3535	return true;
3536	} // if
3537	break;
3538	} // case C_SB
3539	case RISCV::C_SD: {
3540	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
3541	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3542	MI.getOperand(i: `0`).isReg() &&
3543	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3544	MI.getOperand(i: `1`).isReg() &&
3545	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
3546	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `1`)) {
3547	// sd $rs2, ${imm12}(${rs1})
3548	OutInst.setOpcode(RISCV::SD);
3549	// Operand: rs2
3550	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3551	// Operand: rs1
3552	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3553	// Operand: imm12
3554	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3555	OutInst.setLoc(MI.getLoc());
3556	return true;
3557	} // if
3558	break;
3559	} // case C_SD
3560	case RISCV::C_SDSP: {
3561	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
3562	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3563	MI.getOperand(i: `0`).isReg() &&
3564	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3565	MI.getOperand(i: `1`).isReg() &&
3566	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
3567	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `1`)) {
3568	// sd $rs2, ${imm12}(${rs1})
3569	OutInst.setOpcode(RISCV::SD);
3570	// Operand: rs2
3571	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3572	// Operand: rs1
3573	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3574	// Operand: imm12
3575	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3576	OutInst.setLoc(MI.getLoc());
3577	return true;
3578	} // if
3579	break;
3580	} // case C_SDSP
3581	case RISCV::C_SDSP_RV32: {
3582	if (STI.getFeatureBits()[RISCV::FeatureStdExtZclsd] &&
3583	STI.getFeatureBits()[RISCV::FeatureStdExtZilsd] &&
3584	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
3585	MI.getOperand(i: `0`).isReg() &&
3586	RISCVMCRegisterClasses[RISCV::GPRPairRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3587	MI.getOperand(i: `1`).isReg() &&
3588	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
3589	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `1`)) {
3590	// sd $rs2, ${imm12}(${rs1})
3591	OutInst.setOpcode(RISCV::SD_RV32);
3592	// Operand: rs2
3593	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3594	// Operand: rs1
3595	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3596	// Operand: imm12
3597	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3598	OutInst.setLoc(MI.getLoc());
3599	return true;
3600	} // if
3601	break;
3602	} // case C_SDSP_RV32
3603	case RISCV::C_SD_RV32: {
3604	if (STI.getFeatureBits()[RISCV::FeatureStdExtZclsd] &&
3605	STI.getFeatureBits()[RISCV::FeatureStdExtZilsd] &&
3606	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
3607	MI.getOperand(i: `0`).isReg() &&
3608	RISCVMCRegisterClasses[RISCV::GPRPairRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3609	MI.getOperand(i: `1`).isReg() &&
3610	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
3611	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `1`)) {
3612	// sd $rs2, ${imm12}(${rs1})
3613	OutInst.setOpcode(RISCV::SD_RV32);
3614	// Operand: rs2
3615	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3616	// Operand: rs1
3617	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3618	// Operand: imm12
3619	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3620	OutInst.setLoc(MI.getLoc());
3621	return true;
3622	} // if
3623	break;
3624	} // case C_SD_RV32
3625	case RISCV::C_SEXT_B: {
3626	if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] &&
3627	STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
3628	(STI.getFeatureBits()[RISCV::FeatureStdExtP] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZbb]) &&
3629	MI.getOperand(i: `0`).isReg() &&
3630	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3631	MI.getOperand(i: `0`).isReg() &&
3632	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg())) {
3633	// sext.b $rd, $rs1
3634	OutInst.setOpcode(RISCV::SEXT_B);
3635	// Operand: rd
3636	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3637	// Operand: rs1
3638	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3639	OutInst.setLoc(MI.getLoc());
3640	return true;
3641	} // if
3642	break;
3643	} // case C_SEXT_B
3644	case RISCV::C_SEXT_H: {
3645	if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] &&
3646	STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
3647	(STI.getFeatureBits()[RISCV::FeatureStdExtP] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZbb]) &&
3648	MI.getOperand(i: `0`).isReg() &&
3649	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3650	MI.getOperand(i: `0`).isReg() &&
3651	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg())) {
3652	// sext.h $rd, $rs1
3653	OutInst.setOpcode(RISCV::SEXT_H);
3654	// Operand: rd
3655	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3656	// Operand: rs1
3657	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3658	OutInst.setLoc(MI.getLoc());
3659	return true;
3660	} // if
3661	break;
3662	} // case C_SEXT_H
3663	case RISCV::C_SH: {
3664	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
3665	MI.getOperand(i: `0`).isReg() &&
3666	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3667	MI.getOperand(i: `1`).isReg() &&
3668	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
3669	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `1`)) {
3670	// sh $rs2, ${imm12}(${rs1})
3671	OutInst.setOpcode(RISCV::SH);
3672	// Operand: rs2
3673	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3674	// Operand: rs1
3675	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3676	// Operand: imm12
3677	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3678	OutInst.setLoc(MI.getLoc());
3679	return true;
3680	} // if
3681	break;
3682	} // case C_SH
3683	case RISCV::C_SLLI: {
3684	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3685	MI.getOperand(i: `0`).isReg() &&
3686	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3687	MI.getOperand(i: `0`).isReg() &&
3688	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3689	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `6`)) {
3690	// slli $rd, $rs1, $shamt
3691	OutInst.setOpcode(RISCV::SLLI);
3692	// Operand: rd
3693	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3694	// Operand: rs1
3695	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3696	// Operand: shamt
3697	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3698	OutInst.setLoc(MI.getLoc());
3699	return true;
3700	} // if
3701	break;
3702	} // case C_SLLI
3703	case RISCV::C_SRAI: {
3704	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3705	MI.getOperand(i: `0`).isReg() &&
3706	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3707	MI.getOperand(i: `0`).isReg() &&
3708	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3709	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `6`)) {
3710	// srai $rd, $rs1, $shamt
3711	OutInst.setOpcode(RISCV::SRAI);
3712	// Operand: rd
3713	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3714	// Operand: rs1
3715	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3716	// Operand: shamt
3717	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3718	OutInst.setLoc(MI.getLoc());
3719	return true;
3720	} // if
3721	break;
3722	} // case C_SRAI
3723	case RISCV::C_SRLI: {
3724	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3725	MI.getOperand(i: `0`).isReg() &&
3726	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3727	MI.getOperand(i: `0`).isReg() &&
3728	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3729	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `6`)) {
3730	// srli $rd, $rs1, $shamt
3731	OutInst.setOpcode(RISCV::SRLI);
3732	// Operand: rd
3733	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3734	// Operand: rs1
3735	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3736	// Operand: shamt
3737	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3738	OutInst.setLoc(MI.getLoc());
3739	return true;
3740	} // if
3741	break;
3742	} // case C_SRLI
3743	case RISCV::C_SSPOPCHK: {
3744	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcmop] &&
3745	STI.getFeatureBits()[RISCV::FeatureStdExtZicfiss] &&
3746	(MI.getOperand(i: `0`).isReg()) &&
3747	(MI.getOperand(i: `0`).getReg() == RISCV::X5)) {
3748	// sspopchk $rs1
3749	OutInst.setOpcode(RISCV::SSPOPCHK);
3750	// Operand: rs1
3751	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X5));
3752	OutInst.setLoc(MI.getLoc());
3753	return true;
3754	} // if
3755	break;
3756	} // case C_SSPOPCHK
3757	case RISCV::C_SSPUSH: {
3758	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcmop] &&
3759	STI.getFeatureBits()[RISCV::FeatureStdExtZicfiss] &&
3760	(MI.getOperand(i: `0`).isReg()) &&
3761	(MI.getOperand(i: `0`).getReg() == RISCV::X1)) {
3762	// sspush $rs2
3763	OutInst.setOpcode(RISCV::SSPUSH);
3764	// Operand: rs2
3765	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X1));
3766	OutInst.setLoc(MI.getLoc());
3767	return true;
3768	} // if
3769	break;
3770	} // case C_SSPUSH
3771	case RISCV::C_SUB: {
3772	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3773	MI.getOperand(i: `0`).isReg() &&
3774	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3775	MI.getOperand(i: `0`).isReg() &&
3776	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3777	MI.getOperand(i: `2`).isReg() &&
3778	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `2`).getReg())) {
3779	// sub $rd, $rs1, $rs2
3780	OutInst.setOpcode(RISCV::SUB);
3781	// Operand: rd
3782	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3783	// Operand: rs1
3784	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3785	// Operand: rs2
3786	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3787	OutInst.setLoc(MI.getLoc());
3788	return true;
3789	} // if
3790	break;
3791	} // case C_SUB
3792	case RISCV::C_SUBW: {
3793	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
3794	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3795	MI.getOperand(i: `0`).isReg() &&
3796	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3797	MI.getOperand(i: `0`).isReg() &&
3798	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3799	MI.getOperand(i: `2`).isReg() &&
3800	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `2`).getReg())) {
3801	// subw $rd, $rs1, $rs2
3802	OutInst.setOpcode(RISCV::SUBW);
3803	// Operand: rd
3804	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3805	// Operand: rs1
3806	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3807	// Operand: rs2
3808	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3809	OutInst.setLoc(MI.getLoc());
3810	return true;
3811	} // if
3812	break;
3813	} // case C_SUBW
3814	case RISCV::C_SW: {
3815	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3816	MI.getOperand(i: `0`).isReg() &&
3817	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3818	MI.getOperand(i: `1`).isReg() &&
3819	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
3820	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `1`)) {
3821	// sw $rs2, ${imm12}(${rs1})
3822	OutInst.setOpcode(RISCV::SW);
3823	// Operand: rs2
3824	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3825	// Operand: rs1
3826	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3827	// Operand: imm12
3828	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3829	OutInst.setLoc(MI.getLoc());
3830	return true;
3831	} // if
3832	break;
3833	} // case C_SW
3834	case RISCV::C_SWSP: {
3835	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3836	MI.getOperand(i: `0`).isReg() &&
3837	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3838	MI.getOperand(i: `1`).isReg() &&
3839	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
3840	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `1`)) {
3841	// sw $rs2, ${imm12}(${rs1})
3842	OutInst.setOpcode(RISCV::SW);
3843	// Operand: rs2
3844	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3845	// Operand: rs1
3846	OutInst.addOperand(Op: MI.getOperand(i: `1`));
3847	// Operand: imm12
3848	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3849	OutInst.setLoc(MI.getLoc());
3850	return true;
3851	} // if
3852	break;
3853	} // case C_SWSP
3854	case RISCV::C_UNIMP: {
3855	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca])) {
3856	// unimp
3857	OutInst.setOpcode(RISCV::UNIMP);
3858	OutInst.setLoc(MI.getLoc());
3859	return true;
3860	} // if
3861	break;
3862	} // case C_UNIMP
3863	case RISCV::C_XOR: {
3864	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3865	MI.getOperand(i: `0`).isReg() &&
3866	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3867	MI.getOperand(i: `0`).isReg() &&
3868	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3869	MI.getOperand(i: `2`).isReg() &&
3870	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `2`).getReg())) {
3871	// xor $rd, $rs1, $rs2
3872	OutInst.setOpcode(RISCV::XOR);
3873	// Operand: rd
3874	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3875	// Operand: rs1
3876	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3877	// Operand: rs2
3878	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3879	OutInst.setLoc(MI.getLoc());
3880	return true;
3881	} // if
3882	break;
3883	} // case C_XOR
3884	case RISCV::C_ZEXT_B: {
3885	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
3886	MI.getOperand(i: `0`).isReg() &&
3887	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3888	MI.getOperand(i: `0`).isReg() &&
3889	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3890	RISCVValidateMCOperandForUncompress(MCOp: MCOperand::createImm(Val: `255`), STI, PredicateIndex: `1`)) {
3891	// andi $rd, $rs1, $imm12
3892	OutInst.setOpcode(RISCV::ANDI);
3893	// Operand: rd
3894	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3895	// Operand: rs1
3896	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3897	// Operand: imm12
3898	OutInst.addOperand(Op: MCOperand::createImm(Val: `255`));
3899	OutInst.setLoc(MI.getLoc());
3900	return true;
3901	} // if
3902	break;
3903	} // case C_ZEXT_B
3904	case RISCV::C_ZEXT_H: {
3905	if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] &&
3906	STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
3907	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
3908	MI.getOperand(i: `0`).isReg() &&
3909	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3910	MI.getOperand(i: `0`).isReg() &&
3911	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg())) {
3912	// zext.h $rd, $rs1
3913	OutInst.setOpcode(RISCV::ZEXT_H_RV32);
3914	// Operand: rd
3915	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3916	// Operand: rs1
3917	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3918	OutInst.setLoc(MI.getLoc());
3919	return true;
3920	} // if
3921	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
3922	STI.getFeatureBits()[RISCV::FeatureStdExtZbb] &&
3923	STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
3924	MI.getOperand(i: `0`).isReg() &&
3925	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3926	MI.getOperand(i: `0`).isReg() &&
3927	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg())) {
3928	// zext.h $rd, $rs1
3929	OutInst.setOpcode(RISCV::ZEXT_H_RV64);
3930	// Operand: rd
3931	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3932	// Operand: rs1
3933	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3934	OutInst.setLoc(MI.getLoc());
3935	return true;
3936	} // if
3937	break;
3938	} // case C_ZEXT_H
3939	case RISCV::C_ZEXT_W: {
3940	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
3941	STI.getFeatureBits()[RISCV::FeatureStdExtZba] &&
3942	STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
3943	MI.getOperand(i: `0`).isReg() &&
3944	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3945	MI.getOperand(i: `0`).isReg() &&
3946	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg())) {
3947	// add.uw $rd, $rs1, $rs2
3948	OutInst.setOpcode(RISCV::ADD_UW);
3949	// Operand: rd
3950	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3951	// Operand: rs1
3952	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3953	// Operand: rs2
3954	OutInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X0));
3955	OutInst.setLoc(MI.getLoc());
3956	return true;
3957	} // if
3958	break;
3959	} // case C_ZEXT_W
3960	case RISCV::QC_C_BEXTI: {
3961	if (STI.getFeatureBits()[RISCV::FeatureStdExtZbs] &&
3962	STI.getFeatureBits()[RISCV::FeatureVendorXqcibm] &&
3963	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
3964	MI.getOperand(i: `0`).isReg() &&
3965	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3966	MI.getOperand(i: `0`).isReg() &&
3967	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3968	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `6`)) {
3969	// bexti $rd, $rs1, $shamt
3970	OutInst.setOpcode(RISCV::BEXTI);
3971	// Operand: rd
3972	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3973	// Operand: rs1
3974	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3975	// Operand: shamt
3976	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3977	OutInst.setLoc(MI.getLoc());
3978	return true;
3979	} // if
3980	break;
3981	} // case QC_C_BEXTI
3982	case RISCV::QC_C_BSETI: {
3983	if (STI.getFeatureBits()[RISCV::FeatureStdExtZbs] &&
3984	STI.getFeatureBits()[RISCV::FeatureVendorXqcibm] &&
3985	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
3986	MI.getOperand(i: `0`).isReg() &&
3987	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3988	MI.getOperand(i: `0`).isReg() &&
3989	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
3990	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `6`)) {
3991	// bseti $rd, $rs1, $shamt
3992	OutInst.setOpcode(RISCV::BSETI);
3993	// Operand: rd
3994	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3995	// Operand: rs1
3996	OutInst.addOperand(Op: MI.getOperand(i: `0`));
3997	// Operand: shamt
3998	OutInst.addOperand(Op: MI.getOperand(i: `2`));
3999	OutInst.setLoc(MI.getLoc());
4000	return true;
4001	} // if
4002	break;
4003	} // case QC_C_BSETI
4004	case RISCV::QC_C_EXTU: {
4005	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcibm] &&
4006	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
4007	MI.getOperand(i: `0`).isReg() &&
4008	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4009	MI.getOperand(i: `0`).isReg() &&
4010	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4011	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `7`) &&
4012	RISCVValidateMCOperandForUncompress(MCOp: MCOperand::createImm(Val: `0`), STI, PredicateIndex: `8`)) {
4013	// qc.extu $rd, $rs1, $width, $shamt
4014	OutInst.setOpcode(RISCV::QC_EXTU);
4015	// Operand: rd
4016	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4017	// Operand: rs1
4018	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4019	// Operand: width
4020	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4021	// Operand: shamt
4022	OutInst.addOperand(Op: MCOperand::createImm(Val: `0`));
4023	OutInst.setLoc(MI.getLoc());
4024	return true;
4025	} // if
4026	break;
4027	} // case QC_C_EXTU
4028	case RISCV::QC_C_MULIADD: {
4029	if (STI.getFeatureBits()[RISCV::FeatureVendorXqciac] &&
4030	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
4031	MI.getOperand(i: `0`).isReg() &&
4032	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4033	MI.getOperand(i: `2`).isReg() &&
4034	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `2`).getReg()) &&
4035	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `3`), STI, PredicateIndex: `1`)) {
4036	// qc.muliadd $rd, $rs1, $imm12
4037	OutInst.setOpcode(RISCV::QC_MULIADD);
4038	// Operand: rd_wb
4039	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4040	// Operand: rd
4041	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4042	// Operand: rs1
4043	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4044	// Operand: imm12
4045	OutInst.addOperand(Op: MI.getOperand(i: `3`));
4046	OutInst.setLoc(MI.getLoc());
4047	return true;
4048	} // if
4049	break;
4050	} // case QC_C_MULIADD
4051	case RISCV::QC_C_MVEQZ: {
4052	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcicm] &&
4053	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
4054	MI.getOperand(i: `0`).isReg() &&
4055	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4056	MI.getOperand(i: `0`).isReg() &&
4057	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4058	RISCVValidateMCOperandForUncompress(MCOp: MCOperand::createImm(Val: `0`), STI, PredicateIndex: `9`) &&
4059	MI.getOperand(i: `2`).isReg() &&
4060	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(Reg: MI.getOperand(i: `2`).getReg())) {
4061	// qc.mveqi $rd, $rs1, $imm, $rs3
4062	OutInst.setOpcode(RISCV::QC_MVEQI);
4063	// Operand: rd_wb
4064	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4065	// Operand: rd
4066	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4067	// Operand: rs1
4068	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4069	// Operand: imm
4070	OutInst.addOperand(Op: MCOperand::createImm(Val: `0`));
4071	// Operand: rs3
4072	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4073	OutInst.setLoc(MI.getLoc());
4074	return true;
4075	} // if
4076	break;
4077	} // case QC_C_MVEQZ
4078	case RISCV::QC_C_SYNC: {
4079	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcisync] &&
4080	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
4081	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `0`), STI, PredicateIndex: `8`)) {
4082	// qc.sync $imm5
4083	OutInst.setOpcode(RISCV::QC_SYNC);
4084	// Operand: imm5
4085	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4086	OutInst.setLoc(MI.getLoc());
4087	return true;
4088	} // if
4089	break;
4090	} // case QC_C_SYNC
4091	case RISCV::QC_C_SYNCR: {
4092	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcisync] &&
4093	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
4094	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `0`), STI, PredicateIndex: `8`)) {
4095	// qc.syncr $imm5
4096	OutInst.setOpcode(RISCV::QC_SYNCR);
4097	// Operand: imm5
4098	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4099	OutInst.setLoc(MI.getLoc());
4100	return true;
4101	} // if
4102	break;
4103	} // case QC_C_SYNCR
4104	case RISCV::QC_C_SYNCWF: {
4105	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcisync] &&
4106	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
4107	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `0`), STI, PredicateIndex: `8`)) {
4108	// qc.syncwf $imm5
4109	OutInst.setOpcode(RISCV::QC_SYNCWF);
4110	// Operand: imm5
4111	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4112	OutInst.setLoc(MI.getLoc());
4113	return true;
4114	} // if
4115	break;
4116	} // case QC_C_SYNCWF
4117	case RISCV::QC_C_SYNCWL: {
4118	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcisync] &&
4119	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
4120	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `0`), STI, PredicateIndex: `8`)) {
4121	// qc.syncwl $imm5
4122	OutInst.setOpcode(RISCV::QC_SYNCWL);
4123	// Operand: imm5
4124	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4125	OutInst.setLoc(MI.getLoc());
4126	return true;
4127	} // if
4128	break;
4129	} // case QC_C_SYNCWL
4130	case RISCV::QK_C_LBU: {
4131	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
4132	MI.getOperand(i: `0`).isReg() &&
4133	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4134	MI.getOperand(i: `1`).isReg() &&
4135	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
4136	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `1`)) {
4137	// lbu $rd, ${imm12}(${rs1})
4138	OutInst.setOpcode(RISCV::LBU);
4139	// Operand: rd
4140	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4141	// Operand: rs1
4142	OutInst.addOperand(Op: MI.getOperand(i: `1`));
4143	// Operand: imm12
4144	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4145	OutInst.setLoc(MI.getLoc());
4146	return true;
4147	} // if
4148	break;
4149	} // case QK_C_LBU
4150	case RISCV::QK_C_LBUSP: {
4151	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
4152	MI.getOperand(i: `0`).isReg() &&
4153	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4154	MI.getOperand(i: `1`).isReg() &&
4155	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
4156	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `1`)) {
4157	// lbu $rd, ${imm12}(${rs1})
4158	OutInst.setOpcode(RISCV::LBU);
4159	// Operand: rd
4160	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4161	// Operand: rs1
4162	OutInst.addOperand(Op: MI.getOperand(i: `1`));
4163	// Operand: imm12
4164	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4165	OutInst.setLoc(MI.getLoc());
4166	return true;
4167	} // if
4168	break;
4169	} // case QK_C_LBUSP
4170	case RISCV::QK_C_LHU: {
4171	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
4172	MI.getOperand(i: `0`).isReg() &&
4173	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4174	MI.getOperand(i: `1`).isReg() &&
4175	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
4176	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `1`)) {
4177	// lhu $rd, ${imm12}(${rs1})
4178	OutInst.setOpcode(RISCV::LHU);
4179	// Operand: rd
4180	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4181	// Operand: rs1
4182	OutInst.addOperand(Op: MI.getOperand(i: `1`));
4183	// Operand: imm12
4184	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4185	OutInst.setLoc(MI.getLoc());
4186	return true;
4187	} // if
4188	break;
4189	} // case QK_C_LHU
4190	case RISCV::QK_C_LHUSP: {
4191	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
4192	MI.getOperand(i: `0`).isReg() &&
4193	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4194	MI.getOperand(i: `1`).isReg() &&
4195	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
4196	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `1`)) {
4197	// lhu $rd, ${imm12}(${rs1})
4198	OutInst.setOpcode(RISCV::LHU);
4199	// Operand: rd
4200	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4201	// Operand: rs1
4202	OutInst.addOperand(Op: MI.getOperand(i: `1`));
4203	// Operand: imm12
4204	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4205	OutInst.setLoc(MI.getLoc());
4206	return true;
4207	} // if
4208	break;
4209	} // case QK_C_LHUSP
4210	case RISCV::QK_C_SB: {
4211	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
4212	MI.getOperand(i: `0`).isReg() &&
4213	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4214	MI.getOperand(i: `1`).isReg() &&
4215	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
4216	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `1`)) {
4217	// sb $rs2, ${imm12}(${rs1})
4218	OutInst.setOpcode(RISCV::SB);
4219	// Operand: rs2
4220	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4221	// Operand: rs1
4222	OutInst.addOperand(Op: MI.getOperand(i: `1`));
4223	// Operand: imm12
4224	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4225	OutInst.setLoc(MI.getLoc());
4226	return true;
4227	} // if
4228	break;
4229	} // case QK_C_SB
4230	case RISCV::QK_C_SBSP: {
4231	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
4232	MI.getOperand(i: `0`).isReg() &&
4233	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4234	MI.getOperand(i: `1`).isReg() &&
4235	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
4236	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `1`)) {
4237	// sb $rs2, ${imm12}(${rs1})
4238	OutInst.setOpcode(RISCV::SB);
4239	// Operand: rs2
4240	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4241	// Operand: rs1
4242	OutInst.addOperand(Op: MI.getOperand(i: `1`));
4243	// Operand: imm12
4244	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4245	OutInst.setLoc(MI.getLoc());
4246	return true;
4247	} // if
4248	break;
4249	} // case QK_C_SBSP
4250	case RISCV::QK_C_SH: {
4251	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
4252	MI.getOperand(i: `0`).isReg() &&
4253	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4254	MI.getOperand(i: `1`).isReg() &&
4255	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
4256	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `1`)) {
4257	// sh $rs2, ${imm12}(${rs1})
4258	OutInst.setOpcode(RISCV::SH);
4259	// Operand: rs2
4260	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4261	// Operand: rs1
4262	OutInst.addOperand(Op: MI.getOperand(i: `1`));
4263	// Operand: imm12
4264	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4265	OutInst.setLoc(MI.getLoc());
4266	return true;
4267	} // if
4268	break;
4269	} // case QK_C_SH
4270	case RISCV::QK_C_SHSP: {
4271	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
4272	MI.getOperand(i: `0`).isReg() &&
4273	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `0`).getReg()) &&
4274	MI.getOperand(i: `1`).isReg() &&
4275	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg: MI.getOperand(i: `1`).getReg()) &&
4276	RISCVValidateMCOperandForUncompress(MCOp: MI.getOperand(i: `2`), STI, PredicateIndex: `1`)) {
4277	// sh $rs2, ${imm12}(${rs1})
4278	OutInst.setOpcode(RISCV::SH);
4279	// Operand: rs2
4280	OutInst.addOperand(Op: MI.getOperand(i: `0`));
4281	// Operand: rs1
4282	OutInst.addOperand(Op: MI.getOperand(i: `1`));
4283	// Operand: imm12
4284	OutInst.addOperand(Op: MI.getOperand(i: `2`));
4285	OutInst.setLoc(MI.getLoc());
4286	return true;
4287	} // if
4288
4289	} // case QK_C_SHSP
4290	} // switch
4291	return false;
4292	}
4293
4294	#endif //GEN_UNCOMPRESS_INSTR
4295
4296
4297	#ifdef GEN_CHECK_COMPRESS_INSTR
4298	#undef GEN_CHECK_COMPRESS_INSTR
4299
4300	static bool RISCVValidateMachineOperand(const MachineOperand &MO,
4301	const RISCVSubtarget *Subtarget,
4302	unsigned PredicateIndex) {
4303	int64_t Imm = MO.getImm();
4304	switch (PredicateIndex) {
4305	default:
4306	llvm_unreachable("Unknown ImmLeaf Predicate kind");
4307	break;
4308	case `1`: {
4309	// simm6nonzero
4310	return (Imm != `0`) && isInt<`6`>(Imm);
4311	}
4312	case `2`: {
4313	// simm10_lsb0000nonzero
4314	return (Imm != `0`) && isShiftedInt<`6`, `4`>(Imm);
4315	}
4316	case `3`: {
4317	// uimm10_lsb00nonzero
4318	return isShiftedUInt<`8`, `2`>(Imm) && (Imm != `0`);
4319	}
4320	case `4`: {
4321	// simm6
4322	return isInt<`6`>(Imm);
4323	}
4324	case `5`: {
4325	// bare_simm9_lsb0
4326	return isShiftedInt<`8`, `1`>(Imm);
4327	}
4328	case `6`: {
4329	// uimmlog2xlennonzero
4330	if (Subtarget->is64Bit())
4331	return isUInt<`6`>(Imm) && (Imm != `0`);
4332	return isUInt<`5`>(Imm) && (Imm != `0`);
4333	}
4334	case `7`: {
4335	// uimm8_lsb000
4336	return isShiftedUInt<`5`, `3`>(Imm);
4337	}
4338	case `8`: {
4339	// uimm9_lsb000
4340	return isShiftedUInt<`6`, `3`>(Imm);
4341	}
4342	case `9`: {
4343	// uimm7_lsb00
4344	return isShiftedUInt<`5`, `2`>(Imm);
4345	}
4346	case `10`: {
4347	// uimm8_lsb00
4348	return isShiftedUInt<`6`, `2`>(Imm);
4349	}
4350	case `11`: {
4351	// bare_simm12_lsb0
4352	return isShiftedInt<`11`, `1`>(Imm);
4353	}
4354	case `12`: {
4355	// uimm2
4356	return isUInt<`2`>(Imm);
4357	}
4358	case `13`: {
4359	// uimm5
4360	return isUInt<`5`>(Imm);
4361	}
4362	case `14`: {
4363	// uimm4
4364	return isUInt<`4`>(Imm);
4365	}
4366	case `15`: {
4367	// uimm2_lsb0
4368	return isShiftedUInt<`1`, `1`>(Imm);
4369	}
4370	case `16`: {
4371	// uimm6_lsb0
4372	return isShiftedUInt<`5`, `1`>(Imm);
4373	}
4374	case `17`: {
4375	// uimm5_lsb0
4376	return isShiftedUInt<`4`, `1`>(Imm);
4377	}
4378	case `18`: {
4379	// c_lui_imm
4380	return (Imm != `0`) &&
4381	(isUInt<`5`>(Imm) \|\|
4382	(Imm >= `0xfffe0` && Imm <= `0xfffff`));
4383	}
4384	case `19`: {
4385	// uimm5ge6_plus1
4386	return (Imm >= `6`) && (isUInt<`5`>(Imm) \|\| (Imm == `32`));
4387	}
4388	case `20`: {
4389	// simm5nonzero
4390	return (Imm != `0`) && isInt<`5`>(Imm);
4391	}
4392	case `21`: {
4393	// bare_simm13_lsb0
4394	return isShiftedInt<`12`, `1`>(Imm);
4395	}
4396	case `22`: {
4397	// uimm5nonzero
4398	return (Imm != `0`) && isUInt<`5`>(Imm);
4399	}
4400	case `23`: {
4401	// simm21_lsb0_jal
4402	return isShiftedInt<`20`, `1`>(Imm);
4403	}
4404	case `24`: {
4405	// simm12
4406	return isInt<`12`>(Imm);
4407	}
4408	case `25`: {
4409	// simm20_li
4410	return isInt<`20`>(Imm);
4411	}
4412	case `26`: {
4413	// uimm5slist
4414	return ((Imm == `0`) \|\|
4415	(Imm == `1`) \|\|
4416	(Imm == `2`) \|\|
4417	(Imm == `4`) \|\|
4418	(Imm == `8`) \|\|
4419	(Imm == `16`) \|\|
4420	(Imm == `15`) \|\|
4421	(Imm == `31`));
4422	}
4423	}
4424	}
4425
4426	static bool isCompressibleInst(const MachineInstr &MI,
4427	const RISCVSubtarget &STI) {
4428	switch (MI.getOpcode()) {
4429	default: return false;
4430	case RISCV::ADD: {
4431	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
4432	(MI.getOperand(`1`).isReg()) && (MI.getOperand(`0`).isReg()) &&
4433	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
4434	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
4435	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`1`).getReg()) &&
4436	MI.getOperand(`2`).isReg() && MI.getOperand(`2`).getReg().isPhysical() &&
4437	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`2`).getReg())) {
4438	// c.add $rs1, $rs2
4439	// Operand: rd
4440	// Operand: rs1
4441	// Operand: rs2
4442	return true;
4443	} // if
4444	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
4445	(MI.getOperand(`2`).isReg()) && (MI.getOperand(`0`).isReg()) &&
4446	(MI.getOperand(`2`).getReg() == MI.getOperand(`0`).getReg()) &&
4447	MI.getOperand(`2`).isReg() && MI.getOperand(`2`).getReg().isPhysical() &&
4448	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`2`).getReg()) &&
4449	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
4450	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`1`).getReg())) {
4451	// c.add $rs1, $rs2
4452	// Operand: rd
4453	// Operand: rs1
4454	// Operand: rs2
4455	return true;
4456	} // if
4457	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
4458	(MI.getOperand(`1`).isReg()) &&
4459	(MI.getOperand(`1`).getReg() == RISCV::X0) &&
4460	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
4461	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`0`).getReg()) &&
4462	MI.getOperand(`2`).isReg() && MI.getOperand(`2`).getReg().isPhysical() &&
4463	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`2`).getReg())) {
4464	// c.mv $rs1, $rs2
4465	// Operand: rs1
4466	// Operand: rs2
4467	return true;
4468	} // if
4469	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
4470	(MI.getOperand(`2`).isReg()) &&
4471	(MI.getOperand(`2`).getReg() == RISCV::X0) &&
4472	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
4473	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`0`).getReg()) &&
4474	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
4475	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`1`).getReg())) {
4476	// c.mv $rs1, $rs2
4477	// Operand: rs1
4478	// Operand: rs2
4479	return true;
4480	} // if
4481	break;
4482	} // case ADD
4483	case RISCV::ADDI: {
4484	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
4485	(MI.getOperand(`1`).isReg()) && (MI.getOperand(`0`).isReg()) &&
4486	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
4487	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
4488	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`1`).getReg()) &&
4489	MI.getOperand(`2`).isImm() &&
4490	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `1`)) {
4491	// c.addi $rd, $imm
4492	// Operand: rd_wb
4493	// Operand: rd
4494	// Operand: imm
4495	return true;
4496	} // if
4497	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
4498	(MI.getOperand(`0`).isReg()) &&
4499	(MI.getOperand(`0`).getReg() == RISCV::X2) &&
4500	(MI.getOperand(`1`).isReg()) &&
4501	(MI.getOperand(`1`).getReg() == RISCV::X2) &&
4502	MI.getOperand(`2`).isImm() &&
4503	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `2`)) {
4504	// c.addi16sp $rd, $imm
4505	// Operand: rd_wb
4506	// Operand: rd
4507	// Operand: imm
4508	return true;
4509	} // if
4510	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
4511	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
4512	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`0`).getReg()) &&
4513	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
4514	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(`1`).getReg()) &&
4515	MI.getOperand(`2`).isImm() &&
4516	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `3`)) {
4517	// c.addi4spn $rd, $rs1, $imm
4518	// Operand: rd
4519	// Operand: rs1
4520	// Operand: imm
4521	return true;
4522	} // if
4523	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
4524	(MI.getOperand(`1`).isReg()) &&
4525	(MI.getOperand(`1`).getReg() == RISCV::X0) &&
4526	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
4527	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`0`).getReg()) &&
4528	MI.getOperand(`2`).isImm() &&
4529	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `4`)) {
4530	// c.li $rd, $imm
4531	// Operand: rd
4532	// Operand: imm
4533	return true;
4534	} // if
4535	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
4536	(MI.getOperand(`2`).isImm()) &&
4537	(MI.getOperand(`2`).getImm() == `0`) &&
4538	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
4539	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`0`).getReg()) &&
4540	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
4541	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`1`).getReg())) {
4542	// c.mv $rs1, $rs2
4543	// Operand: rs1
4544	// Operand: rs2
4545	return true;
4546	} // if
4547	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
4548	(MI.getOperand(`0`).isReg()) &&
4549	(MI.getOperand(`0`).getReg() == RISCV::X0) &&
4550	(MI.getOperand(`1`).isReg()) &&
4551	(MI.getOperand(`1`).getReg() == RISCV::X0) &&
4552	(MI.getOperand(`2`).isImm()) &&
4553	(MI.getOperand(`2`).getImm() == `0`)) {
4554	// c.nop
4555	return true;
4556	} // if
4557	break;
4558	} // case ADDI
4559	case RISCV::ADDIW: {
4560	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
4561	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
4562	(MI.getOperand(`1`).isReg()) && (MI.getOperand(`0`).isReg()) &&
4563	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
4564	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
4565	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`1`).getReg()) &&
4566	MI.getOperand(`2`).isImm() &&
4567	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `4`)) {
4568	// c.addiw $rd, $imm
4569	// Operand: rd_wb
4570	// Operand: rd
4571	// Operand: imm
4572	return true;
4573	} // if
4574	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
4575	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
4576	(MI.getOperand(`1`).isReg()) &&
4577	(MI.getOperand(`1`).getReg() == RISCV::X0) &&
4578	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
4579	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`0`).getReg()) &&
4580	MI.getOperand(`2`).isImm() &&
4581	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `4`)) {
4582	// c.li $rd, $imm
4583	// Operand: rd
4584	// Operand: imm
4585	return true;
4586	} // if
4587	break;
4588	} // case ADDIW
4589	case RISCV::ADDW: {
4590	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
4591	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
4592	(MI.getOperand(`1`).isReg()) && (MI.getOperand(`0`).isReg()) &&
4593	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
4594	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
4595	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
4596	MI.getOperand(`2`).isReg() && MI.getOperand(`2`).getReg().isPhysical() &&
4597	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`2`).getReg())) {
4598	// c.addw $rd, $rs2
4599	// Operand: rd_wb
4600	// Operand: rd
4601	// Operand: rs2
4602	return true;
4603	} // if
4604	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
4605	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
4606	(MI.getOperand(`2`).isReg()) && (MI.getOperand(`0`).isReg()) &&
4607	(MI.getOperand(`2`).getReg() == MI.getOperand(`0`).getReg()) &&
4608	MI.getOperand(`2`).isReg() && MI.getOperand(`2`).getReg().isPhysical() &&
4609	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`2`).getReg()) &&
4610	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
4611	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg())) {
4612	// c.addw $rd, $rs2
4613	// Operand: rd_wb
4614	// Operand: rd
4615	// Operand: rs2
4616	return true;
4617	} // if
4618	break;
4619	} // case ADDW
4620	case RISCV::ADD_UW: {
4621	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
4622	STI.getFeatureBits()[RISCV::FeatureStdExtZba] &&
4623	STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
4624	(MI.getOperand(`1`).isReg()) && (MI.getOperand(`0`).isReg()) &&
4625	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
4626	(MI.getOperand(`2`).isReg()) &&
4627	(MI.getOperand(`2`).getReg() == RISCV::X0) &&
4628	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
4629	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg())) {
4630	// c.zext.w $rd
4631	// Operand: rd_wb
4632	// Operand: rd
4633	return true;
4634	} // if
4635	break;
4636	} // case ADD_UW
4637	case RISCV::AND: {
4638	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
4639	(MI.getOperand(`1`).isReg()) && (MI.getOperand(`0`).isReg()) &&
4640	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
4641	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
4642	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
4643	MI.getOperand(`2`).isReg() && MI.getOperand(`2`).getReg().isPhysical() &&
4644	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`2`).getReg())) {
4645	// c.and $rd, $rs2
4646	// Operand: rd_wb
4647	// Operand: rd
4648	// Operand: rs2
4649	return true;
4650	} // if
4651	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
4652	(MI.getOperand(`2`).isReg()) && (MI.getOperand(`0`).isReg()) &&
4653	(MI.getOperand(`2`).getReg() == MI.getOperand(`0`).getReg()) &&
4654	MI.getOperand(`2`).isReg() && MI.getOperand(`2`).getReg().isPhysical() &&
4655	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`2`).getReg()) &&
4656	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
4657	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg())) {
4658	// c.and $rd, $rs2
4659	// Operand: rd_wb
4660	// Operand: rd
4661	// Operand: rs2
4662	return true;
4663	} // if
4664	break;
4665	} // case AND
4666	case RISCV::ANDI: {
4667	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
4668	(MI.getOperand(`1`).isReg()) && (MI.getOperand(`0`).isReg()) &&
4669	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
4670	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
4671	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
4672	MI.getOperand(`2`).isImm() &&
4673	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `4`)) {
4674	// c.andi $rs1, $imm
4675	// Operand: rd
4676	// Operand: rs1
4677	// Operand: imm
4678	return true;
4679	} // if
4680	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
4681	(MI.getOperand(`1`).isReg()) && (MI.getOperand(`0`).isReg()) &&
4682	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
4683	(MI.getOperand(`2`).isImm()) &&
4684	(MI.getOperand(`2`).getImm() == `255`) &&
4685	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
4686	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg())) {
4687	// c.zext.b $rd
4688	// Operand: rd_wb
4689	// Operand: rd
4690	return true;
4691	} // if
4692	break;
4693	} // case ANDI
4694	case RISCV::BEQ: {
4695	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
4696	(MI.getOperand(`1`).isReg()) &&
4697	(MI.getOperand(`1`).getReg() == RISCV::X0) &&
4698	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
4699	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`0`).getReg()) &&
4700	MI.getOperand(`2`).isImm() &&
4701	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `5`)) {
4702	// c.beqz $rs1, $imm
4703	// Operand: rs1
4704	// Operand: imm
4705	return true;
4706	} // if
4707	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
4708	(MI.getOperand(`0`).isReg()) &&
4709	(MI.getOperand(`0`).getReg() == RISCV::X0) &&
4710	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
4711	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
4712	MI.getOperand(`2`).isImm() &&
4713	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `5`)) {
4714	// c.beqz $rs1, $imm
4715	// Operand: rs1
4716	// Operand: imm
4717	return true;
4718	} // if
4719	break;
4720	} // case BEQ
4721	case RISCV::BEXTI: {
4722	if (STI.getFeatureBits()[RISCV::FeatureStdExtZbs] &&
4723	STI.getFeatureBits()[RISCV::FeatureVendorXqcibm] &&
4724	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
4725	(MI.getOperand(`1`).isReg()) && (MI.getOperand(`0`).isReg()) &&
4726	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
4727	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
4728	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
4729	MI.getOperand(`2`).isImm() &&
4730	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `6`)) {
4731	// qc.c.bexti $rs1, $shamt
4732	// Operand: rd
4733	// Operand: rs1
4734	// Operand: shamt
4735	return true;
4736	} // if
4737	break;
4738	} // case BEXTI
4739	case RISCV::BNE: {
4740	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
4741	(MI.getOperand(`1`).isReg()) &&
4742	(MI.getOperand(`1`).getReg() == RISCV::X0) &&
4743	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
4744	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`0`).getReg()) &&
4745	MI.getOperand(`2`).isImm() &&
4746	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `5`)) {
4747	// c.bnez $rs1, $imm
4748	// Operand: rs1
4749	// Operand: imm
4750	return true;
4751	} // if
4752	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
4753	(MI.getOperand(`0`).isReg()) &&
4754	(MI.getOperand(`0`).getReg() == RISCV::X0) &&
4755	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
4756	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
4757	MI.getOperand(`2`).isImm() &&
4758	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `5`)) {
4759	// c.bnez $rs1, $imm
4760	// Operand: rs1
4761	// Operand: imm
4762	return true;
4763	} // if
4764	break;
4765	} // case BNE
4766	case RISCV::BSETI: {
4767	if (STI.getFeatureBits()[RISCV::FeatureStdExtZbs] &&
4768	STI.getFeatureBits()[RISCV::FeatureVendorXqcibm] &&
4769	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
4770	(MI.getOperand(`1`).isReg()) && (MI.getOperand(`0`).isReg()) &&
4771	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
4772	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
4773	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
4774	MI.getOperand(`2`).isImm() &&
4775	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `6`)) {
4776	// qc.c.bseti $rs1, $shamt
4777	// Operand: rd
4778	// Operand: rs1
4779	// Operand: shamt
4780	return true;
4781	} // if
4782	break;
4783	} // case BSETI
4784	case RISCV::EBREAK: {
4785	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca])) {
4786	// c.ebreak
4787	return true;
4788	} // if
4789	break;
4790	} // case EBREAK
4791	case RISCV::FLD: {
4792	if (STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
4793	(STI.getFeatureBits()[RISCV::FeatureStdExtC] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZcd]) &&
4794	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
4795	RISCVMCRegisterClasses[RISCV::FPR64CRegClassID].contains(MI.getOperand(`0`).getReg()) &&
4796	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
4797	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
4798	MI.getOperand(`2`).isImm() &&
4799	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `7`)) {
4800	// c.fld $rd, ${imm}(${rs1})
4801	// Operand: rd
4802	// Operand: rs1
4803	// Operand: imm
4804	return true;
4805	} // if
4806	if (STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
4807	(STI.getFeatureBits()[RISCV::FeatureStdExtC] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZcd]) &&
4808	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
4809	RISCVMCRegisterClasses[RISCV::FPR64RegClassID].contains(MI.getOperand(`0`).getReg()) &&
4810	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
4811	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(`1`).getReg()) &&
4812	MI.getOperand(`2`).isImm() &&
4813	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `8`)) {
4814	// c.fldsp $rd, ${imm}(${rs1})
4815	// Operand: rd
4816	// Operand: rs1
4817	// Operand: imm
4818	return true;
4819	} // if
4820	break;
4821	} // case FLD
4822	case RISCV::FLW: {
4823	if (STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
4824	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
4825	(STI.getFeatureBits()[RISCV::FeatureStdExtC] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZce] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZcf]) &&
4826	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
4827	RISCVMCRegisterClasses[RISCV::FPR32CRegClassID].contains(MI.getOperand(`0`).getReg()) &&
4828	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
4829	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
4830	MI.getOperand(`2`).isImm() &&
4831	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `9`)) {
4832	// c.flw $rd, ${imm}(${rs1})
4833	// Operand: rd
4834	// Operand: rs1
4835	// Operand: imm
4836	return true;
4837	} // if
4838	if (STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
4839	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
4840	(STI.getFeatureBits()[RISCV::FeatureStdExtC] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZce] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZcf]) &&
4841	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
4842	RISCVMCRegisterClasses[RISCV::FPR32RegClassID].contains(MI.getOperand(`0`).getReg()) &&
4843	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
4844	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(`1`).getReg()) &&
4845	MI.getOperand(`2`).isImm() &&
4846	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `10`)) {
4847	// c.flwsp $rd, ${imm}(${rs1})
4848	// Operand: rd
4849	// Operand: rs1
4850	// Operand: imm
4851	return true;
4852	} // if
4853	break;
4854	} // case FLW
4855	case RISCV::FSD: {
4856	if (STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
4857	(STI.getFeatureBits()[RISCV::FeatureStdExtC] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZcd]) &&
4858	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
4859	RISCVMCRegisterClasses[RISCV::FPR64CRegClassID].contains(MI.getOperand(`0`).getReg()) &&
4860	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
4861	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
4862	MI.getOperand(`2`).isImm() &&
4863	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `7`)) {
4864	// c.fsd $rs2, ${imm}(${rs1})
4865	// Operand: rs2
4866	// Operand: rs1
4867	// Operand: imm
4868	return true;
4869	} // if
4870	if (STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
4871	(STI.getFeatureBits()[RISCV::FeatureStdExtC] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZcd]) &&
4872	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
4873	RISCVMCRegisterClasses[RISCV::FPR64RegClassID].contains(MI.getOperand(`0`).getReg()) &&
4874	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
4875	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(`1`).getReg()) &&
4876	MI.getOperand(`2`).isImm() &&
4877	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `8`)) {
4878	// c.fsdsp $rs2, ${imm}(${rs1})
4879	// Operand: rs2
4880	// Operand: rs1
4881	// Operand: imm
4882	return true;
4883	} // if
4884	break;
4885	} // case FSD
4886	case RISCV::FSW: {
4887	if (STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
4888	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
4889	(STI.getFeatureBits()[RISCV::FeatureStdExtC] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZce] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZcf]) &&
4890	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
4891	RISCVMCRegisterClasses[RISCV::FPR32CRegClassID].contains(MI.getOperand(`0`).getReg()) &&
4892	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
4893	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
4894	MI.getOperand(`2`).isImm() &&
4895	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `9`)) {
4896	// c.fsw $rs2, ${imm}(${rs1})
4897	// Operand: rs2
4898	// Operand: rs1
4899	// Operand: imm
4900	return true;
4901	} // if
4902	if (STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
4903	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
4904	(STI.getFeatureBits()[RISCV::FeatureStdExtC] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZce] \|\| STI.getFeatureBits()[RISCV::FeatureStdExtZcf]) &&
4905	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
4906	RISCVMCRegisterClasses[RISCV::FPR32RegClassID].contains(MI.getOperand(`0`).getReg()) &&
4907	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
4908	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(`1`).getReg()) &&
4909	MI.getOperand(`2`).isImm() &&
4910	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `10`)) {
4911	// c.fswsp $rs2, ${imm}(${rs1})
4912	// Operand: rs2
4913	// Operand: rs1
4914	// Operand: imm
4915	return true;
4916	} // if
4917	break;
4918	} // case FSW
4919	case RISCV::JAL: {
4920	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
4921	(MI.getOperand(`0`).isReg()) &&
4922	(MI.getOperand(`0`).getReg() == RISCV::X0) &&
4923	MI.getOperand(`1`).isImm() &&
4924	RISCVValidateMachineOperand(MI.getOperand(`1`), &STI, `11`)) {
4925	// c.j $offset
4926	// Operand: offset
4927	return true;
4928	} // if
4929	if (!STI.getFeatureBits()[RISCV::Feature64Bit] &&
4930	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
4931	(MI.getOperand(`0`).isReg()) &&
4932	(MI.getOperand(`0`).getReg() == RISCV::X1) &&
4933	MI.getOperand(`1`).isImm() &&
4934	RISCVValidateMachineOperand(MI.getOperand(`1`), &STI, `11`)) {
4935	// c.jal $offset
4936	// Operand: offset
4937	return true;
4938	} // if
4939	break;
4940	} // case JAL
4941	case RISCV::JALR: {
4942	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
4943	(MI.getOperand(`0`).isReg()) &&
4944	(MI.getOperand(`0`).getReg() == RISCV::X1) &&
4945	(MI.getOperand(`2`).isImm()) &&
4946	(MI.getOperand(`2`).getImm() == `0`) &&
4947	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
4948	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`1`).getReg())) {
4949	// c.jalr $rs1
4950	// Operand: rs1
4951	return true;
4952	} // if
4953	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
4954	(MI.getOperand(`0`).isReg()) &&
4955	(MI.getOperand(`0`).getReg() == RISCV::X0) &&
4956	(MI.getOperand(`2`).isImm()) &&
4957	(MI.getOperand(`2`).getImm() == `0`) &&
4958	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
4959	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`1`).getReg())) {
4960	// c.jr $rs1
4961	// Operand: rs1
4962	return true;
4963	} // if
4964	break;
4965	} // case JALR
4966	case RISCV::LBU: {
4967	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
4968	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
4969	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`0`).getReg()) &&
4970	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
4971	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
4972	MI.getOperand(`2`).isImm() &&
4973	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `12`)) {
4974	// c.lbu $rd, ${imm}(${rs1})
4975	// Operand: rd
4976	// Operand: rs1
4977	// Operand: imm
4978	return true;
4979	} // if
4980	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
4981	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
4982	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`0`).getReg()) &&
4983	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
4984	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
4985	MI.getOperand(`2`).isImm() &&
4986	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `13`)) {
4987	// qk.c.lbu $rd, ${imm}(${rs1})
4988	// Operand: rd
4989	// Operand: rs1
4990	// Operand: imm
4991	return true;
4992	} // if
4993	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
4994	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
4995	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`0`).getReg()) &&
4996	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
4997	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(`1`).getReg()) &&
4998	MI.getOperand(`2`).isImm() &&
4999	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `14`)) {
5000	// qk.c.lbusp $rd_rs2, ${imm}(${rs1})
5001	// Operand: rd_rs2
5002	// Operand: rs1
5003	// Operand: imm
5004	return true;
5005	} // if
5006	break;
5007	} // case LBU
5008	case RISCV::LD: {
5009	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
5010	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
5011	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5012	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`0`).getReg()) &&
5013	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5014	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5015	MI.getOperand(`2`).isImm() &&
5016	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `7`)) {
5017	// c.ld $rd, ${imm}(${rs1})
5018	// Operand: rd
5019	// Operand: rs1
5020	// Operand: imm
5021	return true;
5022	} // if
5023	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
5024	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
5025	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5026	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`0`).getReg()) &&
5027	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5028	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5029	MI.getOperand(`2`).isImm() &&
5030	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `8`)) {
5031	// c.ldsp $rd, ${imm}(${rs1})
5032	// Operand: rd
5033	// Operand: rs1
5034	// Operand: imm
5035	return true;
5036	} // if
5037	break;
5038	} // case LD
5039	case RISCV::LD_RV32: {
5040	if (STI.getFeatureBits()[RISCV::FeatureStdExtZclsd] &&
5041	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5042	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5043	RISCVMCRegisterClasses[RISCV::GPRPairNoX0RegClassID].contains(MI.getOperand(`0`).getReg()) &&
5044	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5045	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5046	MI.getOperand(`2`).isImm() &&
5047	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `8`)) {
5048	// c.ldsp $rd, ${imm}(${rs1})
5049	// Operand: rd
5050	// Operand: rs1
5051	// Operand: imm
5052	return true;
5053	} // if
5054	if (STI.getFeatureBits()[RISCV::FeatureStdExtZclsd] &&
5055	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5056	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5057	RISCVMCRegisterClasses[RISCV::GPRPairCRegClassID].contains(MI.getOperand(`0`).getReg()) &&
5058	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5059	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5060	MI.getOperand(`2`).isImm() &&
5061	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `7`)) {
5062	// c.ld $rd, ${imm}(${rs1})
5063	// Operand: rd
5064	// Operand: rs1
5065	// Operand: imm
5066	return true;
5067	} // if
5068	break;
5069	} // case LD_RV32
5070	case RISCV::LH: {
5071	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
5072	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5073	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`0`).getReg()) &&
5074	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5075	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5076	MI.getOperand(`2`).isImm() &&
5077	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `15`)) {
5078	// c.lh $rd, ${imm}(${rs1})
5079	// Operand: rd
5080	// Operand: rs1
5081	// Operand: imm
5082	return true;
5083	} // if
5084	break;
5085	} // case LH
5086	case RISCV::LHU: {
5087	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
5088	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5089	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`0`).getReg()) &&
5090	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5091	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5092	MI.getOperand(`2`).isImm() &&
5093	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `15`)) {
5094	// c.lhu $rd, ${imm}(${rs1})
5095	// Operand: rd
5096	// Operand: rs1
5097	// Operand: imm
5098	return true;
5099	} // if
5100	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
5101	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5102	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`0`).getReg()) &&
5103	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5104	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5105	MI.getOperand(`2`).isImm() &&
5106	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `16`)) {
5107	// qk.c.lhu $rd, ${imm}(${rs1})
5108	// Operand: rd
5109	// Operand: rs1
5110	// Operand: imm
5111	return true;
5112	} // if
5113	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
5114	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5115	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`0`).getReg()) &&
5116	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5117	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5118	MI.getOperand(`2`).isImm() &&
5119	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `17`)) {
5120	// qk.c.lhusp $rd_rs2, ${imm}(${rs1})
5121	// Operand: rd_rs2
5122	// Operand: rs1
5123	// Operand: imm
5124	return true;
5125	} // if
5126	break;
5127	} // case LHU
5128	case RISCV::LH_INX: {
5129	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
5130	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5131	RISCVMCRegisterClasses[RISCV::GPRF16CRegClassID].contains(MI.getOperand(`0`).getReg()) &&
5132	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5133	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5134	MI.getOperand(`2`).isImm() &&
5135	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `15`)) {
5136	// c.lh $rd, ${imm}(${rs1})
5137	// Operand: rd
5138	// Operand: rs1
5139	// Operand: imm
5140	return true;
5141	} // if
5142	break;
5143	} // case LH_INX
5144	case RISCV::LUI: {
5145	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
5146	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5147	RISCVMCRegisterClasses[RISCV::GPRNoX0X2RegClassID].contains(MI.getOperand(`0`).getReg()) &&
5148	MI.getOperand(`1`).isImm() &&
5149	RISCVValidateMachineOperand(MI.getOperand(`1`), &STI, `18`)) {
5150	// c.lui $rd, $imm
5151	// Operand: rd
5152	// Operand: imm
5153	return true;
5154	} // if
5155	break;
5156	} // case LUI
5157	case RISCV::LW: {
5158	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
5159	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5160	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`0`).getReg()) &&
5161	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5162	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5163	MI.getOperand(`2`).isImm() &&
5164	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `9`)) {
5165	// c.lw $rd, ${imm}(${rs1})
5166	// Operand: rd
5167	// Operand: rs1
5168	// Operand: imm
5169	return true;
5170	} // if
5171	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
5172	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5173	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`0`).getReg()) &&
5174	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5175	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5176	MI.getOperand(`2`).isImm() &&
5177	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `10`)) {
5178	// c.lwsp $rd, ${imm}(${rs1})
5179	// Operand: rd
5180	// Operand: rs1
5181	// Operand: imm
5182	return true;
5183	} // if
5184	break;
5185	} // case LW
5186	case RISCV::LW_INX: {
5187	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
5188	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5189	RISCVMCRegisterClasses[RISCV::GPRF32NoX0RegClassID].contains(MI.getOperand(`0`).getReg()) &&
5190	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5191	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5192	MI.getOperand(`2`).isImm() &&
5193	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `10`)) {
5194	// c.lwsp $rd, ${imm}(${rs1})
5195	// Operand: rd
5196	// Operand: rs1
5197	// Operand: imm
5198	return true;
5199	} // if
5200	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
5201	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5202	RISCVMCRegisterClasses[RISCV::GPRF32CRegClassID].contains(MI.getOperand(`0`).getReg()) &&
5203	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5204	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5205	MI.getOperand(`2`).isImm() &&
5206	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `9`)) {
5207	// c.lw $rd, ${imm}(${rs1})
5208	// Operand: rd
5209	// Operand: rs1
5210	// Operand: imm
5211	return true;
5212	} // if
5213	break;
5214	} // case LW_INX
5215	case RISCV::MUL: {
5216	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
5217	STI.getFeatureBits()[RISCV::FeatureStdExtZmmul] &&
5218	(MI.getOperand(`1`).isReg()) && (MI.getOperand(`0`).isReg()) &&
5219	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
5220	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5221	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5222	MI.getOperand(`2`).isReg() && MI.getOperand(`2`).getReg().isPhysical() &&
5223	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`2`).getReg())) {
5224	// c.mul $rd, $rs2
5225	// Operand: rd_wb
5226	// Operand: rd
5227	// Operand: rs2
5228	return true;
5229	} // if
5230	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
5231	STI.getFeatureBits()[RISCV::FeatureStdExtZmmul] &&
5232	(MI.getOperand(`2`).isReg()) && (MI.getOperand(`0`).isReg()) &&
5233	(MI.getOperand(`2`).getReg() == MI.getOperand(`0`).getReg()) &&
5234	MI.getOperand(`2`).isReg() && MI.getOperand(`2`).getReg().isPhysical() &&
5235	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`2`).getReg()) &&
5236	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5237	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg())) {
5238	// c.mul $rd, $rs2
5239	// Operand: rd_wb
5240	// Operand: rd
5241	// Operand: rs2
5242	return true;
5243	} // if
5244	break;
5245	} // case MUL
5246	case RISCV::OR: {
5247	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
5248	(MI.getOperand(`1`).isReg()) && (MI.getOperand(`0`).isReg()) &&
5249	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
5250	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5251	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5252	MI.getOperand(`2`).isReg() && MI.getOperand(`2`).getReg().isPhysical() &&
5253	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`2`).getReg())) {
5254	// c.or $rd, $rs2
5255	// Operand: rd_wb
5256	// Operand: rd
5257	// Operand: rs2
5258	return true;
5259	} // if
5260	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
5261	(MI.getOperand(`2`).isReg()) && (MI.getOperand(`0`).isReg()) &&
5262	(MI.getOperand(`2`).getReg() == MI.getOperand(`0`).getReg()) &&
5263	MI.getOperand(`2`).isReg() && MI.getOperand(`2`).getReg().isPhysical() &&
5264	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`2`).getReg()) &&
5265	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5266	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg())) {
5267	// c.or $rd, $rs2
5268	// Operand: rd_wb
5269	// Operand: rd
5270	// Operand: rs2
5271	return true;
5272	} // if
5273	break;
5274	} // case OR
5275	case RISCV::QC_EXTU: {
5276	if (STI.getFeatureBits()[RISCV::FeatureStdExtZbs] &&
5277	STI.getFeatureBits()[RISCV::FeatureVendorXqcibm] &&
5278	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5279	(MI.getOperand(`1`).isReg()) && (MI.getOperand(`0`).isReg()) &&
5280	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
5281	(MI.getOperand(`2`).isImm()) &&
5282	(MI.getOperand(`2`).getImm() == `1`) &&
5283	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5284	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5285	MI.getOperand(`3`).isImm() &&
5286	RISCVValidateMachineOperand(MI.getOperand(`3`), &STI, `6`)) {
5287	// qc.c.bexti $rs1, $shamt
5288	// Operand: rd
5289	// Operand: rs1
5290	// Operand: shamt
5291	return true;
5292	} // if
5293	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcibm] &&
5294	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5295	(MI.getOperand(`1`).isReg()) && (MI.getOperand(`0`).isReg()) &&
5296	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
5297	(MI.getOperand(`3`).isImm()) &&
5298	(MI.getOperand(`3`).getImm() == `0`) &&
5299	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5300	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`1`).getReg()) &&
5301	MI.getOperand(`2`).isImm() &&
5302	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `19`)) {
5303	// qc.c.extu $rd, $width
5304	// Operand: rd_wb
5305	// Operand: rd
5306	// Operand: width
5307	return true;
5308	} // if
5309	break;
5310	} // case QC_EXTU
5311	case RISCV::QC_E_ADDI: {
5312	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
5313	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5314	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
5315	(MI.getOperand(`1`).isReg()) && (MI.getOperand(`0`).isReg()) &&
5316	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
5317	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5318	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`1`).getReg()) &&
5319	MI.getOperand(`2`).isImm() &&
5320	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `1`)) {
5321	// c.addi $rd, $imm
5322	// Operand: rd_wb
5323	// Operand: rd
5324	// Operand: imm
5325	return true;
5326	} // if
5327	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
5328	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5329	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
5330	(MI.getOperand(`0`).isReg()) &&
5331	(MI.getOperand(`0`).getReg() == RISCV::X2) &&
5332	(MI.getOperand(`1`).isReg()) &&
5333	(MI.getOperand(`1`).getReg() == RISCV::X2) &&
5334	MI.getOperand(`2`).isImm() &&
5335	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `2`)) {
5336	// c.addi16sp $rd, $imm
5337	// Operand: rd_wb
5338	// Operand: rd
5339	// Operand: imm
5340	return true;
5341	} // if
5342	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
5343	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5344	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
5345	(MI.getOperand(`2`).isImm()) &&
5346	(MI.getOperand(`2`).getImm() == `0`) &&
5347	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5348	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`0`).getReg()) &&
5349	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5350	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`1`).getReg())) {
5351	// c.mv $rs1, $rs2
5352	// Operand: rs1
5353	// Operand: rs2
5354	return true;
5355	} // if
5356	break;
5357	} // case QC_E_ADDI
5358	case RISCV::QC_E_ANDI: {
5359	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilia] &&
5360	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5361	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
5362	(MI.getOperand(`1`).isReg()) && (MI.getOperand(`0`).isReg()) &&
5363	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
5364	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5365	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5366	MI.getOperand(`2`).isImm() &&
5367	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `4`)) {
5368	// c.andi $rs1, $imm
5369	// Operand: rd
5370	// Operand: rs1
5371	// Operand: imm
5372	return true;
5373	} // if
5374	break;
5375	} // case QC_E_ANDI
5376	case RISCV::QC_E_BEQI: {
5377	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcibi] &&
5378	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5379	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5380	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`0`).getReg()) &&
5381	MI.getOperand(`1`).isImm() &&
5382	RISCVValidateMachineOperand(MI.getOperand(`1`), &STI, `20`) &&
5383	MI.getOperand(`2`).isImm() &&
5384	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `21`)) {
5385	// qc.beqi $rs1, $rs2, $imm12
5386	// Operand: rs1
5387	// Operand: rs2
5388	// Operand: imm12
5389	return true;
5390	} // if
5391	break;
5392	} // case QC_E_BEQI
5393	case RISCV::QC_E_BGEI: {
5394	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcibi] &&
5395	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5396	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5397	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`0`).getReg()) &&
5398	MI.getOperand(`1`).isImm() &&
5399	RISCVValidateMachineOperand(MI.getOperand(`1`), &STI, `20`) &&
5400	MI.getOperand(`2`).isImm() &&
5401	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `21`)) {
5402	// qc.bgei $rs1, $rs2, $imm12
5403	// Operand: rs1
5404	// Operand: rs2
5405	// Operand: imm12
5406	return true;
5407	} // if
5408	break;
5409	} // case QC_E_BGEI
5410	case RISCV::QC_E_BGEUI: {
5411	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcibi] &&
5412	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5413	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5414	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`0`).getReg()) &&
5415	MI.getOperand(`1`).isImm() &&
5416	RISCVValidateMachineOperand(MI.getOperand(`1`), &STI, `22`) &&
5417	MI.getOperand(`2`).isImm() &&
5418	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `21`)) {
5419	// qc.bgeui $rs1, $rs2, $imm12
5420	// Operand: rs1
5421	// Operand: rs2
5422	// Operand: imm12
5423	return true;
5424	} // if
5425	break;
5426	} // case QC_E_BGEUI
5427	case RISCV::QC_E_BLTI: {
5428	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcibi] &&
5429	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5430	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5431	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`0`).getReg()) &&
5432	MI.getOperand(`1`).isImm() &&
5433	RISCVValidateMachineOperand(MI.getOperand(`1`), &STI, `20`) &&
5434	MI.getOperand(`2`).isImm() &&
5435	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `21`)) {
5436	// qc.blti $rs1, $rs2, $imm12
5437	// Operand: rs1
5438	// Operand: rs2
5439	// Operand: imm12
5440	return true;
5441	} // if
5442	break;
5443	} // case QC_E_BLTI
5444	case RISCV::QC_E_BLTUI: {
5445	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcibi] &&
5446	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5447	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5448	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`0`).getReg()) &&
5449	MI.getOperand(`1`).isImm() &&
5450	RISCVValidateMachineOperand(MI.getOperand(`1`), &STI, `22`) &&
5451	MI.getOperand(`2`).isImm() &&
5452	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `21`)) {
5453	// qc.bltui $rs1, $rs2, $imm12
5454	// Operand: rs1
5455	// Operand: rs2
5456	// Operand: imm12
5457	return true;
5458	} // if
5459	break;
5460	} // case QC_E_BLTUI
5461	case RISCV::QC_E_BNEI: {
5462	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcibi] &&
5463	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5464	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5465	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`0`).getReg()) &&
5466	MI.getOperand(`1`).isImm() &&
5467	RISCVValidateMachineOperand(MI.getOperand(`1`), &STI, `20`) &&
5468	MI.getOperand(`2`).isImm() &&
5469	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `21`)) {
5470	// qc.bnei $rs1, $rs2, $imm12
5471	// Operand: rs1
5472	// Operand: rs2
5473	// Operand: imm12
5474	return true;
5475	} // if
5476	break;
5477	} // case QC_E_BNEI
5478	case RISCV::QC_E_J: {
5479	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilb] &&
5480	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5481	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
5482	MI.getOperand(`0`).isImm() &&
5483	RISCVValidateMachineOperand(MI.getOperand(`0`), &STI, `11`)) {
5484	// c.j $offset
5485	// Operand: offset
5486	return true;
5487	} // if
5488	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilb] &&
5489	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5490	MI.getOperand(`0`).isImm() &&
5491	RISCVValidateMachineOperand(MI.getOperand(`0`), &STI, `23`)) {
5492	// jal $rd, $imm20
5493	// Operand: rd
5494	// Operand: imm20
5495	return true;
5496	} // if
5497	break;
5498	} // case QC_E_J
5499	case RISCV::QC_E_JAL: {
5500	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilb] &&
5501	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5502	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
5503	MI.getOperand(`0`).isImm() &&
5504	RISCVValidateMachineOperand(MI.getOperand(`0`), &STI, `11`)) {
5505	// c.jal $offset
5506	// Operand: offset
5507	return true;
5508	} // if
5509	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilb] &&
5510	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5511	MI.getOperand(`0`).isImm() &&
5512	RISCVValidateMachineOperand(MI.getOperand(`0`), &STI, `23`)) {
5513	// jal $rd, $imm20
5514	// Operand: rd
5515	// Operand: imm20
5516	return true;
5517	} // if
5518	break;
5519	} // case QC_E_JAL
5520	case RISCV::QC_E_LB: {
5521	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
5522	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5523	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5524	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(`0`).getReg()) &&
5525	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5526	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5527	MI.getOperand(`2`).isImm() &&
5528	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `24`)) {
5529	// lb $rd, ${imm12}(${rs1})
5530	// Operand: rd
5531	// Operand: rs1
5532	// Operand: imm12
5533	return true;
5534	} // if
5535	break;
5536	} // case QC_E_LB
5537	case RISCV::QC_E_LBU: {
5538	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
5539	STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
5540	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5541	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5542	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`0`).getReg()) &&
5543	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5544	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5545	MI.getOperand(`2`).isImm() &&
5546	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `12`)) {
5547	// c.lbu $rd, ${imm}(${rs1})
5548	// Operand: rd
5549	// Operand: rs1
5550	// Operand: imm
5551	return true;
5552	} // if
5553	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
5554	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5555	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5556	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(`0`).getReg()) &&
5557	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5558	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5559	MI.getOperand(`2`).isImm() &&
5560	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `24`)) {
5561	// lbu $rd, ${imm12}(${rs1})
5562	// Operand: rd
5563	// Operand: rs1
5564	// Operand: imm12
5565	return true;
5566	} // if
5567	break;
5568	} // case QC_E_LBU
5569	case RISCV::QC_E_LH: {
5570	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
5571	STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
5572	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5573	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5574	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`0`).getReg()) &&
5575	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5576	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5577	MI.getOperand(`2`).isImm() &&
5578	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `15`)) {
5579	// c.lh $rd, ${imm}(${rs1})
5580	// Operand: rd
5581	// Operand: rs1
5582	// Operand: imm
5583	return true;
5584	} // if
5585	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
5586	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5587	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5588	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(`0`).getReg()) &&
5589	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5590	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5591	MI.getOperand(`2`).isImm() &&
5592	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `24`)) {
5593	// lh $rd, ${imm12}(${rs1})
5594	// Operand: rd
5595	// Operand: rs1
5596	// Operand: imm12
5597	return true;
5598	} // if
5599	break;
5600	} // case QC_E_LH
5601	case RISCV::QC_E_LHU: {
5602	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
5603	STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
5604	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5605	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5606	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`0`).getReg()) &&
5607	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5608	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5609	MI.getOperand(`2`).isImm() &&
5610	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `15`)) {
5611	// c.lhu $rd, ${imm}(${rs1})
5612	// Operand: rd
5613	// Operand: rs1
5614	// Operand: imm
5615	return true;
5616	} // if
5617	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
5618	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5619	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5620	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(`0`).getReg()) &&
5621	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5622	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5623	MI.getOperand(`2`).isImm() &&
5624	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `24`)) {
5625	// lhu $rd, ${imm12}(${rs1})
5626	// Operand: rd
5627	// Operand: rs1
5628	// Operand: imm12
5629	return true;
5630	} // if
5631	break;
5632	} // case QC_E_LHU
5633	case RISCV::QC_E_LI: {
5634	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcili] &&
5635	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5636	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
5637	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5638	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`0`).getReg()) &&
5639	MI.getOperand(`1`).isImm() &&
5640	RISCVValidateMachineOperand(MI.getOperand(`1`), &STI, `4`)) {
5641	// c.li $rd, $imm
5642	// Operand: rd
5643	// Operand: imm
5644	return true;
5645	} // if
5646	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcili] &&
5647	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5648	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5649	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`0`).getReg()) &&
5650	MI.getOperand(`1`).isImm() &&
5651	RISCVValidateMachineOperand(MI.getOperand(`1`), &STI, `25`)) {
5652	// qc.li $rd, $imm20
5653	// Operand: rd
5654	// Operand: imm20
5655	return true;
5656	} // if
5657	break;
5658	} // case QC_E_LI
5659	case RISCV::QC_E_LW: {
5660	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
5661	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5662	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
5663	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5664	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`0`).getReg()) &&
5665	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5666	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5667	MI.getOperand(`2`).isImm() &&
5668	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `9`)) {
5669	// c.lw $rd, ${imm}(${rs1})
5670	// Operand: rd
5671	// Operand: rs1
5672	// Operand: imm
5673	return true;
5674	} // if
5675	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
5676	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5677	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
5678	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5679	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`0`).getReg()) &&
5680	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5681	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5682	MI.getOperand(`2`).isImm() &&
5683	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `10`)) {
5684	// c.lwsp $rd, ${imm}(${rs1})
5685	// Operand: rd
5686	// Operand: rs1
5687	// Operand: imm
5688	return true;
5689	} // if
5690	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
5691	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5692	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5693	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(`0`).getReg()) &&
5694	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5695	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5696	MI.getOperand(`2`).isImm() &&
5697	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `24`)) {
5698	// lw $rd, ${imm12}(${rs1})
5699	// Operand: rd
5700	// Operand: rs1
5701	// Operand: imm12
5702	return true;
5703	} // if
5704	break;
5705	} // case QC_E_LW
5706	case RISCV::QC_E_SB: {
5707	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
5708	STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
5709	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5710	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5711	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`0`).getReg()) &&
5712	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5713	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5714	MI.getOperand(`2`).isImm() &&
5715	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `12`)) {
5716	// c.sb $rs2, ${imm}(${rs1})
5717	// Operand: rs2
5718	// Operand: rs1
5719	// Operand: imm
5720	return true;
5721	} // if
5722	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
5723	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5724	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5725	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(`0`).getReg()) &&
5726	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5727	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5728	MI.getOperand(`2`).isImm() &&
5729	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `24`)) {
5730	// sb $rs2, ${imm12}(${rs1})
5731	// Operand: rs2
5732	// Operand: rs1
5733	// Operand: imm12
5734	return true;
5735	} // if
5736	break;
5737	} // case QC_E_SB
5738	case RISCV::QC_E_SH: {
5739	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
5740	STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
5741	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5742	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5743	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`0`).getReg()) &&
5744	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5745	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5746	MI.getOperand(`2`).isImm() &&
5747	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `15`)) {
5748	// c.sh $rs2, ${imm}(${rs1})
5749	// Operand: rs2
5750	// Operand: rs1
5751	// Operand: imm
5752	return true;
5753	} // if
5754	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
5755	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5756	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5757	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(`0`).getReg()) &&
5758	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5759	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5760	MI.getOperand(`2`).isImm() &&
5761	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `24`)) {
5762	// sh $rs2, ${imm12}(${rs1})
5763	// Operand: rs2
5764	// Operand: rs1
5765	// Operand: imm12
5766	return true;
5767	} // if
5768	break;
5769	} // case QC_E_SH
5770	case RISCV::QC_E_SW: {
5771	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
5772	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5773	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
5774	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5775	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`0`).getReg()) &&
5776	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5777	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5778	MI.getOperand(`2`).isImm() &&
5779	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `9`)) {
5780	// c.sw $rs2, ${imm}(${rs1})
5781	// Operand: rs2
5782	// Operand: rs1
5783	// Operand: imm
5784	return true;
5785	} // if
5786	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
5787	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5788	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
5789	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5790	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(`0`).getReg()) &&
5791	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5792	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5793	MI.getOperand(`2`).isImm() &&
5794	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `10`)) {
5795	// c.swsp $rs2, ${imm}(${rs1})
5796	// Operand: rs2
5797	// Operand: rs1
5798	// Operand: imm
5799	return true;
5800	} // if
5801	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcilo] &&
5802	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5803	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5804	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(`0`).getReg()) &&
5805	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5806	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5807	MI.getOperand(`2`).isImm() &&
5808	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `24`)) {
5809	// sw $rs2, ${imm12}(${rs1})
5810	// Operand: rs2
5811	// Operand: rs1
5812	// Operand: imm12
5813	return true;
5814	} // if
5815	break;
5816	} // case QC_E_SW
5817	case RISCV::QC_LI: {
5818	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcili] &&
5819	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5820	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
5821	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5822	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`0`).getReg()) &&
5823	MI.getOperand(`1`).isImm() &&
5824	RISCVValidateMachineOperand(MI.getOperand(`1`), &STI, `4`)) {
5825	// c.li $rd, $imm
5826	// Operand: rd
5827	// Operand: imm
5828	return true;
5829	} // if
5830	break;
5831	} // case QC_LI
5832	case RISCV::QC_MULIADD: {
5833	if (STI.getFeatureBits()[RISCV::FeatureVendorXqciac] &&
5834	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5835	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5836	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`0`).getReg()) &&
5837	MI.getOperand(`2`).isReg() && MI.getOperand(`2`).getReg().isPhysical() &&
5838	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`2`).getReg()) &&
5839	MI.getOperand(`3`).isImm() &&
5840	RISCVValidateMachineOperand(MI.getOperand(`3`), &STI, `13`)) {
5841	// qc.c.muliadd $rd, $rs1, $uimm
5842	// Operand: rd_wb
5843	// Operand: rd
5844	// Operand: rs1
5845	// Operand: uimm
5846	return true;
5847	} // if
5848	break;
5849	} // case QC_MULIADD
5850	case RISCV::QC_MVEQI: {
5851	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcicm] &&
5852	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5853	(MI.getOperand(`2`).isReg()) && (MI.getOperand(`0`).isReg()) &&
5854	(MI.getOperand(`2`).getReg() == MI.getOperand(`0`).getReg()) &&
5855	(MI.getOperand(`3`).isImm()) &&
5856	(MI.getOperand(`3`).getImm() == `0`) &&
5857	MI.getOperand(`2`).isReg() && MI.getOperand(`2`).getReg().isPhysical() &&
5858	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`2`).getReg()) &&
5859	MI.getOperand(`4`).isReg() && MI.getOperand(`4`).getReg().isPhysical() &&
5860	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`4`).getReg())) {
5861	// qc.c.mveqz $rd, $rs1
5862	// Operand: rd_wb
5863	// Operand: rd
5864	// Operand: rs1
5865	return true;
5866	} // if
5867	break;
5868	} // case QC_MVEQI
5869	case RISCV::QC_MVLTUI: {
5870	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcicm] &&
5871	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5872	(MI.getOperand(`2`).isReg()) && (MI.getOperand(`0`).isReg()) &&
5873	(MI.getOperand(`2`).getReg() == MI.getOperand(`0`).getReg()) &&
5874	(MI.getOperand(`3`).isImm()) &&
5875	(MI.getOperand(`3`).getImm() == `1`) &&
5876	MI.getOperand(`2`).isReg() && MI.getOperand(`2`).getReg().isPhysical() &&
5877	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`2`).getReg()) &&
5878	MI.getOperand(`4`).isReg() && MI.getOperand(`4`).getReg().isPhysical() &&
5879	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`4`).getReg())) {
5880	// qc.c.mveqz $rd, $rs1
5881	// Operand: rd_wb
5882	// Operand: rd
5883	// Operand: rs1
5884	return true;
5885	} // if
5886	break;
5887	} // case QC_MVLTUI
5888	case RISCV::QC_SYNC: {
5889	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcisync] &&
5890	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5891	MI.getOperand(`0`).isImm() &&
5892	RISCVValidateMachineOperand(MI.getOperand(`0`), &STI, `26`)) {
5893	// qc.c.sync $slist
5894	// Operand: slist
5895	return true;
5896	} // if
5897	break;
5898	} // case QC_SYNC
5899	case RISCV::QC_SYNCR: {
5900	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcisync] &&
5901	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5902	MI.getOperand(`0`).isImm() &&
5903	RISCVValidateMachineOperand(MI.getOperand(`0`), &STI, `26`)) {
5904	// qc.c.syncr $slist
5905	// Operand: slist
5906	return true;
5907	} // if
5908	break;
5909	} // case QC_SYNCR
5910	case RISCV::QC_SYNCWF: {
5911	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcisync] &&
5912	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5913	MI.getOperand(`0`).isImm() &&
5914	RISCVValidateMachineOperand(MI.getOperand(`0`), &STI, `26`)) {
5915	// qc.c.syncwf $slist
5916	// Operand: slist
5917	return true;
5918	} // if
5919	break;
5920	} // case QC_SYNCWF
5921	case RISCV::QC_SYNCWL: {
5922	if (STI.getFeatureBits()[RISCV::FeatureVendorXqcisync] &&
5923	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
5924	MI.getOperand(`0`).isImm() &&
5925	RISCVValidateMachineOperand(MI.getOperand(`0`), &STI, `26`)) {
5926	// qc.c.syncwl $slist
5927	// Operand: slist
5928	return true;
5929	} // if
5930	break;
5931	} // case QC_SYNCWL
5932	case RISCV::SB: {
5933	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
5934	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5935	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`0`).getReg()) &&
5936	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5937	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5938	MI.getOperand(`2`).isImm() &&
5939	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `12`)) {
5940	// c.sb $rs2, ${imm}(${rs1})
5941	// Operand: rs2
5942	// Operand: rs1
5943	// Operand: imm
5944	return true;
5945	} // if
5946	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
5947	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5948	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`0`).getReg()) &&
5949	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5950	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5951	MI.getOperand(`2`).isImm() &&
5952	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `13`)) {
5953	// qk.c.sb $rs2, ${imm}(${rs1})
5954	// Operand: rs2
5955	// Operand: rs1
5956	// Operand: imm
5957	return true;
5958	} // if
5959	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
5960	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5961	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`0`).getReg()) &&
5962	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5963	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5964	MI.getOperand(`2`).isImm() &&
5965	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `14`)) {
5966	// qk.c.sbsp $rd_rs2, ${imm}(${rs1})
5967	// Operand: rd_rs2
5968	// Operand: rs1
5969	// Operand: imm
5970	return true;
5971	} // if
5972	break;
5973	} // case SB
5974	case RISCV::SD: {
5975	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
5976	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
5977	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5978	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`0`).getReg()) &&
5979	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5980	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5981	MI.getOperand(`2`).isImm() &&
5982	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `7`)) {
5983	// c.sd $rs2, ${imm}(${rs1})
5984	// Operand: rs2
5985	// Operand: rs1
5986	// Operand: imm
5987	return true;
5988	} // if
5989	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
5990	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
5991	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
5992	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(`0`).getReg()) &&
5993	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
5994	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(`1`).getReg()) &&
5995	MI.getOperand(`2`).isImm() &&
5996	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `8`)) {
5997	// c.sdsp $rs2, ${imm}(${rs1})
5998	// Operand: rs2
5999	// Operand: rs1
6000	// Operand: imm
6001	return true;
6002	} // if
6003	break;
6004	} // case SD
6005	case RISCV::SD_RV32: {
6006	if (STI.getFeatureBits()[RISCV::FeatureStdExtZclsd] &&
6007	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6008	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6009	RISCVMCRegisterClasses[RISCV::GPRPairRegClassID].contains(MI.getOperand(`0`).getReg()) &&
6010	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6011	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(`1`).getReg()) &&
6012	MI.getOperand(`2`).isImm() &&
6013	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `8`)) {
6014	// c.sdsp $rs2, ${imm}(${rs1})
6015	// Operand: rs2
6016	// Operand: rs1
6017	// Operand: imm
6018	return true;
6019	} // if
6020	if (STI.getFeatureBits()[RISCV::FeatureStdExtZclsd] &&
6021	!STI.getFeatureBits()[RISCV::Feature64Bit] &&
6022	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6023	RISCVMCRegisterClasses[RISCV::GPRPairCRegClassID].contains(MI.getOperand(`0`).getReg()) &&
6024	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6025	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
6026	MI.getOperand(`2`).isImm() &&
6027	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `7`)) {
6028	// c.sd $rs2, ${imm}(${rs1})
6029	// Operand: rs2
6030	// Operand: rs1
6031	// Operand: imm
6032	return true;
6033	} // if
6034	break;
6035	} // case SD_RV32
6036	case RISCV::SEXT_B: {
6037	if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] &&
6038	STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
6039	(MI.getOperand(`1`).isReg()) && (MI.getOperand(`0`).isReg()) &&
6040	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
6041	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6042	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg())) {
6043	// c.sext.b $rd
6044	// Operand: rd_wb
6045	// Operand: rd
6046	return true;
6047	} // if
6048	break;
6049	} // case SEXT_B
6050	case RISCV::SEXT_H: {
6051	if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] &&
6052	STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
6053	(MI.getOperand(`1`).isReg()) && (MI.getOperand(`0`).isReg()) &&
6054	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
6055	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6056	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg())) {
6057	// c.sext.h $rd
6058	// Operand: rd_wb
6059	// Operand: rd
6060	return true;
6061	} // if
6062	break;
6063	} // case SEXT_H
6064	case RISCV::SH: {
6065	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
6066	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6067	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`0`).getReg()) &&
6068	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6069	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
6070	MI.getOperand(`2`).isImm() &&
6071	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `15`)) {
6072	// c.sh $rs2, ${imm}(${rs1})
6073	// Operand: rs2
6074	// Operand: rs1
6075	// Operand: imm
6076	return true;
6077	} // if
6078	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
6079	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6080	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`0`).getReg()) &&
6081	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6082	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
6083	MI.getOperand(`2`).isImm() &&
6084	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `16`)) {
6085	// qk.c.sh $rs2, ${imm}(${rs1})
6086	// Operand: rs2
6087	// Operand: rs1
6088	// Operand: imm
6089	return true;
6090	} // if
6091	if (STI.getFeatureBits()[RISCV::FeatureVendorXwchc] &&
6092	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6093	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`0`).getReg()) &&
6094	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6095	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(`1`).getReg()) &&
6096	MI.getOperand(`2`).isImm() &&
6097	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `17`)) {
6098	// qk.c.shsp $rd_rs2, ${imm}(${rs1})
6099	// Operand: rd_rs2
6100	// Operand: rs1
6101	// Operand: imm
6102	return true;
6103	} // if
6104	break;
6105	} // case SH
6106	case RISCV::SH_INX: {
6107	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
6108	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6109	RISCVMCRegisterClasses[RISCV::GPRF16CRegClassID].contains(MI.getOperand(`0`).getReg()) &&
6110	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6111	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
6112	MI.getOperand(`2`).isImm() &&
6113	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `15`)) {
6114	// c.sh $rs2, ${imm}(${rs1})
6115	// Operand: rs2
6116	// Operand: rs1
6117	// Operand: imm
6118	return true;
6119	} // if
6120	break;
6121	} // case SH_INX
6122	case RISCV::SLLI: {
6123	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
6124	(MI.getOperand(`1`).isReg()) && (MI.getOperand(`0`).isReg()) &&
6125	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
6126	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6127	RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(`1`).getReg()) &&
6128	MI.getOperand(`2`).isImm() &&
6129	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `6`)) {
6130	// c.slli $rd, $imm
6131	// Operand: rd_wb
6132	// Operand: rd
6133	// Operand: imm
6134	return true;
6135	} // if
6136	break;
6137	} // case SLLI
6138	case RISCV::SRAI: {
6139	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
6140	(MI.getOperand(`1`).isReg()) && (MI.getOperand(`0`).isReg()) &&
6141	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
6142	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6143	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
6144	MI.getOperand(`2`).isImm() &&
6145	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `6`)) {
6146	// c.srai $rs1, $imm
6147	// Operand: rd
6148	// Operand: rs1
6149	// Operand: imm
6150	return true;
6151	} // if
6152	break;
6153	} // case SRAI
6154	case RISCV::SRLI: {
6155	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
6156	(MI.getOperand(`1`).isReg()) && (MI.getOperand(`0`).isReg()) &&
6157	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
6158	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6159	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
6160	MI.getOperand(`2`).isImm() &&
6161	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `6`)) {
6162	// c.srli $rs1, $imm
6163	// Operand: rd
6164	// Operand: rs1
6165	// Operand: imm
6166	return true;
6167	} // if
6168	break;
6169	} // case SRLI
6170	case RISCV::SSPOPCHK: {
6171	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcmop] &&
6172	STI.getFeatureBits()[RISCV::FeatureStdExtZicfiss] &&
6173	(MI.getOperand(`0`).isReg()) &&
6174	(MI.getOperand(`0`).getReg() == RISCV::X5)) {
6175	// c.sspopchk $rs1
6176	// Operand: rs1
6177	return true;
6178	} // if
6179	break;
6180	} // case SSPOPCHK
6181	case RISCV::SSPUSH: {
6182	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcmop] &&
6183	STI.getFeatureBits()[RISCV::FeatureStdExtZicfiss] &&
6184	(MI.getOperand(`0`).isReg()) &&
6185	(MI.getOperand(`0`).getReg() == RISCV::X1)) {
6186	// c.sspush $rs1
6187	// Operand: rs1
6188	return true;
6189	} // if
6190	break;
6191	} // case SSPUSH
6192	case RISCV::SUB: {
6193	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
6194	(MI.getOperand(`1`).isReg()) && (MI.getOperand(`0`).isReg()) &&
6195	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
6196	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6197	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
6198	MI.getOperand(`2`).isReg() && MI.getOperand(`2`).getReg().isPhysical() &&
6199	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`2`).getReg())) {
6200	// c.sub $rd, $rs2
6201	// Operand: rd_wb
6202	// Operand: rd
6203	// Operand: rs2
6204	return true;
6205	} // if
6206	break;
6207	} // case SUB
6208	case RISCV::SUBW: {
6209	if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
6210	(STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
6211	(MI.getOperand(`1`).isReg()) && (MI.getOperand(`0`).isReg()) &&
6212	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
6213	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6214	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
6215	MI.getOperand(`2`).isReg() && MI.getOperand(`2`).getReg().isPhysical() &&
6216	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`2`).getReg())) {
6217	// c.subw $rd, $rs2
6218	// Operand: rd_wb
6219	// Operand: rd
6220	// Operand: rs2
6221	return true;
6222	} // if
6223	break;
6224	} // case SUBW
6225	case RISCV::SW: {
6226	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
6227	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6228	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`0`).getReg()) &&
6229	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6230	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
6231	MI.getOperand(`2`).isImm() &&
6232	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `9`)) {
6233	// c.sw $rs2, ${imm}(${rs1})
6234	// Operand: rs2
6235	// Operand: rs1
6236	// Operand: imm
6237	return true;
6238	} // if
6239	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
6240	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6241	RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(`0`).getReg()) &&
6242	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6243	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(`1`).getReg()) &&
6244	MI.getOperand(`2`).isImm() &&
6245	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `10`)) {
6246	// c.swsp $rs2, ${imm}(${rs1})
6247	// Operand: rs2
6248	// Operand: rs1
6249	// Operand: imm
6250	return true;
6251	} // if
6252	break;
6253	} // case SW
6254	case RISCV::SW_INX: {
6255	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
6256	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6257	RISCVMCRegisterClasses[RISCV::GPRF32RegClassID].contains(MI.getOperand(`0`).getReg()) &&
6258	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6259	RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(`1`).getReg()) &&
6260	MI.getOperand(`2`).isImm() &&
6261	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `10`)) {
6262	// c.swsp $rs2, ${imm}(${rs1})
6263	// Operand: rs2
6264	// Operand: rs1
6265	// Operand: imm
6266	return true;
6267	} // if
6268	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
6269	MI.getOperand(`0`).isReg() && MI.getOperand(`0`).getReg().isPhysical() &&
6270	RISCVMCRegisterClasses[RISCV::GPRF32CRegClassID].contains(MI.getOperand(`0`).getReg()) &&
6271	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6272	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
6273	MI.getOperand(`2`).isImm() &&
6274	RISCVValidateMachineOperand(MI.getOperand(`2`), &STI, `9`)) {
6275	// c.sw $rs2, ${imm}(${rs1})
6276	// Operand: rs2
6277	// Operand: rs1
6278	// Operand: imm
6279	return true;
6280	} // if
6281	break;
6282	} // case SW_INX
6283	case RISCV::UNIMP: {
6284	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca])) {
6285	// c.unimp
6286	return true;
6287	} // if
6288	break;
6289	} // case UNIMP
6290	case RISCV::XOR: {
6291	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
6292	(MI.getOperand(`1`).isReg()) && (MI.getOperand(`0`).isReg()) &&
6293	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
6294	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6295	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg()) &&
6296	MI.getOperand(`2`).isReg() && MI.getOperand(`2`).getReg().isPhysical() &&
6297	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`2`).getReg())) {
6298	// c.xor $rd, $rs2
6299	// Operand: rd_wb
6300	// Operand: rd
6301	// Operand: rs2
6302	return true;
6303	} // if
6304	if ((STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
6305	(MI.getOperand(`2`).isReg()) && (MI.getOperand(`0`).isReg()) &&
6306	(MI.getOperand(`2`).getReg() == MI.getOperand(`0`).getReg()) &&
6307	MI.getOperand(`2`).isReg() && MI.getOperand(`2`).getReg().isPhysical() &&
6308	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`2`).getReg()) &&
6309	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6310	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg())) {
6311	// c.xor $rd, $rs2
6312	// Operand: rd_wb
6313	// Operand: rd
6314	// Operand: rs2
6315	return true;
6316	} // if
6317	break;
6318	} // case XOR
6319	case RISCV::XORI: {
6320	if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
6321	(MI.getOperand(`1`).isReg()) && (MI.getOperand(`0`).isReg()) &&
6322	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
6323	(MI.getOperand(`2`).isImm()) &&
6324	(MI.getOperand(`2`).getImm() == -`1`) &&
6325	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6326	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg())) {
6327	// c.not $rd
6328	// Operand: rd_wb
6329	// Operand: rd
6330	return true;
6331	} // if
6332	break;
6333	} // case XORI
6334	case RISCV::ZEXT_H_RV32: {
6335	if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] &&
6336	STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
6337	(MI.getOperand(`1`).isReg()) && (MI.getOperand(`0`).isReg()) &&
6338	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
6339	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6340	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg())) {
6341	// c.zext.h $rd
6342	// Operand: rd_wb
6343	// Operand: rd
6344	return true;
6345	} // if
6346	break;
6347	} // case ZEXT_H_RV32
6348	case RISCV::ZEXT_H_RV64: {
6349	if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] &&
6350	STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
6351	(MI.getOperand(`1`).isReg()) && (MI.getOperand(`0`).isReg()) &&
6352	(MI.getOperand(`1`).getReg() == MI.getOperand(`0`).getReg()) &&
6353	MI.getOperand(`1`).isReg() && MI.getOperand(`1`).getReg().isPhysical() &&
6354	RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(`1`).getReg())) {
6355	// c.zext.h $rd
6356	// Operand: rd_wb
6357	// Operand: rd
6358	return true;
6359	} // if
6360
6361	} // case ZEXT_H_RV64
6362	} // switch
6363	return false;
6364	}
6365
6366	#endif //GEN_CHECK_COMPRESS_INSTR
6367
6368

Browse the source code of llvm_projects/build/lib/Target/RISCV/RISCVGenCompressInstEmitter.inc