1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11namespace llvm::SPIRV {
12 enum {
13 PHI = 0,
14 INLINEASM = 1,
15 INLINEASM_BR = 2,
16 CFI_INSTRUCTION = 3,
17 EH_LABEL = 4,
18 GC_LABEL = 5,
19 ANNOTATION_LABEL = 6,
20 KILL = 7,
21 EXTRACT_SUBREG = 8,
22 INSERT_SUBREG = 9,
23 IMPLICIT_DEF = 10,
24 INIT_UNDEF = 11,
25 SUBREG_TO_REG = 12,
26 COPY_TO_REGCLASS = 13,
27 DBG_VALUE = 14,
28 DBG_VALUE_LIST = 15,
29 DBG_INSTR_REF = 16,
30 DBG_PHI = 17,
31 DBG_LABEL = 18,
32 REG_SEQUENCE = 19,
33 COPY = 20,
34 BUNDLE = 21,
35 LIFETIME_START = 22,
36 LIFETIME_END = 23,
37 PSEUDO_PROBE = 24,
38 ARITH_FENCE = 25,
39 STACKMAP = 26,
40 FENTRY_CALL = 27,
41 PATCHPOINT = 28,
42 LOAD_STACK_GUARD = 29,
43 PREALLOCATED_SETUP = 30,
44 PREALLOCATED_ARG = 31,
45 STATEPOINT = 32,
46 LOCAL_ESCAPE = 33,
47 FAULTING_OP = 34,
48 PATCHABLE_OP = 35,
49 PATCHABLE_FUNCTION_ENTER = 36,
50 PATCHABLE_RET = 37,
51 PATCHABLE_FUNCTION_EXIT = 38,
52 PATCHABLE_TAIL_CALL = 39,
53 PATCHABLE_EVENT_CALL = 40,
54 PATCHABLE_TYPED_EVENT_CALL = 41,
55 ICALL_BRANCH_FUNNEL = 42,
56 FAKE_USE = 43,
57 MEMBARRIER = 44,
58 JUMP_TABLE_DEBUG_INFO = 45,
59 CONVERGENCECTRL_ENTRY = 46,
60 CONVERGENCECTRL_ANCHOR = 47,
61 CONVERGENCECTRL_LOOP = 48,
62 CONVERGENCECTRL_GLUE = 49,
63 G_ASSERT_SEXT = 50,
64 G_ASSERT_ZEXT = 51,
65 G_ASSERT_ALIGN = 52,
66 G_ADD = 53,
67 G_SUB = 54,
68 G_MUL = 55,
69 G_SDIV = 56,
70 G_UDIV = 57,
71 G_SREM = 58,
72 G_UREM = 59,
73 G_SDIVREM = 60,
74 G_UDIVREM = 61,
75 G_AND = 62,
76 G_OR = 63,
77 G_XOR = 64,
78 G_ABDS = 65,
79 G_ABDU = 66,
80 G_IMPLICIT_DEF = 67,
81 G_PHI = 68,
82 G_FRAME_INDEX = 69,
83 G_GLOBAL_VALUE = 70,
84 G_PTRAUTH_GLOBAL_VALUE = 71,
85 G_CONSTANT_POOL = 72,
86 G_EXTRACT = 73,
87 G_UNMERGE_VALUES = 74,
88 G_INSERT = 75,
89 G_MERGE_VALUES = 76,
90 G_BUILD_VECTOR = 77,
91 G_BUILD_VECTOR_TRUNC = 78,
92 G_CONCAT_VECTORS = 79,
93 G_PTRTOINT = 80,
94 G_INTTOPTR = 81,
95 G_BITCAST = 82,
96 G_FREEZE = 83,
97 G_CONSTANT_FOLD_BARRIER = 84,
98 G_INTRINSIC_FPTRUNC_ROUND = 85,
99 G_INTRINSIC_TRUNC = 86,
100 G_INTRINSIC_ROUND = 87,
101 G_INTRINSIC_LRINT = 88,
102 G_INTRINSIC_LLRINT = 89,
103 G_INTRINSIC_ROUNDEVEN = 90,
104 G_READCYCLECOUNTER = 91,
105 G_READSTEADYCOUNTER = 92,
106 G_LOAD = 93,
107 G_SEXTLOAD = 94,
108 G_ZEXTLOAD = 95,
109 G_INDEXED_LOAD = 96,
110 G_INDEXED_SEXTLOAD = 97,
111 G_INDEXED_ZEXTLOAD = 98,
112 G_STORE = 99,
113 G_INDEXED_STORE = 100,
114 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 101,
115 G_ATOMIC_CMPXCHG = 102,
116 G_ATOMICRMW_XCHG = 103,
117 G_ATOMICRMW_ADD = 104,
118 G_ATOMICRMW_SUB = 105,
119 G_ATOMICRMW_AND = 106,
120 G_ATOMICRMW_NAND = 107,
121 G_ATOMICRMW_OR = 108,
122 G_ATOMICRMW_XOR = 109,
123 G_ATOMICRMW_MAX = 110,
124 G_ATOMICRMW_MIN = 111,
125 G_ATOMICRMW_UMAX = 112,
126 G_ATOMICRMW_UMIN = 113,
127 G_ATOMICRMW_FADD = 114,
128 G_ATOMICRMW_FSUB = 115,
129 G_ATOMICRMW_FMAX = 116,
130 G_ATOMICRMW_FMIN = 117,
131 G_ATOMICRMW_FMAXIMUM = 118,
132 G_ATOMICRMW_FMINIMUM = 119,
133 G_ATOMICRMW_UINC_WRAP = 120,
134 G_ATOMICRMW_UDEC_WRAP = 121,
135 G_ATOMICRMW_USUB_COND = 122,
136 G_ATOMICRMW_USUB_SAT = 123,
137 G_FENCE = 124,
138 G_PREFETCH = 125,
139 G_BRCOND = 126,
140 G_BRINDIRECT = 127,
141 G_INVOKE_REGION_START = 128,
142 G_INTRINSIC = 129,
143 G_INTRINSIC_W_SIDE_EFFECTS = 130,
144 G_INTRINSIC_CONVERGENT = 131,
145 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 132,
146 G_ANYEXT = 133,
147 G_TRUNC = 134,
148 G_CONSTANT = 135,
149 G_FCONSTANT = 136,
150 G_VASTART = 137,
151 G_VAARG = 138,
152 G_SEXT = 139,
153 G_SEXT_INREG = 140,
154 G_ZEXT = 141,
155 G_SHL = 142,
156 G_LSHR = 143,
157 G_ASHR = 144,
158 G_FSHL = 145,
159 G_FSHR = 146,
160 G_ROTR = 147,
161 G_ROTL = 148,
162 G_ICMP = 149,
163 G_FCMP = 150,
164 G_SCMP = 151,
165 G_UCMP = 152,
166 G_SELECT = 153,
167 G_UADDO = 154,
168 G_UADDE = 155,
169 G_USUBO = 156,
170 G_USUBE = 157,
171 G_SADDO = 158,
172 G_SADDE = 159,
173 G_SSUBO = 160,
174 G_SSUBE = 161,
175 G_UMULO = 162,
176 G_SMULO = 163,
177 G_UMULH = 164,
178 G_SMULH = 165,
179 G_UADDSAT = 166,
180 G_SADDSAT = 167,
181 G_USUBSAT = 168,
182 G_SSUBSAT = 169,
183 G_USHLSAT = 170,
184 G_SSHLSAT = 171,
185 G_SMULFIX = 172,
186 G_UMULFIX = 173,
187 G_SMULFIXSAT = 174,
188 G_UMULFIXSAT = 175,
189 G_SDIVFIX = 176,
190 G_UDIVFIX = 177,
191 G_SDIVFIXSAT = 178,
192 G_UDIVFIXSAT = 179,
193 G_FADD = 180,
194 G_FSUB = 181,
195 G_FMUL = 182,
196 G_FMA = 183,
197 G_FMAD = 184,
198 G_FDIV = 185,
199 G_FREM = 186,
200 G_FPOW = 187,
201 G_FPOWI = 188,
202 G_FEXP = 189,
203 G_FEXP2 = 190,
204 G_FEXP10 = 191,
205 G_FLOG = 192,
206 G_FLOG2 = 193,
207 G_FLOG10 = 194,
208 G_FLDEXP = 195,
209 G_FFREXP = 196,
210 G_FNEG = 197,
211 G_FPEXT = 198,
212 G_FPTRUNC = 199,
213 G_FPTOSI = 200,
214 G_FPTOUI = 201,
215 G_SITOFP = 202,
216 G_UITOFP = 203,
217 G_FPTOSI_SAT = 204,
218 G_FPTOUI_SAT = 205,
219 G_FABS = 206,
220 G_FCOPYSIGN = 207,
221 G_IS_FPCLASS = 208,
222 G_FCANONICALIZE = 209,
223 G_FMINNUM = 210,
224 G_FMAXNUM = 211,
225 G_FMINNUM_IEEE = 212,
226 G_FMAXNUM_IEEE = 213,
227 G_FMINIMUM = 214,
228 G_FMAXIMUM = 215,
229 G_FMINIMUMNUM = 216,
230 G_FMAXIMUMNUM = 217,
231 G_GET_FPENV = 218,
232 G_SET_FPENV = 219,
233 G_RESET_FPENV = 220,
234 G_GET_FPMODE = 221,
235 G_SET_FPMODE = 222,
236 G_RESET_FPMODE = 223,
237 G_PTR_ADD = 224,
238 G_PTRMASK = 225,
239 G_SMIN = 226,
240 G_SMAX = 227,
241 G_UMIN = 228,
242 G_UMAX = 229,
243 G_ABS = 230,
244 G_LROUND = 231,
245 G_LLROUND = 232,
246 G_BR = 233,
247 G_BRJT = 234,
248 G_VSCALE = 235,
249 G_INSERT_SUBVECTOR = 236,
250 G_EXTRACT_SUBVECTOR = 237,
251 G_INSERT_VECTOR_ELT = 238,
252 G_EXTRACT_VECTOR_ELT = 239,
253 G_SHUFFLE_VECTOR = 240,
254 G_SPLAT_VECTOR = 241,
255 G_STEP_VECTOR = 242,
256 G_VECTOR_COMPRESS = 243,
257 G_CTTZ = 244,
258 G_CTTZ_ZERO_UNDEF = 245,
259 G_CTLZ = 246,
260 G_CTLZ_ZERO_UNDEF = 247,
261 G_CTPOP = 248,
262 G_BSWAP = 249,
263 G_BITREVERSE = 250,
264 G_FCEIL = 251,
265 G_FCOS = 252,
266 G_FSIN = 253,
267 G_FSINCOS = 254,
268 G_FTAN = 255,
269 G_FACOS = 256,
270 G_FASIN = 257,
271 G_FATAN = 258,
272 G_FATAN2 = 259,
273 G_FCOSH = 260,
274 G_FSINH = 261,
275 G_FTANH = 262,
276 G_FSQRT = 263,
277 G_FFLOOR = 264,
278 G_FRINT = 265,
279 G_FNEARBYINT = 266,
280 G_ADDRSPACE_CAST = 267,
281 G_BLOCK_ADDR = 268,
282 G_JUMP_TABLE = 269,
283 G_DYN_STACKALLOC = 270,
284 G_STACKSAVE = 271,
285 G_STACKRESTORE = 272,
286 G_STRICT_FADD = 273,
287 G_STRICT_FSUB = 274,
288 G_STRICT_FMUL = 275,
289 G_STRICT_FDIV = 276,
290 G_STRICT_FREM = 277,
291 G_STRICT_FMA = 278,
292 G_STRICT_FSQRT = 279,
293 G_STRICT_FLDEXP = 280,
294 G_READ_REGISTER = 281,
295 G_WRITE_REGISTER = 282,
296 G_MEMCPY = 283,
297 G_MEMCPY_INLINE = 284,
298 G_MEMMOVE = 285,
299 G_MEMSET = 286,
300 G_BZERO = 287,
301 G_TRAP = 288,
302 G_DEBUGTRAP = 289,
303 G_UBSANTRAP = 290,
304 G_VECREDUCE_SEQ_FADD = 291,
305 G_VECREDUCE_SEQ_FMUL = 292,
306 G_VECREDUCE_FADD = 293,
307 G_VECREDUCE_FMUL = 294,
308 G_VECREDUCE_FMAX = 295,
309 G_VECREDUCE_FMIN = 296,
310 G_VECREDUCE_FMAXIMUM = 297,
311 G_VECREDUCE_FMINIMUM = 298,
312 G_VECREDUCE_ADD = 299,
313 G_VECREDUCE_MUL = 300,
314 G_VECREDUCE_AND = 301,
315 G_VECREDUCE_OR = 302,
316 G_VECREDUCE_XOR = 303,
317 G_VECREDUCE_SMAX = 304,
318 G_VECREDUCE_SMIN = 305,
319 G_VECREDUCE_UMAX = 306,
320 G_VECREDUCE_UMIN = 307,
321 G_SBFX = 308,
322 G_UBFX = 309,
323 ASSIGN_TYPE = 310,
324 UNKNOWN_type = 311,
325 OpAccessChain = 312,
326 OpAliasDomainDeclINTEL = 313,
327 OpAliasScopeDeclINTEL = 314,
328 OpAliasScopeListDeclINTEL = 315,
329 OpAll = 316,
330 OpAny = 317,
331 OpArithmeticFenceEXT = 318,
332 OpArrayLength = 319,
333 OpAsmCallINTEL = 320,
334 OpAsmINTEL = 321,
335 OpAsmTargetINTEL = 322,
336 OpAssumeTrueKHR = 323,
337 OpAtomicAnd = 324,
338 OpAtomicCompareExchange = 325,
339 OpAtomicCompareExchangeWeak = 326,
340 OpAtomicExchange = 327,
341 OpAtomicFAddEXT = 328,
342 OpAtomicFMaxEXT = 329,
343 OpAtomicFMinEXT = 330,
344 OpAtomicFlagClear = 331,
345 OpAtomicFlagTestAndSet = 332,
346 OpAtomicIAdd = 333,
347 OpAtomicIDecrement = 334,
348 OpAtomicIIncrement = 335,
349 OpAtomicISub = 336,
350 OpAtomicLoad = 337,
351 OpAtomicOr = 338,
352 OpAtomicSMax = 339,
353 OpAtomicSMin = 340,
354 OpAtomicStore = 341,
355 OpAtomicUMax = 342,
356 OpAtomicUMin = 343,
357 OpAtomicXor = 344,
358 OpBitCount = 345,
359 OpBitFieldInsert = 346,
360 OpBitFieldSExtract = 347,
361 OpBitFieldUExtract = 348,
362 OpBitReverse = 349,
363 OpBitcast = 350,
364 OpBitwiseAndS = 351,
365 OpBitwiseAndV = 352,
366 OpBitwiseFunctionINTEL = 353,
367 OpBitwiseOrS = 354,
368 OpBitwiseOrV = 355,
369 OpBitwiseXorS = 356,
370 OpBitwiseXorV = 357,
371 OpBranch = 358,
372 OpBranchConditional = 359,
373 OpBuildNDRange = 360,
374 OpCapability = 361,
375 OpCaptureEventProfilingInfo = 362,
376 OpCompositeConstruct = 363,
377 OpCompositeConstructContinuedINTEL = 364,
378 OpCompositeExtract = 365,
379 OpCompositeInsert = 366,
380 OpConstantComposite = 367,
381 OpConstantCompositeContinuedINTEL = 368,
382 OpConstantF = 369,
383 OpConstantFalse = 370,
384 OpConstantFunctionPointerINTEL = 371,
385 OpConstantI = 372,
386 OpConstantNull = 373,
387 OpConstantSampler = 374,
388 OpConstantTrue = 375,
389 OpControlBarrier = 376,
390 OpControlBarrierArriveINTEL = 377,
391 OpControlBarrierWaitINTEL = 378,
392 OpConvertBF16ToFINTEL = 379,
393 OpConvertFToBF16INTEL = 380,
394 OpConvertFToS = 381,
395 OpConvertFToU = 382,
396 OpConvertHandleToImageINTEL = 383,
397 OpConvertHandleToSampledImageINTEL = 384,
398 OpConvertHandleToSamplerINTEL = 385,
399 OpConvertPtrToU = 386,
400 OpConvertSToF = 387,
401 OpConvertUToF = 388,
402 OpConvertUToPtr = 389,
403 OpCooperativeMatrixConstructCheckedINTEL = 390,
404 OpCooperativeMatrixGetElementCoordINTEL = 391,
405 OpCooperativeMatrixLengthKHR = 392,
406 OpCooperativeMatrixLoadCheckedINTEL = 393,
407 OpCooperativeMatrixLoadKHR = 394,
408 OpCooperativeMatrixMulAddKHR = 395,
409 OpCooperativeMatrixPrefetchINTEL = 396,
410 OpCooperativeMatrixStoreCheckedINTEL = 397,
411 OpCooperativeMatrixStoreKHR = 398,
412 OpCopyLogical = 399,
413 OpCopyMemory = 400,
414 OpCopyMemorySized = 401,
415 OpCopyObject = 402,
416 OpCreateUserEvent = 403,
417 OpCrossWorkgroupCastToPtrINTEL = 404,
418 OpDPdx = 405,
419 OpDPdxCoarse = 406,
420 OpDPdxFine = 407,
421 OpDPdy = 408,
422 OpDPdyCoarse = 409,
423 OpDPdyFine = 410,
424 OpDecorate = 411,
425 OpDecorateId = 412,
426 OpDecorateString = 413,
427 OpDemoteToHelperInvocation = 414,
428 OpDot = 415,
429 OpEmitStreamVertex = 416,
430 OpEmitVertex = 417,
431 OpEndPrimitive = 418,
432 OpEndStreamPrimitive = 419,
433 OpEnqueueKernel = 420,
434 OpEntryPoint = 421,
435 OpExecutionMode = 422,
436 OpExecutionModeId = 423,
437 OpExpectKHR = 424,
438 OpExtInst = 425,
439 OpExtInstImport = 426,
440 OpExtension = 427,
441 OpFAddS = 428,
442 OpFAddV = 429,
443 OpFConvert = 430,
444 OpFDivS = 431,
445 OpFDivV = 432,
446 OpFMod = 433,
447 OpFMulS = 434,
448 OpFMulV = 435,
449 OpFNegate = 436,
450 OpFNegateV = 437,
451 OpFOrdEqual = 438,
452 OpFOrdGreaterThan = 439,
453 OpFOrdGreaterThanEqual = 440,
454 OpFOrdLessThan = 441,
455 OpFOrdLessThanEqual = 442,
456 OpFOrdNotEqual = 443,
457 OpFRemS = 444,
458 OpFRemV = 445,
459 OpFSubS = 446,
460 OpFSubV = 447,
461 OpFUnordEqual = 448,
462 OpFUnordGreaterThan = 449,
463 OpFUnordGreaterThanEqual = 450,
464 OpFUnordLessThan = 451,
465 OpFUnordLessThanEqual = 452,
466 OpFUnordNotEqual = 453,
467 OpFunction = 454,
468 OpFunctionCall = 455,
469 OpFunctionEnd = 456,
470 OpFunctionParameter = 457,
471 OpFunctionPointerCallINTEL = 458,
472 OpFwidth = 459,
473 OpFwidthCoarse = 460,
474 OpFwidthFine = 461,
475 OpGenericCastToPtr = 462,
476 OpGenericCastToPtrExplicit = 463,
477 OpGenericPtrMemSemantics = 464,
478 OpGetDefaultQueue = 465,
479 OpGroupAll = 466,
480 OpGroupAny = 467,
481 OpGroupAsyncCopy = 468,
482 OpGroupBitwiseAndKHR = 469,
483 OpGroupBitwiseOrKHR = 470,
484 OpGroupBitwiseXorKHR = 471,
485 OpGroupBroadcast = 472,
486 OpGroupFAdd = 473,
487 OpGroupFMax = 474,
488 OpGroupFMin = 475,
489 OpGroupFMulKHR = 476,
490 OpGroupIAdd = 477,
491 OpGroupIMulKHR = 478,
492 OpGroupLogicalAndKHR = 479,
493 OpGroupLogicalOrKHR = 480,
494 OpGroupLogicalXorKHR = 481,
495 OpGroupNonUniformAll = 482,
496 OpGroupNonUniformAllEqual = 483,
497 OpGroupNonUniformAny = 484,
498 OpGroupNonUniformBallot = 485,
499 OpGroupNonUniformBallotBitCount = 486,
500 OpGroupNonUniformBallotBitExtract = 487,
501 OpGroupNonUniformBallotFindLSB = 488,
502 OpGroupNonUniformBallotFindMSB = 489,
503 OpGroupNonUniformBitwiseAnd = 490,
504 OpGroupNonUniformBitwiseOr = 491,
505 OpGroupNonUniformBitwiseXor = 492,
506 OpGroupNonUniformBroadcast = 493,
507 OpGroupNonUniformBroadcastFirst = 494,
508 OpGroupNonUniformElect = 495,
509 OpGroupNonUniformFAdd = 496,
510 OpGroupNonUniformFMax = 497,
511 OpGroupNonUniformFMin = 498,
512 OpGroupNonUniformFMul = 499,
513 OpGroupNonUniformIAdd = 500,
514 OpGroupNonUniformIMul = 501,
515 OpGroupNonUniformInverseBallot = 502,
516 OpGroupNonUniformLogicalAnd = 503,
517 OpGroupNonUniformLogicalOr = 504,
518 OpGroupNonUniformLogicalXor = 505,
519 OpGroupNonUniformRotateKHR = 506,
520 OpGroupNonUniformSMax = 507,
521 OpGroupNonUniformSMin = 508,
522 OpGroupNonUniformShuffle = 509,
523 OpGroupNonUniformShuffleDown = 510,
524 OpGroupNonUniformShuffleUp = 511,
525 OpGroupNonUniformShuffleXor = 512,
526 OpGroupNonUniformUMax = 513,
527 OpGroupNonUniformUMin = 514,
528 OpGroupSMax = 515,
529 OpGroupSMin = 516,
530 OpGroupUMax = 517,
531 OpGroupUMin = 518,
532 OpGroupWaitEvents = 519,
533 OpIAddCarryS = 520,
534 OpIAddCarryV = 521,
535 OpIAddS = 522,
536 OpIAddV = 523,
537 OpIEqual = 524,
538 OpIMulS = 525,
539 OpIMulV = 526,
540 OpINotEqual = 527,
541 OpISubBorrowS = 528,
542 OpISubBorrowV = 529,
543 OpISubS = 530,
544 OpISubV = 531,
545 OpImage = 532,
546 OpImageDrefGather = 533,
547 OpImageFetch = 534,
548 OpImageGather = 535,
549 OpImageQueryFormat = 536,
550 OpImageQueryLevels = 537,
551 OpImageQueryLod = 538,
552 OpImageQueryOrder = 539,
553 OpImageQuerySamples = 540,
554 OpImageQuerySize = 541,
555 OpImageQuerySizeLod = 542,
556 OpImageRead = 543,
557 OpImageSampleDrefExplicitLod = 544,
558 OpImageSampleDrefImplicitLod = 545,
559 OpImageSampleExplicitLod = 546,
560 OpImageSampleFootprintNV = 547,
561 OpImageSampleImplicitLod = 548,
562 OpImageSampleProjDrefExplicitLod = 549,
563 OpImageSampleProjDrefImplicitLod = 550,
564 OpImageSampleProjExplicitLod = 551,
565 OpImageSampleProjImplicitLod = 552,
566 OpImageSparseDrefGather = 553,
567 OpImageSparseFetch = 554,
568 OpImageSparseGather = 555,
569 OpImageSparseRead = 556,
570 OpImageSparseSampleDrefExplicitLod = 557,
571 OpImageSparseSampleDrefImplicitLod = 558,
572 OpImageSparseSampleExplicitLod = 559,
573 OpImageSparseSampleImplicitLod = 560,
574 OpImageSparseSampleProjDrefExplicitLod = 561,
575 OpImageSparseSampleProjDrefImplicitLod = 562,
576 OpImageSparseSampleProjExplicitLod = 563,
577 OpImageSparseSampleProjImplicitLod = 564,
578 OpImageSparseTexelsResident = 565,
579 OpImageTexelPointer = 566,
580 OpImageWrite = 567,
581 OpInBoundsAccessChain = 568,
582 OpInBoundsPtrAccessChain = 569,
583 OpIsFinite = 570,
584 OpIsInf = 571,
585 OpIsNan = 572,
586 OpIsNormal = 573,
587 OpIsValidEvent = 574,
588 OpKill = 575,
589 OpLabel = 576,
590 OpLessOrGreater = 577,
591 OpLifetimeStart = 578,
592 OpLifetimeStop = 579,
593 OpLine = 580,
594 OpLoad = 581,
595 OpLogicalAnd = 582,
596 OpLogicalEqual = 583,
597 OpLogicalNot = 584,
598 OpLogicalNotEqual = 585,
599 OpLogicalOr = 586,
600 OpLoopMerge = 587,
601 OpMatrixTimesMatrix = 588,
602 OpMatrixTimesScalar = 589,
603 OpMatrixTimesVector = 590,
604 OpMemberDecorate = 591,
605 OpMemberDecorateString = 592,
606 OpMemberName = 593,
607 OpMemoryBarrier = 594,
608 OpMemoryModel = 595,
609 OpMemoryNamedBarrier = 596,
610 OpModuleProcessed = 597,
611 OpName = 598,
612 OpNamedBarrierInitialize = 599,
613 OpNoLine = 600,
614 OpNop = 601,
615 OpNot = 602,
616 OpOrdered = 603,
617 OpOuterProduct = 604,
618 OpPhi = 605,
619 OpPtrAccessChain = 606,
620 OpPtrCastToCrossWorkgroupINTEL = 607,
621 OpPtrCastToGeneric = 608,
622 OpPtrDiff = 609,
623 OpPtrEqual = 610,
624 OpPtrNotEqual = 611,
625 OpQuantizeToF16 = 612,
626 OpReadClockKHR = 613,
627 OpReleaseEvent = 614,
628 OpRestoreMemoryINTEL = 615,
629 OpRetainEvent = 616,
630 OpReturn = 617,
631 OpReturnValue = 618,
632 OpSConvert = 619,
633 OpSDivS = 620,
634 OpSDivV = 621,
635 OpSDot = 622,
636 OpSDotAccSat = 623,
637 OpSGreaterThan = 624,
638 OpSGreaterThanEqual = 625,
639 OpSLessThan = 626,
640 OpSLessThanEqual = 627,
641 OpSMod = 628,
642 OpSMulExtended = 629,
643 OpSNegate = 630,
644 OpSRemS = 631,
645 OpSRemV = 632,
646 OpSUDot = 633,
647 OpSUDotAccSat = 634,
648 OpSampledImage = 635,
649 OpSatConvertSToU = 636,
650 OpSatConvertUToS = 637,
651 OpSaveMemoryINTEL = 638,
652 OpSelectSFSCond = 639,
653 OpSelectSFVCond = 640,
654 OpSelectSISCond = 641,
655 OpSelectSIVCond = 642,
656 OpSelectSPSCond = 643,
657 OpSelectSPVCond = 644,
658 OpSelectVFSCond = 645,
659 OpSelectVFVCond = 646,
660 OpSelectVISCond = 647,
661 OpSelectVIVCond = 648,
662 OpSelectVPSCond = 649,
663 OpSelectVPVCond = 650,
664 OpSelectionMerge = 651,
665 OpSetUserEventStatus = 652,
666 OpShiftLeftLogicalS = 653,
667 OpShiftLeftLogicalV = 654,
668 OpShiftRightArithmeticS = 655,
669 OpShiftRightArithmeticV = 656,
670 OpShiftRightLogicalS = 657,
671 OpShiftRightLogicalV = 658,
672 OpSignBitSet = 659,
673 OpSizeOf = 660,
674 OpSource = 661,
675 OpSourceContinued = 662,
676 OpSourceExtension = 663,
677 OpSpecConstant = 664,
678 OpSpecConstantComposite = 665,
679 OpSpecConstantCompositeContinuedINTEL = 666,
680 OpSpecConstantFalse = 667,
681 OpSpecConstantOp = 668,
682 OpSpecConstantTrue = 669,
683 OpStore = 670,
684 OpStrictFAddS = 671,
685 OpStrictFAddV = 672,
686 OpStrictFDivS = 673,
687 OpStrictFDivV = 674,
688 OpStrictFMulS = 675,
689 OpStrictFMulV = 676,
690 OpStrictFRemS = 677,
691 OpStrictFRemV = 678,
692 OpStrictFSubS = 679,
693 OpStrictFSubV = 680,
694 OpString = 681,
695 OpSubgroup2DBlockLoadINTEL = 682,
696 OpSubgroup2DBlockLoadTransformINTEL = 683,
697 OpSubgroup2DBlockLoadTransposeINTEL = 684,
698 OpSubgroup2DBlockPrefetchINTEL = 685,
699 OpSubgroup2DBlockStoreINTEL = 686,
700 OpSubgroupBlockReadINTEL = 687,
701 OpSubgroupBlockWriteINTEL = 688,
702 OpSubgroupImageBlockReadINTEL = 689,
703 OpSubgroupImageBlockWriteINTEL = 690,
704 OpSubgroupImageMediaBlockReadINTEL = 691,
705 OpSubgroupImageMediaBlockWriteINTEL = 692,
706 OpSubgroupMatrixMultiplyAccumulateINTEL = 693,
707 OpSubgroupShuffleDownINTEL = 694,
708 OpSubgroupShuffleINTEL = 695,
709 OpSubgroupShuffleUpINTEL = 696,
710 OpSubgroupShuffleXorINTEL = 697,
711 OpSwitch = 698,
712 OpTranspose = 699,
713 OpTypeAccelerationStructureNV = 700,
714 OpTypeArray = 701,
715 OpTypeBool = 702,
716 OpTypeCooperativeMatrixKHR = 703,
717 OpTypeCooperativeMatrixNV = 704,
718 OpTypeDeviceEvent = 705,
719 OpTypeEvent = 706,
720 OpTypeFloat = 707,
721 OpTypeForwardPointer = 708,
722 OpTypeFunction = 709,
723 OpTypeImage = 710,
724 OpTypeInt = 711,
725 OpTypeMatrix = 712,
726 OpTypeNamedBarrier = 713,
727 OpTypeOpaque = 714,
728 OpTypePipe = 715,
729 OpTypePipeStorage = 716,
730 OpTypePointer = 717,
731 OpTypeQueue = 718,
732 OpTypeReserveId = 719,
733 OpTypeRuntimeArray = 720,
734 OpTypeSampledImage = 721,
735 OpTypeSampler = 722,
736 OpTypeStruct = 723,
737 OpTypeStructContinuedINTEL = 724,
738 OpTypeVector = 725,
739 OpTypeVoid = 726,
740 OpUConvert = 727,
741 OpUDivS = 728,
742 OpUDivV = 729,
743 OpUDot = 730,
744 OpUDotAccSat = 731,
745 OpUGreaterThan = 732,
746 OpUGreaterThanEqual = 733,
747 OpULessThan = 734,
748 OpULessThanEqual = 735,
749 OpUModS = 736,
750 OpUModV = 737,
751 OpUMulExtended = 738,
752 OpUndef = 739,
753 OpUnordered = 740,
754 OpUnreachable = 741,
755 OpVariable = 742,
756 OpVariableLengthArrayINTEL = 743,
757 OpVectorExtractDynamic = 744,
758 OpVectorInsertDynamic = 745,
759 OpVectorShuffle = 746,
760 OpVectorTimesMatrix = 747,
761 OpVectorTimesScalar = 748,
762 INSTRUCTION_LIST_END = 749
763 };
764
765} // end namespace llvm::SPIRV
766#endif // GET_INSTRINFO_ENUM
767
768#ifdef GET_INSTRINFO_SCHED_ENUM
769#undef GET_INSTRINFO_SCHED_ENUM
770namespace llvm::SPIRV::Sched {
771
772 enum {
773 NoInstrModel = 0,
774 SCHED_LIST_END = 1
775 };
776} // end namespace llvm::SPIRV::Sched
777#endif // GET_INSTRINFO_SCHED_ENUM
778
779#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
780namespace llvm {
781
782struct SPIRVInstrTable {
783 MCInstrDesc Insts[749];
784 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
785 MCOperandInfo OperandInfo[467];
786 static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps");
787 MCPhysReg ImplicitOps[1];
788};
789
790} // end namespace llvm
791#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
792
793#ifdef GET_INSTRINFO_MC_DESC
794#undef GET_INSTRINFO_MC_DESC
795namespace llvm {
796
797static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0);
798static constexpr unsigned SPIRVImpOpBase = sizeof SPIRVInstrTable::OperandInfo / (sizeof(MCPhysReg));
799
800extern const SPIRVInstrTable SPIRVDescs = {
801 {
802 { 748, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #748 = OpVectorTimesScalar
803 { 747, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #747 = OpVectorTimesMatrix
804 { 746, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #746 = OpVectorShuffle
805 { 745, 5, 1, 0, 0, 0, 0, 192, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #745 = OpVectorInsertDynamic
806 { 744, 4, 1, 0, 0, 0, 0, 463, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #744 = OpVectorExtractDynamic
807 { 743, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #743 = OpVariableLengthArrayINTEL
808 { 742, 3, 1, 0, 0, 0, 0, 460, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #742 = OpVariable
809 { 741, 0, 0, 0, 0, 0, 0, 1, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #741 = OpUnreachable
810 { 740, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #740 = OpUnordered
811 { 739, 2, 1, 0, 0, 0, 0, 212, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #739 = OpUndef
812 { 738, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #738 = OpUMulExtended
813 { 737, 4, 1, 0, 0, 0, 0, 205, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #737 = OpUModV
814 { 736, 4, 1, 0, 0, 0, 0, 201, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #736 = OpUModS
815 { 735, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #735 = OpULessThanEqual
816 { 734, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #734 = OpULessThan
817 { 733, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #733 = OpUGreaterThanEqual
818 { 732, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #732 = OpUGreaterThan
819 { 731, 5, 1, 0, 0, 0, 0, 192, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #731 = OpUDotAccSat
820 { 730, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #730 = OpUDot
821 { 729, 4, 1, 0, 0, 0, 0, 205, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #729 = OpUDivV
822 { 728, 4, 1, 0, 0, 0, 0, 201, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #728 = OpUDivS
823 { 727, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #727 = OpUConvert
824 { 726, 1, 1, 0, 0, 0, 0, 424, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #726 = OpTypeVoid
825 { 725, 3, 1, 0, 0, 0, 0, 454, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #725 = OpTypeVector
826 { 724, 0, 0, 0, 0, 0, 0, 1, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #724 = OpTypeStructContinuedINTEL
827 { 723, 1, 1, 0, 0, 0, 0, 424, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #723 = OpTypeStruct
828 { 722, 1, 1, 0, 0, 0, 0, 424, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #722 = OpTypeSampler
829 { 721, 2, 1, 0, 0, 0, 0, 441, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #721 = OpTypeSampledImage
830 { 720, 2, 1, 0, 0, 0, 0, 441, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #720 = OpTypeRuntimeArray
831 { 719, 1, 1, 0, 0, 0, 0, 424, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #719 = OpTypeReserveId
832 { 718, 1, 1, 0, 0, 0, 0, 424, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #718 = OpTypeQueue
833 { 717, 3, 1, 0, 0, 0, 0, 457, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #717 = OpTypePointer
834 { 716, 1, 1, 0, 0, 0, 0, 424, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #716 = OpTypePipeStorage
835 { 715, 2, 1, 0, 0, 0, 0, 439, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #715 = OpTypePipe
836 { 714, 2, 1, 0, 0, 0, 0, 439, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #714 = OpTypeOpaque
837 { 713, 1, 1, 0, 0, 0, 0, 424, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #713 = OpTypeNamedBarrier
838 { 712, 3, 1, 0, 0, 0, 0, 454, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #712 = OpTypeMatrix
839 { 711, 3, 1, 0, 0, 0, 0, 451, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #711 = OpTypeInt
840 { 710, 8, 1, 0, 0, 0, 0, 443, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #710 = OpTypeImage
841 { 709, 2, 1, 0, 0, 0, 0, 441, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #709 = OpTypeFunction
842 { 708, 2, 0, 0, 0, 0, 0, 439, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #708 = OpTypeForwardPointer
843 { 707, 2, 1, 0, 0, 0, 0, 155, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #707 = OpTypeFloat
844 { 706, 1, 1, 0, 0, 0, 0, 424, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #706 = OpTypeEvent
845 { 705, 1, 1, 0, 0, 0, 0, 424, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #705 = OpTypeDeviceEvent
846 { 704, 5, 1, 0, 0, 0, 0, 434, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #704 = OpTypeCooperativeMatrixNV
847 { 703, 6, 1, 0, 0, 0, 0, 428, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #703 = OpTypeCooperativeMatrixKHR
848 { 702, 1, 1, 0, 0, 0, 0, 424, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #702 = OpTypeBool
849 { 701, 3, 1, 0, 0, 0, 0, 425, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #701 = OpTypeArray
850 { 700, 1, 1, 0, 0, 0, 0, 424, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #700 = OpTypeAccelerationStructureNV
851 { 699, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #699 = OpTranspose
852 { 698, 2, 0, 0, 0, 0, 0, 161, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #698 = OpSwitch
853 { 697, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #697 = OpSubgroupShuffleXorINTEL
854 { 696, 5, 1, 0, 0, 0, 0, 192, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #696 = OpSubgroupShuffleUpINTEL
855 { 695, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #695 = OpSubgroupShuffleINTEL
856 { 694, 5, 1, 0, 0, 0, 0, 192, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #694 = OpSubgroupShuffleDownINTEL
857 { 693, 6, 1, 0, 0, 0, 0, 175, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #693 = OpSubgroupMatrixMultiplyAccumulateINTEL
858 { 692, 5, 0, 0, 0, 0, 0, 419, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #692 = OpSubgroupImageMediaBlockWriteINTEL
859 { 691, 6, 1, 0, 0, 0, 0, 175, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #691 = OpSubgroupImageMediaBlockReadINTEL
860 { 690, 3, 0, 0, 0, 0, 0, 189, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #690 = OpSubgroupImageBlockWriteINTEL
861 { 689, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #689 = OpSubgroupImageBlockReadINTEL
862 { 688, 2, 0, 0, 0, 0, 0, 161, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #688 = OpSubgroupBlockWriteINTEL
863 { 687, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #687 = OpSubgroupBlockReadINTEL
864 { 686, 10, 0, 0, 0, 0, 0, 400, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #686 = OpSubgroup2DBlockStoreINTEL
865 { 685, 9, 0, 0, 0, 0, 0, 410, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #685 = OpSubgroup2DBlockPrefetchINTEL
866 { 684, 10, 0, 0, 0, 0, 0, 400, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #684 = OpSubgroup2DBlockLoadTransposeINTEL
867 { 683, 10, 0, 0, 0, 0, 0, 400, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #683 = OpSubgroup2DBlockLoadTransformINTEL
868 { 682, 10, 0, 0, 0, 0, 0, 400, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #682 = OpSubgroup2DBlockLoadINTEL
869 { 681, 2, 1, 0, 0, 0, 0, 173, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #681 = OpString
870 { 680, 4, 1, 0, 0, 0, 0, 278, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #680 = OpStrictFSubV
871 { 679, 4, 1, 0, 0, 0, 0, 274, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #679 = OpStrictFSubS
872 { 678, 4, 1, 0, 0, 0, 0, 278, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #678 = OpStrictFRemV
873 { 677, 4, 1, 0, 0, 0, 0, 274, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #677 = OpStrictFRemS
874 { 676, 4, 1, 0, 0, 0, 0, 278, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #676 = OpStrictFMulV
875 { 675, 4, 1, 0, 0, 0, 0, 274, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #675 = OpStrictFMulS
876 { 674, 4, 1, 0, 0, 0, 0, 278, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #674 = OpStrictFDivV
877 { 673, 4, 1, 0, 0, 0, 0, 274, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #673 = OpStrictFDivS
878 { 672, 4, 1, 0, 0, 0, 0, 278, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #672 = OpStrictFAddV
879 { 671, 4, 1, 0, 0, 0, 0, 274, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #671 = OpStrictFAddS
880 { 670, 2, 0, 0, 0, 0, 0, 161, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #670 = OpStore
881 { 669, 2, 1, 0, 0, 0, 0, 212, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #669 = OpSpecConstantTrue
882 { 668, 4, 1, 0, 0, 0, 0, 396, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #668 = OpSpecConstantOp
883 { 667, 2, 1, 0, 0, 0, 0, 212, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #667 = OpSpecConstantFalse
884 { 666, 0, 0, 0, 0, 0, 0, 1, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #666 = OpSpecConstantCompositeContinuedINTEL
885 { 665, 2, 1, 0, 0, 0, 0, 212, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #665 = OpSpecConstantComposite
886 { 664, 3, 1, 0, 0, 0, 0, 393, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #664 = OpSpecConstant
887 { 663, 1, 0, 0, 0, 0, 0, 0, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #663 = OpSourceExtension
888 { 662, 1, 0, 0, 0, 0, 0, 0, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #662 = OpSourceContinued
889 { 661, 2, 0, 0, 0, 0, 0, 391, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #661 = OpSource
890 { 660, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #660 = OpSizeOf
891 { 659, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #659 = OpSignBitSet
892 { 658, 4, 1, 0, 0, 0, 0, 205, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #658 = OpShiftRightLogicalV
893 { 657, 4, 1, 0, 0, 0, 0, 201, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #657 = OpShiftRightLogicalS
894 { 656, 4, 1, 0, 0, 0, 0, 205, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #656 = OpShiftRightArithmeticV
895 { 655, 4, 1, 0, 0, 0, 0, 201, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #655 = OpShiftRightArithmeticS
896 { 654, 4, 1, 0, 0, 0, 0, 205, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #654 = OpShiftLeftLogicalV
897 { 653, 4, 1, 0, 0, 0, 0, 201, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #653 = OpShiftLeftLogicalS
898 { 652, 2, 0, 0, 0, 0, 0, 161, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #652 = OpSetUserEventStatus
899 { 651, 2, 0, 0, 0, 0, 0, 13, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #651 = OpSelectionMerge
900 { 650, 5, 1, 0, 0, 0, 0, 386, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #650 = OpSelectVPVCond
901 { 649, 5, 1, 0, 0, 0, 0, 381, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #649 = OpSelectVPSCond
902 { 648, 5, 1, 0, 0, 0, 0, 376, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #648 = OpSelectVIVCond
903 { 647, 5, 1, 0, 0, 0, 0, 371, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #647 = OpSelectVISCond
904 { 646, 5, 1, 0, 0, 0, 0, 366, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #646 = OpSelectVFVCond
905 { 645, 5, 1, 0, 0, 0, 0, 361, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #645 = OpSelectVFSCond
906 { 644, 5, 1, 0, 0, 0, 0, 356, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #644 = OpSelectSPVCond
907 { 643, 5, 1, 0, 0, 0, 0, 351, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #643 = OpSelectSPSCond
908 { 642, 5, 1, 0, 0, 0, 0, 346, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #642 = OpSelectSIVCond
909 { 641, 5, 1, 0, 0, 0, 0, 341, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #641 = OpSelectSISCond
910 { 640, 5, 1, 0, 0, 0, 0, 336, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #640 = OpSelectSFVCond
911 { 639, 5, 1, 0, 0, 0, 0, 331, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #639 = OpSelectSFSCond
912 { 638, 2, 1, 0, 0, 0, 0, 212, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #638 = OpSaveMemoryINTEL
913 { 637, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #637 = OpSatConvertUToS
914 { 636, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #636 = OpSatConvertSToU
915 { 635, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #635 = OpSampledImage
916 { 634, 5, 1, 0, 0, 0, 0, 192, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #634 = OpSUDotAccSat
917 { 633, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #633 = OpSUDot
918 { 632, 4, 1, 0, 0, 0, 0, 205, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #632 = OpSRemV
919 { 631, 4, 1, 0, 0, 0, 0, 201, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #631 = OpSRemS
920 { 630, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #630 = OpSNegate
921 { 629, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #629 = OpSMulExtended
922 { 628, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #628 = OpSMod
923 { 627, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #627 = OpSLessThanEqual
924 { 626, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #626 = OpSLessThan
925 { 625, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #625 = OpSGreaterThanEqual
926 { 624, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #624 = OpSGreaterThan
927 { 623, 5, 1, 0, 0, 0, 0, 192, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #623 = OpSDotAccSat
928 { 622, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #622 = OpSDot
929 { 621, 4, 1, 0, 0, 0, 0, 205, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #621 = OpSDivV
930 { 620, 4, 1, 0, 0, 0, 0, 201, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #620 = OpSDivS
931 { 619, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #619 = OpSConvert
932 { 618, 1, 0, 0, 0, 0, 0, 160, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #618 = OpReturnValue
933 { 617, 0, 0, 0, 0, 0, 0, 1, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #617 = OpReturn
934 { 616, 1, 0, 0, 0, 0, 0, 160, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #616 = OpRetainEvent
935 { 615, 1, 0, 0, 0, 0, 0, 160, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #615 = OpRestoreMemoryINTEL
936 { 614, 1, 0, 0, 0, 0, 0, 160, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #614 = OpReleaseEvent
937 { 613, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #613 = OpReadClockKHR
938 { 612, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #612 = OpQuantizeToF16
939 { 611, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #611 = OpPtrNotEqual
940 { 610, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #610 = OpPtrEqual
941 { 609, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #609 = OpPtrDiff
942 { 608, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #608 = OpPtrCastToGeneric
943 { 607, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #607 = OpPtrCastToCrossWorkgroupINTEL
944 { 606, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #606 = OpPtrAccessChain
945 { 605, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #605 = OpPhi
946 { 604, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #604 = OpOuterProduct
947 { 603, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #603 = OpOrdered
948 { 602, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #602 = OpNot
949 { 601, 0, 0, 0, 0, 0, 0, 1, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #601 = OpNop
950 { 600, 0, 0, 0, 0, 0, 0, 1, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #600 = OpNoLine
951 { 599, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #599 = OpNamedBarrierInitialize
952 { 598, 2, 0, 0, 0, 0, 0, 250, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #598 = OpName
953 { 597, 1, 0, 0, 0, 0, 0, 0, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #597 = OpModuleProcessed
954 { 596, 3, 0, 0, 0, 0, 0, 189, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #596 = OpMemoryNamedBarrier
955 { 595, 2, 0, 0, 0, 0, 0, 13, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #595 = OpMemoryModel
956 { 594, 2, 0, 0, 0, 0, 0, 161, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #594 = OpMemoryBarrier
957 { 593, 3, 0, 0, 0, 0, 0, 324, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #593 = OpMemberName
958 { 592, 4, 0, 0, 0, 0, 0, 327, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #592 = OpMemberDecorateString
959 { 591, 3, 0, 0, 0, 0, 0, 324, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #591 = OpMemberDecorate
960 { 590, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #590 = OpMatrixTimesVector
961 { 589, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #589 = OpMatrixTimesScalar
962 { 588, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #588 = OpMatrixTimesMatrix
963 { 587, 3, 0, 0, 0, 0, 0, 321, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #587 = OpLoopMerge
964 { 586, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #586 = OpLogicalOr
965 { 585, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #585 = OpLogicalNotEqual
966 { 584, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #584 = OpLogicalNot
967 { 583, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #583 = OpLogicalEqual
968 { 582, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #582 = OpLogicalAnd
969 { 581, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #581 = OpLoad
970 { 580, 3, 0, 0, 0, 0, 0, 318, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #580 = OpLine
971 { 579, 2, 0, 0, 0, 0, 0, 316, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #579 = OpLifetimeStop
972 { 578, 2, 0, 0, 0, 0, 0, 316, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #578 = OpLifetimeStart
973 { 577, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #577 = OpLessOrGreater
974 { 576, 1, 1, 0, 0, 0, 0, 160, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #576 = OpLabel
975 { 575, 0, 0, 0, 0, 0, 0, 1, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #575 = OpKill
976 { 574, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #574 = OpIsValidEvent
977 { 573, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #573 = OpIsNormal
978 { 572, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #572 = OpIsNan
979 { 571, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #571 = OpIsInf
980 { 570, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #570 = OpIsFinite
981 { 569, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #569 = OpInBoundsPtrAccessChain
982 { 568, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #568 = OpInBoundsAccessChain
983 { 567, 3, 0, 0, 0, 0, 0, 189, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #567 = OpImageWrite
984 { 566, 5, 1, 0, 0, 0, 0, 192, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #566 = OpImageTexelPointer
985 { 565, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #565 = OpImageSparseTexelsResident
986 { 564, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #564 = OpImageSparseSampleProjImplicitLod
987 { 563, 7, 1, 0, 0, 0, 0, 303, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #563 = OpImageSparseSampleProjExplicitLod
988 { 562, 5, 1, 0, 0, 0, 0, 192, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #562 = OpImageSparseSampleProjDrefImplicitLod
989 { 561, 7, 1, 0, 0, 0, 0, 303, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #561 = OpImageSparseSampleProjDrefExplicitLod
990 { 560, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #560 = OpImageSparseSampleImplicitLod
991 { 559, 6, 1, 0, 0, 0, 0, 310, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #559 = OpImageSparseSampleExplicitLod
992 { 558, 5, 1, 0, 0, 0, 0, 192, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #558 = OpImageSparseSampleDrefImplicitLod
993 { 557, 7, 1, 0, 0, 0, 0, 303, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #557 = OpImageSparseSampleDrefExplicitLod
994 { 556, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #556 = OpImageSparseRead
995 { 555, 5, 1, 0, 0, 0, 0, 192, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #555 = OpImageSparseGather
996 { 554, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #554 = OpImageSparseFetch
997 { 553, 5, 1, 0, 0, 0, 0, 192, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #553 = OpImageSparseDrefGather
998 { 552, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #552 = OpImageSampleProjImplicitLod
999 { 551, 7, 1, 0, 0, 0, 0, 303, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #551 = OpImageSampleProjExplicitLod
1000 { 550, 5, 1, 0, 0, 0, 0, 192, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #550 = OpImageSampleProjDrefImplicitLod
1001 { 549, 7, 1, 0, 0, 0, 0, 303, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #549 = OpImageSampleProjDrefExplicitLod
1002 { 548, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #548 = OpImageSampleImplicitLod
1003 { 547, 6, 1, 0, 0, 0, 0, 175, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #547 = OpImageSampleFootprintNV
1004 { 546, 6, 1, 0, 0, 0, 0, 310, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #546 = OpImageSampleExplicitLod
1005 { 545, 5, 1, 0, 0, 0, 0, 192, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #545 = OpImageSampleDrefImplicitLod
1006 { 544, 7, 1, 0, 0, 0, 0, 303, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #544 = OpImageSampleDrefExplicitLod
1007 { 543, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #543 = OpImageRead
1008 { 542, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #542 = OpImageQuerySizeLod
1009 { 541, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #541 = OpImageQuerySize
1010 { 540, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #540 = OpImageQuerySamples
1011 { 539, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #539 = OpImageQueryOrder
1012 { 538, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #538 = OpImageQueryLod
1013 { 537, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #537 = OpImageQueryLevels
1014 { 536, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #536 = OpImageQueryFormat
1015 { 535, 5, 1, 0, 0, 0, 0, 192, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #535 = OpImageGather
1016 { 534, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #534 = OpImageFetch
1017 { 533, 5, 1, 0, 0, 0, 0, 192, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #533 = OpImageDrefGather
1018 { 532, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #532 = OpImage
1019 { 531, 4, 1, 0, 0, 0, 0, 205, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #531 = OpISubV
1020 { 530, 4, 1, 0, 0, 0, 0, 201, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #530 = OpISubS
1021 { 529, 4, 1, 0, 0, 0, 0, 205, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #529 = OpISubBorrowV
1022 { 528, 4, 1, 0, 0, 0, 0, 201, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #528 = OpISubBorrowS
1023 { 527, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #527 = OpINotEqual
1024 { 526, 4, 1, 0, 0, 0, 0, 205, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #526 = OpIMulV
1025 { 525, 4, 1, 0, 0, 0, 0, 201, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #525 = OpIMulS
1026 { 524, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #524 = OpIEqual
1027 { 523, 4, 1, 0, 0, 0, 0, 205, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #523 = OpIAddV
1028 { 522, 4, 1, 0, 0, 0, 0, 201, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #522 = OpIAddS
1029 { 521, 4, 1, 0, 0, 0, 0, 205, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #521 = OpIAddCarryV
1030 { 520, 4, 1, 0, 0, 0, 0, 201, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #520 = OpIAddCarryS
1031 { 519, 3, 0, 0, 0, 0, 0, 189, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #519 = OpGroupWaitEvents
1032 { 518, 5, 1, 0, 0, 0, 0, 298, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #518 = OpGroupUMin
1033 { 517, 5, 1, 0, 0, 0, 0, 298, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #517 = OpGroupUMax
1034 { 516, 5, 1, 0, 0, 0, 0, 298, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #516 = OpGroupSMin
1035 { 515, 5, 1, 0, 0, 0, 0, 298, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #515 = OpGroupSMax
1036 { 514, 5, 1, 0, 0, 0, 0, 298, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #514 = OpGroupNonUniformUMin
1037 { 513, 5, 1, 0, 0, 0, 0, 298, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #513 = OpGroupNonUniformUMax
1038 { 512, 5, 1, 0, 0, 0, 0, 192, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #512 = OpGroupNonUniformShuffleXor
1039 { 511, 5, 1, 0, 0, 0, 0, 192, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #511 = OpGroupNonUniformShuffleUp
1040 { 510, 5, 1, 0, 0, 0, 0, 192, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #510 = OpGroupNonUniformShuffleDown
1041 { 509, 5, 1, 0, 0, 0, 0, 192, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #509 = OpGroupNonUniformShuffle
1042 { 508, 5, 1, 0, 0, 0, 0, 298, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #508 = OpGroupNonUniformSMin
1043 { 507, 5, 1, 0, 0, 0, 0, 298, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #507 = OpGroupNonUniformSMax
1044 { 506, 5, 1, 0, 0, 0, 0, 192, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #506 = OpGroupNonUniformRotateKHR
1045 { 505, 5, 1, 0, 0, 0, 0, 298, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #505 = OpGroupNonUniformLogicalXor
1046 { 504, 5, 1, 0, 0, 0, 0, 298, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #504 = OpGroupNonUniformLogicalOr
1047 { 503, 5, 1, 0, 0, 0, 0, 298, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #503 = OpGroupNonUniformLogicalAnd
1048 { 502, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #502 = OpGroupNonUniformInverseBallot
1049 { 501, 5, 1, 0, 0, 0, 0, 298, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #501 = OpGroupNonUniformIMul
1050 { 500, 5, 1, 0, 0, 0, 0, 298, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #500 = OpGroupNonUniformIAdd
1051 { 499, 5, 1, 0, 0, 0, 0, 298, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #499 = OpGroupNonUniformFMul
1052 { 498, 5, 1, 0, 0, 0, 0, 298, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #498 = OpGroupNonUniformFMin
1053 { 497, 5, 1, 0, 0, 0, 0, 298, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #497 = OpGroupNonUniformFMax
1054 { 496, 5, 1, 0, 0, 0, 0, 298, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #496 = OpGroupNonUniformFAdd
1055 { 495, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #495 = OpGroupNonUniformElect
1056 { 494, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #494 = OpGroupNonUniformBroadcastFirst
1057 { 493, 5, 1, 0, 0, 0, 0, 192, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #493 = OpGroupNonUniformBroadcast
1058 { 492, 5, 1, 0, 0, 0, 0, 298, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #492 = OpGroupNonUniformBitwiseXor
1059 { 491, 5, 1, 0, 0, 0, 0, 298, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #491 = OpGroupNonUniformBitwiseOr
1060 { 490, 5, 1, 0, 0, 0, 0, 298, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #490 = OpGroupNonUniformBitwiseAnd
1061 { 489, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #489 = OpGroupNonUniformBallotFindMSB
1062 { 488, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #488 = OpGroupNonUniformBallotFindLSB
1063 { 487, 5, 1, 0, 0, 0, 0, 192, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #487 = OpGroupNonUniformBallotBitExtract
1064 { 486, 5, 1, 0, 0, 0, 0, 298, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #486 = OpGroupNonUniformBallotBitCount
1065 { 485, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #485 = OpGroupNonUniformBallot
1066 { 484, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #484 = OpGroupNonUniformAny
1067 { 483, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #483 = OpGroupNonUniformAllEqual
1068 { 482, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #482 = OpGroupNonUniformAll
1069 { 481, 5, 1, 0, 0, 0, 0, 293, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #481 = OpGroupLogicalXorKHR
1070 { 480, 5, 1, 0, 0, 0, 0, 293, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #480 = OpGroupLogicalOrKHR
1071 { 479, 5, 1, 0, 0, 0, 0, 293, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #479 = OpGroupLogicalAndKHR
1072 { 478, 5, 1, 0, 0, 0, 0, 293, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #478 = OpGroupIMulKHR
1073 { 477, 5, 1, 0, 0, 0, 0, 298, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #477 = OpGroupIAdd
1074 { 476, 5, 1, 0, 0, 0, 0, 293, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #476 = OpGroupFMulKHR
1075 { 475, 5, 1, 0, 0, 0, 0, 298, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #475 = OpGroupFMin
1076 { 474, 5, 1, 0, 0, 0, 0, 298, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #474 = OpGroupFMax
1077 { 473, 5, 1, 0, 0, 0, 0, 298, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #473 = OpGroupFAdd
1078 { 472, 5, 1, 0, 0, 0, 0, 192, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #472 = OpGroupBroadcast
1079 { 471, 5, 1, 0, 0, 0, 0, 293, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #471 = OpGroupBitwiseXorKHR
1080 { 470, 5, 1, 0, 0, 0, 0, 293, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #470 = OpGroupBitwiseOrKHR
1081 { 469, 5, 1, 0, 0, 0, 0, 293, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #469 = OpGroupBitwiseAndKHR
1082 { 468, 8, 1, 0, 0, 0, 0, 181, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #468 = OpGroupAsyncCopy
1083 { 467, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #467 = OpGroupAny
1084 { 466, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #466 = OpGroupAll
1085 { 465, 2, 1, 0, 0, 0, 0, 212, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #465 = OpGetDefaultQueue
1086 { 464, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #464 = OpGenericPtrMemSemantics
1087 { 463, 4, 1, 0, 0, 0, 0, 289, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #463 = OpGenericCastToPtrExplicit
1088 { 462, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #462 = OpGenericCastToPtr
1089 { 461, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #461 = OpFwidthFine
1090 { 460, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #460 = OpFwidthCoarse
1091 { 459, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #459 = OpFwidth
1092 { 458, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #458 = OpFunctionPointerCallINTEL
1093 { 457, 2, 1, 0, 0, 0, 0, 212, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #457 = OpFunctionParameter
1094 { 456, 0, 0, 0, 0, 0, 0, 1, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #456 = OpFunctionEnd
1095 { 455, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #455 = OpFunctionCall
1096 { 454, 4, 1, 0, 0, 0, 0, 285, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #454 = OpFunction
1097 { 453, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #453 = OpFUnordNotEqual
1098 { 452, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #452 = OpFUnordLessThanEqual
1099 { 451, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #451 = OpFUnordLessThan
1100 { 450, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #450 = OpFUnordGreaterThanEqual
1101 { 449, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #449 = OpFUnordGreaterThan
1102 { 448, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #448 = OpFUnordEqual
1103 { 447, 4, 1, 0, 0, 0, 0, 278, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #447 = OpFSubV
1104 { 446, 4, 1, 0, 0, 0, 0, 274, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #446 = OpFSubS
1105 { 445, 4, 1, 0, 0, 0, 0, 278, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #445 = OpFRemV
1106 { 444, 4, 1, 0, 0, 0, 0, 274, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #444 = OpFRemS
1107 { 443, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #443 = OpFOrdNotEqual
1108 { 442, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #442 = OpFOrdLessThanEqual
1109 { 441, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #441 = OpFOrdLessThan
1110 { 440, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #440 = OpFOrdGreaterThanEqual
1111 { 439, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #439 = OpFOrdGreaterThan
1112 { 438, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #438 = OpFOrdEqual
1113 { 437, 3, 1, 0, 0, 0, 0, 282, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #437 = OpFNegateV
1114 { 436, 3, 1, 0, 0, 0, 0, 218, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #436 = OpFNegate
1115 { 435, 4, 1, 0, 0, 0, 0, 278, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #435 = OpFMulV
1116 { 434, 4, 1, 0, 0, 0, 0, 274, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #434 = OpFMulS
1117 { 433, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #433 = OpFMod
1118 { 432, 4, 1, 0, 0, 0, 0, 278, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #432 = OpFDivV
1119 { 431, 4, 1, 0, 0, 0, 0, 274, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #431 = OpFDivS
1120 { 430, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #430 = OpFConvert
1121 { 429, 4, 1, 0, 0, 0, 0, 278, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #429 = OpFAddV
1122 { 428, 4, 1, 0, 0, 0, 0, 274, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #428 = OpFAddS
1123 { 427, 1, 0, 0, 0, 0, 0, 0, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #427 = OpExtension
1124 { 426, 2, 1, 0, 0, 0, 0, 173, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #426 = OpExtInstImport
1125 { 425, 4, 1, 0, 0, 0, 0, 270, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #425 = OpExtInst
1126 { 424, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #424 = OpExpectKHR
1127 { 423, 2, 0, 0, 0, 0, 0, 173, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #423 = OpExecutionModeId
1128 { 422, 2, 0, 0, 0, 0, 0, 173, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #422 = OpExecutionMode
1129 { 421, 3, 0, 0, 0, 0, 0, 267, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #421 = OpEntryPoint
1130 { 420, 12, 1, 0, 0, 0, 0, 255, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #420 = OpEnqueueKernel
1131 { 419, 1, 0, 0, 0, 0, 0, 160, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #419 = OpEndStreamPrimitive
1132 { 418, 0, 0, 0, 0, 0, 0, 1, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #418 = OpEndPrimitive
1133 { 417, 0, 0, 0, 0, 0, 0, 1, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #417 = OpEmitVertex
1134 { 416, 1, 0, 0, 0, 0, 0, 160, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #416 = OpEmitStreamVertex
1135 { 415, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #415 = OpDot
1136 { 414, 0, 0, 0, 0, 0, 0, 1, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #414 = OpDemoteToHelperInvocation
1137 { 413, 3, 0, 0, 0, 0, 0, 252, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #413 = OpDecorateString
1138 { 412, 2, 0, 0, 0, 0, 0, 250, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #412 = OpDecorateId
1139 { 411, 2, 0, 0, 0, 0, 0, 250, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #411 = OpDecorate
1140 { 410, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #410 = OpDPdyFine
1141 { 409, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #409 = OpDPdyCoarse
1142 { 408, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #408 = OpDPdy
1143 { 407, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #407 = OpDPdxFine
1144 { 406, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #406 = OpDPdxCoarse
1145 { 405, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #405 = OpDPdx
1146 { 404, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #404 = OpCrossWorkgroupCastToPtrINTEL
1147 { 403, 2, 1, 0, 0, 0, 0, 212, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #403 = OpCreateUserEvent
1148 { 402, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #402 = OpCopyObject
1149 { 401, 3, 0, 0, 0, 0, 0, 189, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #401 = OpCopyMemorySized
1150 { 400, 2, 0, 0, 0, 0, 0, 161, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #400 = OpCopyMemory
1151 { 399, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #399 = OpCopyLogical
1152 { 398, 3, 0, 0, 0, 0, 0, 189, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #398 = OpCooperativeMatrixStoreKHR
1153 { 397, 7, 0, 0, 0, 0, 0, 243, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #397 = OpCooperativeMatrixStoreCheckedINTEL
1154 { 396, 5, 0, 0, 0, 0, 0, 238, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #396 = OpCooperativeMatrixPrefetchINTEL
1155 { 395, 5, 1, 0, 0, 0, 0, 192, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #395 = OpCooperativeMatrixMulAddKHR
1156 { 394, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #394 = OpCooperativeMatrixLoadKHR
1157 { 393, 8, 1, 0, 0, 0, 0, 181, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #393 = OpCooperativeMatrixLoadCheckedINTEL
1158 { 392, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #392 = OpCooperativeMatrixLengthKHR
1159 { 391, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #391 = OpCooperativeMatrixGetElementCoordINTEL
1160 { 390, 7, 1, 0, 0, 0, 0, 231, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #390 = OpCooperativeMatrixConstructCheckedINTEL
1161 { 389, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #389 = OpConvertUToPtr
1162 { 388, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #388 = OpConvertUToF
1163 { 387, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #387 = OpConvertSToF
1164 { 386, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #386 = OpConvertPtrToU
1165 { 385, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #385 = OpConvertHandleToSamplerINTEL
1166 { 384, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #384 = OpConvertHandleToSampledImageINTEL
1167 { 383, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #383 = OpConvertHandleToImageINTEL
1168 { 382, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #382 = OpConvertFToU
1169 { 381, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #381 = OpConvertFToS
1170 { 380, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #380 = OpConvertFToBF16INTEL
1171 { 379, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #379 = OpConvertBF16ToFINTEL
1172 { 378, 3, 0, 0, 0, 0, 0, 189, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #378 = OpControlBarrierWaitINTEL
1173 { 377, 3, 0, 0, 0, 0, 0, 189, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #377 = OpControlBarrierArriveINTEL
1174 { 376, 3, 0, 0, 0, 0, 0, 189, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #376 = OpControlBarrier
1175 { 375, 2, 1, 0, 0, 0, 0, 221, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #375 = OpConstantTrue
1176 { 374, 5, 1, 0, 0, 0, 0, 226, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #374 = OpConstantSampler
1177 { 373, 2, 1, 0, 0, 0, 0, 212, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #373 = OpConstantNull
1178 { 372, 3, 1, 0, 0, 0, 0, 223, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #372 = OpConstantI
1179 { 371, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #371 = OpConstantFunctionPointerINTEL
1180 { 370, 2, 1, 0, 0, 0, 0, 221, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #370 = OpConstantFalse
1181 { 369, 3, 1, 0, 0, 0, 0, 218, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #369 = OpConstantF
1182 { 368, 0, 0, 0, 0, 0, 0, 1, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #368 = OpConstantCompositeContinuedINTEL
1183 { 367, 2, 1, 0, 0, 0, 0, 212, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #367 = OpConstantComposite
1184 { 366, 4, 1, 0, 0, 0, 0, 214, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #366 = OpCompositeInsert
1185 { 365, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #365 = OpCompositeExtract
1186 { 364, 0, 0, 0, 0, 0, 0, 1, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #364 = OpCompositeConstructContinuedINTEL
1187 { 363, 2, 1, 0, 0, 0, 0, 212, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #363 = OpCompositeConstruct
1188 { 362, 3, 0, 0, 0, 0, 0, 189, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #362 = OpCaptureEventProfilingInfo
1189 { 361, 1, 0, 0, 0, 0, 0, 0, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #361 = OpCapability
1190 { 360, 5, 1, 0, 0, 0, 0, 192, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #360 = OpBuildNDRange
1191 { 359, 3, 0, 0, 0, 0, 0, 209, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #359 = OpBranchConditional
1192 { 358, 1, 0, 0, 0, 0, 0, 0, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #358 = OpBranch
1193 { 357, 4, 1, 0, 0, 0, 0, 205, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #357 = OpBitwiseXorV
1194 { 356, 4, 1, 0, 0, 0, 0, 201, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #356 = OpBitwiseXorS
1195 { 355, 4, 1, 0, 0, 0, 0, 205, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #355 = OpBitwiseOrV
1196 { 354, 4, 1, 0, 0, 0, 0, 201, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #354 = OpBitwiseOrS
1197 { 353, 6, 1, 0, 0, 0, 0, 175, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #353 = OpBitwiseFunctionINTEL
1198 { 352, 4, 1, 0, 0, 0, 0, 205, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #352 = OpBitwiseAndV
1199 { 351, 4, 1, 0, 0, 0, 0, 201, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #351 = OpBitwiseAndS
1200 { 350, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #350 = OpBitcast
1201 { 349, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #349 = OpBitReverse
1202 { 348, 5, 1, 0, 0, 0, 0, 192, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #348 = OpBitFieldUExtract
1203 { 347, 5, 1, 0, 0, 0, 0, 192, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #347 = OpBitFieldSExtract
1204 { 346, 6, 1, 0, 0, 0, 0, 175, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #346 = OpBitFieldInsert
1205 { 345, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #345 = OpBitCount
1206 { 344, 6, 1, 0, 0, 0, 0, 175, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #344 = OpAtomicXor
1207 { 343, 6, 1, 0, 0, 0, 0, 175, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #343 = OpAtomicUMin
1208 { 342, 6, 1, 0, 0, 0, 0, 175, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #342 = OpAtomicUMax
1209 { 341, 4, 0, 0, 0, 0, 0, 197, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #341 = OpAtomicStore
1210 { 340, 6, 1, 0, 0, 0, 0, 175, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #340 = OpAtomicSMin
1211 { 339, 6, 1, 0, 0, 0, 0, 175, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #339 = OpAtomicSMax
1212 { 338, 6, 1, 0, 0, 0, 0, 175, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #338 = OpAtomicOr
1213 { 337, 5, 1, 0, 0, 0, 0, 192, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #337 = OpAtomicLoad
1214 { 336, 6, 1, 0, 0, 0, 0, 175, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #336 = OpAtomicISub
1215 { 335, 5, 1, 0, 0, 0, 0, 192, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #335 = OpAtomicIIncrement
1216 { 334, 5, 1, 0, 0, 0, 0, 192, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #334 = OpAtomicIDecrement
1217 { 333, 6, 1, 0, 0, 0, 0, 175, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #333 = OpAtomicIAdd
1218 { 332, 5, 1, 0, 0, 0, 0, 192, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #332 = OpAtomicFlagTestAndSet
1219 { 331, 3, 0, 0, 0, 0, 0, 189, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #331 = OpAtomicFlagClear
1220 { 330, 6, 1, 0, 0, 0, 0, 175, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #330 = OpAtomicFMinEXT
1221 { 329, 6, 1, 0, 0, 0, 0, 175, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #329 = OpAtomicFMaxEXT
1222 { 328, 6, 1, 0, 0, 0, 0, 175, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #328 = OpAtomicFAddEXT
1223 { 327, 6, 1, 0, 0, 0, 0, 175, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #327 = OpAtomicExchange
1224 { 326, 8, 1, 0, 0, 0, 0, 181, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #326 = OpAtomicCompareExchangeWeak
1225 { 325, 8, 1, 0, 0, 0, 0, 181, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #325 = OpAtomicCompareExchange
1226 { 324, 6, 1, 0, 0, 0, 0, 175, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #324 = OpAtomicAnd
1227 { 323, 1, 0, 0, 0, 0, 0, 160, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #323 = OpAssumeTrueKHR
1228 { 322, 2, 1, 0, 0, 0, 0, 173, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #322 = OpAsmTargetINTEL
1229 { 321, 6, 1, 0, 0, 0, 0, 167, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #321 = OpAsmINTEL
1230 { 320, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #320 = OpAsmCallINTEL
1231 { 319, 4, 1, 0, 0, 0, 0, 163, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #319 = OpArrayLength
1232 { 318, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #318 = OpArithmeticFenceEXT
1233 { 317, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #317 = OpAny
1234 { 316, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #316 = OpAll
1235 { 315, 1, 1, 0, 0, 0, 0, 160, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #315 = OpAliasScopeListDeclINTEL
1236 { 314, 2, 1, 0, 0, 0, 0, 161, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #314 = OpAliasScopeDeclINTEL
1237 { 313, 1, 1, 0, 0, 0, 0, 160, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #313 = OpAliasDomainDeclINTEL
1238 { 312, 3, 1, 0, 0, 0, 0, 157, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #312 = OpAccessChain
1239 { 311, 2, 1, 0, 0, 0, 0, 155, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #311 = UNKNOWN_type
1240 { 310, 3, 1, 0, 0, 0, 0, 152, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #310 = ASSIGN_TYPE
1241 { 309, 4, 1, 0, 0, 0, 0, 148, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #309 = G_UBFX
1242 { 308, 4, 1, 0, 0, 0, 0, 148, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #308 = G_SBFX
1243 { 307, 2, 1, 0, 0, 0, 0, 61, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #307 = G_VECREDUCE_UMIN
1244 { 306, 2, 1, 0, 0, 0, 0, 61, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #306 = G_VECREDUCE_UMAX
1245 { 305, 2, 1, 0, 0, 0, 0, 61, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #305 = G_VECREDUCE_SMIN
1246 { 304, 2, 1, 0, 0, 0, 0, 61, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #304 = G_VECREDUCE_SMAX
1247 { 303, 2, 1, 0, 0, 0, 0, 61, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #303 = G_VECREDUCE_XOR
1248 { 302, 2, 1, 0, 0, 0, 0, 61, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #302 = G_VECREDUCE_OR
1249 { 301, 2, 1, 0, 0, 0, 0, 61, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #301 = G_VECREDUCE_AND
1250 { 300, 2, 1, 0, 0, 0, 0, 61, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #300 = G_VECREDUCE_MUL
1251 { 299, 2, 1, 0, 0, 0, 0, 61, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #299 = G_VECREDUCE_ADD
1252 { 298, 2, 1, 0, 0, 0, 0, 61, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #298 = G_VECREDUCE_FMINIMUM
1253 { 297, 2, 1, 0, 0, 0, 0, 61, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #297 = G_VECREDUCE_FMAXIMUM
1254 { 296, 2, 1, 0, 0, 0, 0, 61, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #296 = G_VECREDUCE_FMIN
1255 { 295, 2, 1, 0, 0, 0, 0, 61, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #295 = G_VECREDUCE_FMAX
1256 { 294, 2, 1, 0, 0, 0, 0, 61, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #294 = G_VECREDUCE_FMUL
1257 { 293, 2, 1, 0, 0, 0, 0, 61, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #293 = G_VECREDUCE_FADD
1258 { 292, 3, 1, 0, 0, 0, 0, 131, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #292 = G_VECREDUCE_SEQ_FMUL
1259 { 291, 3, 1, 0, 0, 0, 0, 131, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #291 = G_VECREDUCE_SEQ_FADD
1260 { 290, 1, 0, 0, 0, 0, 0, 1, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #290 = G_UBSANTRAP
1261 { 289, 0, 0, 0, 0, 0, 0, 1, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #289 = G_DEBUGTRAP
1262 { 288, 0, 0, 0, 0, 0, 0, 1, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #288 = G_TRAP
1263 { 287, 3, 0, 0, 0, 0, 0, 58, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #287 = G_BZERO
1264 { 286, 4, 0, 0, 0, 0, 0, 144, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #286 = G_MEMSET
1265 { 285, 4, 0, 0, 0, 0, 0, 144, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #285 = G_MEMMOVE
1266 { 284, 3, 0, 0, 0, 0, 0, 131, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #284 = G_MEMCPY_INLINE
1267 { 283, 4, 0, 0, 0, 0, 0, 144, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #283 = G_MEMCPY
1268 { 282, 2, 0, 0, 0, 0, 0, 142, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #282 = G_WRITE_REGISTER
1269 { 281, 2, 1, 0, 0, 0, 0, 51, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #281 = G_READ_REGISTER
1270 { 280, 3, 1, 0, 0, 0, 0, 101, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #280 = G_STRICT_FLDEXP
1271 { 279, 2, 1, 0, 0, 0, 0, 67, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #279 = G_STRICT_FSQRT
1272 { 278, 4, 1, 0, 0, 0, 0, 46, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #278 = G_STRICT_FMA
1273 { 277, 3, 1, 0, 0, 0, 0, 43, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #277 = G_STRICT_FREM
1274 { 276, 3, 1, 0, 0, 0, 0, 43, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #276 = G_STRICT_FDIV
1275 { 275, 3, 1, 0, 0, 0, 0, 43, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #275 = G_STRICT_FMUL
1276 { 274, 3, 1, 0, 0, 0, 0, 43, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #274 = G_STRICT_FSUB
1277 { 273, 3, 1, 0, 0, 0, 0, 43, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #273 = G_STRICT_FADD
1278 { 272, 1, 0, 0, 0, 0, 0, 50, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #272 = G_STACKRESTORE
1279 { 271, 1, 1, 0, 0, 0, 0, 50, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #271 = G_STACKSAVE
1280 { 270, 3, 1, 0, 0, 0, 0, 69, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #270 = G_DYN_STACKALLOC
1281 { 269, 2, 1, 0, 0, 0, 0, 51, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #269 = G_JUMP_TABLE
1282 { 268, 2, 1, 0, 0, 0, 0, 51, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #268 = G_BLOCK_ADDR
1283 { 267, 2, 1, 0, 0, 0, 0, 61, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #267 = G_ADDRSPACE_CAST
1284 { 266, 2, 1, 0, 0, 0, 0, 67, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #266 = G_FNEARBYINT
1285 { 265, 2, 1, 0, 0, 0, 0, 67, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #265 = G_FRINT
1286 { 264, 2, 1, 0, 0, 0, 0, 67, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #264 = G_FFLOOR
1287 { 263, 2, 1, 0, 0, 0, 0, 67, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #263 = G_FSQRT
1288 { 262, 2, 1, 0, 0, 0, 0, 67, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #262 = G_FTANH
1289 { 261, 2, 1, 0, 0, 0, 0, 67, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #261 = G_FSINH
1290 { 260, 2, 1, 0, 0, 0, 0, 67, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #260 = G_FCOSH
1291 { 259, 3, 1, 0, 0, 0, 0, 43, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #259 = G_FATAN2
1292 { 258, 2, 1, 0, 0, 0, 0, 67, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #258 = G_FATAN
1293 { 257, 2, 1, 0, 0, 0, 0, 67, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #257 = G_FASIN
1294 { 256, 2, 1, 0, 0, 0, 0, 67, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #256 = G_FACOS
1295 { 255, 2, 1, 0, 0, 0, 0, 67, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #255 = G_FTAN
1296 { 254, 3, 2, 0, 0, 0, 0, 43, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #254 = G_FSINCOS
1297 { 253, 2, 1, 0, 0, 0, 0, 67, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #253 = G_FSIN
1298 { 252, 2, 1, 0, 0, 0, 0, 67, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #252 = G_FCOS
1299 { 251, 2, 1, 0, 0, 0, 0, 67, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #251 = G_FCEIL
1300 { 250, 2, 1, 0, 0, 0, 0, 67, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #250 = G_BITREVERSE
1301 { 249, 2, 1, 0, 0, 0, 0, 67, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #249 = G_BSWAP
1302 { 248, 2, 1, 0, 0, 0, 0, 61, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #248 = G_CTPOP
1303 { 247, 2, 1, 0, 0, 0, 0, 61, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #247 = G_CTLZ_ZERO_UNDEF
1304 { 246, 2, 1, 0, 0, 0, 0, 61, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #246 = G_CTLZ
1305 { 245, 2, 1, 0, 0, 0, 0, 61, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #245 = G_CTTZ_ZERO_UNDEF
1306 { 244, 2, 1, 0, 0, 0, 0, 61, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #244 = G_CTTZ
1307 { 243, 4, 1, 0, 0, 0, 0, 138, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #243 = G_VECTOR_COMPRESS
1308 { 242, 2, 1, 0, 0, 0, 0, 51, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #242 = G_STEP_VECTOR
1309 { 241, 2, 1, 0, 0, 0, 0, 61, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #241 = G_SPLAT_VECTOR
1310 { 240, 4, 1, 0, 0, 0, 0, 134, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #240 = G_SHUFFLE_VECTOR
1311 { 239, 3, 1, 0, 0, 0, 0, 131, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #239 = G_EXTRACT_VECTOR_ELT
1312 { 238, 4, 1, 0, 0, 0, 0, 127, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #238 = G_INSERT_VECTOR_ELT
1313 { 237, 3, 1, 0, 0, 0, 0, 58, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #237 = G_EXTRACT_SUBVECTOR
1314 { 236, 4, 1, 0, 0, 0, 0, 63, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #236 = G_INSERT_SUBVECTOR
1315 { 235, 2, 1, 0, 0, 0, 0, 51, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #235 = G_VSCALE
1316 { 234, 3, 0, 0, 0, 0, 0, 124, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #234 = G_BRJT
1317 { 233, 1, 0, 0, 0, 0, 0, 0, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #233 = G_BR
1318 { 232, 2, 1, 0, 0, 0, 0, 61, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #232 = G_LLROUND
1319 { 231, 2, 1, 0, 0, 0, 0, 61, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #231 = G_LROUND
1320 { 230, 2, 1, 0, 0, 0, 0, 67, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #230 = G_ABS
1321 { 229, 3, 1, 0, 0, 0, 0, 43, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #229 = G_UMAX
1322 { 228, 3, 1, 0, 0, 0, 0, 43, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #228 = G_UMIN
1323 { 227, 3, 1, 0, 0, 0, 0, 43, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #227 = G_SMAX
1324 { 226, 3, 1, 0, 0, 0, 0, 43, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #226 = G_SMIN
1325 { 225, 3, 1, 0, 0, 0, 0, 101, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #225 = G_PTRMASK
1326 { 224, 3, 1, 0, 0, 0, 0, 101, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #224 = G_PTR_ADD
1327 { 223, 0, 0, 0, 0, 0, 0, 1, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #223 = G_RESET_FPMODE
1328 { 222, 1, 0, 0, 0, 0, 0, 50, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #222 = G_SET_FPMODE
1329 { 221, 1, 1, 0, 0, 0, 0, 50, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #221 = G_GET_FPMODE
1330 { 220, 0, 0, 0, 0, 0, 0, 1, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #220 = G_RESET_FPENV
1331 { 219, 1, 0, 0, 0, 0, 0, 50, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #219 = G_SET_FPENV
1332 { 218, 1, 1, 0, 0, 0, 0, 50, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #218 = G_GET_FPENV
1333 { 217, 3, 1, 0, 0, 0, 0, 43, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #217 = G_FMAXIMUMNUM
1334 { 216, 3, 1, 0, 0, 0, 0, 43, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #216 = G_FMINIMUMNUM
1335 { 215, 3, 1, 0, 0, 0, 0, 43, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #215 = G_FMAXIMUM
1336 { 214, 3, 1, 0, 0, 0, 0, 43, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #214 = G_FMINIMUM
1337 { 213, 3, 1, 0, 0, 0, 0, 43, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #213 = G_FMAXNUM_IEEE
1338 { 212, 3, 1, 0, 0, 0, 0, 43, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #212 = G_FMINNUM_IEEE
1339 { 211, 3, 1, 0, 0, 0, 0, 43, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #211 = G_FMAXNUM
1340 { 210, 3, 1, 0, 0, 0, 0, 43, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #210 = G_FMINNUM
1341 { 209, 2, 1, 0, 0, 0, 0, 67, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #209 = G_FCANONICALIZE
1342 { 208, 3, 1, 0, 0, 0, 0, 98, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #208 = G_IS_FPCLASS
1343 { 207, 3, 1, 0, 0, 0, 0, 101, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #207 = G_FCOPYSIGN
1344 { 206, 2, 1, 0, 0, 0, 0, 67, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #206 = G_FABS
1345 { 205, 2, 1, 0, 0, 0, 0, 61, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #205 = G_FPTOUI_SAT
1346 { 204, 2, 1, 0, 0, 0, 0, 61, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #204 = G_FPTOSI_SAT
1347 { 203, 2, 1, 0, 0, 0, 0, 61, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #203 = G_UITOFP
1348 { 202, 2, 1, 0, 0, 0, 0, 61, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #202 = G_SITOFP
1349 { 201, 2, 1, 0, 0, 0, 0, 61, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #201 = G_FPTOUI
1350 { 200, 2, 1, 0, 0, 0, 0, 61, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #200 = G_FPTOSI
1351 { 199, 2, 1, 0, 0, 0, 0, 61, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #199 = G_FPTRUNC
1352 { 198, 2, 1, 0, 0, 0, 0, 61, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #198 = G_FPEXT
1353 { 197, 2, 1, 0, 0, 0, 0, 67, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #197 = G_FNEG
1354 { 196, 3, 2, 0, 0, 0, 0, 91, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #196 = G_FFREXP
1355 { 195, 3, 1, 0, 0, 0, 0, 101, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #195 = G_FLDEXP
1356 { 194, 2, 1, 0, 0, 0, 0, 67, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #194 = G_FLOG10
1357 { 193, 2, 1, 0, 0, 0, 0, 67, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #193 = G_FLOG2
1358 { 192, 2, 1, 0, 0, 0, 0, 67, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #192 = G_FLOG
1359 { 191, 2, 1, 0, 0, 0, 0, 67, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #191 = G_FEXP10
1360 { 190, 2, 1, 0, 0, 0, 0, 67, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #190 = G_FEXP2
1361 { 189, 2, 1, 0, 0, 0, 0, 67, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #189 = G_FEXP
1362 { 188, 3, 1, 0, 0, 0, 0, 101, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #188 = G_FPOWI
1363 { 187, 3, 1, 0, 0, 0, 0, 43, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #187 = G_FPOW
1364 { 186, 3, 1, 0, 0, 0, 0, 43, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #186 = G_FREM
1365 { 185, 3, 1, 0, 0, 0, 0, 43, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #185 = G_FDIV
1366 { 184, 4, 1, 0, 0, 0, 0, 46, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #184 = G_FMAD
1367 { 183, 4, 1, 0, 0, 0, 0, 46, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #183 = G_FMA
1368 { 182, 3, 1, 0, 0, 0, 0, 43, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #182 = G_FMUL
1369 { 181, 3, 1, 0, 0, 0, 0, 43, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #181 = G_FSUB
1370 { 180, 3, 1, 0, 0, 0, 0, 43, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #180 = G_FADD
1371 { 179, 4, 1, 0, 0, 0, 0, 120, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #179 = G_UDIVFIXSAT
1372 { 178, 4, 1, 0, 0, 0, 0, 120, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #178 = G_SDIVFIXSAT
1373 { 177, 4, 1, 0, 0, 0, 0, 120, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #177 = G_UDIVFIX
1374 { 176, 4, 1, 0, 0, 0, 0, 120, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #176 = G_SDIVFIX
1375 { 175, 4, 1, 0, 0, 0, 0, 120, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #175 = G_UMULFIXSAT
1376 { 174, 4, 1, 0, 0, 0, 0, 120, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #174 = G_SMULFIXSAT
1377 { 173, 4, 1, 0, 0, 0, 0, 120, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #173 = G_UMULFIX
1378 { 172, 4, 1, 0, 0, 0, 0, 120, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #172 = G_SMULFIX
1379 { 171, 3, 1, 0, 0, 0, 0, 101, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #171 = G_SSHLSAT
1380 { 170, 3, 1, 0, 0, 0, 0, 101, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #170 = G_USHLSAT
1381 { 169, 3, 1, 0, 0, 0, 0, 43, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #169 = G_SSUBSAT
1382 { 168, 3, 1, 0, 0, 0, 0, 43, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #168 = G_USUBSAT
1383 { 167, 3, 1, 0, 0, 0, 0, 43, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #167 = G_SADDSAT
1384 { 166, 3, 1, 0, 0, 0, 0, 43, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #166 = G_UADDSAT
1385 { 165, 3, 1, 0, 0, 0, 0, 43, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #165 = G_SMULH
1386 { 164, 3, 1, 0, 0, 0, 0, 43, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #164 = G_UMULH
1387 { 163, 4, 2, 0, 0, 0, 0, 87, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #163 = G_SMULO
1388 { 162, 4, 2, 0, 0, 0, 0, 87, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #162 = G_UMULO
1389 { 161, 5, 2, 0, 0, 0, 0, 115, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #161 = G_SSUBE
1390 { 160, 4, 2, 0, 0, 0, 0, 87, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #160 = G_SSUBO
1391 { 159, 5, 2, 0, 0, 0, 0, 115, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #159 = G_SADDE
1392 { 158, 4, 2, 0, 0, 0, 0, 87, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #158 = G_SADDO
1393 { 157, 5, 2, 0, 0, 0, 0, 115, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #157 = G_USUBE
1394 { 156, 4, 2, 0, 0, 0, 0, 87, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #156 = G_USUBO
1395 { 155, 5, 2, 0, 0, 0, 0, 115, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #155 = G_UADDE
1396 { 154, 4, 2, 0, 0, 0, 0, 87, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #154 = G_UADDO
1397 { 153, 4, 1, 0, 0, 0, 0, 87, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #153 = G_SELECT
1398 { 152, 3, 1, 0, 0, 0, 0, 112, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #152 = G_UCMP
1399 { 151, 3, 1, 0, 0, 0, 0, 112, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #151 = G_SCMP
1400 { 150, 4, 1, 0, 0, 0, 0, 108, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #150 = G_FCMP
1401 { 149, 4, 1, 0, 0, 0, 0, 108, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #149 = G_ICMP
1402 { 148, 3, 1, 0, 0, 0, 0, 101, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #148 = G_ROTL
1403 { 147, 3, 1, 0, 0, 0, 0, 101, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #147 = G_ROTR
1404 { 146, 4, 1, 0, 0, 0, 0, 104, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #146 = G_FSHR
1405 { 145, 4, 1, 0, 0, 0, 0, 104, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #145 = G_FSHL
1406 { 144, 3, 1, 0, 0, 0, 0, 101, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #144 = G_ASHR
1407 { 143, 3, 1, 0, 0, 0, 0, 101, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #143 = G_LSHR
1408 { 142, 3, 1, 0, 0, 0, 0, 101, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #142 = G_SHL
1409 { 141, 2, 1, 0, 0, 0, 0, 61, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #141 = G_ZEXT
1410 { 140, 3, 1, 0, 0, 0, 0, 40, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #140 = G_SEXT_INREG
1411 { 139, 2, 1, 0, 0, 0, 0, 61, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #139 = G_SEXT
1412 { 138, 3, 1, 0, 0, 0, 0, 98, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #138 = G_VAARG
1413 { 137, 1, 0, 0, 0, 0, 0, 50, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #137 = G_VASTART
1414 { 136, 2, 1, 0, 0, 0, 0, 51, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #136 = G_FCONSTANT
1415 { 135, 2, 1, 0, 0, 0, 0, 51, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #135 = G_CONSTANT
1416 { 134, 2, 1, 0, 0, 0, 0, 61, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #134 = G_TRUNC
1417 { 133, 2, 1, 0, 0, 0, 0, 61, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #133 = G_ANYEXT
1418 { 132, 1, 0, 0, 0, 0, 0, 0, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #132 = G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
1419 { 131, 1, 0, 0, 0, 0, 0, 0, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #131 = G_INTRINSIC_CONVERGENT
1420 { 130, 1, 0, 0, 0, 0, 0, 0, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #130 = G_INTRINSIC_W_SIDE_EFFECTS
1421 { 129, 1, 0, 0, 0, 0, 0, 0, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #129 = G_INTRINSIC
1422 { 128, 0, 0, 0, 0, 0, 0, 1, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #128 = G_INVOKE_REGION_START
1423 { 127, 1, 0, 0, 0, 0, 0, 50, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #127 = G_BRINDIRECT
1424 { 126, 2, 0, 0, 0, 0, 0, 51, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #126 = G_BRCOND
1425 { 125, 4, 0, 0, 0, 0, 0, 94, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #125 = G_PREFETCH
1426 { 124, 2, 0, 0, 0, 0, 0, 21, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #124 = G_FENCE
1427 { 123, 3, 1, 0, 0, 0, 0, 91, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #123 = G_ATOMICRMW_USUB_SAT
1428 { 122, 3, 1, 0, 0, 0, 0, 91, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #122 = G_ATOMICRMW_USUB_COND
1429 { 121, 3, 1, 0, 0, 0, 0, 91, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #121 = G_ATOMICRMW_UDEC_WRAP
1430 { 120, 3, 1, 0, 0, 0, 0, 91, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #120 = G_ATOMICRMW_UINC_WRAP
1431 { 119, 3, 1, 0, 0, 0, 0, 91, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #119 = G_ATOMICRMW_FMINIMUM
1432 { 118, 3, 1, 0, 0, 0, 0, 91, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #118 = G_ATOMICRMW_FMAXIMUM
1433 { 117, 3, 1, 0, 0, 0, 0, 91, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #117 = G_ATOMICRMW_FMIN
1434 { 116, 3, 1, 0, 0, 0, 0, 91, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #116 = G_ATOMICRMW_FMAX
1435 { 115, 3, 1, 0, 0, 0, 0, 91, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #115 = G_ATOMICRMW_FSUB
1436 { 114, 3, 1, 0, 0, 0, 0, 91, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #114 = G_ATOMICRMW_FADD
1437 { 113, 3, 1, 0, 0, 0, 0, 91, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #113 = G_ATOMICRMW_UMIN
1438 { 112, 3, 1, 0, 0, 0, 0, 91, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #112 = G_ATOMICRMW_UMAX
1439 { 111, 3, 1, 0, 0, 0, 0, 91, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #111 = G_ATOMICRMW_MIN
1440 { 110, 3, 1, 0, 0, 0, 0, 91, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #110 = G_ATOMICRMW_MAX
1441 { 109, 3, 1, 0, 0, 0, 0, 91, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #109 = G_ATOMICRMW_XOR
1442 { 108, 3, 1, 0, 0, 0, 0, 91, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #108 = G_ATOMICRMW_OR
1443 { 107, 3, 1, 0, 0, 0, 0, 91, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #107 = G_ATOMICRMW_NAND
1444 { 106, 3, 1, 0, 0, 0, 0, 91, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #106 = G_ATOMICRMW_AND
1445 { 105, 3, 1, 0, 0, 0, 0, 91, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #105 = G_ATOMICRMW_SUB
1446 { 104, 3, 1, 0, 0, 0, 0, 91, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #104 = G_ATOMICRMW_ADD
1447 { 103, 3, 1, 0, 0, 0, 0, 91, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #103 = G_ATOMICRMW_XCHG
1448 { 102, 4, 1, 0, 0, 0, 0, 87, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #102 = G_ATOMIC_CMPXCHG
1449 { 101, 5, 2, 0, 0, 0, 0, 82, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #101 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
1450 { 100, 5, 1, 0, 0, 0, 0, 77, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #100 = G_INDEXED_STORE
1451 { 99, 2, 0, 0, 0, 0, 0, 61, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #99 = G_STORE
1452 { 98, 5, 2, 0, 0, 0, 0, 72, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #98 = G_INDEXED_ZEXTLOAD
1453 { 97, 5, 2, 0, 0, 0, 0, 72, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #97 = G_INDEXED_SEXTLOAD
1454 { 96, 5, 2, 0, 0, 0, 0, 72, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #96 = G_INDEXED_LOAD
1455 { 95, 2, 1, 0, 0, 0, 0, 61, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #95 = G_ZEXTLOAD
1456 { 94, 2, 1, 0, 0, 0, 0, 61, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #94 = G_SEXTLOAD
1457 { 93, 2, 1, 0, 0, 0, 0, 61, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #93 = G_LOAD
1458 { 92, 1, 1, 0, 0, 0, 0, 50, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #92 = G_READSTEADYCOUNTER
1459 { 91, 1, 1, 0, 0, 0, 0, 50, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #91 = G_READCYCLECOUNTER
1460 { 90, 2, 1, 0, 0, 0, 0, 67, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #90 = G_INTRINSIC_ROUNDEVEN
1461 { 89, 2, 1, 0, 0, 0, 0, 61, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #89 = G_INTRINSIC_LLRINT
1462 { 88, 2, 1, 0, 0, 0, 0, 61, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #88 = G_INTRINSIC_LRINT
1463 { 87, 2, 1, 0, 0, 0, 0, 67, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #87 = G_INTRINSIC_ROUND
1464 { 86, 2, 1, 0, 0, 0, 0, 67, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #86 = G_INTRINSIC_TRUNC
1465 { 85, 3, 1, 0, 0, 0, 0, 69, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #85 = G_INTRINSIC_FPTRUNC_ROUND
1466 { 84, 2, 1, 0, 0, 0, 0, 67, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #84 = G_CONSTANT_FOLD_BARRIER
1467 { 83, 2, 1, 0, 0, 0, 0, 67, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #83 = G_FREEZE
1468 { 82, 2, 1, 0, 0, 0, 0, 61, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #82 = G_BITCAST
1469 { 81, 2, 1, 0, 0, 0, 0, 61, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #81 = G_INTTOPTR
1470 { 80, 2, 1, 0, 0, 0, 0, 61, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #80 = G_PTRTOINT
1471 { 79, 2, 1, 0, 0, 0, 0, 61, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #79 = G_CONCAT_VECTORS
1472 { 78, 2, 1, 0, 0, 0, 0, 61, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #78 = G_BUILD_VECTOR_TRUNC
1473 { 77, 2, 1, 0, 0, 0, 0, 61, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #77 = G_BUILD_VECTOR
1474 { 76, 2, 1, 0, 0, 0, 0, 61, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #76 = G_MERGE_VALUES
1475 { 75, 4, 1, 0, 0, 0, 0, 63, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #75 = G_INSERT
1476 { 74, 2, 1, 0, 0, 0, 0, 61, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #74 = G_UNMERGE_VALUES
1477 { 73, 3, 1, 0, 0, 0, 0, 58, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #73 = G_EXTRACT
1478 { 72, 2, 1, 0, 0, 0, 0, 51, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #72 = G_CONSTANT_POOL
1479 { 71, 5, 1, 0, 0, 0, 0, 53, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #71 = G_PTRAUTH_GLOBAL_VALUE
1480 { 70, 2, 1, 0, 0, 0, 0, 51, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #70 = G_GLOBAL_VALUE
1481 { 69, 2, 1, 0, 0, 0, 0, 51, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #69 = G_FRAME_INDEX
1482 { 68, 1, 1, 0, 0, 0, 0, 50, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #68 = G_PHI
1483 { 67, 1, 1, 0, 0, 0, 0, 50, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #67 = G_IMPLICIT_DEF
1484 { 66, 3, 1, 0, 0, 0, 0, 43, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #66 = G_ABDU
1485 { 65, 3, 1, 0, 0, 0, 0, 43, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #65 = G_ABDS
1486 { 64, 3, 1, 0, 0, 0, 0, 43, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #64 = G_XOR
1487 { 63, 3, 1, 0, 0, 0, 0, 43, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #63 = G_OR
1488 { 62, 3, 1, 0, 0, 0, 0, 43, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #62 = G_AND
1489 { 61, 4, 2, 0, 0, 0, 0, 46, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #61 = G_UDIVREM
1490 { 60, 4, 2, 0, 0, 0, 0, 46, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #60 = G_SDIVREM
1491 { 59, 3, 1, 0, 0, 0, 0, 43, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #59 = G_UREM
1492 { 58, 3, 1, 0, 0, 0, 0, 43, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #58 = G_SREM
1493 { 57, 3, 1, 0, 0, 0, 0, 43, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #57 = G_UDIV
1494 { 56, 3, 1, 0, 0, 0, 0, 43, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #56 = G_SDIV
1495 { 55, 3, 1, 0, 0, 0, 0, 43, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #55 = G_MUL
1496 { 54, 3, 1, 0, 0, 0, 0, 43, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #54 = G_SUB
1497 { 53, 3, 1, 0, 0, 0, 0, 43, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #53 = G_ADD
1498 { 52, 3, 1, 0, 0, 0, 0, 40, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #52 = G_ASSERT_ALIGN
1499 { 51, 3, 1, 0, 0, 0, 0, 40, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #51 = G_ASSERT_ZEXT
1500 { 50, 3, 1, 0, 0, 0, 0, 40, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #50 = G_ASSERT_SEXT
1501 { 49, 1, 0, 0, 0, 0, 0, 0, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #49 = CONVERGENCECTRL_GLUE
1502 { 48, 2, 1, 0, 0, 0, 0, 13, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #48 = CONVERGENCECTRL_LOOP
1503 { 47, 1, 1, 0, 0, 0, 0, 0, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #47 = CONVERGENCECTRL_ANCHOR
1504 { 46, 1, 1, 0, 0, 0, 0, 0, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #46 = CONVERGENCECTRL_ENTRY
1505 { 45, 1, 0, 0, 0, 0, 0, 1, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #45 = JUMP_TABLE_DEBUG_INFO
1506 { 44, 0, 0, 0, 0, 0, 0, 1, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #44 = MEMBARRIER
1507 { 43, 0, 0, 0, 0, 0, 0, 1, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #43 = FAKE_USE
1508 { 42, 0, 0, 0, 0, 0, 0, 1, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #42 = ICALL_BRANCH_FUNNEL
1509 { 41, 3, 0, 0, 0, 0, 0, 37, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #41 = PATCHABLE_TYPED_EVENT_CALL
1510 { 40, 2, 0, 0, 0, 0, 0, 35, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #40 = PATCHABLE_EVENT_CALL
1511 { 39, 0, 0, 0, 0, 0, 0, 1, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #39 = PATCHABLE_TAIL_CALL
1512 { 38, 0, 0, 0, 0, 0, 0, 1, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #38 = PATCHABLE_FUNCTION_EXIT
1513 { 37, 0, 0, 0, 0, 0, 0, 1, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #37 = PATCHABLE_RET
1514 { 36, 0, 0, 0, 0, 0, 0, 1, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #36 = PATCHABLE_FUNCTION_ENTER
1515 { 35, 0, 0, 0, 0, 0, 0, 1, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #35 = PATCHABLE_OP
1516 { 34, 1, 1, 0, 0, 0, 0, 0, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #34 = FAULTING_OP
1517 { 33, 2, 0, 0, 0, 0, 0, 33, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #33 = LOCAL_ESCAPE
1518 { 32, 0, 0, 0, 0, 0, 0, 1, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #32 = STATEPOINT
1519 { 31, 3, 1, 0, 0, 0, 0, 30, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #31 = PREALLOCATED_ARG
1520 { 30, 1, 0, 0, 0, 0, 0, 1, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #30 = PREALLOCATED_SETUP
1521 { 29, 1, 1, 0, 0, 0, 0, 29, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #29 = LOAD_STACK_GUARD
1522 { 28, 6, 1, 0, 0, 0, 0, 23, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #28 = PATCHPOINT
1523 { 27, 0, 0, 0, 0, 0, 0, 1, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #27 = FENTRY_CALL
1524 { 26, 2, 0, 0, 0, 0, 0, 21, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #26 = STACKMAP
1525 { 25, 2, 1, 0, 0, 0, 0, 19, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #25 = ARITH_FENCE
1526 { 24, 4, 0, 0, 0, 0, 0, 15, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #24 = PSEUDO_PROBE
1527 { 23, 1, 0, 0, 0, 0, 0, 1, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #23 = LIFETIME_END
1528 { 22, 1, 0, 0, 0, 0, 0, 1, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #22 = LIFETIME_START
1529 { 21, 0, 0, 0, 0, 0, 0, 1, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #21 = BUNDLE
1530 { 20, 2, 1, 0, 0, 0, 0, 13, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #20 = COPY
1531 { 19, 2, 1, 0, 0, 0, 0, 13, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #19 = REG_SEQUENCE
1532 { 18, 1, 0, 0, 0, 0, 0, 0, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #18 = DBG_LABEL
1533 { 17, 0, 0, 0, 0, 0, 0, 1, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #17 = DBG_PHI
1534 { 16, 0, 0, 0, 0, 0, 0, 1, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #16 = DBG_INSTR_REF
1535 { 15, 0, 0, 0, 0, 0, 0, 1, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #15 = DBG_VALUE_LIST
1536 { 14, 0, 0, 0, 0, 0, 0, 1, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #14 = DBG_VALUE
1537 { 13, 3, 1, 0, 0, 0, 0, 2, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #13 = COPY_TO_REGCLASS
1538 { 12, 4, 1, 0, 0, 0, 0, 9, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #12 = SUBREG_TO_REG
1539 { 11, 1, 1, 0, 0, 0, 0, 0, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #11 = INIT_UNDEF
1540 { 10, 1, 1, 0, 0, 0, 0, 0, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #10 = IMPLICIT_DEF
1541 { 9, 4, 1, 0, 0, 0, 0, 5, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #9 = INSERT_SUBREG
1542 { 8, 3, 1, 0, 0, 0, 0, 2, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #8 = EXTRACT_SUBREG
1543 { 7, 0, 0, 0, 0, 0, 0, 1, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #7 = KILL
1544 { 6, 1, 0, 0, 0, 0, 0, 1, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #6 = ANNOTATION_LABEL
1545 { 5, 1, 0, 0, 0, 0, 0, 1, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #5 = GC_LABEL
1546 { 4, 1, 0, 0, 0, 0, 0, 1, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #4 = EH_LABEL
1547 { 3, 1, 0, 0, 0, 0, 0, 1, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #3 = CFI_INSTRUCTION
1548 { 2, 0, 0, 0, 0, 0, 0, 1, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #2 = INLINEASM_BR
1549 { 1, 0, 0, 0, 0, 0, 0, 1, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1 = INLINEASM
1550 { 0, 1, 1, 0, 0, 0, 0, 0, SPIRVImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #0 = PHI
1551 }, {
1552 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1553 /* 1 */
1554 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1555 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1556 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1557 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1558 /* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1559 /* 15 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1560 /* 19 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
1561 /* 21 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1562 /* 23 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1563 /* 29 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
1564 /* 30 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1565 /* 33 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1566 /* 35 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1567 /* 37 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1568 /* 40 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1569 /* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1570 /* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1571 /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1572 /* 51 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1573 /* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1574 /* 58 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1575 /* 61 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1576 /* 63 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1577 /* 67 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1578 /* 69 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1579 /* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1580 /* 77 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1581 /* 82 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1582 /* 87 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1583 /* 91 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1584 /* 94 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1585 /* 98 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1586 /* 101 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1587 /* 104 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1588 /* 108 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1589 /* 112 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1590 /* 115 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1591 /* 120 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1592 /* 124 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1593 /* 127 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1594 /* 131 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1595 /* 134 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1596 /* 138 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1597 /* 142 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1598 /* 144 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1599 /* 148 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1600 /* 152 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1601 /* 155 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1602 /* 157 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1603 /* 160 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1604 /* 161 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1605 /* 163 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1606 /* 167 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1607 /* 173 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1608 /* 175 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1609 /* 181 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1610 /* 189 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1611 /* 192 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1612 /* 197 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1613 /* 201 */ { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1614 /* 205 */ { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1615 /* 209 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1616 /* 212 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1617 /* 214 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1618 /* 218 */ { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1619 /* 221 */ { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1620 /* 223 */ { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1621 /* 226 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1622 /* 231 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1623 /* 238 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1624 /* 243 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1625 /* 250 */ { SPIRV::ANYRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1626 /* 252 */ { SPIRV::ANYRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1627 /* 255 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1628 /* 267 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1629 /* 270 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1630 /* 274 */ { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1631 /* 278 */ { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1632 /* 282 */ { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1633 /* 285 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1634 /* 289 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1635 /* 293 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1636 /* 298 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1637 /* 303 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1638 /* 310 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1639 /* 316 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1640 /* 318 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1641 /* 321 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1642 /* 324 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1643 /* 327 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1644 /* 331 */ { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1645 /* 336 */ { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1646 /* 341 */ { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1647 /* 346 */ { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1648 /* 351 */ { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1649 /* 356 */ { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1650 /* 361 */ { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1651 /* 366 */ { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1652 /* 371 */ { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1653 /* 376 */ { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1654 /* 381 */ { SPIRV::vpIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vpIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vpIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1655 /* 386 */ { SPIRV::vpIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vpIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vpIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1656 /* 391 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1657 /* 393 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1658 /* 396 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1659 /* 400 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1660 /* 410 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1661 /* 419 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1662 /* 424 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1663 /* 425 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1664 /* 428 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1665 /* 434 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1666 /* 439 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1667 /* 441 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1668 /* 443 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1669 /* 451 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1670 /* 454 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1671 /* 457 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1672 /* 460 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1673 /* 463 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1674 }, {
1675 /* 0 */
1676 }
1677};
1678
1679
1680#ifdef __GNUC__
1681#pragma GCC diagnostic push
1682#pragma GCC diagnostic ignored "-Woverlength-strings"
1683#endif
1684extern const char SPIRVInstrNameData[] = {
1685 /* 0 */ "G_FLOG10\000"
1686 /* 9 */ "G_FEXP10\000"
1687 /* 18 */ "G_FLOG2\000"
1688 /* 26 */ "G_FATAN2\000"
1689 /* 35 */ "G_FEXP2\000"
1690 /* 43 */ "OpQuantizeToF16\000"
1691 /* 59 */ "G_FMA\000"
1692 /* 65 */ "G_STRICT_FMA\000"
1693 /* 78 */ "OpGroupNonUniformBallotFindLSB\000"
1694 /* 109 */ "OpGroupNonUniformBallotFindMSB\000"
1695 /* 140 */ "G_FSUB\000"
1696 /* 147 */ "G_STRICT_FSUB\000"
1697 /* 161 */ "G_ATOMICRMW_FSUB\000"
1698 /* 178 */ "G_SUB\000"
1699 /* 184 */ "G_ATOMICRMW_SUB\000"
1700 /* 200 */ "G_INTRINSIC\000"
1701 /* 212 */ "G_FPTRUNC\000"
1702 /* 222 */ "G_INTRINSIC_TRUNC\000"
1703 /* 240 */ "G_TRUNC\000"
1704 /* 248 */ "G_BUILD_VECTOR_TRUNC\000"
1705 /* 269 */ "G_DYN_STACKALLOC\000"
1706 /* 286 */ "G_FMAD\000"
1707 /* 293 */ "G_INDEXED_SEXTLOAD\000"
1708 /* 312 */ "G_SEXTLOAD\000"
1709 /* 323 */ "G_INDEXED_ZEXTLOAD\000"
1710 /* 342 */ "G_ZEXTLOAD\000"
1711 /* 353 */ "G_INDEXED_LOAD\000"
1712 /* 368 */ "G_LOAD\000"
1713 /* 375 */ "G_VECREDUCE_FADD\000"
1714 /* 392 */ "G_FADD\000"
1715 /* 399 */ "G_VECREDUCE_SEQ_FADD\000"
1716 /* 420 */ "G_STRICT_FADD\000"
1717 /* 434 */ "G_ATOMICRMW_FADD\000"
1718 /* 451 */ "G_VECREDUCE_ADD\000"
1719 /* 467 */ "G_ADD\000"
1720 /* 473 */ "G_PTR_ADD\000"
1721 /* 483 */ "G_ATOMICRMW_ADD\000"
1722 /* 499 */ "G_ATOMICRMW_NAND\000"
1723 /* 516 */ "G_VECREDUCE_AND\000"
1724 /* 532 */ "G_AND\000"
1725 /* 538 */ "G_ATOMICRMW_AND\000"
1726 /* 554 */ "LIFETIME_END\000"
1727 /* 567 */ "G_BRCOND\000"
1728 /* 576 */ "G_ATOMICRMW_USUB_COND\000"
1729 /* 598 */ "G_LLROUND\000"
1730 /* 608 */ "G_LROUND\000"
1731 /* 617 */ "G_INTRINSIC_ROUND\000"
1732 /* 635 */ "G_INTRINSIC_FPTRUNC_ROUND\000"
1733 /* 661 */ "LOAD_STACK_GUARD\000"
1734 /* 678 */ "PSEUDO_PROBE\000"
1735 /* 691 */ "G_SSUBE\000"
1736 /* 699 */ "G_USUBE\000"
1737 /* 707 */ "G_FENCE\000"
1738 /* 715 */ "ARITH_FENCE\000"
1739 /* 727 */ "REG_SEQUENCE\000"
1740 /* 740 */ "G_SADDE\000"
1741 /* 748 */ "G_UADDE\000"
1742 /* 756 */ "G_GET_FPMODE\000"
1743 /* 769 */ "G_RESET_FPMODE\000"
1744 /* 784 */ "G_SET_FPMODE\000"
1745 /* 797 */ "G_FMINNUM_IEEE\000"
1746 /* 812 */ "G_FMAXNUM_IEEE\000"
1747 /* 827 */ "G_VSCALE\000"
1748 /* 836 */ "G_JUMP_TABLE\000"
1749 /* 849 */ "BUNDLE\000"
1750 /* 856 */ "G_MEMCPY_INLINE\000"
1751 /* 872 */ "LOCAL_ESCAPE\000"
1752 /* 885 */ "ASSIGN_TYPE\000"
1753 /* 897 */ "G_STACKRESTORE\000"
1754 /* 912 */ "G_INDEXED_STORE\000"
1755 /* 928 */ "G_STORE\000"
1756 /* 936 */ "G_BITREVERSE\000"
1757 /* 949 */ "FAKE_USE\000"
1758 /* 958 */ "DBG_VALUE\000"
1759 /* 968 */ "G_GLOBAL_VALUE\000"
1760 /* 983 */ "G_PTRAUTH_GLOBAL_VALUE\000"
1761 /* 1006 */ "CONVERGENCECTRL_GLUE\000"
1762 /* 1027 */ "G_STACKSAVE\000"
1763 /* 1039 */ "G_MEMMOVE\000"
1764 /* 1049 */ "G_FREEZE\000"
1765 /* 1058 */ "G_FCANONICALIZE\000"
1766 /* 1074 */ "G_CTLZ_ZERO_UNDEF\000"
1767 /* 1092 */ "G_CTTZ_ZERO_UNDEF\000"
1768 /* 1110 */ "INIT_UNDEF\000"
1769 /* 1121 */ "G_IMPLICIT_DEF\000"
1770 /* 1136 */ "DBG_INSTR_REF\000"
1771 /* 1150 */ "OpConvertSToF\000"
1772 /* 1164 */ "OpConvertUToF\000"
1773 /* 1178 */ "OpConstantF\000"
1774 /* 1190 */ "G_FNEG\000"
1775 /* 1197 */ "EXTRACT_SUBREG\000"
1776 /* 1212 */ "INSERT_SUBREG\000"
1777 /* 1226 */ "G_SEXT_INREG\000"
1778 /* 1239 */ "SUBREG_TO_REG\000"
1779 /* 1253 */ "G_ATOMIC_CMPXCHG\000"
1780 /* 1270 */ "G_ATOMICRMW_XCHG\000"
1781 /* 1287 */ "G_FLOG\000"
1782 /* 1294 */ "G_VAARG\000"
1783 /* 1302 */ "PREALLOCATED_ARG\000"
1784 /* 1319 */ "G_PREFETCH\000"
1785 /* 1330 */ "G_SMULH\000"
1786 /* 1338 */ "G_UMULH\000"
1787 /* 1346 */ "G_FTANH\000"
1788 /* 1354 */ "G_FSINH\000"
1789 /* 1362 */ "G_FCOSH\000"
1790 /* 1370 */ "DBG_PHI\000"
1791 /* 1378 */ "G_FPTOSI\000"
1792 /* 1387 */ "G_FPTOUI\000"
1793 /* 1396 */ "G_FPOWI\000"
1794 /* 1404 */ "OpConstantI\000"
1795 /* 1416 */ "G_PTRMASK\000"
1796 /* 1426 */ "GC_LABEL\000"
1797 /* 1435 */ "DBG_LABEL\000"
1798 /* 1445 */ "EH_LABEL\000"
1799 /* 1454 */ "ANNOTATION_LABEL\000"
1800 /* 1471 */ "ICALL_BRANCH_FUNNEL\000"
1801 /* 1491 */ "OpConvertFToBF16INTEL\000"
1802 /* 1513 */ "OpConvertBF16ToFINTEL\000"
1803 /* 1535 */ "OpSubgroupImageMediaBlockReadINTEL\000"
1804 /* 1570 */ "OpSubgroupImageBlockReadINTEL\000"
1805 /* 1600 */ "OpSubgroupBlockReadINTEL\000"
1806 /* 1625 */ "OpSubgroup2DBlockLoadINTEL\000"
1807 /* 1652 */ "OpCooperativeMatrixLoadCheckedINTEL\000"
1808 /* 1688 */ "OpCooperativeMatrixStoreCheckedINTEL\000"
1809 /* 1725 */ "OpCooperativeMatrixConstructCheckedINTEL\000"
1810 /* 1766 */ "OpSpecConstantCompositeContinuedINTEL\000"
1811 /* 1804 */ "OpConstantCompositeContinuedINTEL\000"
1812 /* 1838 */ "OpTypeStructContinuedINTEL\000"
1813 /* 1865 */ "OpCompositeConstructContinuedINTEL\000"
1814 /* 1900 */ "OpCooperativeMatrixGetElementCoordINTEL\000"
1815 /* 1940 */ "OpConvertHandleToSampledImageINTEL\000"
1816 /* 1975 */ "OpConvertHandleToImageINTEL\000"
1817 /* 2003 */ "OpSubgroupShuffleINTEL\000"
1818 /* 2026 */ "OpSubgroup2DBlockStoreINTEL\000"
1819 /* 2054 */ "OpSubgroup2DBlockLoadTransposeINTEL\000"
1820 /* 2090 */ "OpSubgroupMatrixMultiplyAccumulateINTEL\000"
1821 /* 2130 */ "OpSubgroupImageMediaBlockWriteINTEL\000"
1822 /* 2166 */ "OpSubgroupImageBlockWriteINTEL\000"
1823 /* 2197 */ "OpSubgroupBlockWriteINTEL\000"
1824 /* 2223 */ "OpControlBarrierArriveINTEL\000"
1825 /* 2251 */ "OpSubgroup2DBlockPrefetchINTEL\000"
1826 /* 2282 */ "OpCooperativeMatrixPrefetchINTEL\000"
1827 /* 2315 */ "OpAliasScopeDeclINTEL\000"
1828 /* 2337 */ "OpAliasDomainDeclINTEL\000"
1829 /* 2360 */ "OpAliasScopeListDeclINTEL\000"
1830 /* 2386 */ "OpAsmCallINTEL\000"
1831 /* 2401 */ "OpFunctionPointerCallINTEL\000"
1832 /* 2428 */ "OpSubgroup2DBlockLoadTransformINTEL\000"
1833 /* 2464 */ "OpAsmINTEL\000"
1834 /* 2475 */ "OpBitwiseFunctionINTEL\000"
1835 /* 2498 */ "OpSubgroupShuffleDownINTEL\000"
1836 /* 2525 */ "OpSubgroupShuffleUpINTEL\000"
1837 /* 2550 */ "OpPtrCastToCrossWorkgroupINTEL\000"
1838 /* 2581 */ "OpConvertHandleToSamplerINTEL\000"
1839 /* 2611 */ "OpConstantFunctionPointerINTEL\000"
1840 /* 2642 */ "OpSubgroupShuffleXorINTEL\000"
1841 /* 2668 */ "OpCrossWorkgroupCastToPtrINTEL\000"
1842 /* 2699 */ "OpAsmTargetINTEL\000"
1843 /* 2716 */ "OpControlBarrierWaitINTEL\000"
1844 /* 2742 */ "OpVariableLengthArrayINTEL\000"
1845 /* 2769 */ "OpRestoreMemoryINTEL\000"
1846 /* 2790 */ "OpSaveMemoryINTEL\000"
1847 /* 2808 */ "G_FSHL\000"
1848 /* 2815 */ "G_SHL\000"
1849 /* 2821 */ "G_FCEIL\000"
1850 /* 2829 */ "PATCHABLE_TAIL_CALL\000"
1851 /* 2849 */ "PATCHABLE_TYPED_EVENT_CALL\000"
1852 /* 2876 */ "PATCHABLE_EVENT_CALL\000"
1853 /* 2897 */ "FENTRY_CALL\000"
1854 /* 2909 */ "KILL\000"
1855 /* 2914 */ "G_CONSTANT_POOL\000"
1856 /* 2930 */ "G_ROTL\000"
1857 /* 2937 */ "G_VECREDUCE_FMUL\000"
1858 /* 2954 */ "G_FMUL\000"
1859 /* 2961 */ "G_VECREDUCE_SEQ_FMUL\000"
1860 /* 2982 */ "G_STRICT_FMUL\000"
1861 /* 2996 */ "G_VECREDUCE_MUL\000"
1862 /* 3012 */ "G_MUL\000"
1863 /* 3018 */ "G_FREM\000"
1864 /* 3025 */ "G_STRICT_FREM\000"
1865 /* 3039 */ "G_SREM\000"
1866 /* 3046 */ "G_UREM\000"
1867 /* 3053 */ "G_SDIVREM\000"
1868 /* 3063 */ "G_UDIVREM\000"
1869 /* 3073 */ "INLINEASM\000"
1870 /* 3083 */ "G_VECREDUCE_FMINIMUM\000"
1871 /* 3104 */ "G_FMINIMUM\000"
1872 /* 3115 */ "G_ATOMICRMW_FMINIMUM\000"
1873 /* 3136 */ "G_VECREDUCE_FMAXIMUM\000"
1874 /* 3157 */ "G_FMAXIMUM\000"
1875 /* 3168 */ "G_ATOMICRMW_FMAXIMUM\000"
1876 /* 3189 */ "G_FMINIMUMNUM\000"
1877 /* 3203 */ "G_FMAXIMUMNUM\000"
1878 /* 3217 */ "G_FMINNUM\000"
1879 /* 3227 */ "G_FMAXNUM\000"
1880 /* 3237 */ "G_FATAN\000"
1881 /* 3245 */ "G_FTAN\000"
1882 /* 3252 */ "G_INTRINSIC_ROUNDEVEN\000"
1883 /* 3274 */ "G_ASSERT_ALIGN\000"
1884 /* 3289 */ "G_FCOPYSIGN\000"
1885 /* 3301 */ "G_VECREDUCE_FMIN\000"
1886 /* 3318 */ "G_ATOMICRMW_FMIN\000"
1887 /* 3335 */ "G_VECREDUCE_SMIN\000"
1888 /* 3352 */ "G_SMIN\000"
1889 /* 3359 */ "G_VECREDUCE_UMIN\000"
1890 /* 3376 */ "G_UMIN\000"
1891 /* 3383 */ "G_ATOMICRMW_UMIN\000"
1892 /* 3400 */ "G_ATOMICRMW_MIN\000"
1893 /* 3416 */ "G_FASIN\000"
1894 /* 3424 */ "G_FSIN\000"
1895 /* 3431 */ "CFI_INSTRUCTION\000"
1896 /* 3447 */ "G_SSUBO\000"
1897 /* 3455 */ "G_USUBO\000"
1898 /* 3463 */ "G_SADDO\000"
1899 /* 3471 */ "G_UADDO\000"
1900 /* 3479 */ "JUMP_TABLE_DEBUG_INFO\000"
1901 /* 3501 */ "G_SMULO\000"
1902 /* 3509 */ "G_UMULO\000"
1903 /* 3517 */ "G_BZERO\000"
1904 /* 3525 */ "STACKMAP\000"
1905 /* 3534 */ "G_DEBUGTRAP\000"
1906 /* 3546 */ "G_UBSANTRAP\000"
1907 /* 3558 */ "G_TRAP\000"
1908 /* 3565 */ "G_ATOMICRMW_UDEC_WRAP\000"
1909 /* 3587 */ "G_ATOMICRMW_UINC_WRAP\000"
1910 /* 3609 */ "G_BSWAP\000"
1911 /* 3617 */ "G_SITOFP\000"
1912 /* 3626 */ "G_UITOFP\000"
1913 /* 3635 */ "G_FCMP\000"
1914 /* 3642 */ "G_ICMP\000"
1915 /* 3649 */ "G_SCMP\000"
1916 /* 3656 */ "G_UCMP\000"
1917 /* 3663 */ "CONVERGENCECTRL_LOOP\000"
1918 /* 3684 */ "G_CTPOP\000"
1919 /* 3692 */ "PATCHABLE_OP\000"
1920 /* 3705 */ "FAULTING_OP\000"
1921 /* 3717 */ "PREALLOCATED_SETUP\000"
1922 /* 3736 */ "G_FLDEXP\000"
1923 /* 3745 */ "G_STRICT_FLDEXP\000"
1924 /* 3761 */ "G_FEXP\000"
1925 /* 3768 */ "G_FFREXP\000"
1926 /* 3777 */ "G_BR\000"
1927 /* 3782 */ "INLINEASM_BR\000"
1928 /* 3795 */ "G_BLOCK_ADDR\000"
1929 /* 3808 */ "MEMBARRIER\000"
1930 /* 3819 */ "G_CONSTANT_FOLD_BARRIER\000"
1931 /* 3843 */ "PATCHABLE_FUNCTION_ENTER\000"
1932 /* 3868 */ "G_READCYCLECOUNTER\000"
1933 /* 3887 */ "G_READSTEADYCOUNTER\000"
1934 /* 3907 */ "G_READ_REGISTER\000"
1935 /* 3923 */ "G_WRITE_REGISTER\000"
1936 /* 3940 */ "OpCooperativeMatrixLoadKHR\000"
1937 /* 3967 */ "OpCooperativeMatrixMulAddKHR\000"
1938 /* 3996 */ "OpGroupBitwiseAndKHR\000"
1939 /* 4017 */ "OpGroupLogicalAndKHR\000"
1940 /* 4038 */ "OpCooperativeMatrixStoreKHR\000"
1941 /* 4066 */ "OpGroupNonUniformRotateKHR\000"
1942 /* 4093 */ "OpAssumeTrueKHR\000"
1943 /* 4109 */ "OpCooperativeMatrixLengthKHR\000"
1944 /* 4138 */ "OpReadClockKHR\000"
1945 /* 4153 */ "OpGroupFMulKHR\000"
1946 /* 4168 */ "OpGroupIMulKHR\000"
1947 /* 4183 */ "OpGroupBitwiseOrKHR\000"
1948 /* 4203 */ "OpGroupLogicalOrKHR\000"
1949 /* 4223 */ "OpGroupBitwiseXorKHR\000"
1950 /* 4244 */ "OpGroupLogicalXorKHR\000"
1951 /* 4265 */ "OpExpectKHR\000"
1952 /* 4277 */ "OpTypeCooperativeMatrixKHR\000"
1953 /* 4304 */ "G_ASHR\000"
1954 /* 4311 */ "G_FSHR\000"
1955 /* 4318 */ "G_LSHR\000"
1956 /* 4325 */ "CONVERGENCECTRL_ANCHOR\000"
1957 /* 4348 */ "G_FFLOOR\000"
1958 /* 4357 */ "G_EXTRACT_SUBVECTOR\000"
1959 /* 4377 */ "G_INSERT_SUBVECTOR\000"
1960 /* 4396 */ "G_BUILD_VECTOR\000"
1961 /* 4411 */ "G_SHUFFLE_VECTOR\000"
1962 /* 4428 */ "G_STEP_VECTOR\000"
1963 /* 4442 */ "G_SPLAT_VECTOR\000"
1964 /* 4457 */ "G_VECREDUCE_XOR\000"
1965 /* 4473 */ "G_XOR\000"
1966 /* 4479 */ "G_ATOMICRMW_XOR\000"
1967 /* 4495 */ "G_VECREDUCE_OR\000"
1968 /* 4510 */ "G_OR\000"
1969 /* 4515 */ "G_ATOMICRMW_OR\000"
1970 /* 4530 */ "G_ROTR\000"
1971 /* 4537 */ "G_INTTOPTR\000"
1972 /* 4548 */ "G_FABS\000"
1973 /* 4555 */ "G_ABS\000"
1974 /* 4561 */ "G_ABDS\000"
1975 /* 4568 */ "G_UNMERGE_VALUES\000"
1976 /* 4585 */ "G_MERGE_VALUES\000"
1977 /* 4600 */ "G_FACOS\000"
1978 /* 4608 */ "G_FCOS\000"
1979 /* 4615 */ "G_FSINCOS\000"
1980 /* 4625 */ "G_CONCAT_VECTORS\000"
1981 /* 4642 */ "COPY_TO_REGCLASS\000"
1982 /* 4659 */ "G_IS_FPCLASS\000"
1983 /* 4672 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000"
1984 /* 4702 */ "G_VECTOR_COMPRESS\000"
1985 /* 4720 */ "G_INTRINSIC_W_SIDE_EFFECTS\000"
1986 /* 4747 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000"
1987 /* 4785 */ "OpFSubS\000"
1988 /* 4793 */ "OpStrictFSubS\000"
1989 /* 4807 */ "OpISubS\000"
1990 /* 4815 */ "OpShiftRightArithmeticS\000"
1991 /* 4839 */ "OpFAddS\000"
1992 /* 4847 */ "OpStrictFAddS\000"
1993 /* 4861 */ "OpIAddS\000"
1994 /* 4869 */ "OpBitwiseAndS\000"
1995 /* 4883 */ "OpUModS\000"
1996 /* 4891 */ "OpShiftLeftLogicalS\000"
1997 /* 4911 */ "OpShiftRightLogicalS\000"
1998 /* 4932 */ "OpFMulS\000"
1999 /* 4940 */ "OpStrictFMulS\000"
2000 /* 4954 */ "OpIMulS\000"
2001 /* 4962 */ "OpFRemS\000"
2002 /* 4970 */ "OpStrictFRemS\000"
2003 /* 4984 */ "OpSRemS\000"
2004 /* 4992 */ "OpConvertFToS\000"
2005 /* 5006 */ "OpSatConvertUToS\000"
2006 /* 5023 */ "OpBitwiseOrS\000"
2007 /* 5036 */ "OpBitwiseXorS\000"
2008 /* 5050 */ "OpFDivS\000"
2009 /* 5058 */ "OpStrictFDivS\000"
2010 /* 5072 */ "OpSDivS\000"
2011 /* 5080 */ "OpUDivS\000"
2012 /* 5088 */ "OpISubBorrowS\000"
2013 /* 5102 */ "OpIAddCarryS\000"
2014 /* 5115 */ "G_SSUBSAT\000"
2015 /* 5125 */ "G_USUBSAT\000"
2016 /* 5135 */ "G_SADDSAT\000"
2017 /* 5145 */ "G_UADDSAT\000"
2018 /* 5155 */ "G_SSHLSAT\000"
2019 /* 5165 */ "G_USHLSAT\000"
2020 /* 5175 */ "G_SMULFIXSAT\000"
2021 /* 5188 */ "G_UMULFIXSAT\000"
2022 /* 5201 */ "G_SDIVFIXSAT\000"
2023 /* 5214 */ "G_UDIVFIXSAT\000"
2024 /* 5227 */ "G_ATOMICRMW_USUB_SAT\000"
2025 /* 5248 */ "G_FPTOSI_SAT\000"
2026 /* 5261 */ "G_FPTOUI_SAT\000"
2027 /* 5274 */ "G_EXTRACT\000"
2028 /* 5284 */ "G_SELECT\000"
2029 /* 5293 */ "G_BRINDIRECT\000"
2030 /* 5306 */ "PATCHABLE_RET\000"
2031 /* 5320 */ "G_MEMSET\000"
2032 /* 5329 */ "PATCHABLE_FUNCTION_EXIT\000"
2033 /* 5353 */ "G_BRJT\000"
2034 /* 5360 */ "G_EXTRACT_VECTOR_ELT\000"
2035 /* 5381 */ "G_INSERT_VECTOR_ELT\000"
2036 /* 5401 */ "G_FCONSTANT\000"
2037 /* 5413 */ "G_CONSTANT\000"
2038 /* 5424 */ "G_INTRINSIC_CONVERGENT\000"
2039 /* 5447 */ "STATEPOINT\000"
2040 /* 5458 */ "PATCHPOINT\000"
2041 /* 5469 */ "G_PTRTOINT\000"
2042 /* 5480 */ "G_FRINT\000"
2043 /* 5488 */ "G_INTRINSIC_LLRINT\000"
2044 /* 5507 */ "G_INTRINSIC_LRINT\000"
2045 /* 5525 */ "G_FNEARBYINT\000"
2046 /* 5538 */ "G_VASTART\000"
2047 /* 5548 */ "LIFETIME_START\000"
2048 /* 5563 */ "G_INVOKE_REGION_START\000"
2049 /* 5585 */ "G_INSERT\000"
2050 /* 5594 */ "G_FSQRT\000"
2051 /* 5602 */ "G_STRICT_FSQRT\000"
2052 /* 5617 */ "G_BITCAST\000"
2053 /* 5627 */ "G_ADDRSPACE_CAST\000"
2054 /* 5644 */ "DBG_VALUE_LIST\000"
2055 /* 5659 */ "G_FPEXT\000"
2056 /* 5667 */ "G_SEXT\000"
2057 /* 5674 */ "G_ASSERT_SEXT\000"
2058 /* 5688 */ "G_ANYEXT\000"
2059 /* 5697 */ "G_ZEXT\000"
2060 /* 5704 */ "G_ASSERT_ZEXT\000"
2061 /* 5718 */ "OpAtomicFAddEXT\000"
2062 /* 5734 */ "OpArithmeticFenceEXT\000"
2063 /* 5755 */ "OpAtomicFMinEXT\000"
2064 /* 5771 */ "OpAtomicFMaxEXT\000"
2065 /* 5787 */ "G_ABDU\000"
2066 /* 5794 */ "OpConvertFToU\000"
2067 /* 5808 */ "OpSatConvertSToU\000"
2068 /* 5825 */ "OpConvertPtrToU\000"
2069 /* 5841 */ "G_FDIV\000"
2070 /* 5848 */ "G_STRICT_FDIV\000"
2071 /* 5862 */ "G_SDIV\000"
2072 /* 5869 */ "G_UDIV\000"
2073 /* 5876 */ "G_GET_FPENV\000"
2074 /* 5888 */ "G_RESET_FPENV\000"
2075 /* 5902 */ "G_SET_FPENV\000"
2076 /* 5914 */ "OpTypeAccelerationStructureNV\000"
2077 /* 5944 */ "OpImageSampleFootprintNV\000"
2078 /* 5969 */ "OpTypeCooperativeMatrixNV\000"
2079 /* 5995 */ "OpFSubV\000"
2080 /* 6003 */ "OpStrictFSubV\000"
2081 /* 6017 */ "OpISubV\000"
2082 /* 6025 */ "OpShiftRightArithmeticV\000"
2083 /* 6049 */ "OpFAddV\000"
2084 /* 6057 */ "OpStrictFAddV\000"
2085 /* 6071 */ "OpIAddV\000"
2086 /* 6079 */ "OpBitwiseAndV\000"
2087 /* 6093 */ "OpUModV\000"
2088 /* 6101 */ "OpFNegateV\000"
2089 /* 6112 */ "OpShiftLeftLogicalV\000"
2090 /* 6132 */ "OpShiftRightLogicalV\000"
2091 /* 6153 */ "OpFMulV\000"
2092 /* 6161 */ "OpStrictFMulV\000"
2093 /* 6175 */ "OpIMulV\000"
2094 /* 6183 */ "OpFRemV\000"
2095 /* 6191 */ "OpStrictFRemV\000"
2096 /* 6205 */ "OpSRemV\000"
2097 /* 6213 */ "OpBitwiseOrV\000"
2098 /* 6226 */ "OpBitwiseXorV\000"
2099 /* 6240 */ "OpFDivV\000"
2100 /* 6248 */ "OpStrictFDivV\000"
2101 /* 6262 */ "OpSDivV\000"
2102 /* 6270 */ "OpUDivV\000"
2103 /* 6278 */ "OpISubBorrowV\000"
2104 /* 6292 */ "OpIAddCarryV\000"
2105 /* 6305 */ "G_FPOW\000"
2106 /* 6312 */ "G_VECREDUCE_FMAX\000"
2107 /* 6329 */ "G_ATOMICRMW_FMAX\000"
2108 /* 6346 */ "G_VECREDUCE_SMAX\000"
2109 /* 6363 */ "G_SMAX\000"
2110 /* 6370 */ "G_VECREDUCE_UMAX\000"
2111 /* 6387 */ "G_UMAX\000"
2112 /* 6394 */ "G_ATOMICRMW_UMAX\000"
2113 /* 6411 */ "G_ATOMICRMW_MAX\000"
2114 /* 6427 */ "G_FRAME_INDEX\000"
2115 /* 6441 */ "G_SBFX\000"
2116 /* 6448 */ "G_UBFX\000"
2117 /* 6455 */ "G_SMULFIX\000"
2118 /* 6465 */ "G_UMULFIX\000"
2119 /* 6475 */ "G_SDIVFIX\000"
2120 /* 6485 */ "G_UDIVFIX\000"
2121 /* 6495 */ "G_MEMCPY\000"
2122 /* 6504 */ "COPY\000"
2123 /* 6509 */ "CONVERGENCECTRL_ENTRY\000"
2124 /* 6531 */ "G_CTLZ\000"
2125 /* 6538 */ "G_CTTZ\000"
2126 /* 6545 */ "OpAtomicISub\000"
2127 /* 6558 */ "OpVectorExtractDynamic\000"
2128 /* 6581 */ "OpVectorInsertDynamic\000"
2129 /* 6603 */ "OpPtrCastToGeneric\000"
2130 /* 6622 */ "OpExecutionModeId\000"
2131 /* 6640 */ "OpDecorateId\000"
2132 /* 6653 */ "OpTypeReserveId\000"
2133 /* 6669 */ "OpImageRead\000"
2134 /* 6681 */ "OpImageSparseRead\000"
2135 /* 6699 */ "OpAtomicLoad\000"
2136 /* 6712 */ "OpLoad\000"
2137 /* 6719 */ "OpGroupNonUniformFAdd\000"
2138 /* 6741 */ "OpGroupFAdd\000"
2139 /* 6753 */ "OpAtomicIAdd\000"
2140 /* 6766 */ "OpGroupNonUniformIAdd\000"
2141 /* 6788 */ "OpGroupIAdd\000"
2142 /* 6800 */ "OpSMulExtended\000"
2143 /* 6815 */ "OpUMulExtended\000"
2144 /* 6830 */ "OpOrdered\000"
2145 /* 6840 */ "OpUnordered\000"
2146 /* 6852 */ "OpModuleProcessed\000"
2147 /* 6870 */ "OpSourceContinued\000"
2148 /* 6888 */ "OpCopyMemorySized\000"
2149 /* 6906 */ "OpTypeVoid\000"
2150 /* 6917 */ "OpAtomicAnd\000"
2151 /* 6929 */ "OpGroupNonUniformBitwiseAnd\000"
2152 /* 6957 */ "OpGroupNonUniformLogicalAnd\000"
2153 /* 6985 */ "OpLogicalAnd\000"
2154 /* 6998 */ "OpFunctionEnd\000"
2155 /* 7012 */ "OpSelectSFSCond\000"
2156 /* 7028 */ "OpSelectVFSCond\000"
2157 /* 7044 */ "OpSelectSISCond\000"
2158 /* 7060 */ "OpSelectVISCond\000"
2159 /* 7076 */ "OpSelectSPSCond\000"
2160 /* 7092 */ "OpSelectVPSCond\000"
2161 /* 7108 */ "OpSelectSFVCond\000"
2162 /* 7124 */ "OpSelectVFVCond\000"
2163 /* 7140 */ "OpSelectSIVCond\000"
2164 /* 7156 */ "OpSelectVIVCond\000"
2165 /* 7172 */ "OpSelectSPVCond\000"
2166 /* 7188 */ "OpSelectVPVCond\000"
2167 /* 7204 */ "OpImageQuerySizeLod\000"
2168 /* 7224 */ "OpImageSampleImplicitLod\000"
2169 /* 7249 */ "OpImageSparseSampleImplicitLod\000"
2170 /* 7280 */ "OpImageSampleDrefImplicitLod\000"
2171 /* 7309 */ "OpImageSparseSampleDrefImplicitLod\000"
2172 /* 7344 */ "OpImageSampleProjDrefImplicitLod\000"
2173 /* 7377 */ "OpImageSparseSampleProjDrefImplicitLod\000"
2174 /* 7416 */ "OpImageSampleProjImplicitLod\000"
2175 /* 7445 */ "OpImageSparseSampleProjImplicitLod\000"
2176 /* 7480 */ "OpImageSampleExplicitLod\000"
2177 /* 7505 */ "OpImageSparseSampleExplicitLod\000"
2178 /* 7536 */ "OpImageSampleDrefExplicitLod\000"
2179 /* 7565 */ "OpImageSparseSampleDrefExplicitLod\000"
2180 /* 7600 */ "OpImageSampleProjDrefExplicitLod\000"
2181 /* 7633 */ "OpImageSparseSampleProjDrefExplicitLod\000"
2182 /* 7672 */ "OpImageSampleProjExplicitLod\000"
2183 /* 7701 */ "OpImageSparseSampleProjExplicitLod\000"
2184 /* 7736 */ "OpImageQueryLod\000"
2185 /* 7752 */ "OpFMod\000"
2186 /* 7759 */ "OpSMod\000"
2187 /* 7766 */ "OpSource\000"
2188 /* 7775 */ "OpExecutionMode\000"
2189 /* 7791 */ "OpTypeSampledImage\000"
2190 /* 7810 */ "OpSampledImage\000"
2191 /* 7825 */ "OpTypeImage\000"
2192 /* 7837 */ "OpImage\000"
2193 /* 7845 */ "OpTypePipeStorage\000"
2194 /* 7863 */ "OpBuildNDRange\000"
2195 /* 7878 */ "OpAtomicExchange\000"
2196 /* 7895 */ "OpAtomicCompareExchange\000"
2197 /* 7919 */ "OpSelectionMerge\000"
2198 /* 7936 */ "OpLoopMerge\000"
2199 /* 7948 */ "OpUnreachable\000"
2200 /* 7962 */ "OpVariable\000"
2201 /* 7973 */ "OpGroupNonUniformShuffle\000"
2202 /* 7998 */ "OpVectorShuffle\000"
2203 /* 8014 */ "OpName\000"
2204 /* 8021 */ "OpMemberName\000"
2205 /* 8034 */ "OpFwidthFine\000"
2206 /* 8047 */ "OpDPdxFine\000"
2207 /* 8058 */ "OpDPdyFine\000"
2208 /* 8069 */ "OpNoLine\000"
2209 /* 8078 */ "OpLine\000"
2210 /* 8085 */ "OpTypePipe\000"
2211 /* 8096 */ "UNKNOWN_type\000"
2212 /* 8109 */ "OpAtomicStore\000"
2213 /* 8123 */ "OpStore\000"
2214 /* 8131 */ "OpSpecConstantFalse\000"
2215 /* 8151 */ "OpConstantFalse\000"
2216 /* 8167 */ "OpTranspose\000"
2217 /* 8179 */ "OpFwidthCoarse\000"
2218 /* 8194 */ "OpDPdxCoarse\000"
2219 /* 8207 */ "OpDPdyCoarse\000"
2220 /* 8220 */ "OpBitReverse\000"
2221 /* 8233 */ "OpFNegate\000"
2222 /* 8243 */ "OpSNegate\000"
2223 /* 8253 */ "OpDecorate\000"
2224 /* 8264 */ "OpMemberDecorate\000"
2225 /* 8281 */ "OpIsFinite\000"
2226 /* 8292 */ "OpImageWrite\000"
2227 /* 8305 */ "OpSpecConstantComposite\000"
2228 /* 8329 */ "OpConstantComposite\000"
2229 /* 8349 */ "OpTypeQueue\000"
2230 /* 8361 */ "OpGetDefaultQueue\000"
2231 /* 8379 */ "OpReturnValue\000"
2232 /* 8393 */ "OpTypeOpaque\000"
2233 /* 8406 */ "OpSpecConstantTrue\000"
2234 /* 8425 */ "OpConstantTrue\000"
2235 /* 8440 */ "OpEndPrimitive\000"
2236 /* 8455 */ "OpEndStreamPrimitive\000"
2237 /* 8476 */ "OpImageQuerySize\000"
2238 /* 8493 */ "OpNamedBarrierInitialize\000"
2239 /* 8518 */ "OpSizeOf\000"
2240 /* 8527 */ "OpUndef\000"
2241 /* 8535 */ "OpPtrDiff\000"
2242 /* 8545 */ "OpIsInf\000"
2243 /* 8553 */ "OpDecorateString\000"
2244 /* 8570 */ "OpMemberDecorateString\000"
2245 /* 8593 */ "OpString\000"
2246 /* 8602 */ "OpBranch\000"
2247 /* 8611 */ "OpImageFetch\000"
2248 /* 8624 */ "OpImageSparseFetch\000"
2249 /* 8643 */ "OpSwitch\000"
2250 /* 8652 */ "OpFwidth\000"
2251 /* 8661 */ "OpArrayLength\000"
2252 /* 8675 */ "OpPhi\000"
2253 /* 8681 */ "OpAtomicCompareExchangeWeak\000"
2254 /* 8709 */ "OpCopyLogical\000"
2255 /* 8723 */ "OpIsNormal\000"
2256 /* 8734 */ "OpBranchConditional\000"
2257 /* 8754 */ "OpIEqual\000"
2258 /* 8763 */ "OpFOrdEqual\000"
2259 /* 8775 */ "OpFUnordEqual\000"
2260 /* 8789 */ "OpLogicalEqual\000"
2261 /* 8804 */ "OpGroupNonUniformAllEqual\000"
2262 /* 8830 */ "OpSGreaterThanEqual\000"
2263 /* 8850 */ "OpUGreaterThanEqual\000"
2264 /* 8870 */ "OpFOrdGreaterThanEqual\000"
2265 /* 8893 */ "OpFUnordGreaterThanEqual\000"
2266 /* 8918 */ "OpSLessThanEqual\000"
2267 /* 8935 */ "OpULessThanEqual\000"
2268 /* 8952 */ "OpFOrdLessThanEqual\000"
2269 /* 8972 */ "OpFUnordLessThanEqual\000"
2270 /* 8994 */ "OpPtrEqual\000"
2271 /* 9005 */ "OpINotEqual\000"
2272 /* 9017 */ "OpFOrdNotEqual\000"
2273 /* 9032 */ "OpFUnordNotEqual\000"
2274 /* 9049 */ "OpLogicalNotEqual\000"
2275 /* 9067 */ "OpPtrNotEqual\000"
2276 /* 9081 */ "OpLabel\000"
2277 /* 9089 */ "OpMemoryModel\000"
2278 /* 9103 */ "OpEnqueueKernel\000"
2279 /* 9119 */ "OpGroupNonUniformAll\000"
2280 /* 9140 */ "OpAll\000"
2281 /* 9146 */ "OpGroupAll\000"
2282 /* 9157 */ "OpFunctionCall\000"
2283 /* 9172 */ "OpKill\000"
2284 /* 9179 */ "OpConstantNull\000"
2285 /* 9194 */ "OpTypeBool\000"
2286 /* 9205 */ "OpGroupNonUniformFMul\000"
2287 /* 9227 */ "OpGroupNonUniformIMul\000"
2288 /* 9249 */ "OpIsNan\000"
2289 /* 9257 */ "OpSGreaterThan\000"
2290 /* 9272 */ "OpUGreaterThan\000"
2291 /* 9287 */ "OpFOrdGreaterThan\000"
2292 /* 9305 */ "OpFUnordGreaterThan\000"
2293 /* 9325 */ "OpSLessThan\000"
2294 /* 9337 */ "OpULessThan\000"
2295 /* 9349 */ "OpFOrdLessThan\000"
2296 /* 9364 */ "OpFUnordLessThan\000"
2297 /* 9381 */ "OpGroupNonUniformFMin\000"
2298 /* 9403 */ "OpGroupFMin\000"
2299 /* 9415 */ "OpAtomicSMin\000"
2300 /* 9428 */ "OpGroupNonUniformSMin\000"
2301 /* 9450 */ "OpGroupSMin\000"
2302 /* 9462 */ "OpAtomicUMin\000"
2303 /* 9475 */ "OpGroupNonUniformUMin\000"
2304 /* 9497 */ "OpGroupUMin\000"
2305 /* 9509 */ "OpAccessChain\000"
2306 /* 9523 */ "OpPtrAccessChain\000"
2307 /* 9540 */ "OpInBoundsPtrAccessChain\000"
2308 /* 9565 */ "OpInBoundsAccessChain\000"
2309 /* 9587 */ "OpSourceExtension\000"
2310 /* 9605 */ "OpExtension\000"
2311 /* 9617 */ "OpDemoteToHelperInvocation\000"
2312 /* 9644 */ "OpTypeFunction\000"
2313 /* 9659 */ "OpFunction\000"
2314 /* 9670 */ "OpReturn\000"
2315 /* 9679 */ "OpGroupNonUniformShuffleDown\000"
2316 /* 9708 */ "OpCaptureEventProfilingInfo\000"
2317 /* 9736 */ "OpSpecConstantOp\000"
2318 /* 9753 */ "OpGroupNonUniformShuffleUp\000"
2319 /* 9780 */ "OpNop\000"
2320 /* 9786 */ "OpLifetimeStop\000"
2321 /* 9801 */ "OpAtomicOr\000"
2322 /* 9812 */ "OpGroupNonUniformBitwiseOr\000"
2323 /* 9839 */ "OpGroupNonUniformLogicalOr\000"
2324 /* 9866 */ "OpLogicalOr\000"
2325 /* 9878 */ "OpAtomicFlagClear\000"
2326 /* 9896 */ "OpVectorTimesScalar\000"
2327 /* 9916 */ "OpMatrixTimesScalar\000"
2328 /* 9936 */ "OpImageQueryOrder\000"
2329 /* 9954 */ "OpImageGather\000"
2330 /* 9968 */ "OpImageSparseGather\000"
2331 /* 9988 */ "OpImageDrefGather\000"
2332 /* 10006 */ "OpImageSparseDrefGather\000"
2333 /* 10030 */ "OpTypeNamedBarrier\000"
2334 /* 10049 */ "OpMemoryNamedBarrier\000"
2335 /* 10070 */ "OpControlBarrier\000"
2336 /* 10087 */ "OpMemoryBarrier\000"
2337 /* 10103 */ "OpTypeSampler\000"
2338 /* 10117 */ "OpConstantSampler\000"
2339 /* 10135 */ "OpLessOrGreater\000"
2340 /* 10151 */ "OpFunctionParameter\000"
2341 /* 10171 */ "OpTypeForwardPointer\000"
2342 /* 10192 */ "OpTypePointer\000"
2343 /* 10206 */ "OpImageTexelPointer\000"
2344 /* 10226 */ "OpAtomicXor\000"
2345 /* 10238 */ "OpGroupNonUniformShuffleXor\000"
2346 /* 10266 */ "OpGroupNonUniformBitwiseXor\000"
2347 /* 10294 */ "OpGroupNonUniformLogicalXor\000"
2348 /* 10322 */ "OpTypeVector\000"
2349 /* 10335 */ "OpMatrixTimesVector\000"
2350 /* 10355 */ "OpConvertUToPtr\000"
2351 /* 10371 */ "OpGenericCastToPtr\000"
2352 /* 10390 */ "OpGenericPtrMemSemantics\000"
2353 /* 10415 */ "OpImageQuerySamples\000"
2354 /* 10435 */ "OpImageQueryLevels\000"
2355 /* 10454 */ "OpGroupWaitEvents\000"
2356 /* 10472 */ "OpSetUserEventStatus\000"
2357 /* 10493 */ "OpSDotAccSat\000"
2358 /* 10506 */ "OpSUDotAccSat\000"
2359 /* 10520 */ "OpUDotAccSat\000"
2360 /* 10533 */ "OpImageQueryFormat\000"
2361 /* 10552 */ "OpTypeFloat\000"
2362 /* 10564 */ "OpBitFieldSExtract\000"
2363 /* 10583 */ "OpBitFieldUExtract\000"
2364 /* 10602 */ "OpCompositeExtract\000"
2365 /* 10621 */ "OpGroupNonUniformBallotBitExtract\000"
2366 /* 10655 */ "OpCopyObject\000"
2367 /* 10668 */ "OpGroupNonUniformElect\000"
2368 /* 10691 */ "OpOuterProduct\000"
2369 /* 10706 */ "OpTypeStruct\000"
2370 /* 10719 */ "OpCompositeConstruct\000"
2371 /* 10740 */ "OpAtomicFlagTestAndSet\000"
2372 /* 10763 */ "OpSignBitSet\000"
2373 /* 10776 */ "OpGenericCastToPtrExplicit\000"
2374 /* 10803 */ "OpTypeInt\000"
2375 /* 10813 */ "OpSpecConstant\000"
2376 /* 10828 */ "OpImageSparseTexelsResident\000"
2377 /* 10856 */ "OpAtomicIDecrement\000"
2378 /* 10875 */ "OpAtomicIIncrement\000"
2379 /* 10894 */ "OpIsValidEvent\000"
2380 /* 10909 */ "OpTypeDeviceEvent\000"
2381 /* 10927 */ "OpTypeEvent\000"
2382 /* 10939 */ "OpReleaseEvent\000"
2383 /* 10954 */ "OpRetainEvent\000"
2384 /* 10968 */ "OpCreateUserEvent\000"
2385 /* 10986 */ "OpEntryPoint\000"
2386 /* 10999 */ "OpBitCount\000"
2387 /* 11010 */ "OpGroupNonUniformBallotBitCount\000"
2388 /* 11042 */ "OpSDot\000"
2389 /* 11049 */ "OpSUDot\000"
2390 /* 11057 */ "OpUDot\000"
2391 /* 11064 */ "OpDot\000"
2392 /* 11070 */ "OpLogicalNot\000"
2393 /* 11083 */ "OpNot\000"
2394 /* 11089 */ "OpGroupNonUniformInverseBallot\000"
2395 /* 11120 */ "OpGroupNonUniformBallot\000"
2396 /* 11144 */ "OpLifetimeStart\000"
2397 /* 11160 */ "OpBitFieldInsert\000"
2398 /* 11177 */ "OpCompositeInsert\000"
2399 /* 11195 */ "OpFConvert\000"
2400 /* 11206 */ "OpSConvert\000"
2401 /* 11217 */ "OpUConvert\000"
2402 /* 11228 */ "OpExtInstImport\000"
2403 /* 11244 */ "OpGroupNonUniformBroadcast\000"
2404 /* 11271 */ "OpGroupBroadcast\000"
2405 /* 11288 */ "OpBitcast\000"
2406 /* 11298 */ "OpExtInst\000"
2407 /* 11308 */ "OpGroupNonUniformBroadcastFirst\000"
2408 /* 11340 */ "OpGroupNonUniformFMax\000"
2409 /* 11362 */ "OpGroupFMax\000"
2410 /* 11374 */ "OpAtomicSMax\000"
2411 /* 11387 */ "OpGroupNonUniformSMax\000"
2412 /* 11409 */ "OpGroupSMax\000"
2413 /* 11421 */ "OpAtomicUMax\000"
2414 /* 11434 */ "OpGroupNonUniformUMax\000"
2415 /* 11456 */ "OpGroupUMax\000"
2416 /* 11468 */ "OpDPdx\000"
2417 /* 11475 */ "OpEmitStreamVertex\000"
2418 /* 11494 */ "OpEmitVertex\000"
2419 /* 11507 */ "OpTypeMatrix\000"
2420 /* 11520 */ "OpVectorTimesMatrix\000"
2421 /* 11540 */ "OpMatrixTimesMatrix\000"
2422 /* 11560 */ "OpTypeRuntimeArray\000"
2423 /* 11579 */ "OpTypeArray\000"
2424 /* 11591 */ "OpDPdy\000"
2425 /* 11598 */ "OpGroupNonUniformAny\000"
2426 /* 11619 */ "OpAny\000"
2427 /* 11625 */ "OpGroupAny\000"
2428 /* 11636 */ "OpGroupAsyncCopy\000"
2429 /* 11653 */ "OpCopyMemory\000"
2430 /* 11666 */ "OpCapability\000"
2431};
2432#ifdef __GNUC__
2433#pragma GCC diagnostic pop
2434#endif
2435
2436extern const unsigned SPIRVInstrNameIndices[] = {
2437 1374U, 3073U, 3782U, 3431U, 1445U, 1426U, 1454U, 2909U,
2438 1197U, 1212U, 1123U, 1110U, 1239U, 4642U, 958U, 5644U,
2439 1136U, 1370U, 1435U, 727U, 6504U, 849U, 5548U, 554U,
2440 678U, 715U, 3525U, 2897U, 5458U, 661U, 3717U, 1302U,
2441 5447U, 872U, 3705U, 3692U, 3843U, 5306U, 5329U, 2829U,
2442 2876U, 2849U, 1471U, 949U, 3808U, 3479U, 6509U, 4325U,
2443 3663U, 1006U, 5674U, 5704U, 3274U, 467U, 178U, 3012U,
2444 5862U, 5869U, 3039U, 3046U, 3053U, 3063U, 532U, 4510U,
2445 4473U, 4561U, 5787U, 1121U, 1372U, 6427U, 968U, 983U,
2446 2914U, 5274U, 4568U, 5585U, 4585U, 4396U, 248U, 4625U,
2447 5469U, 4537U, 5617U, 1049U, 3819U, 635U, 222U, 617U,
2448 5507U, 5488U, 3252U, 3868U, 3887U, 368U, 312U, 342U,
2449 353U, 293U, 323U, 928U, 912U, 4672U, 1253U, 1270U,
2450 483U, 184U, 538U, 499U, 4515U, 4479U, 6411U, 3400U,
2451 6394U, 3383U, 434U, 161U, 6329U, 3318U, 3168U, 3115U,
2452 3587U, 3565U, 576U, 5227U, 707U, 1319U, 567U, 5293U,
2453 5563U, 200U, 4720U, 5424U, 4747U, 5688U, 240U, 5413U,
2454 5401U, 5538U, 1294U, 5667U, 1226U, 5697U, 2815U, 4318U,
2455 4304U, 2808U, 4311U, 4530U, 2930U, 3642U, 3635U, 3649U,
2456 3656U, 5284U, 3471U, 748U, 3455U, 699U, 3463U, 740U,
2457 3447U, 691U, 3509U, 3501U, 1338U, 1330U, 5145U, 5135U,
2458 5125U, 5115U, 5165U, 5155U, 6455U, 6465U, 5175U, 5188U,
2459 6475U, 6485U, 5201U, 5214U, 392U, 140U, 2954U, 59U,
2460 286U, 5841U, 3018U, 6305U, 1396U, 3761U, 35U, 9U,
2461 1287U, 18U, 0U, 3736U, 3768U, 1190U, 5659U, 212U,
2462 1378U, 1387U, 3617U, 3626U, 5248U, 5261U, 4548U, 3289U,
2463 4659U, 1058U, 3217U, 3227U, 797U, 812U, 3104U, 3157U,
2464 3189U, 3203U, 5876U, 5902U, 5888U, 756U, 784U, 769U,
2465 473U, 1416U, 3352U, 6363U, 3376U, 6387U, 4555U, 608U,
2466 598U, 3777U, 5353U, 827U, 4377U, 4357U, 5381U, 5360U,
2467 4411U, 4442U, 4428U, 4702U, 6538U, 1092U, 6531U, 1074U,
2468 3684U, 3609U, 936U, 2821U, 4608U, 3424U, 4615U, 3245U,
2469 4600U, 3416U, 3237U, 26U, 1362U, 1354U, 1346U, 5594U,
2470 4348U, 5480U, 5525U, 5627U, 3795U, 836U, 269U, 1027U,
2471 897U, 420U, 147U, 2982U, 5848U, 3025U, 65U, 5602U,
2472 3745U, 3907U, 3923U, 6495U, 856U, 1039U, 5320U, 3517U,
2473 3558U, 3534U, 3546U, 399U, 2961U, 375U, 2937U, 6312U,
2474 3301U, 3136U, 3083U, 451U, 2996U, 516U, 4495U, 4457U,
2475 6346U, 3335U, 6370U, 3359U, 6441U, 6448U, 885U, 8096U,
2476 9509U, 2337U, 2315U, 2360U, 9140U, 11619U, 5734U, 8661U,
2477 2386U, 2464U, 2699U, 4093U, 6917U, 7895U, 8681U, 7878U,
2478 5718U, 5771U, 5755U, 9878U, 10740U, 6753U, 10856U, 10875U,
2479 6545U, 6699U, 9801U, 11374U, 9415U, 8109U, 11421U, 9462U,
2480 10226U, 10999U, 11160U, 10564U, 10583U, 8220U, 11288U, 4869U,
2481 6079U, 2475U, 5023U, 6213U, 5036U, 6226U, 8602U, 8734U,
2482 7863U, 11666U, 9708U, 10719U, 1865U, 10602U, 11177U, 8329U,
2483 1804U, 1178U, 8151U, 2611U, 1404U, 9179U, 10117U, 8425U,
2484 10070U, 2223U, 2716U, 1513U, 1491U, 4992U, 5794U, 1975U,
2485 1940U, 2581U, 5825U, 1150U, 1164U, 10355U, 1725U, 1900U,
2486 4109U, 1652U, 3940U, 3967U, 2282U, 1688U, 4038U, 8709U,
2487 11653U, 6888U, 10655U, 10968U, 2668U, 11468U, 8194U, 8047U,
2488 11591U, 8207U, 8058U, 8253U, 6640U, 8553U, 9617U, 11064U,
2489 11475U, 11494U, 8440U, 8455U, 9103U, 10986U, 7775U, 6622U,
2490 4265U, 11298U, 11228U, 9605U, 4839U, 6049U, 11195U, 5050U,
2491 6240U, 7752U, 4932U, 6153U, 8233U, 6101U, 8763U, 9287U,
2492 8870U, 9349U, 8952U, 9017U, 4962U, 6183U, 4785U, 5995U,
2493 8775U, 9305U, 8893U, 9364U, 8972U, 9032U, 9659U, 9157U,
2494 6998U, 10151U, 2401U, 8652U, 8179U, 8034U, 10371U, 10776U,
2495 10390U, 8361U, 9146U, 11625U, 11636U, 3996U, 4183U, 4223U,
2496 11271U, 6741U, 11362U, 9403U, 4153U, 6788U, 4168U, 4017U,
2497 4203U, 4244U, 9119U, 8804U, 11598U, 11120U, 11010U, 10621U,
2498 78U, 109U, 6929U, 9812U, 10266U, 11244U, 11308U, 10668U,
2499 6719U, 11340U, 9381U, 9205U, 6766U, 9227U, 11089U, 6957U,
2500 9839U, 10294U, 4066U, 11387U, 9428U, 7973U, 9679U, 9753U,
2501 10238U, 11434U, 9475U, 11409U, 9450U, 11456U, 9497U, 10454U,
2502 5102U, 6292U, 4861U, 6071U, 8754U, 4954U, 6175U, 9005U,
2503 5088U, 6278U, 4807U, 6017U, 7837U, 9988U, 8611U, 9954U,
2504 10533U, 10435U, 7736U, 9936U, 10415U, 8476U, 7204U, 6669U,
2505 7536U, 7280U, 7480U, 5944U, 7224U, 7600U, 7344U, 7672U,
2506 7416U, 10006U, 8624U, 9968U, 6681U, 7565U, 7309U, 7505U,
2507 7249U, 7633U, 7377U, 7701U, 7445U, 10828U, 10206U, 8292U,
2508 9565U, 9540U, 8281U, 8545U, 9249U, 8723U, 10894U, 9172U,
2509 9081U, 10135U, 11144U, 9786U, 8078U, 6712U, 6985U, 8789U,
2510 11070U, 9049U, 9866U, 7936U, 11540U, 9916U, 10335U, 8264U,
2511 8570U, 8021U, 10087U, 9089U, 10049U, 6852U, 8014U, 8493U,
2512 8069U, 9780U, 11083U, 6830U, 10691U, 8675U, 9523U, 2550U,
2513 6603U, 8535U, 8994U, 9067U, 43U, 4138U, 10939U, 2769U,
2514 10954U, 9670U, 8379U, 11206U, 5072U, 6262U, 11042U, 10493U,
2515 9257U, 8830U, 9325U, 8918U, 7759U, 6800U, 8243U, 4984U,
2516 6205U, 11049U, 10506U, 7810U, 5808U, 5006U, 2790U, 7012U,
2517 7108U, 7044U, 7140U, 7076U, 7172U, 7028U, 7124U, 7060U,
2518 7156U, 7092U, 7188U, 7919U, 10472U, 4891U, 6112U, 4815U,
2519 6025U, 4911U, 6132U, 10763U, 8518U, 7766U, 6870U, 9587U,
2520 10813U, 8305U, 1766U, 8131U, 9736U, 8406U, 8123U, 4847U,
2521 6057U, 5058U, 6248U, 4940U, 6161U, 4970U, 6191U, 4793U,
2522 6003U, 8593U, 1625U, 2428U, 2054U, 2251U, 2026U, 1600U,
2523 2197U, 1570U, 2166U, 1535U, 2130U, 2090U, 2498U, 2003U,
2524 2525U, 2642U, 8643U, 8167U, 5914U, 11579U, 9194U, 4277U,
2525 5969U, 10909U, 10927U, 10552U, 10171U, 9644U, 7825U, 10803U,
2526 11507U, 10030U, 8393U, 8085U, 7845U, 10192U, 8349U, 6653U,
2527 11560U, 7791U, 10103U, 10706U, 1838U, 10322U, 6906U, 11217U,
2528 5080U, 6270U, 11057U, 10520U, 9272U, 8850U, 9337U, 8935U,
2529 4883U, 6093U, 6815U, 8527U, 6840U, 7948U, 7962U, 2742U,
2530 6558U, 6581U, 7998U, 11520U, 9896U,
2531};
2532
2533static inline void InitSPIRVMCInstrInfo(MCInstrInfo *II) {
2534 II->InitMCInstrInfo(SPIRVDescs.Insts, SPIRVInstrNameIndices, SPIRVInstrNameData, nullptr, nullptr, 749);
2535}
2536
2537} // end namespace llvm
2538#endif // GET_INSTRINFO_MC_DESC
2539
2540#ifdef GET_INSTRINFO_HEADER
2541#undef GET_INSTRINFO_HEADER
2542namespace llvm {
2543struct SPIRVGenInstrInfo : public TargetInstrInfo {
2544 explicit SPIRVGenInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
2545 ~SPIRVGenInstrInfo() override = default;
2546
2547};
2548} // end namespace llvm
2549#endif // GET_INSTRINFO_HEADER
2550
2551#ifdef GET_INSTRINFO_HELPER_DECLS
2552#undef GET_INSTRINFO_HELPER_DECLS
2553
2554
2555#endif // GET_INSTRINFO_HELPER_DECLS
2556
2557#ifdef GET_INSTRINFO_HELPERS
2558#undef GET_INSTRINFO_HELPERS
2559
2560#endif // GET_INSTRINFO_HELPERS
2561
2562#ifdef GET_INSTRINFO_CTOR_DTOR
2563#undef GET_INSTRINFO_CTOR_DTOR
2564namespace llvm {
2565extern const SPIRVInstrTable SPIRVDescs;
2566extern const unsigned SPIRVInstrNameIndices[];
2567extern const char SPIRVInstrNameData[];
2568SPIRVGenInstrInfo::SPIRVGenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
2569 : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
2570 InitMCInstrInfo(SPIRVDescs.Insts, SPIRVInstrNameIndices, SPIRVInstrNameData, nullptr, nullptr, 749);
2571}
2572} // end namespace llvm
2573#endif // GET_INSTRINFO_CTOR_DTOR
2574
2575#ifdef GET_INSTRINFO_MC_HELPER_DECLS
2576#undef GET_INSTRINFO_MC_HELPER_DECLS
2577
2578namespace llvm {
2579class MCInst;
2580class FeatureBitset;
2581
2582namespace SPIRV_MC {
2583
2584void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
2585
2586} // end namespace SPIRV_MC
2587} // end namespace llvm
2588
2589#endif // GET_INSTRINFO_MC_HELPER_DECLS
2590
2591#ifdef GET_INSTRINFO_MC_HELPERS
2592#undef GET_INSTRINFO_MC_HELPERS
2593
2594namespace llvm::SPIRV_MC {
2595} // end namespace llvm::SPIRV_MC
2596#endif // GET_GENISTRINFO_MC_HELPERS
2597
2598#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
2599 defined(GET_AVAILABLE_OPCODE_CHECKER)
2600#define GET_COMPUTE_FEATURES
2601#endif
2602#ifdef GET_COMPUTE_FEATURES
2603#undef GET_COMPUTE_FEATURES
2604namespace llvm::SPIRV_MC {
2605// Bits for subtarget features that participate in instruction matching.
2606enum SubtargetFeatureBits : uint8_t {
2607};
2608
2609inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
2610 FeatureBitset Features;
2611 return Features;
2612}
2613
2614inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
2615 enum : uint8_t {
2616 CEFBS_None,
2617 };
2618
2619 static constexpr FeatureBitset FeatureBitsets[] = {
2620 {}, // CEFBS_None
2621 };
2622 static constexpr uint8_t RequiredFeaturesRefs[] = {
2623 CEFBS_None, // PHI = 0
2624 CEFBS_None, // INLINEASM = 1
2625 CEFBS_None, // INLINEASM_BR = 2
2626 CEFBS_None, // CFI_INSTRUCTION = 3
2627 CEFBS_None, // EH_LABEL = 4
2628 CEFBS_None, // GC_LABEL = 5
2629 CEFBS_None, // ANNOTATION_LABEL = 6
2630 CEFBS_None, // KILL = 7
2631 CEFBS_None, // EXTRACT_SUBREG = 8
2632 CEFBS_None, // INSERT_SUBREG = 9
2633 CEFBS_None, // IMPLICIT_DEF = 10
2634 CEFBS_None, // INIT_UNDEF = 11
2635 CEFBS_None, // SUBREG_TO_REG = 12
2636 CEFBS_None, // COPY_TO_REGCLASS = 13
2637 CEFBS_None, // DBG_VALUE = 14
2638 CEFBS_None, // DBG_VALUE_LIST = 15
2639 CEFBS_None, // DBG_INSTR_REF = 16
2640 CEFBS_None, // DBG_PHI = 17
2641 CEFBS_None, // DBG_LABEL = 18
2642 CEFBS_None, // REG_SEQUENCE = 19
2643 CEFBS_None, // COPY = 20
2644 CEFBS_None, // BUNDLE = 21
2645 CEFBS_None, // LIFETIME_START = 22
2646 CEFBS_None, // LIFETIME_END = 23
2647 CEFBS_None, // PSEUDO_PROBE = 24
2648 CEFBS_None, // ARITH_FENCE = 25
2649 CEFBS_None, // STACKMAP = 26
2650 CEFBS_None, // FENTRY_CALL = 27
2651 CEFBS_None, // PATCHPOINT = 28
2652 CEFBS_None, // LOAD_STACK_GUARD = 29
2653 CEFBS_None, // PREALLOCATED_SETUP = 30
2654 CEFBS_None, // PREALLOCATED_ARG = 31
2655 CEFBS_None, // STATEPOINT = 32
2656 CEFBS_None, // LOCAL_ESCAPE = 33
2657 CEFBS_None, // FAULTING_OP = 34
2658 CEFBS_None, // PATCHABLE_OP = 35
2659 CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 36
2660 CEFBS_None, // PATCHABLE_RET = 37
2661 CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 38
2662 CEFBS_None, // PATCHABLE_TAIL_CALL = 39
2663 CEFBS_None, // PATCHABLE_EVENT_CALL = 40
2664 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 41
2665 CEFBS_None, // ICALL_BRANCH_FUNNEL = 42
2666 CEFBS_None, // FAKE_USE = 43
2667 CEFBS_None, // MEMBARRIER = 44
2668 CEFBS_None, // JUMP_TABLE_DEBUG_INFO = 45
2669 CEFBS_None, // CONVERGENCECTRL_ENTRY = 46
2670 CEFBS_None, // CONVERGENCECTRL_ANCHOR = 47
2671 CEFBS_None, // CONVERGENCECTRL_LOOP = 48
2672 CEFBS_None, // CONVERGENCECTRL_GLUE = 49
2673 CEFBS_None, // G_ASSERT_SEXT = 50
2674 CEFBS_None, // G_ASSERT_ZEXT = 51
2675 CEFBS_None, // G_ASSERT_ALIGN = 52
2676 CEFBS_None, // G_ADD = 53
2677 CEFBS_None, // G_SUB = 54
2678 CEFBS_None, // G_MUL = 55
2679 CEFBS_None, // G_SDIV = 56
2680 CEFBS_None, // G_UDIV = 57
2681 CEFBS_None, // G_SREM = 58
2682 CEFBS_None, // G_UREM = 59
2683 CEFBS_None, // G_SDIVREM = 60
2684 CEFBS_None, // G_UDIVREM = 61
2685 CEFBS_None, // G_AND = 62
2686 CEFBS_None, // G_OR = 63
2687 CEFBS_None, // G_XOR = 64
2688 CEFBS_None, // G_ABDS = 65
2689 CEFBS_None, // G_ABDU = 66
2690 CEFBS_None, // G_IMPLICIT_DEF = 67
2691 CEFBS_None, // G_PHI = 68
2692 CEFBS_None, // G_FRAME_INDEX = 69
2693 CEFBS_None, // G_GLOBAL_VALUE = 70
2694 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE = 71
2695 CEFBS_None, // G_CONSTANT_POOL = 72
2696 CEFBS_None, // G_EXTRACT = 73
2697 CEFBS_None, // G_UNMERGE_VALUES = 74
2698 CEFBS_None, // G_INSERT = 75
2699 CEFBS_None, // G_MERGE_VALUES = 76
2700 CEFBS_None, // G_BUILD_VECTOR = 77
2701 CEFBS_None, // G_BUILD_VECTOR_TRUNC = 78
2702 CEFBS_None, // G_CONCAT_VECTORS = 79
2703 CEFBS_None, // G_PTRTOINT = 80
2704 CEFBS_None, // G_INTTOPTR = 81
2705 CEFBS_None, // G_BITCAST = 82
2706 CEFBS_None, // G_FREEZE = 83
2707 CEFBS_None, // G_CONSTANT_FOLD_BARRIER = 84
2708 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND = 85
2709 CEFBS_None, // G_INTRINSIC_TRUNC = 86
2710 CEFBS_None, // G_INTRINSIC_ROUND = 87
2711 CEFBS_None, // G_INTRINSIC_LRINT = 88
2712 CEFBS_None, // G_INTRINSIC_LLRINT = 89
2713 CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 90
2714 CEFBS_None, // G_READCYCLECOUNTER = 91
2715 CEFBS_None, // G_READSTEADYCOUNTER = 92
2716 CEFBS_None, // G_LOAD = 93
2717 CEFBS_None, // G_SEXTLOAD = 94
2718 CEFBS_None, // G_ZEXTLOAD = 95
2719 CEFBS_None, // G_INDEXED_LOAD = 96
2720 CEFBS_None, // G_INDEXED_SEXTLOAD = 97
2721 CEFBS_None, // G_INDEXED_ZEXTLOAD = 98
2722 CEFBS_None, // G_STORE = 99
2723 CEFBS_None, // G_INDEXED_STORE = 100
2724 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 101
2725 CEFBS_None, // G_ATOMIC_CMPXCHG = 102
2726 CEFBS_None, // G_ATOMICRMW_XCHG = 103
2727 CEFBS_None, // G_ATOMICRMW_ADD = 104
2728 CEFBS_None, // G_ATOMICRMW_SUB = 105
2729 CEFBS_None, // G_ATOMICRMW_AND = 106
2730 CEFBS_None, // G_ATOMICRMW_NAND = 107
2731 CEFBS_None, // G_ATOMICRMW_OR = 108
2732 CEFBS_None, // G_ATOMICRMW_XOR = 109
2733 CEFBS_None, // G_ATOMICRMW_MAX = 110
2734 CEFBS_None, // G_ATOMICRMW_MIN = 111
2735 CEFBS_None, // G_ATOMICRMW_UMAX = 112
2736 CEFBS_None, // G_ATOMICRMW_UMIN = 113
2737 CEFBS_None, // G_ATOMICRMW_FADD = 114
2738 CEFBS_None, // G_ATOMICRMW_FSUB = 115
2739 CEFBS_None, // G_ATOMICRMW_FMAX = 116
2740 CEFBS_None, // G_ATOMICRMW_FMIN = 117
2741 CEFBS_None, // G_ATOMICRMW_FMAXIMUM = 118
2742 CEFBS_None, // G_ATOMICRMW_FMINIMUM = 119
2743 CEFBS_None, // G_ATOMICRMW_UINC_WRAP = 120
2744 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP = 121
2745 CEFBS_None, // G_ATOMICRMW_USUB_COND = 122
2746 CEFBS_None, // G_ATOMICRMW_USUB_SAT = 123
2747 CEFBS_None, // G_FENCE = 124
2748 CEFBS_None, // G_PREFETCH = 125
2749 CEFBS_None, // G_BRCOND = 126
2750 CEFBS_None, // G_BRINDIRECT = 127
2751 CEFBS_None, // G_INVOKE_REGION_START = 128
2752 CEFBS_None, // G_INTRINSIC = 129
2753 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 130
2754 CEFBS_None, // G_INTRINSIC_CONVERGENT = 131
2755 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 132
2756 CEFBS_None, // G_ANYEXT = 133
2757 CEFBS_None, // G_TRUNC = 134
2758 CEFBS_None, // G_CONSTANT = 135
2759 CEFBS_None, // G_FCONSTANT = 136
2760 CEFBS_None, // G_VASTART = 137
2761 CEFBS_None, // G_VAARG = 138
2762 CEFBS_None, // G_SEXT = 139
2763 CEFBS_None, // G_SEXT_INREG = 140
2764 CEFBS_None, // G_ZEXT = 141
2765 CEFBS_None, // G_SHL = 142
2766 CEFBS_None, // G_LSHR = 143
2767 CEFBS_None, // G_ASHR = 144
2768 CEFBS_None, // G_FSHL = 145
2769 CEFBS_None, // G_FSHR = 146
2770 CEFBS_None, // G_ROTR = 147
2771 CEFBS_None, // G_ROTL = 148
2772 CEFBS_None, // G_ICMP = 149
2773 CEFBS_None, // G_FCMP = 150
2774 CEFBS_None, // G_SCMP = 151
2775 CEFBS_None, // G_UCMP = 152
2776 CEFBS_None, // G_SELECT = 153
2777 CEFBS_None, // G_UADDO = 154
2778 CEFBS_None, // G_UADDE = 155
2779 CEFBS_None, // G_USUBO = 156
2780 CEFBS_None, // G_USUBE = 157
2781 CEFBS_None, // G_SADDO = 158
2782 CEFBS_None, // G_SADDE = 159
2783 CEFBS_None, // G_SSUBO = 160
2784 CEFBS_None, // G_SSUBE = 161
2785 CEFBS_None, // G_UMULO = 162
2786 CEFBS_None, // G_SMULO = 163
2787 CEFBS_None, // G_UMULH = 164
2788 CEFBS_None, // G_SMULH = 165
2789 CEFBS_None, // G_UADDSAT = 166
2790 CEFBS_None, // G_SADDSAT = 167
2791 CEFBS_None, // G_USUBSAT = 168
2792 CEFBS_None, // G_SSUBSAT = 169
2793 CEFBS_None, // G_USHLSAT = 170
2794 CEFBS_None, // G_SSHLSAT = 171
2795 CEFBS_None, // G_SMULFIX = 172
2796 CEFBS_None, // G_UMULFIX = 173
2797 CEFBS_None, // G_SMULFIXSAT = 174
2798 CEFBS_None, // G_UMULFIXSAT = 175
2799 CEFBS_None, // G_SDIVFIX = 176
2800 CEFBS_None, // G_UDIVFIX = 177
2801 CEFBS_None, // G_SDIVFIXSAT = 178
2802 CEFBS_None, // G_UDIVFIXSAT = 179
2803 CEFBS_None, // G_FADD = 180
2804 CEFBS_None, // G_FSUB = 181
2805 CEFBS_None, // G_FMUL = 182
2806 CEFBS_None, // G_FMA = 183
2807 CEFBS_None, // G_FMAD = 184
2808 CEFBS_None, // G_FDIV = 185
2809 CEFBS_None, // G_FREM = 186
2810 CEFBS_None, // G_FPOW = 187
2811 CEFBS_None, // G_FPOWI = 188
2812 CEFBS_None, // G_FEXP = 189
2813 CEFBS_None, // G_FEXP2 = 190
2814 CEFBS_None, // G_FEXP10 = 191
2815 CEFBS_None, // G_FLOG = 192
2816 CEFBS_None, // G_FLOG2 = 193
2817 CEFBS_None, // G_FLOG10 = 194
2818 CEFBS_None, // G_FLDEXP = 195
2819 CEFBS_None, // G_FFREXP = 196
2820 CEFBS_None, // G_FNEG = 197
2821 CEFBS_None, // G_FPEXT = 198
2822 CEFBS_None, // G_FPTRUNC = 199
2823 CEFBS_None, // G_FPTOSI = 200
2824 CEFBS_None, // G_FPTOUI = 201
2825 CEFBS_None, // G_SITOFP = 202
2826 CEFBS_None, // G_UITOFP = 203
2827 CEFBS_None, // G_FPTOSI_SAT = 204
2828 CEFBS_None, // G_FPTOUI_SAT = 205
2829 CEFBS_None, // G_FABS = 206
2830 CEFBS_None, // G_FCOPYSIGN = 207
2831 CEFBS_None, // G_IS_FPCLASS = 208
2832 CEFBS_None, // G_FCANONICALIZE = 209
2833 CEFBS_None, // G_FMINNUM = 210
2834 CEFBS_None, // G_FMAXNUM = 211
2835 CEFBS_None, // G_FMINNUM_IEEE = 212
2836 CEFBS_None, // G_FMAXNUM_IEEE = 213
2837 CEFBS_None, // G_FMINIMUM = 214
2838 CEFBS_None, // G_FMAXIMUM = 215
2839 CEFBS_None, // G_FMINIMUMNUM = 216
2840 CEFBS_None, // G_FMAXIMUMNUM = 217
2841 CEFBS_None, // G_GET_FPENV = 218
2842 CEFBS_None, // G_SET_FPENV = 219
2843 CEFBS_None, // G_RESET_FPENV = 220
2844 CEFBS_None, // G_GET_FPMODE = 221
2845 CEFBS_None, // G_SET_FPMODE = 222
2846 CEFBS_None, // G_RESET_FPMODE = 223
2847 CEFBS_None, // G_PTR_ADD = 224
2848 CEFBS_None, // G_PTRMASK = 225
2849 CEFBS_None, // G_SMIN = 226
2850 CEFBS_None, // G_SMAX = 227
2851 CEFBS_None, // G_UMIN = 228
2852 CEFBS_None, // G_UMAX = 229
2853 CEFBS_None, // G_ABS = 230
2854 CEFBS_None, // G_LROUND = 231
2855 CEFBS_None, // G_LLROUND = 232
2856 CEFBS_None, // G_BR = 233
2857 CEFBS_None, // G_BRJT = 234
2858 CEFBS_None, // G_VSCALE = 235
2859 CEFBS_None, // G_INSERT_SUBVECTOR = 236
2860 CEFBS_None, // G_EXTRACT_SUBVECTOR = 237
2861 CEFBS_None, // G_INSERT_VECTOR_ELT = 238
2862 CEFBS_None, // G_EXTRACT_VECTOR_ELT = 239
2863 CEFBS_None, // G_SHUFFLE_VECTOR = 240
2864 CEFBS_None, // G_SPLAT_VECTOR = 241
2865 CEFBS_None, // G_STEP_VECTOR = 242
2866 CEFBS_None, // G_VECTOR_COMPRESS = 243
2867 CEFBS_None, // G_CTTZ = 244
2868 CEFBS_None, // G_CTTZ_ZERO_UNDEF = 245
2869 CEFBS_None, // G_CTLZ = 246
2870 CEFBS_None, // G_CTLZ_ZERO_UNDEF = 247
2871 CEFBS_None, // G_CTPOP = 248
2872 CEFBS_None, // G_BSWAP = 249
2873 CEFBS_None, // G_BITREVERSE = 250
2874 CEFBS_None, // G_FCEIL = 251
2875 CEFBS_None, // G_FCOS = 252
2876 CEFBS_None, // G_FSIN = 253
2877 CEFBS_None, // G_FSINCOS = 254
2878 CEFBS_None, // G_FTAN = 255
2879 CEFBS_None, // G_FACOS = 256
2880 CEFBS_None, // G_FASIN = 257
2881 CEFBS_None, // G_FATAN = 258
2882 CEFBS_None, // G_FATAN2 = 259
2883 CEFBS_None, // G_FCOSH = 260
2884 CEFBS_None, // G_FSINH = 261
2885 CEFBS_None, // G_FTANH = 262
2886 CEFBS_None, // G_FSQRT = 263
2887 CEFBS_None, // G_FFLOOR = 264
2888 CEFBS_None, // G_FRINT = 265
2889 CEFBS_None, // G_FNEARBYINT = 266
2890 CEFBS_None, // G_ADDRSPACE_CAST = 267
2891 CEFBS_None, // G_BLOCK_ADDR = 268
2892 CEFBS_None, // G_JUMP_TABLE = 269
2893 CEFBS_None, // G_DYN_STACKALLOC = 270
2894 CEFBS_None, // G_STACKSAVE = 271
2895 CEFBS_None, // G_STACKRESTORE = 272
2896 CEFBS_None, // G_STRICT_FADD = 273
2897 CEFBS_None, // G_STRICT_FSUB = 274
2898 CEFBS_None, // G_STRICT_FMUL = 275
2899 CEFBS_None, // G_STRICT_FDIV = 276
2900 CEFBS_None, // G_STRICT_FREM = 277
2901 CEFBS_None, // G_STRICT_FMA = 278
2902 CEFBS_None, // G_STRICT_FSQRT = 279
2903 CEFBS_None, // G_STRICT_FLDEXP = 280
2904 CEFBS_None, // G_READ_REGISTER = 281
2905 CEFBS_None, // G_WRITE_REGISTER = 282
2906 CEFBS_None, // G_MEMCPY = 283
2907 CEFBS_None, // G_MEMCPY_INLINE = 284
2908 CEFBS_None, // G_MEMMOVE = 285
2909 CEFBS_None, // G_MEMSET = 286
2910 CEFBS_None, // G_BZERO = 287
2911 CEFBS_None, // G_TRAP = 288
2912 CEFBS_None, // G_DEBUGTRAP = 289
2913 CEFBS_None, // G_UBSANTRAP = 290
2914 CEFBS_None, // G_VECREDUCE_SEQ_FADD = 291
2915 CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 292
2916 CEFBS_None, // G_VECREDUCE_FADD = 293
2917 CEFBS_None, // G_VECREDUCE_FMUL = 294
2918 CEFBS_None, // G_VECREDUCE_FMAX = 295
2919 CEFBS_None, // G_VECREDUCE_FMIN = 296
2920 CEFBS_None, // G_VECREDUCE_FMAXIMUM = 297
2921 CEFBS_None, // G_VECREDUCE_FMINIMUM = 298
2922 CEFBS_None, // G_VECREDUCE_ADD = 299
2923 CEFBS_None, // G_VECREDUCE_MUL = 300
2924 CEFBS_None, // G_VECREDUCE_AND = 301
2925 CEFBS_None, // G_VECREDUCE_OR = 302
2926 CEFBS_None, // G_VECREDUCE_XOR = 303
2927 CEFBS_None, // G_VECREDUCE_SMAX = 304
2928 CEFBS_None, // G_VECREDUCE_SMIN = 305
2929 CEFBS_None, // G_VECREDUCE_UMAX = 306
2930 CEFBS_None, // G_VECREDUCE_UMIN = 307
2931 CEFBS_None, // G_SBFX = 308
2932 CEFBS_None, // G_UBFX = 309
2933 CEFBS_None, // ASSIGN_TYPE = 310
2934 CEFBS_None, // UNKNOWN_type = 311
2935 CEFBS_None, // OpAccessChain = 312
2936 CEFBS_None, // OpAliasDomainDeclINTEL = 313
2937 CEFBS_None, // OpAliasScopeDeclINTEL = 314
2938 CEFBS_None, // OpAliasScopeListDeclINTEL = 315
2939 CEFBS_None, // OpAll = 316
2940 CEFBS_None, // OpAny = 317
2941 CEFBS_None, // OpArithmeticFenceEXT = 318
2942 CEFBS_None, // OpArrayLength = 319
2943 CEFBS_None, // OpAsmCallINTEL = 320
2944 CEFBS_None, // OpAsmINTEL = 321
2945 CEFBS_None, // OpAsmTargetINTEL = 322
2946 CEFBS_None, // OpAssumeTrueKHR = 323
2947 CEFBS_None, // OpAtomicAnd = 324
2948 CEFBS_None, // OpAtomicCompareExchange = 325
2949 CEFBS_None, // OpAtomicCompareExchangeWeak = 326
2950 CEFBS_None, // OpAtomicExchange = 327
2951 CEFBS_None, // OpAtomicFAddEXT = 328
2952 CEFBS_None, // OpAtomicFMaxEXT = 329
2953 CEFBS_None, // OpAtomicFMinEXT = 330
2954 CEFBS_None, // OpAtomicFlagClear = 331
2955 CEFBS_None, // OpAtomicFlagTestAndSet = 332
2956 CEFBS_None, // OpAtomicIAdd = 333
2957 CEFBS_None, // OpAtomicIDecrement = 334
2958 CEFBS_None, // OpAtomicIIncrement = 335
2959 CEFBS_None, // OpAtomicISub = 336
2960 CEFBS_None, // OpAtomicLoad = 337
2961 CEFBS_None, // OpAtomicOr = 338
2962 CEFBS_None, // OpAtomicSMax = 339
2963 CEFBS_None, // OpAtomicSMin = 340
2964 CEFBS_None, // OpAtomicStore = 341
2965 CEFBS_None, // OpAtomicUMax = 342
2966 CEFBS_None, // OpAtomicUMin = 343
2967 CEFBS_None, // OpAtomicXor = 344
2968 CEFBS_None, // OpBitCount = 345
2969 CEFBS_None, // OpBitFieldInsert = 346
2970 CEFBS_None, // OpBitFieldSExtract = 347
2971 CEFBS_None, // OpBitFieldUExtract = 348
2972 CEFBS_None, // OpBitReverse = 349
2973 CEFBS_None, // OpBitcast = 350
2974 CEFBS_None, // OpBitwiseAndS = 351
2975 CEFBS_None, // OpBitwiseAndV = 352
2976 CEFBS_None, // OpBitwiseFunctionINTEL = 353
2977 CEFBS_None, // OpBitwiseOrS = 354
2978 CEFBS_None, // OpBitwiseOrV = 355
2979 CEFBS_None, // OpBitwiseXorS = 356
2980 CEFBS_None, // OpBitwiseXorV = 357
2981 CEFBS_None, // OpBranch = 358
2982 CEFBS_None, // OpBranchConditional = 359
2983 CEFBS_None, // OpBuildNDRange = 360
2984 CEFBS_None, // OpCapability = 361
2985 CEFBS_None, // OpCaptureEventProfilingInfo = 362
2986 CEFBS_None, // OpCompositeConstruct = 363
2987 CEFBS_None, // OpCompositeConstructContinuedINTEL = 364
2988 CEFBS_None, // OpCompositeExtract = 365
2989 CEFBS_None, // OpCompositeInsert = 366
2990 CEFBS_None, // OpConstantComposite = 367
2991 CEFBS_None, // OpConstantCompositeContinuedINTEL = 368
2992 CEFBS_None, // OpConstantF = 369
2993 CEFBS_None, // OpConstantFalse = 370
2994 CEFBS_None, // OpConstantFunctionPointerINTEL = 371
2995 CEFBS_None, // OpConstantI = 372
2996 CEFBS_None, // OpConstantNull = 373
2997 CEFBS_None, // OpConstantSampler = 374
2998 CEFBS_None, // OpConstantTrue = 375
2999 CEFBS_None, // OpControlBarrier = 376
3000 CEFBS_None, // OpControlBarrierArriveINTEL = 377
3001 CEFBS_None, // OpControlBarrierWaitINTEL = 378
3002 CEFBS_None, // OpConvertBF16ToFINTEL = 379
3003 CEFBS_None, // OpConvertFToBF16INTEL = 380
3004 CEFBS_None, // OpConvertFToS = 381
3005 CEFBS_None, // OpConvertFToU = 382
3006 CEFBS_None, // OpConvertHandleToImageINTEL = 383
3007 CEFBS_None, // OpConvertHandleToSampledImageINTEL = 384
3008 CEFBS_None, // OpConvertHandleToSamplerINTEL = 385
3009 CEFBS_None, // OpConvertPtrToU = 386
3010 CEFBS_None, // OpConvertSToF = 387
3011 CEFBS_None, // OpConvertUToF = 388
3012 CEFBS_None, // OpConvertUToPtr = 389
3013 CEFBS_None, // OpCooperativeMatrixConstructCheckedINTEL = 390
3014 CEFBS_None, // OpCooperativeMatrixGetElementCoordINTEL = 391
3015 CEFBS_None, // OpCooperativeMatrixLengthKHR = 392
3016 CEFBS_None, // OpCooperativeMatrixLoadCheckedINTEL = 393
3017 CEFBS_None, // OpCooperativeMatrixLoadKHR = 394
3018 CEFBS_None, // OpCooperativeMatrixMulAddKHR = 395
3019 CEFBS_None, // OpCooperativeMatrixPrefetchINTEL = 396
3020 CEFBS_None, // OpCooperativeMatrixStoreCheckedINTEL = 397
3021 CEFBS_None, // OpCooperativeMatrixStoreKHR = 398
3022 CEFBS_None, // OpCopyLogical = 399
3023 CEFBS_None, // OpCopyMemory = 400
3024 CEFBS_None, // OpCopyMemorySized = 401
3025 CEFBS_None, // OpCopyObject = 402
3026 CEFBS_None, // OpCreateUserEvent = 403
3027 CEFBS_None, // OpCrossWorkgroupCastToPtrINTEL = 404
3028 CEFBS_None, // OpDPdx = 405
3029 CEFBS_None, // OpDPdxCoarse = 406
3030 CEFBS_None, // OpDPdxFine = 407
3031 CEFBS_None, // OpDPdy = 408
3032 CEFBS_None, // OpDPdyCoarse = 409
3033 CEFBS_None, // OpDPdyFine = 410
3034 CEFBS_None, // OpDecorate = 411
3035 CEFBS_None, // OpDecorateId = 412
3036 CEFBS_None, // OpDecorateString = 413
3037 CEFBS_None, // OpDemoteToHelperInvocation = 414
3038 CEFBS_None, // OpDot = 415
3039 CEFBS_None, // OpEmitStreamVertex = 416
3040 CEFBS_None, // OpEmitVertex = 417
3041 CEFBS_None, // OpEndPrimitive = 418
3042 CEFBS_None, // OpEndStreamPrimitive = 419
3043 CEFBS_None, // OpEnqueueKernel = 420
3044 CEFBS_None, // OpEntryPoint = 421
3045 CEFBS_None, // OpExecutionMode = 422
3046 CEFBS_None, // OpExecutionModeId = 423
3047 CEFBS_None, // OpExpectKHR = 424
3048 CEFBS_None, // OpExtInst = 425
3049 CEFBS_None, // OpExtInstImport = 426
3050 CEFBS_None, // OpExtension = 427
3051 CEFBS_None, // OpFAddS = 428
3052 CEFBS_None, // OpFAddV = 429
3053 CEFBS_None, // OpFConvert = 430
3054 CEFBS_None, // OpFDivS = 431
3055 CEFBS_None, // OpFDivV = 432
3056 CEFBS_None, // OpFMod = 433
3057 CEFBS_None, // OpFMulS = 434
3058 CEFBS_None, // OpFMulV = 435
3059 CEFBS_None, // OpFNegate = 436
3060 CEFBS_None, // OpFNegateV = 437
3061 CEFBS_None, // OpFOrdEqual = 438
3062 CEFBS_None, // OpFOrdGreaterThan = 439
3063 CEFBS_None, // OpFOrdGreaterThanEqual = 440
3064 CEFBS_None, // OpFOrdLessThan = 441
3065 CEFBS_None, // OpFOrdLessThanEqual = 442
3066 CEFBS_None, // OpFOrdNotEqual = 443
3067 CEFBS_None, // OpFRemS = 444
3068 CEFBS_None, // OpFRemV = 445
3069 CEFBS_None, // OpFSubS = 446
3070 CEFBS_None, // OpFSubV = 447
3071 CEFBS_None, // OpFUnordEqual = 448
3072 CEFBS_None, // OpFUnordGreaterThan = 449
3073 CEFBS_None, // OpFUnordGreaterThanEqual = 450
3074 CEFBS_None, // OpFUnordLessThan = 451
3075 CEFBS_None, // OpFUnordLessThanEqual = 452
3076 CEFBS_None, // OpFUnordNotEqual = 453
3077 CEFBS_None, // OpFunction = 454
3078 CEFBS_None, // OpFunctionCall = 455
3079 CEFBS_None, // OpFunctionEnd = 456
3080 CEFBS_None, // OpFunctionParameter = 457
3081 CEFBS_None, // OpFunctionPointerCallINTEL = 458
3082 CEFBS_None, // OpFwidth = 459
3083 CEFBS_None, // OpFwidthCoarse = 460
3084 CEFBS_None, // OpFwidthFine = 461
3085 CEFBS_None, // OpGenericCastToPtr = 462
3086 CEFBS_None, // OpGenericCastToPtrExplicit = 463
3087 CEFBS_None, // OpGenericPtrMemSemantics = 464
3088 CEFBS_None, // OpGetDefaultQueue = 465
3089 CEFBS_None, // OpGroupAll = 466
3090 CEFBS_None, // OpGroupAny = 467
3091 CEFBS_None, // OpGroupAsyncCopy = 468
3092 CEFBS_None, // OpGroupBitwiseAndKHR = 469
3093 CEFBS_None, // OpGroupBitwiseOrKHR = 470
3094 CEFBS_None, // OpGroupBitwiseXorKHR = 471
3095 CEFBS_None, // OpGroupBroadcast = 472
3096 CEFBS_None, // OpGroupFAdd = 473
3097 CEFBS_None, // OpGroupFMax = 474
3098 CEFBS_None, // OpGroupFMin = 475
3099 CEFBS_None, // OpGroupFMulKHR = 476
3100 CEFBS_None, // OpGroupIAdd = 477
3101 CEFBS_None, // OpGroupIMulKHR = 478
3102 CEFBS_None, // OpGroupLogicalAndKHR = 479
3103 CEFBS_None, // OpGroupLogicalOrKHR = 480
3104 CEFBS_None, // OpGroupLogicalXorKHR = 481
3105 CEFBS_None, // OpGroupNonUniformAll = 482
3106 CEFBS_None, // OpGroupNonUniformAllEqual = 483
3107 CEFBS_None, // OpGroupNonUniformAny = 484
3108 CEFBS_None, // OpGroupNonUniformBallot = 485
3109 CEFBS_None, // OpGroupNonUniformBallotBitCount = 486
3110 CEFBS_None, // OpGroupNonUniformBallotBitExtract = 487
3111 CEFBS_None, // OpGroupNonUniformBallotFindLSB = 488
3112 CEFBS_None, // OpGroupNonUniformBallotFindMSB = 489
3113 CEFBS_None, // OpGroupNonUniformBitwiseAnd = 490
3114 CEFBS_None, // OpGroupNonUniformBitwiseOr = 491
3115 CEFBS_None, // OpGroupNonUniformBitwiseXor = 492
3116 CEFBS_None, // OpGroupNonUniformBroadcast = 493
3117 CEFBS_None, // OpGroupNonUniformBroadcastFirst = 494
3118 CEFBS_None, // OpGroupNonUniformElect = 495
3119 CEFBS_None, // OpGroupNonUniformFAdd = 496
3120 CEFBS_None, // OpGroupNonUniformFMax = 497
3121 CEFBS_None, // OpGroupNonUniformFMin = 498
3122 CEFBS_None, // OpGroupNonUniformFMul = 499
3123 CEFBS_None, // OpGroupNonUniformIAdd = 500
3124 CEFBS_None, // OpGroupNonUniformIMul = 501
3125 CEFBS_None, // OpGroupNonUniformInverseBallot = 502
3126 CEFBS_None, // OpGroupNonUniformLogicalAnd = 503
3127 CEFBS_None, // OpGroupNonUniformLogicalOr = 504
3128 CEFBS_None, // OpGroupNonUniformLogicalXor = 505
3129 CEFBS_None, // OpGroupNonUniformRotateKHR = 506
3130 CEFBS_None, // OpGroupNonUniformSMax = 507
3131 CEFBS_None, // OpGroupNonUniformSMin = 508
3132 CEFBS_None, // OpGroupNonUniformShuffle = 509
3133 CEFBS_None, // OpGroupNonUniformShuffleDown = 510
3134 CEFBS_None, // OpGroupNonUniformShuffleUp = 511
3135 CEFBS_None, // OpGroupNonUniformShuffleXor = 512
3136 CEFBS_None, // OpGroupNonUniformUMax = 513
3137 CEFBS_None, // OpGroupNonUniformUMin = 514
3138 CEFBS_None, // OpGroupSMax = 515
3139 CEFBS_None, // OpGroupSMin = 516
3140 CEFBS_None, // OpGroupUMax = 517
3141 CEFBS_None, // OpGroupUMin = 518
3142 CEFBS_None, // OpGroupWaitEvents = 519
3143 CEFBS_None, // OpIAddCarryS = 520
3144 CEFBS_None, // OpIAddCarryV = 521
3145 CEFBS_None, // OpIAddS = 522
3146 CEFBS_None, // OpIAddV = 523
3147 CEFBS_None, // OpIEqual = 524
3148 CEFBS_None, // OpIMulS = 525
3149 CEFBS_None, // OpIMulV = 526
3150 CEFBS_None, // OpINotEqual = 527
3151 CEFBS_None, // OpISubBorrowS = 528
3152 CEFBS_None, // OpISubBorrowV = 529
3153 CEFBS_None, // OpISubS = 530
3154 CEFBS_None, // OpISubV = 531
3155 CEFBS_None, // OpImage = 532
3156 CEFBS_None, // OpImageDrefGather = 533
3157 CEFBS_None, // OpImageFetch = 534
3158 CEFBS_None, // OpImageGather = 535
3159 CEFBS_None, // OpImageQueryFormat = 536
3160 CEFBS_None, // OpImageQueryLevels = 537
3161 CEFBS_None, // OpImageQueryLod = 538
3162 CEFBS_None, // OpImageQueryOrder = 539
3163 CEFBS_None, // OpImageQuerySamples = 540
3164 CEFBS_None, // OpImageQuerySize = 541
3165 CEFBS_None, // OpImageQuerySizeLod = 542
3166 CEFBS_None, // OpImageRead = 543
3167 CEFBS_None, // OpImageSampleDrefExplicitLod = 544
3168 CEFBS_None, // OpImageSampleDrefImplicitLod = 545
3169 CEFBS_None, // OpImageSampleExplicitLod = 546
3170 CEFBS_None, // OpImageSampleFootprintNV = 547
3171 CEFBS_None, // OpImageSampleImplicitLod = 548
3172 CEFBS_None, // OpImageSampleProjDrefExplicitLod = 549
3173 CEFBS_None, // OpImageSampleProjDrefImplicitLod = 550
3174 CEFBS_None, // OpImageSampleProjExplicitLod = 551
3175 CEFBS_None, // OpImageSampleProjImplicitLod = 552
3176 CEFBS_None, // OpImageSparseDrefGather = 553
3177 CEFBS_None, // OpImageSparseFetch = 554
3178 CEFBS_None, // OpImageSparseGather = 555
3179 CEFBS_None, // OpImageSparseRead = 556
3180 CEFBS_None, // OpImageSparseSampleDrefExplicitLod = 557
3181 CEFBS_None, // OpImageSparseSampleDrefImplicitLod = 558
3182 CEFBS_None, // OpImageSparseSampleExplicitLod = 559
3183 CEFBS_None, // OpImageSparseSampleImplicitLod = 560
3184 CEFBS_None, // OpImageSparseSampleProjDrefExplicitLod = 561
3185 CEFBS_None, // OpImageSparseSampleProjDrefImplicitLod = 562
3186 CEFBS_None, // OpImageSparseSampleProjExplicitLod = 563
3187 CEFBS_None, // OpImageSparseSampleProjImplicitLod = 564
3188 CEFBS_None, // OpImageSparseTexelsResident = 565
3189 CEFBS_None, // OpImageTexelPointer = 566
3190 CEFBS_None, // OpImageWrite = 567
3191 CEFBS_None, // OpInBoundsAccessChain = 568
3192 CEFBS_None, // OpInBoundsPtrAccessChain = 569
3193 CEFBS_None, // OpIsFinite = 570
3194 CEFBS_None, // OpIsInf = 571
3195 CEFBS_None, // OpIsNan = 572
3196 CEFBS_None, // OpIsNormal = 573
3197 CEFBS_None, // OpIsValidEvent = 574
3198 CEFBS_None, // OpKill = 575
3199 CEFBS_None, // OpLabel = 576
3200 CEFBS_None, // OpLessOrGreater = 577
3201 CEFBS_None, // OpLifetimeStart = 578
3202 CEFBS_None, // OpLifetimeStop = 579
3203 CEFBS_None, // OpLine = 580
3204 CEFBS_None, // OpLoad = 581
3205 CEFBS_None, // OpLogicalAnd = 582
3206 CEFBS_None, // OpLogicalEqual = 583
3207 CEFBS_None, // OpLogicalNot = 584
3208 CEFBS_None, // OpLogicalNotEqual = 585
3209 CEFBS_None, // OpLogicalOr = 586
3210 CEFBS_None, // OpLoopMerge = 587
3211 CEFBS_None, // OpMatrixTimesMatrix = 588
3212 CEFBS_None, // OpMatrixTimesScalar = 589
3213 CEFBS_None, // OpMatrixTimesVector = 590
3214 CEFBS_None, // OpMemberDecorate = 591
3215 CEFBS_None, // OpMemberDecorateString = 592
3216 CEFBS_None, // OpMemberName = 593
3217 CEFBS_None, // OpMemoryBarrier = 594
3218 CEFBS_None, // OpMemoryModel = 595
3219 CEFBS_None, // OpMemoryNamedBarrier = 596
3220 CEFBS_None, // OpModuleProcessed = 597
3221 CEFBS_None, // OpName = 598
3222 CEFBS_None, // OpNamedBarrierInitialize = 599
3223 CEFBS_None, // OpNoLine = 600
3224 CEFBS_None, // OpNop = 601
3225 CEFBS_None, // OpNot = 602
3226 CEFBS_None, // OpOrdered = 603
3227 CEFBS_None, // OpOuterProduct = 604
3228 CEFBS_None, // OpPhi = 605
3229 CEFBS_None, // OpPtrAccessChain = 606
3230 CEFBS_None, // OpPtrCastToCrossWorkgroupINTEL = 607
3231 CEFBS_None, // OpPtrCastToGeneric = 608
3232 CEFBS_None, // OpPtrDiff = 609
3233 CEFBS_None, // OpPtrEqual = 610
3234 CEFBS_None, // OpPtrNotEqual = 611
3235 CEFBS_None, // OpQuantizeToF16 = 612
3236 CEFBS_None, // OpReadClockKHR = 613
3237 CEFBS_None, // OpReleaseEvent = 614
3238 CEFBS_None, // OpRestoreMemoryINTEL = 615
3239 CEFBS_None, // OpRetainEvent = 616
3240 CEFBS_None, // OpReturn = 617
3241 CEFBS_None, // OpReturnValue = 618
3242 CEFBS_None, // OpSConvert = 619
3243 CEFBS_None, // OpSDivS = 620
3244 CEFBS_None, // OpSDivV = 621
3245 CEFBS_None, // OpSDot = 622
3246 CEFBS_None, // OpSDotAccSat = 623
3247 CEFBS_None, // OpSGreaterThan = 624
3248 CEFBS_None, // OpSGreaterThanEqual = 625
3249 CEFBS_None, // OpSLessThan = 626
3250 CEFBS_None, // OpSLessThanEqual = 627
3251 CEFBS_None, // OpSMod = 628
3252 CEFBS_None, // OpSMulExtended = 629
3253 CEFBS_None, // OpSNegate = 630
3254 CEFBS_None, // OpSRemS = 631
3255 CEFBS_None, // OpSRemV = 632
3256 CEFBS_None, // OpSUDot = 633
3257 CEFBS_None, // OpSUDotAccSat = 634
3258 CEFBS_None, // OpSampledImage = 635
3259 CEFBS_None, // OpSatConvertSToU = 636
3260 CEFBS_None, // OpSatConvertUToS = 637
3261 CEFBS_None, // OpSaveMemoryINTEL = 638
3262 CEFBS_None, // OpSelectSFSCond = 639
3263 CEFBS_None, // OpSelectSFVCond = 640
3264 CEFBS_None, // OpSelectSISCond = 641
3265 CEFBS_None, // OpSelectSIVCond = 642
3266 CEFBS_None, // OpSelectSPSCond = 643
3267 CEFBS_None, // OpSelectSPVCond = 644
3268 CEFBS_None, // OpSelectVFSCond = 645
3269 CEFBS_None, // OpSelectVFVCond = 646
3270 CEFBS_None, // OpSelectVISCond = 647
3271 CEFBS_None, // OpSelectVIVCond = 648
3272 CEFBS_None, // OpSelectVPSCond = 649
3273 CEFBS_None, // OpSelectVPVCond = 650
3274 CEFBS_None, // OpSelectionMerge = 651
3275 CEFBS_None, // OpSetUserEventStatus = 652
3276 CEFBS_None, // OpShiftLeftLogicalS = 653
3277 CEFBS_None, // OpShiftLeftLogicalV = 654
3278 CEFBS_None, // OpShiftRightArithmeticS = 655
3279 CEFBS_None, // OpShiftRightArithmeticV = 656
3280 CEFBS_None, // OpShiftRightLogicalS = 657
3281 CEFBS_None, // OpShiftRightLogicalV = 658
3282 CEFBS_None, // OpSignBitSet = 659
3283 CEFBS_None, // OpSizeOf = 660
3284 CEFBS_None, // OpSource = 661
3285 CEFBS_None, // OpSourceContinued = 662
3286 CEFBS_None, // OpSourceExtension = 663
3287 CEFBS_None, // OpSpecConstant = 664
3288 CEFBS_None, // OpSpecConstantComposite = 665
3289 CEFBS_None, // OpSpecConstantCompositeContinuedINTEL = 666
3290 CEFBS_None, // OpSpecConstantFalse = 667
3291 CEFBS_None, // OpSpecConstantOp = 668
3292 CEFBS_None, // OpSpecConstantTrue = 669
3293 CEFBS_None, // OpStore = 670
3294 CEFBS_None, // OpStrictFAddS = 671
3295 CEFBS_None, // OpStrictFAddV = 672
3296 CEFBS_None, // OpStrictFDivS = 673
3297 CEFBS_None, // OpStrictFDivV = 674
3298 CEFBS_None, // OpStrictFMulS = 675
3299 CEFBS_None, // OpStrictFMulV = 676
3300 CEFBS_None, // OpStrictFRemS = 677
3301 CEFBS_None, // OpStrictFRemV = 678
3302 CEFBS_None, // OpStrictFSubS = 679
3303 CEFBS_None, // OpStrictFSubV = 680
3304 CEFBS_None, // OpString = 681
3305 CEFBS_None, // OpSubgroup2DBlockLoadINTEL = 682
3306 CEFBS_None, // OpSubgroup2DBlockLoadTransformINTEL = 683
3307 CEFBS_None, // OpSubgroup2DBlockLoadTransposeINTEL = 684
3308 CEFBS_None, // OpSubgroup2DBlockPrefetchINTEL = 685
3309 CEFBS_None, // OpSubgroup2DBlockStoreINTEL = 686
3310 CEFBS_None, // OpSubgroupBlockReadINTEL = 687
3311 CEFBS_None, // OpSubgroupBlockWriteINTEL = 688
3312 CEFBS_None, // OpSubgroupImageBlockReadINTEL = 689
3313 CEFBS_None, // OpSubgroupImageBlockWriteINTEL = 690
3314 CEFBS_None, // OpSubgroupImageMediaBlockReadINTEL = 691
3315 CEFBS_None, // OpSubgroupImageMediaBlockWriteINTEL = 692
3316 CEFBS_None, // OpSubgroupMatrixMultiplyAccumulateINTEL = 693
3317 CEFBS_None, // OpSubgroupShuffleDownINTEL = 694
3318 CEFBS_None, // OpSubgroupShuffleINTEL = 695
3319 CEFBS_None, // OpSubgroupShuffleUpINTEL = 696
3320 CEFBS_None, // OpSubgroupShuffleXorINTEL = 697
3321 CEFBS_None, // OpSwitch = 698
3322 CEFBS_None, // OpTranspose = 699
3323 CEFBS_None, // OpTypeAccelerationStructureNV = 700
3324 CEFBS_None, // OpTypeArray = 701
3325 CEFBS_None, // OpTypeBool = 702
3326 CEFBS_None, // OpTypeCooperativeMatrixKHR = 703
3327 CEFBS_None, // OpTypeCooperativeMatrixNV = 704
3328 CEFBS_None, // OpTypeDeviceEvent = 705
3329 CEFBS_None, // OpTypeEvent = 706
3330 CEFBS_None, // OpTypeFloat = 707
3331 CEFBS_None, // OpTypeForwardPointer = 708
3332 CEFBS_None, // OpTypeFunction = 709
3333 CEFBS_None, // OpTypeImage = 710
3334 CEFBS_None, // OpTypeInt = 711
3335 CEFBS_None, // OpTypeMatrix = 712
3336 CEFBS_None, // OpTypeNamedBarrier = 713
3337 CEFBS_None, // OpTypeOpaque = 714
3338 CEFBS_None, // OpTypePipe = 715
3339 CEFBS_None, // OpTypePipeStorage = 716
3340 CEFBS_None, // OpTypePointer = 717
3341 CEFBS_None, // OpTypeQueue = 718
3342 CEFBS_None, // OpTypeReserveId = 719
3343 CEFBS_None, // OpTypeRuntimeArray = 720
3344 CEFBS_None, // OpTypeSampledImage = 721
3345 CEFBS_None, // OpTypeSampler = 722
3346 CEFBS_None, // OpTypeStruct = 723
3347 CEFBS_None, // OpTypeStructContinuedINTEL = 724
3348 CEFBS_None, // OpTypeVector = 725
3349 CEFBS_None, // OpTypeVoid = 726
3350 CEFBS_None, // OpUConvert = 727
3351 CEFBS_None, // OpUDivS = 728
3352 CEFBS_None, // OpUDivV = 729
3353 CEFBS_None, // OpUDot = 730
3354 CEFBS_None, // OpUDotAccSat = 731
3355 CEFBS_None, // OpUGreaterThan = 732
3356 CEFBS_None, // OpUGreaterThanEqual = 733
3357 CEFBS_None, // OpULessThan = 734
3358 CEFBS_None, // OpULessThanEqual = 735
3359 CEFBS_None, // OpUModS = 736
3360 CEFBS_None, // OpUModV = 737
3361 CEFBS_None, // OpUMulExtended = 738
3362 CEFBS_None, // OpUndef = 739
3363 CEFBS_None, // OpUnordered = 740
3364 CEFBS_None, // OpUnreachable = 741
3365 CEFBS_None, // OpVariable = 742
3366 CEFBS_None, // OpVariableLengthArrayINTEL = 743
3367 CEFBS_None, // OpVectorExtractDynamic = 744
3368 CEFBS_None, // OpVectorInsertDynamic = 745
3369 CEFBS_None, // OpVectorShuffle = 746
3370 CEFBS_None, // OpVectorTimesMatrix = 747
3371 CEFBS_None, // OpVectorTimesScalar = 748
3372 };
3373
3374 assert(Opcode < 749);
3375 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
3376}
3377
3378} // end namespace llvm::SPIRV_MC
3379#endif // GET_COMPUTE_FEATURES
3380
3381#ifdef GET_AVAILABLE_OPCODE_CHECKER
3382#undef GET_AVAILABLE_OPCODE_CHECKER
3383namespace llvm::SPIRV_MC {
3384bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
3385 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
3386 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
3387 FeatureBitset MissingFeatures =
3388 (AvailableFeatures & RequiredFeatures) ^
3389 RequiredFeatures;
3390 return !MissingFeatures.any();
3391}
3392} // end namespace llvm::SPIRV_MC
3393#endif // GET_AVAILABLE_OPCODE_CHECKER
3394
3395#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
3396#undef ENABLE_INSTR_PREDICATE_VERIFIER
3397#include <sstream>
3398
3399namespace llvm::SPIRV_MC {
3400#ifndef NDEBUG
3401static const char *SubtargetFeatureNames[] = {
3402 nullptr
3403};
3404
3405#endif // NDEBUG
3406
3407void verifyInstructionPredicates(
3408 unsigned Opcode, const FeatureBitset &Features) {
3409#ifndef NDEBUG
3410 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
3411 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
3412 FeatureBitset MissingFeatures =
3413 (AvailableFeatures & RequiredFeatures) ^
3414 RequiredFeatures;
3415 if (MissingFeatures.any()) {
3416 std::ostringstream Msg;
3417 Msg << "Attempting to emit " << &SPIRVInstrNameData[SPIRVInstrNameIndices[Opcode]]
3418 << " instruction but the ";
3419 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
3420 if (MissingFeatures.test(i))
3421 Msg << SubtargetFeatureNames[i] << " ";
3422 Msg << "predicate(s) are not met";
3423 report_fatal_error(Msg.str().c_str());
3424 }
3425#endif // NDEBUG
3426}
3427} // end namespace llvm::SPIRV_MC
3428#endif // ENABLE_INSTR_PREDICATE_VERIFIER
3429
3430