1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register Enum Values *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_REGINFO_ENUM
11#undef GET_REGINFO_ENUM
12
13namespace llvm {
14
15class MCRegisterClass;
16extern const MCRegisterClass SPIRVMCRegisterClasses[];
17
18namespace SPIRV {
19enum : unsigned {
20 NoRegister,
21 ID0 = 1,
22 TYPE0 = 2,
23 fID0 = 3,
24 pID0 = 4,
25 vID0 = 5,
26 vfID0 = 6,
27 vpID0 = 7,
28 NUM_TARGET_REGS // 8
29};
30} // end namespace SPIRV
31
32// Register classes
33
34namespace SPIRV {
35enum {
36 ANYRegClassID = 0,
37 IDRegClassID = 1,
38 TYPERegClassID = 2,
39 fIDRegClassID = 3,
40 iIDRegClassID = 4,
41 pIDRegClassID = 5,
42 vpIDRegClassID = 6,
43 vIDRegClassID = 7,
44 vfIDRegClassID = 8,
45
46};
47} // end namespace SPIRV
48
49// Register pressure sets enum.
50namespace SPIRV {
51enum RegisterPressureSets {
52 TYPE = 0,
53 fID = 1,
54 iID = 2,
55 pID = 3,
56 vpID = 4,
57 vID = 5,
58 vfID = 6,
59 ID = 7,
60};
61} // end namespace SPIRV
62
63} // end namespace llvm
64
65#endif // GET_REGINFO_ENUM
66
67/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
68|* *|
69|* MC Register Information *|
70|* *|
71|* Automatically generated file, do not edit! *|
72|* *|
73\*===----------------------------------------------------------------------===*/
74
75
76#ifdef GET_REGINFO_MC_DESC
77#undef GET_REGINFO_MC_DESC
78
79namespace llvm {
80
81extern const int16_t SPIRVRegDiffLists[] = {
82 /* 0 */ 0,
83};
84
85extern const LaneBitmask SPIRVLaneMaskLists[] = {
86 /* 0 */ LaneBitmask(0xFFFFFFFFFFFFFFFF),
87};
88
89extern const uint16_t SPIRVSubRegIdxLists[] = {
90 /* 0 */
91 /* dummy */ 0
92};
93
94
95#ifdef __GNUC__
96#pragma GCC diagnostic push
97#pragma GCC diagnostic ignored "-Woverlength-strings"
98#endif
99extern const char SPIRVRegStrings[] = {
100 /* 0 */ "vfID0\000"
101 /* 6 */ "vpID0\000"
102 /* 12 */ "vID0\000"
103 /* 17 */ "TYPE0\000"
104};
105#ifdef __GNUC__
106#pragma GCC diagnostic pop
107#endif
108
109extern const MCRegisterDesc SPIRVRegDesc[] = { // Descriptors
110 { 5, 0, 0, 0, 0, 0, 0, 0 },
111 { 2, 0, 0, 0, 0, 0, 0, 0 },
112 { 17, 0, 0, 0, 1, 0, 0, 0 },
113 { 1, 0, 0, 0, 2, 0, 0, 0 },
114 { 7, 0, 0, 0, 3, 0, 0, 0 },
115 { 12, 0, 0, 0, 4, 0, 0, 0 },
116 { 0, 0, 0, 0, 5, 0, 0, 0 },
117 { 6, 0, 0, 0, 6, 0, 0, 0 },
118};
119
120extern const MCPhysReg SPIRVRegUnitRoots[][2] = {
121 { SPIRV::ID0 },
122 { SPIRV::TYPE0 },
123 { SPIRV::fID0 },
124 { SPIRV::pID0 },
125 { SPIRV::vID0 },
126 { SPIRV::vfID0 },
127 { SPIRV::vpID0 },
128};
129
130namespace { // Register classes...
131 // ANY Register Class...
132 const MCPhysReg ANY[] = {
133 SPIRV::TYPE0, SPIRV::ID0, SPIRV::fID0, SPIRV::pID0, SPIRV::vID0, SPIRV::vfID0, SPIRV::vpID0,
134 };
135
136 // ANY Bit set.
137 const uint8_t ANYBits[] = {
138 0xfe,
139 };
140
141 // ID Register Class...
142 const MCPhysReg ID[] = {
143 SPIRV::ID0, SPIRV::fID0, SPIRV::pID0, SPIRV::vID0, SPIRV::vfID0, SPIRV::vpID0,
144 };
145
146 // ID Bit set.
147 const uint8_t IDBits[] = {
148 0xfa,
149 };
150
151 // TYPE Register Class...
152 const MCPhysReg TYPE[] = {
153 SPIRV::TYPE0,
154 };
155
156 // TYPE Bit set.
157 const uint8_t TYPEBits[] = {
158 0x04,
159 };
160
161 // fID Register Class...
162 const MCPhysReg fID[] = {
163 SPIRV::fID0,
164 };
165
166 // fID Bit set.
167 const uint8_t fIDBits[] = {
168 0x08,
169 };
170
171 // iID Register Class...
172 const MCPhysReg iID[] = {
173 SPIRV::ID0,
174 };
175
176 // iID Bit set.
177 const uint8_t iIDBits[] = {
178 0x02,
179 };
180
181 // pID Register Class...
182 const MCPhysReg pID[] = {
183 SPIRV::pID0,
184 };
185
186 // pID Bit set.
187 const uint8_t pIDBits[] = {
188 0x10,
189 };
190
191 // vpID Register Class...
192 const MCPhysReg vpID[] = {
193 SPIRV::vpID0,
194 };
195
196 // vpID Bit set.
197 const uint8_t vpIDBits[] = {
198 0x80,
199 };
200
201 // vID Register Class...
202 const MCPhysReg vID[] = {
203 SPIRV::vID0,
204 };
205
206 // vID Bit set.
207 const uint8_t vIDBits[] = {
208 0x20,
209 };
210
211 // vfID Register Class...
212 const MCPhysReg vfID[] = {
213 SPIRV::vfID0,
214 };
215
216 // vfID Bit set.
217 const uint8_t vfIDBits[] = {
218 0x40,
219 };
220
221} // end anonymous namespace
222
223
224#ifdef __GNUC__
225#pragma GCC diagnostic push
226#pragma GCC diagnostic ignored "-Woverlength-strings"
227#endif
228extern const char SPIRVRegClassStrings[] = {
229 /* 0 */ "vfID\000"
230 /* 5 */ "iID\000"
231 /* 9 */ "vpID\000"
232 /* 14 */ "vID\000"
233 /* 18 */ "TYPE\000"
234 /* 23 */ "ANY\000"
235};
236#ifdef __GNUC__
237#pragma GCC diagnostic pop
238#endif
239
240extern const MCRegisterClass SPIRVMCRegisterClasses[] = {
241 { ANY, ANYBits, 23, 7, sizeof(ANYBits), SPIRV::ANYRegClassID, 64, 1, true, false },
242 { ID, IDBits, 2, 6, sizeof(IDBits), SPIRV::IDRegClassID, 64, 1, true, false },
243 { TYPE, TYPEBits, 18, 1, sizeof(TYPEBits), SPIRV::TYPERegClassID, 64, 1, true, false },
244 { fID, fIDBits, 1, 1, sizeof(fIDBits), SPIRV::fIDRegClassID, 64, 1, true, false },
245 { iID, iIDBits, 5, 1, sizeof(iIDBits), SPIRV::iIDRegClassID, 64, 1, true, false },
246 { pID, pIDBits, 10, 1, sizeof(pIDBits), SPIRV::pIDRegClassID, 64, 1, true, false },
247 { vpID, vpIDBits, 9, 1, sizeof(vpIDBits), SPIRV::vpIDRegClassID, 64, 1, true, false },
248 { vID, vIDBits, 14, 1, sizeof(vIDBits), SPIRV::vIDRegClassID, 128, 1, true, false },
249 { vfID, vfIDBits, 0, 1, sizeof(vfIDBits), SPIRV::vfIDRegClassID, 128, 1, true, false },
250};
251
252extern const uint16_t SPIRVRegEncodingTable[] = {
253 0,
254 0,
255 0,
256 0,
257 0,
258 0,
259 0,
260 0,
261};
262static inline void InitSPIRVMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
263 RI->InitMCRegisterInfo(SPIRVRegDesc, 8, RA, PC, SPIRVMCRegisterClasses, 9, SPIRVRegUnitRoots, 7, SPIRVRegDiffLists, SPIRVLaneMaskLists, SPIRVRegStrings, SPIRVRegClassStrings, SPIRVSubRegIdxLists, 1,
264SPIRVRegEncodingTable);
265
266}
267
268} // end namespace llvm
269
270#endif // GET_REGINFO_MC_DESC
271
272/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
273|* *|
274|* Register Information Header Fragment *|
275|* *|
276|* Automatically generated file, do not edit! *|
277|* *|
278\*===----------------------------------------------------------------------===*/
279
280
281#ifdef GET_REGINFO_HEADER
282#undef GET_REGINFO_HEADER
283
284#include "llvm/CodeGen/TargetRegisterInfo.h"
285
286namespace llvm {
287
288class SPIRVFrameLowering;
289
290struct SPIRVGenRegisterInfo : public TargetRegisterInfo {
291 explicit SPIRVGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
292 unsigned PC = 0, unsigned HwMode = 0);
293 const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
294 unsigned getRegUnitWeight(unsigned RegUnit) const override;
295 unsigned getNumRegPressureSets() const override;
296 const char *getRegPressureSetName(unsigned Idx) const override;
297 unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
298 const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
299 const int *getRegUnitPressureSets(unsigned RegUnit) const override;
300 ArrayRef<const char *> getRegMaskNames() const override;
301 ArrayRef<const uint32_t *> getRegMasks() const override;
302 bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override;
303 bool isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const override;
304 bool isFixedRegister(const MachineFunction &, MCRegister) const override;
305 bool isArgumentRegister(const MachineFunction &, MCRegister) const override;
306 bool isConstantPhysReg(MCRegister PhysReg) const override final;
307 /// Devirtualized TargetFrameLowering.
308 static const SPIRVFrameLowering *getFrameLowering(
309 const MachineFunction &MF);
310};
311
312namespace SPIRV { // Register classes
313 extern const TargetRegisterClass ANYRegClass;
314 extern const TargetRegisterClass IDRegClass;
315 extern const TargetRegisterClass TYPERegClass;
316 extern const TargetRegisterClass fIDRegClass;
317 extern const TargetRegisterClass iIDRegClass;
318 extern const TargetRegisterClass pIDRegClass;
319 extern const TargetRegisterClass vpIDRegClass;
320 extern const TargetRegisterClass vIDRegClass;
321 extern const TargetRegisterClass vfIDRegClass;
322} // end namespace SPIRV
323
324} // end namespace llvm
325
326#endif // GET_REGINFO_HEADER
327
328/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
329|* *|
330|* Target Register and Register Classes Information *|
331|* *|
332|* Automatically generated file, do not edit! *|
333|* *|
334\*===----------------------------------------------------------------------===*/
335
336
337#ifdef GET_REGINFO_TARGET_DESC
338#undef GET_REGINFO_TARGET_DESC
339
340namespace llvm {
341
342extern const MCRegisterClass SPIRVMCRegisterClasses[];
343
344static const MVT::SimpleValueType VTLists[] = {
345 /* 0 */ MVT::i64, MVT::f64, MVT::i64, MVT::v2i64, MVT::v2f64, MVT::i64, MVT::Other,
346 /* 7 */ MVT::f64, MVT::Other,
347 /* 9 */ MVT::v2i64, MVT::Other,
348 /* 11 */ MVT::v2f64, MVT::Other,
349};
350
351static const char *SubRegIndexNameTable[] = { "" };
352
353static const TargetRegisterInfo::SubRegCoveredBits SubRegIdxRangeTable[] = {
354 { 65535, 65535 },
355};
356
357
358static const LaneBitmask SubRegIndexLaneMaskTable[] = {
359 LaneBitmask::getAll(),
360 };
361
362
363
364static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
365 // Mode = 0 (Default)
366 { 64, 64, 64, /*VTLists+*/5 }, // ANY
367 { 64, 64, 64, /*VTLists+*/0 }, // ID
368 { 64, 64, 64, /*VTLists+*/5 }, // TYPE
369 { 64, 64, 64, /*VTLists+*/7 }, // fID
370 { 64, 64, 64, /*VTLists+*/5 }, // iID
371 { 64, 64, 64, /*VTLists+*/5 }, // pID
372 { 64, 64, 64, /*VTLists+*/5 }, // vpID
373 { 128, 128, 64, /*VTLists+*/9 }, // vID
374 { 128, 128, 64, /*VTLists+*/11 }, // vfID
375};
376static const uint32_t ANYSubClassMask[] = {
377 0x000001ff,
378};
379
380static const uint32_t IDSubClassMask[] = {
381 0x000001fa,
382};
383
384static const uint32_t TYPESubClassMask[] = {
385 0x00000004,
386};
387
388static const uint32_t fIDSubClassMask[] = {
389 0x00000008,
390};
391
392static const uint32_t iIDSubClassMask[] = {
393 0x00000010,
394};
395
396static const uint32_t pIDSubClassMask[] = {
397 0x00000020,
398};
399
400static const uint32_t vpIDSubClassMask[] = {
401 0x00000040,
402};
403
404static const uint32_t vIDSubClassMask[] = {
405 0x00000080,
406};
407
408static const uint32_t vfIDSubClassMask[] = {
409 0x00000100,
410};
411
412static const uint16_t SuperRegIdxSeqs[] = {
413 /* 0 */ 0,
414};
415
416static unsigned const IDSuperclasses[] = {
417 SPIRV::ANYRegClassID,
418};
419
420static unsigned const TYPESuperclasses[] = {
421 SPIRV::ANYRegClassID,
422};
423
424static unsigned const fIDSuperclasses[] = {
425 SPIRV::ANYRegClassID,
426 SPIRV::IDRegClassID,
427};
428
429static unsigned const iIDSuperclasses[] = {
430 SPIRV::ANYRegClassID,
431 SPIRV::IDRegClassID,
432};
433
434static unsigned const pIDSuperclasses[] = {
435 SPIRV::ANYRegClassID,
436 SPIRV::IDRegClassID,
437};
438
439static unsigned const vpIDSuperclasses[] = {
440 SPIRV::ANYRegClassID,
441 SPIRV::IDRegClassID,
442};
443
444static unsigned const vIDSuperclasses[] = {
445 SPIRV::ANYRegClassID,
446 SPIRV::IDRegClassID,
447};
448
449static unsigned const vfIDSuperclasses[] = {
450 SPIRV::ANYRegClassID,
451 SPIRV::IDRegClassID,
452};
453
454
455namespace SPIRV { // Register class instances
456 extern const TargetRegisterClass ANYRegClass = {
457 &SPIRVMCRegisterClasses[ANYRegClassID],
458 ANYSubClassMask,
459 SuperRegIdxSeqs + 0,
460 LaneBitmask(0x0000000000000001),
461 0,
462 false,
463 0x00, /* TSFlags */
464 false, /* HasDisjunctSubRegs */
465 false, /* CoveredBySubRegs */
466 nullptr, 0,
467 nullptr
468 };
469
470 extern const TargetRegisterClass IDRegClass = {
471 &SPIRVMCRegisterClasses[IDRegClassID],
472 IDSubClassMask,
473 SuperRegIdxSeqs + 0,
474 LaneBitmask(0x0000000000000001),
475 0,
476 false,
477 0x00, /* TSFlags */
478 false, /* HasDisjunctSubRegs */
479 false, /* CoveredBySubRegs */
480 IDSuperclasses, 1,
481 nullptr
482 };
483
484 extern const TargetRegisterClass TYPERegClass = {
485 &SPIRVMCRegisterClasses[TYPERegClassID],
486 TYPESubClassMask,
487 SuperRegIdxSeqs + 0,
488 LaneBitmask(0x0000000000000001),
489 0,
490 false,
491 0x00, /* TSFlags */
492 false, /* HasDisjunctSubRegs */
493 false, /* CoveredBySubRegs */
494 TYPESuperclasses, 1,
495 nullptr
496 };
497
498 extern const TargetRegisterClass fIDRegClass = {
499 &SPIRVMCRegisterClasses[fIDRegClassID],
500 fIDSubClassMask,
501 SuperRegIdxSeqs + 0,
502 LaneBitmask(0x0000000000000001),
503 0,
504 false,
505 0x00, /* TSFlags */
506 false, /* HasDisjunctSubRegs */
507 false, /* CoveredBySubRegs */
508 fIDSuperclasses, 2,
509 nullptr
510 };
511
512 extern const TargetRegisterClass iIDRegClass = {
513 &SPIRVMCRegisterClasses[iIDRegClassID],
514 iIDSubClassMask,
515 SuperRegIdxSeqs + 0,
516 LaneBitmask(0x0000000000000001),
517 0,
518 false,
519 0x00, /* TSFlags */
520 false, /* HasDisjunctSubRegs */
521 false, /* CoveredBySubRegs */
522 iIDSuperclasses, 2,
523 nullptr
524 };
525
526 extern const TargetRegisterClass pIDRegClass = {
527 &SPIRVMCRegisterClasses[pIDRegClassID],
528 pIDSubClassMask,
529 SuperRegIdxSeqs + 0,
530 LaneBitmask(0x0000000000000001),
531 0,
532 false,
533 0x00, /* TSFlags */
534 false, /* HasDisjunctSubRegs */
535 false, /* CoveredBySubRegs */
536 pIDSuperclasses, 2,
537 nullptr
538 };
539
540 extern const TargetRegisterClass vpIDRegClass = {
541 &SPIRVMCRegisterClasses[vpIDRegClassID],
542 vpIDSubClassMask,
543 SuperRegIdxSeqs + 0,
544 LaneBitmask(0x0000000000000001),
545 0,
546 false,
547 0x00, /* TSFlags */
548 false, /* HasDisjunctSubRegs */
549 false, /* CoveredBySubRegs */
550 vpIDSuperclasses, 2,
551 nullptr
552 };
553
554 extern const TargetRegisterClass vIDRegClass = {
555 &SPIRVMCRegisterClasses[vIDRegClassID],
556 vIDSubClassMask,
557 SuperRegIdxSeqs + 0,
558 LaneBitmask(0x0000000000000001),
559 0,
560 false,
561 0x00, /* TSFlags */
562 false, /* HasDisjunctSubRegs */
563 false, /* CoveredBySubRegs */
564 vIDSuperclasses, 2,
565 nullptr
566 };
567
568 extern const TargetRegisterClass vfIDRegClass = {
569 &SPIRVMCRegisterClasses[vfIDRegClassID],
570 vfIDSubClassMask,
571 SuperRegIdxSeqs + 0,
572 LaneBitmask(0x0000000000000001),
573 0,
574 false,
575 0x00, /* TSFlags */
576 false, /* HasDisjunctSubRegs */
577 false, /* CoveredBySubRegs */
578 vfIDSuperclasses, 2,
579 nullptr
580 };
581
582} // end namespace SPIRV
583
584namespace {
585 const TargetRegisterClass *const RegisterClasses[] = {
586 &SPIRV::ANYRegClass,
587 &SPIRV::IDRegClass,
588 &SPIRV::TYPERegClass,
589 &SPIRV::fIDRegClass,
590 &SPIRV::iIDRegClass,
591 &SPIRV::pIDRegClass,
592 &SPIRV::vpIDRegClass,
593 &SPIRV::vIDRegClass,
594 &SPIRV::vfIDRegClass,
595 };
596} // end anonymous namespace
597
598static const uint8_t CostPerUseTable[] = {
5990, 0, 0, 0, 0, 0, 0, 0, };
600
601
602static const bool InAllocatableClassTable[] = {
603false, true, true, true, true, true, true, true, };
604
605
606static const TargetRegisterInfoDesc SPIRVRegInfoDesc = { // Extra Descriptors
607CostPerUseTable, 1, InAllocatableClassTable};
608
609/// Get the weight in units of pressure for this register class.
610const RegClassWeight &SPIRVGenRegisterInfo::
611getRegClassWeight(const TargetRegisterClass *RC) const {
612 static const RegClassWeight RCWeightTable[] = {
613 {1, 7}, // ANY
614 {1, 6}, // ID
615 {1, 1}, // TYPE
616 {1, 1}, // fID
617 {1, 1}, // iID
618 {1, 1}, // pID
619 {1, 1}, // vpID
620 {1, 1}, // vID
621 {1, 1}, // vfID
622 };
623 return RCWeightTable[RC->getID()];
624}
625
626/// Get the weight in units of pressure for this register unit.
627unsigned SPIRVGenRegisterInfo::
628getRegUnitWeight(unsigned RegUnit) const {
629 assert(RegUnit < 7 && "invalid register unit");
630 // All register units have unit weight.
631 return 1;
632}
633
634
635// Get the number of dimensions of register pressure.
636unsigned SPIRVGenRegisterInfo::getNumRegPressureSets() const {
637 return 8;
638}
639
640// Get the name of this register unit pressure set.
641const char *SPIRVGenRegisterInfo::
642getRegPressureSetName(unsigned Idx) const {
643 static const char *PressureNameTable[] = {
644 "TYPE",
645 "fID",
646 "iID",
647 "pID",
648 "vpID",
649 "vID",
650 "vfID",
651 "ID",
652 };
653 return PressureNameTable[Idx];
654}
655
656// Get the register unit pressure limit for this dimension.
657// This limit must be adjusted dynamically for reserved registers.
658unsigned SPIRVGenRegisterInfo::
659getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
660 static const uint8_t PressureLimitTable[] = {
661 1, // 0: TYPE
662 1, // 1: fID
663 1, // 2: iID
664 1, // 3: pID
665 1, // 4: vpID
666 1, // 5: vID
667 1, // 6: vfID
668 7, // 7: ID
669 };
670 return PressureLimitTable[Idx];
671}
672
673/// Table of pressure sets per register class or unit.
674static const int RCSetsTable[] = {
675 /* 0 */ 0, 7, -1,
676 /* 3 */ 1, 7, -1,
677 /* 6 */ 2, 7, -1,
678 /* 9 */ 3, 7, -1,
679 /* 12 */ 4, 7, -1,
680 /* 15 */ 5, 7, -1,
681 /* 18 */ 6, 7, -1,
682};
683
684/// Get the dimensions of register pressure impacted by this register class.
685/// Returns a -1 terminated array of pressure set IDs
686const int *SPIRVGenRegisterInfo::
687getRegClassPressureSets(const TargetRegisterClass *RC) const {
688 static const uint8_t RCSetStartTable[] = {
689 1,1,0,3,6,9,12,15,18,};
690 return &RCSetsTable[RCSetStartTable[RC->getID()]];
691}
692
693/// Get the dimensions of register pressure impacted by this register unit.
694/// Returns a -1 terminated array of pressure set IDs
695const int *SPIRVGenRegisterInfo::
696getRegUnitPressureSets(unsigned RegUnit) const {
697 assert(RegUnit < 7 && "invalid register unit");
698 static const uint8_t RUSetStartTable[] = {
699 6,0,3,9,15,18,12,};
700 return &RCSetsTable[RUSetStartTable[RegUnit]];
701}
702
703extern const MCRegisterDesc SPIRVRegDesc[];
704extern const int16_t SPIRVRegDiffLists[];
705extern const LaneBitmask SPIRVLaneMaskLists[];
706extern const char SPIRVRegStrings[];
707extern const char SPIRVRegClassStrings[];
708extern const MCPhysReg SPIRVRegUnitRoots[][2];
709extern const uint16_t SPIRVSubRegIdxLists[];
710extern const uint16_t SPIRVRegEncodingTable[];
711SPIRVGenRegisterInfo::
712SPIRVGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
713 unsigned PC, unsigned HwMode)
714 : TargetRegisterInfo(&SPIRVRegInfoDesc, RegisterClasses, RegisterClasses+9,
715 SubRegIndexNameTable, SubRegIdxRangeTable, SubRegIndexLaneMaskTable,
716 LaneBitmask(0xFFFFFFFFFFFFFFFF), RegClassInfos, VTLists, HwMode) {
717 InitMCRegisterInfo(SPIRVRegDesc, 8, RA, PC,
718 SPIRVMCRegisterClasses, 9,
719 SPIRVRegUnitRoots,
720 7,
721 SPIRVRegDiffLists,
722 SPIRVLaneMaskLists,
723 SPIRVRegStrings,
724 SPIRVRegClassStrings,
725 SPIRVSubRegIdxLists,
726 1,
727 SPIRVRegEncodingTable);
728
729}
730
731
732
733ArrayRef<const uint32_t *> SPIRVGenRegisterInfo::getRegMasks() const {
734 return {};
735}
736
737bool SPIRVGenRegisterInfo::
738isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
739 return
740 false;
741}
742
743bool SPIRVGenRegisterInfo::
744isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
745 return
746 false;
747}
748
749bool SPIRVGenRegisterInfo::
750isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
751 return
752 false;
753}
754
755bool SPIRVGenRegisterInfo::
756isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
757 return
758 false;
759}
760
761bool SPIRVGenRegisterInfo::
762isConstantPhysReg(MCRegister PhysReg) const {
763 return
764 false;
765}
766
767ArrayRef<const char *> SPIRVGenRegisterInfo::getRegMaskNames() const {
768 return {};
769}
770
771const SPIRVFrameLowering *
772SPIRVGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
773 return static_cast<const SPIRVFrameLowering *>(
774 MF.getSubtarget().getFrameLowering());
775}
776
777} // end namespace llvm
778
779#endif // GET_REGINFO_TARGET_DESC
780
781