1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Subtarget Enumeration Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_SUBTARGETINFO_ENUM
11#undef GET_SUBTARGETINFO_ENUM
12
13namespace llvm {
14} // end namespace llvm
15
16#endif // GET_SUBTARGETINFO_ENUM
17
18
19#ifdef GET_SUBTARGETINFO_MACRO
20#undef GET_SUBTARGETINFO_MACRO
21#endif // GET_SUBTARGETINFO_MACRO
22
23
24#ifdef GET_SUBTARGETINFO_MC_DESC
25#undef GET_SUBTARGETINFO_MC_DESC
26
27namespace llvm {
28
29#ifdef DBGFIELD
30#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
31#endif
32#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
33#define DBGFIELD(x) x,
34#define DBGVAL_OR_NULLPTR(x) x
35#else
36#define DBGFIELD(x)
37#define DBGVAL_OR_NULLPTR(x) nullptr
38#endif
39
40// ===============================================================
41// Data tables for the new per-operand machine model.
42
43// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}
44extern const llvm::MCWriteProcResEntry SPIRVWriteProcResTable[] = {
45 { 0, 0, 0 }, // Invalid
46}; // SPIRVWriteProcResTable
47
48// {Cycles, WriteResourceID}
49extern const llvm::MCWriteLatencyEntry SPIRVWriteLatencyTable[] = {
50 { 0, 0}, // Invalid
51}; // SPIRVWriteLatencyTable
52
53// {UseIdx, WriteResourceID, Cycles}
54extern const llvm::MCReadAdvanceEntry SPIRVReadAdvanceTable[] = {
55 {0, 0, 0}, // Invalid
56}; // SPIRVReadAdvanceTable
57
58#ifdef __GNUC__
59#pragma GCC diagnostic push
60#pragma GCC diagnostic ignored "-Woverlength-strings"
61#endif
62static constexpr char SPIRVSchedClassNamesStorage[] =
63 "\0"
64 "InvalidSchedClass\0"
65 ;
66#ifdef __GNUC__
67#pragma GCC diagnostic pop
68#endif
69
70static constexpr llvm::StringTable SPIRVSchedClassNames =
71 SPIRVSchedClassNamesStorage;
72
73static const llvm::MCSchedModel NoSchedModel = {
74 MCSchedModel::DefaultIssueWidth,
75 MCSchedModel::DefaultMicroOpBufferSize,
76 MCSchedModel::DefaultLoopMicroOpBufferSize,
77 MCSchedModel::DefaultLoadLatency,
78 MCSchedModel::DefaultHighLatency,
79 MCSchedModel::DefaultMispredictPenalty,
80 false, // PostRAScheduler
81 false, // CompleteModel
82 false, // EnableIntervals
83 0, // Processor ID
84 nullptr, nullptr, 0, 0, // No instruction-level machine model.
85 DBGVAL_OR_NULLPTR(&SPIRVSchedClassNames), // SchedClassNames
86 nullptr, // No Itinerary
87 nullptr // No extra processor descriptor
88};
89
90#undef DBGFIELD
91
92#undef DBGVAL_OR_NULLPTR
93
94// Sorted (by key) array of values for CPU subtype.
95extern const llvm::SubtargetSubTypeKV SPIRVSubTypeKV[] = {
96 { "generic", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
97};
98
99// Sorted array of names of CPU subtypes, including aliases.
100extern const llvm::StringRef SPIRVNames[] = {
101"generic"};
102
103namespace SPIRV_MC {
104unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
105 const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) {
106 // Don't know how to resolve this scheduling class.
107 return 0;
108}
109} // end namespace SPIRV_MC
110
111struct SPIRVGenMCSubtargetInfo : public MCSubtargetInfo {
112 SPIRVGenMCSubtargetInfo(const Triple &TT,
113 StringRef CPU, StringRef TuneCPU, StringRef FS,
114 ArrayRef<StringRef> PN,
115 ArrayRef<SubtargetFeatureKV> PF,
116 ArrayRef<SubtargetSubTypeKV> PD,
117 const MCWriteProcResEntry *WPR,
118 const MCWriteLatencyEntry *WL,
119 const MCReadAdvanceEntry *RA, const InstrStage *IS,
120 const unsigned *OC, const unsigned *FP) :
121 MCSubtargetInfo(TT, CPU, TuneCPU, FS, PN, PF, PD,
122 WPR, WL, RA, IS, OC, FP) { }
123
124 unsigned resolveVariantSchedClass(unsigned SchedClass,
125 const MCInst *MI, const MCInstrInfo *MCII,
126 unsigned CPUID) const override {
127 return SPIRV_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);
128 }
129};
130
131static inline MCSubtargetInfo *createSPIRVMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
132 return new SPIRVGenMCSubtargetInfo(TT, CPU, TuneCPU, FS, SPIRVNames, {}, SPIRVSubTypeKV,
133 SPIRVWriteProcResTable, SPIRVWriteLatencyTable, SPIRVReadAdvanceTable,
134 nullptr, nullptr, nullptr);
135}
136
137} // end namespace llvm
138
139#endif // GET_SUBTARGETINFO_MC_DESC
140
141
142#ifdef GET_SUBTARGETINFO_TARGET_DESC
143#undef GET_SUBTARGETINFO_TARGET_DESC
144
145#include "llvm/ADT/BitmaskEnum.h"
146#include "llvm/Support/Debug.h"
147#include "llvm/Support/raw_ostream.h"
148
149// ParseSubtargetFeatures - Parses features string setting specified
150// subtarget options.
151void llvm::SPIRVSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
152 LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
153 LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
154 LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
155}
156#endif // GET_SUBTARGETINFO_TARGET_DESC
157
158
159#ifdef GET_SUBTARGETINFO_HEADER
160#undef GET_SUBTARGETINFO_HEADER
161
162namespace llvm {
163class DFAPacketizer;
164namespace SPIRV_MC {
165unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID);
166} // end namespace SPIRV_MC
167
168struct SPIRVGenSubtargetInfo : public TargetSubtargetInfo {
169 explicit SPIRVGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
170public:
171 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
172 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const override;
173 DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
174};
175} // end namespace llvm
176
177#endif // GET_SUBTARGETINFO_HEADER
178
179
180#ifdef GET_SUBTARGETINFO_CTOR
181#undef GET_SUBTARGETINFO_CTOR
182
183#include "llvm/CodeGen/TargetSchedule.h"
184
185namespace llvm {
186extern const llvm::StringRef SPIRVNames[];
187extern const llvm::SubtargetFeatureKV SPIRVFeatureKV[];
188extern const llvm::SubtargetSubTypeKV SPIRVSubTypeKV[];
189extern const llvm::MCWriteProcResEntry SPIRVWriteProcResTable[];
190extern const llvm::MCWriteLatencyEntry SPIRVWriteLatencyTable[];
191extern const llvm::MCReadAdvanceEntry SPIRVReadAdvanceTable[];
192SPIRVGenSubtargetInfo::SPIRVGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
193 : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, ArrayRef(SPIRVNames, 1), {}, ArrayRef(SPIRVSubTypeKV, 1),
194 SPIRVWriteProcResTable, SPIRVWriteLatencyTable, SPIRVReadAdvanceTable,
195 nullptr, nullptr, nullptr) {}
196
197unsigned SPIRVGenSubtargetInfo
198::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
199 report_fatal_error("Expected a variant SchedClass");
200} // SPIRVGenSubtargetInfo::resolveSchedClass
201
202unsigned SPIRVGenSubtargetInfo
203::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {
204 return SPIRV_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);
205} // SPIRVGenSubtargetInfo::resolveVariantSchedClass
206
207} // end namespace llvm
208
209#endif // GET_SUBTARGETINFO_CTOR
210
211
212#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
213#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
214
215#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
216
217
218#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
219#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
220
221#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
222
223