1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Machine Code Emitter *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9uint64_t SparcMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
10 SmallVectorImpl<MCFixup> &Fixups,
11 const MCSubtargetInfo &STI) const {
12 static const uint64_t InstBits[] = {
13 UINT64_C(0),
14 UINT64_C(0),
15 UINT64_C(0),
16 UINT64_C(0),
17 UINT64_C(0),
18 UINT64_C(0),
19 UINT64_C(0),
20 UINT64_C(0),
21 UINT64_C(0),
22 UINT64_C(0),
23 UINT64_C(0),
24 UINT64_C(0),
25 UINT64_C(0),
26 UINT64_C(0),
27 UINT64_C(0),
28 UINT64_C(0),
29 UINT64_C(0),
30 UINT64_C(0),
31 UINT64_C(0),
32 UINT64_C(0),
33 UINT64_C(0),
34 UINT64_C(0),
35 UINT64_C(0),
36 UINT64_C(0),
37 UINT64_C(0),
38 UINT64_C(0),
39 UINT64_C(0),
40 UINT64_C(0),
41 UINT64_C(0),
42 UINT64_C(0),
43 UINT64_C(0),
44 UINT64_C(0),
45 UINT64_C(0),
46 UINT64_C(0),
47 UINT64_C(0),
48 UINT64_C(0),
49 UINT64_C(0),
50 UINT64_C(0),
51 UINT64_C(0),
52 UINT64_C(0),
53 UINT64_C(0),
54 UINT64_C(0),
55 UINT64_C(0),
56 UINT64_C(0),
57 UINT64_C(0),
58 UINT64_C(0),
59 UINT64_C(0),
60 UINT64_C(0),
61 UINT64_C(0),
62 UINT64_C(0),
63 UINT64_C(0),
64 UINT64_C(0),
65 UINT64_C(0),
66 UINT64_C(0),
67 UINT64_C(0),
68 UINT64_C(0),
69 UINT64_C(0),
70 UINT64_C(0),
71 UINT64_C(0),
72 UINT64_C(0),
73 UINT64_C(0),
74 UINT64_C(0),
75 UINT64_C(0),
76 UINT64_C(0),
77 UINT64_C(0),
78 UINT64_C(0),
79 UINT64_C(0),
80 UINT64_C(0),
81 UINT64_C(0),
82 UINT64_C(0),
83 UINT64_C(0),
84 UINT64_C(0),
85 UINT64_C(0),
86 UINT64_C(0),
87 UINT64_C(0),
88 UINT64_C(0),
89 UINT64_C(0),
90 UINT64_C(0),
91 UINT64_C(0),
92 UINT64_C(0),
93 UINT64_C(0),
94 UINT64_C(0),
95 UINT64_C(0),
96 UINT64_C(0),
97 UINT64_C(0),
98 UINT64_C(0),
99 UINT64_C(0),
100 UINT64_C(0),
101 UINT64_C(0),
102 UINT64_C(0),
103 UINT64_C(0),
104 UINT64_C(0),
105 UINT64_C(0),
106 UINT64_C(0),
107 UINT64_C(0),
108 UINT64_C(0),
109 UINT64_C(0),
110 UINT64_C(0),
111 UINT64_C(0),
112 UINT64_C(0),
113 UINT64_C(0),
114 UINT64_C(0),
115 UINT64_C(0),
116 UINT64_C(0),
117 UINT64_C(0),
118 UINT64_C(0),
119 UINT64_C(0),
120 UINT64_C(0),
121 UINT64_C(0),
122 UINT64_C(0),
123 UINT64_C(0),
124 UINT64_C(0),
125 UINT64_C(0),
126 UINT64_C(0),
127 UINT64_C(0),
128 UINT64_C(0),
129 UINT64_C(0),
130 UINT64_C(0),
131 UINT64_C(0),
132 UINT64_C(0),
133 UINT64_C(0),
134 UINT64_C(0),
135 UINT64_C(0),
136 UINT64_C(0),
137 UINT64_C(0),
138 UINT64_C(0),
139 UINT64_C(0),
140 UINT64_C(0),
141 UINT64_C(0),
142 UINT64_C(0),
143 UINT64_C(0),
144 UINT64_C(0),
145 UINT64_C(0),
146 UINT64_C(0),
147 UINT64_C(0),
148 UINT64_C(0),
149 UINT64_C(0),
150 UINT64_C(0),
151 UINT64_C(0),
152 UINT64_C(0),
153 UINT64_C(0),
154 UINT64_C(0),
155 UINT64_C(0),
156 UINT64_C(0),
157 UINT64_C(0),
158 UINT64_C(0),
159 UINT64_C(0),
160 UINT64_C(0),
161 UINT64_C(0),
162 UINT64_C(0),
163 UINT64_C(0),
164 UINT64_C(0),
165 UINT64_C(0),
166 UINT64_C(0),
167 UINT64_C(0),
168 UINT64_C(0),
169 UINT64_C(0),
170 UINT64_C(0),
171 UINT64_C(0),
172 UINT64_C(0),
173 UINT64_C(0),
174 UINT64_C(0),
175 UINT64_C(0),
176 UINT64_C(0),
177 UINT64_C(0),
178 UINT64_C(0),
179 UINT64_C(0),
180 UINT64_C(0),
181 UINT64_C(0),
182 UINT64_C(0),
183 UINT64_C(0),
184 UINT64_C(0),
185 UINT64_C(0),
186 UINT64_C(0),
187 UINT64_C(0),
188 UINT64_C(0),
189 UINT64_C(0),
190 UINT64_C(0),
191 UINT64_C(0),
192 UINT64_C(0),
193 UINT64_C(0),
194 UINT64_C(0),
195 UINT64_C(0),
196 UINT64_C(0),
197 UINT64_C(0),
198 UINT64_C(0),
199 UINT64_C(0),
200 UINT64_C(0),
201 UINT64_C(0),
202 UINT64_C(0),
203 UINT64_C(0),
204 UINT64_C(0),
205 UINT64_C(0),
206 UINT64_C(0),
207 UINT64_C(0),
208 UINT64_C(0),
209 UINT64_C(0),
210 UINT64_C(0),
211 UINT64_C(0),
212 UINT64_C(0),
213 UINT64_C(0),
214 UINT64_C(0),
215 UINT64_C(0),
216 UINT64_C(0),
217 UINT64_C(0),
218 UINT64_C(0),
219 UINT64_C(0),
220 UINT64_C(0),
221 UINT64_C(0),
222 UINT64_C(0),
223 UINT64_C(0),
224 UINT64_C(0),
225 UINT64_C(0),
226 UINT64_C(0),
227 UINT64_C(0),
228 UINT64_C(0),
229 UINT64_C(0),
230 UINT64_C(0),
231 UINT64_C(0),
232 UINT64_C(0),
233 UINT64_C(0),
234 UINT64_C(0),
235 UINT64_C(0),
236 UINT64_C(0),
237 UINT64_C(0),
238 UINT64_C(0),
239 UINT64_C(0),
240 UINT64_C(0),
241 UINT64_C(0),
242 UINT64_C(0),
243 UINT64_C(0),
244 UINT64_C(0),
245 UINT64_C(0),
246 UINT64_C(0),
247 UINT64_C(0),
248 UINT64_C(0),
249 UINT64_C(0),
250 UINT64_C(0),
251 UINT64_C(0),
252 UINT64_C(0),
253 UINT64_C(0),
254 UINT64_C(0),
255 UINT64_C(0),
256 UINT64_C(0),
257 UINT64_C(0),
258 UINT64_C(0),
259 UINT64_C(0),
260 UINT64_C(0),
261 UINT64_C(0),
262 UINT64_C(0),
263 UINT64_C(0),
264 UINT64_C(0),
265 UINT64_C(0),
266 UINT64_C(0),
267 UINT64_C(0),
268 UINT64_C(0),
269 UINT64_C(0),
270 UINT64_C(0),
271 UINT64_C(0),
272 UINT64_C(0),
273 UINT64_C(0),
274 UINT64_C(0),
275 UINT64_C(0),
276 UINT64_C(0),
277 UINT64_C(0),
278 UINT64_C(0),
279 UINT64_C(0),
280 UINT64_C(0),
281 UINT64_C(0),
282 UINT64_C(0),
283 UINT64_C(0),
284 UINT64_C(0),
285 UINT64_C(0),
286 UINT64_C(0),
287 UINT64_C(0),
288 UINT64_C(0),
289 UINT64_C(0),
290 UINT64_C(0),
291 UINT64_C(0),
292 UINT64_C(0),
293 UINT64_C(0),
294 UINT64_C(0),
295 UINT64_C(0),
296 UINT64_C(0),
297 UINT64_C(0),
298 UINT64_C(0),
299 UINT64_C(0),
300 UINT64_C(0),
301 UINT64_C(0),
302 UINT64_C(0),
303 UINT64_C(0),
304 UINT64_C(0),
305 UINT64_C(0),
306 UINT64_C(0),
307 UINT64_C(0),
308 UINT64_C(0),
309 UINT64_C(0),
310 UINT64_C(0),
311 UINT64_C(0),
312 UINT64_C(0),
313 UINT64_C(0),
314 UINT64_C(0),
315 UINT64_C(0),
316 UINT64_C(0),
317 UINT64_C(0),
318 UINT64_C(0),
319 UINT64_C(0),
320 UINT64_C(0),
321 UINT64_C(0),
322 UINT64_C(0),
323 UINT64_C(0),
324 UINT64_C(0),
325 UINT64_C(0),
326 UINT64_C(0),
327 UINT64_C(0),
328 UINT64_C(0),
329 UINT64_C(0),
330 UINT64_C(0),
331 UINT64_C(0),
332 UINT64_C(0),
333 UINT64_C(0),
334 UINT64_C(0),
335 UINT64_C(0),
336 UINT64_C(0),
337 UINT64_C(0),
338 UINT64_C(0),
339 UINT64_C(0),
340 UINT64_C(0),
341 UINT64_C(2155880448), // ADDCCri
342 UINT64_C(2155872256), // ADDCCrr
343 UINT64_C(2151686144), // ADDCri
344 UINT64_C(2151677952), // ADDCrr
345 UINT64_C(2160074752), // ADDEri
346 UINT64_C(2160066560), // ADDErr
347 UINT64_C(2175795744), // ADDXC
348 UINT64_C(2175795808), // ADDXCCC
349 UINT64_C(2147491840), // ADDri
350 UINT64_C(2147483648), // ADDrr
351 UINT64_C(2175795968), // ALIGNADDR
352 UINT64_C(2175796032), // ALIGNADDRL
353 UINT64_C(2240282624), // ALLCLEAN
354 UINT64_C(2156404736), // ANDCCri
355 UINT64_C(2156396544), // ANDCCrr
356 UINT64_C(2158501888), // ANDNCCri
357 UINT64_C(2158493696), // ANDNCCrr
358 UINT64_C(2150113280), // ANDNri
359 UINT64_C(2150105088), // ANDNrr
360 UINT64_C(2148016128), // ANDri
361 UINT64_C(2148007936), // ANDrr
362 UINT64_C(2175795776), // ARRAY16
363 UINT64_C(2175795840), // ARRAY32
364 UINT64_C(2175795712), // ARRAY8
365 UINT64_C(276824064), // BA
366 UINT64_C(8388608), // BCOND
367 UINT64_C(545259520), // BCONDA
368 UINT64_C(2176851968), // BINDri
369 UINT64_C(2176843776), // BINDrr
370 UINT64_C(2175796000), // BMASK
371 UINT64_C(21495808), // BPFCC
372 UINT64_C(558366720), // BPFCCA
373 UINT64_C(557842432), // BPFCCANT
374 UINT64_C(20971520), // BPFCCNT
375 UINT64_C(4718592), // BPICC
376 UINT64_C(541589504), // BPICCA
377 UINT64_C(541065216), // BPICCANT
378 UINT64_C(4194304), // BPICCNT
379 UINT64_C(13107200), // BPR
380 UINT64_C(549978112), // BPRA
381 UINT64_C(549453824), // BPRANT
382 UINT64_C(12582912), // BPRNT
383 UINT64_C(6815744), // BPXCC
384 UINT64_C(543686656), // BPXCCA
385 UINT64_C(543162368), // BPXCCANT
386 UINT64_C(6291456), // BPXCCNT
387 UINT64_C(2175797632), // BSHUFFLE
388 UINT64_C(1073741824), // CALL
389 UINT64_C(1073741824), // CALLi
390 UINT64_C(2680168448), // CALLri
391 UINT64_C(2680168448), // CALLrii
392 UINT64_C(2680160256), // CALLrr
393 UINT64_C(2680160256), // CALLrri
394 UINT64_C(3252690944), // CASAri
395 UINT64_C(3252682752), // CASArr
396 UINT64_C(3253739520), // CASXAri
397 UINT64_C(3253731328), // CASXArr
398 UINT64_C(2175796128), // CMASK16
399 UINT64_C(2175796192), // CMASK32
400 UINT64_C(2175796064), // CMASK8
401 UINT64_C(29360128), // CPBCOND
402 UINT64_C(566231040), // CPBCONDA
403 UINT64_C(281026560), // CWBCONDri
404 UINT64_C(281018368), // CWBCONDrr
405 UINT64_C(283123712), // CXBCONDri
406 UINT64_C(283115520), // CXBCONDrr
407 UINT64_C(2179989504), // DONE
408 UINT64_C(2175795328), // EDGE16
409 UINT64_C(2175795392), // EDGE16L
410 UINT64_C(2175795424), // EDGE16LN
411 UINT64_C(2175795360), // EDGE16N
412 UINT64_C(2175795456), // EDGE32
413 UINT64_C(2175795520), // EDGE32L
414 UINT64_C(2175795552), // EDGE32LN
415 UINT64_C(2175795488), // EDGE32N
416 UINT64_C(2175795200), // EDGE8
417 UINT64_C(2175795264), // EDGE8L
418 UINT64_C(2175795296), // EDGE8LN
419 UINT64_C(2175795232), // EDGE8N
420 UINT64_C(2174746944), // FABSD
421 UINT64_C(2174746976), // FABSQ
422 UINT64_C(2174746912), // FABSS
423 UINT64_C(2174748736), // FADDD
424 UINT64_C(2174748768), // FADDQ
425 UINT64_C(2174748704), // FADDS
426 UINT64_C(2175797504), // FALIGNADATA
427 UINT64_C(2175798784), // FAND
428 UINT64_C(2175798528), // FANDNOT1
429 UINT64_C(2175798560), // FANDNOT1S
430 UINT64_C(2175798400), // FANDNOT2
431 UINT64_C(2175798432), // FANDNOT2S
432 UINT64_C(2175798816), // FANDS
433 UINT64_C(25165824), // FBCOND
434 UINT64_C(562036736), // FBCONDA
435 UINT64_C(558366720), // FBCONDA_V9
436 UINT64_C(21495808), // FBCOND_V9
437 UINT64_C(2175797376), // FCHKSM16
438 UINT64_C(2175273536), // FCMPD
439 UINT64_C(2175273536), // FCMPD_V9
440 UINT64_C(2175796544), // FCMPEQ16
441 UINT64_C(2175796672), // FCMPEQ32
442 UINT64_C(2175796480), // FCMPGT16
443 UINT64_C(2175796608), // FCMPGT32
444 UINT64_C(2175796224), // FCMPLE16
445 UINT64_C(2175796352), // FCMPLE32
446 UINT64_C(2175796288), // FCMPNE16
447 UINT64_C(2175796416), // FCMPNE32
448 UINT64_C(2175273568), // FCMPQ
449 UINT64_C(2175273568), // FCMPQ_V9
450 UINT64_C(2175273504), // FCMPS
451 UINT64_C(2175273504), // FCMPS_V9
452 UINT64_C(2174749120), // FDIVD
453 UINT64_C(2174749152), // FDIVQ
454 UINT64_C(2174749088), // FDIVS
455 UINT64_C(2174750144), // FDMULQ
456 UINT64_C(2174753344), // FDTOI
457 UINT64_C(2174753216), // FDTOQ
458 UINT64_C(2174752960), // FDTOS
459 UINT64_C(2174750784), // FDTOX
460 UINT64_C(2175797664), // FEXPAND
461 UINT64_C(2174749760), // FHADDD
462 UINT64_C(2174749728), // FHADDS
463 UINT64_C(2174749888), // FHSUBD
464 UINT64_C(2174749856), // FHSUBS
465 UINT64_C(2174753024), // FITOD
466 UINT64_C(2174753152), // FITOQ
467 UINT64_C(2174752896), // FITOS
468 UINT64_C(2175806016), // FLCMPD
469 UINT64_C(2175805984), // FLCMPS
470 UINT64_C(2178416640), // FLUSH
471 UINT64_C(2170028032), // FLUSHW
472 UINT64_C(2178424832), // FLUSHri
473 UINT64_C(2178416640), // FLUSHrr
474 UINT64_C(2176319552), // FMADDD
475 UINT64_C(2176319520), // FMADDS
476 UINT64_C(2175797248), // FMEAN16
477 UINT64_C(2174746688), // FMOVD
478 UINT64_C(2175270976), // FMOVD_FCC
479 UINT64_C(2175279168), // FMOVD_ICC
480 UINT64_C(2175283264), // FMOVD_XCC
481 UINT64_C(2174746720), // FMOVQ
482 UINT64_C(2175271008), // FMOVQ_FCC
483 UINT64_C(2175279200), // FMOVQ_ICC
484 UINT64_C(2175283296), // FMOVQ_XCC
485 UINT64_C(2175271104), // FMOVRD
486 UINT64_C(2175271136), // FMOVRQ
487 UINT64_C(2175271072), // FMOVRS
488 UINT64_C(2174746656), // FMOVS
489 UINT64_C(2175270944), // FMOVS_FCC
490 UINT64_C(2175279136), // FMOVS_ICC
491 UINT64_C(2175283232), // FMOVS_XCC
492 UINT64_C(2176319680), // FMSUBD
493 UINT64_C(2176319648), // FMSUBS
494 UINT64_C(2175796928), // FMUL8SUX16
495 UINT64_C(2175796960), // FMUL8ULX16
496 UINT64_C(2175796768), // FMUL8X16
497 UINT64_C(2175796896), // FMUL8X16AL
498 UINT64_C(2175796832), // FMUL8X16AU
499 UINT64_C(2174748992), // FMULD
500 UINT64_C(2175796992), // FMULD8SUX16
501 UINT64_C(2175797024), // FMULD8ULX16
502 UINT64_C(2174749024), // FMULQ
503 UINT64_C(2174748960), // FMULS
504 UINT64_C(2174749248), // FNADDD
505 UINT64_C(2174749216), // FNADDS
506 UINT64_C(2175798720), // FNAND
507 UINT64_C(2175798752), // FNANDS
508 UINT64_C(2174746816), // FNEGD
509 UINT64_C(2174746848), // FNEGQ
510 UINT64_C(2174746784), // FNEGS
511 UINT64_C(2174750272), // FNHADDD
512 UINT64_C(2174750240), // FNHADDS
513 UINT64_C(2176319936), // FNMADDD
514 UINT64_C(2176319904), // FNMADDS
515 UINT64_C(2176319808), // FNMSUBD
516 UINT64_C(2176319776), // FNMSUBS
517 UINT64_C(2174749504), // FNMULD
518 UINT64_C(2174749472), // FNMULS
519 UINT64_C(2175798336), // FNOR
520 UINT64_C(2175798368), // FNORS
521 UINT64_C(2175798592), // FNOT1
522 UINT64_C(2175798624), // FNOT1S
523 UINT64_C(2175798464), // FNOT2
524 UINT64_C(2175798496), // FNOT2S
525 UINT64_C(2174750496), // FNSMULD
526 UINT64_C(2175799232), // FONE
527 UINT64_C(2175799264), // FONES
528 UINT64_C(2175799168), // FOR
529 UINT64_C(2175799104), // FORNOT1
530 UINT64_C(2175799136), // FORNOT1S
531 UINT64_C(2175798976), // FORNOT2
532 UINT64_C(2175799008), // FORNOT2S
533 UINT64_C(2175799200), // FORS
534 UINT64_C(2175797088), // FPACK16
535 UINT64_C(2175797056), // FPACK32
536 UINT64_C(2175797152), // FPACKFIX
537 UINT64_C(2175797760), // FPADD16
538 UINT64_C(2175797792), // FPADD16S
539 UINT64_C(2175797824), // FPADD32
540 UINT64_C(2175797856), // FPADD32S
541 UINT64_C(2175797312), // FPADD64
542 UINT64_C(2176319488), // FPMADDX
543 UINT64_C(2176319616), // FPMADDXHI
544 UINT64_C(2175797600), // FPMERGE
545 UINT64_C(2175797888), // FPSUB16
546 UINT64_C(2175797920), // FPSUB16S
547 UINT64_C(2175797952), // FPSUB32
548 UINT64_C(2175797984), // FPSUB32S
549 UINT64_C(2174753120), // FQTOD
550 UINT64_C(2174753376), // FQTOI
551 UINT64_C(2174752992), // FQTOS
552 UINT64_C(2174750816), // FQTOX
553 UINT64_C(2175796512), // FSLAS16
554 UINT64_C(2175796640), // FSLAS32
555 UINT64_C(2175796256), // FSLL16
556 UINT64_C(2175796384), // FSLL32
557 UINT64_C(2174749984), // FSMULD
558 UINT64_C(2174747968), // FSQRTD
559 UINT64_C(2174748000), // FSQRTQ
560 UINT64_C(2174747936), // FSQRTS
561 UINT64_C(2175796576), // FSRA16
562 UINT64_C(2175796704), // FSRA32
563 UINT64_C(2175798912), // FSRC1
564 UINT64_C(2175798944), // FSRC1S
565 UINT64_C(2175799040), // FSRC2
566 UINT64_C(2175799072), // FSRC2S
567 UINT64_C(2175796320), // FSRL16
568 UINT64_C(2175796448), // FSRL32
569 UINT64_C(2174753056), // FSTOD
570 UINT64_C(2174753312), // FSTOI
571 UINT64_C(2174753184), // FSTOQ
572 UINT64_C(2174750752), // FSTOX
573 UINT64_C(2174748864), // FSUBD
574 UINT64_C(2174748896), // FSUBQ
575 UINT64_C(2174748832), // FSUBS
576 UINT64_C(2175798848), // FXNOR
577 UINT64_C(2175798880), // FXNORS
578 UINT64_C(2175798656), // FXOR
579 UINT64_C(2175798688), // FXORS
580 UINT64_C(2174750976), // FXTOD
581 UINT64_C(2174751104), // FXTOQ
582 UINT64_C(2174750848), // FXTOS
583 UINT64_C(2175798272), // FZERO
584 UINT64_C(2175798304), // FZEROS
585 UINT64_C(3226992640), // GDOP_LDXrr
586 UINT64_C(3221225472), // GDOP_LDrr
587 UINT64_C(2340945920), // INVALW
588 UINT64_C(2176851968), // JMPLri
589 UINT64_C(2176843776), // JMPLrr
590 UINT64_C(3229622272), // LDAri
591 UINT64_C(3229614080), // LDArr
592 UINT64_C(3246923776), // LDCSRri
593 UINT64_C(3246915584), // LDCSRrr
594 UINT64_C(3246399488), // LDCri
595 UINT64_C(3246391296), // LDCrr
596 UINT64_C(3231195136), // LDDAri
597 UINT64_C(3231186944), // LDDArr
598 UINT64_C(3247972352), // LDDCri
599 UINT64_C(3247964160), // LDDCrr
600 UINT64_C(3247972352), // LDDFAri
601 UINT64_C(3247964160), // LDDFArr
602 UINT64_C(3239583744), // LDDFri
603 UINT64_C(3239575552), // LDDFrr
604 UINT64_C(3222806528), // LDDri
605 UINT64_C(3222798336), // LDDrr
606 UINT64_C(3246399488), // LDFAri
607 UINT64_C(3246391296), // LDFArr
608 UINT64_C(3238535168), // LDFSRri
609 UINT64_C(3238526976), // LDFSRrr
610 UINT64_C(3238010880), // LDFri
611 UINT64_C(3238002688), // LDFrr
612 UINT64_C(3247448064), // LDQFAri
613 UINT64_C(3247439872), // LDQFArr
614 UINT64_C(3239059456), // LDQFri
615 UINT64_C(3239051264), // LDQFrr
616 UINT64_C(3234340864), // LDSBAri
617 UINT64_C(3234332672), // LDSBArr
618 UINT64_C(3225952256), // LDSBri
619 UINT64_C(3225944064), // LDSBrr
620 UINT64_C(3234865152), // LDSHAri
621 UINT64_C(3234856960), // LDSHArr
622 UINT64_C(3226476544), // LDSHri
623 UINT64_C(3226468352), // LDSHrr
624 UINT64_C(3236438016), // LDSTUBAri
625 UINT64_C(3236429824), // LDSTUBArr
626 UINT64_C(3228049408), // LDSTUBri
627 UINT64_C(3228041216), // LDSTUBrr
628 UINT64_C(3233816576), // LDSWAri
629 UINT64_C(3233808384), // LDSWArr
630 UINT64_C(3225427968), // LDSWri
631 UINT64_C(3225419776), // LDSWrr
632 UINT64_C(3230146560), // LDUBAri
633 UINT64_C(3230138368), // LDUBArr
634 UINT64_C(3221757952), // LDUBri
635 UINT64_C(3221749760), // LDUBrr
636 UINT64_C(3230670848), // LDUHAri
637 UINT64_C(3230662656), // LDUHArr
638 UINT64_C(3222282240), // LDUHri
639 UINT64_C(3222274048), // LDUHrr
640 UINT64_C(3235389440), // LDXAri
641 UINT64_C(3235381248), // LDXArr
642 UINT64_C(3272089600), // LDXFSRri
643 UINT64_C(3272081408), // LDXFSRrr
644 UINT64_C(3227000832), // LDXri
645 UINT64_C(3226992640), // LDXrr
646 UINT64_C(3221233664), // LDri
647 UINT64_C(3221225472), // LDrr
648 UINT64_C(2175795936), // LZCNT
649 UINT64_C(2168709120), // MEMBARi
650 UINT64_C(2175803904), // MOVDTOX
651 UINT64_C(2170560512), // MOVFCCri
652 UINT64_C(2170552320), // MOVFCCrr
653 UINT64_C(2170822656), // MOVICCri
654 UINT64_C(2170814464), // MOVICCrr
655 UINT64_C(2172133376), // MOVRri
656 UINT64_C(2172125184), // MOVRrr
657 UINT64_C(2175804000), // MOVSTOSW
658 UINT64_C(2175803936), // MOVSTOUW
659 UINT64_C(2175804192), // MOVWTOS
660 UINT64_C(2170826752), // MOVXCCri
661 UINT64_C(2170818560), // MOVXCCrr
662 UINT64_C(2175804160), // MOVXTOD
663 UINT64_C(2166366208), // MULSCCri
664 UINT64_C(2166358016), // MULSCCrr
665 UINT64_C(2152210432), // MULXri
666 UINT64_C(2152202240), // MULXrr
667 UINT64_C(16777216), // NOP
668 UINT64_C(2307391488), // NORMALW
669 UINT64_C(2156929024), // ORCCri
670 UINT64_C(2156920832), // ORCCrr
671 UINT64_C(2159026176), // ORNCCri
672 UINT64_C(2159017984), // ORNCCrr
673 UINT64_C(2150637568), // ORNri
674 UINT64_C(2150629376), // ORNrr
675 UINT64_C(2148540416), // ORri
676 UINT64_C(2148532224), // ORrr
677 UINT64_C(2273837056), // OTHERW
678 UINT64_C(2175797184), // PDIST
679 UINT64_C(2175797216), // PDISTN
680 UINT64_C(2171600896), // POPCrr
681 UINT64_C(3253215232), // PREFETCHAi
682 UINT64_C(3253207040), // PREFETCHAr
683 UINT64_C(3244826624), // PREFETCHi
684 UINT64_C(3244818432), // PREFETCHr
685 UINT64_C(2206736384), // PWRPSRri
686 UINT64_C(2206728192), // PWRPSRrr
687 UINT64_C(2168455168), // RDASR
688 UINT64_C(2169749504), // RDFQ
689 UINT64_C(2169503744), // RDPR
690 UINT64_C(2168979456), // RDPSR
691 UINT64_C(2170028032), // RDTBR
692 UINT64_C(2169503744), // RDWIM
693 UINT64_C(2206728192), // RESTORED
694 UINT64_C(2179473408), // RESTOREri
695 UINT64_C(2179465216), // RESTORErr
696 UINT64_C(2177359872), // RET
697 UINT64_C(2177097728), // RETL
698 UINT64_C(2213543936), // RETRY
699 UINT64_C(2177376256), // RETTri
700 UINT64_C(2177368064), // RETTrr
701 UINT64_C(2173173760), // SAVED
702 UINT64_C(2178949120), // SAVEri
703 UINT64_C(2178940928), // SAVErr
704 UINT64_C(2163744768), // SDIVCCri
705 UINT64_C(2163736576), // SDIVCCrr
706 UINT64_C(2171084800), // SDIVXri
707 UINT64_C(2171076608), // SDIVXrr
708 UINT64_C(2155356160), // SDIVri
709 UINT64_C(2155347968), // SDIVrr
710 UINT64_C(16777216), // SETHIi
711 UINT64_C(2175799296), // SHUTDOWN
712 UINT64_C(2175799328), // SIAM
713 UINT64_C(2675974144), // SIR
714 UINT64_C(2166894592), // SLLXri
715 UINT64_C(2166886400), // SLLXrr
716 UINT64_C(2166890496), // SLLri
717 UINT64_C(2166882304), // SLLrr
718 UINT64_C(2180521984), // SMACri
719 UINT64_C(2180513792), // SMACrr
720 UINT64_C(2161647616), // SMULCCri
721 UINT64_C(2161639424), // SMULCCrr
722 UINT64_C(2153259008), // SMULri
723 UINT64_C(2153250816), // SMULrr
724 UINT64_C(2167943168), // SRAXri
725 UINT64_C(2167934976), // SRAXrr
726 UINT64_C(2167939072), // SRAri
727 UINT64_C(2167930880), // SRArr
728 UINT64_C(2167418880), // SRLXri
729 UINT64_C(2167410688), // SRLXrr
730 UINT64_C(2167414784), // SRLri
731 UINT64_C(2167406592), // SRLrr
732 UINT64_C(3231719424), // STAri
733 UINT64_C(3231711232), // STArr
734 UINT64_C(2168700928), // STBAR
735 UINT64_C(3232243712), // STBAri
736 UINT64_C(3232235520), // STBArr
737 UINT64_C(3223855104), // STBri
738 UINT64_C(3223846912), // STBrr
739 UINT64_C(3249020928), // STCSRri
740 UINT64_C(3249012736), // STCSRrr
741 UINT64_C(3248496640), // STCri
742 UINT64_C(3248488448), // STCrr
743 UINT64_C(3233292288), // STDAri
744 UINT64_C(3233284096), // STDArr
745 UINT64_C(3249545216), // STDCQri
746 UINT64_C(3249537024), // STDCQrr
747 UINT64_C(3250069504), // STDCri
748 UINT64_C(3250061312), // STDCrr
749 UINT64_C(3250069504), // STDFAri
750 UINT64_C(3250061312), // STDFArr
751 UINT64_C(3241156608), // STDFQri
752 UINT64_C(3241148416), // STDFQrr
753 UINT64_C(3241680896), // STDFri
754 UINT64_C(3241672704), // STDFrr
755 UINT64_C(3224903680), // STDri
756 UINT64_C(3224895488), // STDrr
757 UINT64_C(3248496640), // STFAri
758 UINT64_C(3248488448), // STFArr
759 UINT64_C(3240632320), // STFSRri
760 UINT64_C(3240624128), // STFSRrr
761 UINT64_C(3240108032), // STFri
762 UINT64_C(3240099840), // STFrr
763 UINT64_C(3232768000), // STHAri
764 UINT64_C(3232759808), // STHArr
765 UINT64_C(3224379392), // STHri
766 UINT64_C(3224371200), // STHrr
767 UINT64_C(3249545216), // STQFAri
768 UINT64_C(3249537024), // STQFArr
769 UINT64_C(3241156608), // STQFri
770 UINT64_C(3241148416), // STQFrr
771 UINT64_C(3236962304), // STXAri
772 UINT64_C(3236954112), // STXArr
773 UINT64_C(3274186752), // STXFSRri
774 UINT64_C(3274178560), // STXFSRrr
775 UINT64_C(3228573696), // STXri
776 UINT64_C(3228565504), // STXrr
777 UINT64_C(3223330816), // STri
778 UINT64_C(3223322624), // STrr
779 UINT64_C(2157977600), // SUBCCri
780 UINT64_C(2157969408), // SUBCCrr
781 UINT64_C(2153783296), // SUBCri
782 UINT64_C(2153775104), // SUBCrr
783 UINT64_C(2162171904), // SUBEri
784 UINT64_C(2162163712), // SUBErr
785 UINT64_C(2149588992), // SUBri
786 UINT64_C(2149580800), // SUBrr
787 UINT64_C(3237486592), // SWAPAri
788 UINT64_C(3237478400), // SWAPArr
789 UINT64_C(3229097984), // SWAPri
790 UINT64_C(3229089792), // SWAPrr
791 UINT64_C(2446336001), // TA1
792 UINT64_C(2446336003), // TA3
793 UINT64_C(2446336005), // TA5
794 UINT64_C(2165317632), // TADDCCTVri
795 UINT64_C(2165309440), // TADDCCTVrr
796 UINT64_C(2164269056), // TADDCCri
797 UINT64_C(2164260864), // TADDCCrr
798 UINT64_C(1073741824), // TAIL_CALL
799 UINT64_C(2176851968), // TAIL_CALLri
800 UINT64_C(2177900544), // TICCri
801 UINT64_C(2177892352), // TICCrr
802 UINT64_C(2147483648), // TLS_ADDrr
803 UINT64_C(1073741824), // TLS_CALL
804 UINT64_C(3226992640), // TLS_LDXrr
805 UINT64_C(3221225472), // TLS_LDrr
806 UINT64_C(2177900544), // TRAPri
807 UINT64_C(2177892352), // TRAPrr
808 UINT64_C(2165841920), // TSUBCCTVri
809 UINT64_C(2165833728), // TSUBCCTVrr
810 UINT64_C(2164793344), // TSUBCCri
811 UINT64_C(2164785152), // TSUBCCrr
812 UINT64_C(2177904640), // TXCCri
813 UINT64_C(2177896448), // TXCCrr
814 UINT64_C(2163220480), // UDIVCCri
815 UINT64_C(2163212288), // UDIVCCrr
816 UINT64_C(2154307584), // UDIVXri
817 UINT64_C(2154299392), // UDIVXrr
818 UINT64_C(2154831872), // UDIVri
819 UINT64_C(2154823680), // UDIVrr
820 UINT64_C(2179997696), // UMACri
821 UINT64_C(2179989504), // UMACrr
822 UINT64_C(2161123328), // UMULCCri
823 UINT64_C(2161115136), // UMULCCrr
824 UINT64_C(2175795904), // UMULXHI
825 UINT64_C(2152734720), // UMULri
826 UINT64_C(2152726528), // UMULrr
827 UINT64_C(0), // UNIMP
828 UINT64_C(2175273536), // V9FCMPD
829 UINT64_C(2175273664), // V9FCMPED
830 UINT64_C(2175273696), // V9FCMPEQ
831 UINT64_C(2175273632), // V9FCMPES
832 UINT64_C(2175273568), // V9FCMPQ
833 UINT64_C(2175273504), // V9FCMPS
834 UINT64_C(2175270976), // V9FMOVD_FCC
835 UINT64_C(2175271008), // V9FMOVQ_FCC
836 UINT64_C(2175270944), // V9FMOVS_FCC
837 UINT64_C(2170560512), // V9MOVFCCri
838 UINT64_C(2170552320), // V9MOVFCCrr
839 UINT64_C(2172657664), // WRASRri
840 UINT64_C(2172649472), // WRASRrr
841 UINT64_C(2173706240), // WRPRri
842 UINT64_C(2173698048), // WRPRrr
843 UINT64_C(2173181952), // WRPSRri
844 UINT64_C(2173173760), // WRPSRrr
845 UINT64_C(2174230528), // WRTBRri
846 UINT64_C(2174222336), // WRTBRrr
847 UINT64_C(2173706240), // WRWIMri
848 UINT64_C(2173698048), // WRWIMrr
849 UINT64_C(2175804064), // XMULX
850 UINT64_C(2175804096), // XMULXHI
851 UINT64_C(2159550464), // XNORCCri
852 UINT64_C(2159542272), // XNORCCrr
853 UINT64_C(2151161856), // XNORri
854 UINT64_C(2151153664), // XNORrr
855 UINT64_C(2157453312), // XORCCri
856 UINT64_C(2157445120), // XORCCrr
857 UINT64_C(2149064704), // XORri
858 UINT64_C(2149056512), // XORrr
859 UINT64_C(0)
860 };
861 const unsigned opcode = MI.getOpcode();
862 uint64_t Value = InstBits[opcode];
863 uint64_t op = 0;
864 (void)op; // suppress warning
865 switch (opcode) {
866 case SP::ALLCLEAN:
867 case SP::DONE:
868 case SP::FLUSH:
869 case SP::FLUSHW:
870 case SP::INVALW:
871 case SP::NOP:
872 case SP::NORMALW:
873 case SP::OTHERW:
874 case SP::RESTORED:
875 case SP::RETRY:
876 case SP::SAVED:
877 case SP::SHUTDOWN:
878 case SP::STBAR:
879 case SP::TA1:
880 case SP::TA3:
881 case SP::TA5: {
882 break;
883 }
884 case SP::BPFCC:
885 case SP::BPFCCA:
886 case SP::BPFCCANT:
887 case SP::BPFCCNT: {
888 // op: cc
889 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
890 op &= UINT64_C(3);
891 op <<= 20;
892 Value |= op;
893 // op: cond
894 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
895 op &= UINT64_C(15);
896 op <<= 25;
897 Value |= op;
898 // op: imm19
899 op = getBranchPredTargetOpValue(MI, OpNo: 0, Fixups, STI);
900 op &= UINT64_C(524287);
901 Value |= op;
902 break;
903 }
904 case SP::BPICC:
905 case SP::BPICCA:
906 case SP::BPICCANT:
907 case SP::BPICCNT:
908 case SP::BPXCC:
909 case SP::BPXCCA:
910 case SP::BPXCCANT:
911 case SP::BPXCCNT:
912 case SP::FBCONDA_V9:
913 case SP::FBCOND_V9: {
914 // op: cond
915 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
916 op &= UINT64_C(15);
917 op <<= 25;
918 Value |= op;
919 // op: imm19
920 op = getBranchPredTargetOpValue(MI, OpNo: 0, Fixups, STI);
921 op &= UINT64_C(524287);
922 Value |= op;
923 break;
924 }
925 case SP::CALL:
926 case SP::CALLi:
927 case SP::TAIL_CALL:
928 case SP::TLS_CALL: {
929 // op: disp
930 op = getCallTargetOpValue(MI, OpNo: 0, Fixups, STI);
931 op &= UINT64_C(1073741823);
932 Value |= op;
933 break;
934 }
935 case SP::CWBCONDrr:
936 case SP::CXBCONDrr: {
937 // op: imm10
938 op = getCompareAndBranchTargetOpValue(MI, OpNo: 0, Fixups, STI);
939 Value |= (op & UINT64_C(768)) << 11;
940 Value |= (op & UINT64_C(255)) << 5;
941 // op: rs1
942 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
943 op &= UINT64_C(31);
944 op <<= 14;
945 Value |= op;
946 // op: rs2
947 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
948 op &= UINT64_C(31);
949 Value |= op;
950 // op: cond
951 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
952 Value |= (op & UINT64_C(8)) << 26;
953 Value |= (op & UINT64_C(7)) << 25;
954 break;
955 }
956 case SP::CWBCONDri:
957 case SP::CXBCONDri: {
958 // op: imm10
959 op = getCompareAndBranchTargetOpValue(MI, OpNo: 0, Fixups, STI);
960 Value |= (op & UINT64_C(768)) << 11;
961 Value |= (op & UINT64_C(255)) << 5;
962 // op: rs1
963 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
964 op &= UINT64_C(31);
965 op <<= 14;
966 Value |= op;
967 // op: simm5
968 op = getSImm5OpValue(MI, OpNo: 3, Fixups, STI);
969 op &= UINT64_C(31);
970 Value |= op;
971 // op: cond
972 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
973 Value |= (op & UINT64_C(8)) << 26;
974 Value |= (op & UINT64_C(7)) << 25;
975 break;
976 }
977 case SP::BPR:
978 case SP::BPRA:
979 case SP::BPRANT:
980 case SP::BPRNT: {
981 // op: imm16
982 op = getBranchOnRegTargetOpValue(MI, OpNo: 0, Fixups, STI);
983 Value |= (op & UINT64_C(49152)) << 6;
984 Value |= (op & UINT64_C(16383));
985 // op: rs1
986 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
987 op &= UINT64_C(31);
988 op <<= 14;
989 Value |= op;
990 // op: rcond
991 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
992 op &= UINT64_C(7);
993 op <<= 25;
994 Value |= op;
995 break;
996 }
997 case SP::BA: {
998 // op: imm22
999 op = getBranchTargetOpValue(MI, OpNo: 0, Fixups, STI);
1000 op &= UINT64_C(4194303);
1001 Value |= op;
1002 break;
1003 }
1004 case SP::BCOND:
1005 case SP::BCONDA:
1006 case SP::CPBCOND:
1007 case SP::CPBCONDA:
1008 case SP::FBCOND:
1009 case SP::FBCONDA: {
1010 // op: imm22
1011 op = getBranchTargetOpValue(MI, OpNo: 0, Fixups, STI);
1012 op &= UINT64_C(4194303);
1013 Value |= op;
1014 // op: cond
1015 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
1016 op &= UINT64_C(15);
1017 op <<= 25;
1018 Value |= op;
1019 break;
1020 }
1021 case SP::UNIMP: {
1022 // op: imm22
1023 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1024 op &= UINT64_C(4194303);
1025 Value |= op;
1026 break;
1027 }
1028 case SP::SETHIi: {
1029 // op: imm22
1030 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
1031 op &= UINT64_C(4194303);
1032 Value |= op;
1033 // op: rd
1034 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1035 op &= UINT64_C(31);
1036 op <<= 25;
1037 Value |= op;
1038 break;
1039 }
1040 case SP::SIAM: {
1041 // op: mode
1042 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1043 op &= UINT64_C(7);
1044 Value |= op;
1045 break;
1046 }
1047 case SP::FONE:
1048 case SP::FONES:
1049 case SP::FZERO:
1050 case SP::FZEROS:
1051 case SP::RDFQ:
1052 case SP::RDPSR:
1053 case SP::RDTBR:
1054 case SP::RDWIM: {
1055 // op: rd
1056 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1057 op &= UINT64_C(31);
1058 op <<= 25;
1059 Value |= op;
1060 break;
1061 }
1062 case SP::V9MOVFCCrr: {
1063 // op: rd
1064 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1065 op &= UINT64_C(31);
1066 op <<= 25;
1067 Value |= op;
1068 // op: cc
1069 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
1070 op &= UINT64_C(3);
1071 op <<= 11;
1072 Value |= op;
1073 // op: cond
1074 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
1075 op &= UINT64_C(15);
1076 op <<= 14;
1077 Value |= op;
1078 // op: rs2
1079 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
1080 op &= UINT64_C(31);
1081 Value |= op;
1082 break;
1083 }
1084 case SP::V9MOVFCCri: {
1085 // op: rd
1086 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1087 op &= UINT64_C(31);
1088 op <<= 25;
1089 Value |= op;
1090 // op: cc
1091 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
1092 op &= UINT64_C(3);
1093 op <<= 11;
1094 Value |= op;
1095 // op: cond
1096 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
1097 op &= UINT64_C(15);
1098 op <<= 14;
1099 Value |= op;
1100 // op: simm11
1101 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
1102 op &= UINT64_C(2047);
1103 Value |= op;
1104 break;
1105 }
1106 case SP::FMOVD_FCC:
1107 case SP::FMOVD_ICC:
1108 case SP::FMOVD_XCC:
1109 case SP::FMOVQ_FCC:
1110 case SP::FMOVQ_ICC:
1111 case SP::FMOVQ_XCC:
1112 case SP::FMOVS_FCC:
1113 case SP::FMOVS_ICC:
1114 case SP::FMOVS_XCC:
1115 case SP::MOVFCCrr:
1116 case SP::MOVICCrr:
1117 case SP::MOVXCCrr: {
1118 // op: rd
1119 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1120 op &= UINT64_C(31);
1121 op <<= 25;
1122 Value |= op;
1123 // op: cond
1124 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
1125 op &= UINT64_C(15);
1126 op <<= 14;
1127 Value |= op;
1128 // op: rs2
1129 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
1130 op &= UINT64_C(31);
1131 Value |= op;
1132 break;
1133 }
1134 case SP::MOVFCCri:
1135 case SP::MOVICCri:
1136 case SP::MOVXCCri: {
1137 // op: rd
1138 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1139 op &= UINT64_C(31);
1140 op <<= 25;
1141 Value |= op;
1142 // op: cond
1143 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
1144 op &= UINT64_C(15);
1145 op <<= 14;
1146 Value |= op;
1147 // op: simm11
1148 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
1149 op &= UINT64_C(2047);
1150 Value |= op;
1151 break;
1152 }
1153 case SP::V9FMOVD_FCC:
1154 case SP::V9FMOVQ_FCC:
1155 case SP::V9FMOVS_FCC: {
1156 // op: rd
1157 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1158 op &= UINT64_C(31);
1159 op <<= 25;
1160 Value |= op;
1161 // op: cond
1162 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
1163 op &= UINT64_C(15);
1164 op <<= 14;
1165 Value |= op;
1166 // op: opf_cc
1167 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
1168 op &= UINT64_C(3);
1169 op <<= 11;
1170 Value |= op;
1171 // op: rs2
1172 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
1173 op &= UINT64_C(31);
1174 Value |= op;
1175 break;
1176 }
1177 case SP::FNOT1:
1178 case SP::FNOT1S:
1179 case SP::FSRC1:
1180 case SP::FSRC1S:
1181 case SP::RDASR:
1182 case SP::RDPR: {
1183 // op: rd
1184 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1185 op &= UINT64_C(31);
1186 op <<= 25;
1187 Value |= op;
1188 // op: rs1
1189 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
1190 op &= UINT64_C(31);
1191 op <<= 14;
1192 Value |= op;
1193 break;
1194 }
1195 case SP::LDArr:
1196 case SP::LDDArr:
1197 case SP::LDDFArr:
1198 case SP::LDFArr:
1199 case SP::LDQFArr:
1200 case SP::LDSBArr:
1201 case SP::LDSHArr:
1202 case SP::LDSTUBArr:
1203 case SP::LDSWArr:
1204 case SP::LDUBArr:
1205 case SP::LDUHArr:
1206 case SP::LDXArr:
1207 case SP::SWAPArr: {
1208 // op: rd
1209 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1210 op &= UINT64_C(31);
1211 op <<= 25;
1212 Value |= op;
1213 // op: rs1
1214 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
1215 op &= UINT64_C(31);
1216 op <<= 14;
1217 Value |= op;
1218 // op: asi
1219 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
1220 op &= UINT64_C(255);
1221 op <<= 5;
1222 Value |= op;
1223 // op: rs2
1224 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
1225 op &= UINT64_C(31);
1226 Value |= op;
1227 break;
1228 }
1229 case SP::CASArr:
1230 case SP::CASXArr: {
1231 // op: rd
1232 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1233 op &= UINT64_C(31);
1234 op <<= 25;
1235 Value |= op;
1236 // op: rs1
1237 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
1238 op &= UINT64_C(31);
1239 op <<= 14;
1240 Value |= op;
1241 // op: asi
1242 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
1243 op &= UINT64_C(255);
1244 op <<= 5;
1245 Value |= op;
1246 // op: rs2
1247 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
1248 op &= UINT64_C(31);
1249 Value |= op;
1250 break;
1251 }
1252 case SP::ADDCCrr:
1253 case SP::ADDCrr:
1254 case SP::ADDErr:
1255 case SP::ADDXC:
1256 case SP::ADDXCCC:
1257 case SP::ADDrr:
1258 case SP::ALIGNADDR:
1259 case SP::ALIGNADDRL:
1260 case SP::ANDCCrr:
1261 case SP::ANDNCCrr:
1262 case SP::ANDNrr:
1263 case SP::ANDrr:
1264 case SP::ARRAY8:
1265 case SP::ARRAY16:
1266 case SP::ARRAY32:
1267 case SP::BMASK:
1268 case SP::BSHUFFLE:
1269 case SP::CASAri:
1270 case SP::CASXAri:
1271 case SP::EDGE8:
1272 case SP::EDGE8L:
1273 case SP::EDGE8LN:
1274 case SP::EDGE8N:
1275 case SP::EDGE16:
1276 case SP::EDGE16L:
1277 case SP::EDGE16LN:
1278 case SP::EDGE16N:
1279 case SP::EDGE32:
1280 case SP::EDGE32L:
1281 case SP::EDGE32LN:
1282 case SP::EDGE32N:
1283 case SP::FADDD:
1284 case SP::FADDQ:
1285 case SP::FADDS:
1286 case SP::FALIGNADATA:
1287 case SP::FAND:
1288 case SP::FANDNOT1:
1289 case SP::FANDNOT1S:
1290 case SP::FANDNOT2:
1291 case SP::FANDNOT2S:
1292 case SP::FANDS:
1293 case SP::FCHKSM16:
1294 case SP::FCMPEQ16:
1295 case SP::FCMPEQ32:
1296 case SP::FCMPGT16:
1297 case SP::FCMPGT32:
1298 case SP::FCMPLE16:
1299 case SP::FCMPLE32:
1300 case SP::FCMPNE16:
1301 case SP::FCMPNE32:
1302 case SP::FDIVD:
1303 case SP::FDIVQ:
1304 case SP::FDIVS:
1305 case SP::FDMULQ:
1306 case SP::FHADDD:
1307 case SP::FHADDS:
1308 case SP::FHSUBD:
1309 case SP::FHSUBS:
1310 case SP::FLCMPD:
1311 case SP::FLCMPS:
1312 case SP::FMEAN16:
1313 case SP::FMUL8SUX16:
1314 case SP::FMUL8ULX16:
1315 case SP::FMUL8X16:
1316 case SP::FMUL8X16AL:
1317 case SP::FMUL8X16AU:
1318 case SP::FMULD:
1319 case SP::FMULD8SUX16:
1320 case SP::FMULD8ULX16:
1321 case SP::FMULQ:
1322 case SP::FMULS:
1323 case SP::FNADDD:
1324 case SP::FNADDS:
1325 case SP::FNAND:
1326 case SP::FNANDS:
1327 case SP::FNHADDD:
1328 case SP::FNHADDS:
1329 case SP::FNMULD:
1330 case SP::FNMULS:
1331 case SP::FNOR:
1332 case SP::FNORS:
1333 case SP::FNSMULD:
1334 case SP::FOR:
1335 case SP::FORNOT1:
1336 case SP::FORNOT1S:
1337 case SP::FORNOT2:
1338 case SP::FORNOT2S:
1339 case SP::FORS:
1340 case SP::FPACK32:
1341 case SP::FPADD16:
1342 case SP::FPADD16S:
1343 case SP::FPADD32:
1344 case SP::FPADD32S:
1345 case SP::FPADD64:
1346 case SP::FPMERGE:
1347 case SP::FPSUB16:
1348 case SP::FPSUB16S:
1349 case SP::FPSUB32:
1350 case SP::FPSUB32S:
1351 case SP::FSLAS16:
1352 case SP::FSLAS32:
1353 case SP::FSLL16:
1354 case SP::FSLL32:
1355 case SP::FSMULD:
1356 case SP::FSRA16:
1357 case SP::FSRA32:
1358 case SP::FSRL16:
1359 case SP::FSRL32:
1360 case SP::FSUBD:
1361 case SP::FSUBQ:
1362 case SP::FSUBS:
1363 case SP::FXNOR:
1364 case SP::FXNORS:
1365 case SP::FXOR:
1366 case SP::FXORS:
1367 case SP::GDOP_LDXrr:
1368 case SP::GDOP_LDrr:
1369 case SP::JMPLrr:
1370 case SP::LDCrr:
1371 case SP::LDDCrr:
1372 case SP::LDDFrr:
1373 case SP::LDDrr:
1374 case SP::LDFrr:
1375 case SP::LDQFrr:
1376 case SP::LDSBrr:
1377 case SP::LDSHrr:
1378 case SP::LDSTUBrr:
1379 case SP::LDSWrr:
1380 case SP::LDUBrr:
1381 case SP::LDUHrr:
1382 case SP::LDXrr:
1383 case SP::LDrr:
1384 case SP::MULSCCrr:
1385 case SP::MULXrr:
1386 case SP::ORCCrr:
1387 case SP::ORNCCrr:
1388 case SP::ORNrr:
1389 case SP::ORrr:
1390 case SP::PDIST:
1391 case SP::PDISTN:
1392 case SP::RESTORErr:
1393 case SP::SAVErr:
1394 case SP::SDIVCCrr:
1395 case SP::SDIVXrr:
1396 case SP::SDIVrr:
1397 case SP::SLLXrr:
1398 case SP::SLLrr:
1399 case SP::SMACrr:
1400 case SP::SMULCCrr:
1401 case SP::SMULrr:
1402 case SP::SRAXrr:
1403 case SP::SRArr:
1404 case SP::SRLXrr:
1405 case SP::SRLrr:
1406 case SP::SUBCCrr:
1407 case SP::SUBCrr:
1408 case SP::SUBErr:
1409 case SP::SUBrr:
1410 case SP::SWAPrr:
1411 case SP::TADDCCTVrr:
1412 case SP::TADDCCrr:
1413 case SP::TLS_ADDrr:
1414 case SP::TLS_LDXrr:
1415 case SP::TLS_LDrr:
1416 case SP::TSUBCCTVrr:
1417 case SP::TSUBCCrr:
1418 case SP::UDIVCCrr:
1419 case SP::UDIVXrr:
1420 case SP::UDIVrr:
1421 case SP::UMACrr:
1422 case SP::UMULCCrr:
1423 case SP::UMULXHI:
1424 case SP::UMULrr:
1425 case SP::V9FCMPD:
1426 case SP::V9FCMPED:
1427 case SP::V9FCMPEQ:
1428 case SP::V9FCMPES:
1429 case SP::V9FCMPQ:
1430 case SP::V9FCMPS:
1431 case SP::WRASRrr:
1432 case SP::WRPRrr:
1433 case SP::XMULX:
1434 case SP::XMULXHI:
1435 case SP::XNORCCrr:
1436 case SP::XNORrr:
1437 case SP::XORCCrr:
1438 case SP::XORrr: {
1439 // op: rd
1440 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1441 op &= UINT64_C(31);
1442 op <<= 25;
1443 Value |= op;
1444 // op: rs1
1445 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
1446 op &= UINT64_C(31);
1447 op <<= 14;
1448 Value |= op;
1449 // op: rs2
1450 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
1451 op &= UINT64_C(31);
1452 Value |= op;
1453 break;
1454 }
1455 case SP::FMOVRD:
1456 case SP::FMOVRQ:
1457 case SP::FMOVRS:
1458 case SP::MOVRrr: {
1459 // op: rd
1460 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1461 op &= UINT64_C(31);
1462 op <<= 25;
1463 Value |= op;
1464 // op: rs1
1465 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
1466 op &= UINT64_C(31);
1467 op <<= 14;
1468 Value |= op;
1469 // op: rs2
1470 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
1471 op &= UINT64_C(31);
1472 Value |= op;
1473 // op: rcond
1474 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
1475 op &= UINT64_C(7);
1476 op <<= 10;
1477 Value |= op;
1478 break;
1479 }
1480 case SP::FMADDD:
1481 case SP::FMADDS:
1482 case SP::FMSUBD:
1483 case SP::FMSUBS:
1484 case SP::FNMADDD:
1485 case SP::FNMADDS:
1486 case SP::FNMSUBD:
1487 case SP::FNMSUBS:
1488 case SP::FPMADDX:
1489 case SP::FPMADDXHI: {
1490 // op: rd
1491 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1492 op &= UINT64_C(31);
1493 op <<= 25;
1494 Value |= op;
1495 // op: rs1
1496 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
1497 op &= UINT64_C(31);
1498 op <<= 14;
1499 Value |= op;
1500 // op: rs3
1501 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
1502 op &= UINT64_C(31);
1503 op <<= 9;
1504 Value |= op;
1505 // op: rs2
1506 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
1507 op &= UINT64_C(31);
1508 Value |= op;
1509 break;
1510 }
1511 case SP::SLLXri:
1512 case SP::SLLri:
1513 case SP::SRAXri:
1514 case SP::SRAri:
1515 case SP::SRLXri:
1516 case SP::SRLri: {
1517 // op: rd
1518 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1519 op &= UINT64_C(31);
1520 op <<= 25;
1521 Value |= op;
1522 // op: rs1
1523 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
1524 op &= UINT64_C(31);
1525 op <<= 14;
1526 Value |= op;
1527 // op: shcnt
1528 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
1529 op &= UINT64_C(63);
1530 Value |= op;
1531 break;
1532 }
1533 case SP::MOVRri: {
1534 // op: rd
1535 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1536 op &= UINT64_C(31);
1537 op <<= 25;
1538 Value |= op;
1539 // op: rs1
1540 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
1541 op &= UINT64_C(31);
1542 op <<= 14;
1543 Value |= op;
1544 // op: simm10
1545 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
1546 op &= UINT64_C(1023);
1547 Value |= op;
1548 // op: rcond
1549 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
1550 op &= UINT64_C(7);
1551 op <<= 10;
1552 Value |= op;
1553 break;
1554 }
1555 case SP::MULXri:
1556 case SP::SDIVXri:
1557 case SP::UDIVXri: {
1558 // op: rd
1559 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1560 op &= UINT64_C(31);
1561 op <<= 25;
1562 Value |= op;
1563 // op: rs1
1564 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
1565 op &= UINT64_C(31);
1566 op <<= 14;
1567 Value |= op;
1568 // op: simm13
1569 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
1570 op &= UINT64_C(8191);
1571 Value |= op;
1572 break;
1573 }
1574 case SP::ADDCCri:
1575 case SP::ADDCri:
1576 case SP::ADDEri:
1577 case SP::ADDri:
1578 case SP::ANDCCri:
1579 case SP::ANDNCCri:
1580 case SP::ANDNri:
1581 case SP::ANDri:
1582 case SP::JMPLri:
1583 case SP::LDAri:
1584 case SP::LDCri:
1585 case SP::LDDAri:
1586 case SP::LDDCri:
1587 case SP::LDDFAri:
1588 case SP::LDDFri:
1589 case SP::LDDri:
1590 case SP::LDFAri:
1591 case SP::LDFri:
1592 case SP::LDQFAri:
1593 case SP::LDQFri:
1594 case SP::LDSBAri:
1595 case SP::LDSBri:
1596 case SP::LDSHAri:
1597 case SP::LDSHri:
1598 case SP::LDSTUBAri:
1599 case SP::LDSTUBri:
1600 case SP::LDSWAri:
1601 case SP::LDSWri:
1602 case SP::LDUBAri:
1603 case SP::LDUBri:
1604 case SP::LDUHAri:
1605 case SP::LDUHri:
1606 case SP::LDXAri:
1607 case SP::LDXri:
1608 case SP::LDri:
1609 case SP::MULSCCri:
1610 case SP::ORCCri:
1611 case SP::ORNCCri:
1612 case SP::ORNri:
1613 case SP::ORri:
1614 case SP::RESTOREri:
1615 case SP::SAVEri:
1616 case SP::SDIVCCri:
1617 case SP::SDIVri:
1618 case SP::SMACri:
1619 case SP::SMULCCri:
1620 case SP::SMULri:
1621 case SP::SUBCCri:
1622 case SP::SUBCri:
1623 case SP::SUBEri:
1624 case SP::SUBri:
1625 case SP::SWAPAri:
1626 case SP::SWAPri:
1627 case SP::TADDCCTVri:
1628 case SP::TADDCCri:
1629 case SP::TSUBCCTVri:
1630 case SP::TSUBCCri:
1631 case SP::UDIVCCri:
1632 case SP::UDIVri:
1633 case SP::UMACri:
1634 case SP::UMULCCri:
1635 case SP::UMULri:
1636 case SP::WRASRri:
1637 case SP::WRPRri:
1638 case SP::XNORCCri:
1639 case SP::XNORri:
1640 case SP::XORCCri:
1641 case SP::XORri: {
1642 // op: rd
1643 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1644 op &= UINT64_C(31);
1645 op <<= 25;
1646 Value |= op;
1647 // op: rs1
1648 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
1649 op &= UINT64_C(31);
1650 op <<= 14;
1651 Value |= op;
1652 // op: simm13
1653 op = getSImm13OpValue(MI, OpNo: 2, Fixups, STI);
1654 op &= UINT64_C(8191);
1655 Value |= op;
1656 break;
1657 }
1658 case SP::FABSD:
1659 case SP::FABSQ:
1660 case SP::FABSS:
1661 case SP::FDTOI:
1662 case SP::FDTOQ:
1663 case SP::FDTOS:
1664 case SP::FDTOX:
1665 case SP::FEXPAND:
1666 case SP::FITOD:
1667 case SP::FITOQ:
1668 case SP::FITOS:
1669 case SP::FMOVD:
1670 case SP::FMOVQ:
1671 case SP::FMOVS:
1672 case SP::FNEGD:
1673 case SP::FNEGQ:
1674 case SP::FNEGS:
1675 case SP::FNOT2:
1676 case SP::FNOT2S:
1677 case SP::FPACK16:
1678 case SP::FPACKFIX:
1679 case SP::FQTOD:
1680 case SP::FQTOI:
1681 case SP::FQTOS:
1682 case SP::FQTOX:
1683 case SP::FSQRTD:
1684 case SP::FSQRTQ:
1685 case SP::FSQRTS:
1686 case SP::FSRC2:
1687 case SP::FSRC2S:
1688 case SP::FSTOD:
1689 case SP::FSTOI:
1690 case SP::FSTOQ:
1691 case SP::FSTOX:
1692 case SP::FXTOD:
1693 case SP::FXTOQ:
1694 case SP::FXTOS:
1695 case SP::LZCNT:
1696 case SP::MOVDTOX:
1697 case SP::MOVSTOSW:
1698 case SP::MOVSTOUW:
1699 case SP::MOVWTOS:
1700 case SP::MOVXTOD:
1701 case SP::POPCrr: {
1702 // op: rd
1703 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1704 op &= UINT64_C(31);
1705 op <<= 25;
1706 Value |= op;
1707 // op: rs2
1708 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
1709 op &= UINT64_C(31);
1710 Value |= op;
1711 break;
1712 }
1713 case SP::STArr:
1714 case SP::STBArr:
1715 case SP::STDArr:
1716 case SP::STDFArr:
1717 case SP::STFArr:
1718 case SP::STHArr:
1719 case SP::STQFArr:
1720 case SP::STXArr: {
1721 // op: rd
1722 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
1723 op &= UINT64_C(31);
1724 op <<= 25;
1725 Value |= op;
1726 // op: rs1
1727 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1728 op &= UINT64_C(31);
1729 op <<= 14;
1730 Value |= op;
1731 // op: asi
1732 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
1733 op &= UINT64_C(255);
1734 op <<= 5;
1735 Value |= op;
1736 // op: rs2
1737 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
1738 op &= UINT64_C(31);
1739 Value |= op;
1740 break;
1741 }
1742 case SP::PREFETCHr:
1743 case SP::STBrr:
1744 case SP::STCrr:
1745 case SP::STDCrr:
1746 case SP::STDFrr:
1747 case SP::STDrr:
1748 case SP::STFrr:
1749 case SP::STHrr:
1750 case SP::STQFrr:
1751 case SP::STXrr:
1752 case SP::STrr: {
1753 // op: rd
1754 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
1755 op &= UINT64_C(31);
1756 op <<= 25;
1757 Value |= op;
1758 // op: rs1
1759 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1760 op &= UINT64_C(31);
1761 op <<= 14;
1762 Value |= op;
1763 // op: rs2
1764 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
1765 op &= UINT64_C(31);
1766 Value |= op;
1767 break;
1768 }
1769 case SP::PREFETCHAi:
1770 case SP::PREFETCHi:
1771 case SP::STAri:
1772 case SP::STBAri:
1773 case SP::STBri:
1774 case SP::STCri:
1775 case SP::STDAri:
1776 case SP::STDCri:
1777 case SP::STDFAri:
1778 case SP::STDFri:
1779 case SP::STDri:
1780 case SP::STFAri:
1781 case SP::STFri:
1782 case SP::STHAri:
1783 case SP::STHri:
1784 case SP::STQFAri:
1785 case SP::STQFri:
1786 case SP::STXAri:
1787 case SP::STXri:
1788 case SP::STri: {
1789 // op: rd
1790 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
1791 op &= UINT64_C(31);
1792 op <<= 25;
1793 Value |= op;
1794 // op: rs1
1795 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1796 op &= UINT64_C(31);
1797 op <<= 14;
1798 Value |= op;
1799 // op: simm13
1800 op = getSImm13OpValue(MI, OpNo: 1, Fixups, STI);
1801 op &= UINT64_C(8191);
1802 Value |= op;
1803 break;
1804 }
1805 case SP::PREFETCHAr: {
1806 // op: rd
1807 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
1808 op &= UINT64_C(31);
1809 op <<= 25;
1810 Value |= op;
1811 // op: rs1
1812 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1813 op &= UINT64_C(31);
1814 op <<= 14;
1815 Value |= op;
1816 // op: asi
1817 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
1818 op &= UINT64_C(255);
1819 op <<= 5;
1820 Value |= op;
1821 // op: rs2
1822 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
1823 op &= UINT64_C(31);
1824 Value |= op;
1825 break;
1826 }
1827 case SP::TICCri:
1828 case SP::TRAPri:
1829 case SP::TXCCri: {
1830 // op: rs1
1831 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1832 op &= UINT64_C(31);
1833 op <<= 14;
1834 Value |= op;
1835 // op: cond
1836 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
1837 op &= UINT64_C(15);
1838 op <<= 25;
1839 Value |= op;
1840 // op: imm
1841 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
1842 op &= UINT64_C(255);
1843 Value |= op;
1844 break;
1845 }
1846 case SP::TICCrr:
1847 case SP::TRAPrr:
1848 case SP::TXCCrr: {
1849 // op: rs1
1850 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1851 op &= UINT64_C(31);
1852 op <<= 14;
1853 Value |= op;
1854 // op: cond
1855 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
1856 op &= UINT64_C(15);
1857 op <<= 25;
1858 Value |= op;
1859 // op: rs2
1860 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
1861 op &= UINT64_C(31);
1862 Value |= op;
1863 break;
1864 }
1865 case SP::BINDrr:
1866 case SP::CALLrr:
1867 case SP::CALLrri:
1868 case SP::FCMPD:
1869 case SP::FCMPD_V9:
1870 case SP::FCMPQ:
1871 case SP::FCMPQ_V9:
1872 case SP::FCMPS:
1873 case SP::FCMPS_V9:
1874 case SP::FLUSHrr:
1875 case SP::LDCSRrr:
1876 case SP::LDFSRrr:
1877 case SP::LDXFSRrr:
1878 case SP::PWRPSRrr:
1879 case SP::RETTrr:
1880 case SP::STCSRrr:
1881 case SP::STDCQrr:
1882 case SP::STDFQrr:
1883 case SP::STFSRrr:
1884 case SP::STXFSRrr:
1885 case SP::WRPSRrr:
1886 case SP::WRTBRrr:
1887 case SP::WRWIMrr: {
1888 // op: rs1
1889 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1890 op &= UINT64_C(31);
1891 op <<= 14;
1892 Value |= op;
1893 // op: rs2
1894 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
1895 op &= UINT64_C(31);
1896 Value |= op;
1897 break;
1898 }
1899 case SP::BINDri:
1900 case SP::CALLri:
1901 case SP::CALLrii:
1902 case SP::FLUSHri:
1903 case SP::LDCSRri:
1904 case SP::LDFSRri:
1905 case SP::LDXFSRri:
1906 case SP::PWRPSRri:
1907 case SP::RETTri:
1908 case SP::STCSRri:
1909 case SP::STDCQri:
1910 case SP::STDFQri:
1911 case SP::STFSRri:
1912 case SP::STXFSRri:
1913 case SP::TAIL_CALLri:
1914 case SP::WRPSRri:
1915 case SP::WRTBRri:
1916 case SP::WRWIMri: {
1917 // op: rs1
1918 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1919 op &= UINT64_C(31);
1920 op <<= 14;
1921 Value |= op;
1922 // op: simm13
1923 op = getSImm13OpValue(MI, OpNo: 1, Fixups, STI);
1924 op &= UINT64_C(8191);
1925 Value |= op;
1926 break;
1927 }
1928 case SP::CMASK8:
1929 case SP::CMASK16:
1930 case SP::CMASK32: {
1931 // op: rs2
1932 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1933 op &= UINT64_C(31);
1934 Value |= op;
1935 break;
1936 }
1937 case SP::MEMBARi:
1938 case SP::RET:
1939 case SP::RETL: {
1940 // op: simm13
1941 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
1942 op &= UINT64_C(8191);
1943 Value |= op;
1944 break;
1945 }
1946 case SP::SIR: {
1947 // op: simm13
1948 op = getSImm13OpValue(MI, OpNo: 0, Fixups, STI);
1949 op &= UINT64_C(8191);
1950 Value |= op;
1951 break;
1952 }
1953 default:
1954 std::string msg;
1955 raw_string_ostream Msg(msg);
1956 Msg << "Not supported instr: " << MI;
1957 report_fatal_error(reason: Msg.str().c_str());
1958 }
1959 return Value;
1960}
1961
1962#ifdef GET_OPERAND_BIT_OFFSET
1963#undef GET_OPERAND_BIT_OFFSET
1964
1965uint32_t SparcMCCodeEmitter::getOperandBitOffset(const MCInst &MI,
1966 unsigned OpNum,
1967 const MCSubtargetInfo &STI) const {
1968 switch (MI.getOpcode()) {
1969 case SP::ALLCLEAN:
1970 case SP::DONE:
1971 case SP::FLUSH:
1972 case SP::FLUSHW:
1973 case SP::INVALW:
1974 case SP::NOP:
1975 case SP::NORMALW:
1976 case SP::OTHERW:
1977 case SP::RESTORED:
1978 case SP::RETRY:
1979 case SP::SAVED:
1980 case SP::SHUTDOWN:
1981 case SP::STBAR:
1982 case SP::TA1:
1983 case SP::TA3:
1984 case SP::TA5: {
1985 break;
1986 }
1987 case SP::CALL:
1988 case SP::CALLi:
1989 case SP::TAIL_CALL:
1990 case SP::TLS_CALL: {
1991 switch (OpNum) {
1992 case 0:
1993 // op: disp
1994 return 0;
1995 }
1996 break;
1997 }
1998 case SP::CWBCONDrr:
1999 case SP::CXBCONDrr: {
2000 switch (OpNum) {
2001 case 0:
2002 // op: imm10
2003 return 5;
2004 case 2:
2005 // op: rs1
2006 return 14;
2007 case 3:
2008 // op: rs2
2009 return 0;
2010 case 1:
2011 // op: cond
2012 return 25;
2013 }
2014 break;
2015 }
2016 case SP::CWBCONDri:
2017 case SP::CXBCONDri: {
2018 switch (OpNum) {
2019 case 0:
2020 // op: imm10
2021 return 5;
2022 case 2:
2023 // op: rs1
2024 return 14;
2025 case 3:
2026 // op: simm5
2027 return 0;
2028 case 1:
2029 // op: cond
2030 return 25;
2031 }
2032 break;
2033 }
2034 case SP::BPR:
2035 case SP::BPRA:
2036 case SP::BPRANT:
2037 case SP::BPRNT: {
2038 switch (OpNum) {
2039 case 0:
2040 // op: imm16
2041 return 0;
2042 case 2:
2043 // op: rs1
2044 return 14;
2045 case 1:
2046 // op: rcond
2047 return 25;
2048 }
2049 break;
2050 }
2051 case SP::BCOND:
2052 case SP::BCONDA:
2053 case SP::CPBCOND:
2054 case SP::CPBCONDA:
2055 case SP::FBCOND:
2056 case SP::FBCONDA: {
2057 switch (OpNum) {
2058 case 0:
2059 // op: imm22
2060 return 0;
2061 case 1:
2062 // op: cond
2063 return 25;
2064 }
2065 break;
2066 }
2067 case SP::BA:
2068 case SP::UNIMP: {
2069 switch (OpNum) {
2070 case 0:
2071 // op: imm22
2072 return 0;
2073 }
2074 break;
2075 }
2076 case SP::SIAM: {
2077 switch (OpNum) {
2078 case 0:
2079 // op: mode
2080 return 0;
2081 }
2082 break;
2083 }
2084 case SP::V9MOVFCCrr: {
2085 switch (OpNum) {
2086 case 0:
2087 // op: rd
2088 return 25;
2089 case 1:
2090 // op: cc
2091 return 11;
2092 case 4:
2093 // op: cond
2094 return 14;
2095 case 2:
2096 // op: rs2
2097 return 0;
2098 }
2099 break;
2100 }
2101 case SP::V9MOVFCCri: {
2102 switch (OpNum) {
2103 case 0:
2104 // op: rd
2105 return 25;
2106 case 1:
2107 // op: cc
2108 return 11;
2109 case 4:
2110 // op: cond
2111 return 14;
2112 case 2:
2113 // op: simm11
2114 return 0;
2115 }
2116 break;
2117 }
2118 case SP::FMOVRD:
2119 case SP::FMOVRQ:
2120 case SP::FMOVRS:
2121 case SP::MOVRrr: {
2122 switch (OpNum) {
2123 case 0:
2124 // op: rd
2125 return 25;
2126 case 1:
2127 // op: rs1
2128 return 14;
2129 case 2:
2130 // op: rs2
2131 return 0;
2132 case 4:
2133 // op: rcond
2134 return 10;
2135 }
2136 break;
2137 }
2138 case SP::ADDCCrr:
2139 case SP::ADDCrr:
2140 case SP::ADDErr:
2141 case SP::ADDXC:
2142 case SP::ADDXCCC:
2143 case SP::ADDrr:
2144 case SP::ALIGNADDR:
2145 case SP::ALIGNADDRL:
2146 case SP::ANDCCrr:
2147 case SP::ANDNCCrr:
2148 case SP::ANDNrr:
2149 case SP::ANDrr:
2150 case SP::ARRAY8:
2151 case SP::ARRAY16:
2152 case SP::ARRAY32:
2153 case SP::BMASK:
2154 case SP::BSHUFFLE:
2155 case SP::CASAri:
2156 case SP::CASXAri:
2157 case SP::EDGE8:
2158 case SP::EDGE8L:
2159 case SP::EDGE8LN:
2160 case SP::EDGE8N:
2161 case SP::EDGE16:
2162 case SP::EDGE16L:
2163 case SP::EDGE16LN:
2164 case SP::EDGE16N:
2165 case SP::EDGE32:
2166 case SP::EDGE32L:
2167 case SP::EDGE32LN:
2168 case SP::EDGE32N:
2169 case SP::FADDD:
2170 case SP::FADDQ:
2171 case SP::FADDS:
2172 case SP::FALIGNADATA:
2173 case SP::FAND:
2174 case SP::FANDNOT1:
2175 case SP::FANDNOT1S:
2176 case SP::FANDNOT2:
2177 case SP::FANDNOT2S:
2178 case SP::FANDS:
2179 case SP::FCHKSM16:
2180 case SP::FCMPEQ16:
2181 case SP::FCMPEQ32:
2182 case SP::FCMPGT16:
2183 case SP::FCMPGT32:
2184 case SP::FCMPLE16:
2185 case SP::FCMPLE32:
2186 case SP::FCMPNE16:
2187 case SP::FCMPNE32:
2188 case SP::FDIVD:
2189 case SP::FDIVQ:
2190 case SP::FDIVS:
2191 case SP::FDMULQ:
2192 case SP::FHADDD:
2193 case SP::FHADDS:
2194 case SP::FHSUBD:
2195 case SP::FHSUBS:
2196 case SP::FLCMPD:
2197 case SP::FLCMPS:
2198 case SP::FMEAN16:
2199 case SP::FMUL8SUX16:
2200 case SP::FMUL8ULX16:
2201 case SP::FMUL8X16:
2202 case SP::FMUL8X16AL:
2203 case SP::FMUL8X16AU:
2204 case SP::FMULD:
2205 case SP::FMULD8SUX16:
2206 case SP::FMULD8ULX16:
2207 case SP::FMULQ:
2208 case SP::FMULS:
2209 case SP::FNADDD:
2210 case SP::FNADDS:
2211 case SP::FNAND:
2212 case SP::FNANDS:
2213 case SP::FNHADDD:
2214 case SP::FNHADDS:
2215 case SP::FNMULD:
2216 case SP::FNMULS:
2217 case SP::FNOR:
2218 case SP::FNORS:
2219 case SP::FNSMULD:
2220 case SP::FOR:
2221 case SP::FORNOT1:
2222 case SP::FORNOT1S:
2223 case SP::FORNOT2:
2224 case SP::FORNOT2S:
2225 case SP::FORS:
2226 case SP::FPACK32:
2227 case SP::FPADD16:
2228 case SP::FPADD16S:
2229 case SP::FPADD32:
2230 case SP::FPADD32S:
2231 case SP::FPADD64:
2232 case SP::FPMERGE:
2233 case SP::FPSUB16:
2234 case SP::FPSUB16S:
2235 case SP::FPSUB32:
2236 case SP::FPSUB32S:
2237 case SP::FSLAS16:
2238 case SP::FSLAS32:
2239 case SP::FSLL16:
2240 case SP::FSLL32:
2241 case SP::FSMULD:
2242 case SP::FSRA16:
2243 case SP::FSRA32:
2244 case SP::FSRL16:
2245 case SP::FSRL32:
2246 case SP::FSUBD:
2247 case SP::FSUBQ:
2248 case SP::FSUBS:
2249 case SP::FXNOR:
2250 case SP::FXNORS:
2251 case SP::FXOR:
2252 case SP::FXORS:
2253 case SP::GDOP_LDXrr:
2254 case SP::GDOP_LDrr:
2255 case SP::JMPLrr:
2256 case SP::LDCrr:
2257 case SP::LDDCrr:
2258 case SP::LDDFrr:
2259 case SP::LDDrr:
2260 case SP::LDFrr:
2261 case SP::LDQFrr:
2262 case SP::LDSBrr:
2263 case SP::LDSHrr:
2264 case SP::LDSTUBrr:
2265 case SP::LDSWrr:
2266 case SP::LDUBrr:
2267 case SP::LDUHrr:
2268 case SP::LDXrr:
2269 case SP::LDrr:
2270 case SP::MULSCCrr:
2271 case SP::MULXrr:
2272 case SP::ORCCrr:
2273 case SP::ORNCCrr:
2274 case SP::ORNrr:
2275 case SP::ORrr:
2276 case SP::PDIST:
2277 case SP::PDISTN:
2278 case SP::RESTORErr:
2279 case SP::SAVErr:
2280 case SP::SDIVCCrr:
2281 case SP::SDIVXrr:
2282 case SP::SDIVrr:
2283 case SP::SLLXrr:
2284 case SP::SLLrr:
2285 case SP::SMACrr:
2286 case SP::SMULCCrr:
2287 case SP::SMULrr:
2288 case SP::SRAXrr:
2289 case SP::SRArr:
2290 case SP::SRLXrr:
2291 case SP::SRLrr:
2292 case SP::SUBCCrr:
2293 case SP::SUBCrr:
2294 case SP::SUBErr:
2295 case SP::SUBrr:
2296 case SP::SWAPrr:
2297 case SP::TADDCCTVrr:
2298 case SP::TADDCCrr:
2299 case SP::TLS_ADDrr:
2300 case SP::TLS_LDXrr:
2301 case SP::TLS_LDrr:
2302 case SP::TSUBCCTVrr:
2303 case SP::TSUBCCrr:
2304 case SP::UDIVCCrr:
2305 case SP::UDIVXrr:
2306 case SP::UDIVrr:
2307 case SP::UMACrr:
2308 case SP::UMULCCrr:
2309 case SP::UMULXHI:
2310 case SP::UMULrr:
2311 case SP::V9FCMPD:
2312 case SP::V9FCMPED:
2313 case SP::V9FCMPEQ:
2314 case SP::V9FCMPES:
2315 case SP::V9FCMPQ:
2316 case SP::V9FCMPS:
2317 case SP::WRASRrr:
2318 case SP::WRPRrr:
2319 case SP::XMULX:
2320 case SP::XMULXHI:
2321 case SP::XNORCCrr:
2322 case SP::XNORrr:
2323 case SP::XORCCrr:
2324 case SP::XORrr: {
2325 switch (OpNum) {
2326 case 0:
2327 // op: rd
2328 return 25;
2329 case 1:
2330 // op: rs1
2331 return 14;
2332 case 2:
2333 // op: rs2
2334 return 0;
2335 }
2336 break;
2337 }
2338 case SP::SLLXri:
2339 case SP::SLLri:
2340 case SP::SRAXri:
2341 case SP::SRAri:
2342 case SP::SRLXri:
2343 case SP::SRLri: {
2344 switch (OpNum) {
2345 case 0:
2346 // op: rd
2347 return 25;
2348 case 1:
2349 // op: rs1
2350 return 14;
2351 case 2:
2352 // op: shcnt
2353 return 0;
2354 }
2355 break;
2356 }
2357 case SP::MOVRri: {
2358 switch (OpNum) {
2359 case 0:
2360 // op: rd
2361 return 25;
2362 case 1:
2363 // op: rs1
2364 return 14;
2365 case 2:
2366 // op: simm10
2367 return 0;
2368 case 4:
2369 // op: rcond
2370 return 10;
2371 }
2372 break;
2373 }
2374 case SP::ADDCCri:
2375 case SP::ADDCri:
2376 case SP::ADDEri:
2377 case SP::ADDri:
2378 case SP::ANDCCri:
2379 case SP::ANDNCCri:
2380 case SP::ANDNri:
2381 case SP::ANDri:
2382 case SP::JMPLri:
2383 case SP::LDAri:
2384 case SP::LDCri:
2385 case SP::LDDAri:
2386 case SP::LDDCri:
2387 case SP::LDDFAri:
2388 case SP::LDDFri:
2389 case SP::LDDri:
2390 case SP::LDFAri:
2391 case SP::LDFri:
2392 case SP::LDQFAri:
2393 case SP::LDQFri:
2394 case SP::LDSBAri:
2395 case SP::LDSBri:
2396 case SP::LDSHAri:
2397 case SP::LDSHri:
2398 case SP::LDSTUBAri:
2399 case SP::LDSTUBri:
2400 case SP::LDSWAri:
2401 case SP::LDSWri:
2402 case SP::LDUBAri:
2403 case SP::LDUBri:
2404 case SP::LDUHAri:
2405 case SP::LDUHri:
2406 case SP::LDXAri:
2407 case SP::LDXri:
2408 case SP::LDri:
2409 case SP::MULSCCri:
2410 case SP::MULXri:
2411 case SP::ORCCri:
2412 case SP::ORNCCri:
2413 case SP::ORNri:
2414 case SP::ORri:
2415 case SP::RESTOREri:
2416 case SP::SAVEri:
2417 case SP::SDIVCCri:
2418 case SP::SDIVXri:
2419 case SP::SDIVri:
2420 case SP::SMACri:
2421 case SP::SMULCCri:
2422 case SP::SMULri:
2423 case SP::SUBCCri:
2424 case SP::SUBCri:
2425 case SP::SUBEri:
2426 case SP::SUBri:
2427 case SP::SWAPAri:
2428 case SP::SWAPri:
2429 case SP::TADDCCTVri:
2430 case SP::TADDCCri:
2431 case SP::TSUBCCTVri:
2432 case SP::TSUBCCri:
2433 case SP::UDIVCCri:
2434 case SP::UDIVXri:
2435 case SP::UDIVri:
2436 case SP::UMACri:
2437 case SP::UMULCCri:
2438 case SP::UMULri:
2439 case SP::WRASRri:
2440 case SP::WRPRri:
2441 case SP::XNORCCri:
2442 case SP::XNORri:
2443 case SP::XORCCri:
2444 case SP::XORri: {
2445 switch (OpNum) {
2446 case 0:
2447 // op: rd
2448 return 25;
2449 case 1:
2450 // op: rs1
2451 return 14;
2452 case 2:
2453 // op: simm13
2454 return 0;
2455 }
2456 break;
2457 }
2458 case SP::LDArr:
2459 case SP::LDDArr:
2460 case SP::LDDFArr:
2461 case SP::LDFArr:
2462 case SP::LDQFArr:
2463 case SP::LDSBArr:
2464 case SP::LDSHArr:
2465 case SP::LDSTUBArr:
2466 case SP::LDSWArr:
2467 case SP::LDUBArr:
2468 case SP::LDUHArr:
2469 case SP::LDXArr:
2470 case SP::SWAPArr: {
2471 switch (OpNum) {
2472 case 0:
2473 // op: rd
2474 return 25;
2475 case 1:
2476 // op: rs1
2477 return 14;
2478 case 3:
2479 // op: asi
2480 return 5;
2481 case 2:
2482 // op: rs2
2483 return 0;
2484 }
2485 break;
2486 }
2487 case SP::FMADDD:
2488 case SP::FMADDS:
2489 case SP::FMSUBD:
2490 case SP::FMSUBS:
2491 case SP::FNMADDD:
2492 case SP::FNMADDS:
2493 case SP::FNMSUBD:
2494 case SP::FNMSUBS:
2495 case SP::FPMADDX:
2496 case SP::FPMADDXHI: {
2497 switch (OpNum) {
2498 case 0:
2499 // op: rd
2500 return 25;
2501 case 1:
2502 // op: rs1
2503 return 14;
2504 case 3:
2505 // op: rs3
2506 return 9;
2507 case 2:
2508 // op: rs2
2509 return 0;
2510 }
2511 break;
2512 }
2513 case SP::CASArr:
2514 case SP::CASXArr: {
2515 switch (OpNum) {
2516 case 0:
2517 // op: rd
2518 return 25;
2519 case 1:
2520 // op: rs1
2521 return 14;
2522 case 4:
2523 // op: asi
2524 return 5;
2525 case 2:
2526 // op: rs2
2527 return 0;
2528 }
2529 break;
2530 }
2531 case SP::FNOT1:
2532 case SP::FNOT1S:
2533 case SP::FSRC1:
2534 case SP::FSRC1S:
2535 case SP::RDASR:
2536 case SP::RDPR: {
2537 switch (OpNum) {
2538 case 0:
2539 // op: rd
2540 return 25;
2541 case 1:
2542 // op: rs1
2543 return 14;
2544 }
2545 break;
2546 }
2547 case SP::FABSD:
2548 case SP::FABSQ:
2549 case SP::FABSS:
2550 case SP::FDTOI:
2551 case SP::FDTOQ:
2552 case SP::FDTOS:
2553 case SP::FDTOX:
2554 case SP::FEXPAND:
2555 case SP::FITOD:
2556 case SP::FITOQ:
2557 case SP::FITOS:
2558 case SP::FMOVD:
2559 case SP::FMOVQ:
2560 case SP::FMOVS:
2561 case SP::FNEGD:
2562 case SP::FNEGQ:
2563 case SP::FNEGS:
2564 case SP::FNOT2:
2565 case SP::FNOT2S:
2566 case SP::FPACK16:
2567 case SP::FPACKFIX:
2568 case SP::FQTOD:
2569 case SP::FQTOI:
2570 case SP::FQTOS:
2571 case SP::FQTOX:
2572 case SP::FSQRTD:
2573 case SP::FSQRTQ:
2574 case SP::FSQRTS:
2575 case SP::FSRC2:
2576 case SP::FSRC2S:
2577 case SP::FSTOD:
2578 case SP::FSTOI:
2579 case SP::FSTOQ:
2580 case SP::FSTOX:
2581 case SP::FXTOD:
2582 case SP::FXTOQ:
2583 case SP::FXTOS:
2584 case SP::LZCNT:
2585 case SP::MOVDTOX:
2586 case SP::MOVSTOSW:
2587 case SP::MOVSTOUW:
2588 case SP::MOVWTOS:
2589 case SP::MOVXTOD:
2590 case SP::POPCrr: {
2591 switch (OpNum) {
2592 case 0:
2593 // op: rd
2594 return 25;
2595 case 1:
2596 // op: rs2
2597 return 0;
2598 }
2599 break;
2600 }
2601 case SP::FMOVD_FCC:
2602 case SP::FMOVD_ICC:
2603 case SP::FMOVD_XCC:
2604 case SP::FMOVQ_FCC:
2605 case SP::FMOVQ_ICC:
2606 case SP::FMOVQ_XCC:
2607 case SP::FMOVS_FCC:
2608 case SP::FMOVS_ICC:
2609 case SP::FMOVS_XCC:
2610 case SP::MOVFCCrr:
2611 case SP::MOVICCrr:
2612 case SP::MOVXCCrr: {
2613 switch (OpNum) {
2614 case 0:
2615 // op: rd
2616 return 25;
2617 case 3:
2618 // op: cond
2619 return 14;
2620 case 1:
2621 // op: rs2
2622 return 0;
2623 }
2624 break;
2625 }
2626 case SP::MOVFCCri:
2627 case SP::MOVICCri:
2628 case SP::MOVXCCri: {
2629 switch (OpNum) {
2630 case 0:
2631 // op: rd
2632 return 25;
2633 case 3:
2634 // op: cond
2635 return 14;
2636 case 1:
2637 // op: simm11
2638 return 0;
2639 }
2640 break;
2641 }
2642 case SP::V9FMOVD_FCC:
2643 case SP::V9FMOVQ_FCC:
2644 case SP::V9FMOVS_FCC: {
2645 switch (OpNum) {
2646 case 0:
2647 // op: rd
2648 return 25;
2649 case 4:
2650 // op: cond
2651 return 14;
2652 case 1:
2653 // op: opf_cc
2654 return 11;
2655 case 2:
2656 // op: rs2
2657 return 0;
2658 }
2659 break;
2660 }
2661 case SP::FONE:
2662 case SP::FONES:
2663 case SP::FZERO:
2664 case SP::FZEROS:
2665 case SP::RDFQ:
2666 case SP::RDPSR:
2667 case SP::RDTBR:
2668 case SP::RDWIM: {
2669 switch (OpNum) {
2670 case 0:
2671 // op: rd
2672 return 25;
2673 }
2674 break;
2675 }
2676 case SP::BINDrr:
2677 case SP::CALLrr:
2678 case SP::CALLrri:
2679 case SP::FCMPD:
2680 case SP::FCMPD_V9:
2681 case SP::FCMPQ:
2682 case SP::FCMPQ_V9:
2683 case SP::FCMPS:
2684 case SP::FCMPS_V9:
2685 case SP::FLUSHrr:
2686 case SP::LDCSRrr:
2687 case SP::LDFSRrr:
2688 case SP::LDXFSRrr:
2689 case SP::PWRPSRrr:
2690 case SP::RETTrr:
2691 case SP::STCSRrr:
2692 case SP::STDCQrr:
2693 case SP::STDFQrr:
2694 case SP::STFSRrr:
2695 case SP::STXFSRrr:
2696 case SP::WRPSRrr:
2697 case SP::WRTBRrr:
2698 case SP::WRWIMrr: {
2699 switch (OpNum) {
2700 case 0:
2701 // op: rs1
2702 return 14;
2703 case 1:
2704 // op: rs2
2705 return 0;
2706 }
2707 break;
2708 }
2709 case SP::BINDri:
2710 case SP::CALLri:
2711 case SP::CALLrii:
2712 case SP::FLUSHri:
2713 case SP::LDCSRri:
2714 case SP::LDFSRri:
2715 case SP::LDXFSRri:
2716 case SP::PWRPSRri:
2717 case SP::RETTri:
2718 case SP::STCSRri:
2719 case SP::STDCQri:
2720 case SP::STDFQri:
2721 case SP::STFSRri:
2722 case SP::STXFSRri:
2723 case SP::TAIL_CALLri:
2724 case SP::WRPSRri:
2725 case SP::WRTBRri:
2726 case SP::WRWIMri: {
2727 switch (OpNum) {
2728 case 0:
2729 // op: rs1
2730 return 14;
2731 case 1:
2732 // op: simm13
2733 return 0;
2734 }
2735 break;
2736 }
2737 case SP::TICCri:
2738 case SP::TRAPri:
2739 case SP::TXCCri: {
2740 switch (OpNum) {
2741 case 0:
2742 // op: rs1
2743 return 14;
2744 case 2:
2745 // op: cond
2746 return 25;
2747 case 1:
2748 // op: imm
2749 return 0;
2750 }
2751 break;
2752 }
2753 case SP::TICCrr:
2754 case SP::TRAPrr:
2755 case SP::TXCCrr: {
2756 switch (OpNum) {
2757 case 0:
2758 // op: rs1
2759 return 14;
2760 case 2:
2761 // op: cond
2762 return 25;
2763 case 1:
2764 // op: rs2
2765 return 0;
2766 }
2767 break;
2768 }
2769 case SP::CMASK8:
2770 case SP::CMASK16:
2771 case SP::CMASK32: {
2772 switch (OpNum) {
2773 case 0:
2774 // op: rs2
2775 return 0;
2776 }
2777 break;
2778 }
2779 case SP::MEMBARi:
2780 case SP::RET:
2781 case SP::RETL:
2782 case SP::SIR: {
2783 switch (OpNum) {
2784 case 0:
2785 // op: simm13
2786 return 0;
2787 }
2788 break;
2789 }
2790 case SP::BPICC:
2791 case SP::BPICCA:
2792 case SP::BPICCANT:
2793 case SP::BPICCNT:
2794 case SP::BPXCC:
2795 case SP::BPXCCA:
2796 case SP::BPXCCANT:
2797 case SP::BPXCCNT:
2798 case SP::FBCONDA_V9:
2799 case SP::FBCOND_V9: {
2800 switch (OpNum) {
2801 case 1:
2802 // op: cond
2803 return 25;
2804 case 0:
2805 // op: imm19
2806 return 0;
2807 }
2808 break;
2809 }
2810 case SP::SETHIi: {
2811 switch (OpNum) {
2812 case 1:
2813 // op: imm22
2814 return 0;
2815 case 0:
2816 // op: rd
2817 return 25;
2818 }
2819 break;
2820 }
2821 case SP::BPFCC:
2822 case SP::BPFCCA:
2823 case SP::BPFCCANT:
2824 case SP::BPFCCNT: {
2825 switch (OpNum) {
2826 case 2:
2827 // op: cc
2828 return 20;
2829 case 1:
2830 // op: cond
2831 return 25;
2832 case 0:
2833 // op: imm19
2834 return 0;
2835 }
2836 break;
2837 }
2838 case SP::PREFETCHr:
2839 case SP::STBrr:
2840 case SP::STCrr:
2841 case SP::STDCrr:
2842 case SP::STDFrr:
2843 case SP::STDrr:
2844 case SP::STFrr:
2845 case SP::STHrr:
2846 case SP::STQFrr:
2847 case SP::STXrr:
2848 case SP::STrr: {
2849 switch (OpNum) {
2850 case 2:
2851 // op: rd
2852 return 25;
2853 case 0:
2854 // op: rs1
2855 return 14;
2856 case 1:
2857 // op: rs2
2858 return 0;
2859 }
2860 break;
2861 }
2862 case SP::PREFETCHAi:
2863 case SP::PREFETCHi:
2864 case SP::STAri:
2865 case SP::STBAri:
2866 case SP::STBri:
2867 case SP::STCri:
2868 case SP::STDAri:
2869 case SP::STDCri:
2870 case SP::STDFAri:
2871 case SP::STDFri:
2872 case SP::STDri:
2873 case SP::STFAri:
2874 case SP::STFri:
2875 case SP::STHAri:
2876 case SP::STHri:
2877 case SP::STQFAri:
2878 case SP::STQFri:
2879 case SP::STXAri:
2880 case SP::STXri:
2881 case SP::STri: {
2882 switch (OpNum) {
2883 case 2:
2884 // op: rd
2885 return 25;
2886 case 0:
2887 // op: rs1
2888 return 14;
2889 case 1:
2890 // op: simm13
2891 return 0;
2892 }
2893 break;
2894 }
2895 case SP::STArr:
2896 case SP::STBArr:
2897 case SP::STDArr:
2898 case SP::STDFArr:
2899 case SP::STFArr:
2900 case SP::STHArr:
2901 case SP::STQFArr:
2902 case SP::STXArr: {
2903 switch (OpNum) {
2904 case 2:
2905 // op: rd
2906 return 25;
2907 case 0:
2908 // op: rs1
2909 return 14;
2910 case 3:
2911 // op: asi
2912 return 5;
2913 case 1:
2914 // op: rs2
2915 return 0;
2916 }
2917 break;
2918 }
2919 case SP::PREFETCHAr: {
2920 switch (OpNum) {
2921 case 3:
2922 // op: rd
2923 return 25;
2924 case 0:
2925 // op: rs1
2926 return 14;
2927 case 2:
2928 // op: asi
2929 return 5;
2930 case 1:
2931 // op: rs2
2932 return 0;
2933 }
2934 break;
2935 }
2936 }
2937 std::string msg;
2938 raw_string_ostream Msg(msg);
2939 Msg << "Not supported instr[opcode]: " << MI << "[" << OpNum << "]";
2940 report_fatal_error(Msg.str().c_str());
2941}
2942
2943#endif // GET_OPERAND_BIT_OFFSET
2944
2945