1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register Enum Values *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_REGINFO_ENUM
11#undef GET_REGINFO_ENUM
12
13namespace llvm {
14
15class MCRegisterClass;
16extern const MCRegisterClass SystemZMCRegisterClasses[];
17
18namespace SystemZ {
19enum : unsigned {
20 NoRegister,
21 CC = 1,
22 FPC = 2,
23 A0 = 3,
24 A1 = 4,
25 A2 = 5,
26 A3 = 6,
27 A4 = 7,
28 A5 = 8,
29 A6 = 9,
30 A7 = 10,
31 A8 = 11,
32 A9 = 12,
33 A10 = 13,
34 A11 = 14,
35 A12 = 15,
36 A13 = 16,
37 A14 = 17,
38 A15 = 18,
39 C0 = 19,
40 C1 = 20,
41 C2 = 21,
42 C3 = 22,
43 C4 = 23,
44 C5 = 24,
45 C6 = 25,
46 C7 = 26,
47 C8 = 27,
48 C9 = 28,
49 C10 = 29,
50 C11 = 30,
51 C12 = 31,
52 C13 = 32,
53 C14 = 33,
54 C15 = 34,
55 V0 = 35,
56 V1 = 36,
57 V2 = 37,
58 V3 = 38,
59 V4 = 39,
60 V5 = 40,
61 V6 = 41,
62 V7 = 42,
63 V8 = 43,
64 V9 = 44,
65 V10 = 45,
66 V11 = 46,
67 V12 = 47,
68 V13 = 48,
69 V14 = 49,
70 V15 = 50,
71 V16 = 51,
72 V17 = 52,
73 V18 = 53,
74 V19 = 54,
75 V20 = 55,
76 V21 = 56,
77 V22 = 57,
78 V23 = 58,
79 V24 = 59,
80 V25 = 60,
81 V26 = 61,
82 V27 = 62,
83 V28 = 63,
84 V29 = 64,
85 V30 = 65,
86 V31 = 66,
87 F0D = 67,
88 F1D = 68,
89 F2D = 69,
90 F3D = 70,
91 F4D = 71,
92 F5D = 72,
93 F6D = 73,
94 F7D = 74,
95 F8D = 75,
96 F9D = 76,
97 F10D = 77,
98 F11D = 78,
99 F12D = 79,
100 F13D = 80,
101 F14D = 81,
102 F15D = 82,
103 F16D = 83,
104 F17D = 84,
105 F18D = 85,
106 F19D = 86,
107 F20D = 87,
108 F21D = 88,
109 F22D = 89,
110 F23D = 90,
111 F24D = 91,
112 F25D = 92,
113 F26D = 93,
114 F27D = 94,
115 F28D = 95,
116 F29D = 96,
117 F30D = 97,
118 F31D = 98,
119 F0H = 99,
120 F1H = 100,
121 F2H = 101,
122 F3H = 102,
123 F4H = 103,
124 F5H = 104,
125 F6H = 105,
126 F7H = 106,
127 F8H = 107,
128 F9H = 108,
129 F10H = 109,
130 F11H = 110,
131 F12H = 111,
132 F13H = 112,
133 F14H = 113,
134 F15H = 114,
135 F16H = 115,
136 F17H = 116,
137 F18H = 117,
138 F19H = 118,
139 F20H = 119,
140 F21H = 120,
141 F22H = 121,
142 F23H = 122,
143 F24H = 123,
144 F25H = 124,
145 F26H = 125,
146 F27H = 126,
147 F28H = 127,
148 F29H = 128,
149 F30H = 129,
150 F31H = 130,
151 F0Q = 131,
152 F1Q = 132,
153 F4Q = 133,
154 F5Q = 134,
155 F8Q = 135,
156 F9Q = 136,
157 F12Q = 137,
158 F13Q = 138,
159 F0S = 139,
160 F1S = 140,
161 F2S = 141,
162 F3S = 142,
163 F4S = 143,
164 F5S = 144,
165 F6S = 145,
166 F7S = 146,
167 F8S = 147,
168 F9S = 148,
169 F10S = 149,
170 F11S = 150,
171 F12S = 151,
172 F13S = 152,
173 F14S = 153,
174 F15S = 154,
175 F16S = 155,
176 F17S = 156,
177 F18S = 157,
178 F19S = 158,
179 F20S = 159,
180 F21S = 160,
181 F22S = 161,
182 F23S = 162,
183 F24S = 163,
184 F25S = 164,
185 F26S = 165,
186 F27S = 166,
187 F28S = 167,
188 F29S = 168,
189 F30S = 169,
190 F31S = 170,
191 R0D = 171,
192 R1D = 172,
193 R2D = 173,
194 R3D = 174,
195 R4D = 175,
196 R5D = 176,
197 R6D = 177,
198 R7D = 178,
199 R8D = 179,
200 R9D = 180,
201 R10D = 181,
202 R11D = 182,
203 R12D = 183,
204 R13D = 184,
205 R14D = 185,
206 R15D = 186,
207 R0H = 187,
208 R1H = 188,
209 R2H = 189,
210 R3H = 190,
211 R4H = 191,
212 R5H = 192,
213 R6H = 193,
214 R7H = 194,
215 R8H = 195,
216 R9H = 196,
217 R10H = 197,
218 R11H = 198,
219 R12H = 199,
220 R13H = 200,
221 R14H = 201,
222 R15H = 202,
223 R0L = 203,
224 R1L = 204,
225 R2L = 205,
226 R3L = 206,
227 R4L = 207,
228 R5L = 208,
229 R6L = 209,
230 R7L = 210,
231 R8L = 211,
232 R9L = 212,
233 R10L = 213,
234 R11L = 214,
235 R12L = 215,
236 R13L = 216,
237 R14L = 217,
238 R15L = 218,
239 R0Q = 219,
240 R2Q = 220,
241 R4Q = 221,
242 R6Q = 222,
243 R8Q = 223,
244 R10Q = 224,
245 R12Q = 225,
246 R14Q = 226,
247 NUM_TARGET_REGS // 227
248};
249} // end namespace SystemZ
250
251// Register classes
252
253namespace SystemZ {
254enum {
255 VR16BitRegClassID = 0,
256 FP16BitRegClassID = 1,
257 GRX32BitRegClassID = 2,
258 VR32BitRegClassID = 3,
259 AR32BitRegClassID = 4,
260 FP32BitRegClassID = 5,
261 GR32BitRegClassID = 6,
262 GRH32BitRegClassID = 7,
263 ADDR32BitRegClassID = 8,
264 CCRRegClassID = 9,
265 FPCRegsRegClassID = 10,
266 AnyRegBitRegClassID = 11,
267 AnyRegBit_with_subreg_h16RegClassID = 12,
268 VR64BitRegClassID = 13,
269 AnyRegBit_with_subreg_h64RegClassID = 14,
270 CR64BitRegClassID = 15,
271 FP64BitRegClassID = 16,
272 GR64BitRegClassID = 17,
273 ADDR64BitRegClassID = 18,
274 VR128BitRegClassID = 19,
275 VF128BitRegClassID = 20,
276 FP128BitRegClassID = 21,
277 GR128BitRegClassID = 22,
278 ADDR128BitRegClassID = 23,
279
280};
281} // end namespace SystemZ
282
283
284// Subregister indices
285
286namespace SystemZ {
287enum : uint16_t {
288 NoSubRegister,
289 subreg_h16, // 1
290 subreg_h32, // 2
291 subreg_h64, // 3
292 subreg_l32, // 4
293 subreg_l64, // 5
294 subreg_lh32, // 6
295 subreg_ll32, // 7
296 subreg_lh32_then_subreg_h16, // 8
297 NUM_TARGET_SUBREGS
298};
299} // end namespace SystemZ
300
301// Register pressure sets enum.
302namespace SystemZ {
303enum RegisterPressureSets {
304 FP16Bit = 0,
305 GR32Bit = 1,
306 GRH32Bit = 2,
307 VR16Bit = 3,
308 GRX32Bit = 4,
309};
310} // end namespace SystemZ
311
312} // end namespace llvm
313
314#endif // GET_REGINFO_ENUM
315
316/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
317|* *|
318|* MC Register Information *|
319|* *|
320|* Automatically generated file, do not edit! *|
321|* *|
322\*===----------------------------------------------------------------------===*/
323
324
325#ifdef GET_REGINFO_MC_DESC
326#undef GET_REGINFO_MC_DESC
327
328namespace llvm {
329
330extern const int16_t SystemZRegDiffLists[] = {
331 /* 0 */ -64, 72, -40, -30, 72, -40, 0,
332 /* 7 */ -62, 72, -40, -30, 72, -40, 0,
333 /* 14 */ -60, 72, -40, -30, 72, -40, 0,
334 /* 21 */ -58, 72, -40, -30, 72, -40, 0,
335 /* 28 */ 32, 72, -40, 0,
336 /* 32 */ 40, -72, -32, 0,
337 /* 36 */ -48, 32, -16, -15, 32, -16, 0,
338 /* 43 */ -47, 32, -16, -15, 32, -16, 0,
339 /* 50 */ -46, 32, -16, -15, 32, -16, 0,
340 /* 57 */ -45, 32, -16, -15, 32, -16, 0,
341 /* 64 */ -44, 32, -16, -15, 32, -16, 0,
342 /* 71 */ -43, 32, -16, -15, 32, -16, 0,
343 /* 78 */ -42, 32, -16, -15, 32, -16, 0,
344 /* 85 */ -41, 32, -16, -15, 32, -16, 0,
345 /* 92 */ 1, 1, 1, 0,
346 /* 96 */ 2, 0,
347 /* 98 */ -32, 40, 0,
348 /* 101 */ -16, 40, 0,
349 /* 104 */ -32, 41, 0,
350 /* 107 */ -16, 41, 0,
351 /* 110 */ -32, 42, 0,
352 /* 113 */ -16, 42, 0,
353 /* 116 */ -32, 43, 0,
354 /* 119 */ -16, 43, 0,
355 /* 122 */ -32, 44, 0,
356 /* 125 */ -16, 44, 0,
357 /* 128 */ -32, 45, 0,
358 /* 131 */ -16, 45, 0,
359 /* 134 */ -32, 46, 0,
360 /* 137 */ -16, 46, 0,
361 /* 140 */ -32, 47, 0,
362 /* 143 */ -16, 47, 0,
363 /* 146 */ -32, 48, 0,
364 /* 149 */ -16, 48, 0,
365 /* 152 */ 40, -72, -32, 88, 0,
366 /* 157 */ 40, -72, -32, 90, 0,
367 /* 162 */ 40, -72, -32, 92, 0,
368 /* 167 */ 40, -72, -32, 94, 0,
369 /* 172 */ 40, -72, -32, 96, 0,
370};
371
372extern const LaneBitmask SystemZLaneMaskLists[] = {
373 /* 0 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000001),
374 /* 2 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000008),
375 /* 4 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008),
376 /* 8 */ LaneBitmask(0xFFFFFFFFFFFFFFFF),
377};
378
379extern const uint16_t SystemZSubRegIdxLists[] = {
380 /* 0 */ 3, 2, 1,
381 /* 3 */ 4, 2,
382 /* 5 */ 3, 4, 2, 5, 7, 6,
383 /* 11 */ 3, 2, 1, 5, 6, 8,
384};
385
386
387#ifdef __GNUC__
388#pragma GCC diagnostic push
389#pragma GCC diagnostic ignored "-Woverlength-strings"
390#endif
391extern const char SystemZRegStrings[] = {
392 /* 0 */ "A10\000"
393 /* 4 */ "C10\000"
394 /* 8 */ "V10\000"
395 /* 12 */ "V20\000"
396 /* 16 */ "V30\000"
397 /* 20 */ "A0\000"
398 /* 23 */ "C0\000"
399 /* 26 */ "V0\000"
400 /* 29 */ "A11\000"
401 /* 33 */ "C11\000"
402 /* 37 */ "V11\000"
403 /* 41 */ "V21\000"
404 /* 45 */ "V31\000"
405 /* 49 */ "A1\000"
406 /* 52 */ "C1\000"
407 /* 55 */ "V1\000"
408 /* 58 */ "A12\000"
409 /* 62 */ "C12\000"
410 /* 66 */ "V12\000"
411 /* 70 */ "V22\000"
412 /* 74 */ "A2\000"
413 /* 77 */ "C2\000"
414 /* 80 */ "V2\000"
415 /* 83 */ "A13\000"
416 /* 87 */ "C13\000"
417 /* 91 */ "V13\000"
418 /* 95 */ "V23\000"
419 /* 99 */ "A3\000"
420 /* 102 */ "C3\000"
421 /* 105 */ "V3\000"
422 /* 108 */ "A14\000"
423 /* 112 */ "C14\000"
424 /* 116 */ "V14\000"
425 /* 120 */ "V24\000"
426 /* 124 */ "A4\000"
427 /* 127 */ "C4\000"
428 /* 130 */ "V4\000"
429 /* 133 */ "A15\000"
430 /* 137 */ "C15\000"
431 /* 141 */ "V15\000"
432 /* 145 */ "V25\000"
433 /* 149 */ "A5\000"
434 /* 152 */ "C5\000"
435 /* 155 */ "V5\000"
436 /* 158 */ "V16\000"
437 /* 162 */ "V26\000"
438 /* 166 */ "A6\000"
439 /* 169 */ "C6\000"
440 /* 172 */ "V6\000"
441 /* 175 */ "V17\000"
442 /* 179 */ "V27\000"
443 /* 183 */ "A7\000"
444 /* 186 */ "C7\000"
445 /* 189 */ "V7\000"
446 /* 192 */ "V18\000"
447 /* 196 */ "V28\000"
448 /* 200 */ "A8\000"
449 /* 203 */ "C8\000"
450 /* 206 */ "V8\000"
451 /* 209 */ "V19\000"
452 /* 213 */ "V29\000"
453 /* 217 */ "A9\000"
454 /* 220 */ "C9\000"
455 /* 223 */ "V9\000"
456 /* 226 */ "CC\000"
457 /* 229 */ "FPC\000"
458 /* 233 */ "F10D\000"
459 /* 238 */ "R10D\000"
460 /* 243 */ "F20D\000"
461 /* 248 */ "F30D\000"
462 /* 253 */ "F0D\000"
463 /* 257 */ "R0D\000"
464 /* 261 */ "F11D\000"
465 /* 266 */ "R11D\000"
466 /* 271 */ "F21D\000"
467 /* 276 */ "F31D\000"
468 /* 281 */ "F1D\000"
469 /* 285 */ "R1D\000"
470 /* 289 */ "F12D\000"
471 /* 294 */ "R12D\000"
472 /* 299 */ "F22D\000"
473 /* 304 */ "F2D\000"
474 /* 308 */ "R2D\000"
475 /* 312 */ "F13D\000"
476 /* 317 */ "R13D\000"
477 /* 322 */ "F23D\000"
478 /* 327 */ "F3D\000"
479 /* 331 */ "R3D\000"
480 /* 335 */ "F14D\000"
481 /* 340 */ "R14D\000"
482 /* 345 */ "F24D\000"
483 /* 350 */ "F4D\000"
484 /* 354 */ "R4D\000"
485 /* 358 */ "F15D\000"
486 /* 363 */ "R15D\000"
487 /* 368 */ "F25D\000"
488 /* 373 */ "F5D\000"
489 /* 377 */ "R5D\000"
490 /* 381 */ "F16D\000"
491 /* 386 */ "F26D\000"
492 /* 391 */ "F6D\000"
493 /* 395 */ "R6D\000"
494 /* 399 */ "F17D\000"
495 /* 404 */ "F27D\000"
496 /* 409 */ "F7D\000"
497 /* 413 */ "R7D\000"
498 /* 417 */ "F18D\000"
499 /* 422 */ "F28D\000"
500 /* 427 */ "F8D\000"
501 /* 431 */ "R8D\000"
502 /* 435 */ "F19D\000"
503 /* 440 */ "F29D\000"
504 /* 445 */ "F9D\000"
505 /* 449 */ "R9D\000"
506 /* 453 */ "F10H\000"
507 /* 458 */ "R10H\000"
508 /* 463 */ "F20H\000"
509 /* 468 */ "F30H\000"
510 /* 473 */ "F0H\000"
511 /* 477 */ "R0H\000"
512 /* 481 */ "F11H\000"
513 /* 486 */ "R11H\000"
514 /* 491 */ "F21H\000"
515 /* 496 */ "F31H\000"
516 /* 501 */ "F1H\000"
517 /* 505 */ "R1H\000"
518 /* 509 */ "F12H\000"
519 /* 514 */ "R12H\000"
520 /* 519 */ "F22H\000"
521 /* 524 */ "F2H\000"
522 /* 528 */ "R2H\000"
523 /* 532 */ "F13H\000"
524 /* 537 */ "R13H\000"
525 /* 542 */ "F23H\000"
526 /* 547 */ "F3H\000"
527 /* 551 */ "R3H\000"
528 /* 555 */ "F14H\000"
529 /* 560 */ "R14H\000"
530 /* 565 */ "F24H\000"
531 /* 570 */ "F4H\000"
532 /* 574 */ "R4H\000"
533 /* 578 */ "F15H\000"
534 /* 583 */ "R15H\000"
535 /* 588 */ "F25H\000"
536 /* 593 */ "F5H\000"
537 /* 597 */ "R5H\000"
538 /* 601 */ "F16H\000"
539 /* 606 */ "F26H\000"
540 /* 611 */ "F6H\000"
541 /* 615 */ "R6H\000"
542 /* 619 */ "F17H\000"
543 /* 624 */ "F27H\000"
544 /* 629 */ "F7H\000"
545 /* 633 */ "R7H\000"
546 /* 637 */ "F18H\000"
547 /* 642 */ "F28H\000"
548 /* 647 */ "F8H\000"
549 /* 651 */ "R8H\000"
550 /* 655 */ "F19H\000"
551 /* 660 */ "F29H\000"
552 /* 665 */ "F9H\000"
553 /* 669 */ "R9H\000"
554 /* 673 */ "R10L\000"
555 /* 678 */ "R0L\000"
556 /* 682 */ "R11L\000"
557 /* 687 */ "R1L\000"
558 /* 691 */ "R12L\000"
559 /* 696 */ "R2L\000"
560 /* 700 */ "R13L\000"
561 /* 705 */ "R3L\000"
562 /* 709 */ "R14L\000"
563 /* 714 */ "R4L\000"
564 /* 718 */ "R15L\000"
565 /* 723 */ "R5L\000"
566 /* 727 */ "R6L\000"
567 /* 731 */ "R7L\000"
568 /* 735 */ "R8L\000"
569 /* 739 */ "R9L\000"
570 /* 743 */ "R10Q\000"
571 /* 748 */ "F0Q\000"
572 /* 752 */ "R0Q\000"
573 /* 756 */ "F1Q\000"
574 /* 760 */ "F12Q\000"
575 /* 765 */ "R12Q\000"
576 /* 770 */ "R2Q\000"
577 /* 774 */ "F13Q\000"
578 /* 779 */ "R14Q\000"
579 /* 784 */ "F4Q\000"
580 /* 788 */ "R4Q\000"
581 /* 792 */ "F5Q\000"
582 /* 796 */ "R6Q\000"
583 /* 800 */ "F8Q\000"
584 /* 804 */ "R8Q\000"
585 /* 808 */ "F9Q\000"
586 /* 812 */ "F10S\000"
587 /* 817 */ "F20S\000"
588 /* 822 */ "F30S\000"
589 /* 827 */ "F0S\000"
590 /* 831 */ "F11S\000"
591 /* 836 */ "F21S\000"
592 /* 841 */ "F31S\000"
593 /* 846 */ "F1S\000"
594 /* 850 */ "F12S\000"
595 /* 855 */ "F22S\000"
596 /* 860 */ "F2S\000"
597 /* 864 */ "F13S\000"
598 /* 869 */ "F23S\000"
599 /* 874 */ "F3S\000"
600 /* 878 */ "F14S\000"
601 /* 883 */ "F24S\000"
602 /* 888 */ "F4S\000"
603 /* 892 */ "F15S\000"
604 /* 897 */ "F25S\000"
605 /* 902 */ "F5S\000"
606 /* 906 */ "F16S\000"
607 /* 911 */ "F26S\000"
608 /* 916 */ "F6S\000"
609 /* 920 */ "F17S\000"
610 /* 925 */ "F27S\000"
611 /* 930 */ "F7S\000"
612 /* 934 */ "F18S\000"
613 /* 939 */ "F28S\000"
614 /* 944 */ "F8S\000"
615 /* 948 */ "F19S\000"
616 /* 953 */ "F29S\000"
617 /* 958 */ "F9S\000"
618};
619#ifdef __GNUC__
620#pragma GCC diagnostic pop
621#endif
622
623extern const MCRegisterDesc SystemZRegDesc[] = { // Descriptors
624 { 3, 0, 0, 0, 0, 0, 0, 0 },
625 { 226, 6, 6, 3, 24576, 8, 0, 0 },
626 { 229, 6, 6, 3, 24577, 8, 0, 0 },
627 { 20, 6, 6, 3, 24578, 8, 0, 0 },
628 { 49, 6, 6, 3, 24579, 8, 0, 0 },
629 { 74, 6, 6, 3, 24580, 8, 0, 0 },
630 { 99, 6, 6, 3, 24581, 8, 0, 0 },
631 { 124, 6, 6, 3, 24582, 8, 0, 0 },
632 { 149, 6, 6, 3, 24583, 8, 0, 0 },
633 { 166, 6, 6, 3, 24584, 8, 0, 0 },
634 { 183, 6, 6, 3, 24585, 8, 0, 0 },
635 { 200, 6, 6, 3, 24586, 8, 0, 0 },
636 { 217, 6, 6, 3, 24587, 8, 0, 0 },
637 { 0, 6, 6, 3, 24588, 8, 0, 0 },
638 { 29, 6, 6, 3, 24589, 8, 0, 0 },
639 { 58, 6, 6, 3, 24590, 8, 0, 0 },
640 { 83, 6, 6, 3, 24591, 8, 0, 0 },
641 { 108, 6, 6, 3, 24592, 8, 0, 0 },
642 { 133, 6, 6, 3, 24593, 8, 0, 0 },
643 { 23, 6, 6, 3, 24594, 8, 0, 0 },
644 { 52, 6, 6, 3, 24595, 8, 0, 0 },
645 { 77, 6, 6, 3, 24596, 8, 0, 0 },
646 { 102, 6, 6, 3, 24597, 8, 0, 0 },
647 { 127, 6, 6, 3, 24598, 8, 0, 0 },
648 { 152, 6, 6, 3, 24599, 8, 0, 0 },
649 { 169, 6, 6, 3, 24600, 8, 0, 0 },
650 { 186, 6, 6, 3, 24601, 8, 0, 0 },
651 { 203, 6, 6, 3, 24602, 8, 0, 0 },
652 { 220, 6, 6, 3, 24603, 8, 0, 0 },
653 { 4, 6, 6, 3, 24604, 8, 0, 0 },
654 { 33, 6, 6, 3, 24605, 8, 0, 0 },
655 { 62, 6, 6, 3, 24606, 8, 0, 0 },
656 { 87, 6, 6, 3, 24607, 8, 0, 0 },
657 { 112, 6, 6, 3, 24608, 8, 0, 0 },
658 { 137, 6, 6, 3, 24609, 8, 0, 0 },
659 { 26, 28, 6, 0, 24610, 1, 0, 0 },
660 { 55, 28, 6, 0, 24611, 1, 0, 0 },
661 { 80, 28, 6, 0, 24612, 1, 0, 0 },
662 { 105, 28, 6, 0, 24613, 1, 0, 0 },
663 { 130, 28, 6, 0, 24614, 1, 0, 0 },
664 { 155, 28, 6, 0, 24615, 1, 0, 0 },
665 { 172, 28, 6, 0, 24616, 1, 0, 0 },
666 { 189, 28, 6, 0, 24617, 1, 0, 0 },
667 { 206, 28, 6, 0, 24618, 1, 0, 0 },
668 { 223, 28, 6, 0, 24619, 1, 0, 0 },
669 { 8, 28, 6, 0, 24620, 1, 0, 0 },
670 { 37, 28, 6, 0, 24621, 1, 0, 0 },
671 { 66, 28, 6, 0, 24622, 1, 0, 0 },
672 { 91, 28, 6, 0, 24623, 1, 0, 0 },
673 { 116, 28, 6, 0, 24624, 1, 0, 0 },
674 { 141, 28, 6, 0, 24625, 1, 0, 0 },
675 { 158, 28, 6, 0, 24626, 1, 0, 0 },
676 { 175, 28, 6, 0, 24627, 1, 0, 0 },
677 { 192, 28, 6, 0, 24628, 1, 0, 0 },
678 { 209, 28, 6, 0, 24629, 1, 0, 0 },
679 { 12, 28, 6, 0, 24630, 1, 0, 0 },
680 { 41, 28, 6, 0, 24631, 1, 0, 0 },
681 { 70, 28, 6, 0, 24632, 1, 0, 0 },
682 { 95, 28, 6, 0, 24633, 1, 0, 0 },
683 { 120, 28, 6, 0, 24634, 1, 0, 0 },
684 { 145, 28, 6, 0, 24635, 1, 0, 0 },
685 { 162, 28, 6, 0, 24636, 1, 0, 0 },
686 { 179, 28, 6, 0, 24637, 1, 0, 0 },
687 { 196, 28, 6, 0, 24638, 1, 0, 0 },
688 { 213, 28, 6, 0, 24639, 1, 0, 0 },
689 { 16, 28, 6, 0, 24640, 1, 0, 0 },
690 { 45, 28, 6, 0, 24641, 1, 0, 0 },
691 { 253, 4, 174, 1, 24610, 1, 0, 0 },
692 { 281, 4, 174, 1, 24611, 1, 0, 0 },
693 { 304, 4, 169, 1, 24612, 1, 0, 0 },
694 { 327, 4, 169, 1, 24613, 1, 0, 0 },
695 { 350, 4, 169, 1, 24614, 1, 0, 0 },
696 { 373, 4, 169, 1, 24615, 1, 0, 0 },
697 { 391, 4, 164, 1, 24616, 1, 0, 0 },
698 { 409, 4, 164, 1, 24617, 1, 0, 0 },
699 { 427, 4, 164, 1, 24618, 1, 0, 0 },
700 { 445, 4, 164, 1, 24619, 1, 0, 0 },
701 { 233, 4, 159, 1, 24620, 1, 0, 0 },
702 { 261, 4, 159, 1, 24621, 1, 0, 0 },
703 { 289, 4, 159, 1, 24622, 1, 0, 0 },
704 { 312, 4, 159, 1, 24623, 1, 0, 0 },
705 { 335, 4, 154, 1, 24624, 1, 0, 0 },
706 { 358, 4, 154, 1, 24625, 1, 0, 0 },
707 { 381, 4, 34, 1, 24626, 1, 0, 0 },
708 { 399, 4, 34, 1, 24627, 1, 0, 0 },
709 { 417, 4, 34, 1, 24628, 1, 0, 0 },
710 { 435, 4, 34, 1, 24629, 1, 0, 0 },
711 { 243, 4, 34, 1, 24630, 1, 0, 0 },
712 { 271, 4, 34, 1, 24631, 1, 0, 0 },
713 { 299, 4, 34, 1, 24632, 1, 0, 0 },
714 { 322, 4, 34, 1, 24633, 1, 0, 0 },
715 { 345, 4, 34, 1, 24634, 1, 0, 0 },
716 { 368, 4, 34, 1, 24635, 1, 0, 0 },
717 { 386, 4, 34, 1, 24636, 1, 0, 0 },
718 { 404, 4, 34, 1, 24637, 1, 0, 0 },
719 { 422, 4, 34, 1, 24638, 1, 0, 0 },
720 { 440, 4, 34, 1, 24639, 1, 0, 0 },
721 { 248, 4, 34, 1, 24640, 1, 0, 0 },
722 { 276, 4, 34, 1, 24641, 1, 0, 0 },
723 { 473, 6, 172, 3, 24610, 8, 0, 0 },
724 { 501, 6, 172, 3, 24611, 8, 0, 0 },
725 { 524, 6, 167, 3, 24612, 8, 0, 0 },
726 { 547, 6, 167, 3, 24613, 8, 0, 0 },
727 { 570, 6, 167, 3, 24614, 8, 0, 0 },
728 { 593, 6, 167, 3, 24615, 8, 0, 0 },
729 { 611, 6, 162, 3, 24616, 8, 0, 0 },
730 { 629, 6, 162, 3, 24617, 8, 0, 0 },
731 { 647, 6, 162, 3, 24618, 8, 0, 0 },
732 { 665, 6, 162, 3, 24619, 8, 0, 0 },
733 { 453, 6, 157, 3, 24620, 8, 0, 0 },
734 { 481, 6, 157, 3, 24621, 8, 0, 0 },
735 { 509, 6, 157, 3, 24622, 8, 0, 0 },
736 { 532, 6, 157, 3, 24623, 8, 0, 0 },
737 { 555, 6, 152, 3, 24624, 8, 0, 0 },
738 { 578, 6, 152, 3, 24625, 8, 0, 0 },
739 { 601, 6, 32, 3, 24626, 8, 0, 0 },
740 { 619, 6, 32, 3, 24627, 8, 0, 0 },
741 { 637, 6, 32, 3, 24628, 8, 0, 0 },
742 { 655, 6, 32, 3, 24629, 8, 0, 0 },
743 { 463, 6, 32, 3, 24630, 8, 0, 0 },
744 { 491, 6, 32, 3, 24631, 8, 0, 0 },
745 { 519, 6, 32, 3, 24632, 8, 0, 0 },
746 { 542, 6, 32, 3, 24633, 8, 0, 0 },
747 { 565, 6, 32, 3, 24634, 8, 0, 0 },
748 { 588, 6, 32, 3, 24635, 8, 0, 0 },
749 { 606, 6, 32, 3, 24636, 8, 0, 0 },
750 { 624, 6, 32, 3, 24637, 8, 0, 0 },
751 { 642, 6, 32, 3, 24638, 8, 0, 0 },
752 { 660, 6, 32, 3, 24639, 8, 0, 0 },
753 { 468, 6, 32, 3, 24640, 8, 0, 0 },
754 { 496, 6, 32, 3, 24641, 8, 0, 0 },
755 { 748, 0, 6, 11, 393250, 2, 0, 0 },
756 { 756, 0, 6, 11, 393251, 2, 0, 0 },
757 { 784, 7, 6, 11, 393254, 2, 0, 0 },
758 { 792, 7, 6, 11, 393255, 2, 0, 0 },
759 { 800, 14, 6, 11, 393258, 2, 0, 0 },
760 { 808, 14, 6, 11, 393259, 2, 0, 0 },
761 { 760, 21, 6, 11, 393262, 2, 0, 0 },
762 { 774, 21, 6, 11, 393263, 2, 0, 0 },
763 { 827, 5, 173, 2, 24610, 1, 0, 0 },
764 { 846, 5, 173, 2, 24611, 1, 0, 0 },
765 { 860, 5, 168, 2, 24612, 1, 0, 0 },
766 { 874, 5, 168, 2, 24613, 1, 0, 0 },
767 { 888, 5, 168, 2, 24614, 1, 0, 0 },
768 { 902, 5, 168, 2, 24615, 1, 0, 0 },
769 { 916, 5, 163, 2, 24616, 1, 0, 0 },
770 { 930, 5, 163, 2, 24617, 1, 0, 0 },
771 { 944, 5, 163, 2, 24618, 1, 0, 0 },
772 { 958, 5, 163, 2, 24619, 1, 0, 0 },
773 { 812, 5, 158, 2, 24620, 1, 0, 0 },
774 { 831, 5, 158, 2, 24621, 1, 0, 0 },
775 { 850, 5, 158, 2, 24622, 1, 0, 0 },
776 { 864, 5, 158, 2, 24623, 1, 0, 0 },
777 { 878, 5, 153, 2, 24624, 1, 0, 0 },
778 { 892, 5, 153, 2, 24625, 1, 0, 0 },
779 { 906, 5, 33, 2, 24626, 1, 0, 0 },
780 { 920, 5, 33, 2, 24627, 1, 0, 0 },
781 { 934, 5, 33, 2, 24628, 1, 0, 0 },
782 { 948, 5, 33, 2, 24629, 1, 0, 0 },
783 { 817, 5, 33, 2, 24630, 1, 0, 0 },
784 { 836, 5, 33, 2, 24631, 1, 0, 0 },
785 { 855, 5, 33, 2, 24632, 1, 0, 0 },
786 { 869, 5, 33, 2, 24633, 1, 0, 0 },
787 { 883, 5, 33, 2, 24634, 1, 0, 0 },
788 { 897, 5, 33, 2, 24635, 1, 0, 0 },
789 { 911, 5, 33, 2, 24636, 1, 0, 0 },
790 { 925, 5, 33, 2, 24637, 1, 0, 0 },
791 { 939, 5, 33, 2, 24638, 1, 0, 0 },
792 { 953, 5, 33, 2, 24639, 1, 0, 0 },
793 { 822, 5, 33, 2, 24640, 1, 0, 0 },
794 { 841, 5, 33, 2, 24641, 1, 0, 0 },
795 { 257, 40, 147, 3, 385090, 0, 0, 0 },
796 { 285, 40, 141, 3, 385092, 0, 0, 0 },
797 { 308, 40, 141, 3, 385094, 0, 0, 0 },
798 { 331, 40, 135, 3, 385096, 0, 0, 0 },
799 { 354, 40, 135, 3, 385098, 0, 0, 0 },
800 { 377, 40, 129, 3, 385100, 0, 0, 0 },
801 { 395, 40, 129, 3, 385102, 0, 0, 0 },
802 { 413, 40, 123, 3, 385104, 0, 0, 0 },
803 { 431, 40, 123, 3, 385106, 0, 0, 0 },
804 { 449, 40, 117, 3, 385108, 0, 0, 0 },
805 { 238, 40, 117, 3, 385110, 0, 0, 0 },
806 { 266, 40, 111, 3, 385112, 0, 0, 0 },
807 { 294, 40, 111, 3, 385114, 0, 0, 0 },
808 { 317, 40, 105, 3, 385116, 0, 0, 0 },
809 { 340, 40, 105, 3, 385118, 0, 0, 0 },
810 { 363, 40, 99, 3, 385120, 0, 0, 0 },
811 { 477, 6, 149, 3, 24643, 8, 0, 0 },
812 { 505, 6, 143, 3, 24645, 8, 0, 0 },
813 { 528, 6, 143, 3, 24647, 8, 0, 0 },
814 { 551, 6, 137, 3, 24649, 8, 0, 0 },
815 { 574, 6, 137, 3, 24651, 8, 0, 0 },
816 { 597, 6, 131, 3, 24653, 8, 0, 0 },
817 { 615, 6, 131, 3, 24655, 8, 0, 0 },
818 { 633, 6, 125, 3, 24657, 8, 0, 0 },
819 { 651, 6, 125, 3, 24659, 8, 0, 0 },
820 { 669, 6, 119, 3, 24661, 8, 0, 0 },
821 { 458, 6, 119, 3, 24663, 8, 0, 0 },
822 { 486, 6, 113, 3, 24665, 8, 0, 0 },
823 { 514, 6, 113, 3, 24667, 8, 0, 0 },
824 { 537, 6, 107, 3, 24669, 8, 0, 0 },
825 { 560, 6, 107, 3, 24671, 8, 0, 0 },
826 { 583, 6, 101, 3, 24673, 8, 0, 0 },
827 { 678, 6, 146, 3, 24642, 8, 0, 0 },
828 { 687, 6, 140, 3, 24644, 8, 0, 0 },
829 { 696, 6, 140, 3, 24646, 8, 0, 0 },
830 { 705, 6, 134, 3, 24648, 8, 0, 0 },
831 { 714, 6, 134, 3, 24650, 8, 0, 0 },
832 { 723, 6, 128, 3, 24652, 8, 0, 0 },
833 { 727, 6, 128, 3, 24654, 8, 0, 0 },
834 { 731, 6, 122, 3, 24656, 8, 0, 0 },
835 { 735, 6, 122, 3, 24658, 8, 0, 0 },
836 { 739, 6, 116, 3, 24660, 8, 0, 0 },
837 { 673, 6, 116, 3, 24662, 8, 0, 0 },
838 { 682, 6, 110, 3, 24664, 8, 0, 0 },
839 { 691, 6, 110, 3, 24666, 8, 0, 0 },
840 { 700, 6, 104, 3, 24668, 8, 0, 0 },
841 { 709, 6, 104, 3, 24670, 8, 0, 0 },
842 { 718, 6, 98, 3, 24672, 8, 0, 0 },
843 { 752, 36, 6, 5, 376898, 4, 0, 0 },
844 { 770, 43, 6, 5, 376902, 4, 0, 0 },
845 { 788, 50, 6, 5, 376906, 4, 0, 0 },
846 { 796, 57, 6, 5, 376910, 4, 0, 0 },
847 { 804, 64, 6, 5, 376914, 4, 0, 0 },
848 { 743, 71, 6, 5, 376918, 4, 0, 0 },
849 { 765, 78, 6, 5, 376922, 4, 0, 0 },
850 { 779, 85, 6, 5, 376926, 4, 0, 0 },
851};
852
853extern const MCPhysReg SystemZRegUnitRoots[][2] = {
854 { SystemZ::CC },
855 { SystemZ::FPC },
856 { SystemZ::A0 },
857 { SystemZ::A1 },
858 { SystemZ::A2 },
859 { SystemZ::A3 },
860 { SystemZ::A4 },
861 { SystemZ::A5 },
862 { SystemZ::A6 },
863 { SystemZ::A7 },
864 { SystemZ::A8 },
865 { SystemZ::A9 },
866 { SystemZ::A10 },
867 { SystemZ::A11 },
868 { SystemZ::A12 },
869 { SystemZ::A13 },
870 { SystemZ::A14 },
871 { SystemZ::A15 },
872 { SystemZ::C0 },
873 { SystemZ::C1 },
874 { SystemZ::C2 },
875 { SystemZ::C3 },
876 { SystemZ::C4 },
877 { SystemZ::C5 },
878 { SystemZ::C6 },
879 { SystemZ::C7 },
880 { SystemZ::C8 },
881 { SystemZ::C9 },
882 { SystemZ::C10 },
883 { SystemZ::C11 },
884 { SystemZ::C12 },
885 { SystemZ::C13 },
886 { SystemZ::C14 },
887 { SystemZ::C15 },
888 { SystemZ::F0H },
889 { SystemZ::F1H },
890 { SystemZ::F2H },
891 { SystemZ::F3H },
892 { SystemZ::F4H },
893 { SystemZ::F5H },
894 { SystemZ::F6H },
895 { SystemZ::F7H },
896 { SystemZ::F8H },
897 { SystemZ::F9H },
898 { SystemZ::F10H },
899 { SystemZ::F11H },
900 { SystemZ::F12H },
901 { SystemZ::F13H },
902 { SystemZ::F14H },
903 { SystemZ::F15H },
904 { SystemZ::F16H },
905 { SystemZ::F17H },
906 { SystemZ::F18H },
907 { SystemZ::F19H },
908 { SystemZ::F20H },
909 { SystemZ::F21H },
910 { SystemZ::F22H },
911 { SystemZ::F23H },
912 { SystemZ::F24H },
913 { SystemZ::F25H },
914 { SystemZ::F26H },
915 { SystemZ::F27H },
916 { SystemZ::F28H },
917 { SystemZ::F29H },
918 { SystemZ::F30H },
919 { SystemZ::F31H },
920 { SystemZ::R0L },
921 { SystemZ::R0H },
922 { SystemZ::R1L },
923 { SystemZ::R1H },
924 { SystemZ::R2L },
925 { SystemZ::R2H },
926 { SystemZ::R3L },
927 { SystemZ::R3H },
928 { SystemZ::R4L },
929 { SystemZ::R4H },
930 { SystemZ::R5L },
931 { SystemZ::R5H },
932 { SystemZ::R6L },
933 { SystemZ::R6H },
934 { SystemZ::R7L },
935 { SystemZ::R7H },
936 { SystemZ::R8L },
937 { SystemZ::R8H },
938 { SystemZ::R9L },
939 { SystemZ::R9H },
940 { SystemZ::R10L },
941 { SystemZ::R10H },
942 { SystemZ::R11L },
943 { SystemZ::R11H },
944 { SystemZ::R12L },
945 { SystemZ::R12H },
946 { SystemZ::R13L },
947 { SystemZ::R13H },
948 { SystemZ::R14L },
949 { SystemZ::R14H },
950 { SystemZ::R15L },
951 { SystemZ::R15H },
952};
953
954namespace { // Register classes...
955 // VR16Bit Register Class...
956 const MCPhysReg VR16Bit[] = {
957 SystemZ::F0H, SystemZ::F1H, SystemZ::F2H, SystemZ::F3H, SystemZ::F4H, SystemZ::F5H, SystemZ::F6H, SystemZ::F7H, SystemZ::F16H, SystemZ::F17H, SystemZ::F18H, SystemZ::F19H, SystemZ::F20H, SystemZ::F21H, SystemZ::F22H, SystemZ::F23H, SystemZ::F24H, SystemZ::F25H, SystemZ::F26H, SystemZ::F27H, SystemZ::F28H, SystemZ::F29H, SystemZ::F30H, SystemZ::F31H, SystemZ::F8H, SystemZ::F9H, SystemZ::F10H, SystemZ::F11H, SystemZ::F12H, SystemZ::F13H, SystemZ::F14H, SystemZ::F15H,
958 };
959
960 // VR16Bit Bit set.
961 const uint8_t VR16BitBits[] = {
962 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
963 };
964
965 // FP16Bit Register Class...
966 const MCPhysReg FP16Bit[] = {
967 SystemZ::F0H, SystemZ::F1H, SystemZ::F2H, SystemZ::F3H, SystemZ::F4H, SystemZ::F5H, SystemZ::F6H, SystemZ::F7H, SystemZ::F8H, SystemZ::F9H, SystemZ::F10H, SystemZ::F11H, SystemZ::F12H, SystemZ::F13H, SystemZ::F14H, SystemZ::F15H,
968 };
969
970 // FP16Bit Bit set.
971 const uint8_t FP16BitBits[] = {
972 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
973 };
974
975 // GRX32Bit Register Class...
976 const MCPhysReg GRX32Bit[] = {
977 SystemZ::R0L, SystemZ::R1L, SystemZ::R2L, SystemZ::R3L, SystemZ::R4L, SystemZ::R5L, SystemZ::R0H, SystemZ::R1H, SystemZ::R2H, SystemZ::R3H, SystemZ::R4H, SystemZ::R5H, SystemZ::R15L, SystemZ::R15H, SystemZ::R14L, SystemZ::R14H, SystemZ::R13L, SystemZ::R13H, SystemZ::R12L, SystemZ::R12H, SystemZ::R11L, SystemZ::R11H, SystemZ::R10L, SystemZ::R10H, SystemZ::R9L, SystemZ::R9H, SystemZ::R8L, SystemZ::R8H, SystemZ::R7L, SystemZ::R7H, SystemZ::R6L, SystemZ::R6H,
978 };
979
980 // GRX32Bit Bit set.
981 const uint8_t GRX32BitBits[] = {
982 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
983 };
984
985 // VR32Bit Register Class...
986 const MCPhysReg VR32Bit[] = {
987 SystemZ::F0S, SystemZ::F1S, SystemZ::F2S, SystemZ::F3S, SystemZ::F4S, SystemZ::F5S, SystemZ::F6S, SystemZ::F7S, SystemZ::F16S, SystemZ::F17S, SystemZ::F18S, SystemZ::F19S, SystemZ::F20S, SystemZ::F21S, SystemZ::F22S, SystemZ::F23S, SystemZ::F24S, SystemZ::F25S, SystemZ::F26S, SystemZ::F27S, SystemZ::F28S, SystemZ::F29S, SystemZ::F30S, SystemZ::F31S, SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S, SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S,
988 };
989
990 // VR32Bit Bit set.
991 const uint8_t VR32BitBits[] = {
992 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
993 };
994
995 // AR32Bit Register Class...
996 const MCPhysReg AR32Bit[] = {
997 SystemZ::A0, SystemZ::A1, SystemZ::A2, SystemZ::A3, SystemZ::A4, SystemZ::A5, SystemZ::A6, SystemZ::A7, SystemZ::A8, SystemZ::A9, SystemZ::A10, SystemZ::A11, SystemZ::A12, SystemZ::A13, SystemZ::A14, SystemZ::A15,
998 };
999
1000 // AR32Bit Bit set.
1001 const uint8_t AR32BitBits[] = {
1002 0xf8, 0xff, 0x07,
1003 };
1004
1005 // FP32Bit Register Class...
1006 const MCPhysReg FP32Bit[] = {
1007 SystemZ::F0S, SystemZ::F1S, SystemZ::F2S, SystemZ::F3S, SystemZ::F4S, SystemZ::F5S, SystemZ::F6S, SystemZ::F7S, SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S, SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S,
1008 };
1009
1010 // FP32Bit Bit set.
1011 const uint8_t FP32BitBits[] = {
1012 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
1013 };
1014
1015 // GR32Bit Register Class...
1016 const MCPhysReg GR32Bit[] = {
1017 SystemZ::R0L, SystemZ::R1L, SystemZ::R2L, SystemZ::R3L, SystemZ::R4L, SystemZ::R5L, SystemZ::R15L, SystemZ::R14L, SystemZ::R13L, SystemZ::R12L, SystemZ::R11L, SystemZ::R10L, SystemZ::R9L, SystemZ::R8L, SystemZ::R7L, SystemZ::R6L,
1018 };
1019
1020 // GR32Bit Bit set.
1021 const uint8_t GR32BitBits[] = {
1022 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
1023 };
1024
1025 // GRH32Bit Register Class...
1026 const MCPhysReg GRH32Bit[] = {
1027 SystemZ::R0H, SystemZ::R1H, SystemZ::R2H, SystemZ::R3H, SystemZ::R4H, SystemZ::R5H, SystemZ::R15H, SystemZ::R14H, SystemZ::R13H, SystemZ::R12H, SystemZ::R11H, SystemZ::R10H, SystemZ::R9H, SystemZ::R8H, SystemZ::R7H, SystemZ::R6H,
1028 };
1029
1030 // GRH32Bit Bit set.
1031 const uint8_t GRH32BitBits[] = {
1032 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
1033 };
1034
1035 // ADDR32Bit Register Class...
1036 const MCPhysReg ADDR32Bit[] = {
1037 SystemZ::R1L, SystemZ::R2L, SystemZ::R3L, SystemZ::R4L, SystemZ::R5L, SystemZ::R15L, SystemZ::R14L, SystemZ::R13L, SystemZ::R12L, SystemZ::R11L, SystemZ::R10L, SystemZ::R9L, SystemZ::R8L, SystemZ::R7L, SystemZ::R6L,
1038 };
1039
1040 // ADDR32Bit Bit set.
1041 const uint8_t ADDR32BitBits[] = {
1042 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07,
1043 };
1044
1045 // CCR Register Class...
1046 const MCPhysReg CCR[] = {
1047 SystemZ::CC,
1048 };
1049
1050 // CCR Bit set.
1051 const uint8_t CCRBits[] = {
1052 0x02,
1053 };
1054
1055 // FPCRegs Register Class...
1056 const MCPhysReg FPCRegs[] = {
1057 SystemZ::FPC,
1058 };
1059
1060 // FPCRegs Bit set.
1061 const uint8_t FPCRegsBits[] = {
1062 0x04,
1063 };
1064
1065 // AnyRegBit Register Class...
1066 const MCPhysReg AnyRegBit[] = {
1067 SystemZ::R0D, SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, SystemZ::R5D, SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D, SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D, SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3, SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7, SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11, SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15,
1068 };
1069
1070 // AnyRegBit Bit set.
1071 const uint8_t AnyRegBitBits[] = {
1072 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07, 0x00, 0xf8, 0xff, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
1073 };
1074
1075 // AnyRegBit_with_subreg_h16 Register Class...
1076 const MCPhysReg AnyRegBit_with_subreg_h16[] = {
1077 SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D, SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3, SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7, SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11, SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15,
1078 };
1079
1080 // AnyRegBit_with_subreg_h16 Bit set.
1081 const uint8_t AnyRegBit_with_subreg_h16Bits[] = {
1082 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07, 0x00, 0xf8, 0xff, 0x07,
1083 };
1084
1085 // VR64Bit Register Class...
1086 const MCPhysReg VR64Bit[] = {
1087 SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, SystemZ::F16D, SystemZ::F17D, SystemZ::F18D, SystemZ::F19D, SystemZ::F20D, SystemZ::F21D, SystemZ::F22D, SystemZ::F23D, SystemZ::F24D, SystemZ::F25D, SystemZ::F26D, SystemZ::F27D, SystemZ::F28D, SystemZ::F29D, SystemZ::F30D, SystemZ::F31D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D,
1088 };
1089
1090 // VR64Bit Bit set.
1091 const uint8_t VR64BitBits[] = {
1092 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
1093 };
1094
1095 // AnyRegBit_with_subreg_h64 Register Class...
1096 const MCPhysReg AnyRegBit_with_subreg_h64[] = {
1097 SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3, SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7, SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11, SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15,
1098 };
1099
1100 // AnyRegBit_with_subreg_h64 Bit set.
1101 const uint8_t AnyRegBit_with_subreg_h64Bits[] = {
1102 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
1103 };
1104
1105 // CR64Bit Register Class...
1106 const MCPhysReg CR64Bit[] = {
1107 SystemZ::C0, SystemZ::C1, SystemZ::C2, SystemZ::C3, SystemZ::C4, SystemZ::C5, SystemZ::C6, SystemZ::C7, SystemZ::C8, SystemZ::C9, SystemZ::C10, SystemZ::C11, SystemZ::C12, SystemZ::C13, SystemZ::C14, SystemZ::C15,
1108 };
1109
1110 // CR64Bit Bit set.
1111 const uint8_t CR64BitBits[] = {
1112 0x00, 0x00, 0xf8, 0xff, 0x07,
1113 };
1114
1115 // FP64Bit Register Class...
1116 const MCPhysReg FP64Bit[] = {
1117 SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D,
1118 };
1119
1120 // FP64Bit Bit set.
1121 const uint8_t FP64BitBits[] = {
1122 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
1123 };
1124
1125 // GR64Bit Register Class...
1126 const MCPhysReg GR64Bit[] = {
1127 SystemZ::R0D, SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, SystemZ::R5D, SystemZ::R15D, SystemZ::R14D, SystemZ::R13D, SystemZ::R12D, SystemZ::R11D, SystemZ::R10D, SystemZ::R9D, SystemZ::R8D, SystemZ::R7D, SystemZ::R6D,
1128 };
1129
1130 // GR64Bit Bit set.
1131 const uint8_t GR64BitBits[] = {
1132 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
1133 };
1134
1135 // ADDR64Bit Register Class...
1136 const MCPhysReg ADDR64Bit[] = {
1137 SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, SystemZ::R5D, SystemZ::R15D, SystemZ::R14D, SystemZ::R13D, SystemZ::R12D, SystemZ::R11D, SystemZ::R10D, SystemZ::R9D, SystemZ::R8D, SystemZ::R7D, SystemZ::R6D,
1138 };
1139
1140 // ADDR64Bit Bit set.
1141 const uint8_t ADDR64BitBits[] = {
1142 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07,
1143 };
1144
1145 // VR128Bit Register Class...
1146 const MCPhysReg VR128Bit[] = {
1147 SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3, SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7, SystemZ::V16, SystemZ::V17, SystemZ::V18, SystemZ::V19, SystemZ::V20, SystemZ::V21, SystemZ::V22, SystemZ::V23, SystemZ::V24, SystemZ::V25, SystemZ::V26, SystemZ::V27, SystemZ::V28, SystemZ::V29, SystemZ::V30, SystemZ::V31, SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11, SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15,
1148 };
1149
1150 // VR128Bit Bit set.
1151 const uint8_t VR128BitBits[] = {
1152 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
1153 };
1154
1155 // VF128Bit Register Class...
1156 const MCPhysReg VF128Bit[] = {
1157 SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3, SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7, SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11, SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15,
1158 };
1159
1160 // VF128Bit Bit set.
1161 const uint8_t VF128BitBits[] = {
1162 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
1163 };
1164
1165 // FP128Bit Register Class...
1166 const MCPhysReg FP128Bit[] = {
1167 SystemZ::F0Q, SystemZ::F1Q, SystemZ::F4Q, SystemZ::F5Q, SystemZ::F8Q, SystemZ::F9Q, SystemZ::F12Q, SystemZ::F13Q,
1168 };
1169
1170 // FP128Bit Bit set.
1171 const uint8_t FP128BitBits[] = {
1172 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
1173 };
1174
1175 // GR128Bit Register Class...
1176 const MCPhysReg GR128Bit[] = {
1177 SystemZ::R0Q, SystemZ::R2Q, SystemZ::R4Q, SystemZ::R12Q, SystemZ::R10Q, SystemZ::R8Q, SystemZ::R6Q, SystemZ::R14Q,
1178 };
1179
1180 // GR128Bit Bit set.
1181 const uint8_t GR128BitBits[] = {
1182 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
1183 };
1184
1185 // ADDR128Bit Register Class...
1186 const MCPhysReg ADDR128Bit[] = {
1187 SystemZ::R2Q, SystemZ::R4Q, SystemZ::R12Q, SystemZ::R10Q, SystemZ::R8Q, SystemZ::R6Q, SystemZ::R14Q,
1188 };
1189
1190 // ADDR128Bit Bit set.
1191 const uint8_t ADDR128BitBits[] = {
1192 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x07,
1193 };
1194
1195} // end anonymous namespace
1196
1197
1198#ifdef __GNUC__
1199#pragma GCC diagnostic push
1200#pragma GCC diagnostic ignored "-Woverlength-strings"
1201#endif
1202extern const char SystemZRegClassStrings[] = {
1203 /* 0 */ "AnyRegBit_with_subreg_h64\000"
1204 /* 26 */ "AnyRegBit_with_subreg_h16\000"
1205 /* 52 */ "CCR\000"
1206 /* 56 */ "FPCRegs\000"
1207 /* 64 */ "GRH32Bit\000"
1208 /* 73 */ "FP32Bit\000"
1209 /* 81 */ "AR32Bit\000"
1210 /* 89 */ "ADDR32Bit\000"
1211 /* 99 */ "GR32Bit\000"
1212 /* 107 */ "VR32Bit\000"
1213 /* 115 */ "GRX32Bit\000"
1214 /* 124 */ "FP64Bit\000"
1215 /* 132 */ "CR64Bit\000"
1216 /* 140 */ "ADDR64Bit\000"
1217 /* 150 */ "GR64Bit\000"
1218 /* 158 */ "VR64Bit\000"
1219 /* 166 */ "FP16Bit\000"
1220 /* 174 */ "VR16Bit\000"
1221 /* 182 */ "VF128Bit\000"
1222 /* 191 */ "FP128Bit\000"
1223 /* 200 */ "ADDR128Bit\000"
1224 /* 211 */ "GR128Bit\000"
1225 /* 220 */ "VR128Bit\000"
1226 /* 229 */ "AnyRegBit\000"
1227};
1228#ifdef __GNUC__
1229#pragma GCC diagnostic pop
1230#endif
1231
1232extern const MCRegisterClass SystemZMCRegisterClasses[] = {
1233 { VR16Bit, VR16BitBits, 174, 32, sizeof(VR16BitBits), SystemZ::VR16BitRegClassID, 16, 1, true, false },
1234 { FP16Bit, FP16BitBits, 166, 16, sizeof(FP16BitBits), SystemZ::FP16BitRegClassID, 0, 1, true, false },
1235 { GRX32Bit, GRX32BitBits, 115, 32, sizeof(GRX32BitBits), SystemZ::GRX32BitRegClassID, 32, 1, true, false },
1236 { VR32Bit, VR32BitBits, 107, 32, sizeof(VR32BitBits), SystemZ::VR32BitRegClassID, 32, 1, true, false },
1237 { AR32Bit, AR32BitBits, 81, 16, sizeof(AR32BitBits), SystemZ::AR32BitRegClassID, 32, 1, false, false },
1238 { FP32Bit, FP32BitBits, 73, 16, sizeof(FP32BitBits), SystemZ::FP32BitRegClassID, 32, 1, true, false },
1239 { GR32Bit, GR32BitBits, 99, 16, sizeof(GR32BitBits), SystemZ::GR32BitRegClassID, 32, 1, true, false },
1240 { GRH32Bit, GRH32BitBits, 64, 16, sizeof(GRH32BitBits), SystemZ::GRH32BitRegClassID, 32, 1, true, false },
1241 { ADDR32Bit, ADDR32BitBits, 89, 15, sizeof(ADDR32BitBits), SystemZ::ADDR32BitRegClassID, 32, 1, true, false },
1242 { CCR, CCRBits, 52, 1, sizeof(CCRBits), SystemZ::CCRRegClassID, 32, -1, false, false },
1243 { FPCRegs, FPCRegsBits, 56, 1, sizeof(FPCRegsBits), SystemZ::FPCRegsRegClassID, 32, 1, false, false },
1244 { AnyRegBit, AnyRegBitBits, 229, 48, sizeof(AnyRegBitBits), SystemZ::AnyRegBitRegClassID, 64, 1, false, false },
1245 { AnyRegBit_with_subreg_h16, AnyRegBit_with_subreg_h16Bits, 26, 32, sizeof(AnyRegBit_with_subreg_h16Bits), SystemZ::AnyRegBit_with_subreg_h16RegClassID, 64, 1, false, false },
1246 { VR64Bit, VR64BitBits, 158, 32, sizeof(VR64BitBits), SystemZ::VR64BitRegClassID, 64, 1, true, false },
1247 { AnyRegBit_with_subreg_h64, AnyRegBit_with_subreg_h64Bits, 0, 16, sizeof(AnyRegBit_with_subreg_h64Bits), SystemZ::AnyRegBit_with_subreg_h64RegClassID, 64, 1, false, false },
1248 { CR64Bit, CR64BitBits, 132, 16, sizeof(CR64BitBits), SystemZ::CR64BitRegClassID, 64, 1, false, false },
1249 { FP64Bit, FP64BitBits, 124, 16, sizeof(FP64BitBits), SystemZ::FP64BitRegClassID, 64, 1, true, false },
1250 { GR64Bit, GR64BitBits, 150, 16, sizeof(GR64BitBits), SystemZ::GR64BitRegClassID, 64, 1, true, false },
1251 { ADDR64Bit, ADDR64BitBits, 140, 15, sizeof(ADDR64BitBits), SystemZ::ADDR64BitRegClassID, 64, 1, true, false },
1252 { VR128Bit, VR128BitBits, 220, 32, sizeof(VR128BitBits), SystemZ::VR128BitRegClassID, 128, 1, true, false },
1253 { VF128Bit, VF128BitBits, 182, 16, sizeof(VF128BitBits), SystemZ::VF128BitRegClassID, 128, 1, true, false },
1254 { FP128Bit, FP128BitBits, 191, 8, sizeof(FP128BitBits), SystemZ::FP128BitRegClassID, 128, 1, true, false },
1255 { GR128Bit, GR128BitBits, 211, 8, sizeof(GR128BitBits), SystemZ::GR128BitRegClassID, 128, 1, true, false },
1256 { ADDR128Bit, ADDR128BitBits, 200, 7, sizeof(ADDR128BitBits), SystemZ::ADDR128BitRegClassID, 128, 1, true, false },
1257};
1258
1259// SystemZ Dwarf<->LLVM register mappings.
1260extern const MCRegisterInfo::DwarfLLVMRegPair SystemZDwarfFlavour0Dwarf2L[] = {
1261 { 0U, SystemZ::R0D },
1262 { 1U, SystemZ::R1D },
1263 { 2U, SystemZ::R2D },
1264 { 3U, SystemZ::R3D },
1265 { 4U, SystemZ::R4D },
1266 { 5U, SystemZ::R5D },
1267 { 6U, SystemZ::R6D },
1268 { 7U, SystemZ::R7D },
1269 { 8U, SystemZ::R8D },
1270 { 9U, SystemZ::R9D },
1271 { 10U, SystemZ::R10D },
1272 { 11U, SystemZ::R11D },
1273 { 12U, SystemZ::R12D },
1274 { 13U, SystemZ::R13D },
1275 { 14U, SystemZ::R14D },
1276 { 15U, SystemZ::R15D },
1277 { 16U, SystemZ::F0D },
1278 { 17U, SystemZ::F2D },
1279 { 18U, SystemZ::F4D },
1280 { 19U, SystemZ::F6D },
1281 { 20U, SystemZ::F1D },
1282 { 21U, SystemZ::F3D },
1283 { 22U, SystemZ::F5D },
1284 { 23U, SystemZ::F7D },
1285 { 24U, SystemZ::F8D },
1286 { 25U, SystemZ::F10D },
1287 { 26U, SystemZ::F12D },
1288 { 27U, SystemZ::F14D },
1289 { 28U, SystemZ::F9D },
1290 { 29U, SystemZ::F11D },
1291 { 30U, SystemZ::F13D },
1292 { 31U, SystemZ::F15D },
1293 { 32U, SystemZ::C0 },
1294 { 33U, SystemZ::C1 },
1295 { 34U, SystemZ::C2 },
1296 { 35U, SystemZ::C3 },
1297 { 36U, SystemZ::C4 },
1298 { 37U, SystemZ::C5 },
1299 { 38U, SystemZ::C6 },
1300 { 39U, SystemZ::C7 },
1301 { 40U, SystemZ::C8 },
1302 { 41U, SystemZ::C9 },
1303 { 42U, SystemZ::C10 },
1304 { 43U, SystemZ::C11 },
1305 { 44U, SystemZ::C12 },
1306 { 45U, SystemZ::C13 },
1307 { 46U, SystemZ::C14 },
1308 { 47U, SystemZ::C15 },
1309 { 48U, SystemZ::A0 },
1310 { 49U, SystemZ::A1 },
1311 { 50U, SystemZ::A2 },
1312 { 51U, SystemZ::A3 },
1313 { 52U, SystemZ::A4 },
1314 { 53U, SystemZ::A5 },
1315 { 54U, SystemZ::A6 },
1316 { 55U, SystemZ::A7 },
1317 { 56U, SystemZ::A8 },
1318 { 57U, SystemZ::A9 },
1319 { 58U, SystemZ::A10 },
1320 { 59U, SystemZ::A11 },
1321 { 60U, SystemZ::A12 },
1322 { 61U, SystemZ::A13 },
1323 { 62U, SystemZ::A14 },
1324 { 63U, SystemZ::A15 },
1325 { 68U, SystemZ::F16D },
1326 { 69U, SystemZ::F18D },
1327 { 70U, SystemZ::F20D },
1328 { 71U, SystemZ::F22D },
1329 { 72U, SystemZ::F17D },
1330 { 73U, SystemZ::F19D },
1331 { 74U, SystemZ::F21D },
1332 { 75U, SystemZ::F23D },
1333 { 76U, SystemZ::F24D },
1334 { 77U, SystemZ::F26D },
1335 { 78U, SystemZ::F28D },
1336 { 79U, SystemZ::F30D },
1337 { 80U, SystemZ::F25D },
1338 { 81U, SystemZ::F27D },
1339 { 82U, SystemZ::F29D },
1340 { 83U, SystemZ::F31D },
1341};
1342extern const unsigned SystemZDwarfFlavour0Dwarf2LSize = std::size(SystemZDwarfFlavour0Dwarf2L);
1343
1344extern const MCRegisterInfo::DwarfLLVMRegPair SystemZEHFlavour0Dwarf2L[] = {
1345 { 0U, SystemZ::R0D },
1346 { 1U, SystemZ::R1D },
1347 { 2U, SystemZ::R2D },
1348 { 3U, SystemZ::R3D },
1349 { 4U, SystemZ::R4D },
1350 { 5U, SystemZ::R5D },
1351 { 6U, SystemZ::R6D },
1352 { 7U, SystemZ::R7D },
1353 { 8U, SystemZ::R8D },
1354 { 9U, SystemZ::R9D },
1355 { 10U, SystemZ::R10D },
1356 { 11U, SystemZ::R11D },
1357 { 12U, SystemZ::R12D },
1358 { 13U, SystemZ::R13D },
1359 { 14U, SystemZ::R14D },
1360 { 15U, SystemZ::R15D },
1361 { 16U, SystemZ::F0D },
1362 { 17U, SystemZ::F2D },
1363 { 18U, SystemZ::F4D },
1364 { 19U, SystemZ::F6D },
1365 { 20U, SystemZ::F1D },
1366 { 21U, SystemZ::F3D },
1367 { 22U, SystemZ::F5D },
1368 { 23U, SystemZ::F7D },
1369 { 24U, SystemZ::F8D },
1370 { 25U, SystemZ::F10D },
1371 { 26U, SystemZ::F12D },
1372 { 27U, SystemZ::F14D },
1373 { 28U, SystemZ::F9D },
1374 { 29U, SystemZ::F11D },
1375 { 30U, SystemZ::F13D },
1376 { 31U, SystemZ::F15D },
1377 { 32U, SystemZ::C0 },
1378 { 33U, SystemZ::C1 },
1379 { 34U, SystemZ::C2 },
1380 { 35U, SystemZ::C3 },
1381 { 36U, SystemZ::C4 },
1382 { 37U, SystemZ::C5 },
1383 { 38U, SystemZ::C6 },
1384 { 39U, SystemZ::C7 },
1385 { 40U, SystemZ::C8 },
1386 { 41U, SystemZ::C9 },
1387 { 42U, SystemZ::C10 },
1388 { 43U, SystemZ::C11 },
1389 { 44U, SystemZ::C12 },
1390 { 45U, SystemZ::C13 },
1391 { 46U, SystemZ::C14 },
1392 { 47U, SystemZ::C15 },
1393 { 48U, SystemZ::A0 },
1394 { 49U, SystemZ::A1 },
1395 { 50U, SystemZ::A2 },
1396 { 51U, SystemZ::A3 },
1397 { 52U, SystemZ::A4 },
1398 { 53U, SystemZ::A5 },
1399 { 54U, SystemZ::A6 },
1400 { 55U, SystemZ::A7 },
1401 { 56U, SystemZ::A8 },
1402 { 57U, SystemZ::A9 },
1403 { 58U, SystemZ::A10 },
1404 { 59U, SystemZ::A11 },
1405 { 60U, SystemZ::A12 },
1406 { 61U, SystemZ::A13 },
1407 { 62U, SystemZ::A14 },
1408 { 63U, SystemZ::A15 },
1409 { 68U, SystemZ::F16D },
1410 { 69U, SystemZ::F18D },
1411 { 70U, SystemZ::F20D },
1412 { 71U, SystemZ::F22D },
1413 { 72U, SystemZ::F17D },
1414 { 73U, SystemZ::F19D },
1415 { 74U, SystemZ::F21D },
1416 { 75U, SystemZ::F23D },
1417 { 76U, SystemZ::F24D },
1418 { 77U, SystemZ::F26D },
1419 { 78U, SystemZ::F28D },
1420 { 79U, SystemZ::F30D },
1421 { 80U, SystemZ::F25D },
1422 { 81U, SystemZ::F27D },
1423 { 82U, SystemZ::F29D },
1424 { 83U, SystemZ::F31D },
1425};
1426extern const unsigned SystemZEHFlavour0Dwarf2LSize = std::size(SystemZEHFlavour0Dwarf2L);
1427
1428extern const MCRegisterInfo::DwarfLLVMRegPair SystemZDwarfFlavour0L2Dwarf[] = {
1429 { SystemZ::A0, 48U },
1430 { SystemZ::A1, 49U },
1431 { SystemZ::A2, 50U },
1432 { SystemZ::A3, 51U },
1433 { SystemZ::A4, 52U },
1434 { SystemZ::A5, 53U },
1435 { SystemZ::A6, 54U },
1436 { SystemZ::A7, 55U },
1437 { SystemZ::A8, 56U },
1438 { SystemZ::A9, 57U },
1439 { SystemZ::A10, 58U },
1440 { SystemZ::A11, 59U },
1441 { SystemZ::A12, 60U },
1442 { SystemZ::A13, 61U },
1443 { SystemZ::A14, 62U },
1444 { SystemZ::A15, 63U },
1445 { SystemZ::C0, 32U },
1446 { SystemZ::C1, 33U },
1447 { SystemZ::C2, 34U },
1448 { SystemZ::C3, 35U },
1449 { SystemZ::C4, 36U },
1450 { SystemZ::C5, 37U },
1451 { SystemZ::C6, 38U },
1452 { SystemZ::C7, 39U },
1453 { SystemZ::C8, 40U },
1454 { SystemZ::C9, 41U },
1455 { SystemZ::C10, 42U },
1456 { SystemZ::C11, 43U },
1457 { SystemZ::C12, 44U },
1458 { SystemZ::C13, 45U },
1459 { SystemZ::C14, 46U },
1460 { SystemZ::C15, 47U },
1461 { SystemZ::V0, 16U },
1462 { SystemZ::V1, 20U },
1463 { SystemZ::V2, 17U },
1464 { SystemZ::V3, 21U },
1465 { SystemZ::V4, 18U },
1466 { SystemZ::V5, 22U },
1467 { SystemZ::V6, 19U },
1468 { SystemZ::V7, 23U },
1469 { SystemZ::V8, 24U },
1470 { SystemZ::V9, 28U },
1471 { SystemZ::V10, 25U },
1472 { SystemZ::V11, 29U },
1473 { SystemZ::V12, 26U },
1474 { SystemZ::V13, 30U },
1475 { SystemZ::V14, 27U },
1476 { SystemZ::V15, 31U },
1477 { SystemZ::V16, 68U },
1478 { SystemZ::V17, 72U },
1479 { SystemZ::V18, 69U },
1480 { SystemZ::V19, 73U },
1481 { SystemZ::V20, 70U },
1482 { SystemZ::V21, 74U },
1483 { SystemZ::V22, 71U },
1484 { SystemZ::V23, 75U },
1485 { SystemZ::V24, 76U },
1486 { SystemZ::V25, 80U },
1487 { SystemZ::V26, 77U },
1488 { SystemZ::V27, 81U },
1489 { SystemZ::V28, 78U },
1490 { SystemZ::V29, 82U },
1491 { SystemZ::V30, 79U },
1492 { SystemZ::V31, 83U },
1493 { SystemZ::F0D, 16U },
1494 { SystemZ::F1D, 20U },
1495 { SystemZ::F2D, 17U },
1496 { SystemZ::F3D, 21U },
1497 { SystemZ::F4D, 18U },
1498 { SystemZ::F5D, 22U },
1499 { SystemZ::F6D, 19U },
1500 { SystemZ::F7D, 23U },
1501 { SystemZ::F8D, 24U },
1502 { SystemZ::F9D, 28U },
1503 { SystemZ::F10D, 25U },
1504 { SystemZ::F11D, 29U },
1505 { SystemZ::F12D, 26U },
1506 { SystemZ::F13D, 30U },
1507 { SystemZ::F14D, 27U },
1508 { SystemZ::F15D, 31U },
1509 { SystemZ::F16D, 68U },
1510 { SystemZ::F17D, 72U },
1511 { SystemZ::F18D, 69U },
1512 { SystemZ::F19D, 73U },
1513 { SystemZ::F20D, 70U },
1514 { SystemZ::F21D, 74U },
1515 { SystemZ::F22D, 71U },
1516 { SystemZ::F23D, 75U },
1517 { SystemZ::F24D, 76U },
1518 { SystemZ::F25D, 80U },
1519 { SystemZ::F26D, 77U },
1520 { SystemZ::F27D, 81U },
1521 { SystemZ::F28D, 78U },
1522 { SystemZ::F29D, 82U },
1523 { SystemZ::F30D, 79U },
1524 { SystemZ::F31D, 83U },
1525 { SystemZ::R0D, 0U },
1526 { SystemZ::R1D, 1U },
1527 { SystemZ::R2D, 2U },
1528 { SystemZ::R3D, 3U },
1529 { SystemZ::R4D, 4U },
1530 { SystemZ::R5D, 5U },
1531 { SystemZ::R6D, 6U },
1532 { SystemZ::R7D, 7U },
1533 { SystemZ::R8D, 8U },
1534 { SystemZ::R9D, 9U },
1535 { SystemZ::R10D, 10U },
1536 { SystemZ::R11D, 11U },
1537 { SystemZ::R12D, 12U },
1538 { SystemZ::R13D, 13U },
1539 { SystemZ::R14D, 14U },
1540 { SystemZ::R15D, 15U },
1541};
1542extern const unsigned SystemZDwarfFlavour0L2DwarfSize = std::size(SystemZDwarfFlavour0L2Dwarf);
1543
1544extern const MCRegisterInfo::DwarfLLVMRegPair SystemZEHFlavour0L2Dwarf[] = {
1545 { SystemZ::A0, 48U },
1546 { SystemZ::A1, 49U },
1547 { SystemZ::A2, 50U },
1548 { SystemZ::A3, 51U },
1549 { SystemZ::A4, 52U },
1550 { SystemZ::A5, 53U },
1551 { SystemZ::A6, 54U },
1552 { SystemZ::A7, 55U },
1553 { SystemZ::A8, 56U },
1554 { SystemZ::A9, 57U },
1555 { SystemZ::A10, 58U },
1556 { SystemZ::A11, 59U },
1557 { SystemZ::A12, 60U },
1558 { SystemZ::A13, 61U },
1559 { SystemZ::A14, 62U },
1560 { SystemZ::A15, 63U },
1561 { SystemZ::C0, 32U },
1562 { SystemZ::C1, 33U },
1563 { SystemZ::C2, 34U },
1564 { SystemZ::C3, 35U },
1565 { SystemZ::C4, 36U },
1566 { SystemZ::C5, 37U },
1567 { SystemZ::C6, 38U },
1568 { SystemZ::C7, 39U },
1569 { SystemZ::C8, 40U },
1570 { SystemZ::C9, 41U },
1571 { SystemZ::C10, 42U },
1572 { SystemZ::C11, 43U },
1573 { SystemZ::C12, 44U },
1574 { SystemZ::C13, 45U },
1575 { SystemZ::C14, 46U },
1576 { SystemZ::C15, 47U },
1577 { SystemZ::V0, 16U },
1578 { SystemZ::V1, 20U },
1579 { SystemZ::V2, 17U },
1580 { SystemZ::V3, 21U },
1581 { SystemZ::V4, 18U },
1582 { SystemZ::V5, 22U },
1583 { SystemZ::V6, 19U },
1584 { SystemZ::V7, 23U },
1585 { SystemZ::V8, 24U },
1586 { SystemZ::V9, 28U },
1587 { SystemZ::V10, 25U },
1588 { SystemZ::V11, 29U },
1589 { SystemZ::V12, 26U },
1590 { SystemZ::V13, 30U },
1591 { SystemZ::V14, 27U },
1592 { SystemZ::V15, 31U },
1593 { SystemZ::V16, 68U },
1594 { SystemZ::V17, 72U },
1595 { SystemZ::V18, 69U },
1596 { SystemZ::V19, 73U },
1597 { SystemZ::V20, 70U },
1598 { SystemZ::V21, 74U },
1599 { SystemZ::V22, 71U },
1600 { SystemZ::V23, 75U },
1601 { SystemZ::V24, 76U },
1602 { SystemZ::V25, 80U },
1603 { SystemZ::V26, 77U },
1604 { SystemZ::V27, 81U },
1605 { SystemZ::V28, 78U },
1606 { SystemZ::V29, 82U },
1607 { SystemZ::V30, 79U },
1608 { SystemZ::V31, 83U },
1609 { SystemZ::F0D, 16U },
1610 { SystemZ::F1D, 20U },
1611 { SystemZ::F2D, 17U },
1612 { SystemZ::F3D, 21U },
1613 { SystemZ::F4D, 18U },
1614 { SystemZ::F5D, 22U },
1615 { SystemZ::F6D, 19U },
1616 { SystemZ::F7D, 23U },
1617 { SystemZ::F8D, 24U },
1618 { SystemZ::F9D, 28U },
1619 { SystemZ::F10D, 25U },
1620 { SystemZ::F11D, 29U },
1621 { SystemZ::F12D, 26U },
1622 { SystemZ::F13D, 30U },
1623 { SystemZ::F14D, 27U },
1624 { SystemZ::F15D, 31U },
1625 { SystemZ::F16D, 68U },
1626 { SystemZ::F17D, 72U },
1627 { SystemZ::F18D, 69U },
1628 { SystemZ::F19D, 73U },
1629 { SystemZ::F20D, 70U },
1630 { SystemZ::F21D, 74U },
1631 { SystemZ::F22D, 71U },
1632 { SystemZ::F23D, 75U },
1633 { SystemZ::F24D, 76U },
1634 { SystemZ::F25D, 80U },
1635 { SystemZ::F26D, 77U },
1636 { SystemZ::F27D, 81U },
1637 { SystemZ::F28D, 78U },
1638 { SystemZ::F29D, 82U },
1639 { SystemZ::F30D, 79U },
1640 { SystemZ::F31D, 83U },
1641 { SystemZ::R0D, 0U },
1642 { SystemZ::R1D, 1U },
1643 { SystemZ::R2D, 2U },
1644 { SystemZ::R3D, 3U },
1645 { SystemZ::R4D, 4U },
1646 { SystemZ::R5D, 5U },
1647 { SystemZ::R6D, 6U },
1648 { SystemZ::R7D, 7U },
1649 { SystemZ::R8D, 8U },
1650 { SystemZ::R9D, 9U },
1651 { SystemZ::R10D, 10U },
1652 { SystemZ::R11D, 11U },
1653 { SystemZ::R12D, 12U },
1654 { SystemZ::R13D, 13U },
1655 { SystemZ::R14D, 14U },
1656 { SystemZ::R15D, 15U },
1657};
1658extern const unsigned SystemZEHFlavour0L2DwarfSize = std::size(SystemZEHFlavour0L2Dwarf);
1659
1660extern const uint16_t SystemZRegEncodingTable[] = {
1661 0,
1662 0,
1663 0,
1664 0,
1665 1,
1666 2,
1667 3,
1668 4,
1669 5,
1670 6,
1671 7,
1672 8,
1673 9,
1674 10,
1675 11,
1676 12,
1677 13,
1678 14,
1679 15,
1680 0,
1681 1,
1682 2,
1683 3,
1684 4,
1685 5,
1686 6,
1687 7,
1688 8,
1689 9,
1690 10,
1691 11,
1692 12,
1693 13,
1694 14,
1695 15,
1696 0,
1697 1,
1698 2,
1699 3,
1700 4,
1701 5,
1702 6,
1703 7,
1704 8,
1705 9,
1706 10,
1707 11,
1708 12,
1709 13,
1710 14,
1711 15,
1712 16,
1713 17,
1714 18,
1715 19,
1716 20,
1717 21,
1718 22,
1719 23,
1720 24,
1721 25,
1722 26,
1723 27,
1724 28,
1725 29,
1726 30,
1727 31,
1728 0,
1729 1,
1730 2,
1731 3,
1732 4,
1733 5,
1734 6,
1735 7,
1736 8,
1737 9,
1738 10,
1739 11,
1740 12,
1741 13,
1742 14,
1743 15,
1744 16,
1745 17,
1746 18,
1747 19,
1748 20,
1749 21,
1750 22,
1751 23,
1752 24,
1753 25,
1754 26,
1755 27,
1756 28,
1757 29,
1758 30,
1759 31,
1760 0,
1761 1,
1762 2,
1763 3,
1764 4,
1765 5,
1766 6,
1767 7,
1768 8,
1769 9,
1770 10,
1771 11,
1772 12,
1773 13,
1774 14,
1775 15,
1776 16,
1777 17,
1778 18,
1779 19,
1780 20,
1781 21,
1782 22,
1783 23,
1784 24,
1785 25,
1786 26,
1787 27,
1788 28,
1789 29,
1790 30,
1791 31,
1792 0,
1793 1,
1794 4,
1795 5,
1796 8,
1797 9,
1798 12,
1799 13,
1800 0,
1801 1,
1802 2,
1803 3,
1804 4,
1805 5,
1806 6,
1807 7,
1808 8,
1809 9,
1810 10,
1811 11,
1812 12,
1813 13,
1814 14,
1815 15,
1816 16,
1817 17,
1818 18,
1819 19,
1820 20,
1821 21,
1822 22,
1823 23,
1824 24,
1825 25,
1826 26,
1827 27,
1828 28,
1829 29,
1830 30,
1831 31,
1832 0,
1833 1,
1834 2,
1835 3,
1836 4,
1837 5,
1838 6,
1839 7,
1840 8,
1841 9,
1842 10,
1843 11,
1844 12,
1845 13,
1846 14,
1847 15,
1848 0,
1849 1,
1850 2,
1851 3,
1852 4,
1853 5,
1854 6,
1855 7,
1856 8,
1857 9,
1858 10,
1859 11,
1860 12,
1861 13,
1862 14,
1863 15,
1864 0,
1865 1,
1866 2,
1867 3,
1868 4,
1869 5,
1870 6,
1871 7,
1872 8,
1873 9,
1874 10,
1875 11,
1876 12,
1877 13,
1878 14,
1879 15,
1880 0,
1881 2,
1882 4,
1883 6,
1884 8,
1885 10,
1886 12,
1887 14,
1888};
1889static inline void InitSystemZMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
1890 RI->InitMCRegisterInfo(SystemZRegDesc, 227, RA, PC, SystemZMCRegisterClasses, 24, SystemZRegUnitRoots, 98, SystemZRegDiffLists, SystemZLaneMaskLists, SystemZRegStrings, SystemZRegClassStrings, SystemZSubRegIdxLists, 9,
1891SystemZRegEncodingTable);
1892
1893 switch (DwarfFlavour) {
1894 default:
1895 llvm_unreachable("Unknown DWARF flavour");
1896 case 0:
1897 RI->mapDwarfRegsToLLVMRegs(SystemZDwarfFlavour0Dwarf2L, SystemZDwarfFlavour0Dwarf2LSize, false);
1898 break;
1899 }
1900 switch (EHFlavour) {
1901 default:
1902 llvm_unreachable("Unknown DWARF flavour");
1903 case 0:
1904 RI->mapDwarfRegsToLLVMRegs(SystemZEHFlavour0Dwarf2L, SystemZEHFlavour0Dwarf2LSize, true);
1905 break;
1906 }
1907 switch (DwarfFlavour) {
1908 default:
1909 llvm_unreachable("Unknown DWARF flavour");
1910 case 0:
1911 RI->mapLLVMRegsToDwarfRegs(SystemZDwarfFlavour0L2Dwarf, SystemZDwarfFlavour0L2DwarfSize, false);
1912 break;
1913 }
1914 switch (EHFlavour) {
1915 default:
1916 llvm_unreachable("Unknown DWARF flavour");
1917 case 0:
1918 RI->mapLLVMRegsToDwarfRegs(SystemZEHFlavour0L2Dwarf, SystemZEHFlavour0L2DwarfSize, true);
1919 break;
1920 }
1921}
1922
1923} // end namespace llvm
1924
1925#endif // GET_REGINFO_MC_DESC
1926
1927/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
1928|* *|
1929|* Register Information Header Fragment *|
1930|* *|
1931|* Automatically generated file, do not edit! *|
1932|* *|
1933\*===----------------------------------------------------------------------===*/
1934
1935
1936#ifdef GET_REGINFO_HEADER
1937#undef GET_REGINFO_HEADER
1938
1939#include "llvm/CodeGen/TargetRegisterInfo.h"
1940
1941namespace llvm {
1942
1943class SystemZFrameLowering;
1944
1945struct SystemZGenRegisterInfo : public TargetRegisterInfo {
1946 explicit SystemZGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
1947 unsigned PC = 0, unsigned HwMode = 0);
1948 unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
1949 unsigned reverseComposeSubRegIndicesImpl(unsigned, unsigned) const override;
1950 LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
1951 LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
1952 const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass *, unsigned) const override;
1953 const TargetRegisterClass *getSubRegisterClass(const TargetRegisterClass *, unsigned) const override;
1954 const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
1955 unsigned getRegUnitWeight(unsigned RegUnit) const override;
1956 unsigned getNumRegPressureSets() const override;
1957 const char *getRegPressureSetName(unsigned Idx) const override;
1958 unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
1959 const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
1960 const int *getRegUnitPressureSets(unsigned RegUnit) const override;
1961 ArrayRef<const char *> getRegMaskNames() const override;
1962 ArrayRef<const uint32_t *> getRegMasks() const override;
1963 bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override;
1964 bool isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const override;
1965 bool isFixedRegister(const MachineFunction &, MCRegister) const override;
1966 bool isArgumentRegister(const MachineFunction &, MCRegister) const override;
1967 bool isConstantPhysReg(MCRegister PhysReg) const override final;
1968 /// Devirtualized TargetFrameLowering.
1969 static const SystemZFrameLowering *getFrameLowering(
1970 const MachineFunction &MF);
1971};
1972
1973namespace SystemZ { // Register classes
1974 extern const TargetRegisterClass VR16BitRegClass;
1975 extern const TargetRegisterClass FP16BitRegClass;
1976 extern const TargetRegisterClass GRX32BitRegClass;
1977 extern const TargetRegisterClass VR32BitRegClass;
1978 extern const TargetRegisterClass AR32BitRegClass;
1979 extern const TargetRegisterClass FP32BitRegClass;
1980 extern const TargetRegisterClass GR32BitRegClass;
1981 extern const TargetRegisterClass GRH32BitRegClass;
1982 extern const TargetRegisterClass ADDR32BitRegClass;
1983 extern const TargetRegisterClass CCRRegClass;
1984 extern const TargetRegisterClass FPCRegsRegClass;
1985 extern const TargetRegisterClass AnyRegBitRegClass;
1986 extern const TargetRegisterClass AnyRegBit_with_subreg_h16RegClass;
1987 extern const TargetRegisterClass VR64BitRegClass;
1988 extern const TargetRegisterClass AnyRegBit_with_subreg_h64RegClass;
1989 extern const TargetRegisterClass CR64BitRegClass;
1990 extern const TargetRegisterClass FP64BitRegClass;
1991 extern const TargetRegisterClass GR64BitRegClass;
1992 extern const TargetRegisterClass ADDR64BitRegClass;
1993 extern const TargetRegisterClass VR128BitRegClass;
1994 extern const TargetRegisterClass VF128BitRegClass;
1995 extern const TargetRegisterClass FP128BitRegClass;
1996 extern const TargetRegisterClass GR128BitRegClass;
1997 extern const TargetRegisterClass ADDR128BitRegClass;
1998} // end namespace SystemZ
1999
2000} // end namespace llvm
2001
2002#endif // GET_REGINFO_HEADER
2003
2004/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2005|* *|
2006|* Target Register and Register Classes Information *|
2007|* *|
2008|* Automatically generated file, do not edit! *|
2009|* *|
2010\*===----------------------------------------------------------------------===*/
2011
2012
2013#ifdef GET_REGINFO_TARGET_DESC
2014#undef GET_REGINFO_TARGET_DESC
2015
2016namespace llvm {
2017
2018extern const MCRegisterClass SystemZMCRegisterClasses[];
2019
2020static const MVT::SimpleValueType VTLists[] = {
2021 /* 0 */ MVT::i32, MVT::Other,
2022 /* 2 */ MVT::i64, MVT::Other,
2023 /* 4 */ MVT::f16, MVT::Other,
2024 /* 6 */ MVT::f32, MVT::Other,
2025 /* 8 */ MVT::f64, MVT::Other,
2026 /* 10 */ MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::i128, MVT::v4f32, MVT::v2f64, MVT::f128, MVT::Other,
2027 /* 19 */ MVT::f32, MVT::v4i8, MVT::v2i16, MVT::Other,
2028 /* 23 */ MVT::i64, MVT::f64, MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v2f32, MVT::Other,
2029 /* 30 */ MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v4f32, MVT::v2f64, MVT::Other,
2030 /* 37 */ MVT::Untyped, MVT::Other,
2031};
2032
2033static const char *SubRegIndexNameTable[] = { "subreg_h16", "subreg_h32", "subreg_h64", "subreg_l32", "subreg_l64", "subreg_lh32", "subreg_ll32", "subreg_lh32_then_subreg_h16", "" };
2034
2035static const TargetRegisterInfo::SubRegCoveredBits SubRegIdxRangeTable[] = {
2036 { 65535, 65535 },
2037 { 16, 16 }, // subreg_h16
2038 { 32, 32 }, // subreg_h32
2039 { 64, 64 }, // subreg_h64
2040 { 0, 32 }, // subreg_l32
2041 { 0, 64 }, // subreg_l64
2042 { 32, 32 }, // subreg_lh32
2043 { 0, 32 }, // subreg_ll32
2044 { 48, 16 }, // subreg_lh32_then_subreg_h16
2045 { 65535, 65535 },
2046 { 16, 16 }, // subreg_h16
2047 { 32, 32 }, // subreg_h32
2048 { 64, 64 }, // subreg_h64
2049 { 0, 32 }, // subreg_l32
2050 { 0, 64 }, // subreg_l64
2051 { 32, 32 }, // subreg_lh32
2052 { 0, 32 }, // subreg_ll32
2053 { 48, 16 }, // subreg_lh32_then_subreg_h16
2054};
2055
2056
2057static const LaneBitmask SubRegIndexLaneMaskTable[] = {
2058 LaneBitmask::getAll(),
2059 LaneBitmask(0x0000000000000001), // subreg_h16
2060 LaneBitmask(0x0000000000000001), // subreg_h32
2061 LaneBitmask(0x0000000000000003), // subreg_h64
2062 LaneBitmask(0x0000000000000002), // subreg_l32
2063 LaneBitmask(0x000000000000000C), // subreg_l64
2064 LaneBitmask(0x0000000000000008), // subreg_lh32
2065 LaneBitmask(0x0000000000000004), // subreg_ll32
2066 LaneBitmask(0x0000000000000008), // subreg_lh32_then_subreg_h16
2067 };
2068
2069
2070
2071static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
2072 // Mode = 0 (Default)
2073 { 16, 16, 16, /*VTLists+*/4 }, // VR16Bit
2074 { 16, 16, 16, /*VTLists+*/4 }, // FP16Bit
2075 { 32, 32, 32, /*VTLists+*/0 }, // GRX32Bit
2076 { 32, 32, 32, /*VTLists+*/19 }, // VR32Bit
2077 { 32, 32, 32, /*VTLists+*/0 }, // AR32Bit
2078 { 32, 32, 32, /*VTLists+*/6 }, // FP32Bit
2079 { 32, 32, 32, /*VTLists+*/0 }, // GR32Bit
2080 { 32, 32, 32, /*VTLists+*/0 }, // GRH32Bit
2081 { 32, 32, 32, /*VTLists+*/0 }, // ADDR32Bit
2082 { 32, 32, 32, /*VTLists+*/0 }, // CCR
2083 { 32, 32, 32, /*VTLists+*/0 }, // FPCRegs
2084 { 64, 64, 64, /*VTLists+*/23 }, // AnyRegBit
2085 { 64, 64, 64, /*VTLists+*/23 }, // AnyRegBit_with_subreg_h16
2086 { 64, 64, 64, /*VTLists+*/24 }, // VR64Bit
2087 { 64, 64, 64, /*VTLists+*/23 }, // AnyRegBit_with_subreg_h64
2088 { 64, 64, 64, /*VTLists+*/2 }, // CR64Bit
2089 { 64, 64, 64, /*VTLists+*/8 }, // FP64Bit
2090 { 64, 64, 64, /*VTLists+*/2 }, // GR64Bit
2091 { 64, 64, 64, /*VTLists+*/2 }, // ADDR64Bit
2092 { 128, 128, 128, /*VTLists+*/10 }, // VR128Bit
2093 { 128, 128, 128, /*VTLists+*/30 }, // VF128Bit
2094 { 128, 128, 128, /*VTLists+*/17 }, // FP128Bit
2095 { 128, 128, 128, /*VTLists+*/37 }, // GR128Bit
2096 { 128, 128, 128, /*VTLists+*/37 }, // ADDR128Bit
2097 // Mode = 1 (NoVecHwMode)
2098 { 16, 16, 16, /*VTLists+*/4 }, // VR16Bit
2099 { 16, 32, 32, /*VTLists+*/4 }, // FP16Bit
2100 { 32, 32, 32, /*VTLists+*/0 }, // GRX32Bit
2101 { 32, 32, 32, /*VTLists+*/19 }, // VR32Bit
2102 { 32, 32, 32, /*VTLists+*/0 }, // AR32Bit
2103 { 32, 32, 32, /*VTLists+*/6 }, // FP32Bit
2104 { 32, 32, 32, /*VTLists+*/0 }, // GR32Bit
2105 { 32, 32, 32, /*VTLists+*/0 }, // GRH32Bit
2106 { 32, 32, 32, /*VTLists+*/0 }, // ADDR32Bit
2107 { 32, 32, 32, /*VTLists+*/0 }, // CCR
2108 { 32, 32, 32, /*VTLists+*/0 }, // FPCRegs
2109 { 64, 64, 64, /*VTLists+*/23 }, // AnyRegBit
2110 { 64, 64, 64, /*VTLists+*/23 }, // AnyRegBit_with_subreg_h16
2111 { 64, 64, 64, /*VTLists+*/24 }, // VR64Bit
2112 { 64, 64, 64, /*VTLists+*/23 }, // AnyRegBit_with_subreg_h64
2113 { 64, 64, 64, /*VTLists+*/2 }, // CR64Bit
2114 { 64, 64, 64, /*VTLists+*/8 }, // FP64Bit
2115 { 64, 64, 64, /*VTLists+*/2 }, // GR64Bit
2116 { 64, 64, 64, /*VTLists+*/2 }, // ADDR64Bit
2117 { 128, 128, 128, /*VTLists+*/10 }, // VR128Bit
2118 { 128, 128, 128, /*VTLists+*/30 }, // VF128Bit
2119 { 128, 128, 128, /*VTLists+*/17 }, // FP128Bit
2120 { 128, 128, 128, /*VTLists+*/37 }, // GR128Bit
2121 { 128, 128, 128, /*VTLists+*/37 }, // ADDR128Bit
2122};
2123static const uint32_t VR16BitSubClassMask[] = {
2124 0x00000003,
2125 0x00397028, // subreg_h16
2126 0x00200000, // subreg_lh32_then_subreg_h16
2127};
2128
2129static const uint32_t FP16BitSubClassMask[] = {
2130 0x00000002,
2131 0x00315020, // subreg_h16
2132 0x00200000, // subreg_lh32_then_subreg_h16
2133};
2134
2135static const uint32_t GRX32BitSubClassMask[] = {
2136 0x000001c4,
2137 0x00c60000, // subreg_h32
2138 0x00c60000, // subreg_l32
2139 0x00c00000, // subreg_lh32
2140 0x00c00000, // subreg_ll32
2141};
2142
2143static const uint32_t VR32BitSubClassMask[] = {
2144 0x00000028,
2145 0x00397000, // subreg_h32
2146 0x00200000, // subreg_lh32
2147};
2148
2149static const uint32_t AR32BitSubClassMask[] = {
2150 0x00000010,
2151};
2152
2153static const uint32_t FP32BitSubClassMask[] = {
2154 0x00000020,
2155 0x00315000, // subreg_h32
2156 0x00200000, // subreg_lh32
2157};
2158
2159static const uint32_t GR32BitSubClassMask[] = {
2160 0x00000140,
2161 0x00c60000, // subreg_l32
2162 0x00c00000, // subreg_ll32
2163};
2164
2165static const uint32_t GRH32BitSubClassMask[] = {
2166 0x00000080,
2167 0x00c60000, // subreg_h32
2168 0x00c00000, // subreg_lh32
2169};
2170
2171static const uint32_t ADDR32BitSubClassMask[] = {
2172 0x00000100,
2173 0x00840000, // subreg_l32
2174 0x00c00000, // subreg_ll32
2175};
2176
2177static const uint32_t CCRSubClassMask[] = {
2178 0x00000200,
2179};
2180
2181static const uint32_t FPCRegsSubClassMask[] = {
2182 0x00000400,
2183};
2184
2185static const uint32_t AnyRegBitSubClassMask[] = {
2186 0x00175800,
2187 0x00f04000, // subreg_h64
2188 0x00e00000, // subreg_l64
2189};
2190
2191static const uint32_t AnyRegBit_with_subreg_h16SubClassMask[] = {
2192 0x00115000,
2193 0x00304000, // subreg_h64
2194 0x00200000, // subreg_l64
2195};
2196
2197static const uint32_t VR64BitSubClassMask[] = {
2198 0x00012000,
2199 0x00384000, // subreg_h64
2200 0x00200000, // subreg_l64
2201};
2202
2203static const uint32_t AnyRegBit_with_subreg_h64SubClassMask[] = {
2204 0x00104000,
2205};
2206
2207static const uint32_t CR64BitSubClassMask[] = {
2208 0x00008000,
2209};
2210
2211static const uint32_t FP64BitSubClassMask[] = {
2212 0x00010000,
2213 0x00304000, // subreg_h64
2214 0x00200000, // subreg_l64
2215};
2216
2217static const uint32_t GR64BitSubClassMask[] = {
2218 0x00060000,
2219 0x00c00000, // subreg_h64
2220 0x00c00000, // subreg_l64
2221};
2222
2223static const uint32_t ADDR64BitSubClassMask[] = {
2224 0x00040000,
2225 0x00800000, // subreg_h64
2226 0x00c00000, // subreg_l64
2227};
2228
2229static const uint32_t VR128BitSubClassMask[] = {
2230 0x00180000,
2231};
2232
2233static const uint32_t VF128BitSubClassMask[] = {
2234 0x00100000,
2235};
2236
2237static const uint32_t FP128BitSubClassMask[] = {
2238 0x00200000,
2239};
2240
2241static const uint32_t GR128BitSubClassMask[] = {
2242 0x00c00000,
2243};
2244
2245static const uint32_t ADDR128BitSubClassMask[] = {
2246 0x00800000,
2247};
2248
2249static const uint16_t SuperRegIdxSeqs[] = {
2250 /* 0 */ 3, 5, 0,
2251 /* 3 */ 2, 6, 0,
2252 /* 6 */ 4, 7, 0,
2253 /* 9 */ 2, 4, 6, 7, 0,
2254 /* 14 */ 1, 8, 0,
2255};
2256
2257static unsigned const FP16BitSuperclasses[] = {
2258 SystemZ::VR16BitRegClassID,
2259};
2260
2261static unsigned const FP32BitSuperclasses[] = {
2262 SystemZ::VR32BitRegClassID,
2263};
2264
2265static unsigned const GR32BitSuperclasses[] = {
2266 SystemZ::GRX32BitRegClassID,
2267};
2268
2269static unsigned const GRH32BitSuperclasses[] = {
2270 SystemZ::GRX32BitRegClassID,
2271};
2272
2273static unsigned const ADDR32BitSuperclasses[] = {
2274 SystemZ::GRX32BitRegClassID,
2275 SystemZ::GR32BitRegClassID,
2276};
2277
2278static unsigned const AnyRegBit_with_subreg_h16Superclasses[] = {
2279 SystemZ::AnyRegBitRegClassID,
2280};
2281
2282static unsigned const AnyRegBit_with_subreg_h64Superclasses[] = {
2283 SystemZ::AnyRegBitRegClassID,
2284 SystemZ::AnyRegBit_with_subreg_h16RegClassID,
2285};
2286
2287static unsigned const FP64BitSuperclasses[] = {
2288 SystemZ::AnyRegBitRegClassID,
2289 SystemZ::AnyRegBit_with_subreg_h16RegClassID,
2290 SystemZ::VR64BitRegClassID,
2291};
2292
2293static unsigned const GR64BitSuperclasses[] = {
2294 SystemZ::AnyRegBitRegClassID,
2295};
2296
2297static unsigned const ADDR64BitSuperclasses[] = {
2298 SystemZ::AnyRegBitRegClassID,
2299 SystemZ::GR64BitRegClassID,
2300};
2301
2302static unsigned const VF128BitSuperclasses[] = {
2303 SystemZ::AnyRegBitRegClassID,
2304 SystemZ::AnyRegBit_with_subreg_h16RegClassID,
2305 SystemZ::AnyRegBit_with_subreg_h64RegClassID,
2306 SystemZ::VR128BitRegClassID,
2307};
2308
2309static unsigned const ADDR128BitSuperclasses[] = {
2310 SystemZ::GR128BitRegClassID,
2311};
2312
2313
2314static inline unsigned VR16BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
2315 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
2316 return S.isTargetXPLINK64();
2317 }
2318
2319static ArrayRef<MCPhysReg> VR16BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
2320 static const MCPhysReg AltOrder1[] = { SystemZ::F0H, SystemZ::F1H, SystemZ::F2H, SystemZ::F3H, SystemZ::F4H, SystemZ::F5H, SystemZ::F6H, SystemZ::F7H, SystemZ::F16H, SystemZ::F17H, SystemZ::F18H, SystemZ::F19H, SystemZ::F20H, SystemZ::F21H, SystemZ::F22H, SystemZ::F23H, SystemZ::F24H, SystemZ::F25H, SystemZ::F26H, SystemZ::F27H, SystemZ::F28H, SystemZ::F29H, SystemZ::F30H, SystemZ::F31H, SystemZ::F8H, SystemZ::F9H, SystemZ::F10H, SystemZ::F11H, SystemZ::F12H, SystemZ::F13H, SystemZ::F14H, SystemZ::F15H };
2321 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::VR16BitRegClassID];
2322 const ArrayRef<MCPhysReg> Order[] = {
2323 ArrayRef(MCR.begin(), MCR.getNumRegs()),
2324 ArrayRef(AltOrder1)
2325 };
2326 const unsigned Select = VR16BitAltOrderSelect(MF, Rev);
2327 assert(Select < 2);
2328 return Order[Select];
2329}
2330
2331static inline unsigned FP16BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
2332 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
2333 return S.isTargetXPLINK64();
2334 }
2335
2336static ArrayRef<MCPhysReg> FP16BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
2337 static const MCPhysReg AltOrder1[] = { SystemZ::F0H, SystemZ::F1H, SystemZ::F2H, SystemZ::F3H, SystemZ::F4H, SystemZ::F5H, SystemZ::F6H, SystemZ::F7H, SystemZ::F8H, SystemZ::F9H, SystemZ::F10H, SystemZ::F11H, SystemZ::F12H, SystemZ::F13H, SystemZ::F14H, SystemZ::F15H };
2338 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::FP16BitRegClassID];
2339 const ArrayRef<MCPhysReg> Order[] = {
2340 ArrayRef(MCR.begin(), MCR.getNumRegs()),
2341 ArrayRef(AltOrder1)
2342 };
2343 const unsigned Select = FP16BitAltOrderSelect(MF, Rev);
2344 assert(Select < 2);
2345 return Order[Select];
2346}
2347
2348static inline unsigned GRX32BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
2349 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
2350 return S.isTargetXPLINK64();
2351 }
2352
2353static ArrayRef<MCPhysReg> GRX32BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
2354 static const MCPhysReg AltOrder1[] = { SystemZ::R0L, SystemZ::R1L, SystemZ::R2L, SystemZ::R3L, SystemZ::R0H, SystemZ::R1H, SystemZ::R2H, SystemZ::R3H, SystemZ::R4L, SystemZ::R4H, SystemZ::R5L, SystemZ::R5H, SystemZ::R6L, SystemZ::R6H, SystemZ::R7L, SystemZ::R7H, SystemZ::R8L, SystemZ::R8H, SystemZ::R9L, SystemZ::R9H, SystemZ::R10L, SystemZ::R10H, SystemZ::R11L, SystemZ::R11H, SystemZ::R12L, SystemZ::R12H, SystemZ::R13L, SystemZ::R13H, SystemZ::R14L, SystemZ::R14H, SystemZ::R15L, SystemZ::R15H };
2355 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::GRX32BitRegClassID];
2356 const ArrayRef<MCPhysReg> Order[] = {
2357 ArrayRef(MCR.begin(), MCR.getNumRegs()),
2358 ArrayRef(AltOrder1)
2359 };
2360 const unsigned Select = GRX32BitAltOrderSelect(MF, Rev);
2361 assert(Select < 2);
2362 return Order[Select];
2363}
2364
2365static inline unsigned VR32BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
2366 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
2367 return S.isTargetXPLINK64();
2368 }
2369
2370static ArrayRef<MCPhysReg> VR32BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
2371 static const MCPhysReg AltOrder1[] = { SystemZ::F0S, SystemZ::F1S, SystemZ::F2S, SystemZ::F3S, SystemZ::F4S, SystemZ::F5S, SystemZ::F6S, SystemZ::F7S, SystemZ::F16S, SystemZ::F17S, SystemZ::F18S, SystemZ::F19S, SystemZ::F20S, SystemZ::F21S, SystemZ::F22S, SystemZ::F23S, SystemZ::F24S, SystemZ::F25S, SystemZ::F26S, SystemZ::F27S, SystemZ::F28S, SystemZ::F29S, SystemZ::F30S, SystemZ::F31S, SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S, SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S };
2372 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::VR32BitRegClassID];
2373 const ArrayRef<MCPhysReg> Order[] = {
2374 ArrayRef(MCR.begin(), MCR.getNumRegs()),
2375 ArrayRef(AltOrder1)
2376 };
2377 const unsigned Select = VR32BitAltOrderSelect(MF, Rev);
2378 assert(Select < 2);
2379 return Order[Select];
2380}
2381
2382static inline unsigned AR32BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
2383 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
2384 return S.isTargetXPLINK64();
2385 }
2386
2387static ArrayRef<MCPhysReg> AR32BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
2388 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::AR32BitRegClassID];
2389 const ArrayRef<MCPhysReg> Order[] = {
2390 ArrayRef(MCR.begin(), MCR.getNumRegs())
2391 };
2392 const unsigned Select = AR32BitAltOrderSelect(MF, Rev);
2393 assert(Select < 1);
2394 return Order[Select];
2395}
2396
2397static inline unsigned FP32BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
2398 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
2399 return S.isTargetXPLINK64();
2400 }
2401
2402static ArrayRef<MCPhysReg> FP32BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
2403 static const MCPhysReg AltOrder1[] = { SystemZ::F0S, SystemZ::F1S, SystemZ::F2S, SystemZ::F3S, SystemZ::F4S, SystemZ::F5S, SystemZ::F6S, SystemZ::F7S, SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S, SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S };
2404 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::FP32BitRegClassID];
2405 const ArrayRef<MCPhysReg> Order[] = {
2406 ArrayRef(MCR.begin(), MCR.getNumRegs()),
2407 ArrayRef(AltOrder1)
2408 };
2409 const unsigned Select = FP32BitAltOrderSelect(MF, Rev);
2410 assert(Select < 2);
2411 return Order[Select];
2412}
2413
2414static inline unsigned GR32BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
2415 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
2416 return S.isTargetXPLINK64();
2417 }
2418
2419static ArrayRef<MCPhysReg> GR32BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
2420 static const MCPhysReg AltOrder1[] = { SystemZ::R0L, SystemZ::R1L, SystemZ::R2L, SystemZ::R3L, SystemZ::R4L, SystemZ::R5L, SystemZ::R6L, SystemZ::R7L, SystemZ::R8L, SystemZ::R9L, SystemZ::R10L, SystemZ::R11L, SystemZ::R12L, SystemZ::R13L, SystemZ::R14L, SystemZ::R15L };
2421 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::GR32BitRegClassID];
2422 const ArrayRef<MCPhysReg> Order[] = {
2423 ArrayRef(MCR.begin(), MCR.getNumRegs()),
2424 ArrayRef(AltOrder1)
2425 };
2426 const unsigned Select = GR32BitAltOrderSelect(MF, Rev);
2427 assert(Select < 2);
2428 return Order[Select];
2429}
2430
2431static inline unsigned GRH32BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
2432 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
2433 return S.isTargetXPLINK64();
2434 }
2435
2436static ArrayRef<MCPhysReg> GRH32BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
2437 static const MCPhysReg AltOrder1[] = { SystemZ::R0H, SystemZ::R1H, SystemZ::R2H, SystemZ::R3H, SystemZ::R4H, SystemZ::R5H, SystemZ::R6H, SystemZ::R7H, SystemZ::R8H, SystemZ::R9H, SystemZ::R10H, SystemZ::R11H, SystemZ::R12H, SystemZ::R13H, SystemZ::R14H, SystemZ::R15H };
2438 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::GRH32BitRegClassID];
2439 const ArrayRef<MCPhysReg> Order[] = {
2440 ArrayRef(MCR.begin(), MCR.getNumRegs()),
2441 ArrayRef(AltOrder1)
2442 };
2443 const unsigned Select = GRH32BitAltOrderSelect(MF, Rev);
2444 assert(Select < 2);
2445 return Order[Select];
2446}
2447
2448static inline unsigned ADDR32BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
2449 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
2450 return S.isTargetXPLINK64();
2451 }
2452
2453static ArrayRef<MCPhysReg> ADDR32BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
2454 static const MCPhysReg AltOrder1[] = { SystemZ::R1L, SystemZ::R2L, SystemZ::R3L, SystemZ::R4L, SystemZ::R5L, SystemZ::R6L, SystemZ::R7L, SystemZ::R8L, SystemZ::R9L, SystemZ::R10L, SystemZ::R11L, SystemZ::R12L, SystemZ::R13L, SystemZ::R14L, SystemZ::R15L };
2455 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::ADDR32BitRegClassID];
2456 const ArrayRef<MCPhysReg> Order[] = {
2457 ArrayRef(MCR.begin(), MCR.getNumRegs()),
2458 ArrayRef(AltOrder1)
2459 };
2460 const unsigned Select = ADDR32BitAltOrderSelect(MF, Rev);
2461 assert(Select < 2);
2462 return Order[Select];
2463}
2464
2465static inline unsigned AnyRegBitAltOrderSelect(const MachineFunction &MF, bool Rev) {
2466 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
2467 return S.isTargetXPLINK64();
2468 }
2469
2470static ArrayRef<MCPhysReg> AnyRegBitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
2471 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::AnyRegBitRegClassID];
2472 const ArrayRef<MCPhysReg> Order[] = {
2473 ArrayRef(MCR.begin(), MCR.getNumRegs())
2474 };
2475 const unsigned Select = AnyRegBitAltOrderSelect(MF, Rev);
2476 assert(Select < 1);
2477 return Order[Select];
2478}
2479
2480static inline unsigned AnyRegBit_with_subreg_h16AltOrderSelect(const MachineFunction &MF, bool Rev) {
2481 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
2482 return S.isTargetXPLINK64();
2483 }
2484
2485static ArrayRef<MCPhysReg> AnyRegBit_with_subreg_h16GetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
2486 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::AnyRegBit_with_subreg_h16RegClassID];
2487 const ArrayRef<MCPhysReg> Order[] = {
2488 ArrayRef(MCR.begin(), MCR.getNumRegs())
2489 };
2490 const unsigned Select = AnyRegBit_with_subreg_h16AltOrderSelect(MF, Rev);
2491 assert(Select < 1);
2492 return Order[Select];
2493}
2494
2495static inline unsigned VR64BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
2496 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
2497 return S.isTargetXPLINK64();
2498 }
2499
2500static ArrayRef<MCPhysReg> VR64BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
2501 static const MCPhysReg AltOrder1[] = { SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, SystemZ::F16D, SystemZ::F17D, SystemZ::F18D, SystemZ::F19D, SystemZ::F20D, SystemZ::F21D, SystemZ::F22D, SystemZ::F23D, SystemZ::F24D, SystemZ::F25D, SystemZ::F26D, SystemZ::F27D, SystemZ::F28D, SystemZ::F29D, SystemZ::F30D, SystemZ::F31D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D };
2502 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::VR64BitRegClassID];
2503 const ArrayRef<MCPhysReg> Order[] = {
2504 ArrayRef(MCR.begin(), MCR.getNumRegs()),
2505 ArrayRef(AltOrder1)
2506 };
2507 const unsigned Select = VR64BitAltOrderSelect(MF, Rev);
2508 assert(Select < 2);
2509 return Order[Select];
2510}
2511
2512static inline unsigned AnyRegBit_with_subreg_h64AltOrderSelect(const MachineFunction &MF, bool Rev) {
2513 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
2514 return S.isTargetXPLINK64();
2515 }
2516
2517static ArrayRef<MCPhysReg> AnyRegBit_with_subreg_h64GetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
2518 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::AnyRegBit_with_subreg_h64RegClassID];
2519 const ArrayRef<MCPhysReg> Order[] = {
2520 ArrayRef(MCR.begin(), MCR.getNumRegs())
2521 };
2522 const unsigned Select = AnyRegBit_with_subreg_h64AltOrderSelect(MF, Rev);
2523 assert(Select < 1);
2524 return Order[Select];
2525}
2526
2527static inline unsigned CR64BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
2528 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
2529 return S.isTargetXPLINK64();
2530 }
2531
2532static ArrayRef<MCPhysReg> CR64BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
2533 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::CR64BitRegClassID];
2534 const ArrayRef<MCPhysReg> Order[] = {
2535 ArrayRef(MCR.begin(), MCR.getNumRegs())
2536 };
2537 const unsigned Select = CR64BitAltOrderSelect(MF, Rev);
2538 assert(Select < 1);
2539 return Order[Select];
2540}
2541
2542static inline unsigned FP64BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
2543 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
2544 return S.isTargetXPLINK64();
2545 }
2546
2547static ArrayRef<MCPhysReg> FP64BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
2548 static const MCPhysReg AltOrder1[] = { SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D };
2549 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::FP64BitRegClassID];
2550 const ArrayRef<MCPhysReg> Order[] = {
2551 ArrayRef(MCR.begin(), MCR.getNumRegs()),
2552 ArrayRef(AltOrder1)
2553 };
2554 const unsigned Select = FP64BitAltOrderSelect(MF, Rev);
2555 assert(Select < 2);
2556 return Order[Select];
2557}
2558
2559static inline unsigned GR64BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
2560 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
2561 return S.isTargetXPLINK64();
2562 }
2563
2564static ArrayRef<MCPhysReg> GR64BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
2565 static const MCPhysReg AltOrder1[] = { SystemZ::R0D, SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, SystemZ::R5D, SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D };
2566 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::GR64BitRegClassID];
2567 const ArrayRef<MCPhysReg> Order[] = {
2568 ArrayRef(MCR.begin(), MCR.getNumRegs()),
2569 ArrayRef(AltOrder1)
2570 };
2571 const unsigned Select = GR64BitAltOrderSelect(MF, Rev);
2572 assert(Select < 2);
2573 return Order[Select];
2574}
2575
2576static inline unsigned ADDR64BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
2577 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
2578 return S.isTargetXPLINK64();
2579 }
2580
2581static ArrayRef<MCPhysReg> ADDR64BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
2582 static const MCPhysReg AltOrder1[] = { SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, SystemZ::R5D, SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D };
2583 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::ADDR64BitRegClassID];
2584 const ArrayRef<MCPhysReg> Order[] = {
2585 ArrayRef(MCR.begin(), MCR.getNumRegs()),
2586 ArrayRef(AltOrder1)
2587 };
2588 const unsigned Select = ADDR64BitAltOrderSelect(MF, Rev);
2589 assert(Select < 2);
2590 return Order[Select];
2591}
2592
2593static inline unsigned VR128BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
2594 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
2595 return S.isTargetXPLINK64();
2596 }
2597
2598static ArrayRef<MCPhysReg> VR128BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
2599 static const MCPhysReg AltOrder1[] = { SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3, SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7, SystemZ::V16, SystemZ::V17, SystemZ::V18, SystemZ::V19, SystemZ::V20, SystemZ::V21, SystemZ::V22, SystemZ::V23, SystemZ::V24, SystemZ::V25, SystemZ::V26, SystemZ::V27, SystemZ::V28, SystemZ::V29, SystemZ::V30, SystemZ::V31, SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11, SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15 };
2600 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::VR128BitRegClassID];
2601 const ArrayRef<MCPhysReg> Order[] = {
2602 ArrayRef(MCR.begin(), MCR.getNumRegs()),
2603 ArrayRef(AltOrder1)
2604 };
2605 const unsigned Select = VR128BitAltOrderSelect(MF, Rev);
2606 assert(Select < 2);
2607 return Order[Select];
2608}
2609
2610static inline unsigned VF128BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
2611 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
2612 return S.isTargetXPLINK64();
2613 }
2614
2615static ArrayRef<MCPhysReg> VF128BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
2616 static const MCPhysReg AltOrder1[] = { SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3, SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7, SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11, SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15 };
2617 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::VF128BitRegClassID];
2618 const ArrayRef<MCPhysReg> Order[] = {
2619 ArrayRef(MCR.begin(), MCR.getNumRegs()),
2620 ArrayRef(AltOrder1)
2621 };
2622 const unsigned Select = VF128BitAltOrderSelect(MF, Rev);
2623 assert(Select < 2);
2624 return Order[Select];
2625}
2626
2627static inline unsigned FP128BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
2628 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
2629 return S.isTargetXPLINK64();
2630 }
2631
2632static ArrayRef<MCPhysReg> FP128BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
2633 static const MCPhysReg AltOrder1[] = { SystemZ::F0Q, SystemZ::F1Q, SystemZ::F4Q, SystemZ::F5Q, SystemZ::F8Q, SystemZ::F9Q, SystemZ::F12Q, SystemZ::F13Q };
2634 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::FP128BitRegClassID];
2635 const ArrayRef<MCPhysReg> Order[] = {
2636 ArrayRef(MCR.begin(), MCR.getNumRegs()),
2637 ArrayRef(AltOrder1)
2638 };
2639 const unsigned Select = FP128BitAltOrderSelect(MF, Rev);
2640 assert(Select < 2);
2641 return Order[Select];
2642}
2643
2644static inline unsigned GR128BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
2645 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
2646 return S.isTargetXPLINK64();
2647 }
2648
2649static ArrayRef<MCPhysReg> GR128BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
2650 static const MCPhysReg AltOrder1[] = { SystemZ::R0Q, SystemZ::R2Q, SystemZ::R4Q, SystemZ::R6Q, SystemZ::R8Q, SystemZ::R10Q, SystemZ::R12Q, SystemZ::R14Q };
2651 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::GR128BitRegClassID];
2652 const ArrayRef<MCPhysReg> Order[] = {
2653 ArrayRef(MCR.begin(), MCR.getNumRegs()),
2654 ArrayRef(AltOrder1)
2655 };
2656 const unsigned Select = GR128BitAltOrderSelect(MF, Rev);
2657 assert(Select < 2);
2658 return Order[Select];
2659}
2660
2661static inline unsigned ADDR128BitAltOrderSelect(const MachineFunction &MF, bool Rev) {
2662 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
2663 return S.isTargetXPLINK64();
2664 }
2665
2666static ArrayRef<MCPhysReg> ADDR128BitGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
2667 static const MCPhysReg AltOrder1[] = { SystemZ::R2Q, SystemZ::R4Q, SystemZ::R6Q, SystemZ::R8Q, SystemZ::R10Q, SystemZ::R12Q, SystemZ::R14Q };
2668 const MCRegisterClass &MCR = SystemZMCRegisterClasses[SystemZ::ADDR128BitRegClassID];
2669 const ArrayRef<MCPhysReg> Order[] = {
2670 ArrayRef(MCR.begin(), MCR.getNumRegs()),
2671 ArrayRef(AltOrder1)
2672 };
2673 const unsigned Select = ADDR128BitAltOrderSelect(MF, Rev);
2674 assert(Select < 2);
2675 return Order[Select];
2676}
2677
2678namespace SystemZ { // Register class instances
2679 extern const TargetRegisterClass VR16BitRegClass = {
2680 &SystemZMCRegisterClasses[VR16BitRegClassID],
2681 VR16BitSubClassMask,
2682 SuperRegIdxSeqs + 14,
2683 LaneBitmask(0x0000000000000001),
2684 0,
2685 false,
2686 0x00, /* TSFlags */
2687 false, /* HasDisjunctSubRegs */
2688 false, /* CoveredBySubRegs */
2689 nullptr, 0,
2690 VR16BitGetRawAllocationOrder
2691 };
2692
2693 extern const TargetRegisterClass FP16BitRegClass = {
2694 &SystemZMCRegisterClasses[FP16BitRegClassID],
2695 FP16BitSubClassMask,
2696 SuperRegIdxSeqs + 14,
2697 LaneBitmask(0x0000000000000001),
2698 0,
2699 false,
2700 0x00, /* TSFlags */
2701 false, /* HasDisjunctSubRegs */
2702 false, /* CoveredBySubRegs */
2703 FP16BitSuperclasses, 1,
2704 FP16BitGetRawAllocationOrder
2705 };
2706
2707 extern const TargetRegisterClass GRX32BitRegClass = {
2708 &SystemZMCRegisterClasses[GRX32BitRegClassID],
2709 GRX32BitSubClassMask,
2710 SuperRegIdxSeqs + 9,
2711 LaneBitmask(0x0000000000000001),
2712 0,
2713 false,
2714 0x00, /* TSFlags */
2715 false, /* HasDisjunctSubRegs */
2716 false, /* CoveredBySubRegs */
2717 nullptr, 0,
2718 GRX32BitGetRawAllocationOrder
2719 };
2720
2721 extern const TargetRegisterClass VR32BitRegClass = {
2722 &SystemZMCRegisterClasses[VR32BitRegClassID],
2723 VR32BitSubClassMask,
2724 SuperRegIdxSeqs + 3,
2725 LaneBitmask(0x0000000000000001),
2726 0,
2727 false,
2728 0x00, /* TSFlags */
2729 false, /* HasDisjunctSubRegs */
2730 false, /* CoveredBySubRegs */
2731 nullptr, 0,
2732 VR32BitGetRawAllocationOrder
2733 };
2734
2735 extern const TargetRegisterClass AR32BitRegClass = {
2736 &SystemZMCRegisterClasses[AR32BitRegClassID],
2737 AR32BitSubClassMask,
2738 SuperRegIdxSeqs + 2,
2739 LaneBitmask(0x0000000000000001),
2740 0,
2741 false,
2742 0x00, /* TSFlags */
2743 false, /* HasDisjunctSubRegs */
2744 false, /* CoveredBySubRegs */
2745 nullptr, 0,
2746 AR32BitGetRawAllocationOrder
2747 };
2748
2749 extern const TargetRegisterClass FP32BitRegClass = {
2750 &SystemZMCRegisterClasses[FP32BitRegClassID],
2751 FP32BitSubClassMask,
2752 SuperRegIdxSeqs + 3,
2753 LaneBitmask(0x0000000000000001),
2754 0,
2755 false,
2756 0x00, /* TSFlags */
2757 false, /* HasDisjunctSubRegs */
2758 false, /* CoveredBySubRegs */
2759 FP32BitSuperclasses, 1,
2760 FP32BitGetRawAllocationOrder
2761 };
2762
2763 extern const TargetRegisterClass GR32BitRegClass = {
2764 &SystemZMCRegisterClasses[GR32BitRegClassID],
2765 GR32BitSubClassMask,
2766 SuperRegIdxSeqs + 6,
2767 LaneBitmask(0x0000000000000001),
2768 0,
2769 false,
2770 0x00, /* TSFlags */
2771 false, /* HasDisjunctSubRegs */
2772 false, /* CoveredBySubRegs */
2773 GR32BitSuperclasses, 1,
2774 GR32BitGetRawAllocationOrder
2775 };
2776
2777 extern const TargetRegisterClass GRH32BitRegClass = {
2778 &SystemZMCRegisterClasses[GRH32BitRegClassID],
2779 GRH32BitSubClassMask,
2780 SuperRegIdxSeqs + 3,
2781 LaneBitmask(0x0000000000000001),
2782 0,
2783 false,
2784 0x00, /* TSFlags */
2785 false, /* HasDisjunctSubRegs */
2786 false, /* CoveredBySubRegs */
2787 GRH32BitSuperclasses, 1,
2788 GRH32BitGetRawAllocationOrder
2789 };
2790
2791 extern const TargetRegisterClass ADDR32BitRegClass = {
2792 &SystemZMCRegisterClasses[ADDR32BitRegClassID],
2793 ADDR32BitSubClassMask,
2794 SuperRegIdxSeqs + 6,
2795 LaneBitmask(0x0000000000000001),
2796 0,
2797 false,
2798 0x00, /* TSFlags */
2799 false, /* HasDisjunctSubRegs */
2800 false, /* CoveredBySubRegs */
2801 ADDR32BitSuperclasses, 2,
2802 ADDR32BitGetRawAllocationOrder
2803 };
2804
2805 extern const TargetRegisterClass CCRRegClass = {
2806 &SystemZMCRegisterClasses[CCRRegClassID],
2807 CCRSubClassMask,
2808 SuperRegIdxSeqs + 2,
2809 LaneBitmask(0x0000000000000001),
2810 0,
2811 false,
2812 0x00, /* TSFlags */
2813 false, /* HasDisjunctSubRegs */
2814 false, /* CoveredBySubRegs */
2815 nullptr, 0,
2816 nullptr
2817 };
2818
2819 extern const TargetRegisterClass FPCRegsRegClass = {
2820 &SystemZMCRegisterClasses[FPCRegsRegClassID],
2821 FPCRegsSubClassMask,
2822 SuperRegIdxSeqs + 2,
2823 LaneBitmask(0x0000000000000001),
2824 0,
2825 false,
2826 0x00, /* TSFlags */
2827 false, /* HasDisjunctSubRegs */
2828 false, /* CoveredBySubRegs */
2829 nullptr, 0,
2830 nullptr
2831 };
2832
2833 extern const TargetRegisterClass AnyRegBitRegClass = {
2834 &SystemZMCRegisterClasses[AnyRegBitRegClassID],
2835 AnyRegBitSubClassMask,
2836 SuperRegIdxSeqs + 0,
2837 LaneBitmask(0x0000000000000003),
2838 0,
2839 false,
2840 0x00, /* TSFlags */
2841 true, /* HasDisjunctSubRegs */
2842 false, /* CoveredBySubRegs */
2843 nullptr, 0,
2844 AnyRegBitGetRawAllocationOrder
2845 };
2846
2847 extern const TargetRegisterClass AnyRegBit_with_subreg_h16RegClass = {
2848 &SystemZMCRegisterClasses[AnyRegBit_with_subreg_h16RegClassID],
2849 AnyRegBit_with_subreg_h16SubClassMask,
2850 SuperRegIdxSeqs + 0,
2851 LaneBitmask(0x0000000000000003),
2852 0,
2853 false,
2854 0x00, /* TSFlags */
2855 false, /* HasDisjunctSubRegs */
2856 false, /* CoveredBySubRegs */
2857 AnyRegBit_with_subreg_h16Superclasses, 1,
2858 AnyRegBit_with_subreg_h16GetRawAllocationOrder
2859 };
2860
2861 extern const TargetRegisterClass VR64BitRegClass = {
2862 &SystemZMCRegisterClasses[VR64BitRegClassID],
2863 VR64BitSubClassMask,
2864 SuperRegIdxSeqs + 0,
2865 LaneBitmask(0x0000000000000001),
2866 0,
2867 false,
2868 0x00, /* TSFlags */
2869 false, /* HasDisjunctSubRegs */
2870 false, /* CoveredBySubRegs */
2871 nullptr, 0,
2872 VR64BitGetRawAllocationOrder
2873 };
2874
2875 extern const TargetRegisterClass AnyRegBit_with_subreg_h64RegClass = {
2876 &SystemZMCRegisterClasses[AnyRegBit_with_subreg_h64RegClassID],
2877 AnyRegBit_with_subreg_h64SubClassMask,
2878 SuperRegIdxSeqs + 2,
2879 LaneBitmask(0x0000000000000003),
2880 0,
2881 false,
2882 0x00, /* TSFlags */
2883 false, /* HasDisjunctSubRegs */
2884 false, /* CoveredBySubRegs */
2885 AnyRegBit_with_subreg_h64Superclasses, 2,
2886 AnyRegBit_with_subreg_h64GetRawAllocationOrder
2887 };
2888
2889 extern const TargetRegisterClass CR64BitRegClass = {
2890 &SystemZMCRegisterClasses[CR64BitRegClassID],
2891 CR64BitSubClassMask,
2892 SuperRegIdxSeqs + 2,
2893 LaneBitmask(0x0000000000000001),
2894 0,
2895 false,
2896 0x00, /* TSFlags */
2897 false, /* HasDisjunctSubRegs */
2898 false, /* CoveredBySubRegs */
2899 nullptr, 0,
2900 CR64BitGetRawAllocationOrder
2901 };
2902
2903 extern const TargetRegisterClass FP64BitRegClass = {
2904 &SystemZMCRegisterClasses[FP64BitRegClassID],
2905 FP64BitSubClassMask,
2906 SuperRegIdxSeqs + 0,
2907 LaneBitmask(0x0000000000000001),
2908 0,
2909 false,
2910 0x00, /* TSFlags */
2911 false, /* HasDisjunctSubRegs */
2912 false, /* CoveredBySubRegs */
2913 FP64BitSuperclasses, 3,
2914 FP64BitGetRawAllocationOrder
2915 };
2916
2917 extern const TargetRegisterClass GR64BitRegClass = {
2918 &SystemZMCRegisterClasses[GR64BitRegClassID],
2919 GR64BitSubClassMask,
2920 SuperRegIdxSeqs + 0,
2921 LaneBitmask(0x0000000000000003),
2922 0,
2923 false,
2924 0x00, /* TSFlags */
2925 true, /* HasDisjunctSubRegs */
2926 true, /* CoveredBySubRegs */
2927 GR64BitSuperclasses, 1,
2928 GR64BitGetRawAllocationOrder
2929 };
2930
2931 extern const TargetRegisterClass ADDR64BitRegClass = {
2932 &SystemZMCRegisterClasses[ADDR64BitRegClassID],
2933 ADDR64BitSubClassMask,
2934 SuperRegIdxSeqs + 0,
2935 LaneBitmask(0x0000000000000003),
2936 0,
2937 false,
2938 0x00, /* TSFlags */
2939 true, /* HasDisjunctSubRegs */
2940 true, /* CoveredBySubRegs */
2941 ADDR64BitSuperclasses, 2,
2942 ADDR64BitGetRawAllocationOrder
2943 };
2944
2945 extern const TargetRegisterClass VR128BitRegClass = {
2946 &SystemZMCRegisterClasses[VR128BitRegClassID],
2947 VR128BitSubClassMask,
2948 SuperRegIdxSeqs + 2,
2949 LaneBitmask(0x0000000000000003),
2950 0,
2951 false,
2952 0x00, /* TSFlags */
2953 false, /* HasDisjunctSubRegs */
2954 false, /* CoveredBySubRegs */
2955 nullptr, 0,
2956 VR128BitGetRawAllocationOrder
2957 };
2958
2959 extern const TargetRegisterClass VF128BitRegClass = {
2960 &SystemZMCRegisterClasses[VF128BitRegClassID],
2961 VF128BitSubClassMask,
2962 SuperRegIdxSeqs + 2,
2963 LaneBitmask(0x0000000000000003),
2964 0,
2965 false,
2966 0x00, /* TSFlags */
2967 false, /* HasDisjunctSubRegs */
2968 false, /* CoveredBySubRegs */
2969 VF128BitSuperclasses, 4,
2970 VF128BitGetRawAllocationOrder
2971 };
2972
2973 extern const TargetRegisterClass FP128BitRegClass = {
2974 &SystemZMCRegisterClasses[FP128BitRegClassID],
2975 FP128BitSubClassMask,
2976 SuperRegIdxSeqs + 2,
2977 LaneBitmask(0x000000000000000F),
2978 0,
2979 false,
2980 0x00, /* TSFlags */
2981 true, /* HasDisjunctSubRegs */
2982 true, /* CoveredBySubRegs */
2983 nullptr, 0,
2984 FP128BitGetRawAllocationOrder
2985 };
2986
2987 extern const TargetRegisterClass GR128BitRegClass = {
2988 &SystemZMCRegisterClasses[GR128BitRegClassID],
2989 GR128BitSubClassMask,
2990 SuperRegIdxSeqs + 2,
2991 LaneBitmask(0x000000000000000F),
2992 0,
2993 false,
2994 0x00, /* TSFlags */
2995 true, /* HasDisjunctSubRegs */
2996 true, /* CoveredBySubRegs */
2997 nullptr, 0,
2998 GR128BitGetRawAllocationOrder
2999 };
3000
3001 extern const TargetRegisterClass ADDR128BitRegClass = {
3002 &SystemZMCRegisterClasses[ADDR128BitRegClassID],
3003 ADDR128BitSubClassMask,
3004 SuperRegIdxSeqs + 2,
3005 LaneBitmask(0x000000000000000F),
3006 0,
3007 false,
3008 0x00, /* TSFlags */
3009 true, /* HasDisjunctSubRegs */
3010 true, /* CoveredBySubRegs */
3011 ADDR128BitSuperclasses, 1,
3012 ADDR128BitGetRawAllocationOrder
3013 };
3014
3015} // end namespace SystemZ
3016
3017namespace {
3018 const TargetRegisterClass *const RegisterClasses[] = {
3019 &SystemZ::VR16BitRegClass,
3020 &SystemZ::FP16BitRegClass,
3021 &SystemZ::GRX32BitRegClass,
3022 &SystemZ::VR32BitRegClass,
3023 &SystemZ::AR32BitRegClass,
3024 &SystemZ::FP32BitRegClass,
3025 &SystemZ::GR32BitRegClass,
3026 &SystemZ::GRH32BitRegClass,
3027 &SystemZ::ADDR32BitRegClass,
3028 &SystemZ::CCRRegClass,
3029 &SystemZ::FPCRegsRegClass,
3030 &SystemZ::AnyRegBitRegClass,
3031 &SystemZ::AnyRegBit_with_subreg_h16RegClass,
3032 &SystemZ::VR64BitRegClass,
3033 &SystemZ::AnyRegBit_with_subreg_h64RegClass,
3034 &SystemZ::CR64BitRegClass,
3035 &SystemZ::FP64BitRegClass,
3036 &SystemZ::GR64BitRegClass,
3037 &SystemZ::ADDR64BitRegClass,
3038 &SystemZ::VR128BitRegClass,
3039 &SystemZ::VF128BitRegClass,
3040 &SystemZ::FP128BitRegClass,
3041 &SystemZ::GR128BitRegClass,
3042 &SystemZ::ADDR128BitRegClass,
3043 };
3044} // end anonymous namespace
3045
3046static const uint8_t CostPerUseTable[] = {
30470, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
3048
3049
3050static const bool InAllocatableClassTable[] = {
3051false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
3052
3053
3054static const TargetRegisterInfoDesc SystemZRegInfoDesc = { // Extra Descriptors
3055CostPerUseTable, 1, InAllocatableClassTable};
3056
3057unsigned SystemZGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
3058 static const uint8_t RowMap[8] = {
3059 0, 0, 0, 0, 1, 1, 0, 0,
3060 };
3061 static const uint8_t Rows[2][8] = {
3062 { SystemZ::subreg_h16, SystemZ::subreg_h32, 0, SystemZ::subreg_l32, 0, 0, 0, 0, },
3063 { SystemZ::subreg_lh32_then_subreg_h16, SystemZ::subreg_lh32, 0, SystemZ::subreg_ll32, 0, 0, 0, 0, },
3064 };
3065
3066 --IdxA; assert(IdxA < 8); (void) IdxA;
3067 --IdxB; assert(IdxB < 8);
3068 return Rows[RowMap[IdxA]][IdxB];
3069}
3070
3071unsigned SystemZGenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
3072 static const uint8_t Table[8][8] = {
3073 { SystemZ::subreg_h16, SystemZ::subreg_h32, 0, SystemZ::subreg_l32, 0, 0, 0, 0, },
3074 { SystemZ::subreg_h16, SystemZ::subreg_h32, 0, SystemZ::subreg_l32, 0, 0, 0, 0, },
3075 { SystemZ::subreg_h16, SystemZ::subreg_h32, 0, SystemZ::subreg_l32, 0, 0, 0, 0, },
3076 { SystemZ::subreg_h16, SystemZ::subreg_h32, 0, SystemZ::subreg_l32, 0, 0, 0, 0, },
3077 { 0, 0, 0, 0, 0, SystemZ::subreg_h32, SystemZ::subreg_l32, SystemZ::subreg_h16, },
3078 { 0, 0, 0, 0, 0, SystemZ::subreg_h32, SystemZ::subreg_l32, SystemZ::subreg_h16, },
3079 { SystemZ::subreg_h16, SystemZ::subreg_h32, 0, SystemZ::subreg_l32, 0, 0, 0, 0, },
3080 { SystemZ::subreg_h16, SystemZ::subreg_h32, 0, SystemZ::subreg_l32, 0, 0, 0, 0, },
3081 };
3082
3083 --IdxA; assert(IdxA < 8);
3084 --IdxB; assert(IdxB < 8);
3085 return Table[IdxA][IdxB];
3086 }
3087
3088 struct MaskRolOp {
3089 LaneBitmask Mask;
3090 uint8_t RotateLeft;
3091 };
3092 static const MaskRolOp LaneMaskComposeSequences[] = {
3093 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 0 }, { LaneBitmask::getNone(), 0 }, // Sequence 0
3094 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 1 }, { LaneBitmask::getNone(), 0 }, // Sequence 2
3095 { LaneBitmask(0x0000000000000001), 3 }, { LaneBitmask(0x0000000000000002), 1 }, { LaneBitmask::getNone(), 0 }, // Sequence 4
3096 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 3 }, { LaneBitmask::getNone(), 0 }, // Sequence 7
3097 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 2 }, { LaneBitmask::getNone(), 0 } // Sequence 9
3098 };
3099 static const uint8_t CompositeSequences[] = {
3100 0, // to subreg_h16
3101 0, // to subreg_h32
3102 0, // to subreg_h64
3103 2, // to subreg_l32
3104 4, // to subreg_l64
3105 7, // to subreg_lh32
3106 9, // to subreg_ll32
3107 7 // to subreg_lh32_then_subreg_h16
3108 };
3109
3110LaneBitmask SystemZGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
3111 --IdxA; assert(IdxA < 8 && "Subregister index out of bounds");
3112 LaneBitmask Result;
3113 for (const MaskRolOp *Ops =
3114 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
3115 Ops->Mask.any(); ++Ops) {
3116 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
3117 if (unsigned S = Ops->RotateLeft)
3118 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
3119 else
3120 Result |= LaneBitmask(M);
3121 }
3122 return Result;
3123}
3124
3125LaneBitmask SystemZGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
3126 LaneMask &= getSubRegIndexLaneMask(IdxA);
3127 --IdxA; assert(IdxA < 8 && "Subregister index out of bounds");
3128 LaneBitmask Result;
3129 for (const MaskRolOp *Ops =
3130 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
3131 Ops->Mask.any(); ++Ops) {
3132 LaneBitmask::Type M = LaneMask.getAsInteger();
3133 if (unsigned S = Ops->RotateLeft)
3134 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
3135 else
3136 Result |= LaneBitmask(M);
3137 }
3138 return Result;
3139}
3140
3141const TargetRegisterClass *SystemZGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
3142 static const uint8_t Table[24][8] = {
3143 { // VR16Bit
3144 0, // subreg_h16
3145 0, // subreg_h32
3146 0, // subreg_h64
3147 0, // subreg_l32
3148 0, // subreg_l64
3149 0, // subreg_lh32
3150 0, // subreg_ll32
3151 0, // subreg_lh32_then_subreg_h16
3152 },
3153 { // FP16Bit
3154 0, // subreg_h16
3155 0, // subreg_h32
3156 0, // subreg_h64
3157 0, // subreg_l32
3158 0, // subreg_l64
3159 0, // subreg_lh32
3160 0, // subreg_ll32
3161 0, // subreg_lh32_then_subreg_h16
3162 },
3163 { // GRX32Bit
3164 0, // subreg_h16
3165 0, // subreg_h32
3166 0, // subreg_h64
3167 0, // subreg_l32
3168 0, // subreg_l64
3169 0, // subreg_lh32
3170 0, // subreg_ll32
3171 0, // subreg_lh32_then_subreg_h16
3172 },
3173 { // VR32Bit
3174 4, // subreg_h16 -> VR32Bit
3175 0, // subreg_h32
3176 0, // subreg_h64
3177 0, // subreg_l32
3178 0, // subreg_l64
3179 0, // subreg_lh32
3180 0, // subreg_ll32
3181 0, // subreg_lh32_then_subreg_h16
3182 },
3183 { // AR32Bit
3184 0, // subreg_h16
3185 0, // subreg_h32
3186 0, // subreg_h64
3187 0, // subreg_l32
3188 0, // subreg_l64
3189 0, // subreg_lh32
3190 0, // subreg_ll32
3191 0, // subreg_lh32_then_subreg_h16
3192 },
3193 { // FP32Bit
3194 6, // subreg_h16 -> FP32Bit
3195 0, // subreg_h32
3196 0, // subreg_h64
3197 0, // subreg_l32
3198 0, // subreg_l64
3199 0, // subreg_lh32
3200 0, // subreg_ll32
3201 0, // subreg_lh32_then_subreg_h16
3202 },
3203 { // GR32Bit
3204 0, // subreg_h16
3205 0, // subreg_h32
3206 0, // subreg_h64
3207 0, // subreg_l32
3208 0, // subreg_l64
3209 0, // subreg_lh32
3210 0, // subreg_ll32
3211 0, // subreg_lh32_then_subreg_h16
3212 },
3213 { // GRH32Bit
3214 0, // subreg_h16
3215 0, // subreg_h32
3216 0, // subreg_h64
3217 0, // subreg_l32
3218 0, // subreg_l64
3219 0, // subreg_lh32
3220 0, // subreg_ll32
3221 0, // subreg_lh32_then_subreg_h16
3222 },
3223 { // ADDR32Bit
3224 0, // subreg_h16
3225 0, // subreg_h32
3226 0, // subreg_h64
3227 0, // subreg_l32
3228 0, // subreg_l64
3229 0, // subreg_lh32
3230 0, // subreg_ll32
3231 0, // subreg_lh32_then_subreg_h16
3232 },
3233 { // CCR
3234 0, // subreg_h16
3235 0, // subreg_h32
3236 0, // subreg_h64
3237 0, // subreg_l32
3238 0, // subreg_l64
3239 0, // subreg_lh32
3240 0, // subreg_ll32
3241 0, // subreg_lh32_then_subreg_h16
3242 },
3243 { // FPCRegs
3244 0, // subreg_h16
3245 0, // subreg_h32
3246 0, // subreg_h64
3247 0, // subreg_l32
3248 0, // subreg_l64
3249 0, // subreg_lh32
3250 0, // subreg_ll32
3251 0, // subreg_lh32_then_subreg_h16
3252 },
3253 { // AnyRegBit
3254 13, // subreg_h16 -> AnyRegBit_with_subreg_h16
3255 12, // subreg_h32 -> AnyRegBit
3256 15, // subreg_h64 -> AnyRegBit_with_subreg_h64
3257 18, // subreg_l32 -> GR64Bit
3258 0, // subreg_l64
3259 0, // subreg_lh32
3260 0, // subreg_ll32
3261 0, // subreg_lh32_then_subreg_h16
3262 },
3263 { // AnyRegBit_with_subreg_h16
3264 13, // subreg_h16 -> AnyRegBit_with_subreg_h16
3265 13, // subreg_h32 -> AnyRegBit_with_subreg_h16
3266 15, // subreg_h64 -> AnyRegBit_with_subreg_h64
3267 0, // subreg_l32
3268 0, // subreg_l64
3269 0, // subreg_lh32
3270 0, // subreg_ll32
3271 0, // subreg_lh32_then_subreg_h16
3272 },
3273 { // VR64Bit
3274 14, // subreg_h16 -> VR64Bit
3275 14, // subreg_h32 -> VR64Bit
3276 0, // subreg_h64
3277 0, // subreg_l32
3278 0, // subreg_l64
3279 0, // subreg_lh32
3280 0, // subreg_ll32
3281 0, // subreg_lh32_then_subreg_h16
3282 },
3283 { // AnyRegBit_with_subreg_h64
3284 15, // subreg_h16 -> AnyRegBit_with_subreg_h64
3285 15, // subreg_h32 -> AnyRegBit_with_subreg_h64
3286 15, // subreg_h64 -> AnyRegBit_with_subreg_h64
3287 0, // subreg_l32
3288 0, // subreg_l64
3289 0, // subreg_lh32
3290 0, // subreg_ll32
3291 0, // subreg_lh32_then_subreg_h16
3292 },
3293 { // CR64Bit
3294 0, // subreg_h16
3295 0, // subreg_h32
3296 0, // subreg_h64
3297 0, // subreg_l32
3298 0, // subreg_l64
3299 0, // subreg_lh32
3300 0, // subreg_ll32
3301 0, // subreg_lh32_then_subreg_h16
3302 },
3303 { // FP64Bit
3304 17, // subreg_h16 -> FP64Bit
3305 17, // subreg_h32 -> FP64Bit
3306 0, // subreg_h64
3307 0, // subreg_l32
3308 0, // subreg_l64
3309 0, // subreg_lh32
3310 0, // subreg_ll32
3311 0, // subreg_lh32_then_subreg_h16
3312 },
3313 { // GR64Bit
3314 0, // subreg_h16
3315 18, // subreg_h32 -> GR64Bit
3316 0, // subreg_h64
3317 18, // subreg_l32 -> GR64Bit
3318 0, // subreg_l64
3319 0, // subreg_lh32
3320 0, // subreg_ll32
3321 0, // subreg_lh32_then_subreg_h16
3322 },
3323 { // ADDR64Bit
3324 0, // subreg_h16
3325 19, // subreg_h32 -> ADDR64Bit
3326 0, // subreg_h64
3327 19, // subreg_l32 -> ADDR64Bit
3328 0, // subreg_l64
3329 0, // subreg_lh32
3330 0, // subreg_ll32
3331 0, // subreg_lh32_then_subreg_h16
3332 },
3333 { // VR128Bit
3334 20, // subreg_h16 -> VR128Bit
3335 20, // subreg_h32 -> VR128Bit
3336 20, // subreg_h64 -> VR128Bit
3337 0, // subreg_l32
3338 0, // subreg_l64
3339 0, // subreg_lh32
3340 0, // subreg_ll32
3341 0, // subreg_lh32_then_subreg_h16
3342 },
3343 { // VF128Bit
3344 21, // subreg_h16 -> VF128Bit
3345 21, // subreg_h32 -> VF128Bit
3346 21, // subreg_h64 -> VF128Bit
3347 0, // subreg_l32
3348 0, // subreg_l64
3349 0, // subreg_lh32
3350 0, // subreg_ll32
3351 0, // subreg_lh32_then_subreg_h16
3352 },
3353 { // FP128Bit
3354 22, // subreg_h16 -> FP128Bit
3355 22, // subreg_h32 -> FP128Bit
3356 22, // subreg_h64 -> FP128Bit
3357 0, // subreg_l32
3358 22, // subreg_l64 -> FP128Bit
3359 22, // subreg_lh32 -> FP128Bit
3360 0, // subreg_ll32
3361 22, // subreg_lh32_then_subreg_h16 -> FP128Bit
3362 },
3363 { // GR128Bit
3364 0, // subreg_h16
3365 23, // subreg_h32 -> GR128Bit
3366 23, // subreg_h64 -> GR128Bit
3367 23, // subreg_l32 -> GR128Bit
3368 23, // subreg_l64 -> GR128Bit
3369 23, // subreg_lh32 -> GR128Bit
3370 23, // subreg_ll32 -> GR128Bit
3371 0, // subreg_lh32_then_subreg_h16
3372 },
3373 { // ADDR128Bit
3374 0, // subreg_h16
3375 24, // subreg_h32 -> ADDR128Bit
3376 24, // subreg_h64 -> ADDR128Bit
3377 24, // subreg_l32 -> ADDR128Bit
3378 24, // subreg_l64 -> ADDR128Bit
3379 24, // subreg_lh32 -> ADDR128Bit
3380 24, // subreg_ll32 -> ADDR128Bit
3381 0, // subreg_lh32_then_subreg_h16
3382 },
3383 };
3384 assert(RC && "Missing regclass");
3385 if (!Idx) return RC;
3386 --Idx;
3387 assert(Idx < 8 && "Bad subreg");
3388 unsigned TV = Table[RC->getID()][Idx];
3389 return TV ? getRegClass(TV - 1) : nullptr;
3390}
3391
3392const TargetRegisterClass *SystemZGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
3393 static const uint8_t Table[24][8] = {
3394 { // VR16Bit
3395 0, // VR16Bit:subreg_h16
3396 0, // VR16Bit:subreg_h32
3397 0, // VR16Bit:subreg_h64
3398 0, // VR16Bit:subreg_l32
3399 0, // VR16Bit:subreg_l64
3400 0, // VR16Bit:subreg_lh32
3401 0, // VR16Bit:subreg_ll32
3402 0, // VR16Bit:subreg_lh32_then_subreg_h16
3403 },
3404 { // FP16Bit
3405 0, // FP16Bit:subreg_h16
3406 0, // FP16Bit:subreg_h32
3407 0, // FP16Bit:subreg_h64
3408 0, // FP16Bit:subreg_l32
3409 0, // FP16Bit:subreg_l64
3410 0, // FP16Bit:subreg_lh32
3411 0, // FP16Bit:subreg_ll32
3412 0, // FP16Bit:subreg_lh32_then_subreg_h16
3413 },
3414 { // GRX32Bit
3415 0, // GRX32Bit:subreg_h16
3416 0, // GRX32Bit:subreg_h32
3417 0, // GRX32Bit:subreg_h64
3418 0, // GRX32Bit:subreg_l32
3419 0, // GRX32Bit:subreg_l64
3420 0, // GRX32Bit:subreg_lh32
3421 0, // GRX32Bit:subreg_ll32
3422 0, // GRX32Bit:subreg_lh32_then_subreg_h16
3423 },
3424 { // VR32Bit
3425 1, // VR32Bit:subreg_h16 -> VR16Bit
3426 0, // VR32Bit:subreg_h32
3427 0, // VR32Bit:subreg_h64
3428 0, // VR32Bit:subreg_l32
3429 0, // VR32Bit:subreg_l64
3430 0, // VR32Bit:subreg_lh32
3431 0, // VR32Bit:subreg_ll32
3432 0, // VR32Bit:subreg_lh32_then_subreg_h16
3433 },
3434 { // AR32Bit
3435 0, // AR32Bit:subreg_h16
3436 0, // AR32Bit:subreg_h32
3437 0, // AR32Bit:subreg_h64
3438 0, // AR32Bit:subreg_l32
3439 0, // AR32Bit:subreg_l64
3440 0, // AR32Bit:subreg_lh32
3441 0, // AR32Bit:subreg_ll32
3442 0, // AR32Bit:subreg_lh32_then_subreg_h16
3443 },
3444 { // FP32Bit
3445 2, // FP32Bit:subreg_h16 -> FP16Bit
3446 0, // FP32Bit:subreg_h32
3447 0, // FP32Bit:subreg_h64
3448 0, // FP32Bit:subreg_l32
3449 0, // FP32Bit:subreg_l64
3450 0, // FP32Bit:subreg_lh32
3451 0, // FP32Bit:subreg_ll32
3452 0, // FP32Bit:subreg_lh32_then_subreg_h16
3453 },
3454 { // GR32Bit
3455 0, // GR32Bit:subreg_h16
3456 0, // GR32Bit:subreg_h32
3457 0, // GR32Bit:subreg_h64
3458 0, // GR32Bit:subreg_l32
3459 0, // GR32Bit:subreg_l64
3460 0, // GR32Bit:subreg_lh32
3461 0, // GR32Bit:subreg_ll32
3462 0, // GR32Bit:subreg_lh32_then_subreg_h16
3463 },
3464 { // GRH32Bit
3465 0, // GRH32Bit:subreg_h16
3466 0, // GRH32Bit:subreg_h32
3467 0, // GRH32Bit:subreg_h64
3468 0, // GRH32Bit:subreg_l32
3469 0, // GRH32Bit:subreg_l64
3470 0, // GRH32Bit:subreg_lh32
3471 0, // GRH32Bit:subreg_ll32
3472 0, // GRH32Bit:subreg_lh32_then_subreg_h16
3473 },
3474 { // ADDR32Bit
3475 0, // ADDR32Bit:subreg_h16
3476 0, // ADDR32Bit:subreg_h32
3477 0, // ADDR32Bit:subreg_h64
3478 0, // ADDR32Bit:subreg_l32
3479 0, // ADDR32Bit:subreg_l64
3480 0, // ADDR32Bit:subreg_lh32
3481 0, // ADDR32Bit:subreg_ll32
3482 0, // ADDR32Bit:subreg_lh32_then_subreg_h16
3483 },
3484 { // CCR
3485 0, // CCR:subreg_h16
3486 0, // CCR:subreg_h32
3487 0, // CCR:subreg_h64
3488 0, // CCR:subreg_l32
3489 0, // CCR:subreg_l64
3490 0, // CCR:subreg_lh32
3491 0, // CCR:subreg_ll32
3492 0, // CCR:subreg_lh32_then_subreg_h16
3493 },
3494 { // FPCRegs
3495 0, // FPCRegs:subreg_h16
3496 0, // FPCRegs:subreg_h32
3497 0, // FPCRegs:subreg_h64
3498 0, // FPCRegs:subreg_l32
3499 0, // FPCRegs:subreg_l64
3500 0, // FPCRegs:subreg_lh32
3501 0, // FPCRegs:subreg_ll32
3502 0, // FPCRegs:subreg_lh32_then_subreg_h16
3503 },
3504 { // AnyRegBit
3505 1, // AnyRegBit:subreg_h16 -> VR16Bit
3506 4, // AnyRegBit:subreg_h32 -> VR32Bit
3507 17, // AnyRegBit:subreg_h64 -> FP64Bit
3508 7, // AnyRegBit:subreg_l32 -> GR32Bit
3509 0, // AnyRegBit:subreg_l64
3510 0, // AnyRegBit:subreg_lh32
3511 0, // AnyRegBit:subreg_ll32
3512 0, // AnyRegBit:subreg_lh32_then_subreg_h16
3513 },
3514 { // AnyRegBit_with_subreg_h16
3515 1, // AnyRegBit_with_subreg_h16:subreg_h16 -> VR16Bit
3516 4, // AnyRegBit_with_subreg_h16:subreg_h32 -> VR32Bit
3517 17, // AnyRegBit_with_subreg_h16:subreg_h64 -> FP64Bit
3518 0, // AnyRegBit_with_subreg_h16:subreg_l32
3519 0, // AnyRegBit_with_subreg_h16:subreg_l64
3520 0, // AnyRegBit_with_subreg_h16:subreg_lh32
3521 0, // AnyRegBit_with_subreg_h16:subreg_ll32
3522 0, // AnyRegBit_with_subreg_h16:subreg_lh32_then_subreg_h16
3523 },
3524 { // VR64Bit
3525 1, // VR64Bit:subreg_h16 -> VR16Bit
3526 4, // VR64Bit:subreg_h32 -> VR32Bit
3527 0, // VR64Bit:subreg_h64
3528 0, // VR64Bit:subreg_l32
3529 0, // VR64Bit:subreg_l64
3530 0, // VR64Bit:subreg_lh32
3531 0, // VR64Bit:subreg_ll32
3532 0, // VR64Bit:subreg_lh32_then_subreg_h16
3533 },
3534 { // AnyRegBit_with_subreg_h64
3535 2, // AnyRegBit_with_subreg_h64:subreg_h16 -> FP16Bit
3536 6, // AnyRegBit_with_subreg_h64:subreg_h32 -> FP32Bit
3537 17, // AnyRegBit_with_subreg_h64:subreg_h64 -> FP64Bit
3538 0, // AnyRegBit_with_subreg_h64:subreg_l32
3539 0, // AnyRegBit_with_subreg_h64:subreg_l64
3540 0, // AnyRegBit_with_subreg_h64:subreg_lh32
3541 0, // AnyRegBit_with_subreg_h64:subreg_ll32
3542 0, // AnyRegBit_with_subreg_h64:subreg_lh32_then_subreg_h16
3543 },
3544 { // CR64Bit
3545 0, // CR64Bit:subreg_h16
3546 0, // CR64Bit:subreg_h32
3547 0, // CR64Bit:subreg_h64
3548 0, // CR64Bit:subreg_l32
3549 0, // CR64Bit:subreg_l64
3550 0, // CR64Bit:subreg_lh32
3551 0, // CR64Bit:subreg_ll32
3552 0, // CR64Bit:subreg_lh32_then_subreg_h16
3553 },
3554 { // FP64Bit
3555 2, // FP64Bit:subreg_h16 -> FP16Bit
3556 6, // FP64Bit:subreg_h32 -> FP32Bit
3557 0, // FP64Bit:subreg_h64
3558 0, // FP64Bit:subreg_l32
3559 0, // FP64Bit:subreg_l64
3560 0, // FP64Bit:subreg_lh32
3561 0, // FP64Bit:subreg_ll32
3562 0, // FP64Bit:subreg_lh32_then_subreg_h16
3563 },
3564 { // GR64Bit
3565 0, // GR64Bit:subreg_h16
3566 8, // GR64Bit:subreg_h32 -> GRH32Bit
3567 0, // GR64Bit:subreg_h64
3568 7, // GR64Bit:subreg_l32 -> GR32Bit
3569 0, // GR64Bit:subreg_l64
3570 0, // GR64Bit:subreg_lh32
3571 0, // GR64Bit:subreg_ll32
3572 0, // GR64Bit:subreg_lh32_then_subreg_h16
3573 },
3574 { // ADDR64Bit
3575 0, // ADDR64Bit:subreg_h16
3576 8, // ADDR64Bit:subreg_h32 -> GRH32Bit
3577 0, // ADDR64Bit:subreg_h64
3578 9, // ADDR64Bit:subreg_l32 -> ADDR32Bit
3579 0, // ADDR64Bit:subreg_l64
3580 0, // ADDR64Bit:subreg_lh32
3581 0, // ADDR64Bit:subreg_ll32
3582 0, // ADDR64Bit:subreg_lh32_then_subreg_h16
3583 },
3584 { // VR128Bit
3585 1, // VR128Bit:subreg_h16 -> VR16Bit
3586 4, // VR128Bit:subreg_h32 -> VR32Bit
3587 14, // VR128Bit:subreg_h64 -> VR64Bit
3588 0, // VR128Bit:subreg_l32
3589 0, // VR128Bit:subreg_l64
3590 0, // VR128Bit:subreg_lh32
3591 0, // VR128Bit:subreg_ll32
3592 0, // VR128Bit:subreg_lh32_then_subreg_h16
3593 },
3594 { // VF128Bit
3595 2, // VF128Bit:subreg_h16 -> FP16Bit
3596 6, // VF128Bit:subreg_h32 -> FP32Bit
3597 17, // VF128Bit:subreg_h64 -> FP64Bit
3598 0, // VF128Bit:subreg_l32
3599 0, // VF128Bit:subreg_l64
3600 0, // VF128Bit:subreg_lh32
3601 0, // VF128Bit:subreg_ll32
3602 0, // VF128Bit:subreg_lh32_then_subreg_h16
3603 },
3604 { // FP128Bit
3605 2, // FP128Bit:subreg_h16 -> FP16Bit
3606 6, // FP128Bit:subreg_h32 -> FP32Bit
3607 17, // FP128Bit:subreg_h64 -> FP64Bit
3608 0, // FP128Bit:subreg_l32
3609 17, // FP128Bit:subreg_l64 -> FP64Bit
3610 6, // FP128Bit:subreg_lh32 -> FP32Bit
3611 0, // FP128Bit:subreg_ll32
3612 2, // FP128Bit:subreg_lh32_then_subreg_h16 -> FP16Bit
3613 },
3614 { // GR128Bit
3615 0, // GR128Bit:subreg_h16
3616 8, // GR128Bit:subreg_h32 -> GRH32Bit
3617 18, // GR128Bit:subreg_h64 -> GR64Bit
3618 7, // GR128Bit:subreg_l32 -> GR32Bit
3619 19, // GR128Bit:subreg_l64 -> ADDR64Bit
3620 8, // GR128Bit:subreg_lh32 -> GRH32Bit
3621 9, // GR128Bit:subreg_ll32 -> ADDR32Bit
3622 0, // GR128Bit:subreg_lh32_then_subreg_h16
3623 },
3624 { // ADDR128Bit
3625 0, // ADDR128Bit:subreg_h16
3626 8, // ADDR128Bit:subreg_h32 -> GRH32Bit
3627 19, // ADDR128Bit:subreg_h64 -> ADDR64Bit
3628 9, // ADDR128Bit:subreg_l32 -> ADDR32Bit
3629 19, // ADDR128Bit:subreg_l64 -> ADDR64Bit
3630 8, // ADDR128Bit:subreg_lh32 -> GRH32Bit
3631 9, // ADDR128Bit:subreg_ll32 -> ADDR32Bit
3632 0, // ADDR128Bit:subreg_lh32_then_subreg_h16
3633 },
3634 };
3635 assert(RC && "Missing regclass");
3636 if (!Idx) return RC;
3637 --Idx;
3638 assert(Idx < 8 && "Bad subreg");
3639 unsigned TV = Table[RC->getID()][Idx];
3640 return TV ? getRegClass(TV - 1) : nullptr;
3641}
3642
3643/// Get the weight in units of pressure for this register class.
3644const RegClassWeight &SystemZGenRegisterInfo::
3645getRegClassWeight(const TargetRegisterClass *RC) const {
3646 static const RegClassWeight RCWeightTable[] = {
3647 {1, 32}, // VR16Bit
3648 {1, 16}, // FP16Bit
3649 {1, 32}, // GRX32Bit
3650 {1, 32}, // VR32Bit
3651 {0, 0}, // AR32Bit
3652 {1, 16}, // FP32Bit
3653 {1, 16}, // GR32Bit
3654 {1, 16}, // GRH32Bit
3655 {1, 15}, // ADDR32Bit
3656 {0, 0}, // CCR
3657 {0, 0}, // FPCRegs
3658 {1, 48}, // AnyRegBit
3659 {1, 16}, // AnyRegBit_with_subreg_h16
3660 {1, 32}, // VR64Bit
3661 {1, 16}, // AnyRegBit_with_subreg_h64
3662 {0, 0}, // CR64Bit
3663 {1, 16}, // FP64Bit
3664 {2, 32}, // GR64Bit
3665 {2, 30}, // ADDR64Bit
3666 {1, 32}, // VR128Bit
3667 {1, 16}, // VF128Bit
3668 {2, 16}, // FP128Bit
3669 {4, 32}, // GR128Bit
3670 {4, 28}, // ADDR128Bit
3671 };
3672 return RCWeightTable[RC->getID()];
3673}
3674
3675/// Get the weight in units of pressure for this register unit.
3676unsigned SystemZGenRegisterInfo::
3677getRegUnitWeight(unsigned RegUnit) const {
3678 assert(RegUnit < 98 && "invalid register unit");
3679 // All register units have unit weight.
3680 return 1;
3681}
3682
3683
3684// Get the number of dimensions of register pressure.
3685unsigned SystemZGenRegisterInfo::getNumRegPressureSets() const {
3686 return 5;
3687}
3688
3689// Get the name of this register unit pressure set.
3690const char *SystemZGenRegisterInfo::
3691getRegPressureSetName(unsigned Idx) const {
3692 static const char *PressureNameTable[] = {
3693 "FP16Bit",
3694 "GR32Bit",
3695 "GRH32Bit",
3696 "VR16Bit",
3697 "GRX32Bit",
3698 };
3699 return PressureNameTable[Idx];
3700}
3701
3702// Get the register unit pressure limit for this dimension.
3703// This limit must be adjusted dynamically for reserved registers.
3704unsigned SystemZGenRegisterInfo::
3705getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
3706 static const uint8_t PressureLimitTable[] = {
3707 16, // 0: FP16Bit
3708 16, // 1: GR32Bit
3709 16, // 2: GRH32Bit
3710 32, // 3: VR16Bit
3711 32, // 4: GRX32Bit
3712 };
3713 return PressureLimitTable[Idx];
3714}
3715
3716/// Table of pressure sets per register class or unit.
3717static const int RCSetsTable[] = {
3718 /* 0 */ 0, 3, -1,
3719 /* 3 */ 1, 4, -1,
3720 /* 6 */ 2, 4, -1,
3721};
3722
3723/// Get the dimensions of register pressure impacted by this register class.
3724/// Returns a -1 terminated array of pressure set IDs
3725const int *SystemZGenRegisterInfo::
3726getRegClassPressureSets(const TargetRegisterClass *RC) const {
3727 static const uint8_t RCSetStartTable[] = {
3728 1,0,4,1,2,0,3,6,3,2,2,2,2,1,2,2,0,4,4,1,0,0,4,4,};
3729 return &RCSetsTable[RCSetStartTable[RC->getID()]];
3730}
3731
3732/// Get the dimensions of register pressure impacted by this register unit.
3733/// Returns a -1 terminated array of pressure set IDs
3734const int *SystemZGenRegisterInfo::
3735getRegUnitPressureSets(unsigned RegUnit) const {
3736 assert(RegUnit < 98 && "invalid register unit");
3737 static const uint8_t RUSetStartTable[] = {
3738 2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,3,6,3,6,3,6,3,6,3,6,3,6,3,6,3,6,3,6,3,6,3,6,3,6,3,6,3,6,3,6,3,6,};
3739 return &RCSetsTable[RUSetStartTable[RegUnit]];
3740}
3741
3742extern const MCRegisterDesc SystemZRegDesc[];
3743extern const int16_t SystemZRegDiffLists[];
3744extern const LaneBitmask SystemZLaneMaskLists[];
3745extern const char SystemZRegStrings[];
3746extern const char SystemZRegClassStrings[];
3747extern const MCPhysReg SystemZRegUnitRoots[][2];
3748extern const uint16_t SystemZSubRegIdxLists[];
3749extern const uint16_t SystemZRegEncodingTable[];
3750// SystemZ Dwarf<->LLVM register mappings.
3751extern const MCRegisterInfo::DwarfLLVMRegPair SystemZDwarfFlavour0Dwarf2L[];
3752extern const unsigned SystemZDwarfFlavour0Dwarf2LSize;
3753
3754extern const MCRegisterInfo::DwarfLLVMRegPair SystemZEHFlavour0Dwarf2L[];
3755extern const unsigned SystemZEHFlavour0Dwarf2LSize;
3756
3757extern const MCRegisterInfo::DwarfLLVMRegPair SystemZDwarfFlavour0L2Dwarf[];
3758extern const unsigned SystemZDwarfFlavour0L2DwarfSize;
3759
3760extern const MCRegisterInfo::DwarfLLVMRegPair SystemZEHFlavour0L2Dwarf[];
3761extern const unsigned SystemZEHFlavour0L2DwarfSize;
3762
3763SystemZGenRegisterInfo::
3764SystemZGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
3765 unsigned PC, unsigned HwMode)
3766 : TargetRegisterInfo(&SystemZRegInfoDesc, RegisterClasses, RegisterClasses+24,
3767 SubRegIndexNameTable, SubRegIdxRangeTable, SubRegIndexLaneMaskTable,
3768 LaneBitmask(0xFFFFFFFFFFFFFFFC), RegClassInfos, VTLists, HwMode) {
3769 InitMCRegisterInfo(SystemZRegDesc, 227, RA, PC,
3770 SystemZMCRegisterClasses, 24,
3771 SystemZRegUnitRoots,
3772 98,
3773 SystemZRegDiffLists,
3774 SystemZLaneMaskLists,
3775 SystemZRegStrings,
3776 SystemZRegClassStrings,
3777 SystemZSubRegIdxLists,
3778 9,
3779 SystemZRegEncodingTable);
3780
3781 switch (DwarfFlavour) {
3782 default:
3783 llvm_unreachable("Unknown DWARF flavour");
3784 case 0:
3785 mapDwarfRegsToLLVMRegs(SystemZDwarfFlavour0Dwarf2L, SystemZDwarfFlavour0Dwarf2LSize, false);
3786 break;
3787 }
3788 switch (EHFlavour) {
3789 default:
3790 llvm_unreachable("Unknown DWARF flavour");
3791 case 0:
3792 mapDwarfRegsToLLVMRegs(SystemZEHFlavour0Dwarf2L, SystemZEHFlavour0Dwarf2LSize, true);
3793 break;
3794 }
3795 switch (DwarfFlavour) {
3796 default:
3797 llvm_unreachable("Unknown DWARF flavour");
3798 case 0:
3799 mapLLVMRegsToDwarfRegs(SystemZDwarfFlavour0L2Dwarf, SystemZDwarfFlavour0L2DwarfSize, false);
3800 break;
3801 }
3802 switch (EHFlavour) {
3803 default:
3804 llvm_unreachable("Unknown DWARF flavour");
3805 case 0:
3806 mapLLVMRegsToDwarfRegs(SystemZEHFlavour0L2Dwarf, SystemZEHFlavour0L2DwarfSize, true);
3807 break;
3808 }
3809}
3810
3811static const MCPhysReg CSR_SystemZ_AllRegs_SaveList[] = { SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, SystemZ::R5D, SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D, SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D, 0 };
3812static const uint32_t CSR_SystemZ_AllRegs_RegMask[] = { 0x00000000, 0x00000000, 0x0007fff8, 0x0007fff8, 0x07fffff8, 0xe7ffe000, 0xf7ffe7ff, 0x00000007, };
3813static const MCPhysReg CSR_SystemZ_AllRegs_Vector_SaveList[] = { SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, SystemZ::R5D, SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D, SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3, SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7, SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11, SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15, SystemZ::V16, SystemZ::V17, SystemZ::V18, SystemZ::V19, SystemZ::V20, SystemZ::V21, SystemZ::V22, SystemZ::V23, SystemZ::V24, SystemZ::V25, SystemZ::V26, SystemZ::V27, SystemZ::V28, SystemZ::V29, SystemZ::V30, SystemZ::V31, 0 };
3814static const uint32_t CSR_SystemZ_AllRegs_Vector_RegMask[] = { 0x00000000, 0xfffffff8, 0xffffffff, 0xffffffff, 0xffffffff, 0xe7ffe7ff, 0xf7ffe7ff, 0x00000007, };
3815static const MCPhysReg CSR_SystemZ_ELF_SaveList[] = { SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D, 0 };
3816static const uint32_t CSR_SystemZ_ELF_RegMask[] = { 0x00000000, 0x00000000, 0x0007f800, 0x0007f800, 0x07f80780, 0x07fe0000, 0xc7fe07fe, 0x00000007, };
3817static const MCPhysReg CSR_SystemZ_NoRegs_SaveList[] = { 0 };
3818static const uint32_t CSR_SystemZ_NoRegs_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
3819static const MCPhysReg CSR_SystemZ_SwiftError_SaveList[] = { SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D, 0 };
3820static const uint32_t CSR_SystemZ_SwiftError_RegMask[] = { 0x00000000, 0x00000000, 0x0007f800, 0x0007f800, 0x07f80780, 0x07ee0000, 0x47ee07ee, 0x00000007, };
3821static const MCPhysReg CSR_SystemZ_XPLINK64_SaveList[] = { SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D, SystemZ::F15D, SystemZ::F14D, SystemZ::F13D, SystemZ::F12D, SystemZ::F11D, SystemZ::F10D, SystemZ::F9D, SystemZ::F8D, 0 };
3822static const uint32_t CSR_SystemZ_XPLINK64_RegMask[] = { 0x00000000, 0x00000000, 0x0007f800, 0x0007f800, 0x07f80780, 0x07f80000, 0x87f807f8, 0x00000007, };
3823static const MCPhysReg CSR_SystemZ_XPLINK64_Vector_SaveList[] = { SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D, SystemZ::F15D, SystemZ::F14D, SystemZ::F13D, SystemZ::F12D, SystemZ::F11D, SystemZ::F10D, SystemZ::F9D, SystemZ::F8D, SystemZ::V23, SystemZ::V22, SystemZ::V21, SystemZ::V20, SystemZ::V19, SystemZ::V18, SystemZ::V17, SystemZ::V16, 0 };
3824static const uint32_t CSR_SystemZ_XPLINK64_Vector_RegMask[] = { 0x00000000, 0x07f80000, 0x07fff800, 0x07fff800, 0xfff80780, 0x07f80007, 0x87f807f8, 0x00000007, };
3825
3826
3827ArrayRef<const uint32_t *> SystemZGenRegisterInfo::getRegMasks() const {
3828 static const uint32_t *const Masks[] = {
3829 CSR_SystemZ_AllRegs_RegMask,
3830 CSR_SystemZ_AllRegs_Vector_RegMask,
3831 CSR_SystemZ_ELF_RegMask,
3832 CSR_SystemZ_NoRegs_RegMask,
3833 CSR_SystemZ_SwiftError_RegMask,
3834 CSR_SystemZ_XPLINK64_RegMask,
3835 CSR_SystemZ_XPLINK64_Vector_RegMask,
3836 };
3837 return ArrayRef(Masks);
3838}
3839
3840bool SystemZGenRegisterInfo::
3841isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
3842 return
3843 false;
3844}
3845
3846bool SystemZGenRegisterInfo::
3847isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
3848 return
3849 false;
3850}
3851
3852bool SystemZGenRegisterInfo::
3853isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
3854 return
3855 false;
3856}
3857
3858bool SystemZGenRegisterInfo::
3859isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
3860 return
3861 false;
3862}
3863
3864bool SystemZGenRegisterInfo::
3865isConstantPhysReg(MCRegister PhysReg) const {
3866 return
3867 false;
3868}
3869
3870ArrayRef<const char *> SystemZGenRegisterInfo::getRegMaskNames() const {
3871 static const char *Names[] = {
3872 "CSR_SystemZ_AllRegs",
3873 "CSR_SystemZ_AllRegs_Vector",
3874 "CSR_SystemZ_ELF",
3875 "CSR_SystemZ_NoRegs",
3876 "CSR_SystemZ_SwiftError",
3877 "CSR_SystemZ_XPLINK64",
3878 "CSR_SystemZ_XPLINK64_Vector",
3879 };
3880 return ArrayRef(Names);
3881}
3882
3883const SystemZFrameLowering *
3884SystemZGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
3885 return static_cast<const SystemZFrameLowering *>(
3886 MF.getSubtarget().getFrameLowering());
3887}
3888
3889} // end namespace llvm
3890
3891#endif // GET_REGINFO_TARGET_DESC
3892
3893