1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Calling Convention Implementation Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifndef GET_CC_REGISTER_LISTS
10
11static bool CC_VE2(unsigned ValNo, MVT ValVT,
12 MVT LocVT, CCValAssign::LocInfo LocInfo,
13 ISD::ArgFlagsTy ArgFlags, CCState &State);
14static bool CC_VE_C(unsigned ValNo, MVT ValVT,
15 MVT LocVT, CCValAssign::LocInfo LocInfo,
16 ISD::ArgFlagsTy ArgFlags, CCState &State);
17static bool CC_VE_C_Stack(unsigned ValNo, MVT ValVT,
18 MVT LocVT, CCValAssign::LocInfo LocInfo,
19 ISD::ArgFlagsTy ArgFlags, CCState &State);
20static bool CC_VE_Fast(unsigned ValNo, MVT ValVT,
21 MVT LocVT, CCValAssign::LocInfo LocInfo,
22 ISD::ArgFlagsTy ArgFlags, CCState &State);
23static bool RetCC_VE_C(unsigned ValNo, MVT ValVT,
24 MVT LocVT, CCValAssign::LocInfo LocInfo,
25 ISD::ArgFlagsTy ArgFlags, CCState &State);
26static bool RetCC_VE_Fast(unsigned ValNo, MVT ValVT,
27 MVT LocVT, CCValAssign::LocInfo LocInfo,
28 ISD::ArgFlagsTy ArgFlags, CCState &State);
29
30
31static bool CC_VE2(unsigned ValNo, MVT ValVT,
32 MVT LocVT, CCValAssign::LocInfo LocInfo,
33 ISD::ArgFlagsTy ArgFlags, CCState &State) {
34
35 if (LocVT == MVT::i1 ||
36 LocVT == MVT::i8 ||
37 LocVT == MVT::i16 ||
38 LocVT == MVT::i32) {
39 LocVT = MVT::i64;
40 if (ArgFlags.isSExt())
41 LocInfo = CCValAssign::SExt;
42 else if (ArgFlags.isZExt())
43 LocInfo = CCValAssign::ZExt;
44 else
45 LocInfo = CCValAssign::AExt;
46 }
47
48 if (LocVT == MVT::f32) {
49 LocVT = MVT::i64;
50 LocInfo = CCValAssign::BCvt;
51 }
52
53 if (LocVT == MVT::f128) {
54 int64_t Offset1 = State.AllocateStack(Size: 16, Alignment: Align(16));
55 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset1, LocVT, HTP: LocInfo));
56 return false;
57 }
58
59 int64_t Offset2 = State.AllocateStack(
60 Size: State.getMachineFunction().getDataLayout().getTypeAllocSize(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())), Alignment: Align(8));
61 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset2, LocVT, HTP: LocInfo));
62 return false;
63
64 return true; // CC didn't match.
65}
66
67
68static bool CC_VE_C(unsigned ValNo, MVT ValVT,
69 MVT LocVT, CCValAssign::LocInfo LocInfo,
70 ISD::ArgFlagsTy ArgFlags, CCState &State) {
71
72 if (LocVT == MVT::i1 ||
73 LocVT == MVT::i8 ||
74 LocVT == MVT::i16 ||
75 LocVT == MVT::i32) {
76 LocVT = MVT::i64;
77 if (ArgFlags.isSExt())
78 LocInfo = CCValAssign::SExt;
79 else if (ArgFlags.isZExt())
80 LocInfo = CCValAssign::ZExt;
81 else
82 LocInfo = CCValAssign::AExt;
83 }
84
85 if (LocVT == MVT::f32) {
86 LocVT = MVT::i64;
87 LocInfo = CCValAssign::BCvt;
88 }
89
90 if (LocVT == MVT::i64 ||
91 LocVT == MVT::f64) {
92 static const MCPhysReg RegList1[] = {
93 VE::SX0, VE::SX1, VE::SX2, VE::SX3, VE::SX4, VE::SX5, VE::SX6, VE::SX7
94 };
95 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
96 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
97 return false;
98 }
99 }
100
101 if (LocVT == MVT::f128) {
102 static const MCPhysReg RegList2[] = {
103 VE::Q0, VE::Q1, VE::Q2, VE::Q3
104 };
105 static const MCPhysReg RegList3[] = {
106 VE::SX0, VE::SX1, VE::SX3, VE::SX5
107 };
108 if (MCRegister Reg = State.AllocateReg(Regs: RegList2, ShadowRegs: RegList3)) {
109 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
110 return false;
111 }
112 }
113
114 if (!CC_VE_C_Stack(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
115 return false;
116
117 return true; // CC didn't match.
118}
119
120
121static bool CC_VE_C_Stack(unsigned ValNo, MVT ValVT,
122 MVT LocVT, CCValAssign::LocInfo LocInfo,
123 ISD::ArgFlagsTy ArgFlags, CCState &State) {
124
125 if (LocVT == MVT::f128) {
126 static const MCPhysReg ShadowRegList1[] = {
127 VE::SX7
128 };
129 int64_t Offset2 = State.AllocateStack(Size: 16, Alignment: Align(16), ShadowRegs: ShadowRegList1);
130 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset2, LocVT, HTP: LocInfo));
131 return false;
132 }
133
134 int64_t Offset3 = State.AllocateStack(
135 Size: State.getMachineFunction().getDataLayout().getTypeAllocSize(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())), Alignment: Align(8));
136 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset3, LocVT, HTP: LocInfo));
137 return false;
138
139 return true; // CC didn't match.
140}
141
142
143static bool CC_VE_Fast(unsigned ValNo, MVT ValVT,
144 MVT LocVT, CCValAssign::LocInfo LocInfo,
145 ISD::ArgFlagsTy ArgFlags, CCState &State) {
146
147 if (LocVT == MVT::v256i32 ||
148 LocVT == MVT::v256f32 ||
149 LocVT == MVT::v256i64 ||
150 LocVT == MVT::v256f64) {
151 static const MCPhysReg RegList1[] = {
152 VE::V0, VE::V1, VE::V2, VE::V3, VE::V4, VE::V5, VE::V6, VE::V7
153 };
154 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
155 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
156 return false;
157 }
158 }
159
160 if (LocVT == MVT::v512i32 ||
161 LocVT == MVT::v512f32) {
162 static const MCPhysReg RegList2[] = {
163 VE::V0, VE::V1, VE::V2, VE::V3, VE::V4, VE::V5, VE::V6, VE::V7
164 };
165 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
166 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
167 return false;
168 }
169 }
170
171 if (LocVT == MVT::v256i1) {
172 static const MCPhysReg RegList3[] = {
173 VE::VM1, VE::VM2, VE::VM3, VE::VM4, VE::VM5, VE::VM6, VE::VM7
174 };
175 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
176 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
177 return false;
178 }
179 }
180
181 if (LocVT == MVT::v512i1) {
182 static const MCPhysReg RegList4[] = {
183 VE::VMP1, VE::VMP2, VE::VMP3
184 };
185 static const MCPhysReg RegList5[] = {
186 VE::VM1, VE::VM3, VE::VM5
187 };
188 if (MCRegister Reg = State.AllocateReg(Regs: RegList4, ShadowRegs: RegList5)) {
189 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
190 return false;
191 }
192 }
193
194 if (!CC_VE_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
195 return false;
196
197 return true; // CC didn't match.
198}
199
200
201static bool RetCC_VE_C(unsigned ValNo, MVT ValVT,
202 MVT LocVT, CCValAssign::LocInfo LocInfo,
203 ISD::ArgFlagsTy ArgFlags, CCState &State) {
204
205 if (LocVT == MVT::i1 ||
206 LocVT == MVT::i8 ||
207 LocVT == MVT::i16 ||
208 LocVT == MVT::i32) {
209 LocVT = MVT::i64;
210 if (ArgFlags.isSExt())
211 LocInfo = CCValAssign::SExt;
212 else if (ArgFlags.isZExt())
213 LocInfo = CCValAssign::ZExt;
214 else
215 LocInfo = CCValAssign::AExt;
216 }
217
218 if (LocVT == MVT::f32) {
219 LocVT = MVT::i64;
220 LocInfo = CCValAssign::BCvt;
221 }
222
223 if (LocVT == MVT::i64 ||
224 LocVT == MVT::f64) {
225 static const MCPhysReg RegList1[] = {
226 VE::SX0, VE::SX1, VE::SX2, VE::SX3, VE::SX4, VE::SX5, VE::SX6, VE::SX7
227 };
228 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
229 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
230 return false;
231 }
232 }
233
234 if (LocVT == MVT::f128) {
235 static const MCPhysReg RegList2[] = {
236 VE::Q0, VE::Q1, VE::Q2, VE::Q3
237 };
238 static const MCPhysReg RegList3[] = {
239 VE::SX0, VE::SX1, VE::SX3, VE::SX5
240 };
241 if (MCRegister Reg = State.AllocateReg(Regs: RegList2, ShadowRegs: RegList3)) {
242 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
243 return false;
244 }
245 }
246
247 return true; // CC didn't match.
248}
249
250
251static bool RetCC_VE_Fast(unsigned ValNo, MVT ValVT,
252 MVT LocVT, CCValAssign::LocInfo LocInfo,
253 ISD::ArgFlagsTy ArgFlags, CCState &State) {
254
255 if (LocVT == MVT::v256i32 ||
256 LocVT == MVT::v256f32 ||
257 LocVT == MVT::v256i64 ||
258 LocVT == MVT::v256f64) {
259 static const MCPhysReg RegList1[] = {
260 VE::V0, VE::V1, VE::V2, VE::V3, VE::V4, VE::V5, VE::V6, VE::V7
261 };
262 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
263 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
264 return false;
265 }
266 }
267
268 if (LocVT == MVT::v512i32 ||
269 LocVT == MVT::v512f32) {
270 static const MCPhysReg RegList2[] = {
271 VE::V0, VE::V1, VE::V2, VE::V3, VE::V4, VE::V5, VE::V6, VE::V7
272 };
273 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
274 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
275 return false;
276 }
277 }
278
279 if (LocVT == MVT::v256i1) {
280 static const MCPhysReg RegList3[] = {
281 VE::VM1, VE::VM2, VE::VM3, VE::VM4, VE::VM5, VE::VM6, VE::VM7
282 };
283 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
284 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
285 return false;
286 }
287 }
288
289 if (LocVT == MVT::v512i1) {
290 static const MCPhysReg RegList4[] = {
291 VE::VMP1, VE::VMP2, VE::VMP3
292 };
293 static const MCPhysReg RegList5[] = {
294 VE::VM1, VE::VM3, VE::VM5
295 };
296 if (MCRegister Reg = State.AllocateReg(Regs: RegList4, ShadowRegs: RegList5)) {
297 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
298 return false;
299 }
300 }
301
302 if (!RetCC_VE_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
303 return false;
304
305 return true; // CC didn't match.
306}
307
308#else
309
310const MCRegister CC_VE2_ArgRegs[] = { 0 };
311const MCRegister CC_VE_C_ArgRegs[] = { VE::SX0, VE::SX1, VE::SX2, VE::SX3, VE::SX4, VE::SX5, VE::SX6, VE::SX7 };
312const MCRegister CC_VE_C_Stack_ArgRegs[] = { 0 };
313const MCRegister CC_VE_Fast_ArgRegs[] = { VE::V0, VE::V1, VE::V2, VE::V3, VE::V4, VE::V5, VE::V6, VE::V7, VE::VM1, VE::VM2, VE::VM3, VE::VM4, VE::VM5, VE::VM6, VE::VM7 };
314const MCRegister RetCC_VE_C_ArgRegs[] = { VE::SX0, VE::SX1, VE::SX2, VE::SX3, VE::SX4, VE::SX5, VE::SX6, VE::SX7 };
315const MCRegister RetCC_VE_Fast_ArgRegs[] = { VE::V0, VE::V1, VE::V2, VE::V3, VE::V4, VE::V5, VE::V6, VE::V7, VE::VM1, VE::VM2, VE::VM3, VE::VM4, VE::VM5, VE::VM6, VE::VM7 };
316
317#endif // CC_REGISTER_LIST
318