1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Calling Convention Implementation Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifndef GET_CC_REGISTER_LISTS
10
11static bool CC_Intel_OCL_BI(unsigned ValNo, MVT ValVT,
12 MVT LocVT, CCValAssign::LocInfo LocInfo,
13 ISD::ArgFlagsTy ArgFlags, CCState &State);
14bool llvm::CC_X86(unsigned ValNo, MVT ValVT,
15 MVT LocVT, CCValAssign::LocInfo LocInfo,
16 ISD::ArgFlagsTy ArgFlags, CCState &State);
17static bool CC_X86_32(unsigned ValNo, MVT ValVT,
18 MVT LocVT, CCValAssign::LocInfo LocInfo,
19 ISD::ArgFlagsTy ArgFlags, CCState &State);
20static bool CC_X86_32_C(unsigned ValNo, MVT ValVT,
21 MVT LocVT, CCValAssign::LocInfo LocInfo,
22 ISD::ArgFlagsTy ArgFlags, CCState &State);
23static bool CC_X86_32_Common(unsigned ValNo, MVT ValVT,
24 MVT LocVT, CCValAssign::LocInfo LocInfo,
25 ISD::ArgFlagsTy ArgFlags, CCState &State);
26static bool CC_X86_32_FastCC(unsigned ValNo, MVT ValVT,
27 MVT LocVT, CCValAssign::LocInfo LocInfo,
28 ISD::ArgFlagsTy ArgFlags, CCState &State);
29static bool CC_X86_32_FastCall(unsigned ValNo, MVT ValVT,
30 MVT LocVT, CCValAssign::LocInfo LocInfo,
31 ISD::ArgFlagsTy ArgFlags, CCState &State);
32static bool CC_X86_32_GHC(unsigned ValNo, MVT ValVT,
33 MVT LocVT, CCValAssign::LocInfo LocInfo,
34 ISD::ArgFlagsTy ArgFlags, CCState &State);
35static bool CC_X86_32_HiPE(unsigned ValNo, MVT ValVT,
36 MVT LocVT, CCValAssign::LocInfo LocInfo,
37 ISD::ArgFlagsTy ArgFlags, CCState &State);
38static bool CC_X86_32_MCU(unsigned ValNo, MVT ValVT,
39 MVT LocVT, CCValAssign::LocInfo LocInfo,
40 ISD::ArgFlagsTy ArgFlags, CCState &State);
41static bool CC_X86_32_RegCall(unsigned ValNo, MVT ValVT,
42 MVT LocVT, CCValAssign::LocInfo LocInfo,
43 ISD::ArgFlagsTy ArgFlags, CCState &State);
44static bool CC_X86_32_RegCallv4_Win(unsigned ValNo, MVT ValVT,
45 MVT LocVT, CCValAssign::LocInfo LocInfo,
46 ISD::ArgFlagsTy ArgFlags, CCState &State);
47static bool CC_X86_32_ThisCall(unsigned ValNo, MVT ValVT,
48 MVT LocVT, CCValAssign::LocInfo LocInfo,
49 ISD::ArgFlagsTy ArgFlags, CCState &State);
50static bool CC_X86_32_ThisCall_Common(unsigned ValNo, MVT ValVT,
51 MVT LocVT, CCValAssign::LocInfo LocInfo,
52 ISD::ArgFlagsTy ArgFlags, CCState &State);
53static bool CC_X86_32_ThisCall_Mingw(unsigned ValNo, MVT ValVT,
54 MVT LocVT, CCValAssign::LocInfo LocInfo,
55 ISD::ArgFlagsTy ArgFlags, CCState &State);
56static bool CC_X86_32_ThisCall_Win(unsigned ValNo, MVT ValVT,
57 MVT LocVT, CCValAssign::LocInfo LocInfo,
58 ISD::ArgFlagsTy ArgFlags, CCState &State);
59static bool CC_X86_32_Vector_Common(unsigned ValNo, MVT ValVT,
60 MVT LocVT, CCValAssign::LocInfo LocInfo,
61 ISD::ArgFlagsTy ArgFlags, CCState &State);
62static bool CC_X86_32_Vector_Darwin(unsigned ValNo, MVT ValVT,
63 MVT LocVT, CCValAssign::LocInfo LocInfo,
64 ISD::ArgFlagsTy ArgFlags, CCState &State);
65static bool CC_X86_32_Vector_Standard(unsigned ValNo, MVT ValVT,
66 MVT LocVT, CCValAssign::LocInfo LocInfo,
67 ISD::ArgFlagsTy ArgFlags, CCState &State);
68static bool CC_X86_64(unsigned ValNo, MVT ValVT,
69 MVT LocVT, CCValAssign::LocInfo LocInfo,
70 ISD::ArgFlagsTy ArgFlags, CCState &State);
71static bool CC_X86_64_AnyReg(unsigned ValNo, MVT ValVT,
72 MVT LocVT, CCValAssign::LocInfo LocInfo,
73 ISD::ArgFlagsTy ArgFlags, CCState &State);
74static bool CC_X86_64_C(unsigned ValNo, MVT ValVT,
75 MVT LocVT, CCValAssign::LocInfo LocInfo,
76 ISD::ArgFlagsTy ArgFlags, CCState &State);
77static bool CC_X86_64_GHC(unsigned ValNo, MVT ValVT,
78 MVT LocVT, CCValAssign::LocInfo LocInfo,
79 ISD::ArgFlagsTy ArgFlags, CCState &State);
80static bool CC_X86_64_HiPE(unsigned ValNo, MVT ValVT,
81 MVT LocVT, CCValAssign::LocInfo LocInfo,
82 ISD::ArgFlagsTy ArgFlags, CCState &State);
83static bool CC_X86_64_Preserve_None(unsigned ValNo, MVT ValVT,
84 MVT LocVT, CCValAssign::LocInfo LocInfo,
85 ISD::ArgFlagsTy ArgFlags, CCState &State);
86static bool CC_X86_SysV64_RegCall(unsigned ValNo, MVT ValVT,
87 MVT LocVT, CCValAssign::LocInfo LocInfo,
88 ISD::ArgFlagsTy ArgFlags, CCState &State);
89static bool CC_X86_Win32_CFGuard_Check(unsigned ValNo, MVT ValVT,
90 MVT LocVT, CCValAssign::LocInfo LocInfo,
91 ISD::ArgFlagsTy ArgFlags, CCState &State);
92static bool CC_X86_Win32_Vector(unsigned ValNo, MVT ValVT,
93 MVT LocVT, CCValAssign::LocInfo LocInfo,
94 ISD::ArgFlagsTy ArgFlags, CCState &State);
95static bool CC_X86_Win32_VectorCall(unsigned ValNo, MVT ValVT,
96 MVT LocVT, CCValAssign::LocInfo LocInfo,
97 ISD::ArgFlagsTy ArgFlags, CCState &State);
98static bool CC_X86_Win64_C(unsigned ValNo, MVT ValVT,
99 MVT LocVT, CCValAssign::LocInfo LocInfo,
100 ISD::ArgFlagsTy ArgFlags, CCState &State);
101static bool CC_X86_Win64_RegCall(unsigned ValNo, MVT ValVT,
102 MVT LocVT, CCValAssign::LocInfo LocInfo,
103 ISD::ArgFlagsTy ArgFlags, CCState &State);
104static bool CC_X86_Win64_RegCallv4(unsigned ValNo, MVT ValVT,
105 MVT LocVT, CCValAssign::LocInfo LocInfo,
106 ISD::ArgFlagsTy ArgFlags, CCState &State);
107static bool CC_X86_Win64_VectorCall(unsigned ValNo, MVT ValVT,
108 MVT LocVT, CCValAssign::LocInfo LocInfo,
109 ISD::ArgFlagsTy ArgFlags, CCState &State);
110static bool RetCC_Intel_OCL_BI(unsigned ValNo, MVT ValVT,
111 MVT LocVT, CCValAssign::LocInfo LocInfo,
112 ISD::ArgFlagsTy ArgFlags, CCState &State);
113bool llvm::RetCC_X86(unsigned ValNo, MVT ValVT,
114 MVT LocVT, CCValAssign::LocInfo LocInfo,
115 ISD::ArgFlagsTy ArgFlags, CCState &State);
116static bool RetCC_X86Common(unsigned ValNo, MVT ValVT,
117 MVT LocVT, CCValAssign::LocInfo LocInfo,
118 ISD::ArgFlagsTy ArgFlags, CCState &State);
119static bool RetCC_X86_32(unsigned ValNo, MVT ValVT,
120 MVT LocVT, CCValAssign::LocInfo LocInfo,
121 ISD::ArgFlagsTy ArgFlags, CCState &State);
122static bool RetCC_X86_32_C(unsigned ValNo, MVT ValVT,
123 MVT LocVT, CCValAssign::LocInfo LocInfo,
124 ISD::ArgFlagsTy ArgFlags, CCState &State);
125static bool RetCC_X86_32_Fast(unsigned ValNo, MVT ValVT,
126 MVT LocVT, CCValAssign::LocInfo LocInfo,
127 ISD::ArgFlagsTy ArgFlags, CCState &State);
128static bool RetCC_X86_32_HiPE(unsigned ValNo, MVT ValVT,
129 MVT LocVT, CCValAssign::LocInfo LocInfo,
130 ISD::ArgFlagsTy ArgFlags, CCState &State);
131static bool RetCC_X86_32_RegCall(unsigned ValNo, MVT ValVT,
132 MVT LocVT, CCValAssign::LocInfo LocInfo,
133 ISD::ArgFlagsTy ArgFlags, CCState &State);
134static bool RetCC_X86_32_RegCallv4_Win(unsigned ValNo, MVT ValVT,
135 MVT LocVT, CCValAssign::LocInfo LocInfo,
136 ISD::ArgFlagsTy ArgFlags, CCState &State);
137static bool RetCC_X86_32_VectorCall(unsigned ValNo, MVT ValVT,
138 MVT LocVT, CCValAssign::LocInfo LocInfo,
139 ISD::ArgFlagsTy ArgFlags, CCState &State);
140static bool RetCC_X86_64(unsigned ValNo, MVT ValVT,
141 MVT LocVT, CCValAssign::LocInfo LocInfo,
142 ISD::ArgFlagsTy ArgFlags, CCState &State);
143static bool RetCC_X86_64_AnyReg(unsigned ValNo, MVT ValVT,
144 MVT LocVT, CCValAssign::LocInfo LocInfo,
145 ISD::ArgFlagsTy ArgFlags, CCState &State);
146static bool RetCC_X86_64_C(unsigned ValNo, MVT ValVT,
147 MVT LocVT, CCValAssign::LocInfo LocInfo,
148 ISD::ArgFlagsTy ArgFlags, CCState &State);
149static bool RetCC_X86_64_HiPE(unsigned ValNo, MVT ValVT,
150 MVT LocVT, CCValAssign::LocInfo LocInfo,
151 ISD::ArgFlagsTy ArgFlags, CCState &State);
152static bool RetCC_X86_64_Swift(unsigned ValNo, MVT ValVT,
153 MVT LocVT, CCValAssign::LocInfo LocInfo,
154 ISD::ArgFlagsTy ArgFlags, CCState &State);
155static bool RetCC_X86_64_Vectorcall(unsigned ValNo, MVT ValVT,
156 MVT LocVT, CCValAssign::LocInfo LocInfo,
157 ISD::ArgFlagsTy ArgFlags, CCState &State);
158static bool RetCC_X86_SysV64_RegCall(unsigned ValNo, MVT ValVT,
159 MVT LocVT, CCValAssign::LocInfo LocInfo,
160 ISD::ArgFlagsTy ArgFlags, CCState &State);
161static bool RetCC_X86_Win64_C(unsigned ValNo, MVT ValVT,
162 MVT LocVT, CCValAssign::LocInfo LocInfo,
163 ISD::ArgFlagsTy ArgFlags, CCState &State);
164static bool RetCC_X86_Win64_RegCall(unsigned ValNo, MVT ValVT,
165 MVT LocVT, CCValAssign::LocInfo LocInfo,
166 ISD::ArgFlagsTy ArgFlags, CCState &State);
167static bool RetCC_X86_Win64_RegCallv4(unsigned ValNo, MVT ValVT,
168 MVT LocVT, CCValAssign::LocInfo LocInfo,
169 ISD::ArgFlagsTy ArgFlags, CCState &State);
170
171
172static bool CC_Intel_OCL_BI(unsigned ValNo, MVT ValVT,
173 MVT LocVT, CCValAssign::LocInfo LocInfo,
174 ISD::ArgFlagsTy ArgFlags, CCState &State) {
175
176 if (LocVT == MVT::i32) {
177 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetWin64()) {
178 static const MCPhysReg RegList1[] = {
179 X86::ECX, X86::EDX, X86::R8D, X86::R9D
180 };
181 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
182 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
183 return false;
184 }
185 }
186 }
187
188 if (LocVT == MVT::i64) {
189 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetWin64()) {
190 static const MCPhysReg RegList2[] = {
191 X86::RCX, X86::RDX, X86::R8, X86::R9
192 };
193 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
194 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
195 return false;
196 }
197 }
198 }
199
200 if (LocVT == MVT::i32) {
201 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
202 static const MCPhysReg RegList3[] = {
203 X86::EDI, X86::ESI, X86::EDX, X86::ECX
204 };
205 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
206 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
207 return false;
208 }
209 }
210 }
211
212 if (LocVT == MVT::i64) {
213 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
214 static const MCPhysReg RegList4[] = {
215 X86::RDI, X86::RSI, X86::RDX, X86::RCX
216 };
217 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
218 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
219 return false;
220 }
221 }
222 }
223
224 if (LocVT == MVT::i32) {
225 int64_t Offset5 = State.AllocateStack(Size: 4, Alignment: Align(4));
226 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset5, LocVT, HTP: LocInfo));
227 return false;
228 }
229
230 if (LocVT == MVT::f32 ||
231 LocVT == MVT::f64 ||
232 LocVT == MVT::v4i32 ||
233 LocVT == MVT::v2i64 ||
234 LocVT == MVT::v4f32 ||
235 LocVT == MVT::v2f64) {
236 static const MCPhysReg RegList6[] = {
237 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
238 };
239 if (MCRegister Reg = State.AllocateReg(Regs: RegList6)) {
240 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
241 return false;
242 }
243 }
244
245 if (LocVT == MVT::v8f32 ||
246 LocVT == MVT::v4f64 ||
247 LocVT == MVT::v8i32 ||
248 LocVT == MVT::v4i64) {
249 static const MCPhysReg RegList7[] = {
250 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3
251 };
252 if (MCRegister Reg = State.AllocateReg(Regs: RegList7)) {
253 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
254 return false;
255 }
256 }
257
258 if (LocVT == MVT::v16f32 ||
259 LocVT == MVT::v8f64 ||
260 LocVT == MVT::v16i32 ||
261 LocVT == MVT::v8i64) {
262 static const MCPhysReg RegList8[] = {
263 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3
264 };
265 if (MCRegister Reg = State.AllocateReg(Regs: RegList8)) {
266 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
267 return false;
268 }
269 }
270
271 if (LocVT == MVT::v16i1 ||
272 LocVT == MVT::v8i1) {
273 if (MCRegister Reg = State.AllocateReg(Reg: X86::K1)) {
274 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
275 return false;
276 }
277 }
278
279 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetWin64()) {
280 if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
281 return false;
282 }
283
284 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
285 if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
286 return false;
287 }
288
289 if (!CC_X86_32_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
290 return false;
291
292 return true; // CC didn't match.
293}
294
295
296bool llvm::CC_X86(unsigned ValNo, MVT ValVT,
297 MVT LocVT, CCValAssign::LocInfo LocInfo,
298 ISD::ArgFlagsTy ArgFlags, CCState &State) {
299
300 if (State.getCallingConv() == CallingConv::Intel_OCL_BI) {
301 if (!CC_Intel_OCL_BI(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
302 return false;
303 }
304
305 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
306 if (!CC_X86_64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
307 return false;
308 }
309
310 if (!CC_X86_32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
311 return false;
312
313 return true; // CC didn't match.
314}
315
316
317static bool CC_X86_32(unsigned ValNo, MVT ValVT,
318 MVT LocVT, CCValAssign::LocInfo LocInfo,
319 ISD::ArgFlagsTy ArgFlags, CCState &State) {
320
321 if (State.getCallingConv() == CallingConv::X86_INTR) {
322 if (CC_X86_Intr(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
323 return false;
324 }
325
326 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetMCU()) {
327 if (!CC_X86_32_MCU(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
328 return false;
329 }
330
331 if (State.getCallingConv() == CallingConv::X86_FastCall) {
332 if (!CC_X86_32_FastCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
333 return false;
334 }
335
336 if (State.getCallingConv() == CallingConv::X86_VectorCall) {
337 if (!CC_X86_Win32_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
338 return false;
339 }
340
341 if (State.getCallingConv() == CallingConv::X86_ThisCall) {
342 if (!CC_X86_32_ThisCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
343 return false;
344 }
345
346 if (State.getCallingConv() == CallingConv::CFGuard_Check) {
347 if (!CC_X86_Win32_CFGuard_Check(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
348 return false;
349 }
350
351 if (State.getCallingConv() == CallingConv::Fast) {
352 if (!CC_X86_32_FastCC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
353 return false;
354 }
355
356 if (State.getCallingConv() == CallingConv::Tail) {
357 if (!CC_X86_32_FastCC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
358 return false;
359 }
360
361 if (State.getCallingConv() == CallingConv::GHC) {
362 if (!CC_X86_32_GHC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
363 return false;
364 }
365
366 if (State.getCallingConv() == CallingConv::HiPE) {
367 if (!CC_X86_32_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
368 return false;
369 }
370
371 if (State.getCallingConv() == CallingConv::X86_RegCall) {
372 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetWin32()) {
373 if (State.getMachineFunction().getFunction().getParent()->getModuleFlag(Key: "RegCallv4")!=nullptr) {
374 if (!CC_X86_32_RegCallv4_Win(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
375 return false;
376 }
377 }
378 }
379
380 if (State.getCallingConv() == CallingConv::X86_RegCall) {
381 if (!CC_X86_32_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
382 return false;
383 }
384
385 if (!CC_X86_32_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
386 return false;
387
388 return true; // CC didn't match.
389}
390
391
392static bool CC_X86_32_C(unsigned ValNo, MVT ValVT,
393 MVT LocVT, CCValAssign::LocInfo LocInfo,
394 ISD::ArgFlagsTy ArgFlags, CCState &State) {
395
396 if (LocVT == MVT::i1 ||
397 LocVT == MVT::i8 ||
398 LocVT == MVT::i16 ||
399 LocVT == MVT::v1i1) {
400 LocVT = MVT::i32;
401 if (ArgFlags.isSExt())
402 LocInfo = CCValAssign::SExt;
403 else if (ArgFlags.isZExt())
404 LocInfo = CCValAssign::ZExt;
405 else
406 LocInfo = CCValAssign::AExt;
407 }
408
409 if (ArgFlags.isNest()) {
410 if (MCRegister Reg = State.AllocateReg(Reg: X86::ECX)) {
411 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
412 return false;
413 }
414 }
415
416 if (State.getCallingConv() == CallingConv::SwiftTail) {
417 if (ArgFlags.isSwiftSelf()) {
418 if (LocVT == MVT::i32) {
419 if (MCRegister Reg = State.AllocateReg(Reg: X86::ECX)) {
420 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
421 return false;
422 }
423 }
424 }
425 }
426
427 if (!State.isVarArg()) {
428 if (ArgFlags.isInReg()) {
429 if (LocVT == MVT::i32) {
430 static const MCPhysReg RegList1[] = {
431 X86::EAX, X86::EDX, X86::ECX
432 };
433 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
434 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
435 return false;
436 }
437 }
438 }
439 }
440
441 if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
442 return false;
443
444 return true; // CC didn't match.
445}
446
447
448static bool CC_X86_32_Common(unsigned ValNo, MVT ValVT,
449 MVT LocVT, CCValAssign::LocInfo LocInfo,
450 ISD::ArgFlagsTy ArgFlags, CCState &State) {
451
452 if (ArgFlags.isByVal()) {
453 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 4, MinAlign: Align(4), ArgFlags);
454 return false;
455 }
456
457 if (ArgFlags.isPreallocated()) {
458 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 4, MinAlign: Align(4), ArgFlags);
459 return false;
460 }
461
462 if (!State.isVarArg()) {
463 if (ArgFlags.isInReg()) {
464 if (LocVT == MVT::f32 ||
465 LocVT == MVT::f64) {
466 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE2()) {
467 static const MCPhysReg RegList1[] = {
468 X86::XMM0, X86::XMM1, X86::XMM2
469 };
470 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
471 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
472 return false;
473 }
474 }
475 }
476 }
477 }
478
479 if (!State.isVarArg()) {
480 if (ArgFlags.isInReg()) {
481 if (LocVT == MVT::f16) {
482 static const MCPhysReg RegList2[] = {
483 X86::XMM0, X86::XMM1, X86::XMM2
484 };
485 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
486 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
487 return false;
488 }
489 }
490 }
491 }
492
493 if (LocVT == MVT::f16) {
494 int64_t Offset3 = State.AllocateStack(Size: 4, Alignment: Align(4));
495 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset3, LocVT, HTP: LocInfo));
496 return false;
497 }
498
499 if (LocVT == MVT::i32 ||
500 LocVT == MVT::f32) {
501 int64_t Offset4 = State.AllocateStack(Size: 4, Alignment: Align(4));
502 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset4, LocVT, HTP: LocInfo));
503 return false;
504 }
505
506 if (LocVT == MVT::f64) {
507 int64_t Offset5 = State.AllocateStack(Size: 8, Alignment: Align(4));
508 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset5, LocVT, HTP: LocInfo));
509 return false;
510 }
511
512 if (LocVT == MVT::f80) {
513 int64_t Offset6 = State.AllocateStack(
514 Size: State.getMachineFunction().getDataLayout().getTypeAllocSize(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())),
515 Alignment: State.getMachineFunction().getDataLayout().getABITypeAlign(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())));
516 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset6, LocVT, HTP: LocInfo));
517 return false;
518 }
519
520 if (LocVT == MVT::v2i1) {
521 LocVT = MVT::v2i64;
522 if (ArgFlags.isSExt())
523 LocInfo = CCValAssign::SExt;
524 else if (ArgFlags.isZExt())
525 LocInfo = CCValAssign::ZExt;
526 else
527 LocInfo = CCValAssign::AExt;
528 }
529
530 if (LocVT == MVT::v4i1) {
531 LocVT = MVT::v4i32;
532 if (ArgFlags.isSExt())
533 LocInfo = CCValAssign::SExt;
534 else if (ArgFlags.isZExt())
535 LocInfo = CCValAssign::ZExt;
536 else
537 LocInfo = CCValAssign::AExt;
538 }
539
540 if (LocVT == MVT::v8i1) {
541 LocVT = MVT::v8i16;
542 if (ArgFlags.isSExt())
543 LocInfo = CCValAssign::SExt;
544 else if (ArgFlags.isZExt())
545 LocInfo = CCValAssign::ZExt;
546 else
547 LocInfo = CCValAssign::AExt;
548 }
549
550 if (LocVT == MVT::v16i1) {
551 LocVT = MVT::v16i8;
552 if (ArgFlags.isSExt())
553 LocInfo = CCValAssign::SExt;
554 else if (ArgFlags.isZExt())
555 LocInfo = CCValAssign::ZExt;
556 else
557 LocInfo = CCValAssign::AExt;
558 }
559
560 if (LocVT == MVT::v32i1) {
561 LocVT = MVT::v32i8;
562 if (ArgFlags.isSExt())
563 LocInfo = CCValAssign::SExt;
564 else if (ArgFlags.isZExt())
565 LocInfo = CCValAssign::ZExt;
566 else
567 LocInfo = CCValAssign::AExt;
568 }
569
570 if (LocVT == MVT::v64i1) {
571 LocVT = MVT::v64i8;
572 if (ArgFlags.isSExt())
573 LocInfo = CCValAssign::SExt;
574 else if (ArgFlags.isZExt())
575 LocInfo = CCValAssign::ZExt;
576 else
577 LocInfo = CCValAssign::AExt;
578 }
579
580 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetDarwin()) {
581 if (!CC_X86_32_Vector_Darwin(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
582 return false;
583 }
584
585 if (!CC_X86_32_Vector_Standard(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
586 return false;
587
588 return true; // CC didn't match.
589}
590
591
592static bool CC_X86_32_FastCC(unsigned ValNo, MVT ValVT,
593 MVT LocVT, CCValAssign::LocInfo LocInfo,
594 ISD::ArgFlagsTy ArgFlags, CCState &State) {
595
596 if (ArgFlags.isByVal()) {
597 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 4, MinAlign: Align(4), ArgFlags);
598 return false;
599 }
600
601 if (LocVT == MVT::i1 ||
602 LocVT == MVT::i8 ||
603 LocVT == MVT::i16 ||
604 LocVT == MVT::v1i1) {
605 LocVT = MVT::i32;
606 if (ArgFlags.isSExt())
607 LocInfo = CCValAssign::SExt;
608 else if (ArgFlags.isZExt())
609 LocInfo = CCValAssign::ZExt;
610 else
611 LocInfo = CCValAssign::AExt;
612 }
613
614 if (ArgFlags.isNest()) {
615 if (MCRegister Reg = State.AllocateReg(Reg: X86::EAX)) {
616 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
617 return false;
618 }
619 }
620
621 if (LocVT == MVT::i32) {
622 static const MCPhysReg RegList1[] = {
623 X86::ECX, X86::EDX
624 };
625 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
626 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
627 return false;
628 }
629 }
630
631 if (!State.isVarArg()) {
632 if (LocVT == MVT::f32 ||
633 LocVT == MVT::f64) {
634 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE2()) {
635 static const MCPhysReg RegList2[] = {
636 X86::XMM0, X86::XMM1, X86::XMM2
637 };
638 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
639 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
640 return false;
641 }
642 }
643 }
644 }
645
646 if (LocVT == MVT::f64) {
647 int64_t Offset3 = State.AllocateStack(Size: 8, Alignment: Align(8));
648 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset3, LocVT, HTP: LocInfo));
649 return false;
650 }
651
652 if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
653 return false;
654
655 return true; // CC didn't match.
656}
657
658
659static bool CC_X86_32_FastCall(unsigned ValNo, MVT ValVT,
660 MVT LocVT, CCValAssign::LocInfo LocInfo,
661 ISD::ArgFlagsTy ArgFlags, CCState &State) {
662
663 if (LocVT == MVT::i1) {
664 LocVT = MVT::i8;
665 if (ArgFlags.isSExt())
666 LocInfo = CCValAssign::SExt;
667 else if (ArgFlags.isZExt())
668 LocInfo = CCValAssign::ZExt;
669 else
670 LocInfo = CCValAssign::AExt;
671 }
672
673 if (ArgFlags.isNest()) {
674 if (MCRegister Reg = State.AllocateReg(Reg: X86::EAX)) {
675 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
676 return false;
677 }
678 }
679
680 if (ArgFlags.isInReg()) {
681 if (LocVT == MVT::i8) {
682 static const MCPhysReg RegList1[] = {
683 X86::CL, X86::DL
684 };
685 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
686 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
687 return false;
688 }
689 }
690 }
691
692 if (ArgFlags.isInReg()) {
693 if (LocVT == MVT::i16) {
694 static const MCPhysReg RegList2[] = {
695 X86::CX, X86::DX
696 };
697 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
698 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
699 return false;
700 }
701 }
702 }
703
704 if (ArgFlags.isInReg()) {
705 if (LocVT == MVT::i32) {
706 static const MCPhysReg RegList3[] = {
707 X86::ECX, X86::EDX
708 };
709 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
710 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
711 return false;
712 }
713 }
714 }
715
716 if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
717 return false;
718
719 return true; // CC didn't match.
720}
721
722
723static bool CC_X86_32_GHC(unsigned ValNo, MVT ValVT,
724 MVT LocVT, CCValAssign::LocInfo LocInfo,
725 ISD::ArgFlagsTy ArgFlags, CCState &State) {
726
727 if (LocVT == MVT::i8 ||
728 LocVT == MVT::i16) {
729 LocVT = MVT::i32;
730 if (ArgFlags.isSExt())
731 LocInfo = CCValAssign::SExt;
732 else if (ArgFlags.isZExt())
733 LocInfo = CCValAssign::ZExt;
734 else
735 LocInfo = CCValAssign::AExt;
736 }
737
738 if (LocVT == MVT::i32) {
739 static const MCPhysReg RegList1[] = {
740 X86::EBX, X86::EBP, X86::EDI, X86::ESI
741 };
742 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
743 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
744 return false;
745 }
746 }
747
748 return true; // CC didn't match.
749}
750
751
752static bool CC_X86_32_HiPE(unsigned ValNo, MVT ValVT,
753 MVT LocVT, CCValAssign::LocInfo LocInfo,
754 ISD::ArgFlagsTy ArgFlags, CCState &State) {
755
756 if (LocVT == MVT::i8 ||
757 LocVT == MVT::i16) {
758 LocVT = MVT::i32;
759 if (ArgFlags.isSExt())
760 LocInfo = CCValAssign::SExt;
761 else if (ArgFlags.isZExt())
762 LocInfo = CCValAssign::ZExt;
763 else
764 LocInfo = CCValAssign::AExt;
765 }
766
767 if (LocVT == MVT::i32) {
768 static const MCPhysReg RegList1[] = {
769 X86::ESI, X86::EBP, X86::EAX, X86::EDX, X86::ECX
770 };
771 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
772 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
773 return false;
774 }
775 }
776
777 if (LocVT == MVT::i32 ||
778 LocVT == MVT::f32) {
779 int64_t Offset2 = State.AllocateStack(Size: 4, Alignment: Align(4));
780 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset2, LocVT, HTP: LocInfo));
781 return false;
782 }
783
784 return true; // CC didn't match.
785}
786
787
788static bool CC_X86_32_MCU(unsigned ValNo, MVT ValVT,
789 MVT LocVT, CCValAssign::LocInfo LocInfo,
790 ISD::ArgFlagsTy ArgFlags, CCState &State) {
791
792 if (ArgFlags.isByVal()) {
793 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 4, MinAlign: Align(4), ArgFlags);
794 return false;
795 }
796
797 if (LocVT == MVT::i1 ||
798 LocVT == MVT::i8 ||
799 LocVT == MVT::i16 ||
800 LocVT == MVT::v1i1) {
801 LocVT = MVT::i32;
802 if (ArgFlags.isSExt())
803 LocInfo = CCValAssign::SExt;
804 else if (ArgFlags.isZExt())
805 LocInfo = CCValAssign::ZExt;
806 else
807 LocInfo = CCValAssign::AExt;
808 }
809
810 if (!State.isVarArg()) {
811 if (LocVT == MVT::i32) {
812 if (CC_X86_32_MCUInReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
813 return false;
814 }
815 }
816
817 if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
818 return false;
819
820 return true; // CC didn't match.
821}
822
823
824static bool CC_X86_32_RegCall(unsigned ValNo, MVT ValVT,
825 MVT LocVT, CCValAssign::LocInfo LocInfo,
826 ISD::ArgFlagsTy ArgFlags, CCState &State) {
827
828 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
829 if (ArgFlags.isByVal()) {
830 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 8, MinAlign: Align(8), ArgFlags);
831 return false;
832 }
833 }
834
835 if (ArgFlags.isByVal()) {
836 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 4, MinAlign: Align(4), ArgFlags);
837 return false;
838 }
839
840 if (LocVT == MVT::i1 ||
841 LocVT == MVT::i8 ||
842 LocVT == MVT::i16 ||
843 LocVT == MVT::v1i1) {
844 LocVT = MVT::i32;
845 if (ArgFlags.isSExt())
846 LocInfo = CCValAssign::SExt;
847 else if (ArgFlags.isZExt())
848 LocInfo = CCValAssign::ZExt;
849 else
850 LocInfo = CCValAssign::AExt;
851 }
852
853 if (LocVT == MVT::v8i1 ||
854 LocVT == MVT::v16i1 ||
855 LocVT == MVT::v32i1) {
856 LocVT = MVT::i32;
857 if (ArgFlags.isSExt())
858 LocInfo = CCValAssign::SExt;
859 else if (ArgFlags.isZExt())
860 LocInfo = CCValAssign::ZExt;
861 else
862 LocInfo = CCValAssign::AExt;
863 }
864
865 if (LocVT == MVT::i32) {
866 static const MCPhysReg RegList1[] = {
867 X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI
868 };
869 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
870 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
871 return false;
872 }
873 }
874
875 if (LocVT == MVT::i64) {
876 if (MCRegister Reg = State.AllocateReg(Reg: X86::RAX)) {
877 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
878 return false;
879 }
880 }
881
882 if (LocVT == MVT::v64i1) {
883 LocVT = MVT::i64;
884 if (ArgFlags.isSExt())
885 LocInfo = CCValAssign::SExt;
886 else if (ArgFlags.isZExt())
887 LocInfo = CCValAssign::ZExt;
888 else
889 LocInfo = CCValAssign::AExt;
890 }
891
892 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
893 if (LocVT == MVT::i64) {
894 if (MCRegister Reg = State.AllocateReg(Reg: X86::RAX)) {
895 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
896 return false;
897 }
898 }
899 }
900
901 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is32Bit()) {
902 if (LocVT == MVT::i64) {
903 if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
904 return false;
905 }
906 }
907
908 if (LocVT == MVT::f32 ||
909 LocVT == MVT::f64 ||
910 LocVT == MVT::f128) {
911 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
912 static const MCPhysReg RegList2[] = {
913 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
914 };
915 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
916 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
917 return false;
918 }
919 }
920 }
921
922 if (LocVT == MVT::f80) {
923 if (MCRegister Reg = State.AllocateReg(Reg: X86::FP0)) {
924 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
925 return false;
926 }
927 }
928
929 if (LocVT == MVT::v16i8 ||
930 LocVT == MVT::v8i16 ||
931 LocVT == MVT::v4i32 ||
932 LocVT == MVT::v2i64 ||
933 LocVT == MVT::v4f32 ||
934 LocVT == MVT::v2f64) {
935 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
936 static const MCPhysReg RegList3[] = {
937 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
938 };
939 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
940 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
941 return false;
942 }
943 }
944 }
945
946 if (LocVT == MVT::v32i8 ||
947 LocVT == MVT::v16i16 ||
948 LocVT == MVT::v8i32 ||
949 LocVT == MVT::v4i64 ||
950 LocVT == MVT::v8f32 ||
951 LocVT == MVT::v4f64) {
952 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX()) {
953 static const MCPhysReg RegList4[] = {
954 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7
955 };
956 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
957 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
958 return false;
959 }
960 }
961 }
962
963 if (LocVT == MVT::v64i8 ||
964 LocVT == MVT::v32i16 ||
965 LocVT == MVT::v16i32 ||
966 LocVT == MVT::v8i64 ||
967 LocVT == MVT::v16f32 ||
968 LocVT == MVT::v8f64) {
969 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX512()) {
970 static const MCPhysReg RegList5[] = {
971 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7
972 };
973 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
974 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
975 return false;
976 }
977 }
978 }
979
980 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
981 if (LocVT == MVT::i32 ||
982 LocVT == MVT::i64 ||
983 LocVT == MVT::f32 ||
984 LocVT == MVT::f64) {
985 int64_t Offset6 = State.AllocateStack(Size: 8, Alignment: Align(8));
986 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset6, LocVT, HTP: LocInfo));
987 return false;
988 }
989 }
990
991 if (LocVT == MVT::i32 ||
992 LocVT == MVT::f32) {
993 int64_t Offset7 = State.AllocateStack(Size: 4, Alignment: Align(4));
994 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset7, LocVT, HTP: LocInfo));
995 return false;
996 }
997
998 if (LocVT == MVT::i64 ||
999 LocVT == MVT::f64) {
1000 int64_t Offset8 = State.AllocateStack(Size: 8, Alignment: Align(4));
1001 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset8, LocVT, HTP: LocInfo));
1002 return false;
1003 }
1004
1005 if (LocVT == MVT::f80 ||
1006 LocVT == MVT::f128) {
1007 int64_t Offset9 = State.AllocateStack(
1008 Size: State.getMachineFunction().getDataLayout().getTypeAllocSize(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())),
1009 Alignment: State.getMachineFunction().getDataLayout().getABITypeAlign(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())));
1010 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset9, LocVT, HTP: LocInfo));
1011 return false;
1012 }
1013
1014 if (LocVT == MVT::v16i8 ||
1015 LocVT == MVT::v8i16 ||
1016 LocVT == MVT::v4i32 ||
1017 LocVT == MVT::v2i64 ||
1018 LocVT == MVT::v4f32 ||
1019 LocVT == MVT::v2f64) {
1020 int64_t Offset10 = State.AllocateStack(Size: 16, Alignment: Align(16));
1021 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset10, LocVT, HTP: LocInfo));
1022 return false;
1023 }
1024
1025 if (LocVT == MVT::v32i8 ||
1026 LocVT == MVT::v16i16 ||
1027 LocVT == MVT::v8i32 ||
1028 LocVT == MVT::v4i64 ||
1029 LocVT == MVT::v8f32 ||
1030 LocVT == MVT::v4f64) {
1031 int64_t Offset11 = State.AllocateStack(Size: 32, Alignment: Align(32));
1032 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset11, LocVT, HTP: LocInfo));
1033 return false;
1034 }
1035
1036 if (LocVT == MVT::v64i8 ||
1037 LocVT == MVT::v32i16 ||
1038 LocVT == MVT::v16i32 ||
1039 LocVT == MVT::v8i64 ||
1040 LocVT == MVT::v16f32 ||
1041 LocVT == MVT::v8f64) {
1042 int64_t Offset12 = State.AllocateStack(Size: 64, Alignment: Align(64));
1043 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset12, LocVT, HTP: LocInfo));
1044 return false;
1045 }
1046
1047 return true; // CC didn't match.
1048}
1049
1050
1051static bool CC_X86_32_RegCallv4_Win(unsigned ValNo, MVT ValVT,
1052 MVT LocVT, CCValAssign::LocInfo LocInfo,
1053 ISD::ArgFlagsTy ArgFlags, CCState &State) {
1054
1055 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
1056 if (ArgFlags.isByVal()) {
1057 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 8, MinAlign: Align(8), ArgFlags);
1058 return false;
1059 }
1060 }
1061
1062 if (ArgFlags.isByVal()) {
1063 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 4, MinAlign: Align(4), ArgFlags);
1064 return false;
1065 }
1066
1067 if (LocVT == MVT::i1 ||
1068 LocVT == MVT::i8 ||
1069 LocVT == MVT::i16 ||
1070 LocVT == MVT::v1i1) {
1071 LocVT = MVT::i32;
1072 if (ArgFlags.isSExt())
1073 LocInfo = CCValAssign::SExt;
1074 else if (ArgFlags.isZExt())
1075 LocInfo = CCValAssign::ZExt;
1076 else
1077 LocInfo = CCValAssign::AExt;
1078 }
1079
1080 if (LocVT == MVT::v8i1 ||
1081 LocVT == MVT::v16i1 ||
1082 LocVT == MVT::v32i1) {
1083 LocVT = MVT::i32;
1084 if (ArgFlags.isSExt())
1085 LocInfo = CCValAssign::SExt;
1086 else if (ArgFlags.isZExt())
1087 LocInfo = CCValAssign::ZExt;
1088 else
1089 LocInfo = CCValAssign::AExt;
1090 }
1091
1092 if (LocVT == MVT::i32) {
1093 static const MCPhysReg RegList1[] = {
1094 X86::ECX, X86::EDX, X86::EDI, X86::ESI
1095 };
1096 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
1097 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1098 return false;
1099 }
1100 }
1101
1102 if (LocVT == MVT::i64) {
1103 if (MCRegister Reg = State.AllocateReg(Reg: X86::RAX)) {
1104 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1105 return false;
1106 }
1107 }
1108
1109 if (LocVT == MVT::v64i1) {
1110 LocVT = MVT::i64;
1111 if (ArgFlags.isSExt())
1112 LocInfo = CCValAssign::SExt;
1113 else if (ArgFlags.isZExt())
1114 LocInfo = CCValAssign::ZExt;
1115 else
1116 LocInfo = CCValAssign::AExt;
1117 }
1118
1119 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
1120 if (LocVT == MVT::i64) {
1121 if (MCRegister Reg = State.AllocateReg(Reg: X86::RAX)) {
1122 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1123 return false;
1124 }
1125 }
1126 }
1127
1128 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is32Bit()) {
1129 if (LocVT == MVT::i64) {
1130 if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1131 return false;
1132 }
1133 }
1134
1135 if (LocVT == MVT::f32 ||
1136 LocVT == MVT::f64 ||
1137 LocVT == MVT::f128) {
1138 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
1139 static const MCPhysReg RegList2[] = {
1140 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1141 };
1142 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
1143 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1144 return false;
1145 }
1146 }
1147 }
1148
1149 if (LocVT == MVT::f80) {
1150 if (MCRegister Reg = State.AllocateReg(Reg: X86::FP0)) {
1151 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1152 return false;
1153 }
1154 }
1155
1156 if (LocVT == MVT::v16i8 ||
1157 LocVT == MVT::v8i16 ||
1158 LocVT == MVT::v4i32 ||
1159 LocVT == MVT::v2i64 ||
1160 LocVT == MVT::v4f32 ||
1161 LocVT == MVT::v2f64) {
1162 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
1163 static const MCPhysReg RegList3[] = {
1164 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1165 };
1166 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
1167 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1168 return false;
1169 }
1170 }
1171 }
1172
1173 if (LocVT == MVT::v32i8 ||
1174 LocVT == MVT::v16i16 ||
1175 LocVT == MVT::v8i32 ||
1176 LocVT == MVT::v4i64 ||
1177 LocVT == MVT::v8f32 ||
1178 LocVT == MVT::v4f64) {
1179 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX()) {
1180 static const MCPhysReg RegList4[] = {
1181 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7
1182 };
1183 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
1184 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1185 return false;
1186 }
1187 }
1188 }
1189
1190 if (LocVT == MVT::v64i8 ||
1191 LocVT == MVT::v32i16 ||
1192 LocVT == MVT::v16i32 ||
1193 LocVT == MVT::v8i64 ||
1194 LocVT == MVT::v16f32 ||
1195 LocVT == MVT::v8f64) {
1196 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX512()) {
1197 static const MCPhysReg RegList5[] = {
1198 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7
1199 };
1200 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
1201 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1202 return false;
1203 }
1204 }
1205 }
1206
1207 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
1208 if (LocVT == MVT::i32 ||
1209 LocVT == MVT::i64 ||
1210 LocVT == MVT::f32 ||
1211 LocVT == MVT::f64) {
1212 int64_t Offset6 = State.AllocateStack(Size: 8, Alignment: Align(8));
1213 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset6, LocVT, HTP: LocInfo));
1214 return false;
1215 }
1216 }
1217
1218 if (LocVT == MVT::i32 ||
1219 LocVT == MVT::f32) {
1220 int64_t Offset7 = State.AllocateStack(Size: 4, Alignment: Align(4));
1221 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset7, LocVT, HTP: LocInfo));
1222 return false;
1223 }
1224
1225 if (LocVT == MVT::i64 ||
1226 LocVT == MVT::f64) {
1227 int64_t Offset8 = State.AllocateStack(Size: 8, Alignment: Align(4));
1228 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset8, LocVT, HTP: LocInfo));
1229 return false;
1230 }
1231
1232 if (LocVT == MVT::f80 ||
1233 LocVT == MVT::f128) {
1234 int64_t Offset9 = State.AllocateStack(
1235 Size: State.getMachineFunction().getDataLayout().getTypeAllocSize(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())),
1236 Alignment: State.getMachineFunction().getDataLayout().getABITypeAlign(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())));
1237 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset9, LocVT, HTP: LocInfo));
1238 return false;
1239 }
1240
1241 if (LocVT == MVT::v16i8 ||
1242 LocVT == MVT::v8i16 ||
1243 LocVT == MVT::v4i32 ||
1244 LocVT == MVT::v2i64 ||
1245 LocVT == MVT::v4f32 ||
1246 LocVT == MVT::v2f64) {
1247 int64_t Offset10 = State.AllocateStack(Size: 16, Alignment: Align(16));
1248 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset10, LocVT, HTP: LocInfo));
1249 return false;
1250 }
1251
1252 if (LocVT == MVT::v32i8 ||
1253 LocVT == MVT::v16i16 ||
1254 LocVT == MVT::v8i32 ||
1255 LocVT == MVT::v4i64 ||
1256 LocVT == MVT::v8f32 ||
1257 LocVT == MVT::v4f64) {
1258 int64_t Offset11 = State.AllocateStack(Size: 32, Alignment: Align(32));
1259 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset11, LocVT, HTP: LocInfo));
1260 return false;
1261 }
1262
1263 if (LocVT == MVT::v64i8 ||
1264 LocVT == MVT::v32i16 ||
1265 LocVT == MVT::v16i32 ||
1266 LocVT == MVT::v8i64 ||
1267 LocVT == MVT::v16f32 ||
1268 LocVT == MVT::v8f64) {
1269 int64_t Offset12 = State.AllocateStack(Size: 64, Alignment: Align(64));
1270 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset12, LocVT, HTP: LocInfo));
1271 return false;
1272 }
1273
1274 return true; // CC didn't match.
1275}
1276
1277
1278static bool CC_X86_32_ThisCall(unsigned ValNo, MVT ValVT,
1279 MVT LocVT, CCValAssign::LocInfo LocInfo,
1280 ISD::ArgFlagsTy ArgFlags, CCState &State) {
1281
1282 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetCygMing()) {
1283 if (!CC_X86_32_ThisCall_Mingw(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1284 return false;
1285 }
1286
1287 if (!CC_X86_32_ThisCall_Win(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1288 return false;
1289
1290 return true; // CC didn't match.
1291}
1292
1293
1294static bool CC_X86_32_ThisCall_Common(unsigned ValNo, MVT ValVT,
1295 MVT LocVT, CCValAssign::LocInfo LocInfo,
1296 ISD::ArgFlagsTy ArgFlags, CCState &State) {
1297
1298 if (LocVT == MVT::i32) {
1299 if (MCRegister Reg = State.AllocateReg(Reg: X86::ECX)) {
1300 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1301 return false;
1302 }
1303 }
1304
1305 if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1306 return false;
1307
1308 return true; // CC didn't match.
1309}
1310
1311
1312static bool CC_X86_32_ThisCall_Mingw(unsigned ValNo, MVT ValVT,
1313 MVT LocVT, CCValAssign::LocInfo LocInfo,
1314 ISD::ArgFlagsTy ArgFlags, CCState &State) {
1315
1316 if (LocVT == MVT::i1 ||
1317 LocVT == MVT::i8 ||
1318 LocVT == MVT::i16 ||
1319 LocVT == MVT::v1i1) {
1320 LocVT = MVT::i32;
1321 if (ArgFlags.isSExt())
1322 LocInfo = CCValAssign::SExt;
1323 else if (ArgFlags.isZExt())
1324 LocInfo = CCValAssign::ZExt;
1325 else
1326 LocInfo = CCValAssign::AExt;
1327 }
1328
1329 if (!CC_X86_32_ThisCall_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1330 return false;
1331
1332 return true; // CC didn't match.
1333}
1334
1335
1336static bool CC_X86_32_ThisCall_Win(unsigned ValNo, MVT ValVT,
1337 MVT LocVT, CCValAssign::LocInfo LocInfo,
1338 ISD::ArgFlagsTy ArgFlags, CCState &State) {
1339
1340 if (LocVT == MVT::i1 ||
1341 LocVT == MVT::i8 ||
1342 LocVT == MVT::i16 ||
1343 LocVT == MVT::v1i1) {
1344 LocVT = MVT::i32;
1345 if (ArgFlags.isSExt())
1346 LocInfo = CCValAssign::SExt;
1347 else if (ArgFlags.isZExt())
1348 LocInfo = CCValAssign::ZExt;
1349 else
1350 LocInfo = CCValAssign::AExt;
1351 }
1352
1353 if (ArgFlags.isSRet()) {
1354 int64_t Offset1 = State.AllocateStack(Size: 4, Alignment: Align(4));
1355 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset1, LocVT, HTP: LocInfo));
1356 return false;
1357 }
1358
1359 if (!CC_X86_32_ThisCall_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1360 return false;
1361
1362 return true; // CC didn't match.
1363}
1364
1365
1366static bool CC_X86_32_Vector_Common(unsigned ValNo, MVT ValVT,
1367 MVT LocVT, CCValAssign::LocInfo LocInfo,
1368 ISD::ArgFlagsTy ArgFlags, CCState &State) {
1369
1370 if (LocVT == MVT::v16i8 ||
1371 LocVT == MVT::v8i16 ||
1372 LocVT == MVT::v4i32 ||
1373 LocVT == MVT::v2i64 ||
1374 LocVT == MVT::v8f16 ||
1375 LocVT == MVT::v8bf16 ||
1376 LocVT == MVT::v4f32 ||
1377 LocVT == MVT::v2f64) {
1378 int64_t Offset1 = State.AllocateStack(Size: 16, Alignment: Align(16));
1379 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset1, LocVT, HTP: LocInfo));
1380 return false;
1381 }
1382
1383 if (LocVT == MVT::v32i8 ||
1384 LocVT == MVT::v16i16 ||
1385 LocVT == MVT::v8i32 ||
1386 LocVT == MVT::v4i64 ||
1387 LocVT == MVT::v16f16 ||
1388 LocVT == MVT::v16bf16 ||
1389 LocVT == MVT::v8f32 ||
1390 LocVT == MVT::v4f64) {
1391 int64_t Offset2 = State.AllocateStack(Size: 32, Alignment: Align(32));
1392 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset2, LocVT, HTP: LocInfo));
1393 return false;
1394 }
1395
1396 if (LocVT == MVT::v64i8 ||
1397 LocVT == MVT::v32i16 ||
1398 LocVT == MVT::v16i32 ||
1399 LocVT == MVT::v8i64 ||
1400 LocVT == MVT::v32f16 ||
1401 LocVT == MVT::v32bf16 ||
1402 LocVT == MVT::v16f32 ||
1403 LocVT == MVT::v8f64) {
1404 int64_t Offset3 = State.AllocateStack(Size: 64, Alignment: Align(64));
1405 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset3, LocVT, HTP: LocInfo));
1406 return false;
1407 }
1408
1409 return true; // CC didn't match.
1410}
1411
1412
1413static bool CC_X86_32_Vector_Darwin(unsigned ValNo, MVT ValVT,
1414 MVT LocVT, CCValAssign::LocInfo LocInfo,
1415 ISD::ArgFlagsTy ArgFlags, CCState &State) {
1416
1417 if (!State.isVarArg()) {
1418 if (LocVT == MVT::v16i8 ||
1419 LocVT == MVT::v8i16 ||
1420 LocVT == MVT::v4i32 ||
1421 LocVT == MVT::v2i64 ||
1422 LocVT == MVT::v8f16 ||
1423 LocVT == MVT::v8bf16 ||
1424 LocVT == MVT::v4f32 ||
1425 LocVT == MVT::v2f64) {
1426 static const MCPhysReg RegList1[] = {
1427 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1428 };
1429 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
1430 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1431 return false;
1432 }
1433 }
1434 }
1435
1436 if (!State.isVarArg()) {
1437 if (LocVT == MVT::v32i8 ||
1438 LocVT == MVT::v16i16 ||
1439 LocVT == MVT::v8i32 ||
1440 LocVT == MVT::v4i64 ||
1441 LocVT == MVT::v16f16 ||
1442 LocVT == MVT::v16bf16 ||
1443 LocVT == MVT::v8f32 ||
1444 LocVT == MVT::v4f64) {
1445 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX()) {
1446 static const MCPhysReg RegList2[] = {
1447 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3
1448 };
1449 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
1450 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1451 return false;
1452 }
1453 }
1454 }
1455 }
1456
1457 if (!State.isVarArg()) {
1458 if (LocVT == MVT::v64i8 ||
1459 LocVT == MVT::v32i16 ||
1460 LocVT == MVT::v16i32 ||
1461 LocVT == MVT::v8i64 ||
1462 LocVT == MVT::v32f16 ||
1463 LocVT == MVT::v32bf16 ||
1464 LocVT == MVT::v16f32 ||
1465 LocVT == MVT::v8f64) {
1466 static const MCPhysReg RegList3[] = {
1467 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3
1468 };
1469 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
1470 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1471 return false;
1472 }
1473 }
1474 }
1475
1476 if (!CC_X86_32_Vector_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1477 return false;
1478
1479 return true; // CC didn't match.
1480}
1481
1482
1483static bool CC_X86_32_Vector_Standard(unsigned ValNo, MVT ValVT,
1484 MVT LocVT, CCValAssign::LocInfo LocInfo,
1485 ISD::ArgFlagsTy ArgFlags, CCState &State) {
1486
1487 if (!State.isVarArg()) {
1488 if (LocVT == MVT::v16i8 ||
1489 LocVT == MVT::v8i16 ||
1490 LocVT == MVT::v4i32 ||
1491 LocVT == MVT::v2i64 ||
1492 LocVT == MVT::v8f16 ||
1493 LocVT == MVT::v8bf16 ||
1494 LocVT == MVT::v4f32 ||
1495 LocVT == MVT::v2f64) {
1496 static const MCPhysReg RegList1[] = {
1497 X86::XMM0, X86::XMM1, X86::XMM2
1498 };
1499 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
1500 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1501 return false;
1502 }
1503 }
1504 }
1505
1506 if (!State.isVarArg()) {
1507 if (LocVT == MVT::v32i8 ||
1508 LocVT == MVT::v16i16 ||
1509 LocVT == MVT::v8i32 ||
1510 LocVT == MVT::v4i64 ||
1511 LocVT == MVT::v16f16 ||
1512 LocVT == MVT::v16bf16 ||
1513 LocVT == MVT::v8f32 ||
1514 LocVT == MVT::v4f64) {
1515 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX()) {
1516 static const MCPhysReg RegList2[] = {
1517 X86::YMM0, X86::YMM1, X86::YMM2
1518 };
1519 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
1520 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1521 return false;
1522 }
1523 }
1524 }
1525 }
1526
1527 if (!State.isVarArg()) {
1528 if (LocVT == MVT::v64i8 ||
1529 LocVT == MVT::v32i16 ||
1530 LocVT == MVT::v16i32 ||
1531 LocVT == MVT::v8i64 ||
1532 LocVT == MVT::v32f16 ||
1533 LocVT == MVT::v32bf16 ||
1534 LocVT == MVT::v16f32 ||
1535 LocVT == MVT::v8f64) {
1536 static const MCPhysReg RegList3[] = {
1537 X86::ZMM0, X86::ZMM1, X86::ZMM2
1538 };
1539 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
1540 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1541 return false;
1542 }
1543 }
1544 }
1545
1546 if (State.isVarArg() && State.getMachineFunction().getSubtarget().getTargetTriple().isWindowsMSVCEnvironment()) {
1547 if (!CC_X86_Win32_Vector(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1548 return false;
1549 }
1550
1551 if (!CC_X86_32_Vector_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1552 return false;
1553
1554 return true; // CC didn't match.
1555}
1556
1557
1558static bool CC_X86_64(unsigned ValNo, MVT ValVT,
1559 MVT LocVT, CCValAssign::LocInfo LocInfo,
1560 ISD::ArgFlagsTy ArgFlags, CCState &State) {
1561
1562 if (State.getCallingConv() == CallingConv::GHC) {
1563 if (!CC_X86_64_GHC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1564 return false;
1565 }
1566
1567 if (State.getCallingConv() == CallingConv::HiPE) {
1568 if (!CC_X86_64_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1569 return false;
1570 }
1571
1572 if (State.getCallingConv() == CallingConv::AnyReg) {
1573 if (!CC_X86_64_AnyReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1574 return false;
1575 }
1576
1577 if (State.getCallingConv() == CallingConv::Win64) {
1578 if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1579 return false;
1580 }
1581
1582 if (State.getCallingConv() == CallingConv::X86_64_SysV) {
1583 if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1584 return false;
1585 }
1586
1587 if (State.getCallingConv() == CallingConv::X86_VectorCall) {
1588 if (!CC_X86_Win64_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1589 return false;
1590 }
1591
1592 if (State.getCallingConv() == CallingConv::X86_RegCall) {
1593 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetWin64()) {
1594 if (State.getMachineFunction().getFunction().getParent()->getModuleFlag(Key: "RegCallv4")!=nullptr) {
1595 if (!CC_X86_Win64_RegCallv4(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1596 return false;
1597 }
1598 }
1599 }
1600
1601 if (State.getCallingConv() == CallingConv::X86_RegCall) {
1602 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetWin64()) {
1603 if (!CC_X86_Win64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1604 return false;
1605 }
1606 }
1607
1608 if (State.getCallingConv() == CallingConv::X86_RegCall) {
1609 if (!CC_X86_SysV64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1610 return false;
1611 }
1612
1613 if (State.getCallingConv() == CallingConv::PreserveNone) {
1614 if (!CC_X86_64_Preserve_None(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1615 return false;
1616 }
1617
1618 if (State.getCallingConv() == CallingConv::X86_INTR) {
1619 if (CC_X86_Intr(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1620 return false;
1621 }
1622
1623 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetWin64()) {
1624 if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1625 return false;
1626 }
1627
1628 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetUEFI64()) {
1629 if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1630 return false;
1631 }
1632
1633 if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1634 return false;
1635
1636 return true; // CC didn't match.
1637}
1638
1639
1640static bool CC_X86_64_AnyReg(unsigned ValNo, MVT ValVT,
1641 MVT LocVT, CCValAssign::LocInfo LocInfo,
1642 ISD::ArgFlagsTy ArgFlags, CCState &State) {
1643
1644 if (CC_X86_AnyReg_Error(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1645 return false;
1646
1647 return true; // CC didn't match.
1648}
1649
1650
1651static bool CC_X86_64_C(unsigned ValNo, MVT ValVT,
1652 MVT LocVT, CCValAssign::LocInfo LocInfo,
1653 ISD::ArgFlagsTy ArgFlags, CCState &State) {
1654
1655 if (ArgFlags.isByVal()) {
1656 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 8, MinAlign: Align(8), ArgFlags);
1657 return false;
1658 }
1659
1660 if (LocVT == MVT::i1 ||
1661 LocVT == MVT::i8 ||
1662 LocVT == MVT::i16 ||
1663 LocVT == MVT::v1i1) {
1664 LocVT = MVT::i32;
1665 if (ArgFlags.isSExt())
1666 LocInfo = CCValAssign::SExt;
1667 else if (ArgFlags.isZExt())
1668 LocInfo = CCValAssign::ZExt;
1669 else
1670 LocInfo = CCValAssign::AExt;
1671 }
1672
1673 if (ArgFlags.isNest()) {
1674 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTarget64BitILP32()) {
1675 if (MCRegister Reg = State.AllocateReg(Reg: X86::R10D)) {
1676 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1677 return false;
1678 }
1679 }
1680 }
1681
1682 if (ArgFlags.isNest()) {
1683 if (MCRegister Reg = State.AllocateReg(Reg: X86::R10)) {
1684 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1685 return false;
1686 }
1687 }
1688
1689 if (ArgFlags.isSwiftSelf()) {
1690 if (LocVT == MVT::i64) {
1691 if (MCRegister Reg = State.AllocateReg(Reg: X86::R13)) {
1692 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1693 return false;
1694 }
1695 }
1696 }
1697
1698 if (ArgFlags.isSwiftError()) {
1699 if (LocVT == MVT::i64) {
1700 if (MCRegister Reg = State.AllocateReg(Reg: X86::R12)) {
1701 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1702 return false;
1703 }
1704 }
1705 }
1706
1707 if (ArgFlags.isSwiftAsync()) {
1708 if (LocVT == MVT::i64) {
1709 if (MCRegister Reg = State.AllocateReg(Reg: X86::R14)) {
1710 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1711 return false;
1712 }
1713 }
1714 }
1715
1716 if (State.getCallingConv() == CallingConv::Swift) {
1717 if (ArgFlags.isSRet()) {
1718 if (LocVT == MVT::i64) {
1719 if (MCRegister Reg = State.AllocateReg(Reg: X86::RAX)) {
1720 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1721 return false;
1722 }
1723 }
1724 }
1725 }
1726
1727 if (State.getCallingConv() == CallingConv::SwiftTail) {
1728 if (ArgFlags.isSRet()) {
1729 if (LocVT == MVT::i64) {
1730 if (MCRegister Reg = State.AllocateReg(Reg: X86::RAX)) {
1731 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1732 return false;
1733 }
1734 }
1735 }
1736 }
1737
1738 if (ArgFlags.isPointer()) {
1739 if (CC_X86_64_Pointer(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1740 return false;
1741 }
1742
1743 if (LocVT == MVT::i32) {
1744 static const MCPhysReg RegList1[] = {
1745 X86::EDI, X86::ESI, X86::EDX, X86::ECX, X86::R8D, X86::R9D
1746 };
1747 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
1748 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1749 return false;
1750 }
1751 }
1752
1753 if (LocVT == MVT::i64) {
1754 if (ArgFlags.isInConsecutiveRegs()) {
1755 if (CC_X86_64_I128(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1756 return false;
1757 }
1758 }
1759
1760 if (LocVT == MVT::i64) {
1761 static const MCPhysReg RegList2[] = {
1762 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1763 };
1764 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
1765 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1766 return false;
1767 }
1768 }
1769
1770 if (LocVT == MVT::v2i1) {
1771 LocVT = MVT::v2i64;
1772 if (ArgFlags.isSExt())
1773 LocInfo = CCValAssign::SExt;
1774 else if (ArgFlags.isZExt())
1775 LocInfo = CCValAssign::ZExt;
1776 else
1777 LocInfo = CCValAssign::AExt;
1778 }
1779
1780 if (LocVT == MVT::v4i1) {
1781 LocVT = MVT::v4i32;
1782 if (ArgFlags.isSExt())
1783 LocInfo = CCValAssign::SExt;
1784 else if (ArgFlags.isZExt())
1785 LocInfo = CCValAssign::ZExt;
1786 else
1787 LocInfo = CCValAssign::AExt;
1788 }
1789
1790 if (LocVT == MVT::v8i1) {
1791 LocVT = MVT::v8i16;
1792 if (ArgFlags.isSExt())
1793 LocInfo = CCValAssign::SExt;
1794 else if (ArgFlags.isZExt())
1795 LocInfo = CCValAssign::ZExt;
1796 else
1797 LocInfo = CCValAssign::AExt;
1798 }
1799
1800 if (LocVT == MVT::v16i1) {
1801 LocVT = MVT::v16i8;
1802 if (ArgFlags.isSExt())
1803 LocInfo = CCValAssign::SExt;
1804 else if (ArgFlags.isZExt())
1805 LocInfo = CCValAssign::ZExt;
1806 else
1807 LocInfo = CCValAssign::AExt;
1808 }
1809
1810 if (LocVT == MVT::v32i1) {
1811 LocVT = MVT::v32i8;
1812 if (ArgFlags.isSExt())
1813 LocInfo = CCValAssign::SExt;
1814 else if (ArgFlags.isZExt())
1815 LocInfo = CCValAssign::ZExt;
1816 else
1817 LocInfo = CCValAssign::AExt;
1818 }
1819
1820 if (LocVT == MVT::v64i1) {
1821 LocVT = MVT::v64i8;
1822 if (ArgFlags.isSExt())
1823 LocInfo = CCValAssign::SExt;
1824 else if (ArgFlags.isZExt())
1825 LocInfo = CCValAssign::ZExt;
1826 else
1827 LocInfo = CCValAssign::AExt;
1828 }
1829
1830 if (LocVT == MVT::f16 ||
1831 LocVT == MVT::f32 ||
1832 LocVT == MVT::f64 ||
1833 LocVT == MVT::f128 ||
1834 LocVT == MVT::v16i8 ||
1835 LocVT == MVT::v8i16 ||
1836 LocVT == MVT::v4i32 ||
1837 LocVT == MVT::v2i64 ||
1838 LocVT == MVT::v8f16 ||
1839 LocVT == MVT::v8bf16 ||
1840 LocVT == MVT::v4f32 ||
1841 LocVT == MVT::v2f64) {
1842 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
1843 static const MCPhysReg RegList3[] = {
1844 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1845 };
1846 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
1847 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1848 return false;
1849 }
1850 }
1851 }
1852
1853 if (!State.isVarArg()) {
1854 if (LocVT == MVT::v32i8 ||
1855 LocVT == MVT::v16i16 ||
1856 LocVT == MVT::v8i32 ||
1857 LocVT == MVT::v4i64 ||
1858 LocVT == MVT::v16f16 ||
1859 LocVT == MVT::v16bf16 ||
1860 LocVT == MVT::v8f32 ||
1861 LocVT == MVT::v4f64) {
1862 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX()) {
1863 static const MCPhysReg RegList4[] = {
1864 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7
1865 };
1866 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
1867 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1868 return false;
1869 }
1870 }
1871 }
1872 }
1873
1874 if (!State.isVarArg()) {
1875 if (LocVT == MVT::v64i8 ||
1876 LocVT == MVT::v32i16 ||
1877 LocVT == MVT::v16i32 ||
1878 LocVT == MVT::v8i64 ||
1879 LocVT == MVT::v32f16 ||
1880 LocVT == MVT::v32bf16 ||
1881 LocVT == MVT::v16f32 ||
1882 LocVT == MVT::v8f64) {
1883 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX512()) {
1884 static const MCPhysReg RegList5[] = {
1885 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7
1886 };
1887 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
1888 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1889 return false;
1890 }
1891 }
1892 }
1893 }
1894
1895 if (LocVT == MVT::i32 ||
1896 LocVT == MVT::i64 ||
1897 LocVT == MVT::f16 ||
1898 LocVT == MVT::f32 ||
1899 LocVT == MVT::f64) {
1900 int64_t Offset6 = State.AllocateStack(Size: 8, Alignment: Align(8));
1901 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset6, LocVT, HTP: LocInfo));
1902 return false;
1903 }
1904
1905 if (LocVT == MVT::f80 ||
1906 LocVT == MVT::f128) {
1907 int64_t Offset7 = State.AllocateStack(
1908 Size: State.getMachineFunction().getDataLayout().getTypeAllocSize(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())),
1909 Alignment: State.getMachineFunction().getDataLayout().getABITypeAlign(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())));
1910 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset7, LocVT, HTP: LocInfo));
1911 return false;
1912 }
1913
1914 if (LocVT == MVT::v16i8 ||
1915 LocVT == MVT::v8i16 ||
1916 LocVT == MVT::v4i32 ||
1917 LocVT == MVT::v2i64 ||
1918 LocVT == MVT::v8f16 ||
1919 LocVT == MVT::v8bf16 ||
1920 LocVT == MVT::v4f32 ||
1921 LocVT == MVT::v2f64) {
1922 int64_t Offset8 = State.AllocateStack(Size: 16, Alignment: Align(16));
1923 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset8, LocVT, HTP: LocInfo));
1924 return false;
1925 }
1926
1927 if (LocVT == MVT::v32i8 ||
1928 LocVT == MVT::v16i16 ||
1929 LocVT == MVT::v8i32 ||
1930 LocVT == MVT::v4i64 ||
1931 LocVT == MVT::v16f16 ||
1932 LocVT == MVT::v16bf16 ||
1933 LocVT == MVT::v8f32 ||
1934 LocVT == MVT::v4f64) {
1935 int64_t Offset9 = State.AllocateStack(Size: 32, Alignment: Align(32));
1936 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset9, LocVT, HTP: LocInfo));
1937 return false;
1938 }
1939
1940 if (LocVT == MVT::v64i8 ||
1941 LocVT == MVT::v32i16 ||
1942 LocVT == MVT::v16i32 ||
1943 LocVT == MVT::v8i64 ||
1944 LocVT == MVT::v32f16 ||
1945 LocVT == MVT::v32bf16 ||
1946 LocVT == MVT::v16f32 ||
1947 LocVT == MVT::v8f64) {
1948 int64_t Offset10 = State.AllocateStack(Size: 64, Alignment: Align(64));
1949 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset10, LocVT, HTP: LocInfo));
1950 return false;
1951 }
1952
1953 return true; // CC didn't match.
1954}
1955
1956
1957static bool CC_X86_64_GHC(unsigned ValNo, MVT ValVT,
1958 MVT LocVT, CCValAssign::LocInfo LocInfo,
1959 ISD::ArgFlagsTy ArgFlags, CCState &State) {
1960
1961 if (LocVT == MVT::i8 ||
1962 LocVT == MVT::i16 ||
1963 LocVT == MVT::i32) {
1964 LocVT = MVT::i64;
1965 if (ArgFlags.isSExt())
1966 LocInfo = CCValAssign::SExt;
1967 else if (ArgFlags.isZExt())
1968 LocInfo = CCValAssign::ZExt;
1969 else
1970 LocInfo = CCValAssign::AExt;
1971 }
1972
1973 if (LocVT == MVT::i64) {
1974 static const MCPhysReg RegList1[] = {
1975 X86::R13, X86::RBP, X86::R12, X86::RBX, X86::R14, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R15
1976 };
1977 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
1978 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1979 return false;
1980 }
1981 }
1982
1983 if (LocVT == MVT::f32 ||
1984 LocVT == MVT::f64 ||
1985 LocVT == MVT::v16i8 ||
1986 LocVT == MVT::v8i16 ||
1987 LocVT == MVT::v4i32 ||
1988 LocVT == MVT::v2i64 ||
1989 LocVT == MVT::v4f32 ||
1990 LocVT == MVT::v2f64) {
1991 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
1992 static const MCPhysReg RegList2[] = {
1993 X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6
1994 };
1995 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
1996 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
1997 return false;
1998 }
1999 }
2000 }
2001
2002 if (LocVT == MVT::v32i8 ||
2003 LocVT == MVT::v16i16 ||
2004 LocVT == MVT::v8i32 ||
2005 LocVT == MVT::v4i64 ||
2006 LocVT == MVT::v8f32 ||
2007 LocVT == MVT::v4f64) {
2008 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX()) {
2009 static const MCPhysReg RegList3[] = {
2010 X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6
2011 };
2012 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
2013 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2014 return false;
2015 }
2016 }
2017 }
2018
2019 if (LocVT == MVT::v64i8 ||
2020 LocVT == MVT::v32i16 ||
2021 LocVT == MVT::v16i32 ||
2022 LocVT == MVT::v8i64 ||
2023 LocVT == MVT::v16f32 ||
2024 LocVT == MVT::v8f64) {
2025 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX512()) {
2026 static const MCPhysReg RegList4[] = {
2027 X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6
2028 };
2029 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
2030 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2031 return false;
2032 }
2033 }
2034 }
2035
2036 return true; // CC didn't match.
2037}
2038
2039
2040static bool CC_X86_64_HiPE(unsigned ValNo, MVT ValVT,
2041 MVT LocVT, CCValAssign::LocInfo LocInfo,
2042 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2043
2044 if (LocVT == MVT::i8 ||
2045 LocVT == MVT::i16 ||
2046 LocVT == MVT::i32) {
2047 LocVT = MVT::i64;
2048 if (ArgFlags.isSExt())
2049 LocInfo = CCValAssign::SExt;
2050 else if (ArgFlags.isZExt())
2051 LocInfo = CCValAssign::ZExt;
2052 else
2053 LocInfo = CCValAssign::AExt;
2054 }
2055
2056 if (LocVT == MVT::i64) {
2057 static const MCPhysReg RegList1[] = {
2058 X86::R15, X86::RBP, X86::RSI, X86::RDX, X86::RCX, X86::R8
2059 };
2060 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
2061 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2062 return false;
2063 }
2064 }
2065
2066 if (LocVT == MVT::i32 ||
2067 LocVT == MVT::i64 ||
2068 LocVT == MVT::f32 ||
2069 LocVT == MVT::f64) {
2070 int64_t Offset2 = State.AllocateStack(Size: 8, Alignment: Align(8));
2071 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset2, LocVT, HTP: LocInfo));
2072 return false;
2073 }
2074
2075 return true; // CC didn't match.
2076}
2077
2078
2079static bool CC_X86_64_Preserve_None(unsigned ValNo, MVT ValVT,
2080 MVT LocVT, CCValAssign::LocInfo LocInfo,
2081 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2082
2083 if (LocVT == MVT::i32) {
2084 static const MCPhysReg RegList1[] = {
2085 X86::R12D, X86::R13D, X86::R14D, X86::R15D, X86::EDI, X86::ESI, X86::EDX, X86::ECX, X86::R8D, X86::R9D, X86::R11D, X86::EAX
2086 };
2087 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
2088 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2089 return false;
2090 }
2091 }
2092
2093 if (LocVT == MVT::i64) {
2094 static const MCPhysReg RegList2[] = {
2095 X86::R12, X86::R13, X86::R14, X86::R15, X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9, X86::R11, X86::RAX
2096 };
2097 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
2098 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2099 return false;
2100 }
2101 }
2102
2103 if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2104 return false;
2105
2106 return true; // CC didn't match.
2107}
2108
2109
2110static bool CC_X86_SysV64_RegCall(unsigned ValNo, MVT ValVT,
2111 MVT LocVT, CCValAssign::LocInfo LocInfo,
2112 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2113
2114 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
2115 if (ArgFlags.isByVal()) {
2116 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 8, MinAlign: Align(8), ArgFlags);
2117 return false;
2118 }
2119 }
2120
2121 if (ArgFlags.isByVal()) {
2122 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 4, MinAlign: Align(4), ArgFlags);
2123 return false;
2124 }
2125
2126 if (LocVT == MVT::i1 ||
2127 LocVT == MVT::i8 ||
2128 LocVT == MVT::i16 ||
2129 LocVT == MVT::v1i1) {
2130 LocVT = MVT::i32;
2131 if (ArgFlags.isSExt())
2132 LocInfo = CCValAssign::SExt;
2133 else if (ArgFlags.isZExt())
2134 LocInfo = CCValAssign::ZExt;
2135 else
2136 LocInfo = CCValAssign::AExt;
2137 }
2138
2139 if (LocVT == MVT::v8i1 ||
2140 LocVT == MVT::v16i1 ||
2141 LocVT == MVT::v32i1) {
2142 LocVT = MVT::i32;
2143 if (ArgFlags.isSExt())
2144 LocInfo = CCValAssign::SExt;
2145 else if (ArgFlags.isZExt())
2146 LocInfo = CCValAssign::ZExt;
2147 else
2148 LocInfo = CCValAssign::AExt;
2149 }
2150
2151 if (LocVT == MVT::i32) {
2152 static const MCPhysReg RegList1[] = {
2153 X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R12D, X86::R13D, X86::R14D, X86::R15D
2154 };
2155 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
2156 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2157 return false;
2158 }
2159 }
2160
2161 if (LocVT == MVT::i64) {
2162 static const MCPhysReg RegList2[] = {
2163 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15
2164 };
2165 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
2166 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2167 return false;
2168 }
2169 }
2170
2171 if (LocVT == MVT::v64i1) {
2172 LocVT = MVT::i64;
2173 if (ArgFlags.isSExt())
2174 LocInfo = CCValAssign::SExt;
2175 else if (ArgFlags.isZExt())
2176 LocInfo = CCValAssign::ZExt;
2177 else
2178 LocInfo = CCValAssign::AExt;
2179 }
2180
2181 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
2182 if (LocVT == MVT::i64) {
2183 static const MCPhysReg RegList3[] = {
2184 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15
2185 };
2186 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
2187 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2188 return false;
2189 }
2190 }
2191 }
2192
2193 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is32Bit()) {
2194 if (LocVT == MVT::i64) {
2195 if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2196 return false;
2197 }
2198 }
2199
2200 if (LocVT == MVT::f32 ||
2201 LocVT == MVT::f64 ||
2202 LocVT == MVT::f128) {
2203 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
2204 static const MCPhysReg RegList4[] = {
2205 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
2206 };
2207 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
2208 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2209 return false;
2210 }
2211 }
2212 }
2213
2214 if (LocVT == MVT::f80) {
2215 if (MCRegister Reg = State.AllocateReg(Reg: X86::FP0)) {
2216 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2217 return false;
2218 }
2219 }
2220
2221 if (LocVT == MVT::v16i8 ||
2222 LocVT == MVT::v8i16 ||
2223 LocVT == MVT::v4i32 ||
2224 LocVT == MVT::v2i64 ||
2225 LocVT == MVT::v4f32 ||
2226 LocVT == MVT::v2f64) {
2227 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
2228 static const MCPhysReg RegList5[] = {
2229 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
2230 };
2231 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
2232 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2233 return false;
2234 }
2235 }
2236 }
2237
2238 if (LocVT == MVT::v32i8 ||
2239 LocVT == MVT::v16i16 ||
2240 LocVT == MVT::v8i32 ||
2241 LocVT == MVT::v4i64 ||
2242 LocVT == MVT::v8f32 ||
2243 LocVT == MVT::v4f64) {
2244 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX()) {
2245 static const MCPhysReg RegList6[] = {
2246 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15
2247 };
2248 if (MCRegister Reg = State.AllocateReg(Regs: RegList6)) {
2249 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2250 return false;
2251 }
2252 }
2253 }
2254
2255 if (LocVT == MVT::v64i8 ||
2256 LocVT == MVT::v32i16 ||
2257 LocVT == MVT::v16i32 ||
2258 LocVT == MVT::v8i64 ||
2259 LocVT == MVT::v16f32 ||
2260 LocVT == MVT::v8f64) {
2261 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX512()) {
2262 static const MCPhysReg RegList7[] = {
2263 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15
2264 };
2265 if (MCRegister Reg = State.AllocateReg(Regs: RegList7)) {
2266 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2267 return false;
2268 }
2269 }
2270 }
2271
2272 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
2273 if (LocVT == MVT::i32 ||
2274 LocVT == MVT::i64 ||
2275 LocVT == MVT::f32 ||
2276 LocVT == MVT::f64) {
2277 int64_t Offset8 = State.AllocateStack(Size: 8, Alignment: Align(8));
2278 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset8, LocVT, HTP: LocInfo));
2279 return false;
2280 }
2281 }
2282
2283 if (LocVT == MVT::i32 ||
2284 LocVT == MVT::f32) {
2285 int64_t Offset9 = State.AllocateStack(Size: 4, Alignment: Align(4));
2286 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset9, LocVT, HTP: LocInfo));
2287 return false;
2288 }
2289
2290 if (LocVT == MVT::i64 ||
2291 LocVT == MVT::f64) {
2292 int64_t Offset10 = State.AllocateStack(Size: 8, Alignment: Align(4));
2293 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset10, LocVT, HTP: LocInfo));
2294 return false;
2295 }
2296
2297 if (LocVT == MVT::f80 ||
2298 LocVT == MVT::f128) {
2299 int64_t Offset11 = State.AllocateStack(
2300 Size: State.getMachineFunction().getDataLayout().getTypeAllocSize(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())),
2301 Alignment: State.getMachineFunction().getDataLayout().getABITypeAlign(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())));
2302 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset11, LocVT, HTP: LocInfo));
2303 return false;
2304 }
2305
2306 if (LocVT == MVT::v16i8 ||
2307 LocVT == MVT::v8i16 ||
2308 LocVT == MVT::v4i32 ||
2309 LocVT == MVT::v2i64 ||
2310 LocVT == MVT::v4f32 ||
2311 LocVT == MVT::v2f64) {
2312 int64_t Offset12 = State.AllocateStack(Size: 16, Alignment: Align(16));
2313 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset12, LocVT, HTP: LocInfo));
2314 return false;
2315 }
2316
2317 if (LocVT == MVT::v32i8 ||
2318 LocVT == MVT::v16i16 ||
2319 LocVT == MVT::v8i32 ||
2320 LocVT == MVT::v4i64 ||
2321 LocVT == MVT::v8f32 ||
2322 LocVT == MVT::v4f64) {
2323 int64_t Offset13 = State.AllocateStack(Size: 32, Alignment: Align(32));
2324 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset13, LocVT, HTP: LocInfo));
2325 return false;
2326 }
2327
2328 if (LocVT == MVT::v64i8 ||
2329 LocVT == MVT::v32i16 ||
2330 LocVT == MVT::v16i32 ||
2331 LocVT == MVT::v8i64 ||
2332 LocVT == MVT::v16f32 ||
2333 LocVT == MVT::v8f64) {
2334 int64_t Offset14 = State.AllocateStack(Size: 64, Alignment: Align(64));
2335 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset14, LocVT, HTP: LocInfo));
2336 return false;
2337 }
2338
2339 return true; // CC didn't match.
2340}
2341
2342
2343static bool CC_X86_Win32_CFGuard_Check(unsigned ValNo, MVT ValVT,
2344 MVT LocVT, CCValAssign::LocInfo LocInfo,
2345 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2346
2347 if (LocVT == MVT::i32) {
2348 if (MCRegister Reg = State.AllocateReg(Reg: X86::ECX)) {
2349 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2350 return false;
2351 }
2352 }
2353
2354 return true; // CC didn't match.
2355}
2356
2357
2358static bool CC_X86_Win32_Vector(unsigned ValNo, MVT ValVT,
2359 MVT LocVT, CCValAssign::LocInfo LocInfo,
2360 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2361
2362 if (LocVT == MVT::v16i8 ||
2363 LocVT == MVT::v8i16 ||
2364 LocVT == MVT::v4i32 ||
2365 LocVT == MVT::v2i64 ||
2366 LocVT == MVT::v8f16 ||
2367 LocVT == MVT::v8bf16 ||
2368 LocVT == MVT::v4f32 ||
2369 LocVT == MVT::v2f64) {
2370 int64_t Offset1 = State.AllocateStack(Size: 16, Alignment: Align(4));
2371 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset1, LocVT, HTP: LocInfo));
2372 return false;
2373 }
2374
2375 if (LocVT == MVT::v32i8 ||
2376 LocVT == MVT::v16i16 ||
2377 LocVT == MVT::v8i32 ||
2378 LocVT == MVT::v4i64 ||
2379 LocVT == MVT::v16f16 ||
2380 LocVT == MVT::v16bf16 ||
2381 LocVT == MVT::v8f32 ||
2382 LocVT == MVT::v4f64) {
2383 int64_t Offset2 = State.AllocateStack(Size: 32, Alignment: Align(4));
2384 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset2, LocVT, HTP: LocInfo));
2385 return false;
2386 }
2387
2388 if (LocVT == MVT::v64i8 ||
2389 LocVT == MVT::v32i16 ||
2390 LocVT == MVT::v16i32 ||
2391 LocVT == MVT::v8i64 ||
2392 LocVT == MVT::v32f16 ||
2393 LocVT == MVT::v32bf16 ||
2394 LocVT == MVT::v16f32 ||
2395 LocVT == MVT::v8f64) {
2396 int64_t Offset3 = State.AllocateStack(Size: 64, Alignment: Align(4));
2397 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset3, LocVT, HTP: LocInfo));
2398 return false;
2399 }
2400
2401 return true; // CC didn't match.
2402}
2403
2404
2405static bool CC_X86_Win32_VectorCall(unsigned ValNo, MVT ValVT,
2406 MVT LocVT, CCValAssign::LocInfo LocInfo,
2407 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2408
2409 if (CC_X86_32_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2410 return false;
2411
2412 if (!CC_X86_32_FastCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2413 return false;
2414
2415 return true; // CC didn't match.
2416}
2417
2418
2419static bool CC_X86_Win64_C(unsigned ValNo, MVT ValVT,
2420 MVT LocVT, CCValAssign::LocInfo LocInfo,
2421 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2422
2423 if (ArgFlags.isByVal()) {
2424 LocVT = MVT::i64;
2425 LocInfo = CCValAssign::Indirect;
2426 }
2427
2428 if (LocVT == MVT::i1 ||
2429 LocVT == MVT::v1i1) {
2430 LocVT = MVT::i8;
2431 if (ArgFlags.isSExt())
2432 LocInfo = CCValAssign::SExt;
2433 else if (ArgFlags.isZExt())
2434 LocInfo = CCValAssign::ZExt;
2435 else
2436 LocInfo = CCValAssign::AExt;
2437 }
2438
2439 if (ArgFlags.isNest()) {
2440 if (MCRegister Reg = State.AllocateReg(Reg: X86::R10)) {
2441 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2442 return false;
2443 }
2444 }
2445
2446 if (ArgFlags.isSwiftError()) {
2447 if (LocVT == MVT::i64) {
2448 if (MCRegister Reg = State.AllocateReg(Reg: X86::R12)) {
2449 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2450 return false;
2451 }
2452 }
2453 }
2454
2455 if (ArgFlags.isSwiftSelf()) {
2456 if (LocVT == MVT::i64) {
2457 if (MCRegister Reg = State.AllocateReg(Reg: X86::R13)) {
2458 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2459 return false;
2460 }
2461 }
2462 }
2463
2464 if (ArgFlags.isSwiftAsync()) {
2465 if (LocVT == MVT::i64) {
2466 if (MCRegister Reg = State.AllocateReg(Reg: X86::R14)) {
2467 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2468 return false;
2469 }
2470 }
2471 }
2472
2473 if (ArgFlags.isCFGuardTarget()) {
2474 if (MCRegister Reg = State.AllocateReg(Reg: X86::RAX)) {
2475 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2476 return false;
2477 }
2478 }
2479
2480 if (LocVT == MVT::v16i8 ||
2481 LocVT == MVT::v8i16 ||
2482 LocVT == MVT::v4i32 ||
2483 LocVT == MVT::v2i64 ||
2484 LocVT == MVT::v8f16 ||
2485 LocVT == MVT::v8bf16 ||
2486 LocVT == MVT::v4f32 ||
2487 LocVT == MVT::v2f64) {
2488 LocVT = MVT::i64;
2489 LocInfo = CCValAssign::Indirect;
2490 }
2491
2492 if (LocVT == MVT::v32i8 ||
2493 LocVT == MVT::v16i16 ||
2494 LocVT == MVT::v8i32 ||
2495 LocVT == MVT::v4i64 ||
2496 LocVT == MVT::v16f16 ||
2497 LocVT == MVT::v16bf16 ||
2498 LocVT == MVT::v8f32 ||
2499 LocVT == MVT::v4f64) {
2500 LocVT = MVT::i64;
2501 LocInfo = CCValAssign::Indirect;
2502 }
2503
2504 if (LocVT == MVT::v64i8 ||
2505 LocVT == MVT::v32i16 ||
2506 LocVT == MVT::v16i32 ||
2507 LocVT == MVT::v32f16 ||
2508 LocVT == MVT::v32bf16 ||
2509 LocVT == MVT::v16f32 ||
2510 LocVT == MVT::v8f64 ||
2511 LocVT == MVT::v8i64) {
2512 LocVT = MVT::i64;
2513 LocInfo = CCValAssign::Indirect;
2514 }
2515
2516 if (LocVT == MVT::f80) {
2517 LocVT = MVT::i64;
2518 LocInfo = CCValAssign::Indirect;
2519 }
2520
2521 if (LocVT == MVT::f128) {
2522 LocVT = MVT::i64;
2523 LocInfo = CCValAssign::Indirect;
2524 }
2525
2526 if (LocVT == MVT::f32) {
2527 if (!State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
2528 LocVT = MVT::i32;
2529 LocInfo = CCValAssign::BCvt;
2530 }
2531 }
2532
2533 if (LocVT == MVT::f64) {
2534 if (!State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
2535 LocVT = MVT::i64;
2536 LocInfo = CCValAssign::BCvt;
2537 }
2538 }
2539
2540 if (LocVT == MVT::f16 ||
2541 LocVT == MVT::f32 ||
2542 LocVT == MVT::f64) {
2543 static const MCPhysReg RegList1[] = {
2544 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2545 };
2546 static const MCPhysReg RegList2[] = {
2547 X86::RCX, X86::RDX, X86::R8, X86::R9
2548 };
2549 if (MCRegister Reg = State.AllocateReg(Regs: RegList1, ShadowRegs: RegList2)) {
2550 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2551 return false;
2552 }
2553 }
2554
2555 if (LocVT == MVT::i8) {
2556 static const MCPhysReg RegList3[] = {
2557 X86::CL, X86::DL, X86::R8B, X86::R9B
2558 };
2559 static const MCPhysReg RegList4[] = {
2560 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2561 };
2562 if (MCRegister Reg = State.AllocateReg(Regs: RegList3, ShadowRegs: RegList4)) {
2563 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2564 return false;
2565 }
2566 }
2567
2568 if (LocVT == MVT::i16) {
2569 static const MCPhysReg RegList5[] = {
2570 X86::CX, X86::DX, X86::R8W, X86::R9W
2571 };
2572 static const MCPhysReg RegList6[] = {
2573 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2574 };
2575 if (MCRegister Reg = State.AllocateReg(Regs: RegList5, ShadowRegs: RegList6)) {
2576 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2577 return false;
2578 }
2579 }
2580
2581 if (LocVT == MVT::i32) {
2582 static const MCPhysReg RegList7[] = {
2583 X86::ECX, X86::EDX, X86::R8D, X86::R9D
2584 };
2585 static const MCPhysReg RegList8[] = {
2586 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2587 };
2588 if (MCRegister Reg = State.AllocateReg(Regs: RegList7, ShadowRegs: RegList8)) {
2589 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2590 return false;
2591 }
2592 }
2593
2594 if (State.getCallingConv() == CallingConv::X86_ThisCall) {
2595 if (ArgFlags.isSRet()) {
2596 if (LocVT == MVT::i64) {
2597 static const MCPhysReg RegList9[] = {
2598 X86::RDX, X86::R8, X86::R9
2599 };
2600 static const MCPhysReg RegList10[] = {
2601 X86::XMM1, X86::XMM2, X86::XMM3
2602 };
2603 if (MCRegister Reg = State.AllocateReg(Regs: RegList9, ShadowRegs: RegList10)) {
2604 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2605 return false;
2606 }
2607 }
2608 }
2609 }
2610
2611 if (LocVT == MVT::i64) {
2612 static const MCPhysReg RegList11[] = {
2613 X86::RCX, X86::RDX, X86::R8, X86::R9
2614 };
2615 static const MCPhysReg RegList12[] = {
2616 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2617 };
2618 if (MCRegister Reg = State.AllocateReg(Regs: RegList11, ShadowRegs: RegList12)) {
2619 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2620 return false;
2621 }
2622 }
2623
2624 if (LocVT == MVT::i8 ||
2625 LocVT == MVT::i16 ||
2626 LocVT == MVT::i32 ||
2627 LocVT == MVT::i64 ||
2628 LocVT == MVT::f16 ||
2629 LocVT == MVT::f32 ||
2630 LocVT == MVT::f64) {
2631 int64_t Offset13 = State.AllocateStack(Size: 8, Alignment: Align(8));
2632 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset13, LocVT, HTP: LocInfo));
2633 return false;
2634 }
2635
2636 return true; // CC didn't match.
2637}
2638
2639
2640static bool CC_X86_Win64_RegCall(unsigned ValNo, MVT ValVT,
2641 MVT LocVT, CCValAssign::LocInfo LocInfo,
2642 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2643
2644 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
2645 if (ArgFlags.isByVal()) {
2646 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 8, MinAlign: Align(8), ArgFlags);
2647 return false;
2648 }
2649 }
2650
2651 if (ArgFlags.isByVal()) {
2652 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 4, MinAlign: Align(4), ArgFlags);
2653 return false;
2654 }
2655
2656 if (LocVT == MVT::i1 ||
2657 LocVT == MVT::i8 ||
2658 LocVT == MVT::i16 ||
2659 LocVT == MVT::v1i1) {
2660 LocVT = MVT::i32;
2661 if (ArgFlags.isSExt())
2662 LocInfo = CCValAssign::SExt;
2663 else if (ArgFlags.isZExt())
2664 LocInfo = CCValAssign::ZExt;
2665 else
2666 LocInfo = CCValAssign::AExt;
2667 }
2668
2669 if (LocVT == MVT::v8i1 ||
2670 LocVT == MVT::v16i1 ||
2671 LocVT == MVT::v32i1) {
2672 LocVT = MVT::i32;
2673 if (ArgFlags.isSExt())
2674 LocInfo = CCValAssign::SExt;
2675 else if (ArgFlags.isZExt())
2676 LocInfo = CCValAssign::ZExt;
2677 else
2678 LocInfo = CCValAssign::AExt;
2679 }
2680
2681 if (LocVT == MVT::i32) {
2682 static const MCPhysReg RegList1[] = {
2683 X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R12D, X86::R14D, X86::R15D
2684 };
2685 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
2686 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2687 return false;
2688 }
2689 }
2690
2691 if (LocVT == MVT::i64) {
2692 static const MCPhysReg RegList2[] = {
2693 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15
2694 };
2695 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
2696 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2697 return false;
2698 }
2699 }
2700
2701 if (LocVT == MVT::v64i1) {
2702 LocVT = MVT::i64;
2703 if (ArgFlags.isSExt())
2704 LocInfo = CCValAssign::SExt;
2705 else if (ArgFlags.isZExt())
2706 LocInfo = CCValAssign::ZExt;
2707 else
2708 LocInfo = CCValAssign::AExt;
2709 }
2710
2711 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
2712 if (LocVT == MVT::i64) {
2713 static const MCPhysReg RegList3[] = {
2714 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15
2715 };
2716 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
2717 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2718 return false;
2719 }
2720 }
2721 }
2722
2723 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is32Bit()) {
2724 if (LocVT == MVT::i64) {
2725 if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2726 return false;
2727 }
2728 }
2729
2730 if (LocVT == MVT::f32 ||
2731 LocVT == MVT::f64 ||
2732 LocVT == MVT::f128) {
2733 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
2734 static const MCPhysReg RegList4[] = {
2735 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
2736 };
2737 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
2738 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2739 return false;
2740 }
2741 }
2742 }
2743
2744 if (LocVT == MVT::f80) {
2745 if (MCRegister Reg = State.AllocateReg(Reg: X86::FP0)) {
2746 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2747 return false;
2748 }
2749 }
2750
2751 if (LocVT == MVT::v16i8 ||
2752 LocVT == MVT::v8i16 ||
2753 LocVT == MVT::v4i32 ||
2754 LocVT == MVT::v2i64 ||
2755 LocVT == MVT::v4f32 ||
2756 LocVT == MVT::v2f64) {
2757 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
2758 static const MCPhysReg RegList5[] = {
2759 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
2760 };
2761 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
2762 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2763 return false;
2764 }
2765 }
2766 }
2767
2768 if (LocVT == MVT::v32i8 ||
2769 LocVT == MVT::v16i16 ||
2770 LocVT == MVT::v8i32 ||
2771 LocVT == MVT::v4i64 ||
2772 LocVT == MVT::v8f32 ||
2773 LocVT == MVT::v4f64) {
2774 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX()) {
2775 static const MCPhysReg RegList6[] = {
2776 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15
2777 };
2778 if (MCRegister Reg = State.AllocateReg(Regs: RegList6)) {
2779 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2780 return false;
2781 }
2782 }
2783 }
2784
2785 if (LocVT == MVT::v64i8 ||
2786 LocVT == MVT::v32i16 ||
2787 LocVT == MVT::v16i32 ||
2788 LocVT == MVT::v8i64 ||
2789 LocVT == MVT::v16f32 ||
2790 LocVT == MVT::v8f64) {
2791 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX512()) {
2792 static const MCPhysReg RegList7[] = {
2793 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15
2794 };
2795 if (MCRegister Reg = State.AllocateReg(Regs: RegList7)) {
2796 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2797 return false;
2798 }
2799 }
2800 }
2801
2802 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
2803 if (LocVT == MVT::i32 ||
2804 LocVT == MVT::i64 ||
2805 LocVT == MVT::f32 ||
2806 LocVT == MVT::f64) {
2807 int64_t Offset8 = State.AllocateStack(Size: 8, Alignment: Align(8));
2808 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset8, LocVT, HTP: LocInfo));
2809 return false;
2810 }
2811 }
2812
2813 if (LocVT == MVT::i32 ||
2814 LocVT == MVT::f32) {
2815 int64_t Offset9 = State.AllocateStack(Size: 4, Alignment: Align(4));
2816 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset9, LocVT, HTP: LocInfo));
2817 return false;
2818 }
2819
2820 if (LocVT == MVT::i64 ||
2821 LocVT == MVT::f64) {
2822 int64_t Offset10 = State.AllocateStack(Size: 8, Alignment: Align(4));
2823 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset10, LocVT, HTP: LocInfo));
2824 return false;
2825 }
2826
2827 if (LocVT == MVT::f80 ||
2828 LocVT == MVT::f128) {
2829 int64_t Offset11 = State.AllocateStack(
2830 Size: State.getMachineFunction().getDataLayout().getTypeAllocSize(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())),
2831 Alignment: State.getMachineFunction().getDataLayout().getABITypeAlign(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())));
2832 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset11, LocVT, HTP: LocInfo));
2833 return false;
2834 }
2835
2836 if (LocVT == MVT::v16i8 ||
2837 LocVT == MVT::v8i16 ||
2838 LocVT == MVT::v4i32 ||
2839 LocVT == MVT::v2i64 ||
2840 LocVT == MVT::v4f32 ||
2841 LocVT == MVT::v2f64) {
2842 int64_t Offset12 = State.AllocateStack(Size: 16, Alignment: Align(16));
2843 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset12, LocVT, HTP: LocInfo));
2844 return false;
2845 }
2846
2847 if (LocVT == MVT::v32i8 ||
2848 LocVT == MVT::v16i16 ||
2849 LocVT == MVT::v8i32 ||
2850 LocVT == MVT::v4i64 ||
2851 LocVT == MVT::v8f32 ||
2852 LocVT == MVT::v4f64) {
2853 int64_t Offset13 = State.AllocateStack(Size: 32, Alignment: Align(32));
2854 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset13, LocVT, HTP: LocInfo));
2855 return false;
2856 }
2857
2858 if (LocVT == MVT::v64i8 ||
2859 LocVT == MVT::v32i16 ||
2860 LocVT == MVT::v16i32 ||
2861 LocVT == MVT::v8i64 ||
2862 LocVT == MVT::v16f32 ||
2863 LocVT == MVT::v8f64) {
2864 int64_t Offset14 = State.AllocateStack(Size: 64, Alignment: Align(64));
2865 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset14, LocVT, HTP: LocInfo));
2866 return false;
2867 }
2868
2869 return true; // CC didn't match.
2870}
2871
2872
2873static bool CC_X86_Win64_RegCallv4(unsigned ValNo, MVT ValVT,
2874 MVT LocVT, CCValAssign::LocInfo LocInfo,
2875 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2876
2877 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
2878 if (ArgFlags.isByVal()) {
2879 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 8, MinAlign: Align(8), ArgFlags);
2880 return false;
2881 }
2882 }
2883
2884 if (ArgFlags.isByVal()) {
2885 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 4, MinAlign: Align(4), ArgFlags);
2886 return false;
2887 }
2888
2889 if (LocVT == MVT::i1 ||
2890 LocVT == MVT::i8 ||
2891 LocVT == MVT::i16 ||
2892 LocVT == MVT::v1i1) {
2893 LocVT = MVT::i32;
2894 if (ArgFlags.isSExt())
2895 LocInfo = CCValAssign::SExt;
2896 else if (ArgFlags.isZExt())
2897 LocInfo = CCValAssign::ZExt;
2898 else
2899 LocInfo = CCValAssign::AExt;
2900 }
2901
2902 if (LocVT == MVT::v8i1 ||
2903 LocVT == MVT::v16i1 ||
2904 LocVT == MVT::v32i1) {
2905 LocVT = MVT::i32;
2906 if (ArgFlags.isSExt())
2907 LocInfo = CCValAssign::SExt;
2908 else if (ArgFlags.isZExt())
2909 LocInfo = CCValAssign::ZExt;
2910 else
2911 LocInfo = CCValAssign::AExt;
2912 }
2913
2914 if (LocVT == MVT::i32) {
2915 static const MCPhysReg RegList1[] = {
2916 X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R11D, X86::R12D, X86::R14D, X86::R15D
2917 };
2918 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
2919 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2920 return false;
2921 }
2922 }
2923
2924 if (LocVT == MVT::i64) {
2925 static const MCPhysReg RegList2[] = {
2926 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R11, X86::R12, X86::R14, X86::R15
2927 };
2928 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
2929 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2930 return false;
2931 }
2932 }
2933
2934 if (LocVT == MVT::v64i1) {
2935 LocVT = MVT::i64;
2936 if (ArgFlags.isSExt())
2937 LocInfo = CCValAssign::SExt;
2938 else if (ArgFlags.isZExt())
2939 LocInfo = CCValAssign::ZExt;
2940 else
2941 LocInfo = CCValAssign::AExt;
2942 }
2943
2944 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
2945 if (LocVT == MVT::i64) {
2946 static const MCPhysReg RegList3[] = {
2947 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R11, X86::R12, X86::R14, X86::R15
2948 };
2949 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
2950 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2951 return false;
2952 }
2953 }
2954 }
2955
2956 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is32Bit()) {
2957 if (LocVT == MVT::i64) {
2958 if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2959 return false;
2960 }
2961 }
2962
2963 if (LocVT == MVT::f32 ||
2964 LocVT == MVT::f64 ||
2965 LocVT == MVT::f128) {
2966 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
2967 static const MCPhysReg RegList4[] = {
2968 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
2969 };
2970 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
2971 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2972 return false;
2973 }
2974 }
2975 }
2976
2977 if (LocVT == MVT::f80) {
2978 if (MCRegister Reg = State.AllocateReg(Reg: X86::FP0)) {
2979 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2980 return false;
2981 }
2982 }
2983
2984 if (LocVT == MVT::v16i8 ||
2985 LocVT == MVT::v8i16 ||
2986 LocVT == MVT::v4i32 ||
2987 LocVT == MVT::v2i64 ||
2988 LocVT == MVT::v4f32 ||
2989 LocVT == MVT::v2f64) {
2990 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
2991 static const MCPhysReg RegList5[] = {
2992 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
2993 };
2994 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
2995 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
2996 return false;
2997 }
2998 }
2999 }
3000
3001 if (LocVT == MVT::v32i8 ||
3002 LocVT == MVT::v16i16 ||
3003 LocVT == MVT::v8i32 ||
3004 LocVT == MVT::v4i64 ||
3005 LocVT == MVT::v8f32 ||
3006 LocVT == MVT::v4f64) {
3007 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX()) {
3008 static const MCPhysReg RegList6[] = {
3009 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15
3010 };
3011 if (MCRegister Reg = State.AllocateReg(Regs: RegList6)) {
3012 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3013 return false;
3014 }
3015 }
3016 }
3017
3018 if (LocVT == MVT::v64i8 ||
3019 LocVT == MVT::v32i16 ||
3020 LocVT == MVT::v16i32 ||
3021 LocVT == MVT::v8i64 ||
3022 LocVT == MVT::v16f32 ||
3023 LocVT == MVT::v8f64) {
3024 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX512()) {
3025 static const MCPhysReg RegList7[] = {
3026 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15
3027 };
3028 if (MCRegister Reg = State.AllocateReg(Regs: RegList7)) {
3029 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3030 return false;
3031 }
3032 }
3033 }
3034
3035 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
3036 if (LocVT == MVT::i32 ||
3037 LocVT == MVT::i64 ||
3038 LocVT == MVT::f32 ||
3039 LocVT == MVT::f64) {
3040 int64_t Offset8 = State.AllocateStack(Size: 8, Alignment: Align(8));
3041 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset8, LocVT, HTP: LocInfo));
3042 return false;
3043 }
3044 }
3045
3046 if (LocVT == MVT::i32 ||
3047 LocVT == MVT::f32) {
3048 int64_t Offset9 = State.AllocateStack(Size: 4, Alignment: Align(4));
3049 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset9, LocVT, HTP: LocInfo));
3050 return false;
3051 }
3052
3053 if (LocVT == MVT::i64 ||
3054 LocVT == MVT::f64) {
3055 int64_t Offset10 = State.AllocateStack(Size: 8, Alignment: Align(4));
3056 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset10, LocVT, HTP: LocInfo));
3057 return false;
3058 }
3059
3060 if (LocVT == MVT::f80 ||
3061 LocVT == MVT::f128) {
3062 int64_t Offset11 = State.AllocateStack(
3063 Size: State.getMachineFunction().getDataLayout().getTypeAllocSize(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())),
3064 Alignment: State.getMachineFunction().getDataLayout().getABITypeAlign(Ty: EVT(LocVT).getTypeForEVT(Context&: State.getContext())));
3065 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset11, LocVT, HTP: LocInfo));
3066 return false;
3067 }
3068
3069 if (LocVT == MVT::v16i8 ||
3070 LocVT == MVT::v8i16 ||
3071 LocVT == MVT::v4i32 ||
3072 LocVT == MVT::v2i64 ||
3073 LocVT == MVT::v4f32 ||
3074 LocVT == MVT::v2f64) {
3075 int64_t Offset12 = State.AllocateStack(Size: 16, Alignment: Align(16));
3076 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset12, LocVT, HTP: LocInfo));
3077 return false;
3078 }
3079
3080 if (LocVT == MVT::v32i8 ||
3081 LocVT == MVT::v16i16 ||
3082 LocVT == MVT::v8i32 ||
3083 LocVT == MVT::v4i64 ||
3084 LocVT == MVT::v8f32 ||
3085 LocVT == MVT::v4f64) {
3086 int64_t Offset13 = State.AllocateStack(Size: 32, Alignment: Align(32));
3087 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset13, LocVT, HTP: LocInfo));
3088 return false;
3089 }
3090
3091 if (LocVT == MVT::v64i8 ||
3092 LocVT == MVT::v32i16 ||
3093 LocVT == MVT::v16i32 ||
3094 LocVT == MVT::v8i64 ||
3095 LocVT == MVT::v16f32 ||
3096 LocVT == MVT::v8f64) {
3097 int64_t Offset14 = State.AllocateStack(Size: 64, Alignment: Align(64));
3098 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset14, LocVT, HTP: LocInfo));
3099 return false;
3100 }
3101
3102 return true; // CC didn't match.
3103}
3104
3105
3106static bool CC_X86_Win64_VectorCall(unsigned ValNo, MVT ValVT,
3107 MVT LocVT, CCValAssign::LocInfo LocInfo,
3108 ISD::ArgFlagsTy ArgFlags, CCState &State) {
3109
3110 if (CC_X86_64_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3111 return false;
3112
3113 if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3114 return false;
3115
3116 return true; // CC didn't match.
3117}
3118
3119
3120static bool RetCC_Intel_OCL_BI(unsigned ValNo, MVT ValVT,
3121 MVT LocVT, CCValAssign::LocInfo LocInfo,
3122 ISD::ArgFlagsTy ArgFlags, CCState &State) {
3123
3124 if (LocVT == MVT::f32 ||
3125 LocVT == MVT::f64 ||
3126 LocVT == MVT::v4i32 ||
3127 LocVT == MVT::v2i64 ||
3128 LocVT == MVT::v4f32 ||
3129 LocVT == MVT::v2f64) {
3130 static const MCPhysReg RegList1[] = {
3131 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
3132 };
3133 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
3134 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3135 return false;
3136 }
3137 }
3138
3139 if (LocVT == MVT::v8f32 ||
3140 LocVT == MVT::v4f64 ||
3141 LocVT == MVT::v8i32 ||
3142 LocVT == MVT::v4i64) {
3143 static const MCPhysReg RegList2[] = {
3144 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3
3145 };
3146 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
3147 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3148 return false;
3149 }
3150 }
3151
3152 if (LocVT == MVT::v16f32 ||
3153 LocVT == MVT::v8f64 ||
3154 LocVT == MVT::v16i32 ||
3155 LocVT == MVT::v8i64) {
3156 static const MCPhysReg RegList3[] = {
3157 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3
3158 };
3159 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
3160 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3161 return false;
3162 }
3163 }
3164
3165 if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3166 return false;
3167
3168 return true; // CC didn't match.
3169}
3170
3171
3172bool llvm::RetCC_X86(unsigned ValNo, MVT ValVT,
3173 MVT LocVT, CCValAssign::LocInfo LocInfo,
3174 ISD::ArgFlagsTy ArgFlags, CCState &State) {
3175
3176 if (State.getCallingConv() == CallingConv::Intel_OCL_BI) {
3177 if (!RetCC_Intel_OCL_BI(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3178 return false;
3179 }
3180
3181 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
3182 if (!RetCC_X86_64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3183 return false;
3184 }
3185
3186 if (!RetCC_X86_32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3187 return false;
3188
3189 return true; // CC didn't match.
3190}
3191
3192
3193static bool RetCC_X86Common(unsigned ValNo, MVT ValVT,
3194 MVT LocVT, CCValAssign::LocInfo LocInfo,
3195 ISD::ArgFlagsTy ArgFlags, CCState &State) {
3196
3197 if (LocVT == MVT::v1i1) {
3198 LocVT = MVT::i8;
3199 if (ArgFlags.isSExt())
3200 LocInfo = CCValAssign::SExt;
3201 else if (ArgFlags.isZExt())
3202 LocInfo = CCValAssign::ZExt;
3203 else
3204 LocInfo = CCValAssign::AExt;
3205 }
3206
3207 if (LocVT == MVT::i1) {
3208 LocVT = MVT::i8;
3209 if (ArgFlags.isSExt())
3210 LocInfo = CCValAssign::SExt;
3211 else if (ArgFlags.isZExt())
3212 LocInfo = CCValAssign::ZExt;
3213 else
3214 LocInfo = CCValAssign::AExt;
3215 }
3216
3217 if (LocVT == MVT::i8) {
3218 static const MCPhysReg RegList1[] = {
3219 X86::AL, X86::DL, X86::CL
3220 };
3221 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
3222 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3223 return false;
3224 }
3225 }
3226
3227 if (LocVT == MVT::i16) {
3228 static const MCPhysReg RegList2[] = {
3229 X86::AX, X86::DX, X86::CX
3230 };
3231 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
3232 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3233 return false;
3234 }
3235 }
3236
3237 if (LocVT == MVT::i32) {
3238 static const MCPhysReg RegList3[] = {
3239 X86::EAX, X86::EDX, X86::ECX
3240 };
3241 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
3242 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3243 return false;
3244 }
3245 }
3246
3247 if (LocVT == MVT::i64) {
3248 static const MCPhysReg RegList4[] = {
3249 X86::RAX, X86::RDX, X86::RCX
3250 };
3251 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
3252 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3253 return false;
3254 }
3255 }
3256
3257 if (LocVT == MVT::v2i1) {
3258 LocVT = MVT::v2i64;
3259 if (ArgFlags.isSExt())
3260 LocInfo = CCValAssign::SExt;
3261 else if (ArgFlags.isZExt())
3262 LocInfo = CCValAssign::ZExt;
3263 else
3264 LocInfo = CCValAssign::AExt;
3265 }
3266
3267 if (LocVT == MVT::v4i1) {
3268 LocVT = MVT::v4i32;
3269 if (ArgFlags.isSExt())
3270 LocInfo = CCValAssign::SExt;
3271 else if (ArgFlags.isZExt())
3272 LocInfo = CCValAssign::ZExt;
3273 else
3274 LocInfo = CCValAssign::AExt;
3275 }
3276
3277 if (LocVT == MVT::v8i1) {
3278 LocVT = MVT::v8i16;
3279 if (ArgFlags.isSExt())
3280 LocInfo = CCValAssign::SExt;
3281 else if (ArgFlags.isZExt())
3282 LocInfo = CCValAssign::ZExt;
3283 else
3284 LocInfo = CCValAssign::AExt;
3285 }
3286
3287 if (LocVT == MVT::v16i1) {
3288 LocVT = MVT::v16i8;
3289 if (ArgFlags.isSExt())
3290 LocInfo = CCValAssign::SExt;
3291 else if (ArgFlags.isZExt())
3292 LocInfo = CCValAssign::ZExt;
3293 else
3294 LocInfo = CCValAssign::AExt;
3295 }
3296
3297 if (LocVT == MVT::v32i1) {
3298 LocVT = MVT::v32i8;
3299 if (ArgFlags.isSExt())
3300 LocInfo = CCValAssign::SExt;
3301 else if (ArgFlags.isZExt())
3302 LocInfo = CCValAssign::ZExt;
3303 else
3304 LocInfo = CCValAssign::AExt;
3305 }
3306
3307 if (LocVT == MVT::v64i1) {
3308 LocVT = MVT::v64i8;
3309 if (ArgFlags.isSExt())
3310 LocInfo = CCValAssign::SExt;
3311 else if (ArgFlags.isZExt())
3312 LocInfo = CCValAssign::ZExt;
3313 else
3314 LocInfo = CCValAssign::AExt;
3315 }
3316
3317 if (LocVT == MVT::v16i8 ||
3318 LocVT == MVT::v8i16 ||
3319 LocVT == MVT::v4i32 ||
3320 LocVT == MVT::v2i64 ||
3321 LocVT == MVT::v8f16 ||
3322 LocVT == MVT::v8bf16 ||
3323 LocVT == MVT::v4f32 ||
3324 LocVT == MVT::v2f64) {
3325 static const MCPhysReg RegList5[] = {
3326 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
3327 };
3328 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
3329 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3330 return false;
3331 }
3332 }
3333
3334 if (LocVT == MVT::v32i8 ||
3335 LocVT == MVT::v16i16 ||
3336 LocVT == MVT::v8i32 ||
3337 LocVT == MVT::v4i64 ||
3338 LocVT == MVT::v16f16 ||
3339 LocVT == MVT::v16bf16 ||
3340 LocVT == MVT::v8f32 ||
3341 LocVT == MVT::v4f64) {
3342 static const MCPhysReg RegList6[] = {
3343 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3
3344 };
3345 if (MCRegister Reg = State.AllocateReg(Regs: RegList6)) {
3346 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3347 return false;
3348 }
3349 }
3350
3351 if (LocVT == MVT::v64i8 ||
3352 LocVT == MVT::v32i16 ||
3353 LocVT == MVT::v16i32 ||
3354 LocVT == MVT::v8i64 ||
3355 LocVT == MVT::v32f16 ||
3356 LocVT == MVT::v32bf16 ||
3357 LocVT == MVT::v16f32 ||
3358 LocVT == MVT::v8f64) {
3359 static const MCPhysReg RegList7[] = {
3360 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3
3361 };
3362 if (MCRegister Reg = State.AllocateReg(Regs: RegList7)) {
3363 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3364 return false;
3365 }
3366 }
3367
3368 if (!State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetWin64()) {
3369 if (!State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetUEFI64()) {
3370 if (LocVT == MVT::f80) {
3371 static const MCPhysReg RegList8[] = {
3372 X86::FP0, X86::FP1
3373 };
3374 if (MCRegister Reg = State.AllocateReg(Regs: RegList8)) {
3375 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3376 return false;
3377 }
3378 }
3379 }
3380 }
3381
3382 return true; // CC didn't match.
3383}
3384
3385
3386static bool RetCC_X86_32(unsigned ValNo, MVT ValVT,
3387 MVT LocVT, CCValAssign::LocInfo LocInfo,
3388 ISD::ArgFlagsTy ArgFlags, CCState &State) {
3389
3390 if (State.getCallingConv() == CallingConv::Fast) {
3391 if (!RetCC_X86_32_Fast(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3392 return false;
3393 }
3394
3395 if (State.getCallingConv() == CallingConv::Tail) {
3396 if (!RetCC_X86_32_Fast(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3397 return false;
3398 }
3399
3400 if (State.getCallingConv() == CallingConv::HiPE) {
3401 if (!RetCC_X86_32_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3402 return false;
3403 }
3404
3405 if (State.getCallingConv() == CallingConv::X86_VectorCall) {
3406 if (!RetCC_X86_32_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3407 return false;
3408 }
3409
3410 if (State.getCallingConv() == CallingConv::X86_RegCall) {
3411 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetWin32()) {
3412 if (State.getMachineFunction().getFunction().getParent()->getModuleFlag(Key: "RegCallv4")!=nullptr) {
3413 if (!RetCC_X86_32_RegCallv4_Win(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3414 return false;
3415 }
3416 }
3417 }
3418
3419 if (State.getCallingConv() == CallingConv::X86_RegCall) {
3420 if (!RetCC_X86_32_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3421 return false;
3422 }
3423
3424 if (!RetCC_X86_32_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3425 return false;
3426
3427 return true; // CC didn't match.
3428}
3429
3430
3431static bool RetCC_X86_32_C(unsigned ValNo, MVT ValVT,
3432 MVT LocVT, CCValAssign::LocInfo LocInfo,
3433 ISD::ArgFlagsTy ArgFlags, CCState &State) {
3434
3435 if (ArgFlags.isInReg()) {
3436 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE2()) {
3437 if (LocVT == MVT::f32 ||
3438 LocVT == MVT::f64) {
3439 static const MCPhysReg RegList1[] = {
3440 X86::XMM0, X86::XMM1, X86::XMM2
3441 };
3442 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
3443 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3444 return false;
3445 }
3446 }
3447 }
3448 }
3449
3450 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasX87()) {
3451 if (LocVT == MVT::f32 ||
3452 LocVT == MVT::f64) {
3453 static const MCPhysReg RegList2[] = {
3454 X86::FP0, X86::FP1
3455 };
3456 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
3457 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3458 return false;
3459 }
3460 }
3461 }
3462
3463 if (!State.getMachineFunction().getSubtarget<X86Subtarget>().hasX87()) {
3464 if (LocVT == MVT::f32) {
3465 static const MCPhysReg RegList3[] = {
3466 X86::EAX, X86::EDX, X86::ECX
3467 };
3468 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
3469 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3470 return false;
3471 }
3472 }
3473 }
3474
3475 if (LocVT == MVT::f16) {
3476 static const MCPhysReg RegList4[] = {
3477 X86::XMM0, X86::XMM1, X86::XMM2
3478 };
3479 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
3480 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3481 return false;
3482 }
3483 }
3484
3485 if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3486 return false;
3487
3488 return true; // CC didn't match.
3489}
3490
3491
3492static bool RetCC_X86_32_Fast(unsigned ValNo, MVT ValVT,
3493 MVT LocVT, CCValAssign::LocInfo LocInfo,
3494 ISD::ArgFlagsTy ArgFlags, CCState &State) {
3495
3496 if (LocVT == MVT::f32) {
3497 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE2()) {
3498 static const MCPhysReg RegList1[] = {
3499 X86::XMM0, X86::XMM1, X86::XMM2
3500 };
3501 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
3502 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3503 return false;
3504 }
3505 }
3506 }
3507
3508 if (LocVT == MVT::f64) {
3509 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE2()) {
3510 static const MCPhysReg RegList2[] = {
3511 X86::XMM0, X86::XMM1, X86::XMM2
3512 };
3513 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
3514 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3515 return false;
3516 }
3517 }
3518 }
3519
3520 if (LocVT == MVT::i8) {
3521 static const MCPhysReg RegList3[] = {
3522 X86::AL, X86::DL, X86::CL
3523 };
3524 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
3525 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3526 return false;
3527 }
3528 }
3529
3530 if (LocVT == MVT::i16) {
3531 static const MCPhysReg RegList4[] = {
3532 X86::AX, X86::DX, X86::CX
3533 };
3534 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
3535 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3536 return false;
3537 }
3538 }
3539
3540 if (LocVT == MVT::i32) {
3541 static const MCPhysReg RegList5[] = {
3542 X86::EAX, X86::EDX, X86::ECX
3543 };
3544 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
3545 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3546 return false;
3547 }
3548 }
3549
3550 if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3551 return false;
3552
3553 return true; // CC didn't match.
3554}
3555
3556
3557static bool RetCC_X86_32_HiPE(unsigned ValNo, MVT ValVT,
3558 MVT LocVT, CCValAssign::LocInfo LocInfo,
3559 ISD::ArgFlagsTy ArgFlags, CCState &State) {
3560
3561 if (LocVT == MVT::i8 ||
3562 LocVT == MVT::i16) {
3563 LocVT = MVT::i32;
3564 if (ArgFlags.isSExt())
3565 LocInfo = CCValAssign::SExt;
3566 else if (ArgFlags.isZExt())
3567 LocInfo = CCValAssign::ZExt;
3568 else
3569 LocInfo = CCValAssign::AExt;
3570 }
3571
3572 if (LocVT == MVT::i32) {
3573 static const MCPhysReg RegList1[] = {
3574 X86::ESI, X86::EBP, X86::EAX, X86::EDX
3575 };
3576 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
3577 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3578 return false;
3579 }
3580 }
3581
3582 return true; // CC didn't match.
3583}
3584
3585
3586static bool RetCC_X86_32_RegCall(unsigned ValNo, MVT ValVT,
3587 MVT LocVT, CCValAssign::LocInfo LocInfo,
3588 ISD::ArgFlagsTy ArgFlags, CCState &State) {
3589
3590 if (LocVT == MVT::i1 ||
3591 LocVT == MVT::v1i1 ||
3592 LocVT == MVT::v8i1) {
3593 LocVT = MVT::i8;
3594 if (ArgFlags.isSExt())
3595 LocInfo = CCValAssign::SExt;
3596 else if (ArgFlags.isZExt())
3597 LocInfo = CCValAssign::ZExt;
3598 else
3599 LocInfo = CCValAssign::AExt;
3600 }
3601
3602 if (LocVT == MVT::v16i1) {
3603 LocVT = MVT::i16;
3604 if (ArgFlags.isSExt())
3605 LocInfo = CCValAssign::SExt;
3606 else if (ArgFlags.isZExt())
3607 LocInfo = CCValAssign::ZExt;
3608 else
3609 LocInfo = CCValAssign::AExt;
3610 }
3611
3612 if (LocVT == MVT::v32i1) {
3613 LocVT = MVT::i32;
3614 if (ArgFlags.isSExt())
3615 LocInfo = CCValAssign::SExt;
3616 else if (ArgFlags.isZExt())
3617 LocInfo = CCValAssign::ZExt;
3618 else
3619 LocInfo = CCValAssign::AExt;
3620 }
3621
3622 if (LocVT == MVT::i8) {
3623 static const MCPhysReg RegList1[] = {
3624 X86::AL, X86::CL, X86::DL, X86::DIL, X86::SIL
3625 };
3626 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
3627 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3628 return false;
3629 }
3630 }
3631
3632 if (LocVT == MVT::i16) {
3633 static const MCPhysReg RegList2[] = {
3634 X86::AX, X86::CX, X86::DX, X86::DI, X86::SI
3635 };
3636 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
3637 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3638 return false;
3639 }
3640 }
3641
3642 if (LocVT == MVT::i32) {
3643 static const MCPhysReg RegList3[] = {
3644 X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI
3645 };
3646 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
3647 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3648 return false;
3649 }
3650 }
3651
3652 if (LocVT == MVT::i64) {
3653 if (MCRegister Reg = State.AllocateReg(Reg: X86::RAX)) {
3654 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3655 return false;
3656 }
3657 }
3658
3659 if (LocVT == MVT::v64i1) {
3660 LocVT = MVT::i64;
3661 if (ArgFlags.isSExt())
3662 LocInfo = CCValAssign::SExt;
3663 else if (ArgFlags.isZExt())
3664 LocInfo = CCValAssign::ZExt;
3665 else
3666 LocInfo = CCValAssign::AExt;
3667 }
3668
3669 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
3670 if (LocVT == MVT::i64) {
3671 if (MCRegister Reg = State.AllocateReg(Reg: X86::RAX)) {
3672 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3673 return false;
3674 }
3675 }
3676 }
3677
3678 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is32Bit()) {
3679 if (LocVT == MVT::i64) {
3680 if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3681 return false;
3682 }
3683 }
3684
3685 if (LocVT == MVT::f80) {
3686 static const MCPhysReg RegList4[] = {
3687 X86::FP0, X86::FP1
3688 };
3689 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
3690 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3691 return false;
3692 }
3693 }
3694
3695 if (LocVT == MVT::f32 ||
3696 LocVT == MVT::f64 ||
3697 LocVT == MVT::f128) {
3698 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
3699 static const MCPhysReg RegList5[] = {
3700 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3701 };
3702 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
3703 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3704 return false;
3705 }
3706 }
3707 }
3708
3709 if (LocVT == MVT::v16i8 ||
3710 LocVT == MVT::v8i16 ||
3711 LocVT == MVT::v4i32 ||
3712 LocVT == MVT::v2i64 ||
3713 LocVT == MVT::v4f32 ||
3714 LocVT == MVT::v2f64) {
3715 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
3716 static const MCPhysReg RegList6[] = {
3717 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3718 };
3719 if (MCRegister Reg = State.AllocateReg(Regs: RegList6)) {
3720 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3721 return false;
3722 }
3723 }
3724 }
3725
3726 if (LocVT == MVT::v32i8 ||
3727 LocVT == MVT::v16i16 ||
3728 LocVT == MVT::v8i32 ||
3729 LocVT == MVT::v4i64 ||
3730 LocVT == MVT::v8f32 ||
3731 LocVT == MVT::v4f64) {
3732 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX()) {
3733 static const MCPhysReg RegList7[] = {
3734 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7
3735 };
3736 if (MCRegister Reg = State.AllocateReg(Regs: RegList7)) {
3737 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3738 return false;
3739 }
3740 }
3741 }
3742
3743 if (LocVT == MVT::v64i8 ||
3744 LocVT == MVT::v32i16 ||
3745 LocVT == MVT::v16i32 ||
3746 LocVT == MVT::v8i64 ||
3747 LocVT == MVT::v16f32 ||
3748 LocVT == MVT::v8f64) {
3749 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX512()) {
3750 static const MCPhysReg RegList8[] = {
3751 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7
3752 };
3753 if (MCRegister Reg = State.AllocateReg(Regs: RegList8)) {
3754 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3755 return false;
3756 }
3757 }
3758 }
3759
3760 return true; // CC didn't match.
3761}
3762
3763
3764static bool RetCC_X86_32_RegCallv4_Win(unsigned ValNo, MVT ValVT,
3765 MVT LocVT, CCValAssign::LocInfo LocInfo,
3766 ISD::ArgFlagsTy ArgFlags, CCState &State) {
3767
3768 if (LocVT == MVT::i1 ||
3769 LocVT == MVT::v1i1 ||
3770 LocVT == MVT::v8i1) {
3771 LocVT = MVT::i8;
3772 if (ArgFlags.isSExt())
3773 LocInfo = CCValAssign::SExt;
3774 else if (ArgFlags.isZExt())
3775 LocInfo = CCValAssign::ZExt;
3776 else
3777 LocInfo = CCValAssign::AExt;
3778 }
3779
3780 if (LocVT == MVT::v16i1) {
3781 LocVT = MVT::i16;
3782 if (ArgFlags.isSExt())
3783 LocInfo = CCValAssign::SExt;
3784 else if (ArgFlags.isZExt())
3785 LocInfo = CCValAssign::ZExt;
3786 else
3787 LocInfo = CCValAssign::AExt;
3788 }
3789
3790 if (LocVT == MVT::v32i1) {
3791 LocVT = MVT::i32;
3792 if (ArgFlags.isSExt())
3793 LocInfo = CCValAssign::SExt;
3794 else if (ArgFlags.isZExt())
3795 LocInfo = CCValAssign::ZExt;
3796 else
3797 LocInfo = CCValAssign::AExt;
3798 }
3799
3800 if (LocVT == MVT::i8) {
3801 static const MCPhysReg RegList1[] = {
3802 X86::CL, X86::DL, X86::DIL, X86::SIL
3803 };
3804 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
3805 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3806 return false;
3807 }
3808 }
3809
3810 if (LocVT == MVT::i16) {
3811 static const MCPhysReg RegList2[] = {
3812 X86::CX, X86::DX, X86::DI, X86::SI
3813 };
3814 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
3815 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3816 return false;
3817 }
3818 }
3819
3820 if (LocVT == MVT::i32) {
3821 static const MCPhysReg RegList3[] = {
3822 X86::ECX, X86::EDX, X86::EDI, X86::ESI
3823 };
3824 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
3825 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3826 return false;
3827 }
3828 }
3829
3830 if (LocVT == MVT::i64) {
3831 if (MCRegister Reg = State.AllocateReg(Reg: X86::RAX)) {
3832 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3833 return false;
3834 }
3835 }
3836
3837 if (LocVT == MVT::v64i1) {
3838 LocVT = MVT::i64;
3839 if (ArgFlags.isSExt())
3840 LocInfo = CCValAssign::SExt;
3841 else if (ArgFlags.isZExt())
3842 LocInfo = CCValAssign::ZExt;
3843 else
3844 LocInfo = CCValAssign::AExt;
3845 }
3846
3847 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
3848 if (LocVT == MVT::i64) {
3849 if (MCRegister Reg = State.AllocateReg(Reg: X86::RAX)) {
3850 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3851 return false;
3852 }
3853 }
3854 }
3855
3856 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is32Bit()) {
3857 if (LocVT == MVT::i64) {
3858 if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3859 return false;
3860 }
3861 }
3862
3863 if (LocVT == MVT::f80) {
3864 static const MCPhysReg RegList4[] = {
3865 X86::FP0, X86::FP1
3866 };
3867 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
3868 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3869 return false;
3870 }
3871 }
3872
3873 if (LocVT == MVT::f32 ||
3874 LocVT == MVT::f64 ||
3875 LocVT == MVT::f128) {
3876 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
3877 static const MCPhysReg RegList5[] = {
3878 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3879 };
3880 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
3881 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3882 return false;
3883 }
3884 }
3885 }
3886
3887 if (LocVT == MVT::v16i8 ||
3888 LocVT == MVT::v8i16 ||
3889 LocVT == MVT::v4i32 ||
3890 LocVT == MVT::v2i64 ||
3891 LocVT == MVT::v4f32 ||
3892 LocVT == MVT::v2f64) {
3893 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
3894 static const MCPhysReg RegList6[] = {
3895 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3896 };
3897 if (MCRegister Reg = State.AllocateReg(Regs: RegList6)) {
3898 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3899 return false;
3900 }
3901 }
3902 }
3903
3904 if (LocVT == MVT::v32i8 ||
3905 LocVT == MVT::v16i16 ||
3906 LocVT == MVT::v8i32 ||
3907 LocVT == MVT::v4i64 ||
3908 LocVT == MVT::v8f32 ||
3909 LocVT == MVT::v4f64) {
3910 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX()) {
3911 static const MCPhysReg RegList7[] = {
3912 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7
3913 };
3914 if (MCRegister Reg = State.AllocateReg(Regs: RegList7)) {
3915 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3916 return false;
3917 }
3918 }
3919 }
3920
3921 if (LocVT == MVT::v64i8 ||
3922 LocVT == MVT::v32i16 ||
3923 LocVT == MVT::v16i32 ||
3924 LocVT == MVT::v8i64 ||
3925 LocVT == MVT::v16f32 ||
3926 LocVT == MVT::v8f64) {
3927 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX512()) {
3928 static const MCPhysReg RegList8[] = {
3929 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7
3930 };
3931 if (MCRegister Reg = State.AllocateReg(Regs: RegList8)) {
3932 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3933 return false;
3934 }
3935 }
3936 }
3937
3938 return true; // CC didn't match.
3939}
3940
3941
3942static bool RetCC_X86_32_VectorCall(unsigned ValNo, MVT ValVT,
3943 MVT LocVT, CCValAssign::LocInfo LocInfo,
3944 ISD::ArgFlagsTy ArgFlags, CCState &State) {
3945
3946 if (LocVT == MVT::f32 ||
3947 LocVT == MVT::f64 ||
3948 LocVT == MVT::f128) {
3949 static const MCPhysReg RegList1[] = {
3950 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
3951 };
3952 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
3953 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
3954 return false;
3955 }
3956 }
3957
3958 if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3959 return false;
3960
3961 return true; // CC didn't match.
3962}
3963
3964
3965static bool RetCC_X86_64(unsigned ValNo, MVT ValVT,
3966 MVT LocVT, CCValAssign::LocInfo LocInfo,
3967 ISD::ArgFlagsTy ArgFlags, CCState &State) {
3968
3969 if (State.getCallingConv() == CallingConv::HiPE) {
3970 if (!RetCC_X86_64_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3971 return false;
3972 }
3973
3974 if (State.getCallingConv() == CallingConv::AnyReg) {
3975 if (!RetCC_X86_64_AnyReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3976 return false;
3977 }
3978
3979 if (State.getCallingConv() == CallingConv::Swift) {
3980 if (!RetCC_X86_64_Swift(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3981 return false;
3982 }
3983
3984 if (State.getCallingConv() == CallingConv::SwiftTail) {
3985 if (!RetCC_X86_64_Swift(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3986 return false;
3987 }
3988
3989 if (State.getCallingConv() == CallingConv::Win64) {
3990 if (!RetCC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3991 return false;
3992 }
3993
3994 if (State.getCallingConv() == CallingConv::X86_64_SysV) {
3995 if (!RetCC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3996 return false;
3997 }
3998
3999 if (State.getCallingConv() == CallingConv::X86_VectorCall) {
4000 if (!RetCC_X86_64_Vectorcall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
4001 return false;
4002 }
4003
4004 if (State.getCallingConv() == CallingConv::X86_RegCall) {
4005 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetWin64()) {
4006 if (State.getMachineFunction().getFunction().getParent()->getModuleFlag(Key: "RegCallv4")!=nullptr) {
4007 if (!RetCC_X86_Win64_RegCallv4(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
4008 return false;
4009 }
4010 }
4011 }
4012
4013 if (State.getCallingConv() == CallingConv::X86_RegCall) {
4014 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetWin64()) {
4015 if (!RetCC_X86_Win64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
4016 return false;
4017 }
4018 }
4019
4020 if (State.getCallingConv() == CallingConv::X86_RegCall) {
4021 if (!RetCC_X86_SysV64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
4022 return false;
4023 }
4024
4025 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetWin64()) {
4026 if (!RetCC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
4027 return false;
4028 }
4029
4030 if (State.getMachineFunction().getSubtarget<X86Subtarget>().isTargetUEFI64()) {
4031 if (!RetCC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
4032 return false;
4033 }
4034
4035 if (!RetCC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
4036 return false;
4037
4038 return true; // CC didn't match.
4039}
4040
4041
4042static bool RetCC_X86_64_AnyReg(unsigned ValNo, MVT ValVT,
4043 MVT LocVT, CCValAssign::LocInfo LocInfo,
4044 ISD::ArgFlagsTy ArgFlags, CCState &State) {
4045
4046 if (CC_X86_AnyReg_Error(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
4047 return false;
4048
4049 return true; // CC didn't match.
4050}
4051
4052
4053static bool RetCC_X86_64_C(unsigned ValNo, MVT ValVT,
4054 MVT LocVT, CCValAssign::LocInfo LocInfo,
4055 ISD::ArgFlagsTy ArgFlags, CCState &State) {
4056
4057 if (LocVT == MVT::f16) {
4058 static const MCPhysReg RegList1[] = {
4059 X86::XMM0, X86::XMM1
4060 };
4061 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
4062 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4063 return false;
4064 }
4065 }
4066
4067 if (LocVT == MVT::f32) {
4068 static const MCPhysReg RegList2[] = {
4069 X86::XMM0, X86::XMM1
4070 };
4071 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
4072 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4073 return false;
4074 }
4075 }
4076
4077 if (LocVT == MVT::f64) {
4078 static const MCPhysReg RegList3[] = {
4079 X86::XMM0, X86::XMM1
4080 };
4081 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
4082 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4083 return false;
4084 }
4085 }
4086
4087 if (LocVT == MVT::f128) {
4088 static const MCPhysReg RegList4[] = {
4089 X86::XMM0, X86::XMM1
4090 };
4091 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
4092 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4093 return false;
4094 }
4095 }
4096
4097 if (ArgFlags.isPointer()) {
4098 if (CC_X86_64_Pointer(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
4099 return false;
4100 }
4101
4102 if (ArgFlags.isSwiftError()) {
4103 if (LocVT == MVT::i64) {
4104 if (MCRegister Reg = State.AllocateReg(Reg: X86::R12)) {
4105 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4106 return false;
4107 }
4108 }
4109 }
4110
4111 if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
4112 return false;
4113
4114 return true; // CC didn't match.
4115}
4116
4117
4118static bool RetCC_X86_64_HiPE(unsigned ValNo, MVT ValVT,
4119 MVT LocVT, CCValAssign::LocInfo LocInfo,
4120 ISD::ArgFlagsTy ArgFlags, CCState &State) {
4121
4122 if (LocVT == MVT::i8 ||
4123 LocVT == MVT::i16 ||
4124 LocVT == MVT::i32) {
4125 LocVT = MVT::i64;
4126 if (ArgFlags.isSExt())
4127 LocInfo = CCValAssign::SExt;
4128 else if (ArgFlags.isZExt())
4129 LocInfo = CCValAssign::ZExt;
4130 else
4131 LocInfo = CCValAssign::AExt;
4132 }
4133
4134 if (LocVT == MVT::i64) {
4135 static const MCPhysReg RegList1[] = {
4136 X86::R15, X86::RBP, X86::RAX, X86::RDX
4137 };
4138 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
4139 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4140 return false;
4141 }
4142 }
4143
4144 return true; // CC didn't match.
4145}
4146
4147
4148static bool RetCC_X86_64_Swift(unsigned ValNo, MVT ValVT,
4149 MVT LocVT, CCValAssign::LocInfo LocInfo,
4150 ISD::ArgFlagsTy ArgFlags, CCState &State) {
4151
4152 if (ArgFlags.isSwiftError()) {
4153 if (LocVT == MVT::i64) {
4154 if (MCRegister Reg = State.AllocateReg(Reg: X86::R12)) {
4155 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4156 return false;
4157 }
4158 }
4159 }
4160
4161 if (LocVT == MVT::v1i1) {
4162 LocVT = MVT::i8;
4163 if (ArgFlags.isSExt())
4164 LocInfo = CCValAssign::SExt;
4165 else if (ArgFlags.isZExt())
4166 LocInfo = CCValAssign::ZExt;
4167 else
4168 LocInfo = CCValAssign::AExt;
4169 }
4170
4171 if (LocVT == MVT::i1) {
4172 LocVT = MVT::i8;
4173 if (ArgFlags.isSExt())
4174 LocInfo = CCValAssign::SExt;
4175 else if (ArgFlags.isZExt())
4176 LocInfo = CCValAssign::ZExt;
4177 else
4178 LocInfo = CCValAssign::AExt;
4179 }
4180
4181 if (LocVT == MVT::i8) {
4182 static const MCPhysReg RegList1[] = {
4183 X86::AL, X86::DL, X86::CL, X86::R8B
4184 };
4185 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
4186 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4187 return false;
4188 }
4189 }
4190
4191 if (LocVT == MVT::i16) {
4192 static const MCPhysReg RegList2[] = {
4193 X86::AX, X86::DX, X86::CX, X86::R8W
4194 };
4195 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
4196 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4197 return false;
4198 }
4199 }
4200
4201 if (LocVT == MVT::i32) {
4202 static const MCPhysReg RegList3[] = {
4203 X86::EAX, X86::EDX, X86::ECX, X86::R8D
4204 };
4205 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
4206 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4207 return false;
4208 }
4209 }
4210
4211 if (LocVT == MVT::i64) {
4212 static const MCPhysReg RegList4[] = {
4213 X86::RAX, X86::RDX, X86::RCX, X86::R8
4214 };
4215 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
4216 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4217 return false;
4218 }
4219 }
4220
4221 if (LocVT == MVT::f32) {
4222 static const MCPhysReg RegList5[] = {
4223 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
4224 };
4225 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
4226 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4227 return false;
4228 }
4229 }
4230
4231 if (LocVT == MVT::f64) {
4232 static const MCPhysReg RegList6[] = {
4233 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
4234 };
4235 if (MCRegister Reg = State.AllocateReg(Regs: RegList6)) {
4236 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4237 return false;
4238 }
4239 }
4240
4241 if (LocVT == MVT::f128) {
4242 static const MCPhysReg RegList7[] = {
4243 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
4244 };
4245 if (MCRegister Reg = State.AllocateReg(Regs: RegList7)) {
4246 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4247 return false;
4248 }
4249 }
4250
4251 if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
4252 return false;
4253
4254 return true; // CC didn't match.
4255}
4256
4257
4258static bool RetCC_X86_64_Vectorcall(unsigned ValNo, MVT ValVT,
4259 MVT LocVT, CCValAssign::LocInfo LocInfo,
4260 ISD::ArgFlagsTy ArgFlags, CCState &State) {
4261
4262 if (LocVT == MVT::f32 ||
4263 LocVT == MVT::f64 ||
4264 LocVT == MVT::f128) {
4265 static const MCPhysReg RegList1[] = {
4266 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
4267 };
4268 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
4269 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4270 return false;
4271 }
4272 }
4273
4274 if (!RetCC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
4275 return false;
4276
4277 return true; // CC didn't match.
4278}
4279
4280
4281static bool RetCC_X86_SysV64_RegCall(unsigned ValNo, MVT ValVT,
4282 MVT LocVT, CCValAssign::LocInfo LocInfo,
4283 ISD::ArgFlagsTy ArgFlags, CCState &State) {
4284
4285 if (LocVT == MVT::i1 ||
4286 LocVT == MVT::v1i1 ||
4287 LocVT == MVT::v8i1) {
4288 LocVT = MVT::i8;
4289 if (ArgFlags.isSExt())
4290 LocInfo = CCValAssign::SExt;
4291 else if (ArgFlags.isZExt())
4292 LocInfo = CCValAssign::ZExt;
4293 else
4294 LocInfo = CCValAssign::AExt;
4295 }
4296
4297 if (LocVT == MVT::v16i1) {
4298 LocVT = MVT::i16;
4299 if (ArgFlags.isSExt())
4300 LocInfo = CCValAssign::SExt;
4301 else if (ArgFlags.isZExt())
4302 LocInfo = CCValAssign::ZExt;
4303 else
4304 LocInfo = CCValAssign::AExt;
4305 }
4306
4307 if (LocVT == MVT::v32i1) {
4308 LocVT = MVT::i32;
4309 if (ArgFlags.isSExt())
4310 LocInfo = CCValAssign::SExt;
4311 else if (ArgFlags.isZExt())
4312 LocInfo = CCValAssign::ZExt;
4313 else
4314 LocInfo = CCValAssign::AExt;
4315 }
4316
4317 if (LocVT == MVT::i8) {
4318 static const MCPhysReg RegList1[] = {
4319 X86::AL, X86::CL, X86::DL, X86::DIL, X86::SIL, X86::R8B, X86::R9B, X86::R12B, X86::R13B, X86::R14B, X86::R15B
4320 };
4321 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
4322 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4323 return false;
4324 }
4325 }
4326
4327 if (LocVT == MVT::i16) {
4328 static const MCPhysReg RegList2[] = {
4329 X86::AX, X86::CX, X86::DX, X86::DI, X86::SI, X86::R8W, X86::R9W, X86::R12W, X86::R13W, X86::R14W, X86::R15W
4330 };
4331 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
4332 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4333 return false;
4334 }
4335 }
4336
4337 if (LocVT == MVT::i32) {
4338 static const MCPhysReg RegList3[] = {
4339 X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R12D, X86::R13D, X86::R14D, X86::R15D
4340 };
4341 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
4342 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4343 return false;
4344 }
4345 }
4346
4347 if (LocVT == MVT::i64) {
4348 static const MCPhysReg RegList4[] = {
4349 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15
4350 };
4351 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
4352 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4353 return false;
4354 }
4355 }
4356
4357 if (LocVT == MVT::v64i1) {
4358 LocVT = MVT::i64;
4359 if (ArgFlags.isSExt())
4360 LocInfo = CCValAssign::SExt;
4361 else if (ArgFlags.isZExt())
4362 LocInfo = CCValAssign::ZExt;
4363 else
4364 LocInfo = CCValAssign::AExt;
4365 }
4366
4367 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
4368 if (LocVT == MVT::i64) {
4369 static const MCPhysReg RegList5[] = {
4370 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15
4371 };
4372 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
4373 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4374 return false;
4375 }
4376 }
4377 }
4378
4379 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is32Bit()) {
4380 if (LocVT == MVT::i64) {
4381 if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
4382 return false;
4383 }
4384 }
4385
4386 if (LocVT == MVT::f80) {
4387 static const MCPhysReg RegList6[] = {
4388 X86::FP0, X86::FP1
4389 };
4390 if (MCRegister Reg = State.AllocateReg(Regs: RegList6)) {
4391 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4392 return false;
4393 }
4394 }
4395
4396 if (LocVT == MVT::f32 ||
4397 LocVT == MVT::f64 ||
4398 LocVT == MVT::f128) {
4399 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
4400 static const MCPhysReg RegList7[] = {
4401 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
4402 };
4403 if (MCRegister Reg = State.AllocateReg(Regs: RegList7)) {
4404 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4405 return false;
4406 }
4407 }
4408 }
4409
4410 if (LocVT == MVT::v16i8 ||
4411 LocVT == MVT::v8i16 ||
4412 LocVT == MVT::v4i32 ||
4413 LocVT == MVT::v2i64 ||
4414 LocVT == MVT::v4f32 ||
4415 LocVT == MVT::v2f64) {
4416 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
4417 static const MCPhysReg RegList8[] = {
4418 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
4419 };
4420 if (MCRegister Reg = State.AllocateReg(Regs: RegList8)) {
4421 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4422 return false;
4423 }
4424 }
4425 }
4426
4427 if (LocVT == MVT::v32i8 ||
4428 LocVT == MVT::v16i16 ||
4429 LocVT == MVT::v8i32 ||
4430 LocVT == MVT::v4i64 ||
4431 LocVT == MVT::v8f32 ||
4432 LocVT == MVT::v4f64) {
4433 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX()) {
4434 static const MCPhysReg RegList9[] = {
4435 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15
4436 };
4437 if (MCRegister Reg = State.AllocateReg(Regs: RegList9)) {
4438 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4439 return false;
4440 }
4441 }
4442 }
4443
4444 if (LocVT == MVT::v64i8 ||
4445 LocVT == MVT::v32i16 ||
4446 LocVT == MVT::v16i32 ||
4447 LocVT == MVT::v8i64 ||
4448 LocVT == MVT::v16f32 ||
4449 LocVT == MVT::v8f64) {
4450 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX512()) {
4451 static const MCPhysReg RegList10[] = {
4452 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15
4453 };
4454 if (MCRegister Reg = State.AllocateReg(Regs: RegList10)) {
4455 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4456 return false;
4457 }
4458 }
4459 }
4460
4461 return true; // CC didn't match.
4462}
4463
4464
4465static bool RetCC_X86_Win64_C(unsigned ValNo, MVT ValVT,
4466 MVT LocVT, CCValAssign::LocInfo LocInfo,
4467 ISD::ArgFlagsTy ArgFlags, CCState &State) {
4468
4469 if (LocVT == MVT::f32) {
4470 if (!State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
4471 LocVT = MVT::i32;
4472 LocInfo = CCValAssign::BCvt;
4473 }
4474 }
4475
4476 if (LocVT == MVT::f64) {
4477 if (!State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
4478 LocVT = MVT::i64;
4479 LocInfo = CCValAssign::BCvt;
4480 }
4481 }
4482
4483 if (!RetCC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
4484 return false;
4485
4486 return true; // CC didn't match.
4487}
4488
4489
4490static bool RetCC_X86_Win64_RegCall(unsigned ValNo, MVT ValVT,
4491 MVT LocVT, CCValAssign::LocInfo LocInfo,
4492 ISD::ArgFlagsTy ArgFlags, CCState &State) {
4493
4494 if (LocVT == MVT::i1 ||
4495 LocVT == MVT::v1i1 ||
4496 LocVT == MVT::v8i1) {
4497 LocVT = MVT::i8;
4498 if (ArgFlags.isSExt())
4499 LocInfo = CCValAssign::SExt;
4500 else if (ArgFlags.isZExt())
4501 LocInfo = CCValAssign::ZExt;
4502 else
4503 LocInfo = CCValAssign::AExt;
4504 }
4505
4506 if (LocVT == MVT::v16i1) {
4507 LocVT = MVT::i16;
4508 if (ArgFlags.isSExt())
4509 LocInfo = CCValAssign::SExt;
4510 else if (ArgFlags.isZExt())
4511 LocInfo = CCValAssign::ZExt;
4512 else
4513 LocInfo = CCValAssign::AExt;
4514 }
4515
4516 if (LocVT == MVT::v32i1) {
4517 LocVT = MVT::i32;
4518 if (ArgFlags.isSExt())
4519 LocInfo = CCValAssign::SExt;
4520 else if (ArgFlags.isZExt())
4521 LocInfo = CCValAssign::ZExt;
4522 else
4523 LocInfo = CCValAssign::AExt;
4524 }
4525
4526 if (LocVT == MVT::i8) {
4527 static const MCPhysReg RegList1[] = {
4528 X86::AL, X86::CL, X86::DL, X86::DIL, X86::SIL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R12B, X86::R14B, X86::R15B
4529 };
4530 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
4531 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4532 return false;
4533 }
4534 }
4535
4536 if (LocVT == MVT::i16) {
4537 static const MCPhysReg RegList2[] = {
4538 X86::AX, X86::CX, X86::DX, X86::DI, X86::SI, X86::R8W, X86::R9W, X86::R10W, X86::R11W, X86::R12W, X86::R14W, X86::R15W
4539 };
4540 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
4541 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4542 return false;
4543 }
4544 }
4545
4546 if (LocVT == MVT::i32) {
4547 static const MCPhysReg RegList3[] = {
4548 X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R12D, X86::R14D, X86::R15D
4549 };
4550 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
4551 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4552 return false;
4553 }
4554 }
4555
4556 if (LocVT == MVT::i64) {
4557 static const MCPhysReg RegList4[] = {
4558 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15
4559 };
4560 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
4561 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4562 return false;
4563 }
4564 }
4565
4566 if (LocVT == MVT::v64i1) {
4567 LocVT = MVT::i64;
4568 if (ArgFlags.isSExt())
4569 LocInfo = CCValAssign::SExt;
4570 else if (ArgFlags.isZExt())
4571 LocInfo = CCValAssign::ZExt;
4572 else
4573 LocInfo = CCValAssign::AExt;
4574 }
4575
4576 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
4577 if (LocVT == MVT::i64) {
4578 static const MCPhysReg RegList5[] = {
4579 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15
4580 };
4581 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
4582 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4583 return false;
4584 }
4585 }
4586 }
4587
4588 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is32Bit()) {
4589 if (LocVT == MVT::i64) {
4590 if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
4591 return false;
4592 }
4593 }
4594
4595 if (LocVT == MVT::f80) {
4596 static const MCPhysReg RegList6[] = {
4597 X86::FP0, X86::FP1
4598 };
4599 if (MCRegister Reg = State.AllocateReg(Regs: RegList6)) {
4600 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4601 return false;
4602 }
4603 }
4604
4605 if (LocVT == MVT::f32 ||
4606 LocVT == MVT::f64 ||
4607 LocVT == MVT::f128) {
4608 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
4609 static const MCPhysReg RegList7[] = {
4610 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
4611 };
4612 if (MCRegister Reg = State.AllocateReg(Regs: RegList7)) {
4613 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4614 return false;
4615 }
4616 }
4617 }
4618
4619 if (LocVT == MVT::v16i8 ||
4620 LocVT == MVT::v8i16 ||
4621 LocVT == MVT::v4i32 ||
4622 LocVT == MVT::v2i64 ||
4623 LocVT == MVT::v4f32 ||
4624 LocVT == MVT::v2f64) {
4625 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
4626 static const MCPhysReg RegList8[] = {
4627 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
4628 };
4629 if (MCRegister Reg = State.AllocateReg(Regs: RegList8)) {
4630 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4631 return false;
4632 }
4633 }
4634 }
4635
4636 if (LocVT == MVT::v32i8 ||
4637 LocVT == MVT::v16i16 ||
4638 LocVT == MVT::v8i32 ||
4639 LocVT == MVT::v4i64 ||
4640 LocVT == MVT::v8f32 ||
4641 LocVT == MVT::v4f64) {
4642 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX()) {
4643 static const MCPhysReg RegList9[] = {
4644 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15
4645 };
4646 if (MCRegister Reg = State.AllocateReg(Regs: RegList9)) {
4647 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4648 return false;
4649 }
4650 }
4651 }
4652
4653 if (LocVT == MVT::v64i8 ||
4654 LocVT == MVT::v32i16 ||
4655 LocVT == MVT::v16i32 ||
4656 LocVT == MVT::v8i64 ||
4657 LocVT == MVT::v16f32 ||
4658 LocVT == MVT::v8f64) {
4659 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX512()) {
4660 static const MCPhysReg RegList10[] = {
4661 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15
4662 };
4663 if (MCRegister Reg = State.AllocateReg(Regs: RegList10)) {
4664 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4665 return false;
4666 }
4667 }
4668 }
4669
4670 return true; // CC didn't match.
4671}
4672
4673
4674static bool RetCC_X86_Win64_RegCallv4(unsigned ValNo, MVT ValVT,
4675 MVT LocVT, CCValAssign::LocInfo LocInfo,
4676 ISD::ArgFlagsTy ArgFlags, CCState &State) {
4677
4678 if (LocVT == MVT::i1 ||
4679 LocVT == MVT::v1i1 ||
4680 LocVT == MVT::v8i1) {
4681 LocVT = MVT::i8;
4682 if (ArgFlags.isSExt())
4683 LocInfo = CCValAssign::SExt;
4684 else if (ArgFlags.isZExt())
4685 LocInfo = CCValAssign::ZExt;
4686 else
4687 LocInfo = CCValAssign::AExt;
4688 }
4689
4690 if (LocVT == MVT::v16i1) {
4691 LocVT = MVT::i16;
4692 if (ArgFlags.isSExt())
4693 LocInfo = CCValAssign::SExt;
4694 else if (ArgFlags.isZExt())
4695 LocInfo = CCValAssign::ZExt;
4696 else
4697 LocInfo = CCValAssign::AExt;
4698 }
4699
4700 if (LocVT == MVT::v32i1) {
4701 LocVT = MVT::i32;
4702 if (ArgFlags.isSExt())
4703 LocInfo = CCValAssign::SExt;
4704 else if (ArgFlags.isZExt())
4705 LocInfo = CCValAssign::ZExt;
4706 else
4707 LocInfo = CCValAssign::AExt;
4708 }
4709
4710 if (LocVT == MVT::i8) {
4711 static const MCPhysReg RegList1[] = {
4712 X86::AL, X86::CL, X86::DL, X86::DIL, X86::SIL, X86::R8B, X86::R9B, X86::R11B, X86::R12B, X86::R14B, X86::R15B
4713 };
4714 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
4715 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4716 return false;
4717 }
4718 }
4719
4720 if (LocVT == MVT::i16) {
4721 static const MCPhysReg RegList2[] = {
4722 X86::AX, X86::CX, X86::DX, X86::DI, X86::SI, X86::R8W, X86::R9W, X86::R11W, X86::R12W, X86::R14W, X86::R15W
4723 };
4724 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
4725 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4726 return false;
4727 }
4728 }
4729
4730 if (LocVT == MVT::i32) {
4731 static const MCPhysReg RegList3[] = {
4732 X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R11D, X86::R12D, X86::R14D, X86::R15D
4733 };
4734 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
4735 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4736 return false;
4737 }
4738 }
4739
4740 if (LocVT == MVT::i64) {
4741 static const MCPhysReg RegList4[] = {
4742 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R11, X86::R12, X86::R14, X86::R15
4743 };
4744 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
4745 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4746 return false;
4747 }
4748 }
4749
4750 if (LocVT == MVT::v64i1) {
4751 LocVT = MVT::i64;
4752 if (ArgFlags.isSExt())
4753 LocInfo = CCValAssign::SExt;
4754 else if (ArgFlags.isZExt())
4755 LocInfo = CCValAssign::ZExt;
4756 else
4757 LocInfo = CCValAssign::AExt;
4758 }
4759
4760 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is64Bit()) {
4761 if (LocVT == MVT::i64) {
4762 static const MCPhysReg RegList5[] = {
4763 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R11, X86::R12, X86::R14, X86::R15
4764 };
4765 if (MCRegister Reg = State.AllocateReg(Regs: RegList5)) {
4766 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4767 return false;
4768 }
4769 }
4770 }
4771
4772 if (State.getMachineFunction().getSubtarget<X86Subtarget>().is32Bit()) {
4773 if (LocVT == MVT::i64) {
4774 if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
4775 return false;
4776 }
4777 }
4778
4779 if (LocVT == MVT::f80) {
4780 static const MCPhysReg RegList6[] = {
4781 X86::FP0, X86::FP1
4782 };
4783 if (MCRegister Reg = State.AllocateReg(Regs: RegList6)) {
4784 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4785 return false;
4786 }
4787 }
4788
4789 if (LocVT == MVT::f32 ||
4790 LocVT == MVT::f64 ||
4791 LocVT == MVT::f128) {
4792 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
4793 static const MCPhysReg RegList7[] = {
4794 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
4795 };
4796 if (MCRegister Reg = State.AllocateReg(Regs: RegList7)) {
4797 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4798 return false;
4799 }
4800 }
4801 }
4802
4803 if (LocVT == MVT::v16i8 ||
4804 LocVT == MVT::v8i16 ||
4805 LocVT == MVT::v4i32 ||
4806 LocVT == MVT::v2i64 ||
4807 LocVT == MVT::v4f32 ||
4808 LocVT == MVT::v2f64) {
4809 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasSSE1()) {
4810 static const MCPhysReg RegList8[] = {
4811 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
4812 };
4813 if (MCRegister Reg = State.AllocateReg(Regs: RegList8)) {
4814 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4815 return false;
4816 }
4817 }
4818 }
4819
4820 if (LocVT == MVT::v32i8 ||
4821 LocVT == MVT::v16i16 ||
4822 LocVT == MVT::v8i32 ||
4823 LocVT == MVT::v4i64 ||
4824 LocVT == MVT::v8f32 ||
4825 LocVT == MVT::v4f64) {
4826 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX()) {
4827 static const MCPhysReg RegList9[] = {
4828 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15
4829 };
4830 if (MCRegister Reg = State.AllocateReg(Regs: RegList9)) {
4831 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4832 return false;
4833 }
4834 }
4835 }
4836
4837 if (LocVT == MVT::v64i8 ||
4838 LocVT == MVT::v32i16 ||
4839 LocVT == MVT::v16i32 ||
4840 LocVT == MVT::v8i64 ||
4841 LocVT == MVT::v16f32 ||
4842 LocVT == MVT::v8f64) {
4843 if (State.getMachineFunction().getSubtarget<X86Subtarget>().hasAVX512()) {
4844 static const MCPhysReg RegList10[] = {
4845 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15
4846 };
4847 if (MCRegister Reg = State.AllocateReg(Regs: RegList10)) {
4848 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
4849 return false;
4850 }
4851 }
4852 }
4853
4854 return true; // CC didn't match.
4855}
4856
4857#else
4858
4859const MCRegister CC_Intel_OCL_BI_ArgRegs[] = { X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::K1, X86::R8, X86::R8D, X86::R9, X86::R9D, X86::RCX, X86::RDI, X86::RDX, X86::RSI, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3 };
4860const MCRegister CC_X86_ArgRegs[] = { 0 };
4861const MCRegister CC_X86_32_ArgRegs[] = { 0 };
4862const MCRegister CC_X86_32_C_ArgRegs[] = { X86::EAX, X86::ECX, X86::EDX };
4863const MCRegister CC_X86_32_Common_ArgRegs[] = { X86::XMM0, X86::XMM1, X86::XMM2 };
4864const MCRegister CC_X86_32_FastCC_ArgRegs[] = { X86::EAX, X86::ECX, X86::EDX, X86::XMM0, X86::XMM1, X86::XMM2 };
4865const MCRegister CC_X86_32_FastCall_ArgRegs[] = { X86::CL, X86::CX, X86::DL, X86::DX, X86::EAX, X86::ECX, X86::EDX };
4866const MCRegister CC_X86_32_GHC_ArgRegs[] = { X86::EBP, X86::EBX, X86::EDI, X86::ESI };
4867const MCRegister CC_X86_32_HiPE_ArgRegs[] = { X86::EAX, X86::EBP, X86::ECX, X86::EDX, X86::ESI };
4868const MCRegister CC_X86_32_MCU_ArgRegs[] = { 0 };
4869const MCRegister CC_X86_32_RegCall_ArgRegs[] = { X86::EAX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::RAX, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7 };
4870const MCRegister CC_X86_32_RegCallv4_Win_ArgRegs[] = { X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::RAX, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7 };
4871const MCRegister CC_X86_32_ThisCall_ArgRegs[] = { 0 };
4872const MCRegister CC_X86_32_ThisCall_Common_ArgRegs[] = { X86::ECX };
4873const MCRegister CC_X86_32_ThisCall_Mingw_ArgRegs[] = { 0 };
4874const MCRegister CC_X86_32_ThisCall_Win_ArgRegs[] = { 0 };
4875const MCRegister CC_X86_32_Vector_Common_ArgRegs[] = { 0 };
4876const MCRegister CC_X86_32_Vector_Darwin_ArgRegs[] = { X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3 };
4877const MCRegister CC_X86_32_Vector_Standard_ArgRegs[] = { X86::XMM0, X86::XMM1, X86::XMM2, X86::YMM0, X86::YMM1, X86::YMM2, X86::ZMM0, X86::ZMM1, X86::ZMM2 };
4878const MCRegister CC_X86_64_ArgRegs[] = { 0 };
4879const MCRegister CC_X86_64_AnyReg_ArgRegs[] = { 0 };
4880const MCRegister CC_X86_64_C_ArgRegs[] = { X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::R10, X86::R10D, X86::R8, X86::R8D, X86::R9, X86::R9D, X86::RAX, X86::RCX, X86::RDI, X86::RDX, X86::RSI, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7 };
4881const MCRegister CC_X86_64_GHC_ArgRegs[] = { X86::R12, X86::R13, X86::R14, X86::R15, X86::R8, X86::R9, X86::RBP, X86::RBX, X86::RDI, X86::RSI, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6 };
4882const MCRegister CC_X86_64_HiPE_ArgRegs[] = { X86::R15, X86::R8, X86::RBP, X86::RCX, X86::RDX, X86::RSI };
4883const MCRegister CC_X86_64_Preserve_None_ArgRegs[] = { X86::EAX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::R11, X86::R11D, X86::R12, X86::R12D, X86::R13, X86::R13D, X86::R14, X86::R14D, X86::R15, X86::R15D, X86::R8, X86::R8D, X86::R9, X86::R9D, X86::RAX, X86::RCX, X86::RDI, X86::RDX, X86::RSI };
4884const MCRegister CC_X86_SysV64_RegCall_ArgRegs[] = { X86::EAX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::R12, X86::R12D, X86::R13, X86::R13D, X86::R14, X86::R14D, X86::R15, X86::R15D, X86::R8, X86::R8D, X86::R9, X86::R9D, X86::RAX, X86::RCX, X86::RDI, X86::RDX, X86::RSI, X86::XMM0, X86::XMM1, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::YMM0, X86::YMM1, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::ZMM0, X86::ZMM1, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9 };
4885const MCRegister CC_X86_Win32_CFGuard_Check_ArgRegs[] = { X86::ECX };
4886const MCRegister CC_X86_Win32_Vector_ArgRegs[] = { 0 };
4887const MCRegister CC_X86_Win32_VectorCall_ArgRegs[] = { 0 };
4888const MCRegister CC_X86_Win64_C_ArgRegs[] = { X86::R10, X86::RAX };
4889const MCRegister CC_X86_Win64_RegCall_ArgRegs[] = { X86::EAX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::R10, X86::R10D, X86::R11, X86::R11D, X86::R12, X86::R12D, X86::R14, X86::R14D, X86::R15, X86::R15D, X86::R8, X86::R8D, X86::R9, X86::R9D, X86::RAX, X86::RCX, X86::RDI, X86::RDX, X86::RSI, X86::XMM0, X86::XMM1, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::YMM0, X86::YMM1, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::ZMM0, X86::ZMM1, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9 };
4890const MCRegister CC_X86_Win64_RegCallv4_ArgRegs[] = { X86::EAX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::R11, X86::R11D, X86::R12, X86::R12D, X86::R14, X86::R14D, X86::R15, X86::R15D, X86::R8, X86::R8D, X86::R9, X86::R9D, X86::RAX, X86::RCX, X86::RDI, X86::RDX, X86::RSI, X86::XMM0, X86::XMM1, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::YMM0, X86::YMM1, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::ZMM0, X86::ZMM1, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9 };
4891const MCRegister CC_X86_Win64_VectorCall_ArgRegs[] = { 0 };
4892const MCRegister RetCC_Intel_OCL_BI_ArgRegs[] = { X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3 };
4893const MCRegister RetCC_X86_ArgRegs[] = { 0 };
4894const MCRegister RetCC_X86Common_ArgRegs[] = { X86::AL, X86::AX, X86::CL, X86::CX, X86::DL, X86::DX, X86::EAX, X86::ECX, X86::EDX, X86::FP0, X86::FP1, X86::RAX, X86::RCX, X86::RDX, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3 };
4895const MCRegister RetCC_X86_32_ArgRegs[] = { 0 };
4896const MCRegister RetCC_X86_32_C_ArgRegs[] = { X86::EAX, X86::ECX, X86::EDX, X86::FP0, X86::FP1, X86::XMM0, X86::XMM1, X86::XMM2 };
4897const MCRegister RetCC_X86_32_Fast_ArgRegs[] = { X86::AL, X86::AX, X86::CL, X86::CX, X86::DL, X86::DX, X86::EAX, X86::ECX, X86::EDX, X86::XMM0, X86::XMM1, X86::XMM2 };
4898const MCRegister RetCC_X86_32_HiPE_ArgRegs[] = { X86::EAX, X86::EBP, X86::EDX, X86::ESI };
4899const MCRegister RetCC_X86_32_RegCall_ArgRegs[] = { X86::AL, X86::AX, X86::CL, X86::CX, X86::DI, X86::DIL, X86::DL, X86::DX, X86::EAX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::FP1, X86::RAX, X86::SI, X86::SIL, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7 };
4900const MCRegister RetCC_X86_32_RegCallv4_Win_ArgRegs[] = { X86::CL, X86::CX, X86::DI, X86::DIL, X86::DL, X86::DX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::FP1, X86::RAX, X86::SI, X86::SIL, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7 };
4901const MCRegister RetCC_X86_32_VectorCall_ArgRegs[] = { X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 };
4902const MCRegister RetCC_X86_64_ArgRegs[] = { 0 };
4903const MCRegister RetCC_X86_64_AnyReg_ArgRegs[] = { 0 };
4904const MCRegister RetCC_X86_64_C_ArgRegs[] = { X86::XMM0, X86::XMM1 };
4905const MCRegister RetCC_X86_64_HiPE_ArgRegs[] = { X86::R15, X86::RAX, X86::RBP, X86::RDX };
4906const MCRegister RetCC_X86_64_Swift_ArgRegs[] = { X86::AL, X86::AX, X86::CL, X86::CX, X86::DL, X86::DX, X86::EAX, X86::ECX, X86::EDX, X86::R8, X86::R8B, X86::R8D, X86::R8W, X86::RAX, X86::RCX, X86::RDX, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 };
4907const MCRegister RetCC_X86_64_Vectorcall_ArgRegs[] = { X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 };
4908const MCRegister RetCC_X86_SysV64_RegCall_ArgRegs[] = { X86::AL, X86::AX, X86::CL, X86::CX, X86::DI, X86::DIL, X86::DL, X86::DX, X86::EAX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::FP1, X86::R12, X86::R12B, X86::R12D, X86::R12W, X86::R13, X86::R13B, X86::R13D, X86::R13W, X86::R14, X86::R14B, X86::R14D, X86::R14W, X86::R15, X86::R15B, X86::R15D, X86::R15W, X86::R8, X86::R8B, X86::R8D, X86::R8W, X86::R9, X86::R9B, X86::R9D, X86::R9W, X86::RAX, X86::RCX, X86::RDI, X86::RDX, X86::RSI, X86::SI, X86::SIL, X86::XMM0, X86::XMM1, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::YMM0, X86::YMM1, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::ZMM0, X86::ZMM1, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9 };
4909const MCRegister RetCC_X86_Win64_C_ArgRegs[] = { 0 };
4910const MCRegister RetCC_X86_Win64_RegCall_ArgRegs[] = { X86::AL, X86::AX, X86::CL, X86::CX, X86::DI, X86::DIL, X86::DL, X86::DX, X86::EAX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::FP1, X86::R10, X86::R10B, X86::R10D, X86::R10W, X86::R11, X86::R11B, X86::R11D, X86::R11W, X86::R12, X86::R12B, X86::R12D, X86::R12W, X86::R14, X86::R14B, X86::R14D, X86::R14W, X86::R15, X86::R15B, X86::R15D, X86::R15W, X86::R8, X86::R8B, X86::R8D, X86::R8W, X86::R9, X86::R9B, X86::R9D, X86::R9W, X86::RAX, X86::RCX, X86::RDI, X86::RDX, X86::RSI, X86::SI, X86::SIL, X86::XMM0, X86::XMM1, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::YMM0, X86::YMM1, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::ZMM0, X86::ZMM1, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9 };
4911const MCRegister RetCC_X86_Win64_RegCallv4_ArgRegs[] = { X86::AL, X86::AX, X86::CL, X86::CX, X86::DI, X86::DIL, X86::DL, X86::DX, X86::EAX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::FP1, X86::R11, X86::R11B, X86::R11D, X86::R11W, X86::R12, X86::R12B, X86::R12D, X86::R12W, X86::R14, X86::R14B, X86::R14D, X86::R14W, X86::R15, X86::R15B, X86::R15D, X86::R15W, X86::R8, X86::R8B, X86::R8D, X86::R8W, X86::R9, X86::R9B, X86::R9D, X86::R9W, X86::RAX, X86::RCX, X86::RDI, X86::RDX, X86::RSI, X86::SI, X86::SIL, X86::XMM0, X86::XMM1, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::YMM0, X86::YMM1, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::ZMM0, X86::ZMM1, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9 };
4912
4913// Registers used by Swift.
4914const MCRegister CC_X86_64_C_Swift_ArgRegs[] = { X86::R12, X86::R13, X86::R14 };
4915const MCRegister CC_X86_Win64_C_Swift_ArgRegs[] = { X86::R12, X86::R13, X86::R14 };
4916const MCRegister RetCC_X86_64_C_Swift_ArgRegs[] = { X86::R12 };
4917const MCRegister RetCC_X86_64_Swift_Swift_ArgRegs[] = { X86::R12 };
4918
4919#endif // CC_REGISTER_LIST
4920