1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register Enum Values *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_REGINFO_ENUM
11#undef GET_REGINFO_ENUM
12
13namespace llvm {
14
15class MCRegisterClass;
16extern const MCRegisterClass X86MCRegisterClasses[];
17
18namespace X86 {
19enum : unsigned {
20 NoRegister,
21 AH = 1,
22 AL = 2,
23 AX = 3,
24 BH = 4,
25 BL = 5,
26 BP = 6,
27 BPH = 7,
28 BPL = 8,
29 BX = 9,
30 CH = 10,
31 CL = 11,
32 CS = 12,
33 CX = 13,
34 DF = 14,
35 DH = 15,
36 DI = 16,
37 DIH = 17,
38 DIL = 18,
39 DL = 19,
40 DS = 20,
41 DX = 21,
42 EAX = 22,
43 EBP = 23,
44 EBX = 24,
45 ECX = 25,
46 EDI = 26,
47 EDX = 27,
48 EFLAGS = 28,
49 EIP = 29,
50 EIZ = 30,
51 ES = 31,
52 ESI = 32,
53 ESP = 33,
54 FPCW = 34,
55 FPSW = 35,
56 FS = 36,
57 FS_BASE = 37,
58 GS = 38,
59 GS_BASE = 39,
60 HAX = 40,
61 HBP = 41,
62 HBX = 42,
63 HCX = 43,
64 HDI = 44,
65 HDX = 45,
66 HIP = 46,
67 HSI = 47,
68 HSP = 48,
69 IP = 49,
70 MXCSR = 50,
71 RAX = 51,
72 RBP = 52,
73 RBX = 53,
74 RCX = 54,
75 RDI = 55,
76 RDX = 56,
77 RFLAGS = 57,
78 RIP = 58,
79 RIZ = 59,
80 RSI = 60,
81 RSP = 61,
82 SI = 62,
83 SIH = 63,
84 SIL = 64,
85 SP = 65,
86 SPH = 66,
87 SPL = 67,
88 SS = 68,
89 SSP = 69,
90 _EFLAGS = 70,
91 CR0 = 71,
92 CR1 = 72,
93 CR2 = 73,
94 CR3 = 74,
95 CR4 = 75,
96 CR5 = 76,
97 CR6 = 77,
98 CR7 = 78,
99 CR8 = 79,
100 CR9 = 80,
101 CR10 = 81,
102 CR11 = 82,
103 CR12 = 83,
104 CR13 = 84,
105 CR14 = 85,
106 CR15 = 86,
107 DR0 = 87,
108 DR1 = 88,
109 DR2 = 89,
110 DR3 = 90,
111 DR4 = 91,
112 DR5 = 92,
113 DR6 = 93,
114 DR7 = 94,
115 DR8 = 95,
116 DR9 = 96,
117 DR10 = 97,
118 DR11 = 98,
119 DR12 = 99,
120 DR13 = 100,
121 DR14 = 101,
122 DR15 = 102,
123 FP0 = 103,
124 FP1 = 104,
125 FP2 = 105,
126 FP3 = 106,
127 FP4 = 107,
128 FP5 = 108,
129 FP6 = 109,
130 FP7 = 110,
131 MM0 = 111,
132 MM1 = 112,
133 MM2 = 113,
134 MM3 = 114,
135 MM4 = 115,
136 MM5 = 116,
137 MM6 = 117,
138 MM7 = 118,
139 R8 = 119,
140 R9 = 120,
141 R10 = 121,
142 R11 = 122,
143 R12 = 123,
144 R13 = 124,
145 R14 = 125,
146 R15 = 126,
147 ST0 = 127,
148 ST1 = 128,
149 ST2 = 129,
150 ST3 = 130,
151 ST4 = 131,
152 ST5 = 132,
153 ST6 = 133,
154 ST7 = 134,
155 XMM0 = 135,
156 XMM1 = 136,
157 XMM2 = 137,
158 XMM3 = 138,
159 XMM4 = 139,
160 XMM5 = 140,
161 XMM6 = 141,
162 XMM7 = 142,
163 XMM8 = 143,
164 XMM9 = 144,
165 XMM10 = 145,
166 XMM11 = 146,
167 XMM12 = 147,
168 XMM13 = 148,
169 XMM14 = 149,
170 XMM15 = 150,
171 R8B = 151,
172 R9B = 152,
173 R10B = 153,
174 R11B = 154,
175 R12B = 155,
176 R13B = 156,
177 R14B = 157,
178 R15B = 158,
179 R8BH = 159,
180 R9BH = 160,
181 R10BH = 161,
182 R11BH = 162,
183 R12BH = 163,
184 R13BH = 164,
185 R14BH = 165,
186 R15BH = 166,
187 R8D = 167,
188 R9D = 168,
189 R10D = 169,
190 R11D = 170,
191 R12D = 171,
192 R13D = 172,
193 R14D = 173,
194 R15D = 174,
195 R8W = 175,
196 R9W = 176,
197 R10W = 177,
198 R11W = 178,
199 R12W = 179,
200 R13W = 180,
201 R14W = 181,
202 R15W = 182,
203 R8WH = 183,
204 R9WH = 184,
205 R10WH = 185,
206 R11WH = 186,
207 R12WH = 187,
208 R13WH = 188,
209 R14WH = 189,
210 R15WH = 190,
211 YMM0 = 191,
212 YMM1 = 192,
213 YMM2 = 193,
214 YMM3 = 194,
215 YMM4 = 195,
216 YMM5 = 196,
217 YMM6 = 197,
218 YMM7 = 198,
219 YMM8 = 199,
220 YMM9 = 200,
221 YMM10 = 201,
222 YMM11 = 202,
223 YMM12 = 203,
224 YMM13 = 204,
225 YMM14 = 205,
226 YMM15 = 206,
227 K0 = 207,
228 K1 = 208,
229 K2 = 209,
230 K3 = 210,
231 K4 = 211,
232 K5 = 212,
233 K6 = 213,
234 K7 = 214,
235 XMM16 = 215,
236 XMM17 = 216,
237 XMM18 = 217,
238 XMM19 = 218,
239 XMM20 = 219,
240 XMM21 = 220,
241 XMM22 = 221,
242 XMM23 = 222,
243 XMM24 = 223,
244 XMM25 = 224,
245 XMM26 = 225,
246 XMM27 = 226,
247 XMM28 = 227,
248 XMM29 = 228,
249 XMM30 = 229,
250 XMM31 = 230,
251 YMM16 = 231,
252 YMM17 = 232,
253 YMM18 = 233,
254 YMM19 = 234,
255 YMM20 = 235,
256 YMM21 = 236,
257 YMM22 = 237,
258 YMM23 = 238,
259 YMM24 = 239,
260 YMM25 = 240,
261 YMM26 = 241,
262 YMM27 = 242,
263 YMM28 = 243,
264 YMM29 = 244,
265 YMM30 = 245,
266 YMM31 = 246,
267 ZMM0 = 247,
268 ZMM1 = 248,
269 ZMM2 = 249,
270 ZMM3 = 250,
271 ZMM4 = 251,
272 ZMM5 = 252,
273 ZMM6 = 253,
274 ZMM7 = 254,
275 ZMM8 = 255,
276 ZMM9 = 256,
277 ZMM10 = 257,
278 ZMM11 = 258,
279 ZMM12 = 259,
280 ZMM13 = 260,
281 ZMM14 = 261,
282 ZMM15 = 262,
283 ZMM16 = 263,
284 ZMM17 = 264,
285 ZMM18 = 265,
286 ZMM19 = 266,
287 ZMM20 = 267,
288 ZMM21 = 268,
289 ZMM22 = 269,
290 ZMM23 = 270,
291 ZMM24 = 271,
292 ZMM25 = 272,
293 ZMM26 = 273,
294 ZMM27 = 274,
295 ZMM28 = 275,
296 ZMM29 = 276,
297 ZMM30 = 277,
298 ZMM31 = 278,
299 K0_K1 = 279,
300 K2_K3 = 280,
301 K4_K5 = 281,
302 K6_K7 = 282,
303 TMMCFG = 283,
304 TMM0 = 284,
305 TMM1 = 285,
306 TMM2 = 286,
307 TMM3 = 287,
308 TMM4 = 288,
309 TMM5 = 289,
310 TMM6 = 290,
311 TMM7 = 291,
312 TMM0_TMM1 = 292,
313 TMM2_TMM3 = 293,
314 TMM4_TMM5 = 294,
315 TMM6_TMM7 = 295,
316 R16 = 296,
317 R17 = 297,
318 R18 = 298,
319 R19 = 299,
320 R20 = 300,
321 R21 = 301,
322 R22 = 302,
323 R23 = 303,
324 R24 = 304,
325 R25 = 305,
326 R26 = 306,
327 R27 = 307,
328 R28 = 308,
329 R29 = 309,
330 R30 = 310,
331 R31 = 311,
332 R16B = 312,
333 R17B = 313,
334 R18B = 314,
335 R19B = 315,
336 R20B = 316,
337 R21B = 317,
338 R22B = 318,
339 R23B = 319,
340 R24B = 320,
341 R25B = 321,
342 R26B = 322,
343 R27B = 323,
344 R28B = 324,
345 R29B = 325,
346 R30B = 326,
347 R31B = 327,
348 R16BH = 328,
349 R17BH = 329,
350 R18BH = 330,
351 R19BH = 331,
352 R20BH = 332,
353 R21BH = 333,
354 R22BH = 334,
355 R23BH = 335,
356 R24BH = 336,
357 R25BH = 337,
358 R26BH = 338,
359 R27BH = 339,
360 R28BH = 340,
361 R29BH = 341,
362 R30BH = 342,
363 R31BH = 343,
364 R16D = 344,
365 R17D = 345,
366 R18D = 346,
367 R19D = 347,
368 R20D = 348,
369 R21D = 349,
370 R22D = 350,
371 R23D = 351,
372 R24D = 352,
373 R25D = 353,
374 R26D = 354,
375 R27D = 355,
376 R28D = 356,
377 R29D = 357,
378 R30D = 358,
379 R31D = 359,
380 R16W = 360,
381 R17W = 361,
382 R18W = 362,
383 R19W = 363,
384 R20W = 364,
385 R21W = 365,
386 R22W = 366,
387 R23W = 367,
388 R24W = 368,
389 R25W = 369,
390 R26W = 370,
391 R27W = 371,
392 R28W = 372,
393 R29W = 373,
394 R30W = 374,
395 R31W = 375,
396 R16WH = 376,
397 R17WH = 377,
398 R18WH = 378,
399 R19WH = 379,
400 R20WH = 380,
401 R21WH = 381,
402 R22WH = 382,
403 R23WH = 383,
404 R24WH = 384,
405 R25WH = 385,
406 R26WH = 386,
407 R27WH = 387,
408 R28WH = 388,
409 R29WH = 389,
410 R30WH = 390,
411 R31WH = 391,
412 NUM_TARGET_REGS // 392
413};
414} // end namespace X86
415
416// Register classes
417
418namespace X86 {
419enum {
420 GR8RegClassID = 0,
421 GRH8RegClassID = 1,
422 GR8_NOREX2RegClassID = 2,
423 GR8_NOREXRegClassID = 3,
424 GR8_ABCD_HRegClassID = 4,
425 GR8_ABCD_LRegClassID = 5,
426 GRH16RegClassID = 6,
427 GR16RegClassID = 7,
428 GR16_NOREX2RegClassID = 8,
429 GR16_NOREXRegClassID = 9,
430 VK1RegClassID = 10,
431 VK16RegClassID = 11,
432 VK2RegClassID = 12,
433 VK4RegClassID = 13,
434 VK8RegClassID = 14,
435 VK16WMRegClassID = 15,
436 VK1WMRegClassID = 16,
437 VK2WMRegClassID = 17,
438 VK4WMRegClassID = 18,
439 VK8WMRegClassID = 19,
440 SEGMENT_REGRegClassID = 20,
441 GR16_ABCDRegClassID = 21,
442 FPCCRRegClassID = 22,
443 FR16XRegClassID = 23,
444 FR16RegClassID = 24,
445 VK16PAIRRegClassID = 25,
446 VK1PAIRRegClassID = 26,
447 VK2PAIRRegClassID = 27,
448 VK4PAIRRegClassID = 28,
449 VK8PAIRRegClassID = 29,
450 VK1PAIR_with_sub_mask_0_in_VK1WMRegClassID = 30,
451 LOW32_ADDR_ACCESS_RBPRegClassID = 31,
452 LOW32_ADDR_ACCESSRegClassID = 32,
453 LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID = 33,
454 FR32XRegClassID = 34,
455 GR32RegClassID = 35,
456 GR32_NOSPRegClassID = 36,
457 LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID = 37,
458 DEBUG_REGRegClassID = 38,
459 FR32RegClassID = 39,
460 GR32_NOREX2RegClassID = 40,
461 GR32_NOREX2_NOSPRegClassID = 41,
462 LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID = 42,
463 GR32_NOREXRegClassID = 43,
464 VK32RegClassID = 44,
465 GR32_NOREX_NOSPRegClassID = 45,
466 RFP32RegClassID = 46,
467 VK32WMRegClassID = 47,
468 GR32_ABCDRegClassID = 48,
469 GR32_TCRegClassID = 49,
470 GR32_ABCD_and_GR32_TCRegClassID = 50,
471 GR32_ADRegClassID = 51,
472 GR32_ArgRefRegClassID = 52,
473 GR32_BPSPRegClassID = 53,
474 GR32_BSIRegClassID = 54,
475 GR32_CBRegClassID = 55,
476 GR32_DCRegClassID = 56,
477 GR32_DIBPRegClassID = 57,
478 GR32_SIDIRegClassID = 58,
479 LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID = 59,
480 CCRRegClassID = 60,
481 DFCCRRegClassID = 61,
482 GR32_ABCD_and_GR32_BSIRegClassID = 62,
483 GR32_AD_and_GR32_ArgRefRegClassID = 63,
484 GR32_ArgRef_and_GR32_CBRegClassID = 64,
485 GR32_BPSP_and_GR32_DIBPRegClassID = 65,
486 GR32_BPSP_and_GR32_TCRegClassID = 66,
487 GR32_BSI_and_GR32_SIDIRegClassID = 67,
488 GR32_DIBP_and_GR32_SIDIRegClassID = 68,
489 LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClassID = 69,
490 LOW32_ADDR_ACCESS_with_sub_32bitRegClassID = 70,
491 RFP64RegClassID = 71,
492 GR64RegClassID = 72,
493 FR64XRegClassID = 73,
494 GR64_with_sub_8bitRegClassID = 74,
495 GR64_NOSPRegClassID = 75,
496 GR64_NOREX2RegClassID = 76,
497 CONTROL_REGRegClassID = 77,
498 FR64RegClassID = 78,
499 GR64_with_sub_16bit_in_GR16_NOREX2RegClassID = 79,
500 GR64_NOREX2_NOSPRegClassID = 80,
501 GR64PLTSafeRegClassID = 81,
502 GR64_TCRegClassID = 82,
503 GR64_NOREXRegClassID = 83,
504 GR64_TCW64RegClassID = 84,
505 GR64_TC_with_sub_8bitRegClassID = 85,
506 GR64_NOREX2_NOSP_and_GR64_TCRegClassID = 86,
507 GR64_TCW64_with_sub_8bitRegClassID = 87,
508 GR64_TC_and_GR64_TCW64RegClassID = 88,
509 GR64_with_sub_16bit_in_GR16_NOREXRegClassID = 89,
510 VK64RegClassID = 90,
511 VR64RegClassID = 91,
512 GR64PLTSafe_and_GR64_TCRegClassID = 92,
513 GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID = 93,
514 GR64_NOREX_NOSPRegClassID = 94,
515 GR64_NOREX_and_GR64_TCRegClassID = 95,
516 GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID = 96,
517 VK64WMRegClassID = 97,
518 GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID = 98,
519 GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID = 99,
520 GR64PLTSafe_and_GR64_TCW64RegClassID = 100,
521 GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID = 101,
522 GR64_NOREX_and_GR64_TCW64RegClassID = 102,
523 GR64_ABCDRegClassID = 103,
524 GR64_with_sub_32bit_in_GR32_TCRegClassID = 104,
525 GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID = 105,
526 GR64_ADRegClassID = 106,
527 GR64_ArgRefRegClassID = 107,
528 GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID = 108,
529 GR64_with_sub_32bit_in_GR32_ArgRefRegClassID = 109,
530 GR64_with_sub_32bit_in_GR32_BPSPRegClassID = 110,
531 GR64_with_sub_32bit_in_GR32_BSIRegClassID = 111,
532 GR64_with_sub_32bit_in_GR32_CBRegClassID = 112,
533 GR64_with_sub_32bit_in_GR32_DIBPRegClassID = 113,
534 GR64_with_sub_32bit_in_GR32_SIDIRegClassID = 114,
535 GR64_ARegClassID = 115,
536 GR64_ArgRef_and_GR64_TCRegClassID = 116,
537 GR64_and_LOW32_ADDR_ACCESSRegClassID = 117,
538 GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClassID = 118,
539 GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefRegClassID = 119,
540 GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBRegClassID = 120,
541 GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClassID = 121,
542 GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClassID = 122,
543 GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClassID = 123,
544 GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClassID = 124,
545 RSTRegClassID = 125,
546 RFP80RegClassID = 126,
547 RFP80_7RegClassID = 127,
548 VR128XRegClassID = 128,
549 VR128RegClassID = 129,
550 VR256XRegClassID = 130,
551 VR256RegClassID = 131,
552 VR512RegClassID = 132,
553 VR512_0_15RegClassID = 133,
554 TILERegClassID = 134,
555 TILEPAIRRegClassID = 135,
556
557};
558} // end namespace X86
559
560
561// Subregister indices
562
563namespace X86 {
564enum : uint16_t {
565 NoSubRegister,
566 sub_8bit, // 1
567 sub_8bit_hi, // 2
568 sub_8bit_hi_phony, // 3
569 sub_16bit, // 4
570 sub_16bit_hi, // 5
571 sub_32bit, // 6
572 sub_mask_0, // 7
573 sub_mask_1, // 8
574 sub_t0, // 9
575 sub_t1, // 10
576 sub_xmm, // 11
577 sub_ymm, // 12
578 NUM_TARGET_SUBREGS
579};
580} // end namespace X86
581
582// Register pressure sets enum.
583namespace X86 {
584enum RegisterPressureSets {
585 SEGMENT_REG = 0,
586 GR32_BPSP = 1,
587 LOW32_ADDR_ACCESS_with_sub_32bit = 2,
588 GR32_BSI = 3,
589 GR32_SIDI = 4,
590 GR32_DIBP_with_GR32_SIDI = 5,
591 GR32_DIBP_with_LOW32_ADDR_ACCESS_with_sub_32bit = 6,
592 RFP32 = 7,
593 GR8_ABCD_H_with_GR32_BSI = 8,
594 GR8_ABCD_L_with_GR32_BSI = 9,
595 VK1 = 10,
596 VR64 = 11,
597 TILE = 12,
598 GR8_NOREX = 13,
599 GR32_TC = 14,
600 GR32_BPSP_with_GR32_TC = 15,
601 FR16 = 16,
602 DEBUG_REG = 17,
603 CONTROL_REG = 18,
604 GR64_NOREX = 19,
605 GR64_TCW64 = 20,
606 GR32_BPSP_with_GR64_TCW64 = 21,
607 GR64_TC_with_GR64_TCW64 = 22,
608 GR64_TC = 23,
609 FR16X = 24,
610 GR64PLTSafe_with_GR64_TC = 25,
611 GR8 = 26,
612 GR8_with_GR32_DIBP = 27,
613 GR8_with_GR32_BSI = 28,
614 GR8_with_LOW32_ADDR_ACCESS_with_sub_32bit = 29,
615 GR8_with_GR64_NOREX = 30,
616 GR8_with_GR64_TCW64 = 31,
617 GR8_with_GR64_TC = 32,
618 GR8_with_GR64PLTSafe = 33,
619 GR8_with_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2 = 34,
620 GR16 = 35,
621};
622} // end namespace X86
623
624} // end namespace llvm
625
626#endif // GET_REGINFO_ENUM
627
628/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
629|* *|
630|* MC Register Information *|
631|* *|
632|* Automatically generated file, do not edit! *|
633|* *|
634\*===----------------------------------------------------------------------===*/
635
636
637#ifdef GET_REGINFO_MC_DESC
638#undef GET_REGINFO_MC_DESC
639
640namespace llvm {
641
642extern const int16_t X86RegDiffLists[] = {
643 /* 0 */ -56, -56, 0,
644 /* 3 */ -32, -48, 0,
645 /* 6 */ 32, -16, -48, 0,
646 /* 10 */ 48, -16, -48, 0,
647 /* 14 */ 16, -8, -48, 0,
648 /* 18 */ 24, -8, -48, 0,
649 /* 22 */ -28, 32, 2, -1, -18, 0,
650 /* 28 */ -32, -16, 0,
651 /* 31 */ -28, 30, 2, -1, -16, 0,
652 /* 37 */ -2, -4, 0,
653 /* 40 */ -29, 20, -3, 0,
654 /* 44 */ -4, -1, 0,
655 /* 47 */ -2, -1, 0,
656 /* 50 */ -1, -1, 0,
657 /* 53 */ 2, -1, 0,
658 /* 56 */ -72, 1, 0,
659 /* 59 */ -71, 1, 0,
660 /* 62 */ -70, 1, 0,
661 /* 65 */ -69, 1, 0,
662 /* 68 */ -8, 1, 0,
663 /* 71 */ -7, 1, 0,
664 /* 74 */ -6, 1, 0,
665 /* 77 */ -5, 1, 0,
666 /* 80 */ 1, 1, 0,
667 /* 83 */ 3, 0,
668 /* 85 */ 4, 0,
669 /* 87 */ 5, 0,
670 /* 89 */ 6, 0,
671 /* 91 */ 1, 7, 0,
672 /* 94 */ 3, 7, 0,
673 /* 97 */ -24, 8, 0,
674 /* 100 */ 1, 11, 0,
675 /* 103 */ 1, 14, 0,
676 /* 106 */ -48, 16, 0,
677 /* 109 */ 48, 8, -24, 8, 24, 0,
678 /* 115 */ -29, -10, 2, -1, 27, 0,
679 /* 121 */ -2, -32, 28, 0,
680 /* 125 */ -1, -32, 28, 0,
681 /* 129 */ -2, -30, 28, 0,
682 /* 133 */ -1, -30, 28, 0,
683 /* 137 */ -15, 28, 0,
684 /* 140 */ -20, 29, 0,
685 /* 143 */ -18, 29, 0,
686 /* 146 */ -17, 29, 0,
687 /* 149 */ 2, 6, 29, 0,
688 /* 153 */ 6, 6, 29, 0,
689 /* 157 */ -2, 10, 29, 0,
690 /* 161 */ -1, 10, 29, 0,
691 /* 165 */ 2, 12, 29, 0,
692 /* 169 */ 3, 12, 29, 0,
693 /* 173 */ 4, 15, 29, 0,
694 /* 177 */ 5, 15, 29, 0,
695 /* 181 */ -2, 17, 29, 0,
696 /* 185 */ -1, 17, 29, 0,
697 /* 189 */ 1, 19, 29, 0,
698 /* 193 */ 2, 19, 29, 0,
699 /* 197 */ -29, -6, -2, -4, 30, 0,
700 /* 203 */ 16, 32, 0,
701 /* 206 */ -29, -12, -2, -1, 33, 0,
702 /* 212 */ -29, -17, 2, -1, 34, 0,
703 /* 218 */ -29, -15, -4, -1, 38, 0,
704 /* 224 */ -29, -19, -1, -1, 39, 0,
705 /* 230 */ 48, 16, -48, 16, 48, 0,
706 /* 236 */ 56, 56, 0,
707 /* 239 */ 68, 0,
708 /* 241 */ 69, 0,
709 /* 243 */ 70, 0,
710 /* 245 */ 71, 0,
711 /* 247 */ 72, 0,
712};
713
714extern const LaneBitmask X86LaneMaskLists[] = {
715 /* 0 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000001),
716 /* 2 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000004),
717 /* 4 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000008),
718 /* 7 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008),
719 /* 10 */ LaneBitmask(0x0000000000000007), LaneBitmask(0x0000000000000008),
720 /* 12 */ LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020),
721 /* 14 */ LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000080),
722 /* 16 */ LaneBitmask(0x0000000000000100),
723 /* 17 */ LaneBitmask(0xFFFFFFFFFFFFFFFF),
724};
725
726extern const uint16_t X86SubRegIdxLists[] = {
727 /* 0 */ 1, 2,
728 /* 2 */ 1, 3,
729 /* 4 */ 6, 4, 1, 2, 5,
730 /* 9 */ 6, 4, 1, 3, 5,
731 /* 14 */ 6, 4, 5,
732 /* 17 */ 7, 8,
733 /* 19 */ 9, 10,
734 /* 21 */ 12, 11,
735};
736
737
738#ifdef __GNUC__
739#pragma GCC diagnostic push
740#pragma GCC diagnostic ignored "-Woverlength-strings"
741#endif
742extern const char X86RegStrings[] = {
743 /* 0 */ "XMM10\000"
744 /* 6 */ "YMM10\000"
745 /* 12 */ "ZMM10\000"
746 /* 18 */ "CR10\000"
747 /* 23 */ "DR10\000"
748 /* 28 */ "XMM20\000"
749 /* 34 */ "YMM20\000"
750 /* 40 */ "ZMM20\000"
751 /* 46 */ "R20\000"
752 /* 50 */ "XMM30\000"
753 /* 56 */ "YMM30\000"
754 /* 62 */ "ZMM30\000"
755 /* 68 */ "R30\000"
756 /* 72 */ "K0\000"
757 /* 75 */ "TMM0\000"
758 /* 80 */ "XMM0\000"
759 /* 85 */ "YMM0\000"
760 /* 90 */ "ZMM0\000"
761 /* 95 */ "FP0\000"
762 /* 99 */ "CR0\000"
763 /* 103 */ "DR0\000"
764 /* 107 */ "ST0\000"
765 /* 111 */ "XMM11\000"
766 /* 117 */ "YMM11\000"
767 /* 123 */ "ZMM11\000"
768 /* 129 */ "CR11\000"
769 /* 134 */ "DR11\000"
770 /* 139 */ "XMM21\000"
771 /* 145 */ "YMM21\000"
772 /* 151 */ "ZMM21\000"
773 /* 157 */ "R21\000"
774 /* 161 */ "XMM31\000"
775 /* 167 */ "YMM31\000"
776 /* 173 */ "ZMM31\000"
777 /* 179 */ "R31\000"
778 /* 183 */ "K0_K1\000"
779 /* 189 */ "TMM0_TMM1\000"
780 /* 199 */ "XMM1\000"
781 /* 204 */ "YMM1\000"
782 /* 209 */ "ZMM1\000"
783 /* 214 */ "FP1\000"
784 /* 218 */ "CR1\000"
785 /* 222 */ "DR1\000"
786 /* 226 */ "ST1\000"
787 /* 230 */ "XMM12\000"
788 /* 236 */ "YMM12\000"
789 /* 242 */ "ZMM12\000"
790 /* 248 */ "CR12\000"
791 /* 253 */ "DR12\000"
792 /* 258 */ "XMM22\000"
793 /* 264 */ "YMM22\000"
794 /* 270 */ "ZMM22\000"
795 /* 276 */ "R22\000"
796 /* 280 */ "K2\000"
797 /* 283 */ "TMM2\000"
798 /* 288 */ "XMM2\000"
799 /* 293 */ "YMM2\000"
800 /* 298 */ "ZMM2\000"
801 /* 303 */ "FP2\000"
802 /* 307 */ "CR2\000"
803 /* 311 */ "DR2\000"
804 /* 315 */ "ST2\000"
805 /* 319 */ "XMM13\000"
806 /* 325 */ "YMM13\000"
807 /* 331 */ "ZMM13\000"
808 /* 337 */ "CR13\000"
809 /* 342 */ "DR13\000"
810 /* 347 */ "XMM23\000"
811 /* 353 */ "YMM23\000"
812 /* 359 */ "ZMM23\000"
813 /* 365 */ "R23\000"
814 /* 369 */ "K2_K3\000"
815 /* 375 */ "TMM2_TMM3\000"
816 /* 385 */ "XMM3\000"
817 /* 390 */ "YMM3\000"
818 /* 395 */ "ZMM3\000"
819 /* 400 */ "FP3\000"
820 /* 404 */ "CR3\000"
821 /* 408 */ "DR3\000"
822 /* 412 */ "ST3\000"
823 /* 416 */ "XMM14\000"
824 /* 422 */ "YMM14\000"
825 /* 428 */ "ZMM14\000"
826 /* 434 */ "CR14\000"
827 /* 439 */ "DR14\000"
828 /* 444 */ "XMM24\000"
829 /* 450 */ "YMM24\000"
830 /* 456 */ "ZMM24\000"
831 /* 462 */ "R24\000"
832 /* 466 */ "K4\000"
833 /* 469 */ "TMM4\000"
834 /* 474 */ "XMM4\000"
835 /* 479 */ "YMM4\000"
836 /* 484 */ "ZMM4\000"
837 /* 489 */ "FP4\000"
838 /* 493 */ "CR4\000"
839 /* 497 */ "DR4\000"
840 /* 501 */ "ST4\000"
841 /* 505 */ "XMM15\000"
842 /* 511 */ "YMM15\000"
843 /* 517 */ "ZMM15\000"
844 /* 523 */ "CR15\000"
845 /* 528 */ "DR15\000"
846 /* 533 */ "XMM25\000"
847 /* 539 */ "YMM25\000"
848 /* 545 */ "ZMM25\000"
849 /* 551 */ "R25\000"
850 /* 555 */ "K4_K5\000"
851 /* 561 */ "TMM4_TMM5\000"
852 /* 571 */ "XMM5\000"
853 /* 576 */ "YMM5\000"
854 /* 581 */ "ZMM5\000"
855 /* 586 */ "FP5\000"
856 /* 590 */ "CR5\000"
857 /* 594 */ "DR5\000"
858 /* 598 */ "ST5\000"
859 /* 602 */ "XMM16\000"
860 /* 608 */ "YMM16\000"
861 /* 614 */ "ZMM16\000"
862 /* 620 */ "R16\000"
863 /* 624 */ "XMM26\000"
864 /* 630 */ "YMM26\000"
865 /* 636 */ "ZMM26\000"
866 /* 642 */ "R26\000"
867 /* 646 */ "K6\000"
868 /* 649 */ "TMM6\000"
869 /* 654 */ "XMM6\000"
870 /* 659 */ "YMM6\000"
871 /* 664 */ "ZMM6\000"
872 /* 669 */ "FP6\000"
873 /* 673 */ "CR6\000"
874 /* 677 */ "DR6\000"
875 /* 681 */ "ST6\000"
876 /* 685 */ "XMM17\000"
877 /* 691 */ "YMM17\000"
878 /* 697 */ "ZMM17\000"
879 /* 703 */ "R17\000"
880 /* 707 */ "XMM27\000"
881 /* 713 */ "YMM27\000"
882 /* 719 */ "ZMM27\000"
883 /* 725 */ "R27\000"
884 /* 729 */ "K6_K7\000"
885 /* 735 */ "TMM6_TMM7\000"
886 /* 745 */ "XMM7\000"
887 /* 750 */ "YMM7\000"
888 /* 755 */ "ZMM7\000"
889 /* 760 */ "FP7\000"
890 /* 764 */ "CR7\000"
891 /* 768 */ "DR7\000"
892 /* 772 */ "ST7\000"
893 /* 776 */ "XMM18\000"
894 /* 782 */ "YMM18\000"
895 /* 788 */ "ZMM18\000"
896 /* 794 */ "R18\000"
897 /* 798 */ "XMM28\000"
898 /* 804 */ "YMM28\000"
899 /* 810 */ "ZMM28\000"
900 /* 816 */ "R28\000"
901 /* 820 */ "XMM8\000"
902 /* 825 */ "YMM8\000"
903 /* 830 */ "ZMM8\000"
904 /* 835 */ "CR8\000"
905 /* 839 */ "DR8\000"
906 /* 843 */ "XMM19\000"
907 /* 849 */ "YMM19\000"
908 /* 855 */ "ZMM19\000"
909 /* 861 */ "R19\000"
910 /* 865 */ "XMM29\000"
911 /* 871 */ "YMM29\000"
912 /* 877 */ "ZMM29\000"
913 /* 883 */ "R29\000"
914 /* 887 */ "XMM9\000"
915 /* 892 */ "YMM9\000"
916 /* 897 */ "ZMM9\000"
917 /* 902 */ "CR9\000"
918 /* 906 */ "DR9\000"
919 /* 910 */ "R10B\000"
920 /* 915 */ "R20B\000"
921 /* 920 */ "R30B\000"
922 /* 925 */ "R11B\000"
923 /* 930 */ "R21B\000"
924 /* 935 */ "R31B\000"
925 /* 940 */ "R12B\000"
926 /* 945 */ "R22B\000"
927 /* 950 */ "R13B\000"
928 /* 955 */ "R23B\000"
929 /* 960 */ "R14B\000"
930 /* 965 */ "R24B\000"
931 /* 970 */ "R15B\000"
932 /* 975 */ "R25B\000"
933 /* 980 */ "R16B\000"
934 /* 985 */ "R26B\000"
935 /* 990 */ "R17B\000"
936 /* 995 */ "R27B\000"
937 /* 1000 */ "R18B\000"
938 /* 1005 */ "R28B\000"
939 /* 1010 */ "R8B\000"
940 /* 1014 */ "R19B\000"
941 /* 1019 */ "R29B\000"
942 /* 1024 */ "R9B\000"
943 /* 1028 */ "R10D\000"
944 /* 1033 */ "R20D\000"
945 /* 1038 */ "R30D\000"
946 /* 1043 */ "R11D\000"
947 /* 1048 */ "R21D\000"
948 /* 1053 */ "R31D\000"
949 /* 1058 */ "R12D\000"
950 /* 1063 */ "R22D\000"
951 /* 1068 */ "R13D\000"
952 /* 1073 */ "R23D\000"
953 /* 1078 */ "R14D\000"
954 /* 1083 */ "R24D\000"
955 /* 1088 */ "R15D\000"
956 /* 1093 */ "R25D\000"
957 /* 1098 */ "R16D\000"
958 /* 1103 */ "R26D\000"
959 /* 1108 */ "R17D\000"
960 /* 1113 */ "R27D\000"
961 /* 1118 */ "R18D\000"
962 /* 1123 */ "R28D\000"
963 /* 1128 */ "R8D\000"
964 /* 1132 */ "R19D\000"
965 /* 1137 */ "R29D\000"
966 /* 1142 */ "R9D\000"
967 /* 1146 */ "FS_BASE\000"
968 /* 1154 */ "GS_BASE\000"
969 /* 1162 */ "DF\000"
970 /* 1165 */ "TMMCFG\000"
971 /* 1172 */ "AH\000"
972 /* 1175 */ "R10BH\000"
973 /* 1181 */ "R20BH\000"
974 /* 1187 */ "R30BH\000"
975 /* 1193 */ "R11BH\000"
976 /* 1199 */ "R21BH\000"
977 /* 1205 */ "R31BH\000"
978 /* 1211 */ "R12BH\000"
979 /* 1217 */ "R22BH\000"
980 /* 1223 */ "R13BH\000"
981 /* 1229 */ "R23BH\000"
982 /* 1235 */ "R14BH\000"
983 /* 1241 */ "R24BH\000"
984 /* 1247 */ "R15BH\000"
985 /* 1253 */ "R25BH\000"
986 /* 1259 */ "R16BH\000"
987 /* 1265 */ "R26BH\000"
988 /* 1271 */ "R17BH\000"
989 /* 1277 */ "R27BH\000"
990 /* 1283 */ "R18BH\000"
991 /* 1289 */ "R28BH\000"
992 /* 1295 */ "R8BH\000"
993 /* 1300 */ "R19BH\000"
994 /* 1306 */ "R29BH\000"
995 /* 1312 */ "R9BH\000"
996 /* 1317 */ "CH\000"
997 /* 1320 */ "DH\000"
998 /* 1323 */ "DIH\000"
999 /* 1327 */ "SIH\000"
1000 /* 1331 */ "BPH\000"
1001 /* 1335 */ "SPH\000"
1002 /* 1339 */ "R10WH\000"
1003 /* 1345 */ "R20WH\000"
1004 /* 1351 */ "R30WH\000"
1005 /* 1357 */ "R11WH\000"
1006 /* 1363 */ "R21WH\000"
1007 /* 1369 */ "R31WH\000"
1008 /* 1375 */ "R12WH\000"
1009 /* 1381 */ "R22WH\000"
1010 /* 1387 */ "R13WH\000"
1011 /* 1393 */ "R23WH\000"
1012 /* 1399 */ "R14WH\000"
1013 /* 1405 */ "R24WH\000"
1014 /* 1411 */ "R15WH\000"
1015 /* 1417 */ "R25WH\000"
1016 /* 1423 */ "R16WH\000"
1017 /* 1429 */ "R26WH\000"
1018 /* 1435 */ "R17WH\000"
1019 /* 1441 */ "R27WH\000"
1020 /* 1447 */ "R18WH\000"
1021 /* 1453 */ "R28WH\000"
1022 /* 1459 */ "R8WH\000"
1023 /* 1464 */ "R19WH\000"
1024 /* 1470 */ "R29WH\000"
1025 /* 1476 */ "R9WH\000"
1026 /* 1481 */ "EDI\000"
1027 /* 1485 */ "HDI\000"
1028 /* 1489 */ "RDI\000"
1029 /* 1493 */ "ESI\000"
1030 /* 1497 */ "HSI\000"
1031 /* 1501 */ "RSI\000"
1032 /* 1505 */ "AL\000"
1033 /* 1508 */ "BL\000"
1034 /* 1511 */ "CL\000"
1035 /* 1514 */ "DL\000"
1036 /* 1517 */ "DIL\000"
1037 /* 1521 */ "SIL\000"
1038 /* 1525 */ "BPL\000"
1039 /* 1529 */ "SPL\000"
1040 /* 1533 */ "EBP\000"
1041 /* 1537 */ "HBP\000"
1042 /* 1541 */ "RBP\000"
1043 /* 1545 */ "EIP\000"
1044 /* 1549 */ "HIP\000"
1045 /* 1553 */ "RIP\000"
1046 /* 1557 */ "ESP\000"
1047 /* 1561 */ "HSP\000"
1048 /* 1565 */ "RSP\000"
1049 /* 1569 */ "SSP\000"
1050 /* 1573 */ "MXCSR\000"
1051 /* 1579 */ "CS\000"
1052 /* 1582 */ "DS\000"
1053 /* 1585 */ "ES\000"
1054 /* 1588 */ "FS\000"
1055 /* 1591 */ "_EFLAGS\000"
1056 /* 1599 */ "RFLAGS\000"
1057 /* 1606 */ "SS\000"
1058 /* 1609 */ "R10W\000"
1059 /* 1614 */ "R20W\000"
1060 /* 1619 */ "R30W\000"
1061 /* 1624 */ "R11W\000"
1062 /* 1629 */ "R21W\000"
1063 /* 1634 */ "R31W\000"
1064 /* 1639 */ "R12W\000"
1065 /* 1644 */ "R22W\000"
1066 /* 1649 */ "R13W\000"
1067 /* 1654 */ "R23W\000"
1068 /* 1659 */ "R14W\000"
1069 /* 1664 */ "R24W\000"
1070 /* 1669 */ "R15W\000"
1071 /* 1674 */ "R25W\000"
1072 /* 1679 */ "R16W\000"
1073 /* 1684 */ "R26W\000"
1074 /* 1689 */ "R17W\000"
1075 /* 1694 */ "R27W\000"
1076 /* 1699 */ "R18W\000"
1077 /* 1704 */ "R28W\000"
1078 /* 1709 */ "R8W\000"
1079 /* 1713 */ "R19W\000"
1080 /* 1718 */ "R29W\000"
1081 /* 1723 */ "R9W\000"
1082 /* 1727 */ "FPCW\000"
1083 /* 1732 */ "FPSW\000"
1084 /* 1737 */ "EAX\000"
1085 /* 1741 */ "HAX\000"
1086 /* 1745 */ "RAX\000"
1087 /* 1749 */ "EBX\000"
1088 /* 1753 */ "HBX\000"
1089 /* 1757 */ "RBX\000"
1090 /* 1761 */ "ECX\000"
1091 /* 1765 */ "HCX\000"
1092 /* 1769 */ "RCX\000"
1093 /* 1773 */ "EDX\000"
1094 /* 1777 */ "HDX\000"
1095 /* 1781 */ "RDX\000"
1096 /* 1785 */ "EIZ\000"
1097 /* 1789 */ "RIZ\000"
1098};
1099#ifdef __GNUC__
1100#pragma GCC diagnostic pop
1101#endif
1102
1103extern const MCRegisterDesc X86RegDesc[] = { // Descriptors
1104 { 5, 0, 0, 0, 0, 0, 0, 0 },
1105 { 1172, 2, 193, 2, 8192, 17, 0, 0 },
1106 { 1505, 2, 189, 2, 8193, 17, 0, 0 },
1107 { 1738, 50, 190, 0, 233472, 0, 0, 0 },
1108 { 1178, 2, 177, 2, 8194, 17, 0, 0 },
1109 { 1508, 2, 173, 2, 8195, 17, 0, 0 },
1110 { 1534, 53, 182, 2, 233476, 2, 0, 0 },
1111 { 1331, 2, 185, 2, 8197, 17, 0, 1 },
1112 { 1525, 2, 181, 2, 8196, 17, 0, 0 },
1113 { 1750, 44, 174, 0, 233474, 0, 0, 0 },
1114 { 1317, 2, 169, 2, 8198, 17, 0, 0 },
1115 { 1511, 2, 165, 2, 8199, 17, 0, 0 },
1116 { 1579, 2, 2, 2, 8200, 17, 0, 0 },
1117 { 1762, 47, 166, 0, 233478, 0, 0, 0 },
1118 { 1162, 2, 2, 2, 8201, 17, 0, 0 },
1119 { 1320, 2, 153, 2, 8202, 17, 0, 0 },
1120 { 1482, 53, 158, 2, 233483, 2, 0, 0 },
1121 { 1323, 2, 161, 2, 8204, 17, 0, 1 },
1122 { 1517, 2, 157, 2, 8203, 17, 0, 0 },
1123 { 1514, 2, 149, 2, 8205, 17, 0, 0 },
1124 { 1582, 2, 2, 2, 8206, 17, 0, 0 },
1125 { 1774, 37, 150, 0, 339978, 0, 0, 0 },
1126 { 1737, 225, 141, 5, 421888, 4, 0, 0 },
1127 { 1533, 213, 141, 10, 409604, 7, 0, 0 },
1128 { 1749, 219, 141, 5, 421890, 4, 0, 0 },
1129 { 1761, 207, 141, 5, 409606, 4, 0, 0 },
1130 { 1481, 116, 141, 10, 372747, 7, 0, 0 },
1131 { 1773, 198, 141, 5, 385034, 4, 0, 0 },
1132 { 1592, 2, 2, 2, 8213, 17, 0, 0 },
1133 { 1545, 41, 141, 15, 233494, 10, 0, 0 },
1134 { 1785, 2, 2, 2, 8216, 17, 0, 0 },
1135 { 1585, 2, 2, 2, 8217, 17, 0, 0 },
1136 { 1493, 32, 123, 10, 327706, 7, 0, 0 },
1137 { 1557, 23, 123, 10, 327709, 7, 0, 0 },
1138 { 1727, 2, 2, 2, 8224, 17, 0, 0 },
1139 { 1732, 2, 2, 2, 8225, 17, 0, 0 },
1140 { 1588, 2, 2, 2, 8226, 17, 0, 0 },
1141 { 1146, 2, 2, 2, 8227, 17, 0, 0 },
1142 { 1596, 2, 2, 2, 8228, 17, 0, 0 },
1143 { 1154, 2, 2, 2, 8229, 17, 0, 0 },
1144 { 1741, 2, 143, 2, 8207, 17, 0, 1 },
1145 { 1537, 2, 143, 2, 8208, 17, 0, 1 },
1146 { 1753, 2, 143, 2, 8209, 17, 0, 1 },
1147 { 1765, 2, 143, 2, 8210, 17, 0, 1 },
1148 { 1485, 2, 143, 2, 8211, 17, 0, 1 },
1149 { 1777, 2, 143, 2, 8212, 17, 0, 1 },
1150 { 1549, 2, 146, 2, 8215, 17, 0, 1 },
1151 { 1497, 2, 137, 2, 8220, 17, 0, 1 },
1152 { 1561, 2, 137, 2, 8223, 17, 0, 1 },
1153 { 1546, 2, 140, 2, 8214, 17, 0, 0 },
1154 { 1573, 2, 2, 2, 8230, 17, 0, 0 },
1155 { 1745, 224, 2, 4, 421888, 4, 0, 0 },
1156 { 1541, 212, 2, 9, 409604, 7, 0, 0 },
1157 { 1757, 218, 2, 4, 421890, 4, 0, 0 },
1158 { 1769, 206, 2, 4, 409606, 4, 0, 0 },
1159 { 1489, 115, 2, 9, 372747, 7, 0, 0 },
1160 { 1781, 197, 2, 4, 385034, 4, 0, 0 },
1161 { 1599, 2, 2, 2, 8231, 17, 0, 0 },
1162 { 1553, 40, 2, 14, 233494, 10, 0, 0 },
1163 { 1789, 2, 2, 2, 8232, 17, 0, 0 },
1164 { 1501, 31, 2, 9, 327706, 7, 0, 0 },
1165 { 1565, 22, 2, 9, 327709, 7, 0, 0 },
1166 { 1494, 53, 130, 2, 233498, 2, 0, 0 },
1167 { 1327, 2, 133, 2, 8219, 17, 0, 1 },
1168 { 1521, 2, 129, 2, 8218, 17, 0, 0 },
1169 { 1558, 53, 122, 2, 233501, 2, 0, 0 },
1170 { 1335, 2, 125, 2, 8222, 17, 0, 1 },
1171 { 1529, 2, 121, 2, 8221, 17, 0, 0 },
1172 { 1606, 2, 2, 2, 8233, 17, 0, 0 },
1173 { 1569, 2, 2, 2, 8234, 17, 0, 0 },
1174 { 1591, 2, 2, 2, 8235, 17, 0, 0 },
1175 { 99, 2, 2, 2, 8236, 17, 0, 0 },
1176 { 218, 2, 2, 2, 8237, 17, 0, 0 },
1177 { 307, 2, 2, 2, 8238, 17, 0, 0 },
1178 { 404, 2, 2, 2, 8239, 17, 0, 0 },
1179 { 493, 2, 2, 2, 8240, 17, 0, 0 },
1180 { 590, 2, 2, 2, 8241, 17, 0, 0 },
1181 { 673, 2, 2, 2, 8242, 17, 0, 0 },
1182 { 764, 2, 2, 2, 8243, 17, 0, 0 },
1183 { 835, 2, 2, 2, 8244, 17, 0, 0 },
1184 { 902, 2, 2, 2, 8245, 17, 0, 0 },
1185 { 18, 2, 2, 2, 8246, 17, 0, 0 },
1186 { 129, 2, 2, 2, 8247, 17, 0, 0 },
1187 { 248, 2, 2, 2, 8248, 17, 0, 0 },
1188 { 337, 2, 2, 2, 8249, 17, 0, 0 },
1189 { 434, 2, 2, 2, 8250, 17, 0, 0 },
1190 { 523, 2, 2, 2, 8251, 17, 0, 0 },
1191 { 103, 2, 2, 2, 8252, 17, 0, 0 },
1192 { 222, 2, 2, 2, 8253, 17, 0, 0 },
1193 { 311, 2, 2, 2, 8254, 17, 0, 0 },
1194 { 408, 2, 2, 2, 8255, 17, 0, 0 },
1195 { 497, 2, 2, 2, 8256, 17, 0, 0 },
1196 { 594, 2, 2, 2, 8257, 17, 0, 0 },
1197 { 677, 2, 2, 2, 8258, 17, 0, 0 },
1198 { 768, 2, 2, 2, 8259, 17, 0, 0 },
1199 { 839, 2, 2, 2, 8260, 17, 0, 0 },
1200 { 906, 2, 2, 2, 8261, 17, 0, 0 },
1201 { 23, 2, 2, 2, 8262, 17, 0, 0 },
1202 { 134, 2, 2, 2, 8263, 17, 0, 0 },
1203 { 253, 2, 2, 2, 8264, 17, 0, 0 },
1204 { 342, 2, 2, 2, 8265, 17, 0, 0 },
1205 { 439, 2, 2, 2, 8266, 17, 0, 0 },
1206 { 528, 2, 2, 2, 8267, 17, 0, 0 },
1207 { 95, 2, 2, 2, 8268, 17, 0, 0 },
1208 { 214, 2, 2, 2, 8269, 17, 0, 0 },
1209 { 303, 2, 2, 2, 8270, 17, 0, 0 },
1210 { 400, 2, 2, 2, 8271, 17, 0, 0 },
1211 { 489, 2, 2, 2, 8272, 17, 0, 0 },
1212 { 586, 2, 2, 2, 8273, 17, 0, 0 },
1213 { 669, 2, 2, 2, 8274, 17, 0, 0 },
1214 { 760, 2, 2, 2, 8275, 17, 0, 0 },
1215 { 76, 2, 2, 2, 8276, 17, 0, 0 },
1216 { 195, 2, 2, 2, 8277, 17, 0, 0 },
1217 { 284, 2, 2, 2, 8278, 17, 0, 0 },
1218 { 381, 2, 2, 2, 8279, 17, 0, 0 },
1219 { 470, 2, 2, 2, 8280, 17, 0, 0 },
1220 { 567, 2, 2, 2, 8281, 17, 0, 0 },
1221 { 650, 2, 2, 2, 8282, 17, 0, 0 },
1222 { 741, 2, 2, 2, 8283, 17, 0, 0 },
1223 { 836, 109, 2, 9, 327772, 7, 0, 0 },
1224 { 903, 109, 2, 9, 327775, 7, 0, 0 },
1225 { 19, 109, 2, 9, 327778, 7, 0, 0 },
1226 { 130, 109, 2, 9, 327781, 7, 0, 0 },
1227 { 249, 109, 2, 9, 327784, 7, 0, 0 },
1228 { 338, 109, 2, 9, 327787, 7, 0, 0 },
1229 { 435, 109, 2, 9, 327790, 7, 0, 0 },
1230 { 524, 109, 2, 9, 327793, 7, 0, 0 },
1231 { 107, 2, 2, 2, 8308, 17, 0, 0 },
1232 { 226, 2, 2, 2, 8309, 17, 0, 0 },
1233 { 315, 2, 2, 2, 8310, 17, 0, 0 },
1234 { 412, 2, 2, 2, 8311, 17, 0, 0 },
1235 { 501, 2, 2, 2, 8312, 17, 0, 0 },
1236 { 598, 2, 2, 2, 8313, 17, 0, 0 },
1237 { 681, 2, 2, 2, 8314, 17, 0, 0 },
1238 { 772, 2, 2, 2, 8315, 17, 0, 0 },
1239 { 80, 2, 236, 2, 8316, 17, 0, 0 },
1240 { 199, 2, 236, 2, 8317, 17, 0, 0 },
1241 { 288, 2, 236, 2, 8318, 17, 0, 0 },
1242 { 385, 2, 236, 2, 8319, 17, 0, 0 },
1243 { 474, 2, 236, 2, 8320, 17, 0, 0 },
1244 { 571, 2, 236, 2, 8321, 17, 0, 0 },
1245 { 654, 2, 236, 2, 8322, 17, 0, 0 },
1246 { 745, 2, 236, 2, 8323, 17, 0, 0 },
1247 { 820, 2, 236, 2, 8324, 17, 0, 0 },
1248 { 887, 2, 236, 2, 8325, 17, 0, 0 },
1249 { 0, 2, 236, 2, 8326, 17, 0, 0 },
1250 { 111, 2, 236, 2, 8327, 17, 0, 0 },
1251 { 230, 2, 236, 2, 8328, 17, 0, 0 },
1252 { 319, 2, 236, 2, 8329, 17, 0, 0 },
1253 { 416, 2, 236, 2, 8330, 17, 0, 0 },
1254 { 505, 2, 236, 2, 8331, 17, 0, 0 },
1255 { 1010, 2, 18, 2, 8284, 17, 0, 0 },
1256 { 1024, 2, 18, 2, 8287, 17, 0, 0 },
1257 { 910, 2, 18, 2, 8290, 17, 0, 0 },
1258 { 925, 2, 18, 2, 8293, 17, 0, 0 },
1259 { 940, 2, 18, 2, 8296, 17, 0, 0 },
1260 { 950, 2, 18, 2, 8299, 17, 0, 0 },
1261 { 960, 2, 18, 2, 8302, 17, 0, 0 },
1262 { 970, 2, 18, 2, 8305, 17, 0, 0 },
1263 { 1295, 2, 14, 2, 8285, 17, 0, 1 },
1264 { 1312, 2, 14, 2, 8288, 17, 0, 1 },
1265 { 1175, 2, 14, 2, 8291, 17, 0, 1 },
1266 { 1193, 2, 14, 2, 8294, 17, 0, 1 },
1267 { 1211, 2, 14, 2, 8297, 17, 0, 1 },
1268 { 1223, 2, 14, 2, 8300, 17, 0, 1 },
1269 { 1235, 2, 14, 2, 8303, 17, 0, 1 },
1270 { 1247, 2, 14, 2, 8306, 17, 0, 1 },
1271 { 1128, 110, 4, 10, 327772, 7, 0, 0 },
1272 { 1142, 110, 4, 10, 327775, 7, 0, 0 },
1273 { 1028, 110, 4, 10, 327778, 7, 0, 0 },
1274 { 1043, 110, 4, 10, 327781, 7, 0, 0 },
1275 { 1058, 110, 4, 10, 327784, 7, 0, 0 },
1276 { 1068, 110, 4, 10, 327787, 7, 0, 0 },
1277 { 1078, 110, 4, 10, 327790, 7, 0, 0 },
1278 { 1088, 110, 4, 10, 327793, 7, 0, 0 },
1279 { 1709, 97, 15, 2, 233564, 2, 0, 0 },
1280 { 1723, 97, 15, 2, 233567, 2, 0, 0 },
1281 { 1609, 97, 15, 2, 233570, 2, 0, 0 },
1282 { 1624, 97, 15, 2, 233573, 2, 0, 0 },
1283 { 1639, 97, 15, 2, 233576, 2, 0, 0 },
1284 { 1649, 97, 15, 2, 233579, 2, 0, 0 },
1285 { 1659, 97, 15, 2, 233582, 2, 0, 0 },
1286 { 1669, 97, 15, 2, 233585, 2, 0, 0 },
1287 { 1459, 2, 7, 2, 8286, 17, 0, 1 },
1288 { 1476, 2, 7, 2, 8289, 17, 0, 1 },
1289 { 1339, 2, 7, 2, 8292, 17, 0, 1 },
1290 { 1357, 2, 7, 2, 8295, 17, 0, 1 },
1291 { 1375, 2, 7, 2, 8298, 17, 0, 1 },
1292 { 1387, 2, 7, 2, 8301, 17, 0, 1 },
1293 { 1399, 2, 7, 2, 8304, 17, 0, 1 },
1294 { 1411, 2, 7, 2, 8307, 17, 0, 1 },
1295 { 85, 1, 237, 22, 8316, 16, 0, 0 },
1296 { 204, 1, 237, 22, 8317, 16, 0, 0 },
1297 { 293, 1, 237, 22, 8318, 16, 0, 0 },
1298 { 390, 1, 237, 22, 8319, 16, 0, 0 },
1299 { 479, 1, 237, 22, 8320, 16, 0, 0 },
1300 { 576, 1, 237, 22, 8321, 16, 0, 0 },
1301 { 659, 1, 237, 22, 8322, 16, 0, 0 },
1302 { 750, 1, 237, 22, 8323, 16, 0, 0 },
1303 { 825, 1, 237, 22, 8324, 16, 0, 0 },
1304 { 892, 1, 237, 22, 8325, 16, 0, 0 },
1305 { 6, 1, 237, 22, 8326, 16, 0, 0 },
1306 { 117, 1, 237, 22, 8327, 16, 0, 0 },
1307 { 236, 1, 237, 22, 8328, 16, 0, 0 },
1308 { 325, 1, 237, 22, 8329, 16, 0, 0 },
1309 { 422, 1, 237, 22, 8330, 16, 0, 0 },
1310 { 511, 1, 237, 22, 8331, 16, 0, 0 },
1311 { 72, 2, 247, 2, 8332, 17, 0, 0 },
1312 { 186, 2, 245, 2, 8333, 17, 0, 0 },
1313 { 280, 2, 245, 2, 8334, 17, 0, 0 },
1314 { 372, 2, 243, 2, 8335, 17, 0, 0 },
1315 { 466, 2, 243, 2, 8336, 17, 0, 0 },
1316 { 558, 2, 241, 2, 8337, 17, 0, 0 },
1317 { 646, 2, 241, 2, 8338, 17, 0, 0 },
1318 { 732, 2, 239, 2, 8339, 17, 0, 0 },
1319 { 602, 2, 203, 2, 8340, 17, 0, 0 },
1320 { 685, 2, 203, 2, 8341, 17, 0, 0 },
1321 { 776, 2, 203, 2, 8342, 17, 0, 0 },
1322 { 843, 2, 203, 2, 8343, 17, 0, 0 },
1323 { 28, 2, 203, 2, 8344, 17, 0, 0 },
1324 { 139, 2, 203, 2, 8345, 17, 0, 0 },
1325 { 258, 2, 203, 2, 8346, 17, 0, 0 },
1326 { 347, 2, 203, 2, 8347, 17, 0, 0 },
1327 { 444, 2, 203, 2, 8348, 17, 0, 0 },
1328 { 533, 2, 203, 2, 8349, 17, 0, 0 },
1329 { 624, 2, 203, 2, 8350, 17, 0, 0 },
1330 { 707, 2, 203, 2, 8351, 17, 0, 0 },
1331 { 798, 2, 203, 2, 8352, 17, 0, 0 },
1332 { 865, 2, 203, 2, 8353, 17, 0, 0 },
1333 { 50, 2, 203, 2, 8354, 17, 0, 0 },
1334 { 161, 2, 203, 2, 8355, 17, 0, 0 },
1335 { 608, 29, 204, 22, 8340, 16, 0, 0 },
1336 { 691, 29, 204, 22, 8341, 16, 0, 0 },
1337 { 782, 29, 204, 22, 8342, 16, 0, 0 },
1338 { 849, 29, 204, 22, 8343, 16, 0, 0 },
1339 { 34, 29, 204, 22, 8344, 16, 0, 0 },
1340 { 145, 29, 204, 22, 8345, 16, 0, 0 },
1341 { 264, 29, 204, 22, 8346, 16, 0, 0 },
1342 { 353, 29, 204, 22, 8347, 16, 0, 0 },
1343 { 450, 29, 204, 22, 8348, 16, 0, 0 },
1344 { 539, 29, 204, 22, 8349, 16, 0, 0 },
1345 { 630, 29, 204, 22, 8350, 16, 0, 0 },
1346 { 713, 29, 204, 22, 8351, 16, 0, 0 },
1347 { 804, 29, 204, 22, 8352, 16, 0, 0 },
1348 { 871, 29, 204, 22, 8353, 16, 0, 0 },
1349 { 56, 29, 204, 22, 8354, 16, 0, 0 },
1350 { 167, 29, 204, 22, 8355, 16, 0, 0 },
1351 { 90, 0, 2, 21, 8316, 16, 0, 0 },
1352 { 209, 0, 2, 21, 8317, 16, 0, 0 },
1353 { 298, 0, 2, 21, 8318, 16, 0, 0 },
1354 { 395, 0, 2, 21, 8319, 16, 0, 0 },
1355 { 484, 0, 2, 21, 8320, 16, 0, 0 },
1356 { 581, 0, 2, 21, 8321, 16, 0, 0 },
1357 { 664, 0, 2, 21, 8322, 16, 0, 0 },
1358 { 755, 0, 2, 21, 8323, 16, 0, 0 },
1359 { 830, 0, 2, 21, 8324, 16, 0, 0 },
1360 { 897, 0, 2, 21, 8325, 16, 0, 0 },
1361 { 12, 0, 2, 21, 8326, 16, 0, 0 },
1362 { 123, 0, 2, 21, 8327, 16, 0, 0 },
1363 { 242, 0, 2, 21, 8328, 16, 0, 0 },
1364 { 331, 0, 2, 21, 8329, 16, 0, 0 },
1365 { 428, 0, 2, 21, 8330, 16, 0, 0 },
1366 { 517, 0, 2, 21, 8331, 16, 0, 0 },
1367 { 614, 28, 2, 21, 8340, 16, 0, 0 },
1368 { 697, 28, 2, 21, 8341, 16, 0, 0 },
1369 { 788, 28, 2, 21, 8342, 16, 0, 0 },
1370 { 855, 28, 2, 21, 8343, 16, 0, 0 },
1371 { 40, 28, 2, 21, 8344, 16, 0, 0 },
1372 { 151, 28, 2, 21, 8345, 16, 0, 0 },
1373 { 270, 28, 2, 21, 8346, 16, 0, 0 },
1374 { 359, 28, 2, 21, 8347, 16, 0, 0 },
1375 { 456, 28, 2, 21, 8348, 16, 0, 0 },
1376 { 545, 28, 2, 21, 8349, 16, 0, 0 },
1377 { 636, 28, 2, 21, 8350, 16, 0, 0 },
1378 { 719, 28, 2, 21, 8351, 16, 0, 0 },
1379 { 810, 28, 2, 21, 8352, 16, 0, 0 },
1380 { 877, 28, 2, 21, 8353, 16, 0, 0 },
1381 { 62, 28, 2, 21, 8354, 16, 0, 0 },
1382 { 173, 28, 2, 21, 8355, 16, 0, 0 },
1383 { 183, 56, 2, 17, 233612, 12, 0, 0 },
1384 { 369, 59, 2, 17, 233614, 12, 0, 0 },
1385 { 555, 62, 2, 17, 233616, 12, 0, 0 },
1386 { 729, 65, 2, 17, 233618, 12, 0, 0 },
1387 { 1165, 2, 2, 2, 8356, 17, 0, 0 },
1388 { 75, 2, 98, 2, 8357, 17, 0, 0 },
1389 { 194, 2, 92, 2, 8358, 17, 0, 0 },
1390 { 283, 2, 92, 2, 8359, 17, 0, 0 },
1391 { 380, 2, 89, 2, 8360, 17, 0, 0 },
1392 { 469, 2, 89, 2, 8361, 17, 0, 0 },
1393 { 566, 2, 87, 2, 8362, 17, 0, 0 },
1394 { 649, 2, 87, 2, 8363, 17, 0, 0 },
1395 { 740, 2, 85, 2, 8364, 17, 0, 0 },
1396 { 189, 68, 2, 19, 233637, 14, 0, 0 },
1397 { 375, 71, 2, 19, 233639, 14, 0, 0 },
1398 { 561, 74, 2, 19, 233641, 14, 0, 0 },
1399 { 735, 77, 2, 19, 233643, 14, 0, 0 },
1400 { 620, 230, 2, 9, 327853, 7, 0, 0 },
1401 { 703, 230, 2, 9, 327856, 7, 0, 0 },
1402 { 794, 230, 2, 9, 327859, 7, 0, 0 },
1403 { 861, 230, 2, 9, 327862, 7, 0, 0 },
1404 { 46, 230, 2, 9, 327865, 7, 0, 0 },
1405 { 157, 230, 2, 9, 327868, 7, 0, 0 },
1406 { 276, 230, 2, 9, 327871, 7, 0, 0 },
1407 { 365, 230, 2, 9, 327874, 7, 0, 0 },
1408 { 462, 230, 2, 9, 327877, 7, 0, 0 },
1409 { 551, 230, 2, 9, 327880, 7, 0, 0 },
1410 { 642, 230, 2, 9, 327883, 7, 0, 0 },
1411 { 725, 230, 2, 9, 327886, 7, 0, 0 },
1412 { 816, 230, 2, 9, 327889, 7, 0, 0 },
1413 { 883, 230, 2, 9, 327892, 7, 0, 0 },
1414 { 68, 230, 2, 9, 327895, 7, 0, 0 },
1415 { 179, 230, 2, 9, 327898, 7, 0, 0 },
1416 { 980, 2, 10, 2, 8365, 17, 0, 0 },
1417 { 990, 2, 10, 2, 8368, 17, 0, 0 },
1418 { 1000, 2, 10, 2, 8371, 17, 0, 0 },
1419 { 1014, 2, 10, 2, 8374, 17, 0, 0 },
1420 { 915, 2, 10, 2, 8377, 17, 0, 0 },
1421 { 930, 2, 10, 2, 8380, 17, 0, 0 },
1422 { 945, 2, 10, 2, 8383, 17, 0, 0 },
1423 { 955, 2, 10, 2, 8386, 17, 0, 0 },
1424 { 965, 2, 10, 2, 8389, 17, 0, 0 },
1425 { 975, 2, 10, 2, 8392, 17, 0, 0 },
1426 { 985, 2, 10, 2, 8395, 17, 0, 0 },
1427 { 995, 2, 10, 2, 8398, 17, 0, 0 },
1428 { 1005, 2, 10, 2, 8401, 17, 0, 0 },
1429 { 1019, 2, 10, 2, 8404, 17, 0, 0 },
1430 { 920, 2, 10, 2, 8407, 17, 0, 0 },
1431 { 935, 2, 10, 2, 8410, 17, 0, 0 },
1432 { 1259, 2, 6, 2, 8366, 17, 0, 1 },
1433 { 1271, 2, 6, 2, 8369, 17, 0, 1 },
1434 { 1283, 2, 6, 2, 8372, 17, 0, 1 },
1435 { 1300, 2, 6, 2, 8375, 17, 0, 1 },
1436 { 1181, 2, 6, 2, 8378, 17, 0, 1 },
1437 { 1199, 2, 6, 2, 8381, 17, 0, 1 },
1438 { 1217, 2, 6, 2, 8384, 17, 0, 1 },
1439 { 1229, 2, 6, 2, 8387, 17, 0, 1 },
1440 { 1241, 2, 6, 2, 8390, 17, 0, 1 },
1441 { 1253, 2, 6, 2, 8393, 17, 0, 1 },
1442 { 1265, 2, 6, 2, 8396, 17, 0, 1 },
1443 { 1277, 2, 6, 2, 8399, 17, 0, 1 },
1444 { 1289, 2, 6, 2, 8402, 17, 0, 1 },
1445 { 1306, 2, 6, 2, 8405, 17, 0, 1 },
1446 { 1187, 2, 6, 2, 8408, 17, 0, 1 },
1447 { 1205, 2, 6, 2, 8411, 17, 0, 1 },
1448 { 1098, 231, 4, 10, 327853, 7, 0, 0 },
1449 { 1108, 231, 4, 10, 327856, 7, 0, 0 },
1450 { 1118, 231, 4, 10, 327859, 7, 0, 0 },
1451 { 1132, 231, 4, 10, 327862, 7, 0, 0 },
1452 { 1033, 231, 4, 10, 327865, 7, 0, 0 },
1453 { 1048, 231, 4, 10, 327868, 7, 0, 0 },
1454 { 1063, 231, 4, 10, 327871, 7, 0, 0 },
1455 { 1073, 231, 4, 10, 327874, 7, 0, 0 },
1456 { 1083, 231, 4, 10, 327877, 7, 0, 0 },
1457 { 1093, 231, 4, 10, 327880, 7, 0, 0 },
1458 { 1103, 231, 4, 10, 327883, 7, 0, 0 },
1459 { 1113, 231, 4, 10, 327886, 7, 0, 0 },
1460 { 1123, 231, 4, 10, 327889, 7, 0, 0 },
1461 { 1137, 231, 4, 10, 327892, 7, 0, 0 },
1462 { 1038, 231, 4, 10, 327895, 7, 0, 0 },
1463 { 1053, 231, 4, 10, 327898, 7, 0, 0 },
1464 { 1679, 106, 7, 2, 233645, 2, 0, 0 },
1465 { 1689, 106, 7, 2, 233648, 2, 0, 0 },
1466 { 1699, 106, 7, 2, 233651, 2, 0, 0 },
1467 { 1713, 106, 7, 2, 233654, 2, 0, 0 },
1468 { 1614, 106, 7, 2, 233657, 2, 0, 0 },
1469 { 1629, 106, 7, 2, 233660, 2, 0, 0 },
1470 { 1644, 106, 7, 2, 233663, 2, 0, 0 },
1471 { 1654, 106, 7, 2, 233666, 2, 0, 0 },
1472 { 1664, 106, 7, 2, 233669, 2, 0, 0 },
1473 { 1674, 106, 7, 2, 233672, 2, 0, 0 },
1474 { 1684, 106, 7, 2, 233675, 2, 0, 0 },
1475 { 1694, 106, 7, 2, 233678, 2, 0, 0 },
1476 { 1704, 106, 7, 2, 233681, 2, 0, 0 },
1477 { 1718, 106, 7, 2, 233684, 2, 0, 0 },
1478 { 1619, 106, 7, 2, 233687, 2, 0, 0 },
1479 { 1634, 106, 7, 2, 233690, 2, 0, 0 },
1480 { 1423, 2, 3, 2, 8367, 17, 0, 1 },
1481 { 1435, 2, 3, 2, 8370, 17, 0, 1 },
1482 { 1447, 2, 3, 2, 8373, 17, 0, 1 },
1483 { 1464, 2, 3, 2, 8376, 17, 0, 1 },
1484 { 1345, 2, 3, 2, 8379, 17, 0, 1 },
1485 { 1363, 2, 3, 2, 8382, 17, 0, 1 },
1486 { 1381, 2, 3, 2, 8385, 17, 0, 1 },
1487 { 1393, 2, 3, 2, 8388, 17, 0, 1 },
1488 { 1405, 2, 3, 2, 8391, 17, 0, 1 },
1489 { 1417, 2, 3, 2, 8394, 17, 0, 1 },
1490 { 1429, 2, 3, 2, 8397, 17, 0, 1 },
1491 { 1441, 2, 3, 2, 8400, 17, 0, 1 },
1492 { 1453, 2, 3, 2, 8403, 17, 0, 1 },
1493 { 1470, 2, 3, 2, 8406, 17, 0, 1 },
1494 { 1351, 2, 3, 2, 8409, 17, 0, 1 },
1495 { 1369, 2, 3, 2, 8412, 17, 0, 1 },
1496};
1497
1498extern const MCPhysReg X86RegUnitRoots[][2] = {
1499 { X86::AH },
1500 { X86::AL },
1501 { X86::BH },
1502 { X86::BL },
1503 { X86::BPL },
1504 { X86::BPH },
1505 { X86::CH },
1506 { X86::CL },
1507 { X86::CS },
1508 { X86::DF },
1509 { X86::DH },
1510 { X86::DIL },
1511 { X86::DIH },
1512 { X86::DL },
1513 { X86::DS },
1514 { X86::HAX },
1515 { X86::HBP },
1516 { X86::HBX },
1517 { X86::HCX },
1518 { X86::HDI },
1519 { X86::HDX },
1520 { X86::EFLAGS },
1521 { X86::IP },
1522 { X86::HIP },
1523 { X86::EIZ },
1524 { X86::ES },
1525 { X86::SIL },
1526 { X86::SIH },
1527 { X86::HSI },
1528 { X86::SPL },
1529 { X86::SPH },
1530 { X86::HSP },
1531 { X86::FPCW },
1532 { X86::FPSW },
1533 { X86::FS },
1534 { X86::FS_BASE },
1535 { X86::GS },
1536 { X86::GS_BASE },
1537 { X86::MXCSR },
1538 { X86::RFLAGS },
1539 { X86::RIZ },
1540 { X86::SS },
1541 { X86::SSP },
1542 { X86::_EFLAGS },
1543 { X86::CR0 },
1544 { X86::CR1 },
1545 { X86::CR2 },
1546 { X86::CR3 },
1547 { X86::CR4 },
1548 { X86::CR5 },
1549 { X86::CR6 },
1550 { X86::CR7 },
1551 { X86::CR8 },
1552 { X86::CR9 },
1553 { X86::CR10 },
1554 { X86::CR11 },
1555 { X86::CR12 },
1556 { X86::CR13 },
1557 { X86::CR14 },
1558 { X86::CR15 },
1559 { X86::DR0 },
1560 { X86::DR1 },
1561 { X86::DR2 },
1562 { X86::DR3 },
1563 { X86::DR4 },
1564 { X86::DR5 },
1565 { X86::DR6 },
1566 { X86::DR7 },
1567 { X86::DR8 },
1568 { X86::DR9 },
1569 { X86::DR10 },
1570 { X86::DR11 },
1571 { X86::DR12 },
1572 { X86::DR13 },
1573 { X86::DR14 },
1574 { X86::DR15 },
1575 { X86::FP0 },
1576 { X86::FP1 },
1577 { X86::FP2 },
1578 { X86::FP3 },
1579 { X86::FP4 },
1580 { X86::FP5 },
1581 { X86::FP6 },
1582 { X86::FP7 },
1583 { X86::MM0 },
1584 { X86::MM1 },
1585 { X86::MM2 },
1586 { X86::MM3 },
1587 { X86::MM4 },
1588 { X86::MM5 },
1589 { X86::MM6 },
1590 { X86::MM7 },
1591 { X86::R8B },
1592 { X86::R8BH },
1593 { X86::R8WH },
1594 { X86::R9B },
1595 { X86::R9BH },
1596 { X86::R9WH },
1597 { X86::R10B },
1598 { X86::R10BH },
1599 { X86::R10WH },
1600 { X86::R11B },
1601 { X86::R11BH },
1602 { X86::R11WH },
1603 { X86::R12B },
1604 { X86::R12BH },
1605 { X86::R12WH },
1606 { X86::R13B },
1607 { X86::R13BH },
1608 { X86::R13WH },
1609 { X86::R14B },
1610 { X86::R14BH },
1611 { X86::R14WH },
1612 { X86::R15B },
1613 { X86::R15BH },
1614 { X86::R15WH },
1615 { X86::ST0 },
1616 { X86::ST1 },
1617 { X86::ST2 },
1618 { X86::ST3 },
1619 { X86::ST4 },
1620 { X86::ST5 },
1621 { X86::ST6 },
1622 { X86::ST7 },
1623 { X86::XMM0 },
1624 { X86::XMM1 },
1625 { X86::XMM2 },
1626 { X86::XMM3 },
1627 { X86::XMM4 },
1628 { X86::XMM5 },
1629 { X86::XMM6 },
1630 { X86::XMM7 },
1631 { X86::XMM8 },
1632 { X86::XMM9 },
1633 { X86::XMM10 },
1634 { X86::XMM11 },
1635 { X86::XMM12 },
1636 { X86::XMM13 },
1637 { X86::XMM14 },
1638 { X86::XMM15 },
1639 { X86::K0 },
1640 { X86::K1 },
1641 { X86::K2 },
1642 { X86::K3 },
1643 { X86::K4 },
1644 { X86::K5 },
1645 { X86::K6 },
1646 { X86::K7 },
1647 { X86::XMM16 },
1648 { X86::XMM17 },
1649 { X86::XMM18 },
1650 { X86::XMM19 },
1651 { X86::XMM20 },
1652 { X86::XMM21 },
1653 { X86::XMM22 },
1654 { X86::XMM23 },
1655 { X86::XMM24 },
1656 { X86::XMM25 },
1657 { X86::XMM26 },
1658 { X86::XMM27 },
1659 { X86::XMM28 },
1660 { X86::XMM29 },
1661 { X86::XMM30 },
1662 { X86::XMM31 },
1663 { X86::TMMCFG },
1664 { X86::TMM0 },
1665 { X86::TMM1 },
1666 { X86::TMM2 },
1667 { X86::TMM3 },
1668 { X86::TMM4 },
1669 { X86::TMM5 },
1670 { X86::TMM6 },
1671 { X86::TMM7 },
1672 { X86::R16B },
1673 { X86::R16BH },
1674 { X86::R16WH },
1675 { X86::R17B },
1676 { X86::R17BH },
1677 { X86::R17WH },
1678 { X86::R18B },
1679 { X86::R18BH },
1680 { X86::R18WH },
1681 { X86::R19B },
1682 { X86::R19BH },
1683 { X86::R19WH },
1684 { X86::R20B },
1685 { X86::R20BH },
1686 { X86::R20WH },
1687 { X86::R21B },
1688 { X86::R21BH },
1689 { X86::R21WH },
1690 { X86::R22B },
1691 { X86::R22BH },
1692 { X86::R22WH },
1693 { X86::R23B },
1694 { X86::R23BH },
1695 { X86::R23WH },
1696 { X86::R24B },
1697 { X86::R24BH },
1698 { X86::R24WH },
1699 { X86::R25B },
1700 { X86::R25BH },
1701 { X86::R25WH },
1702 { X86::R26B },
1703 { X86::R26BH },
1704 { X86::R26WH },
1705 { X86::R27B },
1706 { X86::R27BH },
1707 { X86::R27WH },
1708 { X86::R28B },
1709 { X86::R28BH },
1710 { X86::R28WH },
1711 { X86::R29B },
1712 { X86::R29BH },
1713 { X86::R29WH },
1714 { X86::R30B },
1715 { X86::R30BH },
1716 { X86::R30WH },
1717 { X86::R31B },
1718 { X86::R31BH },
1719 { X86::R31WH },
1720};
1721
1722namespace { // Register classes...
1723 // GR8 Register Class...
1724 const MCPhysReg GR8[] = {
1725 X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH, X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R16B, X86::R17B, X86::R18B, X86::R19B, X86::R22B, X86::R23B, X86::R24B, X86::R25B, X86::R26B, X86::R27B, X86::R30B, X86::R31B, X86::R14B, X86::R15B, X86::R12B, X86::R13B, X86::R20B, X86::R21B, X86::R28B, X86::R29B,
1726 };
1727
1728 // GR8 Bit set.
1729 const uint8_t GR8Bits[] = {
1730 0x36, 0x8d, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
1731 };
1732
1733 // GRH8 Register Class...
1734 const MCPhysReg GRH8[] = {
1735 X86::SIH, X86::DIH, X86::BPH, X86::SPH, X86::R8BH, X86::R9BH, X86::R10BH, X86::R11BH, X86::R12BH, X86::R13BH, X86::R14BH, X86::R15BH, X86::R16BH, X86::R17BH, X86::R18BH, X86::R19BH, X86::R20BH, X86::R21BH, X86::R22BH, X86::R23BH, X86::R24BH, X86::R25BH, X86::R26BH, X86::R27BH, X86::R28BH, X86::R29BH, X86::R30BH, X86::R31BH,
1736 };
1737
1738 // GRH8 Bit set.
1739 const uint8_t GRH8Bits[] = {
1740 0x80, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x80, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
1741 };
1742
1743 // GR8_NOREX2 Register Class...
1744 const MCPhysReg GR8_NOREX2[] = {
1745 X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH, X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R14B, X86::R15B, X86::R12B, X86::R13B,
1746 };
1747
1748 // GR8_NOREX2 Bit set.
1749 const uint8_t GR8_NOREX2Bits[] = {
1750 0x36, 0x8d, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
1751 };
1752
1753 // GR8_NOREX Register Class...
1754 const MCPhysReg GR8_NOREX[] = {
1755 X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH,
1756 };
1757
1758 // GR8_NOREX Bit set.
1759 const uint8_t GR8_NOREXBits[] = {
1760 0x36, 0x8c, 0x08,
1761 };
1762
1763 // GR8_ABCD_H Register Class...
1764 const MCPhysReg GR8_ABCD_H[] = {
1765 X86::AH, X86::CH, X86::DH, X86::BH,
1766 };
1767
1768 // GR8_ABCD_H Bit set.
1769 const uint8_t GR8_ABCD_HBits[] = {
1770 0x12, 0x84,
1771 };
1772
1773 // GR8_ABCD_L Register Class...
1774 const MCPhysReg GR8_ABCD_L[] = {
1775 X86::AL, X86::CL, X86::DL, X86::BL,
1776 };
1777
1778 // GR8_ABCD_L Bit set.
1779 const uint8_t GR8_ABCD_LBits[] = {
1780 0x24, 0x08, 0x08,
1781 };
1782
1783 // GRH16 Register Class...
1784 const MCPhysReg GRH16[] = {
1785 X86::HAX, X86::HCX, X86::HDX, X86::HSI, X86::HDI, X86::HBX, X86::HBP, X86::HSP, X86::HIP, X86::R8WH, X86::R9WH, X86::R10WH, X86::R11WH, X86::R12WH, X86::R13WH, X86::R14WH, X86::R15WH, X86::R16WH, X86::R17WH, X86::R18WH, X86::R19WH, X86::R20WH, X86::R21WH, X86::R22WH, X86::R23WH, X86::R24WH, X86::R25WH, X86::R26WH, X86::R27WH, X86::R28WH, X86::R29WH, X86::R30WH, X86::R31WH,
1786 };
1787
1788 // GRH16 Bit set.
1789 const uint8_t GRH16Bits[] = {
1790 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
1791 };
1792
1793 // GR16 Register Class...
1794 const MCPhysReg GR16[] = {
1795 X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP, X86::SP, X86::R8W, X86::R9W, X86::R10W, X86::R11W, X86::R16W, X86::R17W, X86::R18W, X86::R19W, X86::R22W, X86::R23W, X86::R24W, X86::R25W, X86::R26W, X86::R27W, X86::R30W, X86::R31W, X86::R14W, X86::R15W, X86::R12W, X86::R13W, X86::R20W, X86::R21W, X86::R28W, X86::R29W,
1796 };
1797
1798 // GR16 Bit set.
1799 const uint8_t GR16Bits[] = {
1800 0x48, 0x22, 0x21, 0x00, 0x00, 0x00, 0x00, 0x40, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
1801 };
1802
1803 // GR16_NOREX2 Register Class...
1804 const MCPhysReg GR16_NOREX2[] = {
1805 X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP, X86::SP, X86::R8W, X86::R9W, X86::R10W, X86::R11W, X86::R14W, X86::R15W, X86::R12W, X86::R13W,
1806 };
1807
1808 // GR16_NOREX2 Bit set.
1809 const uint8_t GR16_NOREX2Bits[] = {
1810 0x48, 0x22, 0x21, 0x00, 0x00, 0x00, 0x00, 0x40, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
1811 };
1812
1813 // GR16_NOREX Register Class...
1814 const MCPhysReg GR16_NOREX[] = {
1815 X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP, X86::SP,
1816 };
1817
1818 // GR16_NOREX Bit set.
1819 const uint8_t GR16_NOREXBits[] = {
1820 0x48, 0x22, 0x21, 0x00, 0x00, 0x00, 0x00, 0x40, 0x02,
1821 };
1822
1823 // VK1 Register Class...
1824 const MCPhysReg VK1[] = {
1825 X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
1826 };
1827
1828 // VK1 Bit set.
1829 const uint8_t VK1Bits[] = {
1830 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
1831 };
1832
1833 // VK16 Register Class...
1834 const MCPhysReg VK16[] = {
1835 X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
1836 };
1837
1838 // VK16 Bit set.
1839 const uint8_t VK16Bits[] = {
1840 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
1841 };
1842
1843 // VK2 Register Class...
1844 const MCPhysReg VK2[] = {
1845 X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
1846 };
1847
1848 // VK2 Bit set.
1849 const uint8_t VK2Bits[] = {
1850 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
1851 };
1852
1853 // VK4 Register Class...
1854 const MCPhysReg VK4[] = {
1855 X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
1856 };
1857
1858 // VK4 Bit set.
1859 const uint8_t VK4Bits[] = {
1860 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
1861 };
1862
1863 // VK8 Register Class...
1864 const MCPhysReg VK8[] = {
1865 X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
1866 };
1867
1868 // VK8 Bit set.
1869 const uint8_t VK8Bits[] = {
1870 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
1871 };
1872
1873 // VK16WM Register Class...
1874 const MCPhysReg VK16WM[] = {
1875 X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
1876 };
1877
1878 // VK16WM Bit set.
1879 const uint8_t VK16WMBits[] = {
1880 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f,
1881 };
1882
1883 // VK1WM Register Class...
1884 const MCPhysReg VK1WM[] = {
1885 X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
1886 };
1887
1888 // VK1WM Bit set.
1889 const uint8_t VK1WMBits[] = {
1890 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f,
1891 };
1892
1893 // VK2WM Register Class...
1894 const MCPhysReg VK2WM[] = {
1895 X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
1896 };
1897
1898 // VK2WM Bit set.
1899 const uint8_t VK2WMBits[] = {
1900 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f,
1901 };
1902
1903 // VK4WM Register Class...
1904 const MCPhysReg VK4WM[] = {
1905 X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
1906 };
1907
1908 // VK4WM Bit set.
1909 const uint8_t VK4WMBits[] = {
1910 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f,
1911 };
1912
1913 // VK8WM Register Class...
1914 const MCPhysReg VK8WM[] = {
1915 X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
1916 };
1917
1918 // VK8WM Bit set.
1919 const uint8_t VK8WMBits[] = {
1920 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f,
1921 };
1922
1923 // SEGMENT_REG Register Class...
1924 const MCPhysReg SEGMENT_REG[] = {
1925 X86::CS, X86::DS, X86::SS, X86::ES, X86::FS, X86::GS,
1926 };
1927
1928 // SEGMENT_REG Bit set.
1929 const uint8_t SEGMENT_REGBits[] = {
1930 0x00, 0x10, 0x10, 0x80, 0x50, 0x00, 0x00, 0x00, 0x10,
1931 };
1932
1933 // GR16_ABCD Register Class...
1934 const MCPhysReg GR16_ABCD[] = {
1935 X86::AX, X86::CX, X86::DX, X86::BX,
1936 };
1937
1938 // GR16_ABCD Bit set.
1939 const uint8_t GR16_ABCDBits[] = {
1940 0x08, 0x22, 0x20,
1941 };
1942
1943 // FPCCR Register Class...
1944 const MCPhysReg FPCCR[] = {
1945 X86::FPSW,
1946 };
1947
1948 // FPCCR Bit set.
1949 const uint8_t FPCCRBits[] = {
1950 0x00, 0x00, 0x00, 0x00, 0x08,
1951 };
1952
1953 // FR16X Register Class...
1954 const MCPhysReg FR16X[] = {
1955 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31,
1956 };
1957
1958 // FR16X Bit set.
1959 const uint8_t FR16XBits[] = {
1960 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
1961 };
1962
1963 // FR16 Register Class...
1964 const MCPhysReg FR16[] = {
1965 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15,
1966 };
1967
1968 // FR16 Bit set.
1969 const uint8_t FR16Bits[] = {
1970 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
1971 };
1972
1973 // VK16PAIR Register Class...
1974 const MCPhysReg VK16PAIR[] = {
1975 X86::K0_K1, X86::K2_K3, X86::K4_K5, X86::K6_K7,
1976 };
1977
1978 // VK16PAIR Bit set.
1979 const uint8_t VK16PAIRBits[] = {
1980 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07,
1981 };
1982
1983 // VK1PAIR Register Class...
1984 const MCPhysReg VK1PAIR[] = {
1985 X86::K0_K1, X86::K2_K3, X86::K4_K5, X86::K6_K7,
1986 };
1987
1988 // VK1PAIR Bit set.
1989 const uint8_t VK1PAIRBits[] = {
1990 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07,
1991 };
1992
1993 // VK2PAIR Register Class...
1994 const MCPhysReg VK2PAIR[] = {
1995 X86::K0_K1, X86::K2_K3, X86::K4_K5, X86::K6_K7,
1996 };
1997
1998 // VK2PAIR Bit set.
1999 const uint8_t VK2PAIRBits[] = {
2000 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07,
2001 };
2002
2003 // VK4PAIR Register Class...
2004 const MCPhysReg VK4PAIR[] = {
2005 X86::K0_K1, X86::K2_K3, X86::K4_K5, X86::K6_K7,
2006 };
2007
2008 // VK4PAIR Bit set.
2009 const uint8_t VK4PAIRBits[] = {
2010 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07,
2011 };
2012
2013 // VK8PAIR Register Class...
2014 const MCPhysReg VK8PAIR[] = {
2015 X86::K0_K1, X86::K2_K3, X86::K4_K5, X86::K6_K7,
2016 };
2017
2018 // VK8PAIR Bit set.
2019 const uint8_t VK8PAIRBits[] = {
2020 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07,
2021 };
2022
2023 // VK1PAIR_with_sub_mask_0_in_VK1WM Register Class...
2024 const MCPhysReg VK1PAIR_with_sub_mask_0_in_VK1WM[] = {
2025 X86::K2_K3, X86::K4_K5, X86::K6_K7,
2026 };
2027
2028 // VK1PAIR_with_sub_mask_0_in_VK1WM Bit set.
2029 const uint8_t VK1PAIR_with_sub_mask_0_in_VK1WMBits[] = {
2030 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
2031 };
2032
2033 // LOW32_ADDR_ACCESS_RBP Register Class...
2034 const MCPhysReg LOW32_ADDR_ACCESS_RBP[] = {
2035 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R16D, X86::R17D, X86::R18D, X86::R19D, X86::R22D, X86::R23D, X86::R24D, X86::R25D, X86::R26D, X86::R27D, X86::R30D, X86::R31D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::R20D, X86::R21D, X86::R28D, X86::R29D, X86::RIP, X86::RBP,
2036 };
2037
2038 // LOW32_ADDR_ACCESS_RBP Bit set.
2039 const uint8_t LOW32_ADDR_ACCESS_RBPBits[] = {
2040 0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x10, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
2041 };
2042
2043 // LOW32_ADDR_ACCESS Register Class...
2044 const MCPhysReg LOW32_ADDR_ACCESS[] = {
2045 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R16D, X86::R17D, X86::R18D, X86::R19D, X86::R22D, X86::R23D, X86::R24D, X86::R25D, X86::R26D, X86::R27D, X86::R30D, X86::R31D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::R20D, X86::R21D, X86::R28D, X86::R29D, X86::RIP,
2046 };
2047
2048 // LOW32_ADDR_ACCESS Bit set.
2049 const uint8_t LOW32_ADDR_ACCESSBits[] = {
2050 0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
2051 };
2052
2053 // LOW32_ADDR_ACCESS_RBP_with_sub_8bit Register Class...
2054 const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_8bit[] = {
2055 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R16D, X86::R17D, X86::R18D, X86::R19D, X86::R22D, X86::R23D, X86::R24D, X86::R25D, X86::R26D, X86::R27D, X86::R30D, X86::R31D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::R20D, X86::R21D, X86::R28D, X86::R29D, X86::RBP,
2056 };
2057
2058 // LOW32_ADDR_ACCESS_RBP_with_sub_8bit Bit set.
2059 const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_8bitBits[] = {
2060 0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
2061 };
2062
2063 // FR32X Register Class...
2064 const MCPhysReg FR32X[] = {
2065 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31,
2066 };
2067
2068 // FR32X Bit set.
2069 const uint8_t FR32XBits[] = {
2070 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
2071 };
2072
2073 // GR32 Register Class...
2074 const MCPhysReg GR32[] = {
2075 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R16D, X86::R17D, X86::R18D, X86::R19D, X86::R22D, X86::R23D, X86::R24D, X86::R25D, X86::R26D, X86::R27D, X86::R30D, X86::R31D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::R20D, X86::R21D, X86::R28D, X86::R29D,
2076 };
2077
2078 // GR32 Bit set.
2079 const uint8_t GR32Bits[] = {
2080 0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
2081 };
2082
2083 // GR32_NOSP Register Class...
2084 const MCPhysReg GR32_NOSP[] = {
2085 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R16D, X86::R17D, X86::R18D, X86::R19D, X86::R22D, X86::R23D, X86::R24D, X86::R25D, X86::R26D, X86::R27D, X86::R30D, X86::R31D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::R20D, X86::R21D, X86::R28D, X86::R29D,
2086 };
2087
2088 // GR32_NOSP Bit set.
2089 const uint8_t GR32_NOSPBits[] = {
2090 0x00, 0x00, 0xc0, 0x0f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
2091 };
2092
2093 // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2 Register Class...
2094 const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2[] = {
2095 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::RBP,
2096 };
2097
2098 // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2 Bit set.
2099 const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2Bits[] = {
2100 0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
2101 };
2102
2103 // DEBUG_REG Register Class...
2104 const MCPhysReg DEBUG_REG[] = {
2105 X86::DR0, X86::DR1, X86::DR2, X86::DR3, X86::DR4, X86::DR5, X86::DR6, X86::DR7, X86::DR8, X86::DR9, X86::DR10, X86::DR11, X86::DR12, X86::DR13, X86::DR14, X86::DR15,
2106 };
2107
2108 // DEBUG_REG Bit set.
2109 const uint8_t DEBUG_REGBits[] = {
2110 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
2111 };
2112
2113 // FR32 Register Class...
2114 const MCPhysReg FR32[] = {
2115 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15,
2116 };
2117
2118 // FR32 Bit set.
2119 const uint8_t FR32Bits[] = {
2120 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
2121 };
2122
2123 // GR32_NOREX2 Register Class...
2124 const MCPhysReg GR32_NOREX2[] = {
2125 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D,
2126 };
2127
2128 // GR32_NOREX2 Bit set.
2129 const uint8_t GR32_NOREX2Bits[] = {
2130 0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
2131 };
2132
2133 // GR32_NOREX2_NOSP Register Class...
2134 const MCPhysReg GR32_NOREX2_NOSP[] = {
2135 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D,
2136 };
2137
2138 // GR32_NOREX2_NOSP Bit set.
2139 const uint8_t GR32_NOREX2_NOSPBits[] = {
2140 0x00, 0x00, 0xc0, 0x0f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
2141 };
2142
2143 // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX Register Class...
2144 const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX[] = {
2145 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::RBP,
2146 };
2147
2148 // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX Bit set.
2149 const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXBits[] = {
2150 0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x10,
2151 };
2152
2153 // GR32_NOREX Register Class...
2154 const MCPhysReg GR32_NOREX[] = {
2155 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP,
2156 };
2157
2158 // GR32_NOREX Bit set.
2159 const uint8_t GR32_NOREXBits[] = {
2160 0x00, 0x00, 0xc0, 0x0f, 0x03,
2161 };
2162
2163 // VK32 Register Class...
2164 const MCPhysReg VK32[] = {
2165 X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
2166 };
2167
2168 // VK32 Bit set.
2169 const uint8_t VK32Bits[] = {
2170 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
2171 };
2172
2173 // GR32_NOREX_NOSP Register Class...
2174 const MCPhysReg GR32_NOREX_NOSP[] = {
2175 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP,
2176 };
2177
2178 // GR32_NOREX_NOSP Bit set.
2179 const uint8_t GR32_NOREX_NOSPBits[] = {
2180 0x00, 0x00, 0xc0, 0x0f, 0x01,
2181 };
2182
2183 // RFP32 Register Class...
2184 const MCPhysReg RFP32[] = {
2185 X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6,
2186 };
2187
2188 // RFP32 Bit set.
2189 const uint8_t RFP32Bits[] = {
2190 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f,
2191 };
2192
2193 // VK32WM Register Class...
2194 const MCPhysReg VK32WM[] = {
2195 X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
2196 };
2197
2198 // VK32WM Bit set.
2199 const uint8_t VK32WMBits[] = {
2200 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f,
2201 };
2202
2203 // GR32_ABCD Register Class...
2204 const MCPhysReg GR32_ABCD[] = {
2205 X86::EAX, X86::ECX, X86::EDX, X86::EBX,
2206 };
2207
2208 // GR32_ABCD Bit set.
2209 const uint8_t GR32_ABCDBits[] = {
2210 0x00, 0x00, 0x40, 0x0b,
2211 };
2212
2213 // GR32_TC Register Class...
2214 const MCPhysReg GR32_TC[] = {
2215 X86::EAX, X86::ECX, X86::EDX, X86::ESP,
2216 };
2217
2218 // GR32_TC Bit set.
2219 const uint8_t GR32_TCBits[] = {
2220 0x00, 0x00, 0x40, 0x0a, 0x02,
2221 };
2222
2223 // GR32_ABCD_and_GR32_TC Register Class...
2224 const MCPhysReg GR32_ABCD_and_GR32_TC[] = {
2225 X86::EAX, X86::ECX, X86::EDX,
2226 };
2227
2228 // GR32_ABCD_and_GR32_TC Bit set.
2229 const uint8_t GR32_ABCD_and_GR32_TCBits[] = {
2230 0x00, 0x00, 0x40, 0x0a,
2231 };
2232
2233 // GR32_AD Register Class...
2234 const MCPhysReg GR32_AD[] = {
2235 X86::EAX, X86::EDX,
2236 };
2237
2238 // GR32_AD Bit set.
2239 const uint8_t GR32_ADBits[] = {
2240 0x00, 0x00, 0x40, 0x08,
2241 };
2242
2243 // GR32_ArgRef Register Class...
2244 const MCPhysReg GR32_ArgRef[] = {
2245 X86::ECX, X86::EDX,
2246 };
2247
2248 // GR32_ArgRef Bit set.
2249 const uint8_t GR32_ArgRefBits[] = {
2250 0x00, 0x00, 0x00, 0x0a,
2251 };
2252
2253 // GR32_BPSP Register Class...
2254 const MCPhysReg GR32_BPSP[] = {
2255 X86::EBP, X86::ESP,
2256 };
2257
2258 // GR32_BPSP Bit set.
2259 const uint8_t GR32_BPSPBits[] = {
2260 0x00, 0x00, 0x80, 0x00, 0x02,
2261 };
2262
2263 // GR32_BSI Register Class...
2264 const MCPhysReg GR32_BSI[] = {
2265 X86::EBX, X86::ESI,
2266 };
2267
2268 // GR32_BSI Bit set.
2269 const uint8_t GR32_BSIBits[] = {
2270 0x00, 0x00, 0x00, 0x01, 0x01,
2271 };
2272
2273 // GR32_CB Register Class...
2274 const MCPhysReg GR32_CB[] = {
2275 X86::ECX, X86::EBX,
2276 };
2277
2278 // GR32_CB Bit set.
2279 const uint8_t GR32_CBBits[] = {
2280 0x00, 0x00, 0x00, 0x03,
2281 };
2282
2283 // GR32_DC Register Class...
2284 const MCPhysReg GR32_DC[] = {
2285 X86::EDX, X86::ECX,
2286 };
2287
2288 // GR32_DC Bit set.
2289 const uint8_t GR32_DCBits[] = {
2290 0x00, 0x00, 0x00, 0x0a,
2291 };
2292
2293 // GR32_DIBP Register Class...
2294 const MCPhysReg GR32_DIBP[] = {
2295 X86::EDI, X86::EBP,
2296 };
2297
2298 // GR32_DIBP Bit set.
2299 const uint8_t GR32_DIBPBits[] = {
2300 0x00, 0x00, 0x80, 0x04,
2301 };
2302
2303 // GR32_SIDI Register Class...
2304 const MCPhysReg GR32_SIDI[] = {
2305 X86::ESI, X86::EDI,
2306 };
2307
2308 // GR32_SIDI Bit set.
2309 const uint8_t GR32_SIDIBits[] = {
2310 0x00, 0x00, 0x00, 0x04, 0x01,
2311 };
2312
2313 // LOW32_ADDR_ACCESS_RBP_with_sub_32bit Register Class...
2314 const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_32bit[] = {
2315 X86::RIP, X86::RBP,
2316 };
2317
2318 // LOW32_ADDR_ACCESS_RBP_with_sub_32bit Bit set.
2319 const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_32bitBits[] = {
2320 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x04,
2321 };
2322
2323 // CCR Register Class...
2324 const MCPhysReg CCR[] = {
2325 X86::EFLAGS,
2326 };
2327
2328 // CCR Bit set.
2329 const uint8_t CCRBits[] = {
2330 0x00, 0x00, 0x00, 0x10,
2331 };
2332
2333 // DFCCR Register Class...
2334 const MCPhysReg DFCCR[] = {
2335 X86::DF,
2336 };
2337
2338 // DFCCR Bit set.
2339 const uint8_t DFCCRBits[] = {
2340 0x00, 0x40,
2341 };
2342
2343 // GR32_ABCD_and_GR32_BSI Register Class...
2344 const MCPhysReg GR32_ABCD_and_GR32_BSI[] = {
2345 X86::EBX,
2346 };
2347
2348 // GR32_ABCD_and_GR32_BSI Bit set.
2349 const uint8_t GR32_ABCD_and_GR32_BSIBits[] = {
2350 0x00, 0x00, 0x00, 0x01,
2351 };
2352
2353 // GR32_AD_and_GR32_ArgRef Register Class...
2354 const MCPhysReg GR32_AD_and_GR32_ArgRef[] = {
2355 X86::EDX,
2356 };
2357
2358 // GR32_AD_and_GR32_ArgRef Bit set.
2359 const uint8_t GR32_AD_and_GR32_ArgRefBits[] = {
2360 0x00, 0x00, 0x00, 0x08,
2361 };
2362
2363 // GR32_ArgRef_and_GR32_CB Register Class...
2364 const MCPhysReg GR32_ArgRef_and_GR32_CB[] = {
2365 X86::ECX,
2366 };
2367
2368 // GR32_ArgRef_and_GR32_CB Bit set.
2369 const uint8_t GR32_ArgRef_and_GR32_CBBits[] = {
2370 0x00, 0x00, 0x00, 0x02,
2371 };
2372
2373 // GR32_BPSP_and_GR32_DIBP Register Class...
2374 const MCPhysReg GR32_BPSP_and_GR32_DIBP[] = {
2375 X86::EBP,
2376 };
2377
2378 // GR32_BPSP_and_GR32_DIBP Bit set.
2379 const uint8_t GR32_BPSP_and_GR32_DIBPBits[] = {
2380 0x00, 0x00, 0x80,
2381 };
2382
2383 // GR32_BPSP_and_GR32_TC Register Class...
2384 const MCPhysReg GR32_BPSP_and_GR32_TC[] = {
2385 X86::ESP,
2386 };
2387
2388 // GR32_BPSP_and_GR32_TC Bit set.
2389 const uint8_t GR32_BPSP_and_GR32_TCBits[] = {
2390 0x00, 0x00, 0x00, 0x00, 0x02,
2391 };
2392
2393 // GR32_BSI_and_GR32_SIDI Register Class...
2394 const MCPhysReg GR32_BSI_and_GR32_SIDI[] = {
2395 X86::ESI,
2396 };
2397
2398 // GR32_BSI_and_GR32_SIDI Bit set.
2399 const uint8_t GR32_BSI_and_GR32_SIDIBits[] = {
2400 0x00, 0x00, 0x00, 0x00, 0x01,
2401 };
2402
2403 // GR32_DIBP_and_GR32_SIDI Register Class...
2404 const MCPhysReg GR32_DIBP_and_GR32_SIDI[] = {
2405 X86::EDI,
2406 };
2407
2408 // GR32_DIBP_and_GR32_SIDI Bit set.
2409 const uint8_t GR32_DIBP_and_GR32_SIDIBits[] = {
2410 0x00, 0x00, 0x00, 0x04,
2411 };
2412
2413 // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit Register Class...
2414 const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit[] = {
2415 X86::RBP,
2416 };
2417
2418 // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit Bit set.
2419 const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitBits[] = {
2420 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
2421 };
2422
2423 // LOW32_ADDR_ACCESS_with_sub_32bit Register Class...
2424 const MCPhysReg LOW32_ADDR_ACCESS_with_sub_32bit[] = {
2425 X86::RIP,
2426 };
2427
2428 // LOW32_ADDR_ACCESS_with_sub_32bit Bit set.
2429 const uint8_t LOW32_ADDR_ACCESS_with_sub_32bitBits[] = {
2430 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
2431 };
2432
2433 // RFP64 Register Class...
2434 const MCPhysReg RFP64[] = {
2435 X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6,
2436 };
2437
2438 // RFP64 Bit set.
2439 const uint8_t RFP64Bits[] = {
2440 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f,
2441 };
2442
2443 // GR64 Register Class...
2444 const MCPhysReg GR64[] = {
2445 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R16, X86::R17, X86::R18, X86::R19, X86::R22, X86::R23, X86::R24, X86::R25, X86::R26, X86::R27, X86::R30, X86::R31, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::R20, X86::R21, X86::R28, X86::R29, X86::RBP, X86::RSP, X86::RIP,
2446 };
2447
2448 // GR64 Bit set.
2449 const uint8_t GR64Bits[] = {
2450 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
2451 };
2452
2453 // FR64X Register Class...
2454 const MCPhysReg FR64X[] = {
2455 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31,
2456 };
2457
2458 // FR64X Bit set.
2459 const uint8_t FR64XBits[] = {
2460 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
2461 };
2462
2463 // GR64_with_sub_8bit Register Class...
2464 const MCPhysReg GR64_with_sub_8bit[] = {
2465 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R16, X86::R17, X86::R18, X86::R19, X86::R22, X86::R23, X86::R24, X86::R25, X86::R26, X86::R27, X86::R30, X86::R31, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::R20, X86::R21, X86::R28, X86::R29, X86::RBP, X86::RSP,
2466 };
2467
2468 // GR64_with_sub_8bit Bit set.
2469 const uint8_t GR64_with_sub_8bitBits[] = {
2470 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x31, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
2471 };
2472
2473 // GR64_NOSP Register Class...
2474 const MCPhysReg GR64_NOSP[] = {
2475 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R16, X86::R17, X86::R18, X86::R19, X86::R22, X86::R23, X86::R24, X86::R25, X86::R26, X86::R27, X86::R30, X86::R31, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::R20, X86::R21, X86::R28, X86::R29, X86::RBP,
2476 };
2477
2478 // GR64_NOSP Bit set.
2479 const uint8_t GR64_NOSPBits[] = {
2480 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
2481 };
2482
2483 // GR64_NOREX2 Register Class...
2484 const MCPhysReg GR64_NOREX2[] = {
2485 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP, X86::RSP, X86::RIP,
2486 };
2487
2488 // GR64_NOREX2 Bit set.
2489 const uint8_t GR64_NOREX2Bits[] = {
2490 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
2491 };
2492
2493 // CONTROL_REG Register Class...
2494 const MCPhysReg CONTROL_REG[] = {
2495 X86::CR0, X86::CR1, X86::CR2, X86::CR3, X86::CR4, X86::CR5, X86::CR6, X86::CR7, X86::CR8, X86::CR9, X86::CR10, X86::CR11, X86::CR12, X86::CR13, X86::CR14, X86::CR15,
2496 };
2497
2498 // CONTROL_REG Bit set.
2499 const uint8_t CONTROL_REGBits[] = {
2500 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
2501 };
2502
2503 // FR64 Register Class...
2504 const MCPhysReg FR64[] = {
2505 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15,
2506 };
2507
2508 // FR64 Bit set.
2509 const uint8_t FR64Bits[] = {
2510 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
2511 };
2512
2513 // GR64_with_sub_16bit_in_GR16_NOREX2 Register Class...
2514 const MCPhysReg GR64_with_sub_16bit_in_GR16_NOREX2[] = {
2515 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP, X86::RSP,
2516 };
2517
2518 // GR64_with_sub_16bit_in_GR16_NOREX2 Bit set.
2519 const uint8_t GR64_with_sub_16bit_in_GR16_NOREX2Bits[] = {
2520 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x31, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
2521 };
2522
2523 // GR64_NOREX2_NOSP Register Class...
2524 const MCPhysReg GR64_NOREX2_NOSP[] = {
2525 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP,
2526 };
2527
2528 // GR64_NOREX2_NOSP Bit set.
2529 const uint8_t GR64_NOREX2_NOSPBits[] = {
2530 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
2531 };
2532
2533 // GR64PLTSafe Register Class...
2534 const MCPhysReg GR64PLTSafe[] = {
2535 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP,
2536 };
2537
2538 // GR64PLTSafe Bit set.
2539 const uint8_t GR64PLTSafeBits[] = {
2540 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x79,
2541 };
2542
2543 // GR64_TC Register Class...
2544 const MCPhysReg GR64_TC[] = {
2545 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R11, X86::RIP, X86::RSP,
2546 };
2547
2548 // GR64_TC Bit set.
2549 const uint8_t GR64_TCBits[] = {
2550 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x05,
2551 };
2552
2553 // GR64_NOREX Register Class...
2554 const MCPhysReg GR64_NOREX[] = {
2555 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP, X86::RSP, X86::RIP,
2556 };
2557
2558 // GR64_NOREX Bit set.
2559 const uint8_t GR64_NOREXBits[] = {
2560 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x35,
2561 };
2562
2563 // GR64_TCW64 Register Class...
2564 const MCPhysReg GR64_TCW64[] = {
2565 X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R10, X86::R11, X86::RIP, X86::RSP,
2566 };
2567
2568 // GR64_TCW64 Bit set.
2569 const uint8_t GR64_TCW64Bits[] = {
2570 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x25, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07,
2571 };
2572
2573 // GR64_TC_with_sub_8bit Register Class...
2574 const MCPhysReg GR64_TC_with_sub_8bit[] = {
2575 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R11, X86::RSP,
2576 };
2577
2578 // GR64_TC_with_sub_8bit Bit set.
2579 const uint8_t GR64_TC_with_sub_8bitBits[] = {
2580 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x31, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x05,
2581 };
2582
2583 // GR64_NOREX2_NOSP_and_GR64_TC Register Class...
2584 const MCPhysReg GR64_NOREX2_NOSP_and_GR64_TC[] = {
2585 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R11,
2586 };
2587
2588 // GR64_NOREX2_NOSP_and_GR64_TC Bit set.
2589 const uint8_t GR64_NOREX2_NOSP_and_GR64_TCBits[] = {
2590 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x05,
2591 };
2592
2593 // GR64_TCW64_with_sub_8bit Register Class...
2594 const MCPhysReg GR64_TCW64_with_sub_8bit[] = {
2595 X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R10, X86::R11, X86::RSP,
2596 };
2597
2598 // GR64_TCW64_with_sub_8bit Bit set.
2599 const uint8_t GR64_TCW64_with_sub_8bitBits[] = {
2600 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07,
2601 };
2602
2603 // GR64_TC_and_GR64_TCW64 Register Class...
2604 const MCPhysReg GR64_TC_and_GR64_TCW64[] = {
2605 X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R11, X86::RIP, X86::RSP,
2606 };
2607
2608 // GR64_TC_and_GR64_TCW64 Bit set.
2609 const uint8_t GR64_TC_and_GR64_TCW64Bits[] = {
2610 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x25, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x05,
2611 };
2612
2613 // GR64_with_sub_16bit_in_GR16_NOREX Register Class...
2614 const MCPhysReg GR64_with_sub_16bit_in_GR16_NOREX[] = {
2615 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP, X86::RSP,
2616 };
2617
2618 // GR64_with_sub_16bit_in_GR16_NOREX Bit set.
2619 const uint8_t GR64_with_sub_16bit_in_GR16_NOREXBits[] = {
2620 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x31,
2621 };
2622
2623 // VK64 Register Class...
2624 const MCPhysReg VK64[] = {
2625 X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
2626 };
2627
2628 // VK64 Bit set.
2629 const uint8_t VK64Bits[] = {
2630 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
2631 };
2632
2633 // VR64 Register Class...
2634 const MCPhysReg VR64[] = {
2635 X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7,
2636 };
2637
2638 // VR64 Bit set.
2639 const uint8_t VR64Bits[] = {
2640 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
2641 };
2642
2643 // GR64PLTSafe_and_GR64_TC Register Class...
2644 const MCPhysReg GR64PLTSafe_and_GR64_TC[] = {
2645 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9,
2646 };
2647
2648 // GR64PLTSafe_and_GR64_TC Bit set.
2649 const uint8_t GR64PLTSafe_and_GR64_TCBits[] = {
2650 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01,
2651 };
2652
2653 // GR64_NOREX2_NOSP_and_GR64_TCW64 Register Class...
2654 const MCPhysReg GR64_NOREX2_NOSP_and_GR64_TCW64[] = {
2655 X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R10, X86::R11,
2656 };
2657
2658 // GR64_NOREX2_NOSP_and_GR64_TCW64 Bit set.
2659 const uint8_t GR64_NOREX2_NOSP_and_GR64_TCW64Bits[] = {
2660 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07,
2661 };
2662
2663 // GR64_NOREX_NOSP Register Class...
2664 const MCPhysReg GR64_NOREX_NOSP[] = {
2665 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP,
2666 };
2667
2668 // GR64_NOREX_NOSP Bit set.
2669 const uint8_t GR64_NOREX_NOSPBits[] = {
2670 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x11,
2671 };
2672
2673 // GR64_NOREX_and_GR64_TC Register Class...
2674 const MCPhysReg GR64_NOREX_and_GR64_TC[] = {
2675 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RSP, X86::RIP,
2676 };
2677
2678 // GR64_NOREX_and_GR64_TC Bit set.
2679 const uint8_t GR64_NOREX_and_GR64_TCBits[] = {
2680 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x35,
2681 };
2682
2683 // GR64_TCW64_and_GR64_TC_with_sub_8bit Register Class...
2684 const MCPhysReg GR64_TCW64_and_GR64_TC_with_sub_8bit[] = {
2685 X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R11, X86::RSP,
2686 };
2687
2688 // GR64_TCW64_and_GR64_TC_with_sub_8bit Bit set.
2689 const uint8_t GR64_TCW64_and_GR64_TC_with_sub_8bitBits[] = {
2690 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x05,
2691 };
2692
2693 // VK64WM Register Class...
2694 const MCPhysReg VK64WM[] = {
2695 X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
2696 };
2697
2698 // VK64WM Bit set.
2699 const uint8_t VK64WMBits[] = {
2700 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f,
2701 };
2702
2703 // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64 Register Class...
2704 const MCPhysReg GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64[] = {
2705 X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R11,
2706 };
2707
2708 // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64 Bit set.
2709 const uint8_t GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64Bits[] = {
2710 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x05,
2711 };
2712
2713 // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX Register Class...
2714 const MCPhysReg GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX[] = {
2715 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RSP,
2716 };
2717
2718 // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX Bit set.
2719 const uint8_t GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXBits[] = {
2720 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x31,
2721 };
2722
2723 // GR64PLTSafe_and_GR64_TCW64 Register Class...
2724 const MCPhysReg GR64PLTSafe_and_GR64_TCW64[] = {
2725 X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9,
2726 };
2727
2728 // GR64PLTSafe_and_GR64_TCW64 Bit set.
2729 const uint8_t GR64PLTSafe_and_GR64_TCW64Bits[] = {
2730 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01,
2731 };
2732
2733 // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC Register Class...
2734 const MCPhysReg GR64_NOREX_and_GR64PLTSafe_and_GR64_TC[] = {
2735 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI,
2736 };
2737
2738 // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC Bit set.
2739 const uint8_t GR64_NOREX_and_GR64PLTSafe_and_GR64_TCBits[] = {
2740 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x11,
2741 };
2742
2743 // GR64_NOREX_and_GR64_TCW64 Register Class...
2744 const MCPhysReg GR64_NOREX_and_GR64_TCW64[] = {
2745 X86::RAX, X86::RCX, X86::RDX, X86::RSP, X86::RIP,
2746 };
2747
2748 // GR64_NOREX_and_GR64_TCW64 Bit set.
2749 const uint8_t GR64_NOREX_and_GR64_TCW64Bits[] = {
2750 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x25,
2751 };
2752
2753 // GR64_ABCD Register Class...
2754 const MCPhysReg GR64_ABCD[] = {
2755 X86::RAX, X86::RCX, X86::RDX, X86::RBX,
2756 };
2757
2758 // GR64_ABCD Bit set.
2759 const uint8_t GR64_ABCDBits[] = {
2760 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x68, 0x01,
2761 };
2762
2763 // GR64_with_sub_32bit_in_GR32_TC Register Class...
2764 const MCPhysReg GR64_with_sub_32bit_in_GR32_TC[] = {
2765 X86::RAX, X86::RCX, X86::RDX, X86::RSP,
2766 };
2767
2768 // GR64_with_sub_32bit_in_GR32_TC Bit set.
2769 const uint8_t GR64_with_sub_32bit_in_GR32_TCBits[] = {
2770 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x21,
2771 };
2772
2773 // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC Register Class...
2774 const MCPhysReg GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC[] = {
2775 X86::RAX, X86::RCX, X86::RDX,
2776 };
2777
2778 // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC Bit set.
2779 const uint8_t GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCBits[] = {
2780 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x01,
2781 };
2782
2783 // GR64_AD Register Class...
2784 const MCPhysReg GR64_AD[] = {
2785 X86::RAX, X86::RDX,
2786 };
2787
2788 // GR64_AD Bit set.
2789 const uint8_t GR64_ADBits[] = {
2790 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x01,
2791 };
2792
2793 // GR64_ArgRef Register Class...
2794 const MCPhysReg GR64_ArgRef[] = {
2795 X86::R10, X86::R11,
2796 };
2797
2798 // GR64_ArgRef Bit set.
2799 const uint8_t GR64_ArgRefBits[] = {
2800 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06,
2801 };
2802
2803 // GR64_and_LOW32_ADDR_ACCESS_RBP Register Class...
2804 const MCPhysReg GR64_and_LOW32_ADDR_ACCESS_RBP[] = {
2805 X86::RBP, X86::RIP,
2806 };
2807
2808 // GR64_and_LOW32_ADDR_ACCESS_RBP Bit set.
2809 const uint8_t GR64_and_LOW32_ADDR_ACCESS_RBPBits[] = {
2810 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x04,
2811 };
2812
2813 // GR64_with_sub_32bit_in_GR32_ArgRef Register Class...
2814 const MCPhysReg GR64_with_sub_32bit_in_GR32_ArgRef[] = {
2815 X86::RCX, X86::RDX,
2816 };
2817
2818 // GR64_with_sub_32bit_in_GR32_ArgRef Bit set.
2819 const uint8_t GR64_with_sub_32bit_in_GR32_ArgRefBits[] = {
2820 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x01,
2821 };
2822
2823 // GR64_with_sub_32bit_in_GR32_BPSP Register Class...
2824 const MCPhysReg GR64_with_sub_32bit_in_GR32_BPSP[] = {
2825 X86::RBP, X86::RSP,
2826 };
2827
2828 // GR64_with_sub_32bit_in_GR32_BPSP Bit set.
2829 const uint8_t GR64_with_sub_32bit_in_GR32_BPSPBits[] = {
2830 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x20,
2831 };
2832
2833 // GR64_with_sub_32bit_in_GR32_BSI Register Class...
2834 const MCPhysReg GR64_with_sub_32bit_in_GR32_BSI[] = {
2835 X86::RSI, X86::RBX,
2836 };
2837
2838 // GR64_with_sub_32bit_in_GR32_BSI Bit set.
2839 const uint8_t GR64_with_sub_32bit_in_GR32_BSIBits[] = {
2840 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x10,
2841 };
2842
2843 // GR64_with_sub_32bit_in_GR32_CB Register Class...
2844 const MCPhysReg GR64_with_sub_32bit_in_GR32_CB[] = {
2845 X86::RCX, X86::RBX,
2846 };
2847
2848 // GR64_with_sub_32bit_in_GR32_CB Bit set.
2849 const uint8_t GR64_with_sub_32bit_in_GR32_CBBits[] = {
2850 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60,
2851 };
2852
2853 // GR64_with_sub_32bit_in_GR32_DIBP Register Class...
2854 const MCPhysReg GR64_with_sub_32bit_in_GR32_DIBP[] = {
2855 X86::RDI, X86::RBP,
2856 };
2857
2858 // GR64_with_sub_32bit_in_GR32_DIBP Bit set.
2859 const uint8_t GR64_with_sub_32bit_in_GR32_DIBPBits[] = {
2860 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x90,
2861 };
2862
2863 // GR64_with_sub_32bit_in_GR32_SIDI Register Class...
2864 const MCPhysReg GR64_with_sub_32bit_in_GR32_SIDI[] = {
2865 X86::RSI, X86::RDI,
2866 };
2867
2868 // GR64_with_sub_32bit_in_GR32_SIDI Bit set.
2869 const uint8_t GR64_with_sub_32bit_in_GR32_SIDIBits[] = {
2870 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x10,
2871 };
2872
2873 // GR64_A Register Class...
2874 const MCPhysReg GR64_A[] = {
2875 X86::RAX,
2876 };
2877
2878 // GR64_A Bit set.
2879 const uint8_t GR64_ABits[] = {
2880 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
2881 };
2882
2883 // GR64_ArgRef_and_GR64_TC Register Class...
2884 const MCPhysReg GR64_ArgRef_and_GR64_TC[] = {
2885 X86::R11,
2886 };
2887
2888 // GR64_ArgRef_and_GR64_TC Bit set.
2889 const uint8_t GR64_ArgRef_and_GR64_TCBits[] = {
2890 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
2891 };
2892
2893 // GR64_and_LOW32_ADDR_ACCESS Register Class...
2894 const MCPhysReg GR64_and_LOW32_ADDR_ACCESS[] = {
2895 X86::RIP,
2896 };
2897
2898 // GR64_and_LOW32_ADDR_ACCESS Bit set.
2899 const uint8_t GR64_and_LOW32_ADDR_ACCESSBits[] = {
2900 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
2901 };
2902
2903 // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI Register Class...
2904 const MCPhysReg GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI[] = {
2905 X86::RBX,
2906 };
2907
2908 // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI Bit set.
2909 const uint8_t GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIBits[] = {
2910 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
2911 };
2912
2913 // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef Register Class...
2914 const MCPhysReg GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef[] = {
2915 X86::RDX,
2916 };
2917
2918 // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef Bit set.
2919 const uint8_t GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefBits[] = {
2920 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
2921 };
2922
2923 // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB Register Class...
2924 const MCPhysReg GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB[] = {
2925 X86::RCX,
2926 };
2927
2928 // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB Bit set.
2929 const uint8_t GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBBits[] = {
2930 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
2931 };
2932
2933 // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP Register Class...
2934 const MCPhysReg GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP[] = {
2935 X86::RBP,
2936 };
2937
2938 // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP Bit set.
2939 const uint8_t GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPBits[] = {
2940 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
2941 };
2942
2943 // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC Register Class...
2944 const MCPhysReg GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC[] = {
2945 X86::RSP,
2946 };
2947
2948 // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC Bit set.
2949 const uint8_t GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCBits[] = {
2950 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
2951 };
2952
2953 // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI Register Class...
2954 const MCPhysReg GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI[] = {
2955 X86::RSI,
2956 };
2957
2958 // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI Bit set.
2959 const uint8_t GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIBits[] = {
2960 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
2961 };
2962
2963 // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI Register Class...
2964 const MCPhysReg GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI[] = {
2965 X86::RDI,
2966 };
2967
2968 // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI Bit set.
2969 const uint8_t GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIBits[] = {
2970 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
2971 };
2972
2973 // RST Register Class...
2974 const MCPhysReg RST[] = {
2975 X86::ST0, X86::ST1, X86::ST2, X86::ST3, X86::ST4, X86::ST5, X86::ST6, X86::ST7,
2976 };
2977
2978 // RST Bit set.
2979 const uint8_t RSTBits[] = {
2980 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
2981 };
2982
2983 // RFP80 Register Class...
2984 const MCPhysReg RFP80[] = {
2985 X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6,
2986 };
2987
2988 // RFP80 Bit set.
2989 const uint8_t RFP80Bits[] = {
2990 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f,
2991 };
2992
2993 // RFP80_7 Register Class...
2994 const MCPhysReg RFP80_7[] = {
2995 X86::FP7,
2996 };
2997
2998 // RFP80_7 Bit set.
2999 const uint8_t RFP80_7Bits[] = {
3000 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
3001 };
3002
3003 // VR128X Register Class...
3004 const MCPhysReg VR128X[] = {
3005 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31,
3006 };
3007
3008 // VR128X Bit set.
3009 const uint8_t VR128XBits[] = {
3010 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
3011 };
3012
3013 // VR128 Register Class...
3014 const MCPhysReg VR128[] = {
3015 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15,
3016 };
3017
3018 // VR128 Bit set.
3019 const uint8_t VR128Bits[] = {
3020 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
3021 };
3022
3023 // VR256X Register Class...
3024 const MCPhysReg VR256X[] = {
3025 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, X86::YMM16, X86::YMM17, X86::YMM18, X86::YMM19, X86::YMM20, X86::YMM21, X86::YMM22, X86::YMM23, X86::YMM24, X86::YMM25, X86::YMM26, X86::YMM27, X86::YMM28, X86::YMM29, X86::YMM30, X86::YMM31,
3026 };
3027
3028 // VR256X Bit set.
3029 const uint8_t VR256XBits[] = {
3030 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 0x00, 0x00, 0x80, 0xff, 0x7f,
3031 };
3032
3033 // VR256 Register Class...
3034 const MCPhysReg VR256[] = {
3035 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15,
3036 };
3037
3038 // VR256 Bit set.
3039 const uint8_t VR256Bits[] = {
3040 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
3041 };
3042
3043 // VR512 Register Class...
3044 const MCPhysReg VR512[] = {
3045 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM16, X86::ZMM17, X86::ZMM18, X86::ZMM19, X86::ZMM20, X86::ZMM21, X86::ZMM22, X86::ZMM23, X86::ZMM24, X86::ZMM25, X86::ZMM26, X86::ZMM27, X86::ZMM28, X86::ZMM29, X86::ZMM30, X86::ZMM31,
3046 };
3047
3048 // VR512 Bit set.
3049 const uint8_t VR512Bits[] = {
3050 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f,
3051 };
3052
3053 // VR512_0_15 Register Class...
3054 const MCPhysReg VR512_0_15[] = {
3055 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15,
3056 };
3057
3058 // VR512_0_15 Bit set.
3059 const uint8_t VR512_0_15Bits[] = {
3060 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
3061 };
3062
3063 // TILE Register Class...
3064 const MCPhysReg TILE[] = {
3065 X86::TMM0, X86::TMM1, X86::TMM2, X86::TMM3, X86::TMM4, X86::TMM5, X86::TMM6, X86::TMM7,
3066 };
3067
3068 // TILE Bit set.
3069 const uint8_t TILEBits[] = {
3070 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f,
3071 };
3072
3073 // TILEPAIR Register Class...
3074 const MCPhysReg TILEPAIR[] = {
3075 X86::TMM0_TMM1, X86::TMM2_TMM3, X86::TMM4_TMM5, X86::TMM6_TMM7,
3076 };
3077
3078 // TILEPAIR Bit set.
3079 const uint8_t TILEPAIRBits[] = {
3080 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0,
3081 };
3082
3083} // end anonymous namespace
3084
3085
3086#ifdef __GNUC__
3087#pragma GCC diagnostic push
3088#pragma GCC diagnostic ignored "-Woverlength-strings"
3089#endif
3090extern const char X86RegClassStrings[] = {
3091 /* 0 */ "RFP80\000"
3092 /* 6 */ "VK1\000"
3093 /* 10 */ "VR512\000"
3094 /* 16 */ "VK32\000"
3095 /* 21 */ "RFP32\000"
3096 /* 27 */ "FR32\000"
3097 /* 32 */ "GR32\000"
3098 /* 37 */ "VK2\000"
3099 /* 41 */ "GR32_NOREX2\000"
3100 /* 53 */ "GR64_NOREX2\000"
3101 /* 65 */ "GR64_with_sub_16bit_in_GR16_NOREX2\000"
3102 /* 100 */ "LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2\000"
3103 /* 152 */ "GR8_NOREX2\000"
3104 /* 163 */ "VK64\000"
3105 /* 168 */ "RFP64\000"
3106 /* 174 */ "FR64\000"
3107 /* 179 */ "GR64\000"
3108 /* 184 */ "VR64\000"
3109 /* 189 */ "GR64_TC_and_GR64_TCW64\000"
3110 /* 212 */ "GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64\000"
3111 /* 256 */ "GR64_NOREX_and_GR64_TCW64\000"
3112 /* 282 */ "GR64PLTSafe_and_GR64_TCW64\000"
3113 /* 309 */ "VK4\000"
3114 /* 313 */ "VR512_0_15\000"
3115 /* 324 */ "GRH16\000"
3116 /* 330 */ "VK16\000"
3117 /* 335 */ "FR16\000"
3118 /* 340 */ "GR16\000"
3119 /* 345 */ "VR256\000"
3120 /* 351 */ "RFP80_7\000"
3121 /* 359 */ "VR128\000"
3122 /* 365 */ "GRH8\000"
3123 /* 370 */ "VK8\000"
3124 /* 374 */ "GR8\000"
3125 /* 378 */ "GR64_A\000"
3126 /* 385 */ "GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB\000"
3127 /* 432 */ "GR64_with_sub_32bit_in_GR32_CB\000"
3128 /* 463 */ "GR32_DC\000"
3129 /* 471 */ "GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC\000"
3130 /* 516 */ "GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC\000"
3131 /* 561 */ "GR64_with_sub_32bit_in_GR32_TC\000"
3132 /* 592 */ "GR64_NOREX2_NOSP_and_GR64_TC\000"
3133 /* 621 */ "GR64_NOREX_and_GR64_TC\000"
3134 /* 644 */ "GR64_NOREX_and_GR64PLTSafe_and_GR64_TC\000"
3135 /* 683 */ "GR64_ArgRef_and_GR64_TC\000"
3136 /* 707 */ "GR32_AD\000"
3137 /* 715 */ "GR64_AD\000"
3138 /* 723 */ "GR32_ABCD\000"
3139 /* 733 */ "GR64_ABCD\000"
3140 /* 743 */ "GR16_ABCD\000"
3141 /* 753 */ "TILE\000"
3142 /* 758 */ "DEBUG_REG\000"
3143 /* 768 */ "CONTROL_REG\000"
3144 /* 780 */ "SEGMENT_REG\000"
3145 /* 792 */ "GR8_ABCD_H\000"
3146 /* 803 */ "GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI\000"
3147 /* 849 */ "GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI\000"
3148 /* 896 */ "GR64_with_sub_32bit_in_GR32_SIDI\000"
3149 /* 929 */ "GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI\000"
3150 /* 975 */ "GR64_with_sub_32bit_in_GR32_BSI\000"
3151 /* 1007 */ "GR8_ABCD_L\000"
3152 /* 1018 */ "VK1PAIR_with_sub_mask_0_in_VK1WM\000"
3153 /* 1051 */ "VK32WM\000"
3154 /* 1058 */ "VK2WM\000"
3155 /* 1064 */ "VK64WM\000"
3156 /* 1071 */ "VK4WM\000"
3157 /* 1077 */ "VK16WM\000"
3158 /* 1084 */ "VK8WM\000"
3159 /* 1090 */ "GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP\000"
3160 /* 1137 */ "GR64_with_sub_32bit_in_GR32_DIBP\000"
3161 /* 1170 */ "GR64_and_LOW32_ADDR_ACCESS_RBP\000"
3162 /* 1201 */ "GR32_NOSP\000"
3163 /* 1211 */ "GR32_NOREX2_NOSP\000"
3164 /* 1228 */ "GR64_NOREX2_NOSP\000"
3165 /* 1245 */ "GR64_NOSP\000"
3166 /* 1255 */ "GR32_NOREX_NOSP\000"
3167 /* 1271 */ "GR64_NOREX_NOSP\000"
3168 /* 1287 */ "GR64_with_sub_32bit_in_GR32_BPSP\000"
3169 /* 1320 */ "DFCCR\000"
3170 /* 1326 */ "FPCCR\000"
3171 /* 1332 */ "VK1PAIR\000"
3172 /* 1340 */ "VK2PAIR\000"
3173 /* 1348 */ "VK4PAIR\000"
3174 /* 1356 */ "VK16PAIR\000"
3175 /* 1365 */ "VK8PAIR\000"
3176 /* 1373 */ "TILEPAIR\000"
3177 /* 1382 */ "GR64_and_LOW32_ADDR_ACCESS\000"
3178 /* 1409 */ "RST\000"
3179 /* 1413 */ "FR32X\000"
3180 /* 1419 */ "FR64X\000"
3181 /* 1425 */ "FR16X\000"
3182 /* 1431 */ "VR256X\000"
3183 /* 1438 */ "VR128X\000"
3184 /* 1445 */ "GR32_NOREX\000"
3185 /* 1456 */ "GR64_NOREX\000"
3186 /* 1467 */ "GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX\000"
3187 /* 1513 */ "LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX\000"
3188 /* 1564 */ "GR8_NOREX\000"
3189 /* 1574 */ "GR64PLTSafe\000"
3190 /* 1586 */ "GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef\000"
3191 /* 1633 */ "GR64_with_sub_32bit_in_GR32_ArgRef\000"
3192 /* 1668 */ "GR64_ArgRef\000"
3193 /* 1680 */ "LOW32_ADDR_ACCESS_RBP_with_sub_32bit\000"
3194 /* 1717 */ "LOW32_ADDR_ACCESS_with_sub_32bit\000"
3195 /* 1750 */ "LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit\000"
3196 /* 1801 */ "GR64_with_sub_8bit\000"
3197 /* 1820 */ "GR64_TCW64_with_sub_8bit\000"
3198 /* 1845 */ "GR64_TCW64_and_GR64_TC_with_sub_8bit\000"
3199 /* 1882 */ "LOW32_ADDR_ACCESS_RBP_with_sub_8bit\000"
3200};
3201#ifdef __GNUC__
3202#pragma GCC diagnostic pop
3203#endif
3204
3205extern const MCRegisterClass X86MCRegisterClasses[] = {
3206 { GR8, GR8Bits, 374, 36, sizeof(GR8Bits), X86::GR8RegClassID, 8, 1, true, false },
3207 { GRH8, GRH8Bits, 365, 28, sizeof(GRH8Bits), X86::GRH8RegClassID, 8, 1, false, false },
3208 { GR8_NOREX2, GR8_NOREX2Bits, 152, 20, sizeof(GR8_NOREX2Bits), X86::GR8_NOREX2RegClassID, 8, 1, true, false },
3209 { GR8_NOREX, GR8_NOREXBits, 1564, 8, sizeof(GR8_NOREXBits), X86::GR8_NOREXRegClassID, 8, 1, true, false },
3210 { GR8_ABCD_H, GR8_ABCD_HBits, 792, 4, sizeof(GR8_ABCD_HBits), X86::GR8_ABCD_HRegClassID, 8, 1, true, false },
3211 { GR8_ABCD_L, GR8_ABCD_LBits, 1007, 4, sizeof(GR8_ABCD_LBits), X86::GR8_ABCD_LRegClassID, 8, 1, true, false },
3212 { GRH16, GRH16Bits, 324, 33, sizeof(GRH16Bits), X86::GRH16RegClassID, 16, 1, false, false },
3213 { GR16, GR16Bits, 340, 32, sizeof(GR16Bits), X86::GR16RegClassID, 16, 1, true, false },
3214 { GR16_NOREX2, GR16_NOREX2Bits, 88, 16, sizeof(GR16_NOREX2Bits), X86::GR16_NOREX2RegClassID, 16, 1, true, false },
3215 { GR16_NOREX, GR16_NOREXBits, 1502, 8, sizeof(GR16_NOREXBits), X86::GR16_NOREXRegClassID, 16, 1, true, false },
3216 { VK1, VK1Bits, 6, 8, sizeof(VK1Bits), X86::VK1RegClassID, 16, 1, true, false },
3217 { VK16, VK16Bits, 330, 8, sizeof(VK16Bits), X86::VK16RegClassID, 16, 1, true, false },
3218 { VK2, VK2Bits, 37, 8, sizeof(VK2Bits), X86::VK2RegClassID, 16, 1, true, false },
3219 { VK4, VK4Bits, 309, 8, sizeof(VK4Bits), X86::VK4RegClassID, 16, 1, true, false },
3220 { VK8, VK8Bits, 370, 8, sizeof(VK8Bits), X86::VK8RegClassID, 16, 1, true, false },
3221 { VK16WM, VK16WMBits, 1077, 7, sizeof(VK16WMBits), X86::VK16WMRegClassID, 16, 1, true, false },
3222 { VK1WM, VK1WMBits, 1045, 7, sizeof(VK1WMBits), X86::VK1WMRegClassID, 16, 1, true, false },
3223 { VK2WM, VK2WMBits, 1058, 7, sizeof(VK2WMBits), X86::VK2WMRegClassID, 16, 1, true, false },
3224 { VK4WM, VK4WMBits, 1071, 7, sizeof(VK4WMBits), X86::VK4WMRegClassID, 16, 1, true, false },
3225 { VK8WM, VK8WMBits, 1084, 7, sizeof(VK8WMBits), X86::VK8WMRegClassID, 16, 1, true, false },
3226 { SEGMENT_REG, SEGMENT_REGBits, 780, 6, sizeof(SEGMENT_REGBits), X86::SEGMENT_REGRegClassID, 16, 1, true, false },
3227 { GR16_ABCD, GR16_ABCDBits, 743, 4, sizeof(GR16_ABCDBits), X86::GR16_ABCDRegClassID, 16, 1, true, false },
3228 { FPCCR, FPCCRBits, 1326, 1, sizeof(FPCCRBits), X86::FPCCRRegClassID, 16, -1, false, false },
3229 { FR16X, FR16XBits, 1425, 32, sizeof(FR16XBits), X86::FR16XRegClassID, 32, 1, true, false },
3230 { FR16, FR16Bits, 335, 16, sizeof(FR16Bits), X86::FR16RegClassID, 32, 1, true, false },
3231 { VK16PAIR, VK16PAIRBits, 1356, 4, sizeof(VK16PAIRBits), X86::VK16PAIRRegClassID, 32, 1, true, false },
3232 { VK1PAIR, VK1PAIRBits, 1332, 4, sizeof(VK1PAIRBits), X86::VK1PAIRRegClassID, 32, 1, true, false },
3233 { VK2PAIR, VK2PAIRBits, 1340, 4, sizeof(VK2PAIRBits), X86::VK2PAIRRegClassID, 32, 1, true, false },
3234 { VK4PAIR, VK4PAIRBits, 1348, 4, sizeof(VK4PAIRBits), X86::VK4PAIRRegClassID, 32, 1, true, false },
3235 { VK8PAIR, VK8PAIRBits, 1365, 4, sizeof(VK8PAIRBits), X86::VK8PAIRRegClassID, 32, 1, true, false },
3236 { VK1PAIR_with_sub_mask_0_in_VK1WM, VK1PAIR_with_sub_mask_0_in_VK1WMBits, 1018, 3, sizeof(VK1PAIR_with_sub_mask_0_in_VK1WMBits), X86::VK1PAIR_with_sub_mask_0_in_VK1WMRegClassID, 32, 1, true, false },
3237 { LOW32_ADDR_ACCESS_RBP, LOW32_ADDR_ACCESS_RBPBits, 1179, 34, sizeof(LOW32_ADDR_ACCESS_RBPBits), X86::LOW32_ADDR_ACCESS_RBPRegClassID, 32, 1, true, false },
3238 { LOW32_ADDR_ACCESS, LOW32_ADDR_ACCESSBits, 1391, 33, sizeof(LOW32_ADDR_ACCESSBits), X86::LOW32_ADDR_ACCESSRegClassID, 32, 1, true, false },
3239 { LOW32_ADDR_ACCESS_RBP_with_sub_8bit, LOW32_ADDR_ACCESS_RBP_with_sub_8bitBits, 1882, 33, sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_8bitBits), X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, 32, 1, true, false },
3240 { FR32X, FR32XBits, 1413, 32, sizeof(FR32XBits), X86::FR32XRegClassID, 32, 1, true, false },
3241 { GR32, GR32Bits, 32, 32, sizeof(GR32Bits), X86::GR32RegClassID, 32, 1, true, false },
3242 { GR32_NOSP, GR32_NOSPBits, 1201, 31, sizeof(GR32_NOSPBits), X86::GR32_NOSPRegClassID, 32, 1, true, false },
3243 { LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2, LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2Bits, 100, 17, sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2Bits), X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID, 32, 1, true, false },
3244 { DEBUG_REG, DEBUG_REGBits, 758, 16, sizeof(DEBUG_REGBits), X86::DEBUG_REGRegClassID, 32, 1, true, false },
3245 { FR32, FR32Bits, 27, 16, sizeof(FR32Bits), X86::FR32RegClassID, 32, 1, true, false },
3246 { GR32_NOREX2, GR32_NOREX2Bits, 41, 16, sizeof(GR32_NOREX2Bits), X86::GR32_NOREX2RegClassID, 32, 1, true, false },
3247 { GR32_NOREX2_NOSP, GR32_NOREX2_NOSPBits, 1211, 15, sizeof(GR32_NOREX2_NOSPBits), X86::GR32_NOREX2_NOSPRegClassID, 32, 1, true, false },
3248 { LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX, LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXBits, 1513, 9, sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXBits), X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID, 32, 1, true, false },
3249 { GR32_NOREX, GR32_NOREXBits, 1445, 8, sizeof(GR32_NOREXBits), X86::GR32_NOREXRegClassID, 32, 1, true, false },
3250 { VK32, VK32Bits, 16, 8, sizeof(VK32Bits), X86::VK32RegClassID, 32, 1, true, false },
3251 { GR32_NOREX_NOSP, GR32_NOREX_NOSPBits, 1255, 7, sizeof(GR32_NOREX_NOSPBits), X86::GR32_NOREX_NOSPRegClassID, 32, 1, true, false },
3252 { RFP32, RFP32Bits, 21, 7, sizeof(RFP32Bits), X86::RFP32RegClassID, 32, 1, true, false },
3253 { VK32WM, VK32WMBits, 1051, 7, sizeof(VK32WMBits), X86::VK32WMRegClassID, 32, 1, true, false },
3254 { GR32_ABCD, GR32_ABCDBits, 723, 4, sizeof(GR32_ABCDBits), X86::GR32_ABCDRegClassID, 32, 1, true, false },
3255 { GR32_TC, GR32_TCBits, 508, 4, sizeof(GR32_TCBits), X86::GR32_TCRegClassID, 32, 1, true, false },
3256 { GR32_ABCD_and_GR32_TC, GR32_ABCD_and_GR32_TCBits, 494, 3, sizeof(GR32_ABCD_and_GR32_TCBits), X86::GR32_ABCD_and_GR32_TCRegClassID, 32, 1, true, false },
3257 { GR32_AD, GR32_ADBits, 707, 2, sizeof(GR32_ADBits), X86::GR32_ADRegClassID, 32, 1, true, false },
3258 { GR32_ArgRef, GR32_ArgRefBits, 1621, 2, sizeof(GR32_ArgRefBits), X86::GR32_ArgRefRegClassID, 32, 1, true, false },
3259 { GR32_BPSP, GR32_BPSPBits, 1310, 2, sizeof(GR32_BPSPBits), X86::GR32_BPSPRegClassID, 32, 1, true, false },
3260 { GR32_BSI, GR32_BSIBits, 966, 2, sizeof(GR32_BSIBits), X86::GR32_BSIRegClassID, 32, 1, true, false },
3261 { GR32_CB, GR32_CBBits, 424, 2, sizeof(GR32_CBBits), X86::GR32_CBRegClassID, 32, 1, true, false },
3262 { GR32_DC, GR32_DCBits, 463, 2, sizeof(GR32_DCBits), X86::GR32_DCRegClassID, 32, 1, true, false },
3263 { GR32_DIBP, GR32_DIBPBits, 1127, 2, sizeof(GR32_DIBPBits), X86::GR32_DIBPRegClassID, 32, 1, true, false },
3264 { GR32_SIDI, GR32_SIDIBits, 839, 2, sizeof(GR32_SIDIBits), X86::GR32_SIDIRegClassID, 32, 1, true, false },
3265 { LOW32_ADDR_ACCESS_RBP_with_sub_32bit, LOW32_ADDR_ACCESS_RBP_with_sub_32bitBits, 1680, 2, sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_32bitBits), X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID, 32, 1, true, false },
3266 { CCR, CCRBits, 1322, 1, sizeof(CCRBits), X86::CCRRegClassID, 32, -1, false, false },
3267 { DFCCR, DFCCRBits, 1320, 1, sizeof(DFCCRBits), X86::DFCCRRegClassID, 32, -1, false, false },
3268 { GR32_ABCD_and_GR32_BSI, GR32_ABCD_and_GR32_BSIBits, 952, 1, sizeof(GR32_ABCD_and_GR32_BSIBits), X86::GR32_ABCD_and_GR32_BSIRegClassID, 32, 1, true, false },
3269 { GR32_AD_and_GR32_ArgRef, GR32_AD_and_GR32_ArgRefBits, 1609, 1, sizeof(GR32_AD_and_GR32_ArgRefBits), X86::GR32_AD_and_GR32_ArgRefRegClassID, 32, 1, true, false },
3270 { GR32_ArgRef_and_GR32_CB, GR32_ArgRef_and_GR32_CBBits, 408, 1, sizeof(GR32_ArgRef_and_GR32_CBBits), X86::GR32_ArgRef_and_GR32_CBRegClassID, 32, 1, true, false },
3271 { GR32_BPSP_and_GR32_DIBP, GR32_BPSP_and_GR32_DIBPBits, 1113, 1, sizeof(GR32_BPSP_and_GR32_DIBPBits), X86::GR32_BPSP_and_GR32_DIBPRegClassID, 32, 1, true, false },
3272 { GR32_BPSP_and_GR32_TC, GR32_BPSP_and_GR32_TCBits, 539, 1, sizeof(GR32_BPSP_and_GR32_TCBits), X86::GR32_BPSP_and_GR32_TCRegClassID, 32, 1, true, false },
3273 { GR32_BSI_and_GR32_SIDI, GR32_BSI_and_GR32_SIDIBits, 826, 1, sizeof(GR32_BSI_and_GR32_SIDIBits), X86::GR32_BSI_and_GR32_SIDIRegClassID, 32, 1, true, false },
3274 { GR32_DIBP_and_GR32_SIDI, GR32_DIBP_and_GR32_SIDIBits, 872, 1, sizeof(GR32_DIBP_and_GR32_SIDIBits), X86::GR32_DIBP_and_GR32_SIDIRegClassID, 32, 1, true, false },
3275 { LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit, LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitBits, 1750, 1, sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitBits), X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClassID, 32, 1, true, false },
3276 { LOW32_ADDR_ACCESS_with_sub_32bit, LOW32_ADDR_ACCESS_with_sub_32bitBits, 1717, 1, sizeof(LOW32_ADDR_ACCESS_with_sub_32bitBits), X86::LOW32_ADDR_ACCESS_with_sub_32bitRegClassID, 32, 1, true, false },
3277 { RFP64, RFP64Bits, 168, 7, sizeof(RFP64Bits), X86::RFP64RegClassID, 64, 1, true, false },
3278 { GR64, GR64Bits, 179, 33, sizeof(GR64Bits), X86::GR64RegClassID, 64, 1, true, false },
3279 { FR64X, FR64XBits, 1419, 32, sizeof(FR64XBits), X86::FR64XRegClassID, 64, 1, true, false },
3280 { GR64_with_sub_8bit, GR64_with_sub_8bitBits, 1801, 32, sizeof(GR64_with_sub_8bitBits), X86::GR64_with_sub_8bitRegClassID, 64, 1, true, false },
3281 { GR64_NOSP, GR64_NOSPBits, 1245, 31, sizeof(GR64_NOSPBits), X86::GR64_NOSPRegClassID, 64, 1, true, false },
3282 { GR64_NOREX2, GR64_NOREX2Bits, 53, 17, sizeof(GR64_NOREX2Bits), X86::GR64_NOREX2RegClassID, 64, 1, true, false },
3283 { CONTROL_REG, CONTROL_REGBits, 768, 16, sizeof(CONTROL_REGBits), X86::CONTROL_REGRegClassID, 64, 1, true, false },
3284 { FR64, FR64Bits, 174, 16, sizeof(FR64Bits), X86::FR64RegClassID, 64, 1, true, false },
3285 { GR64_with_sub_16bit_in_GR16_NOREX2, GR64_with_sub_16bit_in_GR16_NOREX2Bits, 65, 16, sizeof(GR64_with_sub_16bit_in_GR16_NOREX2Bits), X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, 64, 1, true, false },
3286 { GR64_NOREX2_NOSP, GR64_NOREX2_NOSPBits, 1228, 15, sizeof(GR64_NOREX2_NOSPBits), X86::GR64_NOREX2_NOSPRegClassID, 64, 1, true, false },
3287 { GR64PLTSafe, GR64PLTSafeBits, 1574, 13, sizeof(GR64PLTSafeBits), X86::GR64PLTSafeRegClassID, 64, 1, true, false },
3288 { GR64_TC, GR64_TCBits, 613, 10, sizeof(GR64_TCBits), X86::GR64_TCRegClassID, 64, 1, true, false },
3289 { GR64_NOREX, GR64_NOREXBits, 1456, 9, sizeof(GR64_NOREXBits), X86::GR64_NOREXRegClassID, 64, 1, true, false },
3290 { GR64_TCW64, GR64_TCW64Bits, 201, 9, sizeof(GR64_TCW64Bits), X86::GR64_TCW64RegClassID, 64, 1, true, false },
3291 { GR64_TC_with_sub_8bit, GR64_TC_with_sub_8bitBits, 1860, 9, sizeof(GR64_TC_with_sub_8bitBits), X86::GR64_TC_with_sub_8bitRegClassID, 64, 1, true, false },
3292 { GR64_NOREX2_NOSP_and_GR64_TC, GR64_NOREX2_NOSP_and_GR64_TCBits, 592, 8, sizeof(GR64_NOREX2_NOSP_and_GR64_TCBits), X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID, 64, 1, true, false },
3293 { GR64_TCW64_with_sub_8bit, GR64_TCW64_with_sub_8bitBits, 1820, 8, sizeof(GR64_TCW64_with_sub_8bitBits), X86::GR64_TCW64_with_sub_8bitRegClassID, 64, 1, true, false },
3294 { GR64_TC_and_GR64_TCW64, GR64_TC_and_GR64_TCW64Bits, 189, 8, sizeof(GR64_TC_and_GR64_TCW64Bits), X86::GR64_TC_and_GR64_TCW64RegClassID, 64, 1, true, false },
3295 { GR64_with_sub_16bit_in_GR16_NOREX, GR64_with_sub_16bit_in_GR16_NOREXBits, 1479, 8, sizeof(GR64_with_sub_16bit_in_GR16_NOREXBits), X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID, 64, 1, true, false },
3296 { VK64, VK64Bits, 163, 8, sizeof(VK64Bits), X86::VK64RegClassID, 64, 1, true, false },
3297 { VR64, VR64Bits, 184, 8, sizeof(VR64Bits), X86::VR64RegClassID, 64, 1, true, false },
3298 { GR64PLTSafe_and_GR64_TC, GR64PLTSafe_and_GR64_TCBits, 659, 7, sizeof(GR64PLTSafe_and_GR64_TCBits), X86::GR64PLTSafe_and_GR64_TCRegClassID, 64, 1, true, false },
3299 { GR64_NOREX2_NOSP_and_GR64_TCW64, GR64_NOREX2_NOSP_and_GR64_TCW64Bits, 224, 7, sizeof(GR64_NOREX2_NOSP_and_GR64_TCW64Bits), X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID, 64, 1, true, false },
3300 { GR64_NOREX_NOSP, GR64_NOREX_NOSPBits, 1271, 7, sizeof(GR64_NOREX_NOSPBits), X86::GR64_NOREX_NOSPRegClassID, 64, 1, true, false },
3301 { GR64_NOREX_and_GR64_TC, GR64_NOREX_and_GR64_TCBits, 621, 7, sizeof(GR64_NOREX_and_GR64_TCBits), X86::GR64_NOREX_and_GR64_TCRegClassID, 64, 1, true, false },
3302 { GR64_TCW64_and_GR64_TC_with_sub_8bit, GR64_TCW64_and_GR64_TC_with_sub_8bitBits, 1845, 7, sizeof(GR64_TCW64_and_GR64_TC_with_sub_8bitBits), X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID, 64, 1, true, false },
3303 { VK64WM, VK64WMBits, 1064, 7, sizeof(VK64WMBits), X86::VK64WMRegClassID, 64, 1, true, false },
3304 { GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64, GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64Bits, 212, 6, sizeof(GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64Bits), X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID, 64, 1, true, false },
3305 { GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX, GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXBits, 1467, 6, sizeof(GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXBits), X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID, 64, 1, true, false },
3306 { GR64PLTSafe_and_GR64_TCW64, GR64PLTSafe_and_GR64_TCW64Bits, 282, 5, sizeof(GR64PLTSafe_and_GR64_TCW64Bits), X86::GR64PLTSafe_and_GR64_TCW64RegClassID, 64, 1, true, false },
3307 { GR64_NOREX_and_GR64PLTSafe_and_GR64_TC, GR64_NOREX_and_GR64PLTSafe_and_GR64_TCBits, 644, 5, sizeof(GR64_NOREX_and_GR64PLTSafe_and_GR64_TCBits), X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID, 64, 1, true, false },
3308 { GR64_NOREX_and_GR64_TCW64, GR64_NOREX_and_GR64_TCW64Bits, 256, 5, sizeof(GR64_NOREX_and_GR64_TCW64Bits), X86::GR64_NOREX_and_GR64_TCW64RegClassID, 64, 1, true, false },
3309 { GR64_ABCD, GR64_ABCDBits, 733, 4, sizeof(GR64_ABCDBits), X86::GR64_ABCDRegClassID, 64, 1, true, false },
3310 { GR64_with_sub_32bit_in_GR32_TC, GR64_with_sub_32bit_in_GR32_TCBits, 561, 4, sizeof(GR64_with_sub_32bit_in_GR32_TCBits), X86::GR64_with_sub_32bit_in_GR32_TCRegClassID, 64, 1, true, false },
3311 { GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC, GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCBits, 471, 3, sizeof(GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCBits), X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID, 64, 1, true, false },
3312 { GR64_AD, GR64_ADBits, 715, 2, sizeof(GR64_ADBits), X86::GR64_ADRegClassID, 64, 1, true, false },
3313 { GR64_ArgRef, GR64_ArgRefBits, 1668, 2, sizeof(GR64_ArgRefBits), X86::GR64_ArgRefRegClassID, 64, 1, true, false },
3314 { GR64_and_LOW32_ADDR_ACCESS_RBP, GR64_and_LOW32_ADDR_ACCESS_RBPBits, 1170, 2, sizeof(GR64_and_LOW32_ADDR_ACCESS_RBPBits), X86::GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID, 64, 1, true, false },
3315 { GR64_with_sub_32bit_in_GR32_ArgRef, GR64_with_sub_32bit_in_GR32_ArgRefBits, 1633, 2, sizeof(GR64_with_sub_32bit_in_GR32_ArgRefBits), X86::GR64_with_sub_32bit_in_GR32_ArgRefRegClassID, 64, 1, true, false },
3316 { GR64_with_sub_32bit_in_GR32_BPSP, GR64_with_sub_32bit_in_GR32_BPSPBits, 1287, 2, sizeof(GR64_with_sub_32bit_in_GR32_BPSPBits), X86::GR64_with_sub_32bit_in_GR32_BPSPRegClassID, 64, 1, true, false },
3317 { GR64_with_sub_32bit_in_GR32_BSI, GR64_with_sub_32bit_in_GR32_BSIBits, 975, 2, sizeof(GR64_with_sub_32bit_in_GR32_BSIBits), X86::GR64_with_sub_32bit_in_GR32_BSIRegClassID, 64, 1, true, false },
3318 { GR64_with_sub_32bit_in_GR32_CB, GR64_with_sub_32bit_in_GR32_CBBits, 432, 2, sizeof(GR64_with_sub_32bit_in_GR32_CBBits), X86::GR64_with_sub_32bit_in_GR32_CBRegClassID, 64, 1, true, false },
3319 { GR64_with_sub_32bit_in_GR32_DIBP, GR64_with_sub_32bit_in_GR32_DIBPBits, 1137, 2, sizeof(GR64_with_sub_32bit_in_GR32_DIBPBits), X86::GR64_with_sub_32bit_in_GR32_DIBPRegClassID, 64, 1, true, false },
3320 { GR64_with_sub_32bit_in_GR32_SIDI, GR64_with_sub_32bit_in_GR32_SIDIBits, 896, 2, sizeof(GR64_with_sub_32bit_in_GR32_SIDIBits), X86::GR64_with_sub_32bit_in_GR32_SIDIRegClassID, 64, 1, true, false },
3321 { GR64_A, GR64_ABits, 378, 1, sizeof(GR64_ABits), X86::GR64_ARegClassID, 64, 1, true, false },
3322 { GR64_ArgRef_and_GR64_TC, GR64_ArgRef_and_GR64_TCBits, 683, 1, sizeof(GR64_ArgRef_and_GR64_TCBits), X86::GR64_ArgRef_and_GR64_TCRegClassID, 64, 1, true, false },
3323 { GR64_and_LOW32_ADDR_ACCESS, GR64_and_LOW32_ADDR_ACCESSBits, 1382, 1, sizeof(GR64_and_LOW32_ADDR_ACCESSBits), X86::GR64_and_LOW32_ADDR_ACCESSRegClassID, 64, 1, true, false },
3324 { GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI, GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIBits, 929, 1, sizeof(GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIBits), X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClassID, 64, 1, true, false },
3325 { GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef, GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefBits, 1586, 1, sizeof(GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefBits), X86::GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefRegClassID, 64, 1, true, false },
3326 { GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB, GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBBits, 385, 1, sizeof(GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBBits), X86::GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBRegClassID, 64, 1, true, false },
3327 { GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP, GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPBits, 1090, 1, sizeof(GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPBits), X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClassID, 64, 1, true, false },
3328 { GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC, GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCBits, 516, 1, sizeof(GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCBits), X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClassID, 64, 1, true, false },
3329 { GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI, GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIBits, 803, 1, sizeof(GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIBits), X86::GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClassID, 64, 1, true, false },
3330 { GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI, GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIBits, 849, 1, sizeof(GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIBits), X86::GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClassID, 64, 1, true, false },
3331 { RST, RSTBits, 1409, 8, sizeof(RSTBits), X86::RSTRegClassID, 80, 1, false, false },
3332 { RFP80, RFP80Bits, 0, 7, sizeof(RFP80Bits), X86::RFP80RegClassID, 80, 1, true, false },
3333 { RFP80_7, RFP80_7Bits, 351, 1, sizeof(RFP80_7Bits), X86::RFP80_7RegClassID, 80, 1, false, false },
3334 { VR128X, VR128XBits, 1438, 32, sizeof(VR128XBits), X86::VR128XRegClassID, 128, 1, true, false },
3335 { VR128, VR128Bits, 359, 16, sizeof(VR128Bits), X86::VR128RegClassID, 128, 1, true, false },
3336 { VR256X, VR256XBits, 1431, 32, sizeof(VR256XBits), X86::VR256XRegClassID, 256, 1, true, false },
3337 { VR256, VR256Bits, 345, 16, sizeof(VR256Bits), X86::VR256RegClassID, 256, 1, true, false },
3338 { VR512, VR512Bits, 10, 32, sizeof(VR512Bits), X86::VR512RegClassID, 512, 1, true, false },
3339 { VR512_0_15, VR512_0_15Bits, 313, 16, sizeof(VR512_0_15Bits), X86::VR512_0_15RegClassID, 512, 1, true, false },
3340 { TILE, TILEBits, 753, 8, sizeof(TILEBits), X86::TILERegClassID, 8192, -1, true, false },
3341 { TILEPAIR, TILEPAIRBits, 1373, 4, sizeof(TILEPAIRBits), X86::TILEPAIRRegClassID, 16384, 1, true, false },
3342};
3343
3344// X86 Dwarf<->LLVM register mappings.
3345extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour0Dwarf2L[] = {
3346 { 0U, X86::RAX },
3347 { 1U, X86::RDX },
3348 { 2U, X86::RCX },
3349 { 3U, X86::RBX },
3350 { 4U, X86::RSI },
3351 { 5U, X86::RDI },
3352 { 6U, X86::RBP },
3353 { 7U, X86::RSP },
3354 { 8U, X86::R8 },
3355 { 9U, X86::R9 },
3356 { 10U, X86::R10 },
3357 { 11U, X86::R11 },
3358 { 12U, X86::R12 },
3359 { 13U, X86::R13 },
3360 { 14U, X86::R14 },
3361 { 15U, X86::R15 },
3362 { 16U, X86::RIP },
3363 { 17U, X86::XMM0 },
3364 { 18U, X86::XMM1 },
3365 { 19U, X86::XMM2 },
3366 { 20U, X86::XMM3 },
3367 { 21U, X86::XMM4 },
3368 { 22U, X86::XMM5 },
3369 { 23U, X86::XMM6 },
3370 { 24U, X86::XMM7 },
3371 { 25U, X86::XMM8 },
3372 { 26U, X86::XMM9 },
3373 { 27U, X86::XMM10 },
3374 { 28U, X86::XMM11 },
3375 { 29U, X86::XMM12 },
3376 { 30U, X86::XMM13 },
3377 { 31U, X86::XMM14 },
3378 { 32U, X86::XMM15 },
3379 { 33U, X86::ST0 },
3380 { 34U, X86::ST1 },
3381 { 35U, X86::ST2 },
3382 { 36U, X86::ST3 },
3383 { 37U, X86::ST4 },
3384 { 38U, X86::ST5 },
3385 { 39U, X86::ST6 },
3386 { 40U, X86::ST7 },
3387 { 41U, X86::MM0 },
3388 { 42U, X86::MM1 },
3389 { 43U, X86::MM2 },
3390 { 44U, X86::MM3 },
3391 { 45U, X86::MM4 },
3392 { 46U, X86::MM5 },
3393 { 47U, X86::MM6 },
3394 { 48U, X86::MM7 },
3395 { 49U, X86::RFLAGS },
3396 { 50U, X86::ES },
3397 { 51U, X86::CS },
3398 { 52U, X86::SS },
3399 { 53U, X86::DS },
3400 { 54U, X86::FS },
3401 { 55U, X86::GS },
3402 { 58U, X86::FS_BASE },
3403 { 59U, X86::GS_BASE },
3404 { 67U, X86::XMM16 },
3405 { 68U, X86::XMM17 },
3406 { 69U, X86::XMM18 },
3407 { 70U, X86::XMM19 },
3408 { 71U, X86::XMM20 },
3409 { 72U, X86::XMM21 },
3410 { 73U, X86::XMM22 },
3411 { 74U, X86::XMM23 },
3412 { 75U, X86::XMM24 },
3413 { 76U, X86::XMM25 },
3414 { 77U, X86::XMM26 },
3415 { 78U, X86::XMM27 },
3416 { 79U, X86::XMM28 },
3417 { 80U, X86::XMM29 },
3418 { 81U, X86::XMM30 },
3419 { 82U, X86::XMM31 },
3420 { 118U, X86::K0 },
3421 { 119U, X86::K1 },
3422 { 120U, X86::K2 },
3423 { 121U, X86::K3 },
3424 { 122U, X86::K4 },
3425 { 123U, X86::K5 },
3426 { 124U, X86::K6 },
3427 { 125U, X86::K7 },
3428 { 130U, X86::R16 },
3429 { 131U, X86::R17 },
3430 { 132U, X86::R18 },
3431 { 133U, X86::R19 },
3432 { 134U, X86::R20 },
3433 { 135U, X86::R21 },
3434 { 136U, X86::R22 },
3435 { 137U, X86::R23 },
3436 { 138U, X86::R24 },
3437 { 139U, X86::R25 },
3438 { 140U, X86::R26 },
3439 { 141U, X86::R27 },
3440 { 142U, X86::R28 },
3441 { 143U, X86::R29 },
3442 { 144U, X86::R30 },
3443 { 145U, X86::R31 },
3444};
3445extern const unsigned X86DwarfFlavour0Dwarf2LSize = std::size(X86DwarfFlavour0Dwarf2L);
3446
3447extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour1Dwarf2L[] = {
3448 { 0U, X86::EAX },
3449 { 1U, X86::ECX },
3450 { 2U, X86::EDX },
3451 { 3U, X86::EBX },
3452 { 4U, X86::EBP },
3453 { 5U, X86::ESP },
3454 { 6U, X86::ESI },
3455 { 7U, X86::EDI },
3456 { 8U, X86::EIP },
3457 { 9U, X86::EFLAGS },
3458 { 12U, X86::ST0 },
3459 { 13U, X86::ST1 },
3460 { 14U, X86::ST2 },
3461 { 15U, X86::ST3 },
3462 { 16U, X86::ST4 },
3463 { 17U, X86::ST5 },
3464 { 18U, X86::ST6 },
3465 { 19U, X86::ST7 },
3466 { 21U, X86::XMM0 },
3467 { 22U, X86::XMM1 },
3468 { 23U, X86::XMM2 },
3469 { 24U, X86::XMM3 },
3470 { 25U, X86::XMM4 },
3471 { 26U, X86::XMM5 },
3472 { 27U, X86::XMM6 },
3473 { 28U, X86::XMM7 },
3474 { 29U, X86::MM0 },
3475 { 30U, X86::MM1 },
3476 { 31U, X86::MM2 },
3477 { 32U, X86::MM3 },
3478 { 33U, X86::MM4 },
3479 { 34U, X86::MM5 },
3480 { 35U, X86::MM6 },
3481 { 36U, X86::MM7 },
3482 { 93U, X86::K0 },
3483 { 94U, X86::K1 },
3484 { 95U, X86::K2 },
3485 { 96U, X86::K3 },
3486 { 97U, X86::K4 },
3487 { 98U, X86::K5 },
3488 { 99U, X86::K6 },
3489 { 100U, X86::K7 },
3490};
3491extern const unsigned X86DwarfFlavour1Dwarf2LSize = std::size(X86DwarfFlavour1Dwarf2L);
3492
3493extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour2Dwarf2L[] = {
3494 { 0U, X86::EAX },
3495 { 1U, X86::ECX },
3496 { 2U, X86::EDX },
3497 { 3U, X86::EBX },
3498 { 4U, X86::ESP },
3499 { 5U, X86::EBP },
3500 { 6U, X86::ESI },
3501 { 7U, X86::EDI },
3502 { 8U, X86::EIP },
3503 { 9U, X86::EFLAGS },
3504 { 11U, X86::ST0 },
3505 { 12U, X86::ST1 },
3506 { 13U, X86::ST2 },
3507 { 14U, X86::ST3 },
3508 { 15U, X86::ST4 },
3509 { 16U, X86::ST5 },
3510 { 17U, X86::ST6 },
3511 { 18U, X86::ST7 },
3512 { 21U, X86::XMM0 },
3513 { 22U, X86::XMM1 },
3514 { 23U, X86::XMM2 },
3515 { 24U, X86::XMM3 },
3516 { 25U, X86::XMM4 },
3517 { 26U, X86::XMM5 },
3518 { 27U, X86::XMM6 },
3519 { 28U, X86::XMM7 },
3520 { 29U, X86::MM0 },
3521 { 30U, X86::MM1 },
3522 { 31U, X86::MM2 },
3523 { 32U, X86::MM3 },
3524 { 33U, X86::MM4 },
3525 { 34U, X86::MM5 },
3526 { 35U, X86::MM6 },
3527 { 36U, X86::MM7 },
3528 { 40U, X86::ES },
3529 { 41U, X86::CS },
3530 { 42U, X86::SS },
3531 { 43U, X86::DS },
3532 { 44U, X86::FS },
3533 { 45U, X86::GS },
3534 { 93U, X86::K0 },
3535 { 94U, X86::K1 },
3536 { 95U, X86::K2 },
3537 { 96U, X86::K3 },
3538 { 97U, X86::K4 },
3539 { 98U, X86::K5 },
3540 { 99U, X86::K6 },
3541 { 100U, X86::K7 },
3542};
3543extern const unsigned X86DwarfFlavour2Dwarf2LSize = std::size(X86DwarfFlavour2Dwarf2L);
3544
3545extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour0Dwarf2L[] = {
3546 { 0U, X86::RAX },
3547 { 1U, X86::RDX },
3548 { 2U, X86::RCX },
3549 { 3U, X86::RBX },
3550 { 4U, X86::RSI },
3551 { 5U, X86::RDI },
3552 { 6U, X86::RBP },
3553 { 7U, X86::RSP },
3554 { 8U, X86::R8 },
3555 { 9U, X86::R9 },
3556 { 10U, X86::R10 },
3557 { 11U, X86::R11 },
3558 { 12U, X86::R12 },
3559 { 13U, X86::R13 },
3560 { 14U, X86::R14 },
3561 { 15U, X86::R15 },
3562 { 16U, X86::RIP },
3563 { 17U, X86::XMM0 },
3564 { 18U, X86::XMM1 },
3565 { 19U, X86::XMM2 },
3566 { 20U, X86::XMM3 },
3567 { 21U, X86::XMM4 },
3568 { 22U, X86::XMM5 },
3569 { 23U, X86::XMM6 },
3570 { 24U, X86::XMM7 },
3571 { 25U, X86::XMM8 },
3572 { 26U, X86::XMM9 },
3573 { 27U, X86::XMM10 },
3574 { 28U, X86::XMM11 },
3575 { 29U, X86::XMM12 },
3576 { 30U, X86::XMM13 },
3577 { 31U, X86::XMM14 },
3578 { 32U, X86::XMM15 },
3579 { 33U, X86::ST0 },
3580 { 34U, X86::ST1 },
3581 { 35U, X86::ST2 },
3582 { 36U, X86::ST3 },
3583 { 37U, X86::ST4 },
3584 { 38U, X86::ST5 },
3585 { 39U, X86::ST6 },
3586 { 40U, X86::ST7 },
3587 { 41U, X86::MM0 },
3588 { 42U, X86::MM1 },
3589 { 43U, X86::MM2 },
3590 { 44U, X86::MM3 },
3591 { 45U, X86::MM4 },
3592 { 46U, X86::MM5 },
3593 { 47U, X86::MM6 },
3594 { 48U, X86::MM7 },
3595 { 49U, X86::RFLAGS },
3596 { 50U, X86::ES },
3597 { 51U, X86::CS },
3598 { 52U, X86::SS },
3599 { 53U, X86::DS },
3600 { 54U, X86::FS },
3601 { 55U, X86::GS },
3602 { 58U, X86::FS_BASE },
3603 { 59U, X86::GS_BASE },
3604 { 67U, X86::XMM16 },
3605 { 68U, X86::XMM17 },
3606 { 69U, X86::XMM18 },
3607 { 70U, X86::XMM19 },
3608 { 71U, X86::XMM20 },
3609 { 72U, X86::XMM21 },
3610 { 73U, X86::XMM22 },
3611 { 74U, X86::XMM23 },
3612 { 75U, X86::XMM24 },
3613 { 76U, X86::XMM25 },
3614 { 77U, X86::XMM26 },
3615 { 78U, X86::XMM27 },
3616 { 79U, X86::XMM28 },
3617 { 80U, X86::XMM29 },
3618 { 81U, X86::XMM30 },
3619 { 82U, X86::XMM31 },
3620 { 118U, X86::K0 },
3621 { 119U, X86::K1 },
3622 { 120U, X86::K2 },
3623 { 121U, X86::K3 },
3624 { 122U, X86::K4 },
3625 { 123U, X86::K5 },
3626 { 124U, X86::K6 },
3627 { 125U, X86::K7 },
3628 { 130U, X86::R16 },
3629 { 131U, X86::R17 },
3630 { 132U, X86::R18 },
3631 { 133U, X86::R19 },
3632 { 134U, X86::R20 },
3633 { 135U, X86::R21 },
3634 { 136U, X86::R22 },
3635 { 137U, X86::R23 },
3636 { 138U, X86::R24 },
3637 { 139U, X86::R25 },
3638 { 140U, X86::R26 },
3639 { 141U, X86::R27 },
3640 { 142U, X86::R28 },
3641 { 143U, X86::R29 },
3642 { 144U, X86::R30 },
3643 { 145U, X86::R31 },
3644};
3645extern const unsigned X86EHFlavour0Dwarf2LSize = std::size(X86EHFlavour0Dwarf2L);
3646
3647extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour1Dwarf2L[] = {
3648 { 0U, X86::EAX },
3649 { 1U, X86::ECX },
3650 { 2U, X86::EDX },
3651 { 3U, X86::EBX },
3652 { 4U, X86::EBP },
3653 { 5U, X86::ESP },
3654 { 6U, X86::ESI },
3655 { 7U, X86::EDI },
3656 { 8U, X86::EIP },
3657 { 9U, X86::EFLAGS },
3658 { 12U, X86::ST0 },
3659 { 13U, X86::ST1 },
3660 { 14U, X86::ST2 },
3661 { 15U, X86::ST3 },
3662 { 16U, X86::ST4 },
3663 { 17U, X86::ST5 },
3664 { 18U, X86::ST6 },
3665 { 19U, X86::ST7 },
3666 { 21U, X86::XMM0 },
3667 { 22U, X86::XMM1 },
3668 { 23U, X86::XMM2 },
3669 { 24U, X86::XMM3 },
3670 { 25U, X86::XMM4 },
3671 { 26U, X86::XMM5 },
3672 { 27U, X86::XMM6 },
3673 { 28U, X86::XMM7 },
3674 { 29U, X86::MM0 },
3675 { 30U, X86::MM1 },
3676 { 31U, X86::MM2 },
3677 { 32U, X86::MM3 },
3678 { 33U, X86::MM4 },
3679 { 34U, X86::MM5 },
3680 { 35U, X86::MM6 },
3681 { 36U, X86::MM7 },
3682 { 93U, X86::K0 },
3683 { 94U, X86::K1 },
3684 { 95U, X86::K2 },
3685 { 96U, X86::K3 },
3686 { 97U, X86::K4 },
3687 { 98U, X86::K5 },
3688 { 99U, X86::K6 },
3689 { 100U, X86::K7 },
3690};
3691extern const unsigned X86EHFlavour1Dwarf2LSize = std::size(X86EHFlavour1Dwarf2L);
3692
3693extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour2Dwarf2L[] = {
3694 { 0U, X86::EAX },
3695 { 1U, X86::ECX },
3696 { 2U, X86::EDX },
3697 { 3U, X86::EBX },
3698 { 4U, X86::ESP },
3699 { 5U, X86::EBP },
3700 { 6U, X86::ESI },
3701 { 7U, X86::EDI },
3702 { 8U, X86::EIP },
3703 { 9U, X86::EFLAGS },
3704 { 11U, X86::ST0 },
3705 { 12U, X86::ST1 },
3706 { 13U, X86::ST2 },
3707 { 14U, X86::ST3 },
3708 { 15U, X86::ST4 },
3709 { 16U, X86::ST5 },
3710 { 17U, X86::ST6 },
3711 { 18U, X86::ST7 },
3712 { 21U, X86::XMM0 },
3713 { 22U, X86::XMM1 },
3714 { 23U, X86::XMM2 },
3715 { 24U, X86::XMM3 },
3716 { 25U, X86::XMM4 },
3717 { 26U, X86::XMM5 },
3718 { 27U, X86::XMM6 },
3719 { 28U, X86::XMM7 },
3720 { 29U, X86::MM0 },
3721 { 30U, X86::MM1 },
3722 { 31U, X86::MM2 },
3723 { 32U, X86::MM3 },
3724 { 33U, X86::MM4 },
3725 { 34U, X86::MM5 },
3726 { 35U, X86::MM6 },
3727 { 36U, X86::MM7 },
3728 { 40U, X86::ES },
3729 { 41U, X86::CS },
3730 { 42U, X86::SS },
3731 { 43U, X86::DS },
3732 { 44U, X86::FS },
3733 { 45U, X86::GS },
3734 { 93U, X86::K0 },
3735 { 94U, X86::K1 },
3736 { 95U, X86::K2 },
3737 { 96U, X86::K3 },
3738 { 97U, X86::K4 },
3739 { 98U, X86::K5 },
3740 { 99U, X86::K6 },
3741 { 100U, X86::K7 },
3742};
3743extern const unsigned X86EHFlavour2Dwarf2LSize = std::size(X86EHFlavour2Dwarf2L);
3744
3745extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour0L2Dwarf[] = {
3746 { X86::CS, 51U },
3747 { X86::DS, 53U },
3748 { X86::EAX, -2U },
3749 { X86::EBP, -2U },
3750 { X86::EBX, -2U },
3751 { X86::ECX, -2U },
3752 { X86::EDI, -2U },
3753 { X86::EDX, -2U },
3754 { X86::EFLAGS, 49U },
3755 { X86::EIP, -2U },
3756 { X86::ES, 50U },
3757 { X86::ESI, -2U },
3758 { X86::ESP, -2U },
3759 { X86::FS, 54U },
3760 { X86::FS_BASE, 58U },
3761 { X86::GS, 55U },
3762 { X86::GS_BASE, 59U },
3763 { X86::RAX, 0U },
3764 { X86::RBP, 6U },
3765 { X86::RBX, 3U },
3766 { X86::RCX, 2U },
3767 { X86::RDI, 5U },
3768 { X86::RDX, 1U },
3769 { X86::RFLAGS, 49U },
3770 { X86::RIP, 16U },
3771 { X86::RSI, 4U },
3772 { X86::RSP, 7U },
3773 { X86::SS, 52U },
3774 { X86::_EFLAGS, 49U },
3775 { X86::MM0, 41U },
3776 { X86::MM1, 42U },
3777 { X86::MM2, 43U },
3778 { X86::MM3, 44U },
3779 { X86::MM4, 45U },
3780 { X86::MM5, 46U },
3781 { X86::MM6, 47U },
3782 { X86::MM7, 48U },
3783 { X86::R8, 8U },
3784 { X86::R9, 9U },
3785 { X86::R10, 10U },
3786 { X86::R11, 11U },
3787 { X86::R12, 12U },
3788 { X86::R13, 13U },
3789 { X86::R14, 14U },
3790 { X86::R15, 15U },
3791 { X86::ST0, 33U },
3792 { X86::ST1, 34U },
3793 { X86::ST2, 35U },
3794 { X86::ST3, 36U },
3795 { X86::ST4, 37U },
3796 { X86::ST5, 38U },
3797 { X86::ST6, 39U },
3798 { X86::ST7, 40U },
3799 { X86::XMM0, 17U },
3800 { X86::XMM1, 18U },
3801 { X86::XMM2, 19U },
3802 { X86::XMM3, 20U },
3803 { X86::XMM4, 21U },
3804 { X86::XMM5, 22U },
3805 { X86::XMM6, 23U },
3806 { X86::XMM7, 24U },
3807 { X86::XMM8, 25U },
3808 { X86::XMM9, 26U },
3809 { X86::XMM10, 27U },
3810 { X86::XMM11, 28U },
3811 { X86::XMM12, 29U },
3812 { X86::XMM13, 30U },
3813 { X86::XMM14, 31U },
3814 { X86::XMM15, 32U },
3815 { X86::YMM0, 17U },
3816 { X86::YMM1, 18U },
3817 { X86::YMM2, 19U },
3818 { X86::YMM3, 20U },
3819 { X86::YMM4, 21U },
3820 { X86::YMM5, 22U },
3821 { X86::YMM6, 23U },
3822 { X86::YMM7, 24U },
3823 { X86::YMM8, 25U },
3824 { X86::YMM9, 26U },
3825 { X86::YMM10, 27U },
3826 { X86::YMM11, 28U },
3827 { X86::YMM12, 29U },
3828 { X86::YMM13, 30U },
3829 { X86::YMM14, 31U },
3830 { X86::YMM15, 32U },
3831 { X86::K0, 118U },
3832 { X86::K1, 119U },
3833 { X86::K2, 120U },
3834 { X86::K3, 121U },
3835 { X86::K4, 122U },
3836 { X86::K5, 123U },
3837 { X86::K6, 124U },
3838 { X86::K7, 125U },
3839 { X86::XMM16, 67U },
3840 { X86::XMM17, 68U },
3841 { X86::XMM18, 69U },
3842 { X86::XMM19, 70U },
3843 { X86::XMM20, 71U },
3844 { X86::XMM21, 72U },
3845 { X86::XMM22, 73U },
3846 { X86::XMM23, 74U },
3847 { X86::XMM24, 75U },
3848 { X86::XMM25, 76U },
3849 { X86::XMM26, 77U },
3850 { X86::XMM27, 78U },
3851 { X86::XMM28, 79U },
3852 { X86::XMM29, 80U },
3853 { X86::XMM30, 81U },
3854 { X86::XMM31, 82U },
3855 { X86::YMM16, 67U },
3856 { X86::YMM17, 68U },
3857 { X86::YMM18, 69U },
3858 { X86::YMM19, 70U },
3859 { X86::YMM20, 71U },
3860 { X86::YMM21, 72U },
3861 { X86::YMM22, 73U },
3862 { X86::YMM23, 74U },
3863 { X86::YMM24, 75U },
3864 { X86::YMM25, 76U },
3865 { X86::YMM26, 77U },
3866 { X86::YMM27, 78U },
3867 { X86::YMM28, 79U },
3868 { X86::YMM29, 80U },
3869 { X86::YMM30, 81U },
3870 { X86::YMM31, 82U },
3871 { X86::ZMM0, 17U },
3872 { X86::ZMM1, 18U },
3873 { X86::ZMM2, 19U },
3874 { X86::ZMM3, 20U },
3875 { X86::ZMM4, 21U },
3876 { X86::ZMM5, 22U },
3877 { X86::ZMM6, 23U },
3878 { X86::ZMM7, 24U },
3879 { X86::ZMM8, 25U },
3880 { X86::ZMM9, 26U },
3881 { X86::ZMM10, 27U },
3882 { X86::ZMM11, 28U },
3883 { X86::ZMM12, 29U },
3884 { X86::ZMM13, 30U },
3885 { X86::ZMM14, 31U },
3886 { X86::ZMM15, 32U },
3887 { X86::ZMM16, 67U },
3888 { X86::ZMM17, 68U },
3889 { X86::ZMM18, 69U },
3890 { X86::ZMM19, 70U },
3891 { X86::ZMM20, 71U },
3892 { X86::ZMM21, 72U },
3893 { X86::ZMM22, 73U },
3894 { X86::ZMM23, 74U },
3895 { X86::ZMM24, 75U },
3896 { X86::ZMM25, 76U },
3897 { X86::ZMM26, 77U },
3898 { X86::ZMM27, 78U },
3899 { X86::ZMM28, 79U },
3900 { X86::ZMM29, 80U },
3901 { X86::ZMM30, 81U },
3902 { X86::ZMM31, 82U },
3903 { X86::R16, 130U },
3904 { X86::R17, 131U },
3905 { X86::R18, 132U },
3906 { X86::R19, 133U },
3907 { X86::R20, 134U },
3908 { X86::R21, 135U },
3909 { X86::R22, 136U },
3910 { X86::R23, 137U },
3911 { X86::R24, 138U },
3912 { X86::R25, 139U },
3913 { X86::R26, 140U },
3914 { X86::R27, 141U },
3915 { X86::R28, 142U },
3916 { X86::R29, 143U },
3917 { X86::R30, 144U },
3918 { X86::R31, 145U },
3919};
3920extern const unsigned X86DwarfFlavour0L2DwarfSize = std::size(X86DwarfFlavour0L2Dwarf);
3921
3922extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour1L2Dwarf[] = {
3923 { X86::CS, -2U },
3924 { X86::DS, -2U },
3925 { X86::EAX, 0U },
3926 { X86::EBP, 4U },
3927 { X86::EBX, 3U },
3928 { X86::ECX, 1U },
3929 { X86::EDI, 7U },
3930 { X86::EDX, 2U },
3931 { X86::EFLAGS, 9U },
3932 { X86::EIP, 8U },
3933 { X86::ES, -2U },
3934 { X86::ESI, 6U },
3935 { X86::ESP, 5U },
3936 { X86::FS, -2U },
3937 { X86::FS_BASE, -2U },
3938 { X86::GS, -2U },
3939 { X86::GS_BASE, -2U },
3940 { X86::RAX, -2U },
3941 { X86::RBP, -2U },
3942 { X86::RBX, -2U },
3943 { X86::RCX, -2U },
3944 { X86::RDI, -2U },
3945 { X86::RDX, -2U },
3946 { X86::RFLAGS, -2U },
3947 { X86::RIP, -2U },
3948 { X86::RSI, -2U },
3949 { X86::RSP, -2U },
3950 { X86::SS, -2U },
3951 { X86::_EFLAGS, 9U },
3952 { X86::MM0, 29U },
3953 { X86::MM1, 30U },
3954 { X86::MM2, 31U },
3955 { X86::MM3, 32U },
3956 { X86::MM4, 33U },
3957 { X86::MM5, 34U },
3958 { X86::MM6, 35U },
3959 { X86::MM7, 36U },
3960 { X86::R8, -2U },
3961 { X86::R9, -2U },
3962 { X86::R10, -2U },
3963 { X86::R11, -2U },
3964 { X86::R12, -2U },
3965 { X86::R13, -2U },
3966 { X86::R14, -2U },
3967 { X86::R15, -2U },
3968 { X86::ST0, 12U },
3969 { X86::ST1, 13U },
3970 { X86::ST2, 14U },
3971 { X86::ST3, 15U },
3972 { X86::ST4, 16U },
3973 { X86::ST5, 17U },
3974 { X86::ST6, 18U },
3975 { X86::ST7, 19U },
3976 { X86::XMM0, 21U },
3977 { X86::XMM1, 22U },
3978 { X86::XMM2, 23U },
3979 { X86::XMM3, 24U },
3980 { X86::XMM4, 25U },
3981 { X86::XMM5, 26U },
3982 { X86::XMM6, 27U },
3983 { X86::XMM7, 28U },
3984 { X86::XMM8, -2U },
3985 { X86::XMM9, -2U },
3986 { X86::XMM10, -2U },
3987 { X86::XMM11, -2U },
3988 { X86::XMM12, -2U },
3989 { X86::XMM13, -2U },
3990 { X86::XMM14, -2U },
3991 { X86::XMM15, -2U },
3992 { X86::YMM0, 21U },
3993 { X86::YMM1, 22U },
3994 { X86::YMM2, 23U },
3995 { X86::YMM3, 24U },
3996 { X86::YMM4, 25U },
3997 { X86::YMM5, 26U },
3998 { X86::YMM6, 27U },
3999 { X86::YMM7, 28U },
4000 { X86::YMM8, -2U },
4001 { X86::YMM9, -2U },
4002 { X86::YMM10, -2U },
4003 { X86::YMM11, -2U },
4004 { X86::YMM12, -2U },
4005 { X86::YMM13, -2U },
4006 { X86::YMM14, -2U },
4007 { X86::YMM15, -2U },
4008 { X86::K0, 93U },
4009 { X86::K1, 94U },
4010 { X86::K2, 95U },
4011 { X86::K3, 96U },
4012 { X86::K4, 97U },
4013 { X86::K5, 98U },
4014 { X86::K6, 99U },
4015 { X86::K7, 100U },
4016 { X86::XMM16, -2U },
4017 { X86::XMM17, -2U },
4018 { X86::XMM18, -2U },
4019 { X86::XMM19, -2U },
4020 { X86::XMM20, -2U },
4021 { X86::XMM21, -2U },
4022 { X86::XMM22, -2U },
4023 { X86::XMM23, -2U },
4024 { X86::XMM24, -2U },
4025 { X86::XMM25, -2U },
4026 { X86::XMM26, -2U },
4027 { X86::XMM27, -2U },
4028 { X86::XMM28, -2U },
4029 { X86::XMM29, -2U },
4030 { X86::XMM30, -2U },
4031 { X86::XMM31, -2U },
4032 { X86::YMM16, -2U },
4033 { X86::YMM17, -2U },
4034 { X86::YMM18, -2U },
4035 { X86::YMM19, -2U },
4036 { X86::YMM20, -2U },
4037 { X86::YMM21, -2U },
4038 { X86::YMM22, -2U },
4039 { X86::YMM23, -2U },
4040 { X86::YMM24, -2U },
4041 { X86::YMM25, -2U },
4042 { X86::YMM26, -2U },
4043 { X86::YMM27, -2U },
4044 { X86::YMM28, -2U },
4045 { X86::YMM29, -2U },
4046 { X86::YMM30, -2U },
4047 { X86::YMM31, -2U },
4048 { X86::ZMM0, 21U },
4049 { X86::ZMM1, 22U },
4050 { X86::ZMM2, 23U },
4051 { X86::ZMM3, 24U },
4052 { X86::ZMM4, 25U },
4053 { X86::ZMM5, 26U },
4054 { X86::ZMM6, 27U },
4055 { X86::ZMM7, 28U },
4056 { X86::ZMM8, -2U },
4057 { X86::ZMM9, -2U },
4058 { X86::ZMM10, -2U },
4059 { X86::ZMM11, -2U },
4060 { X86::ZMM12, -2U },
4061 { X86::ZMM13, -2U },
4062 { X86::ZMM14, -2U },
4063 { X86::ZMM15, -2U },
4064 { X86::ZMM16, -2U },
4065 { X86::ZMM17, -2U },
4066 { X86::ZMM18, -2U },
4067 { X86::ZMM19, -2U },
4068 { X86::ZMM20, -2U },
4069 { X86::ZMM21, -2U },
4070 { X86::ZMM22, -2U },
4071 { X86::ZMM23, -2U },
4072 { X86::ZMM24, -2U },
4073 { X86::ZMM25, -2U },
4074 { X86::ZMM26, -2U },
4075 { X86::ZMM27, -2U },
4076 { X86::ZMM28, -2U },
4077 { X86::ZMM29, -2U },
4078 { X86::ZMM30, -2U },
4079 { X86::ZMM31, -2U },
4080 { X86::R16, -2U },
4081 { X86::R17, -2U },
4082 { X86::R18, -2U },
4083 { X86::R19, -2U },
4084 { X86::R20, -2U },
4085 { X86::R21, -2U },
4086 { X86::R22, -2U },
4087 { X86::R23, -2U },
4088 { X86::R24, -2U },
4089 { X86::R25, -2U },
4090 { X86::R26, -2U },
4091 { X86::R27, -2U },
4092 { X86::R28, -2U },
4093 { X86::R29, -2U },
4094 { X86::R30, -2U },
4095 { X86::R31, -2U },
4096};
4097extern const unsigned X86DwarfFlavour1L2DwarfSize = std::size(X86DwarfFlavour1L2Dwarf);
4098
4099extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour2L2Dwarf[] = {
4100 { X86::CS, 41U },
4101 { X86::DS, 43U },
4102 { X86::EAX, 0U },
4103 { X86::EBP, 5U },
4104 { X86::EBX, 3U },
4105 { X86::ECX, 1U },
4106 { X86::EDI, 7U },
4107 { X86::EDX, 2U },
4108 { X86::EFLAGS, 9U },
4109 { X86::EIP, 8U },
4110 { X86::ES, 40U },
4111 { X86::ESI, 6U },
4112 { X86::ESP, 4U },
4113 { X86::FS, 44U },
4114 { X86::FS_BASE, -2U },
4115 { X86::GS, 45U },
4116 { X86::GS_BASE, -2U },
4117 { X86::RAX, -2U },
4118 { X86::RBP, -2U },
4119 { X86::RBX, -2U },
4120 { X86::RCX, -2U },
4121 { X86::RDI, -2U },
4122 { X86::RDX, -2U },
4123 { X86::RFLAGS, -2U },
4124 { X86::RIP, -2U },
4125 { X86::RSI, -2U },
4126 { X86::RSP, -2U },
4127 { X86::SS, 42U },
4128 { X86::_EFLAGS, 9U },
4129 { X86::MM0, 29U },
4130 { X86::MM1, 30U },
4131 { X86::MM2, 31U },
4132 { X86::MM3, 32U },
4133 { X86::MM4, 33U },
4134 { X86::MM5, 34U },
4135 { X86::MM6, 35U },
4136 { X86::MM7, 36U },
4137 { X86::R8, -2U },
4138 { X86::R9, -2U },
4139 { X86::R10, -2U },
4140 { X86::R11, -2U },
4141 { X86::R12, -2U },
4142 { X86::R13, -2U },
4143 { X86::R14, -2U },
4144 { X86::R15, -2U },
4145 { X86::ST0, 11U },
4146 { X86::ST1, 12U },
4147 { X86::ST2, 13U },
4148 { X86::ST3, 14U },
4149 { X86::ST4, 15U },
4150 { X86::ST5, 16U },
4151 { X86::ST6, 17U },
4152 { X86::ST7, 18U },
4153 { X86::XMM0, 21U },
4154 { X86::XMM1, 22U },
4155 { X86::XMM2, 23U },
4156 { X86::XMM3, 24U },
4157 { X86::XMM4, 25U },
4158 { X86::XMM5, 26U },
4159 { X86::XMM6, 27U },
4160 { X86::XMM7, 28U },
4161 { X86::XMM8, -2U },
4162 { X86::XMM9, -2U },
4163 { X86::XMM10, -2U },
4164 { X86::XMM11, -2U },
4165 { X86::XMM12, -2U },
4166 { X86::XMM13, -2U },
4167 { X86::XMM14, -2U },
4168 { X86::XMM15, -2U },
4169 { X86::YMM0, 21U },
4170 { X86::YMM1, 22U },
4171 { X86::YMM2, 23U },
4172 { X86::YMM3, 24U },
4173 { X86::YMM4, 25U },
4174 { X86::YMM5, 26U },
4175 { X86::YMM6, 27U },
4176 { X86::YMM7, 28U },
4177 { X86::YMM8, -2U },
4178 { X86::YMM9, -2U },
4179 { X86::YMM10, -2U },
4180 { X86::YMM11, -2U },
4181 { X86::YMM12, -2U },
4182 { X86::YMM13, -2U },
4183 { X86::YMM14, -2U },
4184 { X86::YMM15, -2U },
4185 { X86::K0, 93U },
4186 { X86::K1, 94U },
4187 { X86::K2, 95U },
4188 { X86::K3, 96U },
4189 { X86::K4, 97U },
4190 { X86::K5, 98U },
4191 { X86::K6, 99U },
4192 { X86::K7, 100U },
4193 { X86::XMM16, -2U },
4194 { X86::XMM17, -2U },
4195 { X86::XMM18, -2U },
4196 { X86::XMM19, -2U },
4197 { X86::XMM20, -2U },
4198 { X86::XMM21, -2U },
4199 { X86::XMM22, -2U },
4200 { X86::XMM23, -2U },
4201 { X86::XMM24, -2U },
4202 { X86::XMM25, -2U },
4203 { X86::XMM26, -2U },
4204 { X86::XMM27, -2U },
4205 { X86::XMM28, -2U },
4206 { X86::XMM29, -2U },
4207 { X86::XMM30, -2U },
4208 { X86::XMM31, -2U },
4209 { X86::YMM16, -2U },
4210 { X86::YMM17, -2U },
4211 { X86::YMM18, -2U },
4212 { X86::YMM19, -2U },
4213 { X86::YMM20, -2U },
4214 { X86::YMM21, -2U },
4215 { X86::YMM22, -2U },
4216 { X86::YMM23, -2U },
4217 { X86::YMM24, -2U },
4218 { X86::YMM25, -2U },
4219 { X86::YMM26, -2U },
4220 { X86::YMM27, -2U },
4221 { X86::YMM28, -2U },
4222 { X86::YMM29, -2U },
4223 { X86::YMM30, -2U },
4224 { X86::YMM31, -2U },
4225 { X86::ZMM0, 21U },
4226 { X86::ZMM1, 22U },
4227 { X86::ZMM2, 23U },
4228 { X86::ZMM3, 24U },
4229 { X86::ZMM4, 25U },
4230 { X86::ZMM5, 26U },
4231 { X86::ZMM6, 27U },
4232 { X86::ZMM7, 28U },
4233 { X86::ZMM8, -2U },
4234 { X86::ZMM9, -2U },
4235 { X86::ZMM10, -2U },
4236 { X86::ZMM11, -2U },
4237 { X86::ZMM12, -2U },
4238 { X86::ZMM13, -2U },
4239 { X86::ZMM14, -2U },
4240 { X86::ZMM15, -2U },
4241 { X86::ZMM16, -2U },
4242 { X86::ZMM17, -2U },
4243 { X86::ZMM18, -2U },
4244 { X86::ZMM19, -2U },
4245 { X86::ZMM20, -2U },
4246 { X86::ZMM21, -2U },
4247 { X86::ZMM22, -2U },
4248 { X86::ZMM23, -2U },
4249 { X86::ZMM24, -2U },
4250 { X86::ZMM25, -2U },
4251 { X86::ZMM26, -2U },
4252 { X86::ZMM27, -2U },
4253 { X86::ZMM28, -2U },
4254 { X86::ZMM29, -2U },
4255 { X86::ZMM30, -2U },
4256 { X86::ZMM31, -2U },
4257 { X86::R16, -2U },
4258 { X86::R17, -2U },
4259 { X86::R18, -2U },
4260 { X86::R19, -2U },
4261 { X86::R20, -2U },
4262 { X86::R21, -2U },
4263 { X86::R22, -2U },
4264 { X86::R23, -2U },
4265 { X86::R24, -2U },
4266 { X86::R25, -2U },
4267 { X86::R26, -2U },
4268 { X86::R27, -2U },
4269 { X86::R28, -2U },
4270 { X86::R29, -2U },
4271 { X86::R30, -2U },
4272 { X86::R31, -2U },
4273};
4274extern const unsigned X86DwarfFlavour2L2DwarfSize = std::size(X86DwarfFlavour2L2Dwarf);
4275
4276extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour0L2Dwarf[] = {
4277 { X86::CS, 51U },
4278 { X86::DS, 53U },
4279 { X86::EAX, -2U },
4280 { X86::EBP, -2U },
4281 { X86::EBX, -2U },
4282 { X86::ECX, -2U },
4283 { X86::EDI, -2U },
4284 { X86::EDX, -2U },
4285 { X86::EFLAGS, 49U },
4286 { X86::EIP, -2U },
4287 { X86::ES, 50U },
4288 { X86::ESI, -2U },
4289 { X86::ESP, -2U },
4290 { X86::FS, 54U },
4291 { X86::FS_BASE, 58U },
4292 { X86::GS, 55U },
4293 { X86::GS_BASE, 59U },
4294 { X86::RAX, 0U },
4295 { X86::RBP, 6U },
4296 { X86::RBX, 3U },
4297 { X86::RCX, 2U },
4298 { X86::RDI, 5U },
4299 { X86::RDX, 1U },
4300 { X86::RFLAGS, 49U },
4301 { X86::RIP, 16U },
4302 { X86::RSI, 4U },
4303 { X86::RSP, 7U },
4304 { X86::SS, 52U },
4305 { X86::_EFLAGS, 49U },
4306 { X86::MM0, 41U },
4307 { X86::MM1, 42U },
4308 { X86::MM2, 43U },
4309 { X86::MM3, 44U },
4310 { X86::MM4, 45U },
4311 { X86::MM5, 46U },
4312 { X86::MM6, 47U },
4313 { X86::MM7, 48U },
4314 { X86::R8, 8U },
4315 { X86::R9, 9U },
4316 { X86::R10, 10U },
4317 { X86::R11, 11U },
4318 { X86::R12, 12U },
4319 { X86::R13, 13U },
4320 { X86::R14, 14U },
4321 { X86::R15, 15U },
4322 { X86::ST0, 33U },
4323 { X86::ST1, 34U },
4324 { X86::ST2, 35U },
4325 { X86::ST3, 36U },
4326 { X86::ST4, 37U },
4327 { X86::ST5, 38U },
4328 { X86::ST6, 39U },
4329 { X86::ST7, 40U },
4330 { X86::XMM0, 17U },
4331 { X86::XMM1, 18U },
4332 { X86::XMM2, 19U },
4333 { X86::XMM3, 20U },
4334 { X86::XMM4, 21U },
4335 { X86::XMM5, 22U },
4336 { X86::XMM6, 23U },
4337 { X86::XMM7, 24U },
4338 { X86::XMM8, 25U },
4339 { X86::XMM9, 26U },
4340 { X86::XMM10, 27U },
4341 { X86::XMM11, 28U },
4342 { X86::XMM12, 29U },
4343 { X86::XMM13, 30U },
4344 { X86::XMM14, 31U },
4345 { X86::XMM15, 32U },
4346 { X86::YMM0, 17U },
4347 { X86::YMM1, 18U },
4348 { X86::YMM2, 19U },
4349 { X86::YMM3, 20U },
4350 { X86::YMM4, 21U },
4351 { X86::YMM5, 22U },
4352 { X86::YMM6, 23U },
4353 { X86::YMM7, 24U },
4354 { X86::YMM8, 25U },
4355 { X86::YMM9, 26U },
4356 { X86::YMM10, 27U },
4357 { X86::YMM11, 28U },
4358 { X86::YMM12, 29U },
4359 { X86::YMM13, 30U },
4360 { X86::YMM14, 31U },
4361 { X86::YMM15, 32U },
4362 { X86::K0, 118U },
4363 { X86::K1, 119U },
4364 { X86::K2, 120U },
4365 { X86::K3, 121U },
4366 { X86::K4, 122U },
4367 { X86::K5, 123U },
4368 { X86::K6, 124U },
4369 { X86::K7, 125U },
4370 { X86::XMM16, 67U },
4371 { X86::XMM17, 68U },
4372 { X86::XMM18, 69U },
4373 { X86::XMM19, 70U },
4374 { X86::XMM20, 71U },
4375 { X86::XMM21, 72U },
4376 { X86::XMM22, 73U },
4377 { X86::XMM23, 74U },
4378 { X86::XMM24, 75U },
4379 { X86::XMM25, 76U },
4380 { X86::XMM26, 77U },
4381 { X86::XMM27, 78U },
4382 { X86::XMM28, 79U },
4383 { X86::XMM29, 80U },
4384 { X86::XMM30, 81U },
4385 { X86::XMM31, 82U },
4386 { X86::YMM16, 67U },
4387 { X86::YMM17, 68U },
4388 { X86::YMM18, 69U },
4389 { X86::YMM19, 70U },
4390 { X86::YMM20, 71U },
4391 { X86::YMM21, 72U },
4392 { X86::YMM22, 73U },
4393 { X86::YMM23, 74U },
4394 { X86::YMM24, 75U },
4395 { X86::YMM25, 76U },
4396 { X86::YMM26, 77U },
4397 { X86::YMM27, 78U },
4398 { X86::YMM28, 79U },
4399 { X86::YMM29, 80U },
4400 { X86::YMM30, 81U },
4401 { X86::YMM31, 82U },
4402 { X86::ZMM0, 17U },
4403 { X86::ZMM1, 18U },
4404 { X86::ZMM2, 19U },
4405 { X86::ZMM3, 20U },
4406 { X86::ZMM4, 21U },
4407 { X86::ZMM5, 22U },
4408 { X86::ZMM6, 23U },
4409 { X86::ZMM7, 24U },
4410 { X86::ZMM8, 25U },
4411 { X86::ZMM9, 26U },
4412 { X86::ZMM10, 27U },
4413 { X86::ZMM11, 28U },
4414 { X86::ZMM12, 29U },
4415 { X86::ZMM13, 30U },
4416 { X86::ZMM14, 31U },
4417 { X86::ZMM15, 32U },
4418 { X86::ZMM16, 67U },
4419 { X86::ZMM17, 68U },
4420 { X86::ZMM18, 69U },
4421 { X86::ZMM19, 70U },
4422 { X86::ZMM20, 71U },
4423 { X86::ZMM21, 72U },
4424 { X86::ZMM22, 73U },
4425 { X86::ZMM23, 74U },
4426 { X86::ZMM24, 75U },
4427 { X86::ZMM25, 76U },
4428 { X86::ZMM26, 77U },
4429 { X86::ZMM27, 78U },
4430 { X86::ZMM28, 79U },
4431 { X86::ZMM29, 80U },
4432 { X86::ZMM30, 81U },
4433 { X86::ZMM31, 82U },
4434 { X86::R16, 130U },
4435 { X86::R17, 131U },
4436 { X86::R18, 132U },
4437 { X86::R19, 133U },
4438 { X86::R20, 134U },
4439 { X86::R21, 135U },
4440 { X86::R22, 136U },
4441 { X86::R23, 137U },
4442 { X86::R24, 138U },
4443 { X86::R25, 139U },
4444 { X86::R26, 140U },
4445 { X86::R27, 141U },
4446 { X86::R28, 142U },
4447 { X86::R29, 143U },
4448 { X86::R30, 144U },
4449 { X86::R31, 145U },
4450};
4451extern const unsigned X86EHFlavour0L2DwarfSize = std::size(X86EHFlavour0L2Dwarf);
4452
4453extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour1L2Dwarf[] = {
4454 { X86::CS, -2U },
4455 { X86::DS, -2U },
4456 { X86::EAX, 0U },
4457 { X86::EBP, 4U },
4458 { X86::EBX, 3U },
4459 { X86::ECX, 1U },
4460 { X86::EDI, 7U },
4461 { X86::EDX, 2U },
4462 { X86::EFLAGS, 9U },
4463 { X86::EIP, 8U },
4464 { X86::ES, -2U },
4465 { X86::ESI, 6U },
4466 { X86::ESP, 5U },
4467 { X86::FS, -2U },
4468 { X86::FS_BASE, -2U },
4469 { X86::GS, -2U },
4470 { X86::GS_BASE, -2U },
4471 { X86::RAX, -2U },
4472 { X86::RBP, -2U },
4473 { X86::RBX, -2U },
4474 { X86::RCX, -2U },
4475 { X86::RDI, -2U },
4476 { X86::RDX, -2U },
4477 { X86::RFLAGS, -2U },
4478 { X86::RIP, -2U },
4479 { X86::RSI, -2U },
4480 { X86::RSP, -2U },
4481 { X86::SS, -2U },
4482 { X86::_EFLAGS, 9U },
4483 { X86::MM0, 29U },
4484 { X86::MM1, 30U },
4485 { X86::MM2, 31U },
4486 { X86::MM3, 32U },
4487 { X86::MM4, 33U },
4488 { X86::MM5, 34U },
4489 { X86::MM6, 35U },
4490 { X86::MM7, 36U },
4491 { X86::R8, -2U },
4492 { X86::R9, -2U },
4493 { X86::R10, -2U },
4494 { X86::R11, -2U },
4495 { X86::R12, -2U },
4496 { X86::R13, -2U },
4497 { X86::R14, -2U },
4498 { X86::R15, -2U },
4499 { X86::ST0, 12U },
4500 { X86::ST1, 13U },
4501 { X86::ST2, 14U },
4502 { X86::ST3, 15U },
4503 { X86::ST4, 16U },
4504 { X86::ST5, 17U },
4505 { X86::ST6, 18U },
4506 { X86::ST7, 19U },
4507 { X86::XMM0, 21U },
4508 { X86::XMM1, 22U },
4509 { X86::XMM2, 23U },
4510 { X86::XMM3, 24U },
4511 { X86::XMM4, 25U },
4512 { X86::XMM5, 26U },
4513 { X86::XMM6, 27U },
4514 { X86::XMM7, 28U },
4515 { X86::XMM8, -2U },
4516 { X86::XMM9, -2U },
4517 { X86::XMM10, -2U },
4518 { X86::XMM11, -2U },
4519 { X86::XMM12, -2U },
4520 { X86::XMM13, -2U },
4521 { X86::XMM14, -2U },
4522 { X86::XMM15, -2U },
4523 { X86::YMM0, 21U },
4524 { X86::YMM1, 22U },
4525 { X86::YMM2, 23U },
4526 { X86::YMM3, 24U },
4527 { X86::YMM4, 25U },
4528 { X86::YMM5, 26U },
4529 { X86::YMM6, 27U },
4530 { X86::YMM7, 28U },
4531 { X86::YMM8, -2U },
4532 { X86::YMM9, -2U },
4533 { X86::YMM10, -2U },
4534 { X86::YMM11, -2U },
4535 { X86::YMM12, -2U },
4536 { X86::YMM13, -2U },
4537 { X86::YMM14, -2U },
4538 { X86::YMM15, -2U },
4539 { X86::K0, 93U },
4540 { X86::K1, 94U },
4541 { X86::K2, 95U },
4542 { X86::K3, 96U },
4543 { X86::K4, 97U },
4544 { X86::K5, 98U },
4545 { X86::K6, 99U },
4546 { X86::K7, 100U },
4547 { X86::XMM16, -2U },
4548 { X86::XMM17, -2U },
4549 { X86::XMM18, -2U },
4550 { X86::XMM19, -2U },
4551 { X86::XMM20, -2U },
4552 { X86::XMM21, -2U },
4553 { X86::XMM22, -2U },
4554 { X86::XMM23, -2U },
4555 { X86::XMM24, -2U },
4556 { X86::XMM25, -2U },
4557 { X86::XMM26, -2U },
4558 { X86::XMM27, -2U },
4559 { X86::XMM28, -2U },
4560 { X86::XMM29, -2U },
4561 { X86::XMM30, -2U },
4562 { X86::XMM31, -2U },
4563 { X86::YMM16, -2U },
4564 { X86::YMM17, -2U },
4565 { X86::YMM18, -2U },
4566 { X86::YMM19, -2U },
4567 { X86::YMM20, -2U },
4568 { X86::YMM21, -2U },
4569 { X86::YMM22, -2U },
4570 { X86::YMM23, -2U },
4571 { X86::YMM24, -2U },
4572 { X86::YMM25, -2U },
4573 { X86::YMM26, -2U },
4574 { X86::YMM27, -2U },
4575 { X86::YMM28, -2U },
4576 { X86::YMM29, -2U },
4577 { X86::YMM30, -2U },
4578 { X86::YMM31, -2U },
4579 { X86::ZMM0, 21U },
4580 { X86::ZMM1, 22U },
4581 { X86::ZMM2, 23U },
4582 { X86::ZMM3, 24U },
4583 { X86::ZMM4, 25U },
4584 { X86::ZMM5, 26U },
4585 { X86::ZMM6, 27U },
4586 { X86::ZMM7, 28U },
4587 { X86::ZMM8, -2U },
4588 { X86::ZMM9, -2U },
4589 { X86::ZMM10, -2U },
4590 { X86::ZMM11, -2U },
4591 { X86::ZMM12, -2U },
4592 { X86::ZMM13, -2U },
4593 { X86::ZMM14, -2U },
4594 { X86::ZMM15, -2U },
4595 { X86::ZMM16, -2U },
4596 { X86::ZMM17, -2U },
4597 { X86::ZMM18, -2U },
4598 { X86::ZMM19, -2U },
4599 { X86::ZMM20, -2U },
4600 { X86::ZMM21, -2U },
4601 { X86::ZMM22, -2U },
4602 { X86::ZMM23, -2U },
4603 { X86::ZMM24, -2U },
4604 { X86::ZMM25, -2U },
4605 { X86::ZMM26, -2U },
4606 { X86::ZMM27, -2U },
4607 { X86::ZMM28, -2U },
4608 { X86::ZMM29, -2U },
4609 { X86::ZMM30, -2U },
4610 { X86::ZMM31, -2U },
4611 { X86::R16, -2U },
4612 { X86::R17, -2U },
4613 { X86::R18, -2U },
4614 { X86::R19, -2U },
4615 { X86::R20, -2U },
4616 { X86::R21, -2U },
4617 { X86::R22, -2U },
4618 { X86::R23, -2U },
4619 { X86::R24, -2U },
4620 { X86::R25, -2U },
4621 { X86::R26, -2U },
4622 { X86::R27, -2U },
4623 { X86::R28, -2U },
4624 { X86::R29, -2U },
4625 { X86::R30, -2U },
4626 { X86::R31, -2U },
4627};
4628extern const unsigned X86EHFlavour1L2DwarfSize = std::size(X86EHFlavour1L2Dwarf);
4629
4630extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour2L2Dwarf[] = {
4631 { X86::CS, 41U },
4632 { X86::DS, 43U },
4633 { X86::EAX, 0U },
4634 { X86::EBP, 5U },
4635 { X86::EBX, 3U },
4636 { X86::ECX, 1U },
4637 { X86::EDI, 7U },
4638 { X86::EDX, 2U },
4639 { X86::EFLAGS, 9U },
4640 { X86::EIP, 8U },
4641 { X86::ES, 40U },
4642 { X86::ESI, 6U },
4643 { X86::ESP, 4U },
4644 { X86::FS, 44U },
4645 { X86::FS_BASE, -2U },
4646 { X86::GS, 45U },
4647 { X86::GS_BASE, -2U },
4648 { X86::RAX, -2U },
4649 { X86::RBP, -2U },
4650 { X86::RBX, -2U },
4651 { X86::RCX, -2U },
4652 { X86::RDI, -2U },
4653 { X86::RDX, -2U },
4654 { X86::RFLAGS, -2U },
4655 { X86::RIP, -2U },
4656 { X86::RSI, -2U },
4657 { X86::RSP, -2U },
4658 { X86::SS, 42U },
4659 { X86::_EFLAGS, 9U },
4660 { X86::MM0, 29U },
4661 { X86::MM1, 30U },
4662 { X86::MM2, 31U },
4663 { X86::MM3, 32U },
4664 { X86::MM4, 33U },
4665 { X86::MM5, 34U },
4666 { X86::MM6, 35U },
4667 { X86::MM7, 36U },
4668 { X86::R8, -2U },
4669 { X86::R9, -2U },
4670 { X86::R10, -2U },
4671 { X86::R11, -2U },
4672 { X86::R12, -2U },
4673 { X86::R13, -2U },
4674 { X86::R14, -2U },
4675 { X86::R15, -2U },
4676 { X86::ST0, 11U },
4677 { X86::ST1, 12U },
4678 { X86::ST2, 13U },
4679 { X86::ST3, 14U },
4680 { X86::ST4, 15U },
4681 { X86::ST5, 16U },
4682 { X86::ST6, 17U },
4683 { X86::ST7, 18U },
4684 { X86::XMM0, 21U },
4685 { X86::XMM1, 22U },
4686 { X86::XMM2, 23U },
4687 { X86::XMM3, 24U },
4688 { X86::XMM4, 25U },
4689 { X86::XMM5, 26U },
4690 { X86::XMM6, 27U },
4691 { X86::XMM7, 28U },
4692 { X86::XMM8, -2U },
4693 { X86::XMM9, -2U },
4694 { X86::XMM10, -2U },
4695 { X86::XMM11, -2U },
4696 { X86::XMM12, -2U },
4697 { X86::XMM13, -2U },
4698 { X86::XMM14, -2U },
4699 { X86::XMM15, -2U },
4700 { X86::YMM0, 21U },
4701 { X86::YMM1, 22U },
4702 { X86::YMM2, 23U },
4703 { X86::YMM3, 24U },
4704 { X86::YMM4, 25U },
4705 { X86::YMM5, 26U },
4706 { X86::YMM6, 27U },
4707 { X86::YMM7, 28U },
4708 { X86::YMM8, -2U },
4709 { X86::YMM9, -2U },
4710 { X86::YMM10, -2U },
4711 { X86::YMM11, -2U },
4712 { X86::YMM12, -2U },
4713 { X86::YMM13, -2U },
4714 { X86::YMM14, -2U },
4715 { X86::YMM15, -2U },
4716 { X86::K0, 93U },
4717 { X86::K1, 94U },
4718 { X86::K2, 95U },
4719 { X86::K3, 96U },
4720 { X86::K4, 97U },
4721 { X86::K5, 98U },
4722 { X86::K6, 99U },
4723 { X86::K7, 100U },
4724 { X86::XMM16, -2U },
4725 { X86::XMM17, -2U },
4726 { X86::XMM18, -2U },
4727 { X86::XMM19, -2U },
4728 { X86::XMM20, -2U },
4729 { X86::XMM21, -2U },
4730 { X86::XMM22, -2U },
4731 { X86::XMM23, -2U },
4732 { X86::XMM24, -2U },
4733 { X86::XMM25, -2U },
4734 { X86::XMM26, -2U },
4735 { X86::XMM27, -2U },
4736 { X86::XMM28, -2U },
4737 { X86::XMM29, -2U },
4738 { X86::XMM30, -2U },
4739 { X86::XMM31, -2U },
4740 { X86::YMM16, -2U },
4741 { X86::YMM17, -2U },
4742 { X86::YMM18, -2U },
4743 { X86::YMM19, -2U },
4744 { X86::YMM20, -2U },
4745 { X86::YMM21, -2U },
4746 { X86::YMM22, -2U },
4747 { X86::YMM23, -2U },
4748 { X86::YMM24, -2U },
4749 { X86::YMM25, -2U },
4750 { X86::YMM26, -2U },
4751 { X86::YMM27, -2U },
4752 { X86::YMM28, -2U },
4753 { X86::YMM29, -2U },
4754 { X86::YMM30, -2U },
4755 { X86::YMM31, -2U },
4756 { X86::ZMM0, 21U },
4757 { X86::ZMM1, 22U },
4758 { X86::ZMM2, 23U },
4759 { X86::ZMM3, 24U },
4760 { X86::ZMM4, 25U },
4761 { X86::ZMM5, 26U },
4762 { X86::ZMM6, 27U },
4763 { X86::ZMM7, 28U },
4764 { X86::ZMM8, -2U },
4765 { X86::ZMM9, -2U },
4766 { X86::ZMM10, -2U },
4767 { X86::ZMM11, -2U },
4768 { X86::ZMM12, -2U },
4769 { X86::ZMM13, -2U },
4770 { X86::ZMM14, -2U },
4771 { X86::ZMM15, -2U },
4772 { X86::ZMM16, -2U },
4773 { X86::ZMM17, -2U },
4774 { X86::ZMM18, -2U },
4775 { X86::ZMM19, -2U },
4776 { X86::ZMM20, -2U },
4777 { X86::ZMM21, -2U },
4778 { X86::ZMM22, -2U },
4779 { X86::ZMM23, -2U },
4780 { X86::ZMM24, -2U },
4781 { X86::ZMM25, -2U },
4782 { X86::ZMM26, -2U },
4783 { X86::ZMM27, -2U },
4784 { X86::ZMM28, -2U },
4785 { X86::ZMM29, -2U },
4786 { X86::ZMM30, -2U },
4787 { X86::ZMM31, -2U },
4788 { X86::R16, -2U },
4789 { X86::R17, -2U },
4790 { X86::R18, -2U },
4791 { X86::R19, -2U },
4792 { X86::R20, -2U },
4793 { X86::R21, -2U },
4794 { X86::R22, -2U },
4795 { X86::R23, -2U },
4796 { X86::R24, -2U },
4797 { X86::R25, -2U },
4798 { X86::R26, -2U },
4799 { X86::R27, -2U },
4800 { X86::R28, -2U },
4801 { X86::R29, -2U },
4802 { X86::R30, -2U },
4803 { X86::R31, -2U },
4804};
4805extern const unsigned X86EHFlavour2L2DwarfSize = std::size(X86EHFlavour2L2Dwarf);
4806
4807extern const uint16_t X86RegEncodingTable[] = {
4808 0,
4809 4,
4810 0,
4811 0,
4812 7,
4813 3,
4814 5,
4815 65535,
4816 5,
4817 3,
4818 5,
4819 1,
4820 1,
4821 1,
4822 0,
4823 6,
4824 7,
4825 65535,
4826 7,
4827 2,
4828 3,
4829 2,
4830 0,
4831 5,
4832 3,
4833 1,
4834 7,
4835 2,
4836 0,
4837 0,
4838 4,
4839 0,
4840 6,
4841 4,
4842 0,
4843 0,
4844 4,
4845 0,
4846 5,
4847 0,
4848 65535,
4849 65535,
4850 65535,
4851 65535,
4852 65535,
4853 65535,
4854 65535,
4855 65535,
4856 65535,
4857 0,
4858 0,
4859 0,
4860 5,
4861 3,
4862 1,
4863 7,
4864 2,
4865 0,
4866 0,
4867 4,
4868 6,
4869 4,
4870 6,
4871 65535,
4872 6,
4873 4,
4874 65535,
4875 4,
4876 2,
4877 0,
4878 0,
4879 0,
4880 1,
4881 2,
4882 3,
4883 4,
4884 5,
4885 6,
4886 7,
4887 8,
4888 9,
4889 10,
4890 11,
4891 12,
4892 13,
4893 14,
4894 15,
4895 0,
4896 1,
4897 2,
4898 3,
4899 4,
4900 5,
4901 6,
4902 7,
4903 8,
4904 9,
4905 10,
4906 11,
4907 12,
4908 13,
4909 14,
4910 15,
4911 0,
4912 0,
4913 0,
4914 0,
4915 0,
4916 0,
4917 0,
4918 0,
4919 0,
4920 1,
4921 2,
4922 3,
4923 4,
4924 5,
4925 6,
4926 7,
4927 8,
4928 9,
4929 10,
4930 11,
4931 12,
4932 13,
4933 14,
4934 15,
4935 0,
4936 1,
4937 2,
4938 3,
4939 4,
4940 5,
4941 6,
4942 7,
4943 0,
4944 1,
4945 2,
4946 3,
4947 4,
4948 5,
4949 6,
4950 7,
4951 8,
4952 9,
4953 10,
4954 11,
4955 12,
4956 13,
4957 14,
4958 15,
4959 8,
4960 9,
4961 10,
4962 11,
4963 12,
4964 13,
4965 14,
4966 15,
4967 65535,
4968 65535,
4969 65535,
4970 65535,
4971 65535,
4972 65535,
4973 65535,
4974 65535,
4975 8,
4976 9,
4977 10,
4978 11,
4979 12,
4980 13,
4981 14,
4982 15,
4983 8,
4984 9,
4985 10,
4986 11,
4987 12,
4988 13,
4989 14,
4990 15,
4991 65535,
4992 65535,
4993 65535,
4994 65535,
4995 65535,
4996 65535,
4997 65535,
4998 65535,
4999 0,
5000 1,
5001 2,
5002 3,
5003 4,
5004 5,
5005 6,
5006 7,
5007 8,
5008 9,
5009 10,
5010 11,
5011 12,
5012 13,
5013 14,
5014 15,
5015 0,
5016 1,
5017 2,
5018 3,
5019 4,
5020 5,
5021 6,
5022 7,
5023 16,
5024 17,
5025 18,
5026 19,
5027 20,
5028 21,
5029 22,
5030 23,
5031 24,
5032 25,
5033 26,
5034 27,
5035 28,
5036 29,
5037 30,
5038 31,
5039 16,
5040 17,
5041 18,
5042 19,
5043 20,
5044 21,
5045 22,
5046 23,
5047 24,
5048 25,
5049 26,
5050 27,
5051 28,
5052 29,
5053 30,
5054 31,
5055 0,
5056 1,
5057 2,
5058 3,
5059 4,
5060 5,
5061 6,
5062 7,
5063 8,
5064 9,
5065 10,
5066 11,
5067 12,
5068 13,
5069 14,
5070 15,
5071 16,
5072 17,
5073 18,
5074 19,
5075 20,
5076 21,
5077 22,
5078 23,
5079 24,
5080 25,
5081 26,
5082 27,
5083 28,
5084 29,
5085 30,
5086 31,
5087 0,
5088 2,
5089 4,
5090 6,
5091 0,
5092 0,
5093 1,
5094 2,
5095 3,
5096 4,
5097 5,
5098 6,
5099 7,
5100 0,
5101 2,
5102 4,
5103 6,
5104 16,
5105 17,
5106 18,
5107 19,
5108 20,
5109 21,
5110 22,
5111 23,
5112 24,
5113 25,
5114 26,
5115 27,
5116 28,
5117 29,
5118 30,
5119 31,
5120 16,
5121 17,
5122 18,
5123 19,
5124 20,
5125 21,
5126 22,
5127 23,
5128 24,
5129 25,
5130 26,
5131 27,
5132 28,
5133 29,
5134 30,
5135 31,
5136 65535,
5137 65535,
5138 65535,
5139 65535,
5140 65535,
5141 65535,
5142 65535,
5143 65535,
5144 65535,
5145 65535,
5146 65535,
5147 65535,
5148 65535,
5149 65535,
5150 65535,
5151 65535,
5152 16,
5153 17,
5154 18,
5155 19,
5156 20,
5157 21,
5158 22,
5159 23,
5160 24,
5161 25,
5162 26,
5163 27,
5164 28,
5165 29,
5166 30,
5167 31,
5168 16,
5169 17,
5170 18,
5171 19,
5172 20,
5173 21,
5174 22,
5175 23,
5176 24,
5177 25,
5178 26,
5179 27,
5180 28,
5181 29,
5182 30,
5183 31,
5184 65535,
5185 65535,
5186 65535,
5187 65535,
5188 65535,
5189 65535,
5190 65535,
5191 65535,
5192 65535,
5193 65535,
5194 65535,
5195 65535,
5196 65535,
5197 65535,
5198 65535,
5199 65535,
5200};
5201static inline void InitX86MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
5202 RI->InitMCRegisterInfo(X86RegDesc, 392, RA, PC, X86MCRegisterClasses, 136, X86RegUnitRoots, 221, X86RegDiffLists, X86LaneMaskLists, X86RegStrings, X86RegClassStrings, X86SubRegIdxLists, 13,
5203X86RegEncodingTable);
5204
5205 switch (DwarfFlavour) {
5206 default:
5207 llvm_unreachable("Unknown DWARF flavour");
5208 case 0:
5209 RI->mapDwarfRegsToLLVMRegs(X86DwarfFlavour0Dwarf2L, X86DwarfFlavour0Dwarf2LSize, false);
5210 break;
5211 case 1:
5212 RI->mapDwarfRegsToLLVMRegs(X86DwarfFlavour1Dwarf2L, X86DwarfFlavour1Dwarf2LSize, false);
5213 break;
5214 case 2:
5215 RI->mapDwarfRegsToLLVMRegs(X86DwarfFlavour2Dwarf2L, X86DwarfFlavour2Dwarf2LSize, false);
5216 break;
5217 }
5218 switch (EHFlavour) {
5219 default:
5220 llvm_unreachable("Unknown DWARF flavour");
5221 case 0:
5222 RI->mapDwarfRegsToLLVMRegs(X86EHFlavour0Dwarf2L, X86EHFlavour0Dwarf2LSize, true);
5223 break;
5224 case 1:
5225 RI->mapDwarfRegsToLLVMRegs(X86EHFlavour1Dwarf2L, X86EHFlavour1Dwarf2LSize, true);
5226 break;
5227 case 2:
5228 RI->mapDwarfRegsToLLVMRegs(X86EHFlavour2Dwarf2L, X86EHFlavour2Dwarf2LSize, true);
5229 break;
5230 }
5231 switch (DwarfFlavour) {
5232 default:
5233 llvm_unreachable("Unknown DWARF flavour");
5234 case 0:
5235 RI->mapLLVMRegsToDwarfRegs(X86DwarfFlavour0L2Dwarf, X86DwarfFlavour0L2DwarfSize, false);
5236 break;
5237 case 1:
5238 RI->mapLLVMRegsToDwarfRegs(X86DwarfFlavour1L2Dwarf, X86DwarfFlavour1L2DwarfSize, false);
5239 break;
5240 case 2:
5241 RI->mapLLVMRegsToDwarfRegs(X86DwarfFlavour2L2Dwarf, X86DwarfFlavour2L2DwarfSize, false);
5242 break;
5243 }
5244 switch (EHFlavour) {
5245 default:
5246 llvm_unreachable("Unknown DWARF flavour");
5247 case 0:
5248 RI->mapLLVMRegsToDwarfRegs(X86EHFlavour0L2Dwarf, X86EHFlavour0L2DwarfSize, true);
5249 break;
5250 case 1:
5251 RI->mapLLVMRegsToDwarfRegs(X86EHFlavour1L2Dwarf, X86EHFlavour1L2DwarfSize, true);
5252 break;
5253 case 2:
5254 RI->mapLLVMRegsToDwarfRegs(X86EHFlavour2L2Dwarf, X86EHFlavour2L2DwarfSize, true);
5255 break;
5256 }
5257}
5258
5259} // end namespace llvm
5260
5261#endif // GET_REGINFO_MC_DESC
5262
5263/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
5264|* *|
5265|* Register Information Header Fragment *|
5266|* *|
5267|* Automatically generated file, do not edit! *|
5268|* *|
5269\*===----------------------------------------------------------------------===*/
5270
5271
5272#ifdef GET_REGINFO_HEADER
5273#undef GET_REGINFO_HEADER
5274
5275#include "llvm/CodeGen/TargetRegisterInfo.h"
5276
5277namespace llvm {
5278
5279class X86FrameLowering;
5280
5281struct X86GenRegisterInfo : public TargetRegisterInfo {
5282 explicit X86GenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
5283 unsigned PC = 0, unsigned HwMode = 0);
5284 unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
5285 unsigned reverseComposeSubRegIndicesImpl(unsigned, unsigned) const override;
5286 LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
5287 LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
5288 const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass *, unsigned) const override;
5289 const TargetRegisterClass *getSubRegisterClass(const TargetRegisterClass *, unsigned) const override;
5290 const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
5291 unsigned getRegUnitWeight(unsigned RegUnit) const override;
5292 unsigned getNumRegPressureSets() const override;
5293 const char *getRegPressureSetName(unsigned Idx) const override;
5294 unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
5295 const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
5296 const int *getRegUnitPressureSets(unsigned RegUnit) const override;
5297 ArrayRef<const char *> getRegMaskNames() const override;
5298 ArrayRef<const uint32_t *> getRegMasks() const override;
5299 bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override;
5300 bool isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const override;
5301 bool isFixedRegister(const MachineFunction &, MCRegister) const override;
5302 bool isArgumentRegister(const MachineFunction &, MCRegister) const override;
5303 bool isConstantPhysReg(MCRegister PhysReg) const override final;
5304 /// Devirtualized TargetFrameLowering.
5305 static const X86FrameLowering *getFrameLowering(
5306 const MachineFunction &MF);
5307};
5308
5309namespace X86 { // Register classes
5310 extern const TargetRegisterClass GR8RegClass;
5311 extern const TargetRegisterClass GRH8RegClass;
5312 extern const TargetRegisterClass GR8_NOREX2RegClass;
5313 extern const TargetRegisterClass GR8_NOREXRegClass;
5314 extern const TargetRegisterClass GR8_ABCD_HRegClass;
5315 extern const TargetRegisterClass GR8_ABCD_LRegClass;
5316 extern const TargetRegisterClass GRH16RegClass;
5317 extern const TargetRegisterClass GR16RegClass;
5318 extern const TargetRegisterClass GR16_NOREX2RegClass;
5319 extern const TargetRegisterClass GR16_NOREXRegClass;
5320 extern const TargetRegisterClass VK1RegClass;
5321 extern const TargetRegisterClass VK16RegClass;
5322 extern const TargetRegisterClass VK2RegClass;
5323 extern const TargetRegisterClass VK4RegClass;
5324 extern const TargetRegisterClass VK8RegClass;
5325 extern const TargetRegisterClass VK16WMRegClass;
5326 extern const TargetRegisterClass VK1WMRegClass;
5327 extern const TargetRegisterClass VK2WMRegClass;
5328 extern const TargetRegisterClass VK4WMRegClass;
5329 extern const TargetRegisterClass VK8WMRegClass;
5330 extern const TargetRegisterClass SEGMENT_REGRegClass;
5331 extern const TargetRegisterClass GR16_ABCDRegClass;
5332 extern const TargetRegisterClass FPCCRRegClass;
5333 extern const TargetRegisterClass FR16XRegClass;
5334 extern const TargetRegisterClass FR16RegClass;
5335 extern const TargetRegisterClass VK16PAIRRegClass;
5336 extern const TargetRegisterClass VK1PAIRRegClass;
5337 extern const TargetRegisterClass VK2PAIRRegClass;
5338 extern const TargetRegisterClass VK4PAIRRegClass;
5339 extern const TargetRegisterClass VK8PAIRRegClass;
5340 extern const TargetRegisterClass VK1PAIR_with_sub_mask_0_in_VK1WMRegClass;
5341 extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBPRegClass;
5342 extern const TargetRegisterClass LOW32_ADDR_ACCESSRegClass;
5343 extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass;
5344 extern const TargetRegisterClass FR32XRegClass;
5345 extern const TargetRegisterClass GR32RegClass;
5346 extern const TargetRegisterClass GR32_NOSPRegClass;
5347 extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClass;
5348 extern const TargetRegisterClass DEBUG_REGRegClass;
5349 extern const TargetRegisterClass FR32RegClass;
5350 extern const TargetRegisterClass GR32_NOREX2RegClass;
5351 extern const TargetRegisterClass GR32_NOREX2_NOSPRegClass;
5352 extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass;
5353 extern const TargetRegisterClass GR32_NOREXRegClass;
5354 extern const TargetRegisterClass VK32RegClass;
5355 extern const TargetRegisterClass GR32_NOREX_NOSPRegClass;
5356 extern const TargetRegisterClass RFP32RegClass;
5357 extern const TargetRegisterClass VK32WMRegClass;
5358 extern const TargetRegisterClass GR32_ABCDRegClass;
5359 extern const TargetRegisterClass GR32_TCRegClass;
5360 extern const TargetRegisterClass GR32_ABCD_and_GR32_TCRegClass;
5361 extern const TargetRegisterClass GR32_ADRegClass;
5362 extern const TargetRegisterClass GR32_ArgRefRegClass;
5363 extern const TargetRegisterClass GR32_BPSPRegClass;
5364 extern const TargetRegisterClass GR32_BSIRegClass;
5365 extern const TargetRegisterClass GR32_CBRegClass;
5366 extern const TargetRegisterClass GR32_DCRegClass;
5367 extern const TargetRegisterClass GR32_DIBPRegClass;
5368 extern const TargetRegisterClass GR32_SIDIRegClass;
5369 extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass;
5370 extern const TargetRegisterClass CCRRegClass;
5371 extern const TargetRegisterClass DFCCRRegClass;
5372 extern const TargetRegisterClass GR32_ABCD_and_GR32_BSIRegClass;
5373 extern const TargetRegisterClass GR32_AD_and_GR32_ArgRefRegClass;
5374 extern const TargetRegisterClass GR32_ArgRef_and_GR32_CBRegClass;
5375 extern const TargetRegisterClass GR32_BPSP_and_GR32_DIBPRegClass;
5376 extern const TargetRegisterClass GR32_BPSP_and_GR32_TCRegClass;
5377 extern const TargetRegisterClass GR32_BSI_and_GR32_SIDIRegClass;
5378 extern const TargetRegisterClass GR32_DIBP_and_GR32_SIDIRegClass;
5379 extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClass;
5380 extern const TargetRegisterClass LOW32_ADDR_ACCESS_with_sub_32bitRegClass;
5381 extern const TargetRegisterClass RFP64RegClass;
5382 extern const TargetRegisterClass GR64RegClass;
5383 extern const TargetRegisterClass FR64XRegClass;
5384 extern const TargetRegisterClass GR64_with_sub_8bitRegClass;
5385 extern const TargetRegisterClass GR64_NOSPRegClass;
5386 extern const TargetRegisterClass GR64_NOREX2RegClass;
5387 extern const TargetRegisterClass CONTROL_REGRegClass;
5388 extern const TargetRegisterClass FR64RegClass;
5389 extern const TargetRegisterClass GR64_with_sub_16bit_in_GR16_NOREX2RegClass;
5390 extern const TargetRegisterClass GR64_NOREX2_NOSPRegClass;
5391 extern const TargetRegisterClass GR64PLTSafeRegClass;
5392 extern const TargetRegisterClass GR64_TCRegClass;
5393 extern const TargetRegisterClass GR64_NOREXRegClass;
5394 extern const TargetRegisterClass GR64_TCW64RegClass;
5395 extern const TargetRegisterClass GR64_TC_with_sub_8bitRegClass;
5396 extern const TargetRegisterClass GR64_NOREX2_NOSP_and_GR64_TCRegClass;
5397 extern const TargetRegisterClass GR64_TCW64_with_sub_8bitRegClass;
5398 extern const TargetRegisterClass GR64_TC_and_GR64_TCW64RegClass;
5399 extern const TargetRegisterClass GR64_with_sub_16bit_in_GR16_NOREXRegClass;
5400 extern const TargetRegisterClass VK64RegClass;
5401 extern const TargetRegisterClass VR64RegClass;
5402 extern const TargetRegisterClass GR64PLTSafe_and_GR64_TCRegClass;
5403 extern const TargetRegisterClass GR64_NOREX2_NOSP_and_GR64_TCW64RegClass;
5404 extern const TargetRegisterClass GR64_NOREX_NOSPRegClass;
5405 extern const TargetRegisterClass GR64_NOREX_and_GR64_TCRegClass;
5406 extern const TargetRegisterClass GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass;
5407 extern const TargetRegisterClass VK64WMRegClass;
5408 extern const TargetRegisterClass GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClass;
5409 extern const TargetRegisterClass GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass;
5410 extern const TargetRegisterClass GR64PLTSafe_and_GR64_TCW64RegClass;
5411 extern const TargetRegisterClass GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClass;
5412 extern const TargetRegisterClass GR64_NOREX_and_GR64_TCW64RegClass;
5413 extern const TargetRegisterClass GR64_ABCDRegClass;
5414 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_TCRegClass;
5415 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClass;
5416 extern const TargetRegisterClass GR64_ADRegClass;
5417 extern const TargetRegisterClass GR64_ArgRefRegClass;
5418 extern const TargetRegisterClass GR64_and_LOW32_ADDR_ACCESS_RBPRegClass;
5419 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_ArgRefRegClass;
5420 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSPRegClass;
5421 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BSIRegClass;
5422 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_CBRegClass;
5423 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_DIBPRegClass;
5424 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_SIDIRegClass;
5425 extern const TargetRegisterClass GR64_ARegClass;
5426 extern const TargetRegisterClass GR64_ArgRef_and_GR64_TCRegClass;
5427 extern const TargetRegisterClass GR64_and_LOW32_ADDR_ACCESSRegClass;
5428 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClass;
5429 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefRegClass;
5430 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBRegClass;
5431 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClass;
5432 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClass;
5433 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClass;
5434 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClass;
5435 extern const TargetRegisterClass RSTRegClass;
5436 extern const TargetRegisterClass RFP80RegClass;
5437 extern const TargetRegisterClass RFP80_7RegClass;
5438 extern const TargetRegisterClass VR128XRegClass;
5439 extern const TargetRegisterClass VR128RegClass;
5440 extern const TargetRegisterClass VR256XRegClass;
5441 extern const TargetRegisterClass VR256RegClass;
5442 extern const TargetRegisterClass VR512RegClass;
5443 extern const TargetRegisterClass VR512_0_15RegClass;
5444 extern const TargetRegisterClass TILERegClass;
5445 extern const TargetRegisterClass TILEPAIRRegClass;
5446} // end namespace X86
5447
5448} // end namespace llvm
5449
5450#endif // GET_REGINFO_HEADER
5451
5452/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
5453|* *|
5454|* Target Register and Register Classes Information *|
5455|* *|
5456|* Automatically generated file, do not edit! *|
5457|* *|
5458\*===----------------------------------------------------------------------===*/
5459
5460
5461#ifdef GET_REGINFO_TARGET_DESC
5462#undef GET_REGINFO_TARGET_DESC
5463
5464namespace llvm {
5465
5466extern const MCRegisterClass X86MCRegisterClasses[];
5467
5468static const MVT::SimpleValueType VTLists[] = {
5469 /* 0 */ MVT::i8, MVT::Other,
5470 /* 2 */ MVT::i16, MVT::Other,
5471 /* 4 */ MVT::i32, MVT::Other,
5472 /* 6 */ MVT::i64, MVT::Other,
5473 /* 8 */ MVT::f16, MVT::Other,
5474 /* 10 */ MVT::f80, MVT::f64, MVT::f32, MVT::Other,
5475 /* 14 */ MVT::f64, MVT::Other,
5476 /* 16 */ MVT::f80, MVT::Other,
5477 /* 18 */ MVT::v4f32, MVT::v2f64, MVT::v8f16, MVT::v8bf16, MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::f128, MVT::Other,
5478 /* 28 */ MVT::v1i1, MVT::Other,
5479 /* 30 */ MVT::v2i1, MVT::Other,
5480 /* 32 */ MVT::v4i1, MVT::Other,
5481 /* 34 */ MVT::v8i1, MVT::Other,
5482 /* 36 */ MVT::v16i1, MVT::Other,
5483 /* 38 */ MVT::v32i1, MVT::Other,
5484 /* 40 */ MVT::v64i1, MVT::Other,
5485 /* 42 */ MVT::v8f32, MVT::v4f64, MVT::v16f16, MVT::v16bf16, MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64, MVT::Other,
5486 /* 51 */ MVT::v16f32, MVT::v8f64, MVT::v32f16, MVT::v32bf16, MVT::v64i8, MVT::v32i16, MVT::v16i32, MVT::v8i64, MVT::Other,
5487 /* 60 */ MVT::v16f32, MVT::v8f64, MVT::v64i8, MVT::v32i16, MVT::v16i32, MVT::v8i64, MVT::Other,
5488 /* 67 */ MVT::x86mmx, MVT::Other,
5489 /* 69 */ MVT::Untyped, MVT::Other,
5490 /* 71 */ MVT::x86amx, MVT::Other,
5491};
5492
5493static const char *SubRegIndexNameTable[] = { "sub_8bit", "sub_8bit_hi", "sub_8bit_hi_phony", "sub_16bit", "sub_16bit_hi", "sub_32bit", "sub_mask_0", "sub_mask_1", "sub_t0", "sub_t1", "sub_xmm", "sub_ymm", "" };
5494
5495static const TargetRegisterInfo::SubRegCoveredBits SubRegIdxRangeTable[] = {
5496 { 65535, 65535 },
5497 { 0, 8 }, // sub_8bit
5498 { 8, 8 }, // sub_8bit_hi
5499 { 8, 8 }, // sub_8bit_hi_phony
5500 { 0, 16 }, // sub_16bit
5501 { 16, 16 }, // sub_16bit_hi
5502 { 0, 32 }, // sub_32bit
5503 { 0, 65535 }, // sub_mask_0
5504 { 65535, 65535 }, // sub_mask_1
5505 { 0, 8192 }, // sub_t0
5506 { 8192, 8192 }, // sub_t1
5507 { 0, 128 }, // sub_xmm
5508 { 0, 256 }, // sub_ymm
5509};
5510
5511
5512static const LaneBitmask SubRegIndexLaneMaskTable[] = {
5513 LaneBitmask::getAll(),
5514 LaneBitmask(0x0000000000000001), // sub_8bit
5515 LaneBitmask(0x0000000000000002), // sub_8bit_hi
5516 LaneBitmask(0x0000000000000004), // sub_8bit_hi_phony
5517 LaneBitmask(0x0000000000000007), // sub_16bit
5518 LaneBitmask(0x0000000000000008), // sub_16bit_hi
5519 LaneBitmask(0x000000000000000F), // sub_32bit
5520 LaneBitmask(0x0000000000000010), // sub_mask_0
5521 LaneBitmask(0x0000000000000020), // sub_mask_1
5522 LaneBitmask(0x0000000000000040), // sub_t0
5523 LaneBitmask(0x0000000000000080), // sub_t1
5524 LaneBitmask(0x0000000000000100), // sub_xmm
5525 LaneBitmask(0x0000000000000100), // sub_ymm
5526 };
5527
5528
5529
5530static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
5531 // Mode = 0 (Default)
5532 { 8, 8, 8, /*VTLists+*/0 }, // GR8
5533 { 8, 8, 8, /*VTLists+*/0 }, // GRH8
5534 { 8, 8, 8, /*VTLists+*/0 }, // GR8_NOREX2
5535 { 8, 8, 8, /*VTLists+*/0 }, // GR8_NOREX
5536 { 8, 8, 8, /*VTLists+*/0 }, // GR8_ABCD_H
5537 { 8, 8, 8, /*VTLists+*/0 }, // GR8_ABCD_L
5538 { 16, 16, 16, /*VTLists+*/2 }, // GRH16
5539 { 16, 16, 16, /*VTLists+*/2 }, // GR16
5540 { 16, 16, 16, /*VTLists+*/2 }, // GR16_NOREX2
5541 { 16, 16, 16, /*VTLists+*/2 }, // GR16_NOREX
5542 { 16, 16, 16, /*VTLists+*/28 }, // VK1
5543 { 16, 16, 16, /*VTLists+*/36 }, // VK16
5544 { 16, 16, 16, /*VTLists+*/30 }, // VK2
5545 { 16, 16, 16, /*VTLists+*/32 }, // VK4
5546 { 16, 16, 16, /*VTLists+*/34 }, // VK8
5547 { 16, 16, 16, /*VTLists+*/36 }, // VK16WM
5548 { 16, 16, 16, /*VTLists+*/28 }, // VK1WM
5549 { 16, 16, 16, /*VTLists+*/30 }, // VK2WM
5550 { 16, 16, 16, /*VTLists+*/32 }, // VK4WM
5551 { 16, 16, 16, /*VTLists+*/34 }, // VK8WM
5552 { 16, 16, 16, /*VTLists+*/2 }, // SEGMENT_REG
5553 { 16, 16, 16, /*VTLists+*/2 }, // GR16_ABCD
5554 { 16, 16, 16, /*VTLists+*/2 }, // FPCCR
5555 { 32, 32, 16, /*VTLists+*/8 }, // FR16X
5556 { 32, 32, 16, /*VTLists+*/8 }, // FR16
5557 { 32, 32, 16, /*VTLists+*/69 }, // VK16PAIR
5558 { 32, 32, 16, /*VTLists+*/69 }, // VK1PAIR
5559 { 32, 32, 16, /*VTLists+*/69 }, // VK2PAIR
5560 { 32, 32, 16, /*VTLists+*/69 }, // VK4PAIR
5561 { 32, 32, 16, /*VTLists+*/69 }, // VK8PAIR
5562 { 32, 32, 16, /*VTLists+*/69 }, // VK1PAIR_with_sub_mask_0_in_VK1WM
5563 { 32, 32, 32, /*VTLists+*/4 }, // LOW32_ADDR_ACCESS_RBP
5564 { 32, 32, 32, /*VTLists+*/4 }, // LOW32_ADDR_ACCESS
5565 { 32, 32, 32, /*VTLists+*/4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit
5566 { 32, 32, 32, /*VTLists+*/12 }, // FR32X
5567 { 32, 32, 32, /*VTLists+*/4 }, // GR32
5568 { 32, 32, 32, /*VTLists+*/4 }, // GR32_NOSP
5569 { 32, 32, 32, /*VTLists+*/4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
5570 { 32, 32, 32, /*VTLists+*/4 }, // DEBUG_REG
5571 { 32, 32, 32, /*VTLists+*/12 }, // FR32
5572 { 32, 32, 32, /*VTLists+*/4 }, // GR32_NOREX2
5573 { 32, 32, 32, /*VTLists+*/4 }, // GR32_NOREX2_NOSP
5574 { 32, 32, 32, /*VTLists+*/4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
5575 { 32, 32, 32, /*VTLists+*/4 }, // GR32_NOREX
5576 { 32, 32, 32, /*VTLists+*/38 }, // VK32
5577 { 32, 32, 32, /*VTLists+*/4 }, // GR32_NOREX_NOSP
5578 { 32, 32, 32, /*VTLists+*/12 }, // RFP32
5579 { 32, 32, 32, /*VTLists+*/38 }, // VK32WM
5580 { 32, 32, 32, /*VTLists+*/4 }, // GR32_ABCD
5581 { 32, 32, 32, /*VTLists+*/4 }, // GR32_TC
5582 { 32, 32, 32, /*VTLists+*/4 }, // GR32_ABCD_and_GR32_TC
5583 { 32, 32, 32, /*VTLists+*/4 }, // GR32_AD
5584 { 32, 32, 32, /*VTLists+*/4 }, // GR32_ArgRef
5585 { 32, 32, 32, /*VTLists+*/4 }, // GR32_BPSP
5586 { 32, 32, 32, /*VTLists+*/4 }, // GR32_BSI
5587 { 32, 32, 32, /*VTLists+*/4 }, // GR32_CB
5588 { 32, 32, 32, /*VTLists+*/4 }, // GR32_DC
5589 { 32, 32, 32, /*VTLists+*/4 }, // GR32_DIBP
5590 { 32, 32, 32, /*VTLists+*/4 }, // GR32_SIDI
5591 { 32, 32, 32, /*VTLists+*/4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit
5592 { 32, 32, 32, /*VTLists+*/4 }, // CCR
5593 { 32, 32, 32, /*VTLists+*/4 }, // DFCCR
5594 { 32, 32, 32, /*VTLists+*/4 }, // GR32_ABCD_and_GR32_BSI
5595 { 32, 32, 32, /*VTLists+*/4 }, // GR32_AD_and_GR32_ArgRef
5596 { 32, 32, 32, /*VTLists+*/4 }, // GR32_ArgRef_and_GR32_CB
5597 { 32, 32, 32, /*VTLists+*/4 }, // GR32_BPSP_and_GR32_DIBP
5598 { 32, 32, 32, /*VTLists+*/4 }, // GR32_BPSP_and_GR32_TC
5599 { 32, 32, 32, /*VTLists+*/4 }, // GR32_BSI_and_GR32_SIDI
5600 { 32, 32, 32, /*VTLists+*/4 }, // GR32_DIBP_and_GR32_SIDI
5601 { 32, 32, 32, /*VTLists+*/4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
5602 { 32, 32, 32, /*VTLists+*/4 }, // LOW32_ADDR_ACCESS_with_sub_32bit
5603 { 64, 64, 32, /*VTLists+*/14 }, // RFP64
5604 { 64, 64, 64, /*VTLists+*/6 }, // GR64
5605 { 64, 64, 64, /*VTLists+*/14 }, // FR64X
5606 { 64, 64, 64, /*VTLists+*/6 }, // GR64_with_sub_8bit
5607 { 64, 64, 64, /*VTLists+*/6 }, // GR64_NOSP
5608 { 64, 64, 64, /*VTLists+*/6 }, // GR64_NOREX2
5609 { 64, 64, 64, /*VTLists+*/6 }, // CONTROL_REG
5610 { 64, 64, 64, /*VTLists+*/14 }, // FR64
5611 { 64, 64, 64, /*VTLists+*/6 }, // GR64_with_sub_16bit_in_GR16_NOREX2
5612 { 64, 64, 64, /*VTLists+*/6 }, // GR64_NOREX2_NOSP
5613 { 64, 64, 64, /*VTLists+*/6 }, // GR64PLTSafe
5614 { 64, 64, 64, /*VTLists+*/6 }, // GR64_TC
5615 { 64, 64, 64, /*VTLists+*/6 }, // GR64_NOREX
5616 { 64, 64, 64, /*VTLists+*/6 }, // GR64_TCW64
5617 { 64, 64, 64, /*VTLists+*/6 }, // GR64_TC_with_sub_8bit
5618 { 64, 64, 64, /*VTLists+*/6 }, // GR64_NOREX2_NOSP_and_GR64_TC
5619 { 64, 64, 64, /*VTLists+*/6 }, // GR64_TCW64_with_sub_8bit
5620 { 64, 64, 64, /*VTLists+*/6 }, // GR64_TC_and_GR64_TCW64
5621 { 64, 64, 64, /*VTLists+*/6 }, // GR64_with_sub_16bit_in_GR16_NOREX
5622 { 64, 64, 64, /*VTLists+*/40 }, // VK64
5623 { 64, 64, 64, /*VTLists+*/67 }, // VR64
5624 { 64, 64, 64, /*VTLists+*/6 }, // GR64PLTSafe_and_GR64_TC
5625 { 64, 64, 64, /*VTLists+*/6 }, // GR64_NOREX2_NOSP_and_GR64_TCW64
5626 { 64, 64, 64, /*VTLists+*/6 }, // GR64_NOREX_NOSP
5627 { 64, 64, 64, /*VTLists+*/6 }, // GR64_NOREX_and_GR64_TC
5628 { 64, 64, 64, /*VTLists+*/6 }, // GR64_TCW64_and_GR64_TC_with_sub_8bit
5629 { 64, 64, 64, /*VTLists+*/40 }, // VK64WM
5630 { 64, 64, 64, /*VTLists+*/6 }, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
5631 { 64, 64, 64, /*VTLists+*/6 }, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
5632 { 64, 64, 64, /*VTLists+*/6 }, // GR64PLTSafe_and_GR64_TCW64
5633 { 64, 64, 64, /*VTLists+*/6 }, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
5634 { 64, 64, 64, /*VTLists+*/6 }, // GR64_NOREX_and_GR64_TCW64
5635 { 64, 64, 64, /*VTLists+*/6 }, // GR64_ABCD
5636 { 64, 64, 64, /*VTLists+*/6 }, // GR64_with_sub_32bit_in_GR32_TC
5637 { 64, 64, 64, /*VTLists+*/6 }, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
5638 { 64, 64, 64, /*VTLists+*/6 }, // GR64_AD
5639 { 64, 64, 64, /*VTLists+*/6 }, // GR64_ArgRef
5640 { 64, 64, 64, /*VTLists+*/6 }, // GR64_and_LOW32_ADDR_ACCESS_RBP
5641 { 64, 64, 64, /*VTLists+*/6 }, // GR64_with_sub_32bit_in_GR32_ArgRef
5642 { 64, 64, 64, /*VTLists+*/6 }, // GR64_with_sub_32bit_in_GR32_BPSP
5643 { 64, 64, 64, /*VTLists+*/6 }, // GR64_with_sub_32bit_in_GR32_BSI
5644 { 64, 64, 64, /*VTLists+*/6 }, // GR64_with_sub_32bit_in_GR32_CB
5645 { 64, 64, 64, /*VTLists+*/6 }, // GR64_with_sub_32bit_in_GR32_DIBP
5646 { 64, 64, 64, /*VTLists+*/6 }, // GR64_with_sub_32bit_in_GR32_SIDI
5647 { 64, 64, 64, /*VTLists+*/6 }, // GR64_A
5648 { 64, 64, 64, /*VTLists+*/6 }, // GR64_ArgRef_and_GR64_TC
5649 { 64, 64, 64, /*VTLists+*/6 }, // GR64_and_LOW32_ADDR_ACCESS
5650 { 64, 64, 64, /*VTLists+*/6 }, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
5651 { 64, 64, 64, /*VTLists+*/6 }, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
5652 { 64, 64, 64, /*VTLists+*/6 }, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
5653 { 64, 64, 64, /*VTLists+*/6 }, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
5654 { 64, 64, 64, /*VTLists+*/6 }, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
5655 { 64, 64, 64, /*VTLists+*/6 }, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
5656 { 64, 64, 64, /*VTLists+*/6 }, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
5657 { 80, 80, 32, /*VTLists+*/10 }, // RST
5658 { 80, 80, 32, /*VTLists+*/16 }, // RFP80
5659 { 80, 80, 32, /*VTLists+*/16 }, // RFP80_7
5660 { 128, 128, 128, /*VTLists+*/18 }, // VR128X
5661 { 128, 128, 128, /*VTLists+*/18 }, // VR128
5662 { 256, 256, 256, /*VTLists+*/42 }, // VR256X
5663 { 256, 256, 256, /*VTLists+*/42 }, // VR256
5664 { 512, 512, 512, /*VTLists+*/51 }, // VR512
5665 { 512, 512, 512, /*VTLists+*/60 }, // VR512_0_15
5666 { 8192, 8192, 8192, /*VTLists+*/71 }, // TILE
5667 { 16384, 16384, 512, /*VTLists+*/69 }, // TILEPAIR
5668};
5669static const uint32_t GR8SubClassMask[] = {
5670 0x0000003d, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5671 0x00200380, 0xc7ff2f3a, 0x72e38c3f, 0x1fdfefbd, 0x00000000, // sub_8bit
5672 0x00200000, 0xc19d0000, 0x00000001, 0x01c92680, 0x00000000, // sub_8bit_hi
5673};
5674
5675static const uint32_t GRH8SubClassMask[] = {
5676 0x00000002, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5677};
5678
5679static const uint32_t GR8_NOREX2SubClassMask[] = {
5680 0x0000003c, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5681 0x00200300, 0xc7ff2f20, 0x72e3803f, 0x1fdfefbd, 0x00000000, // sub_8bit
5682 0x00200000, 0xc19d0000, 0x00000001, 0x01c92680, 0x00000000, // sub_8bit_hi
5683};
5684
5685static const uint32_t GR8_NOREXSubClassMask[] = {
5686 0x00000038, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5687 0x00200000, 0xc19d0000, 0x00000001, 0x01c92680, 0x00000000, // sub_8bit
5688 0x00200000, 0xc19d0000, 0x00000001, 0x01c92680, 0x00000000, // sub_8bit_hi
5689};
5690
5691static const uint32_t GR8_ABCD_HSubClassMask[] = {
5692 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5693 0x00200000, 0xc19d0000, 0x00000001, 0x01c92680, 0x00000000, // sub_8bit_hi
5694};
5695
5696static const uint32_t GR8_ABCD_LSubClassMask[] = {
5697 0x00000020, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5698 0x00200000, 0xc19d0000, 0x00000001, 0x01c92680, 0x00000000, // sub_8bit
5699};
5700
5701static const uint32_t GRH16SubClassMask[] = {
5702 0x00000040, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5703};
5704
5705static const uint32_t GR16SubClassMask[] = {
5706 0x00200380, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5707 0x00000000, 0xc7ff2f3a, 0x72e38c3f, 0x1fdfefbd, 0x00000000, // sub_16bit
5708};
5709
5710static const uint32_t GR16_NOREX2SubClassMask[] = {
5711 0x00200300, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5712 0x00000000, 0xc7ff2f20, 0x72e3803f, 0x1fdfefbd, 0x00000000, // sub_16bit
5713};
5714
5715static const uint32_t GR16_NOREXSubClassMask[] = {
5716 0x00200200, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5717 0x00000000, 0xc7ff2c00, 0x4200003f, 0x1fcfe7a8, 0x00000000, // sub_16bit
5718};
5719
5720static const uint32_t VK1SubClassMask[] = {
5721 0x000ffc00, 0x00009000, 0x04000000, 0x00000002, 0x00000000,
5722 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
5723 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
5724};
5725
5726static const uint32_t VK16SubClassMask[] = {
5727 0x000ffc00, 0x00009000, 0x04000000, 0x00000002, 0x00000000,
5728 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
5729 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
5730};
5731
5732static const uint32_t VK2SubClassMask[] = {
5733 0x000ffc00, 0x00009000, 0x04000000, 0x00000002, 0x00000000,
5734 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
5735 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
5736};
5737
5738static const uint32_t VK4SubClassMask[] = {
5739 0x000ffc00, 0x00009000, 0x04000000, 0x00000002, 0x00000000,
5740 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
5741 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
5742};
5743
5744static const uint32_t VK8SubClassMask[] = {
5745 0x000ffc00, 0x00009000, 0x04000000, 0x00000002, 0x00000000,
5746 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
5747 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
5748};
5749
5750static const uint32_t VK16WMSubClassMask[] = {
5751 0x000f8000, 0x00008000, 0x00000000, 0x00000002, 0x00000000,
5752 0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
5753 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
5754};
5755
5756static const uint32_t VK1WMSubClassMask[] = {
5757 0x000f8000, 0x00008000, 0x00000000, 0x00000002, 0x00000000,
5758 0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
5759 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
5760};
5761
5762static const uint32_t VK2WMSubClassMask[] = {
5763 0x000f8000, 0x00008000, 0x00000000, 0x00000002, 0x00000000,
5764 0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
5765 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
5766};
5767
5768static const uint32_t VK4WMSubClassMask[] = {
5769 0x000f8000, 0x00008000, 0x00000000, 0x00000002, 0x00000000,
5770 0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
5771 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
5772};
5773
5774static const uint32_t VK8WMSubClassMask[] = {
5775 0x000f8000, 0x00008000, 0x00000000, 0x00000002, 0x00000000,
5776 0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
5777 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
5778};
5779
5780static const uint32_t SEGMENT_REGSubClassMask[] = {
5781 0x00100000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5782};
5783
5784static const uint32_t GR16_ABCDSubClassMask[] = {
5785 0x00200000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5786 0x00000000, 0xc19d0000, 0x00000001, 0x01c92680, 0x00000000, // sub_16bit
5787};
5788
5789static const uint32_t FPCCRSubClassMask[] = {
5790 0x00400000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5791};
5792
5793static const uint32_t FR16XSubClassMask[] = {
5794 0x01800000, 0x00000084, 0x00004200, 0x00000000, 0x00000003,
5795 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000003c, // sub_xmm
5796};
5797
5798static const uint32_t FR16SubClassMask[] = {
5799 0x01000000, 0x00000080, 0x00004000, 0x00000000, 0x00000002,
5800 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000028, // sub_xmm
5801};
5802
5803static const uint32_t VK16PAIRSubClassMask[] = {
5804 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5805};
5806
5807static const uint32_t VK1PAIRSubClassMask[] = {
5808 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5809};
5810
5811static const uint32_t VK2PAIRSubClassMask[] = {
5812 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5813};
5814
5815static const uint32_t VK4PAIRSubClassMask[] = {
5816 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5817};
5818
5819static const uint32_t VK8PAIRSubClassMask[] = {
5820 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5821};
5822
5823static const uint32_t VK1PAIR_with_sub_mask_0_in_VK1WMSubClassMask[] = {
5824 0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5825};
5826
5827static const uint32_t LOW32_ADDR_ACCESS_RBPSubClassMask[] = {
5828 0x80000000, 0xcfff2f3b, 0x0000007f, 0x02201000, 0x00000000,
5829 0x00000000, 0x00000000, 0x72e38c20, 0x1fdfefbd, 0x00000000, // sub_32bit
5830};
5831
5832static const uint32_t LOW32_ADDR_ACCESSSubClassMask[] = {
5833 0x00000000, 0xc7ff2b19, 0x0000005f, 0x00200000, 0x00000000,
5834 0x00000000, 0x00000000, 0x72e38c20, 0x1fdfefbd, 0x00000000, // sub_32bit
5835};
5836
5837static const uint32_t LOW32_ADDR_ACCESS_RBP_with_sub_8bitSubClassMask[] = {
5838 0x00000000, 0xc7ff2f3a, 0x0000003f, 0x02000000, 0x00000000,
5839 0x00000000, 0x00000000, 0x72e38c20, 0x1fdfefbd, 0x00000000, // sub_32bit
5840};
5841
5842static const uint32_t FR32XSubClassMask[] = {
5843 0x00000000, 0x00000084, 0x00004200, 0x00000000, 0x00000003,
5844 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000003c, // sub_xmm
5845};
5846
5847static const uint32_t GR32SubClassMask[] = {
5848 0x00000000, 0xc7ff2b18, 0x0000001f, 0x00000000, 0x00000000,
5849 0x00000000, 0x00000000, 0x72e38c20, 0x1fdfefbd, 0x00000000, // sub_32bit
5850};
5851
5852static const uint32_t GR32_NOSPSubClassMask[] = {
5853 0x00000000, 0xc7dd2210, 0x0000001b, 0x00000000, 0x00000000,
5854 0x00000000, 0x00000000, 0x70430820, 0x1bdfaeb4, 0x00000000, // sub_32bit
5855};
5856
5857static const uint32_t LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2SubClassMask[] = {
5858 0x00000000, 0xc7ff2f20, 0x0000003f, 0x02000000, 0x00000000,
5859 0x00000000, 0x00000000, 0x72e38020, 0x1fdfefbd, 0x00000000, // sub_32bit
5860};
5861
5862static const uint32_t DEBUG_REGSubClassMask[] = {
5863 0x00000000, 0x00000040, 0x00000000, 0x00000000, 0x00000000,
5864};
5865
5866static const uint32_t FR32SubClassMask[] = {
5867 0x00000000, 0x00000080, 0x00004000, 0x00000000, 0x00000002,
5868 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000028, // sub_xmm
5869};
5870
5871static const uint32_t GR32_NOREX2SubClassMask[] = {
5872 0x00000000, 0xc7ff2b00, 0x0000001f, 0x00000000, 0x00000000,
5873 0x00000000, 0x00000000, 0x72e38020, 0x1fdfefbd, 0x00000000, // sub_32bit
5874};
5875
5876static const uint32_t GR32_NOREX2_NOSPSubClassMask[] = {
5877 0x00000000, 0xc7dd2200, 0x0000001b, 0x00000000, 0x00000000,
5878 0x00000000, 0x00000000, 0x70430020, 0x1bdfaeb4, 0x00000000, // sub_32bit
5879};
5880
5881static const uint32_t LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXSubClassMask[] = {
5882 0x00000000, 0xc7ff2c00, 0x0000003f, 0x02000000, 0x00000000,
5883 0x00000000, 0x00000000, 0x42000020, 0x1fcfe7a8, 0x00000000, // sub_32bit
5884};
5885
5886static const uint32_t GR32_NOREXSubClassMask[] = {
5887 0x00000000, 0xc7ff2800, 0x0000001f, 0x00000000, 0x00000000,
5888 0x00000000, 0x00000000, 0x42000020, 0x1fcfe7a8, 0x00000000, // sub_32bit
5889};
5890
5891static const uint32_t VK32SubClassMask[] = {
5892 0x00000000, 0x00009000, 0x04000000, 0x00000002, 0x00000000,
5893 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
5894 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
5895};
5896
5897static const uint32_t GR32_NOREX_NOSPSubClassMask[] = {
5898 0x00000000, 0xc7dd2000, 0x0000001b, 0x00000000, 0x00000000,
5899 0x00000000, 0x00000000, 0x40000020, 0x1bcfa6a0, 0x00000000, // sub_32bit
5900};
5901
5902static const uint32_t RFP32SubClassMask[] = {
5903 0x00000000, 0x00004000, 0x00000080, 0x40000000, 0x00000000,
5904};
5905
5906static const uint32_t VK32WMSubClassMask[] = {
5907 0x00000000, 0x00008000, 0x00000000, 0x00000002, 0x00000000,
5908 0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
5909 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
5910};
5911
5912static const uint32_t GR32_ABCDSubClassMask[] = {
5913 0x00000000, 0xc19d0000, 0x00000001, 0x00000000, 0x00000000,
5914 0x00000000, 0x00000000, 0x00000000, 0x01c92680, 0x00000000, // sub_32bit
5915};
5916
5917static const uint32_t GR32_TCSubClassMask[] = {
5918 0x00000000, 0x811e0000, 0x00000005, 0x00000000, 0x00000000,
5919 0x00000000, 0x00000000, 0x00000000, 0x05882700, 0x00000000, // sub_32bit
5920};
5921
5922static const uint32_t GR32_ABCD_and_GR32_TCSubClassMask[] = {
5923 0x00000000, 0x811c0000, 0x00000001, 0x00000000, 0x00000000,
5924 0x00000000, 0x00000000, 0x00000000, 0x01882600, 0x00000000, // sub_32bit
5925};
5926
5927static const uint32_t GR32_ADSubClassMask[] = {
5928 0x00000000, 0x80080000, 0x00000000, 0x00000000, 0x00000000,
5929 0x00000000, 0x00000000, 0x00000000, 0x00880400, 0x00000000, // sub_32bit
5930};
5931
5932static const uint32_t GR32_ArgRefSubClassMask[] = {
5933 0x00000000, 0x81100000, 0x00000001, 0x00000000, 0x00000000,
5934 0x00000000, 0x00000000, 0x00000000, 0x01802000, 0x00000000, // sub_32bit
5935};
5936
5937static const uint32_t GR32_BPSPSubClassMask[] = {
5938 0x00000000, 0x00200000, 0x00000006, 0x00000000, 0x00000000,
5939 0x00000000, 0x00000000, 0x00000020, 0x06004000, 0x00000000, // sub_32bit
5940};
5941
5942static const uint32_t GR32_BSISubClassMask[] = {
5943 0x00000000, 0x40400000, 0x00000008, 0x00000000, 0x00000000,
5944 0x00000000, 0x00000000, 0x00000000, 0x08408000, 0x00000000, // sub_32bit
5945};
5946
5947static const uint32_t GR32_CBSubClassMask[] = {
5948 0x00000000, 0x40800000, 0x00000001, 0x00000000, 0x00000000,
5949 0x00000000, 0x00000000, 0x00000000, 0x01410000, 0x00000000, // sub_32bit
5950};
5951
5952static const uint32_t GR32_DCSubClassMask[] = {
5953 0x00000000, 0x81000000, 0x00000001, 0x00000000, 0x00000000,
5954 0x00000000, 0x00000000, 0x00000000, 0x01802000, 0x00000000, // sub_32bit
5955};
5956
5957static const uint32_t GR32_DIBPSubClassMask[] = {
5958 0x00000000, 0x02000000, 0x00000012, 0x00000000, 0x00000000,
5959 0x00000000, 0x00000000, 0x00000020, 0x12020000, 0x00000000, // sub_32bit
5960};
5961
5962static const uint32_t GR32_SIDISubClassMask[] = {
5963 0x00000000, 0x04000000, 0x00000018, 0x00000000, 0x00000000,
5964 0x00000000, 0x00000000, 0x00000000, 0x18040000, 0x00000000, // sub_32bit
5965};
5966
5967static const uint32_t LOW32_ADDR_ACCESS_RBP_with_sub_32bitSubClassMask[] = {
5968 0x00000000, 0x08000000, 0x00000060, 0x02201000, 0x00000000,
5969};
5970
5971static const uint32_t CCRSubClassMask[] = {
5972 0x00000000, 0x10000000, 0x00000000, 0x00000000, 0x00000000,
5973};
5974
5975static const uint32_t DFCCRSubClassMask[] = {
5976 0x00000000, 0x20000000, 0x00000000, 0x00000000, 0x00000000,
5977};
5978
5979static const uint32_t GR32_ABCD_and_GR32_BSISubClassMask[] = {
5980 0x00000000, 0x40000000, 0x00000000, 0x00000000, 0x00000000,
5981 0x00000000, 0x00000000, 0x00000000, 0x00400000, 0x00000000, // sub_32bit
5982};
5983
5984static const uint32_t GR32_AD_and_GR32_ArgRefSubClassMask[] = {
5985 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x00000000,
5986 0x00000000, 0x00000000, 0x00000000, 0x00800000, 0x00000000, // sub_32bit
5987};
5988
5989static const uint32_t GR32_ArgRef_and_GR32_CBSubClassMask[] = {
5990 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000,
5991 0x00000000, 0x00000000, 0x00000000, 0x01000000, 0x00000000, // sub_32bit
5992};
5993
5994static const uint32_t GR32_BPSP_and_GR32_DIBPSubClassMask[] = {
5995 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000,
5996 0x00000000, 0x00000000, 0x00000020, 0x02000000, 0x00000000, // sub_32bit
5997};
5998
5999static const uint32_t GR32_BPSP_and_GR32_TCSubClassMask[] = {
6000 0x00000000, 0x00000000, 0x00000004, 0x00000000, 0x00000000,
6001 0x00000000, 0x00000000, 0x00000000, 0x04000000, 0x00000000, // sub_32bit
6002};
6003
6004static const uint32_t GR32_BSI_and_GR32_SIDISubClassMask[] = {
6005 0x00000000, 0x00000000, 0x00000008, 0x00000000, 0x00000000,
6006 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x00000000, // sub_32bit
6007};
6008
6009static const uint32_t GR32_DIBP_and_GR32_SIDISubClassMask[] = {
6010 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000,
6011 0x00000000, 0x00000000, 0x00000000, 0x10000000, 0x00000000, // sub_32bit
6012};
6013
6014static const uint32_t LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitSubClassMask[] = {
6015 0x00000000, 0x00000000, 0x00000020, 0x02000000, 0x00000000,
6016};
6017
6018static const uint32_t LOW32_ADDR_ACCESS_with_sub_32bitSubClassMask[] = {
6019 0x00000000, 0x00000000, 0x00000040, 0x00200000, 0x00000000,
6020};
6021
6022static const uint32_t RFP64SubClassMask[] = {
6023 0x00000000, 0x00000000, 0x00000080, 0x40000000, 0x00000000,
6024};
6025
6026static const uint32_t GR64SubClassMask[] = {
6027 0x00000000, 0x00000000, 0xf3ff9d00, 0x1ffffffd, 0x00000000,
6028};
6029
6030static const uint32_t FR64XSubClassMask[] = {
6031 0x00000000, 0x00000000, 0x00004200, 0x00000000, 0x00000003,
6032 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000003c, // sub_xmm
6033};
6034
6035static const uint32_t GR64_with_sub_8bitSubClassMask[] = {
6036 0x00000000, 0x00000000, 0x72e38c00, 0x1fdfefbd, 0x00000000,
6037};
6038
6039static const uint32_t GR64_NOSPSubClassMask[] = {
6040 0x00000000, 0x00000000, 0x70430800, 0x1bdfaeb4, 0x00000000,
6041};
6042
6043static const uint32_t GR64_NOREX2SubClassMask[] = {
6044 0x00000000, 0x00000000, 0xf3ff9000, 0x1ffffffd, 0x00000000,
6045};
6046
6047static const uint32_t CONTROL_REGSubClassMask[] = {
6048 0x00000000, 0x00000000, 0x00002000, 0x00000000, 0x00000000,
6049};
6050
6051static const uint32_t FR64SubClassMask[] = {
6052 0x00000000, 0x00000000, 0x00004000, 0x00000000, 0x00000002,
6053 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000028, // sub_xmm
6054};
6055
6056static const uint32_t GR64_with_sub_16bit_in_GR16_NOREX2SubClassMask[] = {
6057 0x00000000, 0x00000000, 0x72e38000, 0x1fdfefbd, 0x00000000,
6058};
6059
6060static const uint32_t GR64_NOREX2_NOSPSubClassMask[] = {
6061 0x00000000, 0x00000000, 0x70430000, 0x1bdfaeb4, 0x00000000,
6062};
6063
6064static const uint32_t GR64PLTSafeSubClassMask[] = {
6065 0x00000000, 0x00000000, 0x50020000, 0x1bcfa6b0, 0x00000000,
6066};
6067
6068static const uint32_t GR64_TCSubClassMask[] = {
6069 0x00000000, 0x00000000, 0x91640000, 0x1dbc277d, 0x00000000,
6070};
6071
6072static const uint32_t GR64_NOREXSubClassMask[] = {
6073 0x00000000, 0x00000000, 0xc2080000, 0x1feff7e8, 0x00000000,
6074};
6075
6076static const uint32_t GR64_TCW64SubClassMask[] = {
6077 0x00000000, 0x00000000, 0x21900000, 0x05b82f55, 0x00000000,
6078};
6079
6080static const uint32_t GR64_TC_with_sub_8bitSubClassMask[] = {
6081 0x00000000, 0x00000000, 0x10600000, 0x1d9c273d, 0x00000000,
6082};
6083
6084static const uint32_t GR64_NOREX2_NOSP_and_GR64_TCSubClassMask[] = {
6085 0x00000000, 0x00000000, 0x10400000, 0x199c2634, 0x00000000,
6086};
6087
6088static const uint32_t GR64_TCW64_with_sub_8bitSubClassMask[] = {
6089 0x00000000, 0x00000000, 0x20800000, 0x05982f15, 0x00000000,
6090};
6091
6092static const uint32_t GR64_TC_and_GR64_TCW64SubClassMask[] = {
6093 0x00000000, 0x00000000, 0x01000000, 0x05b82755, 0x00000000,
6094};
6095
6096static const uint32_t GR64_with_sub_16bit_in_GR16_NOREXSubClassMask[] = {
6097 0x00000000, 0x00000000, 0x42000000, 0x1fcfe7a8, 0x00000000,
6098};
6099
6100static const uint32_t VK64SubClassMask[] = {
6101 0x00000000, 0x00000000, 0x04000000, 0x00000002, 0x00000000,
6102 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
6103 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
6104};
6105
6106static const uint32_t VR64SubClassMask[] = {
6107 0x00000000, 0x00000000, 0x08000000, 0x00000000, 0x00000000,
6108};
6109
6110static const uint32_t GR64PLTSafe_and_GR64_TCSubClassMask[] = {
6111 0x00000000, 0x00000000, 0x10000000, 0x198c2630, 0x00000000,
6112};
6113
6114static const uint32_t GR64_NOREX2_NOSP_and_GR64_TCW64SubClassMask[] = {
6115 0x00000000, 0x00000000, 0x20000000, 0x01982e14, 0x00000000,
6116};
6117
6118static const uint32_t GR64_NOREX_NOSPSubClassMask[] = {
6119 0x00000000, 0x00000000, 0x40000000, 0x1bcfa6a0, 0x00000000,
6120};
6121
6122static const uint32_t GR64_NOREX_and_GR64_TCSubClassMask[] = {
6123 0x00000000, 0x00000000, 0x80000000, 0x1dac2768, 0x00000000,
6124};
6125
6126static const uint32_t GR64_TCW64_and_GR64_TC_with_sub_8bitSubClassMask[] = {
6127 0x00000000, 0x00000000, 0x00000000, 0x05982715, 0x00000000,
6128};
6129
6130static const uint32_t VK64WMSubClassMask[] = {
6131 0x00000000, 0x00000000, 0x00000000, 0x00000002, 0x00000000,
6132 0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
6133 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
6134};
6135
6136static const uint32_t GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64SubClassMask[] = {
6137 0x00000000, 0x00000000, 0x00000000, 0x01982614, 0x00000000,
6138};
6139
6140static const uint32_t GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXSubClassMask[] = {
6141 0x00000000, 0x00000000, 0x00000000, 0x1d8c2728, 0x00000000,
6142};
6143
6144static const uint32_t GR64PLTSafe_and_GR64_TCW64SubClassMask[] = {
6145 0x00000000, 0x00000000, 0x00000000, 0x01882610, 0x00000000,
6146};
6147
6148static const uint32_t GR64_NOREX_and_GR64PLTSafe_and_GR64_TCSubClassMask[] = {
6149 0x00000000, 0x00000000, 0x00000000, 0x198c2620, 0x00000000,
6150};
6151
6152static const uint32_t GR64_NOREX_and_GR64_TCW64SubClassMask[] = {
6153 0x00000000, 0x00000000, 0x00000000, 0x05a82740, 0x00000000,
6154};
6155
6156static const uint32_t GR64_ABCDSubClassMask[] = {
6157 0x00000000, 0x00000000, 0x00000000, 0x01c92680, 0x00000000,
6158};
6159
6160static const uint32_t GR64_with_sub_32bit_in_GR32_TCSubClassMask[] = {
6161 0x00000000, 0x00000000, 0x00000000, 0x05882700, 0x00000000,
6162};
6163
6164static const uint32_t GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCSubClassMask[] = {
6165 0x00000000, 0x00000000, 0x00000000, 0x01882600, 0x00000000,
6166};
6167
6168static const uint32_t GR64_ADSubClassMask[] = {
6169 0x00000000, 0x00000000, 0x00000000, 0x00880400, 0x00000000,
6170};
6171
6172static const uint32_t GR64_ArgRefSubClassMask[] = {
6173 0x00000000, 0x00000000, 0x00000000, 0x00100800, 0x00000000,
6174};
6175
6176static const uint32_t GR64_and_LOW32_ADDR_ACCESS_RBPSubClassMask[] = {
6177 0x00000000, 0x00000000, 0x00000000, 0x02201000, 0x00000000,
6178};
6179
6180static const uint32_t GR64_with_sub_32bit_in_GR32_ArgRefSubClassMask[] = {
6181 0x00000000, 0x00000000, 0x00000000, 0x01802000, 0x00000000,
6182};
6183
6184static const uint32_t GR64_with_sub_32bit_in_GR32_BPSPSubClassMask[] = {
6185 0x00000000, 0x00000000, 0x00000000, 0x06004000, 0x00000000,
6186};
6187
6188static const uint32_t GR64_with_sub_32bit_in_GR32_BSISubClassMask[] = {
6189 0x00000000, 0x00000000, 0x00000000, 0x08408000, 0x00000000,
6190};
6191
6192static const uint32_t GR64_with_sub_32bit_in_GR32_CBSubClassMask[] = {
6193 0x00000000, 0x00000000, 0x00000000, 0x01410000, 0x00000000,
6194};
6195
6196static const uint32_t GR64_with_sub_32bit_in_GR32_DIBPSubClassMask[] = {
6197 0x00000000, 0x00000000, 0x00000000, 0x12020000, 0x00000000,
6198};
6199
6200static const uint32_t GR64_with_sub_32bit_in_GR32_SIDISubClassMask[] = {
6201 0x00000000, 0x00000000, 0x00000000, 0x18040000, 0x00000000,
6202};
6203
6204static const uint32_t GR64_ASubClassMask[] = {
6205 0x00000000, 0x00000000, 0x00000000, 0x00080000, 0x00000000,
6206};
6207
6208static const uint32_t GR64_ArgRef_and_GR64_TCSubClassMask[] = {
6209 0x00000000, 0x00000000, 0x00000000, 0x00100000, 0x00000000,
6210};
6211
6212static const uint32_t GR64_and_LOW32_ADDR_ACCESSSubClassMask[] = {
6213 0x00000000, 0x00000000, 0x00000000, 0x00200000, 0x00000000,
6214};
6215
6216static const uint32_t GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSISubClassMask[] = {
6217 0x00000000, 0x00000000, 0x00000000, 0x00400000, 0x00000000,
6218};
6219
6220static const uint32_t GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefSubClassMask[] = {
6221 0x00000000, 0x00000000, 0x00000000, 0x00800000, 0x00000000,
6222};
6223
6224static const uint32_t GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBSubClassMask[] = {
6225 0x00000000, 0x00000000, 0x00000000, 0x01000000, 0x00000000,
6226};
6227
6228static const uint32_t GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPSubClassMask[] = {
6229 0x00000000, 0x00000000, 0x00000000, 0x02000000, 0x00000000,
6230};
6231
6232static const uint32_t GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCSubClassMask[] = {
6233 0x00000000, 0x00000000, 0x00000000, 0x04000000, 0x00000000,
6234};
6235
6236static const uint32_t GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDISubClassMask[] = {
6237 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x00000000,
6238};
6239
6240static const uint32_t GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDISubClassMask[] = {
6241 0x00000000, 0x00000000, 0x00000000, 0x10000000, 0x00000000,
6242};
6243
6244static const uint32_t RSTSubClassMask[] = {
6245 0x00000000, 0x00000000, 0x00000000, 0x20000000, 0x00000000,
6246};
6247
6248static const uint32_t RFP80SubClassMask[] = {
6249 0x00000000, 0x00000000, 0x00000000, 0x40000000, 0x00000000,
6250};
6251
6252static const uint32_t RFP80_7SubClassMask[] = {
6253 0x00000000, 0x00000000, 0x00000000, 0x80000000, 0x00000000,
6254};
6255
6256static const uint32_t VR128XSubClassMask[] = {
6257 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000003,
6258 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000003c, // sub_xmm
6259};
6260
6261static const uint32_t VR128SubClassMask[] = {
6262 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000002,
6263 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000028, // sub_xmm
6264};
6265
6266static const uint32_t VR256XSubClassMask[] = {
6267 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000000c,
6268 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000030, // sub_ymm
6269};
6270
6271static const uint32_t VR256SubClassMask[] = {
6272 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008,
6273 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000020, // sub_ymm
6274};
6275
6276static const uint32_t VR512SubClassMask[] = {
6277 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000030,
6278};
6279
6280static const uint32_t VR512_0_15SubClassMask[] = {
6281 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000020,
6282};
6283
6284static const uint32_t TILESubClassMask[] = {
6285 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000040,
6286 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000080, // sub_t0
6287 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000080, // sub_t1
6288};
6289
6290static const uint32_t TILEPAIRSubClassMask[] = {
6291 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000080,
6292};
6293
6294static const uint16_t SuperRegIdxSeqs[] = {
6295 /* 0 */ 1, 0,
6296 /* 2 */ 1, 2, 0,
6297 /* 5 */ 4, 0,
6298 /* 7 */ 6, 0,
6299 /* 9 */ 7, 8, 0,
6300 /* 12 */ 9, 10, 0,
6301 /* 15 */ 11, 0,
6302 /* 17 */ 12, 0,
6303};
6304
6305static unsigned const GR8_NOREX2Superclasses[] = {
6306 X86::GR8RegClassID,
6307};
6308
6309static unsigned const GR8_NOREXSuperclasses[] = {
6310 X86::GR8RegClassID,
6311 X86::GR8_NOREX2RegClassID,
6312};
6313
6314static unsigned const GR8_ABCD_HSuperclasses[] = {
6315 X86::GR8RegClassID,
6316 X86::GR8_NOREX2RegClassID,
6317 X86::GR8_NOREXRegClassID,
6318};
6319
6320static unsigned const GR8_ABCD_LSuperclasses[] = {
6321 X86::GR8RegClassID,
6322 X86::GR8_NOREX2RegClassID,
6323 X86::GR8_NOREXRegClassID,
6324};
6325
6326static unsigned const GR16_NOREX2Superclasses[] = {
6327 X86::GR16RegClassID,
6328};
6329
6330static unsigned const GR16_NOREXSuperclasses[] = {
6331 X86::GR16RegClassID,
6332 X86::GR16_NOREX2RegClassID,
6333};
6334
6335static unsigned const VK1Superclasses[] = {
6336 X86::VK16RegClassID,
6337 X86::VK2RegClassID,
6338 X86::VK4RegClassID,
6339 X86::VK8RegClassID,
6340};
6341
6342static unsigned const VK16Superclasses[] = {
6343 X86::VK1RegClassID,
6344 X86::VK2RegClassID,
6345 X86::VK4RegClassID,
6346 X86::VK8RegClassID,
6347};
6348
6349static unsigned const VK2Superclasses[] = {
6350 X86::VK1RegClassID,
6351 X86::VK16RegClassID,
6352 X86::VK4RegClassID,
6353 X86::VK8RegClassID,
6354};
6355
6356static unsigned const VK4Superclasses[] = {
6357 X86::VK1RegClassID,
6358 X86::VK16RegClassID,
6359 X86::VK2RegClassID,
6360 X86::VK8RegClassID,
6361};
6362
6363static unsigned const VK8Superclasses[] = {
6364 X86::VK1RegClassID,
6365 X86::VK16RegClassID,
6366 X86::VK2RegClassID,
6367 X86::VK4RegClassID,
6368};
6369
6370static unsigned const VK16WMSuperclasses[] = {
6371 X86::VK1RegClassID,
6372 X86::VK16RegClassID,
6373 X86::VK2RegClassID,
6374 X86::VK4RegClassID,
6375 X86::VK8RegClassID,
6376 X86::VK1WMRegClassID,
6377 X86::VK2WMRegClassID,
6378 X86::VK4WMRegClassID,
6379 X86::VK8WMRegClassID,
6380};
6381
6382static unsigned const VK1WMSuperclasses[] = {
6383 X86::VK1RegClassID,
6384 X86::VK16RegClassID,
6385 X86::VK2RegClassID,
6386 X86::VK4RegClassID,
6387 X86::VK8RegClassID,
6388 X86::VK16WMRegClassID,
6389 X86::VK2WMRegClassID,
6390 X86::VK4WMRegClassID,
6391 X86::VK8WMRegClassID,
6392};
6393
6394static unsigned const VK2WMSuperclasses[] = {
6395 X86::VK1RegClassID,
6396 X86::VK16RegClassID,
6397 X86::VK2RegClassID,
6398 X86::VK4RegClassID,
6399 X86::VK8RegClassID,
6400 X86::VK16WMRegClassID,
6401 X86::VK1WMRegClassID,
6402 X86::VK4WMRegClassID,
6403 X86::VK8WMRegClassID,
6404};
6405
6406static unsigned const VK4WMSuperclasses[] = {
6407 X86::VK1RegClassID,
6408 X86::VK16RegClassID,
6409 X86::VK2RegClassID,
6410 X86::VK4RegClassID,
6411 X86::VK8RegClassID,
6412 X86::VK16WMRegClassID,
6413 X86::VK1WMRegClassID,
6414 X86::VK2WMRegClassID,
6415 X86::VK8WMRegClassID,
6416};
6417
6418static unsigned const VK8WMSuperclasses[] = {
6419 X86::VK1RegClassID,
6420 X86::VK16RegClassID,
6421 X86::VK2RegClassID,
6422 X86::VK4RegClassID,
6423 X86::VK8RegClassID,
6424 X86::VK16WMRegClassID,
6425 X86::VK1WMRegClassID,
6426 X86::VK2WMRegClassID,
6427 X86::VK4WMRegClassID,
6428};
6429
6430static unsigned const GR16_ABCDSuperclasses[] = {
6431 X86::GR16RegClassID,
6432 X86::GR16_NOREX2RegClassID,
6433 X86::GR16_NOREXRegClassID,
6434};
6435
6436static unsigned const FR16Superclasses[] = {
6437 X86::FR16XRegClassID,
6438};
6439
6440static unsigned const VK16PAIRSuperclasses[] = {
6441 X86::VK1PAIRRegClassID,
6442 X86::VK2PAIRRegClassID,
6443 X86::VK4PAIRRegClassID,
6444 X86::VK8PAIRRegClassID,
6445};
6446
6447static unsigned const VK1PAIRSuperclasses[] = {
6448 X86::VK16PAIRRegClassID,
6449 X86::VK2PAIRRegClassID,
6450 X86::VK4PAIRRegClassID,
6451 X86::VK8PAIRRegClassID,
6452};
6453
6454static unsigned const VK2PAIRSuperclasses[] = {
6455 X86::VK16PAIRRegClassID,
6456 X86::VK1PAIRRegClassID,
6457 X86::VK4PAIRRegClassID,
6458 X86::VK8PAIRRegClassID,
6459};
6460
6461static unsigned const VK4PAIRSuperclasses[] = {
6462 X86::VK16PAIRRegClassID,
6463 X86::VK1PAIRRegClassID,
6464 X86::VK2PAIRRegClassID,
6465 X86::VK8PAIRRegClassID,
6466};
6467
6468static unsigned const VK8PAIRSuperclasses[] = {
6469 X86::VK16PAIRRegClassID,
6470 X86::VK1PAIRRegClassID,
6471 X86::VK2PAIRRegClassID,
6472 X86::VK4PAIRRegClassID,
6473};
6474
6475static unsigned const VK1PAIR_with_sub_mask_0_in_VK1WMSuperclasses[] = {
6476 X86::VK16PAIRRegClassID,
6477 X86::VK1PAIRRegClassID,
6478 X86::VK2PAIRRegClassID,
6479 X86::VK4PAIRRegClassID,
6480 X86::VK8PAIRRegClassID,
6481};
6482
6483static unsigned const LOW32_ADDR_ACCESSSuperclasses[] = {
6484 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
6485};
6486
6487static unsigned const LOW32_ADDR_ACCESS_RBP_with_sub_8bitSuperclasses[] = {
6488 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
6489};
6490
6491static unsigned const FR32XSuperclasses[] = {
6492 X86::FR16XRegClassID,
6493};
6494
6495static unsigned const GR32Superclasses[] = {
6496 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
6497 X86::LOW32_ADDR_ACCESSRegClassID,
6498 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
6499};
6500
6501static unsigned const GR32_NOSPSuperclasses[] = {
6502 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
6503 X86::LOW32_ADDR_ACCESSRegClassID,
6504 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
6505 X86::GR32RegClassID,
6506};
6507
6508static unsigned const LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2Superclasses[] = {
6509 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
6510 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
6511};
6512
6513static unsigned const FR32Superclasses[] = {
6514 X86::FR16XRegClassID,
6515 X86::FR16RegClassID,
6516 X86::FR32XRegClassID,
6517};
6518
6519static unsigned const GR32_NOREX2Superclasses[] = {
6520 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
6521 X86::LOW32_ADDR_ACCESSRegClassID,
6522 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
6523 X86::GR32RegClassID,
6524 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
6525};
6526
6527static unsigned const GR32_NOREX2_NOSPSuperclasses[] = {
6528 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
6529 X86::LOW32_ADDR_ACCESSRegClassID,
6530 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
6531 X86::GR32RegClassID,
6532 X86::GR32_NOSPRegClassID,
6533 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
6534 X86::GR32_NOREX2RegClassID,
6535};
6536
6537static unsigned const LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXSuperclasses[] = {
6538 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
6539 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
6540 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
6541};
6542
6543static unsigned const GR32_NOREXSuperclasses[] = {
6544 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
6545 X86::LOW32_ADDR_ACCESSRegClassID,
6546 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
6547 X86::GR32RegClassID,
6548 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
6549 X86::GR32_NOREX2RegClassID,
6550 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
6551};
6552
6553static unsigned const VK32Superclasses[] = {
6554 X86::VK1RegClassID,
6555 X86::VK16RegClassID,
6556 X86::VK2RegClassID,
6557 X86::VK4RegClassID,
6558 X86::VK8RegClassID,
6559};
6560
6561static unsigned const GR32_NOREX_NOSPSuperclasses[] = {
6562 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
6563 X86::LOW32_ADDR_ACCESSRegClassID,
6564 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
6565 X86::GR32RegClassID,
6566 X86::GR32_NOSPRegClassID,
6567 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
6568 X86::GR32_NOREX2RegClassID,
6569 X86::GR32_NOREX2_NOSPRegClassID,
6570 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
6571 X86::GR32_NOREXRegClassID,
6572};
6573
6574static unsigned const VK32WMSuperclasses[] = {
6575 X86::VK1RegClassID,
6576 X86::VK16RegClassID,
6577 X86::VK2RegClassID,
6578 X86::VK4RegClassID,
6579 X86::VK8RegClassID,
6580 X86::VK16WMRegClassID,
6581 X86::VK1WMRegClassID,
6582 X86::VK2WMRegClassID,
6583 X86::VK4WMRegClassID,
6584 X86::VK8WMRegClassID,
6585 X86::VK32RegClassID,
6586};
6587
6588static unsigned const GR32_ABCDSuperclasses[] = {
6589 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
6590 X86::LOW32_ADDR_ACCESSRegClassID,
6591 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
6592 X86::GR32RegClassID,
6593 X86::GR32_NOSPRegClassID,
6594 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
6595 X86::GR32_NOREX2RegClassID,
6596 X86::GR32_NOREX2_NOSPRegClassID,
6597 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
6598 X86::GR32_NOREXRegClassID,
6599 X86::GR32_NOREX_NOSPRegClassID,
6600};
6601
6602static unsigned const GR32_TCSuperclasses[] = {
6603 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
6604 X86::LOW32_ADDR_ACCESSRegClassID,
6605 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
6606 X86::GR32RegClassID,
6607 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
6608 X86::GR32_NOREX2RegClassID,
6609 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
6610 X86::GR32_NOREXRegClassID,
6611};
6612
6613static unsigned const GR32_ABCD_and_GR32_TCSuperclasses[] = {
6614 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
6615 X86::LOW32_ADDR_ACCESSRegClassID,
6616 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
6617 X86::GR32RegClassID,
6618 X86::GR32_NOSPRegClassID,
6619 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
6620 X86::GR32_NOREX2RegClassID,
6621 X86::GR32_NOREX2_NOSPRegClassID,
6622 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
6623 X86::GR32_NOREXRegClassID,
6624 X86::GR32_NOREX_NOSPRegClassID,
6625 X86::GR32_ABCDRegClassID,
6626 X86::GR32_TCRegClassID,
6627};
6628
6629static unsigned const GR32_ADSuperclasses[] = {
6630 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
6631 X86::LOW32_ADDR_ACCESSRegClassID,
6632 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
6633 X86::GR32RegClassID,
6634 X86::GR32_NOSPRegClassID,
6635 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
6636 X86::GR32_NOREX2RegClassID,
6637 X86::GR32_NOREX2_NOSPRegClassID,
6638 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
6639 X86::GR32_NOREXRegClassID,
6640 X86::GR32_NOREX_NOSPRegClassID,
6641 X86::GR32_ABCDRegClassID,
6642 X86::GR32_TCRegClassID,
6643 X86::GR32_ABCD_and_GR32_TCRegClassID,
6644};
6645
6646static unsigned const GR32_ArgRefSuperclasses[] = {
6647 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
6648 X86::LOW32_ADDR_ACCESSRegClassID,
6649 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
6650 X86::GR32RegClassID,
6651 X86::GR32_NOSPRegClassID,
6652 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
6653 X86::GR32_NOREX2RegClassID,
6654 X86::GR32_NOREX2_NOSPRegClassID,
6655 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
6656 X86::GR32_NOREXRegClassID,
6657 X86::GR32_NOREX_NOSPRegClassID,
6658 X86::GR32_ABCDRegClassID,
6659 X86::GR32_TCRegClassID,
6660 X86::GR32_ABCD_and_GR32_TCRegClassID,
6661};
6662
6663static unsigned const GR32_BPSPSuperclasses[] = {
6664 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
6665 X86::LOW32_ADDR_ACCESSRegClassID,
6666 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
6667 X86::GR32RegClassID,
6668 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
6669 X86::GR32_NOREX2RegClassID,
6670 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
6671 X86::GR32_NOREXRegClassID,
6672};
6673
6674static unsigned const GR32_BSISuperclasses[] = {
6675 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
6676 X86::LOW32_ADDR_ACCESSRegClassID,
6677 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
6678 X86::GR32RegClassID,
6679 X86::GR32_NOSPRegClassID,
6680 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
6681 X86::GR32_NOREX2RegClassID,
6682 X86::GR32_NOREX2_NOSPRegClassID,
6683 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
6684 X86::GR32_NOREXRegClassID,
6685 X86::GR32_NOREX_NOSPRegClassID,
6686};
6687
6688static unsigned const GR32_CBSuperclasses[] = {
6689 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
6690 X86::LOW32_ADDR_ACCESSRegClassID,
6691 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
6692 X86::GR32RegClassID,
6693 X86::GR32_NOSPRegClassID,
6694 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
6695 X86::GR32_NOREX2RegClassID,
6696 X86::GR32_NOREX2_NOSPRegClassID,
6697 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
6698 X86::GR32_NOREXRegClassID,
6699 X86::GR32_NOREX_NOSPRegClassID,
6700 X86::GR32_ABCDRegClassID,
6701};
6702
6703static unsigned const GR32_DCSuperclasses[] = {
6704 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
6705 X86::LOW32_ADDR_ACCESSRegClassID,
6706 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
6707 X86::GR32RegClassID,
6708 X86::GR32_NOSPRegClassID,
6709 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
6710 X86::GR32_NOREX2RegClassID,
6711 X86::GR32_NOREX2_NOSPRegClassID,
6712 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
6713 X86::GR32_NOREXRegClassID,
6714 X86::GR32_NOREX_NOSPRegClassID,
6715 X86::GR32_ABCDRegClassID,
6716 X86::GR32_TCRegClassID,
6717 X86::GR32_ABCD_and_GR32_TCRegClassID,
6718 X86::GR32_ArgRefRegClassID,
6719};
6720
6721static unsigned const GR32_DIBPSuperclasses[] = {
6722 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
6723 X86::LOW32_ADDR_ACCESSRegClassID,
6724 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
6725 X86::GR32RegClassID,
6726 X86::GR32_NOSPRegClassID,
6727 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
6728 X86::GR32_NOREX2RegClassID,
6729 X86::GR32_NOREX2_NOSPRegClassID,
6730 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
6731 X86::GR32_NOREXRegClassID,
6732 X86::GR32_NOREX_NOSPRegClassID,
6733};
6734
6735static unsigned const GR32_SIDISuperclasses[] = {
6736 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
6737 X86::LOW32_ADDR_ACCESSRegClassID,
6738 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
6739 X86::GR32RegClassID,
6740 X86::GR32_NOSPRegClassID,
6741 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
6742 X86::GR32_NOREX2RegClassID,
6743 X86::GR32_NOREX2_NOSPRegClassID,
6744 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
6745 X86::GR32_NOREXRegClassID,
6746 X86::GR32_NOREX_NOSPRegClassID,
6747};
6748
6749static unsigned const LOW32_ADDR_ACCESS_RBP_with_sub_32bitSuperclasses[] = {
6750 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
6751};
6752
6753static unsigned const GR32_ABCD_and_GR32_BSISuperclasses[] = {
6754 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
6755 X86::LOW32_ADDR_ACCESSRegClassID,
6756 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
6757 X86::GR32RegClassID,
6758 X86::GR32_NOSPRegClassID,
6759 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
6760 X86::GR32_NOREX2RegClassID,
6761 X86::GR32_NOREX2_NOSPRegClassID,
6762 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
6763 X86::GR32_NOREXRegClassID,
6764 X86::GR32_NOREX_NOSPRegClassID,
6765 X86::GR32_ABCDRegClassID,
6766 X86::GR32_BSIRegClassID,
6767 X86::GR32_CBRegClassID,
6768};
6769
6770static unsigned const GR32_AD_and_GR32_ArgRefSuperclasses[] = {
6771 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
6772 X86::LOW32_ADDR_ACCESSRegClassID,
6773 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
6774 X86::GR32RegClassID,
6775 X86::GR32_NOSPRegClassID,
6776 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
6777 X86::GR32_NOREX2RegClassID,
6778 X86::GR32_NOREX2_NOSPRegClassID,
6779 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
6780 X86::GR32_NOREXRegClassID,
6781 X86::GR32_NOREX_NOSPRegClassID,
6782 X86::GR32_ABCDRegClassID,
6783 X86::GR32_TCRegClassID,
6784 X86::GR32_ABCD_and_GR32_TCRegClassID,
6785 X86::GR32_ADRegClassID,
6786 X86::GR32_ArgRefRegClassID,
6787 X86::GR32_DCRegClassID,
6788};
6789
6790static unsigned const GR32_ArgRef_and_GR32_CBSuperclasses[] = {
6791 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
6792 X86::LOW32_ADDR_ACCESSRegClassID,
6793 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
6794 X86::GR32RegClassID,
6795 X86::GR32_NOSPRegClassID,
6796 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
6797 X86::GR32_NOREX2RegClassID,
6798 X86::GR32_NOREX2_NOSPRegClassID,
6799 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
6800 X86::GR32_NOREXRegClassID,
6801 X86::GR32_NOREX_NOSPRegClassID,
6802 X86::GR32_ABCDRegClassID,
6803 X86::GR32_TCRegClassID,
6804 X86::GR32_ABCD_and_GR32_TCRegClassID,
6805 X86::GR32_ArgRefRegClassID,
6806 X86::GR32_CBRegClassID,
6807 X86::GR32_DCRegClassID,
6808};
6809
6810static unsigned const GR32_BPSP_and_GR32_DIBPSuperclasses[] = {
6811 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
6812 X86::LOW32_ADDR_ACCESSRegClassID,
6813 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
6814 X86::GR32RegClassID,
6815 X86::GR32_NOSPRegClassID,
6816 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
6817 X86::GR32_NOREX2RegClassID,
6818 X86::GR32_NOREX2_NOSPRegClassID,
6819 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
6820 X86::GR32_NOREXRegClassID,
6821 X86::GR32_NOREX_NOSPRegClassID,
6822 X86::GR32_BPSPRegClassID,
6823 X86::GR32_DIBPRegClassID,
6824};
6825
6826static unsigned const GR32_BPSP_and_GR32_TCSuperclasses[] = {
6827 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
6828 X86::LOW32_ADDR_ACCESSRegClassID,
6829 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
6830 X86::GR32RegClassID,
6831 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
6832 X86::GR32_NOREX2RegClassID,
6833 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
6834 X86::GR32_NOREXRegClassID,
6835 X86::GR32_TCRegClassID,
6836 X86::GR32_BPSPRegClassID,
6837};
6838
6839static unsigned const GR32_BSI_and_GR32_SIDISuperclasses[] = {
6840 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
6841 X86::LOW32_ADDR_ACCESSRegClassID,
6842 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
6843 X86::GR32RegClassID,
6844 X86::GR32_NOSPRegClassID,
6845 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
6846 X86::GR32_NOREX2RegClassID,
6847 X86::GR32_NOREX2_NOSPRegClassID,
6848 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
6849 X86::GR32_NOREXRegClassID,
6850 X86::GR32_NOREX_NOSPRegClassID,
6851 X86::GR32_BSIRegClassID,
6852 X86::GR32_SIDIRegClassID,
6853};
6854
6855static unsigned const GR32_DIBP_and_GR32_SIDISuperclasses[] = {
6856 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
6857 X86::LOW32_ADDR_ACCESSRegClassID,
6858 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
6859 X86::GR32RegClassID,
6860 X86::GR32_NOSPRegClassID,
6861 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
6862 X86::GR32_NOREX2RegClassID,
6863 X86::GR32_NOREX2_NOSPRegClassID,
6864 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
6865 X86::GR32_NOREXRegClassID,
6866 X86::GR32_NOREX_NOSPRegClassID,
6867 X86::GR32_DIBPRegClassID,
6868 X86::GR32_SIDIRegClassID,
6869};
6870
6871static unsigned const LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitSuperclasses[] = {
6872 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
6873 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
6874 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
6875 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
6876 X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID,
6877};
6878
6879static unsigned const LOW32_ADDR_ACCESS_with_sub_32bitSuperclasses[] = {
6880 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
6881 X86::LOW32_ADDR_ACCESSRegClassID,
6882 X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID,
6883};
6884
6885static unsigned const RFP64Superclasses[] = {
6886 X86::RFP32RegClassID,
6887};
6888
6889static unsigned const FR64XSuperclasses[] = {
6890 X86::FR16XRegClassID,
6891 X86::FR32XRegClassID,
6892};
6893
6894static unsigned const GR64_with_sub_8bitSuperclasses[] = {
6895 X86::GR64RegClassID,
6896};
6897
6898static unsigned const GR64_NOSPSuperclasses[] = {
6899 X86::GR64RegClassID,
6900 X86::GR64_with_sub_8bitRegClassID,
6901};
6902
6903static unsigned const GR64_NOREX2Superclasses[] = {
6904 X86::GR64RegClassID,
6905};
6906
6907static unsigned const FR64Superclasses[] = {
6908 X86::FR16XRegClassID,
6909 X86::FR16RegClassID,
6910 X86::FR32XRegClassID,
6911 X86::FR32RegClassID,
6912 X86::FR64XRegClassID,
6913};
6914
6915static unsigned const GR64_with_sub_16bit_in_GR16_NOREX2Superclasses[] = {
6916 X86::GR64RegClassID,
6917 X86::GR64_with_sub_8bitRegClassID,
6918 X86::GR64_NOREX2RegClassID,
6919};
6920
6921static unsigned const GR64_NOREX2_NOSPSuperclasses[] = {
6922 X86::GR64RegClassID,
6923 X86::GR64_with_sub_8bitRegClassID,
6924 X86::GR64_NOSPRegClassID,
6925 X86::GR64_NOREX2RegClassID,
6926 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
6927};
6928
6929static unsigned const GR64PLTSafeSuperclasses[] = {
6930 X86::GR64RegClassID,
6931 X86::GR64_with_sub_8bitRegClassID,
6932 X86::GR64_NOSPRegClassID,
6933 X86::GR64_NOREX2RegClassID,
6934 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
6935 X86::GR64_NOREX2_NOSPRegClassID,
6936};
6937
6938static unsigned const GR64_TCSuperclasses[] = {
6939 X86::GR64RegClassID,
6940 X86::GR64_NOREX2RegClassID,
6941};
6942
6943static unsigned const GR64_NOREXSuperclasses[] = {
6944 X86::GR64RegClassID,
6945 X86::GR64_NOREX2RegClassID,
6946};
6947
6948static unsigned const GR64_TCW64Superclasses[] = {
6949 X86::GR64RegClassID,
6950 X86::GR64_NOREX2RegClassID,
6951};
6952
6953static unsigned const GR64_TC_with_sub_8bitSuperclasses[] = {
6954 X86::GR64RegClassID,
6955 X86::GR64_with_sub_8bitRegClassID,
6956 X86::GR64_NOREX2RegClassID,
6957 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
6958 X86::GR64_TCRegClassID,
6959};
6960
6961static unsigned const GR64_NOREX2_NOSP_and_GR64_TCSuperclasses[] = {
6962 X86::GR64RegClassID,
6963 X86::GR64_with_sub_8bitRegClassID,
6964 X86::GR64_NOSPRegClassID,
6965 X86::GR64_NOREX2RegClassID,
6966 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
6967 X86::GR64_NOREX2_NOSPRegClassID,
6968 X86::GR64_TCRegClassID,
6969 X86::GR64_TC_with_sub_8bitRegClassID,
6970};
6971
6972static unsigned const GR64_TCW64_with_sub_8bitSuperclasses[] = {
6973 X86::GR64RegClassID,
6974 X86::GR64_with_sub_8bitRegClassID,
6975 X86::GR64_NOREX2RegClassID,
6976 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
6977 X86::GR64_TCW64RegClassID,
6978};
6979
6980static unsigned const GR64_TC_and_GR64_TCW64Superclasses[] = {
6981 X86::GR64RegClassID,
6982 X86::GR64_NOREX2RegClassID,
6983 X86::GR64_TCRegClassID,
6984 X86::GR64_TCW64RegClassID,
6985};
6986
6987static unsigned const GR64_with_sub_16bit_in_GR16_NOREXSuperclasses[] = {
6988 X86::GR64RegClassID,
6989 X86::GR64_with_sub_8bitRegClassID,
6990 X86::GR64_NOREX2RegClassID,
6991 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
6992 X86::GR64_NOREXRegClassID,
6993};
6994
6995static unsigned const VK64Superclasses[] = {
6996 X86::VK1RegClassID,
6997 X86::VK16RegClassID,
6998 X86::VK2RegClassID,
6999 X86::VK4RegClassID,
7000 X86::VK8RegClassID,
7001 X86::VK32RegClassID,
7002};
7003
7004static unsigned const GR64PLTSafe_and_GR64_TCSuperclasses[] = {
7005 X86::GR64RegClassID,
7006 X86::GR64_with_sub_8bitRegClassID,
7007 X86::GR64_NOSPRegClassID,
7008 X86::GR64_NOREX2RegClassID,
7009 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
7010 X86::GR64_NOREX2_NOSPRegClassID,
7011 X86::GR64PLTSafeRegClassID,
7012 X86::GR64_TCRegClassID,
7013 X86::GR64_TC_with_sub_8bitRegClassID,
7014 X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
7015};
7016
7017static unsigned const GR64_NOREX2_NOSP_and_GR64_TCW64Superclasses[] = {
7018 X86::GR64RegClassID,
7019 X86::GR64_with_sub_8bitRegClassID,
7020 X86::GR64_NOSPRegClassID,
7021 X86::GR64_NOREX2RegClassID,
7022 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
7023 X86::GR64_NOREX2_NOSPRegClassID,
7024 X86::GR64_TCW64RegClassID,
7025 X86::GR64_TCW64_with_sub_8bitRegClassID,
7026};
7027
7028static unsigned const GR64_NOREX_NOSPSuperclasses[] = {
7029 X86::GR64RegClassID,
7030 X86::GR64_with_sub_8bitRegClassID,
7031 X86::GR64_NOSPRegClassID,
7032 X86::GR64_NOREX2RegClassID,
7033 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
7034 X86::GR64_NOREX2_NOSPRegClassID,
7035 X86::GR64PLTSafeRegClassID,
7036 X86::GR64_NOREXRegClassID,
7037 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
7038};
7039
7040static unsigned const GR64_NOREX_and_GR64_TCSuperclasses[] = {
7041 X86::GR64RegClassID,
7042 X86::GR64_NOREX2RegClassID,
7043 X86::GR64_TCRegClassID,
7044 X86::GR64_NOREXRegClassID,
7045};
7046
7047static unsigned const GR64_TCW64_and_GR64_TC_with_sub_8bitSuperclasses[] = {
7048 X86::GR64RegClassID,
7049 X86::GR64_with_sub_8bitRegClassID,
7050 X86::GR64_NOREX2RegClassID,
7051 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
7052 X86::GR64_TCRegClassID,
7053 X86::GR64_TCW64RegClassID,
7054 X86::GR64_TC_with_sub_8bitRegClassID,
7055 X86::GR64_TCW64_with_sub_8bitRegClassID,
7056 X86::GR64_TC_and_GR64_TCW64RegClassID,
7057};
7058
7059static unsigned const VK64WMSuperclasses[] = {
7060 X86::VK1RegClassID,
7061 X86::VK16RegClassID,
7062 X86::VK2RegClassID,
7063 X86::VK4RegClassID,
7064 X86::VK8RegClassID,
7065 X86::VK16WMRegClassID,
7066 X86::VK1WMRegClassID,
7067 X86::VK2WMRegClassID,
7068 X86::VK4WMRegClassID,
7069 X86::VK8WMRegClassID,
7070 X86::VK32RegClassID,
7071 X86::VK32WMRegClassID,
7072 X86::VK64RegClassID,
7073};
7074
7075static unsigned const GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64Superclasses[] = {
7076 X86::GR64RegClassID,
7077 X86::GR64_with_sub_8bitRegClassID,
7078 X86::GR64_NOSPRegClassID,
7079 X86::GR64_NOREX2RegClassID,
7080 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
7081 X86::GR64_NOREX2_NOSPRegClassID,
7082 X86::GR64_TCRegClassID,
7083 X86::GR64_TCW64RegClassID,
7084 X86::GR64_TC_with_sub_8bitRegClassID,
7085 X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
7086 X86::GR64_TCW64_with_sub_8bitRegClassID,
7087 X86::GR64_TC_and_GR64_TCW64RegClassID,
7088 X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
7089 X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID,
7090};
7091
7092static unsigned const GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXSuperclasses[] = {
7093 X86::GR64RegClassID,
7094 X86::GR64_with_sub_8bitRegClassID,
7095 X86::GR64_NOREX2RegClassID,
7096 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
7097 X86::GR64_TCRegClassID,
7098 X86::GR64_NOREXRegClassID,
7099 X86::GR64_TC_with_sub_8bitRegClassID,
7100 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
7101 X86::GR64_NOREX_and_GR64_TCRegClassID,
7102};
7103
7104static unsigned const GR64PLTSafe_and_GR64_TCW64Superclasses[] = {
7105 X86::GR64RegClassID,
7106 X86::GR64_with_sub_8bitRegClassID,
7107 X86::GR64_NOSPRegClassID,
7108 X86::GR64_NOREX2RegClassID,
7109 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
7110 X86::GR64_NOREX2_NOSPRegClassID,
7111 X86::GR64PLTSafeRegClassID,
7112 X86::GR64_TCRegClassID,
7113 X86::GR64_TCW64RegClassID,
7114 X86::GR64_TC_with_sub_8bitRegClassID,
7115 X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
7116 X86::GR64_TCW64_with_sub_8bitRegClassID,
7117 X86::GR64_TC_and_GR64_TCW64RegClassID,
7118 X86::GR64PLTSafe_and_GR64_TCRegClassID,
7119 X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
7120 X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID,
7121 X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
7122};
7123
7124static unsigned const GR64_NOREX_and_GR64PLTSafe_and_GR64_TCSuperclasses[] = {
7125 X86::GR64RegClassID,
7126 X86::GR64_with_sub_8bitRegClassID,
7127 X86::GR64_NOSPRegClassID,
7128 X86::GR64_NOREX2RegClassID,
7129 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
7130 X86::GR64_NOREX2_NOSPRegClassID,
7131 X86::GR64PLTSafeRegClassID,
7132 X86::GR64_TCRegClassID,
7133 X86::GR64_NOREXRegClassID,
7134 X86::GR64_TC_with_sub_8bitRegClassID,
7135 X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
7136 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
7137 X86::GR64PLTSafe_and_GR64_TCRegClassID,
7138 X86::GR64_NOREX_NOSPRegClassID,
7139 X86::GR64_NOREX_and_GR64_TCRegClassID,
7140 X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
7141};
7142
7143static unsigned const GR64_NOREX_and_GR64_TCW64Superclasses[] = {
7144 X86::GR64RegClassID,
7145 X86::GR64_NOREX2RegClassID,
7146 X86::GR64_TCRegClassID,
7147 X86::GR64_NOREXRegClassID,
7148 X86::GR64_TCW64RegClassID,
7149 X86::GR64_TC_and_GR64_TCW64RegClassID,
7150 X86::GR64_NOREX_and_GR64_TCRegClassID,
7151};
7152
7153static unsigned const GR64_ABCDSuperclasses[] = {
7154 X86::GR64RegClassID,
7155 X86::GR64_with_sub_8bitRegClassID,
7156 X86::GR64_NOSPRegClassID,
7157 X86::GR64_NOREX2RegClassID,
7158 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
7159 X86::GR64_NOREX2_NOSPRegClassID,
7160 X86::GR64PLTSafeRegClassID,
7161 X86::GR64_NOREXRegClassID,
7162 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
7163 X86::GR64_NOREX_NOSPRegClassID,
7164};
7165
7166static unsigned const GR64_with_sub_32bit_in_GR32_TCSuperclasses[] = {
7167 X86::GR64RegClassID,
7168 X86::GR64_with_sub_8bitRegClassID,
7169 X86::GR64_NOREX2RegClassID,
7170 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
7171 X86::GR64_TCRegClassID,
7172 X86::GR64_NOREXRegClassID,
7173 X86::GR64_TCW64RegClassID,
7174 X86::GR64_TC_with_sub_8bitRegClassID,
7175 X86::GR64_TCW64_with_sub_8bitRegClassID,
7176 X86::GR64_TC_and_GR64_TCW64RegClassID,
7177 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
7178 X86::GR64_NOREX_and_GR64_TCRegClassID,
7179 X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID,
7180 X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
7181 X86::GR64_NOREX_and_GR64_TCW64RegClassID,
7182};
7183
7184static unsigned const GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCSuperclasses[] = {
7185 X86::GR64RegClassID,
7186 X86::GR64_with_sub_8bitRegClassID,
7187 X86::GR64_NOSPRegClassID,
7188 X86::GR64_NOREX2RegClassID,
7189 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
7190 X86::GR64_NOREX2_NOSPRegClassID,
7191 X86::GR64PLTSafeRegClassID,
7192 X86::GR64_TCRegClassID,
7193 X86::GR64_NOREXRegClassID,
7194 X86::GR64_TCW64RegClassID,
7195 X86::GR64_TC_with_sub_8bitRegClassID,
7196 X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
7197 X86::GR64_TCW64_with_sub_8bitRegClassID,
7198 X86::GR64_TC_and_GR64_TCW64RegClassID,
7199 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
7200 X86::GR64PLTSafe_and_GR64_TCRegClassID,
7201 X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
7202 X86::GR64_NOREX_NOSPRegClassID,
7203 X86::GR64_NOREX_and_GR64_TCRegClassID,
7204 X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID,
7205 X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
7206 X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
7207 X86::GR64PLTSafe_and_GR64_TCW64RegClassID,
7208 X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID,
7209 X86::GR64_NOREX_and_GR64_TCW64RegClassID,
7210 X86::GR64_ABCDRegClassID,
7211 X86::GR64_with_sub_32bit_in_GR32_TCRegClassID,
7212};
7213
7214static unsigned const GR64_ADSuperclasses[] = {
7215 X86::GR64RegClassID,
7216 X86::GR64_with_sub_8bitRegClassID,
7217 X86::GR64_NOSPRegClassID,
7218 X86::GR64_NOREX2RegClassID,
7219 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
7220 X86::GR64_NOREX2_NOSPRegClassID,
7221 X86::GR64PLTSafeRegClassID,
7222 X86::GR64_TCRegClassID,
7223 X86::GR64_NOREXRegClassID,
7224 X86::GR64_TCW64RegClassID,
7225 X86::GR64_TC_with_sub_8bitRegClassID,
7226 X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
7227 X86::GR64_TCW64_with_sub_8bitRegClassID,
7228 X86::GR64_TC_and_GR64_TCW64RegClassID,
7229 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
7230 X86::GR64PLTSafe_and_GR64_TCRegClassID,
7231 X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
7232 X86::GR64_NOREX_NOSPRegClassID,
7233 X86::GR64_NOREX_and_GR64_TCRegClassID,
7234 X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID,
7235 X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
7236 X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
7237 X86::GR64PLTSafe_and_GR64_TCW64RegClassID,
7238 X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID,
7239 X86::GR64_NOREX_and_GR64_TCW64RegClassID,
7240 X86::GR64_ABCDRegClassID,
7241 X86::GR64_with_sub_32bit_in_GR32_TCRegClassID,
7242 X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID,
7243};
7244
7245static unsigned const GR64_ArgRefSuperclasses[] = {
7246 X86::GR64RegClassID,
7247 X86::GR64_with_sub_8bitRegClassID,
7248 X86::GR64_NOSPRegClassID,
7249 X86::GR64_NOREX2RegClassID,
7250 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
7251 X86::GR64_NOREX2_NOSPRegClassID,
7252 X86::GR64_TCW64RegClassID,
7253 X86::GR64_TCW64_with_sub_8bitRegClassID,
7254 X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
7255};
7256
7257static unsigned const GR64_and_LOW32_ADDR_ACCESS_RBPSuperclasses[] = {
7258 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
7259 X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID,
7260 X86::GR64RegClassID,
7261 X86::GR64_NOREX2RegClassID,
7262 X86::GR64_NOREXRegClassID,
7263};
7264
7265static unsigned const GR64_with_sub_32bit_in_GR32_ArgRefSuperclasses[] = {
7266 X86::GR64RegClassID,
7267 X86::GR64_with_sub_8bitRegClassID,
7268 X86::GR64_NOSPRegClassID,
7269 X86::GR64_NOREX2RegClassID,
7270 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
7271 X86::GR64_NOREX2_NOSPRegClassID,
7272 X86::GR64PLTSafeRegClassID,
7273 X86::GR64_TCRegClassID,
7274 X86::GR64_NOREXRegClassID,
7275 X86::GR64_TCW64RegClassID,
7276 X86::GR64_TC_with_sub_8bitRegClassID,
7277 X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
7278 X86::GR64_TCW64_with_sub_8bitRegClassID,
7279 X86::GR64_TC_and_GR64_TCW64RegClassID,
7280 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
7281 X86::GR64PLTSafe_and_GR64_TCRegClassID,
7282 X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
7283 X86::GR64_NOREX_NOSPRegClassID,
7284 X86::GR64_NOREX_and_GR64_TCRegClassID,
7285 X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID,
7286 X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
7287 X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
7288 X86::GR64PLTSafe_and_GR64_TCW64RegClassID,
7289 X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID,
7290 X86::GR64_NOREX_and_GR64_TCW64RegClassID,
7291 X86::GR64_ABCDRegClassID,
7292 X86::GR64_with_sub_32bit_in_GR32_TCRegClassID,
7293 X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID,
7294};
7295
7296static unsigned const GR64_with_sub_32bit_in_GR32_BPSPSuperclasses[] = {
7297 X86::GR64RegClassID,
7298 X86::GR64_with_sub_8bitRegClassID,
7299 X86::GR64_NOREX2RegClassID,
7300 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
7301 X86::GR64_NOREXRegClassID,
7302 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
7303};
7304
7305static unsigned const GR64_with_sub_32bit_in_GR32_BSISuperclasses[] = {
7306 X86::GR64RegClassID,
7307 X86::GR64_with_sub_8bitRegClassID,
7308 X86::GR64_NOSPRegClassID,
7309 X86::GR64_NOREX2RegClassID,
7310 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
7311 X86::GR64_NOREX2_NOSPRegClassID,
7312 X86::GR64PLTSafeRegClassID,
7313 X86::GR64_NOREXRegClassID,
7314 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
7315 X86::GR64_NOREX_NOSPRegClassID,
7316};
7317
7318static unsigned const GR64_with_sub_32bit_in_GR32_CBSuperclasses[] = {
7319 X86::GR64RegClassID,
7320 X86::GR64_with_sub_8bitRegClassID,
7321 X86::GR64_NOSPRegClassID,
7322 X86::GR64_NOREX2RegClassID,
7323 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
7324 X86::GR64_NOREX2_NOSPRegClassID,
7325 X86::GR64PLTSafeRegClassID,
7326 X86::GR64_NOREXRegClassID,
7327 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
7328 X86::GR64_NOREX_NOSPRegClassID,
7329 X86::GR64_ABCDRegClassID,
7330};
7331
7332static unsigned const GR64_with_sub_32bit_in_GR32_DIBPSuperclasses[] = {
7333 X86::GR64RegClassID,
7334 X86::GR64_with_sub_8bitRegClassID,
7335 X86::GR64_NOSPRegClassID,
7336 X86::GR64_NOREX2RegClassID,
7337 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
7338 X86::GR64_NOREX2_NOSPRegClassID,
7339 X86::GR64PLTSafeRegClassID,
7340 X86::GR64_NOREXRegClassID,
7341 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
7342 X86::GR64_NOREX_NOSPRegClassID,
7343};
7344
7345static unsigned const GR64_with_sub_32bit_in_GR32_SIDISuperclasses[] = {
7346 X86::GR64RegClassID,
7347 X86::GR64_with_sub_8bitRegClassID,
7348 X86::GR64_NOSPRegClassID,
7349 X86::GR64_NOREX2RegClassID,
7350 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
7351 X86::GR64_NOREX2_NOSPRegClassID,
7352 X86::GR64PLTSafeRegClassID,
7353 X86::GR64_TCRegClassID,
7354 X86::GR64_NOREXRegClassID,
7355 X86::GR64_TC_with_sub_8bitRegClassID,
7356 X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
7357 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
7358 X86::GR64PLTSafe_and_GR64_TCRegClassID,
7359 X86::GR64_NOREX_NOSPRegClassID,
7360 X86::GR64_NOREX_and_GR64_TCRegClassID,
7361 X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
7362 X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID,
7363};
7364
7365static unsigned const GR64_ASuperclasses[] = {
7366 X86::GR64RegClassID,
7367 X86::GR64_with_sub_8bitRegClassID,
7368 X86::GR64_NOSPRegClassID,
7369 X86::GR64_NOREX2RegClassID,
7370 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
7371 X86::GR64_NOREX2_NOSPRegClassID,
7372 X86::GR64PLTSafeRegClassID,
7373 X86::GR64_TCRegClassID,
7374 X86::GR64_NOREXRegClassID,
7375 X86::GR64_TCW64RegClassID,
7376 X86::GR64_TC_with_sub_8bitRegClassID,
7377 X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
7378 X86::GR64_TCW64_with_sub_8bitRegClassID,
7379 X86::GR64_TC_and_GR64_TCW64RegClassID,
7380 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
7381 X86::GR64PLTSafe_and_GR64_TCRegClassID,
7382 X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
7383 X86::GR64_NOREX_NOSPRegClassID,
7384 X86::GR64_NOREX_and_GR64_TCRegClassID,
7385 X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID,
7386 X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
7387 X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
7388 X86::GR64PLTSafe_and_GR64_TCW64RegClassID,
7389 X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID,
7390 X86::GR64_NOREX_and_GR64_TCW64RegClassID,
7391 X86::GR64_ABCDRegClassID,
7392 X86::GR64_with_sub_32bit_in_GR32_TCRegClassID,
7393 X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID,
7394 X86::GR64_ADRegClassID,
7395};
7396
7397static unsigned const GR64_ArgRef_and_GR64_TCSuperclasses[] = {
7398 X86::GR64RegClassID,
7399 X86::GR64_with_sub_8bitRegClassID,
7400 X86::GR64_NOSPRegClassID,
7401 X86::GR64_NOREX2RegClassID,
7402 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
7403 X86::GR64_NOREX2_NOSPRegClassID,
7404 X86::GR64_TCRegClassID,
7405 X86::GR64_TCW64RegClassID,
7406 X86::GR64_TC_with_sub_8bitRegClassID,
7407 X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
7408 X86::GR64_TCW64_with_sub_8bitRegClassID,
7409 X86::GR64_TC_and_GR64_TCW64RegClassID,
7410 X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
7411 X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID,
7412 X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
7413 X86::GR64_ArgRefRegClassID,
7414};
7415
7416static unsigned const GR64_and_LOW32_ADDR_ACCESSSuperclasses[] = {
7417 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
7418 X86::LOW32_ADDR_ACCESSRegClassID,
7419 X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID,
7420 X86::LOW32_ADDR_ACCESS_with_sub_32bitRegClassID,
7421 X86::GR64RegClassID,
7422 X86::GR64_NOREX2RegClassID,
7423 X86::GR64_TCRegClassID,
7424 X86::GR64_NOREXRegClassID,
7425 X86::GR64_TCW64RegClassID,
7426 X86::GR64_TC_and_GR64_TCW64RegClassID,
7427 X86::GR64_NOREX_and_GR64_TCRegClassID,
7428 X86::GR64_NOREX_and_GR64_TCW64RegClassID,
7429 X86::GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID,
7430};
7431
7432static unsigned const GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSISuperclasses[] = {
7433 X86::GR64RegClassID,
7434 X86::GR64_with_sub_8bitRegClassID,
7435 X86::GR64_NOSPRegClassID,
7436 X86::GR64_NOREX2RegClassID,
7437 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
7438 X86::GR64_NOREX2_NOSPRegClassID,
7439 X86::GR64PLTSafeRegClassID,
7440 X86::GR64_NOREXRegClassID,
7441 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
7442 X86::GR64_NOREX_NOSPRegClassID,
7443 X86::GR64_ABCDRegClassID,
7444 X86::GR64_with_sub_32bit_in_GR32_BSIRegClassID,
7445 X86::GR64_with_sub_32bit_in_GR32_CBRegClassID,
7446};
7447
7448static unsigned const GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefSuperclasses[] = {
7449 X86::GR64RegClassID,
7450 X86::GR64_with_sub_8bitRegClassID,
7451 X86::GR64_NOSPRegClassID,
7452 X86::GR64_NOREX2RegClassID,
7453 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
7454 X86::GR64_NOREX2_NOSPRegClassID,
7455 X86::GR64PLTSafeRegClassID,
7456 X86::GR64_TCRegClassID,
7457 X86::GR64_NOREXRegClassID,
7458 X86::GR64_TCW64RegClassID,
7459 X86::GR64_TC_with_sub_8bitRegClassID,
7460 X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
7461 X86::GR64_TCW64_with_sub_8bitRegClassID,
7462 X86::GR64_TC_and_GR64_TCW64RegClassID,
7463 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
7464 X86::GR64PLTSafe_and_GR64_TCRegClassID,
7465 X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
7466 X86::GR64_NOREX_NOSPRegClassID,
7467 X86::GR64_NOREX_and_GR64_TCRegClassID,
7468 X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID,
7469 X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
7470 X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
7471 X86::GR64PLTSafe_and_GR64_TCW64RegClassID,
7472 X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID,
7473 X86::GR64_NOREX_and_GR64_TCW64RegClassID,
7474 X86::GR64_ABCDRegClassID,
7475 X86::GR64_with_sub_32bit_in_GR32_TCRegClassID,
7476 X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID,
7477 X86::GR64_ADRegClassID,
7478 X86::GR64_with_sub_32bit_in_GR32_ArgRefRegClassID,
7479};
7480
7481static unsigned const GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBSuperclasses[] = {
7482 X86::GR64RegClassID,
7483 X86::GR64_with_sub_8bitRegClassID,
7484 X86::GR64_NOSPRegClassID,
7485 X86::GR64_NOREX2RegClassID,
7486 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
7487 X86::GR64_NOREX2_NOSPRegClassID,
7488 X86::GR64PLTSafeRegClassID,
7489 X86::GR64_TCRegClassID,
7490 X86::GR64_NOREXRegClassID,
7491 X86::GR64_TCW64RegClassID,
7492 X86::GR64_TC_with_sub_8bitRegClassID,
7493 X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
7494 X86::GR64_TCW64_with_sub_8bitRegClassID,
7495 X86::GR64_TC_and_GR64_TCW64RegClassID,
7496 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
7497 X86::GR64PLTSafe_and_GR64_TCRegClassID,
7498 X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
7499 X86::GR64_NOREX_NOSPRegClassID,
7500 X86::GR64_NOREX_and_GR64_TCRegClassID,
7501 X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID,
7502 X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
7503 X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
7504 X86::GR64PLTSafe_and_GR64_TCW64RegClassID,
7505 X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID,
7506 X86::GR64_NOREX_and_GR64_TCW64RegClassID,
7507 X86::GR64_ABCDRegClassID,
7508 X86::GR64_with_sub_32bit_in_GR32_TCRegClassID,
7509 X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID,
7510 X86::GR64_with_sub_32bit_in_GR32_ArgRefRegClassID,
7511 X86::GR64_with_sub_32bit_in_GR32_CBRegClassID,
7512};
7513
7514static unsigned const GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPSuperclasses[] = {
7515 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
7516 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
7517 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
7518 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
7519 X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID,
7520 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClassID,
7521 X86::GR64RegClassID,
7522 X86::GR64_with_sub_8bitRegClassID,
7523 X86::GR64_NOSPRegClassID,
7524 X86::GR64_NOREX2RegClassID,
7525 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
7526 X86::GR64_NOREX2_NOSPRegClassID,
7527 X86::GR64PLTSafeRegClassID,
7528 X86::GR64_NOREXRegClassID,
7529 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
7530 X86::GR64_NOREX_NOSPRegClassID,
7531 X86::GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID,
7532 X86::GR64_with_sub_32bit_in_GR32_BPSPRegClassID,
7533 X86::GR64_with_sub_32bit_in_GR32_DIBPRegClassID,
7534};
7535
7536static unsigned const GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCSuperclasses[] = {
7537 X86::GR64RegClassID,
7538 X86::GR64_with_sub_8bitRegClassID,
7539 X86::GR64_NOREX2RegClassID,
7540 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
7541 X86::GR64_TCRegClassID,
7542 X86::GR64_NOREXRegClassID,
7543 X86::GR64_TCW64RegClassID,
7544 X86::GR64_TC_with_sub_8bitRegClassID,
7545 X86::GR64_TCW64_with_sub_8bitRegClassID,
7546 X86::GR64_TC_and_GR64_TCW64RegClassID,
7547 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
7548 X86::GR64_NOREX_and_GR64_TCRegClassID,
7549 X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID,
7550 X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
7551 X86::GR64_NOREX_and_GR64_TCW64RegClassID,
7552 X86::GR64_with_sub_32bit_in_GR32_TCRegClassID,
7553 X86::GR64_with_sub_32bit_in_GR32_BPSPRegClassID,
7554};
7555
7556static unsigned const GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDISuperclasses[] = {
7557 X86::GR64RegClassID,
7558 X86::GR64_with_sub_8bitRegClassID,
7559 X86::GR64_NOSPRegClassID,
7560 X86::GR64_NOREX2RegClassID,
7561 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
7562 X86::GR64_NOREX2_NOSPRegClassID,
7563 X86::GR64PLTSafeRegClassID,
7564 X86::GR64_TCRegClassID,
7565 X86::GR64_NOREXRegClassID,
7566 X86::GR64_TC_with_sub_8bitRegClassID,
7567 X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
7568 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
7569 X86::GR64PLTSafe_and_GR64_TCRegClassID,
7570 X86::GR64_NOREX_NOSPRegClassID,
7571 X86::GR64_NOREX_and_GR64_TCRegClassID,
7572 X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
7573 X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID,
7574 X86::GR64_with_sub_32bit_in_GR32_BSIRegClassID,
7575 X86::GR64_with_sub_32bit_in_GR32_SIDIRegClassID,
7576};
7577
7578static unsigned const GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDISuperclasses[] = {
7579 X86::GR64RegClassID,
7580 X86::GR64_with_sub_8bitRegClassID,
7581 X86::GR64_NOSPRegClassID,
7582 X86::GR64_NOREX2RegClassID,
7583 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
7584 X86::GR64_NOREX2_NOSPRegClassID,
7585 X86::GR64PLTSafeRegClassID,
7586 X86::GR64_TCRegClassID,
7587 X86::GR64_NOREXRegClassID,
7588 X86::GR64_TC_with_sub_8bitRegClassID,
7589 X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
7590 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
7591 X86::GR64PLTSafe_and_GR64_TCRegClassID,
7592 X86::GR64_NOREX_NOSPRegClassID,
7593 X86::GR64_NOREX_and_GR64_TCRegClassID,
7594 X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
7595 X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID,
7596 X86::GR64_with_sub_32bit_in_GR32_DIBPRegClassID,
7597 X86::GR64_with_sub_32bit_in_GR32_SIDIRegClassID,
7598};
7599
7600static unsigned const RFP80Superclasses[] = {
7601 X86::RFP32RegClassID,
7602 X86::RFP64RegClassID,
7603};
7604
7605static unsigned const VR128XSuperclasses[] = {
7606 X86::FR16XRegClassID,
7607 X86::FR32XRegClassID,
7608 X86::FR64XRegClassID,
7609};
7610
7611static unsigned const VR128Superclasses[] = {
7612 X86::FR16XRegClassID,
7613 X86::FR16RegClassID,
7614 X86::FR32XRegClassID,
7615 X86::FR32RegClassID,
7616 X86::FR64XRegClassID,
7617 X86::FR64RegClassID,
7618 X86::VR128XRegClassID,
7619};
7620
7621static unsigned const VR256Superclasses[] = {
7622 X86::VR256XRegClassID,
7623};
7624
7625static unsigned const VR512_0_15Superclasses[] = {
7626 X86::VR512RegClassID,
7627};
7628
7629
7630static inline unsigned GR8AltOrderSelect(const MachineFunction &MF, bool Rev) {
7631 return MF.getSubtarget<X86Subtarget>().is64Bit();
7632 }
7633
7634static ArrayRef<MCPhysReg> GR8GetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
7635 static const MCPhysReg AltOrder1[] = { X86::AL, X86::CL, X86::DL, X86::BL, X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R16B, X86::R17B, X86::R18B, X86::R19B, X86::R22B, X86::R23B, X86::R24B, X86::R25B, X86::R26B, X86::R27B, X86::R30B, X86::R31B, X86::R14B, X86::R15B, X86::R12B, X86::R13B, X86::R20B, X86::R21B, X86::R28B, X86::R29B };
7636 const MCRegisterClass &MCR = X86MCRegisterClasses[X86::GR8RegClassID];
7637 const ArrayRef<MCPhysReg> Order[] = {
7638 ArrayRef(MCR.begin(), MCR.getNumRegs()),
7639 ArrayRef(AltOrder1)
7640 };
7641 const unsigned Select = GR8AltOrderSelect(MF, Rev);
7642 assert(Select < 2);
7643 return Order[Select];
7644}
7645
7646static inline unsigned GR8_NOREX2AltOrderSelect(const MachineFunction &MF, bool Rev) {
7647 return MF.getSubtarget<X86Subtarget>().is64Bit();
7648 }
7649
7650static ArrayRef<MCPhysReg> GR8_NOREX2GetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
7651 static const MCPhysReg AltOrder1[] = { X86::AL, X86::CL, X86::DL, X86::BL, X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R14B, X86::R15B, X86::R12B, X86::R13B };
7652 const MCRegisterClass &MCR = X86MCRegisterClasses[X86::GR8_NOREX2RegClassID];
7653 const ArrayRef<MCPhysReg> Order[] = {
7654 ArrayRef(MCR.begin(), MCR.getNumRegs()),
7655 ArrayRef(AltOrder1)
7656 };
7657 const unsigned Select = GR8_NOREX2AltOrderSelect(MF, Rev);
7658 assert(Select < 2);
7659 return Order[Select];
7660}
7661
7662static inline unsigned GR8_NOREXAltOrderSelect(const MachineFunction &MF, bool Rev) {
7663 return MF.getSubtarget<X86Subtarget>().is64Bit();
7664 }
7665
7666static ArrayRef<MCPhysReg> GR8_NOREXGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
7667 static const MCPhysReg AltOrder1[] = { X86::AL, X86::CL, X86::DL, X86::BL };
7668 const MCRegisterClass &MCR = X86MCRegisterClasses[X86::GR8_NOREXRegClassID];
7669 const ArrayRef<MCPhysReg> Order[] = {
7670 ArrayRef(MCR.begin(), MCR.getNumRegs()),
7671 ArrayRef(AltOrder1)
7672 };
7673 const unsigned Select = GR8_NOREXAltOrderSelect(MF, Rev);
7674 assert(Select < 2);
7675 return Order[Select];
7676}
7677
7678static inline unsigned FR32XAltOrderSelect(const MachineFunction &MF, bool Rev) {
7679 return Rev;
7680 }
7681
7682static ArrayRef<MCPhysReg> FR32XGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
7683 static const MCPhysReg AltOrder1[] = { X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15 };
7684 const MCRegisterClass &MCR = X86MCRegisterClasses[X86::FR32XRegClassID];
7685 const ArrayRef<MCPhysReg> Order[] = {
7686 ArrayRef(MCR.begin(), MCR.getNumRegs()),
7687 ArrayRef(AltOrder1)
7688 };
7689 const unsigned Select = FR32XAltOrderSelect(MF, Rev);
7690 assert(Select < 2);
7691 return Order[Select];
7692}
7693
7694static inline unsigned FR64XAltOrderSelect(const MachineFunction &MF, bool Rev) {
7695 return Rev;
7696 }
7697
7698static ArrayRef<MCPhysReg> FR64XGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
7699 static const MCPhysReg AltOrder1[] = { X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15 };
7700 const MCRegisterClass &MCR = X86MCRegisterClasses[X86::FR64XRegClassID];
7701 const ArrayRef<MCPhysReg> Order[] = {
7702 ArrayRef(MCR.begin(), MCR.getNumRegs()),
7703 ArrayRef(AltOrder1)
7704 };
7705 const unsigned Select = FR64XAltOrderSelect(MF, Rev);
7706 assert(Select < 2);
7707 return Order[Select];
7708}
7709
7710static inline unsigned VR128XAltOrderSelect(const MachineFunction &MF, bool Rev) {
7711 return Rev;
7712 }
7713
7714static ArrayRef<MCPhysReg> VR128XGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
7715 static const MCPhysReg AltOrder1[] = { X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15 };
7716 const MCRegisterClass &MCR = X86MCRegisterClasses[X86::VR128XRegClassID];
7717 const ArrayRef<MCPhysReg> Order[] = {
7718 ArrayRef(MCR.begin(), MCR.getNumRegs()),
7719 ArrayRef(AltOrder1)
7720 };
7721 const unsigned Select = VR128XAltOrderSelect(MF, Rev);
7722 assert(Select < 2);
7723 return Order[Select];
7724}
7725
7726static inline unsigned VR256XAltOrderSelect(const MachineFunction &MF, bool Rev) {
7727 return Rev;
7728 }
7729
7730static ArrayRef<MCPhysReg> VR256XGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
7731 static const MCPhysReg AltOrder1[] = { X86::YMM16, X86::YMM17, X86::YMM18, X86::YMM19, X86::YMM20, X86::YMM21, X86::YMM22, X86::YMM23, X86::YMM24, X86::YMM25, X86::YMM26, X86::YMM27, X86::YMM28, X86::YMM29, X86::YMM30, X86::YMM31, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15 };
7732 const MCRegisterClass &MCR = X86MCRegisterClasses[X86::VR256XRegClassID];
7733 const ArrayRef<MCPhysReg> Order[] = {
7734 ArrayRef(MCR.begin(), MCR.getNumRegs()),
7735 ArrayRef(AltOrder1)
7736 };
7737 const unsigned Select = VR256XAltOrderSelect(MF, Rev);
7738 assert(Select < 2);
7739 return Order[Select];
7740}
7741
7742namespace X86 { // Register class instances
7743 extern const TargetRegisterClass GR8RegClass = {
7744 &X86MCRegisterClasses[GR8RegClassID],
7745 GR8SubClassMask,
7746 SuperRegIdxSeqs + 2,
7747 LaneBitmask(0x0000000000000001),
7748 0,
7749 false,
7750 0x00, /* TSFlags */
7751 false, /* HasDisjunctSubRegs */
7752 false, /* CoveredBySubRegs */
7753 nullptr, 0,
7754 GR8GetRawAllocationOrder
7755 };
7756
7757 extern const TargetRegisterClass GRH8RegClass = {
7758 &X86MCRegisterClasses[GRH8RegClassID],
7759 GRH8SubClassMask,
7760 SuperRegIdxSeqs + 1,
7761 LaneBitmask(0x0000000000000001),
7762 0,
7763 false,
7764 0x00, /* TSFlags */
7765 false, /* HasDisjunctSubRegs */
7766 false, /* CoveredBySubRegs */
7767 nullptr, 0,
7768 nullptr
7769 };
7770
7771 extern const TargetRegisterClass GR8_NOREX2RegClass = {
7772 &X86MCRegisterClasses[GR8_NOREX2RegClassID],
7773 GR8_NOREX2SubClassMask,
7774 SuperRegIdxSeqs + 2,
7775 LaneBitmask(0x0000000000000001),
7776 0,
7777 false,
7778 0x00, /* TSFlags */
7779 false, /* HasDisjunctSubRegs */
7780 false, /* CoveredBySubRegs */
7781 GR8_NOREX2Superclasses, 1,
7782 GR8_NOREX2GetRawAllocationOrder
7783 };
7784
7785 extern const TargetRegisterClass GR8_NOREXRegClass = {
7786 &X86MCRegisterClasses[GR8_NOREXRegClassID],
7787 GR8_NOREXSubClassMask,
7788 SuperRegIdxSeqs + 2,
7789 LaneBitmask(0x0000000000000001),
7790 0,
7791 false,
7792 0x00, /* TSFlags */
7793 false, /* HasDisjunctSubRegs */
7794 false, /* CoveredBySubRegs */
7795 GR8_NOREXSuperclasses, 2,
7796 GR8_NOREXGetRawAllocationOrder
7797 };
7798
7799 extern const TargetRegisterClass GR8_ABCD_HRegClass = {
7800 &X86MCRegisterClasses[GR8_ABCD_HRegClassID],
7801 GR8_ABCD_HSubClassMask,
7802 SuperRegIdxSeqs + 3,
7803 LaneBitmask(0x0000000000000001),
7804 0,
7805 false,
7806 0x00, /* TSFlags */
7807 false, /* HasDisjunctSubRegs */
7808 false, /* CoveredBySubRegs */
7809 GR8_ABCD_HSuperclasses, 3,
7810 nullptr
7811 };
7812
7813 extern const TargetRegisterClass GR8_ABCD_LRegClass = {
7814 &X86MCRegisterClasses[GR8_ABCD_LRegClassID],
7815 GR8_ABCD_LSubClassMask,
7816 SuperRegIdxSeqs + 0,
7817 LaneBitmask(0x0000000000000001),
7818 0,
7819 false,
7820 0x00, /* TSFlags */
7821 false, /* HasDisjunctSubRegs */
7822 false, /* CoveredBySubRegs */
7823 GR8_ABCD_LSuperclasses, 3,
7824 nullptr
7825 };
7826
7827 extern const TargetRegisterClass GRH16RegClass = {
7828 &X86MCRegisterClasses[GRH16RegClassID],
7829 GRH16SubClassMask,
7830 SuperRegIdxSeqs + 1,
7831 LaneBitmask(0x0000000000000001),
7832 0,
7833 false,
7834 0x00, /* TSFlags */
7835 false, /* HasDisjunctSubRegs */
7836 false, /* CoveredBySubRegs */
7837 nullptr, 0,
7838 nullptr
7839 };
7840
7841 extern const TargetRegisterClass GR16RegClass = {
7842 &X86MCRegisterClasses[GR16RegClassID],
7843 GR16SubClassMask,
7844 SuperRegIdxSeqs + 5,
7845 LaneBitmask(0x0000000000000003),
7846 0,
7847 false,
7848 0x00, /* TSFlags */
7849 true, /* HasDisjunctSubRegs */
7850 true, /* CoveredBySubRegs */
7851 nullptr, 0,
7852 nullptr
7853 };
7854
7855 extern const TargetRegisterClass GR16_NOREX2RegClass = {
7856 &X86MCRegisterClasses[GR16_NOREX2RegClassID],
7857 GR16_NOREX2SubClassMask,
7858 SuperRegIdxSeqs + 5,
7859 LaneBitmask(0x0000000000000003),
7860 0,
7861 false,
7862 0x00, /* TSFlags */
7863 true, /* HasDisjunctSubRegs */
7864 true, /* CoveredBySubRegs */
7865 GR16_NOREX2Superclasses, 1,
7866 nullptr
7867 };
7868
7869 extern const TargetRegisterClass GR16_NOREXRegClass = {
7870 &X86MCRegisterClasses[GR16_NOREXRegClassID],
7871 GR16_NOREXSubClassMask,
7872 SuperRegIdxSeqs + 5,
7873 LaneBitmask(0x0000000000000003),
7874 0,
7875 false,
7876 0x00, /* TSFlags */
7877 true, /* HasDisjunctSubRegs */
7878 true, /* CoveredBySubRegs */
7879 GR16_NOREXSuperclasses, 2,
7880 nullptr
7881 };
7882
7883 extern const TargetRegisterClass VK1RegClass = {
7884 &X86MCRegisterClasses[VK1RegClassID],
7885 VK1SubClassMask,
7886 SuperRegIdxSeqs + 9,
7887 LaneBitmask(0x0000000000000001),
7888 0,
7889 false,
7890 0x00, /* TSFlags */
7891 false, /* HasDisjunctSubRegs */
7892 false, /* CoveredBySubRegs */
7893 VK1Superclasses, 4,
7894 nullptr
7895 };
7896
7897 extern const TargetRegisterClass VK16RegClass = {
7898 &X86MCRegisterClasses[VK16RegClassID],
7899 VK16SubClassMask,
7900 SuperRegIdxSeqs + 9,
7901 LaneBitmask(0x0000000000000001),
7902 0,
7903 false,
7904 0x00, /* TSFlags */
7905 false, /* HasDisjunctSubRegs */
7906 false, /* CoveredBySubRegs */
7907 VK16Superclasses, 4,
7908 nullptr
7909 };
7910
7911 extern const TargetRegisterClass VK2RegClass = {
7912 &X86MCRegisterClasses[VK2RegClassID],
7913 VK2SubClassMask,
7914 SuperRegIdxSeqs + 9,
7915 LaneBitmask(0x0000000000000001),
7916 0,
7917 false,
7918 0x00, /* TSFlags */
7919 false, /* HasDisjunctSubRegs */
7920 false, /* CoveredBySubRegs */
7921 VK2Superclasses, 4,
7922 nullptr
7923 };
7924
7925 extern const TargetRegisterClass VK4RegClass = {
7926 &X86MCRegisterClasses[VK4RegClassID],
7927 VK4SubClassMask,
7928 SuperRegIdxSeqs + 9,
7929 LaneBitmask(0x0000000000000001),
7930 0,
7931 false,
7932 0x00, /* TSFlags */
7933 false, /* HasDisjunctSubRegs */
7934 false, /* CoveredBySubRegs */
7935 VK4Superclasses, 4,
7936 nullptr
7937 };
7938
7939 extern const TargetRegisterClass VK8RegClass = {
7940 &X86MCRegisterClasses[VK8RegClassID],
7941 VK8SubClassMask,
7942 SuperRegIdxSeqs + 9,
7943 LaneBitmask(0x0000000000000001),
7944 0,
7945 false,
7946 0x00, /* TSFlags */
7947 false, /* HasDisjunctSubRegs */
7948 false, /* CoveredBySubRegs */
7949 VK8Superclasses, 4,
7950 nullptr
7951 };
7952
7953 extern const TargetRegisterClass VK16WMRegClass = {
7954 &X86MCRegisterClasses[VK16WMRegClassID],
7955 VK16WMSubClassMask,
7956 SuperRegIdxSeqs + 9,
7957 LaneBitmask(0x0000000000000001),
7958 0,
7959 false,
7960 0x00, /* TSFlags */
7961 false, /* HasDisjunctSubRegs */
7962 false, /* CoveredBySubRegs */
7963 VK16WMSuperclasses, 9,
7964 nullptr
7965 };
7966
7967 extern const TargetRegisterClass VK1WMRegClass = {
7968 &X86MCRegisterClasses[VK1WMRegClassID],
7969 VK1WMSubClassMask,
7970 SuperRegIdxSeqs + 9,
7971 LaneBitmask(0x0000000000000001),
7972 0,
7973 false,
7974 0x00, /* TSFlags */
7975 false, /* HasDisjunctSubRegs */
7976 false, /* CoveredBySubRegs */
7977 VK1WMSuperclasses, 9,
7978 nullptr
7979 };
7980
7981 extern const TargetRegisterClass VK2WMRegClass = {
7982 &X86MCRegisterClasses[VK2WMRegClassID],
7983 VK2WMSubClassMask,
7984 SuperRegIdxSeqs + 9,
7985 LaneBitmask(0x0000000000000001),
7986 0,
7987 false,
7988 0x00, /* TSFlags */
7989 false, /* HasDisjunctSubRegs */
7990 false, /* CoveredBySubRegs */
7991 VK2WMSuperclasses, 9,
7992 nullptr
7993 };
7994
7995 extern const TargetRegisterClass VK4WMRegClass = {
7996 &X86MCRegisterClasses[VK4WMRegClassID],
7997 VK4WMSubClassMask,
7998 SuperRegIdxSeqs + 9,
7999 LaneBitmask(0x0000000000000001),
8000 0,
8001 false,
8002 0x00, /* TSFlags */
8003 false, /* HasDisjunctSubRegs */
8004 false, /* CoveredBySubRegs */
8005 VK4WMSuperclasses, 9,
8006 nullptr
8007 };
8008
8009 extern const TargetRegisterClass VK8WMRegClass = {
8010 &X86MCRegisterClasses[VK8WMRegClassID],
8011 VK8WMSubClassMask,
8012 SuperRegIdxSeqs + 9,
8013 LaneBitmask(0x0000000000000001),
8014 0,
8015 false,
8016 0x00, /* TSFlags */
8017 false, /* HasDisjunctSubRegs */
8018 false, /* CoveredBySubRegs */
8019 VK8WMSuperclasses, 9,
8020 nullptr
8021 };
8022
8023 extern const TargetRegisterClass SEGMENT_REGRegClass = {
8024 &X86MCRegisterClasses[SEGMENT_REGRegClassID],
8025 SEGMENT_REGSubClassMask,
8026 SuperRegIdxSeqs + 1,
8027 LaneBitmask(0x0000000000000001),
8028 0,
8029 false,
8030 0x00, /* TSFlags */
8031 false, /* HasDisjunctSubRegs */
8032 false, /* CoveredBySubRegs */
8033 nullptr, 0,
8034 nullptr
8035 };
8036
8037 extern const TargetRegisterClass GR16_ABCDRegClass = {
8038 &X86MCRegisterClasses[GR16_ABCDRegClassID],
8039 GR16_ABCDSubClassMask,
8040 SuperRegIdxSeqs + 5,
8041 LaneBitmask(0x0000000000000003),
8042 0,
8043 false,
8044 0x00, /* TSFlags */
8045 true, /* HasDisjunctSubRegs */
8046 true, /* CoveredBySubRegs */
8047 GR16_ABCDSuperclasses, 3,
8048 nullptr
8049 };
8050
8051 extern const TargetRegisterClass FPCCRRegClass = {
8052 &X86MCRegisterClasses[FPCCRRegClassID],
8053 FPCCRSubClassMask,
8054 SuperRegIdxSeqs + 1,
8055 LaneBitmask(0x0000000000000001),
8056 0,
8057 false,
8058 0x00, /* TSFlags */
8059 false, /* HasDisjunctSubRegs */
8060 false, /* CoveredBySubRegs */
8061 nullptr, 0,
8062 nullptr
8063 };
8064
8065 extern const TargetRegisterClass FR16XRegClass = {
8066 &X86MCRegisterClasses[FR16XRegClassID],
8067 FR16XSubClassMask,
8068 SuperRegIdxSeqs + 15,
8069 LaneBitmask(0x0000000000000001),
8070 0,
8071 false,
8072 0x00, /* TSFlags */
8073 false, /* HasDisjunctSubRegs */
8074 false, /* CoveredBySubRegs */
8075 nullptr, 0,
8076 nullptr
8077 };
8078
8079 extern const TargetRegisterClass FR16RegClass = {
8080 &X86MCRegisterClasses[FR16RegClassID],
8081 FR16SubClassMask,
8082 SuperRegIdxSeqs + 15,
8083 LaneBitmask(0x0000000000000001),
8084 0,
8085 false,
8086 0x00, /* TSFlags */
8087 false, /* HasDisjunctSubRegs */
8088 false, /* CoveredBySubRegs */
8089 FR16Superclasses, 1,
8090 nullptr
8091 };
8092
8093 extern const TargetRegisterClass VK16PAIRRegClass = {
8094 &X86MCRegisterClasses[VK16PAIRRegClassID],
8095 VK16PAIRSubClassMask,
8096 SuperRegIdxSeqs + 1,
8097 LaneBitmask(0x0000000000000030),
8098 0,
8099 false,
8100 0x00, /* TSFlags */
8101 true, /* HasDisjunctSubRegs */
8102 true, /* CoveredBySubRegs */
8103 VK16PAIRSuperclasses, 4,
8104 nullptr
8105 };
8106
8107 extern const TargetRegisterClass VK1PAIRRegClass = {
8108 &X86MCRegisterClasses[VK1PAIRRegClassID],
8109 VK1PAIRSubClassMask,
8110 SuperRegIdxSeqs + 1,
8111 LaneBitmask(0x0000000000000030),
8112 0,
8113 false,
8114 0x00, /* TSFlags */
8115 true, /* HasDisjunctSubRegs */
8116 true, /* CoveredBySubRegs */
8117 VK1PAIRSuperclasses, 4,
8118 nullptr
8119 };
8120
8121 extern const TargetRegisterClass VK2PAIRRegClass = {
8122 &X86MCRegisterClasses[VK2PAIRRegClassID],
8123 VK2PAIRSubClassMask,
8124 SuperRegIdxSeqs + 1,
8125 LaneBitmask(0x0000000000000030),
8126 0,
8127 false,
8128 0x00, /* TSFlags */
8129 true, /* HasDisjunctSubRegs */
8130 true, /* CoveredBySubRegs */
8131 VK2PAIRSuperclasses, 4,
8132 nullptr
8133 };
8134
8135 extern const TargetRegisterClass VK4PAIRRegClass = {
8136 &X86MCRegisterClasses[VK4PAIRRegClassID],
8137 VK4PAIRSubClassMask,
8138 SuperRegIdxSeqs + 1,
8139 LaneBitmask(0x0000000000000030),
8140 0,
8141 false,
8142 0x00, /* TSFlags */
8143 true, /* HasDisjunctSubRegs */
8144 true, /* CoveredBySubRegs */
8145 VK4PAIRSuperclasses, 4,
8146 nullptr
8147 };
8148
8149 extern const TargetRegisterClass VK8PAIRRegClass = {
8150 &X86MCRegisterClasses[VK8PAIRRegClassID],
8151 VK8PAIRSubClassMask,
8152 SuperRegIdxSeqs + 1,
8153 LaneBitmask(0x0000000000000030),
8154 0,
8155 false,
8156 0x00, /* TSFlags */
8157 true, /* HasDisjunctSubRegs */
8158 true, /* CoveredBySubRegs */
8159 VK8PAIRSuperclasses, 4,
8160 nullptr
8161 };
8162
8163 extern const TargetRegisterClass VK1PAIR_with_sub_mask_0_in_VK1WMRegClass = {
8164 &X86MCRegisterClasses[VK1PAIR_with_sub_mask_0_in_VK1WMRegClassID],
8165 VK1PAIR_with_sub_mask_0_in_VK1WMSubClassMask,
8166 SuperRegIdxSeqs + 1,
8167 LaneBitmask(0x0000000000000030),
8168 0,
8169 false,
8170 0x00, /* TSFlags */
8171 true, /* HasDisjunctSubRegs */
8172 true, /* CoveredBySubRegs */
8173 VK1PAIR_with_sub_mask_0_in_VK1WMSuperclasses, 5,
8174 nullptr
8175 };
8176
8177 extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBPRegClass = {
8178 &X86MCRegisterClasses[LOW32_ADDR_ACCESS_RBPRegClassID],
8179 LOW32_ADDR_ACCESS_RBPSubClassMask,
8180 SuperRegIdxSeqs + 7,
8181 LaneBitmask(0x000000000000000F),
8182 0,
8183 false,
8184 0x00, /* TSFlags */
8185 true, /* HasDisjunctSubRegs */
8186 false, /* CoveredBySubRegs */
8187 nullptr, 0,
8188 nullptr
8189 };
8190
8191 extern const TargetRegisterClass LOW32_ADDR_ACCESSRegClass = {
8192 &X86MCRegisterClasses[LOW32_ADDR_ACCESSRegClassID],
8193 LOW32_ADDR_ACCESSSubClassMask,
8194 SuperRegIdxSeqs + 7,
8195 LaneBitmask(0x000000000000000F),
8196 0,
8197 false,
8198 0x00, /* TSFlags */
8199 true, /* HasDisjunctSubRegs */
8200 false, /* CoveredBySubRegs */
8201 LOW32_ADDR_ACCESSSuperclasses, 1,
8202 nullptr
8203 };
8204
8205 extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass = {
8206 &X86MCRegisterClasses[LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID],
8207 LOW32_ADDR_ACCESS_RBP_with_sub_8bitSubClassMask,
8208 SuperRegIdxSeqs + 7,
8209 LaneBitmask(0x000000000000000F),
8210 0,
8211 false,
8212 0x00, /* TSFlags */
8213 true, /* HasDisjunctSubRegs */
8214 false, /* CoveredBySubRegs */
8215 LOW32_ADDR_ACCESS_RBP_with_sub_8bitSuperclasses, 1,
8216 nullptr
8217 };
8218
8219 extern const TargetRegisterClass FR32XRegClass = {
8220 &X86MCRegisterClasses[FR32XRegClassID],
8221 FR32XSubClassMask,
8222 SuperRegIdxSeqs + 15,
8223 LaneBitmask(0x0000000000000001),
8224 0,
8225 false,
8226 0x00, /* TSFlags */
8227 false, /* HasDisjunctSubRegs */
8228 false, /* CoveredBySubRegs */
8229 FR32XSuperclasses, 1,
8230 FR32XGetRawAllocationOrder
8231 };
8232
8233 extern const TargetRegisterClass GR32RegClass = {
8234 &X86MCRegisterClasses[GR32RegClassID],
8235 GR32SubClassMask,
8236 SuperRegIdxSeqs + 7,
8237 LaneBitmask(0x000000000000000F),
8238 0,
8239 false,
8240 0x00, /* TSFlags */
8241 true, /* HasDisjunctSubRegs */
8242 true, /* CoveredBySubRegs */
8243 GR32Superclasses, 3,
8244 nullptr
8245 };
8246
8247 extern const TargetRegisterClass GR32_NOSPRegClass = {
8248 &X86MCRegisterClasses[GR32_NOSPRegClassID],
8249 GR32_NOSPSubClassMask,
8250 SuperRegIdxSeqs + 7,
8251 LaneBitmask(0x000000000000000F),
8252 0,
8253 false,
8254 0x00, /* TSFlags */
8255 true, /* HasDisjunctSubRegs */
8256 true, /* CoveredBySubRegs */
8257 GR32_NOSPSuperclasses, 4,
8258 nullptr
8259 };
8260
8261 extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClass = {
8262 &X86MCRegisterClasses[LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID],
8263 LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2SubClassMask,
8264 SuperRegIdxSeqs + 7,
8265 LaneBitmask(0x000000000000000F),
8266 0,
8267 false,
8268 0x00, /* TSFlags */
8269 true, /* HasDisjunctSubRegs */
8270 false, /* CoveredBySubRegs */
8271 LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2Superclasses, 2,
8272 nullptr
8273 };
8274
8275 extern const TargetRegisterClass DEBUG_REGRegClass = {
8276 &X86MCRegisterClasses[DEBUG_REGRegClassID],
8277 DEBUG_REGSubClassMask,
8278 SuperRegIdxSeqs + 1,
8279 LaneBitmask(0x0000000000000001),
8280 0,
8281 false,
8282 0x00, /* TSFlags */
8283 false, /* HasDisjunctSubRegs */
8284 false, /* CoveredBySubRegs */
8285 nullptr, 0,
8286 nullptr
8287 };
8288
8289 extern const TargetRegisterClass FR32RegClass = {
8290 &X86MCRegisterClasses[FR32RegClassID],
8291 FR32SubClassMask,
8292 SuperRegIdxSeqs + 15,
8293 LaneBitmask(0x0000000000000001),
8294 0,
8295 false,
8296 0x00, /* TSFlags */
8297 false, /* HasDisjunctSubRegs */
8298 false, /* CoveredBySubRegs */
8299 FR32Superclasses, 3,
8300 nullptr
8301 };
8302
8303 extern const TargetRegisterClass GR32_NOREX2RegClass = {
8304 &X86MCRegisterClasses[GR32_NOREX2RegClassID],
8305 GR32_NOREX2SubClassMask,
8306 SuperRegIdxSeqs + 7,
8307 LaneBitmask(0x000000000000000F),
8308 0,
8309 false,
8310 0x00, /* TSFlags */
8311 true, /* HasDisjunctSubRegs */
8312 true, /* CoveredBySubRegs */
8313 GR32_NOREX2Superclasses, 5,
8314 nullptr
8315 };
8316
8317 extern const TargetRegisterClass GR32_NOREX2_NOSPRegClass = {
8318 &X86MCRegisterClasses[GR32_NOREX2_NOSPRegClassID],
8319 GR32_NOREX2_NOSPSubClassMask,
8320 SuperRegIdxSeqs + 7,
8321 LaneBitmask(0x000000000000000F),
8322 0,
8323 false,
8324 0x00, /* TSFlags */
8325 true, /* HasDisjunctSubRegs */
8326 true, /* CoveredBySubRegs */
8327 GR32_NOREX2_NOSPSuperclasses, 7,
8328 nullptr
8329 };
8330
8331 extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass = {
8332 &X86MCRegisterClasses[LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID],
8333 LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXSubClassMask,
8334 SuperRegIdxSeqs + 7,
8335 LaneBitmask(0x000000000000000F),
8336 0,
8337 false,
8338 0x00, /* TSFlags */
8339 true, /* HasDisjunctSubRegs */
8340 false, /* CoveredBySubRegs */
8341 LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXSuperclasses, 3,
8342 nullptr
8343 };
8344
8345 extern const TargetRegisterClass GR32_NOREXRegClass = {
8346 &X86MCRegisterClasses[GR32_NOREXRegClassID],
8347 GR32_NOREXSubClassMask,
8348 SuperRegIdxSeqs + 7,
8349 LaneBitmask(0x000000000000000F),
8350 0,
8351 false,
8352 0x00, /* TSFlags */
8353 true, /* HasDisjunctSubRegs */
8354 true, /* CoveredBySubRegs */
8355 GR32_NOREXSuperclasses, 7,
8356 nullptr
8357 };
8358
8359 extern const TargetRegisterClass VK32RegClass = {
8360 &X86MCRegisterClasses[VK32RegClassID],
8361 VK32SubClassMask,
8362 SuperRegIdxSeqs + 9,
8363 LaneBitmask(0x0000000000000001),
8364 0,
8365 false,
8366 0x00, /* TSFlags */
8367 false, /* HasDisjunctSubRegs */
8368 false, /* CoveredBySubRegs */
8369 VK32Superclasses, 5,
8370 nullptr
8371 };
8372
8373 extern const TargetRegisterClass GR32_NOREX_NOSPRegClass = {
8374 &X86MCRegisterClasses[GR32_NOREX_NOSPRegClassID],
8375 GR32_NOREX_NOSPSubClassMask,
8376 SuperRegIdxSeqs + 7,
8377 LaneBitmask(0x000000000000000F),
8378 0,
8379 false,
8380 0x00, /* TSFlags */
8381 true, /* HasDisjunctSubRegs */
8382 true, /* CoveredBySubRegs */
8383 GR32_NOREX_NOSPSuperclasses, 10,
8384 nullptr
8385 };
8386
8387 extern const TargetRegisterClass RFP32RegClass = {
8388 &X86MCRegisterClasses[RFP32RegClassID],
8389 RFP32SubClassMask,
8390 SuperRegIdxSeqs + 1,
8391 LaneBitmask(0x0000000000000001),
8392 0,
8393 false,
8394 0x00, /* TSFlags */
8395 false, /* HasDisjunctSubRegs */
8396 false, /* CoveredBySubRegs */
8397 nullptr, 0,
8398 nullptr
8399 };
8400
8401 extern const TargetRegisterClass VK32WMRegClass = {
8402 &X86MCRegisterClasses[VK32WMRegClassID],
8403 VK32WMSubClassMask,
8404 SuperRegIdxSeqs + 9,
8405 LaneBitmask(0x0000000000000001),
8406 0,
8407 false,
8408 0x00, /* TSFlags */
8409 false, /* HasDisjunctSubRegs */
8410 false, /* CoveredBySubRegs */
8411 VK32WMSuperclasses, 11,
8412 nullptr
8413 };
8414
8415 extern const TargetRegisterClass GR32_ABCDRegClass = {
8416 &X86MCRegisterClasses[GR32_ABCDRegClassID],
8417 GR32_ABCDSubClassMask,
8418 SuperRegIdxSeqs + 7,
8419 LaneBitmask(0x000000000000000F),
8420 0,
8421 false,
8422 0x00, /* TSFlags */
8423 true, /* HasDisjunctSubRegs */
8424 true, /* CoveredBySubRegs */
8425 GR32_ABCDSuperclasses, 11,
8426 nullptr
8427 };
8428
8429 extern const TargetRegisterClass GR32_TCRegClass = {
8430 &X86MCRegisterClasses[GR32_TCRegClassID],
8431 GR32_TCSubClassMask,
8432 SuperRegIdxSeqs + 7,
8433 LaneBitmask(0x000000000000000F),
8434 0,
8435 false,
8436 0x00, /* TSFlags */
8437 true, /* HasDisjunctSubRegs */
8438 true, /* CoveredBySubRegs */
8439 GR32_TCSuperclasses, 8,
8440 nullptr
8441 };
8442
8443 extern const TargetRegisterClass GR32_ABCD_and_GR32_TCRegClass = {
8444 &X86MCRegisterClasses[GR32_ABCD_and_GR32_TCRegClassID],
8445 GR32_ABCD_and_GR32_TCSubClassMask,
8446 SuperRegIdxSeqs + 7,
8447 LaneBitmask(0x000000000000000F),
8448 0,
8449 false,
8450 0x00, /* TSFlags */
8451 true, /* HasDisjunctSubRegs */
8452 true, /* CoveredBySubRegs */
8453 GR32_ABCD_and_GR32_TCSuperclasses, 13,
8454 nullptr
8455 };
8456
8457 extern const TargetRegisterClass GR32_ADRegClass = {
8458 &X86MCRegisterClasses[GR32_ADRegClassID],
8459 GR32_ADSubClassMask,
8460 SuperRegIdxSeqs + 7,
8461 LaneBitmask(0x000000000000000F),
8462 0,
8463 false,
8464 0x00, /* TSFlags */
8465 true, /* HasDisjunctSubRegs */
8466 true, /* CoveredBySubRegs */
8467 GR32_ADSuperclasses, 14,
8468 nullptr
8469 };
8470
8471 extern const TargetRegisterClass GR32_ArgRefRegClass = {
8472 &X86MCRegisterClasses[GR32_ArgRefRegClassID],
8473 GR32_ArgRefSubClassMask,
8474 SuperRegIdxSeqs + 7,
8475 LaneBitmask(0x000000000000000F),
8476 0,
8477 false,
8478 0x00, /* TSFlags */
8479 true, /* HasDisjunctSubRegs */
8480 true, /* CoveredBySubRegs */
8481 GR32_ArgRefSuperclasses, 14,
8482 nullptr
8483 };
8484
8485 extern const TargetRegisterClass GR32_BPSPRegClass = {
8486 &X86MCRegisterClasses[GR32_BPSPRegClassID],
8487 GR32_BPSPSubClassMask,
8488 SuperRegIdxSeqs + 7,
8489 LaneBitmask(0x000000000000000F),
8490 0,
8491 false,
8492 0x00, /* TSFlags */
8493 true, /* HasDisjunctSubRegs */
8494 true, /* CoveredBySubRegs */
8495 GR32_BPSPSuperclasses, 8,
8496 nullptr
8497 };
8498
8499 extern const TargetRegisterClass GR32_BSIRegClass = {
8500 &X86MCRegisterClasses[GR32_BSIRegClassID],
8501 GR32_BSISubClassMask,
8502 SuperRegIdxSeqs + 7,
8503 LaneBitmask(0x000000000000000F),
8504 0,
8505 false,
8506 0x00, /* TSFlags */
8507 true, /* HasDisjunctSubRegs */
8508 true, /* CoveredBySubRegs */
8509 GR32_BSISuperclasses, 11,
8510 nullptr
8511 };
8512
8513 extern const TargetRegisterClass GR32_CBRegClass = {
8514 &X86MCRegisterClasses[GR32_CBRegClassID],
8515 GR32_CBSubClassMask,
8516 SuperRegIdxSeqs + 7,
8517 LaneBitmask(0x000000000000000F),
8518 0,
8519 false,
8520 0x00, /* TSFlags */
8521 true, /* HasDisjunctSubRegs */
8522 true, /* CoveredBySubRegs */
8523 GR32_CBSuperclasses, 12,
8524 nullptr
8525 };
8526
8527 extern const TargetRegisterClass GR32_DCRegClass = {
8528 &X86MCRegisterClasses[GR32_DCRegClassID],
8529 GR32_DCSubClassMask,
8530 SuperRegIdxSeqs + 7,
8531 LaneBitmask(0x000000000000000F),
8532 0,
8533 false,
8534 0x00, /* TSFlags */
8535 true, /* HasDisjunctSubRegs */
8536 true, /* CoveredBySubRegs */
8537 GR32_DCSuperclasses, 15,
8538 nullptr
8539 };
8540
8541 extern const TargetRegisterClass GR32_DIBPRegClass = {
8542 &X86MCRegisterClasses[GR32_DIBPRegClassID],
8543 GR32_DIBPSubClassMask,
8544 SuperRegIdxSeqs + 7,
8545 LaneBitmask(0x000000000000000F),
8546 0,
8547 false,
8548 0x00, /* TSFlags */
8549 true, /* HasDisjunctSubRegs */
8550 true, /* CoveredBySubRegs */
8551 GR32_DIBPSuperclasses, 11,
8552 nullptr
8553 };
8554
8555 extern const TargetRegisterClass GR32_SIDIRegClass = {
8556 &X86MCRegisterClasses[GR32_SIDIRegClassID],
8557 GR32_SIDISubClassMask,
8558 SuperRegIdxSeqs + 7,
8559 LaneBitmask(0x000000000000000F),
8560 0,
8561 false,
8562 0x00, /* TSFlags */
8563 true, /* HasDisjunctSubRegs */
8564 true, /* CoveredBySubRegs */
8565 GR32_SIDISuperclasses, 11,
8566 nullptr
8567 };
8568
8569 extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass = {
8570 &X86MCRegisterClasses[LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID],
8571 LOW32_ADDR_ACCESS_RBP_with_sub_32bitSubClassMask,
8572 SuperRegIdxSeqs + 1,
8573 LaneBitmask(0x000000000000000F),
8574 0,
8575 false,
8576 0x00, /* TSFlags */
8577 true, /* HasDisjunctSubRegs */
8578 false, /* CoveredBySubRegs */
8579 LOW32_ADDR_ACCESS_RBP_with_sub_32bitSuperclasses, 1,
8580 nullptr
8581 };
8582
8583 extern const TargetRegisterClass CCRRegClass = {
8584 &X86MCRegisterClasses[CCRRegClassID],
8585 CCRSubClassMask,
8586 SuperRegIdxSeqs + 1,
8587 LaneBitmask(0x0000000000000001),
8588 0,
8589 false,
8590 0x00, /* TSFlags */
8591 false, /* HasDisjunctSubRegs */
8592 false, /* CoveredBySubRegs */
8593 nullptr, 0,
8594 nullptr
8595 };
8596
8597 extern const TargetRegisterClass DFCCRRegClass = {
8598 &X86MCRegisterClasses[DFCCRRegClassID],
8599 DFCCRSubClassMask,
8600 SuperRegIdxSeqs + 1,
8601 LaneBitmask(0x0000000000000001),
8602 0,
8603 false,
8604 0x00, /* TSFlags */
8605 false, /* HasDisjunctSubRegs */
8606 false, /* CoveredBySubRegs */
8607 nullptr, 0,
8608 nullptr
8609 };
8610
8611 extern const TargetRegisterClass GR32_ABCD_and_GR32_BSIRegClass = {
8612 &X86MCRegisterClasses[GR32_ABCD_and_GR32_BSIRegClassID],
8613 GR32_ABCD_and_GR32_BSISubClassMask,
8614 SuperRegIdxSeqs + 7,
8615 LaneBitmask(0x000000000000000F),
8616 0,
8617 false,
8618 0x00, /* TSFlags */
8619 true, /* HasDisjunctSubRegs */
8620 true, /* CoveredBySubRegs */
8621 GR32_ABCD_and_GR32_BSISuperclasses, 14,
8622 nullptr
8623 };
8624
8625 extern const TargetRegisterClass GR32_AD_and_GR32_ArgRefRegClass = {
8626 &X86MCRegisterClasses[GR32_AD_and_GR32_ArgRefRegClassID],
8627 GR32_AD_and_GR32_ArgRefSubClassMask,
8628 SuperRegIdxSeqs + 7,
8629 LaneBitmask(0x000000000000000F),
8630 0,
8631 false,
8632 0x00, /* TSFlags */
8633 true, /* HasDisjunctSubRegs */
8634 true, /* CoveredBySubRegs */
8635 GR32_AD_and_GR32_ArgRefSuperclasses, 17,
8636 nullptr
8637 };
8638
8639 extern const TargetRegisterClass GR32_ArgRef_and_GR32_CBRegClass = {
8640 &X86MCRegisterClasses[GR32_ArgRef_and_GR32_CBRegClassID],
8641 GR32_ArgRef_and_GR32_CBSubClassMask,
8642 SuperRegIdxSeqs + 7,
8643 LaneBitmask(0x000000000000000F),
8644 0,
8645 false,
8646 0x00, /* TSFlags */
8647 true, /* HasDisjunctSubRegs */
8648 true, /* CoveredBySubRegs */
8649 GR32_ArgRef_and_GR32_CBSuperclasses, 17,
8650 nullptr
8651 };
8652
8653 extern const TargetRegisterClass GR32_BPSP_and_GR32_DIBPRegClass = {
8654 &X86MCRegisterClasses[GR32_BPSP_and_GR32_DIBPRegClassID],
8655 GR32_BPSP_and_GR32_DIBPSubClassMask,
8656 SuperRegIdxSeqs + 7,
8657 LaneBitmask(0x000000000000000F),
8658 0,
8659 false,
8660 0x00, /* TSFlags */
8661 true, /* HasDisjunctSubRegs */
8662 true, /* CoveredBySubRegs */
8663 GR32_BPSP_and_GR32_DIBPSuperclasses, 13,
8664 nullptr
8665 };
8666
8667 extern const TargetRegisterClass GR32_BPSP_and_GR32_TCRegClass = {
8668 &X86MCRegisterClasses[GR32_BPSP_and_GR32_TCRegClassID],
8669 GR32_BPSP_and_GR32_TCSubClassMask,
8670 SuperRegIdxSeqs + 7,
8671 LaneBitmask(0x000000000000000F),
8672 0,
8673 false,
8674 0x00, /* TSFlags */
8675 true, /* HasDisjunctSubRegs */
8676 true, /* CoveredBySubRegs */
8677 GR32_BPSP_and_GR32_TCSuperclasses, 10,
8678 nullptr
8679 };
8680
8681 extern const TargetRegisterClass GR32_BSI_and_GR32_SIDIRegClass = {
8682 &X86MCRegisterClasses[GR32_BSI_and_GR32_SIDIRegClassID],
8683 GR32_BSI_and_GR32_SIDISubClassMask,
8684 SuperRegIdxSeqs + 7,
8685 LaneBitmask(0x000000000000000F),
8686 0,
8687 false,
8688 0x00, /* TSFlags */
8689 true, /* HasDisjunctSubRegs */
8690 true, /* CoveredBySubRegs */
8691 GR32_BSI_and_GR32_SIDISuperclasses, 13,
8692 nullptr
8693 };
8694
8695 extern const TargetRegisterClass GR32_DIBP_and_GR32_SIDIRegClass = {
8696 &X86MCRegisterClasses[GR32_DIBP_and_GR32_SIDIRegClassID],
8697 GR32_DIBP_and_GR32_SIDISubClassMask,
8698 SuperRegIdxSeqs + 7,
8699 LaneBitmask(0x000000000000000F),
8700 0,
8701 false,
8702 0x00, /* TSFlags */
8703 true, /* HasDisjunctSubRegs */
8704 true, /* CoveredBySubRegs */
8705 GR32_DIBP_and_GR32_SIDISuperclasses, 13,
8706 nullptr
8707 };
8708
8709 extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClass = {
8710 &X86MCRegisterClasses[LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClassID],
8711 LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitSubClassMask,
8712 SuperRegIdxSeqs + 1,
8713 LaneBitmask(0x000000000000000F),
8714 0,
8715 false,
8716 0x00, /* TSFlags */
8717 true, /* HasDisjunctSubRegs */
8718 false, /* CoveredBySubRegs */
8719 LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitSuperclasses, 5,
8720 nullptr
8721 };
8722
8723 extern const TargetRegisterClass LOW32_ADDR_ACCESS_with_sub_32bitRegClass = {
8724 &X86MCRegisterClasses[LOW32_ADDR_ACCESS_with_sub_32bitRegClassID],
8725 LOW32_ADDR_ACCESS_with_sub_32bitSubClassMask,
8726 SuperRegIdxSeqs + 1,
8727 LaneBitmask(0x000000000000000F),
8728 0,
8729 false,
8730 0x00, /* TSFlags */
8731 true, /* HasDisjunctSubRegs */
8732 false, /* CoveredBySubRegs */
8733 LOW32_ADDR_ACCESS_with_sub_32bitSuperclasses, 3,
8734 nullptr
8735 };
8736
8737 extern const TargetRegisterClass RFP64RegClass = {
8738 &X86MCRegisterClasses[RFP64RegClassID],
8739 RFP64SubClassMask,
8740 SuperRegIdxSeqs + 1,
8741 LaneBitmask(0x0000000000000001),
8742 0,
8743 false,
8744 0x00, /* TSFlags */
8745 false, /* HasDisjunctSubRegs */
8746 false, /* CoveredBySubRegs */
8747 RFP64Superclasses, 1,
8748 nullptr
8749 };
8750
8751 extern const TargetRegisterClass GR64RegClass = {
8752 &X86MCRegisterClasses[GR64RegClassID],
8753 GR64SubClassMask,
8754 SuperRegIdxSeqs + 1,
8755 LaneBitmask(0x000000000000000F),
8756 0,
8757 false,
8758 0x00, /* TSFlags */
8759 true, /* HasDisjunctSubRegs */
8760 false, /* CoveredBySubRegs */
8761 nullptr, 0,
8762 nullptr
8763 };
8764
8765 extern const TargetRegisterClass FR64XRegClass = {
8766 &X86MCRegisterClasses[FR64XRegClassID],
8767 FR64XSubClassMask,
8768 SuperRegIdxSeqs + 15,
8769 LaneBitmask(0x0000000000000001),
8770 0,
8771 false,
8772 0x00, /* TSFlags */
8773 false, /* HasDisjunctSubRegs */
8774 false, /* CoveredBySubRegs */
8775 FR64XSuperclasses, 2,
8776 FR64XGetRawAllocationOrder
8777 };
8778
8779 extern const TargetRegisterClass GR64_with_sub_8bitRegClass = {
8780 &X86MCRegisterClasses[GR64_with_sub_8bitRegClassID],
8781 GR64_with_sub_8bitSubClassMask,
8782 SuperRegIdxSeqs + 1,
8783 LaneBitmask(0x000000000000000F),
8784 0,
8785 false,
8786 0x00, /* TSFlags */
8787 true, /* HasDisjunctSubRegs */
8788 false, /* CoveredBySubRegs */
8789 GR64_with_sub_8bitSuperclasses, 1,
8790 nullptr
8791 };
8792
8793 extern const TargetRegisterClass GR64_NOSPRegClass = {
8794 &X86MCRegisterClasses[GR64_NOSPRegClassID],
8795 GR64_NOSPSubClassMask,
8796 SuperRegIdxSeqs + 1,
8797 LaneBitmask(0x000000000000000F),
8798 0,
8799 false,
8800 0x00, /* TSFlags */
8801 true, /* HasDisjunctSubRegs */
8802 false, /* CoveredBySubRegs */
8803 GR64_NOSPSuperclasses, 2,
8804 nullptr
8805 };
8806
8807 extern const TargetRegisterClass GR64_NOREX2RegClass = {
8808 &X86MCRegisterClasses[GR64_NOREX2RegClassID],
8809 GR64_NOREX2SubClassMask,
8810 SuperRegIdxSeqs + 1,
8811 LaneBitmask(0x000000000000000F),
8812 0,
8813 false,
8814 0x00, /* TSFlags */
8815 true, /* HasDisjunctSubRegs */
8816 false, /* CoveredBySubRegs */
8817 GR64_NOREX2Superclasses, 1,
8818 nullptr
8819 };
8820
8821 extern const TargetRegisterClass CONTROL_REGRegClass = {
8822 &X86MCRegisterClasses[CONTROL_REGRegClassID],
8823 CONTROL_REGSubClassMask,
8824 SuperRegIdxSeqs + 1,
8825 LaneBitmask(0x0000000000000001),
8826 0,
8827 false,
8828 0x00, /* TSFlags */
8829 false, /* HasDisjunctSubRegs */
8830 false, /* CoveredBySubRegs */
8831 nullptr, 0,
8832 nullptr
8833 };
8834
8835 extern const TargetRegisterClass FR64RegClass = {
8836 &X86MCRegisterClasses[FR64RegClassID],
8837 FR64SubClassMask,
8838 SuperRegIdxSeqs + 15,
8839 LaneBitmask(0x0000000000000001),
8840 0,
8841 false,
8842 0x00, /* TSFlags */
8843 false, /* HasDisjunctSubRegs */
8844 false, /* CoveredBySubRegs */
8845 FR64Superclasses, 5,
8846 nullptr
8847 };
8848
8849 extern const TargetRegisterClass GR64_with_sub_16bit_in_GR16_NOREX2RegClass = {
8850 &X86MCRegisterClasses[GR64_with_sub_16bit_in_GR16_NOREX2RegClassID],
8851 GR64_with_sub_16bit_in_GR16_NOREX2SubClassMask,
8852 SuperRegIdxSeqs + 1,
8853 LaneBitmask(0x000000000000000F),
8854 0,
8855 false,
8856 0x00, /* TSFlags */
8857 true, /* HasDisjunctSubRegs */
8858 false, /* CoveredBySubRegs */
8859 GR64_with_sub_16bit_in_GR16_NOREX2Superclasses, 3,
8860 nullptr
8861 };
8862
8863 extern const TargetRegisterClass GR64_NOREX2_NOSPRegClass = {
8864 &X86MCRegisterClasses[GR64_NOREX2_NOSPRegClassID],
8865 GR64_NOREX2_NOSPSubClassMask,
8866 SuperRegIdxSeqs + 1,
8867 LaneBitmask(0x000000000000000F),
8868 0,
8869 false,
8870 0x00, /* TSFlags */
8871 true, /* HasDisjunctSubRegs */
8872 false, /* CoveredBySubRegs */
8873 GR64_NOREX2_NOSPSuperclasses, 5,
8874 nullptr
8875 };
8876
8877 extern const TargetRegisterClass GR64PLTSafeRegClass = {
8878 &X86MCRegisterClasses[GR64PLTSafeRegClassID],
8879 GR64PLTSafeSubClassMask,
8880 SuperRegIdxSeqs + 1,
8881 LaneBitmask(0x000000000000000F),
8882 0,
8883 false,
8884 0x00, /* TSFlags */
8885 true, /* HasDisjunctSubRegs */
8886 false, /* CoveredBySubRegs */
8887 GR64PLTSafeSuperclasses, 6,
8888 nullptr
8889 };
8890
8891 extern const TargetRegisterClass GR64_TCRegClass = {
8892 &X86MCRegisterClasses[GR64_TCRegClassID],
8893 GR64_TCSubClassMask,
8894 SuperRegIdxSeqs + 1,
8895 LaneBitmask(0x000000000000000F),
8896 0,
8897 false,
8898 0x00, /* TSFlags */
8899 true, /* HasDisjunctSubRegs */
8900 false, /* CoveredBySubRegs */
8901 GR64_TCSuperclasses, 2,
8902 nullptr
8903 };
8904
8905 extern const TargetRegisterClass GR64_NOREXRegClass = {
8906 &X86MCRegisterClasses[GR64_NOREXRegClassID],
8907 GR64_NOREXSubClassMask,
8908 SuperRegIdxSeqs + 1,
8909 LaneBitmask(0x000000000000000F),
8910 0,
8911 false,
8912 0x00, /* TSFlags */
8913 true, /* HasDisjunctSubRegs */
8914 false, /* CoveredBySubRegs */
8915 GR64_NOREXSuperclasses, 2,
8916 nullptr
8917 };
8918
8919 extern const TargetRegisterClass GR64_TCW64RegClass = {
8920 &X86MCRegisterClasses[GR64_TCW64RegClassID],
8921 GR64_TCW64SubClassMask,
8922 SuperRegIdxSeqs + 1,
8923 LaneBitmask(0x000000000000000F),
8924 0,
8925 false,
8926 0x00, /* TSFlags */
8927 true, /* HasDisjunctSubRegs */
8928 false, /* CoveredBySubRegs */
8929 GR64_TCW64Superclasses, 2,
8930 nullptr
8931 };
8932
8933 extern const TargetRegisterClass GR64_TC_with_sub_8bitRegClass = {
8934 &X86MCRegisterClasses[GR64_TC_with_sub_8bitRegClassID],
8935 GR64_TC_with_sub_8bitSubClassMask,
8936 SuperRegIdxSeqs + 1,
8937 LaneBitmask(0x000000000000000F),
8938 0,
8939 false,
8940 0x00, /* TSFlags */
8941 true, /* HasDisjunctSubRegs */
8942 false, /* CoveredBySubRegs */
8943 GR64_TC_with_sub_8bitSuperclasses, 5,
8944 nullptr
8945 };
8946
8947 extern const TargetRegisterClass GR64_NOREX2_NOSP_and_GR64_TCRegClass = {
8948 &X86MCRegisterClasses[GR64_NOREX2_NOSP_and_GR64_TCRegClassID],
8949 GR64_NOREX2_NOSP_and_GR64_TCSubClassMask,
8950 SuperRegIdxSeqs + 1,
8951 LaneBitmask(0x000000000000000F),
8952 0,
8953 false,
8954 0x00, /* TSFlags */
8955 true, /* HasDisjunctSubRegs */
8956 false, /* CoveredBySubRegs */
8957 GR64_NOREX2_NOSP_and_GR64_TCSuperclasses, 8,
8958 nullptr
8959 };
8960
8961 extern const TargetRegisterClass GR64_TCW64_with_sub_8bitRegClass = {
8962 &X86MCRegisterClasses[GR64_TCW64_with_sub_8bitRegClassID],
8963 GR64_TCW64_with_sub_8bitSubClassMask,
8964 SuperRegIdxSeqs + 1,
8965 LaneBitmask(0x000000000000000F),
8966 0,
8967 false,
8968 0x00, /* TSFlags */
8969 true, /* HasDisjunctSubRegs */
8970 false, /* CoveredBySubRegs */
8971 GR64_TCW64_with_sub_8bitSuperclasses, 5,
8972 nullptr
8973 };
8974
8975 extern const TargetRegisterClass GR64_TC_and_GR64_TCW64RegClass = {
8976 &X86MCRegisterClasses[GR64_TC_and_GR64_TCW64RegClassID],
8977 GR64_TC_and_GR64_TCW64SubClassMask,
8978 SuperRegIdxSeqs + 1,
8979 LaneBitmask(0x000000000000000F),
8980 0,
8981 false,
8982 0x00, /* TSFlags */
8983 true, /* HasDisjunctSubRegs */
8984 false, /* CoveredBySubRegs */
8985 GR64_TC_and_GR64_TCW64Superclasses, 4,
8986 nullptr
8987 };
8988
8989 extern const TargetRegisterClass GR64_with_sub_16bit_in_GR16_NOREXRegClass = {
8990 &X86MCRegisterClasses[GR64_with_sub_16bit_in_GR16_NOREXRegClassID],
8991 GR64_with_sub_16bit_in_GR16_NOREXSubClassMask,
8992 SuperRegIdxSeqs + 1,
8993 LaneBitmask(0x000000000000000F),
8994 0,
8995 false,
8996 0x00, /* TSFlags */
8997 true, /* HasDisjunctSubRegs */
8998 false, /* CoveredBySubRegs */
8999 GR64_with_sub_16bit_in_GR16_NOREXSuperclasses, 5,
9000 nullptr
9001 };
9002
9003 extern const TargetRegisterClass VK64RegClass = {
9004 &X86MCRegisterClasses[VK64RegClassID],
9005 VK64SubClassMask,
9006 SuperRegIdxSeqs + 9,
9007 LaneBitmask(0x0000000000000001),
9008 0,
9009 false,
9010 0x00, /* TSFlags */
9011 false, /* HasDisjunctSubRegs */
9012 false, /* CoveredBySubRegs */
9013 VK64Superclasses, 6,
9014 nullptr
9015 };
9016
9017 extern const TargetRegisterClass VR64RegClass = {
9018 &X86MCRegisterClasses[VR64RegClassID],
9019 VR64SubClassMask,
9020 SuperRegIdxSeqs + 1,
9021 LaneBitmask(0x0000000000000001),
9022 0,
9023 false,
9024 0x00, /* TSFlags */
9025 false, /* HasDisjunctSubRegs */
9026 false, /* CoveredBySubRegs */
9027 nullptr, 0,
9028 nullptr
9029 };
9030
9031 extern const TargetRegisterClass GR64PLTSafe_and_GR64_TCRegClass = {
9032 &X86MCRegisterClasses[GR64PLTSafe_and_GR64_TCRegClassID],
9033 GR64PLTSafe_and_GR64_TCSubClassMask,
9034 SuperRegIdxSeqs + 1,
9035 LaneBitmask(0x000000000000000F),
9036 0,
9037 false,
9038 0x00, /* TSFlags */
9039 true, /* HasDisjunctSubRegs */
9040 false, /* CoveredBySubRegs */
9041 GR64PLTSafe_and_GR64_TCSuperclasses, 10,
9042 nullptr
9043 };
9044
9045 extern const TargetRegisterClass GR64_NOREX2_NOSP_and_GR64_TCW64RegClass = {
9046 &X86MCRegisterClasses[GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID],
9047 GR64_NOREX2_NOSP_and_GR64_TCW64SubClassMask,
9048 SuperRegIdxSeqs + 1,
9049 LaneBitmask(0x000000000000000F),
9050 0,
9051 false,
9052 0x00, /* TSFlags */
9053 true, /* HasDisjunctSubRegs */
9054 false, /* CoveredBySubRegs */
9055 GR64_NOREX2_NOSP_and_GR64_TCW64Superclasses, 8,
9056 nullptr
9057 };
9058
9059 extern const TargetRegisterClass GR64_NOREX_NOSPRegClass = {
9060 &X86MCRegisterClasses[GR64_NOREX_NOSPRegClassID],
9061 GR64_NOREX_NOSPSubClassMask,
9062 SuperRegIdxSeqs + 1,
9063 LaneBitmask(0x000000000000000F),
9064 0,
9065 false,
9066 0x00, /* TSFlags */
9067 true, /* HasDisjunctSubRegs */
9068 false, /* CoveredBySubRegs */
9069 GR64_NOREX_NOSPSuperclasses, 9,
9070 nullptr
9071 };
9072
9073 extern const TargetRegisterClass GR64_NOREX_and_GR64_TCRegClass = {
9074 &X86MCRegisterClasses[GR64_NOREX_and_GR64_TCRegClassID],
9075 GR64_NOREX_and_GR64_TCSubClassMask,
9076 SuperRegIdxSeqs + 1,
9077 LaneBitmask(0x000000000000000F),
9078 0,
9079 false,
9080 0x00, /* TSFlags */
9081 true, /* HasDisjunctSubRegs */
9082 false, /* CoveredBySubRegs */
9083 GR64_NOREX_and_GR64_TCSuperclasses, 4,
9084 nullptr
9085 };
9086
9087 extern const TargetRegisterClass GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass = {
9088 &X86MCRegisterClasses[GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID],
9089 GR64_TCW64_and_GR64_TC_with_sub_8bitSubClassMask,
9090 SuperRegIdxSeqs + 1,
9091 LaneBitmask(0x000000000000000F),
9092 0,
9093 false,
9094 0x00, /* TSFlags */
9095 true, /* HasDisjunctSubRegs */
9096 false, /* CoveredBySubRegs */
9097 GR64_TCW64_and_GR64_TC_with_sub_8bitSuperclasses, 9,
9098 nullptr
9099 };
9100
9101 extern const TargetRegisterClass VK64WMRegClass = {
9102 &X86MCRegisterClasses[VK64WMRegClassID],
9103 VK64WMSubClassMask,
9104 SuperRegIdxSeqs + 9,
9105 LaneBitmask(0x0000000000000001),
9106 0,
9107 false,
9108 0x00, /* TSFlags */
9109 false, /* HasDisjunctSubRegs */
9110 false, /* CoveredBySubRegs */
9111 VK64WMSuperclasses, 13,
9112 nullptr
9113 };
9114
9115 extern const TargetRegisterClass GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClass = {
9116 &X86MCRegisterClasses[GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID],
9117 GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64SubClassMask,
9118 SuperRegIdxSeqs + 1,
9119 LaneBitmask(0x000000000000000F),
9120 0,
9121 false,
9122 0x00, /* TSFlags */
9123 true, /* HasDisjunctSubRegs */
9124 false, /* CoveredBySubRegs */
9125 GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64Superclasses, 14,
9126 nullptr
9127 };
9128
9129 extern const TargetRegisterClass GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass = {
9130 &X86MCRegisterClasses[GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID],
9131 GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXSubClassMask,
9132 SuperRegIdxSeqs + 1,
9133 LaneBitmask(0x000000000000000F),
9134 0,
9135 false,
9136 0x00, /* TSFlags */
9137 true, /* HasDisjunctSubRegs */
9138 false, /* CoveredBySubRegs */
9139 GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXSuperclasses, 9,
9140 nullptr
9141 };
9142
9143 extern const TargetRegisterClass GR64PLTSafe_and_GR64_TCW64RegClass = {
9144 &X86MCRegisterClasses[GR64PLTSafe_and_GR64_TCW64RegClassID],
9145 GR64PLTSafe_and_GR64_TCW64SubClassMask,
9146 SuperRegIdxSeqs + 1,
9147 LaneBitmask(0x000000000000000F),
9148 0,
9149 false,
9150 0x00, /* TSFlags */
9151 true, /* HasDisjunctSubRegs */
9152 false, /* CoveredBySubRegs */
9153 GR64PLTSafe_and_GR64_TCW64Superclasses, 17,
9154 nullptr
9155 };
9156
9157 extern const TargetRegisterClass GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClass = {
9158 &X86MCRegisterClasses[GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID],
9159 GR64_NOREX_and_GR64PLTSafe_and_GR64_TCSubClassMask,
9160 SuperRegIdxSeqs + 1,
9161 LaneBitmask(0x000000000000000F),
9162 0,
9163 false,
9164 0x00, /* TSFlags */
9165 true, /* HasDisjunctSubRegs */
9166 false, /* CoveredBySubRegs */
9167 GR64_NOREX_and_GR64PLTSafe_and_GR64_TCSuperclasses, 16,
9168 nullptr
9169 };
9170
9171 extern const TargetRegisterClass GR64_NOREX_and_GR64_TCW64RegClass = {
9172 &X86MCRegisterClasses[GR64_NOREX_and_GR64_TCW64RegClassID],
9173 GR64_NOREX_and_GR64_TCW64SubClassMask,
9174 SuperRegIdxSeqs + 1,
9175 LaneBitmask(0x000000000000000F),
9176 0,
9177 false,
9178 0x00, /* TSFlags */
9179 true, /* HasDisjunctSubRegs */
9180 false, /* CoveredBySubRegs */
9181 GR64_NOREX_and_GR64_TCW64Superclasses, 7,
9182 nullptr
9183 };
9184
9185 extern const TargetRegisterClass GR64_ABCDRegClass = {
9186 &X86MCRegisterClasses[GR64_ABCDRegClassID],
9187 GR64_ABCDSubClassMask,
9188 SuperRegIdxSeqs + 1,
9189 LaneBitmask(0x000000000000000F),
9190 0,
9191 false,
9192 0x00, /* TSFlags */
9193 true, /* HasDisjunctSubRegs */
9194 false, /* CoveredBySubRegs */
9195 GR64_ABCDSuperclasses, 10,
9196 nullptr
9197 };
9198
9199 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_TCRegClass = {
9200 &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_TCRegClassID],
9201 GR64_with_sub_32bit_in_GR32_TCSubClassMask,
9202 SuperRegIdxSeqs + 1,
9203 LaneBitmask(0x000000000000000F),
9204 0,
9205 false,
9206 0x00, /* TSFlags */
9207 true, /* HasDisjunctSubRegs */
9208 false, /* CoveredBySubRegs */
9209 GR64_with_sub_32bit_in_GR32_TCSuperclasses, 15,
9210 nullptr
9211 };
9212
9213 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClass = {
9214 &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID],
9215 GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCSubClassMask,
9216 SuperRegIdxSeqs + 1,
9217 LaneBitmask(0x000000000000000F),
9218 0,
9219 false,
9220 0x00, /* TSFlags */
9221 true, /* HasDisjunctSubRegs */
9222 false, /* CoveredBySubRegs */
9223 GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCSuperclasses, 27,
9224 nullptr
9225 };
9226
9227 extern const TargetRegisterClass GR64_ADRegClass = {
9228 &X86MCRegisterClasses[GR64_ADRegClassID],
9229 GR64_ADSubClassMask,
9230 SuperRegIdxSeqs + 1,
9231 LaneBitmask(0x000000000000000F),
9232 0,
9233 false,
9234 0x00, /* TSFlags */
9235 true, /* HasDisjunctSubRegs */
9236 false, /* CoveredBySubRegs */
9237 GR64_ADSuperclasses, 28,
9238 nullptr
9239 };
9240
9241 extern const TargetRegisterClass GR64_ArgRefRegClass = {
9242 &X86MCRegisterClasses[GR64_ArgRefRegClassID],
9243 GR64_ArgRefSubClassMask,
9244 SuperRegIdxSeqs + 1,
9245 LaneBitmask(0x000000000000000F),
9246 0,
9247 false,
9248 0x00, /* TSFlags */
9249 true, /* HasDisjunctSubRegs */
9250 false, /* CoveredBySubRegs */
9251 GR64_ArgRefSuperclasses, 9,
9252 nullptr
9253 };
9254
9255 extern const TargetRegisterClass GR64_and_LOW32_ADDR_ACCESS_RBPRegClass = {
9256 &X86MCRegisterClasses[GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID],
9257 GR64_and_LOW32_ADDR_ACCESS_RBPSubClassMask,
9258 SuperRegIdxSeqs + 1,
9259 LaneBitmask(0x000000000000000F),
9260 0,
9261 false,
9262 0x00, /* TSFlags */
9263 true, /* HasDisjunctSubRegs */
9264 false, /* CoveredBySubRegs */
9265 GR64_and_LOW32_ADDR_ACCESS_RBPSuperclasses, 5,
9266 nullptr
9267 };
9268
9269 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_ArgRefRegClass = {
9270 &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_ArgRefRegClassID],
9271 GR64_with_sub_32bit_in_GR32_ArgRefSubClassMask,
9272 SuperRegIdxSeqs + 1,
9273 LaneBitmask(0x000000000000000F),
9274 0,
9275 false,
9276 0x00, /* TSFlags */
9277 true, /* HasDisjunctSubRegs */
9278 false, /* CoveredBySubRegs */
9279 GR64_with_sub_32bit_in_GR32_ArgRefSuperclasses, 28,
9280 nullptr
9281 };
9282
9283 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSPRegClass = {
9284 &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_BPSPRegClassID],
9285 GR64_with_sub_32bit_in_GR32_BPSPSubClassMask,
9286 SuperRegIdxSeqs + 1,
9287 LaneBitmask(0x000000000000000F),
9288 0,
9289 false,
9290 0x00, /* TSFlags */
9291 true, /* HasDisjunctSubRegs */
9292 false, /* CoveredBySubRegs */
9293 GR64_with_sub_32bit_in_GR32_BPSPSuperclasses, 6,
9294 nullptr
9295 };
9296
9297 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BSIRegClass = {
9298 &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_BSIRegClassID],
9299 GR64_with_sub_32bit_in_GR32_BSISubClassMask,
9300 SuperRegIdxSeqs + 1,
9301 LaneBitmask(0x000000000000000F),
9302 0,
9303 false,
9304 0x00, /* TSFlags */
9305 true, /* HasDisjunctSubRegs */
9306 false, /* CoveredBySubRegs */
9307 GR64_with_sub_32bit_in_GR32_BSISuperclasses, 10,
9308 nullptr
9309 };
9310
9311 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_CBRegClass = {
9312 &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_CBRegClassID],
9313 GR64_with_sub_32bit_in_GR32_CBSubClassMask,
9314 SuperRegIdxSeqs + 1,
9315 LaneBitmask(0x000000000000000F),
9316 0,
9317 false,
9318 0x00, /* TSFlags */
9319 true, /* HasDisjunctSubRegs */
9320 false, /* CoveredBySubRegs */
9321 GR64_with_sub_32bit_in_GR32_CBSuperclasses, 11,
9322 nullptr
9323 };
9324
9325 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_DIBPRegClass = {
9326 &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_DIBPRegClassID],
9327 GR64_with_sub_32bit_in_GR32_DIBPSubClassMask,
9328 SuperRegIdxSeqs + 1,
9329 LaneBitmask(0x000000000000000F),
9330 0,
9331 false,
9332 0x00, /* TSFlags */
9333 true, /* HasDisjunctSubRegs */
9334 false, /* CoveredBySubRegs */
9335 GR64_with_sub_32bit_in_GR32_DIBPSuperclasses, 10,
9336 nullptr
9337 };
9338
9339 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_SIDIRegClass = {
9340 &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_SIDIRegClassID],
9341 GR64_with_sub_32bit_in_GR32_SIDISubClassMask,
9342 SuperRegIdxSeqs + 1,
9343 LaneBitmask(0x000000000000000F),
9344 0,
9345 false,
9346 0x00, /* TSFlags */
9347 true, /* HasDisjunctSubRegs */
9348 false, /* CoveredBySubRegs */
9349 GR64_with_sub_32bit_in_GR32_SIDISuperclasses, 17,
9350 nullptr
9351 };
9352
9353 extern const TargetRegisterClass GR64_ARegClass = {
9354 &X86MCRegisterClasses[GR64_ARegClassID],
9355 GR64_ASubClassMask,
9356 SuperRegIdxSeqs + 1,
9357 LaneBitmask(0x000000000000000F),
9358 0,
9359 false,
9360 0x00, /* TSFlags */
9361 true, /* HasDisjunctSubRegs */
9362 false, /* CoveredBySubRegs */
9363 GR64_ASuperclasses, 29,
9364 nullptr
9365 };
9366
9367 extern const TargetRegisterClass GR64_ArgRef_and_GR64_TCRegClass = {
9368 &X86MCRegisterClasses[GR64_ArgRef_and_GR64_TCRegClassID],
9369 GR64_ArgRef_and_GR64_TCSubClassMask,
9370 SuperRegIdxSeqs + 1,
9371 LaneBitmask(0x000000000000000F),
9372 0,
9373 false,
9374 0x00, /* TSFlags */
9375 true, /* HasDisjunctSubRegs */
9376 false, /* CoveredBySubRegs */
9377 GR64_ArgRef_and_GR64_TCSuperclasses, 16,
9378 nullptr
9379 };
9380
9381 extern const TargetRegisterClass GR64_and_LOW32_ADDR_ACCESSRegClass = {
9382 &X86MCRegisterClasses[GR64_and_LOW32_ADDR_ACCESSRegClassID],
9383 GR64_and_LOW32_ADDR_ACCESSSubClassMask,
9384 SuperRegIdxSeqs + 1,
9385 LaneBitmask(0x000000000000000F),
9386 0,
9387 false,
9388 0x00, /* TSFlags */
9389 true, /* HasDisjunctSubRegs */
9390 false, /* CoveredBySubRegs */
9391 GR64_and_LOW32_ADDR_ACCESSSuperclasses, 13,
9392 nullptr
9393 };
9394
9395 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClass = {
9396 &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClassID],
9397 GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSISubClassMask,
9398 SuperRegIdxSeqs + 1,
9399 LaneBitmask(0x000000000000000F),
9400 0,
9401 false,
9402 0x00, /* TSFlags */
9403 true, /* HasDisjunctSubRegs */
9404 false, /* CoveredBySubRegs */
9405 GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSISuperclasses, 13,
9406 nullptr
9407 };
9408
9409 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefRegClass = {
9410 &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefRegClassID],
9411 GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefSubClassMask,
9412 SuperRegIdxSeqs + 1,
9413 LaneBitmask(0x000000000000000F),
9414 0,
9415 false,
9416 0x00, /* TSFlags */
9417 true, /* HasDisjunctSubRegs */
9418 false, /* CoveredBySubRegs */
9419 GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefSuperclasses, 30,
9420 nullptr
9421 };
9422
9423 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBRegClass = {
9424 &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBRegClassID],
9425 GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBSubClassMask,
9426 SuperRegIdxSeqs + 1,
9427 LaneBitmask(0x000000000000000F),
9428 0,
9429 false,
9430 0x00, /* TSFlags */
9431 true, /* HasDisjunctSubRegs */
9432 false, /* CoveredBySubRegs */
9433 GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBSuperclasses, 30,
9434 nullptr
9435 };
9436
9437 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClass = {
9438 &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClassID],
9439 GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPSubClassMask,
9440 SuperRegIdxSeqs + 1,
9441 LaneBitmask(0x000000000000000F),
9442 0,
9443 false,
9444 0x00, /* TSFlags */
9445 true, /* HasDisjunctSubRegs */
9446 false, /* CoveredBySubRegs */
9447 GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPSuperclasses, 19,
9448 nullptr
9449 };
9450
9451 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClass = {
9452 &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClassID],
9453 GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCSubClassMask,
9454 SuperRegIdxSeqs + 1,
9455 LaneBitmask(0x000000000000000F),
9456 0,
9457 false,
9458 0x00, /* TSFlags */
9459 true, /* HasDisjunctSubRegs */
9460 false, /* CoveredBySubRegs */
9461 GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCSuperclasses, 17,
9462 nullptr
9463 };
9464
9465 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClass = {
9466 &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClassID],
9467 GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDISubClassMask,
9468 SuperRegIdxSeqs + 1,
9469 LaneBitmask(0x000000000000000F),
9470 0,
9471 false,
9472 0x00, /* TSFlags */
9473 true, /* HasDisjunctSubRegs */
9474 false, /* CoveredBySubRegs */
9475 GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDISuperclasses, 19,
9476 nullptr
9477 };
9478
9479 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClass = {
9480 &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClassID],
9481 GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDISubClassMask,
9482 SuperRegIdxSeqs + 1,
9483 LaneBitmask(0x000000000000000F),
9484 0,
9485 false,
9486 0x00, /* TSFlags */
9487 true, /* HasDisjunctSubRegs */
9488 false, /* CoveredBySubRegs */
9489 GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDISuperclasses, 19,
9490 nullptr
9491 };
9492
9493 extern const TargetRegisterClass RSTRegClass = {
9494 &X86MCRegisterClasses[RSTRegClassID],
9495 RSTSubClassMask,
9496 SuperRegIdxSeqs + 1,
9497 LaneBitmask(0x0000000000000001),
9498 0,
9499 false,
9500 0x00, /* TSFlags */
9501 false, /* HasDisjunctSubRegs */
9502 false, /* CoveredBySubRegs */
9503 nullptr, 0,
9504 nullptr
9505 };
9506
9507 extern const TargetRegisterClass RFP80RegClass = {
9508 &X86MCRegisterClasses[RFP80RegClassID],
9509 RFP80SubClassMask,
9510 SuperRegIdxSeqs + 1,
9511 LaneBitmask(0x0000000000000001),
9512 0,
9513 false,
9514 0x00, /* TSFlags */
9515 false, /* HasDisjunctSubRegs */
9516 false, /* CoveredBySubRegs */
9517 RFP80Superclasses, 2,
9518 nullptr
9519 };
9520
9521 extern const TargetRegisterClass RFP80_7RegClass = {
9522 &X86MCRegisterClasses[RFP80_7RegClassID],
9523 RFP80_7SubClassMask,
9524 SuperRegIdxSeqs + 1,
9525 LaneBitmask(0x0000000000000001),
9526 0,
9527 false,
9528 0x00, /* TSFlags */
9529 false, /* HasDisjunctSubRegs */
9530 false, /* CoveredBySubRegs */
9531 nullptr, 0,
9532 nullptr
9533 };
9534
9535 extern const TargetRegisterClass VR128XRegClass = {
9536 &X86MCRegisterClasses[VR128XRegClassID],
9537 VR128XSubClassMask,
9538 SuperRegIdxSeqs + 15,
9539 LaneBitmask(0x0000000000000001),
9540 0,
9541 false,
9542 0x00, /* TSFlags */
9543 false, /* HasDisjunctSubRegs */
9544 false, /* CoveredBySubRegs */
9545 VR128XSuperclasses, 3,
9546 VR128XGetRawAllocationOrder
9547 };
9548
9549 extern const TargetRegisterClass VR128RegClass = {
9550 &X86MCRegisterClasses[VR128RegClassID],
9551 VR128SubClassMask,
9552 SuperRegIdxSeqs + 15,
9553 LaneBitmask(0x0000000000000001),
9554 0,
9555 false,
9556 0x00, /* TSFlags */
9557 false, /* HasDisjunctSubRegs */
9558 false, /* CoveredBySubRegs */
9559 VR128Superclasses, 7,
9560 nullptr
9561 };
9562
9563 extern const TargetRegisterClass VR256XRegClass = {
9564 &X86MCRegisterClasses[VR256XRegClassID],
9565 VR256XSubClassMask,
9566 SuperRegIdxSeqs + 17,
9567 LaneBitmask(0x0000000000000100),
9568 0,
9569 false,
9570 0x00, /* TSFlags */
9571 false, /* HasDisjunctSubRegs */
9572 false, /* CoveredBySubRegs */
9573 nullptr, 0,
9574 VR256XGetRawAllocationOrder
9575 };
9576
9577 extern const TargetRegisterClass VR256RegClass = {
9578 &X86MCRegisterClasses[VR256RegClassID],
9579 VR256SubClassMask,
9580 SuperRegIdxSeqs + 17,
9581 LaneBitmask(0x0000000000000100),
9582 0,
9583 false,
9584 0x00, /* TSFlags */
9585 false, /* HasDisjunctSubRegs */
9586 false, /* CoveredBySubRegs */
9587 VR256Superclasses, 1,
9588 nullptr
9589 };
9590
9591 extern const TargetRegisterClass VR512RegClass = {
9592 &X86MCRegisterClasses[VR512RegClassID],
9593 VR512SubClassMask,
9594 SuperRegIdxSeqs + 1,
9595 LaneBitmask(0x0000000000000100),
9596 0,
9597 false,
9598 0x00, /* TSFlags */
9599 false, /* HasDisjunctSubRegs */
9600 false, /* CoveredBySubRegs */
9601 nullptr, 0,
9602 nullptr
9603 };
9604
9605 extern const TargetRegisterClass VR512_0_15RegClass = {
9606 &X86MCRegisterClasses[VR512_0_15RegClassID],
9607 VR512_0_15SubClassMask,
9608 SuperRegIdxSeqs + 1,
9609 LaneBitmask(0x0000000000000100),
9610 0,
9611 false,
9612 0x00, /* TSFlags */
9613 false, /* HasDisjunctSubRegs */
9614 false, /* CoveredBySubRegs */
9615 VR512_0_15Superclasses, 1,
9616 nullptr
9617 };
9618
9619 extern const TargetRegisterClass TILERegClass = {
9620 &X86MCRegisterClasses[TILERegClassID],
9621 TILESubClassMask,
9622 SuperRegIdxSeqs + 12,
9623 LaneBitmask(0x0000000000000001),
9624 0,
9625 false,
9626 0x00, /* TSFlags */
9627 false, /* HasDisjunctSubRegs */
9628 false, /* CoveredBySubRegs */
9629 nullptr, 0,
9630 nullptr
9631 };
9632
9633 extern const TargetRegisterClass TILEPAIRRegClass = {
9634 &X86MCRegisterClasses[TILEPAIRRegClassID],
9635 TILEPAIRSubClassMask,
9636 SuperRegIdxSeqs + 1,
9637 LaneBitmask(0x00000000000000C0),
9638 0,
9639 false,
9640 0x00, /* TSFlags */
9641 true, /* HasDisjunctSubRegs */
9642 true, /* CoveredBySubRegs */
9643 nullptr, 0,
9644 nullptr
9645 };
9646
9647} // end namespace X86
9648
9649namespace {
9650 const TargetRegisterClass *const RegisterClasses[] = {
9651 &X86::GR8RegClass,
9652 &X86::GRH8RegClass,
9653 &X86::GR8_NOREX2RegClass,
9654 &X86::GR8_NOREXRegClass,
9655 &X86::GR8_ABCD_HRegClass,
9656 &X86::GR8_ABCD_LRegClass,
9657 &X86::GRH16RegClass,
9658 &X86::GR16RegClass,
9659 &X86::GR16_NOREX2RegClass,
9660 &X86::GR16_NOREXRegClass,
9661 &X86::VK1RegClass,
9662 &X86::VK16RegClass,
9663 &X86::VK2RegClass,
9664 &X86::VK4RegClass,
9665 &X86::VK8RegClass,
9666 &X86::VK16WMRegClass,
9667 &X86::VK1WMRegClass,
9668 &X86::VK2WMRegClass,
9669 &X86::VK4WMRegClass,
9670 &X86::VK8WMRegClass,
9671 &X86::SEGMENT_REGRegClass,
9672 &X86::GR16_ABCDRegClass,
9673 &X86::FPCCRRegClass,
9674 &X86::FR16XRegClass,
9675 &X86::FR16RegClass,
9676 &X86::VK16PAIRRegClass,
9677 &X86::VK1PAIRRegClass,
9678 &X86::VK2PAIRRegClass,
9679 &X86::VK4PAIRRegClass,
9680 &X86::VK8PAIRRegClass,
9681 &X86::VK1PAIR_with_sub_mask_0_in_VK1WMRegClass,
9682 &X86::LOW32_ADDR_ACCESS_RBPRegClass,
9683 &X86::LOW32_ADDR_ACCESSRegClass,
9684 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
9685 &X86::FR32XRegClass,
9686 &X86::GR32RegClass,
9687 &X86::GR32_NOSPRegClass,
9688 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClass,
9689 &X86::DEBUG_REGRegClass,
9690 &X86::FR32RegClass,
9691 &X86::GR32_NOREX2RegClass,
9692 &X86::GR32_NOREX2_NOSPRegClass,
9693 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
9694 &X86::GR32_NOREXRegClass,
9695 &X86::VK32RegClass,
9696 &X86::GR32_NOREX_NOSPRegClass,
9697 &X86::RFP32RegClass,
9698 &X86::VK32WMRegClass,
9699 &X86::GR32_ABCDRegClass,
9700 &X86::GR32_TCRegClass,
9701 &X86::GR32_ABCD_and_GR32_TCRegClass,
9702 &X86::GR32_ADRegClass,
9703 &X86::GR32_ArgRefRegClass,
9704 &X86::GR32_BPSPRegClass,
9705 &X86::GR32_BSIRegClass,
9706 &X86::GR32_CBRegClass,
9707 &X86::GR32_DCRegClass,
9708 &X86::GR32_DIBPRegClass,
9709 &X86::GR32_SIDIRegClass,
9710 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass,
9711 &X86::CCRRegClass,
9712 &X86::DFCCRRegClass,
9713 &X86::GR32_ABCD_and_GR32_BSIRegClass,
9714 &X86::GR32_AD_and_GR32_ArgRefRegClass,
9715 &X86::GR32_ArgRef_and_GR32_CBRegClass,
9716 &X86::GR32_BPSP_and_GR32_DIBPRegClass,
9717 &X86::GR32_BPSP_and_GR32_TCRegClass,
9718 &X86::GR32_BSI_and_GR32_SIDIRegClass,
9719 &X86::GR32_DIBP_and_GR32_SIDIRegClass,
9720 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClass,
9721 &X86::LOW32_ADDR_ACCESS_with_sub_32bitRegClass,
9722 &X86::RFP64RegClass,
9723 &X86::GR64RegClass,
9724 &X86::FR64XRegClass,
9725 &X86::GR64_with_sub_8bitRegClass,
9726 &X86::GR64_NOSPRegClass,
9727 &X86::GR64_NOREX2RegClass,
9728 &X86::CONTROL_REGRegClass,
9729 &X86::FR64RegClass,
9730 &X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClass,
9731 &X86::GR64_NOREX2_NOSPRegClass,
9732 &X86::GR64PLTSafeRegClass,
9733 &X86::GR64_TCRegClass,
9734 &X86::GR64_NOREXRegClass,
9735 &X86::GR64_TCW64RegClass,
9736 &X86::GR64_TC_with_sub_8bitRegClass,
9737 &X86::GR64_NOREX2_NOSP_and_GR64_TCRegClass,
9738 &X86::GR64_TCW64_with_sub_8bitRegClass,
9739 &X86::GR64_TC_and_GR64_TCW64RegClass,
9740 &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
9741 &X86::VK64RegClass,
9742 &X86::VR64RegClass,
9743 &X86::GR64PLTSafe_and_GR64_TCRegClass,
9744 &X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClass,
9745 &X86::GR64_NOREX_NOSPRegClass,
9746 &X86::GR64_NOREX_and_GR64_TCRegClass,
9747 &X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass,
9748 &X86::VK64WMRegClass,
9749 &X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClass,
9750 &X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass,
9751 &X86::GR64PLTSafe_and_GR64_TCW64RegClass,
9752 &X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClass,
9753 &X86::GR64_NOREX_and_GR64_TCW64RegClass,
9754 &X86::GR64_ABCDRegClass,
9755 &X86::GR64_with_sub_32bit_in_GR32_TCRegClass,
9756 &X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClass,
9757 &X86::GR64_ADRegClass,
9758 &X86::GR64_ArgRefRegClass,
9759 &X86::GR64_and_LOW32_ADDR_ACCESS_RBPRegClass,
9760 &X86::GR64_with_sub_32bit_in_GR32_ArgRefRegClass,
9761 &X86::GR64_with_sub_32bit_in_GR32_BPSPRegClass,
9762 &X86::GR64_with_sub_32bit_in_GR32_BSIRegClass,
9763 &X86::GR64_with_sub_32bit_in_GR32_CBRegClass,
9764 &X86::GR64_with_sub_32bit_in_GR32_DIBPRegClass,
9765 &X86::GR64_with_sub_32bit_in_GR32_SIDIRegClass,
9766 &X86::GR64_ARegClass,
9767 &X86::GR64_ArgRef_and_GR64_TCRegClass,
9768 &X86::GR64_and_LOW32_ADDR_ACCESSRegClass,
9769 &X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClass,
9770 &X86::GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefRegClass,
9771 &X86::GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBRegClass,
9772 &X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClass,
9773 &X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClass,
9774 &X86::GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClass,
9775 &X86::GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClass,
9776 &X86::RSTRegClass,
9777 &X86::RFP80RegClass,
9778 &X86::RFP80_7RegClass,
9779 &X86::VR128XRegClass,
9780 &X86::VR128RegClass,
9781 &X86::VR256XRegClass,
9782 &X86::VR256RegClass,
9783 &X86::VR512RegClass,
9784 &X86::VR512_0_15RegClass,
9785 &X86::TILERegClass,
9786 &X86::TILEPAIRRegClass,
9787 };
9788} // end anonymous namespace
9789
9790static const uint8_t CostPerUseTable[] = {
97910, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
9792
9793
9794static const bool InAllocatableClassTable[] = {
9795false, true, true, true, true, true, true, false, true, true, true, true, true, true, false, true, true, false, true, true, true, true, true, true, true, true, true, true, false, false, false, true, true, true, false, false, true, false, true, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, false, true, false, true, true, true, false, true, true, false, true, true, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, };
9796
9797
9798static const TargetRegisterInfoDesc X86RegInfoDesc = { // Extra Descriptors
9799CostPerUseTable, 1, InAllocatableClassTable};
9800
9801unsigned X86GenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
9802 static const uint8_t Rows[1][12] = {
9803 { X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, 0, 0, X86::sub_xmm, 0, },
9804 };
9805
9806 --IdxA; assert(IdxA < 12); (void) IdxA;
9807 --IdxB; assert(IdxB < 12);
9808 return Rows[0][IdxB];
9809}
9810
9811unsigned X86GenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
9812 static const uint8_t Table[12][12] = {
9813 { X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, 0, 0, X86::sub_xmm, 0, },
9814 { X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, 0, 0, X86::sub_xmm, 0, },
9815 { X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, 0, 0, X86::sub_xmm, 0, },
9816 { X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, 0, 0, X86::sub_xmm, 0, },
9817 { X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, 0, 0, X86::sub_xmm, 0, },
9818 { X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, 0, 0, X86::sub_xmm, 0, },
9819 { X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, 0, 0, X86::sub_xmm, 0, },
9820 { X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, 0, 0, X86::sub_xmm, 0, },
9821 { X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, 0, 0, X86::sub_xmm, 0, },
9822 { X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, 0, 0, X86::sub_xmm, 0, },
9823 { X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, 0, 0, X86::sub_xmm, 0, },
9824 { X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, 0, 0, X86::sub_xmm, 0, },
9825 };
9826
9827 --IdxA; assert(IdxA < 12);
9828 --IdxB; assert(IdxB < 12);
9829 return Table[IdxA][IdxB];
9830 }
9831
9832 struct MaskRolOp {
9833 LaneBitmask Mask;
9834 uint8_t RotateLeft;
9835 };
9836 static const MaskRolOp LaneMaskComposeSequences[] = {
9837 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 0 }, { LaneBitmask::getNone(), 0 }, // Sequence 0
9838 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 1 }, { LaneBitmask::getNone(), 0 }, // Sequence 2
9839 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 2 }, { LaneBitmask::getNone(), 0 }, // Sequence 4
9840 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 3 }, { LaneBitmask::getNone(), 0 }, // Sequence 6
9841 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 4 }, { LaneBitmask::getNone(), 0 }, // Sequence 8
9842 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 5 }, { LaneBitmask::getNone(), 0 }, // Sequence 10
9843 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 6 }, { LaneBitmask::getNone(), 0 }, // Sequence 12
9844 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 7 }, { LaneBitmask::getNone(), 0 }, // Sequence 14
9845 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 8 }, { LaneBitmask::getNone(), 0 } // Sequence 16
9846 };
9847 static const uint8_t CompositeSequences[] = {
9848 0, // to sub_8bit
9849 2, // to sub_8bit_hi
9850 4, // to sub_8bit_hi_phony
9851 0, // to sub_16bit
9852 6, // to sub_16bit_hi
9853 0, // to sub_32bit
9854 8, // to sub_mask_0
9855 10, // to sub_mask_1
9856 12, // to sub_t0
9857 14, // to sub_t1
9858 16, // to sub_xmm
9859 0 // to sub_ymm
9860 };
9861
9862LaneBitmask X86GenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
9863 --IdxA; assert(IdxA < 12 && "Subregister index out of bounds");
9864 LaneBitmask Result;
9865 for (const MaskRolOp *Ops =
9866 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
9867 Ops->Mask.any(); ++Ops) {
9868 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
9869 if (unsigned S = Ops->RotateLeft)
9870 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
9871 else
9872 Result |= LaneBitmask(M);
9873 }
9874 return Result;
9875}
9876
9877LaneBitmask X86GenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
9878 LaneMask &= getSubRegIndexLaneMask(IdxA);
9879 --IdxA; assert(IdxA < 12 && "Subregister index out of bounds");
9880 LaneBitmask Result;
9881 for (const MaskRolOp *Ops =
9882 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
9883 Ops->Mask.any(); ++Ops) {
9884 LaneBitmask::Type M = LaneMask.getAsInteger();
9885 if (unsigned S = Ops->RotateLeft)
9886 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
9887 else
9888 Result |= LaneBitmask(M);
9889 }
9890 return Result;
9891}
9892
9893const TargetRegisterClass *X86GenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
9894 static const uint8_t Table[136][12] = {
9895 { // GR8
9896 0, // sub_8bit
9897 0, // sub_8bit_hi
9898 0, // sub_8bit_hi_phony
9899 0, // sub_16bit
9900 0, // sub_16bit_hi
9901 0, // sub_32bit
9902 0, // sub_mask_0
9903 0, // sub_mask_1
9904 0, // sub_t0
9905 0, // sub_t1
9906 0, // sub_xmm
9907 0, // sub_ymm
9908 },
9909 { // GRH8
9910 0, // sub_8bit
9911 0, // sub_8bit_hi
9912 0, // sub_8bit_hi_phony
9913 0, // sub_16bit
9914 0, // sub_16bit_hi
9915 0, // sub_32bit
9916 0, // sub_mask_0
9917 0, // sub_mask_1
9918 0, // sub_t0
9919 0, // sub_t1
9920 0, // sub_xmm
9921 0, // sub_ymm
9922 },
9923 { // GR8_NOREX2
9924 0, // sub_8bit
9925 0, // sub_8bit_hi
9926 0, // sub_8bit_hi_phony
9927 0, // sub_16bit
9928 0, // sub_16bit_hi
9929 0, // sub_32bit
9930 0, // sub_mask_0
9931 0, // sub_mask_1
9932 0, // sub_t0
9933 0, // sub_t1
9934 0, // sub_xmm
9935 0, // sub_ymm
9936 },
9937 { // GR8_NOREX
9938 0, // sub_8bit
9939 0, // sub_8bit_hi
9940 0, // sub_8bit_hi_phony
9941 0, // sub_16bit
9942 0, // sub_16bit_hi
9943 0, // sub_32bit
9944 0, // sub_mask_0
9945 0, // sub_mask_1
9946 0, // sub_t0
9947 0, // sub_t1
9948 0, // sub_xmm
9949 0, // sub_ymm
9950 },
9951 { // GR8_ABCD_H
9952 0, // sub_8bit
9953 0, // sub_8bit_hi
9954 0, // sub_8bit_hi_phony
9955 0, // sub_16bit
9956 0, // sub_16bit_hi
9957 0, // sub_32bit
9958 0, // sub_mask_0
9959 0, // sub_mask_1
9960 0, // sub_t0
9961 0, // sub_t1
9962 0, // sub_xmm
9963 0, // sub_ymm
9964 },
9965 { // GR8_ABCD_L
9966 0, // sub_8bit
9967 0, // sub_8bit_hi
9968 0, // sub_8bit_hi_phony
9969 0, // sub_16bit
9970 0, // sub_16bit_hi
9971 0, // sub_32bit
9972 0, // sub_mask_0
9973 0, // sub_mask_1
9974 0, // sub_t0
9975 0, // sub_t1
9976 0, // sub_xmm
9977 0, // sub_ymm
9978 },
9979 { // GRH16
9980 0, // sub_8bit
9981 0, // sub_8bit_hi
9982 0, // sub_8bit_hi_phony
9983 0, // sub_16bit
9984 0, // sub_16bit_hi
9985 0, // sub_32bit
9986 0, // sub_mask_0
9987 0, // sub_mask_1
9988 0, // sub_t0
9989 0, // sub_t1
9990 0, // sub_xmm
9991 0, // sub_ymm
9992 },
9993 { // GR16
9994 8, // sub_8bit -> GR16
9995 22, // sub_8bit_hi -> GR16_ABCD
9996 0, // sub_8bit_hi_phony
9997 0, // sub_16bit
9998 0, // sub_16bit_hi
9999 0, // sub_32bit
10000 0, // sub_mask_0
10001 0, // sub_mask_1
10002 0, // sub_t0
10003 0, // sub_t1
10004 0, // sub_xmm
10005 0, // sub_ymm
10006 },
10007 { // GR16_NOREX2
10008 9, // sub_8bit -> GR16_NOREX2
10009 22, // sub_8bit_hi -> GR16_ABCD
10010 0, // sub_8bit_hi_phony
10011 0, // sub_16bit
10012 0, // sub_16bit_hi
10013 0, // sub_32bit
10014 0, // sub_mask_0
10015 0, // sub_mask_1
10016 0, // sub_t0
10017 0, // sub_t1
10018 0, // sub_xmm
10019 0, // sub_ymm
10020 },
10021 { // GR16_NOREX
10022 10, // sub_8bit -> GR16_NOREX
10023 22, // sub_8bit_hi -> GR16_ABCD
10024 0, // sub_8bit_hi_phony
10025 0, // sub_16bit
10026 0, // sub_16bit_hi
10027 0, // sub_32bit
10028 0, // sub_mask_0
10029 0, // sub_mask_1
10030 0, // sub_t0
10031 0, // sub_t1
10032 0, // sub_xmm
10033 0, // sub_ymm
10034 },
10035 { // VK1
10036 0, // sub_8bit
10037 0, // sub_8bit_hi
10038 0, // sub_8bit_hi_phony
10039 0, // sub_16bit
10040 0, // sub_16bit_hi
10041 0, // sub_32bit
10042 0, // sub_mask_0
10043 0, // sub_mask_1
10044 0, // sub_t0
10045 0, // sub_t1
10046 0, // sub_xmm
10047 0, // sub_ymm
10048 },
10049 { // VK16
10050 0, // sub_8bit
10051 0, // sub_8bit_hi
10052 0, // sub_8bit_hi_phony
10053 0, // sub_16bit
10054 0, // sub_16bit_hi
10055 0, // sub_32bit
10056 0, // sub_mask_0
10057 0, // sub_mask_1
10058 0, // sub_t0
10059 0, // sub_t1
10060 0, // sub_xmm
10061 0, // sub_ymm
10062 },
10063 { // VK2
10064 0, // sub_8bit
10065 0, // sub_8bit_hi
10066 0, // sub_8bit_hi_phony
10067 0, // sub_16bit
10068 0, // sub_16bit_hi
10069 0, // sub_32bit
10070 0, // sub_mask_0
10071 0, // sub_mask_1
10072 0, // sub_t0
10073 0, // sub_t1
10074 0, // sub_xmm
10075 0, // sub_ymm
10076 },
10077 { // VK4
10078 0, // sub_8bit
10079 0, // sub_8bit_hi
10080 0, // sub_8bit_hi_phony
10081 0, // sub_16bit
10082 0, // sub_16bit_hi
10083 0, // sub_32bit
10084 0, // sub_mask_0
10085 0, // sub_mask_1
10086 0, // sub_t0
10087 0, // sub_t1
10088 0, // sub_xmm
10089 0, // sub_ymm
10090 },
10091 { // VK8
10092 0, // sub_8bit
10093 0, // sub_8bit_hi
10094 0, // sub_8bit_hi_phony
10095 0, // sub_16bit
10096 0, // sub_16bit_hi
10097 0, // sub_32bit
10098 0, // sub_mask_0
10099 0, // sub_mask_1
10100 0, // sub_t0
10101 0, // sub_t1
10102 0, // sub_xmm
10103 0, // sub_ymm
10104 },
10105 { // VK16WM
10106 0, // sub_8bit
10107 0, // sub_8bit_hi
10108 0, // sub_8bit_hi_phony
10109 0, // sub_16bit
10110 0, // sub_16bit_hi
10111 0, // sub_32bit
10112 0, // sub_mask_0
10113 0, // sub_mask_1
10114 0, // sub_t0
10115 0, // sub_t1
10116 0, // sub_xmm
10117 0, // sub_ymm
10118 },
10119 { // VK1WM
10120 0, // sub_8bit
10121 0, // sub_8bit_hi
10122 0, // sub_8bit_hi_phony
10123 0, // sub_16bit
10124 0, // sub_16bit_hi
10125 0, // sub_32bit
10126 0, // sub_mask_0
10127 0, // sub_mask_1
10128 0, // sub_t0
10129 0, // sub_t1
10130 0, // sub_xmm
10131 0, // sub_ymm
10132 },
10133 { // VK2WM
10134 0, // sub_8bit
10135 0, // sub_8bit_hi
10136 0, // sub_8bit_hi_phony
10137 0, // sub_16bit
10138 0, // sub_16bit_hi
10139 0, // sub_32bit
10140 0, // sub_mask_0
10141 0, // sub_mask_1
10142 0, // sub_t0
10143 0, // sub_t1
10144 0, // sub_xmm
10145 0, // sub_ymm
10146 },
10147 { // VK4WM
10148 0, // sub_8bit
10149 0, // sub_8bit_hi
10150 0, // sub_8bit_hi_phony
10151 0, // sub_16bit
10152 0, // sub_16bit_hi
10153 0, // sub_32bit
10154 0, // sub_mask_0
10155 0, // sub_mask_1
10156 0, // sub_t0
10157 0, // sub_t1
10158 0, // sub_xmm
10159 0, // sub_ymm
10160 },
10161 { // VK8WM
10162 0, // sub_8bit
10163 0, // sub_8bit_hi
10164 0, // sub_8bit_hi_phony
10165 0, // sub_16bit
10166 0, // sub_16bit_hi
10167 0, // sub_32bit
10168 0, // sub_mask_0
10169 0, // sub_mask_1
10170 0, // sub_t0
10171 0, // sub_t1
10172 0, // sub_xmm
10173 0, // sub_ymm
10174 },
10175 { // SEGMENT_REG
10176 0, // sub_8bit
10177 0, // sub_8bit_hi
10178 0, // sub_8bit_hi_phony
10179 0, // sub_16bit
10180 0, // sub_16bit_hi
10181 0, // sub_32bit
10182 0, // sub_mask_0
10183 0, // sub_mask_1
10184 0, // sub_t0
10185 0, // sub_t1
10186 0, // sub_xmm
10187 0, // sub_ymm
10188 },
10189 { // GR16_ABCD
10190 22, // sub_8bit -> GR16_ABCD
10191 22, // sub_8bit_hi -> GR16_ABCD
10192 0, // sub_8bit_hi_phony
10193 0, // sub_16bit
10194 0, // sub_16bit_hi
10195 0, // sub_32bit
10196 0, // sub_mask_0
10197 0, // sub_mask_1
10198 0, // sub_t0
10199 0, // sub_t1
10200 0, // sub_xmm
10201 0, // sub_ymm
10202 },
10203 { // FPCCR
10204 0, // sub_8bit
10205 0, // sub_8bit_hi
10206 0, // sub_8bit_hi_phony
10207 0, // sub_16bit
10208 0, // sub_16bit_hi
10209 0, // sub_32bit
10210 0, // sub_mask_0
10211 0, // sub_mask_1
10212 0, // sub_t0
10213 0, // sub_t1
10214 0, // sub_xmm
10215 0, // sub_ymm
10216 },
10217 { // FR16X
10218 0, // sub_8bit
10219 0, // sub_8bit_hi
10220 0, // sub_8bit_hi_phony
10221 0, // sub_16bit
10222 0, // sub_16bit_hi
10223 0, // sub_32bit
10224 0, // sub_mask_0
10225 0, // sub_mask_1
10226 0, // sub_t0
10227 0, // sub_t1
10228 0, // sub_xmm
10229 0, // sub_ymm
10230 },
10231 { // FR16
10232 0, // sub_8bit
10233 0, // sub_8bit_hi
10234 0, // sub_8bit_hi_phony
10235 0, // sub_16bit
10236 0, // sub_16bit_hi
10237 0, // sub_32bit
10238 0, // sub_mask_0
10239 0, // sub_mask_1
10240 0, // sub_t0
10241 0, // sub_t1
10242 0, // sub_xmm
10243 0, // sub_ymm
10244 },
10245 { // VK16PAIR
10246 0, // sub_8bit
10247 0, // sub_8bit_hi
10248 0, // sub_8bit_hi_phony
10249 0, // sub_16bit
10250 0, // sub_16bit_hi
10251 0, // sub_32bit
10252 26, // sub_mask_0 -> VK16PAIR
10253 26, // sub_mask_1 -> VK16PAIR
10254 0, // sub_t0
10255 0, // sub_t1
10256 0, // sub_xmm
10257 0, // sub_ymm
10258 },
10259 { // VK1PAIR
10260 0, // sub_8bit
10261 0, // sub_8bit_hi
10262 0, // sub_8bit_hi_phony
10263 0, // sub_16bit
10264 0, // sub_16bit_hi
10265 0, // sub_32bit
10266 27, // sub_mask_0 -> VK1PAIR
10267 27, // sub_mask_1 -> VK1PAIR
10268 0, // sub_t0
10269 0, // sub_t1
10270 0, // sub_xmm
10271 0, // sub_ymm
10272 },
10273 { // VK2PAIR
10274 0, // sub_8bit
10275 0, // sub_8bit_hi
10276 0, // sub_8bit_hi_phony
10277 0, // sub_16bit
10278 0, // sub_16bit_hi
10279 0, // sub_32bit
10280 28, // sub_mask_0 -> VK2PAIR
10281 28, // sub_mask_1 -> VK2PAIR
10282 0, // sub_t0
10283 0, // sub_t1
10284 0, // sub_xmm
10285 0, // sub_ymm
10286 },
10287 { // VK4PAIR
10288 0, // sub_8bit
10289 0, // sub_8bit_hi
10290 0, // sub_8bit_hi_phony
10291 0, // sub_16bit
10292 0, // sub_16bit_hi
10293 0, // sub_32bit
10294 29, // sub_mask_0 -> VK4PAIR
10295 29, // sub_mask_1 -> VK4PAIR
10296 0, // sub_t0
10297 0, // sub_t1
10298 0, // sub_xmm
10299 0, // sub_ymm
10300 },
10301 { // VK8PAIR
10302 0, // sub_8bit
10303 0, // sub_8bit_hi
10304 0, // sub_8bit_hi_phony
10305 0, // sub_16bit
10306 0, // sub_16bit_hi
10307 0, // sub_32bit
10308 30, // sub_mask_0 -> VK8PAIR
10309 30, // sub_mask_1 -> VK8PAIR
10310 0, // sub_t0
10311 0, // sub_t1
10312 0, // sub_xmm
10313 0, // sub_ymm
10314 },
10315 { // VK1PAIR_with_sub_mask_0_in_VK1WM
10316 0, // sub_8bit
10317 0, // sub_8bit_hi
10318 0, // sub_8bit_hi_phony
10319 0, // sub_16bit
10320 0, // sub_16bit_hi
10321 0, // sub_32bit
10322 31, // sub_mask_0 -> VK1PAIR_with_sub_mask_0_in_VK1WM
10323 31, // sub_mask_1 -> VK1PAIR_with_sub_mask_0_in_VK1WM
10324 0, // sub_t0
10325 0, // sub_t1
10326 0, // sub_xmm
10327 0, // sub_ymm
10328 },
10329 { // LOW32_ADDR_ACCESS_RBP
10330 34, // sub_8bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit
10331 49, // sub_8bit_hi -> GR32_ABCD
10332 0, // sub_8bit_hi_phony
10333 32, // sub_16bit -> LOW32_ADDR_ACCESS_RBP
10334 32, // sub_16bit_hi -> LOW32_ADDR_ACCESS_RBP
10335 60, // sub_32bit -> LOW32_ADDR_ACCESS_RBP_with_sub_32bit
10336 0, // sub_mask_0
10337 0, // sub_mask_1
10338 0, // sub_t0
10339 0, // sub_t1
10340 0, // sub_xmm
10341 0, // sub_ymm
10342 },
10343 { // LOW32_ADDR_ACCESS
10344 36, // sub_8bit -> GR32
10345 49, // sub_8bit_hi -> GR32_ABCD
10346 0, // sub_8bit_hi_phony
10347 33, // sub_16bit -> LOW32_ADDR_ACCESS
10348 33, // sub_16bit_hi -> LOW32_ADDR_ACCESS
10349 71, // sub_32bit -> LOW32_ADDR_ACCESS_with_sub_32bit
10350 0, // sub_mask_0
10351 0, // sub_mask_1
10352 0, // sub_t0
10353 0, // sub_t1
10354 0, // sub_xmm
10355 0, // sub_ymm
10356 },
10357 { // LOW32_ADDR_ACCESS_RBP_with_sub_8bit
10358 34, // sub_8bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit
10359 49, // sub_8bit_hi -> GR32_ABCD
10360 0, // sub_8bit_hi_phony
10361 34, // sub_16bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit
10362 34, // sub_16bit_hi -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit
10363 70, // sub_32bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
10364 0, // sub_mask_0
10365 0, // sub_mask_1
10366 0, // sub_t0
10367 0, // sub_t1
10368 0, // sub_xmm
10369 0, // sub_ymm
10370 },
10371 { // FR32X
10372 0, // sub_8bit
10373 0, // sub_8bit_hi
10374 0, // sub_8bit_hi_phony
10375 0, // sub_16bit
10376 0, // sub_16bit_hi
10377 0, // sub_32bit
10378 0, // sub_mask_0
10379 0, // sub_mask_1
10380 0, // sub_t0
10381 0, // sub_t1
10382 0, // sub_xmm
10383 0, // sub_ymm
10384 },
10385 { // GR32
10386 36, // sub_8bit -> GR32
10387 49, // sub_8bit_hi -> GR32_ABCD
10388 0, // sub_8bit_hi_phony
10389 36, // sub_16bit -> GR32
10390 36, // sub_16bit_hi -> GR32
10391 0, // sub_32bit
10392 0, // sub_mask_0
10393 0, // sub_mask_1
10394 0, // sub_t0
10395 0, // sub_t1
10396 0, // sub_xmm
10397 0, // sub_ymm
10398 },
10399 { // GR32_NOSP
10400 37, // sub_8bit -> GR32_NOSP
10401 49, // sub_8bit_hi -> GR32_ABCD
10402 0, // sub_8bit_hi_phony
10403 37, // sub_16bit -> GR32_NOSP
10404 37, // sub_16bit_hi -> GR32_NOSP
10405 0, // sub_32bit
10406 0, // sub_mask_0
10407 0, // sub_mask_1
10408 0, // sub_t0
10409 0, // sub_t1
10410 0, // sub_xmm
10411 0, // sub_ymm
10412 },
10413 { // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
10414 38, // sub_8bit -> LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
10415 49, // sub_8bit_hi -> GR32_ABCD
10416 0, // sub_8bit_hi_phony
10417 38, // sub_16bit -> LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
10418 38, // sub_16bit_hi -> LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
10419 70, // sub_32bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
10420 0, // sub_mask_0
10421 0, // sub_mask_1
10422 0, // sub_t0
10423 0, // sub_t1
10424 0, // sub_xmm
10425 0, // sub_ymm
10426 },
10427 { // DEBUG_REG
10428 0, // sub_8bit
10429 0, // sub_8bit_hi
10430 0, // sub_8bit_hi_phony
10431 0, // sub_16bit
10432 0, // sub_16bit_hi
10433 0, // sub_32bit
10434 0, // sub_mask_0
10435 0, // sub_mask_1
10436 0, // sub_t0
10437 0, // sub_t1
10438 0, // sub_xmm
10439 0, // sub_ymm
10440 },
10441 { // FR32
10442 0, // sub_8bit
10443 0, // sub_8bit_hi
10444 0, // sub_8bit_hi_phony
10445 0, // sub_16bit
10446 0, // sub_16bit_hi
10447 0, // sub_32bit
10448 0, // sub_mask_0
10449 0, // sub_mask_1
10450 0, // sub_t0
10451 0, // sub_t1
10452 0, // sub_xmm
10453 0, // sub_ymm
10454 },
10455 { // GR32_NOREX2
10456 41, // sub_8bit -> GR32_NOREX2
10457 49, // sub_8bit_hi -> GR32_ABCD
10458 0, // sub_8bit_hi_phony
10459 41, // sub_16bit -> GR32_NOREX2
10460 41, // sub_16bit_hi -> GR32_NOREX2
10461 0, // sub_32bit
10462 0, // sub_mask_0
10463 0, // sub_mask_1
10464 0, // sub_t0
10465 0, // sub_t1
10466 0, // sub_xmm
10467 0, // sub_ymm
10468 },
10469 { // GR32_NOREX2_NOSP
10470 42, // sub_8bit -> GR32_NOREX2_NOSP
10471 49, // sub_8bit_hi -> GR32_ABCD
10472 0, // sub_8bit_hi_phony
10473 42, // sub_16bit -> GR32_NOREX2_NOSP
10474 42, // sub_16bit_hi -> GR32_NOREX2_NOSP
10475 0, // sub_32bit
10476 0, // sub_mask_0
10477 0, // sub_mask_1
10478 0, // sub_t0
10479 0, // sub_t1
10480 0, // sub_xmm
10481 0, // sub_ymm
10482 },
10483 { // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
10484 43, // sub_8bit -> LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
10485 49, // sub_8bit_hi -> GR32_ABCD
10486 0, // sub_8bit_hi_phony
10487 43, // sub_16bit -> LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
10488 43, // sub_16bit_hi -> LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
10489 70, // sub_32bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
10490 0, // sub_mask_0
10491 0, // sub_mask_1
10492 0, // sub_t0
10493 0, // sub_t1
10494 0, // sub_xmm
10495 0, // sub_ymm
10496 },
10497 { // GR32_NOREX
10498 44, // sub_8bit -> GR32_NOREX
10499 49, // sub_8bit_hi -> GR32_ABCD
10500 0, // sub_8bit_hi_phony
10501 44, // sub_16bit -> GR32_NOREX
10502 44, // sub_16bit_hi -> GR32_NOREX
10503 0, // sub_32bit
10504 0, // sub_mask_0
10505 0, // sub_mask_1
10506 0, // sub_t0
10507 0, // sub_t1
10508 0, // sub_xmm
10509 0, // sub_ymm
10510 },
10511 { // VK32
10512 0, // sub_8bit
10513 0, // sub_8bit_hi
10514 0, // sub_8bit_hi_phony
10515 0, // sub_16bit
10516 0, // sub_16bit_hi
10517 0, // sub_32bit
10518 0, // sub_mask_0
10519 0, // sub_mask_1
10520 0, // sub_t0
10521 0, // sub_t1
10522 0, // sub_xmm
10523 0, // sub_ymm
10524 },
10525 { // GR32_NOREX_NOSP
10526 46, // sub_8bit -> GR32_NOREX_NOSP
10527 49, // sub_8bit_hi -> GR32_ABCD
10528 0, // sub_8bit_hi_phony
10529 46, // sub_16bit -> GR32_NOREX_NOSP
10530 46, // sub_16bit_hi -> GR32_NOREX_NOSP
10531 0, // sub_32bit
10532 0, // sub_mask_0
10533 0, // sub_mask_1
10534 0, // sub_t0
10535 0, // sub_t1
10536 0, // sub_xmm
10537 0, // sub_ymm
10538 },
10539 { // RFP32
10540 0, // sub_8bit
10541 0, // sub_8bit_hi
10542 0, // sub_8bit_hi_phony
10543 0, // sub_16bit
10544 0, // sub_16bit_hi
10545 0, // sub_32bit
10546 0, // sub_mask_0
10547 0, // sub_mask_1
10548 0, // sub_t0
10549 0, // sub_t1
10550 0, // sub_xmm
10551 0, // sub_ymm
10552 },
10553 { // VK32WM
10554 0, // sub_8bit
10555 0, // sub_8bit_hi
10556 0, // sub_8bit_hi_phony
10557 0, // sub_16bit
10558 0, // sub_16bit_hi
10559 0, // sub_32bit
10560 0, // sub_mask_0
10561 0, // sub_mask_1
10562 0, // sub_t0
10563 0, // sub_t1
10564 0, // sub_xmm
10565 0, // sub_ymm
10566 },
10567 { // GR32_ABCD
10568 49, // sub_8bit -> GR32_ABCD
10569 49, // sub_8bit_hi -> GR32_ABCD
10570 0, // sub_8bit_hi_phony
10571 49, // sub_16bit -> GR32_ABCD
10572 49, // sub_16bit_hi -> GR32_ABCD
10573 0, // sub_32bit
10574 0, // sub_mask_0
10575 0, // sub_mask_1
10576 0, // sub_t0
10577 0, // sub_t1
10578 0, // sub_xmm
10579 0, // sub_ymm
10580 },
10581 { // GR32_TC
10582 50, // sub_8bit -> GR32_TC
10583 51, // sub_8bit_hi -> GR32_ABCD_and_GR32_TC
10584 0, // sub_8bit_hi_phony
10585 50, // sub_16bit -> GR32_TC
10586 50, // sub_16bit_hi -> GR32_TC
10587 0, // sub_32bit
10588 0, // sub_mask_0
10589 0, // sub_mask_1
10590 0, // sub_t0
10591 0, // sub_t1
10592 0, // sub_xmm
10593 0, // sub_ymm
10594 },
10595 { // GR32_ABCD_and_GR32_TC
10596 51, // sub_8bit -> GR32_ABCD_and_GR32_TC
10597 51, // sub_8bit_hi -> GR32_ABCD_and_GR32_TC
10598 0, // sub_8bit_hi_phony
10599 51, // sub_16bit -> GR32_ABCD_and_GR32_TC
10600 51, // sub_16bit_hi -> GR32_ABCD_and_GR32_TC
10601 0, // sub_32bit
10602 0, // sub_mask_0
10603 0, // sub_mask_1
10604 0, // sub_t0
10605 0, // sub_t1
10606 0, // sub_xmm
10607 0, // sub_ymm
10608 },
10609 { // GR32_AD
10610 52, // sub_8bit -> GR32_AD
10611 52, // sub_8bit_hi -> GR32_AD
10612 0, // sub_8bit_hi_phony
10613 52, // sub_16bit -> GR32_AD
10614 52, // sub_16bit_hi -> GR32_AD
10615 0, // sub_32bit
10616 0, // sub_mask_0
10617 0, // sub_mask_1
10618 0, // sub_t0
10619 0, // sub_t1
10620 0, // sub_xmm
10621 0, // sub_ymm
10622 },
10623 { // GR32_ArgRef
10624 53, // sub_8bit -> GR32_ArgRef
10625 53, // sub_8bit_hi -> GR32_ArgRef
10626 0, // sub_8bit_hi_phony
10627 53, // sub_16bit -> GR32_ArgRef
10628 53, // sub_16bit_hi -> GR32_ArgRef
10629 0, // sub_32bit
10630 0, // sub_mask_0
10631 0, // sub_mask_1
10632 0, // sub_t0
10633 0, // sub_t1
10634 0, // sub_xmm
10635 0, // sub_ymm
10636 },
10637 { // GR32_BPSP
10638 54, // sub_8bit -> GR32_BPSP
10639 0, // sub_8bit_hi
10640 54, // sub_8bit_hi_phony -> GR32_BPSP
10641 54, // sub_16bit -> GR32_BPSP
10642 54, // sub_16bit_hi -> GR32_BPSP
10643 0, // sub_32bit
10644 0, // sub_mask_0
10645 0, // sub_mask_1
10646 0, // sub_t0
10647 0, // sub_t1
10648 0, // sub_xmm
10649 0, // sub_ymm
10650 },
10651 { // GR32_BSI
10652 55, // sub_8bit -> GR32_BSI
10653 63, // sub_8bit_hi -> GR32_ABCD_and_GR32_BSI
10654 0, // sub_8bit_hi_phony
10655 55, // sub_16bit -> GR32_BSI
10656 55, // sub_16bit_hi -> GR32_BSI
10657 0, // sub_32bit
10658 0, // sub_mask_0
10659 0, // sub_mask_1
10660 0, // sub_t0
10661 0, // sub_t1
10662 0, // sub_xmm
10663 0, // sub_ymm
10664 },
10665 { // GR32_CB
10666 56, // sub_8bit -> GR32_CB
10667 56, // sub_8bit_hi -> GR32_CB
10668 0, // sub_8bit_hi_phony
10669 56, // sub_16bit -> GR32_CB
10670 56, // sub_16bit_hi -> GR32_CB
10671 0, // sub_32bit
10672 0, // sub_mask_0
10673 0, // sub_mask_1
10674 0, // sub_t0
10675 0, // sub_t1
10676 0, // sub_xmm
10677 0, // sub_ymm
10678 },
10679 { // GR32_DC
10680 57, // sub_8bit -> GR32_DC
10681 57, // sub_8bit_hi -> GR32_DC
10682 0, // sub_8bit_hi_phony
10683 57, // sub_16bit -> GR32_DC
10684 57, // sub_16bit_hi -> GR32_DC
10685 0, // sub_32bit
10686 0, // sub_mask_0
10687 0, // sub_mask_1
10688 0, // sub_t0
10689 0, // sub_t1
10690 0, // sub_xmm
10691 0, // sub_ymm
10692 },
10693 { // GR32_DIBP
10694 58, // sub_8bit -> GR32_DIBP
10695 0, // sub_8bit_hi
10696 58, // sub_8bit_hi_phony -> GR32_DIBP
10697 58, // sub_16bit -> GR32_DIBP
10698 58, // sub_16bit_hi -> GR32_DIBP
10699 0, // sub_32bit
10700 0, // sub_mask_0
10701 0, // sub_mask_1
10702 0, // sub_t0
10703 0, // sub_t1
10704 0, // sub_xmm
10705 0, // sub_ymm
10706 },
10707 { // GR32_SIDI
10708 59, // sub_8bit -> GR32_SIDI
10709 0, // sub_8bit_hi
10710 59, // sub_8bit_hi_phony -> GR32_SIDI
10711 59, // sub_16bit -> GR32_SIDI
10712 59, // sub_16bit_hi -> GR32_SIDI
10713 0, // sub_32bit
10714 0, // sub_mask_0
10715 0, // sub_mask_1
10716 0, // sub_t0
10717 0, // sub_t1
10718 0, // sub_xmm
10719 0, // sub_ymm
10720 },
10721 { // LOW32_ADDR_ACCESS_RBP_with_sub_32bit
10722 70, // sub_8bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
10723 0, // sub_8bit_hi
10724 0, // sub_8bit_hi_phony
10725 60, // sub_16bit -> LOW32_ADDR_ACCESS_RBP_with_sub_32bit
10726 60, // sub_16bit_hi -> LOW32_ADDR_ACCESS_RBP_with_sub_32bit
10727 60, // sub_32bit -> LOW32_ADDR_ACCESS_RBP_with_sub_32bit
10728 0, // sub_mask_0
10729 0, // sub_mask_1
10730 0, // sub_t0
10731 0, // sub_t1
10732 0, // sub_xmm
10733 0, // sub_ymm
10734 },
10735 { // CCR
10736 0, // sub_8bit
10737 0, // sub_8bit_hi
10738 0, // sub_8bit_hi_phony
10739 0, // sub_16bit
10740 0, // sub_16bit_hi
10741 0, // sub_32bit
10742 0, // sub_mask_0
10743 0, // sub_mask_1
10744 0, // sub_t0
10745 0, // sub_t1
10746 0, // sub_xmm
10747 0, // sub_ymm
10748 },
10749 { // DFCCR
10750 0, // sub_8bit
10751 0, // sub_8bit_hi
10752 0, // sub_8bit_hi_phony
10753 0, // sub_16bit
10754 0, // sub_16bit_hi
10755 0, // sub_32bit
10756 0, // sub_mask_0
10757 0, // sub_mask_1
10758 0, // sub_t0
10759 0, // sub_t1
10760 0, // sub_xmm
10761 0, // sub_ymm
10762 },
10763 { // GR32_ABCD_and_GR32_BSI
10764 63, // sub_8bit -> GR32_ABCD_and_GR32_BSI
10765 63, // sub_8bit_hi -> GR32_ABCD_and_GR32_BSI
10766 0, // sub_8bit_hi_phony
10767 63, // sub_16bit -> GR32_ABCD_and_GR32_BSI
10768 63, // sub_16bit_hi -> GR32_ABCD_and_GR32_BSI
10769 0, // sub_32bit
10770 0, // sub_mask_0
10771 0, // sub_mask_1
10772 0, // sub_t0
10773 0, // sub_t1
10774 0, // sub_xmm
10775 0, // sub_ymm
10776 },
10777 { // GR32_AD_and_GR32_ArgRef
10778 64, // sub_8bit -> GR32_AD_and_GR32_ArgRef
10779 64, // sub_8bit_hi -> GR32_AD_and_GR32_ArgRef
10780 0, // sub_8bit_hi_phony
10781 64, // sub_16bit -> GR32_AD_and_GR32_ArgRef
10782 64, // sub_16bit_hi -> GR32_AD_and_GR32_ArgRef
10783 0, // sub_32bit
10784 0, // sub_mask_0
10785 0, // sub_mask_1
10786 0, // sub_t0
10787 0, // sub_t1
10788 0, // sub_xmm
10789 0, // sub_ymm
10790 },
10791 { // GR32_ArgRef_and_GR32_CB
10792 65, // sub_8bit -> GR32_ArgRef_and_GR32_CB
10793 65, // sub_8bit_hi -> GR32_ArgRef_and_GR32_CB
10794 0, // sub_8bit_hi_phony
10795 65, // sub_16bit -> GR32_ArgRef_and_GR32_CB
10796 65, // sub_16bit_hi -> GR32_ArgRef_and_GR32_CB
10797 0, // sub_32bit
10798 0, // sub_mask_0
10799 0, // sub_mask_1
10800 0, // sub_t0
10801 0, // sub_t1
10802 0, // sub_xmm
10803 0, // sub_ymm
10804 },
10805 { // GR32_BPSP_and_GR32_DIBP
10806 66, // sub_8bit -> GR32_BPSP_and_GR32_DIBP
10807 0, // sub_8bit_hi
10808 66, // sub_8bit_hi_phony -> GR32_BPSP_and_GR32_DIBP
10809 66, // sub_16bit -> GR32_BPSP_and_GR32_DIBP
10810 66, // sub_16bit_hi -> GR32_BPSP_and_GR32_DIBP
10811 0, // sub_32bit
10812 0, // sub_mask_0
10813 0, // sub_mask_1
10814 0, // sub_t0
10815 0, // sub_t1
10816 0, // sub_xmm
10817 0, // sub_ymm
10818 },
10819 { // GR32_BPSP_and_GR32_TC
10820 67, // sub_8bit -> GR32_BPSP_and_GR32_TC
10821 0, // sub_8bit_hi
10822 67, // sub_8bit_hi_phony -> GR32_BPSP_and_GR32_TC
10823 67, // sub_16bit -> GR32_BPSP_and_GR32_TC
10824 67, // sub_16bit_hi -> GR32_BPSP_and_GR32_TC
10825 0, // sub_32bit
10826 0, // sub_mask_0
10827 0, // sub_mask_1
10828 0, // sub_t0
10829 0, // sub_t1
10830 0, // sub_xmm
10831 0, // sub_ymm
10832 },
10833 { // GR32_BSI_and_GR32_SIDI
10834 68, // sub_8bit -> GR32_BSI_and_GR32_SIDI
10835 0, // sub_8bit_hi
10836 68, // sub_8bit_hi_phony -> GR32_BSI_and_GR32_SIDI
10837 68, // sub_16bit -> GR32_BSI_and_GR32_SIDI
10838 68, // sub_16bit_hi -> GR32_BSI_and_GR32_SIDI
10839 0, // sub_32bit
10840 0, // sub_mask_0
10841 0, // sub_mask_1
10842 0, // sub_t0
10843 0, // sub_t1
10844 0, // sub_xmm
10845 0, // sub_ymm
10846 },
10847 { // GR32_DIBP_and_GR32_SIDI
10848 69, // sub_8bit -> GR32_DIBP_and_GR32_SIDI
10849 0, // sub_8bit_hi
10850 69, // sub_8bit_hi_phony -> GR32_DIBP_and_GR32_SIDI
10851 69, // sub_16bit -> GR32_DIBP_and_GR32_SIDI
10852 69, // sub_16bit_hi -> GR32_DIBP_and_GR32_SIDI
10853 0, // sub_32bit
10854 0, // sub_mask_0
10855 0, // sub_mask_1
10856 0, // sub_t0
10857 0, // sub_t1
10858 0, // sub_xmm
10859 0, // sub_ymm
10860 },
10861 { // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
10862 70, // sub_8bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
10863 0, // sub_8bit_hi
10864 70, // sub_8bit_hi_phony -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
10865 70, // sub_16bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
10866 70, // sub_16bit_hi -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
10867 70, // sub_32bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
10868 0, // sub_mask_0
10869 0, // sub_mask_1
10870 0, // sub_t0
10871 0, // sub_t1
10872 0, // sub_xmm
10873 0, // sub_ymm
10874 },
10875 { // LOW32_ADDR_ACCESS_with_sub_32bit
10876 0, // sub_8bit
10877 0, // sub_8bit_hi
10878 0, // sub_8bit_hi_phony
10879 71, // sub_16bit -> LOW32_ADDR_ACCESS_with_sub_32bit
10880 71, // sub_16bit_hi -> LOW32_ADDR_ACCESS_with_sub_32bit
10881 71, // sub_32bit -> LOW32_ADDR_ACCESS_with_sub_32bit
10882 0, // sub_mask_0
10883 0, // sub_mask_1
10884 0, // sub_t0
10885 0, // sub_t1
10886 0, // sub_xmm
10887 0, // sub_ymm
10888 },
10889 { // RFP64
10890 0, // sub_8bit
10891 0, // sub_8bit_hi
10892 0, // sub_8bit_hi_phony
10893 0, // sub_16bit
10894 0, // sub_16bit_hi
10895 0, // sub_32bit
10896 0, // sub_mask_0
10897 0, // sub_mask_1
10898 0, // sub_t0
10899 0, // sub_t1
10900 0, // sub_xmm
10901 0, // sub_ymm
10902 },
10903 { // GR64
10904 75, // sub_8bit -> GR64_with_sub_8bit
10905 104, // sub_8bit_hi -> GR64_ABCD
10906 0, // sub_8bit_hi_phony
10907 73, // sub_16bit -> GR64
10908 73, // sub_16bit_hi -> GR64
10909 73, // sub_32bit -> GR64
10910 0, // sub_mask_0
10911 0, // sub_mask_1
10912 0, // sub_t0
10913 0, // sub_t1
10914 0, // sub_xmm
10915 0, // sub_ymm
10916 },
10917 { // FR64X
10918 0, // sub_8bit
10919 0, // sub_8bit_hi
10920 0, // sub_8bit_hi_phony
10921 0, // sub_16bit
10922 0, // sub_16bit_hi
10923 0, // sub_32bit
10924 0, // sub_mask_0
10925 0, // sub_mask_1
10926 0, // sub_t0
10927 0, // sub_t1
10928 0, // sub_xmm
10929 0, // sub_ymm
10930 },
10931 { // GR64_with_sub_8bit
10932 75, // sub_8bit -> GR64_with_sub_8bit
10933 104, // sub_8bit_hi -> GR64_ABCD
10934 0, // sub_8bit_hi_phony
10935 75, // sub_16bit -> GR64_with_sub_8bit
10936 75, // sub_16bit_hi -> GR64_with_sub_8bit
10937 75, // sub_32bit -> GR64_with_sub_8bit
10938 0, // sub_mask_0
10939 0, // sub_mask_1
10940 0, // sub_t0
10941 0, // sub_t1
10942 0, // sub_xmm
10943 0, // sub_ymm
10944 },
10945 { // GR64_NOSP
10946 76, // sub_8bit -> GR64_NOSP
10947 104, // sub_8bit_hi -> GR64_ABCD
10948 0, // sub_8bit_hi_phony
10949 76, // sub_16bit -> GR64_NOSP
10950 76, // sub_16bit_hi -> GR64_NOSP
10951 76, // sub_32bit -> GR64_NOSP
10952 0, // sub_mask_0
10953 0, // sub_mask_1
10954 0, // sub_t0
10955 0, // sub_t1
10956 0, // sub_xmm
10957 0, // sub_ymm
10958 },
10959 { // GR64_NOREX2
10960 80, // sub_8bit -> GR64_with_sub_16bit_in_GR16_NOREX2
10961 104, // sub_8bit_hi -> GR64_ABCD
10962 0, // sub_8bit_hi_phony
10963 77, // sub_16bit -> GR64_NOREX2
10964 77, // sub_16bit_hi -> GR64_NOREX2
10965 77, // sub_32bit -> GR64_NOREX2
10966 0, // sub_mask_0
10967 0, // sub_mask_1
10968 0, // sub_t0
10969 0, // sub_t1
10970 0, // sub_xmm
10971 0, // sub_ymm
10972 },
10973 { // CONTROL_REG
10974 0, // sub_8bit
10975 0, // sub_8bit_hi
10976 0, // sub_8bit_hi_phony
10977 0, // sub_16bit
10978 0, // sub_16bit_hi
10979 0, // sub_32bit
10980 0, // sub_mask_0
10981 0, // sub_mask_1
10982 0, // sub_t0
10983 0, // sub_t1
10984 0, // sub_xmm
10985 0, // sub_ymm
10986 },
10987 { // FR64
10988 0, // sub_8bit
10989 0, // sub_8bit_hi
10990 0, // sub_8bit_hi_phony
10991 0, // sub_16bit
10992 0, // sub_16bit_hi
10993 0, // sub_32bit
10994 0, // sub_mask_0
10995 0, // sub_mask_1
10996 0, // sub_t0
10997 0, // sub_t1
10998 0, // sub_xmm
10999 0, // sub_ymm
11000 },
11001 { // GR64_with_sub_16bit_in_GR16_NOREX2
11002 80, // sub_8bit -> GR64_with_sub_16bit_in_GR16_NOREX2
11003 104, // sub_8bit_hi -> GR64_ABCD
11004 0, // sub_8bit_hi_phony
11005 80, // sub_16bit -> GR64_with_sub_16bit_in_GR16_NOREX2
11006 80, // sub_16bit_hi -> GR64_with_sub_16bit_in_GR16_NOREX2
11007 80, // sub_32bit -> GR64_with_sub_16bit_in_GR16_NOREX2
11008 0, // sub_mask_0
11009 0, // sub_mask_1
11010 0, // sub_t0
11011 0, // sub_t1
11012 0, // sub_xmm
11013 0, // sub_ymm
11014 },
11015 { // GR64_NOREX2_NOSP
11016 81, // sub_8bit -> GR64_NOREX2_NOSP
11017 104, // sub_8bit_hi -> GR64_ABCD
11018 0, // sub_8bit_hi_phony
11019 81, // sub_16bit -> GR64_NOREX2_NOSP
11020 81, // sub_16bit_hi -> GR64_NOREX2_NOSP
11021 81, // sub_32bit -> GR64_NOREX2_NOSP
11022 0, // sub_mask_0
11023 0, // sub_mask_1
11024 0, // sub_t0
11025 0, // sub_t1
11026 0, // sub_xmm
11027 0, // sub_ymm
11028 },
11029 { // GR64PLTSafe
11030 82, // sub_8bit -> GR64PLTSafe
11031 104, // sub_8bit_hi -> GR64_ABCD
11032 0, // sub_8bit_hi_phony
11033 82, // sub_16bit -> GR64PLTSafe
11034 82, // sub_16bit_hi -> GR64PLTSafe
11035 82, // sub_32bit -> GR64PLTSafe
11036 0, // sub_mask_0
11037 0, // sub_mask_1
11038 0, // sub_t0
11039 0, // sub_t1
11040 0, // sub_xmm
11041 0, // sub_ymm
11042 },
11043 { // GR64_TC
11044 86, // sub_8bit -> GR64_TC_with_sub_8bit
11045 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
11046 0, // sub_8bit_hi_phony
11047 83, // sub_16bit -> GR64_TC
11048 83, // sub_16bit_hi -> GR64_TC
11049 83, // sub_32bit -> GR64_TC
11050 0, // sub_mask_0
11051 0, // sub_mask_1
11052 0, // sub_t0
11053 0, // sub_t1
11054 0, // sub_xmm
11055 0, // sub_ymm
11056 },
11057 { // GR64_NOREX
11058 90, // sub_8bit -> GR64_with_sub_16bit_in_GR16_NOREX
11059 104, // sub_8bit_hi -> GR64_ABCD
11060 0, // sub_8bit_hi_phony
11061 84, // sub_16bit -> GR64_NOREX
11062 84, // sub_16bit_hi -> GR64_NOREX
11063 84, // sub_32bit -> GR64_NOREX
11064 0, // sub_mask_0
11065 0, // sub_mask_1
11066 0, // sub_t0
11067 0, // sub_t1
11068 0, // sub_xmm
11069 0, // sub_ymm
11070 },
11071 { // GR64_TCW64
11072 88, // sub_8bit -> GR64_TCW64_with_sub_8bit
11073 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
11074 0, // sub_8bit_hi_phony
11075 85, // sub_16bit -> GR64_TCW64
11076 85, // sub_16bit_hi -> GR64_TCW64
11077 85, // sub_32bit -> GR64_TCW64
11078 0, // sub_mask_0
11079 0, // sub_mask_1
11080 0, // sub_t0
11081 0, // sub_t1
11082 0, // sub_xmm
11083 0, // sub_ymm
11084 },
11085 { // GR64_TC_with_sub_8bit
11086 86, // sub_8bit -> GR64_TC_with_sub_8bit
11087 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
11088 0, // sub_8bit_hi_phony
11089 86, // sub_16bit -> GR64_TC_with_sub_8bit
11090 86, // sub_16bit_hi -> GR64_TC_with_sub_8bit
11091 86, // sub_32bit -> GR64_TC_with_sub_8bit
11092 0, // sub_mask_0
11093 0, // sub_mask_1
11094 0, // sub_t0
11095 0, // sub_t1
11096 0, // sub_xmm
11097 0, // sub_ymm
11098 },
11099 { // GR64_NOREX2_NOSP_and_GR64_TC
11100 87, // sub_8bit -> GR64_NOREX2_NOSP_and_GR64_TC
11101 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
11102 0, // sub_8bit_hi_phony
11103 87, // sub_16bit -> GR64_NOREX2_NOSP_and_GR64_TC
11104 87, // sub_16bit_hi -> GR64_NOREX2_NOSP_and_GR64_TC
11105 87, // sub_32bit -> GR64_NOREX2_NOSP_and_GR64_TC
11106 0, // sub_mask_0
11107 0, // sub_mask_1
11108 0, // sub_t0
11109 0, // sub_t1
11110 0, // sub_xmm
11111 0, // sub_ymm
11112 },
11113 { // GR64_TCW64_with_sub_8bit
11114 88, // sub_8bit -> GR64_TCW64_with_sub_8bit
11115 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
11116 0, // sub_8bit_hi_phony
11117 88, // sub_16bit -> GR64_TCW64_with_sub_8bit
11118 88, // sub_16bit_hi -> GR64_TCW64_with_sub_8bit
11119 88, // sub_32bit -> GR64_TCW64_with_sub_8bit
11120 0, // sub_mask_0
11121 0, // sub_mask_1
11122 0, // sub_t0
11123 0, // sub_t1
11124 0, // sub_xmm
11125 0, // sub_ymm
11126 },
11127 { // GR64_TC_and_GR64_TCW64
11128 97, // sub_8bit -> GR64_TCW64_and_GR64_TC_with_sub_8bit
11129 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
11130 0, // sub_8bit_hi_phony
11131 89, // sub_16bit -> GR64_TC_and_GR64_TCW64
11132 89, // sub_16bit_hi -> GR64_TC_and_GR64_TCW64
11133 89, // sub_32bit -> GR64_TC_and_GR64_TCW64
11134 0, // sub_mask_0
11135 0, // sub_mask_1
11136 0, // sub_t0
11137 0, // sub_t1
11138 0, // sub_xmm
11139 0, // sub_ymm
11140 },
11141 { // GR64_with_sub_16bit_in_GR16_NOREX
11142 90, // sub_8bit -> GR64_with_sub_16bit_in_GR16_NOREX
11143 104, // sub_8bit_hi -> GR64_ABCD
11144 0, // sub_8bit_hi_phony
11145 90, // sub_16bit -> GR64_with_sub_16bit_in_GR16_NOREX
11146 90, // sub_16bit_hi -> GR64_with_sub_16bit_in_GR16_NOREX
11147 90, // sub_32bit -> GR64_with_sub_16bit_in_GR16_NOREX
11148 0, // sub_mask_0
11149 0, // sub_mask_1
11150 0, // sub_t0
11151 0, // sub_t1
11152 0, // sub_xmm
11153 0, // sub_ymm
11154 },
11155 { // VK64
11156 0, // sub_8bit
11157 0, // sub_8bit_hi
11158 0, // sub_8bit_hi_phony
11159 0, // sub_16bit
11160 0, // sub_16bit_hi
11161 0, // sub_32bit
11162 0, // sub_mask_0
11163 0, // sub_mask_1
11164 0, // sub_t0
11165 0, // sub_t1
11166 0, // sub_xmm
11167 0, // sub_ymm
11168 },
11169 { // VR64
11170 0, // sub_8bit
11171 0, // sub_8bit_hi
11172 0, // sub_8bit_hi_phony
11173 0, // sub_16bit
11174 0, // sub_16bit_hi
11175 0, // sub_32bit
11176 0, // sub_mask_0
11177 0, // sub_mask_1
11178 0, // sub_t0
11179 0, // sub_t1
11180 0, // sub_xmm
11181 0, // sub_ymm
11182 },
11183 { // GR64PLTSafe_and_GR64_TC
11184 93, // sub_8bit -> GR64PLTSafe_and_GR64_TC
11185 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
11186 0, // sub_8bit_hi_phony
11187 93, // sub_16bit -> GR64PLTSafe_and_GR64_TC
11188 93, // sub_16bit_hi -> GR64PLTSafe_and_GR64_TC
11189 93, // sub_32bit -> GR64PLTSafe_and_GR64_TC
11190 0, // sub_mask_0
11191 0, // sub_mask_1
11192 0, // sub_t0
11193 0, // sub_t1
11194 0, // sub_xmm
11195 0, // sub_ymm
11196 },
11197 { // GR64_NOREX2_NOSP_and_GR64_TCW64
11198 94, // sub_8bit -> GR64_NOREX2_NOSP_and_GR64_TCW64
11199 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
11200 0, // sub_8bit_hi_phony
11201 94, // sub_16bit -> GR64_NOREX2_NOSP_and_GR64_TCW64
11202 94, // sub_16bit_hi -> GR64_NOREX2_NOSP_and_GR64_TCW64
11203 94, // sub_32bit -> GR64_NOREX2_NOSP_and_GR64_TCW64
11204 0, // sub_mask_0
11205 0, // sub_mask_1
11206 0, // sub_t0
11207 0, // sub_t1
11208 0, // sub_xmm
11209 0, // sub_ymm
11210 },
11211 { // GR64_NOREX_NOSP
11212 95, // sub_8bit -> GR64_NOREX_NOSP
11213 104, // sub_8bit_hi -> GR64_ABCD
11214 0, // sub_8bit_hi_phony
11215 95, // sub_16bit -> GR64_NOREX_NOSP
11216 95, // sub_16bit_hi -> GR64_NOREX_NOSP
11217 95, // sub_32bit -> GR64_NOREX_NOSP
11218 0, // sub_mask_0
11219 0, // sub_mask_1
11220 0, // sub_t0
11221 0, // sub_t1
11222 0, // sub_xmm
11223 0, // sub_ymm
11224 },
11225 { // GR64_NOREX_and_GR64_TC
11226 100, // sub_8bit -> GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
11227 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
11228 0, // sub_8bit_hi_phony
11229 96, // sub_16bit -> GR64_NOREX_and_GR64_TC
11230 96, // sub_16bit_hi -> GR64_NOREX_and_GR64_TC
11231 96, // sub_32bit -> GR64_NOREX_and_GR64_TC
11232 0, // sub_mask_0
11233 0, // sub_mask_1
11234 0, // sub_t0
11235 0, // sub_t1
11236 0, // sub_xmm
11237 0, // sub_ymm
11238 },
11239 { // GR64_TCW64_and_GR64_TC_with_sub_8bit
11240 97, // sub_8bit -> GR64_TCW64_and_GR64_TC_with_sub_8bit
11241 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
11242 0, // sub_8bit_hi_phony
11243 97, // sub_16bit -> GR64_TCW64_and_GR64_TC_with_sub_8bit
11244 97, // sub_16bit_hi -> GR64_TCW64_and_GR64_TC_with_sub_8bit
11245 97, // sub_32bit -> GR64_TCW64_and_GR64_TC_with_sub_8bit
11246 0, // sub_mask_0
11247 0, // sub_mask_1
11248 0, // sub_t0
11249 0, // sub_t1
11250 0, // sub_xmm
11251 0, // sub_ymm
11252 },
11253 { // VK64WM
11254 0, // sub_8bit
11255 0, // sub_8bit_hi
11256 0, // sub_8bit_hi_phony
11257 0, // sub_16bit
11258 0, // sub_16bit_hi
11259 0, // sub_32bit
11260 0, // sub_mask_0
11261 0, // sub_mask_1
11262 0, // sub_t0
11263 0, // sub_t1
11264 0, // sub_xmm
11265 0, // sub_ymm
11266 },
11267 { // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
11268 99, // sub_8bit -> GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
11269 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
11270 0, // sub_8bit_hi_phony
11271 99, // sub_16bit -> GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
11272 99, // sub_16bit_hi -> GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
11273 99, // sub_32bit -> GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
11274 0, // sub_mask_0
11275 0, // sub_mask_1
11276 0, // sub_t0
11277 0, // sub_t1
11278 0, // sub_xmm
11279 0, // sub_ymm
11280 },
11281 { // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
11282 100, // sub_8bit -> GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
11283 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
11284 0, // sub_8bit_hi_phony
11285 100, // sub_16bit -> GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
11286 100, // sub_16bit_hi -> GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
11287 100, // sub_32bit -> GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
11288 0, // sub_mask_0
11289 0, // sub_mask_1
11290 0, // sub_t0
11291 0, // sub_t1
11292 0, // sub_xmm
11293 0, // sub_ymm
11294 },
11295 { // GR64PLTSafe_and_GR64_TCW64
11296 101, // sub_8bit -> GR64PLTSafe_and_GR64_TCW64
11297 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
11298 0, // sub_8bit_hi_phony
11299 101, // sub_16bit -> GR64PLTSafe_and_GR64_TCW64
11300 101, // sub_16bit_hi -> GR64PLTSafe_and_GR64_TCW64
11301 101, // sub_32bit -> GR64PLTSafe_and_GR64_TCW64
11302 0, // sub_mask_0
11303 0, // sub_mask_1
11304 0, // sub_t0
11305 0, // sub_t1
11306 0, // sub_xmm
11307 0, // sub_ymm
11308 },
11309 { // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
11310 102, // sub_8bit -> GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
11311 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
11312 0, // sub_8bit_hi_phony
11313 102, // sub_16bit -> GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
11314 102, // sub_16bit_hi -> GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
11315 102, // sub_32bit -> GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
11316 0, // sub_mask_0
11317 0, // sub_mask_1
11318 0, // sub_t0
11319 0, // sub_t1
11320 0, // sub_xmm
11321 0, // sub_ymm
11322 },
11323 { // GR64_NOREX_and_GR64_TCW64
11324 105, // sub_8bit -> GR64_with_sub_32bit_in_GR32_TC
11325 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
11326 0, // sub_8bit_hi_phony
11327 103, // sub_16bit -> GR64_NOREX_and_GR64_TCW64
11328 103, // sub_16bit_hi -> GR64_NOREX_and_GR64_TCW64
11329 103, // sub_32bit -> GR64_NOREX_and_GR64_TCW64
11330 0, // sub_mask_0
11331 0, // sub_mask_1
11332 0, // sub_t0
11333 0, // sub_t1
11334 0, // sub_xmm
11335 0, // sub_ymm
11336 },
11337 { // GR64_ABCD
11338 104, // sub_8bit -> GR64_ABCD
11339 104, // sub_8bit_hi -> GR64_ABCD
11340 0, // sub_8bit_hi_phony
11341 104, // sub_16bit -> GR64_ABCD
11342 104, // sub_16bit_hi -> GR64_ABCD
11343 104, // sub_32bit -> GR64_ABCD
11344 0, // sub_mask_0
11345 0, // sub_mask_1
11346 0, // sub_t0
11347 0, // sub_t1
11348 0, // sub_xmm
11349 0, // sub_ymm
11350 },
11351 { // GR64_with_sub_32bit_in_GR32_TC
11352 105, // sub_8bit -> GR64_with_sub_32bit_in_GR32_TC
11353 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
11354 0, // sub_8bit_hi_phony
11355 105, // sub_16bit -> GR64_with_sub_32bit_in_GR32_TC
11356 105, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_TC
11357 105, // sub_32bit -> GR64_with_sub_32bit_in_GR32_TC
11358 0, // sub_mask_0
11359 0, // sub_mask_1
11360 0, // sub_t0
11361 0, // sub_t1
11362 0, // sub_xmm
11363 0, // sub_ymm
11364 },
11365 { // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
11366 106, // sub_8bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
11367 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
11368 0, // sub_8bit_hi_phony
11369 106, // sub_16bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
11370 106, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
11371 106, // sub_32bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
11372 0, // sub_mask_0
11373 0, // sub_mask_1
11374 0, // sub_t0
11375 0, // sub_t1
11376 0, // sub_xmm
11377 0, // sub_ymm
11378 },
11379 { // GR64_AD
11380 107, // sub_8bit -> GR64_AD
11381 107, // sub_8bit_hi -> GR64_AD
11382 0, // sub_8bit_hi_phony
11383 107, // sub_16bit -> GR64_AD
11384 107, // sub_16bit_hi -> GR64_AD
11385 107, // sub_32bit -> GR64_AD
11386 0, // sub_mask_0
11387 0, // sub_mask_1
11388 0, // sub_t0
11389 0, // sub_t1
11390 0, // sub_xmm
11391 0, // sub_ymm
11392 },
11393 { // GR64_ArgRef
11394 108, // sub_8bit -> GR64_ArgRef
11395 0, // sub_8bit_hi
11396 108, // sub_8bit_hi_phony -> GR64_ArgRef
11397 108, // sub_16bit -> GR64_ArgRef
11398 108, // sub_16bit_hi -> GR64_ArgRef
11399 108, // sub_32bit -> GR64_ArgRef
11400 0, // sub_mask_0
11401 0, // sub_mask_1
11402 0, // sub_t0
11403 0, // sub_t1
11404 0, // sub_xmm
11405 0, // sub_ymm
11406 },
11407 { // GR64_and_LOW32_ADDR_ACCESS_RBP
11408 122, // sub_8bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
11409 0, // sub_8bit_hi
11410 0, // sub_8bit_hi_phony
11411 109, // sub_16bit -> GR64_and_LOW32_ADDR_ACCESS_RBP
11412 109, // sub_16bit_hi -> GR64_and_LOW32_ADDR_ACCESS_RBP
11413 109, // sub_32bit -> GR64_and_LOW32_ADDR_ACCESS_RBP
11414 0, // sub_mask_0
11415 0, // sub_mask_1
11416 0, // sub_t0
11417 0, // sub_t1
11418 0, // sub_xmm
11419 0, // sub_ymm
11420 },
11421 { // GR64_with_sub_32bit_in_GR32_ArgRef
11422 110, // sub_8bit -> GR64_with_sub_32bit_in_GR32_ArgRef
11423 110, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ArgRef
11424 0, // sub_8bit_hi_phony
11425 110, // sub_16bit -> GR64_with_sub_32bit_in_GR32_ArgRef
11426 110, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_ArgRef
11427 110, // sub_32bit -> GR64_with_sub_32bit_in_GR32_ArgRef
11428 0, // sub_mask_0
11429 0, // sub_mask_1
11430 0, // sub_t0
11431 0, // sub_t1
11432 0, // sub_xmm
11433 0, // sub_ymm
11434 },
11435 { // GR64_with_sub_32bit_in_GR32_BPSP
11436 111, // sub_8bit -> GR64_with_sub_32bit_in_GR32_BPSP
11437 0, // sub_8bit_hi
11438 111, // sub_8bit_hi_phony -> GR64_with_sub_32bit_in_GR32_BPSP
11439 111, // sub_16bit -> GR64_with_sub_32bit_in_GR32_BPSP
11440 111, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_BPSP
11441 111, // sub_32bit -> GR64_with_sub_32bit_in_GR32_BPSP
11442 0, // sub_mask_0
11443 0, // sub_mask_1
11444 0, // sub_t0
11445 0, // sub_t1
11446 0, // sub_xmm
11447 0, // sub_ymm
11448 },
11449 { // GR64_with_sub_32bit_in_GR32_BSI
11450 112, // sub_8bit -> GR64_with_sub_32bit_in_GR32_BSI
11451 119, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
11452 0, // sub_8bit_hi_phony
11453 112, // sub_16bit -> GR64_with_sub_32bit_in_GR32_BSI
11454 112, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_BSI
11455 112, // sub_32bit -> GR64_with_sub_32bit_in_GR32_BSI
11456 0, // sub_mask_0
11457 0, // sub_mask_1
11458 0, // sub_t0
11459 0, // sub_t1
11460 0, // sub_xmm
11461 0, // sub_ymm
11462 },
11463 { // GR64_with_sub_32bit_in_GR32_CB
11464 113, // sub_8bit -> GR64_with_sub_32bit_in_GR32_CB
11465 113, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_CB
11466 0, // sub_8bit_hi_phony
11467 113, // sub_16bit -> GR64_with_sub_32bit_in_GR32_CB
11468 113, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_CB
11469 113, // sub_32bit -> GR64_with_sub_32bit_in_GR32_CB
11470 0, // sub_mask_0
11471 0, // sub_mask_1
11472 0, // sub_t0
11473 0, // sub_t1
11474 0, // sub_xmm
11475 0, // sub_ymm
11476 },
11477 { // GR64_with_sub_32bit_in_GR32_DIBP
11478 114, // sub_8bit -> GR64_with_sub_32bit_in_GR32_DIBP
11479 0, // sub_8bit_hi
11480 114, // sub_8bit_hi_phony -> GR64_with_sub_32bit_in_GR32_DIBP
11481 114, // sub_16bit -> GR64_with_sub_32bit_in_GR32_DIBP
11482 114, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_DIBP
11483 114, // sub_32bit -> GR64_with_sub_32bit_in_GR32_DIBP
11484 0, // sub_mask_0
11485 0, // sub_mask_1
11486 0, // sub_t0
11487 0, // sub_t1
11488 0, // sub_xmm
11489 0, // sub_ymm
11490 },
11491 { // GR64_with_sub_32bit_in_GR32_SIDI
11492 115, // sub_8bit -> GR64_with_sub_32bit_in_GR32_SIDI
11493 0, // sub_8bit_hi
11494 115, // sub_8bit_hi_phony -> GR64_with_sub_32bit_in_GR32_SIDI
11495 115, // sub_16bit -> GR64_with_sub_32bit_in_GR32_SIDI
11496 115, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_SIDI
11497 115, // sub_32bit -> GR64_with_sub_32bit_in_GR32_SIDI
11498 0, // sub_mask_0
11499 0, // sub_mask_1
11500 0, // sub_t0
11501 0, // sub_t1
11502 0, // sub_xmm
11503 0, // sub_ymm
11504 },
11505 { // GR64_A
11506 116, // sub_8bit -> GR64_A
11507 116, // sub_8bit_hi -> GR64_A
11508 0, // sub_8bit_hi_phony
11509 116, // sub_16bit -> GR64_A
11510 116, // sub_16bit_hi -> GR64_A
11511 116, // sub_32bit -> GR64_A
11512 0, // sub_mask_0
11513 0, // sub_mask_1
11514 0, // sub_t0
11515 0, // sub_t1
11516 0, // sub_xmm
11517 0, // sub_ymm
11518 },
11519 { // GR64_ArgRef_and_GR64_TC
11520 117, // sub_8bit -> GR64_ArgRef_and_GR64_TC
11521 0, // sub_8bit_hi
11522 117, // sub_8bit_hi_phony -> GR64_ArgRef_and_GR64_TC
11523 117, // sub_16bit -> GR64_ArgRef_and_GR64_TC
11524 117, // sub_16bit_hi -> GR64_ArgRef_and_GR64_TC
11525 117, // sub_32bit -> GR64_ArgRef_and_GR64_TC
11526 0, // sub_mask_0
11527 0, // sub_mask_1
11528 0, // sub_t0
11529 0, // sub_t1
11530 0, // sub_xmm
11531 0, // sub_ymm
11532 },
11533 { // GR64_and_LOW32_ADDR_ACCESS
11534 0, // sub_8bit
11535 0, // sub_8bit_hi
11536 0, // sub_8bit_hi_phony
11537 118, // sub_16bit -> GR64_and_LOW32_ADDR_ACCESS
11538 118, // sub_16bit_hi -> GR64_and_LOW32_ADDR_ACCESS
11539 118, // sub_32bit -> GR64_and_LOW32_ADDR_ACCESS
11540 0, // sub_mask_0
11541 0, // sub_mask_1
11542 0, // sub_t0
11543 0, // sub_t1
11544 0, // sub_xmm
11545 0, // sub_ymm
11546 },
11547 { // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
11548 119, // sub_8bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
11549 119, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
11550 0, // sub_8bit_hi_phony
11551 119, // sub_16bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
11552 119, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
11553 119, // sub_32bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
11554 0, // sub_mask_0
11555 0, // sub_mask_1
11556 0, // sub_t0
11557 0, // sub_t1
11558 0, // sub_xmm
11559 0, // sub_ymm
11560 },
11561 { // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
11562 120, // sub_8bit -> GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
11563 120, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
11564 0, // sub_8bit_hi_phony
11565 120, // sub_16bit -> GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
11566 120, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
11567 120, // sub_32bit -> GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
11568 0, // sub_mask_0
11569 0, // sub_mask_1
11570 0, // sub_t0
11571 0, // sub_t1
11572 0, // sub_xmm
11573 0, // sub_ymm
11574 },
11575 { // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
11576 121, // sub_8bit -> GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
11577 121, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
11578 0, // sub_8bit_hi_phony
11579 121, // sub_16bit -> GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
11580 121, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
11581 121, // sub_32bit -> GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
11582 0, // sub_mask_0
11583 0, // sub_mask_1
11584 0, // sub_t0
11585 0, // sub_t1
11586 0, // sub_xmm
11587 0, // sub_ymm
11588 },
11589 { // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
11590 122, // sub_8bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
11591 0, // sub_8bit_hi
11592 122, // sub_8bit_hi_phony -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
11593 122, // sub_16bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
11594 122, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
11595 122, // sub_32bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
11596 0, // sub_mask_0
11597 0, // sub_mask_1
11598 0, // sub_t0
11599 0, // sub_t1
11600 0, // sub_xmm
11601 0, // sub_ymm
11602 },
11603 { // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
11604 123, // sub_8bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
11605 0, // sub_8bit_hi
11606 123, // sub_8bit_hi_phony -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
11607 123, // sub_16bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
11608 123, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
11609 123, // sub_32bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
11610 0, // sub_mask_0
11611 0, // sub_mask_1
11612 0, // sub_t0
11613 0, // sub_t1
11614 0, // sub_xmm
11615 0, // sub_ymm
11616 },
11617 { // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
11618 124, // sub_8bit -> GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
11619 0, // sub_8bit_hi
11620 124, // sub_8bit_hi_phony -> GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
11621 124, // sub_16bit -> GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
11622 124, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
11623 124, // sub_32bit -> GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
11624 0, // sub_mask_0
11625 0, // sub_mask_1
11626 0, // sub_t0
11627 0, // sub_t1
11628 0, // sub_xmm
11629 0, // sub_ymm
11630 },
11631 { // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
11632 125, // sub_8bit -> GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
11633 0, // sub_8bit_hi
11634 125, // sub_8bit_hi_phony -> GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
11635 125, // sub_16bit -> GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
11636 125, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
11637 125, // sub_32bit -> GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
11638 0, // sub_mask_0
11639 0, // sub_mask_1
11640 0, // sub_t0
11641 0, // sub_t1
11642 0, // sub_xmm
11643 0, // sub_ymm
11644 },
11645 { // RST
11646 0, // sub_8bit
11647 0, // sub_8bit_hi
11648 0, // sub_8bit_hi_phony
11649 0, // sub_16bit
11650 0, // sub_16bit_hi
11651 0, // sub_32bit
11652 0, // sub_mask_0
11653 0, // sub_mask_1
11654 0, // sub_t0
11655 0, // sub_t1
11656 0, // sub_xmm
11657 0, // sub_ymm
11658 },
11659 { // RFP80
11660 0, // sub_8bit
11661 0, // sub_8bit_hi
11662 0, // sub_8bit_hi_phony
11663 0, // sub_16bit
11664 0, // sub_16bit_hi
11665 0, // sub_32bit
11666 0, // sub_mask_0
11667 0, // sub_mask_1
11668 0, // sub_t0
11669 0, // sub_t1
11670 0, // sub_xmm
11671 0, // sub_ymm
11672 },
11673 { // RFP80_7
11674 0, // sub_8bit
11675 0, // sub_8bit_hi
11676 0, // sub_8bit_hi_phony
11677 0, // sub_16bit
11678 0, // sub_16bit_hi
11679 0, // sub_32bit
11680 0, // sub_mask_0
11681 0, // sub_mask_1
11682 0, // sub_t0
11683 0, // sub_t1
11684 0, // sub_xmm
11685 0, // sub_ymm
11686 },
11687 { // VR128X
11688 0, // sub_8bit
11689 0, // sub_8bit_hi
11690 0, // sub_8bit_hi_phony
11691 0, // sub_16bit
11692 0, // sub_16bit_hi
11693 0, // sub_32bit
11694 0, // sub_mask_0
11695 0, // sub_mask_1
11696 0, // sub_t0
11697 0, // sub_t1
11698 0, // sub_xmm
11699 0, // sub_ymm
11700 },
11701 { // VR128
11702 0, // sub_8bit
11703 0, // sub_8bit_hi
11704 0, // sub_8bit_hi_phony
11705 0, // sub_16bit
11706 0, // sub_16bit_hi
11707 0, // sub_32bit
11708 0, // sub_mask_0
11709 0, // sub_mask_1
11710 0, // sub_t0
11711 0, // sub_t1
11712 0, // sub_xmm
11713 0, // sub_ymm
11714 },
11715 { // VR256X
11716 0, // sub_8bit
11717 0, // sub_8bit_hi
11718 0, // sub_8bit_hi_phony
11719 0, // sub_16bit
11720 0, // sub_16bit_hi
11721 0, // sub_32bit
11722 0, // sub_mask_0
11723 0, // sub_mask_1
11724 0, // sub_t0
11725 0, // sub_t1
11726 131, // sub_xmm -> VR256X
11727 0, // sub_ymm
11728 },
11729 { // VR256
11730 0, // sub_8bit
11731 0, // sub_8bit_hi
11732 0, // sub_8bit_hi_phony
11733 0, // sub_16bit
11734 0, // sub_16bit_hi
11735 0, // sub_32bit
11736 0, // sub_mask_0
11737 0, // sub_mask_1
11738 0, // sub_t0
11739 0, // sub_t1
11740 132, // sub_xmm -> VR256
11741 0, // sub_ymm
11742 },
11743 { // VR512
11744 0, // sub_8bit
11745 0, // sub_8bit_hi
11746 0, // sub_8bit_hi_phony
11747 0, // sub_16bit
11748 0, // sub_16bit_hi
11749 0, // sub_32bit
11750 0, // sub_mask_0
11751 0, // sub_mask_1
11752 0, // sub_t0
11753 0, // sub_t1
11754 133, // sub_xmm -> VR512
11755 133, // sub_ymm -> VR512
11756 },
11757 { // VR512_0_15
11758 0, // sub_8bit
11759 0, // sub_8bit_hi
11760 0, // sub_8bit_hi_phony
11761 0, // sub_16bit
11762 0, // sub_16bit_hi
11763 0, // sub_32bit
11764 0, // sub_mask_0
11765 0, // sub_mask_1
11766 0, // sub_t0
11767 0, // sub_t1
11768 134, // sub_xmm -> VR512_0_15
11769 134, // sub_ymm -> VR512_0_15
11770 },
11771 { // TILE
11772 0, // sub_8bit
11773 0, // sub_8bit_hi
11774 0, // sub_8bit_hi_phony
11775 0, // sub_16bit
11776 0, // sub_16bit_hi
11777 0, // sub_32bit
11778 0, // sub_mask_0
11779 0, // sub_mask_1
11780 0, // sub_t0
11781 0, // sub_t1
11782 0, // sub_xmm
11783 0, // sub_ymm
11784 },
11785 { // TILEPAIR
11786 0, // sub_8bit
11787 0, // sub_8bit_hi
11788 0, // sub_8bit_hi_phony
11789 0, // sub_16bit
11790 0, // sub_16bit_hi
11791 0, // sub_32bit
11792 0, // sub_mask_0
11793 0, // sub_mask_1
11794 136, // sub_t0 -> TILEPAIR
11795 136, // sub_t1 -> TILEPAIR
11796 0, // sub_xmm
11797 0, // sub_ymm
11798 },
11799 };
11800 assert(RC && "Missing regclass");
11801 if (!Idx) return RC;
11802 --Idx;
11803 assert(Idx < 12 && "Bad subreg");
11804 unsigned TV = Table[RC->getID()][Idx];
11805 return TV ? getRegClass(TV - 1) : nullptr;
11806}
11807
11808const TargetRegisterClass *X86GenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
11809 static const uint8_t Table[136][12] = {
11810 { // GR8
11811 0, // GR8:sub_8bit
11812 0, // GR8:sub_8bit_hi
11813 0, // GR8:sub_8bit_hi_phony
11814 0, // GR8:sub_16bit
11815 0, // GR8:sub_16bit_hi
11816 0, // GR8:sub_32bit
11817 0, // GR8:sub_mask_0
11818 0, // GR8:sub_mask_1
11819 0, // GR8:sub_t0
11820 0, // GR8:sub_t1
11821 0, // GR8:sub_xmm
11822 0, // GR8:sub_ymm
11823 },
11824 { // GRH8
11825 0, // GRH8:sub_8bit
11826 0, // GRH8:sub_8bit_hi
11827 0, // GRH8:sub_8bit_hi_phony
11828 0, // GRH8:sub_16bit
11829 0, // GRH8:sub_16bit_hi
11830 0, // GRH8:sub_32bit
11831 0, // GRH8:sub_mask_0
11832 0, // GRH8:sub_mask_1
11833 0, // GRH8:sub_t0
11834 0, // GRH8:sub_t1
11835 0, // GRH8:sub_xmm
11836 0, // GRH8:sub_ymm
11837 },
11838 { // GR8_NOREX2
11839 0, // GR8_NOREX2:sub_8bit
11840 0, // GR8_NOREX2:sub_8bit_hi
11841 0, // GR8_NOREX2:sub_8bit_hi_phony
11842 0, // GR8_NOREX2:sub_16bit
11843 0, // GR8_NOREX2:sub_16bit_hi
11844 0, // GR8_NOREX2:sub_32bit
11845 0, // GR8_NOREX2:sub_mask_0
11846 0, // GR8_NOREX2:sub_mask_1
11847 0, // GR8_NOREX2:sub_t0
11848 0, // GR8_NOREX2:sub_t1
11849 0, // GR8_NOREX2:sub_xmm
11850 0, // GR8_NOREX2:sub_ymm
11851 },
11852 { // GR8_NOREX
11853 0, // GR8_NOREX:sub_8bit
11854 0, // GR8_NOREX:sub_8bit_hi
11855 0, // GR8_NOREX:sub_8bit_hi_phony
11856 0, // GR8_NOREX:sub_16bit
11857 0, // GR8_NOREX:sub_16bit_hi
11858 0, // GR8_NOREX:sub_32bit
11859 0, // GR8_NOREX:sub_mask_0
11860 0, // GR8_NOREX:sub_mask_1
11861 0, // GR8_NOREX:sub_t0
11862 0, // GR8_NOREX:sub_t1
11863 0, // GR8_NOREX:sub_xmm
11864 0, // GR8_NOREX:sub_ymm
11865 },
11866 { // GR8_ABCD_H
11867 0, // GR8_ABCD_H:sub_8bit
11868 0, // GR8_ABCD_H:sub_8bit_hi
11869 0, // GR8_ABCD_H:sub_8bit_hi_phony
11870 0, // GR8_ABCD_H:sub_16bit
11871 0, // GR8_ABCD_H:sub_16bit_hi
11872 0, // GR8_ABCD_H:sub_32bit
11873 0, // GR8_ABCD_H:sub_mask_0
11874 0, // GR8_ABCD_H:sub_mask_1
11875 0, // GR8_ABCD_H:sub_t0
11876 0, // GR8_ABCD_H:sub_t1
11877 0, // GR8_ABCD_H:sub_xmm
11878 0, // GR8_ABCD_H:sub_ymm
11879 },
11880 { // GR8_ABCD_L
11881 0, // GR8_ABCD_L:sub_8bit
11882 0, // GR8_ABCD_L:sub_8bit_hi
11883 0, // GR8_ABCD_L:sub_8bit_hi_phony
11884 0, // GR8_ABCD_L:sub_16bit
11885 0, // GR8_ABCD_L:sub_16bit_hi
11886 0, // GR8_ABCD_L:sub_32bit
11887 0, // GR8_ABCD_L:sub_mask_0
11888 0, // GR8_ABCD_L:sub_mask_1
11889 0, // GR8_ABCD_L:sub_t0
11890 0, // GR8_ABCD_L:sub_t1
11891 0, // GR8_ABCD_L:sub_xmm
11892 0, // GR8_ABCD_L:sub_ymm
11893 },
11894 { // GRH16
11895 0, // GRH16:sub_8bit
11896 0, // GRH16:sub_8bit_hi
11897 0, // GRH16:sub_8bit_hi_phony
11898 0, // GRH16:sub_16bit
11899 0, // GRH16:sub_16bit_hi
11900 0, // GRH16:sub_32bit
11901 0, // GRH16:sub_mask_0
11902 0, // GRH16:sub_mask_1
11903 0, // GRH16:sub_t0
11904 0, // GRH16:sub_t1
11905 0, // GRH16:sub_xmm
11906 0, // GRH16:sub_ymm
11907 },
11908 { // GR16
11909 1, // GR16:sub_8bit -> GR8
11910 5, // GR16:sub_8bit_hi -> GR8_ABCD_H
11911 0, // GR16:sub_8bit_hi_phony
11912 0, // GR16:sub_16bit
11913 0, // GR16:sub_16bit_hi
11914 0, // GR16:sub_32bit
11915 0, // GR16:sub_mask_0
11916 0, // GR16:sub_mask_1
11917 0, // GR16:sub_t0
11918 0, // GR16:sub_t1
11919 0, // GR16:sub_xmm
11920 0, // GR16:sub_ymm
11921 },
11922 { // GR16_NOREX2
11923 3, // GR16_NOREX2:sub_8bit -> GR8_NOREX2
11924 5, // GR16_NOREX2:sub_8bit_hi -> GR8_ABCD_H
11925 0, // GR16_NOREX2:sub_8bit_hi_phony
11926 0, // GR16_NOREX2:sub_16bit
11927 0, // GR16_NOREX2:sub_16bit_hi
11928 0, // GR16_NOREX2:sub_32bit
11929 0, // GR16_NOREX2:sub_mask_0
11930 0, // GR16_NOREX2:sub_mask_1
11931 0, // GR16_NOREX2:sub_t0
11932 0, // GR16_NOREX2:sub_t1
11933 0, // GR16_NOREX2:sub_xmm
11934 0, // GR16_NOREX2:sub_ymm
11935 },
11936 { // GR16_NOREX
11937 3, // GR16_NOREX:sub_8bit -> GR8_NOREX2
11938 5, // GR16_NOREX:sub_8bit_hi -> GR8_ABCD_H
11939 0, // GR16_NOREX:sub_8bit_hi_phony
11940 0, // GR16_NOREX:sub_16bit
11941 0, // GR16_NOREX:sub_16bit_hi
11942 0, // GR16_NOREX:sub_32bit
11943 0, // GR16_NOREX:sub_mask_0
11944 0, // GR16_NOREX:sub_mask_1
11945 0, // GR16_NOREX:sub_t0
11946 0, // GR16_NOREX:sub_t1
11947 0, // GR16_NOREX:sub_xmm
11948 0, // GR16_NOREX:sub_ymm
11949 },
11950 { // VK1
11951 0, // VK1:sub_8bit
11952 0, // VK1:sub_8bit_hi
11953 0, // VK1:sub_8bit_hi_phony
11954 0, // VK1:sub_16bit
11955 0, // VK1:sub_16bit_hi
11956 0, // VK1:sub_32bit
11957 0, // VK1:sub_mask_0
11958 0, // VK1:sub_mask_1
11959 0, // VK1:sub_t0
11960 0, // VK1:sub_t1
11961 0, // VK1:sub_xmm
11962 0, // VK1:sub_ymm
11963 },
11964 { // VK16
11965 0, // VK16:sub_8bit
11966 0, // VK16:sub_8bit_hi
11967 0, // VK16:sub_8bit_hi_phony
11968 0, // VK16:sub_16bit
11969 0, // VK16:sub_16bit_hi
11970 0, // VK16:sub_32bit
11971 0, // VK16:sub_mask_0
11972 0, // VK16:sub_mask_1
11973 0, // VK16:sub_t0
11974 0, // VK16:sub_t1
11975 0, // VK16:sub_xmm
11976 0, // VK16:sub_ymm
11977 },
11978 { // VK2
11979 0, // VK2:sub_8bit
11980 0, // VK2:sub_8bit_hi
11981 0, // VK2:sub_8bit_hi_phony
11982 0, // VK2:sub_16bit
11983 0, // VK2:sub_16bit_hi
11984 0, // VK2:sub_32bit
11985 0, // VK2:sub_mask_0
11986 0, // VK2:sub_mask_1
11987 0, // VK2:sub_t0
11988 0, // VK2:sub_t1
11989 0, // VK2:sub_xmm
11990 0, // VK2:sub_ymm
11991 },
11992 { // VK4
11993 0, // VK4:sub_8bit
11994 0, // VK4:sub_8bit_hi
11995 0, // VK4:sub_8bit_hi_phony
11996 0, // VK4:sub_16bit
11997 0, // VK4:sub_16bit_hi
11998 0, // VK4:sub_32bit
11999 0, // VK4:sub_mask_0
12000 0, // VK4:sub_mask_1
12001 0, // VK4:sub_t0
12002 0, // VK4:sub_t1
12003 0, // VK4:sub_xmm
12004 0, // VK4:sub_ymm
12005 },
12006 { // VK8
12007 0, // VK8:sub_8bit
12008 0, // VK8:sub_8bit_hi
12009 0, // VK8:sub_8bit_hi_phony
12010 0, // VK8:sub_16bit
12011 0, // VK8:sub_16bit_hi
12012 0, // VK8:sub_32bit
12013 0, // VK8:sub_mask_0
12014 0, // VK8:sub_mask_1
12015 0, // VK8:sub_t0
12016 0, // VK8:sub_t1
12017 0, // VK8:sub_xmm
12018 0, // VK8:sub_ymm
12019 },
12020 { // VK16WM
12021 0, // VK16WM:sub_8bit
12022 0, // VK16WM:sub_8bit_hi
12023 0, // VK16WM:sub_8bit_hi_phony
12024 0, // VK16WM:sub_16bit
12025 0, // VK16WM:sub_16bit_hi
12026 0, // VK16WM:sub_32bit
12027 0, // VK16WM:sub_mask_0
12028 0, // VK16WM:sub_mask_1
12029 0, // VK16WM:sub_t0
12030 0, // VK16WM:sub_t1
12031 0, // VK16WM:sub_xmm
12032 0, // VK16WM:sub_ymm
12033 },
12034 { // VK1WM
12035 0, // VK1WM:sub_8bit
12036 0, // VK1WM:sub_8bit_hi
12037 0, // VK1WM:sub_8bit_hi_phony
12038 0, // VK1WM:sub_16bit
12039 0, // VK1WM:sub_16bit_hi
12040 0, // VK1WM:sub_32bit
12041 0, // VK1WM:sub_mask_0
12042 0, // VK1WM:sub_mask_1
12043 0, // VK1WM:sub_t0
12044 0, // VK1WM:sub_t1
12045 0, // VK1WM:sub_xmm
12046 0, // VK1WM:sub_ymm
12047 },
12048 { // VK2WM
12049 0, // VK2WM:sub_8bit
12050 0, // VK2WM:sub_8bit_hi
12051 0, // VK2WM:sub_8bit_hi_phony
12052 0, // VK2WM:sub_16bit
12053 0, // VK2WM:sub_16bit_hi
12054 0, // VK2WM:sub_32bit
12055 0, // VK2WM:sub_mask_0
12056 0, // VK2WM:sub_mask_1
12057 0, // VK2WM:sub_t0
12058 0, // VK2WM:sub_t1
12059 0, // VK2WM:sub_xmm
12060 0, // VK2WM:sub_ymm
12061 },
12062 { // VK4WM
12063 0, // VK4WM:sub_8bit
12064 0, // VK4WM:sub_8bit_hi
12065 0, // VK4WM:sub_8bit_hi_phony
12066 0, // VK4WM:sub_16bit
12067 0, // VK4WM:sub_16bit_hi
12068 0, // VK4WM:sub_32bit
12069 0, // VK4WM:sub_mask_0
12070 0, // VK4WM:sub_mask_1
12071 0, // VK4WM:sub_t0
12072 0, // VK4WM:sub_t1
12073 0, // VK4WM:sub_xmm
12074 0, // VK4WM:sub_ymm
12075 },
12076 { // VK8WM
12077 0, // VK8WM:sub_8bit
12078 0, // VK8WM:sub_8bit_hi
12079 0, // VK8WM:sub_8bit_hi_phony
12080 0, // VK8WM:sub_16bit
12081 0, // VK8WM:sub_16bit_hi
12082 0, // VK8WM:sub_32bit
12083 0, // VK8WM:sub_mask_0
12084 0, // VK8WM:sub_mask_1
12085 0, // VK8WM:sub_t0
12086 0, // VK8WM:sub_t1
12087 0, // VK8WM:sub_xmm
12088 0, // VK8WM:sub_ymm
12089 },
12090 { // SEGMENT_REG
12091 0, // SEGMENT_REG:sub_8bit
12092 0, // SEGMENT_REG:sub_8bit_hi
12093 0, // SEGMENT_REG:sub_8bit_hi_phony
12094 0, // SEGMENT_REG:sub_16bit
12095 0, // SEGMENT_REG:sub_16bit_hi
12096 0, // SEGMENT_REG:sub_32bit
12097 0, // SEGMENT_REG:sub_mask_0
12098 0, // SEGMENT_REG:sub_mask_1
12099 0, // SEGMENT_REG:sub_t0
12100 0, // SEGMENT_REG:sub_t1
12101 0, // SEGMENT_REG:sub_xmm
12102 0, // SEGMENT_REG:sub_ymm
12103 },
12104 { // GR16_ABCD
12105 6, // GR16_ABCD:sub_8bit -> GR8_ABCD_L
12106 5, // GR16_ABCD:sub_8bit_hi -> GR8_ABCD_H
12107 0, // GR16_ABCD:sub_8bit_hi_phony
12108 0, // GR16_ABCD:sub_16bit
12109 0, // GR16_ABCD:sub_16bit_hi
12110 0, // GR16_ABCD:sub_32bit
12111 0, // GR16_ABCD:sub_mask_0
12112 0, // GR16_ABCD:sub_mask_1
12113 0, // GR16_ABCD:sub_t0
12114 0, // GR16_ABCD:sub_t1
12115 0, // GR16_ABCD:sub_xmm
12116 0, // GR16_ABCD:sub_ymm
12117 },
12118 { // FPCCR
12119 0, // FPCCR:sub_8bit
12120 0, // FPCCR:sub_8bit_hi
12121 0, // FPCCR:sub_8bit_hi_phony
12122 0, // FPCCR:sub_16bit
12123 0, // FPCCR:sub_16bit_hi
12124 0, // FPCCR:sub_32bit
12125 0, // FPCCR:sub_mask_0
12126 0, // FPCCR:sub_mask_1
12127 0, // FPCCR:sub_t0
12128 0, // FPCCR:sub_t1
12129 0, // FPCCR:sub_xmm
12130 0, // FPCCR:sub_ymm
12131 },
12132 { // FR16X
12133 0, // FR16X:sub_8bit
12134 0, // FR16X:sub_8bit_hi
12135 0, // FR16X:sub_8bit_hi_phony
12136 0, // FR16X:sub_16bit
12137 0, // FR16X:sub_16bit_hi
12138 0, // FR16X:sub_32bit
12139 0, // FR16X:sub_mask_0
12140 0, // FR16X:sub_mask_1
12141 0, // FR16X:sub_t0
12142 0, // FR16X:sub_t1
12143 0, // FR16X:sub_xmm
12144 0, // FR16X:sub_ymm
12145 },
12146 { // FR16
12147 0, // FR16:sub_8bit
12148 0, // FR16:sub_8bit_hi
12149 0, // FR16:sub_8bit_hi_phony
12150 0, // FR16:sub_16bit
12151 0, // FR16:sub_16bit_hi
12152 0, // FR16:sub_32bit
12153 0, // FR16:sub_mask_0
12154 0, // FR16:sub_mask_1
12155 0, // FR16:sub_t0
12156 0, // FR16:sub_t1
12157 0, // FR16:sub_xmm
12158 0, // FR16:sub_ymm
12159 },
12160 { // VK16PAIR
12161 0, // VK16PAIR:sub_8bit
12162 0, // VK16PAIR:sub_8bit_hi
12163 0, // VK16PAIR:sub_8bit_hi_phony
12164 0, // VK16PAIR:sub_16bit
12165 0, // VK16PAIR:sub_16bit_hi
12166 0, // VK16PAIR:sub_32bit
12167 91, // VK16PAIR:sub_mask_0 -> VK64
12168 98, // VK16PAIR:sub_mask_1 -> VK64WM
12169 0, // VK16PAIR:sub_t0
12170 0, // VK16PAIR:sub_t1
12171 0, // VK16PAIR:sub_xmm
12172 0, // VK16PAIR:sub_ymm
12173 },
12174 { // VK1PAIR
12175 0, // VK1PAIR:sub_8bit
12176 0, // VK1PAIR:sub_8bit_hi
12177 0, // VK1PAIR:sub_8bit_hi_phony
12178 0, // VK1PAIR:sub_16bit
12179 0, // VK1PAIR:sub_16bit_hi
12180 0, // VK1PAIR:sub_32bit
12181 91, // VK1PAIR:sub_mask_0 -> VK64
12182 98, // VK1PAIR:sub_mask_1 -> VK64WM
12183 0, // VK1PAIR:sub_t0
12184 0, // VK1PAIR:sub_t1
12185 0, // VK1PAIR:sub_xmm
12186 0, // VK1PAIR:sub_ymm
12187 },
12188 { // VK2PAIR
12189 0, // VK2PAIR:sub_8bit
12190 0, // VK2PAIR:sub_8bit_hi
12191 0, // VK2PAIR:sub_8bit_hi_phony
12192 0, // VK2PAIR:sub_16bit
12193 0, // VK2PAIR:sub_16bit_hi
12194 0, // VK2PAIR:sub_32bit
12195 91, // VK2PAIR:sub_mask_0 -> VK64
12196 98, // VK2PAIR:sub_mask_1 -> VK64WM
12197 0, // VK2PAIR:sub_t0
12198 0, // VK2PAIR:sub_t1
12199 0, // VK2PAIR:sub_xmm
12200 0, // VK2PAIR:sub_ymm
12201 },
12202 { // VK4PAIR
12203 0, // VK4PAIR:sub_8bit
12204 0, // VK4PAIR:sub_8bit_hi
12205 0, // VK4PAIR:sub_8bit_hi_phony
12206 0, // VK4PAIR:sub_16bit
12207 0, // VK4PAIR:sub_16bit_hi
12208 0, // VK4PAIR:sub_32bit
12209 91, // VK4PAIR:sub_mask_0 -> VK64
12210 98, // VK4PAIR:sub_mask_1 -> VK64WM
12211 0, // VK4PAIR:sub_t0
12212 0, // VK4PAIR:sub_t1
12213 0, // VK4PAIR:sub_xmm
12214 0, // VK4PAIR:sub_ymm
12215 },
12216 { // VK8PAIR
12217 0, // VK8PAIR:sub_8bit
12218 0, // VK8PAIR:sub_8bit_hi
12219 0, // VK8PAIR:sub_8bit_hi_phony
12220 0, // VK8PAIR:sub_16bit
12221 0, // VK8PAIR:sub_16bit_hi
12222 0, // VK8PAIR:sub_32bit
12223 91, // VK8PAIR:sub_mask_0 -> VK64
12224 98, // VK8PAIR:sub_mask_1 -> VK64WM
12225 0, // VK8PAIR:sub_t0
12226 0, // VK8PAIR:sub_t1
12227 0, // VK8PAIR:sub_xmm
12228 0, // VK8PAIR:sub_ymm
12229 },
12230 { // VK1PAIR_with_sub_mask_0_in_VK1WM
12231 0, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_8bit
12232 0, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_8bit_hi
12233 0, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_8bit_hi_phony
12234 0, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_16bit
12235 0, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_16bit_hi
12236 0, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_32bit
12237 98, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_mask_0 -> VK64WM
12238 98, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_mask_1 -> VK64WM
12239 0, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_t0
12240 0, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_t1
12241 0, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_xmm
12242 0, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_ymm
12243 },
12244 { // LOW32_ADDR_ACCESS_RBP
12245 1, // LOW32_ADDR_ACCESS_RBP:sub_8bit -> GR8
12246 5, // LOW32_ADDR_ACCESS_RBP:sub_8bit_hi -> GR8_ABCD_H
12247 0, // LOW32_ADDR_ACCESS_RBP:sub_8bit_hi_phony
12248 8, // LOW32_ADDR_ACCESS_RBP:sub_16bit -> GR16
12249 0, // LOW32_ADDR_ACCESS_RBP:sub_16bit_hi
12250 66, // LOW32_ADDR_ACCESS_RBP:sub_32bit -> GR32_BPSP_and_GR32_DIBP
12251 0, // LOW32_ADDR_ACCESS_RBP:sub_mask_0
12252 0, // LOW32_ADDR_ACCESS_RBP:sub_mask_1
12253 0, // LOW32_ADDR_ACCESS_RBP:sub_t0
12254 0, // LOW32_ADDR_ACCESS_RBP:sub_t1
12255 0, // LOW32_ADDR_ACCESS_RBP:sub_xmm
12256 0, // LOW32_ADDR_ACCESS_RBP:sub_ymm
12257 },
12258 { // LOW32_ADDR_ACCESS
12259 1, // LOW32_ADDR_ACCESS:sub_8bit -> GR8
12260 5, // LOW32_ADDR_ACCESS:sub_8bit_hi -> GR8_ABCD_H
12261 0, // LOW32_ADDR_ACCESS:sub_8bit_hi_phony
12262 8, // LOW32_ADDR_ACCESS:sub_16bit -> GR16
12263 0, // LOW32_ADDR_ACCESS:sub_16bit_hi
12264 0, // LOW32_ADDR_ACCESS:sub_32bit
12265 0, // LOW32_ADDR_ACCESS:sub_mask_0
12266 0, // LOW32_ADDR_ACCESS:sub_mask_1
12267 0, // LOW32_ADDR_ACCESS:sub_t0
12268 0, // LOW32_ADDR_ACCESS:sub_t1
12269 0, // LOW32_ADDR_ACCESS:sub_xmm
12270 0, // LOW32_ADDR_ACCESS:sub_ymm
12271 },
12272 { // LOW32_ADDR_ACCESS_RBP_with_sub_8bit
12273 1, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_8bit -> GR8
12274 5, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_8bit_hi -> GR8_ABCD_H
12275 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_8bit_hi_phony
12276 8, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_16bit -> GR16
12277 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_16bit_hi
12278 66, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_32bit -> GR32_BPSP_and_GR32_DIBP
12279 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_mask_0
12280 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_mask_1
12281 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_t0
12282 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_t1
12283 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_xmm
12284 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_ymm
12285 },
12286 { // FR32X
12287 0, // FR32X:sub_8bit
12288 0, // FR32X:sub_8bit_hi
12289 0, // FR32X:sub_8bit_hi_phony
12290 0, // FR32X:sub_16bit
12291 0, // FR32X:sub_16bit_hi
12292 0, // FR32X:sub_32bit
12293 0, // FR32X:sub_mask_0
12294 0, // FR32X:sub_mask_1
12295 0, // FR32X:sub_t0
12296 0, // FR32X:sub_t1
12297 0, // FR32X:sub_xmm
12298 0, // FR32X:sub_ymm
12299 },
12300 { // GR32
12301 1, // GR32:sub_8bit -> GR8
12302 5, // GR32:sub_8bit_hi -> GR8_ABCD_H
12303 0, // GR32:sub_8bit_hi_phony
12304 8, // GR32:sub_16bit -> GR16
12305 0, // GR32:sub_16bit_hi
12306 0, // GR32:sub_32bit
12307 0, // GR32:sub_mask_0
12308 0, // GR32:sub_mask_1
12309 0, // GR32:sub_t0
12310 0, // GR32:sub_t1
12311 0, // GR32:sub_xmm
12312 0, // GR32:sub_ymm
12313 },
12314 { // GR32_NOSP
12315 1, // GR32_NOSP:sub_8bit -> GR8
12316 5, // GR32_NOSP:sub_8bit_hi -> GR8_ABCD_H
12317 0, // GR32_NOSP:sub_8bit_hi_phony
12318 8, // GR32_NOSP:sub_16bit -> GR16
12319 0, // GR32_NOSP:sub_16bit_hi
12320 0, // GR32_NOSP:sub_32bit
12321 0, // GR32_NOSP:sub_mask_0
12322 0, // GR32_NOSP:sub_mask_1
12323 0, // GR32_NOSP:sub_t0
12324 0, // GR32_NOSP:sub_t1
12325 0, // GR32_NOSP:sub_xmm
12326 0, // GR32_NOSP:sub_ymm
12327 },
12328 { // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
12329 3, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_8bit -> GR8_NOREX2
12330 5, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_8bit_hi -> GR8_ABCD_H
12331 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_8bit_hi_phony
12332 9, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_16bit -> GR16_NOREX2
12333 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_16bit_hi
12334 66, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_32bit -> GR32_BPSP_and_GR32_DIBP
12335 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_mask_0
12336 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_mask_1
12337 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_t0
12338 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_t1
12339 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_xmm
12340 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_ymm
12341 },
12342 { // DEBUG_REG
12343 0, // DEBUG_REG:sub_8bit
12344 0, // DEBUG_REG:sub_8bit_hi
12345 0, // DEBUG_REG:sub_8bit_hi_phony
12346 0, // DEBUG_REG:sub_16bit
12347 0, // DEBUG_REG:sub_16bit_hi
12348 0, // DEBUG_REG:sub_32bit
12349 0, // DEBUG_REG:sub_mask_0
12350 0, // DEBUG_REG:sub_mask_1
12351 0, // DEBUG_REG:sub_t0
12352 0, // DEBUG_REG:sub_t1
12353 0, // DEBUG_REG:sub_xmm
12354 0, // DEBUG_REG:sub_ymm
12355 },
12356 { // FR32
12357 0, // FR32:sub_8bit
12358 0, // FR32:sub_8bit_hi
12359 0, // FR32:sub_8bit_hi_phony
12360 0, // FR32:sub_16bit
12361 0, // FR32:sub_16bit_hi
12362 0, // FR32:sub_32bit
12363 0, // FR32:sub_mask_0
12364 0, // FR32:sub_mask_1
12365 0, // FR32:sub_t0
12366 0, // FR32:sub_t1
12367 0, // FR32:sub_xmm
12368 0, // FR32:sub_ymm
12369 },
12370 { // GR32_NOREX2
12371 3, // GR32_NOREX2:sub_8bit -> GR8_NOREX2
12372 5, // GR32_NOREX2:sub_8bit_hi -> GR8_ABCD_H
12373 0, // GR32_NOREX2:sub_8bit_hi_phony
12374 9, // GR32_NOREX2:sub_16bit -> GR16_NOREX2
12375 0, // GR32_NOREX2:sub_16bit_hi
12376 0, // GR32_NOREX2:sub_32bit
12377 0, // GR32_NOREX2:sub_mask_0
12378 0, // GR32_NOREX2:sub_mask_1
12379 0, // GR32_NOREX2:sub_t0
12380 0, // GR32_NOREX2:sub_t1
12381 0, // GR32_NOREX2:sub_xmm
12382 0, // GR32_NOREX2:sub_ymm
12383 },
12384 { // GR32_NOREX2_NOSP
12385 3, // GR32_NOREX2_NOSP:sub_8bit -> GR8_NOREX2
12386 5, // GR32_NOREX2_NOSP:sub_8bit_hi -> GR8_ABCD_H
12387 0, // GR32_NOREX2_NOSP:sub_8bit_hi_phony
12388 9, // GR32_NOREX2_NOSP:sub_16bit -> GR16_NOREX2
12389 0, // GR32_NOREX2_NOSP:sub_16bit_hi
12390 0, // GR32_NOREX2_NOSP:sub_32bit
12391 0, // GR32_NOREX2_NOSP:sub_mask_0
12392 0, // GR32_NOREX2_NOSP:sub_mask_1
12393 0, // GR32_NOREX2_NOSP:sub_t0
12394 0, // GR32_NOREX2_NOSP:sub_t1
12395 0, // GR32_NOREX2_NOSP:sub_xmm
12396 0, // GR32_NOREX2_NOSP:sub_ymm
12397 },
12398 { // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
12399 3, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_8bit -> GR8_NOREX2
12400 5, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_8bit_hi -> GR8_ABCD_H
12401 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_8bit_hi_phony
12402 10, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_16bit -> GR16_NOREX
12403 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_16bit_hi
12404 66, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_32bit -> GR32_BPSP_and_GR32_DIBP
12405 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_mask_0
12406 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_mask_1
12407 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_t0
12408 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_t1
12409 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_xmm
12410 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_ymm
12411 },
12412 { // GR32_NOREX
12413 3, // GR32_NOREX:sub_8bit -> GR8_NOREX2
12414 5, // GR32_NOREX:sub_8bit_hi -> GR8_ABCD_H
12415 0, // GR32_NOREX:sub_8bit_hi_phony
12416 10, // GR32_NOREX:sub_16bit -> GR16_NOREX
12417 0, // GR32_NOREX:sub_16bit_hi
12418 0, // GR32_NOREX:sub_32bit
12419 0, // GR32_NOREX:sub_mask_0
12420 0, // GR32_NOREX:sub_mask_1
12421 0, // GR32_NOREX:sub_t0
12422 0, // GR32_NOREX:sub_t1
12423 0, // GR32_NOREX:sub_xmm
12424 0, // GR32_NOREX:sub_ymm
12425 },
12426 { // VK32
12427 0, // VK32:sub_8bit
12428 0, // VK32:sub_8bit_hi
12429 0, // VK32:sub_8bit_hi_phony
12430 0, // VK32:sub_16bit
12431 0, // VK32:sub_16bit_hi
12432 0, // VK32:sub_32bit
12433 0, // VK32:sub_mask_0
12434 0, // VK32:sub_mask_1
12435 0, // VK32:sub_t0
12436 0, // VK32:sub_t1
12437 0, // VK32:sub_xmm
12438 0, // VK32:sub_ymm
12439 },
12440 { // GR32_NOREX_NOSP
12441 3, // GR32_NOREX_NOSP:sub_8bit -> GR8_NOREX2
12442 5, // GR32_NOREX_NOSP:sub_8bit_hi -> GR8_ABCD_H
12443 0, // GR32_NOREX_NOSP:sub_8bit_hi_phony
12444 10, // GR32_NOREX_NOSP:sub_16bit -> GR16_NOREX
12445 0, // GR32_NOREX_NOSP:sub_16bit_hi
12446 0, // GR32_NOREX_NOSP:sub_32bit
12447 0, // GR32_NOREX_NOSP:sub_mask_0
12448 0, // GR32_NOREX_NOSP:sub_mask_1
12449 0, // GR32_NOREX_NOSP:sub_t0
12450 0, // GR32_NOREX_NOSP:sub_t1
12451 0, // GR32_NOREX_NOSP:sub_xmm
12452 0, // GR32_NOREX_NOSP:sub_ymm
12453 },
12454 { // RFP32
12455 0, // RFP32:sub_8bit
12456 0, // RFP32:sub_8bit_hi
12457 0, // RFP32:sub_8bit_hi_phony
12458 0, // RFP32:sub_16bit
12459 0, // RFP32:sub_16bit_hi
12460 0, // RFP32:sub_32bit
12461 0, // RFP32:sub_mask_0
12462 0, // RFP32:sub_mask_1
12463 0, // RFP32:sub_t0
12464 0, // RFP32:sub_t1
12465 0, // RFP32:sub_xmm
12466 0, // RFP32:sub_ymm
12467 },
12468 { // VK32WM
12469 0, // VK32WM:sub_8bit
12470 0, // VK32WM:sub_8bit_hi
12471 0, // VK32WM:sub_8bit_hi_phony
12472 0, // VK32WM:sub_16bit
12473 0, // VK32WM:sub_16bit_hi
12474 0, // VK32WM:sub_32bit
12475 0, // VK32WM:sub_mask_0
12476 0, // VK32WM:sub_mask_1
12477 0, // VK32WM:sub_t0
12478 0, // VK32WM:sub_t1
12479 0, // VK32WM:sub_xmm
12480 0, // VK32WM:sub_ymm
12481 },
12482 { // GR32_ABCD
12483 6, // GR32_ABCD:sub_8bit -> GR8_ABCD_L
12484 5, // GR32_ABCD:sub_8bit_hi -> GR8_ABCD_H
12485 0, // GR32_ABCD:sub_8bit_hi_phony
12486 22, // GR32_ABCD:sub_16bit -> GR16_ABCD
12487 0, // GR32_ABCD:sub_16bit_hi
12488 0, // GR32_ABCD:sub_32bit
12489 0, // GR32_ABCD:sub_mask_0
12490 0, // GR32_ABCD:sub_mask_1
12491 0, // GR32_ABCD:sub_t0
12492 0, // GR32_ABCD:sub_t1
12493 0, // GR32_ABCD:sub_xmm
12494 0, // GR32_ABCD:sub_ymm
12495 },
12496 { // GR32_TC
12497 3, // GR32_TC:sub_8bit -> GR8_NOREX2
12498 5, // GR32_TC:sub_8bit_hi -> GR8_ABCD_H
12499 0, // GR32_TC:sub_8bit_hi_phony
12500 10, // GR32_TC:sub_16bit -> GR16_NOREX
12501 0, // GR32_TC:sub_16bit_hi
12502 0, // GR32_TC:sub_32bit
12503 0, // GR32_TC:sub_mask_0
12504 0, // GR32_TC:sub_mask_1
12505 0, // GR32_TC:sub_t0
12506 0, // GR32_TC:sub_t1
12507 0, // GR32_TC:sub_xmm
12508 0, // GR32_TC:sub_ymm
12509 },
12510 { // GR32_ABCD_and_GR32_TC
12511 6, // GR32_ABCD_and_GR32_TC:sub_8bit -> GR8_ABCD_L
12512 5, // GR32_ABCD_and_GR32_TC:sub_8bit_hi -> GR8_ABCD_H
12513 0, // GR32_ABCD_and_GR32_TC:sub_8bit_hi_phony
12514 22, // GR32_ABCD_and_GR32_TC:sub_16bit -> GR16_ABCD
12515 0, // GR32_ABCD_and_GR32_TC:sub_16bit_hi
12516 0, // GR32_ABCD_and_GR32_TC:sub_32bit
12517 0, // GR32_ABCD_and_GR32_TC:sub_mask_0
12518 0, // GR32_ABCD_and_GR32_TC:sub_mask_1
12519 0, // GR32_ABCD_and_GR32_TC:sub_t0
12520 0, // GR32_ABCD_and_GR32_TC:sub_t1
12521 0, // GR32_ABCD_and_GR32_TC:sub_xmm
12522 0, // GR32_ABCD_and_GR32_TC:sub_ymm
12523 },
12524 { // GR32_AD
12525 6, // GR32_AD:sub_8bit -> GR8_ABCD_L
12526 5, // GR32_AD:sub_8bit_hi -> GR8_ABCD_H
12527 0, // GR32_AD:sub_8bit_hi_phony
12528 22, // GR32_AD:sub_16bit -> GR16_ABCD
12529 0, // GR32_AD:sub_16bit_hi
12530 0, // GR32_AD:sub_32bit
12531 0, // GR32_AD:sub_mask_0
12532 0, // GR32_AD:sub_mask_1
12533 0, // GR32_AD:sub_t0
12534 0, // GR32_AD:sub_t1
12535 0, // GR32_AD:sub_xmm
12536 0, // GR32_AD:sub_ymm
12537 },
12538 { // GR32_ArgRef
12539 6, // GR32_ArgRef:sub_8bit -> GR8_ABCD_L
12540 5, // GR32_ArgRef:sub_8bit_hi -> GR8_ABCD_H
12541 0, // GR32_ArgRef:sub_8bit_hi_phony
12542 22, // GR32_ArgRef:sub_16bit -> GR16_ABCD
12543 0, // GR32_ArgRef:sub_16bit_hi
12544 0, // GR32_ArgRef:sub_32bit
12545 0, // GR32_ArgRef:sub_mask_0
12546 0, // GR32_ArgRef:sub_mask_1
12547 0, // GR32_ArgRef:sub_t0
12548 0, // GR32_ArgRef:sub_t1
12549 0, // GR32_ArgRef:sub_xmm
12550 0, // GR32_ArgRef:sub_ymm
12551 },
12552 { // GR32_BPSP
12553 3, // GR32_BPSP:sub_8bit -> GR8_NOREX2
12554 0, // GR32_BPSP:sub_8bit_hi
12555 0, // GR32_BPSP:sub_8bit_hi_phony
12556 10, // GR32_BPSP:sub_16bit -> GR16_NOREX
12557 0, // GR32_BPSP:sub_16bit_hi
12558 0, // GR32_BPSP:sub_32bit
12559 0, // GR32_BPSP:sub_mask_0
12560 0, // GR32_BPSP:sub_mask_1
12561 0, // GR32_BPSP:sub_t0
12562 0, // GR32_BPSP:sub_t1
12563 0, // GR32_BPSP:sub_xmm
12564 0, // GR32_BPSP:sub_ymm
12565 },
12566 { // GR32_BSI
12567 3, // GR32_BSI:sub_8bit -> GR8_NOREX2
12568 5, // GR32_BSI:sub_8bit_hi -> GR8_ABCD_H
12569 0, // GR32_BSI:sub_8bit_hi_phony
12570 10, // GR32_BSI:sub_16bit -> GR16_NOREX
12571 0, // GR32_BSI:sub_16bit_hi
12572 0, // GR32_BSI:sub_32bit
12573 0, // GR32_BSI:sub_mask_0
12574 0, // GR32_BSI:sub_mask_1
12575 0, // GR32_BSI:sub_t0
12576 0, // GR32_BSI:sub_t1
12577 0, // GR32_BSI:sub_xmm
12578 0, // GR32_BSI:sub_ymm
12579 },
12580 { // GR32_CB
12581 6, // GR32_CB:sub_8bit -> GR8_ABCD_L
12582 5, // GR32_CB:sub_8bit_hi -> GR8_ABCD_H
12583 0, // GR32_CB:sub_8bit_hi_phony
12584 22, // GR32_CB:sub_16bit -> GR16_ABCD
12585 0, // GR32_CB:sub_16bit_hi
12586 0, // GR32_CB:sub_32bit
12587 0, // GR32_CB:sub_mask_0
12588 0, // GR32_CB:sub_mask_1
12589 0, // GR32_CB:sub_t0
12590 0, // GR32_CB:sub_t1
12591 0, // GR32_CB:sub_xmm
12592 0, // GR32_CB:sub_ymm
12593 },
12594 { // GR32_DC
12595 6, // GR32_DC:sub_8bit -> GR8_ABCD_L
12596 5, // GR32_DC:sub_8bit_hi -> GR8_ABCD_H
12597 0, // GR32_DC:sub_8bit_hi_phony
12598 22, // GR32_DC:sub_16bit -> GR16_ABCD
12599 0, // GR32_DC:sub_16bit_hi
12600 0, // GR32_DC:sub_32bit
12601 0, // GR32_DC:sub_mask_0
12602 0, // GR32_DC:sub_mask_1
12603 0, // GR32_DC:sub_t0
12604 0, // GR32_DC:sub_t1
12605 0, // GR32_DC:sub_xmm
12606 0, // GR32_DC:sub_ymm
12607 },
12608 { // GR32_DIBP
12609 3, // GR32_DIBP:sub_8bit -> GR8_NOREX2
12610 0, // GR32_DIBP:sub_8bit_hi
12611 0, // GR32_DIBP:sub_8bit_hi_phony
12612 10, // GR32_DIBP:sub_16bit -> GR16_NOREX
12613 0, // GR32_DIBP:sub_16bit_hi
12614 0, // GR32_DIBP:sub_32bit
12615 0, // GR32_DIBP:sub_mask_0
12616 0, // GR32_DIBP:sub_mask_1
12617 0, // GR32_DIBP:sub_t0
12618 0, // GR32_DIBP:sub_t1
12619 0, // GR32_DIBP:sub_xmm
12620 0, // GR32_DIBP:sub_ymm
12621 },
12622 { // GR32_SIDI
12623 3, // GR32_SIDI:sub_8bit -> GR8_NOREX2
12624 0, // GR32_SIDI:sub_8bit_hi
12625 0, // GR32_SIDI:sub_8bit_hi_phony
12626 10, // GR32_SIDI:sub_16bit -> GR16_NOREX
12627 0, // GR32_SIDI:sub_16bit_hi
12628 0, // GR32_SIDI:sub_32bit
12629 0, // GR32_SIDI:sub_mask_0
12630 0, // GR32_SIDI:sub_mask_1
12631 0, // GR32_SIDI:sub_t0
12632 0, // GR32_SIDI:sub_t1
12633 0, // GR32_SIDI:sub_xmm
12634 0, // GR32_SIDI:sub_ymm
12635 },
12636 { // LOW32_ADDR_ACCESS_RBP_with_sub_32bit
12637 3, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_8bit -> GR8_NOREX2
12638 0, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_8bit_hi
12639 0, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_8bit_hi_phony
12640 10, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_16bit -> GR16_NOREX
12641 0, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_16bit_hi
12642 66, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_32bit -> GR32_BPSP_and_GR32_DIBP
12643 0, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_mask_0
12644 0, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_mask_1
12645 0, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_t0
12646 0, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_t1
12647 0, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_xmm
12648 0, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_ymm
12649 },
12650 { // CCR
12651 0, // CCR:sub_8bit
12652 0, // CCR:sub_8bit_hi
12653 0, // CCR:sub_8bit_hi_phony
12654 0, // CCR:sub_16bit
12655 0, // CCR:sub_16bit_hi
12656 0, // CCR:sub_32bit
12657 0, // CCR:sub_mask_0
12658 0, // CCR:sub_mask_1
12659 0, // CCR:sub_t0
12660 0, // CCR:sub_t1
12661 0, // CCR:sub_xmm
12662 0, // CCR:sub_ymm
12663 },
12664 { // DFCCR
12665 0, // DFCCR:sub_8bit
12666 0, // DFCCR:sub_8bit_hi
12667 0, // DFCCR:sub_8bit_hi_phony
12668 0, // DFCCR:sub_16bit
12669 0, // DFCCR:sub_16bit_hi
12670 0, // DFCCR:sub_32bit
12671 0, // DFCCR:sub_mask_0
12672 0, // DFCCR:sub_mask_1
12673 0, // DFCCR:sub_t0
12674 0, // DFCCR:sub_t1
12675 0, // DFCCR:sub_xmm
12676 0, // DFCCR:sub_ymm
12677 },
12678 { // GR32_ABCD_and_GR32_BSI
12679 6, // GR32_ABCD_and_GR32_BSI:sub_8bit -> GR8_ABCD_L
12680 5, // GR32_ABCD_and_GR32_BSI:sub_8bit_hi -> GR8_ABCD_H
12681 0, // GR32_ABCD_and_GR32_BSI:sub_8bit_hi_phony
12682 22, // GR32_ABCD_and_GR32_BSI:sub_16bit -> GR16_ABCD
12683 0, // GR32_ABCD_and_GR32_BSI:sub_16bit_hi
12684 0, // GR32_ABCD_and_GR32_BSI:sub_32bit
12685 0, // GR32_ABCD_and_GR32_BSI:sub_mask_0
12686 0, // GR32_ABCD_and_GR32_BSI:sub_mask_1
12687 0, // GR32_ABCD_and_GR32_BSI:sub_t0
12688 0, // GR32_ABCD_and_GR32_BSI:sub_t1
12689 0, // GR32_ABCD_and_GR32_BSI:sub_xmm
12690 0, // GR32_ABCD_and_GR32_BSI:sub_ymm
12691 },
12692 { // GR32_AD_and_GR32_ArgRef
12693 6, // GR32_AD_and_GR32_ArgRef:sub_8bit -> GR8_ABCD_L
12694 5, // GR32_AD_and_GR32_ArgRef:sub_8bit_hi -> GR8_ABCD_H
12695 0, // GR32_AD_and_GR32_ArgRef:sub_8bit_hi_phony
12696 22, // GR32_AD_and_GR32_ArgRef:sub_16bit -> GR16_ABCD
12697 0, // GR32_AD_and_GR32_ArgRef:sub_16bit_hi
12698 0, // GR32_AD_and_GR32_ArgRef:sub_32bit
12699 0, // GR32_AD_and_GR32_ArgRef:sub_mask_0
12700 0, // GR32_AD_and_GR32_ArgRef:sub_mask_1
12701 0, // GR32_AD_and_GR32_ArgRef:sub_t0
12702 0, // GR32_AD_and_GR32_ArgRef:sub_t1
12703 0, // GR32_AD_and_GR32_ArgRef:sub_xmm
12704 0, // GR32_AD_and_GR32_ArgRef:sub_ymm
12705 },
12706 { // GR32_ArgRef_and_GR32_CB
12707 6, // GR32_ArgRef_and_GR32_CB:sub_8bit -> GR8_ABCD_L
12708 5, // GR32_ArgRef_and_GR32_CB:sub_8bit_hi -> GR8_ABCD_H
12709 0, // GR32_ArgRef_and_GR32_CB:sub_8bit_hi_phony
12710 22, // GR32_ArgRef_and_GR32_CB:sub_16bit -> GR16_ABCD
12711 0, // GR32_ArgRef_and_GR32_CB:sub_16bit_hi
12712 0, // GR32_ArgRef_and_GR32_CB:sub_32bit
12713 0, // GR32_ArgRef_and_GR32_CB:sub_mask_0
12714 0, // GR32_ArgRef_and_GR32_CB:sub_mask_1
12715 0, // GR32_ArgRef_and_GR32_CB:sub_t0
12716 0, // GR32_ArgRef_and_GR32_CB:sub_t1
12717 0, // GR32_ArgRef_and_GR32_CB:sub_xmm
12718 0, // GR32_ArgRef_and_GR32_CB:sub_ymm
12719 },
12720 { // GR32_BPSP_and_GR32_DIBP
12721 3, // GR32_BPSP_and_GR32_DIBP:sub_8bit -> GR8_NOREX2
12722 0, // GR32_BPSP_and_GR32_DIBP:sub_8bit_hi
12723 0, // GR32_BPSP_and_GR32_DIBP:sub_8bit_hi_phony
12724 10, // GR32_BPSP_and_GR32_DIBP:sub_16bit -> GR16_NOREX
12725 0, // GR32_BPSP_and_GR32_DIBP:sub_16bit_hi
12726 0, // GR32_BPSP_and_GR32_DIBP:sub_32bit
12727 0, // GR32_BPSP_and_GR32_DIBP:sub_mask_0
12728 0, // GR32_BPSP_and_GR32_DIBP:sub_mask_1
12729 0, // GR32_BPSP_and_GR32_DIBP:sub_t0
12730 0, // GR32_BPSP_and_GR32_DIBP:sub_t1
12731 0, // GR32_BPSP_and_GR32_DIBP:sub_xmm
12732 0, // GR32_BPSP_and_GR32_DIBP:sub_ymm
12733 },
12734 { // GR32_BPSP_and_GR32_TC
12735 3, // GR32_BPSP_and_GR32_TC:sub_8bit -> GR8_NOREX2
12736 0, // GR32_BPSP_and_GR32_TC:sub_8bit_hi
12737 0, // GR32_BPSP_and_GR32_TC:sub_8bit_hi_phony
12738 10, // GR32_BPSP_and_GR32_TC:sub_16bit -> GR16_NOREX
12739 0, // GR32_BPSP_and_GR32_TC:sub_16bit_hi
12740 0, // GR32_BPSP_and_GR32_TC:sub_32bit
12741 0, // GR32_BPSP_and_GR32_TC:sub_mask_0
12742 0, // GR32_BPSP_and_GR32_TC:sub_mask_1
12743 0, // GR32_BPSP_and_GR32_TC:sub_t0
12744 0, // GR32_BPSP_and_GR32_TC:sub_t1
12745 0, // GR32_BPSP_and_GR32_TC:sub_xmm
12746 0, // GR32_BPSP_and_GR32_TC:sub_ymm
12747 },
12748 { // GR32_BSI_and_GR32_SIDI
12749 3, // GR32_BSI_and_GR32_SIDI:sub_8bit -> GR8_NOREX2
12750 0, // GR32_BSI_and_GR32_SIDI:sub_8bit_hi
12751 0, // GR32_BSI_and_GR32_SIDI:sub_8bit_hi_phony
12752 10, // GR32_BSI_and_GR32_SIDI:sub_16bit -> GR16_NOREX
12753 0, // GR32_BSI_and_GR32_SIDI:sub_16bit_hi
12754 0, // GR32_BSI_and_GR32_SIDI:sub_32bit
12755 0, // GR32_BSI_and_GR32_SIDI:sub_mask_0
12756 0, // GR32_BSI_and_GR32_SIDI:sub_mask_1
12757 0, // GR32_BSI_and_GR32_SIDI:sub_t0
12758 0, // GR32_BSI_and_GR32_SIDI:sub_t1
12759 0, // GR32_BSI_and_GR32_SIDI:sub_xmm
12760 0, // GR32_BSI_and_GR32_SIDI:sub_ymm
12761 },
12762 { // GR32_DIBP_and_GR32_SIDI
12763 3, // GR32_DIBP_and_GR32_SIDI:sub_8bit -> GR8_NOREX2
12764 0, // GR32_DIBP_and_GR32_SIDI:sub_8bit_hi
12765 0, // GR32_DIBP_and_GR32_SIDI:sub_8bit_hi_phony
12766 10, // GR32_DIBP_and_GR32_SIDI:sub_16bit -> GR16_NOREX
12767 0, // GR32_DIBP_and_GR32_SIDI:sub_16bit_hi
12768 0, // GR32_DIBP_and_GR32_SIDI:sub_32bit
12769 0, // GR32_DIBP_and_GR32_SIDI:sub_mask_0
12770 0, // GR32_DIBP_and_GR32_SIDI:sub_mask_1
12771 0, // GR32_DIBP_and_GR32_SIDI:sub_t0
12772 0, // GR32_DIBP_and_GR32_SIDI:sub_t1
12773 0, // GR32_DIBP_and_GR32_SIDI:sub_xmm
12774 0, // GR32_DIBP_and_GR32_SIDI:sub_ymm
12775 },
12776 { // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
12777 3, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_8bit -> GR8_NOREX2
12778 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_8bit_hi
12779 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_8bit_hi_phony
12780 10, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_16bit -> GR16_NOREX
12781 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_16bit_hi
12782 66, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_32bit -> GR32_BPSP_and_GR32_DIBP
12783 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_mask_0
12784 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_mask_1
12785 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_t0
12786 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_t1
12787 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_xmm
12788 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_ymm
12789 },
12790 { // LOW32_ADDR_ACCESS_with_sub_32bit
12791 0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_8bit
12792 0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_8bit_hi
12793 0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_8bit_hi_phony
12794 0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_16bit
12795 0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_16bit_hi
12796 0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_32bit
12797 0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_mask_0
12798 0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_mask_1
12799 0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_t0
12800 0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_t1
12801 0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_xmm
12802 0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_ymm
12803 },
12804 { // RFP64
12805 0, // RFP64:sub_8bit
12806 0, // RFP64:sub_8bit_hi
12807 0, // RFP64:sub_8bit_hi_phony
12808 0, // RFP64:sub_16bit
12809 0, // RFP64:sub_16bit_hi
12810 0, // RFP64:sub_32bit
12811 0, // RFP64:sub_mask_0
12812 0, // RFP64:sub_mask_1
12813 0, // RFP64:sub_t0
12814 0, // RFP64:sub_t1
12815 0, // RFP64:sub_xmm
12816 0, // RFP64:sub_ymm
12817 },
12818 { // GR64
12819 1, // GR64:sub_8bit -> GR8
12820 5, // GR64:sub_8bit_hi -> GR8_ABCD_H
12821 0, // GR64:sub_8bit_hi_phony
12822 8, // GR64:sub_16bit -> GR16
12823 0, // GR64:sub_16bit_hi
12824 36, // GR64:sub_32bit -> GR32
12825 0, // GR64:sub_mask_0
12826 0, // GR64:sub_mask_1
12827 0, // GR64:sub_t0
12828 0, // GR64:sub_t1
12829 0, // GR64:sub_xmm
12830 0, // GR64:sub_ymm
12831 },
12832 { // FR64X
12833 0, // FR64X:sub_8bit
12834 0, // FR64X:sub_8bit_hi
12835 0, // FR64X:sub_8bit_hi_phony
12836 0, // FR64X:sub_16bit
12837 0, // FR64X:sub_16bit_hi
12838 0, // FR64X:sub_32bit
12839 0, // FR64X:sub_mask_0
12840 0, // FR64X:sub_mask_1
12841 0, // FR64X:sub_t0
12842 0, // FR64X:sub_t1
12843 0, // FR64X:sub_xmm
12844 0, // FR64X:sub_ymm
12845 },
12846 { // GR64_with_sub_8bit
12847 1, // GR64_with_sub_8bit:sub_8bit -> GR8
12848 5, // GR64_with_sub_8bit:sub_8bit_hi -> GR8_ABCD_H
12849 0, // GR64_with_sub_8bit:sub_8bit_hi_phony
12850 8, // GR64_with_sub_8bit:sub_16bit -> GR16
12851 0, // GR64_with_sub_8bit:sub_16bit_hi
12852 36, // GR64_with_sub_8bit:sub_32bit -> GR32
12853 0, // GR64_with_sub_8bit:sub_mask_0
12854 0, // GR64_with_sub_8bit:sub_mask_1
12855 0, // GR64_with_sub_8bit:sub_t0
12856 0, // GR64_with_sub_8bit:sub_t1
12857 0, // GR64_with_sub_8bit:sub_xmm
12858 0, // GR64_with_sub_8bit:sub_ymm
12859 },
12860 { // GR64_NOSP
12861 1, // GR64_NOSP:sub_8bit -> GR8
12862 5, // GR64_NOSP:sub_8bit_hi -> GR8_ABCD_H
12863 0, // GR64_NOSP:sub_8bit_hi_phony
12864 8, // GR64_NOSP:sub_16bit -> GR16
12865 0, // GR64_NOSP:sub_16bit_hi
12866 37, // GR64_NOSP:sub_32bit -> GR32_NOSP
12867 0, // GR64_NOSP:sub_mask_0
12868 0, // GR64_NOSP:sub_mask_1
12869 0, // GR64_NOSP:sub_t0
12870 0, // GR64_NOSP:sub_t1
12871 0, // GR64_NOSP:sub_xmm
12872 0, // GR64_NOSP:sub_ymm
12873 },
12874 { // GR64_NOREX2
12875 3, // GR64_NOREX2:sub_8bit -> GR8_NOREX2
12876 5, // GR64_NOREX2:sub_8bit_hi -> GR8_ABCD_H
12877 0, // GR64_NOREX2:sub_8bit_hi_phony
12878 9, // GR64_NOREX2:sub_16bit -> GR16_NOREX2
12879 0, // GR64_NOREX2:sub_16bit_hi
12880 41, // GR64_NOREX2:sub_32bit -> GR32_NOREX2
12881 0, // GR64_NOREX2:sub_mask_0
12882 0, // GR64_NOREX2:sub_mask_1
12883 0, // GR64_NOREX2:sub_t0
12884 0, // GR64_NOREX2:sub_t1
12885 0, // GR64_NOREX2:sub_xmm
12886 0, // GR64_NOREX2:sub_ymm
12887 },
12888 { // CONTROL_REG
12889 0, // CONTROL_REG:sub_8bit
12890 0, // CONTROL_REG:sub_8bit_hi
12891 0, // CONTROL_REG:sub_8bit_hi_phony
12892 0, // CONTROL_REG:sub_16bit
12893 0, // CONTROL_REG:sub_16bit_hi
12894 0, // CONTROL_REG:sub_32bit
12895 0, // CONTROL_REG:sub_mask_0
12896 0, // CONTROL_REG:sub_mask_1
12897 0, // CONTROL_REG:sub_t0
12898 0, // CONTROL_REG:sub_t1
12899 0, // CONTROL_REG:sub_xmm
12900 0, // CONTROL_REG:sub_ymm
12901 },
12902 { // FR64
12903 0, // FR64:sub_8bit
12904 0, // FR64:sub_8bit_hi
12905 0, // FR64:sub_8bit_hi_phony
12906 0, // FR64:sub_16bit
12907 0, // FR64:sub_16bit_hi
12908 0, // FR64:sub_32bit
12909 0, // FR64:sub_mask_0
12910 0, // FR64:sub_mask_1
12911 0, // FR64:sub_t0
12912 0, // FR64:sub_t1
12913 0, // FR64:sub_xmm
12914 0, // FR64:sub_ymm
12915 },
12916 { // GR64_with_sub_16bit_in_GR16_NOREX2
12917 3, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_8bit -> GR8_NOREX2
12918 5, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_8bit_hi -> GR8_ABCD_H
12919 0, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_8bit_hi_phony
12920 9, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_16bit -> GR16_NOREX2
12921 0, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_16bit_hi
12922 41, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_32bit -> GR32_NOREX2
12923 0, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_mask_0
12924 0, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_mask_1
12925 0, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_t0
12926 0, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_t1
12927 0, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_xmm
12928 0, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_ymm
12929 },
12930 { // GR64_NOREX2_NOSP
12931 3, // GR64_NOREX2_NOSP:sub_8bit -> GR8_NOREX2
12932 5, // GR64_NOREX2_NOSP:sub_8bit_hi -> GR8_ABCD_H
12933 0, // GR64_NOREX2_NOSP:sub_8bit_hi_phony
12934 9, // GR64_NOREX2_NOSP:sub_16bit -> GR16_NOREX2
12935 0, // GR64_NOREX2_NOSP:sub_16bit_hi
12936 42, // GR64_NOREX2_NOSP:sub_32bit -> GR32_NOREX2_NOSP
12937 0, // GR64_NOREX2_NOSP:sub_mask_0
12938 0, // GR64_NOREX2_NOSP:sub_mask_1
12939 0, // GR64_NOREX2_NOSP:sub_t0
12940 0, // GR64_NOREX2_NOSP:sub_t1
12941 0, // GR64_NOREX2_NOSP:sub_xmm
12942 0, // GR64_NOREX2_NOSP:sub_ymm
12943 },
12944 { // GR64PLTSafe
12945 3, // GR64PLTSafe:sub_8bit -> GR8_NOREX2
12946 5, // GR64PLTSafe:sub_8bit_hi -> GR8_ABCD_H
12947 0, // GR64PLTSafe:sub_8bit_hi_phony
12948 9, // GR64PLTSafe:sub_16bit -> GR16_NOREX2
12949 0, // GR64PLTSafe:sub_16bit_hi
12950 42, // GR64PLTSafe:sub_32bit -> GR32_NOREX2_NOSP
12951 0, // GR64PLTSafe:sub_mask_0
12952 0, // GR64PLTSafe:sub_mask_1
12953 0, // GR64PLTSafe:sub_t0
12954 0, // GR64PLTSafe:sub_t1
12955 0, // GR64PLTSafe:sub_xmm
12956 0, // GR64PLTSafe:sub_ymm
12957 },
12958 { // GR64_TC
12959 3, // GR64_TC:sub_8bit -> GR8_NOREX2
12960 5, // GR64_TC:sub_8bit_hi -> GR8_ABCD_H
12961 0, // GR64_TC:sub_8bit_hi_phony
12962 9, // GR64_TC:sub_16bit -> GR16_NOREX2
12963 0, // GR64_TC:sub_16bit_hi
12964 41, // GR64_TC:sub_32bit -> GR32_NOREX2
12965 0, // GR64_TC:sub_mask_0
12966 0, // GR64_TC:sub_mask_1
12967 0, // GR64_TC:sub_t0
12968 0, // GR64_TC:sub_t1
12969 0, // GR64_TC:sub_xmm
12970 0, // GR64_TC:sub_ymm
12971 },
12972 { // GR64_NOREX
12973 3, // GR64_NOREX:sub_8bit -> GR8_NOREX2
12974 5, // GR64_NOREX:sub_8bit_hi -> GR8_ABCD_H
12975 0, // GR64_NOREX:sub_8bit_hi_phony
12976 10, // GR64_NOREX:sub_16bit -> GR16_NOREX
12977 0, // GR64_NOREX:sub_16bit_hi
12978 44, // GR64_NOREX:sub_32bit -> GR32_NOREX
12979 0, // GR64_NOREX:sub_mask_0
12980 0, // GR64_NOREX:sub_mask_1
12981 0, // GR64_NOREX:sub_t0
12982 0, // GR64_NOREX:sub_t1
12983 0, // GR64_NOREX:sub_xmm
12984 0, // GR64_NOREX:sub_ymm
12985 },
12986 { // GR64_TCW64
12987 3, // GR64_TCW64:sub_8bit -> GR8_NOREX2
12988 5, // GR64_TCW64:sub_8bit_hi -> GR8_ABCD_H
12989 0, // GR64_TCW64:sub_8bit_hi_phony
12990 9, // GR64_TCW64:sub_16bit -> GR16_NOREX2
12991 0, // GR64_TCW64:sub_16bit_hi
12992 41, // GR64_TCW64:sub_32bit -> GR32_NOREX2
12993 0, // GR64_TCW64:sub_mask_0
12994 0, // GR64_TCW64:sub_mask_1
12995 0, // GR64_TCW64:sub_t0
12996 0, // GR64_TCW64:sub_t1
12997 0, // GR64_TCW64:sub_xmm
12998 0, // GR64_TCW64:sub_ymm
12999 },
13000 { // GR64_TC_with_sub_8bit
13001 3, // GR64_TC_with_sub_8bit:sub_8bit -> GR8_NOREX2
13002 5, // GR64_TC_with_sub_8bit:sub_8bit_hi -> GR8_ABCD_H
13003 0, // GR64_TC_with_sub_8bit:sub_8bit_hi_phony
13004 9, // GR64_TC_with_sub_8bit:sub_16bit -> GR16_NOREX2
13005 0, // GR64_TC_with_sub_8bit:sub_16bit_hi
13006 41, // GR64_TC_with_sub_8bit:sub_32bit -> GR32_NOREX2
13007 0, // GR64_TC_with_sub_8bit:sub_mask_0
13008 0, // GR64_TC_with_sub_8bit:sub_mask_1
13009 0, // GR64_TC_with_sub_8bit:sub_t0
13010 0, // GR64_TC_with_sub_8bit:sub_t1
13011 0, // GR64_TC_with_sub_8bit:sub_xmm
13012 0, // GR64_TC_with_sub_8bit:sub_ymm
13013 },
13014 { // GR64_NOREX2_NOSP_and_GR64_TC
13015 3, // GR64_NOREX2_NOSP_and_GR64_TC:sub_8bit -> GR8_NOREX2
13016 5, // GR64_NOREX2_NOSP_and_GR64_TC:sub_8bit_hi -> GR8_ABCD_H
13017 0, // GR64_NOREX2_NOSP_and_GR64_TC:sub_8bit_hi_phony
13018 9, // GR64_NOREX2_NOSP_and_GR64_TC:sub_16bit -> GR16_NOREX2
13019 0, // GR64_NOREX2_NOSP_and_GR64_TC:sub_16bit_hi
13020 42, // GR64_NOREX2_NOSP_and_GR64_TC:sub_32bit -> GR32_NOREX2_NOSP
13021 0, // GR64_NOREX2_NOSP_and_GR64_TC:sub_mask_0
13022 0, // GR64_NOREX2_NOSP_and_GR64_TC:sub_mask_1
13023 0, // GR64_NOREX2_NOSP_and_GR64_TC:sub_t0
13024 0, // GR64_NOREX2_NOSP_and_GR64_TC:sub_t1
13025 0, // GR64_NOREX2_NOSP_and_GR64_TC:sub_xmm
13026 0, // GR64_NOREX2_NOSP_and_GR64_TC:sub_ymm
13027 },
13028 { // GR64_TCW64_with_sub_8bit
13029 3, // GR64_TCW64_with_sub_8bit:sub_8bit -> GR8_NOREX2
13030 5, // GR64_TCW64_with_sub_8bit:sub_8bit_hi -> GR8_ABCD_H
13031 0, // GR64_TCW64_with_sub_8bit:sub_8bit_hi_phony
13032 9, // GR64_TCW64_with_sub_8bit:sub_16bit -> GR16_NOREX2
13033 0, // GR64_TCW64_with_sub_8bit:sub_16bit_hi
13034 41, // GR64_TCW64_with_sub_8bit:sub_32bit -> GR32_NOREX2
13035 0, // GR64_TCW64_with_sub_8bit:sub_mask_0
13036 0, // GR64_TCW64_with_sub_8bit:sub_mask_1
13037 0, // GR64_TCW64_with_sub_8bit:sub_t0
13038 0, // GR64_TCW64_with_sub_8bit:sub_t1
13039 0, // GR64_TCW64_with_sub_8bit:sub_xmm
13040 0, // GR64_TCW64_with_sub_8bit:sub_ymm
13041 },
13042 { // GR64_TC_and_GR64_TCW64
13043 3, // GR64_TC_and_GR64_TCW64:sub_8bit -> GR8_NOREX2
13044 5, // GR64_TC_and_GR64_TCW64:sub_8bit_hi -> GR8_ABCD_H
13045 0, // GR64_TC_and_GR64_TCW64:sub_8bit_hi_phony
13046 9, // GR64_TC_and_GR64_TCW64:sub_16bit -> GR16_NOREX2
13047 0, // GR64_TC_and_GR64_TCW64:sub_16bit_hi
13048 41, // GR64_TC_and_GR64_TCW64:sub_32bit -> GR32_NOREX2
13049 0, // GR64_TC_and_GR64_TCW64:sub_mask_0
13050 0, // GR64_TC_and_GR64_TCW64:sub_mask_1
13051 0, // GR64_TC_and_GR64_TCW64:sub_t0
13052 0, // GR64_TC_and_GR64_TCW64:sub_t1
13053 0, // GR64_TC_and_GR64_TCW64:sub_xmm
13054 0, // GR64_TC_and_GR64_TCW64:sub_ymm
13055 },
13056 { // GR64_with_sub_16bit_in_GR16_NOREX
13057 3, // GR64_with_sub_16bit_in_GR16_NOREX:sub_8bit -> GR8_NOREX2
13058 5, // GR64_with_sub_16bit_in_GR16_NOREX:sub_8bit_hi -> GR8_ABCD_H
13059 0, // GR64_with_sub_16bit_in_GR16_NOREX:sub_8bit_hi_phony
13060 10, // GR64_with_sub_16bit_in_GR16_NOREX:sub_16bit -> GR16_NOREX
13061 0, // GR64_with_sub_16bit_in_GR16_NOREX:sub_16bit_hi
13062 44, // GR64_with_sub_16bit_in_GR16_NOREX:sub_32bit -> GR32_NOREX
13063 0, // GR64_with_sub_16bit_in_GR16_NOREX:sub_mask_0
13064 0, // GR64_with_sub_16bit_in_GR16_NOREX:sub_mask_1
13065 0, // GR64_with_sub_16bit_in_GR16_NOREX:sub_t0
13066 0, // GR64_with_sub_16bit_in_GR16_NOREX:sub_t1
13067 0, // GR64_with_sub_16bit_in_GR16_NOREX:sub_xmm
13068 0, // GR64_with_sub_16bit_in_GR16_NOREX:sub_ymm
13069 },
13070 { // VK64
13071 0, // VK64:sub_8bit
13072 0, // VK64:sub_8bit_hi
13073 0, // VK64:sub_8bit_hi_phony
13074 0, // VK64:sub_16bit
13075 0, // VK64:sub_16bit_hi
13076 0, // VK64:sub_32bit
13077 0, // VK64:sub_mask_0
13078 0, // VK64:sub_mask_1
13079 0, // VK64:sub_t0
13080 0, // VK64:sub_t1
13081 0, // VK64:sub_xmm
13082 0, // VK64:sub_ymm
13083 },
13084 { // VR64
13085 0, // VR64:sub_8bit
13086 0, // VR64:sub_8bit_hi
13087 0, // VR64:sub_8bit_hi_phony
13088 0, // VR64:sub_16bit
13089 0, // VR64:sub_16bit_hi
13090 0, // VR64:sub_32bit
13091 0, // VR64:sub_mask_0
13092 0, // VR64:sub_mask_1
13093 0, // VR64:sub_t0
13094 0, // VR64:sub_t1
13095 0, // VR64:sub_xmm
13096 0, // VR64:sub_ymm
13097 },
13098 { // GR64PLTSafe_and_GR64_TC
13099 3, // GR64PLTSafe_and_GR64_TC:sub_8bit -> GR8_NOREX2
13100 5, // GR64PLTSafe_and_GR64_TC:sub_8bit_hi -> GR8_ABCD_H
13101 0, // GR64PLTSafe_and_GR64_TC:sub_8bit_hi_phony
13102 9, // GR64PLTSafe_and_GR64_TC:sub_16bit -> GR16_NOREX2
13103 0, // GR64PLTSafe_and_GR64_TC:sub_16bit_hi
13104 42, // GR64PLTSafe_and_GR64_TC:sub_32bit -> GR32_NOREX2_NOSP
13105 0, // GR64PLTSafe_and_GR64_TC:sub_mask_0
13106 0, // GR64PLTSafe_and_GR64_TC:sub_mask_1
13107 0, // GR64PLTSafe_and_GR64_TC:sub_t0
13108 0, // GR64PLTSafe_and_GR64_TC:sub_t1
13109 0, // GR64PLTSafe_and_GR64_TC:sub_xmm
13110 0, // GR64PLTSafe_and_GR64_TC:sub_ymm
13111 },
13112 { // GR64_NOREX2_NOSP_and_GR64_TCW64
13113 3, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_8bit -> GR8_NOREX2
13114 5, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_8bit_hi -> GR8_ABCD_H
13115 0, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_8bit_hi_phony
13116 9, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_16bit -> GR16_NOREX2
13117 0, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_16bit_hi
13118 42, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_32bit -> GR32_NOREX2_NOSP
13119 0, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_mask_0
13120 0, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_mask_1
13121 0, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_t0
13122 0, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_t1
13123 0, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_xmm
13124 0, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_ymm
13125 },
13126 { // GR64_NOREX_NOSP
13127 3, // GR64_NOREX_NOSP:sub_8bit -> GR8_NOREX2
13128 5, // GR64_NOREX_NOSP:sub_8bit_hi -> GR8_ABCD_H
13129 0, // GR64_NOREX_NOSP:sub_8bit_hi_phony
13130 10, // GR64_NOREX_NOSP:sub_16bit -> GR16_NOREX
13131 0, // GR64_NOREX_NOSP:sub_16bit_hi
13132 46, // GR64_NOREX_NOSP:sub_32bit -> GR32_NOREX_NOSP
13133 0, // GR64_NOREX_NOSP:sub_mask_0
13134 0, // GR64_NOREX_NOSP:sub_mask_1
13135 0, // GR64_NOREX_NOSP:sub_t0
13136 0, // GR64_NOREX_NOSP:sub_t1
13137 0, // GR64_NOREX_NOSP:sub_xmm
13138 0, // GR64_NOREX_NOSP:sub_ymm
13139 },
13140 { // GR64_NOREX_and_GR64_TC
13141 3, // GR64_NOREX_and_GR64_TC:sub_8bit -> GR8_NOREX2
13142 5, // GR64_NOREX_and_GR64_TC:sub_8bit_hi -> GR8_ABCD_H
13143 0, // GR64_NOREX_and_GR64_TC:sub_8bit_hi_phony
13144 10, // GR64_NOREX_and_GR64_TC:sub_16bit -> GR16_NOREX
13145 0, // GR64_NOREX_and_GR64_TC:sub_16bit_hi
13146 44, // GR64_NOREX_and_GR64_TC:sub_32bit -> GR32_NOREX
13147 0, // GR64_NOREX_and_GR64_TC:sub_mask_0
13148 0, // GR64_NOREX_and_GR64_TC:sub_mask_1
13149 0, // GR64_NOREX_and_GR64_TC:sub_t0
13150 0, // GR64_NOREX_and_GR64_TC:sub_t1
13151 0, // GR64_NOREX_and_GR64_TC:sub_xmm
13152 0, // GR64_NOREX_and_GR64_TC:sub_ymm
13153 },
13154 { // GR64_TCW64_and_GR64_TC_with_sub_8bit
13155 3, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_8bit -> GR8_NOREX2
13156 5, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_8bit_hi -> GR8_ABCD_H
13157 0, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_8bit_hi_phony
13158 9, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_16bit -> GR16_NOREX2
13159 0, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_16bit_hi
13160 41, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_32bit -> GR32_NOREX2
13161 0, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_mask_0
13162 0, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_mask_1
13163 0, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_t0
13164 0, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_t1
13165 0, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_xmm
13166 0, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_ymm
13167 },
13168 { // VK64WM
13169 0, // VK64WM:sub_8bit
13170 0, // VK64WM:sub_8bit_hi
13171 0, // VK64WM:sub_8bit_hi_phony
13172 0, // VK64WM:sub_16bit
13173 0, // VK64WM:sub_16bit_hi
13174 0, // VK64WM:sub_32bit
13175 0, // VK64WM:sub_mask_0
13176 0, // VK64WM:sub_mask_1
13177 0, // VK64WM:sub_t0
13178 0, // VK64WM:sub_t1
13179 0, // VK64WM:sub_xmm
13180 0, // VK64WM:sub_ymm
13181 },
13182 { // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
13183 3, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_8bit -> GR8_NOREX2
13184 5, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_8bit_hi -> GR8_ABCD_H
13185 0, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_8bit_hi_phony
13186 9, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_16bit -> GR16_NOREX2
13187 0, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_16bit_hi
13188 42, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_32bit -> GR32_NOREX2_NOSP
13189 0, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_mask_0
13190 0, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_mask_1
13191 0, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_t0
13192 0, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_t1
13193 0, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_xmm
13194 0, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_ymm
13195 },
13196 { // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
13197 3, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_8bit -> GR8_NOREX2
13198 5, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_8bit_hi -> GR8_ABCD_H
13199 0, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_8bit_hi_phony
13200 10, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_16bit -> GR16_NOREX
13201 0, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_16bit_hi
13202 44, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_32bit -> GR32_NOREX
13203 0, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_mask_0
13204 0, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_mask_1
13205 0, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_t0
13206 0, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_t1
13207 0, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_xmm
13208 0, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_ymm
13209 },
13210 { // GR64PLTSafe_and_GR64_TCW64
13211 3, // GR64PLTSafe_and_GR64_TCW64:sub_8bit -> GR8_NOREX2
13212 5, // GR64PLTSafe_and_GR64_TCW64:sub_8bit_hi -> GR8_ABCD_H
13213 0, // GR64PLTSafe_and_GR64_TCW64:sub_8bit_hi_phony
13214 9, // GR64PLTSafe_and_GR64_TCW64:sub_16bit -> GR16_NOREX2
13215 0, // GR64PLTSafe_and_GR64_TCW64:sub_16bit_hi
13216 42, // GR64PLTSafe_and_GR64_TCW64:sub_32bit -> GR32_NOREX2_NOSP
13217 0, // GR64PLTSafe_and_GR64_TCW64:sub_mask_0
13218 0, // GR64PLTSafe_and_GR64_TCW64:sub_mask_1
13219 0, // GR64PLTSafe_and_GR64_TCW64:sub_t0
13220 0, // GR64PLTSafe_and_GR64_TCW64:sub_t1
13221 0, // GR64PLTSafe_and_GR64_TCW64:sub_xmm
13222 0, // GR64PLTSafe_and_GR64_TCW64:sub_ymm
13223 },
13224 { // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
13225 3, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_8bit -> GR8_NOREX2
13226 5, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_8bit_hi -> GR8_ABCD_H
13227 0, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_8bit_hi_phony
13228 10, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_16bit -> GR16_NOREX
13229 0, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_16bit_hi
13230 46, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_32bit -> GR32_NOREX_NOSP
13231 0, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_mask_0
13232 0, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_mask_1
13233 0, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_t0
13234 0, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_t1
13235 0, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_xmm
13236 0, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_ymm
13237 },
13238 { // GR64_NOREX_and_GR64_TCW64
13239 3, // GR64_NOREX_and_GR64_TCW64:sub_8bit -> GR8_NOREX2
13240 5, // GR64_NOREX_and_GR64_TCW64:sub_8bit_hi -> GR8_ABCD_H
13241 0, // GR64_NOREX_and_GR64_TCW64:sub_8bit_hi_phony
13242 10, // GR64_NOREX_and_GR64_TCW64:sub_16bit -> GR16_NOREX
13243 0, // GR64_NOREX_and_GR64_TCW64:sub_16bit_hi
13244 50, // GR64_NOREX_and_GR64_TCW64:sub_32bit -> GR32_TC
13245 0, // GR64_NOREX_and_GR64_TCW64:sub_mask_0
13246 0, // GR64_NOREX_and_GR64_TCW64:sub_mask_1
13247 0, // GR64_NOREX_and_GR64_TCW64:sub_t0
13248 0, // GR64_NOREX_and_GR64_TCW64:sub_t1
13249 0, // GR64_NOREX_and_GR64_TCW64:sub_xmm
13250 0, // GR64_NOREX_and_GR64_TCW64:sub_ymm
13251 },
13252 { // GR64_ABCD
13253 6, // GR64_ABCD:sub_8bit -> GR8_ABCD_L
13254 5, // GR64_ABCD:sub_8bit_hi -> GR8_ABCD_H
13255 0, // GR64_ABCD:sub_8bit_hi_phony
13256 22, // GR64_ABCD:sub_16bit -> GR16_ABCD
13257 0, // GR64_ABCD:sub_16bit_hi
13258 49, // GR64_ABCD:sub_32bit -> GR32_ABCD
13259 0, // GR64_ABCD:sub_mask_0
13260 0, // GR64_ABCD:sub_mask_1
13261 0, // GR64_ABCD:sub_t0
13262 0, // GR64_ABCD:sub_t1
13263 0, // GR64_ABCD:sub_xmm
13264 0, // GR64_ABCD:sub_ymm
13265 },
13266 { // GR64_with_sub_32bit_in_GR32_TC
13267 3, // GR64_with_sub_32bit_in_GR32_TC:sub_8bit -> GR8_NOREX2
13268 5, // GR64_with_sub_32bit_in_GR32_TC:sub_8bit_hi -> GR8_ABCD_H
13269 0, // GR64_with_sub_32bit_in_GR32_TC:sub_8bit_hi_phony
13270 10, // GR64_with_sub_32bit_in_GR32_TC:sub_16bit -> GR16_NOREX
13271 0, // GR64_with_sub_32bit_in_GR32_TC:sub_16bit_hi
13272 50, // GR64_with_sub_32bit_in_GR32_TC:sub_32bit -> GR32_TC
13273 0, // GR64_with_sub_32bit_in_GR32_TC:sub_mask_0
13274 0, // GR64_with_sub_32bit_in_GR32_TC:sub_mask_1
13275 0, // GR64_with_sub_32bit_in_GR32_TC:sub_t0
13276 0, // GR64_with_sub_32bit_in_GR32_TC:sub_t1
13277 0, // GR64_with_sub_32bit_in_GR32_TC:sub_xmm
13278 0, // GR64_with_sub_32bit_in_GR32_TC:sub_ymm
13279 },
13280 { // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
13281 6, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_8bit -> GR8_ABCD_L
13282 5, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_8bit_hi -> GR8_ABCD_H
13283 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_8bit_hi_phony
13284 22, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_16bit -> GR16_ABCD
13285 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_16bit_hi
13286 51, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_32bit -> GR32_ABCD_and_GR32_TC
13287 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_mask_0
13288 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_mask_1
13289 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_t0
13290 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_t1
13291 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_xmm
13292 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_ymm
13293 },
13294 { // GR64_AD
13295 6, // GR64_AD:sub_8bit -> GR8_ABCD_L
13296 5, // GR64_AD:sub_8bit_hi -> GR8_ABCD_H
13297 0, // GR64_AD:sub_8bit_hi_phony
13298 22, // GR64_AD:sub_16bit -> GR16_ABCD
13299 0, // GR64_AD:sub_16bit_hi
13300 52, // GR64_AD:sub_32bit -> GR32_AD
13301 0, // GR64_AD:sub_mask_0
13302 0, // GR64_AD:sub_mask_1
13303 0, // GR64_AD:sub_t0
13304 0, // GR64_AD:sub_t1
13305 0, // GR64_AD:sub_xmm
13306 0, // GR64_AD:sub_ymm
13307 },
13308 { // GR64_ArgRef
13309 3, // GR64_ArgRef:sub_8bit -> GR8_NOREX2
13310 0, // GR64_ArgRef:sub_8bit_hi
13311 0, // GR64_ArgRef:sub_8bit_hi_phony
13312 9, // GR64_ArgRef:sub_16bit -> GR16_NOREX2
13313 0, // GR64_ArgRef:sub_16bit_hi
13314 42, // GR64_ArgRef:sub_32bit -> GR32_NOREX2_NOSP
13315 0, // GR64_ArgRef:sub_mask_0
13316 0, // GR64_ArgRef:sub_mask_1
13317 0, // GR64_ArgRef:sub_t0
13318 0, // GR64_ArgRef:sub_t1
13319 0, // GR64_ArgRef:sub_xmm
13320 0, // GR64_ArgRef:sub_ymm
13321 },
13322 { // GR64_and_LOW32_ADDR_ACCESS_RBP
13323 3, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_8bit -> GR8_NOREX2
13324 0, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_8bit_hi
13325 0, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_8bit_hi_phony
13326 10, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_16bit -> GR16_NOREX
13327 0, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_16bit_hi
13328 66, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_32bit -> GR32_BPSP_and_GR32_DIBP
13329 0, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_mask_0
13330 0, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_mask_1
13331 0, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_t0
13332 0, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_t1
13333 0, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_xmm
13334 0, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_ymm
13335 },
13336 { // GR64_with_sub_32bit_in_GR32_ArgRef
13337 6, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_8bit -> GR8_ABCD_L
13338 5, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_8bit_hi -> GR8_ABCD_H
13339 0, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_8bit_hi_phony
13340 22, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_16bit -> GR16_ABCD
13341 0, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_16bit_hi
13342 53, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_32bit -> GR32_ArgRef
13343 0, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_mask_0
13344 0, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_mask_1
13345 0, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_t0
13346 0, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_t1
13347 0, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_xmm
13348 0, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_ymm
13349 },
13350 { // GR64_with_sub_32bit_in_GR32_BPSP
13351 3, // GR64_with_sub_32bit_in_GR32_BPSP:sub_8bit -> GR8_NOREX2
13352 0, // GR64_with_sub_32bit_in_GR32_BPSP:sub_8bit_hi
13353 0, // GR64_with_sub_32bit_in_GR32_BPSP:sub_8bit_hi_phony
13354 10, // GR64_with_sub_32bit_in_GR32_BPSP:sub_16bit -> GR16_NOREX
13355 0, // GR64_with_sub_32bit_in_GR32_BPSP:sub_16bit_hi
13356 54, // GR64_with_sub_32bit_in_GR32_BPSP:sub_32bit -> GR32_BPSP
13357 0, // GR64_with_sub_32bit_in_GR32_BPSP:sub_mask_0
13358 0, // GR64_with_sub_32bit_in_GR32_BPSP:sub_mask_1
13359 0, // GR64_with_sub_32bit_in_GR32_BPSP:sub_t0
13360 0, // GR64_with_sub_32bit_in_GR32_BPSP:sub_t1
13361 0, // GR64_with_sub_32bit_in_GR32_BPSP:sub_xmm
13362 0, // GR64_with_sub_32bit_in_GR32_BPSP:sub_ymm
13363 },
13364 { // GR64_with_sub_32bit_in_GR32_BSI
13365 3, // GR64_with_sub_32bit_in_GR32_BSI:sub_8bit -> GR8_NOREX2
13366 5, // GR64_with_sub_32bit_in_GR32_BSI:sub_8bit_hi -> GR8_ABCD_H
13367 0, // GR64_with_sub_32bit_in_GR32_BSI:sub_8bit_hi_phony
13368 10, // GR64_with_sub_32bit_in_GR32_BSI:sub_16bit -> GR16_NOREX
13369 0, // GR64_with_sub_32bit_in_GR32_BSI:sub_16bit_hi
13370 55, // GR64_with_sub_32bit_in_GR32_BSI:sub_32bit -> GR32_BSI
13371 0, // GR64_with_sub_32bit_in_GR32_BSI:sub_mask_0
13372 0, // GR64_with_sub_32bit_in_GR32_BSI:sub_mask_1
13373 0, // GR64_with_sub_32bit_in_GR32_BSI:sub_t0
13374 0, // GR64_with_sub_32bit_in_GR32_BSI:sub_t1
13375 0, // GR64_with_sub_32bit_in_GR32_BSI:sub_xmm
13376 0, // GR64_with_sub_32bit_in_GR32_BSI:sub_ymm
13377 },
13378 { // GR64_with_sub_32bit_in_GR32_CB
13379 6, // GR64_with_sub_32bit_in_GR32_CB:sub_8bit -> GR8_ABCD_L
13380 5, // GR64_with_sub_32bit_in_GR32_CB:sub_8bit_hi -> GR8_ABCD_H
13381 0, // GR64_with_sub_32bit_in_GR32_CB:sub_8bit_hi_phony
13382 22, // GR64_with_sub_32bit_in_GR32_CB:sub_16bit -> GR16_ABCD
13383 0, // GR64_with_sub_32bit_in_GR32_CB:sub_16bit_hi
13384 56, // GR64_with_sub_32bit_in_GR32_CB:sub_32bit -> GR32_CB
13385 0, // GR64_with_sub_32bit_in_GR32_CB:sub_mask_0
13386 0, // GR64_with_sub_32bit_in_GR32_CB:sub_mask_1
13387 0, // GR64_with_sub_32bit_in_GR32_CB:sub_t0
13388 0, // GR64_with_sub_32bit_in_GR32_CB:sub_t1
13389 0, // GR64_with_sub_32bit_in_GR32_CB:sub_xmm
13390 0, // GR64_with_sub_32bit_in_GR32_CB:sub_ymm
13391 },
13392 { // GR64_with_sub_32bit_in_GR32_DIBP
13393 3, // GR64_with_sub_32bit_in_GR32_DIBP:sub_8bit -> GR8_NOREX2
13394 0, // GR64_with_sub_32bit_in_GR32_DIBP:sub_8bit_hi
13395 0, // GR64_with_sub_32bit_in_GR32_DIBP:sub_8bit_hi_phony
13396 10, // GR64_with_sub_32bit_in_GR32_DIBP:sub_16bit -> GR16_NOREX
13397 0, // GR64_with_sub_32bit_in_GR32_DIBP:sub_16bit_hi
13398 58, // GR64_with_sub_32bit_in_GR32_DIBP:sub_32bit -> GR32_DIBP
13399 0, // GR64_with_sub_32bit_in_GR32_DIBP:sub_mask_0
13400 0, // GR64_with_sub_32bit_in_GR32_DIBP:sub_mask_1
13401 0, // GR64_with_sub_32bit_in_GR32_DIBP:sub_t0
13402 0, // GR64_with_sub_32bit_in_GR32_DIBP:sub_t1
13403 0, // GR64_with_sub_32bit_in_GR32_DIBP:sub_xmm
13404 0, // GR64_with_sub_32bit_in_GR32_DIBP:sub_ymm
13405 },
13406 { // GR64_with_sub_32bit_in_GR32_SIDI
13407 3, // GR64_with_sub_32bit_in_GR32_SIDI:sub_8bit -> GR8_NOREX2
13408 0, // GR64_with_sub_32bit_in_GR32_SIDI:sub_8bit_hi
13409 0, // GR64_with_sub_32bit_in_GR32_SIDI:sub_8bit_hi_phony
13410 10, // GR64_with_sub_32bit_in_GR32_SIDI:sub_16bit -> GR16_NOREX
13411 0, // GR64_with_sub_32bit_in_GR32_SIDI:sub_16bit_hi
13412 59, // GR64_with_sub_32bit_in_GR32_SIDI:sub_32bit -> GR32_SIDI
13413 0, // GR64_with_sub_32bit_in_GR32_SIDI:sub_mask_0
13414 0, // GR64_with_sub_32bit_in_GR32_SIDI:sub_mask_1
13415 0, // GR64_with_sub_32bit_in_GR32_SIDI:sub_t0
13416 0, // GR64_with_sub_32bit_in_GR32_SIDI:sub_t1
13417 0, // GR64_with_sub_32bit_in_GR32_SIDI:sub_xmm
13418 0, // GR64_with_sub_32bit_in_GR32_SIDI:sub_ymm
13419 },
13420 { // GR64_A
13421 6, // GR64_A:sub_8bit -> GR8_ABCD_L
13422 5, // GR64_A:sub_8bit_hi -> GR8_ABCD_H
13423 0, // GR64_A:sub_8bit_hi_phony
13424 22, // GR64_A:sub_16bit -> GR16_ABCD
13425 0, // GR64_A:sub_16bit_hi
13426 52, // GR64_A:sub_32bit -> GR32_AD
13427 0, // GR64_A:sub_mask_0
13428 0, // GR64_A:sub_mask_1
13429 0, // GR64_A:sub_t0
13430 0, // GR64_A:sub_t1
13431 0, // GR64_A:sub_xmm
13432 0, // GR64_A:sub_ymm
13433 },
13434 { // GR64_ArgRef_and_GR64_TC
13435 3, // GR64_ArgRef_and_GR64_TC:sub_8bit -> GR8_NOREX2
13436 0, // GR64_ArgRef_and_GR64_TC:sub_8bit_hi
13437 0, // GR64_ArgRef_and_GR64_TC:sub_8bit_hi_phony
13438 9, // GR64_ArgRef_and_GR64_TC:sub_16bit -> GR16_NOREX2
13439 0, // GR64_ArgRef_and_GR64_TC:sub_16bit_hi
13440 42, // GR64_ArgRef_and_GR64_TC:sub_32bit -> GR32_NOREX2_NOSP
13441 0, // GR64_ArgRef_and_GR64_TC:sub_mask_0
13442 0, // GR64_ArgRef_and_GR64_TC:sub_mask_1
13443 0, // GR64_ArgRef_and_GR64_TC:sub_t0
13444 0, // GR64_ArgRef_and_GR64_TC:sub_t1
13445 0, // GR64_ArgRef_and_GR64_TC:sub_xmm
13446 0, // GR64_ArgRef_and_GR64_TC:sub_ymm
13447 },
13448 { // GR64_and_LOW32_ADDR_ACCESS
13449 0, // GR64_and_LOW32_ADDR_ACCESS:sub_8bit
13450 0, // GR64_and_LOW32_ADDR_ACCESS:sub_8bit_hi
13451 0, // GR64_and_LOW32_ADDR_ACCESS:sub_8bit_hi_phony
13452 0, // GR64_and_LOW32_ADDR_ACCESS:sub_16bit
13453 0, // GR64_and_LOW32_ADDR_ACCESS:sub_16bit_hi
13454 0, // GR64_and_LOW32_ADDR_ACCESS:sub_32bit
13455 0, // GR64_and_LOW32_ADDR_ACCESS:sub_mask_0
13456 0, // GR64_and_LOW32_ADDR_ACCESS:sub_mask_1
13457 0, // GR64_and_LOW32_ADDR_ACCESS:sub_t0
13458 0, // GR64_and_LOW32_ADDR_ACCESS:sub_t1
13459 0, // GR64_and_LOW32_ADDR_ACCESS:sub_xmm
13460 0, // GR64_and_LOW32_ADDR_ACCESS:sub_ymm
13461 },
13462 { // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
13463 6, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_8bit -> GR8_ABCD_L
13464 5, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_8bit_hi -> GR8_ABCD_H
13465 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_8bit_hi_phony
13466 22, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_16bit -> GR16_ABCD
13467 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_16bit_hi
13468 63, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_32bit -> GR32_ABCD_and_GR32_BSI
13469 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_mask_0
13470 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_mask_1
13471 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_t0
13472 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_t1
13473 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_xmm
13474 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_ymm
13475 },
13476 { // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
13477 6, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_8bit -> GR8_ABCD_L
13478 5, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_8bit_hi -> GR8_ABCD_H
13479 0, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_8bit_hi_phony
13480 22, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_16bit -> GR16_ABCD
13481 0, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_16bit_hi
13482 64, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_32bit -> GR32_AD_and_GR32_ArgRef
13483 0, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_mask_0
13484 0, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_mask_1
13485 0, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_t0
13486 0, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_t1
13487 0, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_xmm
13488 0, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_ymm
13489 },
13490 { // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
13491 6, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_8bit -> GR8_ABCD_L
13492 5, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_8bit_hi -> GR8_ABCD_H
13493 0, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_8bit_hi_phony
13494 22, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_16bit -> GR16_ABCD
13495 0, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_16bit_hi
13496 65, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_32bit -> GR32_ArgRef_and_GR32_CB
13497 0, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_mask_0
13498 0, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_mask_1
13499 0, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_t0
13500 0, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_t1
13501 0, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_xmm
13502 0, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_ymm
13503 },
13504 { // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
13505 3, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_8bit -> GR8_NOREX2
13506 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_8bit_hi
13507 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_8bit_hi_phony
13508 10, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_16bit -> GR16_NOREX
13509 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_16bit_hi
13510 66, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_32bit -> GR32_BPSP_and_GR32_DIBP
13511 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_mask_0
13512 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_mask_1
13513 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_t0
13514 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_t1
13515 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_xmm
13516 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_ymm
13517 },
13518 { // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
13519 3, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_8bit -> GR8_NOREX2
13520 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_8bit_hi
13521 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_8bit_hi_phony
13522 10, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_16bit -> GR16_NOREX
13523 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_16bit_hi
13524 67, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_32bit -> GR32_BPSP_and_GR32_TC
13525 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_mask_0
13526 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_mask_1
13527 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_t0
13528 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_t1
13529 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_xmm
13530 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_ymm
13531 },
13532 { // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
13533 3, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_8bit -> GR8_NOREX2
13534 0, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_8bit_hi
13535 0, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_8bit_hi_phony
13536 10, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_16bit -> GR16_NOREX
13537 0, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_16bit_hi
13538 68, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_32bit -> GR32_BSI_and_GR32_SIDI
13539 0, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_mask_0
13540 0, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_mask_1
13541 0, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_t0
13542 0, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_t1
13543 0, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_xmm
13544 0, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_ymm
13545 },
13546 { // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
13547 3, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_8bit -> GR8_NOREX2
13548 0, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_8bit_hi
13549 0, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_8bit_hi_phony
13550 10, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_16bit -> GR16_NOREX
13551 0, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_16bit_hi
13552 69, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_32bit -> GR32_DIBP_and_GR32_SIDI
13553 0, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_mask_0
13554 0, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_mask_1
13555 0, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_t0
13556 0, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_t1
13557 0, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_xmm
13558 0, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_ymm
13559 },
13560 { // RST
13561 0, // RST:sub_8bit
13562 0, // RST:sub_8bit_hi
13563 0, // RST:sub_8bit_hi_phony
13564 0, // RST:sub_16bit
13565 0, // RST:sub_16bit_hi
13566 0, // RST:sub_32bit
13567 0, // RST:sub_mask_0
13568 0, // RST:sub_mask_1
13569 0, // RST:sub_t0
13570 0, // RST:sub_t1
13571 0, // RST:sub_xmm
13572 0, // RST:sub_ymm
13573 },
13574 { // RFP80
13575 0, // RFP80:sub_8bit
13576 0, // RFP80:sub_8bit_hi
13577 0, // RFP80:sub_8bit_hi_phony
13578 0, // RFP80:sub_16bit
13579 0, // RFP80:sub_16bit_hi
13580 0, // RFP80:sub_32bit
13581 0, // RFP80:sub_mask_0
13582 0, // RFP80:sub_mask_1
13583 0, // RFP80:sub_t0
13584 0, // RFP80:sub_t1
13585 0, // RFP80:sub_xmm
13586 0, // RFP80:sub_ymm
13587 },
13588 { // RFP80_7
13589 0, // RFP80_7:sub_8bit
13590 0, // RFP80_7:sub_8bit_hi
13591 0, // RFP80_7:sub_8bit_hi_phony
13592 0, // RFP80_7:sub_16bit
13593 0, // RFP80_7:sub_16bit_hi
13594 0, // RFP80_7:sub_32bit
13595 0, // RFP80_7:sub_mask_0
13596 0, // RFP80_7:sub_mask_1
13597 0, // RFP80_7:sub_t0
13598 0, // RFP80_7:sub_t1
13599 0, // RFP80_7:sub_xmm
13600 0, // RFP80_7:sub_ymm
13601 },
13602 { // VR128X
13603 0, // VR128X:sub_8bit
13604 0, // VR128X:sub_8bit_hi
13605 0, // VR128X:sub_8bit_hi_phony
13606 0, // VR128X:sub_16bit
13607 0, // VR128X:sub_16bit_hi
13608 0, // VR128X:sub_32bit
13609 0, // VR128X:sub_mask_0
13610 0, // VR128X:sub_mask_1
13611 0, // VR128X:sub_t0
13612 0, // VR128X:sub_t1
13613 0, // VR128X:sub_xmm
13614 0, // VR128X:sub_ymm
13615 },
13616 { // VR128
13617 0, // VR128:sub_8bit
13618 0, // VR128:sub_8bit_hi
13619 0, // VR128:sub_8bit_hi_phony
13620 0, // VR128:sub_16bit
13621 0, // VR128:sub_16bit_hi
13622 0, // VR128:sub_32bit
13623 0, // VR128:sub_mask_0
13624 0, // VR128:sub_mask_1
13625 0, // VR128:sub_t0
13626 0, // VR128:sub_t1
13627 0, // VR128:sub_xmm
13628 0, // VR128:sub_ymm
13629 },
13630 { // VR256X
13631 0, // VR256X:sub_8bit
13632 0, // VR256X:sub_8bit_hi
13633 0, // VR256X:sub_8bit_hi_phony
13634 0, // VR256X:sub_16bit
13635 0, // VR256X:sub_16bit_hi
13636 0, // VR256X:sub_32bit
13637 0, // VR256X:sub_mask_0
13638 0, // VR256X:sub_mask_1
13639 0, // VR256X:sub_t0
13640 0, // VR256X:sub_t1
13641 24, // VR256X:sub_xmm -> FR16X
13642 0, // VR256X:sub_ymm
13643 },
13644 { // VR256
13645 0, // VR256:sub_8bit
13646 0, // VR256:sub_8bit_hi
13647 0, // VR256:sub_8bit_hi_phony
13648 0, // VR256:sub_16bit
13649 0, // VR256:sub_16bit_hi
13650 0, // VR256:sub_32bit
13651 0, // VR256:sub_mask_0
13652 0, // VR256:sub_mask_1
13653 0, // VR256:sub_t0
13654 0, // VR256:sub_t1
13655 25, // VR256:sub_xmm -> FR16
13656 0, // VR256:sub_ymm
13657 },
13658 { // VR512
13659 0, // VR512:sub_8bit
13660 0, // VR512:sub_8bit_hi
13661 0, // VR512:sub_8bit_hi_phony
13662 0, // VR512:sub_16bit
13663 0, // VR512:sub_16bit_hi
13664 0, // VR512:sub_32bit
13665 0, // VR512:sub_mask_0
13666 0, // VR512:sub_mask_1
13667 0, // VR512:sub_t0
13668 0, // VR512:sub_t1
13669 24, // VR512:sub_xmm -> FR16X
13670 131, // VR512:sub_ymm -> VR256X
13671 },
13672 { // VR512_0_15
13673 0, // VR512_0_15:sub_8bit
13674 0, // VR512_0_15:sub_8bit_hi
13675 0, // VR512_0_15:sub_8bit_hi_phony
13676 0, // VR512_0_15:sub_16bit
13677 0, // VR512_0_15:sub_16bit_hi
13678 0, // VR512_0_15:sub_32bit
13679 0, // VR512_0_15:sub_mask_0
13680 0, // VR512_0_15:sub_mask_1
13681 0, // VR512_0_15:sub_t0
13682 0, // VR512_0_15:sub_t1
13683 25, // VR512_0_15:sub_xmm -> FR16
13684 132, // VR512_0_15:sub_ymm -> VR256
13685 },
13686 { // TILE
13687 0, // TILE:sub_8bit
13688 0, // TILE:sub_8bit_hi
13689 0, // TILE:sub_8bit_hi_phony
13690 0, // TILE:sub_16bit
13691 0, // TILE:sub_16bit_hi
13692 0, // TILE:sub_32bit
13693 0, // TILE:sub_mask_0
13694 0, // TILE:sub_mask_1
13695 0, // TILE:sub_t0
13696 0, // TILE:sub_t1
13697 0, // TILE:sub_xmm
13698 0, // TILE:sub_ymm
13699 },
13700 { // TILEPAIR
13701 0, // TILEPAIR:sub_8bit
13702 0, // TILEPAIR:sub_8bit_hi
13703 0, // TILEPAIR:sub_8bit_hi_phony
13704 0, // TILEPAIR:sub_16bit
13705 0, // TILEPAIR:sub_16bit_hi
13706 0, // TILEPAIR:sub_32bit
13707 0, // TILEPAIR:sub_mask_0
13708 0, // TILEPAIR:sub_mask_1
13709 135, // TILEPAIR:sub_t0 -> TILE
13710 135, // TILEPAIR:sub_t1 -> TILE
13711 0, // TILEPAIR:sub_xmm
13712 0, // TILEPAIR:sub_ymm
13713 },
13714 };
13715 assert(RC && "Missing regclass");
13716 if (!Idx) return RC;
13717 --Idx;
13718 assert(Idx < 12 && "Bad subreg");
13719 unsigned TV = Table[RC->getID()][Idx];
13720 return TV ? getRegClass(TV - 1) : nullptr;
13721}
13722
13723/// Get the weight in units of pressure for this register class.
13724const RegClassWeight &X86GenRegisterInfo::
13725getRegClassWeight(const TargetRegisterClass *RC) const {
13726 static const RegClassWeight RCWeightTable[] = {
13727 {1, 36}, // GR8
13728 {0, 0}, // GRH8
13729 {1, 20}, // GR8_NOREX2
13730 {1, 8}, // GR8_NOREX
13731 {1, 4}, // GR8_ABCD_H
13732 {1, 4}, // GR8_ABCD_L
13733 {0, 0}, // GRH16
13734 {2, 64}, // GR16
13735 {2, 32}, // GR16_NOREX2
13736 {2, 16}, // GR16_NOREX
13737 {1, 8}, // VK1
13738 {1, 8}, // VK16
13739 {1, 8}, // VK2
13740 {1, 8}, // VK4
13741 {1, 8}, // VK8
13742 {1, 7}, // VK16WM
13743 {1, 7}, // VK1WM
13744 {1, 7}, // VK2WM
13745 {1, 7}, // VK4WM
13746 {1, 7}, // VK8WM
13747 {1, 6}, // SEGMENT_REG
13748 {2, 8}, // GR16_ABCD
13749 {0, 0}, // FPCCR
13750 {1, 32}, // FR16X
13751 {1, 16}, // FR16
13752 {2, 8}, // VK16PAIR
13753 {2, 8}, // VK1PAIR
13754 {2, 8}, // VK2PAIR
13755 {2, 8}, // VK4PAIR
13756 {2, 8}, // VK8PAIR
13757 {2, 6}, // VK1PAIR_with_sub_mask_0_in_VK1WM
13758 {2, 66}, // LOW32_ADDR_ACCESS_RBP
13759 {2, 66}, // LOW32_ADDR_ACCESS
13760 {2, 64}, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit
13761 {1, 32}, // FR32X
13762 {2, 64}, // GR32
13763 {2, 62}, // GR32_NOSP
13764 {2, 32}, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
13765 {1, 16}, // DEBUG_REG
13766 {1, 16}, // FR32
13767 {2, 32}, // GR32_NOREX2
13768 {2, 30}, // GR32_NOREX2_NOSP
13769 {2, 16}, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
13770 {2, 16}, // GR32_NOREX
13771 {1, 8}, // VK32
13772 {2, 14}, // GR32_NOREX_NOSP
13773 {1, 7}, // RFP32
13774 {1, 7}, // VK32WM
13775 {2, 8}, // GR32_ABCD
13776 {2, 8}, // GR32_TC
13777 {2, 6}, // GR32_ABCD_and_GR32_TC
13778 {2, 4}, // GR32_AD
13779 {2, 4}, // GR32_ArgRef
13780 {2, 4}, // GR32_BPSP
13781 {2, 4}, // GR32_BSI
13782 {2, 4}, // GR32_CB
13783 {2, 4}, // GR32_DC
13784 {2, 4}, // GR32_DIBP
13785 {2, 4}, // GR32_SIDI
13786 {2, 4}, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit
13787 {0, 0}, // CCR
13788 {0, 0}, // DFCCR
13789 {2, 2}, // GR32_ABCD_and_GR32_BSI
13790 {2, 2}, // GR32_AD_and_GR32_ArgRef
13791 {2, 2}, // GR32_ArgRef_and_GR32_CB
13792 {2, 2}, // GR32_BPSP_and_GR32_DIBP
13793 {2, 2}, // GR32_BPSP_and_GR32_TC
13794 {2, 2}, // GR32_BSI_and_GR32_SIDI
13795 {2, 2}, // GR32_DIBP_and_GR32_SIDI
13796 {2, 2}, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
13797 {2, 2}, // LOW32_ADDR_ACCESS_with_sub_32bit
13798 {1, 7}, // RFP64
13799 {2, 66}, // GR64
13800 {1, 32}, // FR64X
13801 {2, 64}, // GR64_with_sub_8bit
13802 {2, 62}, // GR64_NOSP
13803 {2, 34}, // GR64_NOREX2
13804 {1, 16}, // CONTROL_REG
13805 {1, 16}, // FR64
13806 {2, 32}, // GR64_with_sub_16bit_in_GR16_NOREX2
13807 {2, 30}, // GR64_NOREX2_NOSP
13808 {2, 26}, // GR64PLTSafe
13809 {2, 20}, // GR64_TC
13810 {2, 18}, // GR64_NOREX
13811 {2, 18}, // GR64_TCW64
13812 {2, 18}, // GR64_TC_with_sub_8bit
13813 {2, 16}, // GR64_NOREX2_NOSP_and_GR64_TC
13814 {2, 16}, // GR64_TCW64_with_sub_8bit
13815 {2, 16}, // GR64_TC_and_GR64_TCW64
13816 {2, 16}, // GR64_with_sub_16bit_in_GR16_NOREX
13817 {1, 8}, // VK64
13818 {1, 8}, // VR64
13819 {2, 14}, // GR64PLTSafe_and_GR64_TC
13820 {2, 14}, // GR64_NOREX2_NOSP_and_GR64_TCW64
13821 {2, 14}, // GR64_NOREX_NOSP
13822 {2, 14}, // GR64_NOREX_and_GR64_TC
13823 {2, 14}, // GR64_TCW64_and_GR64_TC_with_sub_8bit
13824 {1, 7}, // VK64WM
13825 {2, 12}, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
13826 {2, 12}, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
13827 {2, 10}, // GR64PLTSafe_and_GR64_TCW64
13828 {2, 10}, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
13829 {2, 10}, // GR64_NOREX_and_GR64_TCW64
13830 {2, 8}, // GR64_ABCD
13831 {2, 8}, // GR64_with_sub_32bit_in_GR32_TC
13832 {2, 6}, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
13833 {2, 4}, // GR64_AD
13834 {2, 4}, // GR64_ArgRef
13835 {2, 4}, // GR64_and_LOW32_ADDR_ACCESS_RBP
13836 {2, 4}, // GR64_with_sub_32bit_in_GR32_ArgRef
13837 {2, 4}, // GR64_with_sub_32bit_in_GR32_BPSP
13838 {2, 4}, // GR64_with_sub_32bit_in_GR32_BSI
13839 {2, 4}, // GR64_with_sub_32bit_in_GR32_CB
13840 {2, 4}, // GR64_with_sub_32bit_in_GR32_DIBP
13841 {2, 4}, // GR64_with_sub_32bit_in_GR32_SIDI
13842 {2, 2}, // GR64_A
13843 {2, 2}, // GR64_ArgRef_and_GR64_TC
13844 {2, 2}, // GR64_and_LOW32_ADDR_ACCESS
13845 {2, 2}, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
13846 {2, 2}, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
13847 {2, 2}, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
13848 {2, 2}, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
13849 {2, 2}, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
13850 {2, 2}, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
13851 {2, 2}, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
13852 {0, 0}, // RST
13853 {1, 7}, // RFP80
13854 {0, 0}, // RFP80_7
13855 {1, 32}, // VR128X
13856 {1, 16}, // VR128
13857 {1, 32}, // VR256X
13858 {1, 16}, // VR256
13859 {1, 32}, // VR512
13860 {1, 16}, // VR512_0_15
13861 {1, 8}, // TILE
13862 {2, 8}, // TILEPAIR
13863 };
13864 return RCWeightTable[RC->getID()];
13865}
13866
13867/// Get the weight in units of pressure for this register unit.
13868unsigned X86GenRegisterInfo::
13869getRegUnitWeight(unsigned RegUnit) const {
13870 assert(RegUnit < 221 && "invalid register unit");
13871 // All register units have unit weight.
13872 return 1;
13873}
13874
13875
13876// Get the number of dimensions of register pressure.
13877unsigned X86GenRegisterInfo::getNumRegPressureSets() const {
13878 return 36;
13879}
13880
13881// Get the name of this register unit pressure set.
13882const char *X86GenRegisterInfo::
13883getRegPressureSetName(unsigned Idx) const {
13884 static const char *PressureNameTable[] = {
13885 "SEGMENT_REG",
13886 "GR32_BPSP",
13887 "LOW32_ADDR_ACCESS_with_sub_32bit",
13888 "GR32_BSI",
13889 "GR32_SIDI",
13890 "GR32_DIBP_with_GR32_SIDI",
13891 "GR32_DIBP_with_LOW32_ADDR_ACCESS_with_sub_32bit",
13892 "RFP32",
13893 "GR8_ABCD_H_with_GR32_BSI",
13894 "GR8_ABCD_L_with_GR32_BSI",
13895 "VK1",
13896 "VR64",
13897 "TILE",
13898 "GR8_NOREX",
13899 "GR32_TC",
13900 "GR32_BPSP_with_GR32_TC",
13901 "FR16",
13902 "DEBUG_REG",
13903 "CONTROL_REG",
13904 "GR64_NOREX",
13905 "GR64_TCW64",
13906 "GR32_BPSP_with_GR64_TCW64",
13907 "GR64_TC_with_GR64_TCW64",
13908 "GR64_TC",
13909 "FR16X",
13910 "GR64PLTSafe_with_GR64_TC",
13911 "GR8",
13912 "GR8_with_GR32_DIBP",
13913 "GR8_with_GR32_BSI",
13914 "GR8_with_LOW32_ADDR_ACCESS_with_sub_32bit",
13915 "GR8_with_GR64_NOREX",
13916 "GR8_with_GR64_TCW64",
13917 "GR8_with_GR64_TC",
13918 "GR8_with_GR64PLTSafe",
13919 "GR8_with_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2",
13920 "GR16",
13921 };
13922 return PressureNameTable[Idx];
13923}
13924
13925// Get the register unit pressure limit for this dimension.
13926// This limit must be adjusted dynamically for reserved registers.
13927unsigned X86GenRegisterInfo::
13928getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
13929 static const uint8_t PressureLimitTable[] = {
13930 6, // 0: SEGMENT_REG
13931 6, // 1: GR32_BPSP
13932 6, // 2: LOW32_ADDR_ACCESS_with_sub_32bit
13933 6, // 3: GR32_BSI
13934 6, // 4: GR32_SIDI
13935 6, // 5: GR32_DIBP_with_GR32_SIDI
13936 6, // 6: GR32_DIBP_with_LOW32_ADDR_ACCESS_with_sub_32bit
13937 7, // 7: RFP32
13938 7, // 8: GR8_ABCD_H_with_GR32_BSI
13939 7, // 9: GR8_ABCD_L_with_GR32_BSI
13940 8, // 10: VK1
13941 8, // 11: VR64
13942 8, // 12: TILE
13943 10, // 13: GR8_NOREX
13944 12, // 14: GR32_TC
13945 12, // 15: GR32_BPSP_with_GR32_TC
13946 16, // 16: FR16
13947 16, // 17: DEBUG_REG
13948 16, // 18: CONTROL_REG
13949 18, // 19: GR64_NOREX
13950 20, // 20: GR64_TCW64
13951 20, // 21: GR32_BPSP_with_GR64_TCW64
13952 22, // 22: GR64_TC_with_GR64_TCW64
13953 26, // 23: GR64_TC
13954 32, // 24: FR16X
13955 34, // 25: GR64PLTSafe_with_GR64_TC
13956 38, // 26: GR8
13957 38, // 27: GR8_with_GR32_DIBP
13958 38, // 28: GR8_with_GR32_BSI
13959 39, // 29: GR8_with_LOW32_ADDR_ACCESS_with_sub_32bit
13960 42, // 30: GR8_with_GR64_NOREX
13961 43, // 31: GR8_with_GR64_TCW64
13962 44, // 32: GR8_with_GR64_TC
13963 45, // 33: GR8_with_GR64PLTSafe
13964 48, // 34: GR8_with_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
13965 66, // 35: GR16
13966 };
13967 return PressureLimitTable[Idx];
13968}
13969
13970/// Table of pressure sets per register class or unit.
13971static const int RCSetsTable[] = {
13972 /* 0 */ 0, -1,
13973 /* 2 */ 7, -1,
13974 /* 4 */ 10, -1,
13975 /* 6 */ 11, -1,
13976 /* 8 */ 12, -1,
13977 /* 10 */ 17, -1,
13978 /* 12 */ 18, -1,
13979 /* 14 */ 16, 24, -1,
13980 /* 17 */ 25, 35, -1,
13981 /* 20 */ 19, 23, 25, 30, 35, -1,
13982 /* 26 */ 2, 6, 15, 19, 21, 23, 25, 29, 30, 35, -1,
13983 /* 37 */ 20, 21, 22, 23, 25, 31, 35, -1,
13984 /* 45 */ 22, 23, 25, 32, 35, -1,
13985 /* 51 */ 19, 22, 23, 25, 30, 32, 35, -1,
13986 /* 59 */ 20, 21, 22, 23, 25, 31, 32, 35, -1,
13987 /* 68 */ 14, 15, 19, 20, 21, 22, 23, 25, 30, 31, 32, 35, -1,
13988 /* 81 */ 2, 6, 14, 15, 19, 20, 21, 22, 23, 25, 29, 30, 31, 32, 35, -1,
13989 /* 97 */ 25, 34, 35, -1,
13990 /* 101 */ 19, 23, 25, 30, 34, 35, -1,
13991 /* 108 */ 1, 2, 15, 19, 21, 23, 25, 26, 30, 34, 35, -1,
13992 /* 120 */ 20, 21, 22, 23, 25, 31, 34, 35, -1,
13993 /* 129 */ 22, 23, 25, 32, 34, 35, -1,
13994 /* 136 */ 19, 22, 23, 25, 30, 32, 34, 35, -1,
13995 /* 145 */ 20, 21, 22, 23, 25, 31, 32, 34, 35, -1,
13996 /* 155 */ 1, 2, 14, 15, 19, 20, 21, 22, 23, 25, 26, 30, 31, 32, 34, 35, -1,
13997 /* 172 */ 25, 33, 34, 35, -1,
13998 /* 177 */ 19, 23, 25, 30, 33, 34, 35, -1,
13999 /* 185 */ 1, 5, 6, 19, 23, 25, 27, 30, 33, 34, 35, -1,
14000 /* 197 */ 1, 2, 5, 6, 15, 19, 21, 23, 25, 26, 27, 29, 30, 33, 34, 35, -1,
14001 /* 214 */ 22, 23, 25, 32, 33, 34, 35, -1,
14002 /* 222 */ 3, 4, 8, 9, 13, 19, 23, 25, 28, 30, 32, 33, 34, 35, -1,
14003 /* 237 */ 4, 5, 19, 22, 23, 25, 28, 30, 32, 33, 34, 35, -1,
14004 /* 250 */ 3, 4, 5, 8, 9, 13, 19, 22, 23, 25, 28, 30, 32, 33, 34, 35, -1,
14005 /* 267 */ 1, 4, 5, 6, 19, 22, 23, 25, 27, 28, 30, 32, 33, 34, 35, -1,
14006 /* 283 */ 20, 21, 22, 23, 25, 31, 32, 33, 34, 35, -1,
14007 /* 294 */ 3, 13, 14, 19, 20, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
14008 /* 312 */ 8, 13, 14, 19, 20, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
14009 /* 330 */ 3, 4, 8, 9, 13, 14, 19, 20, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
14010 /* 351 */ 1, 2, 5, 6, 15, 19, 21, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
14011 /* 371 */ 1, 4, 5, 6, 19, 22, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
14012 /* 390 */ 3, 4, 5, 8, 9, 13, 19, 22, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
14013 /* 411 */ 1, 2, 14, 15, 19, 20, 21, 22, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
14014 /* 432 */ 3, 13, 14, 15, 19, 20, 21, 22, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
14015 /* 453 */ 3, 8, 13, 14, 15, 19, 20, 21, 22, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
14016 /* 475 */ 3, 9, 13, 14, 15, 19, 20, 21, 22, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
14017};
14018
14019/// Get the dimensions of register pressure impacted by this register class.
14020/// Returns a -1 terminated array of pressure set IDs
14021const int *X86GenRegisterInfo::
14022getRegClassPressureSets(const TargetRegisterClass *RC) const {
14023 static const uint16_t RCSetStartTable[] = {
14024 301,1,300,295,312,333,1,18,97,101,4,4,4,4,4,4,4,4,4,4,0,295,1,15,14,4,4,4,4,4,4,18,18,18,15,18,18,97,10,14,97,97,101,101,4,177,2,4,295,157,433,433,433,108,222,294,433,185,237,26,1,1,330,433,432,197,155,250,267,197,81,2,18,15,18,18,17,12,14,97,97,172,45,20,37,129,129,120,59,101,4,6,214,120,177,51,145,4,145,136,283,239,68,295,157,433,433,120,26,433,108,222,294,185,237,433,145,81,330,433,432,197,155,250,267,1,2,1,15,14,15,14,15,14,8,8,};
14025 return &RCSetsTable[RCSetStartTable[RC->getID()]];
14026}
14027
14028/// Get the dimensions of register pressure impacted by this register unit.
14029/// Returns a -1 terminated array of pressure set IDs
14030const int *X86GenRegisterInfo::
14031getRegUnitPressureSets(unsigned RegUnit) const {
14032 assert(RegUnit < 221 && "invalid register unit");
14033 static const uint16_t RUSetStartTable[] = {
14034 454,476,330,330,351,1,453,475,0,1,454,371,1,476,0,1,1,1,1,1,1,1,81,1,1,0,390,1,1,411,1,1,1,1,0,1,0,1,1,1,1,0,1,1,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,2,2,2,2,2,2,2,1,6,6,6,6,6,6,6,6,416,1,1,416,1,1,416,1,1,416,1,1,300,1,1,300,1,1,300,1,1,300,1,1,1,1,1,1,1,1,1,1,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,4,4,4,4,4,4,4,4,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,1,8,8,8,8,8,8,8,8,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,};
14035 return &RCSetsTable[RUSetStartTable[RegUnit]];
14036}
14037
14038extern const MCRegisterDesc X86RegDesc[];
14039extern const int16_t X86RegDiffLists[];
14040extern const LaneBitmask X86LaneMaskLists[];
14041extern const char X86RegStrings[];
14042extern const char X86RegClassStrings[];
14043extern const MCPhysReg X86RegUnitRoots[][2];
14044extern const uint16_t X86SubRegIdxLists[];
14045extern const uint16_t X86RegEncodingTable[];
14046// X86 Dwarf<->LLVM register mappings.
14047extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour0Dwarf2L[];
14048extern const unsigned X86DwarfFlavour0Dwarf2LSize;
14049
14050extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour1Dwarf2L[];
14051extern const unsigned X86DwarfFlavour1Dwarf2LSize;
14052
14053extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour2Dwarf2L[];
14054extern const unsigned X86DwarfFlavour2Dwarf2LSize;
14055
14056extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour0Dwarf2L[];
14057extern const unsigned X86EHFlavour0Dwarf2LSize;
14058
14059extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour1Dwarf2L[];
14060extern const unsigned X86EHFlavour1Dwarf2LSize;
14061
14062extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour2Dwarf2L[];
14063extern const unsigned X86EHFlavour2Dwarf2LSize;
14064
14065extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour0L2Dwarf[];
14066extern const unsigned X86DwarfFlavour0L2DwarfSize;
14067
14068extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour1L2Dwarf[];
14069extern const unsigned X86DwarfFlavour1L2DwarfSize;
14070
14071extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour2L2Dwarf[];
14072extern const unsigned X86DwarfFlavour2L2DwarfSize;
14073
14074extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour0L2Dwarf[];
14075extern const unsigned X86EHFlavour0L2DwarfSize;
14076
14077extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour1L2Dwarf[];
14078extern const unsigned X86EHFlavour1L2DwarfSize;
14079
14080extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour2L2Dwarf[];
14081extern const unsigned X86EHFlavour2L2DwarfSize;
14082
14083X86GenRegisterInfo::
14084X86GenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
14085 unsigned PC, unsigned HwMode)
14086 : TargetRegisterInfo(&X86RegInfoDesc, RegisterClasses, RegisterClasses+136,
14087 SubRegIndexNameTable, SubRegIdxRangeTable, SubRegIndexLaneMaskTable,
14088 LaneBitmask(0xFFFFFFFFFFFFFEF0), RegClassInfos, VTLists, HwMode) {
14089 InitMCRegisterInfo(X86RegDesc, 392, RA, PC,
14090 X86MCRegisterClasses, 136,
14091 X86RegUnitRoots,
14092 221,
14093 X86RegDiffLists,
14094 X86LaneMaskLists,
14095 X86RegStrings,
14096 X86RegClassStrings,
14097 X86SubRegIdxLists,
14098 13,
14099 X86RegEncodingTable);
14100
14101 switch (DwarfFlavour) {
14102 default:
14103 llvm_unreachable("Unknown DWARF flavour");
14104 case 0:
14105 mapDwarfRegsToLLVMRegs(X86DwarfFlavour0Dwarf2L, X86DwarfFlavour0Dwarf2LSize, false);
14106 break;
14107 case 1:
14108 mapDwarfRegsToLLVMRegs(X86DwarfFlavour1Dwarf2L, X86DwarfFlavour1Dwarf2LSize, false);
14109 break;
14110 case 2:
14111 mapDwarfRegsToLLVMRegs(X86DwarfFlavour2Dwarf2L, X86DwarfFlavour2Dwarf2LSize, false);
14112 break;
14113 }
14114 switch (EHFlavour) {
14115 default:
14116 llvm_unreachable("Unknown DWARF flavour");
14117 case 0:
14118 mapDwarfRegsToLLVMRegs(X86EHFlavour0Dwarf2L, X86EHFlavour0Dwarf2LSize, true);
14119 break;
14120 case 1:
14121 mapDwarfRegsToLLVMRegs(X86EHFlavour1Dwarf2L, X86EHFlavour1Dwarf2LSize, true);
14122 break;
14123 case 2:
14124 mapDwarfRegsToLLVMRegs(X86EHFlavour2Dwarf2L, X86EHFlavour2Dwarf2LSize, true);
14125 break;
14126 }
14127 switch (DwarfFlavour) {
14128 default:
14129 llvm_unreachable("Unknown DWARF flavour");
14130 case 0:
14131 mapLLVMRegsToDwarfRegs(X86DwarfFlavour0L2Dwarf, X86DwarfFlavour0L2DwarfSize, false);
14132 break;
14133 case 1:
14134 mapLLVMRegsToDwarfRegs(X86DwarfFlavour1L2Dwarf, X86DwarfFlavour1L2DwarfSize, false);
14135 break;
14136 case 2:
14137 mapLLVMRegsToDwarfRegs(X86DwarfFlavour2L2Dwarf, X86DwarfFlavour2L2DwarfSize, false);
14138 break;
14139 }
14140 switch (EHFlavour) {
14141 default:
14142 llvm_unreachable("Unknown DWARF flavour");
14143 case 0:
14144 mapLLVMRegsToDwarfRegs(X86EHFlavour0L2Dwarf, X86EHFlavour0L2DwarfSize, true);
14145 break;
14146 case 1:
14147 mapLLVMRegsToDwarfRegs(X86EHFlavour1L2Dwarf, X86EHFlavour1L2DwarfSize, true);
14148 break;
14149 case 2:
14150 mapLLVMRegsToDwarfRegs(X86EHFlavour2L2Dwarf, X86EHFlavour2L2DwarfSize, true);
14151 break;
14152 }
14153}
14154
14155static const MCPhysReg CSR_32_SaveList[] = { X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0 };
14156static const uint32_t CSR_32_RegMask[] = { 0x058703f0, 0xc0009601, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
14157static const MCPhysReg CSR_32EHRet_SaveList[] = { X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0 };
14158static const uint32_t CSR_32EHRet_RegMask[] = { 0x0def83fe, 0xc000b701, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
14159static const MCPhysReg CSR_32_AllRegs_SaveList[] = { X86::EAX, X86::EBX, X86::ECX, X86::EDX, X86::EBP, X86::ESI, X86::EDI, 0 };
14160static const uint32_t CSR_32_AllRegs_RegMask[] = { 0x0fefaffe, 0xc000bf01, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
14161static const MCPhysReg CSR_32_AllRegs_AVX_SaveList[] = { X86::EAX, X86::EBX, X86::ECX, X86::EDX, X86::EBP, X86::ESI, X86::EDI, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, 0 };
14162static const uint32_t CSR_32_AllRegs_AVX_RegMask[] = { 0x0fefaffe, 0xc000bf01, 0x00000001, 0x00000000, 0x00007f80, 0x80000000, 0x0000007f, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
14163static const MCPhysReg CSR_32_AllRegs_AVX512_SaveList[] = { X86::EAX, X86::EBX, X86::ECX, X86::EDX, X86::EBP, X86::ESI, X86::EDI, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 0 };
14164static const uint32_t CSR_32_AllRegs_AVX512_RegMask[] = { 0x0fefaffe, 0xc000bf01, 0x00000001, 0x00000000, 0x00007f80, 0x80000000, 0x007f807f, 0x7f800000, 0x07800000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
14165static const MCPhysReg CSR_32_AllRegs_SSE_SaveList[] = { X86::EAX, X86::EBX, X86::ECX, X86::EDX, X86::EBP, X86::ESI, X86::EDI, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, 0 };
14166static const uint32_t CSR_32_AllRegs_SSE_RegMask[] = { 0x0fefaffe, 0xc000bf01, 0x00000001, 0x00000000, 0x00007f80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
14167static const MCPhysReg CSR_32_RegCall_SaveList[] = { X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, 0 };
14168static const uint32_t CSR_32_RegCall_RegMask[] = { 0x058703f0, 0xc0009601, 0x00000001, 0x00000000, 0x00007800, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
14169static const MCPhysReg CSR_32_RegCall_NoSSE_SaveList[] = { X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0 };
14170static const uint32_t CSR_32_RegCall_NoSSE_RegMask[] = { 0x058703f0, 0xc0009601, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
14171static const MCPhysReg CSR_64_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 };
14172static const uint32_t CSR_64_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x78000000, 0x78000000, 0x78787878, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
14173static const MCPhysReg CSR_64EHRet_SaveList[] = { X86::RAX, X86::RDX, X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 };
14174static const uint32_t CSR_64EHRet_RegMask[] = { 0x09e883fe, 0x01382700, 0x00000000, 0x78000000, 0x78000000, 0x78787878, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
14175static const MCPhysReg CSR_64_AllRegs_SaveList[] = { X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::RAX, 0 };
14176static const uint32_t CSR_64_AllRegs_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x7f800000, 0xffffff80, 0x7fffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
14177static const MCPhysReg CSR_64_AllRegs_AVX_SaveList[] = { X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 0 };
14178static const uint32_t CSR_64_AllRegs_AVX_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x7f800000, 0xffffff80, 0xffffffff, 0x00007fff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
14179static const MCPhysReg CSR_64_AllRegs_AVX512_SaveList[] = { X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM16, X86::ZMM17, X86::ZMM18, X86::ZMM19, X86::ZMM20, X86::ZMM21, X86::ZMM22, X86::ZMM23, X86::ZMM24, X86::ZMM25, X86::ZMM26, X86::ZMM27, X86::ZMM28, X86::ZMM29, X86::ZMM30, X86::ZMM31, X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 0 };
14180static const uint32_t CSR_64_AllRegs_AVX512_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x7f800000, 0xffffff80, 0xffffffff, 0xffffffff, 0xffffffff, 0x07ffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
14181static const MCPhysReg CSR_64_AllRegs_NoSSE_SaveList[] = { X86::RAX, X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 };
14182static const uint32_t CSR_64_AllRegs_NoSSE_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x7f800000, 0xff800000, 0x7fffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
14183static const MCPhysReg CSR_64_CXX_TLS_Darwin_PE_SaveList[] = { X86::RBP, 0 };
14184static const uint32_t CSR_64_CXX_TLS_Darwin_PE_RegMask[] = { 0x008001c0, 0x00100200, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
14185static const MCPhysReg CSR_64_CXX_TLS_Darwin_ViaCopy_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RCX, X86::RDX, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, 0 };
14186static const uint32_t CSR_64_CXX_TLS_Darwin_ViaCopy_RegMask[] = { 0x0b28ae30, 0xd160ac01, 0x00000001, 0x7f800000, 0xff800000, 0x7fffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
14187static const MCPhysReg CSR_64_Intel_OCL_BI_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
14188static const uint32_t CSR_64_Intel_OCL_BI_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x78000000, 0x787f8000, 0x78787878, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
14189static const MCPhysReg CSR_64_Intel_OCL_BI_AVX_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 0 };
14190static const uint32_t CSR_64_Intel_OCL_BI_AVX_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x78000000, 0x787f8000, 0x78787878, 0x00007f80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
14191static const MCPhysReg CSR_64_Intel_OCL_BI_AVX512_SaveList[] = { X86::RBX, X86::RSI, X86::R14, X86::R15, X86::ZMM16, X86::ZMM17, X86::ZMM18, X86::ZMM19, X86::ZMM20, X86::ZMM21, X86::ZMM22, X86::ZMM23, X86::ZMM24, X86::ZMM25, X86::ZMM26, X86::ZMM27, X86::ZMM28, X86::ZMM29, X86::ZMM30, X86::ZMM31, X86::K4, X86::K5, X86::K6, X86::K7, 0 };
14192static const uint32_t CSR_64_Intel_OCL_BI_AVX512_RegMask[] = { 0x01000230, 0xd0208401, 0x00000001, 0x60000000, 0x60000000, 0x60606060, 0xfff80000, 0x007fffff, 0x067fff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
14193static const MCPhysReg CSR_64_MostRegs_SaveList[] = { X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
14194static const uint32_t CSR_64_MostRegs_RegMask[] = { 0x0fafaff0, 0xd1f0be01, 0x00000001, 0x7f800000, 0xffffff80, 0x7fffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
14195static const MCPhysReg CSR_64_NoneRegs_SaveList[] = { X86::RBP, 0 };
14196static const uint32_t CSR_64_NoneRegs_RegMask[] = { 0x008001c0, 0x00100200, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
14197static const MCPhysReg CSR_64_RT_AllRegs_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
14198static const uint32_t CSR_64_RT_AllRegs_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x7b800000, 0xfbffff80, 0x7bfbfbfb, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
14199static const MCPhysReg CSR_64_RT_AllRegs_AVX_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 0 };
14200static const uint32_t CSR_64_RT_AllRegs_AVX_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x7b800000, 0xfbffff80, 0xfbfbfbfb, 0x00007fff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
14201static const MCPhysReg CSR_64_RT_MostRegs_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, 0 };
14202static const uint32_t CSR_64_RT_MostRegs_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x7b800000, 0xfb800000, 0x7bfbfbfb, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
14203static const MCPhysReg CSR_64_SwiftError_SaveList[] = { X86::RBX, X86::R13, X86::R14, X86::R15, X86::RBP, 0 };
14204static const uint32_t CSR_64_SwiftError_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x70000000, 0x70000000, 0x70707070, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
14205static const MCPhysReg CSR_64_SwiftTail_SaveList[] = { X86::RBX, X86::R12, X86::R15, X86::RBP, 0 };
14206static const uint32_t CSR_64_SwiftTail_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x48000000, 0x48000000, 0x48484848, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
14207static const MCPhysReg CSR_64_TLS_Darwin_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RCX, X86::RDX, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, 0 };
14208static const uint32_t CSR_64_TLS_Darwin_RegMask[] = { 0x0ba8aff0, 0xd170ae01, 0x00000001, 0x7f800000, 0xff800000, 0x7fffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
14209static const MCPhysReg CSR_IPRA_32_SaveList[] = { X86::EBP, X86::ESI, 0 };
14210static const uint32_t CSR_IPRA_32_RegMask[] = { 0x008001c0, 0xc0008201, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
14211static const MCPhysReg CSR_IPRA_64_SaveList[] = { X86::RBP, X86::RBX, 0 };
14212static const uint32_t CSR_IPRA_64_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
14213static const MCPhysReg CSR_NoRegs_SaveList[] = { 0 };
14214static const uint32_t CSR_NoRegs_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
14215static const MCPhysReg CSR_SysV64_RegCall_SaveList[] = { X86::RBX, X86::RBP, X86::R12, X86::R13, X86::R14, X86::R15, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
14216static const uint32_t CSR_SysV64_RegCall_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x78000000, 0x787f8000, 0x78787878, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
14217static const MCPhysReg CSR_SysV64_RegCall_NoSSE_SaveList[] = { X86::RBX, X86::RBP, X86::R12, X86::R13, X86::R14, X86::R15, 0 };
14218static const uint32_t CSR_SysV64_RegCall_NoSSE_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x78000000, 0x78000000, 0x78787878, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
14219static const MCPhysReg CSR_Win32_CFGuard_Check_SaveList[] = { X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::ECX, 0 };
14220static const uint32_t CSR_Win32_CFGuard_Check_RegMask[] = { 0x07872ff0, 0xc0009e01, 0x00000001, 0x00000000, 0x00007800, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
14221static const MCPhysReg CSR_Win32_CFGuard_Check_NoSSE_SaveList[] = { X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ECX, 0 };
14222static const uint32_t CSR_Win32_CFGuard_Check_NoSSE_RegMask[] = { 0x07872ff0, 0xc0009e01, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
14223static const MCPhysReg CSR_Win64_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R13, X86::R14, X86::R15, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
14224static const uint32_t CSR_Win64_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x78000000, 0x787fe000, 0x78787878, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
14225static const MCPhysReg CSR_Win64_Intel_OCL_BI_AVX_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R13, X86::R14, X86::R15, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 0 };
14226static const uint32_t CSR_Win64_Intel_OCL_BI_AVX_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x78000000, 0x787fe000, 0x78787878, 0x00007fe0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
14227static const MCPhysReg CSR_Win64_Intel_OCL_BI_AVX512_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R13, X86::R14, X86::R15, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM16, X86::ZMM17, X86::ZMM18, X86::ZMM19, X86::ZMM20, X86::ZMM21, X86::K4, X86::K5, X86::K6, X86::K7, 0 };
14228static const uint32_t CSR_Win64_Intel_OCL_BI_AVX512_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x78000000, 0x787fe000, 0x78787878, 0x1ff87fe0, 0xe0001f80, 0x06001fff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
14229static const MCPhysReg CSR_Win64_NoSSE_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R13, X86::R14, X86::R15, 0 };
14230static const uint32_t CSR_Win64_NoSSE_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x78000000, 0x78000000, 0x78787878, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
14231static const MCPhysReg CSR_Win64_RT_MostRegs_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
14232static const uint32_t CSR_Win64_RT_MostRegs_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x7b800000, 0xfbffe000, 0x7bfbfbfb, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
14233static const MCPhysReg CSR_Win64_RegCall_SaveList[] = { X86::RBX, X86::RBP, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
14234static const uint32_t CSR_Win64_RegCall_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x7e000000, 0x7e7f8000, 0x7e7e7e7e, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
14235static const MCPhysReg CSR_Win64_RegCall_NoSSE_SaveList[] = { X86::RBX, X86::RBP, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, 0 };
14236static const uint32_t CSR_Win64_RegCall_NoSSE_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x7e000000, 0x7e000000, 0x7e7e7e7e, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
14237static const MCPhysReg CSR_Win64_SwiftError_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R13, X86::R14, X86::R15, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
14238static const uint32_t CSR_Win64_SwiftError_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x70000000, 0x707fe000, 0x70707070, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
14239static const MCPhysReg CSR_Win64_SwiftTail_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R15, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
14240static const uint32_t CSR_Win64_SwiftTail_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x48000000, 0x487fe000, 0x48484848, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
14241
14242
14243ArrayRef<const uint32_t *> X86GenRegisterInfo::getRegMasks() const {
14244 static const uint32_t *const Masks[] = {
14245 CSR_32_RegMask,
14246 CSR_32EHRet_RegMask,
14247 CSR_32_AllRegs_RegMask,
14248 CSR_32_AllRegs_AVX_RegMask,
14249 CSR_32_AllRegs_AVX512_RegMask,
14250 CSR_32_AllRegs_SSE_RegMask,
14251 CSR_32_RegCall_RegMask,
14252 CSR_32_RegCall_NoSSE_RegMask,
14253 CSR_64_RegMask,
14254 CSR_64EHRet_RegMask,
14255 CSR_64_AllRegs_RegMask,
14256 CSR_64_AllRegs_AVX_RegMask,
14257 CSR_64_AllRegs_AVX512_RegMask,
14258 CSR_64_AllRegs_NoSSE_RegMask,
14259 CSR_64_CXX_TLS_Darwin_PE_RegMask,
14260 CSR_64_CXX_TLS_Darwin_ViaCopy_RegMask,
14261 CSR_64_Intel_OCL_BI_RegMask,
14262 CSR_64_Intel_OCL_BI_AVX_RegMask,
14263 CSR_64_Intel_OCL_BI_AVX512_RegMask,
14264 CSR_64_MostRegs_RegMask,
14265 CSR_64_NoneRegs_RegMask,
14266 CSR_64_RT_AllRegs_RegMask,
14267 CSR_64_RT_AllRegs_AVX_RegMask,
14268 CSR_64_RT_MostRegs_RegMask,
14269 CSR_64_SwiftError_RegMask,
14270 CSR_64_SwiftTail_RegMask,
14271 CSR_64_TLS_Darwin_RegMask,
14272 CSR_IPRA_32_RegMask,
14273 CSR_IPRA_64_RegMask,
14274 CSR_NoRegs_RegMask,
14275 CSR_SysV64_RegCall_RegMask,
14276 CSR_SysV64_RegCall_NoSSE_RegMask,
14277 CSR_Win32_CFGuard_Check_RegMask,
14278 CSR_Win32_CFGuard_Check_NoSSE_RegMask,
14279 CSR_Win64_RegMask,
14280 CSR_Win64_Intel_OCL_BI_AVX_RegMask,
14281 CSR_Win64_Intel_OCL_BI_AVX512_RegMask,
14282 CSR_Win64_NoSSE_RegMask,
14283 CSR_Win64_RT_MostRegs_RegMask,
14284 CSR_Win64_RegCall_RegMask,
14285 CSR_Win64_RegCall_NoSSE_RegMask,
14286 CSR_Win64_SwiftError_RegMask,
14287 CSR_Win64_SwiftTail_RegMask,
14288 };
14289 return ArrayRef(Masks);
14290}
14291
14292bool X86GenRegisterInfo::
14293isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
14294 return
14295 X86::GR64RegClass.contains(PhysReg) ||
14296 X86::GR32RegClass.contains(PhysReg) ||
14297 X86::GR16RegClass.contains(PhysReg) ||
14298 X86::GR8RegClass.contains(PhysReg) ||
14299 false;
14300}
14301
14302bool X86GenRegisterInfo::
14303isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
14304 return
14305 X86::GR64RegClass.hasSubClassEq(RC) ||
14306 X86::GR32RegClass.hasSubClassEq(RC) ||
14307 X86::GR16RegClass.hasSubClassEq(RC) ||
14308 X86::GR8RegClass.hasSubClassEq(RC) ||
14309 false;
14310}
14311
14312bool X86GenRegisterInfo::
14313isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
14314 return
14315 X86::DEBUG_REGRegClass.contains(PhysReg) ||
14316 X86::CONTROL_REGRegClass.contains(PhysReg) ||
14317 X86::CCRRegClass.contains(PhysReg) ||
14318 X86::FPCCRRegClass.contains(PhysReg) ||
14319 X86::DFCCRRegClass.contains(PhysReg) ||
14320 X86::TILERegClass.contains(PhysReg) ||
14321 X86::VK1PAIRRegClass.contains(PhysReg) ||
14322 X86::VK2PAIRRegClass.contains(PhysReg) ||
14323 X86::VK4PAIRRegClass.contains(PhysReg) ||
14324 X86::VK8PAIRRegClass.contains(PhysReg) ||
14325 X86::VK16PAIRRegClass.contains(PhysReg) ||
14326 false;
14327}
14328
14329bool X86GenRegisterInfo::
14330isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
14331 return
14332 false;
14333}
14334
14335bool X86GenRegisterInfo::
14336isConstantPhysReg(MCRegister PhysReg) const {
14337 return
14338 false;
14339}
14340
14341ArrayRef<const char *> X86GenRegisterInfo::getRegMaskNames() const {
14342 static const char *Names[] = {
14343 "CSR_32",
14344 "CSR_32EHRet",
14345 "CSR_32_AllRegs",
14346 "CSR_32_AllRegs_AVX",
14347 "CSR_32_AllRegs_AVX512",
14348 "CSR_32_AllRegs_SSE",
14349 "CSR_32_RegCall",
14350 "CSR_32_RegCall_NoSSE",
14351 "CSR_64",
14352 "CSR_64EHRet",
14353 "CSR_64_AllRegs",
14354 "CSR_64_AllRegs_AVX",
14355 "CSR_64_AllRegs_AVX512",
14356 "CSR_64_AllRegs_NoSSE",
14357 "CSR_64_CXX_TLS_Darwin_PE",
14358 "CSR_64_CXX_TLS_Darwin_ViaCopy",
14359 "CSR_64_Intel_OCL_BI",
14360 "CSR_64_Intel_OCL_BI_AVX",
14361 "CSR_64_Intel_OCL_BI_AVX512",
14362 "CSR_64_MostRegs",
14363 "CSR_64_NoneRegs",
14364 "CSR_64_RT_AllRegs",
14365 "CSR_64_RT_AllRegs_AVX",
14366 "CSR_64_RT_MostRegs",
14367 "CSR_64_SwiftError",
14368 "CSR_64_SwiftTail",
14369 "CSR_64_TLS_Darwin",
14370 "CSR_IPRA_32",
14371 "CSR_IPRA_64",
14372 "CSR_NoRegs",
14373 "CSR_SysV64_RegCall",
14374 "CSR_SysV64_RegCall_NoSSE",
14375 "CSR_Win32_CFGuard_Check",
14376 "CSR_Win32_CFGuard_Check_NoSSE",
14377 "CSR_Win64",
14378 "CSR_Win64_Intel_OCL_BI_AVX",
14379 "CSR_Win64_Intel_OCL_BI_AVX512",
14380 "CSR_Win64_NoSSE",
14381 "CSR_Win64_RT_MostRegs",
14382 "CSR_Win64_RegCall",
14383 "CSR_Win64_RegCall_NoSSE",
14384 "CSR_Win64_SwiftError",
14385 "CSR_Win64_SwiftTail",
14386 };
14387 return ArrayRef(Names);
14388}
14389
14390const X86FrameLowering *
14391X86GenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
14392 return static_cast<const X86FrameLowering *>(
14393 MF.getSubtarget().getFrameLowering());
14394}
14395
14396} // end namespace llvm
14397
14398#endif // GET_REGINFO_TARGET_DESC
14399
14400