1//===-- X86AsmParser.cpp - Parse X86 assembly to MCInst instructions ------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "MCTargetDesc/X86BaseInfo.h"
10#include "MCTargetDesc/X86EncodingOptimization.h"
11#include "MCTargetDesc/X86IntelInstPrinter.h"
12#include "MCTargetDesc/X86MCAsmInfo.h"
13#include "MCTargetDesc/X86MCExpr.h"
14#include "MCTargetDesc/X86MCTargetDesc.h"
15#include "MCTargetDesc/X86TargetStreamer.h"
16#include "TargetInfo/X86TargetInfo.h"
17#include "X86Operand.h"
18#include "llvm/ADT/STLExtras.h"
19#include "llvm/ADT/SmallString.h"
20#include "llvm/ADT/SmallVector.h"
21#include "llvm/ADT/StringSwitch.h"
22#include "llvm/ADT/Twine.h"
23#include "llvm/MC/MCContext.h"
24#include "llvm/MC/MCExpr.h"
25#include "llvm/MC/MCInst.h"
26#include "llvm/MC/MCInstrInfo.h"
27#include "llvm/MC/MCParser/AsmLexer.h"
28#include "llvm/MC/MCParser/MCAsmParser.h"
29#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
30#include "llvm/MC/MCParser/MCTargetAsmParser.h"
31#include "llvm/MC/MCRegisterInfo.h"
32#include "llvm/MC/MCSection.h"
33#include "llvm/MC/MCStreamer.h"
34#include "llvm/MC/MCSubtargetInfo.h"
35#include "llvm/MC/MCSymbol.h"
36#include "llvm/MC/TargetRegistry.h"
37#include "llvm/Support/CommandLine.h"
38#include "llvm/Support/Compiler.h"
39#include "llvm/Support/SourceMgr.h"
40#include "llvm/Support/raw_ostream.h"
41#include <algorithm>
42#include <memory>
43
44using namespace llvm;
45
46static cl::opt<bool> LVIInlineAsmHardening(
47 "x86-experimental-lvi-inline-asm-hardening",
48 cl::desc("Harden inline assembly code that may be vulnerable to Load Value"
49 " Injection (LVI). This feature is experimental."), cl::Hidden);
50
51static bool checkScale(unsigned Scale, StringRef &ErrMsg) {
52 if (Scale != 1 && Scale != 2 && Scale != 4 && Scale != 8) {
53 ErrMsg = "scale factor in address must be 1, 2, 4 or 8";
54 return true;
55 }
56 return false;
57}
58
59namespace {
60
61// Including the generated SSE2AVX compression tables.
62#define GET_X86_SSE2AVX_TABLE
63#include "X86GenInstrMapping.inc"
64
65static const char OpPrecedence[] = {
66 0, // IC_OR
67 1, // IC_XOR
68 2, // IC_AND
69 4, // IC_LSHIFT
70 4, // IC_RSHIFT
71 5, // IC_PLUS
72 5, // IC_MINUS
73 6, // IC_MULTIPLY
74 6, // IC_DIVIDE
75 6, // IC_MOD
76 7, // IC_NOT
77 8, // IC_NEG
78 9, // IC_RPAREN
79 10, // IC_LPAREN
80 0, // IC_IMM
81 0, // IC_REGISTER
82 3, // IC_EQ
83 3, // IC_NE
84 3, // IC_LT
85 3, // IC_LE
86 3, // IC_GT
87 3 // IC_GE
88};
89
90class X86AsmParser : public MCTargetAsmParser {
91 ParseInstructionInfo *InstInfo;
92 bool Code16GCC;
93 unsigned ForcedDataPrefix = 0;
94
95 enum OpcodePrefix {
96 OpcodePrefix_Default,
97 OpcodePrefix_REX,
98 OpcodePrefix_REX2,
99 OpcodePrefix_VEX,
100 OpcodePrefix_VEX2,
101 OpcodePrefix_VEX3,
102 OpcodePrefix_EVEX,
103 };
104
105 OpcodePrefix ForcedOpcodePrefix = OpcodePrefix_Default;
106
107 enum DispEncoding {
108 DispEncoding_Default,
109 DispEncoding_Disp8,
110 DispEncoding_Disp32,
111 };
112
113 DispEncoding ForcedDispEncoding = DispEncoding_Default;
114
115 // Does this instruction use apx extended register?
116 bool UseApxExtendedReg = false;
117 // Is this instruction explicitly required not to update flags?
118 bool ForcedNoFlag = false;
119
120private:
121 SMLoc consumeToken() {
122 MCAsmParser &Parser = getParser();
123 SMLoc Result = Parser.getTok().getLoc();
124 Parser.Lex();
125 return Result;
126 }
127
128 bool tokenIsStartOfStatement(AsmToken::TokenKind Token) override {
129 return Token == AsmToken::LCurly;
130 }
131
132 X86TargetStreamer &getTargetStreamer() {
133 assert(getParser().getStreamer().getTargetStreamer() &&
134 "do not have a target streamer");
135 MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
136 return static_cast<X86TargetStreamer &>(TS);
137 }
138
139 unsigned MatchInstruction(const OperandVector &Operands, MCInst &Inst,
140 uint64_t &ErrorInfo, FeatureBitset &MissingFeatures,
141 bool matchingInlineAsm, unsigned VariantID = 0) {
142 // In Code16GCC mode, match as 32-bit.
143 if (Code16GCC)
144 SwitchMode(mode: X86::Is32Bit);
145 unsigned rv = MatchInstructionImpl(Operands, Inst, ErrorInfo,
146 MissingFeatures, matchingInlineAsm,
147 VariantID);
148 if (Code16GCC)
149 SwitchMode(mode: X86::Is16Bit);
150 return rv;
151 }
152
153 enum InfixCalculatorTok {
154 IC_OR = 0,
155 IC_XOR,
156 IC_AND,
157 IC_LSHIFT,
158 IC_RSHIFT,
159 IC_PLUS,
160 IC_MINUS,
161 IC_MULTIPLY,
162 IC_DIVIDE,
163 IC_MOD,
164 IC_NOT,
165 IC_NEG,
166 IC_RPAREN,
167 IC_LPAREN,
168 IC_IMM,
169 IC_REGISTER,
170 IC_EQ,
171 IC_NE,
172 IC_LT,
173 IC_LE,
174 IC_GT,
175 IC_GE
176 };
177
178 enum IntelOperatorKind {
179 IOK_INVALID = 0,
180 IOK_LENGTH,
181 IOK_SIZE,
182 IOK_TYPE,
183 };
184
185 enum MasmOperatorKind {
186 MOK_INVALID = 0,
187 MOK_LENGTHOF,
188 MOK_SIZEOF,
189 MOK_TYPE,
190 };
191
192 class InfixCalculator {
193 typedef std::pair< InfixCalculatorTok, int64_t > ICToken;
194 SmallVector<InfixCalculatorTok, 4> InfixOperatorStack;
195 SmallVector<ICToken, 4> PostfixStack;
196
197 bool isUnaryOperator(InfixCalculatorTok Op) const {
198 return Op == IC_NEG || Op == IC_NOT;
199 }
200
201 public:
202 int64_t popOperand() {
203 assert (!PostfixStack.empty() && "Poped an empty stack!");
204 ICToken Op = PostfixStack.pop_back_val();
205 if (!(Op.first == IC_IMM || Op.first == IC_REGISTER))
206 return -1; // The invalid Scale value will be caught later by checkScale
207 return Op.second;
208 }
209 void pushOperand(InfixCalculatorTok Op, int64_t Val = 0) {
210 assert ((Op == IC_IMM || Op == IC_REGISTER) &&
211 "Unexpected operand!");
212 PostfixStack.push_back(Elt: std::make_pair(x&: Op, y&: Val));
213 }
214
215 void popOperator() { InfixOperatorStack.pop_back(); }
216 void pushOperator(InfixCalculatorTok Op) {
217 // Push the new operator if the stack is empty.
218 if (InfixOperatorStack.empty()) {
219 InfixOperatorStack.push_back(Elt: Op);
220 return;
221 }
222
223 // Push the new operator if it has a higher precedence than the operator
224 // on the top of the stack or the operator on the top of the stack is a
225 // left parentheses.
226 unsigned Idx = InfixOperatorStack.size() - 1;
227 InfixCalculatorTok StackOp = InfixOperatorStack[Idx];
228 if (OpPrecedence[Op] > OpPrecedence[StackOp] || StackOp == IC_LPAREN) {
229 InfixOperatorStack.push_back(Elt: Op);
230 return;
231 }
232
233 // The operator on the top of the stack has higher precedence than the
234 // new operator.
235 unsigned ParenCount = 0;
236 while (true) {
237 // Nothing to process.
238 if (InfixOperatorStack.empty())
239 break;
240
241 Idx = InfixOperatorStack.size() - 1;
242 StackOp = InfixOperatorStack[Idx];
243 if (!(OpPrecedence[StackOp] >= OpPrecedence[Op] || ParenCount))
244 break;
245
246 // If we have an even parentheses count and we see a left parentheses,
247 // then stop processing.
248 if (!ParenCount && StackOp == IC_LPAREN)
249 break;
250
251 if (StackOp == IC_RPAREN) {
252 ++ParenCount;
253 InfixOperatorStack.pop_back();
254 } else if (StackOp == IC_LPAREN) {
255 --ParenCount;
256 InfixOperatorStack.pop_back();
257 } else {
258 InfixOperatorStack.pop_back();
259 PostfixStack.push_back(Elt: std::make_pair(x&: StackOp, y: 0));
260 }
261 }
262 // Push the new operator.
263 InfixOperatorStack.push_back(Elt: Op);
264 }
265
266 int64_t execute() {
267 // Push any remaining operators onto the postfix stack.
268 while (!InfixOperatorStack.empty()) {
269 InfixCalculatorTok StackOp = InfixOperatorStack.pop_back_val();
270 if (StackOp != IC_LPAREN && StackOp != IC_RPAREN)
271 PostfixStack.push_back(Elt: std::make_pair(x&: StackOp, y: 0));
272 }
273
274 if (PostfixStack.empty())
275 return 0;
276
277 SmallVector<ICToken, 16> OperandStack;
278 for (const ICToken &Op : PostfixStack) {
279 if (Op.first == IC_IMM || Op.first == IC_REGISTER) {
280 OperandStack.push_back(Elt: Op);
281 } else if (isUnaryOperator(Op: Op.first)) {
282 assert (OperandStack.size() > 0 && "Too few operands.");
283 ICToken Operand = OperandStack.pop_back_val();
284 assert (Operand.first == IC_IMM &&
285 "Unary operation with a register!");
286 switch (Op.first) {
287 default:
288 report_fatal_error(reason: "Unexpected operator!");
289 break;
290 case IC_NEG:
291 OperandStack.push_back(Elt: std::make_pair(x: IC_IMM, y: -Operand.second));
292 break;
293 case IC_NOT:
294 OperandStack.push_back(Elt: std::make_pair(x: IC_IMM, y: ~Operand.second));
295 break;
296 }
297 } else {
298 assert (OperandStack.size() > 1 && "Too few operands.");
299 int64_t Val;
300 ICToken Op2 = OperandStack.pop_back_val();
301 ICToken Op1 = OperandStack.pop_back_val();
302 switch (Op.first) {
303 default:
304 report_fatal_error(reason: "Unexpected operator!");
305 break;
306 case IC_PLUS:
307 Val = Op1.second + Op2.second;
308 OperandStack.push_back(Elt: std::make_pair(x: IC_IMM, y&: Val));
309 break;
310 case IC_MINUS:
311 Val = Op1.second - Op2.second;
312 OperandStack.push_back(Elt: std::make_pair(x: IC_IMM, y&: Val));
313 break;
314 case IC_MULTIPLY:
315 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
316 "Multiply operation with an immediate and a register!");
317 Val = Op1.second * Op2.second;
318 OperandStack.push_back(Elt: std::make_pair(x: IC_IMM, y&: Val));
319 break;
320 case IC_DIVIDE:
321 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
322 "Divide operation with an immediate and a register!");
323 assert (Op2.second != 0 && "Division by zero!");
324 Val = Op1.second / Op2.second;
325 OperandStack.push_back(Elt: std::make_pair(x: IC_IMM, y&: Val));
326 break;
327 case IC_MOD:
328 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
329 "Modulo operation with an immediate and a register!");
330 Val = Op1.second % Op2.second;
331 OperandStack.push_back(Elt: std::make_pair(x: IC_IMM, y&: Val));
332 break;
333 case IC_OR:
334 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
335 "Or operation with an immediate and a register!");
336 Val = Op1.second | Op2.second;
337 OperandStack.push_back(Elt: std::make_pair(x: IC_IMM, y&: Val));
338 break;
339 case IC_XOR:
340 assert(Op1.first == IC_IMM && Op2.first == IC_IMM &&
341 "Xor operation with an immediate and a register!");
342 Val = Op1.second ^ Op2.second;
343 OperandStack.push_back(Elt: std::make_pair(x: IC_IMM, y&: Val));
344 break;
345 case IC_AND:
346 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
347 "And operation with an immediate and a register!");
348 Val = Op1.second & Op2.second;
349 OperandStack.push_back(Elt: std::make_pair(x: IC_IMM, y&: Val));
350 break;
351 case IC_LSHIFT:
352 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
353 "Left shift operation with an immediate and a register!");
354 Val = Op1.second << Op2.second;
355 OperandStack.push_back(Elt: std::make_pair(x: IC_IMM, y&: Val));
356 break;
357 case IC_RSHIFT:
358 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
359 "Right shift operation with an immediate and a register!");
360 Val = Op1.second >> Op2.second;
361 OperandStack.push_back(Elt: std::make_pair(x: IC_IMM, y&: Val));
362 break;
363 case IC_EQ:
364 assert(Op1.first == IC_IMM && Op2.first == IC_IMM &&
365 "Equals operation with an immediate and a register!");
366 Val = (Op1.second == Op2.second) ? -1 : 0;
367 OperandStack.push_back(Elt: std::make_pair(x: IC_IMM, y&: Val));
368 break;
369 case IC_NE:
370 assert(Op1.first == IC_IMM && Op2.first == IC_IMM &&
371 "Not-equals operation with an immediate and a register!");
372 Val = (Op1.second != Op2.second) ? -1 : 0;
373 OperandStack.push_back(Elt: std::make_pair(x: IC_IMM, y&: Val));
374 break;
375 case IC_LT:
376 assert(Op1.first == IC_IMM && Op2.first == IC_IMM &&
377 "Less-than operation with an immediate and a register!");
378 Val = (Op1.second < Op2.second) ? -1 : 0;
379 OperandStack.push_back(Elt: std::make_pair(x: IC_IMM, y&: Val));
380 break;
381 case IC_LE:
382 assert(Op1.first == IC_IMM && Op2.first == IC_IMM &&
383 "Less-than-or-equal operation with an immediate and a "
384 "register!");
385 Val = (Op1.second <= Op2.second) ? -1 : 0;
386 OperandStack.push_back(Elt: std::make_pair(x: IC_IMM, y&: Val));
387 break;
388 case IC_GT:
389 assert(Op1.first == IC_IMM && Op2.first == IC_IMM &&
390 "Greater-than operation with an immediate and a register!");
391 Val = (Op1.second > Op2.second) ? -1 : 0;
392 OperandStack.push_back(Elt: std::make_pair(x: IC_IMM, y&: Val));
393 break;
394 case IC_GE:
395 assert(Op1.first == IC_IMM && Op2.first == IC_IMM &&
396 "Greater-than-or-equal operation with an immediate and a "
397 "register!");
398 Val = (Op1.second >= Op2.second) ? -1 : 0;
399 OperandStack.push_back(Elt: std::make_pair(x: IC_IMM, y&: Val));
400 break;
401 }
402 }
403 }
404 assert (OperandStack.size() == 1 && "Expected a single result.");
405 return OperandStack.pop_back_val().second;
406 }
407 };
408
409 enum IntelExprState {
410 IES_INIT,
411 IES_OR,
412 IES_XOR,
413 IES_AND,
414 IES_EQ,
415 IES_NE,
416 IES_LT,
417 IES_LE,
418 IES_GT,
419 IES_GE,
420 IES_LSHIFT,
421 IES_RSHIFT,
422 IES_PLUS,
423 IES_MINUS,
424 IES_OFFSET,
425 IES_CAST,
426 IES_NOT,
427 IES_MULTIPLY,
428 IES_DIVIDE,
429 IES_MOD,
430 IES_LBRAC,
431 IES_RBRAC,
432 IES_LPAREN,
433 IES_RPAREN,
434 IES_REGISTER,
435 IES_INTEGER,
436 IES_ERROR
437 };
438
439 class IntelExprStateMachine {
440 IntelExprState State = IES_INIT, PrevState = IES_ERROR;
441 MCRegister BaseReg, IndexReg, TmpReg;
442 unsigned Scale = 0;
443 int64_t Imm = 0;
444 const MCExpr *Sym = nullptr;
445 StringRef SymName;
446 InfixCalculator IC;
447 InlineAsmIdentifierInfo Info;
448 short BracCount = 0;
449 bool MemExpr = false;
450 bool BracketUsed = false;
451 bool OffsetOperator = false;
452 bool AttachToOperandIdx = false;
453 bool IsPIC = false;
454 SMLoc OffsetOperatorLoc;
455 AsmTypeInfo CurType;
456
457 bool setSymRef(const MCExpr *Val, StringRef ID, StringRef &ErrMsg) {
458 if (Sym) {
459 ErrMsg = "cannot use more than one symbol in memory operand";
460 return true;
461 }
462 Sym = Val;
463 SymName = ID;
464 return false;
465 }
466
467 public:
468 IntelExprStateMachine() = default;
469
470 void addImm(int64_t imm) { Imm += imm; }
471 short getBracCount() const { return BracCount; }
472 bool isMemExpr() const { return MemExpr; }
473 bool isBracketUsed() const { return BracketUsed; }
474 bool isOffsetOperator() const { return OffsetOperator; }
475 SMLoc getOffsetLoc() const { return OffsetOperatorLoc; }
476 MCRegister getBaseReg() const { return BaseReg; }
477 MCRegister getIndexReg() const { return IndexReg; }
478 unsigned getScale() const { return Scale; }
479 const MCExpr *getSym() const { return Sym; }
480 StringRef getSymName() const { return SymName; }
481 StringRef getType() const { return CurType.Name; }
482 unsigned getSize() const { return CurType.Size; }
483 unsigned getElementSize() const { return CurType.ElementSize; }
484 unsigned getLength() const { return CurType.Length; }
485 int64_t getImm() { return Imm + IC.execute(); }
486 bool isValidEndState() const {
487 return State == IES_RBRAC || State == IES_RPAREN ||
488 State == IES_INTEGER || State == IES_REGISTER ||
489 State == IES_OFFSET;
490 }
491
492 // Is the intel expression appended after an operand index.
493 // [OperandIdx][Intel Expression]
494 // This is neccessary for checking if it is an independent
495 // intel expression at back end when parse inline asm.
496 void setAppendAfterOperand() { AttachToOperandIdx = true; }
497
498 bool isPIC() const { return IsPIC; }
499 void setPIC() { IsPIC = true; }
500
501 bool hadError() const { return State == IES_ERROR; }
502 const InlineAsmIdentifierInfo &getIdentifierInfo() const { return Info; }
503
504 bool regsUseUpError(StringRef &ErrMsg) {
505 // This case mostly happen in inline asm, e.g. Arr[BaseReg + IndexReg]
506 // can not intruduce additional register in inline asm in PIC model.
507 if (IsPIC && AttachToOperandIdx)
508 ErrMsg = "Don't use 2 or more regs for mem offset in PIC model!";
509 else
510 ErrMsg = "BaseReg/IndexReg already set!";
511 return true;
512 }
513
514 void onOr() {
515 IntelExprState CurrState = State;
516 switch (State) {
517 default:
518 State = IES_ERROR;
519 break;
520 case IES_INTEGER:
521 case IES_RPAREN:
522 case IES_REGISTER:
523 State = IES_OR;
524 IC.pushOperator(Op: IC_OR);
525 break;
526 }
527 PrevState = CurrState;
528 }
529 void onXor() {
530 IntelExprState CurrState = State;
531 switch (State) {
532 default:
533 State = IES_ERROR;
534 break;
535 case IES_INTEGER:
536 case IES_RPAREN:
537 case IES_REGISTER:
538 State = IES_XOR;
539 IC.pushOperator(Op: IC_XOR);
540 break;
541 }
542 PrevState = CurrState;
543 }
544 void onAnd() {
545 IntelExprState CurrState = State;
546 switch (State) {
547 default:
548 State = IES_ERROR;
549 break;
550 case IES_INTEGER:
551 case IES_RPAREN:
552 case IES_REGISTER:
553 State = IES_AND;
554 IC.pushOperator(Op: IC_AND);
555 break;
556 }
557 PrevState = CurrState;
558 }
559 void onEq() {
560 IntelExprState CurrState = State;
561 switch (State) {
562 default:
563 State = IES_ERROR;
564 break;
565 case IES_INTEGER:
566 case IES_RPAREN:
567 case IES_REGISTER:
568 State = IES_EQ;
569 IC.pushOperator(Op: IC_EQ);
570 break;
571 }
572 PrevState = CurrState;
573 }
574 void onNE() {
575 IntelExprState CurrState = State;
576 switch (State) {
577 default:
578 State = IES_ERROR;
579 break;
580 case IES_INTEGER:
581 case IES_RPAREN:
582 case IES_REGISTER:
583 State = IES_NE;
584 IC.pushOperator(Op: IC_NE);
585 break;
586 }
587 PrevState = CurrState;
588 }
589 void onLT() {
590 IntelExprState CurrState = State;
591 switch (State) {
592 default:
593 State = IES_ERROR;
594 break;
595 case IES_INTEGER:
596 case IES_RPAREN:
597 case IES_REGISTER:
598 State = IES_LT;
599 IC.pushOperator(Op: IC_LT);
600 break;
601 }
602 PrevState = CurrState;
603 }
604 void onLE() {
605 IntelExprState CurrState = State;
606 switch (State) {
607 default:
608 State = IES_ERROR;
609 break;
610 case IES_INTEGER:
611 case IES_RPAREN:
612 case IES_REGISTER:
613 State = IES_LE;
614 IC.pushOperator(Op: IC_LE);
615 break;
616 }
617 PrevState = CurrState;
618 }
619 void onGT() {
620 IntelExprState CurrState = State;
621 switch (State) {
622 default:
623 State = IES_ERROR;
624 break;
625 case IES_INTEGER:
626 case IES_RPAREN:
627 case IES_REGISTER:
628 State = IES_GT;
629 IC.pushOperator(Op: IC_GT);
630 break;
631 }
632 PrevState = CurrState;
633 }
634 void onGE() {
635 IntelExprState CurrState = State;
636 switch (State) {
637 default:
638 State = IES_ERROR;
639 break;
640 case IES_INTEGER:
641 case IES_RPAREN:
642 case IES_REGISTER:
643 State = IES_GE;
644 IC.pushOperator(Op: IC_GE);
645 break;
646 }
647 PrevState = CurrState;
648 }
649 void onLShift() {
650 IntelExprState CurrState = State;
651 switch (State) {
652 default:
653 State = IES_ERROR;
654 break;
655 case IES_INTEGER:
656 case IES_RPAREN:
657 case IES_REGISTER:
658 State = IES_LSHIFT;
659 IC.pushOperator(Op: IC_LSHIFT);
660 break;
661 }
662 PrevState = CurrState;
663 }
664 void onRShift() {
665 IntelExprState CurrState = State;
666 switch (State) {
667 default:
668 State = IES_ERROR;
669 break;
670 case IES_INTEGER:
671 case IES_RPAREN:
672 case IES_REGISTER:
673 State = IES_RSHIFT;
674 IC.pushOperator(Op: IC_RSHIFT);
675 break;
676 }
677 PrevState = CurrState;
678 }
679 bool onPlus(StringRef &ErrMsg) {
680 IntelExprState CurrState = State;
681 switch (State) {
682 default:
683 State = IES_ERROR;
684 break;
685 case IES_INTEGER:
686 case IES_RPAREN:
687 case IES_REGISTER:
688 case IES_OFFSET:
689 State = IES_PLUS;
690 IC.pushOperator(Op: IC_PLUS);
691 if (CurrState == IES_REGISTER && PrevState != IES_MULTIPLY) {
692 // If we already have a BaseReg, then assume this is the IndexReg with
693 // no explicit scale.
694 if (!BaseReg) {
695 BaseReg = TmpReg;
696 } else {
697 if (IndexReg)
698 return regsUseUpError(ErrMsg);
699 IndexReg = TmpReg;
700 Scale = 0;
701 }
702 }
703 break;
704 }
705 PrevState = CurrState;
706 return false;
707 }
708 bool onMinus(StringRef &ErrMsg) {
709 IntelExprState CurrState = State;
710 switch (State) {
711 default:
712 State = IES_ERROR;
713 break;
714 case IES_OR:
715 case IES_XOR:
716 case IES_AND:
717 case IES_EQ:
718 case IES_NE:
719 case IES_LT:
720 case IES_LE:
721 case IES_GT:
722 case IES_GE:
723 case IES_LSHIFT:
724 case IES_RSHIFT:
725 case IES_PLUS:
726 case IES_NOT:
727 case IES_MULTIPLY:
728 case IES_DIVIDE:
729 case IES_MOD:
730 case IES_LPAREN:
731 case IES_RPAREN:
732 case IES_LBRAC:
733 case IES_RBRAC:
734 case IES_INTEGER:
735 case IES_REGISTER:
736 case IES_INIT:
737 case IES_OFFSET:
738 State = IES_MINUS;
739 // push minus operator if it is not a negate operator
740 if (CurrState == IES_REGISTER || CurrState == IES_RPAREN ||
741 CurrState == IES_INTEGER || CurrState == IES_RBRAC ||
742 CurrState == IES_OFFSET)
743 IC.pushOperator(Op: IC_MINUS);
744 else if (PrevState == IES_REGISTER && CurrState == IES_MULTIPLY) {
745 // We have negate operator for Scale: it's illegal
746 ErrMsg = "Scale can't be negative";
747 return true;
748 } else
749 IC.pushOperator(Op: IC_NEG);
750 if (CurrState == IES_REGISTER && PrevState != IES_MULTIPLY) {
751 // If we already have a BaseReg, then assume this is the IndexReg with
752 // no explicit scale.
753 if (!BaseReg) {
754 BaseReg = TmpReg;
755 } else {
756 if (IndexReg)
757 return regsUseUpError(ErrMsg);
758 IndexReg = TmpReg;
759 Scale = 0;
760 }
761 }
762 break;
763 }
764 PrevState = CurrState;
765 return false;
766 }
767 void onNot() {
768 IntelExprState CurrState = State;
769 switch (State) {
770 default:
771 State = IES_ERROR;
772 break;
773 case IES_OR:
774 case IES_XOR:
775 case IES_AND:
776 case IES_EQ:
777 case IES_NE:
778 case IES_LT:
779 case IES_LE:
780 case IES_GT:
781 case IES_GE:
782 case IES_LSHIFT:
783 case IES_RSHIFT:
784 case IES_PLUS:
785 case IES_MINUS:
786 case IES_NOT:
787 case IES_MULTIPLY:
788 case IES_DIVIDE:
789 case IES_MOD:
790 case IES_LPAREN:
791 case IES_LBRAC:
792 case IES_INIT:
793 State = IES_NOT;
794 IC.pushOperator(Op: IC_NOT);
795 break;
796 }
797 PrevState = CurrState;
798 }
799 bool onRegister(MCRegister Reg, StringRef &ErrMsg) {
800 IntelExprState CurrState = State;
801 switch (State) {
802 default:
803 State = IES_ERROR;
804 break;
805 case IES_PLUS:
806 case IES_LPAREN:
807 case IES_LBRAC:
808 State = IES_REGISTER;
809 TmpReg = Reg;
810 IC.pushOperand(Op: IC_REGISTER);
811 break;
812 case IES_MULTIPLY:
813 // Index Register - Scale * Register
814 if (PrevState == IES_INTEGER) {
815 if (IndexReg)
816 return regsUseUpError(ErrMsg);
817 State = IES_REGISTER;
818 IndexReg = Reg;
819 // Get the scale and replace the 'Scale * Register' with '0'.
820 Scale = IC.popOperand();
821 if (checkScale(Scale, ErrMsg))
822 return true;
823 IC.pushOperand(Op: IC_IMM);
824 IC.popOperator();
825 } else {
826 State = IES_ERROR;
827 }
828 break;
829 }
830 PrevState = CurrState;
831 return false;
832 }
833 bool onIdentifierExpr(const MCExpr *SymRef, StringRef SymRefName,
834 const InlineAsmIdentifierInfo &IDInfo,
835 const AsmTypeInfo &Type, bool ParsingMSInlineAsm,
836 StringRef &ErrMsg) {
837 // InlineAsm: Treat an enum value as an integer
838 if (ParsingMSInlineAsm)
839 if (IDInfo.isKind(kind: InlineAsmIdentifierInfo::IK_EnumVal))
840 return onInteger(TmpInt: IDInfo.Enum.EnumVal, ErrMsg);
841 // Treat a symbolic constant like an integer
842 if (auto *CE = dyn_cast<MCConstantExpr>(Val: SymRef))
843 return onInteger(TmpInt: CE->getValue(), ErrMsg);
844 PrevState = State;
845 switch (State) {
846 default:
847 State = IES_ERROR;
848 break;
849 case IES_CAST:
850 case IES_PLUS:
851 case IES_MINUS:
852 case IES_NOT:
853 case IES_INIT:
854 case IES_LBRAC:
855 case IES_LPAREN:
856 if (setSymRef(Val: SymRef, ID: SymRefName, ErrMsg))
857 return true;
858 MemExpr = true;
859 State = IES_INTEGER;
860 IC.pushOperand(Op: IC_IMM);
861 if (ParsingMSInlineAsm)
862 Info = IDInfo;
863 setTypeInfo(Type);
864 break;
865 }
866 return false;
867 }
868 bool onInteger(int64_t TmpInt, StringRef &ErrMsg) {
869 IntelExprState CurrState = State;
870 switch (State) {
871 default:
872 State = IES_ERROR;
873 break;
874 case IES_PLUS:
875 case IES_MINUS:
876 case IES_NOT:
877 case IES_OR:
878 case IES_XOR:
879 case IES_AND:
880 case IES_EQ:
881 case IES_NE:
882 case IES_LT:
883 case IES_LE:
884 case IES_GT:
885 case IES_GE:
886 case IES_LSHIFT:
887 case IES_RSHIFT:
888 case IES_DIVIDE:
889 case IES_MOD:
890 case IES_MULTIPLY:
891 case IES_LPAREN:
892 case IES_INIT:
893 case IES_LBRAC:
894 State = IES_INTEGER;
895 if (PrevState == IES_REGISTER && CurrState == IES_MULTIPLY) {
896 // Index Register - Register * Scale
897 if (IndexReg)
898 return regsUseUpError(ErrMsg);
899 IndexReg = TmpReg;
900 Scale = TmpInt;
901 if (checkScale(Scale, ErrMsg))
902 return true;
903 // Get the scale and replace the 'Register * Scale' with '0'.
904 IC.popOperator();
905 } else {
906 IC.pushOperand(Op: IC_IMM, Val: TmpInt);
907 }
908 break;
909 }
910 PrevState = CurrState;
911 return false;
912 }
913 void onStar() {
914 PrevState = State;
915 switch (State) {
916 default:
917 State = IES_ERROR;
918 break;
919 case IES_INTEGER:
920 case IES_REGISTER:
921 case IES_RPAREN:
922 State = IES_MULTIPLY;
923 IC.pushOperator(Op: IC_MULTIPLY);
924 break;
925 }
926 }
927 void onDivide() {
928 PrevState = State;
929 switch (State) {
930 default:
931 State = IES_ERROR;
932 break;
933 case IES_INTEGER:
934 case IES_RPAREN:
935 State = IES_DIVIDE;
936 IC.pushOperator(Op: IC_DIVIDE);
937 break;
938 }
939 }
940 void onMod() {
941 PrevState = State;
942 switch (State) {
943 default:
944 State = IES_ERROR;
945 break;
946 case IES_INTEGER:
947 case IES_RPAREN:
948 State = IES_MOD;
949 IC.pushOperator(Op: IC_MOD);
950 break;
951 }
952 }
953 bool onLBrac() {
954 if (BracCount)
955 return true;
956 PrevState = State;
957 switch (State) {
958 default:
959 State = IES_ERROR;
960 break;
961 case IES_RBRAC:
962 case IES_INTEGER:
963 case IES_RPAREN:
964 State = IES_PLUS;
965 IC.pushOperator(Op: IC_PLUS);
966 CurType.Length = 1;
967 CurType.Size = CurType.ElementSize;
968 break;
969 case IES_INIT:
970 case IES_CAST:
971 assert(!BracCount && "BracCount should be zero on parsing's start");
972 State = IES_LBRAC;
973 break;
974 }
975 MemExpr = true;
976 BracketUsed = true;
977 BracCount++;
978 return false;
979 }
980 bool onRBrac(StringRef &ErrMsg) {
981 IntelExprState CurrState = State;
982 switch (State) {
983 default:
984 State = IES_ERROR;
985 break;
986 case IES_INTEGER:
987 case IES_OFFSET:
988 case IES_REGISTER:
989 case IES_RPAREN:
990 if (BracCount-- != 1) {
991 ErrMsg = "unexpected bracket encountered";
992 return true;
993 }
994 State = IES_RBRAC;
995 if (CurrState == IES_REGISTER && PrevState != IES_MULTIPLY) {
996 // If we already have a BaseReg, then assume this is the IndexReg with
997 // no explicit scale.
998 if (!BaseReg) {
999 BaseReg = TmpReg;
1000 } else {
1001 if (IndexReg)
1002 return regsUseUpError(ErrMsg);
1003 IndexReg = TmpReg;
1004 Scale = 0;
1005 }
1006 }
1007 break;
1008 }
1009 PrevState = CurrState;
1010 return false;
1011 }
1012 void onLParen() {
1013 IntelExprState CurrState = State;
1014 switch (State) {
1015 default:
1016 State = IES_ERROR;
1017 break;
1018 case IES_PLUS:
1019 case IES_MINUS:
1020 case IES_NOT:
1021 case IES_OR:
1022 case IES_XOR:
1023 case IES_AND:
1024 case IES_EQ:
1025 case IES_NE:
1026 case IES_LT:
1027 case IES_LE:
1028 case IES_GT:
1029 case IES_GE:
1030 case IES_LSHIFT:
1031 case IES_RSHIFT:
1032 case IES_MULTIPLY:
1033 case IES_DIVIDE:
1034 case IES_MOD:
1035 case IES_LPAREN:
1036 case IES_INIT:
1037 case IES_LBRAC:
1038 State = IES_LPAREN;
1039 IC.pushOperator(Op: IC_LPAREN);
1040 break;
1041 }
1042 PrevState = CurrState;
1043 }
1044 void onRParen() {
1045 PrevState = State;
1046 switch (State) {
1047 default:
1048 State = IES_ERROR;
1049 break;
1050 case IES_INTEGER:
1051 case IES_OFFSET:
1052 case IES_REGISTER:
1053 case IES_RBRAC:
1054 case IES_RPAREN:
1055 State = IES_RPAREN;
1056 IC.pushOperator(Op: IC_RPAREN);
1057 break;
1058 }
1059 }
1060 bool onOffset(const MCExpr *Val, SMLoc OffsetLoc, StringRef ID,
1061 const InlineAsmIdentifierInfo &IDInfo,
1062 bool ParsingMSInlineAsm, StringRef &ErrMsg) {
1063 PrevState = State;
1064 switch (State) {
1065 default:
1066 ErrMsg = "unexpected offset operator expression";
1067 return true;
1068 case IES_PLUS:
1069 case IES_INIT:
1070 case IES_LBRAC:
1071 if (setSymRef(Val, ID, ErrMsg))
1072 return true;
1073 OffsetOperator = true;
1074 OffsetOperatorLoc = OffsetLoc;
1075 State = IES_OFFSET;
1076 // As we cannot yet resolve the actual value (offset), we retain
1077 // the requested semantics by pushing a '0' to the operands stack
1078 IC.pushOperand(Op: IC_IMM);
1079 if (ParsingMSInlineAsm) {
1080 Info = IDInfo;
1081 }
1082 break;
1083 }
1084 return false;
1085 }
1086 void onCast(AsmTypeInfo Info) {
1087 PrevState = State;
1088 switch (State) {
1089 default:
1090 State = IES_ERROR;
1091 break;
1092 case IES_LPAREN:
1093 setTypeInfo(Info);
1094 State = IES_CAST;
1095 break;
1096 }
1097 }
1098 void setTypeInfo(AsmTypeInfo Type) { CurType = Type; }
1099 };
1100
1101 bool Error(SMLoc L, const Twine &Msg, SMRange Range = std::nullopt,
1102 bool MatchingInlineAsm = false) {
1103 MCAsmParser &Parser = getParser();
1104 if (MatchingInlineAsm) {
1105 return false;
1106 }
1107 return Parser.Error(L, Msg, Range);
1108 }
1109
1110 bool MatchRegisterByName(MCRegister &RegNo, StringRef RegName, SMLoc StartLoc,
1111 SMLoc EndLoc);
1112 bool ParseRegister(MCRegister &RegNo, SMLoc &StartLoc, SMLoc &EndLoc,
1113 bool RestoreOnFailure);
1114
1115 std::unique_ptr<X86Operand> DefaultMemSIOperand(SMLoc Loc);
1116 std::unique_ptr<X86Operand> DefaultMemDIOperand(SMLoc Loc);
1117 bool IsSIReg(MCRegister Reg);
1118 MCRegister GetSIDIForRegClass(unsigned RegClassID, bool IsSIReg);
1119 void
1120 AddDefaultSrcDestOperands(OperandVector &Operands,
1121 std::unique_ptr<llvm::MCParsedAsmOperand> &&Src,
1122 std::unique_ptr<llvm::MCParsedAsmOperand> &&Dst);
1123 bool VerifyAndAdjustOperands(OperandVector &OrigOperands,
1124 OperandVector &FinalOperands);
1125 bool parseOperand(OperandVector &Operands, StringRef Name);
1126 bool parseATTOperand(OperandVector &Operands);
1127 bool parseIntelOperand(OperandVector &Operands, StringRef Name);
1128 bool ParseIntelOffsetOperator(const MCExpr *&Val, StringRef &ID,
1129 InlineAsmIdentifierInfo &Info, SMLoc &End);
1130 bool ParseIntelDotOperator(IntelExprStateMachine &SM, SMLoc &End);
1131 unsigned IdentifyIntelInlineAsmOperator(StringRef Name);
1132 unsigned ParseIntelInlineAsmOperator(unsigned OpKind);
1133 unsigned IdentifyMasmOperator(StringRef Name);
1134 bool ParseMasmOperator(unsigned OpKind, int64_t &Val);
1135 bool ParseRoundingModeOp(SMLoc Start, OperandVector &Operands);
1136 bool parseCFlagsOp(OperandVector &Operands);
1137 bool ParseIntelNamedOperator(StringRef Name, IntelExprStateMachine &SM,
1138 bool &ParseError, SMLoc &End);
1139 bool ParseMasmNamedOperator(StringRef Name, IntelExprStateMachine &SM,
1140 bool &ParseError, SMLoc &End);
1141 void RewriteIntelExpression(IntelExprStateMachine &SM, SMLoc Start,
1142 SMLoc End);
1143 bool ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End);
1144 bool ParseIntelInlineAsmIdentifier(const MCExpr *&Val, StringRef &Identifier,
1145 InlineAsmIdentifierInfo &Info,
1146 bool IsUnevaluatedOperand, SMLoc &End,
1147 bool IsParsingOffsetOperator = false);
1148 void tryParseOperandIdx(AsmToken::TokenKind PrevTK,
1149 IntelExprStateMachine &SM);
1150
1151 bool ParseMemOperand(MCRegister SegReg, const MCExpr *Disp, SMLoc StartLoc,
1152 SMLoc EndLoc, OperandVector &Operands);
1153
1154 X86::CondCode ParseConditionCode(StringRef CCode);
1155
1156 bool ParseIntelMemoryOperandSize(unsigned &Size);
1157 bool CreateMemForMSInlineAsm(MCRegister SegReg, const MCExpr *Disp,
1158 MCRegister BaseReg, MCRegister IndexReg,
1159 unsigned Scale, bool NonAbsMem, SMLoc Start,
1160 SMLoc End, unsigned Size, StringRef Identifier,
1161 const InlineAsmIdentifierInfo &Info,
1162 OperandVector &Operands);
1163
1164 bool parseDirectiveArch();
1165 bool parseDirectiveNops(SMLoc L);
1166 bool parseDirectiveEven(SMLoc L);
1167 bool ParseDirectiveCode(StringRef IDVal, SMLoc L);
1168
1169 /// CodeView FPO data directives.
1170 bool parseDirectiveFPOProc(SMLoc L);
1171 bool parseDirectiveFPOSetFrame(SMLoc L);
1172 bool parseDirectiveFPOPushReg(SMLoc L);
1173 bool parseDirectiveFPOStackAlloc(SMLoc L);
1174 bool parseDirectiveFPOStackAlign(SMLoc L);
1175 bool parseDirectiveFPOEndPrologue(SMLoc L);
1176 bool parseDirectiveFPOEndProc(SMLoc L);
1177
1178 /// SEH directives.
1179 bool parseSEHRegisterNumber(unsigned RegClassID, MCRegister &RegNo);
1180 bool parseDirectiveSEHPushReg(SMLoc);
1181 bool parseDirectiveSEHSetFrame(SMLoc);
1182 bool parseDirectiveSEHSaveReg(SMLoc);
1183 bool parseDirectiveSEHSaveXMM(SMLoc);
1184 bool parseDirectiveSEHPushFrame(SMLoc);
1185
1186 unsigned checkTargetMatchPredicate(MCInst &Inst) override;
1187
1188 bool validateInstruction(MCInst &Inst, const OperandVector &Ops);
1189 bool processInstruction(MCInst &Inst, const OperandVector &Ops);
1190
1191 // Load Value Injection (LVI) Mitigations for machine code
1192 void emitWarningForSpecialLVIInstruction(SMLoc Loc);
1193 void applyLVICFIMitigation(MCInst &Inst, MCStreamer &Out);
1194 void applyLVILoadHardeningMitigation(MCInst &Inst, MCStreamer &Out);
1195
1196 /// Wrapper around MCStreamer::emitInstruction(). Possibly adds
1197 /// instrumentation around Inst.
1198 void emitInstruction(MCInst &Inst, OperandVector &Operands, MCStreamer &Out);
1199
1200 bool matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1201 OperandVector &Operands, MCStreamer &Out,
1202 uint64_t &ErrorInfo,
1203 bool MatchingInlineAsm) override;
1204
1205 void MatchFPUWaitAlias(SMLoc IDLoc, X86Operand &Op, OperandVector &Operands,
1206 MCStreamer &Out, bool MatchingInlineAsm);
1207
1208 bool ErrorMissingFeature(SMLoc IDLoc, const FeatureBitset &MissingFeatures,
1209 bool MatchingInlineAsm);
1210
1211 bool matchAndEmitATTInstruction(SMLoc IDLoc, unsigned &Opcode, MCInst &Inst,
1212 OperandVector &Operands, MCStreamer &Out,
1213 uint64_t &ErrorInfo, bool MatchingInlineAsm);
1214
1215 bool matchAndEmitIntelInstruction(SMLoc IDLoc, unsigned &Opcode, MCInst &Inst,
1216 OperandVector &Operands, MCStreamer &Out,
1217 uint64_t &ErrorInfo,
1218 bool MatchingInlineAsm);
1219
1220 bool omitRegisterFromClobberLists(MCRegister Reg) override;
1221
1222 /// Parses AVX512 specific operand primitives: masked registers ({%k<NUM>}, {z})
1223 /// and memory broadcasting ({1to<NUM>}) primitives, updating Operands vector if required.
1224 /// return false if no parsing errors occurred, true otherwise.
1225 bool HandleAVX512Operand(OperandVector &Operands);
1226
1227 bool ParseZ(std::unique_ptr<X86Operand> &Z, const SMLoc &StartLoc);
1228
1229 bool is64BitMode() const {
1230 // FIXME: Can tablegen auto-generate this?
1231 return getSTI().hasFeature(Feature: X86::Is64Bit);
1232 }
1233 bool is32BitMode() const {
1234 // FIXME: Can tablegen auto-generate this?
1235 return getSTI().hasFeature(Feature: X86::Is32Bit);
1236 }
1237 bool is16BitMode() const {
1238 // FIXME: Can tablegen auto-generate this?
1239 return getSTI().hasFeature(Feature: X86::Is16Bit);
1240 }
1241 void SwitchMode(unsigned mode) {
1242 MCSubtargetInfo &STI = copySTI();
1243 FeatureBitset AllModes({X86::Is64Bit, X86::Is32Bit, X86::Is16Bit});
1244 FeatureBitset OldMode = STI.getFeatureBits() & AllModes;
1245 FeatureBitset FB = ComputeAvailableFeatures(
1246 FB: STI.ToggleFeature(FB: OldMode.flip(I: mode)));
1247 setAvailableFeatures(FB);
1248
1249 assert(FeatureBitset({mode}) == (STI.getFeatureBits() & AllModes));
1250 }
1251
1252 unsigned getPointerWidth() {
1253 if (is16BitMode()) return 16;
1254 if (is32BitMode()) return 32;
1255 if (is64BitMode()) return 64;
1256 llvm_unreachable("invalid mode");
1257 }
1258
1259 bool isParsingIntelSyntax() {
1260 return getParser().getAssemblerDialect();
1261 }
1262
1263 /// @name Auto-generated Matcher Functions
1264 /// {
1265
1266#define GET_ASSEMBLER_HEADER
1267#include "X86GenAsmMatcher.inc"
1268
1269 /// }
1270
1271public:
1272 enum X86MatchResultTy {
1273 Match_Unsupported = FIRST_TARGET_MATCH_RESULT_TY,
1274#define GET_OPERAND_DIAGNOSTIC_TYPES
1275#include "X86GenAsmMatcher.inc"
1276 };
1277
1278 X86AsmParser(const MCSubtargetInfo &sti, MCAsmParser &Parser,
1279 const MCInstrInfo &mii, const MCTargetOptions &Options)
1280 : MCTargetAsmParser(Options, sti, mii), InstInfo(nullptr),
1281 Code16GCC(false) {
1282
1283 Parser.addAliasForDirective(Directive: ".word", Alias: ".2byte");
1284
1285 // Initialize the set of available features.
1286 setAvailableFeatures(ComputeAvailableFeatures(FB: getSTI().getFeatureBits()));
1287 }
1288
1289 bool parseRegister(MCRegister &Reg, SMLoc &StartLoc, SMLoc &EndLoc) override;
1290 ParseStatus tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
1291 SMLoc &EndLoc) override;
1292
1293 bool parsePrimaryExpr(const MCExpr *&Res, SMLoc &EndLoc) override;
1294
1295 bool parseInstruction(ParseInstructionInfo &Info, StringRef Name,
1296 SMLoc NameLoc, OperandVector &Operands) override;
1297
1298 bool ParseDirective(AsmToken DirectiveID) override;
1299};
1300} // end anonymous namespace
1301
1302#define GET_REGISTER_MATCHER
1303#define GET_SUBTARGET_FEATURE_NAME
1304#include "X86GenAsmMatcher.inc"
1305
1306static bool CheckBaseRegAndIndexRegAndScale(MCRegister BaseReg,
1307 MCRegister IndexReg, unsigned Scale,
1308 bool Is64BitMode,
1309 StringRef &ErrMsg) {
1310 // If we have both a base register and an index register make sure they are
1311 // both 64-bit or 32-bit registers.
1312 // To support VSIB, IndexReg can be 128-bit or 256-bit registers.
1313
1314 if (BaseReg &&
1315 !(BaseReg == X86::RIP || BaseReg == X86::EIP ||
1316 X86MCRegisterClasses[X86::GR16RegClassID].contains(Reg: BaseReg) ||
1317 X86MCRegisterClasses[X86::GR32RegClassID].contains(Reg: BaseReg) ||
1318 X86MCRegisterClasses[X86::GR64RegClassID].contains(Reg: BaseReg))) {
1319 ErrMsg = "invalid base+index expression";
1320 return true;
1321 }
1322
1323 if (IndexReg &&
1324 !(IndexReg == X86::EIZ || IndexReg == X86::RIZ ||
1325 X86MCRegisterClasses[X86::GR16RegClassID].contains(Reg: IndexReg) ||
1326 X86MCRegisterClasses[X86::GR32RegClassID].contains(Reg: IndexReg) ||
1327 X86MCRegisterClasses[X86::GR64RegClassID].contains(Reg: IndexReg) ||
1328 X86MCRegisterClasses[X86::VR128XRegClassID].contains(Reg: IndexReg) ||
1329 X86MCRegisterClasses[X86::VR256XRegClassID].contains(Reg: IndexReg) ||
1330 X86MCRegisterClasses[X86::VR512RegClassID].contains(Reg: IndexReg))) {
1331 ErrMsg = "invalid base+index expression";
1332 return true;
1333 }
1334
1335 if (((BaseReg == X86::RIP || BaseReg == X86::EIP) && IndexReg) ||
1336 IndexReg == X86::EIP || IndexReg == X86::RIP || IndexReg == X86::ESP ||
1337 IndexReg == X86::RSP) {
1338 ErrMsg = "invalid base+index expression";
1339 return true;
1340 }
1341
1342 // Check for use of invalid 16-bit registers. Only BX/BP/SI/DI are allowed,
1343 // and then only in non-64-bit modes.
1344 if (X86MCRegisterClasses[X86::GR16RegClassID].contains(Reg: BaseReg) &&
1345 (Is64BitMode || (BaseReg != X86::BX && BaseReg != X86::BP &&
1346 BaseReg != X86::SI && BaseReg != X86::DI))) {
1347 ErrMsg = "invalid 16-bit base register";
1348 return true;
1349 }
1350
1351 if (!BaseReg &&
1352 X86MCRegisterClasses[X86::GR16RegClassID].contains(Reg: IndexReg)) {
1353 ErrMsg = "16-bit memory operand may not include only index register";
1354 return true;
1355 }
1356
1357 if (BaseReg && IndexReg) {
1358 if (X86MCRegisterClasses[X86::GR64RegClassID].contains(Reg: BaseReg) &&
1359 (X86MCRegisterClasses[X86::GR16RegClassID].contains(Reg: IndexReg) ||
1360 X86MCRegisterClasses[X86::GR32RegClassID].contains(Reg: IndexReg) ||
1361 IndexReg == X86::EIZ)) {
1362 ErrMsg = "base register is 64-bit, but index register is not";
1363 return true;
1364 }
1365 if (X86MCRegisterClasses[X86::GR32RegClassID].contains(Reg: BaseReg) &&
1366 (X86MCRegisterClasses[X86::GR16RegClassID].contains(Reg: IndexReg) ||
1367 X86MCRegisterClasses[X86::GR64RegClassID].contains(Reg: IndexReg) ||
1368 IndexReg == X86::RIZ)) {
1369 ErrMsg = "base register is 32-bit, but index register is not";
1370 return true;
1371 }
1372 if (X86MCRegisterClasses[X86::GR16RegClassID].contains(Reg: BaseReg)) {
1373 if (X86MCRegisterClasses[X86::GR32RegClassID].contains(Reg: IndexReg) ||
1374 X86MCRegisterClasses[X86::GR64RegClassID].contains(Reg: IndexReg)) {
1375 ErrMsg = "base register is 16-bit, but index register is not";
1376 return true;
1377 }
1378 if ((BaseReg != X86::BX && BaseReg != X86::BP) ||
1379 (IndexReg != X86::SI && IndexReg != X86::DI)) {
1380 ErrMsg = "invalid 16-bit base/index register combination";
1381 return true;
1382 }
1383 }
1384 }
1385
1386 // RIP/EIP-relative addressing is only supported in 64-bit mode.
1387 if (!Is64BitMode && (BaseReg == X86::RIP || BaseReg == X86::EIP)) {
1388 ErrMsg = "IP-relative addressing requires 64-bit mode";
1389 return true;
1390 }
1391
1392 return checkScale(Scale, ErrMsg);
1393}
1394
1395bool X86AsmParser::MatchRegisterByName(MCRegister &RegNo, StringRef RegName,
1396 SMLoc StartLoc, SMLoc EndLoc) {
1397 // If we encounter a %, ignore it. This code handles registers with and
1398 // without the prefix, unprefixed registers can occur in cfi directives.
1399 RegName.consume_front(Prefix: "%");
1400
1401 RegNo = MatchRegisterName(Name: RegName);
1402
1403 // If the match failed, try the register name as lowercase.
1404 if (!RegNo)
1405 RegNo = MatchRegisterName(Name: RegName.lower());
1406
1407 // The "flags" and "mxcsr" registers cannot be referenced directly.
1408 // Treat it as an identifier instead.
1409 if (isParsingMSInlineAsm() && isParsingIntelSyntax() &&
1410 (RegNo == X86::EFLAGS || RegNo == X86::MXCSR))
1411 RegNo = MCRegister();
1412
1413 if (!is64BitMode()) {
1414 // FIXME: This should be done using Requires<Not64BitMode> and
1415 // Requires<In64BitMode> so "eiz" usage in 64-bit instructions can be also
1416 // checked.
1417 if (RegNo == X86::RIZ || RegNo == X86::RIP ||
1418 X86MCRegisterClasses[X86::GR64RegClassID].contains(Reg: RegNo) ||
1419 X86II::isX86_64NonExtLowByteReg(Reg: RegNo) ||
1420 X86II::isX86_64ExtendedReg(Reg: RegNo)) {
1421 return Error(L: StartLoc,
1422 Msg: "register %" + RegName + " is only available in 64-bit mode",
1423 Range: SMRange(StartLoc, EndLoc));
1424 }
1425 }
1426
1427 if (X86II::isApxExtendedReg(Reg: RegNo))
1428 UseApxExtendedReg = true;
1429
1430 // If this is "db[0-15]", match it as an alias
1431 // for dr[0-15].
1432 if (!RegNo && RegName.starts_with(Prefix: "db")) {
1433 if (RegName.size() == 3) {
1434 switch (RegName[2]) {
1435 case '0':
1436 RegNo = X86::DR0;
1437 break;
1438 case '1':
1439 RegNo = X86::DR1;
1440 break;
1441 case '2':
1442 RegNo = X86::DR2;
1443 break;
1444 case '3':
1445 RegNo = X86::DR3;
1446 break;
1447 case '4':
1448 RegNo = X86::DR4;
1449 break;
1450 case '5':
1451 RegNo = X86::DR5;
1452 break;
1453 case '6':
1454 RegNo = X86::DR6;
1455 break;
1456 case '7':
1457 RegNo = X86::DR7;
1458 break;
1459 case '8':
1460 RegNo = X86::DR8;
1461 break;
1462 case '9':
1463 RegNo = X86::DR9;
1464 break;
1465 }
1466 } else if (RegName.size() == 4 && RegName[2] == '1') {
1467 switch (RegName[3]) {
1468 case '0':
1469 RegNo = X86::DR10;
1470 break;
1471 case '1':
1472 RegNo = X86::DR11;
1473 break;
1474 case '2':
1475 RegNo = X86::DR12;
1476 break;
1477 case '3':
1478 RegNo = X86::DR13;
1479 break;
1480 case '4':
1481 RegNo = X86::DR14;
1482 break;
1483 case '5':
1484 RegNo = X86::DR15;
1485 break;
1486 }
1487 }
1488 }
1489
1490 if (!RegNo) {
1491 if (isParsingIntelSyntax())
1492 return true;
1493 return Error(L: StartLoc, Msg: "invalid register name", Range: SMRange(StartLoc, EndLoc));
1494 }
1495 return false;
1496}
1497
1498bool X86AsmParser::ParseRegister(MCRegister &RegNo, SMLoc &StartLoc,
1499 SMLoc &EndLoc, bool RestoreOnFailure) {
1500 MCAsmParser &Parser = getParser();
1501 AsmLexer &Lexer = getLexer();
1502 RegNo = MCRegister();
1503
1504 SmallVector<AsmToken, 5> Tokens;
1505 auto OnFailure = [RestoreOnFailure, &Lexer, &Tokens]() {
1506 if (RestoreOnFailure) {
1507 while (!Tokens.empty()) {
1508 Lexer.UnLex(Token: Tokens.pop_back_val());
1509 }
1510 }
1511 };
1512
1513 const AsmToken &PercentTok = Parser.getTok();
1514 StartLoc = PercentTok.getLoc();
1515
1516 // If we encounter a %, ignore it. This code handles registers with and
1517 // without the prefix, unprefixed registers can occur in cfi directives.
1518 if (!isParsingIntelSyntax() && PercentTok.is(K: AsmToken::Percent)) {
1519 Tokens.push_back(Elt: PercentTok);
1520 Parser.Lex(); // Eat percent token.
1521 }
1522
1523 const AsmToken &Tok = Parser.getTok();
1524 EndLoc = Tok.getEndLoc();
1525
1526 if (Tok.isNot(K: AsmToken::Identifier)) {
1527 OnFailure();
1528 if (isParsingIntelSyntax()) return true;
1529 return Error(L: StartLoc, Msg: "invalid register name",
1530 Range: SMRange(StartLoc, EndLoc));
1531 }
1532
1533 if (MatchRegisterByName(RegNo, RegName: Tok.getString(), StartLoc, EndLoc)) {
1534 OnFailure();
1535 return true;
1536 }
1537
1538 // Parse "%st" as "%st(0)" and "%st(1)", which is multiple tokens.
1539 if (RegNo == X86::ST0) {
1540 Tokens.push_back(Elt: Tok);
1541 Parser.Lex(); // Eat 'st'
1542
1543 // Check to see if we have '(4)' after %st.
1544 if (Lexer.isNot(K: AsmToken::LParen))
1545 return false;
1546 // Lex the paren.
1547 Tokens.push_back(Elt: Parser.getTok());
1548 Parser.Lex();
1549
1550 const AsmToken &IntTok = Parser.getTok();
1551 if (IntTok.isNot(K: AsmToken::Integer)) {
1552 OnFailure();
1553 return Error(L: IntTok.getLoc(), Msg: "expected stack index");
1554 }
1555 switch (IntTok.getIntVal()) {
1556 case 0: RegNo = X86::ST0; break;
1557 case 1: RegNo = X86::ST1; break;
1558 case 2: RegNo = X86::ST2; break;
1559 case 3: RegNo = X86::ST3; break;
1560 case 4: RegNo = X86::ST4; break;
1561 case 5: RegNo = X86::ST5; break;
1562 case 6: RegNo = X86::ST6; break;
1563 case 7: RegNo = X86::ST7; break;
1564 default:
1565 OnFailure();
1566 return Error(L: IntTok.getLoc(), Msg: "invalid stack index");
1567 }
1568
1569 // Lex IntTok
1570 Tokens.push_back(Elt: IntTok);
1571 Parser.Lex();
1572 if (Lexer.isNot(K: AsmToken::RParen)) {
1573 OnFailure();
1574 return Error(L: Parser.getTok().getLoc(), Msg: "expected ')'");
1575 }
1576
1577 EndLoc = Parser.getTok().getEndLoc();
1578 Parser.Lex(); // Eat ')'
1579 return false;
1580 }
1581
1582 EndLoc = Parser.getTok().getEndLoc();
1583
1584 if (!RegNo) {
1585 OnFailure();
1586 if (isParsingIntelSyntax()) return true;
1587 return Error(L: StartLoc, Msg: "invalid register name",
1588 Range: SMRange(StartLoc, EndLoc));
1589 }
1590
1591 Parser.Lex(); // Eat identifier token.
1592 return false;
1593}
1594
1595bool X86AsmParser::parseRegister(MCRegister &Reg, SMLoc &StartLoc,
1596 SMLoc &EndLoc) {
1597 return ParseRegister(RegNo&: Reg, StartLoc, EndLoc, /*RestoreOnFailure=*/false);
1598}
1599
1600ParseStatus X86AsmParser::tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
1601 SMLoc &EndLoc) {
1602 bool Result = ParseRegister(RegNo&: Reg, StartLoc, EndLoc, /*RestoreOnFailure=*/true);
1603 bool PendingErrors = getParser().hasPendingError();
1604 getParser().clearPendingErrors();
1605 if (PendingErrors)
1606 return ParseStatus::Failure;
1607 if (Result)
1608 return ParseStatus::NoMatch;
1609 return ParseStatus::Success;
1610}
1611
1612std::unique_ptr<X86Operand> X86AsmParser::DefaultMemSIOperand(SMLoc Loc) {
1613 bool Parse32 = is32BitMode() || Code16GCC;
1614 MCRegister Basereg =
1615 is64BitMode() ? X86::RSI : (Parse32 ? X86::ESI : X86::SI);
1616 const MCExpr *Disp = MCConstantExpr::create(Value: 0, Ctx&: getContext());
1617 return X86Operand::CreateMem(ModeSize: getPointerWidth(), /*SegReg=*/0, Disp,
1618 /*BaseReg=*/Basereg, /*IndexReg=*/0, /*Scale=*/1,
1619 StartLoc: Loc, EndLoc: Loc, Size: 0);
1620}
1621
1622std::unique_ptr<X86Operand> X86AsmParser::DefaultMemDIOperand(SMLoc Loc) {
1623 bool Parse32 = is32BitMode() || Code16GCC;
1624 MCRegister Basereg =
1625 is64BitMode() ? X86::RDI : (Parse32 ? X86::EDI : X86::DI);
1626 const MCExpr *Disp = MCConstantExpr::create(Value: 0, Ctx&: getContext());
1627 return X86Operand::CreateMem(ModeSize: getPointerWidth(), /*SegReg=*/0, Disp,
1628 /*BaseReg=*/Basereg, /*IndexReg=*/0, /*Scale=*/1,
1629 StartLoc: Loc, EndLoc: Loc, Size: 0);
1630}
1631
1632bool X86AsmParser::IsSIReg(MCRegister Reg) {
1633 switch (Reg.id()) {
1634 default: llvm_unreachable("Only (R|E)SI and (R|E)DI are expected!");
1635 case X86::RSI:
1636 case X86::ESI:
1637 case X86::SI:
1638 return true;
1639 case X86::RDI:
1640 case X86::EDI:
1641 case X86::DI:
1642 return false;
1643 }
1644}
1645
1646MCRegister X86AsmParser::GetSIDIForRegClass(unsigned RegClassID, bool IsSIReg) {
1647 switch (RegClassID) {
1648 default: llvm_unreachable("Unexpected register class");
1649 case X86::GR64RegClassID:
1650 return IsSIReg ? X86::RSI : X86::RDI;
1651 case X86::GR32RegClassID:
1652 return IsSIReg ? X86::ESI : X86::EDI;
1653 case X86::GR16RegClassID:
1654 return IsSIReg ? X86::SI : X86::DI;
1655 }
1656}
1657
1658void X86AsmParser::AddDefaultSrcDestOperands(
1659 OperandVector& Operands, std::unique_ptr<llvm::MCParsedAsmOperand> &&Src,
1660 std::unique_ptr<llvm::MCParsedAsmOperand> &&Dst) {
1661 if (isParsingIntelSyntax()) {
1662 Operands.push_back(Elt: std::move(Dst));
1663 Operands.push_back(Elt: std::move(Src));
1664 }
1665 else {
1666 Operands.push_back(Elt: std::move(Src));
1667 Operands.push_back(Elt: std::move(Dst));
1668 }
1669}
1670
1671bool X86AsmParser::VerifyAndAdjustOperands(OperandVector &OrigOperands,
1672 OperandVector &FinalOperands) {
1673
1674 if (OrigOperands.size() > 1) {
1675 // Check if sizes match, OrigOperands also contains the instruction name
1676 assert(OrigOperands.size() == FinalOperands.size() + 1 &&
1677 "Operand size mismatch");
1678
1679 SmallVector<std::pair<SMLoc, std::string>, 2> Warnings;
1680 // Verify types match
1681 int RegClassID = -1;
1682 for (unsigned int i = 0; i < FinalOperands.size(); ++i) {
1683 X86Operand &OrigOp = static_cast<X86Operand &>(*OrigOperands[i + 1]);
1684 X86Operand &FinalOp = static_cast<X86Operand &>(*FinalOperands[i]);
1685
1686 if (FinalOp.isReg() &&
1687 (!OrigOp.isReg() || FinalOp.getReg() != OrigOp.getReg()))
1688 // Return false and let a normal complaint about bogus operands happen
1689 return false;
1690
1691 if (FinalOp.isMem()) {
1692
1693 if (!OrigOp.isMem())
1694 // Return false and let a normal complaint about bogus operands happen
1695 return false;
1696
1697 MCRegister OrigReg = OrigOp.Mem.BaseReg;
1698 MCRegister FinalReg = FinalOp.Mem.BaseReg;
1699
1700 // If we've already encounterd a register class, make sure all register
1701 // bases are of the same register class
1702 if (RegClassID != -1 &&
1703 !X86MCRegisterClasses[RegClassID].contains(Reg: OrigReg)) {
1704 return Error(L: OrigOp.getStartLoc(),
1705 Msg: "mismatching source and destination index registers");
1706 }
1707
1708 if (X86MCRegisterClasses[X86::GR64RegClassID].contains(Reg: OrigReg))
1709 RegClassID = X86::GR64RegClassID;
1710 else if (X86MCRegisterClasses[X86::GR32RegClassID].contains(Reg: OrigReg))
1711 RegClassID = X86::GR32RegClassID;
1712 else if (X86MCRegisterClasses[X86::GR16RegClassID].contains(Reg: OrigReg))
1713 RegClassID = X86::GR16RegClassID;
1714 else
1715 // Unexpected register class type
1716 // Return false and let a normal complaint about bogus operands happen
1717 return false;
1718
1719 bool IsSI = IsSIReg(Reg: FinalReg);
1720 FinalReg = GetSIDIForRegClass(RegClassID, IsSIReg: IsSI);
1721
1722 if (FinalReg != OrigReg) {
1723 std::string RegName = IsSI ? "ES:(R|E)SI" : "ES:(R|E)DI";
1724 Warnings.push_back(Elt: std::make_pair(
1725 x: OrigOp.getStartLoc(),
1726 y: "memory operand is only for determining the size, " + RegName +
1727 " will be used for the location"));
1728 }
1729
1730 FinalOp.Mem.Size = OrigOp.Mem.Size;
1731 FinalOp.Mem.SegReg = OrigOp.Mem.SegReg;
1732 FinalOp.Mem.BaseReg = FinalReg;
1733 }
1734 }
1735
1736 // Produce warnings only if all the operands passed the adjustment - prevent
1737 // legal cases like "movsd (%rax), %xmm0" mistakenly produce warnings
1738 for (auto &WarningMsg : Warnings) {
1739 Warning(L: WarningMsg.first, Msg: WarningMsg.second);
1740 }
1741
1742 // Remove old operands
1743 for (unsigned int i = 0; i < FinalOperands.size(); ++i)
1744 OrigOperands.pop_back();
1745 }
1746 // OrigOperands.append(FinalOperands.begin(), FinalOperands.end());
1747 for (auto &Op : FinalOperands)
1748 OrigOperands.push_back(Elt: std::move(Op));
1749
1750 return false;
1751}
1752
1753bool X86AsmParser::parseOperand(OperandVector &Operands, StringRef Name) {
1754 if (isParsingIntelSyntax())
1755 return parseIntelOperand(Operands, Name);
1756
1757 return parseATTOperand(Operands);
1758}
1759
1760bool X86AsmParser::CreateMemForMSInlineAsm(
1761 MCRegister SegReg, const MCExpr *Disp, MCRegister BaseReg,
1762 MCRegister IndexReg, unsigned Scale, bool NonAbsMem, SMLoc Start, SMLoc End,
1763 unsigned Size, StringRef Identifier, const InlineAsmIdentifierInfo &Info,
1764 OperandVector &Operands) {
1765 // If we found a decl other than a VarDecl, then assume it is a FuncDecl or
1766 // some other label reference.
1767 if (Info.isKind(kind: InlineAsmIdentifierInfo::IK_Label)) {
1768 // Create an absolute memory reference in order to match against
1769 // instructions taking a PC relative operand.
1770 Operands.push_back(Elt: X86Operand::CreateMem(ModeSize: getPointerWidth(), Disp, StartLoc: Start,
1771 EndLoc: End, Size, SymName: Identifier,
1772 OpDecl: Info.Label.Decl));
1773 return false;
1774 }
1775 // We either have a direct symbol reference, or an offset from a symbol. The
1776 // parser always puts the symbol on the LHS, so look there for size
1777 // calculation purposes.
1778 unsigned FrontendSize = 0;
1779 void *Decl = nullptr;
1780 bool IsGlobalLV = false;
1781 if (Info.isKind(kind: InlineAsmIdentifierInfo::IK_Var)) {
1782 // Size is in terms of bits in this context.
1783 FrontendSize = Info.Var.Type * 8;
1784 Decl = Info.Var.Decl;
1785 IsGlobalLV = Info.Var.IsGlobalLV;
1786 }
1787 // It is widely common for MS InlineAsm to use a global variable and one/two
1788 // registers in a mmory expression, and though unaccessible via rip/eip.
1789 if (IsGlobalLV) {
1790 if (BaseReg || IndexReg) {
1791 Operands.push_back(Elt: X86Operand::CreateMem(ModeSize: getPointerWidth(), Disp, StartLoc: Start,
1792 EndLoc: End, Size, SymName: Identifier, OpDecl: Decl, FrontendSize: 0,
1793 UseUpRegs: BaseReg && IndexReg));
1794 return false;
1795 }
1796 if (NonAbsMem)
1797 BaseReg = 1; // Make isAbsMem() false
1798 }
1799 Operands.push_back(Elt: X86Operand::CreateMem(
1800 ModeSize: getPointerWidth(), SegReg, Disp, BaseReg, IndexReg, Scale, StartLoc: Start, EndLoc: End,
1801 Size,
1802 /*DefaultBaseReg=*/X86::RIP, SymName: Identifier, OpDecl: Decl, FrontendSize));
1803 return false;
1804}
1805
1806// Some binary bitwise operators have a named synonymous
1807// Query a candidate string for being such a named operator
1808// and if so - invoke the appropriate handler
1809bool X86AsmParser::ParseIntelNamedOperator(StringRef Name,
1810 IntelExprStateMachine &SM,
1811 bool &ParseError, SMLoc &End) {
1812 // A named operator should be either lower or upper case, but not a mix...
1813 // except in MASM, which uses full case-insensitivity.
1814 if (Name != Name.lower() && Name != Name.upper() &&
1815 !getParser().isParsingMasm())
1816 return false;
1817 if (Name.equals_insensitive(RHS: "not")) {
1818 SM.onNot();
1819 } else if (Name.equals_insensitive(RHS: "or")) {
1820 SM.onOr();
1821 } else if (Name.equals_insensitive(RHS: "shl")) {
1822 SM.onLShift();
1823 } else if (Name.equals_insensitive(RHS: "shr")) {
1824 SM.onRShift();
1825 } else if (Name.equals_insensitive(RHS: "xor")) {
1826 SM.onXor();
1827 } else if (Name.equals_insensitive(RHS: "and")) {
1828 SM.onAnd();
1829 } else if (Name.equals_insensitive(RHS: "mod")) {
1830 SM.onMod();
1831 } else if (Name.equals_insensitive(RHS: "offset")) {
1832 SMLoc OffsetLoc = getTok().getLoc();
1833 const MCExpr *Val = nullptr;
1834 StringRef ID;
1835 InlineAsmIdentifierInfo Info;
1836 ParseError = ParseIntelOffsetOperator(Val, ID, Info, End);
1837 if (ParseError)
1838 return true;
1839 StringRef ErrMsg;
1840 ParseError =
1841 SM.onOffset(Val, OffsetLoc, ID, IDInfo: Info, ParsingMSInlineAsm: isParsingMSInlineAsm(), ErrMsg);
1842 if (ParseError)
1843 return Error(L: SMLoc::getFromPointer(Ptr: Name.data()), Msg: ErrMsg);
1844 } else {
1845 return false;
1846 }
1847 if (!Name.equals_insensitive(RHS: "offset"))
1848 End = consumeToken();
1849 return true;
1850}
1851bool X86AsmParser::ParseMasmNamedOperator(StringRef Name,
1852 IntelExprStateMachine &SM,
1853 bool &ParseError, SMLoc &End) {
1854 if (Name.equals_insensitive(RHS: "eq")) {
1855 SM.onEq();
1856 } else if (Name.equals_insensitive(RHS: "ne")) {
1857 SM.onNE();
1858 } else if (Name.equals_insensitive(RHS: "lt")) {
1859 SM.onLT();
1860 } else if (Name.equals_insensitive(RHS: "le")) {
1861 SM.onLE();
1862 } else if (Name.equals_insensitive(RHS: "gt")) {
1863 SM.onGT();
1864 } else if (Name.equals_insensitive(RHS: "ge")) {
1865 SM.onGE();
1866 } else {
1867 return false;
1868 }
1869 End = consumeToken();
1870 return true;
1871}
1872
1873// Check if current intel expression append after an operand.
1874// Like: [Operand][Intel Expression]
1875void X86AsmParser::tryParseOperandIdx(AsmToken::TokenKind PrevTK,
1876 IntelExprStateMachine &SM) {
1877 if (PrevTK != AsmToken::RBrac)
1878 return;
1879
1880 SM.setAppendAfterOperand();
1881}
1882
1883bool X86AsmParser::ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End) {
1884 MCAsmParser &Parser = getParser();
1885 StringRef ErrMsg;
1886
1887 AsmToken::TokenKind PrevTK = AsmToken::Error;
1888
1889 if (getContext().getObjectFileInfo()->isPositionIndependent())
1890 SM.setPIC();
1891
1892 bool Done = false;
1893 while (!Done) {
1894 // Get a fresh reference on each loop iteration in case the previous
1895 // iteration moved the token storage during UnLex().
1896 const AsmToken &Tok = Parser.getTok();
1897
1898 bool UpdateLocLex = true;
1899 AsmToken::TokenKind TK = getLexer().getKind();
1900
1901 switch (TK) {
1902 default:
1903 if ((Done = SM.isValidEndState()))
1904 break;
1905 return Error(L: Tok.getLoc(), Msg: "unknown token in expression");
1906 case AsmToken::Error:
1907 return Error(L: getLexer().getErrLoc(), Msg: getLexer().getErr());
1908 break;
1909 case AsmToken::Real:
1910 // DotOperator: [ebx].0
1911 UpdateLocLex = false;
1912 if (ParseIntelDotOperator(SM, End))
1913 return true;
1914 break;
1915 case AsmToken::Dot:
1916 if (!Parser.isParsingMasm()) {
1917 if ((Done = SM.isValidEndState()))
1918 break;
1919 return Error(L: Tok.getLoc(), Msg: "unknown token in expression");
1920 }
1921 // MASM allows spaces around the dot operator (e.g., "var . x")
1922 Lex();
1923 UpdateLocLex = false;
1924 if (ParseIntelDotOperator(SM, End))
1925 return true;
1926 break;
1927 case AsmToken::Dollar:
1928 if (!Parser.isParsingMasm()) {
1929 if ((Done = SM.isValidEndState()))
1930 break;
1931 return Error(L: Tok.getLoc(), Msg: "unknown token in expression");
1932 }
1933 [[fallthrough]];
1934 case AsmToken::String: {
1935 if (Parser.isParsingMasm()) {
1936 // MASM parsers handle strings in expressions as constants.
1937 SMLoc ValueLoc = Tok.getLoc();
1938 int64_t Res;
1939 const MCExpr *Val;
1940 if (Parser.parsePrimaryExpr(Res&: Val, EndLoc&: End, TypeInfo: nullptr))
1941 return true;
1942 UpdateLocLex = false;
1943 if (!Val->evaluateAsAbsolute(Res, Asm: getStreamer().getAssemblerPtr()))
1944 return Error(L: ValueLoc, Msg: "expected absolute value");
1945 if (SM.onInteger(TmpInt: Res, ErrMsg))
1946 return Error(L: ValueLoc, Msg: ErrMsg);
1947 break;
1948 }
1949 [[fallthrough]];
1950 }
1951 case AsmToken::At:
1952 case AsmToken::Identifier: {
1953 SMLoc IdentLoc = Tok.getLoc();
1954 StringRef Identifier = Tok.getString();
1955 UpdateLocLex = false;
1956 if (Parser.isParsingMasm()) {
1957 size_t DotOffset = Identifier.find_first_of(C: '.');
1958 if (DotOffset != StringRef::npos) {
1959 consumeToken();
1960 StringRef LHS = Identifier.slice(Start: 0, End: DotOffset);
1961 StringRef Dot = Identifier.substr(Start: DotOffset, N: 1);
1962 StringRef RHS = Identifier.substr(Start: DotOffset + 1);
1963 if (!RHS.empty()) {
1964 getLexer().UnLex(Token: AsmToken(AsmToken::Identifier, RHS));
1965 }
1966 getLexer().UnLex(Token: AsmToken(AsmToken::Dot, Dot));
1967 if (!LHS.empty()) {
1968 getLexer().UnLex(Token: AsmToken(AsmToken::Identifier, LHS));
1969 }
1970 break;
1971 }
1972 }
1973 // (MASM only) <TYPE> PTR operator
1974 if (Parser.isParsingMasm()) {
1975 const AsmToken &NextTok = getLexer().peekTok();
1976 if (NextTok.is(K: AsmToken::Identifier) &&
1977 NextTok.getIdentifier().equals_insensitive(RHS: "ptr")) {
1978 AsmTypeInfo Info;
1979 if (Parser.lookUpType(Name: Identifier, Info))
1980 return Error(L: Tok.getLoc(), Msg: "unknown type");
1981 SM.onCast(Info);
1982 // Eat type and PTR.
1983 consumeToken();
1984 End = consumeToken();
1985 break;
1986 }
1987 }
1988 // Register, or (MASM only) <register>.<field>
1989 MCRegister Reg;
1990 if (Tok.is(K: AsmToken::Identifier)) {
1991 if (!ParseRegister(RegNo&: Reg, StartLoc&: IdentLoc, EndLoc&: End, /*RestoreOnFailure=*/true)) {
1992 if (SM.onRegister(Reg, ErrMsg))
1993 return Error(L: IdentLoc, Msg: ErrMsg);
1994 break;
1995 }
1996 if (Parser.isParsingMasm()) {
1997 const std::pair<StringRef, StringRef> IDField =
1998 Tok.getString().split(Separator: '.');
1999 const StringRef ID = IDField.first, Field = IDField.second;
2000 SMLoc IDEndLoc = SMLoc::getFromPointer(Ptr: ID.data() + ID.size());
2001 if (!Field.empty() &&
2002 !MatchRegisterByName(RegNo&: Reg, RegName: ID, StartLoc: IdentLoc, EndLoc: IDEndLoc)) {
2003 if (SM.onRegister(Reg, ErrMsg))
2004 return Error(L: IdentLoc, Msg: ErrMsg);
2005
2006 AsmFieldInfo Info;
2007 SMLoc FieldStartLoc = SMLoc::getFromPointer(Ptr: Field.data());
2008 if (Parser.lookUpField(Name: Field, Info))
2009 return Error(L: FieldStartLoc, Msg: "unknown offset");
2010 else if (SM.onPlus(ErrMsg))
2011 return Error(L: getTok().getLoc(), Msg: ErrMsg);
2012 else if (SM.onInteger(TmpInt: Info.Offset, ErrMsg))
2013 return Error(L: IdentLoc, Msg: ErrMsg);
2014 SM.setTypeInfo(Info.Type);
2015
2016 End = consumeToken();
2017 break;
2018 }
2019 }
2020 }
2021 // Operator synonymous ("not", "or" etc.)
2022 bool ParseError = false;
2023 if (ParseIntelNamedOperator(Name: Identifier, SM, ParseError, End)) {
2024 if (ParseError)
2025 return true;
2026 break;
2027 }
2028 if (Parser.isParsingMasm() &&
2029 ParseMasmNamedOperator(Name: Identifier, SM, ParseError, End)) {
2030 if (ParseError)
2031 return true;
2032 break;
2033 }
2034 // Symbol reference, when parsing assembly content
2035 InlineAsmIdentifierInfo Info;
2036 AsmFieldInfo FieldInfo;
2037 const MCExpr *Val;
2038 if (isParsingMSInlineAsm() || Parser.isParsingMasm()) {
2039 // MS Dot Operator expression
2040 if (Identifier.contains(C: '.') &&
2041 (PrevTK == AsmToken::RBrac || PrevTK == AsmToken::RParen)) {
2042 if (ParseIntelDotOperator(SM, End))
2043 return true;
2044 break;
2045 }
2046 }
2047 if (isParsingMSInlineAsm()) {
2048 // MS InlineAsm operators (TYPE/LENGTH/SIZE)
2049 if (unsigned OpKind = IdentifyIntelInlineAsmOperator(Name: Identifier)) {
2050 if (int64_t Val = ParseIntelInlineAsmOperator(OpKind)) {
2051 if (SM.onInteger(TmpInt: Val, ErrMsg))
2052 return Error(L: IdentLoc, Msg: ErrMsg);
2053 } else {
2054 return true;
2055 }
2056 break;
2057 }
2058 // MS InlineAsm identifier
2059 // Call parseIdentifier() to combine @ with the identifier behind it.
2060 if (TK == AsmToken::At && Parser.parseIdentifier(Res&: Identifier))
2061 return Error(L: IdentLoc, Msg: "expected identifier");
2062 if (ParseIntelInlineAsmIdentifier(Val, Identifier, Info, IsUnevaluatedOperand: false, End))
2063 return true;
2064 else if (SM.onIdentifierExpr(SymRef: Val, SymRefName: Identifier, IDInfo: Info, Type: FieldInfo.Type,
2065 ParsingMSInlineAsm: true, ErrMsg))
2066 return Error(L: IdentLoc, Msg: ErrMsg);
2067 break;
2068 }
2069 if (Parser.isParsingMasm()) {
2070 if (unsigned OpKind = IdentifyMasmOperator(Name: Identifier)) {
2071 int64_t Val;
2072 if (ParseMasmOperator(OpKind, Val))
2073 return true;
2074 if (SM.onInteger(TmpInt: Val, ErrMsg))
2075 return Error(L: IdentLoc, Msg: ErrMsg);
2076 break;
2077 }
2078 if (!getParser().lookUpType(Name: Identifier, Info&: FieldInfo.Type)) {
2079 // Field offset immediate; <TYPE>.<field specification>
2080 Lex(); // eat type
2081 bool EndDot = parseOptionalToken(T: AsmToken::Dot);
2082 while (EndDot || (getTok().is(K: AsmToken::Identifier) &&
2083 getTok().getString().starts_with(Prefix: "."))) {
2084 getParser().parseIdentifier(Res&: Identifier);
2085 if (!EndDot)
2086 Identifier.consume_front(Prefix: ".");
2087 EndDot = Identifier.consume_back(Suffix: ".");
2088 if (getParser().lookUpField(Base: FieldInfo.Type.Name, Member: Identifier,
2089 Info&: FieldInfo)) {
2090 SMLoc IDEnd =
2091 SMLoc::getFromPointer(Ptr: Identifier.data() + Identifier.size());
2092 return Error(L: IdentLoc, Msg: "Unable to lookup field reference!",
2093 Range: SMRange(IdentLoc, IDEnd));
2094 }
2095 if (!EndDot)
2096 EndDot = parseOptionalToken(T: AsmToken::Dot);
2097 }
2098 if (SM.onInteger(TmpInt: FieldInfo.Offset, ErrMsg))
2099 return Error(L: IdentLoc, Msg: ErrMsg);
2100 break;
2101 }
2102 }
2103 if (getParser().parsePrimaryExpr(Res&: Val, EndLoc&: End, TypeInfo: &FieldInfo.Type)) {
2104 return Error(L: Tok.getLoc(), Msg: "Unexpected identifier!");
2105 } else if (SM.onIdentifierExpr(SymRef: Val, SymRefName: Identifier, IDInfo: Info, Type: FieldInfo.Type,
2106 ParsingMSInlineAsm: false, ErrMsg)) {
2107 return Error(L: IdentLoc, Msg: ErrMsg);
2108 }
2109 break;
2110 }
2111 case AsmToken::Integer: {
2112 // Look for 'b' or 'f' following an Integer as a directional label
2113 SMLoc Loc = getTok().getLoc();
2114 int64_t IntVal = getTok().getIntVal();
2115 End = consumeToken();
2116 UpdateLocLex = false;
2117 if (getLexer().getKind() == AsmToken::Identifier) {
2118 StringRef IDVal = getTok().getString();
2119 if (IDVal == "f" || IDVal == "b") {
2120 MCSymbol *Sym =
2121 getContext().getDirectionalLocalSymbol(LocalLabelVal: IntVal, Before: IDVal == "b");
2122 auto Variant = X86::S_None;
2123 const MCExpr *Val =
2124 MCSymbolRefExpr::create(Symbol: Sym, specifier: Variant, Ctx&: getContext());
2125 if (IDVal == "b" && Sym->isUndefined())
2126 return Error(L: Loc, Msg: "invalid reference to undefined symbol");
2127 StringRef Identifier = Sym->getName();
2128 InlineAsmIdentifierInfo Info;
2129 AsmTypeInfo Type;
2130 if (SM.onIdentifierExpr(SymRef: Val, SymRefName: Identifier, IDInfo: Info, Type,
2131 ParsingMSInlineAsm: isParsingMSInlineAsm(), ErrMsg))
2132 return Error(L: Loc, Msg: ErrMsg);
2133 End = consumeToken();
2134 } else {
2135 if (SM.onInteger(TmpInt: IntVal, ErrMsg))
2136 return Error(L: Loc, Msg: ErrMsg);
2137 }
2138 } else {
2139 if (SM.onInteger(TmpInt: IntVal, ErrMsg))
2140 return Error(L: Loc, Msg: ErrMsg);
2141 }
2142 break;
2143 }
2144 case AsmToken::Plus:
2145 if (SM.onPlus(ErrMsg))
2146 return Error(L: getTok().getLoc(), Msg: ErrMsg);
2147 break;
2148 case AsmToken::Minus:
2149 if (SM.onMinus(ErrMsg))
2150 return Error(L: getTok().getLoc(), Msg: ErrMsg);
2151 break;
2152 case AsmToken::Tilde: SM.onNot(); break;
2153 case AsmToken::Star: SM.onStar(); break;
2154 case AsmToken::Slash: SM.onDivide(); break;
2155 case AsmToken::Percent: SM.onMod(); break;
2156 case AsmToken::Pipe: SM.onOr(); break;
2157 case AsmToken::Caret: SM.onXor(); break;
2158 case AsmToken::Amp: SM.onAnd(); break;
2159 case AsmToken::LessLess:
2160 SM.onLShift(); break;
2161 case AsmToken::GreaterGreater:
2162 SM.onRShift(); break;
2163 case AsmToken::LBrac:
2164 if (SM.onLBrac())
2165 return Error(L: Tok.getLoc(), Msg: "unexpected bracket encountered");
2166 tryParseOperandIdx(PrevTK, SM);
2167 break;
2168 case AsmToken::RBrac:
2169 if (SM.onRBrac(ErrMsg)) {
2170 return Error(L: Tok.getLoc(), Msg: ErrMsg);
2171 }
2172 break;
2173 case AsmToken::LParen: SM.onLParen(); break;
2174 case AsmToken::RParen: SM.onRParen(); break;
2175 }
2176 if (SM.hadError())
2177 return Error(L: Tok.getLoc(), Msg: "unknown token in expression");
2178
2179 if (!Done && UpdateLocLex)
2180 End = consumeToken();
2181
2182 PrevTK = TK;
2183 }
2184 return false;
2185}
2186
2187void X86AsmParser::RewriteIntelExpression(IntelExprStateMachine &SM,
2188 SMLoc Start, SMLoc End) {
2189 SMLoc Loc = Start;
2190 unsigned ExprLen = End.getPointer() - Start.getPointer();
2191 // Skip everything before a symbol displacement (if we have one)
2192 if (SM.getSym() && !SM.isOffsetOperator()) {
2193 StringRef SymName = SM.getSymName();
2194 if (unsigned Len = SymName.data() - Start.getPointer())
2195 InstInfo->AsmRewrites->emplace_back(Args: AOK_Skip, Args&: Start, Args&: Len);
2196 Loc = SMLoc::getFromPointer(Ptr: SymName.data() + SymName.size());
2197 ExprLen = End.getPointer() - (SymName.data() + SymName.size());
2198 // If we have only a symbol than there's no need for complex rewrite,
2199 // simply skip everything after it
2200 if (!(SM.getBaseReg() || SM.getIndexReg() || SM.getImm())) {
2201 if (ExprLen)
2202 InstInfo->AsmRewrites->emplace_back(Args: AOK_Skip, Args&: Loc, Args&: ExprLen);
2203 return;
2204 }
2205 }
2206 // Build an Intel Expression rewrite
2207 StringRef BaseRegStr;
2208 StringRef IndexRegStr;
2209 StringRef OffsetNameStr;
2210 if (SM.getBaseReg())
2211 BaseRegStr = X86IntelInstPrinter::getRegisterName(Reg: SM.getBaseReg());
2212 if (SM.getIndexReg())
2213 IndexRegStr = X86IntelInstPrinter::getRegisterName(Reg: SM.getIndexReg());
2214 if (SM.isOffsetOperator())
2215 OffsetNameStr = SM.getSymName();
2216 // Emit it
2217 IntelExpr Expr(BaseRegStr, IndexRegStr, SM.getScale(), OffsetNameStr,
2218 SM.getImm(), SM.isMemExpr());
2219 InstInfo->AsmRewrites->emplace_back(Args&: Loc, Args&: ExprLen, Args&: Expr);
2220}
2221
2222// Inline assembly may use variable names with namespace alias qualifiers.
2223bool X86AsmParser::ParseIntelInlineAsmIdentifier(
2224 const MCExpr *&Val, StringRef &Identifier, InlineAsmIdentifierInfo &Info,
2225 bool IsUnevaluatedOperand, SMLoc &End, bool IsParsingOffsetOperator) {
2226 MCAsmParser &Parser = getParser();
2227 assert(isParsingMSInlineAsm() && "Expected to be parsing inline assembly.");
2228 Val = nullptr;
2229
2230 StringRef LineBuf(Identifier.data());
2231 SemaCallback->LookupInlineAsmIdentifier(LineBuf, Info, IsUnevaluatedContext: IsUnevaluatedOperand);
2232
2233 const AsmToken &Tok = Parser.getTok();
2234 SMLoc Loc = Tok.getLoc();
2235
2236 // Advance the token stream until the end of the current token is
2237 // after the end of what the frontend claimed.
2238 const char *EndPtr = Tok.getLoc().getPointer() + LineBuf.size();
2239 do {
2240 End = Tok.getEndLoc();
2241 getLexer().Lex();
2242 } while (End.getPointer() < EndPtr);
2243 Identifier = LineBuf;
2244
2245 // The frontend should end parsing on an assembler token boundary, unless it
2246 // failed parsing.
2247 assert((End.getPointer() == EndPtr ||
2248 Info.isKind(InlineAsmIdentifierInfo::IK_Invalid)) &&
2249 "frontend claimed part of a token?");
2250
2251 // If the identifier lookup was unsuccessful, assume that we are dealing with
2252 // a label.
2253 if (Info.isKind(kind: InlineAsmIdentifierInfo::IK_Invalid)) {
2254 StringRef InternalName =
2255 SemaCallback->LookupInlineAsmLabel(Identifier, SM&: getSourceManager(),
2256 Location: Loc, Create: false);
2257 assert(InternalName.size() && "We should have an internal name here.");
2258 // Push a rewrite for replacing the identifier name with the internal name,
2259 // unless we are parsing the operand of an offset operator
2260 if (!IsParsingOffsetOperator)
2261 InstInfo->AsmRewrites->emplace_back(Args: AOK_Label, Args&: Loc, Args: Identifier.size(),
2262 Args&: InternalName);
2263 else
2264 Identifier = InternalName;
2265 } else if (Info.isKind(kind: InlineAsmIdentifierInfo::IK_EnumVal))
2266 return false;
2267 // Create the symbol reference.
2268 MCSymbol *Sym = getContext().getOrCreateSymbol(Name: Identifier);
2269 auto Variant = X86::S_None;
2270 Val = MCSymbolRefExpr::create(Symbol: Sym, specifier: Variant, Ctx&: getParser().getContext());
2271 return false;
2272}
2273
2274//ParseRoundingModeOp - Parse AVX-512 rounding mode operand
2275bool X86AsmParser::ParseRoundingModeOp(SMLoc Start, OperandVector &Operands) {
2276 MCAsmParser &Parser = getParser();
2277 const AsmToken &Tok = Parser.getTok();
2278 // Eat "{" and mark the current place.
2279 const SMLoc consumedToken = consumeToken();
2280 if (Tok.isNot(K: AsmToken::Identifier))
2281 return Error(L: Tok.getLoc(), Msg: "Expected an identifier after {");
2282 if (Tok.getIdentifier().starts_with(Prefix: "r")) {
2283 int rndMode = StringSwitch<int>(Tok.getIdentifier())
2284 .Case(S: "rn", Value: X86::STATIC_ROUNDING::TO_NEAREST_INT)
2285 .Case(S: "rd", Value: X86::STATIC_ROUNDING::TO_NEG_INF)
2286 .Case(S: "ru", Value: X86::STATIC_ROUNDING::TO_POS_INF)
2287 .Case(S: "rz", Value: X86::STATIC_ROUNDING::TO_ZERO)
2288 .Default(Value: -1);
2289 if (-1 == rndMode)
2290 return Error(L: Tok.getLoc(), Msg: "Invalid rounding mode.");
2291 Parser.Lex(); // Eat "r*" of r*-sae
2292 if (!getLexer().is(K: AsmToken::Minus))
2293 return Error(L: Tok.getLoc(), Msg: "Expected - at this point");
2294 Parser.Lex(); // Eat "-"
2295 Parser.Lex(); // Eat the sae
2296 if (!getLexer().is(K: AsmToken::RCurly))
2297 return Error(L: Tok.getLoc(), Msg: "Expected } at this point");
2298 SMLoc End = Tok.getEndLoc();
2299 Parser.Lex(); // Eat "}"
2300 const MCExpr *RndModeOp =
2301 MCConstantExpr::create(Value: rndMode, Ctx&: Parser.getContext());
2302 Operands.push_back(Elt: X86Operand::CreateImm(Val: RndModeOp, StartLoc: Start, EndLoc: End));
2303 return false;
2304 }
2305 if (Tok.getIdentifier() == "sae") {
2306 Parser.Lex(); // Eat the sae
2307 if (!getLexer().is(K: AsmToken::RCurly))
2308 return Error(L: Tok.getLoc(), Msg: "Expected } at this point");
2309 Parser.Lex(); // Eat "}"
2310 Operands.push_back(Elt: X86Operand::CreateToken(Str: "{sae}", Loc: consumedToken));
2311 return false;
2312 }
2313 return Error(L: Tok.getLoc(), Msg: "unknown token in expression");
2314}
2315
2316/// Parse condtional flags for CCMP/CTEST, e.g {dfv=of,sf,zf,cf} right after
2317/// mnemonic.
2318bool X86AsmParser::parseCFlagsOp(OperandVector &Operands) {
2319 MCAsmParser &Parser = getParser();
2320 AsmToken Tok = Parser.getTok();
2321 const SMLoc Start = Tok.getLoc();
2322 if (!Tok.is(K: AsmToken::LCurly))
2323 return Error(L: Tok.getLoc(), Msg: "Expected { at this point");
2324 Parser.Lex(); // Eat "{"
2325 Tok = Parser.getTok();
2326 if (Tok.getIdentifier().lower() != "dfv")
2327 return Error(L: Tok.getLoc(), Msg: "Expected dfv at this point");
2328 Parser.Lex(); // Eat "dfv"
2329 Tok = Parser.getTok();
2330 if (!Tok.is(K: AsmToken::Equal))
2331 return Error(L: Tok.getLoc(), Msg: "Expected = at this point");
2332 Parser.Lex(); // Eat "="
2333
2334 Tok = Parser.getTok();
2335 SMLoc End;
2336 if (Tok.is(K: AsmToken::RCurly)) {
2337 End = Tok.getEndLoc();
2338 Operands.push_back(Elt: X86Operand::CreateImm(
2339 Val: MCConstantExpr::create(Value: 0, Ctx&: Parser.getContext()), StartLoc: Start, EndLoc: End));
2340 Parser.Lex(); // Eat "}"
2341 return false;
2342 }
2343 unsigned CFlags = 0;
2344 for (unsigned I = 0; I < 4; ++I) {
2345 Tok = Parser.getTok();
2346 unsigned CFlag = StringSwitch<unsigned>(Tok.getIdentifier().lower())
2347 .Case(S: "of", Value: 0x8)
2348 .Case(S: "sf", Value: 0x4)
2349 .Case(S: "zf", Value: 0x2)
2350 .Case(S: "cf", Value: 0x1)
2351 .Default(Value: ~0U);
2352 if (CFlag == ~0U)
2353 return Error(L: Tok.getLoc(), Msg: "Invalid conditional flags");
2354
2355 if (CFlags & CFlag)
2356 return Error(L: Tok.getLoc(), Msg: "Duplicated conditional flag");
2357 CFlags |= CFlag;
2358
2359 Parser.Lex(); // Eat one conditional flag
2360 Tok = Parser.getTok();
2361 if (Tok.is(K: AsmToken::RCurly)) {
2362 End = Tok.getEndLoc();
2363 Operands.push_back(Elt: X86Operand::CreateImm(
2364 Val: MCConstantExpr::create(Value: CFlags, Ctx&: Parser.getContext()), StartLoc: Start, EndLoc: End));
2365 Parser.Lex(); // Eat "}"
2366 return false;
2367 } else if (I == 3) {
2368 return Error(L: Tok.getLoc(), Msg: "Expected } at this point");
2369 } else if (Tok.isNot(K: AsmToken::Comma)) {
2370 return Error(L: Tok.getLoc(), Msg: "Expected } or , at this point");
2371 }
2372 Parser.Lex(); // Eat ","
2373 }
2374 llvm_unreachable("Unexpected control flow");
2375}
2376
2377/// Parse the '.' operator.
2378bool X86AsmParser::ParseIntelDotOperator(IntelExprStateMachine &SM,
2379 SMLoc &End) {
2380 const AsmToken &Tok = getTok();
2381 AsmFieldInfo Info;
2382
2383 // Drop the optional '.'.
2384 StringRef DotDispStr = Tok.getString();
2385 DotDispStr.consume_front(Prefix: ".");
2386 bool TrailingDot = false;
2387
2388 // .Imm gets lexed as a real.
2389 if (Tok.is(K: AsmToken::Real)) {
2390 APInt DotDisp;
2391 if (DotDispStr.getAsInteger(Radix: 10, Result&: DotDisp))
2392 return Error(L: Tok.getLoc(), Msg: "Unexpected offset");
2393 Info.Offset = DotDisp.getZExtValue();
2394 } else if ((isParsingMSInlineAsm() || getParser().isParsingMasm()) &&
2395 Tok.is(K: AsmToken::Identifier)) {
2396 TrailingDot = DotDispStr.consume_back(Suffix: ".");
2397 const std::pair<StringRef, StringRef> BaseMember = DotDispStr.split(Separator: '.');
2398 const StringRef Base = BaseMember.first, Member = BaseMember.second;
2399 if (getParser().lookUpField(Base: SM.getType(), Member: DotDispStr, Info) &&
2400 getParser().lookUpField(Base: SM.getSymName(), Member: DotDispStr, Info) &&
2401 getParser().lookUpField(Name: DotDispStr, Info) &&
2402 (!SemaCallback ||
2403 SemaCallback->LookupInlineAsmField(Base, Member, Offset&: Info.Offset)))
2404 return Error(L: Tok.getLoc(), Msg: "Unable to lookup field reference!");
2405 } else {
2406 return Error(L: Tok.getLoc(), Msg: "Unexpected token type!");
2407 }
2408
2409 // Eat the DotExpression and update End
2410 End = SMLoc::getFromPointer(Ptr: DotDispStr.data());
2411 const char *DotExprEndLoc = DotDispStr.data() + DotDispStr.size();
2412 while (Tok.getLoc().getPointer() < DotExprEndLoc)
2413 Lex();
2414 if (TrailingDot)
2415 getLexer().UnLex(Token: AsmToken(AsmToken::Dot, "."));
2416 SM.addImm(imm: Info.Offset);
2417 SM.setTypeInfo(Info.Type);
2418 return false;
2419}
2420
2421/// Parse the 'offset' operator.
2422/// This operator is used to specify the location of a given operand
2423bool X86AsmParser::ParseIntelOffsetOperator(const MCExpr *&Val, StringRef &ID,
2424 InlineAsmIdentifierInfo &Info,
2425 SMLoc &End) {
2426 // Eat offset, mark start of identifier.
2427 SMLoc Start = Lex().getLoc();
2428 ID = getTok().getString();
2429 if (!isParsingMSInlineAsm()) {
2430 if ((getTok().isNot(K: AsmToken::Identifier) &&
2431 getTok().isNot(K: AsmToken::String)) ||
2432 getParser().parsePrimaryExpr(Res&: Val, EndLoc&: End, TypeInfo: nullptr))
2433 return Error(L: Start, Msg: "unexpected token!");
2434 } else if (ParseIntelInlineAsmIdentifier(Val, Identifier&: ID, Info, IsUnevaluatedOperand: false, End, IsParsingOffsetOperator: true)) {
2435 return Error(L: Start, Msg: "unable to lookup expression");
2436 } else if (Info.isKind(kind: InlineAsmIdentifierInfo::IK_EnumVal)) {
2437 return Error(L: Start, Msg: "offset operator cannot yet handle constants");
2438 }
2439 return false;
2440}
2441
2442// Query a candidate string for being an Intel assembly operator
2443// Report back its kind, or IOK_INVALID if does not evaluated as a known one
2444unsigned X86AsmParser::IdentifyIntelInlineAsmOperator(StringRef Name) {
2445 return StringSwitch<unsigned>(Name)
2446 .Cases(S0: "TYPE",S1: "type",Value: IOK_TYPE)
2447 .Cases(S0: "SIZE",S1: "size",Value: IOK_SIZE)
2448 .Cases(S0: "LENGTH",S1: "length",Value: IOK_LENGTH)
2449 .Default(Value: IOK_INVALID);
2450}
2451
2452/// Parse the 'LENGTH', 'TYPE' and 'SIZE' operators. The LENGTH operator
2453/// returns the number of elements in an array. It returns the value 1 for
2454/// non-array variables. The SIZE operator returns the size of a C or C++
2455/// variable. A variable's size is the product of its LENGTH and TYPE. The
2456/// TYPE operator returns the size of a C or C++ type or variable. If the
2457/// variable is an array, TYPE returns the size of a single element.
2458unsigned X86AsmParser::ParseIntelInlineAsmOperator(unsigned OpKind) {
2459 MCAsmParser &Parser = getParser();
2460 const AsmToken &Tok = Parser.getTok();
2461 Parser.Lex(); // Eat operator.
2462
2463 const MCExpr *Val = nullptr;
2464 InlineAsmIdentifierInfo Info;
2465 SMLoc Start = Tok.getLoc(), End;
2466 StringRef Identifier = Tok.getString();
2467 if (ParseIntelInlineAsmIdentifier(Val, Identifier, Info,
2468 /*IsUnevaluatedOperand=*/true, End))
2469 return 0;
2470
2471 if (!Info.isKind(kind: InlineAsmIdentifierInfo::IK_Var)) {
2472 Error(L: Start, Msg: "unable to lookup expression");
2473 return 0;
2474 }
2475
2476 unsigned CVal = 0;
2477 switch(OpKind) {
2478 default: llvm_unreachable("Unexpected operand kind!");
2479 case IOK_LENGTH: CVal = Info.Var.Length; break;
2480 case IOK_SIZE: CVal = Info.Var.Size; break;
2481 case IOK_TYPE: CVal = Info.Var.Type; break;
2482 }
2483
2484 return CVal;
2485}
2486
2487// Query a candidate string for being an Intel assembly operator
2488// Report back its kind, or IOK_INVALID if does not evaluated as a known one
2489unsigned X86AsmParser::IdentifyMasmOperator(StringRef Name) {
2490 return StringSwitch<unsigned>(Name.lower())
2491 .Case(S: "type", Value: MOK_TYPE)
2492 .Cases(S0: "size", S1: "sizeof", Value: MOK_SIZEOF)
2493 .Cases(S0: "length", S1: "lengthof", Value: MOK_LENGTHOF)
2494 .Default(Value: MOK_INVALID);
2495}
2496
2497/// Parse the 'LENGTHOF', 'SIZEOF', and 'TYPE' operators. The LENGTHOF operator
2498/// returns the number of elements in an array. It returns the value 1 for
2499/// non-array variables. The SIZEOF operator returns the size of a type or
2500/// variable in bytes. A variable's size is the product of its LENGTH and TYPE.
2501/// The TYPE operator returns the size of a variable. If the variable is an
2502/// array, TYPE returns the size of a single element.
2503bool X86AsmParser::ParseMasmOperator(unsigned OpKind, int64_t &Val) {
2504 MCAsmParser &Parser = getParser();
2505 SMLoc OpLoc = Parser.getTok().getLoc();
2506 Parser.Lex(); // Eat operator.
2507
2508 Val = 0;
2509 if (OpKind == MOK_SIZEOF || OpKind == MOK_TYPE) {
2510 // Check for SIZEOF(<type>) and TYPE(<type>).
2511 bool InParens = Parser.getTok().is(K: AsmToken::LParen);
2512 const AsmToken &IDTok = InParens ? getLexer().peekTok() : Parser.getTok();
2513 AsmTypeInfo Type;
2514 if (IDTok.is(K: AsmToken::Identifier) &&
2515 !Parser.lookUpType(Name: IDTok.getIdentifier(), Info&: Type)) {
2516 Val = Type.Size;
2517
2518 // Eat tokens.
2519 if (InParens)
2520 parseToken(T: AsmToken::LParen);
2521 parseToken(T: AsmToken::Identifier);
2522 if (InParens)
2523 parseToken(T: AsmToken::RParen);
2524 }
2525 }
2526
2527 if (!Val) {
2528 IntelExprStateMachine SM;
2529 SMLoc End, Start = Parser.getTok().getLoc();
2530 if (ParseIntelExpression(SM, End))
2531 return true;
2532
2533 switch (OpKind) {
2534 default:
2535 llvm_unreachable("Unexpected operand kind!");
2536 case MOK_SIZEOF:
2537 Val = SM.getSize();
2538 break;
2539 case MOK_LENGTHOF:
2540 Val = SM.getLength();
2541 break;
2542 case MOK_TYPE:
2543 Val = SM.getElementSize();
2544 break;
2545 }
2546
2547 if (!Val)
2548 return Error(L: OpLoc, Msg: "expression has unknown type", Range: SMRange(Start, End));
2549 }
2550
2551 return false;
2552}
2553
2554bool X86AsmParser::ParseIntelMemoryOperandSize(unsigned &Size) {
2555 Size = StringSwitch<unsigned>(getTok().getString())
2556 .Cases(S0: "BYTE", S1: "byte", Value: 8)
2557 .Cases(S0: "WORD", S1: "word", Value: 16)
2558 .Cases(S0: "DWORD", S1: "dword", Value: 32)
2559 .Cases(S0: "FLOAT", S1: "float", Value: 32)
2560 .Cases(S0: "LONG", S1: "long", Value: 32)
2561 .Cases(S0: "FWORD", S1: "fword", Value: 48)
2562 .Cases(S0: "DOUBLE", S1: "double", Value: 64)
2563 .Cases(S0: "QWORD", S1: "qword", Value: 64)
2564 .Cases(S0: "MMWORD",S1: "mmword", Value: 64)
2565 .Cases(S0: "XWORD", S1: "xword", Value: 80)
2566 .Cases(S0: "TBYTE", S1: "tbyte", Value: 80)
2567 .Cases(S0: "XMMWORD", S1: "xmmword", Value: 128)
2568 .Cases(S0: "YMMWORD", S1: "ymmword", Value: 256)
2569 .Cases(S0: "ZMMWORD", S1: "zmmword", Value: 512)
2570 .Default(Value: 0);
2571 if (Size) {
2572 const AsmToken &Tok = Lex(); // Eat operand size (e.g., byte, word).
2573 if (!(Tok.getString() == "PTR" || Tok.getString() == "ptr"))
2574 return Error(L: Tok.getLoc(), Msg: "Expected 'PTR' or 'ptr' token!");
2575 Lex(); // Eat ptr.
2576 }
2577 return false;
2578}
2579
2580bool X86AsmParser::parseIntelOperand(OperandVector &Operands, StringRef Name) {
2581 MCAsmParser &Parser = getParser();
2582 const AsmToken &Tok = Parser.getTok();
2583 SMLoc Start, End;
2584
2585 // Parse optional Size directive.
2586 unsigned Size;
2587 if (ParseIntelMemoryOperandSize(Size))
2588 return true;
2589 bool PtrInOperand = bool(Size);
2590
2591 Start = Tok.getLoc();
2592
2593 // Rounding mode operand.
2594 if (getLexer().is(K: AsmToken::LCurly))
2595 return ParseRoundingModeOp(Start, Operands);
2596
2597 // Register operand.
2598 MCRegister RegNo;
2599 if (Tok.is(K: AsmToken::Identifier) && !parseRegister(Reg&: RegNo, StartLoc&: Start, EndLoc&: End)) {
2600 if (RegNo == X86::RIP)
2601 return Error(L: Start, Msg: "rip can only be used as a base register");
2602 // A Register followed by ':' is considered a segment override
2603 if (Tok.isNot(K: AsmToken::Colon)) {
2604 if (PtrInOperand)
2605 return Error(L: Start, Msg: "expected memory operand after 'ptr', "
2606 "found register operand instead");
2607 Operands.push_back(Elt: X86Operand::CreateReg(Reg: RegNo, StartLoc: Start, EndLoc: End));
2608 return false;
2609 }
2610 // An alleged segment override. check if we have a valid segment register
2611 if (!X86MCRegisterClasses[X86::SEGMENT_REGRegClassID].contains(Reg: RegNo))
2612 return Error(L: Start, Msg: "invalid segment register");
2613 // Eat ':' and update Start location
2614 Start = Lex().getLoc();
2615 }
2616
2617 // Immediates and Memory
2618 IntelExprStateMachine SM;
2619 if (ParseIntelExpression(SM, End))
2620 return true;
2621
2622 if (isParsingMSInlineAsm())
2623 RewriteIntelExpression(SM, Start, End: Tok.getLoc());
2624
2625 int64_t Imm = SM.getImm();
2626 const MCExpr *Disp = SM.getSym();
2627 const MCExpr *ImmDisp = MCConstantExpr::create(Value: Imm, Ctx&: getContext());
2628 if (Disp && Imm)
2629 Disp = MCBinaryExpr::createAdd(LHS: Disp, RHS: ImmDisp, Ctx&: getContext());
2630 if (!Disp)
2631 Disp = ImmDisp;
2632
2633 // RegNo != 0 specifies a valid segment register,
2634 // and we are parsing a segment override
2635 if (!SM.isMemExpr() && !RegNo) {
2636 if (isParsingMSInlineAsm() && SM.isOffsetOperator()) {
2637 const InlineAsmIdentifierInfo &Info = SM.getIdentifierInfo();
2638 if (Info.isKind(kind: InlineAsmIdentifierInfo::IK_Var)) {
2639 // Disp includes the address of a variable; make sure this is recorded
2640 // for later handling.
2641 Operands.push_back(Elt: X86Operand::CreateImm(Val: Disp, StartLoc: Start, EndLoc: End,
2642 SymName: SM.getSymName(), OpDecl: Info.Var.Decl,
2643 GlobalRef: Info.Var.IsGlobalLV));
2644 return false;
2645 }
2646 }
2647
2648 Operands.push_back(Elt: X86Operand::CreateImm(Val: Disp, StartLoc: Start, EndLoc: End));
2649 return false;
2650 }
2651
2652 StringRef ErrMsg;
2653 MCRegister BaseReg = SM.getBaseReg();
2654 MCRegister IndexReg = SM.getIndexReg();
2655 if (IndexReg && BaseReg == X86::RIP)
2656 BaseReg = MCRegister();
2657 unsigned Scale = SM.getScale();
2658 if (!PtrInOperand)
2659 Size = SM.getElementSize() << 3;
2660
2661 if (Scale == 0 && BaseReg != X86::ESP && BaseReg != X86::RSP &&
2662 (IndexReg == X86::ESP || IndexReg == X86::RSP))
2663 std::swap(a&: BaseReg, b&: IndexReg);
2664
2665 // If BaseReg is a vector register and IndexReg is not, swap them unless
2666 // Scale was specified in which case it would be an error.
2667 if (Scale == 0 &&
2668 !(X86MCRegisterClasses[X86::VR128XRegClassID].contains(Reg: IndexReg) ||
2669 X86MCRegisterClasses[X86::VR256XRegClassID].contains(Reg: IndexReg) ||
2670 X86MCRegisterClasses[X86::VR512RegClassID].contains(Reg: IndexReg)) &&
2671 (X86MCRegisterClasses[X86::VR128XRegClassID].contains(Reg: BaseReg) ||
2672 X86MCRegisterClasses[X86::VR256XRegClassID].contains(Reg: BaseReg) ||
2673 X86MCRegisterClasses[X86::VR512RegClassID].contains(Reg: BaseReg)))
2674 std::swap(a&: BaseReg, b&: IndexReg);
2675
2676 if (Scale != 0 &&
2677 X86MCRegisterClasses[X86::GR16RegClassID].contains(Reg: IndexReg))
2678 return Error(L: Start, Msg: "16-bit addresses cannot have a scale");
2679
2680 // If there was no explicit scale specified, change it to 1.
2681 if (Scale == 0)
2682 Scale = 1;
2683
2684 // If this is a 16-bit addressing mode with the base and index in the wrong
2685 // order, swap them so CheckBaseRegAndIndexRegAndScale doesn't fail. It is
2686 // shared with att syntax where order matters.
2687 if ((BaseReg == X86::SI || BaseReg == X86::DI) &&
2688 (IndexReg == X86::BX || IndexReg == X86::BP))
2689 std::swap(a&: BaseReg, b&: IndexReg);
2690
2691 if ((BaseReg || IndexReg) &&
2692 CheckBaseRegAndIndexRegAndScale(BaseReg, IndexReg, Scale, Is64BitMode: is64BitMode(),
2693 ErrMsg))
2694 return Error(L: Start, Msg: ErrMsg);
2695 bool IsUnconditionalBranch =
2696 Name.equals_insensitive(RHS: "jmp") || Name.equals_insensitive(RHS: "call");
2697 if (isParsingMSInlineAsm())
2698 return CreateMemForMSInlineAsm(SegReg: RegNo, Disp, BaseReg, IndexReg, Scale,
2699 NonAbsMem: IsUnconditionalBranch && is64BitMode(),
2700 Start, End, Size, Identifier: SM.getSymName(),
2701 Info: SM.getIdentifierInfo(), Operands);
2702
2703 // When parsing x64 MS-style assembly, all non-absolute references to a named
2704 // variable default to RIP-relative.
2705 MCRegister DefaultBaseReg;
2706 bool MaybeDirectBranchDest = true;
2707
2708 if (Parser.isParsingMasm()) {
2709 if (is64BitMode() &&
2710 ((PtrInOperand && !IndexReg) || SM.getElementSize() > 0)) {
2711 DefaultBaseReg = X86::RIP;
2712 }
2713 if (IsUnconditionalBranch) {
2714 if (PtrInOperand) {
2715 MaybeDirectBranchDest = false;
2716 if (is64BitMode())
2717 DefaultBaseReg = X86::RIP;
2718 } else if (!BaseReg && !IndexReg && Disp &&
2719 Disp->getKind() == MCExpr::SymbolRef) {
2720 if (is64BitMode()) {
2721 if (SM.getSize() == 8) {
2722 MaybeDirectBranchDest = false;
2723 DefaultBaseReg = X86::RIP;
2724 }
2725 } else {
2726 if (SM.getSize() == 4 || SM.getSize() == 2)
2727 MaybeDirectBranchDest = false;
2728 }
2729 }
2730 }
2731 } else if (IsUnconditionalBranch) {
2732 // Treat `call [offset fn_ref]` (or `jmp`) syntax as an error.
2733 if (!PtrInOperand && SM.isOffsetOperator())
2734 return Error(
2735 L: Start, Msg: "`OFFSET` operator cannot be used in an unconditional branch");
2736 if (PtrInOperand || SM.isBracketUsed())
2737 MaybeDirectBranchDest = false;
2738 }
2739
2740 if ((BaseReg || IndexReg || RegNo || DefaultBaseReg))
2741 Operands.push_back(Elt: X86Operand::CreateMem(
2742 ModeSize: getPointerWidth(), SegReg: RegNo, Disp, BaseReg, IndexReg, Scale, StartLoc: Start, EndLoc: End,
2743 Size, DefaultBaseReg, /*SymName=*/StringRef(), /*OpDecl=*/nullptr,
2744 /*FrontendSize=*/0, /*UseUpRegs=*/false, MaybeDirectBranchDest));
2745 else
2746 Operands.push_back(Elt: X86Operand::CreateMem(
2747 ModeSize: getPointerWidth(), Disp, StartLoc: Start, EndLoc: End, Size, /*SymName=*/StringRef(),
2748 /*OpDecl=*/nullptr, /*FrontendSize=*/0, /*UseUpRegs=*/false,
2749 MaybeDirectBranchDest));
2750 return false;
2751}
2752
2753bool X86AsmParser::parseATTOperand(OperandVector &Operands) {
2754 MCAsmParser &Parser = getParser();
2755 switch (getLexer().getKind()) {
2756 case AsmToken::Dollar: {
2757 // $42 or $ID -> immediate.
2758 SMLoc Start = Parser.getTok().getLoc(), End;
2759 Parser.Lex();
2760 const MCExpr *Val;
2761 // This is an immediate, so we should not parse a register. Do a precheck
2762 // for '%' to supercede intra-register parse errors.
2763 SMLoc L = Parser.getTok().getLoc();
2764 if (check(P: getLexer().is(K: AsmToken::Percent), Loc: L,
2765 Msg: "expected immediate expression") ||
2766 getParser().parseExpression(Res&: Val, EndLoc&: End) ||
2767 check(P: isa<X86MCExpr>(Val), Loc: L, Msg: "expected immediate expression"))
2768 return true;
2769 Operands.push_back(Elt: X86Operand::CreateImm(Val, StartLoc: Start, EndLoc: End));
2770 return false;
2771 }
2772 case AsmToken::LCurly: {
2773 SMLoc Start = Parser.getTok().getLoc();
2774 return ParseRoundingModeOp(Start, Operands);
2775 }
2776 default: {
2777 // This a memory operand or a register. We have some parsing complications
2778 // as a '(' may be part of an immediate expression or the addressing mode
2779 // block. This is complicated by the fact that an assembler-level variable
2780 // may refer either to a register or an immediate expression.
2781
2782 SMLoc Loc = Parser.getTok().getLoc(), EndLoc;
2783 const MCExpr *Expr = nullptr;
2784 MCRegister Reg;
2785 if (getLexer().isNot(K: AsmToken::LParen)) {
2786 // No '(' so this is either a displacement expression or a register.
2787 if (Parser.parseExpression(Res&: Expr, EndLoc))
2788 return true;
2789 if (auto *RE = dyn_cast<X86MCExpr>(Val: Expr)) {
2790 // Segment Register. Reset Expr and copy value to register.
2791 Expr = nullptr;
2792 Reg = RE->getReg();
2793
2794 // Check the register.
2795 if (Reg == X86::EIZ || Reg == X86::RIZ)
2796 return Error(
2797 L: Loc, Msg: "%eiz and %riz can only be used as index registers",
2798 Range: SMRange(Loc, EndLoc));
2799 if (Reg == X86::RIP)
2800 return Error(L: Loc, Msg: "%rip can only be used as a base register",
2801 Range: SMRange(Loc, EndLoc));
2802 // Return register that are not segment prefixes immediately.
2803 if (!Parser.parseOptionalToken(T: AsmToken::Colon)) {
2804 Operands.push_back(Elt: X86Operand::CreateReg(Reg, StartLoc: Loc, EndLoc));
2805 return false;
2806 }
2807 if (!X86MCRegisterClasses[X86::SEGMENT_REGRegClassID].contains(Reg))
2808 return Error(L: Loc, Msg: "invalid segment register");
2809 // Accept a '*' absolute memory reference after the segment. Place it
2810 // before the full memory operand.
2811 if (getLexer().is(K: AsmToken::Star))
2812 Operands.push_back(Elt: X86Operand::CreateToken(Str: "*", Loc: consumeToken()));
2813 }
2814 }
2815 // This is a Memory operand.
2816 return ParseMemOperand(SegReg: Reg, Disp: Expr, StartLoc: Loc, EndLoc, Operands);
2817 }
2818 }
2819}
2820
2821// X86::COND_INVALID if not a recognized condition code or alternate mnemonic,
2822// otherwise the EFLAGS Condition Code enumerator.
2823X86::CondCode X86AsmParser::ParseConditionCode(StringRef CC) {
2824 return StringSwitch<X86::CondCode>(CC)
2825 .Case(S: "o", Value: X86::COND_O) // Overflow
2826 .Case(S: "no", Value: X86::COND_NO) // No Overflow
2827 .Cases(S0: "b", S1: "nae", Value: X86::COND_B) // Below/Neither Above nor Equal
2828 .Cases(S0: "ae", S1: "nb", Value: X86::COND_AE) // Above or Equal/Not Below
2829 .Cases(S0: "e", S1: "z", Value: X86::COND_E) // Equal/Zero
2830 .Cases(S0: "ne", S1: "nz", Value: X86::COND_NE) // Not Equal/Not Zero
2831 .Cases(S0: "be", S1: "na", Value: X86::COND_BE) // Below or Equal/Not Above
2832 .Cases(S0: "a", S1: "nbe", Value: X86::COND_A) // Above/Neither Below nor Equal
2833 .Case(S: "s", Value: X86::COND_S) // Sign
2834 .Case(S: "ns", Value: X86::COND_NS) // No Sign
2835 .Cases(S0: "p", S1: "pe", Value: X86::COND_P) // Parity/Parity Even
2836 .Cases(S0: "np", S1: "po", Value: X86::COND_NP) // No Parity/Parity Odd
2837 .Cases(S0: "l", S1: "nge", Value: X86::COND_L) // Less/Neither Greater nor Equal
2838 .Cases(S0: "ge", S1: "nl", Value: X86::COND_GE) // Greater or Equal/Not Less
2839 .Cases(S0: "le", S1: "ng", Value: X86::COND_LE) // Less or Equal/Not Greater
2840 .Cases(S0: "g", S1: "nle", Value: X86::COND_G) // Greater/Neither Less nor Equal
2841 .Default(Value: X86::COND_INVALID);
2842}
2843
2844// true on failure, false otherwise
2845// If no {z} mark was found - Parser doesn't advance
2846bool X86AsmParser::ParseZ(std::unique_ptr<X86Operand> &Z,
2847 const SMLoc &StartLoc) {
2848 MCAsmParser &Parser = getParser();
2849 // Assuming we are just pass the '{' mark, quering the next token
2850 // Searched for {z}, but none was found. Return false, as no parsing error was
2851 // encountered
2852 if (!(getLexer().is(K: AsmToken::Identifier) &&
2853 (getLexer().getTok().getIdentifier() == "z")))
2854 return false;
2855 Parser.Lex(); // Eat z
2856 // Query and eat the '}' mark
2857 if (!getLexer().is(K: AsmToken::RCurly))
2858 return Error(L: getLexer().getLoc(), Msg: "Expected } at this point");
2859 Parser.Lex(); // Eat '}'
2860 // Assign Z with the {z} mark operand
2861 Z = X86Operand::CreateToken(Str: "{z}", Loc: StartLoc);
2862 return false;
2863}
2864
2865// true on failure, false otherwise
2866bool X86AsmParser::HandleAVX512Operand(OperandVector &Operands) {
2867 MCAsmParser &Parser = getParser();
2868 if (getLexer().is(K: AsmToken::LCurly)) {
2869 // Eat "{" and mark the current place.
2870 const SMLoc consumedToken = consumeToken();
2871 // Distinguish {1to<NUM>} from {%k<NUM>}.
2872 if(getLexer().is(K: AsmToken::Integer)) {
2873 // Parse memory broadcasting ({1to<NUM>}).
2874 if (getLexer().getTok().getIntVal() != 1)
2875 return TokError(Msg: "Expected 1to<NUM> at this point");
2876 StringRef Prefix = getLexer().getTok().getString();
2877 Parser.Lex(); // Eat first token of 1to8
2878 if (!getLexer().is(K: AsmToken::Identifier))
2879 return TokError(Msg: "Expected 1to<NUM> at this point");
2880 // Recognize only reasonable suffixes.
2881 SmallVector<char, 5> BroadcastVector;
2882 StringRef BroadcastString = (Prefix + getLexer().getTok().getIdentifier())
2883 .toStringRef(Out&: BroadcastVector);
2884 if (!BroadcastString.starts_with(Prefix: "1to"))
2885 return TokError(Msg: "Expected 1to<NUM> at this point");
2886 const char *BroadcastPrimitive =
2887 StringSwitch<const char *>(BroadcastString)
2888 .Case(S: "1to2", Value: "{1to2}")
2889 .Case(S: "1to4", Value: "{1to4}")
2890 .Case(S: "1to8", Value: "{1to8}")
2891 .Case(S: "1to16", Value: "{1to16}")
2892 .Case(S: "1to32", Value: "{1to32}")
2893 .Default(Value: nullptr);
2894 if (!BroadcastPrimitive)
2895 return TokError(Msg: "Invalid memory broadcast primitive.");
2896 Parser.Lex(); // Eat trailing token of 1toN
2897 if (!getLexer().is(K: AsmToken::RCurly))
2898 return TokError(Msg: "Expected } at this point");
2899 Parser.Lex(); // Eat "}"
2900 Operands.push_back(Elt: X86Operand::CreateToken(Str: BroadcastPrimitive,
2901 Loc: consumedToken));
2902 // No AVX512 specific primitives can pass
2903 // after memory broadcasting, so return.
2904 return false;
2905 } else {
2906 // Parse either {k}{z}, {z}{k}, {k} or {z}
2907 // last one have no meaning, but GCC accepts it
2908 // Currently, we're just pass a '{' mark
2909 std::unique_ptr<X86Operand> Z;
2910 if (ParseZ(Z, StartLoc: consumedToken))
2911 return true;
2912 // Reaching here means that parsing of the allegadly '{z}' mark yielded
2913 // no errors.
2914 // Query for the need of further parsing for a {%k<NUM>} mark
2915 if (!Z || getLexer().is(K: AsmToken::LCurly)) {
2916 SMLoc StartLoc = Z ? consumeToken() : consumedToken;
2917 // Parse an op-mask register mark ({%k<NUM>}), which is now to be
2918 // expected
2919 MCRegister RegNo;
2920 SMLoc RegLoc;
2921 if (!parseRegister(Reg&: RegNo, StartLoc&: RegLoc, EndLoc&: StartLoc) &&
2922 X86MCRegisterClasses[X86::VK1RegClassID].contains(Reg: RegNo)) {
2923 if (RegNo == X86::K0)
2924 return Error(L: RegLoc, Msg: "Register k0 can't be used as write mask");
2925 if (!getLexer().is(K: AsmToken::RCurly))
2926 return Error(L: getLexer().getLoc(), Msg: "Expected } at this point");
2927 Operands.push_back(Elt: X86Operand::CreateToken(Str: "{", Loc: StartLoc));
2928 Operands.push_back(
2929 Elt: X86Operand::CreateReg(Reg: RegNo, StartLoc, EndLoc: StartLoc));
2930 Operands.push_back(Elt: X86Operand::CreateToken(Str: "}", Loc: consumeToken()));
2931 } else
2932 return Error(L: getLexer().getLoc(),
2933 Msg: "Expected an op-mask register at this point");
2934 // {%k<NUM>} mark is found, inquire for {z}
2935 if (getLexer().is(K: AsmToken::LCurly) && !Z) {
2936 // Have we've found a parsing error, or found no (expected) {z} mark
2937 // - report an error
2938 if (ParseZ(Z, StartLoc: consumeToken()) || !Z)
2939 return Error(L: getLexer().getLoc(),
2940 Msg: "Expected a {z} mark at this point");
2941
2942 }
2943 // '{z}' on its own is meaningless, hence should be ignored.
2944 // on the contrary - have it been accompanied by a K register,
2945 // allow it.
2946 if (Z)
2947 Operands.push_back(Elt: std::move(Z));
2948 }
2949 }
2950 }
2951 return false;
2952}
2953
2954/// ParseMemOperand: 'seg : disp(basereg, indexreg, scale)'. The '%ds:' prefix
2955/// has already been parsed if present. disp may be provided as well.
2956bool X86AsmParser::ParseMemOperand(MCRegister SegReg, const MCExpr *Disp,
2957 SMLoc StartLoc, SMLoc EndLoc,
2958 OperandVector &Operands) {
2959 MCAsmParser &Parser = getParser();
2960 SMLoc Loc;
2961 // Based on the initial passed values, we may be in any of these cases, we are
2962 // in one of these cases (with current position (*)):
2963
2964 // 1. seg : * disp (base-index-scale-expr)
2965 // 2. seg : *(disp) (base-index-scale-expr)
2966 // 3. seg : *(base-index-scale-expr)
2967 // 4. disp *(base-index-scale-expr)
2968 // 5. *(disp) (base-index-scale-expr)
2969 // 6. *(base-index-scale-expr)
2970 // 7. disp *
2971 // 8. *(disp)
2972
2973 // If we do not have an displacement yet, check if we're in cases 4 or 6 by
2974 // checking if the first object after the parenthesis is a register (or an
2975 // identifier referring to a register) and parse the displacement or default
2976 // to 0 as appropriate.
2977 auto isAtMemOperand = [this]() {
2978 if (this->getLexer().isNot(K: AsmToken::LParen))
2979 return false;
2980 AsmToken Buf[2];
2981 StringRef Id;
2982 auto TokCount = this->getLexer().peekTokens(Buf, ShouldSkipSpace: true);
2983 if (TokCount == 0)
2984 return false;
2985 switch (Buf[0].getKind()) {
2986 case AsmToken::Percent:
2987 case AsmToken::Comma:
2988 return true;
2989 // These lower cases are doing a peekIdentifier.
2990 case AsmToken::At:
2991 case AsmToken::Dollar:
2992 if ((TokCount > 1) &&
2993 (Buf[1].is(K: AsmToken::Identifier) || Buf[1].is(K: AsmToken::String)) &&
2994 (Buf[0].getLoc().getPointer() + 1 == Buf[1].getLoc().getPointer()))
2995 Id = StringRef(Buf[0].getLoc().getPointer(),
2996 Buf[1].getIdentifier().size() + 1);
2997 break;
2998 case AsmToken::Identifier:
2999 case AsmToken::String:
3000 Id = Buf[0].getIdentifier();
3001 break;
3002 default:
3003 return false;
3004 }
3005 // We have an ID. Check if it is bound to a register.
3006 if (!Id.empty()) {
3007 MCSymbol *Sym = this->getContext().getOrCreateSymbol(Name: Id);
3008 if (Sym->isVariable()) {
3009 auto V = Sym->getVariableValue();
3010 return isa<X86MCExpr>(Val: V);
3011 }
3012 }
3013 return false;
3014 };
3015
3016 if (!Disp) {
3017 // Parse immediate if we're not at a mem operand yet.
3018 if (!isAtMemOperand()) {
3019 if (Parser.parseTokenLoc(Loc) || Parser.parseExpression(Res&: Disp, EndLoc))
3020 return true;
3021 assert(!isa<X86MCExpr>(Disp) && "Expected non-register here.");
3022 } else {
3023 // Disp is implicitly zero if we haven't parsed it yet.
3024 Disp = MCConstantExpr::create(Value: 0, Ctx&: Parser.getContext());
3025 }
3026 }
3027
3028 // We are now either at the end of the operand or at the '(' at the start of a
3029 // base-index-scale-expr.
3030
3031 if (!parseOptionalToken(T: AsmToken::LParen)) {
3032 if (!SegReg)
3033 Operands.push_back(
3034 Elt: X86Operand::CreateMem(ModeSize: getPointerWidth(), Disp, StartLoc, EndLoc));
3035 else
3036 Operands.push_back(Elt: X86Operand::CreateMem(ModeSize: getPointerWidth(), SegReg, Disp,
3037 BaseReg: 0, IndexReg: 0, Scale: 1, StartLoc, EndLoc));
3038 return false;
3039 }
3040
3041 // If we reached here, then eat the '(' and Process
3042 // the rest of the memory operand.
3043 MCRegister BaseReg, IndexReg;
3044 unsigned Scale = 1;
3045 SMLoc BaseLoc = getLexer().getLoc();
3046 const MCExpr *E;
3047 StringRef ErrMsg;
3048
3049 // Parse BaseReg if one is provided.
3050 if (getLexer().isNot(K: AsmToken::Comma) && getLexer().isNot(K: AsmToken::RParen)) {
3051 if (Parser.parseExpression(Res&: E, EndLoc) ||
3052 check(P: !isa<X86MCExpr>(Val: E), Loc: BaseLoc, Msg: "expected register here"))
3053 return true;
3054
3055 // Check the register.
3056 BaseReg = cast<X86MCExpr>(Val: E)->getReg();
3057 if (BaseReg == X86::EIZ || BaseReg == X86::RIZ)
3058 return Error(L: BaseLoc, Msg: "eiz and riz can only be used as index registers",
3059 Range: SMRange(BaseLoc, EndLoc));
3060 }
3061
3062 if (parseOptionalToken(T: AsmToken::Comma)) {
3063 // Following the comma we should have either an index register, or a scale
3064 // value. We don't support the later form, but we want to parse it
3065 // correctly.
3066 //
3067 // Even though it would be completely consistent to support syntax like
3068 // "1(%eax,,1)", the assembler doesn't. Use "eiz" or "riz" for this.
3069 if (getLexer().isNot(K: AsmToken::RParen)) {
3070 if (Parser.parseTokenLoc(Loc) || Parser.parseExpression(Res&: E, EndLoc))
3071 return true;
3072
3073 if (!isa<X86MCExpr>(Val: E)) {
3074 // We've parsed an unexpected Scale Value instead of an index
3075 // register. Interpret it as an absolute.
3076 int64_t ScaleVal;
3077 if (!E->evaluateAsAbsolute(Res&: ScaleVal, Asm: getStreamer().getAssemblerPtr()))
3078 return Error(L: Loc, Msg: "expected absolute expression");
3079 if (ScaleVal != 1)
3080 Warning(L: Loc, Msg: "scale factor without index register is ignored");
3081 Scale = 1;
3082 } else { // IndexReg Found.
3083 IndexReg = cast<X86MCExpr>(Val: E)->getReg();
3084
3085 if (BaseReg == X86::RIP)
3086 return Error(L: Loc,
3087 Msg: "%rip as base register can not have an index register");
3088 if (IndexReg == X86::RIP)
3089 return Error(L: Loc, Msg: "%rip is not allowed as an index register");
3090
3091 if (parseOptionalToken(T: AsmToken::Comma)) {
3092 // Parse the scale amount:
3093 // ::= ',' [scale-expression]
3094
3095 // A scale amount without an index is ignored.
3096 if (getLexer().isNot(K: AsmToken::RParen)) {
3097 int64_t ScaleVal;
3098 if (Parser.parseTokenLoc(Loc) ||
3099 Parser.parseAbsoluteExpression(Res&: ScaleVal))
3100 return Error(L: Loc, Msg: "expected scale expression");
3101 Scale = (unsigned)ScaleVal;
3102 // Validate the scale amount.
3103 if (X86MCRegisterClasses[X86::GR16RegClassID].contains(Reg: BaseReg) &&
3104 Scale != 1)
3105 return Error(L: Loc, Msg: "scale factor in 16-bit address must be 1");
3106 if (checkScale(Scale, ErrMsg))
3107 return Error(L: Loc, Msg: ErrMsg);
3108 }
3109 }
3110 }
3111 }
3112 }
3113
3114 // Ok, we've eaten the memory operand, verify we have a ')' and eat it too.
3115 if (parseToken(T: AsmToken::RParen, Msg: "unexpected token in memory operand"))
3116 return true;
3117
3118 // This is to support otherwise illegal operand (%dx) found in various
3119 // unofficial manuals examples (e.g. "out[s]?[bwl]? %al, (%dx)") and must now
3120 // be supported. Mark such DX variants separately fix only in special cases.
3121 if (BaseReg == X86::DX && !IndexReg && Scale == 1 && !SegReg &&
3122 isa<MCConstantExpr>(Val: Disp) &&
3123 cast<MCConstantExpr>(Val: Disp)->getValue() == 0) {
3124 Operands.push_back(Elt: X86Operand::CreateDXReg(StartLoc: BaseLoc, EndLoc: BaseLoc));
3125 return false;
3126 }
3127
3128 if (CheckBaseRegAndIndexRegAndScale(BaseReg, IndexReg, Scale, Is64BitMode: is64BitMode(),
3129 ErrMsg))
3130 return Error(L: BaseLoc, Msg: ErrMsg);
3131
3132 // If the displacement is a constant, check overflows. For 64-bit addressing,
3133 // gas requires isInt<32> and otherwise reports an error. For others, gas
3134 // reports a warning and allows a wider range. E.g. gas allows
3135 // [-0xffffffff,0xffffffff] for 32-bit addressing (e.g. Linux kernel uses
3136 // `leal -__PAGE_OFFSET(%ecx),%esp` where __PAGE_OFFSET is 0xc0000000).
3137 if (BaseReg || IndexReg) {
3138 if (auto CE = dyn_cast<MCConstantExpr>(Val: Disp)) {
3139 auto Imm = CE->getValue();
3140 bool Is64 = X86MCRegisterClasses[X86::GR64RegClassID].contains(Reg: BaseReg) ||
3141 X86MCRegisterClasses[X86::GR64RegClassID].contains(Reg: IndexReg);
3142 bool Is16 = X86MCRegisterClasses[X86::GR16RegClassID].contains(Reg: BaseReg);
3143 if (Is64) {
3144 if (!isInt<32>(x: Imm))
3145 return Error(L: BaseLoc, Msg: "displacement " + Twine(Imm) +
3146 " is not within [-2147483648, 2147483647]");
3147 } else if (!Is16) {
3148 if (!isUInt<32>(x: Imm < 0 ? -uint64_t(Imm) : uint64_t(Imm))) {
3149 Warning(L: BaseLoc, Msg: "displacement " + Twine(Imm) +
3150 " shortened to 32-bit signed " +
3151 Twine(static_cast<int32_t>(Imm)));
3152 }
3153 } else if (!isUInt<16>(x: Imm < 0 ? -uint64_t(Imm) : uint64_t(Imm))) {
3154 Warning(L: BaseLoc, Msg: "displacement " + Twine(Imm) +
3155 " shortened to 16-bit signed " +
3156 Twine(static_cast<int16_t>(Imm)));
3157 }
3158 }
3159 }
3160
3161 if (SegReg || BaseReg || IndexReg)
3162 Operands.push_back(Elt: X86Operand::CreateMem(ModeSize: getPointerWidth(), SegReg, Disp,
3163 BaseReg, IndexReg, Scale, StartLoc,
3164 EndLoc));
3165 else
3166 Operands.push_back(
3167 Elt: X86Operand::CreateMem(ModeSize: getPointerWidth(), Disp, StartLoc, EndLoc));
3168 return false;
3169}
3170
3171// Parse either a standard primary expression or a register.
3172bool X86AsmParser::parsePrimaryExpr(const MCExpr *&Res, SMLoc &EndLoc) {
3173 MCAsmParser &Parser = getParser();
3174 // See if this is a register first.
3175 if (getTok().is(K: AsmToken::Percent) ||
3176 (isParsingIntelSyntax() && getTok().is(K: AsmToken::Identifier) &&
3177 MatchRegisterName(Name: Parser.getTok().getString()))) {
3178 SMLoc StartLoc = Parser.getTok().getLoc();
3179 MCRegister RegNo;
3180 if (parseRegister(Reg&: RegNo, StartLoc, EndLoc))
3181 return true;
3182 Res = X86MCExpr::create(Reg: RegNo, Ctx&: Parser.getContext());
3183 return false;
3184 }
3185 return Parser.parsePrimaryExpr(Res, EndLoc, TypeInfo: nullptr);
3186}
3187
3188bool X86AsmParser::parseInstruction(ParseInstructionInfo &Info, StringRef Name,
3189 SMLoc NameLoc, OperandVector &Operands) {
3190 MCAsmParser &Parser = getParser();
3191 InstInfo = &Info;
3192
3193 // Reset the forced VEX encoding.
3194 ForcedOpcodePrefix = OpcodePrefix_Default;
3195 ForcedDispEncoding = DispEncoding_Default;
3196 UseApxExtendedReg = false;
3197 ForcedNoFlag = false;
3198
3199 // Parse pseudo prefixes.
3200 while (true) {
3201 if (Name == "{") {
3202 if (getLexer().isNot(K: AsmToken::Identifier))
3203 return Error(L: Parser.getTok().getLoc(), Msg: "Unexpected token after '{'");
3204 std::string Prefix = Parser.getTok().getString().lower();
3205 Parser.Lex(); // Eat identifier.
3206 if (getLexer().isNot(K: AsmToken::RCurly))
3207 return Error(L: Parser.getTok().getLoc(), Msg: "Expected '}'");
3208 Parser.Lex(); // Eat curly.
3209
3210 if (Prefix == "rex")
3211 ForcedOpcodePrefix = OpcodePrefix_REX;
3212 else if (Prefix == "rex2")
3213 ForcedOpcodePrefix = OpcodePrefix_REX2;
3214 else if (Prefix == "vex")
3215 ForcedOpcodePrefix = OpcodePrefix_VEX;
3216 else if (Prefix == "vex2")
3217 ForcedOpcodePrefix = OpcodePrefix_VEX2;
3218 else if (Prefix == "vex3")
3219 ForcedOpcodePrefix = OpcodePrefix_VEX3;
3220 else if (Prefix == "evex")
3221 ForcedOpcodePrefix = OpcodePrefix_EVEX;
3222 else if (Prefix == "disp8")
3223 ForcedDispEncoding = DispEncoding_Disp8;
3224 else if (Prefix == "disp32")
3225 ForcedDispEncoding = DispEncoding_Disp32;
3226 else if (Prefix == "nf")
3227 ForcedNoFlag = true;
3228 else
3229 return Error(L: NameLoc, Msg: "unknown prefix");
3230
3231 NameLoc = Parser.getTok().getLoc();
3232 if (getLexer().is(K: AsmToken::LCurly)) {
3233 Parser.Lex();
3234 Name = "{";
3235 } else {
3236 if (getLexer().isNot(K: AsmToken::Identifier))
3237 return Error(L: Parser.getTok().getLoc(), Msg: "Expected identifier");
3238 // FIXME: The mnemonic won't match correctly if its not in lower case.
3239 Name = Parser.getTok().getString();
3240 Parser.Lex();
3241 }
3242 continue;
3243 }
3244 // Parse MASM style pseudo prefixes.
3245 if (isParsingMSInlineAsm()) {
3246 if (Name.equals_insensitive(RHS: "vex"))
3247 ForcedOpcodePrefix = OpcodePrefix_VEX;
3248 else if (Name.equals_insensitive(RHS: "vex2"))
3249 ForcedOpcodePrefix = OpcodePrefix_VEX2;
3250 else if (Name.equals_insensitive(RHS: "vex3"))
3251 ForcedOpcodePrefix = OpcodePrefix_VEX3;
3252 else if (Name.equals_insensitive(RHS: "evex"))
3253 ForcedOpcodePrefix = OpcodePrefix_EVEX;
3254
3255 if (ForcedOpcodePrefix != OpcodePrefix_Default) {
3256 if (getLexer().isNot(K: AsmToken::Identifier))
3257 return Error(L: Parser.getTok().getLoc(), Msg: "Expected identifier");
3258 // FIXME: The mnemonic won't match correctly if its not in lower case.
3259 Name = Parser.getTok().getString();
3260 NameLoc = Parser.getTok().getLoc();
3261 Parser.Lex();
3262 }
3263 }
3264 break;
3265 }
3266
3267 // Support the suffix syntax for overriding displacement size as well.
3268 if (Name.consume_back(Suffix: ".d32")) {
3269 ForcedDispEncoding = DispEncoding_Disp32;
3270 } else if (Name.consume_back(Suffix: ".d8")) {
3271 ForcedDispEncoding = DispEncoding_Disp8;
3272 }
3273
3274 StringRef PatchedName = Name;
3275
3276 // Hack to skip "short" following Jcc.
3277 if (isParsingIntelSyntax() &&
3278 (PatchedName == "jmp" || PatchedName == "jc" || PatchedName == "jnc" ||
3279 PatchedName == "jcxz" || PatchedName == "jecxz" ||
3280 (PatchedName.starts_with(Prefix: "j") &&
3281 ParseConditionCode(CC: PatchedName.substr(Start: 1)) != X86::COND_INVALID))) {
3282 StringRef NextTok = Parser.getTok().getString();
3283 if (Parser.isParsingMasm() ? NextTok.equals_insensitive(RHS: "short")
3284 : NextTok == "short") {
3285 SMLoc NameEndLoc =
3286 NameLoc.getFromPointer(Ptr: NameLoc.getPointer() + Name.size());
3287 // Eat the short keyword.
3288 Parser.Lex();
3289 // MS and GAS ignore the short keyword; they both determine the jmp type
3290 // based on the distance of the label. (NASM does emit different code with
3291 // and without "short," though.)
3292 InstInfo->AsmRewrites->emplace_back(Args: AOK_Skip, Args&: NameEndLoc,
3293 Args: NextTok.size() + 1);
3294 }
3295 }
3296
3297 // FIXME: Hack to recognize setneb as setne.
3298 if (PatchedName.starts_with(Prefix: "set") && PatchedName.ends_with(Suffix: "b") &&
3299 PatchedName != "setzub" && PatchedName != "setzunb" &&
3300 PatchedName != "setb" && PatchedName != "setnb")
3301 PatchedName = PatchedName.substr(Start: 0, N: Name.size()-1);
3302
3303 unsigned ComparisonPredicate = ~0U;
3304
3305 // FIXME: Hack to recognize cmp<comparison code>{sh,ss,sd,ph,ps,pd}.
3306 if ((PatchedName.starts_with(Prefix: "cmp") || PatchedName.starts_with(Prefix: "vcmp")) &&
3307 (PatchedName.ends_with(Suffix: "ss") || PatchedName.ends_with(Suffix: "sd") ||
3308 PatchedName.ends_with(Suffix: "sh") || PatchedName.ends_with(Suffix: "ph") ||
3309 PatchedName.ends_with(Suffix: "bf16") || PatchedName.ends_with(Suffix: "ps") ||
3310 PatchedName.ends_with(Suffix: "pd"))) {
3311 bool IsVCMP = PatchedName[0] == 'v';
3312 unsigned CCIdx = IsVCMP ? 4 : 3;
3313 unsigned suffixLength = PatchedName.ends_with(Suffix: "bf16") ? 5 : 2;
3314 unsigned CC = StringSwitch<unsigned>(
3315 PatchedName.slice(Start: CCIdx, End: PatchedName.size() - suffixLength))
3316 .Case(S: "eq", Value: 0x00)
3317 .Case(S: "eq_oq", Value: 0x00)
3318 .Case(S: "lt", Value: 0x01)
3319 .Case(S: "lt_os", Value: 0x01)
3320 .Case(S: "le", Value: 0x02)
3321 .Case(S: "le_os", Value: 0x02)
3322 .Case(S: "unord", Value: 0x03)
3323 .Case(S: "unord_q", Value: 0x03)
3324 .Case(S: "neq", Value: 0x04)
3325 .Case(S: "neq_uq", Value: 0x04)
3326 .Case(S: "nlt", Value: 0x05)
3327 .Case(S: "nlt_us", Value: 0x05)
3328 .Case(S: "nle", Value: 0x06)
3329 .Case(S: "nle_us", Value: 0x06)
3330 .Case(S: "ord", Value: 0x07)
3331 .Case(S: "ord_q", Value: 0x07)
3332 /* AVX only from here */
3333 .Case(S: "eq_uq", Value: 0x08)
3334 .Case(S: "nge", Value: 0x09)
3335 .Case(S: "nge_us", Value: 0x09)
3336 .Case(S: "ngt", Value: 0x0A)
3337 .Case(S: "ngt_us", Value: 0x0A)
3338 .Case(S: "false", Value: 0x0B)
3339 .Case(S: "false_oq", Value: 0x0B)
3340 .Case(S: "neq_oq", Value: 0x0C)
3341 .Case(S: "ge", Value: 0x0D)
3342 .Case(S: "ge_os", Value: 0x0D)
3343 .Case(S: "gt", Value: 0x0E)
3344 .Case(S: "gt_os", Value: 0x0E)
3345 .Case(S: "true", Value: 0x0F)
3346 .Case(S: "true_uq", Value: 0x0F)
3347 .Case(S: "eq_os", Value: 0x10)
3348 .Case(S: "lt_oq", Value: 0x11)
3349 .Case(S: "le_oq", Value: 0x12)
3350 .Case(S: "unord_s", Value: 0x13)
3351 .Case(S: "neq_us", Value: 0x14)
3352 .Case(S: "nlt_uq", Value: 0x15)
3353 .Case(S: "nle_uq", Value: 0x16)
3354 .Case(S: "ord_s", Value: 0x17)
3355 .Case(S: "eq_us", Value: 0x18)
3356 .Case(S: "nge_uq", Value: 0x19)
3357 .Case(S: "ngt_uq", Value: 0x1A)
3358 .Case(S: "false_os", Value: 0x1B)
3359 .Case(S: "neq_os", Value: 0x1C)
3360 .Case(S: "ge_oq", Value: 0x1D)
3361 .Case(S: "gt_oq", Value: 0x1E)
3362 .Case(S: "true_us", Value: 0x1F)
3363 .Default(Value: ~0U);
3364 if (CC != ~0U && (IsVCMP || CC < 8) &&
3365 (IsVCMP || PatchedName.back() != 'h')) {
3366 if (PatchedName.ends_with(Suffix: "ss"))
3367 PatchedName = IsVCMP ? "vcmpss" : "cmpss";
3368 else if (PatchedName.ends_with(Suffix: "sd"))
3369 PatchedName = IsVCMP ? "vcmpsd" : "cmpsd";
3370 else if (PatchedName.ends_with(Suffix: "ps"))
3371 PatchedName = IsVCMP ? "vcmpps" : "cmpps";
3372 else if (PatchedName.ends_with(Suffix: "pd"))
3373 PatchedName = IsVCMP ? "vcmppd" : "cmppd";
3374 else if (PatchedName.ends_with(Suffix: "sh"))
3375 PatchedName = "vcmpsh";
3376 else if (PatchedName.ends_with(Suffix: "ph"))
3377 PatchedName = "vcmpph";
3378 else if (PatchedName.ends_with(Suffix: "bf16"))
3379 PatchedName = "vcmpbf16";
3380 else
3381 llvm_unreachable("Unexpected suffix!");
3382
3383 ComparisonPredicate = CC;
3384 }
3385 }
3386
3387 // FIXME: Hack to recognize vpcmp<comparison code>{ub,uw,ud,uq,b,w,d,q}.
3388 if (PatchedName.starts_with(Prefix: "vpcmp") &&
3389 (PatchedName.back() == 'b' || PatchedName.back() == 'w' ||
3390 PatchedName.back() == 'd' || PatchedName.back() == 'q')) {
3391 unsigned SuffixSize = PatchedName.drop_back().back() == 'u' ? 2 : 1;
3392 unsigned CC = StringSwitch<unsigned>(
3393 PatchedName.slice(Start: 5, End: PatchedName.size() - SuffixSize))
3394 .Case(S: "eq", Value: 0x0) // Only allowed on unsigned. Checked below.
3395 .Case(S: "lt", Value: 0x1)
3396 .Case(S: "le", Value: 0x2)
3397 //.Case("false", 0x3) // Not a documented alias.
3398 .Case(S: "neq", Value: 0x4)
3399 .Case(S: "nlt", Value: 0x5)
3400 .Case(S: "nle", Value: 0x6)
3401 //.Case("true", 0x7) // Not a documented alias.
3402 .Default(Value: ~0U);
3403 if (CC != ~0U && (CC != 0 || SuffixSize == 2)) {
3404 switch (PatchedName.back()) {
3405 default: llvm_unreachable("Unexpected character!");
3406 case 'b': PatchedName = SuffixSize == 2 ? "vpcmpub" : "vpcmpb"; break;
3407 case 'w': PatchedName = SuffixSize == 2 ? "vpcmpuw" : "vpcmpw"; break;
3408 case 'd': PatchedName = SuffixSize == 2 ? "vpcmpud" : "vpcmpd"; break;
3409 case 'q': PatchedName = SuffixSize == 2 ? "vpcmpuq" : "vpcmpq"; break;
3410 }
3411 // Set up the immediate to push into the operands later.
3412 ComparisonPredicate = CC;
3413 }
3414 }
3415
3416 // FIXME: Hack to recognize vpcom<comparison code>{ub,uw,ud,uq,b,w,d,q}.
3417 if (PatchedName.starts_with(Prefix: "vpcom") &&
3418 (PatchedName.back() == 'b' || PatchedName.back() == 'w' ||
3419 PatchedName.back() == 'd' || PatchedName.back() == 'q')) {
3420 unsigned SuffixSize = PatchedName.drop_back().back() == 'u' ? 2 : 1;
3421 unsigned CC = StringSwitch<unsigned>(
3422 PatchedName.slice(Start: 5, End: PatchedName.size() - SuffixSize))
3423 .Case(S: "lt", Value: 0x0)
3424 .Case(S: "le", Value: 0x1)
3425 .Case(S: "gt", Value: 0x2)
3426 .Case(S: "ge", Value: 0x3)
3427 .Case(S: "eq", Value: 0x4)
3428 .Case(S: "neq", Value: 0x5)
3429 .Case(S: "false", Value: 0x6)
3430 .Case(S: "true", Value: 0x7)
3431 .Default(Value: ~0U);
3432 if (CC != ~0U) {
3433 switch (PatchedName.back()) {
3434 default: llvm_unreachable("Unexpected character!");
3435 case 'b': PatchedName = SuffixSize == 2 ? "vpcomub" : "vpcomb"; break;
3436 case 'w': PatchedName = SuffixSize == 2 ? "vpcomuw" : "vpcomw"; break;
3437 case 'd': PatchedName = SuffixSize == 2 ? "vpcomud" : "vpcomd"; break;
3438 case 'q': PatchedName = SuffixSize == 2 ? "vpcomuq" : "vpcomq"; break;
3439 }
3440 // Set up the immediate to push into the operands later.
3441 ComparisonPredicate = CC;
3442 }
3443 }
3444
3445 // Determine whether this is an instruction prefix.
3446 // FIXME:
3447 // Enhance prefixes integrity robustness. for example, following forms
3448 // are currently tolerated:
3449 // repz repnz <insn> ; GAS errors for the use of two similar prefixes
3450 // lock addq %rax, %rbx ; Destination operand must be of memory type
3451 // xacquire <insn> ; xacquire must be accompanied by 'lock'
3452 bool IsPrefix =
3453 StringSwitch<bool>(Name)
3454 .Cases(S0: "cs", S1: "ds", S2: "es", S3: "fs", S4: "gs", S5: "ss", Value: true)
3455 .Cases(S0: "rex64", S1: "data32", S2: "data16", S3: "addr32", S4: "addr16", Value: true)
3456 .Cases(S0: "xacquire", S1: "xrelease", Value: true)
3457 .Cases(S0: "acquire", S1: "release", Value: isParsingIntelSyntax())
3458 .Default(Value: false);
3459
3460 auto isLockRepeatNtPrefix = [](StringRef N) {
3461 return StringSwitch<bool>(N)
3462 .Cases(S0: "lock", S1: "rep", S2: "repe", S3: "repz", S4: "repne", S5: "repnz", S6: "notrack", Value: true)
3463 .Default(Value: false);
3464 };
3465
3466 bool CurlyAsEndOfStatement = false;
3467
3468 unsigned Flags = X86::IP_NO_PREFIX;
3469 while (isLockRepeatNtPrefix(Name.lower())) {
3470 unsigned Prefix =
3471 StringSwitch<unsigned>(Name)
3472 .Cases(S0: "lock", S1: "lock", Value: X86::IP_HAS_LOCK)
3473 .Cases(S0: "rep", S1: "repe", S2: "repz", Value: X86::IP_HAS_REPEAT)
3474 .Cases(S0: "repne", S1: "repnz", Value: X86::IP_HAS_REPEAT_NE)
3475 .Cases(S0: "notrack", S1: "notrack", Value: X86::IP_HAS_NOTRACK)
3476 .Default(Value: X86::IP_NO_PREFIX); // Invalid prefix (impossible)
3477 Flags |= Prefix;
3478 if (getLexer().is(K: AsmToken::EndOfStatement)) {
3479 // We don't have real instr with the given prefix
3480 // let's use the prefix as the instr.
3481 // TODO: there could be several prefixes one after another
3482 Flags = X86::IP_NO_PREFIX;
3483 break;
3484 }
3485 // FIXME: The mnemonic won't match correctly if its not in lower case.
3486 Name = Parser.getTok().getString();
3487 Parser.Lex(); // eat the prefix
3488 // Hack: we could have something like "rep # some comment" or
3489 // "lock; cmpxchg16b $1" or "lock\0A\09incl" or "lock/incl"
3490 while (Name.starts_with(Prefix: ";") || Name.starts_with(Prefix: "\n") ||
3491 Name.starts_with(Prefix: "#") || Name.starts_with(Prefix: "\t") ||
3492 Name.starts_with(Prefix: "/")) {
3493 // FIXME: The mnemonic won't match correctly if its not in lower case.
3494 Name = Parser.getTok().getString();
3495 Parser.Lex(); // go to next prefix or instr
3496 }
3497 }
3498
3499 if (Flags)
3500 PatchedName = Name;
3501
3502 // Hacks to handle 'data16' and 'data32'
3503 if (PatchedName == "data16" && is16BitMode()) {
3504 return Error(L: NameLoc, Msg: "redundant data16 prefix");
3505 }
3506 if (PatchedName == "data32") {
3507 if (is32BitMode())
3508 return Error(L: NameLoc, Msg: "redundant data32 prefix");
3509 if (is64BitMode())
3510 return Error(L: NameLoc, Msg: "'data32' is not supported in 64-bit mode");
3511 // Hack to 'data16' for the table lookup.
3512 PatchedName = "data16";
3513
3514 if (getLexer().isNot(K: AsmToken::EndOfStatement)) {
3515 StringRef Next = Parser.getTok().getString();
3516 getLexer().Lex();
3517 // data32 effectively changes the instruction suffix.
3518 // TODO Generalize.
3519 if (Next == "callw")
3520 Next = "calll";
3521 if (Next == "ljmpw")
3522 Next = "ljmpl";
3523
3524 Name = Next;
3525 PatchedName = Name;
3526 ForcedDataPrefix = X86::Is32Bit;
3527 IsPrefix = false;
3528 }
3529 }
3530
3531 Operands.push_back(Elt: X86Operand::CreateToken(Str: PatchedName, Loc: NameLoc));
3532
3533 // Push the immediate if we extracted one from the mnemonic.
3534 if (ComparisonPredicate != ~0U && !isParsingIntelSyntax()) {
3535 const MCExpr *ImmOp = MCConstantExpr::create(Value: ComparisonPredicate,
3536 Ctx&: getParser().getContext());
3537 Operands.push_back(Elt: X86Operand::CreateImm(Val: ImmOp, StartLoc: NameLoc, EndLoc: NameLoc));
3538 }
3539
3540 // Parse condtional flags after mnemonic.
3541 if ((Name.starts_with(Prefix: "ccmp") || Name.starts_with(Prefix: "ctest")) &&
3542 parseCFlagsOp(Operands))
3543 return true;
3544
3545 // This does the actual operand parsing. Don't parse any more if we have a
3546 // prefix juxtaposed with an operation like "lock incl 4(%rax)", because we
3547 // just want to parse the "lock" as the first instruction and the "incl" as
3548 // the next one.
3549 if (getLexer().isNot(K: AsmToken::EndOfStatement) && !IsPrefix) {
3550 // Parse '*' modifier.
3551 if (getLexer().is(K: AsmToken::Star))
3552 Operands.push_back(Elt: X86Operand::CreateToken(Str: "*", Loc: consumeToken()));
3553
3554 // Read the operands.
3555 while (true) {
3556 if (parseOperand(Operands, Name))
3557 return true;
3558 if (HandleAVX512Operand(Operands))
3559 return true;
3560
3561 // check for comma and eat it
3562 if (getLexer().is(K: AsmToken::Comma))
3563 Parser.Lex();
3564 else
3565 break;
3566 }
3567
3568 // In MS inline asm curly braces mark the beginning/end of a block,
3569 // therefore they should be interepreted as end of statement
3570 CurlyAsEndOfStatement =
3571 isParsingIntelSyntax() && isParsingMSInlineAsm() &&
3572 (getLexer().is(K: AsmToken::LCurly) || getLexer().is(K: AsmToken::RCurly));
3573 if (getLexer().isNot(K: AsmToken::EndOfStatement) && !CurlyAsEndOfStatement)
3574 return TokError(Msg: "unexpected token in argument list");
3575 }
3576
3577 // Push the immediate if we extracted one from the mnemonic.
3578 if (ComparisonPredicate != ~0U && isParsingIntelSyntax()) {
3579 const MCExpr *ImmOp = MCConstantExpr::create(Value: ComparisonPredicate,
3580 Ctx&: getParser().getContext());
3581 Operands.push_back(Elt: X86Operand::CreateImm(Val: ImmOp, StartLoc: NameLoc, EndLoc: NameLoc));
3582 }
3583
3584 // Consume the EndOfStatement or the prefix separator Slash
3585 if (getLexer().is(K: AsmToken::EndOfStatement) ||
3586 (IsPrefix && getLexer().is(K: AsmToken::Slash)))
3587 Parser.Lex();
3588 else if (CurlyAsEndOfStatement)
3589 // Add an actual EndOfStatement before the curly brace
3590 Info.AsmRewrites->emplace_back(Args: AOK_EndOfStatement,
3591 Args: getLexer().getTok().getLoc(), Args: 0);
3592
3593 // This is for gas compatibility and cannot be done in td.
3594 // Adding "p" for some floating point with no argument.
3595 // For example: fsub --> fsubp
3596 bool IsFp =
3597 Name == "fsub" || Name == "fdiv" || Name == "fsubr" || Name == "fdivr";
3598 if (IsFp && Operands.size() == 1) {
3599 const char *Repl = StringSwitch<const char *>(Name)
3600 .Case(S: "fsub", Value: "fsubp")
3601 .Case(S: "fdiv", Value: "fdivp")
3602 .Case(S: "fsubr", Value: "fsubrp")
3603 .Case(S: "fdivr", Value: "fdivrp");
3604 static_cast<X86Operand &>(*Operands[0]).setTokenValue(Repl);
3605 }
3606
3607 if ((Name == "mov" || Name == "movw" || Name == "movl") &&
3608 (Operands.size() == 3)) {
3609 X86Operand &Op1 = (X86Operand &)*Operands[1];
3610 X86Operand &Op2 = (X86Operand &)*Operands[2];
3611 SMLoc Loc = Op1.getEndLoc();
3612 // Moving a 32 or 16 bit value into a segment register has the same
3613 // behavior. Modify such instructions to always take shorter form.
3614 if (Op1.isReg() && Op2.isReg() &&
3615 X86MCRegisterClasses[X86::SEGMENT_REGRegClassID].contains(
3616 Reg: Op2.getReg()) &&
3617 (X86MCRegisterClasses[X86::GR16RegClassID].contains(Reg: Op1.getReg()) ||
3618 X86MCRegisterClasses[X86::GR32RegClassID].contains(Reg: Op1.getReg()))) {
3619 // Change instruction name to match new instruction.
3620 if (Name != "mov" && Name[3] == (is16BitMode() ? 'l' : 'w')) {
3621 Name = is16BitMode() ? "movw" : "movl";
3622 Operands[0] = X86Operand::CreateToken(Str: Name, Loc: NameLoc);
3623 }
3624 // Select the correct equivalent 16-/32-bit source register.
3625 MCRegister Reg =
3626 getX86SubSuperRegister(Reg: Op1.getReg(), Size: is16BitMode() ? 16 : 32);
3627 Operands[1] = X86Operand::CreateReg(Reg, StartLoc: Loc, EndLoc: Loc);
3628 }
3629 }
3630
3631 // This is a terrible hack to handle "out[s]?[bwl]? %al, (%dx)" ->
3632 // "outb %al, %dx". Out doesn't take a memory form, but this is a widely
3633 // documented form in various unofficial manuals, so a lot of code uses it.
3634 if ((Name == "outb" || Name == "outsb" || Name == "outw" || Name == "outsw" ||
3635 Name == "outl" || Name == "outsl" || Name == "out" || Name == "outs") &&
3636 Operands.size() == 3) {
3637 X86Operand &Op = (X86Operand &)*Operands.back();
3638 if (Op.isDXReg())
3639 Operands.back() = X86Operand::CreateReg(Reg: X86::DX, StartLoc: Op.getStartLoc(),
3640 EndLoc: Op.getEndLoc());
3641 }
3642 // Same hack for "in[s]?[bwl]? (%dx), %al" -> "inb %dx, %al".
3643 if ((Name == "inb" || Name == "insb" || Name == "inw" || Name == "insw" ||
3644 Name == "inl" || Name == "insl" || Name == "in" || Name == "ins") &&
3645 Operands.size() == 3) {
3646 X86Operand &Op = (X86Operand &)*Operands[1];
3647 if (Op.isDXReg())
3648 Operands[1] = X86Operand::CreateReg(Reg: X86::DX, StartLoc: Op.getStartLoc(),
3649 EndLoc: Op.getEndLoc());
3650 }
3651
3652 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 2> TmpOperands;
3653 bool HadVerifyError = false;
3654
3655 // Append default arguments to "ins[bwld]"
3656 if (Name.starts_with(Prefix: "ins") &&
3657 (Operands.size() == 1 || Operands.size() == 3) &&
3658 (Name == "insb" || Name == "insw" || Name == "insl" || Name == "insd" ||
3659 Name == "ins")) {
3660
3661 AddDefaultSrcDestOperands(Operands&: TmpOperands,
3662 Src: X86Operand::CreateReg(Reg: X86::DX, StartLoc: NameLoc, EndLoc: NameLoc),
3663 Dst: DefaultMemDIOperand(Loc: NameLoc));
3664 HadVerifyError = VerifyAndAdjustOperands(OrigOperands&: Operands, FinalOperands&: TmpOperands);
3665 }
3666
3667 // Append default arguments to "outs[bwld]"
3668 if (Name.starts_with(Prefix: "outs") &&
3669 (Operands.size() == 1 || Operands.size() == 3) &&
3670 (Name == "outsb" || Name == "outsw" || Name == "outsl" ||
3671 Name == "outsd" || Name == "outs")) {
3672 AddDefaultSrcDestOperands(Operands&: TmpOperands, Src: DefaultMemSIOperand(Loc: NameLoc),
3673 Dst: X86Operand::CreateReg(Reg: X86::DX, StartLoc: NameLoc, EndLoc: NameLoc));
3674 HadVerifyError = VerifyAndAdjustOperands(OrigOperands&: Operands, FinalOperands&: TmpOperands);
3675 }
3676
3677 // Transform "lods[bwlq]" into "lods[bwlq] ($SIREG)" for appropriate
3678 // values of $SIREG according to the mode. It would be nice if this
3679 // could be achieved with InstAlias in the tables.
3680 if (Name.starts_with(Prefix: "lods") &&
3681 (Operands.size() == 1 || Operands.size() == 2) &&
3682 (Name == "lods" || Name == "lodsb" || Name == "lodsw" ||
3683 Name == "lodsl" || Name == "lodsd" || Name == "lodsq")) {
3684 TmpOperands.push_back(Elt: DefaultMemSIOperand(Loc: NameLoc));
3685 HadVerifyError = VerifyAndAdjustOperands(OrigOperands&: Operands, FinalOperands&: TmpOperands);
3686 }
3687
3688 // Transform "stos[bwlq]" into "stos[bwlq] ($DIREG)" for appropriate
3689 // values of $DIREG according to the mode. It would be nice if this
3690 // could be achieved with InstAlias in the tables.
3691 if (Name.starts_with(Prefix: "stos") &&
3692 (Operands.size() == 1 || Operands.size() == 2) &&
3693 (Name == "stos" || Name == "stosb" || Name == "stosw" ||
3694 Name == "stosl" || Name == "stosd" || Name == "stosq")) {
3695 TmpOperands.push_back(Elt: DefaultMemDIOperand(Loc: NameLoc));
3696 HadVerifyError = VerifyAndAdjustOperands(OrigOperands&: Operands, FinalOperands&: TmpOperands);
3697 }
3698
3699 // Transform "scas[bwlq]" into "scas[bwlq] ($DIREG)" for appropriate
3700 // values of $DIREG according to the mode. It would be nice if this
3701 // could be achieved with InstAlias in the tables.
3702 if (Name.starts_with(Prefix: "scas") &&
3703 (Operands.size() == 1 || Operands.size() == 2) &&
3704 (Name == "scas" || Name == "scasb" || Name == "scasw" ||
3705 Name == "scasl" || Name == "scasd" || Name == "scasq")) {
3706 TmpOperands.push_back(Elt: DefaultMemDIOperand(Loc: NameLoc));
3707 HadVerifyError = VerifyAndAdjustOperands(OrigOperands&: Operands, FinalOperands&: TmpOperands);
3708 }
3709
3710 // Add default SI and DI operands to "cmps[bwlq]".
3711 if (Name.starts_with(Prefix: "cmps") &&
3712 (Operands.size() == 1 || Operands.size() == 3) &&
3713 (Name == "cmps" || Name == "cmpsb" || Name == "cmpsw" ||
3714 Name == "cmpsl" || Name == "cmpsd" || Name == "cmpsq")) {
3715 AddDefaultSrcDestOperands(Operands&: TmpOperands, Src: DefaultMemDIOperand(Loc: NameLoc),
3716 Dst: DefaultMemSIOperand(Loc: NameLoc));
3717 HadVerifyError = VerifyAndAdjustOperands(OrigOperands&: Operands, FinalOperands&: TmpOperands);
3718 }
3719
3720 // Add default SI and DI operands to "movs[bwlq]".
3721 if (((Name.starts_with(Prefix: "movs") &&
3722 (Name == "movs" || Name == "movsb" || Name == "movsw" ||
3723 Name == "movsl" || Name == "movsd" || Name == "movsq")) ||
3724 (Name.starts_with(Prefix: "smov") &&
3725 (Name == "smov" || Name == "smovb" || Name == "smovw" ||
3726 Name == "smovl" || Name == "smovd" || Name == "smovq"))) &&
3727 (Operands.size() == 1 || Operands.size() == 3)) {
3728 if (Name == "movsd" && Operands.size() == 1 && !isParsingIntelSyntax())
3729 Operands.back() = X86Operand::CreateToken(Str: "movsl", Loc: NameLoc);
3730 AddDefaultSrcDestOperands(Operands&: TmpOperands, Src: DefaultMemSIOperand(Loc: NameLoc),
3731 Dst: DefaultMemDIOperand(Loc: NameLoc));
3732 HadVerifyError = VerifyAndAdjustOperands(OrigOperands&: Operands, FinalOperands&: TmpOperands);
3733 }
3734
3735 // Check if we encountered an error for one the string insturctions
3736 if (HadVerifyError) {
3737 return HadVerifyError;
3738 }
3739
3740 // Transforms "xlat mem8" into "xlatb"
3741 if ((Name == "xlat" || Name == "xlatb") && Operands.size() == 2) {
3742 X86Operand &Op1 = static_cast<X86Operand &>(*Operands[1]);
3743 if (Op1.isMem8()) {
3744 Warning(L: Op1.getStartLoc(), Msg: "memory operand is only for determining the "
3745 "size, (R|E)BX will be used for the location");
3746 Operands.pop_back();
3747 static_cast<X86Operand &>(*Operands[0]).setTokenValue("xlatb");
3748 }
3749 }
3750
3751 if (Flags)
3752 Operands.push_back(Elt: X86Operand::CreatePrefix(Prefixes: Flags, StartLoc: NameLoc, EndLoc: NameLoc));
3753 return false;
3754}
3755
3756static bool convertSSEToAVX(MCInst &Inst) {
3757 ArrayRef<X86TableEntry> Table{X86SSE2AVXTable};
3758 unsigned Opcode = Inst.getOpcode();
3759 const auto I = llvm::lower_bound(Range&: Table, Value&: Opcode);
3760 if (I == Table.end() || I->OldOpc != Opcode)
3761 return false;
3762
3763 Inst.setOpcode(I->NewOpc);
3764 // AVX variant of BLENDVPD/BLENDVPS/PBLENDVB instructions has more
3765 // operand compare to SSE variant, which is added below
3766 if (X86::isBLENDVPD(Opcode) || X86::isBLENDVPS(Opcode) ||
3767 X86::isPBLENDVB(Opcode))
3768 Inst.addOperand(Op: Inst.getOperand(i: 2));
3769
3770 return true;
3771}
3772
3773bool X86AsmParser::processInstruction(MCInst &Inst, const OperandVector &Ops) {
3774 if (MCOptions.X86Sse2Avx && convertSSEToAVX(Inst))
3775 return true;
3776
3777 if (ForcedOpcodePrefix != OpcodePrefix_VEX3 &&
3778 X86::optimizeInstFromVEX3ToVEX2(MI&: Inst, Desc: MII.get(Opcode: Inst.getOpcode())))
3779 return true;
3780
3781 if (X86::optimizeShiftRotateWithImmediateOne(MI&: Inst))
3782 return true;
3783
3784 auto replaceWithCCMPCTEST = [&](unsigned Opcode) -> bool {
3785 if (ForcedOpcodePrefix == OpcodePrefix_EVEX) {
3786 Inst.setFlags(~(X86::IP_USE_EVEX)&Inst.getFlags());
3787 Inst.setOpcode(Opcode);
3788 Inst.addOperand(Op: MCOperand::createImm(Val: 0));
3789 Inst.addOperand(Op: MCOperand::createImm(Val: 10));
3790 return true;
3791 }
3792 return false;
3793 };
3794
3795 switch (Inst.getOpcode()) {
3796 default: return false;
3797 case X86::JMP_1:
3798 // {disp32} forces a larger displacement as if the instruction was relaxed.
3799 // NOTE: 16-bit mode uses 16-bit displacement even though it says {disp32}.
3800 // This matches GNU assembler.
3801 if (ForcedDispEncoding == DispEncoding_Disp32) {
3802 Inst.setOpcode(is16BitMode() ? X86::JMP_2 : X86::JMP_4);
3803 return true;
3804 }
3805
3806 return false;
3807 case X86::JCC_1:
3808 // {disp32} forces a larger displacement as if the instruction was relaxed.
3809 // NOTE: 16-bit mode uses 16-bit displacement even though it says {disp32}.
3810 // This matches GNU assembler.
3811 if (ForcedDispEncoding == DispEncoding_Disp32) {
3812 Inst.setOpcode(is16BitMode() ? X86::JCC_2 : X86::JCC_4);
3813 return true;
3814 }
3815
3816 return false;
3817 case X86::INT: {
3818 // Transforms "int $3" into "int3" as a size optimization.
3819 // We can't write this as an InstAlias.
3820 if (!Inst.getOperand(i: 0).isImm() || Inst.getOperand(i: 0).getImm() != 3)
3821 return false;
3822 Inst.clear();
3823 Inst.setOpcode(X86::INT3);
3824 return true;
3825 }
3826 // `{evex} cmp <>, <>` is alias of `ccmpt {dfv=} <>, <>`, and
3827 // `{evex} test <>, <>` is alias of `ctest {dfv=} <>, <>`
3828#define FROM_TO(FROM, TO) \
3829 case X86::FROM: \
3830 return replaceWithCCMPCTEST(X86::TO);
3831 FROM_TO(CMP64rr, CCMP64rr)
3832 FROM_TO(CMP64mi32, CCMP64mi32)
3833 FROM_TO(CMP64mi8, CCMP64mi8)
3834 FROM_TO(CMP64mr, CCMP64mr)
3835 FROM_TO(CMP64ri32, CCMP64ri32)
3836 FROM_TO(CMP64ri8, CCMP64ri8)
3837 FROM_TO(CMP64rm, CCMP64rm)
3838
3839 FROM_TO(CMP32rr, CCMP32rr)
3840 FROM_TO(CMP32mi, CCMP32mi)
3841 FROM_TO(CMP32mi8, CCMP32mi8)
3842 FROM_TO(CMP32mr, CCMP32mr)
3843 FROM_TO(CMP32ri, CCMP32ri)
3844 FROM_TO(CMP32ri8, CCMP32ri8)
3845 FROM_TO(CMP32rm, CCMP32rm)
3846
3847 FROM_TO(CMP16rr, CCMP16rr)
3848 FROM_TO(CMP16mi, CCMP16mi)
3849 FROM_TO(CMP16mi8, CCMP16mi8)
3850 FROM_TO(CMP16mr, CCMP16mr)
3851 FROM_TO(CMP16ri, CCMP16ri)
3852 FROM_TO(CMP16ri8, CCMP16ri8)
3853 FROM_TO(CMP16rm, CCMP16rm)
3854
3855 FROM_TO(CMP8rr, CCMP8rr)
3856 FROM_TO(CMP8mi, CCMP8mi)
3857 FROM_TO(CMP8mr, CCMP8mr)
3858 FROM_TO(CMP8ri, CCMP8ri)
3859 FROM_TO(CMP8rm, CCMP8rm)
3860
3861 FROM_TO(TEST64rr, CTEST64rr)
3862 FROM_TO(TEST64mi32, CTEST64mi32)
3863 FROM_TO(TEST64mr, CTEST64mr)
3864 FROM_TO(TEST64ri32, CTEST64ri32)
3865
3866 FROM_TO(TEST32rr, CTEST32rr)
3867 FROM_TO(TEST32mi, CTEST32mi)
3868 FROM_TO(TEST32mr, CTEST32mr)
3869 FROM_TO(TEST32ri, CTEST32ri)
3870
3871 FROM_TO(TEST16rr, CTEST16rr)
3872 FROM_TO(TEST16mi, CTEST16mi)
3873 FROM_TO(TEST16mr, CTEST16mr)
3874 FROM_TO(TEST16ri, CTEST16ri)
3875
3876 FROM_TO(TEST8rr, CTEST8rr)
3877 FROM_TO(TEST8mi, CTEST8mi)
3878 FROM_TO(TEST8mr, CTEST8mr)
3879 FROM_TO(TEST8ri, CTEST8ri)
3880#undef FROM_TO
3881 }
3882}
3883
3884bool X86AsmParser::validateInstruction(MCInst &Inst, const OperandVector &Ops) {
3885 using namespace X86;
3886 const MCRegisterInfo *MRI = getContext().getRegisterInfo();
3887 unsigned Opcode = Inst.getOpcode();
3888 uint64_t TSFlags = MII.get(Opcode).TSFlags;
3889 if (isVFCMADDCPH(Opcode) || isVFCMADDCSH(Opcode) || isVFMADDCPH(Opcode) ||
3890 isVFMADDCSH(Opcode)) {
3891 MCRegister Dest = Inst.getOperand(i: 0).getReg();
3892 for (unsigned i = 2; i < Inst.getNumOperands(); i++)
3893 if (Inst.getOperand(i).isReg() && Dest == Inst.getOperand(i).getReg())
3894 return Warning(L: Ops[0]->getStartLoc(), Msg: "Destination register should be "
3895 "distinct from source registers");
3896 } else if (isVFCMULCPH(Opcode) || isVFCMULCSH(Opcode) || isVFMULCPH(Opcode) ||
3897 isVFMULCSH(Opcode)) {
3898 MCRegister Dest = Inst.getOperand(i: 0).getReg();
3899 // The mask variants have different operand list. Scan from the third
3900 // operand to avoid emitting incorrect warning.
3901 // VFMULCPHZrr Dest, Src1, Src2
3902 // VFMULCPHZrrk Dest, Dest, Mask, Src1, Src2
3903 // VFMULCPHZrrkz Dest, Mask, Src1, Src2
3904 for (unsigned i = ((TSFlags & X86II::EVEX_K) ? 2 : 1);
3905 i < Inst.getNumOperands(); i++)
3906 if (Inst.getOperand(i).isReg() && Dest == Inst.getOperand(i).getReg())
3907 return Warning(L: Ops[0]->getStartLoc(), Msg: "Destination register should be "
3908 "distinct from source registers");
3909 } else if (isV4FMADDPS(Opcode) || isV4FMADDSS(Opcode) ||
3910 isV4FNMADDPS(Opcode) || isV4FNMADDSS(Opcode) ||
3911 isVP4DPWSSDS(Opcode) || isVP4DPWSSD(Opcode)) {
3912 MCRegister Src2 =
3913 Inst.getOperand(i: Inst.getNumOperands() - X86::AddrNumOperands - 1)
3914 .getReg();
3915 unsigned Src2Enc = MRI->getEncodingValue(Reg: Src2);
3916 if (Src2Enc % 4 != 0) {
3917 StringRef RegName = X86IntelInstPrinter::getRegisterName(Reg: Src2);
3918 unsigned GroupStart = (Src2Enc / 4) * 4;
3919 unsigned GroupEnd = GroupStart + 3;
3920 return Warning(L: Ops[0]->getStartLoc(),
3921 Msg: "source register '" + RegName + "' implicitly denotes '" +
3922 RegName.take_front(N: 3) + Twine(GroupStart) + "' to '" +
3923 RegName.take_front(N: 3) + Twine(GroupEnd) +
3924 "' source group");
3925 }
3926 } else if (isVGATHERDPD(Opcode) || isVGATHERDPS(Opcode) ||
3927 isVGATHERQPD(Opcode) || isVGATHERQPS(Opcode) ||
3928 isVPGATHERDD(Opcode) || isVPGATHERDQ(Opcode) ||
3929 isVPGATHERQD(Opcode) || isVPGATHERQQ(Opcode)) {
3930 bool HasEVEX = (TSFlags & X86II::EncodingMask) == X86II::EVEX;
3931 if (HasEVEX) {
3932 unsigned Dest = MRI->getEncodingValue(Reg: Inst.getOperand(i: 0).getReg());
3933 unsigned Index = MRI->getEncodingValue(
3934 Reg: Inst.getOperand(i: 4 + X86::AddrIndexReg).getReg());
3935 if (Dest == Index)
3936 return Warning(L: Ops[0]->getStartLoc(), Msg: "index and destination registers "
3937 "should be distinct");
3938 } else {
3939 unsigned Dest = MRI->getEncodingValue(Reg: Inst.getOperand(i: 0).getReg());
3940 unsigned Mask = MRI->getEncodingValue(Reg: Inst.getOperand(i: 1).getReg());
3941 unsigned Index = MRI->getEncodingValue(
3942 Reg: Inst.getOperand(i: 3 + X86::AddrIndexReg).getReg());
3943 if (Dest == Mask || Dest == Index || Mask == Index)
3944 return Warning(L: Ops[0]->getStartLoc(), Msg: "mask, index, and destination "
3945 "registers should be distinct");
3946 }
3947 } else if (isTCMMIMFP16PS(Opcode) || isTCMMRLFP16PS(Opcode) ||
3948 isTDPBF16PS(Opcode) || isTDPFP16PS(Opcode) || isTDPBSSD(Opcode) ||
3949 isTDPBSUD(Opcode) || isTDPBUSD(Opcode) || isTDPBUUD(Opcode)) {
3950 MCRegister SrcDest = Inst.getOperand(i: 0).getReg();
3951 MCRegister Src1 = Inst.getOperand(i: 2).getReg();
3952 MCRegister Src2 = Inst.getOperand(i: 3).getReg();
3953 if (SrcDest == Src1 || SrcDest == Src2 || Src1 == Src2)
3954 return Error(L: Ops[0]->getStartLoc(), Msg: "all tmm registers must be distinct");
3955 }
3956
3957 // Check that we aren't mixing AH/BH/CH/DH with REX prefix. We only need to
3958 // check this with the legacy encoding, VEX/EVEX/XOP don't use REX.
3959 if ((TSFlags & X86II::EncodingMask) == 0) {
3960 MCRegister HReg;
3961 bool UsesRex = TSFlags & X86II::REX_W;
3962 unsigned NumOps = Inst.getNumOperands();
3963 for (unsigned i = 0; i != NumOps; ++i) {
3964 const MCOperand &MO = Inst.getOperand(i);
3965 if (!MO.isReg())
3966 continue;
3967 MCRegister Reg = MO.getReg();
3968 if (Reg == X86::AH || Reg == X86::BH || Reg == X86::CH || Reg == X86::DH)
3969 HReg = Reg;
3970 if (X86II::isX86_64NonExtLowByteReg(Reg) ||
3971 X86II::isX86_64ExtendedReg(Reg))
3972 UsesRex = true;
3973 }
3974
3975 if (UsesRex && HReg) {
3976 StringRef RegName = X86IntelInstPrinter::getRegisterName(Reg: HReg);
3977 return Error(L: Ops[0]->getStartLoc(),
3978 Msg: "can't encode '" + RegName + "' in an instruction requiring "
3979 "REX prefix");
3980 }
3981 }
3982
3983 if ((Opcode == X86::PREFETCHIT0 || Opcode == X86::PREFETCHIT1)) {
3984 const MCOperand &MO = Inst.getOperand(i: X86::AddrBaseReg);
3985 if (!MO.isReg() || MO.getReg() != X86::RIP)
3986 return Warning(
3987 L: Ops[0]->getStartLoc(),
3988 Msg: Twine((Inst.getOpcode() == X86::PREFETCHIT0 ? "'prefetchit0'"
3989 : "'prefetchit1'")) +
3990 " only supports RIP-relative address");
3991 }
3992 return false;
3993}
3994
3995void X86AsmParser::emitWarningForSpecialLVIInstruction(SMLoc Loc) {
3996 Warning(L: Loc, Msg: "Instruction may be vulnerable to LVI and "
3997 "requires manual mitigation");
3998 Note(L: SMLoc(), Msg: "See https://software.intel.com/"
3999 "security-software-guidance/insights/"
4000 "deep-dive-load-value-injection#specialinstructions"
4001 " for more information");
4002}
4003
4004/// RET instructions and also instructions that indirect calls/jumps from memory
4005/// combine a load and a branch within a single instruction. To mitigate these
4006/// instructions against LVI, they must be decomposed into separate load and
4007/// branch instructions, with an LFENCE in between. For more details, see:
4008/// - X86LoadValueInjectionRetHardening.cpp
4009/// - X86LoadValueInjectionIndirectThunks.cpp
4010/// - https://software.intel.com/security-software-guidance/insights/deep-dive-load-value-injection
4011///
4012/// Returns `true` if a mitigation was applied or warning was emitted.
4013void X86AsmParser::applyLVICFIMitigation(MCInst &Inst, MCStreamer &Out) {
4014 // Information on control-flow instructions that require manual mitigation can
4015 // be found here:
4016 // https://software.intel.com/security-software-guidance/insights/deep-dive-load-value-injection#specialinstructions
4017 switch (Inst.getOpcode()) {
4018 case X86::RET16:
4019 case X86::RET32:
4020 case X86::RET64:
4021 case X86::RETI16:
4022 case X86::RETI32:
4023 case X86::RETI64: {
4024 MCInst ShlInst, FenceInst;
4025 bool Parse32 = is32BitMode() || Code16GCC;
4026 MCRegister Basereg =
4027 is64BitMode() ? X86::RSP : (Parse32 ? X86::ESP : X86::SP);
4028 const MCExpr *Disp = MCConstantExpr::create(Value: 0, Ctx&: getContext());
4029 auto ShlMemOp = X86Operand::CreateMem(ModeSize: getPointerWidth(), /*SegReg=*/0, Disp,
4030 /*BaseReg=*/Basereg, /*IndexReg=*/0,
4031 /*Scale=*/1, StartLoc: SMLoc{}, EndLoc: SMLoc{}, Size: 0);
4032 ShlInst.setOpcode(X86::SHL64mi);
4033 ShlMemOp->addMemOperands(Inst&: ShlInst, N: 5);
4034 ShlInst.addOperand(Op: MCOperand::createImm(Val: 0));
4035 FenceInst.setOpcode(X86::LFENCE);
4036 Out.emitInstruction(Inst: ShlInst, STI: getSTI());
4037 Out.emitInstruction(Inst: FenceInst, STI: getSTI());
4038 return;
4039 }
4040 case X86::JMP16m:
4041 case X86::JMP32m:
4042 case X86::JMP64m:
4043 case X86::CALL16m:
4044 case X86::CALL32m:
4045 case X86::CALL64m:
4046 emitWarningForSpecialLVIInstruction(Loc: Inst.getLoc());
4047 return;
4048 }
4049}
4050
4051/// To mitigate LVI, every instruction that performs a load can be followed by
4052/// an LFENCE instruction to squash any potential mis-speculation. There are
4053/// some instructions that require additional considerations, and may requre
4054/// manual mitigation. For more details, see:
4055/// https://software.intel.com/security-software-guidance/insights/deep-dive-load-value-injection
4056///
4057/// Returns `true` if a mitigation was applied or warning was emitted.
4058void X86AsmParser::applyLVILoadHardeningMitigation(MCInst &Inst,
4059 MCStreamer &Out) {
4060 auto Opcode = Inst.getOpcode();
4061 auto Flags = Inst.getFlags();
4062 if ((Flags & X86::IP_HAS_REPEAT) || (Flags & X86::IP_HAS_REPEAT_NE)) {
4063 // Information on REP string instructions that require manual mitigation can
4064 // be found here:
4065 // https://software.intel.com/security-software-guidance/insights/deep-dive-load-value-injection#specialinstructions
4066 switch (Opcode) {
4067 case X86::CMPSB:
4068 case X86::CMPSW:
4069 case X86::CMPSL:
4070 case X86::CMPSQ:
4071 case X86::SCASB:
4072 case X86::SCASW:
4073 case X86::SCASL:
4074 case X86::SCASQ:
4075 emitWarningForSpecialLVIInstruction(Loc: Inst.getLoc());
4076 return;
4077 }
4078 } else if (Opcode == X86::REP_PREFIX || Opcode == X86::REPNE_PREFIX) {
4079 // If a REP instruction is found on its own line, it may or may not be
4080 // followed by a vulnerable instruction. Emit a warning just in case.
4081 emitWarningForSpecialLVIInstruction(Loc: Inst.getLoc());
4082 return;
4083 }
4084
4085 const MCInstrDesc &MCID = MII.get(Opcode: Inst.getOpcode());
4086
4087 // Can't mitigate after terminators or calls. A control flow change may have
4088 // already occurred.
4089 if (MCID.isTerminator() || MCID.isCall())
4090 return;
4091
4092 // LFENCE has the mayLoad property, don't double fence.
4093 if (MCID.mayLoad() && Inst.getOpcode() != X86::LFENCE) {
4094 MCInst FenceInst;
4095 FenceInst.setOpcode(X86::LFENCE);
4096 Out.emitInstruction(Inst: FenceInst, STI: getSTI());
4097 }
4098}
4099
4100void X86AsmParser::emitInstruction(MCInst &Inst, OperandVector &Operands,
4101 MCStreamer &Out) {
4102 if (LVIInlineAsmHardening &&
4103 getSTI().hasFeature(Feature: X86::FeatureLVIControlFlowIntegrity))
4104 applyLVICFIMitigation(Inst, Out);
4105
4106 Out.emitInstruction(Inst, STI: getSTI());
4107
4108 if (LVIInlineAsmHardening &&
4109 getSTI().hasFeature(Feature: X86::FeatureLVILoadHardening))
4110 applyLVILoadHardeningMitigation(Inst, Out);
4111}
4112
4113static unsigned getPrefixes(OperandVector &Operands) {
4114 unsigned Result = 0;
4115 X86Operand &Prefix = static_cast<X86Operand &>(*Operands.back());
4116 if (Prefix.isPrefix()) {
4117 Result = Prefix.getPrefix();
4118 Operands.pop_back();
4119 }
4120 return Result;
4121}
4122
4123bool X86AsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
4124 OperandVector &Operands,
4125 MCStreamer &Out, uint64_t &ErrorInfo,
4126 bool MatchingInlineAsm) {
4127 assert(!Operands.empty() && "Unexpect empty operand list!");
4128 assert((*Operands[0]).isToken() && "Leading operand should always be a mnemonic!");
4129
4130 // First, handle aliases that expand to multiple instructions.
4131 MatchFPUWaitAlias(IDLoc, Op&: static_cast<X86Operand &>(*Operands[0]), Operands,
4132 Out, MatchingInlineAsm);
4133 unsigned Prefixes = getPrefixes(Operands);
4134
4135 MCInst Inst;
4136
4137 // If REX/REX2/VEX/EVEX encoding is forced, we need to pass the USE_* flag to
4138 // the encoder and printer.
4139 if (ForcedOpcodePrefix == OpcodePrefix_REX)
4140 Prefixes |= X86::IP_USE_REX;
4141 else if (ForcedOpcodePrefix == OpcodePrefix_REX2)
4142 Prefixes |= X86::IP_USE_REX2;
4143 else if (ForcedOpcodePrefix == OpcodePrefix_VEX)
4144 Prefixes |= X86::IP_USE_VEX;
4145 else if (ForcedOpcodePrefix == OpcodePrefix_VEX2)
4146 Prefixes |= X86::IP_USE_VEX2;
4147 else if (ForcedOpcodePrefix == OpcodePrefix_VEX3)
4148 Prefixes |= X86::IP_USE_VEX3;
4149 else if (ForcedOpcodePrefix == OpcodePrefix_EVEX)
4150 Prefixes |= X86::IP_USE_EVEX;
4151
4152 // Set encoded flags for {disp8} and {disp32}.
4153 if (ForcedDispEncoding == DispEncoding_Disp8)
4154 Prefixes |= X86::IP_USE_DISP8;
4155 else if (ForcedDispEncoding == DispEncoding_Disp32)
4156 Prefixes |= X86::IP_USE_DISP32;
4157
4158 if (Prefixes)
4159 Inst.setFlags(Prefixes);
4160
4161 return isParsingIntelSyntax()
4162 ? matchAndEmitIntelInstruction(IDLoc, Opcode, Inst, Operands, Out,
4163 ErrorInfo, MatchingInlineAsm)
4164 : matchAndEmitATTInstruction(IDLoc, Opcode, Inst, Operands, Out,
4165 ErrorInfo, MatchingInlineAsm);
4166}
4167
4168void X86AsmParser::MatchFPUWaitAlias(SMLoc IDLoc, X86Operand &Op,
4169 OperandVector &Operands, MCStreamer &Out,
4170 bool MatchingInlineAsm) {
4171 // FIXME: This should be replaced with a real .td file alias mechanism.
4172 // Also, MatchInstructionImpl should actually *do* the EmitInstruction
4173 // call.
4174 const char *Repl = StringSwitch<const char *>(Op.getToken())
4175 .Case(S: "finit", Value: "fninit")
4176 .Case(S: "fsave", Value: "fnsave")
4177 .Case(S: "fstcw", Value: "fnstcw")
4178 .Case(S: "fstcww", Value: "fnstcw")
4179 .Case(S: "fstenv", Value: "fnstenv")
4180 .Case(S: "fstsw", Value: "fnstsw")
4181 .Case(S: "fstsww", Value: "fnstsw")
4182 .Case(S: "fclex", Value: "fnclex")
4183 .Default(Value: nullptr);
4184 if (Repl) {
4185 MCInst Inst;
4186 Inst.setOpcode(X86::WAIT);
4187 Inst.setLoc(IDLoc);
4188 if (!MatchingInlineAsm)
4189 emitInstruction(Inst, Operands, Out);
4190 Operands[0] = X86Operand::CreateToken(Str: Repl, Loc: IDLoc);
4191 }
4192}
4193
4194bool X86AsmParser::ErrorMissingFeature(SMLoc IDLoc,
4195 const FeatureBitset &MissingFeatures,
4196 bool MatchingInlineAsm) {
4197 assert(MissingFeatures.any() && "Unknown missing feature!");
4198 SmallString<126> Msg;
4199 raw_svector_ostream OS(Msg);
4200 OS << "instruction requires:";
4201 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i) {
4202 if (MissingFeatures[i])
4203 OS << ' ' << getSubtargetFeatureName(Val: i);
4204 }
4205 return Error(L: IDLoc, Msg: OS.str(), Range: SMRange(), MatchingInlineAsm);
4206}
4207
4208unsigned X86AsmParser::checkTargetMatchPredicate(MCInst &Inst) {
4209 unsigned Opc = Inst.getOpcode();
4210 const MCInstrDesc &MCID = MII.get(Opcode: Opc);
4211 uint64_t TSFlags = MCID.TSFlags;
4212
4213 if (UseApxExtendedReg && !X86II::canUseApxExtendedReg(Desc: MCID))
4214 return Match_Unsupported;
4215 if (ForcedNoFlag == !(TSFlags & X86II::EVEX_NF) && !X86::isCFCMOVCC(Opcode: Opc))
4216 return Match_Unsupported;
4217
4218 switch (ForcedOpcodePrefix) {
4219 case OpcodePrefix_Default:
4220 break;
4221 case OpcodePrefix_REX:
4222 case OpcodePrefix_REX2:
4223 if (TSFlags & X86II::EncodingMask)
4224 return Match_Unsupported;
4225 break;
4226 case OpcodePrefix_VEX:
4227 case OpcodePrefix_VEX2:
4228 case OpcodePrefix_VEX3:
4229 if ((TSFlags & X86II::EncodingMask) != X86II::VEX)
4230 return Match_Unsupported;
4231 break;
4232 case OpcodePrefix_EVEX:
4233 if (is64BitMode() && (TSFlags & X86II::EncodingMask) != X86II::EVEX &&
4234 !X86::isCMP(Opcode: Opc) && !X86::isTEST(Opcode: Opc))
4235 return Match_Unsupported;
4236 if (!is64BitMode() && (TSFlags & X86II::EncodingMask) != X86II::EVEX)
4237 return Match_Unsupported;
4238 break;
4239 }
4240
4241 if ((TSFlags & X86II::ExplicitOpPrefixMask) == X86II::ExplicitVEXPrefix &&
4242 (ForcedOpcodePrefix != OpcodePrefix_VEX &&
4243 ForcedOpcodePrefix != OpcodePrefix_VEX2 &&
4244 ForcedOpcodePrefix != OpcodePrefix_VEX3))
4245 return Match_Unsupported;
4246
4247 return Match_Success;
4248}
4249
4250bool X86AsmParser::matchAndEmitATTInstruction(
4251 SMLoc IDLoc, unsigned &Opcode, MCInst &Inst, OperandVector &Operands,
4252 MCStreamer &Out, uint64_t &ErrorInfo, bool MatchingInlineAsm) {
4253 X86Operand &Op = static_cast<X86Operand &>(*Operands[0]);
4254 SMRange EmptyRange = std::nullopt;
4255 // In 16-bit mode, if data32 is specified, temporarily switch to 32-bit mode
4256 // when matching the instruction.
4257 if (ForcedDataPrefix == X86::Is32Bit)
4258 SwitchMode(mode: X86::Is32Bit);
4259 // First, try a direct match.
4260 FeatureBitset MissingFeatures;
4261 unsigned OriginalError = MatchInstruction(Operands, Inst, ErrorInfo,
4262 MissingFeatures, matchingInlineAsm: MatchingInlineAsm,
4263 VariantID: isParsingIntelSyntax());
4264 if (ForcedDataPrefix == X86::Is32Bit) {
4265 SwitchMode(mode: X86::Is16Bit);
4266 ForcedDataPrefix = 0;
4267 }
4268 switch (OriginalError) {
4269 default: llvm_unreachable("Unexpected match result!");
4270 case Match_Success:
4271 if (!MatchingInlineAsm && validateInstruction(Inst, Ops: Operands))
4272 return true;
4273 // Some instructions need post-processing to, for example, tweak which
4274 // encoding is selected. Loop on it while changes happen so the
4275 // individual transformations can chain off each other.
4276 if (!MatchingInlineAsm)
4277 while (processInstruction(Inst, Ops: Operands))
4278 ;
4279
4280 Inst.setLoc(IDLoc);
4281 if (!MatchingInlineAsm)
4282 emitInstruction(Inst, Operands, Out);
4283 Opcode = Inst.getOpcode();
4284 return false;
4285 case Match_InvalidImmUnsignedi4: {
4286 SMLoc ErrorLoc = ((X86Operand &)*Operands[ErrorInfo]).getStartLoc();
4287 if (ErrorLoc == SMLoc())
4288 ErrorLoc = IDLoc;
4289 return Error(L: ErrorLoc, Msg: "immediate must be an integer in range [0, 15]",
4290 Range: EmptyRange, MatchingInlineAsm);
4291 }
4292 case Match_MissingFeature:
4293 return ErrorMissingFeature(IDLoc, MissingFeatures, MatchingInlineAsm);
4294 case Match_InvalidOperand:
4295 case Match_MnemonicFail:
4296 case Match_Unsupported:
4297 break;
4298 }
4299 if (Op.getToken().empty()) {
4300 Error(L: IDLoc, Msg: "instruction must have size higher than 0", Range: EmptyRange,
4301 MatchingInlineAsm);
4302 return true;
4303 }
4304
4305 // FIXME: Ideally, we would only attempt suffix matches for things which are
4306 // valid prefixes, and we could just infer the right unambiguous
4307 // type. However, that requires substantially more matcher support than the
4308 // following hack.
4309
4310 // Change the operand to point to a temporary token.
4311 StringRef Base = Op.getToken();
4312 SmallString<16> Tmp;
4313 Tmp += Base;
4314 Tmp += ' ';
4315 Op.setTokenValue(Tmp);
4316
4317 // If this instruction starts with an 'f', then it is a floating point stack
4318 // instruction. These come in up to three forms for 32-bit, 64-bit, and
4319 // 80-bit floating point, which use the suffixes s,l,t respectively.
4320 //
4321 // Otherwise, we assume that this may be an integer instruction, which comes
4322 // in 8/16/32/64-bit forms using the b,w,l,q suffixes respectively.
4323 const char *Suffixes = Base[0] != 'f' ? "bwlq" : "slt\0";
4324 // MemSize corresponding to Suffixes. { 8, 16, 32, 64 } { 32, 64, 80, 0 }
4325 const char *MemSize = Base[0] != 'f' ? "\x08\x10\x20\x40" : "\x20\x40\x50\0";
4326
4327 // Check for the various suffix matches.
4328 uint64_t ErrorInfoIgnore;
4329 FeatureBitset ErrorInfoMissingFeatures; // Init suppresses compiler warnings.
4330 unsigned Match[4];
4331
4332 // Some instruction like VPMULDQ is NOT the variant of VPMULD but a new one.
4333 // So we should make sure the suffix matcher only works for memory variant
4334 // that has the same size with the suffix.
4335 // FIXME: This flag is a workaround for legacy instructions that didn't
4336 // declare non suffix variant assembly.
4337 bool HasVectorReg = false;
4338 X86Operand *MemOp = nullptr;
4339 for (const auto &Op : Operands) {
4340 X86Operand *X86Op = static_cast<X86Operand *>(Op.get());
4341 if (X86Op->isVectorReg())
4342 HasVectorReg = true;
4343 else if (X86Op->isMem()) {
4344 MemOp = X86Op;
4345 assert(MemOp->Mem.Size == 0 && "Memory size always 0 under ATT syntax");
4346 // Have we found an unqualified memory operand,
4347 // break. IA allows only one memory operand.
4348 break;
4349 }
4350 }
4351
4352 for (unsigned I = 0, E = std::size(Match); I != E; ++I) {
4353 Tmp.back() = Suffixes[I];
4354 if (MemOp && HasVectorReg)
4355 MemOp->Mem.Size = MemSize[I];
4356 Match[I] = Match_MnemonicFail;
4357 if (MemOp || !HasVectorReg) {
4358 Match[I] =
4359 MatchInstruction(Operands, Inst, ErrorInfo&: ErrorInfoIgnore, MissingFeatures,
4360 matchingInlineAsm: MatchingInlineAsm, VariantID: isParsingIntelSyntax());
4361 // If this returned as a missing feature failure, remember that.
4362 if (Match[I] == Match_MissingFeature)
4363 ErrorInfoMissingFeatures = MissingFeatures;
4364 }
4365 }
4366
4367 // Restore the old token.
4368 Op.setTokenValue(Base);
4369
4370 // If exactly one matched, then we treat that as a successful match (and the
4371 // instruction will already have been filled in correctly, since the failing
4372 // matches won't have modified it).
4373 unsigned NumSuccessfulMatches = llvm::count(Range&: Match, Element: Match_Success);
4374 if (NumSuccessfulMatches == 1) {
4375 if (!MatchingInlineAsm && validateInstruction(Inst, Ops: Operands))
4376 return true;
4377 // Some instructions need post-processing to, for example, tweak which
4378 // encoding is selected. Loop on it while changes happen so the
4379 // individual transformations can chain off each other.
4380 if (!MatchingInlineAsm)
4381 while (processInstruction(Inst, Ops: Operands))
4382 ;
4383
4384 Inst.setLoc(IDLoc);
4385 if (!MatchingInlineAsm)
4386 emitInstruction(Inst, Operands, Out);
4387 Opcode = Inst.getOpcode();
4388 return false;
4389 }
4390
4391 // Otherwise, the match failed, try to produce a decent error message.
4392
4393 // If we had multiple suffix matches, then identify this as an ambiguous
4394 // match.
4395 if (NumSuccessfulMatches > 1) {
4396 char MatchChars[4];
4397 unsigned NumMatches = 0;
4398 for (unsigned I = 0, E = std::size(Match); I != E; ++I)
4399 if (Match[I] == Match_Success)
4400 MatchChars[NumMatches++] = Suffixes[I];
4401
4402 SmallString<126> Msg;
4403 raw_svector_ostream OS(Msg);
4404 OS << "ambiguous instructions require an explicit suffix (could be ";
4405 for (unsigned i = 0; i != NumMatches; ++i) {
4406 if (i != 0)
4407 OS << ", ";
4408 if (i + 1 == NumMatches)
4409 OS << "or ";
4410 OS << "'" << Base << MatchChars[i] << "'";
4411 }
4412 OS << ")";
4413 Error(L: IDLoc, Msg: OS.str(), Range: EmptyRange, MatchingInlineAsm);
4414 return true;
4415 }
4416
4417 // Okay, we know that none of the variants matched successfully.
4418
4419 // If all of the instructions reported an invalid mnemonic, then the original
4420 // mnemonic was invalid.
4421 if (llvm::count(Range&: Match, Element: Match_MnemonicFail) == 4) {
4422 if (OriginalError == Match_MnemonicFail)
4423 return Error(L: IDLoc, Msg: "invalid instruction mnemonic '" + Base + "'",
4424 Range: Op.getLocRange(), MatchingInlineAsm);
4425
4426 if (OriginalError == Match_Unsupported)
4427 return Error(L: IDLoc, Msg: "unsupported instruction", Range: EmptyRange,
4428 MatchingInlineAsm);
4429
4430 assert(OriginalError == Match_InvalidOperand && "Unexpected error");
4431 // Recover location info for the operand if we know which was the problem.
4432 if (ErrorInfo != ~0ULL) {
4433 if (ErrorInfo >= Operands.size())
4434 return Error(L: IDLoc, Msg: "too few operands for instruction", Range: EmptyRange,
4435 MatchingInlineAsm);
4436
4437 X86Operand &Operand = (X86Operand &)*Operands[ErrorInfo];
4438 if (Operand.getStartLoc().isValid()) {
4439 SMRange OperandRange = Operand.getLocRange();
4440 return Error(L: Operand.getStartLoc(), Msg: "invalid operand for instruction",
4441 Range: OperandRange, MatchingInlineAsm);
4442 }
4443 }
4444
4445 return Error(L: IDLoc, Msg: "invalid operand for instruction", Range: EmptyRange,
4446 MatchingInlineAsm);
4447 }
4448
4449 // If one instruction matched as unsupported, report this as unsupported.
4450 if (llvm::count(Range&: Match, Element: Match_Unsupported) == 1) {
4451 return Error(L: IDLoc, Msg: "unsupported instruction", Range: EmptyRange,
4452 MatchingInlineAsm);
4453 }
4454
4455 // If one instruction matched with a missing feature, report this as a
4456 // missing feature.
4457 if (llvm::count(Range&: Match, Element: Match_MissingFeature) == 1) {
4458 ErrorInfo = Match_MissingFeature;
4459 return ErrorMissingFeature(IDLoc, MissingFeatures: ErrorInfoMissingFeatures,
4460 MatchingInlineAsm);
4461 }
4462
4463 // If one instruction matched with an invalid operand, report this as an
4464 // operand failure.
4465 if (llvm::count(Range&: Match, Element: Match_InvalidOperand) == 1) {
4466 return Error(L: IDLoc, Msg: "invalid operand for instruction", Range: EmptyRange,
4467 MatchingInlineAsm);
4468 }
4469
4470 // If all of these were an outright failure, report it in a useless way.
4471 Error(L: IDLoc, Msg: "unknown use of instruction mnemonic without a size suffix",
4472 Range: EmptyRange, MatchingInlineAsm);
4473 return true;
4474}
4475
4476bool X86AsmParser::matchAndEmitIntelInstruction(
4477 SMLoc IDLoc, unsigned &Opcode, MCInst &Inst, OperandVector &Operands,
4478 MCStreamer &Out, uint64_t &ErrorInfo, bool MatchingInlineAsm) {
4479 X86Operand &Op = static_cast<X86Operand &>(*Operands[0]);
4480 SMRange EmptyRange = std::nullopt;
4481 // Find one unsized memory operand, if present.
4482 X86Operand *UnsizedMemOp = nullptr;
4483 for (const auto &Op : Operands) {
4484 X86Operand *X86Op = static_cast<X86Operand *>(Op.get());
4485 if (X86Op->isMemUnsized()) {
4486 UnsizedMemOp = X86Op;
4487 // Have we found an unqualified memory operand,
4488 // break. IA allows only one memory operand.
4489 break;
4490 }
4491 }
4492
4493 // Allow some instructions to have implicitly pointer-sized operands. This is
4494 // compatible with gas.
4495 StringRef Mnemonic = (static_cast<X86Operand &>(*Operands[0])).getToken();
4496 if (UnsizedMemOp) {
4497 static const char *const PtrSizedInstrs[] = {"call", "jmp", "push", "pop"};
4498 for (const char *Instr : PtrSizedInstrs) {
4499 if (Mnemonic == Instr) {
4500 UnsizedMemOp->Mem.Size = getPointerWidth();
4501 break;
4502 }
4503 }
4504 }
4505
4506 SmallVector<unsigned, 8> Match;
4507 FeatureBitset ErrorInfoMissingFeatures;
4508 FeatureBitset MissingFeatures;
4509 StringRef Base = (static_cast<X86Operand &>(*Operands[0])).getToken();
4510
4511 // If unsized push has immediate operand we should default the default pointer
4512 // size for the size.
4513 if (Mnemonic == "push" && Operands.size() == 2) {
4514 auto *X86Op = static_cast<X86Operand *>(Operands[1].get());
4515 if (X86Op->isImm()) {
4516 // If it's not a constant fall through and let remainder take care of it.
4517 const auto *CE = dyn_cast<MCConstantExpr>(Val: X86Op->getImm());
4518 unsigned Size = getPointerWidth();
4519 if (CE &&
4520 (isIntN(N: Size, x: CE->getValue()) || isUIntN(N: Size, x: CE->getValue()))) {
4521 SmallString<16> Tmp;
4522 Tmp += Base;
4523 Tmp += (is64BitMode())
4524 ? "q"
4525 : (is32BitMode()) ? "l" : (is16BitMode()) ? "w" : " ";
4526 Op.setTokenValue(Tmp);
4527 // Do match in ATT mode to allow explicit suffix usage.
4528 Match.push_back(Elt: MatchInstruction(Operands, Inst, ErrorInfo,
4529 MissingFeatures, matchingInlineAsm: MatchingInlineAsm,
4530 VariantID: false /*isParsingIntelSyntax()*/));
4531 Op.setTokenValue(Base);
4532 }
4533 }
4534 }
4535
4536 // If an unsized memory operand is present, try to match with each memory
4537 // operand size. In Intel assembly, the size is not part of the instruction
4538 // mnemonic.
4539 if (UnsizedMemOp && UnsizedMemOp->isMemUnsized()) {
4540 static const unsigned MopSizes[] = {8, 16, 32, 64, 80, 128, 256, 512};
4541 for (unsigned Size : MopSizes) {
4542 UnsizedMemOp->Mem.Size = Size;
4543 uint64_t ErrorInfoIgnore;
4544 unsigned LastOpcode = Inst.getOpcode();
4545 unsigned M = MatchInstruction(Operands, Inst, ErrorInfo&: ErrorInfoIgnore,
4546 MissingFeatures, matchingInlineAsm: MatchingInlineAsm,
4547 VariantID: isParsingIntelSyntax());
4548 if (Match.empty() || LastOpcode != Inst.getOpcode())
4549 Match.push_back(Elt: M);
4550
4551 // If this returned as a missing feature failure, remember that.
4552 if (Match.back() == Match_MissingFeature)
4553 ErrorInfoMissingFeatures = MissingFeatures;
4554 }
4555
4556 // Restore the size of the unsized memory operand if we modified it.
4557 UnsizedMemOp->Mem.Size = 0;
4558 }
4559
4560 // If we haven't matched anything yet, this is not a basic integer or FPU
4561 // operation. There shouldn't be any ambiguity in our mnemonic table, so try
4562 // matching with the unsized operand.
4563 if (Match.empty()) {
4564 Match.push_back(Elt: MatchInstruction(
4565 Operands, Inst, ErrorInfo, MissingFeatures, matchingInlineAsm: MatchingInlineAsm,
4566 VariantID: isParsingIntelSyntax()));
4567 // If this returned as a missing feature failure, remember that.
4568 if (Match.back() == Match_MissingFeature)
4569 ErrorInfoMissingFeatures = MissingFeatures;
4570 }
4571
4572 // Restore the size of the unsized memory operand if we modified it.
4573 if (UnsizedMemOp)
4574 UnsizedMemOp->Mem.Size = 0;
4575
4576 // If it's a bad mnemonic, all results will be the same.
4577 if (Match.back() == Match_MnemonicFail) {
4578 return Error(L: IDLoc, Msg: "invalid instruction mnemonic '" + Mnemonic + "'",
4579 Range: Op.getLocRange(), MatchingInlineAsm);
4580 }
4581
4582 unsigned NumSuccessfulMatches = llvm::count(Range&: Match, Element: Match_Success);
4583
4584 // If matching was ambiguous and we had size information from the frontend,
4585 // try again with that. This handles cases like "movxz eax, m8/m16".
4586 if (UnsizedMemOp && NumSuccessfulMatches > 1 &&
4587 UnsizedMemOp->getMemFrontendSize()) {
4588 UnsizedMemOp->Mem.Size = UnsizedMemOp->getMemFrontendSize();
4589 unsigned M = MatchInstruction(
4590 Operands, Inst, ErrorInfo, MissingFeatures, matchingInlineAsm: MatchingInlineAsm,
4591 VariantID: isParsingIntelSyntax());
4592 if (M == Match_Success)
4593 NumSuccessfulMatches = 1;
4594
4595 // Add a rewrite that encodes the size information we used from the
4596 // frontend.
4597 InstInfo->AsmRewrites->emplace_back(
4598 Args: AOK_SizeDirective, Args: UnsizedMemOp->getStartLoc(),
4599 /*Len=*/Args: 0, Args: UnsizedMemOp->getMemFrontendSize());
4600 }
4601
4602 // If exactly one matched, then we treat that as a successful match (and the
4603 // instruction will already have been filled in correctly, since the failing
4604 // matches won't have modified it).
4605 if (NumSuccessfulMatches == 1) {
4606 if (!MatchingInlineAsm && validateInstruction(Inst, Ops: Operands))
4607 return true;
4608 // Some instructions need post-processing to, for example, tweak which
4609 // encoding is selected. Loop on it while changes happen so the individual
4610 // transformations can chain off each other.
4611 if (!MatchingInlineAsm)
4612 while (processInstruction(Inst, Ops: Operands))
4613 ;
4614 Inst.setLoc(IDLoc);
4615 if (!MatchingInlineAsm)
4616 emitInstruction(Inst, Operands, Out);
4617 Opcode = Inst.getOpcode();
4618 return false;
4619 } else if (NumSuccessfulMatches > 1) {
4620 assert(UnsizedMemOp &&
4621 "multiple matches only possible with unsized memory operands");
4622 return Error(L: UnsizedMemOp->getStartLoc(),
4623 Msg: "ambiguous operand size for instruction '" + Mnemonic + "\'",
4624 Range: UnsizedMemOp->getLocRange());
4625 }
4626
4627 // If one instruction matched as unsupported, report this as unsupported.
4628 if (llvm::count(Range&: Match, Element: Match_Unsupported) == 1) {
4629 return Error(L: IDLoc, Msg: "unsupported instruction", Range: EmptyRange,
4630 MatchingInlineAsm);
4631 }
4632
4633 // If one instruction matched with a missing feature, report this as a
4634 // missing feature.
4635 if (llvm::count(Range&: Match, Element: Match_MissingFeature) == 1) {
4636 ErrorInfo = Match_MissingFeature;
4637 return ErrorMissingFeature(IDLoc, MissingFeatures: ErrorInfoMissingFeatures,
4638 MatchingInlineAsm);
4639 }
4640
4641 // If one instruction matched with an invalid operand, report this as an
4642 // operand failure.
4643 if (llvm::count(Range&: Match, Element: Match_InvalidOperand) == 1) {
4644 return Error(L: IDLoc, Msg: "invalid operand for instruction", Range: EmptyRange,
4645 MatchingInlineAsm);
4646 }
4647
4648 if (llvm::count(Range&: Match, Element: Match_InvalidImmUnsignedi4) == 1) {
4649 SMLoc ErrorLoc = ((X86Operand &)*Operands[ErrorInfo]).getStartLoc();
4650 if (ErrorLoc == SMLoc())
4651 ErrorLoc = IDLoc;
4652 return Error(L: ErrorLoc, Msg: "immediate must be an integer in range [0, 15]",
4653 Range: EmptyRange, MatchingInlineAsm);
4654 }
4655
4656 // If all of these were an outright failure, report it in a useless way.
4657 return Error(L: IDLoc, Msg: "unknown instruction mnemonic", Range: EmptyRange,
4658 MatchingInlineAsm);
4659}
4660
4661bool X86AsmParser::omitRegisterFromClobberLists(MCRegister Reg) {
4662 return X86MCRegisterClasses[X86::SEGMENT_REGRegClassID].contains(Reg);
4663}
4664
4665bool X86AsmParser::ParseDirective(AsmToken DirectiveID) {
4666 MCAsmParser &Parser = getParser();
4667 StringRef IDVal = DirectiveID.getIdentifier();
4668 if (IDVal.starts_with(Prefix: ".arch"))
4669 return parseDirectiveArch();
4670 if (IDVal.starts_with(Prefix: ".code"))
4671 return ParseDirectiveCode(IDVal, L: DirectiveID.getLoc());
4672 else if (IDVal.starts_with(Prefix: ".att_syntax")) {
4673 if (getLexer().isNot(K: AsmToken::EndOfStatement)) {
4674 if (Parser.getTok().getString() == "prefix")
4675 Parser.Lex();
4676 else if (Parser.getTok().getString() == "noprefix")
4677 return Error(L: DirectiveID.getLoc(), Msg: "'.att_syntax noprefix' is not "
4678 "supported: registers must have a "
4679 "'%' prefix in .att_syntax");
4680 }
4681 getParser().setAssemblerDialect(0);
4682 return false;
4683 } else if (IDVal.starts_with(Prefix: ".intel_syntax")) {
4684 getParser().setAssemblerDialect(1);
4685 if (getLexer().isNot(K: AsmToken::EndOfStatement)) {
4686 if (Parser.getTok().getString() == "noprefix")
4687 Parser.Lex();
4688 else if (Parser.getTok().getString() == "prefix")
4689 return Error(L: DirectiveID.getLoc(), Msg: "'.intel_syntax prefix' is not "
4690 "supported: registers must not have "
4691 "a '%' prefix in .intel_syntax");
4692 }
4693 return false;
4694 } else if (IDVal == ".nops")
4695 return parseDirectiveNops(L: DirectiveID.getLoc());
4696 else if (IDVal == ".even")
4697 return parseDirectiveEven(L: DirectiveID.getLoc());
4698 else if (IDVal == ".cv_fpo_proc")
4699 return parseDirectiveFPOProc(L: DirectiveID.getLoc());
4700 else if (IDVal == ".cv_fpo_setframe")
4701 return parseDirectiveFPOSetFrame(L: DirectiveID.getLoc());
4702 else if (IDVal == ".cv_fpo_pushreg")
4703 return parseDirectiveFPOPushReg(L: DirectiveID.getLoc());
4704 else if (IDVal == ".cv_fpo_stackalloc")
4705 return parseDirectiveFPOStackAlloc(L: DirectiveID.getLoc());
4706 else if (IDVal == ".cv_fpo_stackalign")
4707 return parseDirectiveFPOStackAlign(L: DirectiveID.getLoc());
4708 else if (IDVal == ".cv_fpo_endprologue")
4709 return parseDirectiveFPOEndPrologue(L: DirectiveID.getLoc());
4710 else if (IDVal == ".cv_fpo_endproc")
4711 return parseDirectiveFPOEndProc(L: DirectiveID.getLoc());
4712 else if (IDVal == ".seh_pushreg" ||
4713 (Parser.isParsingMasm() && IDVal.equals_insensitive(RHS: ".pushreg")))
4714 return parseDirectiveSEHPushReg(DirectiveID.getLoc());
4715 else if (IDVal == ".seh_setframe" ||
4716 (Parser.isParsingMasm() && IDVal.equals_insensitive(RHS: ".setframe")))
4717 return parseDirectiveSEHSetFrame(DirectiveID.getLoc());
4718 else if (IDVal == ".seh_savereg" ||
4719 (Parser.isParsingMasm() && IDVal.equals_insensitive(RHS: ".savereg")))
4720 return parseDirectiveSEHSaveReg(DirectiveID.getLoc());
4721 else if (IDVal == ".seh_savexmm" ||
4722 (Parser.isParsingMasm() && IDVal.equals_insensitive(RHS: ".savexmm128")))
4723 return parseDirectiveSEHSaveXMM(DirectiveID.getLoc());
4724 else if (IDVal == ".seh_pushframe" ||
4725 (Parser.isParsingMasm() && IDVal.equals_insensitive(RHS: ".pushframe")))
4726 return parseDirectiveSEHPushFrame(DirectiveID.getLoc());
4727
4728 return true;
4729}
4730
4731bool X86AsmParser::parseDirectiveArch() {
4732 // Ignore .arch for now.
4733 getParser().parseStringToEndOfStatement();
4734 return false;
4735}
4736
4737/// parseDirectiveNops
4738/// ::= .nops size[, control]
4739bool X86AsmParser::parseDirectiveNops(SMLoc L) {
4740 int64_t NumBytes = 0, Control = 0;
4741 SMLoc NumBytesLoc, ControlLoc;
4742 const MCSubtargetInfo& STI = getSTI();
4743 NumBytesLoc = getTok().getLoc();
4744 if (getParser().checkForValidSection() ||
4745 getParser().parseAbsoluteExpression(Res&: NumBytes))
4746 return true;
4747
4748 if (parseOptionalToken(T: AsmToken::Comma)) {
4749 ControlLoc = getTok().getLoc();
4750 if (getParser().parseAbsoluteExpression(Res&: Control))
4751 return true;
4752 }
4753 if (getParser().parseEOL())
4754 return true;
4755
4756 if (NumBytes <= 0) {
4757 Error(L: NumBytesLoc, Msg: "'.nops' directive with non-positive size");
4758 return false;
4759 }
4760
4761 if (Control < 0) {
4762 Error(L: ControlLoc, Msg: "'.nops' directive with negative NOP size");
4763 return false;
4764 }
4765
4766 /// Emit nops
4767 getParser().getStreamer().emitNops(NumBytes, ControlledNopLength: Control, Loc: L, STI);
4768
4769 return false;
4770}
4771
4772/// parseDirectiveEven
4773/// ::= .even
4774bool X86AsmParser::parseDirectiveEven(SMLoc L) {
4775 if (parseEOL())
4776 return false;
4777
4778 const MCSection *Section = getStreamer().getCurrentSectionOnly();
4779 if (!Section) {
4780 getStreamer().initSections(NoExecStack: false, STI: getSTI());
4781 Section = getStreamer().getCurrentSectionOnly();
4782 }
4783 if (Section->useCodeAlign())
4784 getStreamer().emitCodeAlignment(Alignment: Align(2), STI: &getSTI(), MaxBytesToEmit: 0);
4785 else
4786 getStreamer().emitValueToAlignment(Alignment: Align(2), Value: 0, ValueSize: 1, MaxBytesToEmit: 0);
4787 return false;
4788}
4789
4790/// ParseDirectiveCode
4791/// ::= .code16 | .code32 | .code64
4792bool X86AsmParser::ParseDirectiveCode(StringRef IDVal, SMLoc L) {
4793 MCAsmParser &Parser = getParser();
4794 Code16GCC = false;
4795 if (IDVal == ".code16") {
4796 Parser.Lex();
4797 if (!is16BitMode()) {
4798 SwitchMode(mode: X86::Is16Bit);
4799 getTargetStreamer().emitCode16();
4800 }
4801 } else if (IDVal == ".code16gcc") {
4802 // .code16gcc parses as if in 32-bit mode, but emits code in 16-bit mode.
4803 Parser.Lex();
4804 Code16GCC = true;
4805 if (!is16BitMode()) {
4806 SwitchMode(mode: X86::Is16Bit);
4807 getTargetStreamer().emitCode16();
4808 }
4809 } else if (IDVal == ".code32") {
4810 Parser.Lex();
4811 if (!is32BitMode()) {
4812 SwitchMode(mode: X86::Is32Bit);
4813 getTargetStreamer().emitCode32();
4814 }
4815 } else if (IDVal == ".code64") {
4816 Parser.Lex();
4817 if (!is64BitMode()) {
4818 SwitchMode(mode: X86::Is64Bit);
4819 getTargetStreamer().emitCode64();
4820 }
4821 } else {
4822 Error(L, Msg: "unknown directive " + IDVal);
4823 return false;
4824 }
4825
4826 return false;
4827}
4828
4829// .cv_fpo_proc foo
4830bool X86AsmParser::parseDirectiveFPOProc(SMLoc L) {
4831 MCAsmParser &Parser = getParser();
4832 StringRef ProcName;
4833 int64_t ParamsSize;
4834 if (Parser.parseIdentifier(Res&: ProcName))
4835 return Parser.TokError(Msg: "expected symbol name");
4836 if (Parser.parseIntToken(V&: ParamsSize, ErrMsg: "expected parameter byte count"))
4837 return true;
4838 if (!isUIntN(N: 32, x: ParamsSize))
4839 return Parser.TokError(Msg: "parameters size out of range");
4840 if (parseEOL())
4841 return true;
4842 MCSymbol *ProcSym = getContext().getOrCreateSymbol(Name: ProcName);
4843 return getTargetStreamer().emitFPOProc(ProcSym, ParamsSize, L);
4844}
4845
4846// .cv_fpo_setframe ebp
4847bool X86AsmParser::parseDirectiveFPOSetFrame(SMLoc L) {
4848 MCRegister Reg;
4849 SMLoc DummyLoc;
4850 if (parseRegister(Reg, StartLoc&: DummyLoc, EndLoc&: DummyLoc) || parseEOL())
4851 return true;
4852 return getTargetStreamer().emitFPOSetFrame(Reg, L);
4853}
4854
4855// .cv_fpo_pushreg ebx
4856bool X86AsmParser::parseDirectiveFPOPushReg(SMLoc L) {
4857 MCRegister Reg;
4858 SMLoc DummyLoc;
4859 if (parseRegister(Reg, StartLoc&: DummyLoc, EndLoc&: DummyLoc) || parseEOL())
4860 return true;
4861 return getTargetStreamer().emitFPOPushReg(Reg, L);
4862}
4863
4864// .cv_fpo_stackalloc 20
4865bool X86AsmParser::parseDirectiveFPOStackAlloc(SMLoc L) {
4866 MCAsmParser &Parser = getParser();
4867 int64_t Offset;
4868 if (Parser.parseIntToken(V&: Offset, ErrMsg: "expected offset") || parseEOL())
4869 return true;
4870 return getTargetStreamer().emitFPOStackAlloc(StackAlloc: Offset, L);
4871}
4872
4873// .cv_fpo_stackalign 8
4874bool X86AsmParser::parseDirectiveFPOStackAlign(SMLoc L) {
4875 MCAsmParser &Parser = getParser();
4876 int64_t Offset;
4877 if (Parser.parseIntToken(V&: Offset, ErrMsg: "expected offset") || parseEOL())
4878 return true;
4879 return getTargetStreamer().emitFPOStackAlign(Align: Offset, L);
4880}
4881
4882// .cv_fpo_endprologue
4883bool X86AsmParser::parseDirectiveFPOEndPrologue(SMLoc L) {
4884 MCAsmParser &Parser = getParser();
4885 if (Parser.parseEOL())
4886 return true;
4887 return getTargetStreamer().emitFPOEndPrologue(L);
4888}
4889
4890// .cv_fpo_endproc
4891bool X86AsmParser::parseDirectiveFPOEndProc(SMLoc L) {
4892 MCAsmParser &Parser = getParser();
4893 if (Parser.parseEOL())
4894 return true;
4895 return getTargetStreamer().emitFPOEndProc(L);
4896}
4897
4898bool X86AsmParser::parseSEHRegisterNumber(unsigned RegClassID,
4899 MCRegister &RegNo) {
4900 SMLoc startLoc = getLexer().getLoc();
4901 const MCRegisterInfo *MRI = getContext().getRegisterInfo();
4902
4903 // Try parsing the argument as a register first.
4904 if (getLexer().getTok().isNot(K: AsmToken::Integer)) {
4905 SMLoc endLoc;
4906 if (parseRegister(Reg&: RegNo, StartLoc&: startLoc, EndLoc&: endLoc))
4907 return true;
4908
4909 if (!X86MCRegisterClasses[RegClassID].contains(Reg: RegNo)) {
4910 return Error(L: startLoc,
4911 Msg: "register is not supported for use with this directive");
4912 }
4913 } else {
4914 // Otherwise, an integer number matching the encoding of the desired
4915 // register may appear.
4916 int64_t EncodedReg;
4917 if (getParser().parseAbsoluteExpression(Res&: EncodedReg))
4918 return true;
4919
4920 // The SEH register number is the same as the encoding register number. Map
4921 // from the encoding back to the LLVM register number.
4922 RegNo = MCRegister();
4923 for (MCPhysReg Reg : X86MCRegisterClasses[RegClassID]) {
4924 if (MRI->getEncodingValue(Reg) == EncodedReg) {
4925 RegNo = Reg;
4926 break;
4927 }
4928 }
4929 if (!RegNo) {
4930 return Error(L: startLoc,
4931 Msg: "incorrect register number for use with this directive");
4932 }
4933 }
4934
4935 return false;
4936}
4937
4938bool X86AsmParser::parseDirectiveSEHPushReg(SMLoc Loc) {
4939 MCRegister Reg;
4940 if (parseSEHRegisterNumber(RegClassID: X86::GR64RegClassID, RegNo&: Reg))
4941 return true;
4942
4943 if (getLexer().isNot(K: AsmToken::EndOfStatement))
4944 return TokError(Msg: "expected end of directive");
4945
4946 getParser().Lex();
4947 getStreamer().emitWinCFIPushReg(Register: Reg, Loc);
4948 return false;
4949}
4950
4951bool X86AsmParser::parseDirectiveSEHSetFrame(SMLoc Loc) {
4952 MCRegister Reg;
4953 int64_t Off;
4954 if (parseSEHRegisterNumber(RegClassID: X86::GR64RegClassID, RegNo&: Reg))
4955 return true;
4956 if (getLexer().isNot(K: AsmToken::Comma))
4957 return TokError(Msg: "you must specify a stack pointer offset");
4958
4959 getParser().Lex();
4960 if (getParser().parseAbsoluteExpression(Res&: Off))
4961 return true;
4962
4963 if (getLexer().isNot(K: AsmToken::EndOfStatement))
4964 return TokError(Msg: "expected end of directive");
4965
4966 getParser().Lex();
4967 getStreamer().emitWinCFISetFrame(Register: Reg, Offset: Off, Loc);
4968 return false;
4969}
4970
4971bool X86AsmParser::parseDirectiveSEHSaveReg(SMLoc Loc) {
4972 MCRegister Reg;
4973 int64_t Off;
4974 if (parseSEHRegisterNumber(RegClassID: X86::GR64RegClassID, RegNo&: Reg))
4975 return true;
4976 if (getLexer().isNot(K: AsmToken::Comma))
4977 return TokError(Msg: "you must specify an offset on the stack");
4978
4979 getParser().Lex();
4980 if (getParser().parseAbsoluteExpression(Res&: Off))
4981 return true;
4982
4983 if (getLexer().isNot(K: AsmToken::EndOfStatement))
4984 return TokError(Msg: "expected end of directive");
4985
4986 getParser().Lex();
4987 getStreamer().emitWinCFISaveReg(Register: Reg, Offset: Off, Loc);
4988 return false;
4989}
4990
4991bool X86AsmParser::parseDirectiveSEHSaveXMM(SMLoc Loc) {
4992 MCRegister Reg;
4993 int64_t Off;
4994 if (parseSEHRegisterNumber(RegClassID: X86::VR128XRegClassID, RegNo&: Reg))
4995 return true;
4996 if (getLexer().isNot(K: AsmToken::Comma))
4997 return TokError(Msg: "you must specify an offset on the stack");
4998
4999 getParser().Lex();
5000 if (getParser().parseAbsoluteExpression(Res&: Off))
5001 return true;
5002
5003 if (getLexer().isNot(K: AsmToken::EndOfStatement))
5004 return TokError(Msg: "expected end of directive");
5005
5006 getParser().Lex();
5007 getStreamer().emitWinCFISaveXMM(Register: Reg, Offset: Off, Loc);
5008 return false;
5009}
5010
5011bool X86AsmParser::parseDirectiveSEHPushFrame(SMLoc Loc) {
5012 bool Code = false;
5013 StringRef CodeID;
5014 if (getLexer().is(K: AsmToken::At)) {
5015 SMLoc startLoc = getLexer().getLoc();
5016 getParser().Lex();
5017 if (!getParser().parseIdentifier(Res&: CodeID)) {
5018 if (CodeID != "code")
5019 return Error(L: startLoc, Msg: "expected @code");
5020 Code = true;
5021 }
5022 }
5023
5024 if (getLexer().isNot(K: AsmToken::EndOfStatement))
5025 return TokError(Msg: "expected end of directive");
5026
5027 getParser().Lex();
5028 getStreamer().emitWinCFIPushFrame(Code, Loc);
5029 return false;
5030}
5031
5032// Force static initialization.
5033extern "C" LLVM_C_ABI void LLVMInitializeX86AsmParser() {
5034 RegisterMCAsmParser<X86AsmParser> X(getTheX86_32Target());
5035 RegisterMCAsmParser<X86AsmParser> Y(getTheX86_64Target());
5036}
5037
5038#define GET_MATCHER_IMPLEMENTATION
5039#include "X86GenAsmMatcher.inc"
5040