1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* X86 Mnemonic tables *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10namespace X86 {
11
12#ifdef GET_X86_MNEMONIC_TABLES_H
13#undef GET_X86_MNEMONIC_TABLES_H
14
15bool isFSUBRP(unsigned Opcode);
16bool isVPDPBUSDS(unsigned Opcode);
17bool isPUNPCKLWD(unsigned Opcode);
18bool isVREDUCEBF16(unsigned Opcode);
19bool isPUNPCKLQDQ(unsigned Opcode);
20bool isRDFSBASE(unsigned Opcode);
21bool isVPCMOV(unsigned Opcode);
22bool isVDIVSD(unsigned Opcode);
23bool isVCVTTPS2IBS(unsigned Opcode);
24bool isVPEXTRW(unsigned Opcode);
25bool isLODSD(unsigned Opcode);
26bool isVPTESTNMQ(unsigned Opcode);
27bool isCVTSS2SD(unsigned Opcode);
28bool isVGETMANTPD(unsigned Opcode);
29bool isVMOVDQA64(unsigned Opcode);
30bool isINVLPG(unsigned Opcode);
31bool isVGETEXPBF16(unsigned Opcode);
32bool isVBROADCASTF64X4(unsigned Opcode);
33bool isVPERMI2Q(unsigned Opcode);
34bool isVPMOVSXBD(unsigned Opcode);
35bool isVFMSUB132SS(unsigned Opcode);
36bool isVPMOVUSDW(unsigned Opcode);
37bool isAAD(unsigned Opcode);
38bool isIDIV(unsigned Opcode);
39bool isCVTTPS2DQ(unsigned Opcode);
40bool isVBROADCASTF32X8(unsigned Opcode);
41bool isVFMSUBSS(unsigned Opcode);
42bool isEMMS(unsigned Opcode);
43bool isVPDPBSUD(unsigned Opcode);
44bool isPMOVSXWQ(unsigned Opcode);
45bool isPSRLW(unsigned Opcode);
46bool isMOVNTDQA(unsigned Opcode);
47bool isFUCOMPI(unsigned Opcode);
48bool isANDNPS(unsigned Opcode);
49bool isVINSERTF64X2(unsigned Opcode);
50bool isCLTS(unsigned Opcode);
51bool isSETSSBSY(unsigned Opcode);
52bool isVMULPD(unsigned Opcode);
53bool isVFMADDSUB132PS(unsigned Opcode);
54bool isVPMADCSWD(unsigned Opcode);
55bool isVSCATTERPF0DPS(unsigned Opcode);
56bool isXCHG(unsigned Opcode);
57bool isVGATHERPF1QPS(unsigned Opcode);
58bool isVCVTNEPS2BF16(unsigned Opcode);
59bool isVFMADDSS(unsigned Opcode);
60bool isINTO(unsigned Opcode);
61bool isANDPD(unsigned Opcode);
62bool isSEAMCALL(unsigned Opcode);
63bool isVPDPBSSDS(unsigned Opcode);
64bool isUNPCKHPS(unsigned Opcode);
65bool isSETZUCC(unsigned Opcode);
66bool isSHUFPD(unsigned Opcode);
67bool isFCMOVNB(unsigned Opcode);
68bool isCVTTSS2SI(unsigned Opcode);
69bool isEXTRQ(unsigned Opcode);
70bool isSHLD(unsigned Opcode);
71bool isVBROADCASTSS(unsigned Opcode);
72bool isCLUI(unsigned Opcode);
73bool isVINSERTI128(unsigned Opcode);
74bool isVBLENDPD(unsigned Opcode);
75bool isVPSHLDW(unsigned Opcode);
76bool isT2RPNTLVWZ0T1(unsigned Opcode);
77bool isVCVTNEEPH2PS(unsigned Opcode);
78bool isVCVTTSD2SI(unsigned Opcode);
79bool isVSM4KEY4(unsigned Opcode);
80bool isWRMSRNS(unsigned Opcode);
81bool isCMPSB(unsigned Opcode);
82bool isVRCPBF16(unsigned Opcode);
83bool isMULSS(unsigned Opcode);
84bool isVMRUN(unsigned Opcode);
85bool isVPSRLVD(unsigned Opcode);
86bool isLEAVE(unsigned Opcode);
87bool isVGETMANTPS(unsigned Opcode);
88bool isXSHA256(unsigned Opcode);
89bool isTCONJTFP16(unsigned Opcode);
90bool isBOUND(unsigned Opcode);
91bool isSFENCE(unsigned Opcode);
92bool isVPHADDD(unsigned Opcode);
93bool isADOX(unsigned Opcode);
94bool isVPSLLQ(unsigned Opcode);
95bool isVCVTPH2HF8(unsigned Opcode);
96bool isPFRSQIT1(unsigned Opcode);
97bool isCLAC(unsigned Opcode);
98bool isKNOTW(unsigned Opcode);
99bool isVCVTPH2PD(unsigned Opcode);
100bool isVAESENC(unsigned Opcode);
101bool isMOVNTI(unsigned Opcode);
102bool isFXCH(unsigned Opcode);
103bool isPOPP(unsigned Opcode);
104bool isVPBLENDMD(unsigned Opcode);
105bool isFSINCOS(unsigned Opcode);
106bool isVPMULLW(unsigned Opcode);
107bool isVPMOVSXBW(unsigned Opcode);
108bool isSTC(unsigned Opcode);
109bool isVPINSRB(unsigned Opcode);
110bool isLWPVAL(unsigned Opcode);
111bool isKXORB(unsigned Opcode);
112bool isRSTORSSP(unsigned Opcode);
113bool isVPRORQ(unsigned Opcode);
114bool isVSM3MSG1(unsigned Opcode);
115bool isFICOM(unsigned Opcode);
116bool isMAXPS(unsigned Opcode);
117bool isFNCLEX(unsigned Opcode);
118bool isVMOVMSKPS(unsigned Opcode);
119bool isVPMOVDB(unsigned Opcode);
120bool isLLWPCB(unsigned Opcode);
121bool isVMULSS(unsigned Opcode);
122bool isAESENCLAST(unsigned Opcode);
123bool isTILEMOVROW(unsigned Opcode);
124bool isVMINMAXPH(unsigned Opcode);
125bool isVPMAXUB(unsigned Opcode);
126bool isAAS(unsigned Opcode);
127bool isFADD(unsigned Opcode);
128bool isJMP(unsigned Opcode);
129bool isXCRYPTECB(unsigned Opcode);
130bool isPFRCPIT1(unsigned Opcode);
131bool isPMULHRW(unsigned Opcode);
132bool isVCVTPH2PS(unsigned Opcode);
133bool isVPBLENDVB(unsigned Opcode);
134bool isPCMPESTRI(unsigned Opcode);
135bool isSENDUIPI(unsigned Opcode);
136bool isFLDLN2(unsigned Opcode);
137bool isVPMACSWD(unsigned Opcode);
138bool isSHA1MSG1(unsigned Opcode);
139bool isVADDPS(unsigned Opcode);
140bool isVCVTPS2DQ(unsigned Opcode);
141bool isPFPNACC(unsigned Opcode);
142bool isFMUL(unsigned Opcode);
143bool isFNSAVE(unsigned Opcode);
144bool isCDQE(unsigned Opcode);
145bool isVPMACSDD(unsigned Opcode);
146bool isVSQRTPS(unsigned Opcode);
147bool isCMPSQ(unsigned Opcode);
148bool isVPSCATTERDD(unsigned Opcode);
149bool isVCVTTSD2USIS(unsigned Opcode);
150bool isVRNDSCALESD(unsigned Opcode);
151bool isSUBPS(unsigned Opcode);
152bool isVMAXSH(unsigned Opcode);
153bool isFLDZ(unsigned Opcode);
154bool isVFNMADD132SS(unsigned Opcode);
155bool isLGDTW(unsigned Opcode);
156bool isTCVTROWPS2PHH(unsigned Opcode);
157bool isINC(unsigned Opcode);
158bool isVPANDN(unsigned Opcode);
159bool isPABSB(unsigned Opcode);
160bool isVSHA512RNDS2(unsigned Opcode);
161bool isPHADDSW(unsigned Opcode);
162bool isVPMAXUD(unsigned Opcode);
163bool isVPMOVSQW(unsigned Opcode);
164bool isADDSUBPS(unsigned Opcode);
165bool isVPMACSSDQL(unsigned Opcode);
166bool isPXOR(unsigned Opcode);
167bool isVPSRAD(unsigned Opcode);
168bool isVPSHAB(unsigned Opcode);
169bool isBTR(unsigned Opcode);
170bool isKORW(unsigned Opcode);
171bool isVRANGESS(unsigned Opcode);
172bool isVCMPPS(unsigned Opcode);
173bool isVPLZCNTD(unsigned Opcode);
174bool isTDPBUUD(unsigned Opcode);
175bool isROUNDPS(unsigned Opcode);
176bool isFABS(unsigned Opcode);
177bool isSUBPD(unsigned Opcode);
178bool isGF2P8MULB(unsigned Opcode);
179bool isTZMSK(unsigned Opcode);
180bool isVMINMAXSD(unsigned Opcode);
181bool isANDPS(unsigned Opcode);
182bool isVEXTRACTF32X8(unsigned Opcode);
183bool isSEAMRET(unsigned Opcode);
184bool isVPCOMW(unsigned Opcode);
185bool isVFIXUPIMMPD(unsigned Opcode);
186bool isKANDND(unsigned Opcode);
187bool isVMRESUME(unsigned Opcode);
188bool isCVTPD2DQ(unsigned Opcode);
189bool isVFNMADD213PS(unsigned Opcode);
190bool isVPEXTRD(unsigned Opcode);
191bool isPACKUSWB(unsigned Opcode);
192bool isVEXTRACTI32X8(unsigned Opcode);
193bool isVHADDPD(unsigned Opcode);
194bool isVPSADBW(unsigned Opcode);
195bool isMOVDQ2Q(unsigned Opcode);
196bool isPUNPCKHBW(unsigned Opcode);
197bool isXOR(unsigned Opcode);
198bool isPSIGNB(unsigned Opcode);
199bool isVPHADDSW(unsigned Opcode);
200bool isFADDP(unsigned Opcode);
201bool isNEG(unsigned Opcode);
202bool isFLDLG2(unsigned Opcode);
203bool isFNOP(unsigned Opcode);
204bool isVMINSS(unsigned Opcode);
205bool isPCMPISTRM(unsigned Opcode);
206bool isVFMADD132SS(unsigned Opcode);
207bool isFDIVRP(unsigned Opcode);
208bool isPUSHAL(unsigned Opcode);
209bool isVPMACSDQL(unsigned Opcode);
210bool isSUBSD(unsigned Opcode);
211bool isVPBLENDMQ(unsigned Opcode);
212bool isVGATHERDPS(unsigned Opcode);
213bool isSYSRET(unsigned Opcode);
214bool isVPADDB(unsigned Opcode);
215bool isXEND(unsigned Opcode);
216bool isWRSSD(unsigned Opcode);
217bool isVMINMAXSS(unsigned Opcode);
218bool isVCVTDQ2PH(unsigned Opcode);
219bool isCVTPD2PS(unsigned Opcode);
220bool isMAXPD(unsigned Opcode);
221bool isRCPSS(unsigned Opcode);
222bool isVMOVAPD(unsigned Opcode);
223bool isVPSUBSB(unsigned Opcode);
224bool isRDTSC(unsigned Opcode);
225bool isVCVTTPS2UDQS(unsigned Opcode);
226bool isVPMADCSSWD(unsigned Opcode);
227bool isVFNMADD213PH(unsigned Opcode);
228bool isVGF2P8AFFINEQB(unsigned Opcode);
229bool isPMOVZXWD(unsigned Opcode);
230bool isPMINUD(unsigned Opcode);
231bool isVCVTPH2UW(unsigned Opcode);
232bool isPADDSW(unsigned Opcode);
233bool isXSUSLDTRK(unsigned Opcode);
234bool isLFENCE(unsigned Opcode);
235bool isCRC32(unsigned Opcode);
236bool isAESENCWIDE256KL(unsigned Opcode);
237bool isMOVAPD(unsigned Opcode);
238bool isVFMADD213PS(unsigned Opcode);
239bool isVPDPWUUDS(unsigned Opcode);
240bool isMOVSLDUP(unsigned Opcode);
241bool isCLDEMOTE(unsigned Opcode);
242bool isVFNMADD231PS(unsigned Opcode);
243bool isVMOVMSKPD(unsigned Opcode);
244bool isPREFETCHT0(unsigned Opcode);
245bool isVCVTNEOBF162PS(unsigned Opcode);
246bool isVPCMPUD(unsigned Opcode);
247bool isVMAXSD(unsigned Opcode);
248bool isVRCP28SD(unsigned Opcode);
249bool isVMAXPS(unsigned Opcode);
250bool isVPMOVD2M(unsigned Opcode);
251bool isVPMACSSWD(unsigned Opcode);
252bool isVUCOMISD(unsigned Opcode);
253bool isLTR(unsigned Opcode);
254bool isVCVTUSI2SH(unsigned Opcode);
255bool isVSCATTERPF1QPS(unsigned Opcode);
256bool isWRGSBASE(unsigned Opcode);
257bool isSTOSQ(unsigned Opcode);
258bool isVSQRTSD(unsigned Opcode);
259bool isVPERMIL2PD(unsigned Opcode);
260bool isT2RPNTLVWZ1RST1(unsigned Opcode);
261bool isVFCMADDCSH(unsigned Opcode);
262bool isVFMADDSUB213PS(unsigned Opcode);
263bool isPFSUB(unsigned Opcode);
264bool isVSQRTSS(unsigned Opcode);
265bool isVEXPANDPS(unsigned Opcode);
266bool isVPCOMPRESSW(unsigned Opcode);
267bool isPEXTRD(unsigned Opcode);
268bool isVCVTTPS2UQQS(unsigned Opcode);
269bool isSYSEXITQ(unsigned Opcode);
270bool isROUNDSD(unsigned Opcode);
271bool isVFMADD132BF16(unsigned Opcode);
272bool isFCOM(unsigned Opcode);
273bool isVFNMSUBSS(unsigned Opcode);
274bool isKSHIFTLW(unsigned Opcode);
275bool isSCASD(unsigned Opcode);
276bool isVMPTRLD(unsigned Opcode);
277bool isVAESDECLAST(unsigned Opcode);
278bool isVFMADDSUBPS(unsigned Opcode);
279bool isVCVTUQQ2PS(unsigned Opcode);
280bool isVPMOVUSDB(unsigned Opcode);
281bool isVPROTW(unsigned Opcode);
282bool isVDPPS(unsigned Opcode);
283bool isVRSQRT14PD(unsigned Opcode);
284bool isVTESTPD(unsigned Opcode);
285bool isVFNMADD231SH(unsigned Opcode);
286bool isENDBR64(unsigned Opcode);
287bool isMULSD(unsigned Opcode);
288bool isXRSTORS(unsigned Opcode);
289bool isPREFETCHNTA(unsigned Opcode);
290bool isVPCOMD(unsigned Opcode);
291bool isVPCOMUB(unsigned Opcode);
292bool isVPHSUBD(unsigned Opcode);
293bool isVBROADCASTI64X2(unsigned Opcode);
294bool isFPATAN(unsigned Opcode);
295bool isLOOPE(unsigned Opcode);
296bool isPCMPEQW(unsigned Opcode);
297bool isVFMADDCSH(unsigned Opcode);
298bool isVPDPBSSD(unsigned Opcode);
299bool isMOVRS(unsigned Opcode);
300bool isVFMSUBADD132PH(unsigned Opcode);
301bool isKADDW(unsigned Opcode);
302bool isPTEST(unsigned Opcode);
303bool isVRSQRT28PS(unsigned Opcode);
304bool isVGF2P8AFFINEINVQB(unsigned Opcode);
305bool isSERIALIZE(unsigned Opcode);
306bool isVPHADDWQ(unsigned Opcode);
307bool isVRNDSCALESH(unsigned Opcode);
308bool isAAA(unsigned Opcode);
309bool isVADDBF16(unsigned Opcode);
310bool isWRMSRLIST(unsigned Opcode);
311bool isVCVTPH2PSX(unsigned Opcode);
312bool isVFMSUB231PH(unsigned Opcode);
313bool isVGATHERQPD(unsigned Opcode);
314bool isKADDB(unsigned Opcode);
315bool isCVTPD2PI(unsigned Opcode);
316bool isVFNMSUB213PH(unsigned Opcode);
317bool isXORPS(unsigned Opcode);
318bool isVPCMPESTRI(unsigned Opcode);
319bool isVPADDSB(unsigned Opcode);
320bool isPOP2(unsigned Opcode);
321bool isRDMSRLIST(unsigned Opcode);
322bool isVPSHRDW(unsigned Opcode);
323bool isVPDPBUSD(unsigned Opcode);
324bool isVCMPPH(unsigned Opcode);
325bool isVANDNPD(unsigned Opcode);
326bool isSUB(unsigned Opcode);
327bool isVRSQRT28PD(unsigned Opcode);
328bool isVFNMADD132PH(unsigned Opcode);
329bool isVPMACSSWW(unsigned Opcode);
330bool isXSTORE(unsigned Opcode);
331bool isVPROTQ(unsigned Opcode);
332bool isVPHADDBD(unsigned Opcode);
333bool isVPMAXSB(unsigned Opcode);
334bool isVMOVDQU8(unsigned Opcode);
335bool isVPMOVSXWD(unsigned Opcode);
336bool isVMINMAXPD(unsigned Opcode);
337bool isSHA256RNDS2(unsigned Opcode);
338bool isKANDB(unsigned Opcode);
339bool isTPAUSE(unsigned Opcode);
340bool isPUSH(unsigned Opcode);
341bool isVRNDSCALESS(unsigned Opcode);
342bool isVRNDSCALEBF16(unsigned Opcode);
343bool isVPCMPISTRI(unsigned Opcode);
344bool isSTGI(unsigned Opcode);
345bool isSBB(unsigned Opcode);
346bool isBLCS(unsigned Opcode);
347bool isVCVTSD2SH(unsigned Opcode);
348bool isVPERMW(unsigned Opcode);
349bool isXRESLDTRK(unsigned Opcode);
350bool isAESENC256KL(unsigned Opcode);
351bool isVGATHERDPD(unsigned Opcode);
352bool isHRESET(unsigned Opcode);
353bool isVFMSUBADD231PD(unsigned Opcode);
354bool isVFRCZSS(unsigned Opcode);
355bool isMINPS(unsigned Opcode);
356bool isFPREM1(unsigned Opcode);
357bool isVPCMPUB(unsigned Opcode);
358bool isVSQRTPD(unsigned Opcode);
359bool isVFRCZPS(unsigned Opcode);
360bool isVFNMADD213SS(unsigned Opcode);
361bool isVPMOVDW(unsigned Opcode);
362bool isVCVTPH2HF8S(unsigned Opcode);
363bool isVPSHRDVQ(unsigned Opcode);
364bool isVBROADCASTSD(unsigned Opcode);
365bool isVSHUFPD(unsigned Opcode);
366bool isVPSUBSW(unsigned Opcode);
367bool isKUNPCKBW(unsigned Opcode);
368bool isVPBLENDD(unsigned Opcode);
369bool isUNPCKHPD(unsigned Opcode);
370bool isVFNMADD231SD(unsigned Opcode);
371bool isVPBROADCASTMW2D(unsigned Opcode);
372bool isVPMULTISHIFTQB(unsigned Opcode);
373bool isVP2INTERSECTQ(unsigned Opcode);
374bool isVFNMSUB132BF16(unsigned Opcode);
375bool isTTCMMIMFP16PS(unsigned Opcode);
376bool isVFMADD213BF16(unsigned Opcode);
377bool isVPUNPCKHWD(unsigned Opcode);
378bool isVPERM2F128(unsigned Opcode);
379bool isINSD(unsigned Opcode);
380bool isLFS(unsigned Opcode);
381bool isFMULP(unsigned Opcode);
382bool isCWD(unsigned Opcode);
383bool isVDIVSS(unsigned Opcode);
384bool isVPSRLQ(unsigned Opcode);
385bool isFSQRT(unsigned Opcode);
386bool isJRCXZ(unsigned Opcode);
387bool isVPMOVMSKB(unsigned Opcode);
388bool isAESDEC256KL(unsigned Opcode);
389bool isFLDENV(unsigned Opcode);
390bool isVPHSUBWD(unsigned Opcode);
391bool isWBNOINVD(unsigned Opcode);
392bool isVEXPANDPD(unsigned Opcode);
393bool isFYL2XP1(unsigned Opcode);
394bool isPREFETCHT2(unsigned Opcode);
395bool isVPDPBSUDS(unsigned Opcode);
396bool isVSHA512MSG2(unsigned Opcode);
397bool isPMULHUW(unsigned Opcode);
398bool isKANDNB(unsigned Opcode);
399bool isVCVTUW2PH(unsigned Opcode);
400bool isAESDECWIDE256KL(unsigned Opcode);
401bool isVPGATHERDD(unsigned Opcode);
402bool isVREDUCESH(unsigned Opcode);
403bool isPOPFQ(unsigned Opcode);
404bool isPAVGUSB(unsigned Opcode);
405bool isVALIGND(unsigned Opcode);
406bool isVPHMINPOSUW(unsigned Opcode);
407bool isLIDTD(unsigned Opcode);
408bool isVPERMT2PD(unsigned Opcode);
409bool isVMLAUNCH(unsigned Opcode);
410bool isVPXORQ(unsigned Opcode);
411bool isMOVNTDQ(unsigned Opcode);
412bool isPOP2P(unsigned Opcode);
413bool isVADDPD(unsigned Opcode);
414bool isSMSW(unsigned Opcode);
415bool isVEXP2PD(unsigned Opcode);
416bool isPMULUDQ(unsigned Opcode);
417bool isIRET(unsigned Opcode);
418bool isMULPS(unsigned Opcode);
419bool isTDPBF8PS(unsigned Opcode);
420bool isVFNMSUBPD(unsigned Opcode);
421bool isPHADDW(unsigned Opcode);
422bool isRDSEED(unsigned Opcode);
423bool isVPSHLW(unsigned Opcode);
424bool isRMPUPDATE(unsigned Opcode);
425bool isVFMADD231PH(unsigned Opcode);
426bool isVPSHAD(unsigned Opcode);
427bool isCLWB(unsigned Opcode);
428bool isPSUBUSB(unsigned Opcode);
429bool isVCVTTSD2USI(unsigned Opcode);
430bool isVEXTRACTPS(unsigned Opcode);
431bool isMOVLPD(unsigned Opcode);
432bool isLGDTD(unsigned Opcode);
433bool isVPBROADCASTMB2Q(unsigned Opcode);
434bool isOUT(unsigned Opcode);
435bool isVMSAVE(unsigned Opcode);
436bool isVCVTQQ2PD(unsigned Opcode);
437bool isVFMADD213PH(unsigned Opcode);
438bool isFCMOVBE(unsigned Opcode);
439bool isMOVSHDUP(unsigned Opcode);
440bool isVPMOVUSQB(unsigned Opcode);
441bool isFIST(unsigned Opcode);
442bool isHADDPD(unsigned Opcode);
443bool isPACKSSWB(unsigned Opcode);
444bool isVPMACSSDQH(unsigned Opcode);
445bool isVFNMSUB132SD(unsigned Opcode);
446bool isVPMASKMOVQ(unsigned Opcode);
447bool isVCOMPRESSPD(unsigned Opcode);
448bool isVFMADD213SS(unsigned Opcode);
449bool isVPCMPQ(unsigned Opcode);
450bool isVADDSH(unsigned Opcode);
451bool isVFNMADDSD(unsigned Opcode);
452bool isUMWAIT(unsigned Opcode);
453bool isVPUNPCKHDQ(unsigned Opcode);
454bool isLCALL(unsigned Opcode);
455bool isAESDEC128KL(unsigned Opcode);
456bool isVSUBPS(unsigned Opcode);
457bool isFSTP(unsigned Opcode);
458bool isVCVTUDQ2PD(unsigned Opcode);
459bool isVPMOVSWB(unsigned Opcode);
460bool isVPANDNQ(unsigned Opcode);
461bool isSYSENTER(unsigned Opcode);
462bool isVPHADDWD(unsigned Opcode);
463bool isVMOVHPD(unsigned Opcode);
464bool isMOVHPD(unsigned Opcode);
465bool isVDIVPH(unsigned Opcode);
466bool isFFREE(unsigned Opcode);
467bool isVGATHERPF1DPS(unsigned Opcode);
468bool isVFNMADD231PD(unsigned Opcode);
469bool isVFCMULCPH(unsigned Opcode);
470bool isVPADDD(unsigned Opcode);
471bool isVSM3MSG2(unsigned Opcode);
472bool isVPCOMUQ(unsigned Opcode);
473bool isVERR(unsigned Opcode);
474bool isKORTESTQ(unsigned Opcode);
475bool isVFMSUB132SD(unsigned Opcode);
476bool isTILEZERO(unsigned Opcode);
477bool isPFADD(unsigned Opcode);
478bool isVCVTSI2SD(unsigned Opcode);
479bool isTILELOADDRS(unsigned Opcode);
480bool isVSTMXCSR(unsigned Opcode);
481bool isVCVTTSH2SI(unsigned Opcode);
482bool isRET(unsigned Opcode);
483bool isLZCNT(unsigned Opcode);
484bool isMULPD(unsigned Opcode);
485bool isVBROADCASTI32X2(unsigned Opcode);
486bool isVCVTPH2W(unsigned Opcode);
487bool isCQO(unsigned Opcode);
488bool isFSUBR(unsigned Opcode);
489bool isDPPD(unsigned Opcode);
490bool isFCOS(unsigned Opcode);
491bool isXSAVES(unsigned Opcode);
492bool isTZCNT(unsigned Opcode);
493bool isLJMP(unsigned Opcode);
494bool isCMOVCC(unsigned Opcode);
495bool isVCVTBIASPH2HF8(unsigned Opcode);
496bool isINVEPT(unsigned Opcode);
497bool isADDSUBPD(unsigned Opcode);
498bool isVMOVSHDUP(unsigned Opcode);
499bool isKSHIFTRD(unsigned Opcode);
500bool isVCVTSS2SD(unsigned Opcode);
501bool isPADDQ(unsigned Opcode);
502bool isVEXTRACTI64X4(unsigned Opcode);
503bool isVFMSUB231SS(unsigned Opcode);
504bool isVPCMPEQB(unsigned Opcode);
505bool isVPTERNLOGD(unsigned Opcode);
506bool isLEA(unsigned Opcode);
507bool isPSUBB(unsigned Opcode);
508bool isKADDQ(unsigned Opcode);
509bool isMOVSX(unsigned Opcode);
510bool isVALIGNQ(unsigned Opcode);
511bool isVCVTNE2PS2BF16(unsigned Opcode);
512bool isVPSRAW(unsigned Opcode);
513bool isVFMSUBADD231PH(unsigned Opcode);
514bool isCVTDQ2PS(unsigned Opcode);
515bool isFBLD(unsigned Opcode);
516bool isLMSW(unsigned Opcode);
517bool isWRMSR(unsigned Opcode);
518bool isMINSS(unsigned Opcode);
519bool isFSCALE(unsigned Opcode);
520bool isVFNMADD213SH(unsigned Opcode);
521bool isIMULZU(unsigned Opcode);
522bool isVPHADDUBD(unsigned Opcode);
523bool isRDSSPQ(unsigned Opcode);
524bool isVCVTBF162IBS(unsigned Opcode);
525bool isLGDT(unsigned Opcode);
526bool isVPSHLDVD(unsigned Opcode);
527bool isPFCMPGT(unsigned Opcode);
528bool isVRNDSCALEPH(unsigned Opcode);
529bool isJCXZ(unsigned Opcode);
530bool isVPMOVZXBW(unsigned Opcode);
531bool isVFMADDSUB231PD(unsigned Opcode);
532bool isVBLENDMPD(unsigned Opcode);
533bool isHSUBPS(unsigned Opcode);
534bool isPREFETCHIT0(unsigned Opcode);
535bool isKTESTD(unsigned Opcode);
536bool isVCVTNEOPH2PS(unsigned Opcode);
537bool isVBLENDVPD(unsigned Opcode);
538bool isVCVTSS2USI(unsigned Opcode);
539bool isVCVTTPS2DQS(unsigned Opcode);
540bool isVPANDD(unsigned Opcode);
541bool isPMINSW(unsigned Opcode);
542bool isSTAC(unsigned Opcode);
543bool isVFMSUB213PS(unsigned Opcode);
544bool isPOPAL(unsigned Opcode);
545bool isVCVTPS2UQQ(unsigned Opcode);
546bool isRDRAND(unsigned Opcode);
547bool isJCC(unsigned Opcode);
548bool isVPMINSQ(unsigned Opcode);
549bool isVADDSD(unsigned Opcode);
550bool isDPPS(unsigned Opcode);
551bool isPINSRQ(unsigned Opcode);
552bool isVUCOMISS(unsigned Opcode);
553bool isVPDPWSUD(unsigned Opcode);
554bool isKANDNW(unsigned Opcode);
555bool isAOR(unsigned Opcode);
556bool isPMAXUB(unsigned Opcode);
557bool isANDNPD(unsigned Opcode);
558bool isINVPCID(unsigned Opcode);
559bool isRDGSBASE(unsigned Opcode);
560bool isVPMOVSQD(unsigned Opcode);
561bool isBT(unsigned Opcode);
562bool isVPROLVQ(unsigned Opcode);
563bool isVFMADDSUB132PD(unsigned Opcode);
564bool isRORX(unsigned Opcode);
565bool isPADDUSW(unsigned Opcode);
566bool isPFNACC(unsigned Opcode);
567bool isAND(unsigned Opcode);
568bool isPSLLQ(unsigned Opcode);
569bool isVFMSUB132PH(unsigned Opcode);
570bool isXSAVE(unsigned Opcode);
571bool isKNOTQ(unsigned Opcode);
572bool isXTEST(unsigned Opcode);
573bool isVINSERTPS(unsigned Opcode);
574bool isXSAVEOPT(unsigned Opcode);
575bool isLDS(unsigned Opcode);
576bool isVFMADDSUB213PD(unsigned Opcode);
577bool isVINSERTF32X4(unsigned Opcode);
578bool isVRSQRTPS(unsigned Opcode);
579bool isVSUBPH(unsigned Opcode);
580bool isPMOVSXBW(unsigned Opcode);
581bool isVPSRLDQ(unsigned Opcode);
582bool isADC(unsigned Opcode);
583bool isPHADDD(unsigned Opcode);
584bool isVDPPHPS(unsigned Opcode);
585bool isVMINPH(unsigned Opcode);
586bool isVMINSD(unsigned Opcode);
587bool isVROUNDPD(unsigned Opcode);
588bool isVFCMADDCPH(unsigned Opcode);
589bool isINCSSPQ(unsigned Opcode);
590bool isVPUNPCKLDQ(unsigned Opcode);
591bool isVMINSH(unsigned Opcode);
592bool isINSERTQ(unsigned Opcode);
593bool isBLCI(unsigned Opcode);
594bool isHLT(unsigned Opcode);
595bool isVPCOMUW(unsigned Opcode);
596bool isVPMOVSXDQ(unsigned Opcode);
597bool isVFNMSUB231PS(unsigned Opcode);
598bool isVFNMSUB213SH(unsigned Opcode);
599bool isVCVTTPD2UQQ(unsigned Opcode);
600bool isSQRTSS(unsigned Opcode);
601bool isIMUL(unsigned Opcode);
602bool isVCVTSS2SI(unsigned Opcode);
603bool isPUSHAW(unsigned Opcode);
604bool isSTOSD(unsigned Opcode);
605bool isPSRLDQ(unsigned Opcode);
606bool isVSCATTERQPS(unsigned Opcode);
607bool isFIDIV(unsigned Opcode);
608bool isVFMSUB213PD(unsigned Opcode);
609bool isVFMADDSUB231PH(unsigned Opcode);
610bool isTDCALL(unsigned Opcode);
611bool isPVALIDATE(unsigned Opcode);
612bool isVPSHUFLW(unsigned Opcode);
613bool isPCLMULQDQ(unsigned Opcode);
614bool isCMPXCHG8B(unsigned Opcode);
615bool isVPMOVM2B(unsigned Opcode);
616bool isVCVTUDQ2PH(unsigned Opcode);
617bool isPEXTRQ(unsigned Opcode);
618bool isXCRYPTCTR(unsigned Opcode);
619bool isVREDUCEPH(unsigned Opcode);
620bool isUCOMISD(unsigned Opcode);
621bool isOUTSD(unsigned Opcode);
622bool isSUBSS(unsigned Opcode);
623bool isVFMSUBPS(unsigned Opcode);
624bool isVPBLENDW(unsigned Opcode);
625bool isBZHI(unsigned Opcode);
626bool isVPRORVD(unsigned Opcode);
627bool isRMPQUERY(unsigned Opcode);
628bool isVPEXPANDB(unsigned Opcode);
629bool isVPSCATTERDQ(unsigned Opcode);
630bool isPSMASH(unsigned Opcode);
631bool isVPSHLDQ(unsigned Opcode);
632bool isVSCATTERPF1DPD(unsigned Opcode);
633bool isMONTMUL(unsigned Opcode);
634bool isVCVTPH2UQQ(unsigned Opcode);
635bool isPSLLD(unsigned Opcode);
636bool isSAR(unsigned Opcode);
637bool isLDTILECFG(unsigned Opcode);
638bool isPMINUB(unsigned Opcode);
639bool isVCVTNEEBF162PS(unsigned Opcode);
640bool isMOVDIR64B(unsigned Opcode);
641bool isSTR(unsigned Opcode);
642bool isKANDNQ(unsigned Opcode);
643bool isBSF(unsigned Opcode);
644bool isVPDPBUUDS(unsigned Opcode);
645bool isINCSSPD(unsigned Opcode);
646bool isSQRTPS(unsigned Opcode);
647bool isTTRANSPOSED(unsigned Opcode);
648bool isCMPXCHG(unsigned Opcode);
649bool isVPSIGNW(unsigned Opcode);
650bool isVCOMISBF16(unsigned Opcode);
651bool isLES(unsigned Opcode);
652bool isCVTSS2SI(unsigned Opcode);
653bool isVPMOVUSWB(unsigned Opcode);
654bool isFCOMPI(unsigned Opcode);
655bool isPUNPCKHWD(unsigned Opcode);
656bool isPFACC(unsigned Opcode);
657bool isVPTESTNMW(unsigned Opcode);
658bool isVPMULDQ(unsigned Opcode);
659bool isSHRX(unsigned Opcode);
660bool isKXORQ(unsigned Opcode);
661bool isVGETEXPSD(unsigned Opcode);
662bool isV4FNMADDPS(unsigned Opcode);
663bool isVFNMSUB231SD(unsigned Opcode);
664bool isVPSHLD(unsigned Opcode);
665bool isPAVGB(unsigned Opcode);
666bool isPMOVZXBD(unsigned Opcode);
667bool isKORTESTW(unsigned Opcode);
668bool isVSHUFPS(unsigned Opcode);
669bool isAESENCWIDE128KL(unsigned Opcode);
670bool isVPXORD(unsigned Opcode);
671bool isVPSHAW(unsigned Opcode);
672bool isVFMSUB132BF16(unsigned Opcode);
673bool isVPERMT2B(unsigned Opcode);
674bool isVFMADD213PD(unsigned Opcode);
675bool isVPGATHERQD(unsigned Opcode);
676bool isVFNMSUB213BF16(unsigned Opcode);
677bool isVCVTPS2IBS(unsigned Opcode);
678bool isVPCMPGTW(unsigned Opcode);
679bool isVMOVRSB(unsigned Opcode);
680bool isVGETMANTSH(unsigned Opcode);
681bool isVANDPS(unsigned Opcode);
682bool isVDIVPS(unsigned Opcode);
683bool isVANDNPS(unsigned Opcode);
684bool isVPBROADCASTW(unsigned Opcode);
685bool isFLDL2T(unsigned Opcode);
686bool isVPERMB(unsigned Opcode);
687bool isFCMOVNBE(unsigned Opcode);
688bool isVCVTTPH2W(unsigned Opcode);
689bool isPMOVZXBQ(unsigned Opcode);
690bool isT2RPNTLVWZ0RS(unsigned Opcode);
691bool isPF2ID(unsigned Opcode);
692bool isVFNMADD132PD(unsigned Opcode);
693bool isPMULHRSW(unsigned Opcode);
694bool isKADDD(unsigned Opcode);
695bool isVFNMSUB132SH(unsigned Opcode);
696bool isUIRET(unsigned Opcode);
697bool isBSR(unsigned Opcode);
698bool isPCMPEQQ(unsigned Opcode);
699bool isCDQ(unsigned Opcode);
700bool isPMAXSW(unsigned Opcode);
701bool isSIDTD(unsigned Opcode);
702bool isVCVTPS2PHX(unsigned Opcode);
703bool isVPSLLVQ(unsigned Opcode);
704bool isMOVQ(unsigned Opcode);
705bool isVCMPBF16(unsigned Opcode);
706bool isPREFETCH(unsigned Opcode);
707bool isCLRSSBSY(unsigned Opcode);
708bool isTCVTROWPS2PHL(unsigned Opcode);
709bool isPSHUFW(unsigned Opcode);
710bool isVPDPWSUDS(unsigned Opcode);
711bool isVPMOVSXBQ(unsigned Opcode);
712bool isFICOMP(unsigned Opcode);
713bool isVLDMXCSR(unsigned Opcode);
714bool isVPSUBUSW(unsigned Opcode);
715bool isVFNMSUB132SS(unsigned Opcode);
716bool isRETF(unsigned Opcode);
717bool isKMOVQ(unsigned Opcode);
718bool isVPADDUSW(unsigned Opcode);
719bool isPACKSSDW(unsigned Opcode);
720bool isUMONITOR(unsigned Opcode);
721bool isENQCMDS(unsigned Opcode);
722bool isVCOMXSD(unsigned Opcode);
723bool isVPMAXSQ(unsigned Opcode);
724bool isVFMSUB213BF16(unsigned Opcode);
725bool isVPERMT2Q(unsigned Opcode);
726bool isFDECSTP(unsigned Opcode);
727bool isVPTESTMQ(unsigned Opcode);
728bool isVRCP14PD(unsigned Opcode);
729bool isARPL(unsigned Opcode);
730bool isVFMSUB213SD(unsigned Opcode);
731bool isJMPABS(unsigned Opcode);
732bool isVUNPCKHPS(unsigned Opcode);
733bool isVFNMADDSS(unsigned Opcode);
734bool isSIDT(unsigned Opcode);
735bool isVPCMPGTB(unsigned Opcode);
736bool isVPRORD(unsigned Opcode);
737bool isVSUBSS(unsigned Opcode);
738bool isPUSHFQ(unsigned Opcode);
739bool isVCVTHF82PH(unsigned Opcode);
740bool isVPCLMULQDQ(unsigned Opcode);
741bool isVPADDUSB(unsigned Opcode);
742bool isVPCMPD(unsigned Opcode);
743bool isMOVSD(unsigned Opcode);
744bool isPSUBUSW(unsigned Opcode);
745bool isVFMSUBADD132PS(unsigned Opcode);
746bool isMOVMSKPS(unsigned Opcode);
747bool isVFIXUPIMMSS(unsigned Opcode);
748bool isMFENCE(unsigned Opcode);
749bool isFTST(unsigned Opcode);
750bool isVPMADDWD(unsigned Opcode);
751bool isPOP(unsigned Opcode);
752bool isPSUBW(unsigned Opcode);
753bool isBSWAP(unsigned Opcode);
754bool isPFMIN(unsigned Opcode);
755bool isVFPCLASSPD(unsigned Opcode);
756bool isVPSHRDVD(unsigned Opcode);
757bool isPADDW(unsigned Opcode);
758bool isT2RPNTLVWZ1(unsigned Opcode);
759bool isCVTSI2SD(unsigned Opcode);
760bool isENQCMD(unsigned Opcode);
761bool isXSHA1(unsigned Opcode);
762bool isVFNMADD132SD(unsigned Opcode);
763bool isMOVZX(unsigned Opcode);
764bool isVFIXUPIMMSD(unsigned Opcode);
765bool isT2RPNTLVWZ0RST1(unsigned Opcode);
766bool isINVD(unsigned Opcode);
767bool isVFIXUPIMMPS(unsigned Opcode);
768bool isMOVDQU(unsigned Opcode);
769bool isVFPCLASSPS(unsigned Opcode);
770bool isMOVSQ(unsigned Opcode);
771bool isAESDECWIDE128KL(unsigned Opcode);
772bool isROUNDSS(unsigned Opcode);
773bool isVPERMILPS(unsigned Opcode);
774bool isVPMOVW2M(unsigned Opcode);
775bool isVMULSD(unsigned Opcode);
776bool isVPERMI2W(unsigned Opcode);
777bool isVPSHUFB(unsigned Opcode);
778bool isFST(unsigned Opcode);
779bool isVPHSUBW(unsigned Opcode);
780bool isVREDUCESS(unsigned Opcode);
781bool isFRNDINT(unsigned Opcode);
782bool isSHR(unsigned Opcode);
783bool isLOOPNE(unsigned Opcode);
784bool isVCVTTPH2UQQ(unsigned Opcode);
785bool isSHA1NEXTE(unsigned Opcode);
786bool isVFMADD132SD(unsigned Opcode);
787bool isPSRAW(unsigned Opcode);
788bool isVPBROADCASTQ(unsigned Opcode);
789bool isCLC(unsigned Opcode);
790bool isPOPAW(unsigned Opcode);
791bool isTCMMIMFP16PS(unsigned Opcode);
792bool isVCVTTPS2UQQ(unsigned Opcode);
793bool isVCVTQQ2PH(unsigned Opcode);
794bool isVMOVUPD(unsigned Opcode);
795bool isFPTAN(unsigned Opcode);
796bool isVMASKMOVPD(unsigned Opcode);
797bool isVMOVLHPS(unsigned Opcode);
798bool isAESKEYGENASSIST(unsigned Opcode);
799bool isXSAVEOPT64(unsigned Opcode);
800bool isXSAVEC(unsigned Opcode);
801bool isVPLZCNTQ(unsigned Opcode);
802bool isVPSUBW(unsigned Opcode);
803bool isCMPCCXADD(unsigned Opcode);
804bool isVFMSUBADD213PH(unsigned Opcode);
805bool isVFMADDSUBPD(unsigned Opcode);
806bool isVPMINSW(unsigned Opcode);
807bool isVFNMSUB132PS(unsigned Opcode);
808bool isVMOVAPS(unsigned Opcode);
809bool isVPEXTRQ(unsigned Opcode);
810bool isVSCALEFSH(unsigned Opcode);
811bool isVCVTPD2PS(unsigned Opcode);
812bool isCLGI(unsigned Opcode);
813bool isVAESDEC(unsigned Opcode);
814bool isPFMUL(unsigned Opcode);
815bool isVCVTBIASPH2BF8S(unsigned Opcode);
816bool isMOVDIRI(unsigned Opcode);
817bool isSHUFPS(unsigned Opcode);
818bool isVFNMSUB231SS(unsigned Opcode);
819bool isVMWRITE(unsigned Opcode);
820bool isVINSERTF128(unsigned Opcode);
821bool isFISUBR(unsigned Opcode);
822bool isVINSERTI32X4(unsigned Opcode);
823bool isVPSLLDQ(unsigned Opcode);
824bool isPOPCNT(unsigned Opcode);
825bool isVXORPD(unsigned Opcode);
826bool isXLATB(unsigned Opcode);
827bool isDIV(unsigned Opcode);
828bool isVPSHLDVQ(unsigned Opcode);
829bool isMOVDDUP(unsigned Opcode);
830bool isVMOVDQU64(unsigned Opcode);
831bool isVPCOMPRESSQ(unsigned Opcode);
832bool isVFMSUBADD132PD(unsigned Opcode);
833bool isADDSD(unsigned Opcode);
834bool isBLENDPD(unsigned Opcode);
835bool isVPERMILPD(unsigned Opcode);
836bool isPMADDUBSW(unsigned Opcode);
837bool isPOPFD(unsigned Opcode);
838bool isCMPSW(unsigned Opcode);
839bool isLDMXCSR(unsigned Opcode);
840bool isVMULPS(unsigned Opcode);
841bool isVROUNDSD(unsigned Opcode);
842bool isVFMADD132PD(unsigned Opcode);
843bool isVPANDQ(unsigned Opcode);
844bool isVPSRAQ(unsigned Opcode);
845bool isVCOMISD(unsigned Opcode);
846bool isVCVTBIASPH2BF8(unsigned Opcode);
847bool isFFREEP(unsigned Opcode);
848bool isT2RPNTLVWZ1RS(unsigned Opcode);
849bool isVCMPPD(unsigned Opcode);
850bool isVFNMADD213PD(unsigned Opcode);
851bool isVFNMSUB132PH(unsigned Opcode);
852bool isVPHADDBW(unsigned Opcode);
853bool isVPPERM(unsigned Opcode);
854bool isVCVTPS2PD(unsigned Opcode);
855bool isCBW(unsigned Opcode);
856bool isVMOVUPS(unsigned Opcode);
857bool isVPMAXUQ(unsigned Opcode);
858bool isWRSSQ(unsigned Opcode);
859bool isPACKUSDW(unsigned Opcode);
860bool isVCVTTBF162IBS(unsigned Opcode);
861bool isXBEGIN(unsigned Opcode);
862bool isVCVTPD2UQQ(unsigned Opcode);
863bool isFCMOVB(unsigned Opcode);
864bool isNOP(unsigned Opcode);
865bool isVPABSQ(unsigned Opcode);
866bool isVTESTPS(unsigned Opcode);
867bool isPHSUBW(unsigned Opcode);
868bool isPUSH2P(unsigned Opcode);
869bool isFISTTP(unsigned Opcode);
870bool isCFCMOVCC(unsigned Opcode);
871bool isVPINSRD(unsigned Opcode);
872bool isPCMPESTRM(unsigned Opcode);
873bool isVFNMSUB213PS(unsigned Opcode);
874bool isPHSUBD(unsigned Opcode);
875bool isVCVTTPD2DQS(unsigned Opcode);
876bool isSLDT(unsigned Opcode);
877bool isVHADDPS(unsigned Opcode);
878bool isVMOVNTDQ(unsigned Opcode);
879bool isVPMINSD(unsigned Opcode);
880bool isVFRCZSD(unsigned Opcode);
881bool isVPTESTMW(unsigned Opcode);
882bool isVPMOVZXWD(unsigned Opcode);
883bool isPSADBW(unsigned Opcode);
884bool isVCVTSD2SI(unsigned Opcode);
885bool isVMAXPH(unsigned Opcode);
886bool isLODSB(unsigned Opcode);
887bool isPHMINPOSUW(unsigned Opcode);
888bool isVPROLVD(unsigned Opcode);
889bool isWRFSBASE(unsigned Opcode);
890bool isVRSQRT14PS(unsigned Opcode);
891bool isVPHSUBDQ(unsigned Opcode);
892bool isIRETD(unsigned Opcode);
893bool isVMOVRSD(unsigned Opcode);
894bool isCVTSI2SS(unsigned Opcode);
895bool isVPMULHRSW(unsigned Opcode);
896bool isPI2FD(unsigned Opcode);
897bool isGF2P8AFFINEQB(unsigned Opcode);
898bool isPAND(unsigned Opcode);
899bool isVFNMSUB231SH(unsigned Opcode);
900bool isVCVTPH2BF8(unsigned Opcode);
901bool isVMOVHLPS(unsigned Opcode);
902bool isPEXTRB(unsigned Opcode);
903bool isVMMCALL(unsigned Opcode);
904bool isKNOTD(unsigned Opcode);
905bool isVCVTSH2SS(unsigned Opcode);
906bool isVPUNPCKLQDQ(unsigned Opcode);
907bool isVPERMIL2PS(unsigned Opcode);
908bool isVPCMPGTD(unsigned Opcode);
909bool isCMPXCHG16B(unsigned Opcode);
910bool isTDPHF8PS(unsigned Opcode);
911bool isVZEROUPPER(unsigned Opcode);
912bool isMOVAPS(unsigned Opcode);
913bool isVPCMPW(unsigned Opcode);
914bool isFUCOMPP(unsigned Opcode);
915bool isXSETBV(unsigned Opcode);
916bool isSLWPCB(unsigned Opcode);
917bool isSCASW(unsigned Opcode);
918bool isFCMOVNE(unsigned Opcode);
919bool isPBNDKB(unsigned Opcode);
920bool isVPMULLD(unsigned Opcode);
921bool isVP4DPWSSDS(unsigned Opcode);
922bool isVCVT2PH2HF8(unsigned Opcode);
923bool isPINSRW(unsigned Opcode);
924bool isVCVTSI2SH(unsigned Opcode);
925bool isVINSERTF32X8(unsigned Opcode);
926bool isKSHIFTLB(unsigned Opcode);
927bool isSEAMOPS(unsigned Opcode);
928bool isVPMULUDQ(unsigned Opcode);
929bool isVPMOVSQB(unsigned Opcode);
930bool isVPTESTMD(unsigned Opcode);
931bool isVPHADDDQ(unsigned Opcode);
932bool isKUNPCKDQ(unsigned Opcode);
933bool isT1MSKC(unsigned Opcode);
934bool isVPCOMB(unsigned Opcode);
935bool isVBLENDPS(unsigned Opcode);
936bool isPTWRITE(unsigned Opcode);
937bool isVCVTPH2BF8S(unsigned Opcode);
938bool isCVTPS2PI(unsigned Opcode);
939bool isVPROTD(unsigned Opcode);
940bool isCALL(unsigned Opcode);
941bool isTILELOADDRST1(unsigned Opcode);
942bool isVPERMPS(unsigned Opcode);
943bool isVPSHUFBITQMB(unsigned Opcode);
944bool isVMOVSLDUP(unsigned Opcode);
945bool isINVLPGA(unsigned Opcode);
946bool isVCVTPH2QQ(unsigned Opcode);
947bool isADD(unsigned Opcode);
948bool isPSUBSW(unsigned Opcode);
949bool isSIDTW(unsigned Opcode);
950bool isVFNMADD231PH(unsigned Opcode);
951bool isVEXTRACTF64X2(unsigned Opcode);
952bool isFCOMI(unsigned Opcode);
953bool isRSM(unsigned Opcode);
954bool isVPCOMUD(unsigned Opcode);
955bool isVPMOVZXBQ(unsigned Opcode);
956bool isUWRMSR(unsigned Opcode);
957bool isLGS(unsigned Opcode);
958bool isVMOVNTPD(unsigned Opcode);
959bool isRDPRU(unsigned Opcode);
960bool isVPUNPCKHBW(unsigned Opcode);
961bool isVUCOMXSD(unsigned Opcode);
962bool isANDN(unsigned Opcode);
963bool isVCVTTPH2UW(unsigned Opcode);
964bool isVMFUNC(unsigned Opcode);
965bool isT2RPNTLVWZ0(unsigned Opcode);
966bool isFIMUL(unsigned Opcode);
967bool isBLCFILL(unsigned Opcode);
968bool isVGATHERPF0DPS(unsigned Opcode);
969bool isVFMSUBADD231PS(unsigned Opcode);
970bool isVREDUCESD(unsigned Opcode);
971bool isVCOMXSH(unsigned Opcode);
972bool isVXORPS(unsigned Opcode);
973bool isPSWAPD(unsigned Opcode);
974bool isPMAXSD(unsigned Opcode);
975bool isVCMPSS(unsigned Opcode);
976bool isEXTRACTPS(unsigned Opcode);
977bool isVPMOVZXBD(unsigned Opcode);
978bool isOUTSW(unsigned Opcode);
979bool isKORTESTB(unsigned Opcode);
980bool isVREDUCEPS(unsigned Opcode);
981bool isPEXTRW(unsigned Opcode);
982bool isFNINIT(unsigned Opcode);
983bool isVCVTPH2IBS(unsigned Opcode);
984bool isROL(unsigned Opcode);
985bool isVCVTPS2QQ(unsigned Opcode);
986bool isVGETMANTPH(unsigned Opcode);
987bool isPUNPCKLDQ(unsigned Opcode);
988bool isPADDD(unsigned Opcode);
989bool isVPSLLD(unsigned Opcode);
990bool isPFCMPGE(unsigned Opcode);
991bool isVGETMANTBF16(unsigned Opcode);
992bool isVSUBBF16(unsigned Opcode);
993bool isVPMOVM2D(unsigned Opcode);
994bool isVCVTTSS2USIS(unsigned Opcode);
995bool isVHSUBPS(unsigned Opcode);
996bool isENDBR32(unsigned Opcode);
997bool isMOVSXD(unsigned Opcode);
998bool isPSIGND(unsigned Opcode);
999bool isVPTEST(unsigned Opcode);
1000bool isVPDPWUSD(unsigned Opcode);
1001bool isHSUBPD(unsigned Opcode);
1002bool isADCX(unsigned Opcode);
1003bool isCVTTPD2PI(unsigned Opcode);
1004bool isPDEP(unsigned Opcode);
1005bool isTDPBUSD(unsigned Opcode);
1006bool isVCVTBIASPH2HF8S(unsigned Opcode);
1007bool isVBROADCASTI32X4(unsigned Opcode);
1008bool isVCVTPH2UDQ(unsigned Opcode);
1009bool isVPHADDW(unsigned Opcode);
1010bool isFLDL2E(unsigned Opcode);
1011bool isCLZERO(unsigned Opcode);
1012bool isPBLENDW(unsigned Opcode);
1013bool isVCVTBF162IUBS(unsigned Opcode);
1014bool isVCVTSH2USI(unsigned Opcode);
1015bool isVANDPD(unsigned Opcode);
1016bool isBEXTR(unsigned Opcode);
1017bool isSTD(unsigned Opcode);
1018bool isVAESKEYGENASSIST(unsigned Opcode);
1019bool isCMPSD(unsigned Opcode);
1020bool isMOVSS(unsigned Opcode);
1021bool isVCVTUQQ2PD(unsigned Opcode);
1022bool isVEXTRACTI32X4(unsigned Opcode);
1023bool isFLDCW(unsigned Opcode);
1024bool isINSW(unsigned Opcode);
1025bool isRDPID(unsigned Opcode);
1026bool isVUCOMXSS(unsigned Opcode);
1027bool isKANDQ(unsigned Opcode);
1028bool isV4FMADDPS(unsigned Opcode);
1029bool isPMOVZXWQ(unsigned Opcode);
1030bool isVFPCLASSSD(unsigned Opcode);
1031bool isBLENDPS(unsigned Opcode);
1032bool isVPACKSSDW(unsigned Opcode);
1033bool isVPINSRW(unsigned Opcode);
1034bool isFXAM(unsigned Opcode);
1035bool isVMINMAXBF16(unsigned Opcode);
1036bool isVSHUFF64X2(unsigned Opcode);
1037bool isVPACKUSWB(unsigned Opcode);
1038bool isVRSQRT28SS(unsigned Opcode);
1039bool isGETSEC(unsigned Opcode);
1040bool isVEXTRACTF64X4(unsigned Opcode);
1041bool isVPHSUBBW(unsigned Opcode);
1042bool isBLSR(unsigned Opcode);
1043bool isFILD(unsigned Opcode);
1044bool isRETFQ(unsigned Opcode);
1045bool isVADDSS(unsigned Opcode);
1046bool isCOMISS(unsigned Opcode);
1047bool isCLI(unsigned Opcode);
1048bool isVERW(unsigned Opcode);
1049bool isBTC(unsigned Opcode);
1050bool isVPHADDUBQ(unsigned Opcode);
1051bool isVPORQ(unsigned Opcode);
1052bool isORPD(unsigned Opcode);
1053bool isVMOVSS(unsigned Opcode);
1054bool isVPSUBD(unsigned Opcode);
1055bool isVGATHERPF1QPD(unsigned Opcode);
1056bool isENCODEKEY256(unsigned Opcode);
1057bool isGF2P8AFFINEINVQB(unsigned Opcode);
1058bool isXRSTOR64(unsigned Opcode);
1059bool isKANDW(unsigned Opcode);
1060bool isLODSQ(unsigned Opcode);
1061bool isVMOVRSW(unsigned Opcode);
1062bool isVSUBSH(unsigned Opcode);
1063bool isLSS(unsigned Opcode);
1064bool isPMOVSXBQ(unsigned Opcode);
1065bool isVCVTTSD2SIS(unsigned Opcode);
1066bool isVCMPSH(unsigned Opcode);
1067bool isVFMADD132PS(unsigned Opcode);
1068bool isVPACKSSWB(unsigned Opcode);
1069bool isPCMPGTQ(unsigned Opcode);
1070bool isVFMADD132SH(unsigned Opcode);
1071bool isVCVTUQQ2PH(unsigned Opcode);
1072bool isVCVTQQ2PS(unsigned Opcode);
1073bool isVCVTTSS2USI(unsigned Opcode);
1074bool isVPMOVM2Q(unsigned Opcode);
1075bool isVMOVD(unsigned Opcode);
1076bool isVCVTTPS2QQS(unsigned Opcode);
1077bool isVSQRTBF16(unsigned Opcode);
1078bool isVFPCLASSPH(unsigned Opcode);
1079bool isVCVTSS2SH(unsigned Opcode);
1080bool isSCASB(unsigned Opcode);
1081bool isPSRLD(unsigned Opcode);
1082bool isVADDPH(unsigned Opcode);
1083bool isFSUB(unsigned Opcode);
1084bool isVCVTTPH2IBS(unsigned Opcode);
1085bool isVEXTRACTI64X2(unsigned Opcode);
1086bool isPMINUW(unsigned Opcode);
1087bool isPSUBSB(unsigned Opcode);
1088bool isVCVT2PS2PHX(unsigned Opcode);
1089bool isVPCMPEQD(unsigned Opcode);
1090bool isVPSCATTERQD(unsigned Opcode);
1091bool isVPSHLDD(unsigned Opcode);
1092bool isKXNORB(unsigned Opcode);
1093bool isLDDQU(unsigned Opcode);
1094bool isMASKMOVQ(unsigned Opcode);
1095bool isPABSW(unsigned Opcode);
1096bool isVPROLD(unsigned Opcode);
1097bool isVPCOMQ(unsigned Opcode);
1098bool isVSCATTERDPD(unsigned Opcode);
1099bool isFXRSTOR(unsigned Opcode);
1100bool isVPCMPUW(unsigned Opcode);
1101bool isWBINVD(unsigned Opcode);
1102bool isVCVTTPD2UDQ(unsigned Opcode);
1103bool isERETU(unsigned Opcode);
1104bool isPFRCPIT2(unsigned Opcode);
1105bool isTTCMMRLFP16PS(unsigned Opcode);
1106bool isVPERMT2W(unsigned Opcode);
1107bool isVEXTRACTF32X4(unsigned Opcode);
1108bool isVGATHERPF0DPD(unsigned Opcode);
1109bool isVBROADCASTF32X2(unsigned Opcode);
1110bool isVRCP14SD(unsigned Opcode);
1111bool isPABSD(unsigned Opcode);
1112bool isLAHF(unsigned Opcode);
1113bool isPINSRB(unsigned Opcode);
1114bool isSKINIT(unsigned Opcode);
1115bool isENTER(unsigned Opcode);
1116bool isVCVTSI2SS(unsigned Opcode);
1117bool isVFMADD231PD(unsigned Opcode);
1118bool isLOADIWKEY(unsigned Opcode);
1119bool isVMOVNTDQA(unsigned Opcode);
1120bool isVPERMT2PS(unsigned Opcode);
1121bool isPUSHF(unsigned Opcode);
1122bool isMPSADBW(unsigned Opcode);
1123bool isVMINMAXSH(unsigned Opcode);
1124bool isVRSQRT14SS(unsigned Opcode);
1125bool isVCVTDQ2PD(unsigned Opcode);
1126bool isVORPS(unsigned Opcode);
1127bool isVPEXPANDQ(unsigned Opcode);
1128bool isVPSHRDD(unsigned Opcode);
1129bool isTDPBSSD(unsigned Opcode);
1130bool isTESTUI(unsigned Opcode);
1131bool isVFMADDPD(unsigned Opcode);
1132bool isVPANDND(unsigned Opcode);
1133bool isVPMOVSDB(unsigned Opcode);
1134bool isVPBROADCASTB(unsigned Opcode);
1135bool isCVTPI2PD(unsigned Opcode);
1136bool isVPERMI2B(unsigned Opcode);
1137bool isVPMINSB(unsigned Opcode);
1138bool isLAR(unsigned Opcode);
1139bool isINVLPGB(unsigned Opcode);
1140bool isTLBSYNC(unsigned Opcode);
1141bool isFDIVP(unsigned Opcode);
1142bool isVPSRLW(unsigned Opcode);
1143bool isVRCP28SS(unsigned Opcode);
1144bool isVMOVHPS(unsigned Opcode);
1145bool isVPMACSSDD(unsigned Opcode);
1146bool isPEXT(unsigned Opcode);
1147bool isVMAXBF16(unsigned Opcode);
1148bool isVRSQRT14SD(unsigned Opcode);
1149bool isVPDPWSSD(unsigned Opcode);
1150bool isVFMSUB231SD(unsigned Opcode);
1151bool isVPMOVZXWQ(unsigned Opcode);
1152bool isVMOVDQA(unsigned Opcode);
1153bool isVFNMSUB213SD(unsigned Opcode);
1154bool isVMINPS(unsigned Opcode);
1155bool isVFMSUB231PS(unsigned Opcode);
1156bool isVPCOMPRESSB(unsigned Opcode);
1157bool isVPCMPEQQ(unsigned Opcode);
1158bool isVRCPSS(unsigned Opcode);
1159bool isVSCATTERPF1DPS(unsigned Opcode);
1160bool isVPHADDUBW(unsigned Opcode);
1161bool isXORPD(unsigned Opcode);
1162bool isVPSCATTERQQ(unsigned Opcode);
1163bool isVCVTW2PH(unsigned Opcode);
1164bool isVFMADDCPH(unsigned Opcode);
1165bool isVSUBPD(unsigned Opcode);
1166bool isVPACKUSDW(unsigned Opcode);
1167bool isVSCALEFSS(unsigned Opcode);
1168bool isAESIMC(unsigned Opcode);
1169bool isVRCP28PS(unsigned Opcode);
1170bool isAAND(unsigned Opcode);
1171bool isDAA(unsigned Opcode);
1172bool isVCVTPD2UDQ(unsigned Opcode);
1173bool isKTESTW(unsigned Opcode);
1174bool isVPADDQ(unsigned Opcode);
1175bool isPALIGNR(unsigned Opcode);
1176bool isPMAXUW(unsigned Opcode);
1177bool isVFMADDSD(unsigned Opcode);
1178bool isPFMAX(unsigned Opcode);
1179bool isVPOR(unsigned Opcode);
1180bool isVPSUBB(unsigned Opcode);
1181bool isVPAVGB(unsigned Opcode);
1182bool isINSB(unsigned Opcode);
1183bool isFYL2X(unsigned Opcode);
1184bool isVFNMSUB132PD(unsigned Opcode);
1185bool isVFNMSUBPS(unsigned Opcode);
1186bool isVFMADD231PS(unsigned Opcode);
1187bool isVCVTTSS2SI(unsigned Opcode);
1188bool isTCMMRLFP16PS(unsigned Opcode);
1189bool isFCOMPP(unsigned Opcode);
1190bool isMOVD(unsigned Opcode);
1191bool isMOVBE(unsigned Opcode);
1192bool isVP2INTERSECTD(unsigned Opcode);
1193bool isVPMULLQ(unsigned Opcode);
1194bool isVSCALEFPS(unsigned Opcode);
1195bool isVPMACSDQH(unsigned Opcode);
1196bool isVPTESTNMD(unsigned Opcode);
1197bool isFCOMP(unsigned Opcode);
1198bool isPREFETCHWT1(unsigned Opcode);
1199bool isVCMPSD(unsigned Opcode);
1200bool isSGDTD(unsigned Opcode);
1201bool isWRUSSD(unsigned Opcode);
1202bool isFSUBP(unsigned Opcode);
1203bool isVUNPCKLPS(unsigned Opcode);
1204bool isVFNMSUB213SS(unsigned Opcode);
1205bool isROUNDPD(unsigned Opcode);
1206bool isVPMAXSW(unsigned Opcode);
1207bool isVCVTTPH2DQ(unsigned Opcode);
1208bool isVPUNPCKLWD(unsigned Opcode);
1209bool isKSHIFTLD(unsigned Opcode);
1210bool isTCVTROWPS2BF16H(unsigned Opcode);
1211bool isVFMADD231SD(unsigned Opcode);
1212bool isADDPS(unsigned Opcode);
1213bool isVPSLLVD(unsigned Opcode);
1214bool isVFNMADD132SH(unsigned Opcode);
1215bool isVMOVNTPS(unsigned Opcode);
1216bool isVCVTPD2DQ(unsigned Opcode);
1217bool isVPXOR(unsigned Opcode);
1218bool isSTMXCSR(unsigned Opcode);
1219bool isVRCP14SS(unsigned Opcode);
1220bool isUD2(unsigned Opcode);
1221bool isVPOPCNTW(unsigned Opcode);
1222bool isVRSQRTSH(unsigned Opcode);
1223bool isVSCATTERPF0DPD(unsigned Opcode);
1224bool isVFMADDPS(unsigned Opcode);
1225bool isXSAVEC64(unsigned Opcode);
1226bool isVPMADDUBSW(unsigned Opcode);
1227bool isVPMOVZXDQ(unsigned Opcode);
1228bool isVRCP14PS(unsigned Opcode);
1229bool isTCONJTCMMIMFP16PS(unsigned Opcode);
1230bool isVSQRTSH(unsigned Opcode);
1231bool isTCVTROWD2PS(unsigned Opcode);
1232bool isLOOP(unsigned Opcode);
1233bool isSTUI(unsigned Opcode);
1234bool isVCVTTPS2UDQ(unsigned Opcode);
1235bool isVCOMPRESSPS(unsigned Opcode);
1236bool isTTDPBF16PS(unsigned Opcode);
1237bool isVCVTTBF162IUBS(unsigned Opcode);
1238bool isVPADDW(unsigned Opcode);
1239bool isVRNDSCALEPS(unsigned Opcode);
1240bool isVPSIGND(unsigned Opcode);
1241bool isXABORT(unsigned Opcode);
1242bool isVPHADDUWD(unsigned Opcode);
1243bool isT2RPNTLVWZ1T1(unsigned Opcode);
1244bool isVCVT2PH2HF8S(unsigned Opcode);
1245bool isVDBPSADBW(unsigned Opcode);
1246bool isPSLLW(unsigned Opcode);
1247bool isVPMOVQD(unsigned Opcode);
1248bool isVINSERTI64X4(unsigned Opcode);
1249bool isVPERMI2PS(unsigned Opcode);
1250bool isVMULPH(unsigned Opcode);
1251bool isVPCMPUQ(unsigned Opcode);
1252bool isVCVTUSI2SD(unsigned Opcode);
1253bool isKXNORW(unsigned Opcode);
1254bool isBLCIC(unsigned Opcode);
1255bool isVFNMADD213SD(unsigned Opcode);
1256bool isVPMACSWW(unsigned Opcode);
1257bool isVMOVLPS(unsigned Opcode);
1258bool isPCONFIG(unsigned Opcode);
1259bool isPANDN(unsigned Opcode);
1260bool isVGETEXPPD(unsigned Opcode);
1261bool isVPSRLVQ(unsigned Opcode);
1262bool isUD1(unsigned Opcode);
1263bool isPMAXSB(unsigned Opcode);
1264bool isVPROLQ(unsigned Opcode);
1265bool isVSCATTERPF1QPD(unsigned Opcode);
1266bool isVPSRLD(unsigned Opcode);
1267bool isINT3(unsigned Opcode);
1268bool isXRSTORS64(unsigned Opcode);
1269bool isCVTSD2SI(unsigned Opcode);
1270bool isVMAXSS(unsigned Opcode);
1271bool isVPMINUB(unsigned Opcode);
1272bool isKXNORQ(unsigned Opcode);
1273bool isFLD(unsigned Opcode);
1274bool isVSHUFI32X4(unsigned Opcode);
1275bool isSAHF(unsigned Opcode);
1276bool isPFRSQRT(unsigned Opcode);
1277bool isSHRD(unsigned Opcode);
1278bool isSYSEXIT(unsigned Opcode);
1279bool isXSAVE64(unsigned Opcode);
1280bool isVPMAXSD(unsigned Opcode);
1281bool isCVTTSD2SI(unsigned Opcode);
1282bool isVCVTTSS2SIS(unsigned Opcode);
1283bool isPMOVMSKB(unsigned Opcode);
1284bool isVRANGEPS(unsigned Opcode);
1285bool isVADDSUBPS(unsigned Opcode);
1286bool isVBROADCASTI128(unsigned Opcode);
1287bool isPADDUSB(unsigned Opcode);
1288bool isENCODEKEY128(unsigned Opcode);
1289bool isOR(unsigned Opcode);
1290bool isSTOSW(unsigned Opcode);
1291bool isVCVTTPD2UQQS(unsigned Opcode);
1292bool isPAVGW(unsigned Opcode);
1293bool isVCVTPD2PH(unsigned Opcode);
1294bool isSHLX(unsigned Opcode);
1295bool isVCVTSH2SD(unsigned Opcode);
1296bool isVFMADD231SS(unsigned Opcode);
1297bool isMOVNTSD(unsigned Opcode);
1298bool isFLDPI(unsigned Opcode);
1299bool isVCVTUSI2SS(unsigned Opcode);
1300bool isPMOVSXBD(unsigned Opcode);
1301bool isVPRORVQ(unsigned Opcode);
1302bool isVPERMT2D(unsigned Opcode);
1303bool isADDSS(unsigned Opcode);
1304bool isAADD(unsigned Opcode);
1305bool isVPSRLVW(unsigned Opcode);
1306bool isVRSQRTPH(unsigned Opcode);
1307bool isVLDDQU(unsigned Opcode);
1308bool isKMOVD(unsigned Opcode);
1309bool isENCLV(unsigned Opcode);
1310bool isENCLU(unsigned Opcode);
1311bool isPREFETCHT1(unsigned Opcode);
1312bool isRSQRTPS(unsigned Opcode);
1313bool isVCVTTSH2USI(unsigned Opcode);
1314bool isPADDB(unsigned Opcode);
1315bool isVMASKMOVDQU(unsigned Opcode);
1316bool isPUNPCKLBW(unsigned Opcode);
1317bool isMOV(unsigned Opcode);
1318bool isVCVTTPH2IUBS(unsigned Opcode);
1319bool isMUL(unsigned Opcode);
1320bool isRCL(unsigned Opcode);
1321bool isVRCPSH(unsigned Opcode);
1322bool isPFCMPEQ(unsigned Opcode);
1323bool isMONITOR(unsigned Opcode);
1324bool isFDIVR(unsigned Opcode);
1325bool isPMINSD(unsigned Opcode);
1326bool isPFRCP(unsigned Opcode);
1327bool isKTESTQ(unsigned Opcode);
1328bool isVCVTTPD2DQ(unsigned Opcode);
1329bool isVSHUFF32X4(unsigned Opcode);
1330bool isVPSLLVW(unsigned Opcode);
1331bool isTDPBSUD(unsigned Opcode);
1332bool isVPMINUQ(unsigned Opcode);
1333bool isFIADD(unsigned Opcode);
1334bool isFCMOVNU(unsigned Opcode);
1335bool isVHSUBPD(unsigned Opcode);
1336bool isKSHIFTRQ(unsigned Opcode);
1337bool isMOVUPS(unsigned Opcode);
1338bool isVMCALL(unsigned Opcode);
1339bool isXADD(unsigned Opcode);
1340bool isXRSTOR(unsigned Opcode);
1341bool isVGATHERPF1DPD(unsigned Opcode);
1342bool isRCR(unsigned Opcode);
1343bool isFNSTCW(unsigned Opcode);
1344bool isVPMOVSDW(unsigned Opcode);
1345bool isVFMSUB132SH(unsigned Opcode);
1346bool isVPCONFLICTQ(unsigned Opcode);
1347bool isSWAPGS(unsigned Opcode);
1348bool isVPMOVQ2M(unsigned Opcode);
1349bool isVPSRAVW(unsigned Opcode);
1350bool isMOVDQA(unsigned Opcode);
1351bool isDIVSD(unsigned Opcode);
1352bool isPCMPGTB(unsigned Opcode);
1353bool isSHA256MSG2(unsigned Opcode);
1354bool isTTMMULTF32PS(unsigned Opcode);
1355bool isKXORW(unsigned Opcode);
1356bool isLIDTW(unsigned Opcode);
1357bool isPMULHW(unsigned Opcode);
1358bool isVAESENCLAST(unsigned Opcode);
1359bool isVINSERTI32X8(unsigned Opcode);
1360bool isVRCPPS(unsigned Opcode);
1361bool isVRSQRTBF16(unsigned Opcode);
1362bool isVGATHERQPS(unsigned Opcode);
1363bool isCTESTCC(unsigned Opcode);
1364bool isPMADDWD(unsigned Opcode);
1365bool isUCOMISS(unsigned Opcode);
1366bool isXGETBV(unsigned Opcode);
1367bool isVCVTPD2QQ(unsigned Opcode);
1368bool isVGETEXPPS(unsigned Opcode);
1369bool isFISTP(unsigned Opcode);
1370bool isVINSERTF64X4(unsigned Opcode);
1371bool isVMOVDQU16(unsigned Opcode);
1372bool isVFMADD132PH(unsigned Opcode);
1373bool isVFMSUBADD213PS(unsigned Opcode);
1374bool isVMOVDQU32(unsigned Opcode);
1375bool isFUCOM(unsigned Opcode);
1376bool isVFNMADD213BF16(unsigned Opcode);
1377bool isHADDPS(unsigned Opcode);
1378bool isCMP(unsigned Opcode);
1379bool isCVTTPS2PI(unsigned Opcode);
1380bool isIRETQ(unsigned Opcode);
1381bool isPF2IW(unsigned Opcode);
1382bool isPSHUFD(unsigned Opcode);
1383bool isVDPPD(unsigned Opcode);
1384bool isPSHUFHW(unsigned Opcode);
1385bool isRMPADJUST(unsigned Opcode);
1386bool isPI2FW(unsigned Opcode);
1387bool isVCVTTPH2QQ(unsigned Opcode);
1388bool isDIVPD(unsigned Opcode);
1389bool isCLFLUSH(unsigned Opcode);
1390bool isVPMINUW(unsigned Opcode);
1391bool isIN(unsigned Opcode);
1392bool isWRPKRU(unsigned Opcode);
1393bool isINSERTPS(unsigned Opcode);
1394bool isAAM(unsigned Opcode);
1395bool isVPHADDUDQ(unsigned Opcode);
1396bool isVSHA512MSG1(unsigned Opcode);
1397bool isDIVPS(unsigned Opcode);
1398bool isKNOTB(unsigned Opcode);
1399bool isBLSFILL(unsigned Opcode);
1400bool isVPCMPGTQ(unsigned Opcode);
1401bool isMINSD(unsigned Opcode);
1402bool isFPREM(unsigned Opcode);
1403bool isVPUNPCKHQDQ(unsigned Opcode);
1404bool isMINPD(unsigned Opcode);
1405bool isVCVTTPD2QQ(unsigned Opcode);
1406bool isVFMSUBPD(unsigned Opcode);
1407bool isV4FMADDSS(unsigned Opcode);
1408bool isCPUID(unsigned Opcode);
1409bool isSETCC(unsigned Opcode);
1410bool isVPDPWUUD(unsigned Opcode);
1411bool isVCVTTPS2IUBS(unsigned Opcode);
1412bool isPMOVSXDQ(unsigned Opcode);
1413bool isMWAIT(unsigned Opcode);
1414bool isVPEXTRB(unsigned Opcode);
1415bool isINVVPID(unsigned Opcode);
1416bool isVPSHUFD(unsigned Opcode);
1417bool isVMINBF16(unsigned Opcode);
1418bool isMOVLPS(unsigned Opcode);
1419bool isVBLENDMPS(unsigned Opcode);
1420bool isPMULLW(unsigned Opcode);
1421bool isVCVTSH2SI(unsigned Opcode);
1422bool isVPMOVSXWQ(unsigned Opcode);
1423bool isFNSTENV(unsigned Opcode);
1424bool isVCVT2PH2BF8(unsigned Opcode);
1425bool isVPERMI2PD(unsigned Opcode);
1426bool isMAXSS(unsigned Opcode);
1427bool isCWDE(unsigned Opcode);
1428bool isVBROADCASTI32X8(unsigned Opcode);
1429bool isINT(unsigned Opcode);
1430bool isENCLS(unsigned Opcode);
1431bool isMOVNTQ(unsigned Opcode);
1432bool isVDIVSH(unsigned Opcode);
1433bool isMOVHLPS(unsigned Opcode);
1434bool isVPMASKMOVD(unsigned Opcode);
1435bool isVMOVSD(unsigned Opcode);
1436bool isVPMINUD(unsigned Opcode);
1437bool isVPCMPISTRM(unsigned Opcode);
1438bool isVGETMANTSD(unsigned Opcode);
1439bool isKSHIFTRW(unsigned Opcode);
1440bool isAESDECLAST(unsigned Opcode);
1441bool isVFNMSUB231BF16(unsigned Opcode);
1442bool isVMPTRST(unsigned Opcode);
1443bool isLLDT(unsigned Opcode);
1444bool isVPTESTMB(unsigned Opcode);
1445bool isMOVSB(unsigned Opcode);
1446bool isTILELOADD(unsigned Opcode);
1447bool isKTESTB(unsigned Opcode);
1448bool isMOVUPD(unsigned Opcode);
1449bool isLKGS(unsigned Opcode);
1450bool isSGDTW(unsigned Opcode);
1451bool isDIVSS(unsigned Opcode);
1452bool isPUNPCKHQDQ(unsigned Opcode);
1453bool isVFMADD213SD(unsigned Opcode);
1454bool isKXORD(unsigned Opcode);
1455bool isVPMOVB2M(unsigned Opcode);
1456bool isVMREAD(unsigned Opcode);
1457bool isVPDPWSSDS(unsigned Opcode);
1458bool isTILERELEASE(unsigned Opcode);
1459bool isVUCOMXSH(unsigned Opcode);
1460bool isCLFLUSHOPT(unsigned Opcode);
1461bool isDAS(unsigned Opcode);
1462bool isVSCALEFPH(unsigned Opcode);
1463bool isVSUBSD(unsigned Opcode);
1464bool isVCOMISS(unsigned Opcode);
1465bool isVMULBF16(unsigned Opcode);
1466bool isORPS(unsigned Opcode);
1467bool isTDPFP16PS(unsigned Opcode);
1468bool isVMAXPD(unsigned Opcode);
1469bool isVPMOVWB(unsigned Opcode);
1470bool isVEXP2PS(unsigned Opcode);
1471bool isVPGATHERDQ(unsigned Opcode);
1472bool isVPSRAVQ(unsigned Opcode);
1473bool isPCMPISTRI(unsigned Opcode);
1474bool isVFMSUB231PD(unsigned Opcode);
1475bool isRDMSR(unsigned Opcode);
1476bool isKORTESTD(unsigned Opcode);
1477bool isVPBLENDMW(unsigned Opcode);
1478bool isPSHUFB(unsigned Opcode);
1479bool isVDPBF16PS(unsigned Opcode);
1480bool isTDPBF16PS(unsigned Opcode);
1481bool isFCMOVE(unsigned Opcode);
1482bool isVFMADD231BF16(unsigned Opcode);
1483bool isCMPSS(unsigned Opcode);
1484bool isMASKMOVDQU(unsigned Opcode);
1485bool isVPDPWUSDS(unsigned Opcode);
1486bool isSARX(unsigned Opcode);
1487bool isSGDT(unsigned Opcode);
1488bool isVFMULCPH(unsigned Opcode);
1489bool isURDMSR(unsigned Opcode);
1490bool isKUNPCKWD(unsigned Opcode);
1491bool isVSCALEFBF16(unsigned Opcode);
1492bool isCVTPS2PD(unsigned Opcode);
1493bool isFBSTP(unsigned Opcode);
1494bool isPSUBQ(unsigned Opcode);
1495bool isFXSAVE64(unsigned Opcode);
1496bool isKMOVW(unsigned Opcode);
1497bool isBTS(unsigned Opcode);
1498bool isVPHADDBQ(unsigned Opcode);
1499bool isFRSTOR(unsigned Opcode);
1500bool isVFMSUB132PD(unsigned Opcode);
1501bool isPMULLD(unsigned Opcode);
1502bool isSHA1MSG2(unsigned Opcode);
1503bool isJECXZ(unsigned Opcode);
1504bool isVCVTUDQ2PS(unsigned Opcode);
1505bool isAESENC(unsigned Opcode);
1506bool isVMINMAXPS(unsigned Opcode);
1507bool isPSIGNW(unsigned Opcode);
1508bool isUNPCKLPD(unsigned Opcode);
1509bool isPUSHP(unsigned Opcode);
1510bool isBLSI(unsigned Opcode);
1511bool isVPTESTNMB(unsigned Opcode);
1512bool isWRUSSQ(unsigned Opcode);
1513bool isVGF2P8MULB(unsigned Opcode);
1514bool isVPUNPCKLBW(unsigned Opcode);
1515bool isVRANGESD(unsigned Opcode);
1516bool isCLD(unsigned Opcode);
1517bool isVSCALEFPD(unsigned Opcode);
1518bool isVCOMXSS(unsigned Opcode);
1519bool isVPERMQ(unsigned Opcode);
1520bool isVPSHLDVW(unsigned Opcode);
1521bool isROR(unsigned Opcode);
1522bool isVFMADDSUB132PH(unsigned Opcode);
1523bool isDEC(unsigned Opcode);
1524bool isVGETEXPSH(unsigned Opcode);
1525bool isAESDEC(unsigned Opcode);
1526bool isKORD(unsigned Opcode);
1527bool isVPMULHW(unsigned Opcode);
1528bool isTILELOADDT1(unsigned Opcode);
1529bool isVMASKMOVPS(unsigned Opcode);
1530bool isPMOVZXDQ(unsigned Opcode);
1531bool isVCVTPS2PH(unsigned Opcode);
1532bool isCVTDQ2PD(unsigned Opcode);
1533bool isVCVTSD2SS(unsigned Opcode);
1534bool isVFMSUB213PH(unsigned Opcode);
1535bool isVPROTB(unsigned Opcode);
1536bool isPINSRD(unsigned Opcode);
1537bool isVMXON(unsigned Opcode);
1538bool isVFCMULCSH(unsigned Opcode);
1539bool isVFMULCSH(unsigned Opcode);
1540bool isVRANGEPD(unsigned Opcode);
1541bool isCMC(unsigned Opcode);
1542bool isVFNMADD231BF16(unsigned Opcode);
1543bool isSHA256MSG1(unsigned Opcode);
1544bool isFLD1(unsigned Opcode);
1545bool isCMPPS(unsigned Opcode);
1546bool isVPAVGW(unsigned Opcode);
1547bool isVFMADD213SH(unsigned Opcode);
1548bool isTTDPFP16PS(unsigned Opcode);
1549bool isVPINSRQ(unsigned Opcode);
1550bool isMOVABS(unsigned Opcode);
1551bool isVPSHAQ(unsigned Opcode);
1552bool isRDTSCP(unsigned Opcode);
1553bool isVFNMADD231SS(unsigned Opcode);
1554bool isTEST(unsigned Opcode);
1555bool isVPERMD(unsigned Opcode);
1556bool isVBCSTNESH2PS(unsigned Opcode);
1557bool isVGATHERPF0QPD(unsigned Opcode);
1558bool isVPERM2I128(unsigned Opcode);
1559bool isVMPSADBW(unsigned Opcode);
1560bool isVFNMSUB231PD(unsigned Opcode);
1561bool isPADDSB(unsigned Opcode);
1562bool isMWAITX(unsigned Opcode);
1563bool isMONITORX(unsigned Opcode);
1564bool isVPEXPANDD(unsigned Opcode);
1565bool isVFRCZPD(unsigned Opcode);
1566bool isVRCPPH(unsigned Opcode);
1567bool isFEMMS(unsigned Opcode);
1568bool isVSCATTERQPD(unsigned Opcode);
1569bool isVMOVW(unsigned Opcode);
1570bool isVPBROADCASTD(unsigned Opcode);
1571bool isSTOSB(unsigned Opcode);
1572bool isFUCOMI(unsigned Opcode);
1573bool isVBROADCASTI64X4(unsigned Opcode);
1574bool isFCMOVU(unsigned Opcode);
1575bool isPSHUFLW(unsigned Opcode);
1576bool isCVTPI2PS(unsigned Opcode);
1577bool isVCVTTPD2UDQS(unsigned Opcode);
1578bool isSYSCALL(unsigned Opcode);
1579bool isVFMADD231SH(unsigned Opcode);
1580bool isPMOVZXBW(unsigned Opcode);
1581bool isVPOPCNTB(unsigned Opcode);
1582bool isVCVTDQ2PS(unsigned Opcode);
1583bool isPSUBD(unsigned Opcode);
1584bool isVPCMPEQW(unsigned Opcode);
1585bool isMOVSW(unsigned Opcode);
1586bool isVSM3RNDS2(unsigned Opcode);
1587bool isVPMOVUSQD(unsigned Opcode);
1588bool isCVTTPD2DQ(unsigned Opcode);
1589bool isVPEXPANDW(unsigned Opcode);
1590bool isVUCOMISH(unsigned Opcode);
1591bool isVZEROALL(unsigned Opcode);
1592bool isVPAND(unsigned Opcode);
1593bool isPMULDQ(unsigned Opcode);
1594bool isVPSHUFHW(unsigned Opcode);
1595bool isVPALIGNR(unsigned Opcode);
1596bool isSQRTSD(unsigned Opcode);
1597bool isVCVTTPH2UDQ(unsigned Opcode);
1598bool isVGETEXPPH(unsigned Opcode);
1599bool isADDPD(unsigned Opcode);
1600bool isVFNMADDPD(unsigned Opcode);
1601bool isSTTILECFG(unsigned Opcode);
1602bool isVMINPD(unsigned Opcode);
1603bool isSHA1RNDS4(unsigned Opcode);
1604bool isPBLENDVB(unsigned Opcode);
1605bool isVBROADCASTF128(unsigned Opcode);
1606bool isVPSHRDQ(unsigned Opcode);
1607bool isVAESIMC(unsigned Opcode);
1608bool isCOMISD(unsigned Opcode);
1609bool isVMOVSH(unsigned Opcode);
1610bool isPFSUBR(unsigned Opcode);
1611bool isRDSSPD(unsigned Opcode);
1612bool isWAIT(unsigned Opcode);
1613bool isVFPCLASSSS(unsigned Opcode);
1614bool isPCMPGTD(unsigned Opcode);
1615bool isVGATHERPF0QPS(unsigned Opcode);
1616bool isBLENDVPS(unsigned Opcode);
1617bool isVBROADCASTF32X4(unsigned Opcode);
1618bool isVPMADD52LUQ(unsigned Opcode);
1619bool isVMOVLPD(unsigned Opcode);
1620bool isVMOVQ(unsigned Opcode);
1621bool isVMOVDQU(unsigned Opcode);
1622bool isAESENC128KL(unsigned Opcode);
1623bool isVFMADDSUB231PS(unsigned Opcode);
1624bool isVFNMSUB213PD(unsigned Opcode);
1625bool isVPCONFLICTD(unsigned Opcode);
1626bool isVFMADDSUB213PH(unsigned Opcode);
1627bool isVPHSUBSW(unsigned Opcode);
1628bool isPUNPCKHDQ(unsigned Opcode);
1629bool isVSHUFI64X2(unsigned Opcode);
1630bool isVFMSUBSD(unsigned Opcode);
1631bool isVPORD(unsigned Opcode);
1632bool isRCPPS(unsigned Opcode);
1633bool isVEXTRACTI128(unsigned Opcode);
1634bool isVCVT2PH2BF8S(unsigned Opcode);
1635bool isVPSHRDVW(unsigned Opcode);
1636bool isVUNPCKLPD(unsigned Opcode);
1637bool isVPSRAVD(unsigned Opcode);
1638bool isVMULSH(unsigned Opcode);
1639bool isMOVNTSS(unsigned Opcode);
1640bool isSTI(unsigned Opcode);
1641bool isVSM4RNDS4(unsigned Opcode);
1642bool isVMCLEAR(unsigned Opcode);
1643bool isVPMADD52HUQ(unsigned Opcode);
1644bool isLIDT(unsigned Opcode);
1645bool isPUSH2(unsigned Opcode);
1646bool isVCVTPS2IUBS(unsigned Opcode);
1647bool isRDPKRU(unsigned Opcode);
1648bool isVPCMPB(unsigned Opcode);
1649bool isVFMSUB231BF16(unsigned Opcode);
1650bool isFINCSTP(unsigned Opcode);
1651bool isKORQ(unsigned Opcode);
1652bool isXCRYPTCBC(unsigned Opcode);
1653bool isRDPMC(unsigned Opcode);
1654bool isMOVMSKPD(unsigned Opcode);
1655bool isVFMSUB231SH(unsigned Opcode);
1656bool isVEXTRACTF128(unsigned Opcode);
1657bool isVPSHLB(unsigned Opcode);
1658bool isXSAVES64(unsigned Opcode);
1659bool isSHL(unsigned Opcode);
1660bool isAXOR(unsigned Opcode);
1661bool isVINSERTI64X2(unsigned Opcode);
1662bool isSYSRETQ(unsigned Opcode);
1663bool isVSCATTERPF0QPD(unsigned Opcode);
1664bool isVFMSUB213SH(unsigned Opcode);
1665bool isVPMOVQW(unsigned Opcode);
1666bool isVREDUCEPD(unsigned Opcode);
1667bool isNOT(unsigned Opcode);
1668bool isLWPINS(unsigned Opcode);
1669bool isVSCATTERDPS(unsigned Opcode);
1670bool isVPMOVM2W(unsigned Opcode);
1671bool isVFNMADD132PS(unsigned Opcode);
1672bool isMOVNTPS(unsigned Opcode);
1673bool isVRSQRTSS(unsigned Opcode);
1674bool isKMOVB(unsigned Opcode);
1675bool isCVTSD2SS(unsigned Opcode);
1676bool isVBROADCASTF64X2(unsigned Opcode);
1677bool isMOVNTPD(unsigned Opcode);
1678bool isMAXSD(unsigned Opcode);
1679bool isCMPPD(unsigned Opcode);
1680bool isVPCMPESTRM(unsigned Opcode);
1681bool isVFMSUB132PS(unsigned Opcode);
1682bool isVCOMISH(unsigned Opcode);
1683bool isF2XM1(unsigned Opcode);
1684bool isVDIVBF16(unsigned Opcode);
1685bool isSQRTPD(unsigned Opcode);
1686bool isVFMSUBADDPS(unsigned Opcode);
1687bool isFXTRACT(unsigned Opcode);
1688bool isVP4DPWSSD(unsigned Opcode);
1689bool isTDPBHF8PS(unsigned Opcode);
1690bool isVFMSUBADDPD(unsigned Opcode);
1691bool isVBCSTNEBF162PS(unsigned Opcode);
1692bool isVPGATHERQQ(unsigned Opcode);
1693bool isPCMPEQB(unsigned Opcode);
1694bool isTILESTORED(unsigned Opcode);
1695bool isBLSMSK(unsigned Opcode);
1696bool isVCVTTPS2DQ(unsigned Opcode);
1697bool isVRNDSCALEPD(unsigned Opcode);
1698bool isVFPCLASSBF16(unsigned Opcode);
1699bool isVMLOAD(unsigned Opcode);
1700bool isVPTERNLOGQ(unsigned Opcode);
1701bool isKXNORD(unsigned Opcode);
1702bool isFXSAVE(unsigned Opcode);
1703bool isVUNPCKHPD(unsigned Opcode);
1704bool isCVTPS2DQ(unsigned Opcode);
1705bool isTMMULTF32PS(unsigned Opcode);
1706bool isVFMSUB213SS(unsigned Opcode);
1707bool isVPOPCNTD(unsigned Opcode);
1708bool isSALC(unsigned Opcode);
1709bool isV4FNMADDSS(unsigned Opcode);
1710bool isXCRYPTOFB(unsigned Opcode);
1711bool isVORPD(unsigned Opcode);
1712bool isLSL(unsigned Opcode);
1713bool isXCRYPTCFB(unsigned Opcode);
1714bool isVGETEXPSS(unsigned Opcode);
1715bool isPSLLDQ(unsigned Opcode);
1716bool isVPDPBUUD(unsigned Opcode);
1717bool isVMXOFF(unsigned Opcode);
1718bool isBLSIC(unsigned Opcode);
1719bool isMOVLHPS(unsigned Opcode);
1720bool isVMOVRSQ(unsigned Opcode);
1721bool isVFNMSUBSD(unsigned Opcode);
1722bool isVCVTPH2IUBS(unsigned Opcode);
1723bool isVFPCLASSSH(unsigned Opcode);
1724bool isVPSHLQ(unsigned Opcode);
1725bool isVROUNDPS(unsigned Opcode);
1726bool isVSCATTERPF0QPS(unsigned Opcode);
1727bool isERETS(unsigned Opcode);
1728bool isVPERMI2D(unsigned Opcode);
1729bool isFUCOMP(unsigned Opcode);
1730bool isVCVTTPS2QQ(unsigned Opcode);
1731bool isPUSHFD(unsigned Opcode);
1732bool isKORB(unsigned Opcode);
1733bool isVRCP28PD(unsigned Opcode);
1734bool isVPABSD(unsigned Opcode);
1735bool isVROUNDSS(unsigned Opcode);
1736bool isVCVTSD2USI(unsigned Opcode);
1737bool isVPABSB(unsigned Opcode);
1738bool isPMAXUD(unsigned Opcode);
1739bool isVPMULHUW(unsigned Opcode);
1740bool isVPERMPD(unsigned Opcode);
1741bool isFCHS(unsigned Opcode);
1742bool isVPBLENDMB(unsigned Opcode);
1743bool isVGETMANTSS(unsigned Opcode);
1744bool isVPSLLW(unsigned Opcode);
1745bool isVDIVPD(unsigned Opcode);
1746bool isBLCMSK(unsigned Opcode);
1747bool isFDIV(unsigned Opcode);
1748bool isRSQRTSS(unsigned Opcode);
1749bool isPOR(unsigned Opcode);
1750bool isVMOVDQA32(unsigned Opcode);
1751bool isVPHADDUWQ(unsigned Opcode);
1752bool isPSRAD(unsigned Opcode);
1753bool isPREFETCHW(unsigned Opcode);
1754bool isFIDIVR(unsigned Opcode);
1755bool isMOVHPS(unsigned Opcode);
1756bool isVFNMSUB231PH(unsigned Opcode);
1757bool isUNPCKLPS(unsigned Opcode);
1758bool isVPSIGNB(unsigned Opcode);
1759bool isSAVEPREVSSP(unsigned Opcode);
1760bool isVSCALEFSD(unsigned Opcode);
1761bool isFSIN(unsigned Opcode);
1762bool isSCASQ(unsigned Opcode);
1763bool isVCVTTPD2QQS(unsigned Opcode);
1764bool isPCMPGTW(unsigned Opcode);
1765bool isMULX(unsigned Opcode);
1766bool isVPMAXUW(unsigned Opcode);
1767bool isPAUSE(unsigned Opcode);
1768bool isMOVQ2DQ(unsigned Opcode);
1769bool isVPSUBQ(unsigned Opcode);
1770bool isVPABSW(unsigned Opcode);
1771bool isVPCOMPRESSD(unsigned Opcode);
1772bool isVPMOVUSQW(unsigned Opcode);
1773bool isBLENDVPD(unsigned Opcode);
1774bool isVFNMADD132BF16(unsigned Opcode);
1775bool isVPMOVQB(unsigned Opcode);
1776bool isVBLENDVPS(unsigned Opcode);
1777bool isKSHIFTLQ(unsigned Opcode);
1778bool isPMOVSXWD(unsigned Opcode);
1779bool isPHSUBSW(unsigned Opcode);
1780bool isPSRLQ(unsigned Opcode);
1781bool isVCVTPH2DQ(unsigned Opcode);
1782bool isFISUB(unsigned Opcode);
1783bool isVCVTPS2UDQ(unsigned Opcode);
1784bool isVMOVDDUP(unsigned Opcode);
1785bool isPCMPEQD(unsigned Opcode);
1786bool isVRSQRT28SD(unsigned Opcode);
1787bool isTDPHBF8PS(unsigned Opcode);
1788bool isLODSW(unsigned Opcode);
1789bool isVPOPCNTQ(unsigned Opcode);
1790bool isKSHIFTRB(unsigned Opcode);
1791bool isVFNMADDPS(unsigned Opcode);
1792bool isCCMPCC(unsigned Opcode);
1793bool isFXRSTOR64(unsigned Opcode);
1794bool isVFMSUBADD213PD(unsigned Opcode);
1795bool isVSQRTPH(unsigned Opcode);
1796bool isPOPF(unsigned Opcode);
1797bool isVPSUBUSB(unsigned Opcode);
1798bool isTCVTROWPS2BF16L(unsigned Opcode);
1799bool isPREFETCHIT1(unsigned Opcode);
1800bool isVPADDSW(unsigned Opcode);
1801bool isVADDSUBPD(unsigned Opcode);
1802bool isKANDD(unsigned Opcode);
1803bool isOUTSB(unsigned Opcode);
1804bool isPREFETCHRST2(unsigned Opcode);
1805bool isFNSTSW(unsigned Opcode);
1806bool isPMINSB(unsigned Opcode);
1807#endif // GET_X86_MNEMONIC_TABLES_H
1808
1809#ifdef GET_X86_MNEMONIC_TABLES_CPP
1810#undef GET_X86_MNEMONIC_TABLES_CPP
1811
1812bool isFSUBRP(unsigned Opcode) {
1813 return Opcode == SUBR_FPrST0;
1814}
1815
1816bool isVPDPBUSDS(unsigned Opcode) {
1817 switch (Opcode) {
1818 case VPDPBUSDSYrm:
1819 case VPDPBUSDSYrr:
1820 case VPDPBUSDSZ128m:
1821 case VPDPBUSDSZ128mb:
1822 case VPDPBUSDSZ128mbk:
1823 case VPDPBUSDSZ128mbkz:
1824 case VPDPBUSDSZ128mk:
1825 case VPDPBUSDSZ128mkz:
1826 case VPDPBUSDSZ128r:
1827 case VPDPBUSDSZ128rk:
1828 case VPDPBUSDSZ128rkz:
1829 case VPDPBUSDSZ256m:
1830 case VPDPBUSDSZ256mb:
1831 case VPDPBUSDSZ256mbk:
1832 case VPDPBUSDSZ256mbkz:
1833 case VPDPBUSDSZ256mk:
1834 case VPDPBUSDSZ256mkz:
1835 case VPDPBUSDSZ256r:
1836 case VPDPBUSDSZ256rk:
1837 case VPDPBUSDSZ256rkz:
1838 case VPDPBUSDSZm:
1839 case VPDPBUSDSZmb:
1840 case VPDPBUSDSZmbk:
1841 case VPDPBUSDSZmbkz:
1842 case VPDPBUSDSZmk:
1843 case VPDPBUSDSZmkz:
1844 case VPDPBUSDSZr:
1845 case VPDPBUSDSZrk:
1846 case VPDPBUSDSZrkz:
1847 case VPDPBUSDSrm:
1848 case VPDPBUSDSrr:
1849 return true;
1850 }
1851 return false;
1852}
1853
1854bool isPUNPCKLWD(unsigned Opcode) {
1855 switch (Opcode) {
1856 case MMX_PUNPCKLWDrm:
1857 case MMX_PUNPCKLWDrr:
1858 case PUNPCKLWDrm:
1859 case PUNPCKLWDrr:
1860 return true;
1861 }
1862 return false;
1863}
1864
1865bool isVREDUCEBF16(unsigned Opcode) {
1866 switch (Opcode) {
1867 case VREDUCEBF16Z128rmbi:
1868 case VREDUCEBF16Z128rmbik:
1869 case VREDUCEBF16Z128rmbikz:
1870 case VREDUCEBF16Z128rmi:
1871 case VREDUCEBF16Z128rmik:
1872 case VREDUCEBF16Z128rmikz:
1873 case VREDUCEBF16Z128rri:
1874 case VREDUCEBF16Z128rrik:
1875 case VREDUCEBF16Z128rrikz:
1876 case VREDUCEBF16Z256rmbi:
1877 case VREDUCEBF16Z256rmbik:
1878 case VREDUCEBF16Z256rmbikz:
1879 case VREDUCEBF16Z256rmi:
1880 case VREDUCEBF16Z256rmik:
1881 case VREDUCEBF16Z256rmikz:
1882 case VREDUCEBF16Z256rri:
1883 case VREDUCEBF16Z256rrik:
1884 case VREDUCEBF16Z256rrikz:
1885 case VREDUCEBF16Zrmbi:
1886 case VREDUCEBF16Zrmbik:
1887 case VREDUCEBF16Zrmbikz:
1888 case VREDUCEBF16Zrmi:
1889 case VREDUCEBF16Zrmik:
1890 case VREDUCEBF16Zrmikz:
1891 case VREDUCEBF16Zrri:
1892 case VREDUCEBF16Zrrik:
1893 case VREDUCEBF16Zrrikz:
1894 return true;
1895 }
1896 return false;
1897}
1898
1899bool isPUNPCKLQDQ(unsigned Opcode) {
1900 switch (Opcode) {
1901 case PUNPCKLQDQrm:
1902 case PUNPCKLQDQrr:
1903 return true;
1904 }
1905 return false;
1906}
1907
1908bool isRDFSBASE(unsigned Opcode) {
1909 switch (Opcode) {
1910 case RDFSBASE:
1911 case RDFSBASE64:
1912 return true;
1913 }
1914 return false;
1915}
1916
1917bool isVPCMOV(unsigned Opcode) {
1918 switch (Opcode) {
1919 case VPCMOVYrmr:
1920 case VPCMOVYrrm:
1921 case VPCMOVYrrr:
1922 case VPCMOVYrrr_REV:
1923 case VPCMOVrmr:
1924 case VPCMOVrrm:
1925 case VPCMOVrrr:
1926 case VPCMOVrrr_REV:
1927 return true;
1928 }
1929 return false;
1930}
1931
1932bool isVDIVSD(unsigned Opcode) {
1933 switch (Opcode) {
1934 case VDIVSDZrm_Int:
1935 case VDIVSDZrmk_Int:
1936 case VDIVSDZrmkz_Int:
1937 case VDIVSDZrr_Int:
1938 case VDIVSDZrrb_Int:
1939 case VDIVSDZrrbk_Int:
1940 case VDIVSDZrrbkz_Int:
1941 case VDIVSDZrrk_Int:
1942 case VDIVSDZrrkz_Int:
1943 case VDIVSDrm_Int:
1944 case VDIVSDrr_Int:
1945 return true;
1946 }
1947 return false;
1948}
1949
1950bool isVCVTTPS2IBS(unsigned Opcode) {
1951 switch (Opcode) {
1952 case VCVTTPS2IBSZ128rm:
1953 case VCVTTPS2IBSZ128rmb:
1954 case VCVTTPS2IBSZ128rmbk:
1955 case VCVTTPS2IBSZ128rmbkz:
1956 case VCVTTPS2IBSZ128rmk:
1957 case VCVTTPS2IBSZ128rmkz:
1958 case VCVTTPS2IBSZ128rr:
1959 case VCVTTPS2IBSZ128rrk:
1960 case VCVTTPS2IBSZ128rrkz:
1961 case VCVTTPS2IBSZ256rm:
1962 case VCVTTPS2IBSZ256rmb:
1963 case VCVTTPS2IBSZ256rmbk:
1964 case VCVTTPS2IBSZ256rmbkz:
1965 case VCVTTPS2IBSZ256rmk:
1966 case VCVTTPS2IBSZ256rmkz:
1967 case VCVTTPS2IBSZ256rr:
1968 case VCVTTPS2IBSZ256rrk:
1969 case VCVTTPS2IBSZ256rrkz:
1970 case VCVTTPS2IBSZrm:
1971 case VCVTTPS2IBSZrmb:
1972 case VCVTTPS2IBSZrmbk:
1973 case VCVTTPS2IBSZrmbkz:
1974 case VCVTTPS2IBSZrmk:
1975 case VCVTTPS2IBSZrmkz:
1976 case VCVTTPS2IBSZrr:
1977 case VCVTTPS2IBSZrrb:
1978 case VCVTTPS2IBSZrrbk:
1979 case VCVTTPS2IBSZrrbkz:
1980 case VCVTTPS2IBSZrrk:
1981 case VCVTTPS2IBSZrrkz:
1982 return true;
1983 }
1984 return false;
1985}
1986
1987bool isVPEXTRW(unsigned Opcode) {
1988 switch (Opcode) {
1989 case VPEXTRWZmri:
1990 case VPEXTRWZrri:
1991 case VPEXTRWZrri_REV:
1992 case VPEXTRWmri:
1993 case VPEXTRWrri:
1994 case VPEXTRWrri_REV:
1995 return true;
1996 }
1997 return false;
1998}
1999
2000bool isLODSD(unsigned Opcode) {
2001 return Opcode == LODSL;
2002}
2003
2004bool isVPTESTNMQ(unsigned Opcode) {
2005 switch (Opcode) {
2006 case VPTESTNMQZ128rm:
2007 case VPTESTNMQZ128rmb:
2008 case VPTESTNMQZ128rmbk:
2009 case VPTESTNMQZ128rmk:
2010 case VPTESTNMQZ128rr:
2011 case VPTESTNMQZ128rrk:
2012 case VPTESTNMQZ256rm:
2013 case VPTESTNMQZ256rmb:
2014 case VPTESTNMQZ256rmbk:
2015 case VPTESTNMQZ256rmk:
2016 case VPTESTNMQZ256rr:
2017 case VPTESTNMQZ256rrk:
2018 case VPTESTNMQZrm:
2019 case VPTESTNMQZrmb:
2020 case VPTESTNMQZrmbk:
2021 case VPTESTNMQZrmk:
2022 case VPTESTNMQZrr:
2023 case VPTESTNMQZrrk:
2024 return true;
2025 }
2026 return false;
2027}
2028
2029bool isCVTSS2SD(unsigned Opcode) {
2030 switch (Opcode) {
2031 case CVTSS2SDrm_Int:
2032 case CVTSS2SDrr_Int:
2033 return true;
2034 }
2035 return false;
2036}
2037
2038bool isVGETMANTPD(unsigned Opcode) {
2039 switch (Opcode) {
2040 case VGETMANTPDZ128rmbi:
2041 case VGETMANTPDZ128rmbik:
2042 case VGETMANTPDZ128rmbikz:
2043 case VGETMANTPDZ128rmi:
2044 case VGETMANTPDZ128rmik:
2045 case VGETMANTPDZ128rmikz:
2046 case VGETMANTPDZ128rri:
2047 case VGETMANTPDZ128rrik:
2048 case VGETMANTPDZ128rrikz:
2049 case VGETMANTPDZ256rmbi:
2050 case VGETMANTPDZ256rmbik:
2051 case VGETMANTPDZ256rmbikz:
2052 case VGETMANTPDZ256rmi:
2053 case VGETMANTPDZ256rmik:
2054 case VGETMANTPDZ256rmikz:
2055 case VGETMANTPDZ256rri:
2056 case VGETMANTPDZ256rrik:
2057 case VGETMANTPDZ256rrikz:
2058 case VGETMANTPDZrmbi:
2059 case VGETMANTPDZrmbik:
2060 case VGETMANTPDZrmbikz:
2061 case VGETMANTPDZrmi:
2062 case VGETMANTPDZrmik:
2063 case VGETMANTPDZrmikz:
2064 case VGETMANTPDZrri:
2065 case VGETMANTPDZrrib:
2066 case VGETMANTPDZrribk:
2067 case VGETMANTPDZrribkz:
2068 case VGETMANTPDZrrik:
2069 case VGETMANTPDZrrikz:
2070 return true;
2071 }
2072 return false;
2073}
2074
2075bool isVMOVDQA64(unsigned Opcode) {
2076 switch (Opcode) {
2077 case VMOVDQA64Z128mr:
2078 case VMOVDQA64Z128mrk:
2079 case VMOVDQA64Z128rm:
2080 case VMOVDQA64Z128rmk:
2081 case VMOVDQA64Z128rmkz:
2082 case VMOVDQA64Z128rr:
2083 case VMOVDQA64Z128rr_REV:
2084 case VMOVDQA64Z128rrk:
2085 case VMOVDQA64Z128rrk_REV:
2086 case VMOVDQA64Z128rrkz:
2087 case VMOVDQA64Z128rrkz_REV:
2088 case VMOVDQA64Z256mr:
2089 case VMOVDQA64Z256mrk:
2090 case VMOVDQA64Z256rm:
2091 case VMOVDQA64Z256rmk:
2092 case VMOVDQA64Z256rmkz:
2093 case VMOVDQA64Z256rr:
2094 case VMOVDQA64Z256rr_REV:
2095 case VMOVDQA64Z256rrk:
2096 case VMOVDQA64Z256rrk_REV:
2097 case VMOVDQA64Z256rrkz:
2098 case VMOVDQA64Z256rrkz_REV:
2099 case VMOVDQA64Zmr:
2100 case VMOVDQA64Zmrk:
2101 case VMOVDQA64Zrm:
2102 case VMOVDQA64Zrmk:
2103 case VMOVDQA64Zrmkz:
2104 case VMOVDQA64Zrr:
2105 case VMOVDQA64Zrr_REV:
2106 case VMOVDQA64Zrrk:
2107 case VMOVDQA64Zrrk_REV:
2108 case VMOVDQA64Zrrkz:
2109 case VMOVDQA64Zrrkz_REV:
2110 return true;
2111 }
2112 return false;
2113}
2114
2115bool isINVLPG(unsigned Opcode) {
2116 return Opcode == INVLPG;
2117}
2118
2119bool isVGETEXPBF16(unsigned Opcode) {
2120 switch (Opcode) {
2121 case VGETEXPBF16Z128m:
2122 case VGETEXPBF16Z128mb:
2123 case VGETEXPBF16Z128mbk:
2124 case VGETEXPBF16Z128mbkz:
2125 case VGETEXPBF16Z128mk:
2126 case VGETEXPBF16Z128mkz:
2127 case VGETEXPBF16Z128r:
2128 case VGETEXPBF16Z128rk:
2129 case VGETEXPBF16Z128rkz:
2130 case VGETEXPBF16Z256m:
2131 case VGETEXPBF16Z256mb:
2132 case VGETEXPBF16Z256mbk:
2133 case VGETEXPBF16Z256mbkz:
2134 case VGETEXPBF16Z256mk:
2135 case VGETEXPBF16Z256mkz:
2136 case VGETEXPBF16Z256r:
2137 case VGETEXPBF16Z256rk:
2138 case VGETEXPBF16Z256rkz:
2139 case VGETEXPBF16Zm:
2140 case VGETEXPBF16Zmb:
2141 case VGETEXPBF16Zmbk:
2142 case VGETEXPBF16Zmbkz:
2143 case VGETEXPBF16Zmk:
2144 case VGETEXPBF16Zmkz:
2145 case VGETEXPBF16Zr:
2146 case VGETEXPBF16Zrk:
2147 case VGETEXPBF16Zrkz:
2148 return true;
2149 }
2150 return false;
2151}
2152
2153bool isVBROADCASTF64X4(unsigned Opcode) {
2154 switch (Opcode) {
2155 case VBROADCASTF64X4Zrm:
2156 case VBROADCASTF64X4Zrmk:
2157 case VBROADCASTF64X4Zrmkz:
2158 return true;
2159 }
2160 return false;
2161}
2162
2163bool isVPERMI2Q(unsigned Opcode) {
2164 switch (Opcode) {
2165 case VPERMI2QZ128rm:
2166 case VPERMI2QZ128rmb:
2167 case VPERMI2QZ128rmbk:
2168 case VPERMI2QZ128rmbkz:
2169 case VPERMI2QZ128rmk:
2170 case VPERMI2QZ128rmkz:
2171 case VPERMI2QZ128rr:
2172 case VPERMI2QZ128rrk:
2173 case VPERMI2QZ128rrkz:
2174 case VPERMI2QZ256rm:
2175 case VPERMI2QZ256rmb:
2176 case VPERMI2QZ256rmbk:
2177 case VPERMI2QZ256rmbkz:
2178 case VPERMI2QZ256rmk:
2179 case VPERMI2QZ256rmkz:
2180 case VPERMI2QZ256rr:
2181 case VPERMI2QZ256rrk:
2182 case VPERMI2QZ256rrkz:
2183 case VPERMI2QZrm:
2184 case VPERMI2QZrmb:
2185 case VPERMI2QZrmbk:
2186 case VPERMI2QZrmbkz:
2187 case VPERMI2QZrmk:
2188 case VPERMI2QZrmkz:
2189 case VPERMI2QZrr:
2190 case VPERMI2QZrrk:
2191 case VPERMI2QZrrkz:
2192 return true;
2193 }
2194 return false;
2195}
2196
2197bool isVPMOVSXBD(unsigned Opcode) {
2198 switch (Opcode) {
2199 case VPMOVSXBDYrm:
2200 case VPMOVSXBDYrr:
2201 case VPMOVSXBDZ128rm:
2202 case VPMOVSXBDZ128rmk:
2203 case VPMOVSXBDZ128rmkz:
2204 case VPMOVSXBDZ128rr:
2205 case VPMOVSXBDZ128rrk:
2206 case VPMOVSXBDZ128rrkz:
2207 case VPMOVSXBDZ256rm:
2208 case VPMOVSXBDZ256rmk:
2209 case VPMOVSXBDZ256rmkz:
2210 case VPMOVSXBDZ256rr:
2211 case VPMOVSXBDZ256rrk:
2212 case VPMOVSXBDZ256rrkz:
2213 case VPMOVSXBDZrm:
2214 case VPMOVSXBDZrmk:
2215 case VPMOVSXBDZrmkz:
2216 case VPMOVSXBDZrr:
2217 case VPMOVSXBDZrrk:
2218 case VPMOVSXBDZrrkz:
2219 case VPMOVSXBDrm:
2220 case VPMOVSXBDrr:
2221 return true;
2222 }
2223 return false;
2224}
2225
2226bool isVFMSUB132SS(unsigned Opcode) {
2227 switch (Opcode) {
2228 case VFMSUB132SSZm_Int:
2229 case VFMSUB132SSZmk_Int:
2230 case VFMSUB132SSZmkz_Int:
2231 case VFMSUB132SSZr_Int:
2232 case VFMSUB132SSZrb_Int:
2233 case VFMSUB132SSZrbk_Int:
2234 case VFMSUB132SSZrbkz_Int:
2235 case VFMSUB132SSZrk_Int:
2236 case VFMSUB132SSZrkz_Int:
2237 case VFMSUB132SSm_Int:
2238 case VFMSUB132SSr_Int:
2239 return true;
2240 }
2241 return false;
2242}
2243
2244bool isVPMOVUSDW(unsigned Opcode) {
2245 switch (Opcode) {
2246 case VPMOVUSDWZ128mr:
2247 case VPMOVUSDWZ128mrk:
2248 case VPMOVUSDWZ128rr:
2249 case VPMOVUSDWZ128rrk:
2250 case VPMOVUSDWZ128rrkz:
2251 case VPMOVUSDWZ256mr:
2252 case VPMOVUSDWZ256mrk:
2253 case VPMOVUSDWZ256rr:
2254 case VPMOVUSDWZ256rrk:
2255 case VPMOVUSDWZ256rrkz:
2256 case VPMOVUSDWZmr:
2257 case VPMOVUSDWZmrk:
2258 case VPMOVUSDWZrr:
2259 case VPMOVUSDWZrrk:
2260 case VPMOVUSDWZrrkz:
2261 return true;
2262 }
2263 return false;
2264}
2265
2266bool isAAD(unsigned Opcode) {
2267 return Opcode == AAD8i8;
2268}
2269
2270bool isIDIV(unsigned Opcode) {
2271 switch (Opcode) {
2272 case IDIV16m:
2273 case IDIV16m_EVEX:
2274 case IDIV16m_NF:
2275 case IDIV16r:
2276 case IDIV16r_EVEX:
2277 case IDIV16r_NF:
2278 case IDIV32m:
2279 case IDIV32m_EVEX:
2280 case IDIV32m_NF:
2281 case IDIV32r:
2282 case IDIV32r_EVEX:
2283 case IDIV32r_NF:
2284 case IDIV64m:
2285 case IDIV64m_EVEX:
2286 case IDIV64m_NF:
2287 case IDIV64r:
2288 case IDIV64r_EVEX:
2289 case IDIV64r_NF:
2290 case IDIV8m:
2291 case IDIV8m_EVEX:
2292 case IDIV8m_NF:
2293 case IDIV8r:
2294 case IDIV8r_EVEX:
2295 case IDIV8r_NF:
2296 return true;
2297 }
2298 return false;
2299}
2300
2301bool isCVTTPS2DQ(unsigned Opcode) {
2302 switch (Opcode) {
2303 case CVTTPS2DQrm:
2304 case CVTTPS2DQrr:
2305 return true;
2306 }
2307 return false;
2308}
2309
2310bool isVBROADCASTF32X8(unsigned Opcode) {
2311 switch (Opcode) {
2312 case VBROADCASTF32X8Zrm:
2313 case VBROADCASTF32X8Zrmk:
2314 case VBROADCASTF32X8Zrmkz:
2315 return true;
2316 }
2317 return false;
2318}
2319
2320bool isVFMSUBSS(unsigned Opcode) {
2321 switch (Opcode) {
2322 case VFMSUBSS4mr:
2323 case VFMSUBSS4rm:
2324 case VFMSUBSS4rr:
2325 case VFMSUBSS4rr_REV:
2326 return true;
2327 }
2328 return false;
2329}
2330
2331bool isEMMS(unsigned Opcode) {
2332 return Opcode == MMX_EMMS;
2333}
2334
2335bool isVPDPBSUD(unsigned Opcode) {
2336 switch (Opcode) {
2337 case VPDPBSUDYrm:
2338 case VPDPBSUDYrr:
2339 case VPDPBSUDZ128m:
2340 case VPDPBSUDZ128mb:
2341 case VPDPBSUDZ128mbk:
2342 case VPDPBSUDZ128mbkz:
2343 case VPDPBSUDZ128mk:
2344 case VPDPBSUDZ128mkz:
2345 case VPDPBSUDZ128r:
2346 case VPDPBSUDZ128rk:
2347 case VPDPBSUDZ128rkz:
2348 case VPDPBSUDZ256m:
2349 case VPDPBSUDZ256mb:
2350 case VPDPBSUDZ256mbk:
2351 case VPDPBSUDZ256mbkz:
2352 case VPDPBSUDZ256mk:
2353 case VPDPBSUDZ256mkz:
2354 case VPDPBSUDZ256r:
2355 case VPDPBSUDZ256rk:
2356 case VPDPBSUDZ256rkz:
2357 case VPDPBSUDZm:
2358 case VPDPBSUDZmb:
2359 case VPDPBSUDZmbk:
2360 case VPDPBSUDZmbkz:
2361 case VPDPBSUDZmk:
2362 case VPDPBSUDZmkz:
2363 case VPDPBSUDZr:
2364 case VPDPBSUDZrk:
2365 case VPDPBSUDZrkz:
2366 case VPDPBSUDrm:
2367 case VPDPBSUDrr:
2368 return true;
2369 }
2370 return false;
2371}
2372
2373bool isPMOVSXWQ(unsigned Opcode) {
2374 switch (Opcode) {
2375 case PMOVSXWQrm:
2376 case PMOVSXWQrr:
2377 return true;
2378 }
2379 return false;
2380}
2381
2382bool isPSRLW(unsigned Opcode) {
2383 switch (Opcode) {
2384 case MMX_PSRLWri:
2385 case MMX_PSRLWrm:
2386 case MMX_PSRLWrr:
2387 case PSRLWri:
2388 case PSRLWrm:
2389 case PSRLWrr:
2390 return true;
2391 }
2392 return false;
2393}
2394
2395bool isMOVNTDQA(unsigned Opcode) {
2396 return Opcode == MOVNTDQArm;
2397}
2398
2399bool isFUCOMPI(unsigned Opcode) {
2400 return Opcode == UCOM_FIPr;
2401}
2402
2403bool isANDNPS(unsigned Opcode) {
2404 switch (Opcode) {
2405 case ANDNPSrm:
2406 case ANDNPSrr:
2407 return true;
2408 }
2409 return false;
2410}
2411
2412bool isVINSERTF64X2(unsigned Opcode) {
2413 switch (Opcode) {
2414 case VINSERTF64X2Z256rmi:
2415 case VINSERTF64X2Z256rmik:
2416 case VINSERTF64X2Z256rmikz:
2417 case VINSERTF64X2Z256rri:
2418 case VINSERTF64X2Z256rrik:
2419 case VINSERTF64X2Z256rrikz:
2420 case VINSERTF64X2Zrmi:
2421 case VINSERTF64X2Zrmik:
2422 case VINSERTF64X2Zrmikz:
2423 case VINSERTF64X2Zrri:
2424 case VINSERTF64X2Zrrik:
2425 case VINSERTF64X2Zrrikz:
2426 return true;
2427 }
2428 return false;
2429}
2430
2431bool isCLTS(unsigned Opcode) {
2432 return Opcode == CLTS;
2433}
2434
2435bool isSETSSBSY(unsigned Opcode) {
2436 return Opcode == SETSSBSY;
2437}
2438
2439bool isVMULPD(unsigned Opcode) {
2440 switch (Opcode) {
2441 case VMULPDYrm:
2442 case VMULPDYrr:
2443 case VMULPDZ128rm:
2444 case VMULPDZ128rmb:
2445 case VMULPDZ128rmbk:
2446 case VMULPDZ128rmbkz:
2447 case VMULPDZ128rmk:
2448 case VMULPDZ128rmkz:
2449 case VMULPDZ128rr:
2450 case VMULPDZ128rrk:
2451 case VMULPDZ128rrkz:
2452 case VMULPDZ256rm:
2453 case VMULPDZ256rmb:
2454 case VMULPDZ256rmbk:
2455 case VMULPDZ256rmbkz:
2456 case VMULPDZ256rmk:
2457 case VMULPDZ256rmkz:
2458 case VMULPDZ256rr:
2459 case VMULPDZ256rrk:
2460 case VMULPDZ256rrkz:
2461 case VMULPDZrm:
2462 case VMULPDZrmb:
2463 case VMULPDZrmbk:
2464 case VMULPDZrmbkz:
2465 case VMULPDZrmk:
2466 case VMULPDZrmkz:
2467 case VMULPDZrr:
2468 case VMULPDZrrb:
2469 case VMULPDZrrbk:
2470 case VMULPDZrrbkz:
2471 case VMULPDZrrk:
2472 case VMULPDZrrkz:
2473 case VMULPDrm:
2474 case VMULPDrr:
2475 return true;
2476 }
2477 return false;
2478}
2479
2480bool isVFMADDSUB132PS(unsigned Opcode) {
2481 switch (Opcode) {
2482 case VFMADDSUB132PSYm:
2483 case VFMADDSUB132PSYr:
2484 case VFMADDSUB132PSZ128m:
2485 case VFMADDSUB132PSZ128mb:
2486 case VFMADDSUB132PSZ128mbk:
2487 case VFMADDSUB132PSZ128mbkz:
2488 case VFMADDSUB132PSZ128mk:
2489 case VFMADDSUB132PSZ128mkz:
2490 case VFMADDSUB132PSZ128r:
2491 case VFMADDSUB132PSZ128rk:
2492 case VFMADDSUB132PSZ128rkz:
2493 case VFMADDSUB132PSZ256m:
2494 case VFMADDSUB132PSZ256mb:
2495 case VFMADDSUB132PSZ256mbk:
2496 case VFMADDSUB132PSZ256mbkz:
2497 case VFMADDSUB132PSZ256mk:
2498 case VFMADDSUB132PSZ256mkz:
2499 case VFMADDSUB132PSZ256r:
2500 case VFMADDSUB132PSZ256rk:
2501 case VFMADDSUB132PSZ256rkz:
2502 case VFMADDSUB132PSZm:
2503 case VFMADDSUB132PSZmb:
2504 case VFMADDSUB132PSZmbk:
2505 case VFMADDSUB132PSZmbkz:
2506 case VFMADDSUB132PSZmk:
2507 case VFMADDSUB132PSZmkz:
2508 case VFMADDSUB132PSZr:
2509 case VFMADDSUB132PSZrb:
2510 case VFMADDSUB132PSZrbk:
2511 case VFMADDSUB132PSZrbkz:
2512 case VFMADDSUB132PSZrk:
2513 case VFMADDSUB132PSZrkz:
2514 case VFMADDSUB132PSm:
2515 case VFMADDSUB132PSr:
2516 return true;
2517 }
2518 return false;
2519}
2520
2521bool isVPMADCSWD(unsigned Opcode) {
2522 switch (Opcode) {
2523 case VPMADCSWDrm:
2524 case VPMADCSWDrr:
2525 return true;
2526 }
2527 return false;
2528}
2529
2530bool isVSCATTERPF0DPS(unsigned Opcode) {
2531 return Opcode == VSCATTERPF0DPSm;
2532}
2533
2534bool isXCHG(unsigned Opcode) {
2535 switch (Opcode) {
2536 case XCHG16ar:
2537 case XCHG16rm:
2538 case XCHG16rr:
2539 case XCHG32ar:
2540 case XCHG32rm:
2541 case XCHG32rr:
2542 case XCHG64ar:
2543 case XCHG64rm:
2544 case XCHG64rr:
2545 case XCHG8rm:
2546 case XCHG8rr:
2547 return true;
2548 }
2549 return false;
2550}
2551
2552bool isVGATHERPF1QPS(unsigned Opcode) {
2553 return Opcode == VGATHERPF1QPSm;
2554}
2555
2556bool isVCVTNEPS2BF16(unsigned Opcode) {
2557 switch (Opcode) {
2558 case VCVTNEPS2BF16Yrm:
2559 case VCVTNEPS2BF16Yrr:
2560 case VCVTNEPS2BF16Z128rm:
2561 case VCVTNEPS2BF16Z128rmb:
2562 case VCVTNEPS2BF16Z128rmbk:
2563 case VCVTNEPS2BF16Z128rmbkz:
2564 case VCVTNEPS2BF16Z128rmk:
2565 case VCVTNEPS2BF16Z128rmkz:
2566 case VCVTNEPS2BF16Z128rr:
2567 case VCVTNEPS2BF16Z128rrk:
2568 case VCVTNEPS2BF16Z128rrkz:
2569 case VCVTNEPS2BF16Z256rm:
2570 case VCVTNEPS2BF16Z256rmb:
2571 case VCVTNEPS2BF16Z256rmbk:
2572 case VCVTNEPS2BF16Z256rmbkz:
2573 case VCVTNEPS2BF16Z256rmk:
2574 case VCVTNEPS2BF16Z256rmkz:
2575 case VCVTNEPS2BF16Z256rr:
2576 case VCVTNEPS2BF16Z256rrk:
2577 case VCVTNEPS2BF16Z256rrkz:
2578 case VCVTNEPS2BF16Zrm:
2579 case VCVTNEPS2BF16Zrmb:
2580 case VCVTNEPS2BF16Zrmbk:
2581 case VCVTNEPS2BF16Zrmbkz:
2582 case VCVTNEPS2BF16Zrmk:
2583 case VCVTNEPS2BF16Zrmkz:
2584 case VCVTNEPS2BF16Zrr:
2585 case VCVTNEPS2BF16Zrrk:
2586 case VCVTNEPS2BF16Zrrkz:
2587 case VCVTNEPS2BF16rm:
2588 case VCVTNEPS2BF16rr:
2589 return true;
2590 }
2591 return false;
2592}
2593
2594bool isVFMADDSS(unsigned Opcode) {
2595 switch (Opcode) {
2596 case VFMADDSS4mr:
2597 case VFMADDSS4rm:
2598 case VFMADDSS4rr:
2599 case VFMADDSS4rr_REV:
2600 return true;
2601 }
2602 return false;
2603}
2604
2605bool isINTO(unsigned Opcode) {
2606 return Opcode == INTO;
2607}
2608
2609bool isANDPD(unsigned Opcode) {
2610 switch (Opcode) {
2611 case ANDPDrm:
2612 case ANDPDrr:
2613 return true;
2614 }
2615 return false;
2616}
2617
2618bool isSEAMCALL(unsigned Opcode) {
2619 return Opcode == SEAMCALL;
2620}
2621
2622bool isVPDPBSSDS(unsigned Opcode) {
2623 switch (Opcode) {
2624 case VPDPBSSDSYrm:
2625 case VPDPBSSDSYrr:
2626 case VPDPBSSDSZ128m:
2627 case VPDPBSSDSZ128mb:
2628 case VPDPBSSDSZ128mbk:
2629 case VPDPBSSDSZ128mbkz:
2630 case VPDPBSSDSZ128mk:
2631 case VPDPBSSDSZ128mkz:
2632 case VPDPBSSDSZ128r:
2633 case VPDPBSSDSZ128rk:
2634 case VPDPBSSDSZ128rkz:
2635 case VPDPBSSDSZ256m:
2636 case VPDPBSSDSZ256mb:
2637 case VPDPBSSDSZ256mbk:
2638 case VPDPBSSDSZ256mbkz:
2639 case VPDPBSSDSZ256mk:
2640 case VPDPBSSDSZ256mkz:
2641 case VPDPBSSDSZ256r:
2642 case VPDPBSSDSZ256rk:
2643 case VPDPBSSDSZ256rkz:
2644 case VPDPBSSDSZm:
2645 case VPDPBSSDSZmb:
2646 case VPDPBSSDSZmbk:
2647 case VPDPBSSDSZmbkz:
2648 case VPDPBSSDSZmk:
2649 case VPDPBSSDSZmkz:
2650 case VPDPBSSDSZr:
2651 case VPDPBSSDSZrk:
2652 case VPDPBSSDSZrkz:
2653 case VPDPBSSDSrm:
2654 case VPDPBSSDSrr:
2655 return true;
2656 }
2657 return false;
2658}
2659
2660bool isUNPCKHPS(unsigned Opcode) {
2661 switch (Opcode) {
2662 case UNPCKHPSrm:
2663 case UNPCKHPSrr:
2664 return true;
2665 }
2666 return false;
2667}
2668
2669bool isSETZUCC(unsigned Opcode) {
2670 switch (Opcode) {
2671 case SETZUCCm:
2672 case SETZUCCr:
2673 return true;
2674 }
2675 return false;
2676}
2677
2678bool isSHUFPD(unsigned Opcode) {
2679 switch (Opcode) {
2680 case SHUFPDrmi:
2681 case SHUFPDrri:
2682 return true;
2683 }
2684 return false;
2685}
2686
2687bool isFCMOVNB(unsigned Opcode) {
2688 return Opcode == CMOVNB_F;
2689}
2690
2691bool isCVTTSS2SI(unsigned Opcode) {
2692 switch (Opcode) {
2693 case CVTTSS2SI64rm_Int:
2694 case CVTTSS2SI64rr_Int:
2695 case CVTTSS2SIrm_Int:
2696 case CVTTSS2SIrr_Int:
2697 return true;
2698 }
2699 return false;
2700}
2701
2702bool isEXTRQ(unsigned Opcode) {
2703 switch (Opcode) {
2704 case EXTRQ:
2705 case EXTRQI:
2706 return true;
2707 }
2708 return false;
2709}
2710
2711bool isSHLD(unsigned Opcode) {
2712 switch (Opcode) {
2713 case SHLD16mrCL:
2714 case SHLD16mrCL_EVEX:
2715 case SHLD16mrCL_ND:
2716 case SHLD16mrCL_NF:
2717 case SHLD16mrCL_NF_ND:
2718 case SHLD16mri8:
2719 case SHLD16mri8_EVEX:
2720 case SHLD16mri8_ND:
2721 case SHLD16mri8_NF:
2722 case SHLD16mri8_NF_ND:
2723 case SHLD16rrCL:
2724 case SHLD16rrCL_EVEX:
2725 case SHLD16rrCL_ND:
2726 case SHLD16rrCL_NF:
2727 case SHLD16rrCL_NF_ND:
2728 case SHLD16rri8:
2729 case SHLD16rri8_EVEX:
2730 case SHLD16rri8_ND:
2731 case SHLD16rri8_NF:
2732 case SHLD16rri8_NF_ND:
2733 case SHLD32mrCL:
2734 case SHLD32mrCL_EVEX:
2735 case SHLD32mrCL_ND:
2736 case SHLD32mrCL_NF:
2737 case SHLD32mrCL_NF_ND:
2738 case SHLD32mri8:
2739 case SHLD32mri8_EVEX:
2740 case SHLD32mri8_ND:
2741 case SHLD32mri8_NF:
2742 case SHLD32mri8_NF_ND:
2743 case SHLD32rrCL:
2744 case SHLD32rrCL_EVEX:
2745 case SHLD32rrCL_ND:
2746 case SHLD32rrCL_NF:
2747 case SHLD32rrCL_NF_ND:
2748 case SHLD32rri8:
2749 case SHLD32rri8_EVEX:
2750 case SHLD32rri8_ND:
2751 case SHLD32rri8_NF:
2752 case SHLD32rri8_NF_ND:
2753 case SHLD64mrCL:
2754 case SHLD64mrCL_EVEX:
2755 case SHLD64mrCL_ND:
2756 case SHLD64mrCL_NF:
2757 case SHLD64mrCL_NF_ND:
2758 case SHLD64mri8:
2759 case SHLD64mri8_EVEX:
2760 case SHLD64mri8_ND:
2761 case SHLD64mri8_NF:
2762 case SHLD64mri8_NF_ND:
2763 case SHLD64rrCL:
2764 case SHLD64rrCL_EVEX:
2765 case SHLD64rrCL_ND:
2766 case SHLD64rrCL_NF:
2767 case SHLD64rrCL_NF_ND:
2768 case SHLD64rri8:
2769 case SHLD64rri8_EVEX:
2770 case SHLD64rri8_ND:
2771 case SHLD64rri8_NF:
2772 case SHLD64rri8_NF_ND:
2773 return true;
2774 }
2775 return false;
2776}
2777
2778bool isVBROADCASTSS(unsigned Opcode) {
2779 switch (Opcode) {
2780 case VBROADCASTSSYrm:
2781 case VBROADCASTSSYrr:
2782 case VBROADCASTSSZ128rm:
2783 case VBROADCASTSSZ128rmk:
2784 case VBROADCASTSSZ128rmkz:
2785 case VBROADCASTSSZ128rr:
2786 case VBROADCASTSSZ128rrk:
2787 case VBROADCASTSSZ128rrkz:
2788 case VBROADCASTSSZ256rm:
2789 case VBROADCASTSSZ256rmk:
2790 case VBROADCASTSSZ256rmkz:
2791 case VBROADCASTSSZ256rr:
2792 case VBROADCASTSSZ256rrk:
2793 case VBROADCASTSSZ256rrkz:
2794 case VBROADCASTSSZrm:
2795 case VBROADCASTSSZrmk:
2796 case VBROADCASTSSZrmkz:
2797 case VBROADCASTSSZrr:
2798 case VBROADCASTSSZrrk:
2799 case VBROADCASTSSZrrkz:
2800 case VBROADCASTSSrm:
2801 case VBROADCASTSSrr:
2802 return true;
2803 }
2804 return false;
2805}
2806
2807bool isCLUI(unsigned Opcode) {
2808 return Opcode == CLUI;
2809}
2810
2811bool isVINSERTI128(unsigned Opcode) {
2812 switch (Opcode) {
2813 case VINSERTI128rmi:
2814 case VINSERTI128rri:
2815 return true;
2816 }
2817 return false;
2818}
2819
2820bool isVBLENDPD(unsigned Opcode) {
2821 switch (Opcode) {
2822 case VBLENDPDYrmi:
2823 case VBLENDPDYrri:
2824 case VBLENDPDrmi:
2825 case VBLENDPDrri:
2826 return true;
2827 }
2828 return false;
2829}
2830
2831bool isVPSHLDW(unsigned Opcode) {
2832 switch (Opcode) {
2833 case VPSHLDWZ128rmi:
2834 case VPSHLDWZ128rmik:
2835 case VPSHLDWZ128rmikz:
2836 case VPSHLDWZ128rri:
2837 case VPSHLDWZ128rrik:
2838 case VPSHLDWZ128rrikz:
2839 case VPSHLDWZ256rmi:
2840 case VPSHLDWZ256rmik:
2841 case VPSHLDWZ256rmikz:
2842 case VPSHLDWZ256rri:
2843 case VPSHLDWZ256rrik:
2844 case VPSHLDWZ256rrikz:
2845 case VPSHLDWZrmi:
2846 case VPSHLDWZrmik:
2847 case VPSHLDWZrmikz:
2848 case VPSHLDWZrri:
2849 case VPSHLDWZrrik:
2850 case VPSHLDWZrrikz:
2851 return true;
2852 }
2853 return false;
2854}
2855
2856bool isT2RPNTLVWZ0T1(unsigned Opcode) {
2857 switch (Opcode) {
2858 case T2RPNTLVWZ0T1:
2859 case T2RPNTLVWZ0T1_EVEX:
2860 return true;
2861 }
2862 return false;
2863}
2864
2865bool isVCVTNEEPH2PS(unsigned Opcode) {
2866 switch (Opcode) {
2867 case VCVTNEEPH2PSYrm:
2868 case VCVTNEEPH2PSrm:
2869 return true;
2870 }
2871 return false;
2872}
2873
2874bool isVCVTTSD2SI(unsigned Opcode) {
2875 switch (Opcode) {
2876 case VCVTTSD2SI64Zrm_Int:
2877 case VCVTTSD2SI64Zrr_Int:
2878 case VCVTTSD2SI64Zrrb_Int:
2879 case VCVTTSD2SI64rm_Int:
2880 case VCVTTSD2SI64rr_Int:
2881 case VCVTTSD2SIZrm_Int:
2882 case VCVTTSD2SIZrr_Int:
2883 case VCVTTSD2SIZrrb_Int:
2884 case VCVTTSD2SIrm_Int:
2885 case VCVTTSD2SIrr_Int:
2886 return true;
2887 }
2888 return false;
2889}
2890
2891bool isVSM4KEY4(unsigned Opcode) {
2892 switch (Opcode) {
2893 case VSM4KEY4Yrm:
2894 case VSM4KEY4Yrr:
2895 case VSM4KEY4Z128rm:
2896 case VSM4KEY4Z128rr:
2897 case VSM4KEY4Z256rm:
2898 case VSM4KEY4Z256rr:
2899 case VSM4KEY4Zrm:
2900 case VSM4KEY4Zrr:
2901 case VSM4KEY4rm:
2902 case VSM4KEY4rr:
2903 return true;
2904 }
2905 return false;
2906}
2907
2908bool isWRMSRNS(unsigned Opcode) {
2909 switch (Opcode) {
2910 case WRMSRNS:
2911 case WRMSRNSir:
2912 case WRMSRNSir_EVEX:
2913 return true;
2914 }
2915 return false;
2916}
2917
2918bool isCMPSB(unsigned Opcode) {
2919 return Opcode == CMPSB;
2920}
2921
2922bool isVRCPBF16(unsigned Opcode) {
2923 switch (Opcode) {
2924 case VRCPBF16Z128m:
2925 case VRCPBF16Z128mb:
2926 case VRCPBF16Z128mbk:
2927 case VRCPBF16Z128mbkz:
2928 case VRCPBF16Z128mk:
2929 case VRCPBF16Z128mkz:
2930 case VRCPBF16Z128r:
2931 case VRCPBF16Z128rk:
2932 case VRCPBF16Z128rkz:
2933 case VRCPBF16Z256m:
2934 case VRCPBF16Z256mb:
2935 case VRCPBF16Z256mbk:
2936 case VRCPBF16Z256mbkz:
2937 case VRCPBF16Z256mk:
2938 case VRCPBF16Z256mkz:
2939 case VRCPBF16Z256r:
2940 case VRCPBF16Z256rk:
2941 case VRCPBF16Z256rkz:
2942 case VRCPBF16Zm:
2943 case VRCPBF16Zmb:
2944 case VRCPBF16Zmbk:
2945 case VRCPBF16Zmbkz:
2946 case VRCPBF16Zmk:
2947 case VRCPBF16Zmkz:
2948 case VRCPBF16Zr:
2949 case VRCPBF16Zrk:
2950 case VRCPBF16Zrkz:
2951 return true;
2952 }
2953 return false;
2954}
2955
2956bool isMULSS(unsigned Opcode) {
2957 switch (Opcode) {
2958 case MULSSrm_Int:
2959 case MULSSrr_Int:
2960 return true;
2961 }
2962 return false;
2963}
2964
2965bool isVMRUN(unsigned Opcode) {
2966 switch (Opcode) {
2967 case VMRUN32:
2968 case VMRUN64:
2969 return true;
2970 }
2971 return false;
2972}
2973
2974bool isVPSRLVD(unsigned Opcode) {
2975 switch (Opcode) {
2976 case VPSRLVDYrm:
2977 case VPSRLVDYrr:
2978 case VPSRLVDZ128rm:
2979 case VPSRLVDZ128rmb:
2980 case VPSRLVDZ128rmbk:
2981 case VPSRLVDZ128rmbkz:
2982 case VPSRLVDZ128rmk:
2983 case VPSRLVDZ128rmkz:
2984 case VPSRLVDZ128rr:
2985 case VPSRLVDZ128rrk:
2986 case VPSRLVDZ128rrkz:
2987 case VPSRLVDZ256rm:
2988 case VPSRLVDZ256rmb:
2989 case VPSRLVDZ256rmbk:
2990 case VPSRLVDZ256rmbkz:
2991 case VPSRLVDZ256rmk:
2992 case VPSRLVDZ256rmkz:
2993 case VPSRLVDZ256rr:
2994 case VPSRLVDZ256rrk:
2995 case VPSRLVDZ256rrkz:
2996 case VPSRLVDZrm:
2997 case VPSRLVDZrmb:
2998 case VPSRLVDZrmbk:
2999 case VPSRLVDZrmbkz:
3000 case VPSRLVDZrmk:
3001 case VPSRLVDZrmkz:
3002 case VPSRLVDZrr:
3003 case VPSRLVDZrrk:
3004 case VPSRLVDZrrkz:
3005 case VPSRLVDrm:
3006 case VPSRLVDrr:
3007 return true;
3008 }
3009 return false;
3010}
3011
3012bool isLEAVE(unsigned Opcode) {
3013 switch (Opcode) {
3014 case LEAVE:
3015 case LEAVE64:
3016 return true;
3017 }
3018 return false;
3019}
3020
3021bool isVGETMANTPS(unsigned Opcode) {
3022 switch (Opcode) {
3023 case VGETMANTPSZ128rmbi:
3024 case VGETMANTPSZ128rmbik:
3025 case VGETMANTPSZ128rmbikz:
3026 case VGETMANTPSZ128rmi:
3027 case VGETMANTPSZ128rmik:
3028 case VGETMANTPSZ128rmikz:
3029 case VGETMANTPSZ128rri:
3030 case VGETMANTPSZ128rrik:
3031 case VGETMANTPSZ128rrikz:
3032 case VGETMANTPSZ256rmbi:
3033 case VGETMANTPSZ256rmbik:
3034 case VGETMANTPSZ256rmbikz:
3035 case VGETMANTPSZ256rmi:
3036 case VGETMANTPSZ256rmik:
3037 case VGETMANTPSZ256rmikz:
3038 case VGETMANTPSZ256rri:
3039 case VGETMANTPSZ256rrik:
3040 case VGETMANTPSZ256rrikz:
3041 case VGETMANTPSZrmbi:
3042 case VGETMANTPSZrmbik:
3043 case VGETMANTPSZrmbikz:
3044 case VGETMANTPSZrmi:
3045 case VGETMANTPSZrmik:
3046 case VGETMANTPSZrmikz:
3047 case VGETMANTPSZrri:
3048 case VGETMANTPSZrrib:
3049 case VGETMANTPSZrribk:
3050 case VGETMANTPSZrribkz:
3051 case VGETMANTPSZrrik:
3052 case VGETMANTPSZrrikz:
3053 return true;
3054 }
3055 return false;
3056}
3057
3058bool isXSHA256(unsigned Opcode) {
3059 return Opcode == XSHA256;
3060}
3061
3062bool isTCONJTFP16(unsigned Opcode) {
3063 return Opcode == TCONJTFP16;
3064}
3065
3066bool isBOUND(unsigned Opcode) {
3067 switch (Opcode) {
3068 case BOUNDS16rm:
3069 case BOUNDS32rm:
3070 return true;
3071 }
3072 return false;
3073}
3074
3075bool isSFENCE(unsigned Opcode) {
3076 return Opcode == SFENCE;
3077}
3078
3079bool isVPHADDD(unsigned Opcode) {
3080 switch (Opcode) {
3081 case VPHADDDYrm:
3082 case VPHADDDYrr:
3083 case VPHADDDrm:
3084 case VPHADDDrr:
3085 return true;
3086 }
3087 return false;
3088}
3089
3090bool isADOX(unsigned Opcode) {
3091 switch (Opcode) {
3092 case ADOX32rm:
3093 case ADOX32rm_EVEX:
3094 case ADOX32rm_ND:
3095 case ADOX32rr:
3096 case ADOX32rr_EVEX:
3097 case ADOX32rr_ND:
3098 case ADOX64rm:
3099 case ADOX64rm_EVEX:
3100 case ADOX64rm_ND:
3101 case ADOX64rr:
3102 case ADOX64rr_EVEX:
3103 case ADOX64rr_ND:
3104 return true;
3105 }
3106 return false;
3107}
3108
3109bool isVPSLLQ(unsigned Opcode) {
3110 switch (Opcode) {
3111 case VPSLLQYri:
3112 case VPSLLQYrm:
3113 case VPSLLQYrr:
3114 case VPSLLQZ128mbi:
3115 case VPSLLQZ128mbik:
3116 case VPSLLQZ128mbikz:
3117 case VPSLLQZ128mi:
3118 case VPSLLQZ128mik:
3119 case VPSLLQZ128mikz:
3120 case VPSLLQZ128ri:
3121 case VPSLLQZ128rik:
3122 case VPSLLQZ128rikz:
3123 case VPSLLQZ128rm:
3124 case VPSLLQZ128rmk:
3125 case VPSLLQZ128rmkz:
3126 case VPSLLQZ128rr:
3127 case VPSLLQZ128rrk:
3128 case VPSLLQZ128rrkz:
3129 case VPSLLQZ256mbi:
3130 case VPSLLQZ256mbik:
3131 case VPSLLQZ256mbikz:
3132 case VPSLLQZ256mi:
3133 case VPSLLQZ256mik:
3134 case VPSLLQZ256mikz:
3135 case VPSLLQZ256ri:
3136 case VPSLLQZ256rik:
3137 case VPSLLQZ256rikz:
3138 case VPSLLQZ256rm:
3139 case VPSLLQZ256rmk:
3140 case VPSLLQZ256rmkz:
3141 case VPSLLQZ256rr:
3142 case VPSLLQZ256rrk:
3143 case VPSLLQZ256rrkz:
3144 case VPSLLQZmbi:
3145 case VPSLLQZmbik:
3146 case VPSLLQZmbikz:
3147 case VPSLLQZmi:
3148 case VPSLLQZmik:
3149 case VPSLLQZmikz:
3150 case VPSLLQZri:
3151 case VPSLLQZrik:
3152 case VPSLLQZrikz:
3153 case VPSLLQZrm:
3154 case VPSLLQZrmk:
3155 case VPSLLQZrmkz:
3156 case VPSLLQZrr:
3157 case VPSLLQZrrk:
3158 case VPSLLQZrrkz:
3159 case VPSLLQri:
3160 case VPSLLQrm:
3161 case VPSLLQrr:
3162 return true;
3163 }
3164 return false;
3165}
3166
3167bool isVCVTPH2HF8(unsigned Opcode) {
3168 switch (Opcode) {
3169 case VCVTPH2HF8Z128rm:
3170 case VCVTPH2HF8Z128rmb:
3171 case VCVTPH2HF8Z128rmbk:
3172 case VCVTPH2HF8Z128rmbkz:
3173 case VCVTPH2HF8Z128rmk:
3174 case VCVTPH2HF8Z128rmkz:
3175 case VCVTPH2HF8Z128rr:
3176 case VCVTPH2HF8Z128rrk:
3177 case VCVTPH2HF8Z128rrkz:
3178 case VCVTPH2HF8Z256rm:
3179 case VCVTPH2HF8Z256rmb:
3180 case VCVTPH2HF8Z256rmbk:
3181 case VCVTPH2HF8Z256rmbkz:
3182 case VCVTPH2HF8Z256rmk:
3183 case VCVTPH2HF8Z256rmkz:
3184 case VCVTPH2HF8Z256rr:
3185 case VCVTPH2HF8Z256rrk:
3186 case VCVTPH2HF8Z256rrkz:
3187 case VCVTPH2HF8Zrm:
3188 case VCVTPH2HF8Zrmb:
3189 case VCVTPH2HF8Zrmbk:
3190 case VCVTPH2HF8Zrmbkz:
3191 case VCVTPH2HF8Zrmk:
3192 case VCVTPH2HF8Zrmkz:
3193 case VCVTPH2HF8Zrr:
3194 case VCVTPH2HF8Zrrk:
3195 case VCVTPH2HF8Zrrkz:
3196 return true;
3197 }
3198 return false;
3199}
3200
3201bool isPFRSQIT1(unsigned Opcode) {
3202 switch (Opcode) {
3203 case PFRSQIT1rm:
3204 case PFRSQIT1rr:
3205 return true;
3206 }
3207 return false;
3208}
3209
3210bool isCLAC(unsigned Opcode) {
3211 return Opcode == CLAC;
3212}
3213
3214bool isKNOTW(unsigned Opcode) {
3215 return Opcode == KNOTWkk;
3216}
3217
3218bool isVCVTPH2PD(unsigned Opcode) {
3219 switch (Opcode) {
3220 case VCVTPH2PDZ128rm:
3221 case VCVTPH2PDZ128rmb:
3222 case VCVTPH2PDZ128rmbk:
3223 case VCVTPH2PDZ128rmbkz:
3224 case VCVTPH2PDZ128rmk:
3225 case VCVTPH2PDZ128rmkz:
3226 case VCVTPH2PDZ128rr:
3227 case VCVTPH2PDZ128rrk:
3228 case VCVTPH2PDZ128rrkz:
3229 case VCVTPH2PDZ256rm:
3230 case VCVTPH2PDZ256rmb:
3231 case VCVTPH2PDZ256rmbk:
3232 case VCVTPH2PDZ256rmbkz:
3233 case VCVTPH2PDZ256rmk:
3234 case VCVTPH2PDZ256rmkz:
3235 case VCVTPH2PDZ256rr:
3236 case VCVTPH2PDZ256rrk:
3237 case VCVTPH2PDZ256rrkz:
3238 case VCVTPH2PDZrm:
3239 case VCVTPH2PDZrmb:
3240 case VCVTPH2PDZrmbk:
3241 case VCVTPH2PDZrmbkz:
3242 case VCVTPH2PDZrmk:
3243 case VCVTPH2PDZrmkz:
3244 case VCVTPH2PDZrr:
3245 case VCVTPH2PDZrrb:
3246 case VCVTPH2PDZrrbk:
3247 case VCVTPH2PDZrrbkz:
3248 case VCVTPH2PDZrrk:
3249 case VCVTPH2PDZrrkz:
3250 return true;
3251 }
3252 return false;
3253}
3254
3255bool isVAESENC(unsigned Opcode) {
3256 switch (Opcode) {
3257 case VAESENCYrm:
3258 case VAESENCYrr:
3259 case VAESENCZ128rm:
3260 case VAESENCZ128rr:
3261 case VAESENCZ256rm:
3262 case VAESENCZ256rr:
3263 case VAESENCZrm:
3264 case VAESENCZrr:
3265 case VAESENCrm:
3266 case VAESENCrr:
3267 return true;
3268 }
3269 return false;
3270}
3271
3272bool isMOVNTI(unsigned Opcode) {
3273 switch (Opcode) {
3274 case MOVNTI_64mr:
3275 case MOVNTImr:
3276 return true;
3277 }
3278 return false;
3279}
3280
3281bool isFXCH(unsigned Opcode) {
3282 return Opcode == XCH_F;
3283}
3284
3285bool isPOPP(unsigned Opcode) {
3286 return Opcode == POPP64r;
3287}
3288
3289bool isVPBLENDMD(unsigned Opcode) {
3290 switch (Opcode) {
3291 case VPBLENDMDZ128rm:
3292 case VPBLENDMDZ128rmb:
3293 case VPBLENDMDZ128rmbk:
3294 case VPBLENDMDZ128rmbkz:
3295 case VPBLENDMDZ128rmk:
3296 case VPBLENDMDZ128rmkz:
3297 case VPBLENDMDZ128rr:
3298 case VPBLENDMDZ128rrk:
3299 case VPBLENDMDZ128rrkz:
3300 case VPBLENDMDZ256rm:
3301 case VPBLENDMDZ256rmb:
3302 case VPBLENDMDZ256rmbk:
3303 case VPBLENDMDZ256rmbkz:
3304 case VPBLENDMDZ256rmk:
3305 case VPBLENDMDZ256rmkz:
3306 case VPBLENDMDZ256rr:
3307 case VPBLENDMDZ256rrk:
3308 case VPBLENDMDZ256rrkz:
3309 case VPBLENDMDZrm:
3310 case VPBLENDMDZrmb:
3311 case VPBLENDMDZrmbk:
3312 case VPBLENDMDZrmbkz:
3313 case VPBLENDMDZrmk:
3314 case VPBLENDMDZrmkz:
3315 case VPBLENDMDZrr:
3316 case VPBLENDMDZrrk:
3317 case VPBLENDMDZrrkz:
3318 return true;
3319 }
3320 return false;
3321}
3322
3323bool isFSINCOS(unsigned Opcode) {
3324 return Opcode == FSINCOS;
3325}
3326
3327bool isVPMULLW(unsigned Opcode) {
3328 switch (Opcode) {
3329 case VPMULLWYrm:
3330 case VPMULLWYrr:
3331 case VPMULLWZ128rm:
3332 case VPMULLWZ128rmk:
3333 case VPMULLWZ128rmkz:
3334 case VPMULLWZ128rr:
3335 case VPMULLWZ128rrk:
3336 case VPMULLWZ128rrkz:
3337 case VPMULLWZ256rm:
3338 case VPMULLWZ256rmk:
3339 case VPMULLWZ256rmkz:
3340 case VPMULLWZ256rr:
3341 case VPMULLWZ256rrk:
3342 case VPMULLWZ256rrkz:
3343 case VPMULLWZrm:
3344 case VPMULLWZrmk:
3345 case VPMULLWZrmkz:
3346 case VPMULLWZrr:
3347 case VPMULLWZrrk:
3348 case VPMULLWZrrkz:
3349 case VPMULLWrm:
3350 case VPMULLWrr:
3351 return true;
3352 }
3353 return false;
3354}
3355
3356bool isVPMOVSXBW(unsigned Opcode) {
3357 switch (Opcode) {
3358 case VPMOVSXBWYrm:
3359 case VPMOVSXBWYrr:
3360 case VPMOVSXBWZ128rm:
3361 case VPMOVSXBWZ128rmk:
3362 case VPMOVSXBWZ128rmkz:
3363 case VPMOVSXBWZ128rr:
3364 case VPMOVSXBWZ128rrk:
3365 case VPMOVSXBWZ128rrkz:
3366 case VPMOVSXBWZ256rm:
3367 case VPMOVSXBWZ256rmk:
3368 case VPMOVSXBWZ256rmkz:
3369 case VPMOVSXBWZ256rr:
3370 case VPMOVSXBWZ256rrk:
3371 case VPMOVSXBWZ256rrkz:
3372 case VPMOVSXBWZrm:
3373 case VPMOVSXBWZrmk:
3374 case VPMOVSXBWZrmkz:
3375 case VPMOVSXBWZrr:
3376 case VPMOVSXBWZrrk:
3377 case VPMOVSXBWZrrkz:
3378 case VPMOVSXBWrm:
3379 case VPMOVSXBWrr:
3380 return true;
3381 }
3382 return false;
3383}
3384
3385bool isSTC(unsigned Opcode) {
3386 return Opcode == STC;
3387}
3388
3389bool isVPINSRB(unsigned Opcode) {
3390 switch (Opcode) {
3391 case VPINSRBZrmi:
3392 case VPINSRBZrri:
3393 case VPINSRBrmi:
3394 case VPINSRBrri:
3395 return true;
3396 }
3397 return false;
3398}
3399
3400bool isLWPVAL(unsigned Opcode) {
3401 switch (Opcode) {
3402 case LWPVAL32rmi:
3403 case LWPVAL32rri:
3404 case LWPVAL64rmi:
3405 case LWPVAL64rri:
3406 return true;
3407 }
3408 return false;
3409}
3410
3411bool isKXORB(unsigned Opcode) {
3412 return Opcode == KXORBkk;
3413}
3414
3415bool isRSTORSSP(unsigned Opcode) {
3416 return Opcode == RSTORSSP;
3417}
3418
3419bool isVPRORQ(unsigned Opcode) {
3420 switch (Opcode) {
3421 case VPRORQZ128mbi:
3422 case VPRORQZ128mbik:
3423 case VPRORQZ128mbikz:
3424 case VPRORQZ128mi:
3425 case VPRORQZ128mik:
3426 case VPRORQZ128mikz:
3427 case VPRORQZ128ri:
3428 case VPRORQZ128rik:
3429 case VPRORQZ128rikz:
3430 case VPRORQZ256mbi:
3431 case VPRORQZ256mbik:
3432 case VPRORQZ256mbikz:
3433 case VPRORQZ256mi:
3434 case VPRORQZ256mik:
3435 case VPRORQZ256mikz:
3436 case VPRORQZ256ri:
3437 case VPRORQZ256rik:
3438 case VPRORQZ256rikz:
3439 case VPRORQZmbi:
3440 case VPRORQZmbik:
3441 case VPRORQZmbikz:
3442 case VPRORQZmi:
3443 case VPRORQZmik:
3444 case VPRORQZmikz:
3445 case VPRORQZri:
3446 case VPRORQZrik:
3447 case VPRORQZrikz:
3448 return true;
3449 }
3450 return false;
3451}
3452
3453bool isVSM3MSG1(unsigned Opcode) {
3454 switch (Opcode) {
3455 case VSM3MSG1rm:
3456 case VSM3MSG1rr:
3457 return true;
3458 }
3459 return false;
3460}
3461
3462bool isFICOM(unsigned Opcode) {
3463 switch (Opcode) {
3464 case FICOM16m:
3465 case FICOM32m:
3466 return true;
3467 }
3468 return false;
3469}
3470
3471bool isMAXPS(unsigned Opcode) {
3472 switch (Opcode) {
3473 case MAXPSrm:
3474 case MAXPSrr:
3475 return true;
3476 }
3477 return false;
3478}
3479
3480bool isFNCLEX(unsigned Opcode) {
3481 return Opcode == FNCLEX;
3482}
3483
3484bool isVMOVMSKPS(unsigned Opcode) {
3485 switch (Opcode) {
3486 case VMOVMSKPSYrr:
3487 case VMOVMSKPSrr:
3488 return true;
3489 }
3490 return false;
3491}
3492
3493bool isVPMOVDB(unsigned Opcode) {
3494 switch (Opcode) {
3495 case VPMOVDBZ128mr:
3496 case VPMOVDBZ128mrk:
3497 case VPMOVDBZ128rr:
3498 case VPMOVDBZ128rrk:
3499 case VPMOVDBZ128rrkz:
3500 case VPMOVDBZ256mr:
3501 case VPMOVDBZ256mrk:
3502 case VPMOVDBZ256rr:
3503 case VPMOVDBZ256rrk:
3504 case VPMOVDBZ256rrkz:
3505 case VPMOVDBZmr:
3506 case VPMOVDBZmrk:
3507 case VPMOVDBZrr:
3508 case VPMOVDBZrrk:
3509 case VPMOVDBZrrkz:
3510 return true;
3511 }
3512 return false;
3513}
3514
3515bool isLLWPCB(unsigned Opcode) {
3516 switch (Opcode) {
3517 case LLWPCB:
3518 case LLWPCB64:
3519 return true;
3520 }
3521 return false;
3522}
3523
3524bool isVMULSS(unsigned Opcode) {
3525 switch (Opcode) {
3526 case VMULSSZrm_Int:
3527 case VMULSSZrmk_Int:
3528 case VMULSSZrmkz_Int:
3529 case VMULSSZrr_Int:
3530 case VMULSSZrrb_Int:
3531 case VMULSSZrrbk_Int:
3532 case VMULSSZrrbkz_Int:
3533 case VMULSSZrrk_Int:
3534 case VMULSSZrrkz_Int:
3535 case VMULSSrm_Int:
3536 case VMULSSrr_Int:
3537 return true;
3538 }
3539 return false;
3540}
3541
3542bool isAESENCLAST(unsigned Opcode) {
3543 switch (Opcode) {
3544 case AESENCLASTrm:
3545 case AESENCLASTrr:
3546 return true;
3547 }
3548 return false;
3549}
3550
3551bool isTILEMOVROW(unsigned Opcode) {
3552 switch (Opcode) {
3553 case TILEMOVROWrre:
3554 case TILEMOVROWrri:
3555 return true;
3556 }
3557 return false;
3558}
3559
3560bool isVMINMAXPH(unsigned Opcode) {
3561 switch (Opcode) {
3562 case VMINMAXPHZ128rmbi:
3563 case VMINMAXPHZ128rmbik:
3564 case VMINMAXPHZ128rmbikz:
3565 case VMINMAXPHZ128rmi:
3566 case VMINMAXPHZ128rmik:
3567 case VMINMAXPHZ128rmikz:
3568 case VMINMAXPHZ128rri:
3569 case VMINMAXPHZ128rrik:
3570 case VMINMAXPHZ128rrikz:
3571 case VMINMAXPHZ256rmbi:
3572 case VMINMAXPHZ256rmbik:
3573 case VMINMAXPHZ256rmbikz:
3574 case VMINMAXPHZ256rmi:
3575 case VMINMAXPHZ256rmik:
3576 case VMINMAXPHZ256rmikz:
3577 case VMINMAXPHZ256rri:
3578 case VMINMAXPHZ256rrik:
3579 case VMINMAXPHZ256rrikz:
3580 case VMINMAXPHZrmbi:
3581 case VMINMAXPHZrmbik:
3582 case VMINMAXPHZrmbikz:
3583 case VMINMAXPHZrmi:
3584 case VMINMAXPHZrmik:
3585 case VMINMAXPHZrmikz:
3586 case VMINMAXPHZrri:
3587 case VMINMAXPHZrrib:
3588 case VMINMAXPHZrribk:
3589 case VMINMAXPHZrribkz:
3590 case VMINMAXPHZrrik:
3591 case VMINMAXPHZrrikz:
3592 return true;
3593 }
3594 return false;
3595}
3596
3597bool isVPMAXUB(unsigned Opcode) {
3598 switch (Opcode) {
3599 case VPMAXUBYrm:
3600 case VPMAXUBYrr:
3601 case VPMAXUBZ128rm:
3602 case VPMAXUBZ128rmk:
3603 case VPMAXUBZ128rmkz:
3604 case VPMAXUBZ128rr:
3605 case VPMAXUBZ128rrk:
3606 case VPMAXUBZ128rrkz:
3607 case VPMAXUBZ256rm:
3608 case VPMAXUBZ256rmk:
3609 case VPMAXUBZ256rmkz:
3610 case VPMAXUBZ256rr:
3611 case VPMAXUBZ256rrk:
3612 case VPMAXUBZ256rrkz:
3613 case VPMAXUBZrm:
3614 case VPMAXUBZrmk:
3615 case VPMAXUBZrmkz:
3616 case VPMAXUBZrr:
3617 case VPMAXUBZrrk:
3618 case VPMAXUBZrrkz:
3619 case VPMAXUBrm:
3620 case VPMAXUBrr:
3621 return true;
3622 }
3623 return false;
3624}
3625
3626bool isAAS(unsigned Opcode) {
3627 return Opcode == AAS;
3628}
3629
3630bool isFADD(unsigned Opcode) {
3631 switch (Opcode) {
3632 case ADD_F32m:
3633 case ADD_F64m:
3634 case ADD_FST0r:
3635 case ADD_FrST0:
3636 return true;
3637 }
3638 return false;
3639}
3640
3641bool isJMP(unsigned Opcode) {
3642 switch (Opcode) {
3643 case FARJMP32m:
3644 case JMP16m:
3645 case JMP16r:
3646 case JMP32m:
3647 case JMP32r:
3648 case JMP64m:
3649 case JMP64r:
3650 case JMP_1:
3651 case JMP_2:
3652 case JMP_4:
3653 return true;
3654 }
3655 return false;
3656}
3657
3658bool isXCRYPTECB(unsigned Opcode) {
3659 return Opcode == XCRYPTECB;
3660}
3661
3662bool isPFRCPIT1(unsigned Opcode) {
3663 switch (Opcode) {
3664 case PFRCPIT1rm:
3665 case PFRCPIT1rr:
3666 return true;
3667 }
3668 return false;
3669}
3670
3671bool isPMULHRW(unsigned Opcode) {
3672 switch (Opcode) {
3673 case PMULHRWrm:
3674 case PMULHRWrr:
3675 return true;
3676 }
3677 return false;
3678}
3679
3680bool isVCVTPH2PS(unsigned Opcode) {
3681 switch (Opcode) {
3682 case VCVTPH2PSYrm:
3683 case VCVTPH2PSYrr:
3684 case VCVTPH2PSZ128rm:
3685 case VCVTPH2PSZ128rmk:
3686 case VCVTPH2PSZ128rmkz:
3687 case VCVTPH2PSZ128rr:
3688 case VCVTPH2PSZ128rrk:
3689 case VCVTPH2PSZ128rrkz:
3690 case VCVTPH2PSZ256rm:
3691 case VCVTPH2PSZ256rmk:
3692 case VCVTPH2PSZ256rmkz:
3693 case VCVTPH2PSZ256rr:
3694 case VCVTPH2PSZ256rrk:
3695 case VCVTPH2PSZ256rrkz:
3696 case VCVTPH2PSZrm:
3697 case VCVTPH2PSZrmk:
3698 case VCVTPH2PSZrmkz:
3699 case VCVTPH2PSZrr:
3700 case VCVTPH2PSZrrb:
3701 case VCVTPH2PSZrrbk:
3702 case VCVTPH2PSZrrbkz:
3703 case VCVTPH2PSZrrk:
3704 case VCVTPH2PSZrrkz:
3705 case VCVTPH2PSrm:
3706 case VCVTPH2PSrr:
3707 return true;
3708 }
3709 return false;
3710}
3711
3712bool isVPBLENDVB(unsigned Opcode) {
3713 switch (Opcode) {
3714 case VPBLENDVBYrmr:
3715 case VPBLENDVBYrrr:
3716 case VPBLENDVBrmr:
3717 case VPBLENDVBrrr:
3718 return true;
3719 }
3720 return false;
3721}
3722
3723bool isPCMPESTRI(unsigned Opcode) {
3724 switch (Opcode) {
3725 case PCMPESTRIrmi:
3726 case PCMPESTRIrri:
3727 return true;
3728 }
3729 return false;
3730}
3731
3732bool isSENDUIPI(unsigned Opcode) {
3733 return Opcode == SENDUIPI;
3734}
3735
3736bool isFLDLN2(unsigned Opcode) {
3737 return Opcode == FLDLN2;
3738}
3739
3740bool isVPMACSWD(unsigned Opcode) {
3741 switch (Opcode) {
3742 case VPMACSWDrm:
3743 case VPMACSWDrr:
3744 return true;
3745 }
3746 return false;
3747}
3748
3749bool isSHA1MSG1(unsigned Opcode) {
3750 switch (Opcode) {
3751 case SHA1MSG1rm:
3752 case SHA1MSG1rr:
3753 return true;
3754 }
3755 return false;
3756}
3757
3758bool isVADDPS(unsigned Opcode) {
3759 switch (Opcode) {
3760 case VADDPSYrm:
3761 case VADDPSYrr:
3762 case VADDPSZ128rm:
3763 case VADDPSZ128rmb:
3764 case VADDPSZ128rmbk:
3765 case VADDPSZ128rmbkz:
3766 case VADDPSZ128rmk:
3767 case VADDPSZ128rmkz:
3768 case VADDPSZ128rr:
3769 case VADDPSZ128rrk:
3770 case VADDPSZ128rrkz:
3771 case VADDPSZ256rm:
3772 case VADDPSZ256rmb:
3773 case VADDPSZ256rmbk:
3774 case VADDPSZ256rmbkz:
3775 case VADDPSZ256rmk:
3776 case VADDPSZ256rmkz:
3777 case VADDPSZ256rr:
3778 case VADDPSZ256rrk:
3779 case VADDPSZ256rrkz:
3780 case VADDPSZrm:
3781 case VADDPSZrmb:
3782 case VADDPSZrmbk:
3783 case VADDPSZrmbkz:
3784 case VADDPSZrmk:
3785 case VADDPSZrmkz:
3786 case VADDPSZrr:
3787 case VADDPSZrrb:
3788 case VADDPSZrrbk:
3789 case VADDPSZrrbkz:
3790 case VADDPSZrrk:
3791 case VADDPSZrrkz:
3792 case VADDPSrm:
3793 case VADDPSrr:
3794 return true;
3795 }
3796 return false;
3797}
3798
3799bool isVCVTPS2DQ(unsigned Opcode) {
3800 switch (Opcode) {
3801 case VCVTPS2DQYrm:
3802 case VCVTPS2DQYrr:
3803 case VCVTPS2DQZ128rm:
3804 case VCVTPS2DQZ128rmb:
3805 case VCVTPS2DQZ128rmbk:
3806 case VCVTPS2DQZ128rmbkz:
3807 case VCVTPS2DQZ128rmk:
3808 case VCVTPS2DQZ128rmkz:
3809 case VCVTPS2DQZ128rr:
3810 case VCVTPS2DQZ128rrk:
3811 case VCVTPS2DQZ128rrkz:
3812 case VCVTPS2DQZ256rm:
3813 case VCVTPS2DQZ256rmb:
3814 case VCVTPS2DQZ256rmbk:
3815 case VCVTPS2DQZ256rmbkz:
3816 case VCVTPS2DQZ256rmk:
3817 case VCVTPS2DQZ256rmkz:
3818 case VCVTPS2DQZ256rr:
3819 case VCVTPS2DQZ256rrk:
3820 case VCVTPS2DQZ256rrkz:
3821 case VCVTPS2DQZrm:
3822 case VCVTPS2DQZrmb:
3823 case VCVTPS2DQZrmbk:
3824 case VCVTPS2DQZrmbkz:
3825 case VCVTPS2DQZrmk:
3826 case VCVTPS2DQZrmkz:
3827 case VCVTPS2DQZrr:
3828 case VCVTPS2DQZrrb:
3829 case VCVTPS2DQZrrbk:
3830 case VCVTPS2DQZrrbkz:
3831 case VCVTPS2DQZrrk:
3832 case VCVTPS2DQZrrkz:
3833 case VCVTPS2DQrm:
3834 case VCVTPS2DQrr:
3835 return true;
3836 }
3837 return false;
3838}
3839
3840bool isPFPNACC(unsigned Opcode) {
3841 switch (Opcode) {
3842 case PFPNACCrm:
3843 case PFPNACCrr:
3844 return true;
3845 }
3846 return false;
3847}
3848
3849bool isFMUL(unsigned Opcode) {
3850 switch (Opcode) {
3851 case MUL_F32m:
3852 case MUL_F64m:
3853 case MUL_FST0r:
3854 case MUL_FrST0:
3855 return true;
3856 }
3857 return false;
3858}
3859
3860bool isFNSAVE(unsigned Opcode) {
3861 return Opcode == FSAVEm;
3862}
3863
3864bool isCDQE(unsigned Opcode) {
3865 return Opcode == CDQE;
3866}
3867
3868bool isVPMACSDD(unsigned Opcode) {
3869 switch (Opcode) {
3870 case VPMACSDDrm:
3871 case VPMACSDDrr:
3872 return true;
3873 }
3874 return false;
3875}
3876
3877bool isVSQRTPS(unsigned Opcode) {
3878 switch (Opcode) {
3879 case VSQRTPSYm:
3880 case VSQRTPSYr:
3881 case VSQRTPSZ128m:
3882 case VSQRTPSZ128mb:
3883 case VSQRTPSZ128mbk:
3884 case VSQRTPSZ128mbkz:
3885 case VSQRTPSZ128mk:
3886 case VSQRTPSZ128mkz:
3887 case VSQRTPSZ128r:
3888 case VSQRTPSZ128rk:
3889 case VSQRTPSZ128rkz:
3890 case VSQRTPSZ256m:
3891 case VSQRTPSZ256mb:
3892 case VSQRTPSZ256mbk:
3893 case VSQRTPSZ256mbkz:
3894 case VSQRTPSZ256mk:
3895 case VSQRTPSZ256mkz:
3896 case VSQRTPSZ256r:
3897 case VSQRTPSZ256rk:
3898 case VSQRTPSZ256rkz:
3899 case VSQRTPSZm:
3900 case VSQRTPSZmb:
3901 case VSQRTPSZmbk:
3902 case VSQRTPSZmbkz:
3903 case VSQRTPSZmk:
3904 case VSQRTPSZmkz:
3905 case VSQRTPSZr:
3906 case VSQRTPSZrb:
3907 case VSQRTPSZrbk:
3908 case VSQRTPSZrbkz:
3909 case VSQRTPSZrk:
3910 case VSQRTPSZrkz:
3911 case VSQRTPSm:
3912 case VSQRTPSr:
3913 return true;
3914 }
3915 return false;
3916}
3917
3918bool isCMPSQ(unsigned Opcode) {
3919 return Opcode == CMPSQ;
3920}
3921
3922bool isVPSCATTERDD(unsigned Opcode) {
3923 switch (Opcode) {
3924 case VPSCATTERDDZ128mr:
3925 case VPSCATTERDDZ256mr:
3926 case VPSCATTERDDZmr:
3927 return true;
3928 }
3929 return false;
3930}
3931
3932bool isVCVTTSD2USIS(unsigned Opcode) {
3933 switch (Opcode) {
3934 case VCVTTSD2USI64Srm_Int:
3935 case VCVTTSD2USI64Srr_Int:
3936 case VCVTTSD2USI64Srrb_Int:
3937 case VCVTTSD2USISrm_Int:
3938 case VCVTTSD2USISrr_Int:
3939 case VCVTTSD2USISrrb_Int:
3940 return true;
3941 }
3942 return false;
3943}
3944
3945bool isVRNDSCALESD(unsigned Opcode) {
3946 switch (Opcode) {
3947 case VRNDSCALESDZrmi_Int:
3948 case VRNDSCALESDZrmik_Int:
3949 case VRNDSCALESDZrmikz_Int:
3950 case VRNDSCALESDZrri_Int:
3951 case VRNDSCALESDZrrib_Int:
3952 case VRNDSCALESDZrribk_Int:
3953 case VRNDSCALESDZrribkz_Int:
3954 case VRNDSCALESDZrrik_Int:
3955 case VRNDSCALESDZrrikz_Int:
3956 return true;
3957 }
3958 return false;
3959}
3960
3961bool isSUBPS(unsigned Opcode) {
3962 switch (Opcode) {
3963 case SUBPSrm:
3964 case SUBPSrr:
3965 return true;
3966 }
3967 return false;
3968}
3969
3970bool isVMAXSH(unsigned Opcode) {
3971 switch (Opcode) {
3972 case VMAXSHZrm_Int:
3973 case VMAXSHZrmk_Int:
3974 case VMAXSHZrmkz_Int:
3975 case VMAXSHZrr_Int:
3976 case VMAXSHZrrb_Int:
3977 case VMAXSHZrrbk_Int:
3978 case VMAXSHZrrbkz_Int:
3979 case VMAXSHZrrk_Int:
3980 case VMAXSHZrrkz_Int:
3981 return true;
3982 }
3983 return false;
3984}
3985
3986bool isFLDZ(unsigned Opcode) {
3987 return Opcode == LD_F0;
3988}
3989
3990bool isVFNMADD132SS(unsigned Opcode) {
3991 switch (Opcode) {
3992 case VFNMADD132SSZm_Int:
3993 case VFNMADD132SSZmk_Int:
3994 case VFNMADD132SSZmkz_Int:
3995 case VFNMADD132SSZr_Int:
3996 case VFNMADD132SSZrb_Int:
3997 case VFNMADD132SSZrbk_Int:
3998 case VFNMADD132SSZrbkz_Int:
3999 case VFNMADD132SSZrk_Int:
4000 case VFNMADD132SSZrkz_Int:
4001 case VFNMADD132SSm_Int:
4002 case VFNMADD132SSr_Int:
4003 return true;
4004 }
4005 return false;
4006}
4007
4008bool isLGDTW(unsigned Opcode) {
4009 return Opcode == LGDT16m;
4010}
4011
4012bool isTCVTROWPS2PHH(unsigned Opcode) {
4013 switch (Opcode) {
4014 case TCVTROWPS2PHHrre:
4015 case TCVTROWPS2PHHrri:
4016 return true;
4017 }
4018 return false;
4019}
4020
4021bool isINC(unsigned Opcode) {
4022 switch (Opcode) {
4023 case INC16m:
4024 case INC16m_EVEX:
4025 case INC16m_ND:
4026 case INC16m_NF:
4027 case INC16m_NF_ND:
4028 case INC16r:
4029 case INC16r_EVEX:
4030 case INC16r_ND:
4031 case INC16r_NF:
4032 case INC16r_NF_ND:
4033 case INC16r_alt:
4034 case INC32m:
4035 case INC32m_EVEX:
4036 case INC32m_ND:
4037 case INC32m_NF:
4038 case INC32m_NF_ND:
4039 case INC32r:
4040 case INC32r_EVEX:
4041 case INC32r_ND:
4042 case INC32r_NF:
4043 case INC32r_NF_ND:
4044 case INC32r_alt:
4045 case INC64m:
4046 case INC64m_EVEX:
4047 case INC64m_ND:
4048 case INC64m_NF:
4049 case INC64m_NF_ND:
4050 case INC64r:
4051 case INC64r_EVEX:
4052 case INC64r_ND:
4053 case INC64r_NF:
4054 case INC64r_NF_ND:
4055 case INC8m:
4056 case INC8m_EVEX:
4057 case INC8m_ND:
4058 case INC8m_NF:
4059 case INC8m_NF_ND:
4060 case INC8r:
4061 case INC8r_EVEX:
4062 case INC8r_ND:
4063 case INC8r_NF:
4064 case INC8r_NF_ND:
4065 return true;
4066 }
4067 return false;
4068}
4069
4070bool isVPANDN(unsigned Opcode) {
4071 switch (Opcode) {
4072 case VPANDNYrm:
4073 case VPANDNYrr:
4074 case VPANDNrm:
4075 case VPANDNrr:
4076 return true;
4077 }
4078 return false;
4079}
4080
4081bool isPABSB(unsigned Opcode) {
4082 switch (Opcode) {
4083 case MMX_PABSBrm:
4084 case MMX_PABSBrr:
4085 case PABSBrm:
4086 case PABSBrr:
4087 return true;
4088 }
4089 return false;
4090}
4091
4092bool isVSHA512RNDS2(unsigned Opcode) {
4093 return Opcode == VSHA512RNDS2rr;
4094}
4095
4096bool isPHADDSW(unsigned Opcode) {
4097 switch (Opcode) {
4098 case MMX_PHADDSWrm:
4099 case MMX_PHADDSWrr:
4100 case PHADDSWrm:
4101 case PHADDSWrr:
4102 return true;
4103 }
4104 return false;
4105}
4106
4107bool isVPMAXUD(unsigned Opcode) {
4108 switch (Opcode) {
4109 case VPMAXUDYrm:
4110 case VPMAXUDYrr:
4111 case VPMAXUDZ128rm:
4112 case VPMAXUDZ128rmb:
4113 case VPMAXUDZ128rmbk:
4114 case VPMAXUDZ128rmbkz:
4115 case VPMAXUDZ128rmk:
4116 case VPMAXUDZ128rmkz:
4117 case VPMAXUDZ128rr:
4118 case VPMAXUDZ128rrk:
4119 case VPMAXUDZ128rrkz:
4120 case VPMAXUDZ256rm:
4121 case VPMAXUDZ256rmb:
4122 case VPMAXUDZ256rmbk:
4123 case VPMAXUDZ256rmbkz:
4124 case VPMAXUDZ256rmk:
4125 case VPMAXUDZ256rmkz:
4126 case VPMAXUDZ256rr:
4127 case VPMAXUDZ256rrk:
4128 case VPMAXUDZ256rrkz:
4129 case VPMAXUDZrm:
4130 case VPMAXUDZrmb:
4131 case VPMAXUDZrmbk:
4132 case VPMAXUDZrmbkz:
4133 case VPMAXUDZrmk:
4134 case VPMAXUDZrmkz:
4135 case VPMAXUDZrr:
4136 case VPMAXUDZrrk:
4137 case VPMAXUDZrrkz:
4138 case VPMAXUDrm:
4139 case VPMAXUDrr:
4140 return true;
4141 }
4142 return false;
4143}
4144
4145bool isVPMOVSQW(unsigned Opcode) {
4146 switch (Opcode) {
4147 case VPMOVSQWZ128mr:
4148 case VPMOVSQWZ128mrk:
4149 case VPMOVSQWZ128rr:
4150 case VPMOVSQWZ128rrk:
4151 case VPMOVSQWZ128rrkz:
4152 case VPMOVSQWZ256mr:
4153 case VPMOVSQWZ256mrk:
4154 case VPMOVSQWZ256rr:
4155 case VPMOVSQWZ256rrk:
4156 case VPMOVSQWZ256rrkz:
4157 case VPMOVSQWZmr:
4158 case VPMOVSQWZmrk:
4159 case VPMOVSQWZrr:
4160 case VPMOVSQWZrrk:
4161 case VPMOVSQWZrrkz:
4162 return true;
4163 }
4164 return false;
4165}
4166
4167bool isADDSUBPS(unsigned Opcode) {
4168 switch (Opcode) {
4169 case ADDSUBPSrm:
4170 case ADDSUBPSrr:
4171 return true;
4172 }
4173 return false;
4174}
4175
4176bool isVPMACSSDQL(unsigned Opcode) {
4177 switch (Opcode) {
4178 case VPMACSSDQLrm:
4179 case VPMACSSDQLrr:
4180 return true;
4181 }
4182 return false;
4183}
4184
4185bool isPXOR(unsigned Opcode) {
4186 switch (Opcode) {
4187 case MMX_PXORrm:
4188 case MMX_PXORrr:
4189 case PXORrm:
4190 case PXORrr:
4191 return true;
4192 }
4193 return false;
4194}
4195
4196bool isVPSRAD(unsigned Opcode) {
4197 switch (Opcode) {
4198 case VPSRADYri:
4199 case VPSRADYrm:
4200 case VPSRADYrr:
4201 case VPSRADZ128mbi:
4202 case VPSRADZ128mbik:
4203 case VPSRADZ128mbikz:
4204 case VPSRADZ128mi:
4205 case VPSRADZ128mik:
4206 case VPSRADZ128mikz:
4207 case VPSRADZ128ri:
4208 case VPSRADZ128rik:
4209 case VPSRADZ128rikz:
4210 case VPSRADZ128rm:
4211 case VPSRADZ128rmk:
4212 case VPSRADZ128rmkz:
4213 case VPSRADZ128rr:
4214 case VPSRADZ128rrk:
4215 case VPSRADZ128rrkz:
4216 case VPSRADZ256mbi:
4217 case VPSRADZ256mbik:
4218 case VPSRADZ256mbikz:
4219 case VPSRADZ256mi:
4220 case VPSRADZ256mik:
4221 case VPSRADZ256mikz:
4222 case VPSRADZ256ri:
4223 case VPSRADZ256rik:
4224 case VPSRADZ256rikz:
4225 case VPSRADZ256rm:
4226 case VPSRADZ256rmk:
4227 case VPSRADZ256rmkz:
4228 case VPSRADZ256rr:
4229 case VPSRADZ256rrk:
4230 case VPSRADZ256rrkz:
4231 case VPSRADZmbi:
4232 case VPSRADZmbik:
4233 case VPSRADZmbikz:
4234 case VPSRADZmi:
4235 case VPSRADZmik:
4236 case VPSRADZmikz:
4237 case VPSRADZri:
4238 case VPSRADZrik:
4239 case VPSRADZrikz:
4240 case VPSRADZrm:
4241 case VPSRADZrmk:
4242 case VPSRADZrmkz:
4243 case VPSRADZrr:
4244 case VPSRADZrrk:
4245 case VPSRADZrrkz:
4246 case VPSRADri:
4247 case VPSRADrm:
4248 case VPSRADrr:
4249 return true;
4250 }
4251 return false;
4252}
4253
4254bool isVPSHAB(unsigned Opcode) {
4255 switch (Opcode) {
4256 case VPSHABmr:
4257 case VPSHABrm:
4258 case VPSHABrr:
4259 case VPSHABrr_REV:
4260 return true;
4261 }
4262 return false;
4263}
4264
4265bool isBTR(unsigned Opcode) {
4266 switch (Opcode) {
4267 case BTR16mi8:
4268 case BTR16mr:
4269 case BTR16ri8:
4270 case BTR16rr:
4271 case BTR32mi8:
4272 case BTR32mr:
4273 case BTR32ri8:
4274 case BTR32rr:
4275 case BTR64mi8:
4276 case BTR64mr:
4277 case BTR64ri8:
4278 case BTR64rr:
4279 return true;
4280 }
4281 return false;
4282}
4283
4284bool isKORW(unsigned Opcode) {
4285 return Opcode == KORWkk;
4286}
4287
4288bool isVRANGESS(unsigned Opcode) {
4289 switch (Opcode) {
4290 case VRANGESSZrmi:
4291 case VRANGESSZrmik:
4292 case VRANGESSZrmikz:
4293 case VRANGESSZrri:
4294 case VRANGESSZrrib:
4295 case VRANGESSZrribk:
4296 case VRANGESSZrribkz:
4297 case VRANGESSZrrik:
4298 case VRANGESSZrrikz:
4299 return true;
4300 }
4301 return false;
4302}
4303
4304bool isVCMPPS(unsigned Opcode) {
4305 switch (Opcode) {
4306 case VCMPPSYrmi:
4307 case VCMPPSYrri:
4308 case VCMPPSZ128rmbi:
4309 case VCMPPSZ128rmbik:
4310 case VCMPPSZ128rmi:
4311 case VCMPPSZ128rmik:
4312 case VCMPPSZ128rri:
4313 case VCMPPSZ128rrik:
4314 case VCMPPSZ256rmbi:
4315 case VCMPPSZ256rmbik:
4316 case VCMPPSZ256rmi:
4317 case VCMPPSZ256rmik:
4318 case VCMPPSZ256rri:
4319 case VCMPPSZ256rrik:
4320 case VCMPPSZrmbi:
4321 case VCMPPSZrmbik:
4322 case VCMPPSZrmi:
4323 case VCMPPSZrmik:
4324 case VCMPPSZrri:
4325 case VCMPPSZrrib:
4326 case VCMPPSZrribk:
4327 case VCMPPSZrrik:
4328 case VCMPPSrmi:
4329 case VCMPPSrri:
4330 return true;
4331 }
4332 return false;
4333}
4334
4335bool isVPLZCNTD(unsigned Opcode) {
4336 switch (Opcode) {
4337 case VPLZCNTDZ128rm:
4338 case VPLZCNTDZ128rmb:
4339 case VPLZCNTDZ128rmbk:
4340 case VPLZCNTDZ128rmbkz:
4341 case VPLZCNTDZ128rmk:
4342 case VPLZCNTDZ128rmkz:
4343 case VPLZCNTDZ128rr:
4344 case VPLZCNTDZ128rrk:
4345 case VPLZCNTDZ128rrkz:
4346 case VPLZCNTDZ256rm:
4347 case VPLZCNTDZ256rmb:
4348 case VPLZCNTDZ256rmbk:
4349 case VPLZCNTDZ256rmbkz:
4350 case VPLZCNTDZ256rmk:
4351 case VPLZCNTDZ256rmkz:
4352 case VPLZCNTDZ256rr:
4353 case VPLZCNTDZ256rrk:
4354 case VPLZCNTDZ256rrkz:
4355 case VPLZCNTDZrm:
4356 case VPLZCNTDZrmb:
4357 case VPLZCNTDZrmbk:
4358 case VPLZCNTDZrmbkz:
4359 case VPLZCNTDZrmk:
4360 case VPLZCNTDZrmkz:
4361 case VPLZCNTDZrr:
4362 case VPLZCNTDZrrk:
4363 case VPLZCNTDZrrkz:
4364 return true;
4365 }
4366 return false;
4367}
4368
4369bool isTDPBUUD(unsigned Opcode) {
4370 return Opcode == TDPBUUD;
4371}
4372
4373bool isROUNDPS(unsigned Opcode) {
4374 switch (Opcode) {
4375 case ROUNDPSmi:
4376 case ROUNDPSri:
4377 return true;
4378 }
4379 return false;
4380}
4381
4382bool isFABS(unsigned Opcode) {
4383 return Opcode == ABS_F;
4384}
4385
4386bool isSUBPD(unsigned Opcode) {
4387 switch (Opcode) {
4388 case SUBPDrm:
4389 case SUBPDrr:
4390 return true;
4391 }
4392 return false;
4393}
4394
4395bool isGF2P8MULB(unsigned Opcode) {
4396 switch (Opcode) {
4397 case GF2P8MULBrm:
4398 case GF2P8MULBrr:
4399 return true;
4400 }
4401 return false;
4402}
4403
4404bool isTZMSK(unsigned Opcode) {
4405 switch (Opcode) {
4406 case TZMSK32rm:
4407 case TZMSK32rr:
4408 case TZMSK64rm:
4409 case TZMSK64rr:
4410 return true;
4411 }
4412 return false;
4413}
4414
4415bool isVMINMAXSD(unsigned Opcode) {
4416 switch (Opcode) {
4417 case VMINMAXSDrmi_Int:
4418 case VMINMAXSDrmik_Int:
4419 case VMINMAXSDrmikz_Int:
4420 case VMINMAXSDrri_Int:
4421 case VMINMAXSDrrib_Int:
4422 case VMINMAXSDrribk_Int:
4423 case VMINMAXSDrribkz_Int:
4424 case VMINMAXSDrrik_Int:
4425 case VMINMAXSDrrikz_Int:
4426 return true;
4427 }
4428 return false;
4429}
4430
4431bool isANDPS(unsigned Opcode) {
4432 switch (Opcode) {
4433 case ANDPSrm:
4434 case ANDPSrr:
4435 return true;
4436 }
4437 return false;
4438}
4439
4440bool isVEXTRACTF32X8(unsigned Opcode) {
4441 switch (Opcode) {
4442 case VEXTRACTF32X8Zmri:
4443 case VEXTRACTF32X8Zmrik:
4444 case VEXTRACTF32X8Zrri:
4445 case VEXTRACTF32X8Zrrik:
4446 case VEXTRACTF32X8Zrrikz:
4447 return true;
4448 }
4449 return false;
4450}
4451
4452bool isSEAMRET(unsigned Opcode) {
4453 return Opcode == SEAMRET;
4454}
4455
4456bool isVPCOMW(unsigned Opcode) {
4457 switch (Opcode) {
4458 case VPCOMWmi:
4459 case VPCOMWri:
4460 return true;
4461 }
4462 return false;
4463}
4464
4465bool isVFIXUPIMMPD(unsigned Opcode) {
4466 switch (Opcode) {
4467 case VFIXUPIMMPDZ128rmbi:
4468 case VFIXUPIMMPDZ128rmbik:
4469 case VFIXUPIMMPDZ128rmbikz:
4470 case VFIXUPIMMPDZ128rmi:
4471 case VFIXUPIMMPDZ128rmik:
4472 case VFIXUPIMMPDZ128rmikz:
4473 case VFIXUPIMMPDZ128rri:
4474 case VFIXUPIMMPDZ128rrik:
4475 case VFIXUPIMMPDZ128rrikz:
4476 case VFIXUPIMMPDZ256rmbi:
4477 case VFIXUPIMMPDZ256rmbik:
4478 case VFIXUPIMMPDZ256rmbikz:
4479 case VFIXUPIMMPDZ256rmi:
4480 case VFIXUPIMMPDZ256rmik:
4481 case VFIXUPIMMPDZ256rmikz:
4482 case VFIXUPIMMPDZ256rri:
4483 case VFIXUPIMMPDZ256rrik:
4484 case VFIXUPIMMPDZ256rrikz:
4485 case VFIXUPIMMPDZrmbi:
4486 case VFIXUPIMMPDZrmbik:
4487 case VFIXUPIMMPDZrmbikz:
4488 case VFIXUPIMMPDZrmi:
4489 case VFIXUPIMMPDZrmik:
4490 case VFIXUPIMMPDZrmikz:
4491 case VFIXUPIMMPDZrri:
4492 case VFIXUPIMMPDZrrib:
4493 case VFIXUPIMMPDZrribk:
4494 case VFIXUPIMMPDZrribkz:
4495 case VFIXUPIMMPDZrrik:
4496 case VFIXUPIMMPDZrrikz:
4497 return true;
4498 }
4499 return false;
4500}
4501
4502bool isKANDND(unsigned Opcode) {
4503 return Opcode == KANDNDkk;
4504}
4505
4506bool isVMRESUME(unsigned Opcode) {
4507 return Opcode == VMRESUME;
4508}
4509
4510bool isCVTPD2DQ(unsigned Opcode) {
4511 switch (Opcode) {
4512 case CVTPD2DQrm:
4513 case CVTPD2DQrr:
4514 return true;
4515 }
4516 return false;
4517}
4518
4519bool isVFNMADD213PS(unsigned Opcode) {
4520 switch (Opcode) {
4521 case VFNMADD213PSYm:
4522 case VFNMADD213PSYr:
4523 case VFNMADD213PSZ128m:
4524 case VFNMADD213PSZ128mb:
4525 case VFNMADD213PSZ128mbk:
4526 case VFNMADD213PSZ128mbkz:
4527 case VFNMADD213PSZ128mk:
4528 case VFNMADD213PSZ128mkz:
4529 case VFNMADD213PSZ128r:
4530 case VFNMADD213PSZ128rk:
4531 case VFNMADD213PSZ128rkz:
4532 case VFNMADD213PSZ256m:
4533 case VFNMADD213PSZ256mb:
4534 case VFNMADD213PSZ256mbk:
4535 case VFNMADD213PSZ256mbkz:
4536 case VFNMADD213PSZ256mk:
4537 case VFNMADD213PSZ256mkz:
4538 case VFNMADD213PSZ256r:
4539 case VFNMADD213PSZ256rk:
4540 case VFNMADD213PSZ256rkz:
4541 case VFNMADD213PSZm:
4542 case VFNMADD213PSZmb:
4543 case VFNMADD213PSZmbk:
4544 case VFNMADD213PSZmbkz:
4545 case VFNMADD213PSZmk:
4546 case VFNMADD213PSZmkz:
4547 case VFNMADD213PSZr:
4548 case VFNMADD213PSZrb:
4549 case VFNMADD213PSZrbk:
4550 case VFNMADD213PSZrbkz:
4551 case VFNMADD213PSZrk:
4552 case VFNMADD213PSZrkz:
4553 case VFNMADD213PSm:
4554 case VFNMADD213PSr:
4555 return true;
4556 }
4557 return false;
4558}
4559
4560bool isVPEXTRD(unsigned Opcode) {
4561 switch (Opcode) {
4562 case VPEXTRDZmri:
4563 case VPEXTRDZrri:
4564 case VPEXTRDmri:
4565 case VPEXTRDrri:
4566 return true;
4567 }
4568 return false;
4569}
4570
4571bool isPACKUSWB(unsigned Opcode) {
4572 switch (Opcode) {
4573 case MMX_PACKUSWBrm:
4574 case MMX_PACKUSWBrr:
4575 case PACKUSWBrm:
4576 case PACKUSWBrr:
4577 return true;
4578 }
4579 return false;
4580}
4581
4582bool isVEXTRACTI32X8(unsigned Opcode) {
4583 switch (Opcode) {
4584 case VEXTRACTI32X8Zmri:
4585 case VEXTRACTI32X8Zmrik:
4586 case VEXTRACTI32X8Zrri:
4587 case VEXTRACTI32X8Zrrik:
4588 case VEXTRACTI32X8Zrrikz:
4589 return true;
4590 }
4591 return false;
4592}
4593
4594bool isVHADDPD(unsigned Opcode) {
4595 switch (Opcode) {
4596 case VHADDPDYrm:
4597 case VHADDPDYrr:
4598 case VHADDPDrm:
4599 case VHADDPDrr:
4600 return true;
4601 }
4602 return false;
4603}
4604
4605bool isVPSADBW(unsigned Opcode) {
4606 switch (Opcode) {
4607 case VPSADBWYrm:
4608 case VPSADBWYrr:
4609 case VPSADBWZ128rm:
4610 case VPSADBWZ128rr:
4611 case VPSADBWZ256rm:
4612 case VPSADBWZ256rr:
4613 case VPSADBWZrm:
4614 case VPSADBWZrr:
4615 case VPSADBWrm:
4616 case VPSADBWrr:
4617 return true;
4618 }
4619 return false;
4620}
4621
4622bool isMOVDQ2Q(unsigned Opcode) {
4623 return Opcode == MMX_MOVDQ2Qrr;
4624}
4625
4626bool isPUNPCKHBW(unsigned Opcode) {
4627 switch (Opcode) {
4628 case MMX_PUNPCKHBWrm:
4629 case MMX_PUNPCKHBWrr:
4630 case PUNPCKHBWrm:
4631 case PUNPCKHBWrr:
4632 return true;
4633 }
4634 return false;
4635}
4636
4637bool isXOR(unsigned Opcode) {
4638 switch (Opcode) {
4639 case XOR16i16:
4640 case XOR16mi:
4641 case XOR16mi8:
4642 case XOR16mi8_EVEX:
4643 case XOR16mi8_ND:
4644 case XOR16mi8_NF:
4645 case XOR16mi8_NF_ND:
4646 case XOR16mi_EVEX:
4647 case XOR16mi_ND:
4648 case XOR16mi_NF:
4649 case XOR16mi_NF_ND:
4650 case XOR16mr:
4651 case XOR16mr_EVEX:
4652 case XOR16mr_ND:
4653 case XOR16mr_NF:
4654 case XOR16mr_NF_ND:
4655 case XOR16ri:
4656 case XOR16ri8:
4657 case XOR16ri8_EVEX:
4658 case XOR16ri8_ND:
4659 case XOR16ri8_NF:
4660 case XOR16ri8_NF_ND:
4661 case XOR16ri_EVEX:
4662 case XOR16ri_ND:
4663 case XOR16ri_NF:
4664 case XOR16ri_NF_ND:
4665 case XOR16rm:
4666 case XOR16rm_EVEX:
4667 case XOR16rm_ND:
4668 case XOR16rm_NF:
4669 case XOR16rm_NF_ND:
4670 case XOR16rr:
4671 case XOR16rr_EVEX:
4672 case XOR16rr_EVEX_REV:
4673 case XOR16rr_ND:
4674 case XOR16rr_ND_REV:
4675 case XOR16rr_NF:
4676 case XOR16rr_NF_ND:
4677 case XOR16rr_NF_ND_REV:
4678 case XOR16rr_NF_REV:
4679 case XOR16rr_REV:
4680 case XOR32i32:
4681 case XOR32mi:
4682 case XOR32mi8:
4683 case XOR32mi8_EVEX:
4684 case XOR32mi8_ND:
4685 case XOR32mi8_NF:
4686 case XOR32mi8_NF_ND:
4687 case XOR32mi_EVEX:
4688 case XOR32mi_ND:
4689 case XOR32mi_NF:
4690 case XOR32mi_NF_ND:
4691 case XOR32mr:
4692 case XOR32mr_EVEX:
4693 case XOR32mr_ND:
4694 case XOR32mr_NF:
4695 case XOR32mr_NF_ND:
4696 case XOR32ri:
4697 case XOR32ri8:
4698 case XOR32ri8_EVEX:
4699 case XOR32ri8_ND:
4700 case XOR32ri8_NF:
4701 case XOR32ri8_NF_ND:
4702 case XOR32ri_EVEX:
4703 case XOR32ri_ND:
4704 case XOR32ri_NF:
4705 case XOR32ri_NF_ND:
4706 case XOR32rm:
4707 case XOR32rm_EVEX:
4708 case XOR32rm_ND:
4709 case XOR32rm_NF:
4710 case XOR32rm_NF_ND:
4711 case XOR32rr:
4712 case XOR32rr_EVEX:
4713 case XOR32rr_EVEX_REV:
4714 case XOR32rr_ND:
4715 case XOR32rr_ND_REV:
4716 case XOR32rr_NF:
4717 case XOR32rr_NF_ND:
4718 case XOR32rr_NF_ND_REV:
4719 case XOR32rr_NF_REV:
4720 case XOR32rr_REV:
4721 case XOR64i32:
4722 case XOR64mi32:
4723 case XOR64mi32_EVEX:
4724 case XOR64mi32_ND:
4725 case XOR64mi32_NF:
4726 case XOR64mi32_NF_ND:
4727 case XOR64mi8:
4728 case XOR64mi8_EVEX:
4729 case XOR64mi8_ND:
4730 case XOR64mi8_NF:
4731 case XOR64mi8_NF_ND:
4732 case XOR64mr:
4733 case XOR64mr_EVEX:
4734 case XOR64mr_ND:
4735 case XOR64mr_NF:
4736 case XOR64mr_NF_ND:
4737 case XOR64ri32:
4738 case XOR64ri32_EVEX:
4739 case XOR64ri32_ND:
4740 case XOR64ri32_NF:
4741 case XOR64ri32_NF_ND:
4742 case XOR64ri8:
4743 case XOR64ri8_EVEX:
4744 case XOR64ri8_ND:
4745 case XOR64ri8_NF:
4746 case XOR64ri8_NF_ND:
4747 case XOR64rm:
4748 case XOR64rm_EVEX:
4749 case XOR64rm_ND:
4750 case XOR64rm_NF:
4751 case XOR64rm_NF_ND:
4752 case XOR64rr:
4753 case XOR64rr_EVEX:
4754 case XOR64rr_EVEX_REV:
4755 case XOR64rr_ND:
4756 case XOR64rr_ND_REV:
4757 case XOR64rr_NF:
4758 case XOR64rr_NF_ND:
4759 case XOR64rr_NF_ND_REV:
4760 case XOR64rr_NF_REV:
4761 case XOR64rr_REV:
4762 case XOR8i8:
4763 case XOR8mi:
4764 case XOR8mi8:
4765 case XOR8mi_EVEX:
4766 case XOR8mi_ND:
4767 case XOR8mi_NF:
4768 case XOR8mi_NF_ND:
4769 case XOR8mr:
4770 case XOR8mr_EVEX:
4771 case XOR8mr_ND:
4772 case XOR8mr_NF:
4773 case XOR8mr_NF_ND:
4774 case XOR8ri:
4775 case XOR8ri8:
4776 case XOR8ri_EVEX:
4777 case XOR8ri_ND:
4778 case XOR8ri_NF:
4779 case XOR8ri_NF_ND:
4780 case XOR8rm:
4781 case XOR8rm_EVEX:
4782 case XOR8rm_ND:
4783 case XOR8rm_NF:
4784 case XOR8rm_NF_ND:
4785 case XOR8rr:
4786 case XOR8rr_EVEX:
4787 case XOR8rr_EVEX_REV:
4788 case XOR8rr_ND:
4789 case XOR8rr_ND_REV:
4790 case XOR8rr_NF:
4791 case XOR8rr_NF_ND:
4792 case XOR8rr_NF_ND_REV:
4793 case XOR8rr_NF_REV:
4794 case XOR8rr_REV:
4795 return true;
4796 }
4797 return false;
4798}
4799
4800bool isPSIGNB(unsigned Opcode) {
4801 switch (Opcode) {
4802 case MMX_PSIGNBrm:
4803 case MMX_PSIGNBrr:
4804 case PSIGNBrm:
4805 case PSIGNBrr:
4806 return true;
4807 }
4808 return false;
4809}
4810
4811bool isVPHADDSW(unsigned Opcode) {
4812 switch (Opcode) {
4813 case VPHADDSWYrm:
4814 case VPHADDSWYrr:
4815 case VPHADDSWrm:
4816 case VPHADDSWrr:
4817 return true;
4818 }
4819 return false;
4820}
4821
4822bool isFADDP(unsigned Opcode) {
4823 return Opcode == ADD_FPrST0;
4824}
4825
4826bool isNEG(unsigned Opcode) {
4827 switch (Opcode) {
4828 case NEG16m:
4829 case NEG16m_EVEX:
4830 case NEG16m_ND:
4831 case NEG16m_NF:
4832 case NEG16m_NF_ND:
4833 case NEG16r:
4834 case NEG16r_EVEX:
4835 case NEG16r_ND:
4836 case NEG16r_NF:
4837 case NEG16r_NF_ND:
4838 case NEG32m:
4839 case NEG32m_EVEX:
4840 case NEG32m_ND:
4841 case NEG32m_NF:
4842 case NEG32m_NF_ND:
4843 case NEG32r:
4844 case NEG32r_EVEX:
4845 case NEG32r_ND:
4846 case NEG32r_NF:
4847 case NEG32r_NF_ND:
4848 case NEG64m:
4849 case NEG64m_EVEX:
4850 case NEG64m_ND:
4851 case NEG64m_NF:
4852 case NEG64m_NF_ND:
4853 case NEG64r:
4854 case NEG64r_EVEX:
4855 case NEG64r_ND:
4856 case NEG64r_NF:
4857 case NEG64r_NF_ND:
4858 case NEG8m:
4859 case NEG8m_EVEX:
4860 case NEG8m_ND:
4861 case NEG8m_NF:
4862 case NEG8m_NF_ND:
4863 case NEG8r:
4864 case NEG8r_EVEX:
4865 case NEG8r_ND:
4866 case NEG8r_NF:
4867 case NEG8r_NF_ND:
4868 return true;
4869 }
4870 return false;
4871}
4872
4873bool isFLDLG2(unsigned Opcode) {
4874 return Opcode == FLDLG2;
4875}
4876
4877bool isFNOP(unsigned Opcode) {
4878 return Opcode == FNOP;
4879}
4880
4881bool isVMINSS(unsigned Opcode) {
4882 switch (Opcode) {
4883 case VMINSSZrm_Int:
4884 case VMINSSZrmk_Int:
4885 case VMINSSZrmkz_Int:
4886 case VMINSSZrr_Int:
4887 case VMINSSZrrb_Int:
4888 case VMINSSZrrbk_Int:
4889 case VMINSSZrrbkz_Int:
4890 case VMINSSZrrk_Int:
4891 case VMINSSZrrkz_Int:
4892 case VMINSSrm_Int:
4893 case VMINSSrr_Int:
4894 return true;
4895 }
4896 return false;
4897}
4898
4899bool isPCMPISTRM(unsigned Opcode) {
4900 switch (Opcode) {
4901 case PCMPISTRMrmi:
4902 case PCMPISTRMrri:
4903 return true;
4904 }
4905 return false;
4906}
4907
4908bool isVFMADD132SS(unsigned Opcode) {
4909 switch (Opcode) {
4910 case VFMADD132SSZm_Int:
4911 case VFMADD132SSZmk_Int:
4912 case VFMADD132SSZmkz_Int:
4913 case VFMADD132SSZr_Int:
4914 case VFMADD132SSZrb_Int:
4915 case VFMADD132SSZrbk_Int:
4916 case VFMADD132SSZrbkz_Int:
4917 case VFMADD132SSZrk_Int:
4918 case VFMADD132SSZrkz_Int:
4919 case VFMADD132SSm_Int:
4920 case VFMADD132SSr_Int:
4921 return true;
4922 }
4923 return false;
4924}
4925
4926bool isFDIVRP(unsigned Opcode) {
4927 return Opcode == DIVR_FPrST0;
4928}
4929
4930bool isPUSHAL(unsigned Opcode) {
4931 return Opcode == PUSHA32;
4932}
4933
4934bool isVPMACSDQL(unsigned Opcode) {
4935 switch (Opcode) {
4936 case VPMACSDQLrm:
4937 case VPMACSDQLrr:
4938 return true;
4939 }
4940 return false;
4941}
4942
4943bool isSUBSD(unsigned Opcode) {
4944 switch (Opcode) {
4945 case SUBSDrm_Int:
4946 case SUBSDrr_Int:
4947 return true;
4948 }
4949 return false;
4950}
4951
4952bool isVPBLENDMQ(unsigned Opcode) {
4953 switch (Opcode) {
4954 case VPBLENDMQZ128rm:
4955 case VPBLENDMQZ128rmb:
4956 case VPBLENDMQZ128rmbk:
4957 case VPBLENDMQZ128rmbkz:
4958 case VPBLENDMQZ128rmk:
4959 case VPBLENDMQZ128rmkz:
4960 case VPBLENDMQZ128rr:
4961 case VPBLENDMQZ128rrk:
4962 case VPBLENDMQZ128rrkz:
4963 case VPBLENDMQZ256rm:
4964 case VPBLENDMQZ256rmb:
4965 case VPBLENDMQZ256rmbk:
4966 case VPBLENDMQZ256rmbkz:
4967 case VPBLENDMQZ256rmk:
4968 case VPBLENDMQZ256rmkz:
4969 case VPBLENDMQZ256rr:
4970 case VPBLENDMQZ256rrk:
4971 case VPBLENDMQZ256rrkz:
4972 case VPBLENDMQZrm:
4973 case VPBLENDMQZrmb:
4974 case VPBLENDMQZrmbk:
4975 case VPBLENDMQZrmbkz:
4976 case VPBLENDMQZrmk:
4977 case VPBLENDMQZrmkz:
4978 case VPBLENDMQZrr:
4979 case VPBLENDMQZrrk:
4980 case VPBLENDMQZrrkz:
4981 return true;
4982 }
4983 return false;
4984}
4985
4986bool isVGATHERDPS(unsigned Opcode) {
4987 switch (Opcode) {
4988 case VGATHERDPSYrm:
4989 case VGATHERDPSZ128rm:
4990 case VGATHERDPSZ256rm:
4991 case VGATHERDPSZrm:
4992 case VGATHERDPSrm:
4993 return true;
4994 }
4995 return false;
4996}
4997
4998bool isSYSRET(unsigned Opcode) {
4999 return Opcode == SYSRET;
5000}
5001
5002bool isVPADDB(unsigned Opcode) {
5003 switch (Opcode) {
5004 case VPADDBYrm:
5005 case VPADDBYrr:
5006 case VPADDBZ128rm:
5007 case VPADDBZ128rmk:
5008 case VPADDBZ128rmkz:
5009 case VPADDBZ128rr:
5010 case VPADDBZ128rrk:
5011 case VPADDBZ128rrkz:
5012 case VPADDBZ256rm:
5013 case VPADDBZ256rmk:
5014 case VPADDBZ256rmkz:
5015 case VPADDBZ256rr:
5016 case VPADDBZ256rrk:
5017 case VPADDBZ256rrkz:
5018 case VPADDBZrm:
5019 case VPADDBZrmk:
5020 case VPADDBZrmkz:
5021 case VPADDBZrr:
5022 case VPADDBZrrk:
5023 case VPADDBZrrkz:
5024 case VPADDBrm:
5025 case VPADDBrr:
5026 return true;
5027 }
5028 return false;
5029}
5030
5031bool isXEND(unsigned Opcode) {
5032 return Opcode == XEND;
5033}
5034
5035bool isWRSSD(unsigned Opcode) {
5036 switch (Opcode) {
5037 case WRSSD:
5038 case WRSSD_EVEX:
5039 return true;
5040 }
5041 return false;
5042}
5043
5044bool isVMINMAXSS(unsigned Opcode) {
5045 switch (Opcode) {
5046 case VMINMAXSSrmi_Int:
5047 case VMINMAXSSrmik_Int:
5048 case VMINMAXSSrmikz_Int:
5049 case VMINMAXSSrri_Int:
5050 case VMINMAXSSrrib_Int:
5051 case VMINMAXSSrribk_Int:
5052 case VMINMAXSSrribkz_Int:
5053 case VMINMAXSSrrik_Int:
5054 case VMINMAXSSrrikz_Int:
5055 return true;
5056 }
5057 return false;
5058}
5059
5060bool isVCVTDQ2PH(unsigned Opcode) {
5061 switch (Opcode) {
5062 case VCVTDQ2PHZ128rm:
5063 case VCVTDQ2PHZ128rmb:
5064 case VCVTDQ2PHZ128rmbk:
5065 case VCVTDQ2PHZ128rmbkz:
5066 case VCVTDQ2PHZ128rmk:
5067 case VCVTDQ2PHZ128rmkz:
5068 case VCVTDQ2PHZ128rr:
5069 case VCVTDQ2PHZ128rrk:
5070 case VCVTDQ2PHZ128rrkz:
5071 case VCVTDQ2PHZ256rm:
5072 case VCVTDQ2PHZ256rmb:
5073 case VCVTDQ2PHZ256rmbk:
5074 case VCVTDQ2PHZ256rmbkz:
5075 case VCVTDQ2PHZ256rmk:
5076 case VCVTDQ2PHZ256rmkz:
5077 case VCVTDQ2PHZ256rr:
5078 case VCVTDQ2PHZ256rrk:
5079 case VCVTDQ2PHZ256rrkz:
5080 case VCVTDQ2PHZrm:
5081 case VCVTDQ2PHZrmb:
5082 case VCVTDQ2PHZrmbk:
5083 case VCVTDQ2PHZrmbkz:
5084 case VCVTDQ2PHZrmk:
5085 case VCVTDQ2PHZrmkz:
5086 case VCVTDQ2PHZrr:
5087 case VCVTDQ2PHZrrb:
5088 case VCVTDQ2PHZrrbk:
5089 case VCVTDQ2PHZrrbkz:
5090 case VCVTDQ2PHZrrk:
5091 case VCVTDQ2PHZrrkz:
5092 return true;
5093 }
5094 return false;
5095}
5096
5097bool isCVTPD2PS(unsigned Opcode) {
5098 switch (Opcode) {
5099 case CVTPD2PSrm:
5100 case CVTPD2PSrr:
5101 return true;
5102 }
5103 return false;
5104}
5105
5106bool isMAXPD(unsigned Opcode) {
5107 switch (Opcode) {
5108 case MAXPDrm:
5109 case MAXPDrr:
5110 return true;
5111 }
5112 return false;
5113}
5114
5115bool isRCPSS(unsigned Opcode) {
5116 switch (Opcode) {
5117 case RCPSSm_Int:
5118 case RCPSSr_Int:
5119 return true;
5120 }
5121 return false;
5122}
5123
5124bool isVMOVAPD(unsigned Opcode) {
5125 switch (Opcode) {
5126 case VMOVAPDYmr:
5127 case VMOVAPDYrm:
5128 case VMOVAPDYrr:
5129 case VMOVAPDYrr_REV:
5130 case VMOVAPDZ128mr:
5131 case VMOVAPDZ128mrk:
5132 case VMOVAPDZ128rm:
5133 case VMOVAPDZ128rmk:
5134 case VMOVAPDZ128rmkz:
5135 case VMOVAPDZ128rr:
5136 case VMOVAPDZ128rr_REV:
5137 case VMOVAPDZ128rrk:
5138 case VMOVAPDZ128rrk_REV:
5139 case VMOVAPDZ128rrkz:
5140 case VMOVAPDZ128rrkz_REV:
5141 case VMOVAPDZ256mr:
5142 case VMOVAPDZ256mrk:
5143 case VMOVAPDZ256rm:
5144 case VMOVAPDZ256rmk:
5145 case VMOVAPDZ256rmkz:
5146 case VMOVAPDZ256rr:
5147 case VMOVAPDZ256rr_REV:
5148 case VMOVAPDZ256rrk:
5149 case VMOVAPDZ256rrk_REV:
5150 case VMOVAPDZ256rrkz:
5151 case VMOVAPDZ256rrkz_REV:
5152 case VMOVAPDZmr:
5153 case VMOVAPDZmrk:
5154 case VMOVAPDZrm:
5155 case VMOVAPDZrmk:
5156 case VMOVAPDZrmkz:
5157 case VMOVAPDZrr:
5158 case VMOVAPDZrr_REV:
5159 case VMOVAPDZrrk:
5160 case VMOVAPDZrrk_REV:
5161 case VMOVAPDZrrkz:
5162 case VMOVAPDZrrkz_REV:
5163 case VMOVAPDmr:
5164 case VMOVAPDrm:
5165 case VMOVAPDrr:
5166 case VMOVAPDrr_REV:
5167 return true;
5168 }
5169 return false;
5170}
5171
5172bool isVPSUBSB(unsigned Opcode) {
5173 switch (Opcode) {
5174 case VPSUBSBYrm:
5175 case VPSUBSBYrr:
5176 case VPSUBSBZ128rm:
5177 case VPSUBSBZ128rmk:
5178 case VPSUBSBZ128rmkz:
5179 case VPSUBSBZ128rr:
5180 case VPSUBSBZ128rrk:
5181 case VPSUBSBZ128rrkz:
5182 case VPSUBSBZ256rm:
5183 case VPSUBSBZ256rmk:
5184 case VPSUBSBZ256rmkz:
5185 case VPSUBSBZ256rr:
5186 case VPSUBSBZ256rrk:
5187 case VPSUBSBZ256rrkz:
5188 case VPSUBSBZrm:
5189 case VPSUBSBZrmk:
5190 case VPSUBSBZrmkz:
5191 case VPSUBSBZrr:
5192 case VPSUBSBZrrk:
5193 case VPSUBSBZrrkz:
5194 case VPSUBSBrm:
5195 case VPSUBSBrr:
5196 return true;
5197 }
5198 return false;
5199}
5200
5201bool isRDTSC(unsigned Opcode) {
5202 return Opcode == RDTSC;
5203}
5204
5205bool isVCVTTPS2UDQS(unsigned Opcode) {
5206 switch (Opcode) {
5207 case VCVTTPS2UDQSZ128rm:
5208 case VCVTTPS2UDQSZ128rmb:
5209 case VCVTTPS2UDQSZ128rmbk:
5210 case VCVTTPS2UDQSZ128rmbkz:
5211 case VCVTTPS2UDQSZ128rmk:
5212 case VCVTTPS2UDQSZ128rmkz:
5213 case VCVTTPS2UDQSZ128rr:
5214 case VCVTTPS2UDQSZ128rrk:
5215 case VCVTTPS2UDQSZ128rrkz:
5216 case VCVTTPS2UDQSZ256rm:
5217 case VCVTTPS2UDQSZ256rmb:
5218 case VCVTTPS2UDQSZ256rmbk:
5219 case VCVTTPS2UDQSZ256rmbkz:
5220 case VCVTTPS2UDQSZ256rmk:
5221 case VCVTTPS2UDQSZ256rmkz:
5222 case VCVTTPS2UDQSZ256rr:
5223 case VCVTTPS2UDQSZ256rrk:
5224 case VCVTTPS2UDQSZ256rrkz:
5225 case VCVTTPS2UDQSZrm:
5226 case VCVTTPS2UDQSZrmb:
5227 case VCVTTPS2UDQSZrmbk:
5228 case VCVTTPS2UDQSZrmbkz:
5229 case VCVTTPS2UDQSZrmk:
5230 case VCVTTPS2UDQSZrmkz:
5231 case VCVTTPS2UDQSZrr:
5232 case VCVTTPS2UDQSZrrb:
5233 case VCVTTPS2UDQSZrrbk:
5234 case VCVTTPS2UDQSZrrbkz:
5235 case VCVTTPS2UDQSZrrk:
5236 case VCVTTPS2UDQSZrrkz:
5237 return true;
5238 }
5239 return false;
5240}
5241
5242bool isVPMADCSSWD(unsigned Opcode) {
5243 switch (Opcode) {
5244 case VPMADCSSWDrm:
5245 case VPMADCSSWDrr:
5246 return true;
5247 }
5248 return false;
5249}
5250
5251bool isVFNMADD213PH(unsigned Opcode) {
5252 switch (Opcode) {
5253 case VFNMADD213PHZ128m:
5254 case VFNMADD213PHZ128mb:
5255 case VFNMADD213PHZ128mbk:
5256 case VFNMADD213PHZ128mbkz:
5257 case VFNMADD213PHZ128mk:
5258 case VFNMADD213PHZ128mkz:
5259 case VFNMADD213PHZ128r:
5260 case VFNMADD213PHZ128rk:
5261 case VFNMADD213PHZ128rkz:
5262 case VFNMADD213PHZ256m:
5263 case VFNMADD213PHZ256mb:
5264 case VFNMADD213PHZ256mbk:
5265 case VFNMADD213PHZ256mbkz:
5266 case VFNMADD213PHZ256mk:
5267 case VFNMADD213PHZ256mkz:
5268 case VFNMADD213PHZ256r:
5269 case VFNMADD213PHZ256rk:
5270 case VFNMADD213PHZ256rkz:
5271 case VFNMADD213PHZm:
5272 case VFNMADD213PHZmb:
5273 case VFNMADD213PHZmbk:
5274 case VFNMADD213PHZmbkz:
5275 case VFNMADD213PHZmk:
5276 case VFNMADD213PHZmkz:
5277 case VFNMADD213PHZr:
5278 case VFNMADD213PHZrb:
5279 case VFNMADD213PHZrbk:
5280 case VFNMADD213PHZrbkz:
5281 case VFNMADD213PHZrk:
5282 case VFNMADD213PHZrkz:
5283 return true;
5284 }
5285 return false;
5286}
5287
5288bool isVGF2P8AFFINEQB(unsigned Opcode) {
5289 switch (Opcode) {
5290 case VGF2P8AFFINEQBYrmi:
5291 case VGF2P8AFFINEQBYrri:
5292 case VGF2P8AFFINEQBZ128rmbi:
5293 case VGF2P8AFFINEQBZ128rmbik:
5294 case VGF2P8AFFINEQBZ128rmbikz:
5295 case VGF2P8AFFINEQBZ128rmi:
5296 case VGF2P8AFFINEQBZ128rmik:
5297 case VGF2P8AFFINEQBZ128rmikz:
5298 case VGF2P8AFFINEQBZ128rri:
5299 case VGF2P8AFFINEQBZ128rrik:
5300 case VGF2P8AFFINEQBZ128rrikz:
5301 case VGF2P8AFFINEQBZ256rmbi:
5302 case VGF2P8AFFINEQBZ256rmbik:
5303 case VGF2P8AFFINEQBZ256rmbikz:
5304 case VGF2P8AFFINEQBZ256rmi:
5305 case VGF2P8AFFINEQBZ256rmik:
5306 case VGF2P8AFFINEQBZ256rmikz:
5307 case VGF2P8AFFINEQBZ256rri:
5308 case VGF2P8AFFINEQBZ256rrik:
5309 case VGF2P8AFFINEQBZ256rrikz:
5310 case VGF2P8AFFINEQBZrmbi:
5311 case VGF2P8AFFINEQBZrmbik:
5312 case VGF2P8AFFINEQBZrmbikz:
5313 case VGF2P8AFFINEQBZrmi:
5314 case VGF2P8AFFINEQBZrmik:
5315 case VGF2P8AFFINEQBZrmikz:
5316 case VGF2P8AFFINEQBZrri:
5317 case VGF2P8AFFINEQBZrrik:
5318 case VGF2P8AFFINEQBZrrikz:
5319 case VGF2P8AFFINEQBrmi:
5320 case VGF2P8AFFINEQBrri:
5321 return true;
5322 }
5323 return false;
5324}
5325
5326bool isPMOVZXWD(unsigned Opcode) {
5327 switch (Opcode) {
5328 case PMOVZXWDrm:
5329 case PMOVZXWDrr:
5330 return true;
5331 }
5332 return false;
5333}
5334
5335bool isPMINUD(unsigned Opcode) {
5336 switch (Opcode) {
5337 case PMINUDrm:
5338 case PMINUDrr:
5339 return true;
5340 }
5341 return false;
5342}
5343
5344bool isVCVTPH2UW(unsigned Opcode) {
5345 switch (Opcode) {
5346 case VCVTPH2UWZ128rm:
5347 case VCVTPH2UWZ128rmb:
5348 case VCVTPH2UWZ128rmbk:
5349 case VCVTPH2UWZ128rmbkz:
5350 case VCVTPH2UWZ128rmk:
5351 case VCVTPH2UWZ128rmkz:
5352 case VCVTPH2UWZ128rr:
5353 case VCVTPH2UWZ128rrk:
5354 case VCVTPH2UWZ128rrkz:
5355 case VCVTPH2UWZ256rm:
5356 case VCVTPH2UWZ256rmb:
5357 case VCVTPH2UWZ256rmbk:
5358 case VCVTPH2UWZ256rmbkz:
5359 case VCVTPH2UWZ256rmk:
5360 case VCVTPH2UWZ256rmkz:
5361 case VCVTPH2UWZ256rr:
5362 case VCVTPH2UWZ256rrk:
5363 case VCVTPH2UWZ256rrkz:
5364 case VCVTPH2UWZrm:
5365 case VCVTPH2UWZrmb:
5366 case VCVTPH2UWZrmbk:
5367 case VCVTPH2UWZrmbkz:
5368 case VCVTPH2UWZrmk:
5369 case VCVTPH2UWZrmkz:
5370 case VCVTPH2UWZrr:
5371 case VCVTPH2UWZrrb:
5372 case VCVTPH2UWZrrbk:
5373 case VCVTPH2UWZrrbkz:
5374 case VCVTPH2UWZrrk:
5375 case VCVTPH2UWZrrkz:
5376 return true;
5377 }
5378 return false;
5379}
5380
5381bool isPADDSW(unsigned Opcode) {
5382 switch (Opcode) {
5383 case MMX_PADDSWrm:
5384 case MMX_PADDSWrr:
5385 case PADDSWrm:
5386 case PADDSWrr:
5387 return true;
5388 }
5389 return false;
5390}
5391
5392bool isXSUSLDTRK(unsigned Opcode) {
5393 return Opcode == XSUSLDTRK;
5394}
5395
5396bool isLFENCE(unsigned Opcode) {
5397 return Opcode == LFENCE;
5398}
5399
5400bool isCRC32(unsigned Opcode) {
5401 switch (Opcode) {
5402 case CRC32r32m16:
5403 case CRC32r32m16_EVEX:
5404 case CRC32r32m32:
5405 case CRC32r32m32_EVEX:
5406 case CRC32r32m8:
5407 case CRC32r32m8_EVEX:
5408 case CRC32r32r16:
5409 case CRC32r32r16_EVEX:
5410 case CRC32r32r32:
5411 case CRC32r32r32_EVEX:
5412 case CRC32r32r8:
5413 case CRC32r32r8_EVEX:
5414 case CRC32r64m64:
5415 case CRC32r64m64_EVEX:
5416 case CRC32r64m8:
5417 case CRC32r64m8_EVEX:
5418 case CRC32r64r64:
5419 case CRC32r64r64_EVEX:
5420 case CRC32r64r8:
5421 case CRC32r64r8_EVEX:
5422 return true;
5423 }
5424 return false;
5425}
5426
5427bool isAESENCWIDE256KL(unsigned Opcode) {
5428 return Opcode == AESENCWIDE256KL;
5429}
5430
5431bool isMOVAPD(unsigned Opcode) {
5432 switch (Opcode) {
5433 case MOVAPDmr:
5434 case MOVAPDrm:
5435 case MOVAPDrr:
5436 case MOVAPDrr_REV:
5437 return true;
5438 }
5439 return false;
5440}
5441
5442bool isVFMADD213PS(unsigned Opcode) {
5443 switch (Opcode) {
5444 case VFMADD213PSYm:
5445 case VFMADD213PSYr:
5446 case VFMADD213PSZ128m:
5447 case VFMADD213PSZ128mb:
5448 case VFMADD213PSZ128mbk:
5449 case VFMADD213PSZ128mbkz:
5450 case VFMADD213PSZ128mk:
5451 case VFMADD213PSZ128mkz:
5452 case VFMADD213PSZ128r:
5453 case VFMADD213PSZ128rk:
5454 case VFMADD213PSZ128rkz:
5455 case VFMADD213PSZ256m:
5456 case VFMADD213PSZ256mb:
5457 case VFMADD213PSZ256mbk:
5458 case VFMADD213PSZ256mbkz:
5459 case VFMADD213PSZ256mk:
5460 case VFMADD213PSZ256mkz:
5461 case VFMADD213PSZ256r:
5462 case VFMADD213PSZ256rk:
5463 case VFMADD213PSZ256rkz:
5464 case VFMADD213PSZm:
5465 case VFMADD213PSZmb:
5466 case VFMADD213PSZmbk:
5467 case VFMADD213PSZmbkz:
5468 case VFMADD213PSZmk:
5469 case VFMADD213PSZmkz:
5470 case VFMADD213PSZr:
5471 case VFMADD213PSZrb:
5472 case VFMADD213PSZrbk:
5473 case VFMADD213PSZrbkz:
5474 case VFMADD213PSZrk:
5475 case VFMADD213PSZrkz:
5476 case VFMADD213PSm:
5477 case VFMADD213PSr:
5478 return true;
5479 }
5480 return false;
5481}
5482
5483bool isVPDPWUUDS(unsigned Opcode) {
5484 switch (Opcode) {
5485 case VPDPWUUDSYrm:
5486 case VPDPWUUDSYrr:
5487 case VPDPWUUDSZ128m:
5488 case VPDPWUUDSZ128mb:
5489 case VPDPWUUDSZ128mbk:
5490 case VPDPWUUDSZ128mbkz:
5491 case VPDPWUUDSZ128mk:
5492 case VPDPWUUDSZ128mkz:
5493 case VPDPWUUDSZ128r:
5494 case VPDPWUUDSZ128rk:
5495 case VPDPWUUDSZ128rkz:
5496 case VPDPWUUDSZ256m:
5497 case VPDPWUUDSZ256mb:
5498 case VPDPWUUDSZ256mbk:
5499 case VPDPWUUDSZ256mbkz:
5500 case VPDPWUUDSZ256mk:
5501 case VPDPWUUDSZ256mkz:
5502 case VPDPWUUDSZ256r:
5503 case VPDPWUUDSZ256rk:
5504 case VPDPWUUDSZ256rkz:
5505 case VPDPWUUDSZm:
5506 case VPDPWUUDSZmb:
5507 case VPDPWUUDSZmbk:
5508 case VPDPWUUDSZmbkz:
5509 case VPDPWUUDSZmk:
5510 case VPDPWUUDSZmkz:
5511 case VPDPWUUDSZr:
5512 case VPDPWUUDSZrk:
5513 case VPDPWUUDSZrkz:
5514 case VPDPWUUDSrm:
5515 case VPDPWUUDSrr:
5516 return true;
5517 }
5518 return false;
5519}
5520
5521bool isMOVSLDUP(unsigned Opcode) {
5522 switch (Opcode) {
5523 case MOVSLDUPrm:
5524 case MOVSLDUPrr:
5525 return true;
5526 }
5527 return false;
5528}
5529
5530bool isCLDEMOTE(unsigned Opcode) {
5531 return Opcode == CLDEMOTE;
5532}
5533
5534bool isVFNMADD231PS(unsigned Opcode) {
5535 switch (Opcode) {
5536 case VFNMADD231PSYm:
5537 case VFNMADD231PSYr:
5538 case VFNMADD231PSZ128m:
5539 case VFNMADD231PSZ128mb:
5540 case VFNMADD231PSZ128mbk:
5541 case VFNMADD231PSZ128mbkz:
5542 case VFNMADD231PSZ128mk:
5543 case VFNMADD231PSZ128mkz:
5544 case VFNMADD231PSZ128r:
5545 case VFNMADD231PSZ128rk:
5546 case VFNMADD231PSZ128rkz:
5547 case VFNMADD231PSZ256m:
5548 case VFNMADD231PSZ256mb:
5549 case VFNMADD231PSZ256mbk:
5550 case VFNMADD231PSZ256mbkz:
5551 case VFNMADD231PSZ256mk:
5552 case VFNMADD231PSZ256mkz:
5553 case VFNMADD231PSZ256r:
5554 case VFNMADD231PSZ256rk:
5555 case VFNMADD231PSZ256rkz:
5556 case VFNMADD231PSZm:
5557 case VFNMADD231PSZmb:
5558 case VFNMADD231PSZmbk:
5559 case VFNMADD231PSZmbkz:
5560 case VFNMADD231PSZmk:
5561 case VFNMADD231PSZmkz:
5562 case VFNMADD231PSZr:
5563 case VFNMADD231PSZrb:
5564 case VFNMADD231PSZrbk:
5565 case VFNMADD231PSZrbkz:
5566 case VFNMADD231PSZrk:
5567 case VFNMADD231PSZrkz:
5568 case VFNMADD231PSm:
5569 case VFNMADD231PSr:
5570 return true;
5571 }
5572 return false;
5573}
5574
5575bool isVMOVMSKPD(unsigned Opcode) {
5576 switch (Opcode) {
5577 case VMOVMSKPDYrr:
5578 case VMOVMSKPDrr:
5579 return true;
5580 }
5581 return false;
5582}
5583
5584bool isPREFETCHT0(unsigned Opcode) {
5585 return Opcode == PREFETCHT0;
5586}
5587
5588bool isVCVTNEOBF162PS(unsigned Opcode) {
5589 switch (Opcode) {
5590 case VCVTNEOBF162PSYrm:
5591 case VCVTNEOBF162PSrm:
5592 return true;
5593 }
5594 return false;
5595}
5596
5597bool isVPCMPUD(unsigned Opcode) {
5598 switch (Opcode) {
5599 case VPCMPUDZ128rmbi:
5600 case VPCMPUDZ128rmbik:
5601 case VPCMPUDZ128rmi:
5602 case VPCMPUDZ128rmik:
5603 case VPCMPUDZ128rri:
5604 case VPCMPUDZ128rrik:
5605 case VPCMPUDZ256rmbi:
5606 case VPCMPUDZ256rmbik:
5607 case VPCMPUDZ256rmi:
5608 case VPCMPUDZ256rmik:
5609 case VPCMPUDZ256rri:
5610 case VPCMPUDZ256rrik:
5611 case VPCMPUDZrmbi:
5612 case VPCMPUDZrmbik:
5613 case VPCMPUDZrmi:
5614 case VPCMPUDZrmik:
5615 case VPCMPUDZrri:
5616 case VPCMPUDZrrik:
5617 return true;
5618 }
5619 return false;
5620}
5621
5622bool isVMAXSD(unsigned Opcode) {
5623 switch (Opcode) {
5624 case VMAXSDZrm_Int:
5625 case VMAXSDZrmk_Int:
5626 case VMAXSDZrmkz_Int:
5627 case VMAXSDZrr_Int:
5628 case VMAXSDZrrb_Int:
5629 case VMAXSDZrrbk_Int:
5630 case VMAXSDZrrbkz_Int:
5631 case VMAXSDZrrk_Int:
5632 case VMAXSDZrrkz_Int:
5633 case VMAXSDrm_Int:
5634 case VMAXSDrr_Int:
5635 return true;
5636 }
5637 return false;
5638}
5639
5640bool isVRCP28SD(unsigned Opcode) {
5641 switch (Opcode) {
5642 case VRCP28SDZm:
5643 case VRCP28SDZmk:
5644 case VRCP28SDZmkz:
5645 case VRCP28SDZr:
5646 case VRCP28SDZrb:
5647 case VRCP28SDZrbk:
5648 case VRCP28SDZrbkz:
5649 case VRCP28SDZrk:
5650 case VRCP28SDZrkz:
5651 return true;
5652 }
5653 return false;
5654}
5655
5656bool isVMAXPS(unsigned Opcode) {
5657 switch (Opcode) {
5658 case VMAXPSYrm:
5659 case VMAXPSYrr:
5660 case VMAXPSZ128rm:
5661 case VMAXPSZ128rmb:
5662 case VMAXPSZ128rmbk:
5663 case VMAXPSZ128rmbkz:
5664 case VMAXPSZ128rmk:
5665 case VMAXPSZ128rmkz:
5666 case VMAXPSZ128rr:
5667 case VMAXPSZ128rrk:
5668 case VMAXPSZ128rrkz:
5669 case VMAXPSZ256rm:
5670 case VMAXPSZ256rmb:
5671 case VMAXPSZ256rmbk:
5672 case VMAXPSZ256rmbkz:
5673 case VMAXPSZ256rmk:
5674 case VMAXPSZ256rmkz:
5675 case VMAXPSZ256rr:
5676 case VMAXPSZ256rrk:
5677 case VMAXPSZ256rrkz:
5678 case VMAXPSZrm:
5679 case VMAXPSZrmb:
5680 case VMAXPSZrmbk:
5681 case VMAXPSZrmbkz:
5682 case VMAXPSZrmk:
5683 case VMAXPSZrmkz:
5684 case VMAXPSZrr:
5685 case VMAXPSZrrb:
5686 case VMAXPSZrrbk:
5687 case VMAXPSZrrbkz:
5688 case VMAXPSZrrk:
5689 case VMAXPSZrrkz:
5690 case VMAXPSrm:
5691 case VMAXPSrr:
5692 return true;
5693 }
5694 return false;
5695}
5696
5697bool isVPMOVD2M(unsigned Opcode) {
5698 switch (Opcode) {
5699 case VPMOVD2MZ128kr:
5700 case VPMOVD2MZ256kr:
5701 case VPMOVD2MZkr:
5702 return true;
5703 }
5704 return false;
5705}
5706
5707bool isVPMACSSWD(unsigned Opcode) {
5708 switch (Opcode) {
5709 case VPMACSSWDrm:
5710 case VPMACSSWDrr:
5711 return true;
5712 }
5713 return false;
5714}
5715
5716bool isVUCOMISD(unsigned Opcode) {
5717 switch (Opcode) {
5718 case VUCOMISDZrm:
5719 case VUCOMISDZrr:
5720 case VUCOMISDZrrb:
5721 case VUCOMISDrm:
5722 case VUCOMISDrr:
5723 return true;
5724 }
5725 return false;
5726}
5727
5728bool isLTR(unsigned Opcode) {
5729 switch (Opcode) {
5730 case LTRm:
5731 case LTRr:
5732 return true;
5733 }
5734 return false;
5735}
5736
5737bool isVCVTUSI2SH(unsigned Opcode) {
5738 switch (Opcode) {
5739 case VCVTUSI2SHZrm_Int:
5740 case VCVTUSI2SHZrr_Int:
5741 case VCVTUSI2SHZrrb_Int:
5742 case VCVTUSI642SHZrm_Int:
5743 case VCVTUSI642SHZrr_Int:
5744 case VCVTUSI642SHZrrb_Int:
5745 return true;
5746 }
5747 return false;
5748}
5749
5750bool isVSCATTERPF1QPS(unsigned Opcode) {
5751 return Opcode == VSCATTERPF1QPSm;
5752}
5753
5754bool isWRGSBASE(unsigned Opcode) {
5755 switch (Opcode) {
5756 case WRGSBASE:
5757 case WRGSBASE64:
5758 return true;
5759 }
5760 return false;
5761}
5762
5763bool isSTOSQ(unsigned Opcode) {
5764 return Opcode == STOSQ;
5765}
5766
5767bool isVSQRTSD(unsigned Opcode) {
5768 switch (Opcode) {
5769 case VSQRTSDZm_Int:
5770 case VSQRTSDZmk_Int:
5771 case VSQRTSDZmkz_Int:
5772 case VSQRTSDZr_Int:
5773 case VSQRTSDZrb_Int:
5774 case VSQRTSDZrbk_Int:
5775 case VSQRTSDZrbkz_Int:
5776 case VSQRTSDZrk_Int:
5777 case VSQRTSDZrkz_Int:
5778 case VSQRTSDm_Int:
5779 case VSQRTSDr_Int:
5780 return true;
5781 }
5782 return false;
5783}
5784
5785bool isVPERMIL2PD(unsigned Opcode) {
5786 switch (Opcode) {
5787 case VPERMIL2PDYmr:
5788 case VPERMIL2PDYrm:
5789 case VPERMIL2PDYrr:
5790 case VPERMIL2PDYrr_REV:
5791 case VPERMIL2PDmr:
5792 case VPERMIL2PDrm:
5793 case VPERMIL2PDrr:
5794 case VPERMIL2PDrr_REV:
5795 return true;
5796 }
5797 return false;
5798}
5799
5800bool isT2RPNTLVWZ1RST1(unsigned Opcode) {
5801 switch (Opcode) {
5802 case T2RPNTLVWZ1RST1:
5803 case T2RPNTLVWZ1RST1_EVEX:
5804 return true;
5805 }
5806 return false;
5807}
5808
5809bool isVFCMADDCSH(unsigned Opcode) {
5810 switch (Opcode) {
5811 case VFCMADDCSHZm:
5812 case VFCMADDCSHZmk:
5813 case VFCMADDCSHZmkz:
5814 case VFCMADDCSHZr:
5815 case VFCMADDCSHZrb:
5816 case VFCMADDCSHZrbk:
5817 case VFCMADDCSHZrbkz:
5818 case VFCMADDCSHZrk:
5819 case VFCMADDCSHZrkz:
5820 return true;
5821 }
5822 return false;
5823}
5824
5825bool isVFMADDSUB213PS(unsigned Opcode) {
5826 switch (Opcode) {
5827 case VFMADDSUB213PSYm:
5828 case VFMADDSUB213PSYr:
5829 case VFMADDSUB213PSZ128m:
5830 case VFMADDSUB213PSZ128mb:
5831 case VFMADDSUB213PSZ128mbk:
5832 case VFMADDSUB213PSZ128mbkz:
5833 case VFMADDSUB213PSZ128mk:
5834 case VFMADDSUB213PSZ128mkz:
5835 case VFMADDSUB213PSZ128r:
5836 case VFMADDSUB213PSZ128rk:
5837 case VFMADDSUB213PSZ128rkz:
5838 case VFMADDSUB213PSZ256m:
5839 case VFMADDSUB213PSZ256mb:
5840 case VFMADDSUB213PSZ256mbk:
5841 case VFMADDSUB213PSZ256mbkz:
5842 case VFMADDSUB213PSZ256mk:
5843 case VFMADDSUB213PSZ256mkz:
5844 case VFMADDSUB213PSZ256r:
5845 case VFMADDSUB213PSZ256rk:
5846 case VFMADDSUB213PSZ256rkz:
5847 case VFMADDSUB213PSZm:
5848 case VFMADDSUB213PSZmb:
5849 case VFMADDSUB213PSZmbk:
5850 case VFMADDSUB213PSZmbkz:
5851 case VFMADDSUB213PSZmk:
5852 case VFMADDSUB213PSZmkz:
5853 case VFMADDSUB213PSZr:
5854 case VFMADDSUB213PSZrb:
5855 case VFMADDSUB213PSZrbk:
5856 case VFMADDSUB213PSZrbkz:
5857 case VFMADDSUB213PSZrk:
5858 case VFMADDSUB213PSZrkz:
5859 case VFMADDSUB213PSm:
5860 case VFMADDSUB213PSr:
5861 return true;
5862 }
5863 return false;
5864}
5865
5866bool isPFSUB(unsigned Opcode) {
5867 switch (Opcode) {
5868 case PFSUBrm:
5869 case PFSUBrr:
5870 return true;
5871 }
5872 return false;
5873}
5874
5875bool isVSQRTSS(unsigned Opcode) {
5876 switch (Opcode) {
5877 case VSQRTSSZm_Int:
5878 case VSQRTSSZmk_Int:
5879 case VSQRTSSZmkz_Int:
5880 case VSQRTSSZr_Int:
5881 case VSQRTSSZrb_Int:
5882 case VSQRTSSZrbk_Int:
5883 case VSQRTSSZrbkz_Int:
5884 case VSQRTSSZrk_Int:
5885 case VSQRTSSZrkz_Int:
5886 case VSQRTSSm_Int:
5887 case VSQRTSSr_Int:
5888 return true;
5889 }
5890 return false;
5891}
5892
5893bool isVEXPANDPS(unsigned Opcode) {
5894 switch (Opcode) {
5895 case VEXPANDPSZ128rm:
5896 case VEXPANDPSZ128rmk:
5897 case VEXPANDPSZ128rmkz:
5898 case VEXPANDPSZ128rr:
5899 case VEXPANDPSZ128rrk:
5900 case VEXPANDPSZ128rrkz:
5901 case VEXPANDPSZ256rm:
5902 case VEXPANDPSZ256rmk:
5903 case VEXPANDPSZ256rmkz:
5904 case VEXPANDPSZ256rr:
5905 case VEXPANDPSZ256rrk:
5906 case VEXPANDPSZ256rrkz:
5907 case VEXPANDPSZrm:
5908 case VEXPANDPSZrmk:
5909 case VEXPANDPSZrmkz:
5910 case VEXPANDPSZrr:
5911 case VEXPANDPSZrrk:
5912 case VEXPANDPSZrrkz:
5913 return true;
5914 }
5915 return false;
5916}
5917
5918bool isVPCOMPRESSW(unsigned Opcode) {
5919 switch (Opcode) {
5920 case VPCOMPRESSWZ128mr:
5921 case VPCOMPRESSWZ128mrk:
5922 case VPCOMPRESSWZ128rr:
5923 case VPCOMPRESSWZ128rrk:
5924 case VPCOMPRESSWZ128rrkz:
5925 case VPCOMPRESSWZ256mr:
5926 case VPCOMPRESSWZ256mrk:
5927 case VPCOMPRESSWZ256rr:
5928 case VPCOMPRESSWZ256rrk:
5929 case VPCOMPRESSWZ256rrkz:
5930 case VPCOMPRESSWZmr:
5931 case VPCOMPRESSWZmrk:
5932 case VPCOMPRESSWZrr:
5933 case VPCOMPRESSWZrrk:
5934 case VPCOMPRESSWZrrkz:
5935 return true;
5936 }
5937 return false;
5938}
5939
5940bool isPEXTRD(unsigned Opcode) {
5941 switch (Opcode) {
5942 case PEXTRDmri:
5943 case PEXTRDrri:
5944 return true;
5945 }
5946 return false;
5947}
5948
5949bool isVCVTTPS2UQQS(unsigned Opcode) {
5950 switch (Opcode) {
5951 case VCVTTPS2UQQSZ128rm:
5952 case VCVTTPS2UQQSZ128rmb:
5953 case VCVTTPS2UQQSZ128rmbk:
5954 case VCVTTPS2UQQSZ128rmbkz:
5955 case VCVTTPS2UQQSZ128rmk:
5956 case VCVTTPS2UQQSZ128rmkz:
5957 case VCVTTPS2UQQSZ128rr:
5958 case VCVTTPS2UQQSZ128rrk:
5959 case VCVTTPS2UQQSZ128rrkz:
5960 case VCVTTPS2UQQSZ256rm:
5961 case VCVTTPS2UQQSZ256rmb:
5962 case VCVTTPS2UQQSZ256rmbk:
5963 case VCVTTPS2UQQSZ256rmbkz:
5964 case VCVTTPS2UQQSZ256rmk:
5965 case VCVTTPS2UQQSZ256rmkz:
5966 case VCVTTPS2UQQSZ256rr:
5967 case VCVTTPS2UQQSZ256rrb:
5968 case VCVTTPS2UQQSZ256rrbk:
5969 case VCVTTPS2UQQSZ256rrbkz:
5970 case VCVTTPS2UQQSZ256rrk:
5971 case VCVTTPS2UQQSZ256rrkz:
5972 case VCVTTPS2UQQSZrm:
5973 case VCVTTPS2UQQSZrmb:
5974 case VCVTTPS2UQQSZrmbk:
5975 case VCVTTPS2UQQSZrmbkz:
5976 case VCVTTPS2UQQSZrmk:
5977 case VCVTTPS2UQQSZrmkz:
5978 case VCVTTPS2UQQSZrr:
5979 case VCVTTPS2UQQSZrrb:
5980 case VCVTTPS2UQQSZrrbk:
5981 case VCVTTPS2UQQSZrrbkz:
5982 case VCVTTPS2UQQSZrrk:
5983 case VCVTTPS2UQQSZrrkz:
5984 return true;
5985 }
5986 return false;
5987}
5988
5989bool isSYSEXITQ(unsigned Opcode) {
5990 return Opcode == SYSEXIT64;
5991}
5992
5993bool isROUNDSD(unsigned Opcode) {
5994 switch (Opcode) {
5995 case ROUNDSDmi_Int:
5996 case ROUNDSDri_Int:
5997 return true;
5998 }
5999 return false;
6000}
6001
6002bool isVFMADD132BF16(unsigned Opcode) {
6003 switch (Opcode) {
6004 case VFMADD132BF16Z128m:
6005 case VFMADD132BF16Z128mb:
6006 case VFMADD132BF16Z128mbk:
6007 case VFMADD132BF16Z128mbkz:
6008 case VFMADD132BF16Z128mk:
6009 case VFMADD132BF16Z128mkz:
6010 case VFMADD132BF16Z128r:
6011 case VFMADD132BF16Z128rk:
6012 case VFMADD132BF16Z128rkz:
6013 case VFMADD132BF16Z256m:
6014 case VFMADD132BF16Z256mb:
6015 case VFMADD132BF16Z256mbk:
6016 case VFMADD132BF16Z256mbkz:
6017 case VFMADD132BF16Z256mk:
6018 case VFMADD132BF16Z256mkz:
6019 case VFMADD132BF16Z256r:
6020 case VFMADD132BF16Z256rk:
6021 case VFMADD132BF16Z256rkz:
6022 case VFMADD132BF16Zm:
6023 case VFMADD132BF16Zmb:
6024 case VFMADD132BF16Zmbk:
6025 case VFMADD132BF16Zmbkz:
6026 case VFMADD132BF16Zmk:
6027 case VFMADD132BF16Zmkz:
6028 case VFMADD132BF16Zr:
6029 case VFMADD132BF16Zrk:
6030 case VFMADD132BF16Zrkz:
6031 return true;
6032 }
6033 return false;
6034}
6035
6036bool isFCOM(unsigned Opcode) {
6037 switch (Opcode) {
6038 case COM_FST0r:
6039 case FCOM32m:
6040 case FCOM64m:
6041 return true;
6042 }
6043 return false;
6044}
6045
6046bool isVFNMSUBSS(unsigned Opcode) {
6047 switch (Opcode) {
6048 case VFNMSUBSS4mr:
6049 case VFNMSUBSS4rm:
6050 case VFNMSUBSS4rr:
6051 case VFNMSUBSS4rr_REV:
6052 return true;
6053 }
6054 return false;
6055}
6056
6057bool isKSHIFTLW(unsigned Opcode) {
6058 return Opcode == KSHIFTLWki;
6059}
6060
6061bool isSCASD(unsigned Opcode) {
6062 return Opcode == SCASL;
6063}
6064
6065bool isVMPTRLD(unsigned Opcode) {
6066 return Opcode == VMPTRLDm;
6067}
6068
6069bool isVAESDECLAST(unsigned Opcode) {
6070 switch (Opcode) {
6071 case VAESDECLASTYrm:
6072 case VAESDECLASTYrr:
6073 case VAESDECLASTZ128rm:
6074 case VAESDECLASTZ128rr:
6075 case VAESDECLASTZ256rm:
6076 case VAESDECLASTZ256rr:
6077 case VAESDECLASTZrm:
6078 case VAESDECLASTZrr:
6079 case VAESDECLASTrm:
6080 case VAESDECLASTrr:
6081 return true;
6082 }
6083 return false;
6084}
6085
6086bool isVFMADDSUBPS(unsigned Opcode) {
6087 switch (Opcode) {
6088 case VFMADDSUBPS4Ymr:
6089 case VFMADDSUBPS4Yrm:
6090 case VFMADDSUBPS4Yrr:
6091 case VFMADDSUBPS4Yrr_REV:
6092 case VFMADDSUBPS4mr:
6093 case VFMADDSUBPS4rm:
6094 case VFMADDSUBPS4rr:
6095 case VFMADDSUBPS4rr_REV:
6096 return true;
6097 }
6098 return false;
6099}
6100
6101bool isVCVTUQQ2PS(unsigned Opcode) {
6102 switch (Opcode) {
6103 case VCVTUQQ2PSZ128rm:
6104 case VCVTUQQ2PSZ128rmb:
6105 case VCVTUQQ2PSZ128rmbk:
6106 case VCVTUQQ2PSZ128rmbkz:
6107 case VCVTUQQ2PSZ128rmk:
6108 case VCVTUQQ2PSZ128rmkz:
6109 case VCVTUQQ2PSZ128rr:
6110 case VCVTUQQ2PSZ128rrk:
6111 case VCVTUQQ2PSZ128rrkz:
6112 case VCVTUQQ2PSZ256rm:
6113 case VCVTUQQ2PSZ256rmb:
6114 case VCVTUQQ2PSZ256rmbk:
6115 case VCVTUQQ2PSZ256rmbkz:
6116 case VCVTUQQ2PSZ256rmk:
6117 case VCVTUQQ2PSZ256rmkz:
6118 case VCVTUQQ2PSZ256rr:
6119 case VCVTUQQ2PSZ256rrk:
6120 case VCVTUQQ2PSZ256rrkz:
6121 case VCVTUQQ2PSZrm:
6122 case VCVTUQQ2PSZrmb:
6123 case VCVTUQQ2PSZrmbk:
6124 case VCVTUQQ2PSZrmbkz:
6125 case VCVTUQQ2PSZrmk:
6126 case VCVTUQQ2PSZrmkz:
6127 case VCVTUQQ2PSZrr:
6128 case VCVTUQQ2PSZrrb:
6129 case VCVTUQQ2PSZrrbk:
6130 case VCVTUQQ2PSZrrbkz:
6131 case VCVTUQQ2PSZrrk:
6132 case VCVTUQQ2PSZrrkz:
6133 return true;
6134 }
6135 return false;
6136}
6137
6138bool isVPMOVUSDB(unsigned Opcode) {
6139 switch (Opcode) {
6140 case VPMOVUSDBZ128mr:
6141 case VPMOVUSDBZ128mrk:
6142 case VPMOVUSDBZ128rr:
6143 case VPMOVUSDBZ128rrk:
6144 case VPMOVUSDBZ128rrkz:
6145 case VPMOVUSDBZ256mr:
6146 case VPMOVUSDBZ256mrk:
6147 case VPMOVUSDBZ256rr:
6148 case VPMOVUSDBZ256rrk:
6149 case VPMOVUSDBZ256rrkz:
6150 case VPMOVUSDBZmr:
6151 case VPMOVUSDBZmrk:
6152 case VPMOVUSDBZrr:
6153 case VPMOVUSDBZrrk:
6154 case VPMOVUSDBZrrkz:
6155 return true;
6156 }
6157 return false;
6158}
6159
6160bool isVPROTW(unsigned Opcode) {
6161 switch (Opcode) {
6162 case VPROTWmi:
6163 case VPROTWmr:
6164 case VPROTWri:
6165 case VPROTWrm:
6166 case VPROTWrr:
6167 case VPROTWrr_REV:
6168 return true;
6169 }
6170 return false;
6171}
6172
6173bool isVDPPS(unsigned Opcode) {
6174 switch (Opcode) {
6175 case VDPPSYrmi:
6176 case VDPPSYrri:
6177 case VDPPSrmi:
6178 case VDPPSrri:
6179 return true;
6180 }
6181 return false;
6182}
6183
6184bool isVRSQRT14PD(unsigned Opcode) {
6185 switch (Opcode) {
6186 case VRSQRT14PDZ128m:
6187 case VRSQRT14PDZ128mb:
6188 case VRSQRT14PDZ128mbk:
6189 case VRSQRT14PDZ128mbkz:
6190 case VRSQRT14PDZ128mk:
6191 case VRSQRT14PDZ128mkz:
6192 case VRSQRT14PDZ128r:
6193 case VRSQRT14PDZ128rk:
6194 case VRSQRT14PDZ128rkz:
6195 case VRSQRT14PDZ256m:
6196 case VRSQRT14PDZ256mb:
6197 case VRSQRT14PDZ256mbk:
6198 case VRSQRT14PDZ256mbkz:
6199 case VRSQRT14PDZ256mk:
6200 case VRSQRT14PDZ256mkz:
6201 case VRSQRT14PDZ256r:
6202 case VRSQRT14PDZ256rk:
6203 case VRSQRT14PDZ256rkz:
6204 case VRSQRT14PDZm:
6205 case VRSQRT14PDZmb:
6206 case VRSQRT14PDZmbk:
6207 case VRSQRT14PDZmbkz:
6208 case VRSQRT14PDZmk:
6209 case VRSQRT14PDZmkz:
6210 case VRSQRT14PDZr:
6211 case VRSQRT14PDZrk:
6212 case VRSQRT14PDZrkz:
6213 return true;
6214 }
6215 return false;
6216}
6217
6218bool isVTESTPD(unsigned Opcode) {
6219 switch (Opcode) {
6220 case VTESTPDYrm:
6221 case VTESTPDYrr:
6222 case VTESTPDrm:
6223 case VTESTPDrr:
6224 return true;
6225 }
6226 return false;
6227}
6228
6229bool isVFNMADD231SH(unsigned Opcode) {
6230 switch (Opcode) {
6231 case VFNMADD231SHZm_Int:
6232 case VFNMADD231SHZmk_Int:
6233 case VFNMADD231SHZmkz_Int:
6234 case VFNMADD231SHZr_Int:
6235 case VFNMADD231SHZrb_Int:
6236 case VFNMADD231SHZrbk_Int:
6237 case VFNMADD231SHZrbkz_Int:
6238 case VFNMADD231SHZrk_Int:
6239 case VFNMADD231SHZrkz_Int:
6240 return true;
6241 }
6242 return false;
6243}
6244
6245bool isENDBR64(unsigned Opcode) {
6246 return Opcode == ENDBR64;
6247}
6248
6249bool isMULSD(unsigned Opcode) {
6250 switch (Opcode) {
6251 case MULSDrm_Int:
6252 case MULSDrr_Int:
6253 return true;
6254 }
6255 return false;
6256}
6257
6258bool isXRSTORS(unsigned Opcode) {
6259 return Opcode == XRSTORS;
6260}
6261
6262bool isPREFETCHNTA(unsigned Opcode) {
6263 return Opcode == PREFETCHNTA;
6264}
6265
6266bool isVPCOMD(unsigned Opcode) {
6267 switch (Opcode) {
6268 case VPCOMDmi:
6269 case VPCOMDri:
6270 return true;
6271 }
6272 return false;
6273}
6274
6275bool isVPCOMUB(unsigned Opcode) {
6276 switch (Opcode) {
6277 case VPCOMUBmi:
6278 case VPCOMUBri:
6279 return true;
6280 }
6281 return false;
6282}
6283
6284bool isVPHSUBD(unsigned Opcode) {
6285 switch (Opcode) {
6286 case VPHSUBDYrm:
6287 case VPHSUBDYrr:
6288 case VPHSUBDrm:
6289 case VPHSUBDrr:
6290 return true;
6291 }
6292 return false;
6293}
6294
6295bool isVBROADCASTI64X2(unsigned Opcode) {
6296 switch (Opcode) {
6297 case VBROADCASTI64X2Z256rm:
6298 case VBROADCASTI64X2Z256rmk:
6299 case VBROADCASTI64X2Z256rmkz:
6300 case VBROADCASTI64X2Zrm:
6301 case VBROADCASTI64X2Zrmk:
6302 case VBROADCASTI64X2Zrmkz:
6303 return true;
6304 }
6305 return false;
6306}
6307
6308bool isFPATAN(unsigned Opcode) {
6309 return Opcode == FPATAN;
6310}
6311
6312bool isLOOPE(unsigned Opcode) {
6313 return Opcode == LOOPE;
6314}
6315
6316bool isPCMPEQW(unsigned Opcode) {
6317 switch (Opcode) {
6318 case MMX_PCMPEQWrm:
6319 case MMX_PCMPEQWrr:
6320 case PCMPEQWrm:
6321 case PCMPEQWrr:
6322 return true;
6323 }
6324 return false;
6325}
6326
6327bool isVFMADDCSH(unsigned Opcode) {
6328 switch (Opcode) {
6329 case VFMADDCSHZm:
6330 case VFMADDCSHZmk:
6331 case VFMADDCSHZmkz:
6332 case VFMADDCSHZr:
6333 case VFMADDCSHZrb:
6334 case VFMADDCSHZrbk:
6335 case VFMADDCSHZrbkz:
6336 case VFMADDCSHZrk:
6337 case VFMADDCSHZrkz:
6338 return true;
6339 }
6340 return false;
6341}
6342
6343bool isVPDPBSSD(unsigned Opcode) {
6344 switch (Opcode) {
6345 case VPDPBSSDYrm:
6346 case VPDPBSSDYrr:
6347 case VPDPBSSDZ128m:
6348 case VPDPBSSDZ128mb:
6349 case VPDPBSSDZ128mbk:
6350 case VPDPBSSDZ128mbkz:
6351 case VPDPBSSDZ128mk:
6352 case VPDPBSSDZ128mkz:
6353 case VPDPBSSDZ128r:
6354 case VPDPBSSDZ128rk:
6355 case VPDPBSSDZ128rkz:
6356 case VPDPBSSDZ256m:
6357 case VPDPBSSDZ256mb:
6358 case VPDPBSSDZ256mbk:
6359 case VPDPBSSDZ256mbkz:
6360 case VPDPBSSDZ256mk:
6361 case VPDPBSSDZ256mkz:
6362 case VPDPBSSDZ256r:
6363 case VPDPBSSDZ256rk:
6364 case VPDPBSSDZ256rkz:
6365 case VPDPBSSDZm:
6366 case VPDPBSSDZmb:
6367 case VPDPBSSDZmbk:
6368 case VPDPBSSDZmbkz:
6369 case VPDPBSSDZmk:
6370 case VPDPBSSDZmkz:
6371 case VPDPBSSDZr:
6372 case VPDPBSSDZrk:
6373 case VPDPBSSDZrkz:
6374 case VPDPBSSDrm:
6375 case VPDPBSSDrr:
6376 return true;
6377 }
6378 return false;
6379}
6380
6381bool isMOVRS(unsigned Opcode) {
6382 switch (Opcode) {
6383 case MOVRS16rm:
6384 case MOVRS16rm_EVEX:
6385 case MOVRS32rm:
6386 case MOVRS32rm_EVEX:
6387 case MOVRS64rm:
6388 case MOVRS64rm_EVEX:
6389 case MOVRS8rm:
6390 case MOVRS8rm_EVEX:
6391 return true;
6392 }
6393 return false;
6394}
6395
6396bool isVFMSUBADD132PH(unsigned Opcode) {
6397 switch (Opcode) {
6398 case VFMSUBADD132PHZ128m:
6399 case VFMSUBADD132PHZ128mb:
6400 case VFMSUBADD132PHZ128mbk:
6401 case VFMSUBADD132PHZ128mbkz:
6402 case VFMSUBADD132PHZ128mk:
6403 case VFMSUBADD132PHZ128mkz:
6404 case VFMSUBADD132PHZ128r:
6405 case VFMSUBADD132PHZ128rk:
6406 case VFMSUBADD132PHZ128rkz:
6407 case VFMSUBADD132PHZ256m:
6408 case VFMSUBADD132PHZ256mb:
6409 case VFMSUBADD132PHZ256mbk:
6410 case VFMSUBADD132PHZ256mbkz:
6411 case VFMSUBADD132PHZ256mk:
6412 case VFMSUBADD132PHZ256mkz:
6413 case VFMSUBADD132PHZ256r:
6414 case VFMSUBADD132PHZ256rk:
6415 case VFMSUBADD132PHZ256rkz:
6416 case VFMSUBADD132PHZm:
6417 case VFMSUBADD132PHZmb:
6418 case VFMSUBADD132PHZmbk:
6419 case VFMSUBADD132PHZmbkz:
6420 case VFMSUBADD132PHZmk:
6421 case VFMSUBADD132PHZmkz:
6422 case VFMSUBADD132PHZr:
6423 case VFMSUBADD132PHZrb:
6424 case VFMSUBADD132PHZrbk:
6425 case VFMSUBADD132PHZrbkz:
6426 case VFMSUBADD132PHZrk:
6427 case VFMSUBADD132PHZrkz:
6428 return true;
6429 }
6430 return false;
6431}
6432
6433bool isKADDW(unsigned Opcode) {
6434 return Opcode == KADDWkk;
6435}
6436
6437bool isPTEST(unsigned Opcode) {
6438 switch (Opcode) {
6439 case PTESTrm:
6440 case PTESTrr:
6441 return true;
6442 }
6443 return false;
6444}
6445
6446bool isVRSQRT28PS(unsigned Opcode) {
6447 switch (Opcode) {
6448 case VRSQRT28PSZm:
6449 case VRSQRT28PSZmb:
6450 case VRSQRT28PSZmbk:
6451 case VRSQRT28PSZmbkz:
6452 case VRSQRT28PSZmk:
6453 case VRSQRT28PSZmkz:
6454 case VRSQRT28PSZr:
6455 case VRSQRT28PSZrb:
6456 case VRSQRT28PSZrbk:
6457 case VRSQRT28PSZrbkz:
6458 case VRSQRT28PSZrk:
6459 case VRSQRT28PSZrkz:
6460 return true;
6461 }
6462 return false;
6463}
6464
6465bool isVGF2P8AFFINEINVQB(unsigned Opcode) {
6466 switch (Opcode) {
6467 case VGF2P8AFFINEINVQBYrmi:
6468 case VGF2P8AFFINEINVQBYrri:
6469 case VGF2P8AFFINEINVQBZ128rmbi:
6470 case VGF2P8AFFINEINVQBZ128rmbik:
6471 case VGF2P8AFFINEINVQBZ128rmbikz:
6472 case VGF2P8AFFINEINVQBZ128rmi:
6473 case VGF2P8AFFINEINVQBZ128rmik:
6474 case VGF2P8AFFINEINVQBZ128rmikz:
6475 case VGF2P8AFFINEINVQBZ128rri:
6476 case VGF2P8AFFINEINVQBZ128rrik:
6477 case VGF2P8AFFINEINVQBZ128rrikz:
6478 case VGF2P8AFFINEINVQBZ256rmbi:
6479 case VGF2P8AFFINEINVQBZ256rmbik:
6480 case VGF2P8AFFINEINVQBZ256rmbikz:
6481 case VGF2P8AFFINEINVQBZ256rmi:
6482 case VGF2P8AFFINEINVQBZ256rmik:
6483 case VGF2P8AFFINEINVQBZ256rmikz:
6484 case VGF2P8AFFINEINVQBZ256rri:
6485 case VGF2P8AFFINEINVQBZ256rrik:
6486 case VGF2P8AFFINEINVQBZ256rrikz:
6487 case VGF2P8AFFINEINVQBZrmbi:
6488 case VGF2P8AFFINEINVQBZrmbik:
6489 case VGF2P8AFFINEINVQBZrmbikz:
6490 case VGF2P8AFFINEINVQBZrmi:
6491 case VGF2P8AFFINEINVQBZrmik:
6492 case VGF2P8AFFINEINVQBZrmikz:
6493 case VGF2P8AFFINEINVQBZrri:
6494 case VGF2P8AFFINEINVQBZrrik:
6495 case VGF2P8AFFINEINVQBZrrikz:
6496 case VGF2P8AFFINEINVQBrmi:
6497 case VGF2P8AFFINEINVQBrri:
6498 return true;
6499 }
6500 return false;
6501}
6502
6503bool isSERIALIZE(unsigned Opcode) {
6504 return Opcode == SERIALIZE;
6505}
6506
6507bool isVPHADDWQ(unsigned Opcode) {
6508 switch (Opcode) {
6509 case VPHADDWQrm:
6510 case VPHADDWQrr:
6511 return true;
6512 }
6513 return false;
6514}
6515
6516bool isVRNDSCALESH(unsigned Opcode) {
6517 switch (Opcode) {
6518 case VRNDSCALESHZrmi_Int:
6519 case VRNDSCALESHZrmik_Int:
6520 case VRNDSCALESHZrmikz_Int:
6521 case VRNDSCALESHZrri_Int:
6522 case VRNDSCALESHZrrib_Int:
6523 case VRNDSCALESHZrribk_Int:
6524 case VRNDSCALESHZrribkz_Int:
6525 case VRNDSCALESHZrrik_Int:
6526 case VRNDSCALESHZrrikz_Int:
6527 return true;
6528 }
6529 return false;
6530}
6531
6532bool isAAA(unsigned Opcode) {
6533 return Opcode == AAA;
6534}
6535
6536bool isVADDBF16(unsigned Opcode) {
6537 switch (Opcode) {
6538 case VADDBF16Z128rm:
6539 case VADDBF16Z128rmb:
6540 case VADDBF16Z128rmbk:
6541 case VADDBF16Z128rmbkz:
6542 case VADDBF16Z128rmk:
6543 case VADDBF16Z128rmkz:
6544 case VADDBF16Z128rr:
6545 case VADDBF16Z128rrk:
6546 case VADDBF16Z128rrkz:
6547 case VADDBF16Z256rm:
6548 case VADDBF16Z256rmb:
6549 case VADDBF16Z256rmbk:
6550 case VADDBF16Z256rmbkz:
6551 case VADDBF16Z256rmk:
6552 case VADDBF16Z256rmkz:
6553 case VADDBF16Z256rr:
6554 case VADDBF16Z256rrk:
6555 case VADDBF16Z256rrkz:
6556 case VADDBF16Zrm:
6557 case VADDBF16Zrmb:
6558 case VADDBF16Zrmbk:
6559 case VADDBF16Zrmbkz:
6560 case VADDBF16Zrmk:
6561 case VADDBF16Zrmkz:
6562 case VADDBF16Zrr:
6563 case VADDBF16Zrrk:
6564 case VADDBF16Zrrkz:
6565 return true;
6566 }
6567 return false;
6568}
6569
6570bool isWRMSRLIST(unsigned Opcode) {
6571 return Opcode == WRMSRLIST;
6572}
6573
6574bool isVCVTPH2PSX(unsigned Opcode) {
6575 switch (Opcode) {
6576 case VCVTPH2PSXZ128rm:
6577 case VCVTPH2PSXZ128rmb:
6578 case VCVTPH2PSXZ128rmbk:
6579 case VCVTPH2PSXZ128rmbkz:
6580 case VCVTPH2PSXZ128rmk:
6581 case VCVTPH2PSXZ128rmkz:
6582 case VCVTPH2PSXZ128rr:
6583 case VCVTPH2PSXZ128rrk:
6584 case VCVTPH2PSXZ128rrkz:
6585 case VCVTPH2PSXZ256rm:
6586 case VCVTPH2PSXZ256rmb:
6587 case VCVTPH2PSXZ256rmbk:
6588 case VCVTPH2PSXZ256rmbkz:
6589 case VCVTPH2PSXZ256rmk:
6590 case VCVTPH2PSXZ256rmkz:
6591 case VCVTPH2PSXZ256rr:
6592 case VCVTPH2PSXZ256rrk:
6593 case VCVTPH2PSXZ256rrkz:
6594 case VCVTPH2PSXZrm:
6595 case VCVTPH2PSXZrmb:
6596 case VCVTPH2PSXZrmbk:
6597 case VCVTPH2PSXZrmbkz:
6598 case VCVTPH2PSXZrmk:
6599 case VCVTPH2PSXZrmkz:
6600 case VCVTPH2PSXZrr:
6601 case VCVTPH2PSXZrrb:
6602 case VCVTPH2PSXZrrbk:
6603 case VCVTPH2PSXZrrbkz:
6604 case VCVTPH2PSXZrrk:
6605 case VCVTPH2PSXZrrkz:
6606 return true;
6607 }
6608 return false;
6609}
6610
6611bool isVFMSUB231PH(unsigned Opcode) {
6612 switch (Opcode) {
6613 case VFMSUB231PHZ128m:
6614 case VFMSUB231PHZ128mb:
6615 case VFMSUB231PHZ128mbk:
6616 case VFMSUB231PHZ128mbkz:
6617 case VFMSUB231PHZ128mk:
6618 case VFMSUB231PHZ128mkz:
6619 case VFMSUB231PHZ128r:
6620 case VFMSUB231PHZ128rk:
6621 case VFMSUB231PHZ128rkz:
6622 case VFMSUB231PHZ256m:
6623 case VFMSUB231PHZ256mb:
6624 case VFMSUB231PHZ256mbk:
6625 case VFMSUB231PHZ256mbkz:
6626 case VFMSUB231PHZ256mk:
6627 case VFMSUB231PHZ256mkz:
6628 case VFMSUB231PHZ256r:
6629 case VFMSUB231PHZ256rk:
6630 case VFMSUB231PHZ256rkz:
6631 case VFMSUB231PHZm:
6632 case VFMSUB231PHZmb:
6633 case VFMSUB231PHZmbk:
6634 case VFMSUB231PHZmbkz:
6635 case VFMSUB231PHZmk:
6636 case VFMSUB231PHZmkz:
6637 case VFMSUB231PHZr:
6638 case VFMSUB231PHZrb:
6639 case VFMSUB231PHZrbk:
6640 case VFMSUB231PHZrbkz:
6641 case VFMSUB231PHZrk:
6642 case VFMSUB231PHZrkz:
6643 return true;
6644 }
6645 return false;
6646}
6647
6648bool isVGATHERQPD(unsigned Opcode) {
6649 switch (Opcode) {
6650 case VGATHERQPDYrm:
6651 case VGATHERQPDZ128rm:
6652 case VGATHERQPDZ256rm:
6653 case VGATHERQPDZrm:
6654 case VGATHERQPDrm:
6655 return true;
6656 }
6657 return false;
6658}
6659
6660bool isKADDB(unsigned Opcode) {
6661 return Opcode == KADDBkk;
6662}
6663
6664bool isCVTPD2PI(unsigned Opcode) {
6665 switch (Opcode) {
6666 case MMX_CVTPD2PIrm:
6667 case MMX_CVTPD2PIrr:
6668 return true;
6669 }
6670 return false;
6671}
6672
6673bool isVFNMSUB213PH(unsigned Opcode) {
6674 switch (Opcode) {
6675 case VFNMSUB213PHZ128m:
6676 case VFNMSUB213PHZ128mb:
6677 case VFNMSUB213PHZ128mbk:
6678 case VFNMSUB213PHZ128mbkz:
6679 case VFNMSUB213PHZ128mk:
6680 case VFNMSUB213PHZ128mkz:
6681 case VFNMSUB213PHZ128r:
6682 case VFNMSUB213PHZ128rk:
6683 case VFNMSUB213PHZ128rkz:
6684 case VFNMSUB213PHZ256m:
6685 case VFNMSUB213PHZ256mb:
6686 case VFNMSUB213PHZ256mbk:
6687 case VFNMSUB213PHZ256mbkz:
6688 case VFNMSUB213PHZ256mk:
6689 case VFNMSUB213PHZ256mkz:
6690 case VFNMSUB213PHZ256r:
6691 case VFNMSUB213PHZ256rk:
6692 case VFNMSUB213PHZ256rkz:
6693 case VFNMSUB213PHZm:
6694 case VFNMSUB213PHZmb:
6695 case VFNMSUB213PHZmbk:
6696 case VFNMSUB213PHZmbkz:
6697 case VFNMSUB213PHZmk:
6698 case VFNMSUB213PHZmkz:
6699 case VFNMSUB213PHZr:
6700 case VFNMSUB213PHZrb:
6701 case VFNMSUB213PHZrbk:
6702 case VFNMSUB213PHZrbkz:
6703 case VFNMSUB213PHZrk:
6704 case VFNMSUB213PHZrkz:
6705 return true;
6706 }
6707 return false;
6708}
6709
6710bool isXORPS(unsigned Opcode) {
6711 switch (Opcode) {
6712 case XORPSrm:
6713 case XORPSrr:
6714 return true;
6715 }
6716 return false;
6717}
6718
6719bool isVPCMPESTRI(unsigned Opcode) {
6720 switch (Opcode) {
6721 case VPCMPESTRIrmi:
6722 case VPCMPESTRIrri:
6723 return true;
6724 }
6725 return false;
6726}
6727
6728bool isVPADDSB(unsigned Opcode) {
6729 switch (Opcode) {
6730 case VPADDSBYrm:
6731 case VPADDSBYrr:
6732 case VPADDSBZ128rm:
6733 case VPADDSBZ128rmk:
6734 case VPADDSBZ128rmkz:
6735 case VPADDSBZ128rr:
6736 case VPADDSBZ128rrk:
6737 case VPADDSBZ128rrkz:
6738 case VPADDSBZ256rm:
6739 case VPADDSBZ256rmk:
6740 case VPADDSBZ256rmkz:
6741 case VPADDSBZ256rr:
6742 case VPADDSBZ256rrk:
6743 case VPADDSBZ256rrkz:
6744 case VPADDSBZrm:
6745 case VPADDSBZrmk:
6746 case VPADDSBZrmkz:
6747 case VPADDSBZrr:
6748 case VPADDSBZrrk:
6749 case VPADDSBZrrkz:
6750 case VPADDSBrm:
6751 case VPADDSBrr:
6752 return true;
6753 }
6754 return false;
6755}
6756
6757bool isPOP2(unsigned Opcode) {
6758 return Opcode == POP2;
6759}
6760
6761bool isRDMSRLIST(unsigned Opcode) {
6762 return Opcode == RDMSRLIST;
6763}
6764
6765bool isVPSHRDW(unsigned Opcode) {
6766 switch (Opcode) {
6767 case VPSHRDWZ128rmi:
6768 case VPSHRDWZ128rmik:
6769 case VPSHRDWZ128rmikz:
6770 case VPSHRDWZ128rri:
6771 case VPSHRDWZ128rrik:
6772 case VPSHRDWZ128rrikz:
6773 case VPSHRDWZ256rmi:
6774 case VPSHRDWZ256rmik:
6775 case VPSHRDWZ256rmikz:
6776 case VPSHRDWZ256rri:
6777 case VPSHRDWZ256rrik:
6778 case VPSHRDWZ256rrikz:
6779 case VPSHRDWZrmi:
6780 case VPSHRDWZrmik:
6781 case VPSHRDWZrmikz:
6782 case VPSHRDWZrri:
6783 case VPSHRDWZrrik:
6784 case VPSHRDWZrrikz:
6785 return true;
6786 }
6787 return false;
6788}
6789
6790bool isVPDPBUSD(unsigned Opcode) {
6791 switch (Opcode) {
6792 case VPDPBUSDYrm:
6793 case VPDPBUSDYrr:
6794 case VPDPBUSDZ128m:
6795 case VPDPBUSDZ128mb:
6796 case VPDPBUSDZ128mbk:
6797 case VPDPBUSDZ128mbkz:
6798 case VPDPBUSDZ128mk:
6799 case VPDPBUSDZ128mkz:
6800 case VPDPBUSDZ128r:
6801 case VPDPBUSDZ128rk:
6802 case VPDPBUSDZ128rkz:
6803 case VPDPBUSDZ256m:
6804 case VPDPBUSDZ256mb:
6805 case VPDPBUSDZ256mbk:
6806 case VPDPBUSDZ256mbkz:
6807 case VPDPBUSDZ256mk:
6808 case VPDPBUSDZ256mkz:
6809 case VPDPBUSDZ256r:
6810 case VPDPBUSDZ256rk:
6811 case VPDPBUSDZ256rkz:
6812 case VPDPBUSDZm:
6813 case VPDPBUSDZmb:
6814 case VPDPBUSDZmbk:
6815 case VPDPBUSDZmbkz:
6816 case VPDPBUSDZmk:
6817 case VPDPBUSDZmkz:
6818 case VPDPBUSDZr:
6819 case VPDPBUSDZrk:
6820 case VPDPBUSDZrkz:
6821 case VPDPBUSDrm:
6822 case VPDPBUSDrr:
6823 return true;
6824 }
6825 return false;
6826}
6827
6828bool isVCMPPH(unsigned Opcode) {
6829 switch (Opcode) {
6830 case VCMPPHZ128rmbi:
6831 case VCMPPHZ128rmbik:
6832 case VCMPPHZ128rmi:
6833 case VCMPPHZ128rmik:
6834 case VCMPPHZ128rri:
6835 case VCMPPHZ128rrik:
6836 case VCMPPHZ256rmbi:
6837 case VCMPPHZ256rmbik:
6838 case VCMPPHZ256rmi:
6839 case VCMPPHZ256rmik:
6840 case VCMPPHZ256rri:
6841 case VCMPPHZ256rrik:
6842 case VCMPPHZrmbi:
6843 case VCMPPHZrmbik:
6844 case VCMPPHZrmi:
6845 case VCMPPHZrmik:
6846 case VCMPPHZrri:
6847 case VCMPPHZrrib:
6848 case VCMPPHZrribk:
6849 case VCMPPHZrrik:
6850 return true;
6851 }
6852 return false;
6853}
6854
6855bool isVANDNPD(unsigned Opcode) {
6856 switch (Opcode) {
6857 case VANDNPDYrm:
6858 case VANDNPDYrr:
6859 case VANDNPDZ128rm:
6860 case VANDNPDZ128rmb:
6861 case VANDNPDZ128rmbk:
6862 case VANDNPDZ128rmbkz:
6863 case VANDNPDZ128rmk:
6864 case VANDNPDZ128rmkz:
6865 case VANDNPDZ128rr:
6866 case VANDNPDZ128rrk:
6867 case VANDNPDZ128rrkz:
6868 case VANDNPDZ256rm:
6869 case VANDNPDZ256rmb:
6870 case VANDNPDZ256rmbk:
6871 case VANDNPDZ256rmbkz:
6872 case VANDNPDZ256rmk:
6873 case VANDNPDZ256rmkz:
6874 case VANDNPDZ256rr:
6875 case VANDNPDZ256rrk:
6876 case VANDNPDZ256rrkz:
6877 case VANDNPDZrm:
6878 case VANDNPDZrmb:
6879 case VANDNPDZrmbk:
6880 case VANDNPDZrmbkz:
6881 case VANDNPDZrmk:
6882 case VANDNPDZrmkz:
6883 case VANDNPDZrr:
6884 case VANDNPDZrrk:
6885 case VANDNPDZrrkz:
6886 case VANDNPDrm:
6887 case VANDNPDrr:
6888 return true;
6889 }
6890 return false;
6891}
6892
6893bool isSUB(unsigned Opcode) {
6894 switch (Opcode) {
6895 case SUB16i16:
6896 case SUB16mi:
6897 case SUB16mi8:
6898 case SUB16mi8_EVEX:
6899 case SUB16mi8_ND:
6900 case SUB16mi8_NF:
6901 case SUB16mi8_NF_ND:
6902 case SUB16mi_EVEX:
6903 case SUB16mi_ND:
6904 case SUB16mi_NF:
6905 case SUB16mi_NF_ND:
6906 case SUB16mr:
6907 case SUB16mr_EVEX:
6908 case SUB16mr_ND:
6909 case SUB16mr_NF:
6910 case SUB16mr_NF_ND:
6911 case SUB16ri:
6912 case SUB16ri8:
6913 case SUB16ri8_EVEX:
6914 case SUB16ri8_ND:
6915 case SUB16ri8_NF:
6916 case SUB16ri8_NF_ND:
6917 case SUB16ri_EVEX:
6918 case SUB16ri_ND:
6919 case SUB16ri_NF:
6920 case SUB16ri_NF_ND:
6921 case SUB16rm:
6922 case SUB16rm_EVEX:
6923 case SUB16rm_ND:
6924 case SUB16rm_NF:
6925 case SUB16rm_NF_ND:
6926 case SUB16rr:
6927 case SUB16rr_EVEX:
6928 case SUB16rr_EVEX_REV:
6929 case SUB16rr_ND:
6930 case SUB16rr_ND_REV:
6931 case SUB16rr_NF:
6932 case SUB16rr_NF_ND:
6933 case SUB16rr_NF_ND_REV:
6934 case SUB16rr_NF_REV:
6935 case SUB16rr_REV:
6936 case SUB32i32:
6937 case SUB32mi:
6938 case SUB32mi8:
6939 case SUB32mi8_EVEX:
6940 case SUB32mi8_ND:
6941 case SUB32mi8_NF:
6942 case SUB32mi8_NF_ND:
6943 case SUB32mi_EVEX:
6944 case SUB32mi_ND:
6945 case SUB32mi_NF:
6946 case SUB32mi_NF_ND:
6947 case SUB32mr:
6948 case SUB32mr_EVEX:
6949 case SUB32mr_ND:
6950 case SUB32mr_NF:
6951 case SUB32mr_NF_ND:
6952 case SUB32ri:
6953 case SUB32ri8:
6954 case SUB32ri8_EVEX:
6955 case SUB32ri8_ND:
6956 case SUB32ri8_NF:
6957 case SUB32ri8_NF_ND:
6958 case SUB32ri_EVEX:
6959 case SUB32ri_ND:
6960 case SUB32ri_NF:
6961 case SUB32ri_NF_ND:
6962 case SUB32rm:
6963 case SUB32rm_EVEX:
6964 case SUB32rm_ND:
6965 case SUB32rm_NF:
6966 case SUB32rm_NF_ND:
6967 case SUB32rr:
6968 case SUB32rr_EVEX:
6969 case SUB32rr_EVEX_REV:
6970 case SUB32rr_ND:
6971 case SUB32rr_ND_REV:
6972 case SUB32rr_NF:
6973 case SUB32rr_NF_ND:
6974 case SUB32rr_NF_ND_REV:
6975 case SUB32rr_NF_REV:
6976 case SUB32rr_REV:
6977 case SUB64i32:
6978 case SUB64mi32:
6979 case SUB64mi32_EVEX:
6980 case SUB64mi32_ND:
6981 case SUB64mi32_NF:
6982 case SUB64mi32_NF_ND:
6983 case SUB64mi8:
6984 case SUB64mi8_EVEX:
6985 case SUB64mi8_ND:
6986 case SUB64mi8_NF:
6987 case SUB64mi8_NF_ND:
6988 case SUB64mr:
6989 case SUB64mr_EVEX:
6990 case SUB64mr_ND:
6991 case SUB64mr_NF:
6992 case SUB64mr_NF_ND:
6993 case SUB64ri32:
6994 case SUB64ri32_EVEX:
6995 case SUB64ri32_ND:
6996 case SUB64ri32_NF:
6997 case SUB64ri32_NF_ND:
6998 case SUB64ri8:
6999 case SUB64ri8_EVEX:
7000 case SUB64ri8_ND:
7001 case SUB64ri8_NF:
7002 case SUB64ri8_NF_ND:
7003 case SUB64rm:
7004 case SUB64rm_EVEX:
7005 case SUB64rm_ND:
7006 case SUB64rm_NF:
7007 case SUB64rm_NF_ND:
7008 case SUB64rr:
7009 case SUB64rr_EVEX:
7010 case SUB64rr_EVEX_REV:
7011 case SUB64rr_ND:
7012 case SUB64rr_ND_REV:
7013 case SUB64rr_NF:
7014 case SUB64rr_NF_ND:
7015 case SUB64rr_NF_ND_REV:
7016 case SUB64rr_NF_REV:
7017 case SUB64rr_REV:
7018 case SUB8i8:
7019 case SUB8mi:
7020 case SUB8mi8:
7021 case SUB8mi_EVEX:
7022 case SUB8mi_ND:
7023 case SUB8mi_NF:
7024 case SUB8mi_NF_ND:
7025 case SUB8mr:
7026 case SUB8mr_EVEX:
7027 case SUB8mr_ND:
7028 case SUB8mr_NF:
7029 case SUB8mr_NF_ND:
7030 case SUB8ri:
7031 case SUB8ri8:
7032 case SUB8ri_EVEX:
7033 case SUB8ri_ND:
7034 case SUB8ri_NF:
7035 case SUB8ri_NF_ND:
7036 case SUB8rm:
7037 case SUB8rm_EVEX:
7038 case SUB8rm_ND:
7039 case SUB8rm_NF:
7040 case SUB8rm_NF_ND:
7041 case SUB8rr:
7042 case SUB8rr_EVEX:
7043 case SUB8rr_EVEX_REV:
7044 case SUB8rr_ND:
7045 case SUB8rr_ND_REV:
7046 case SUB8rr_NF:
7047 case SUB8rr_NF_ND:
7048 case SUB8rr_NF_ND_REV:
7049 case SUB8rr_NF_REV:
7050 case SUB8rr_REV:
7051 return true;
7052 }
7053 return false;
7054}
7055
7056bool isVRSQRT28PD(unsigned Opcode) {
7057 switch (Opcode) {
7058 case VRSQRT28PDZm:
7059 case VRSQRT28PDZmb:
7060 case VRSQRT28PDZmbk:
7061 case VRSQRT28PDZmbkz:
7062 case VRSQRT28PDZmk:
7063 case VRSQRT28PDZmkz:
7064 case VRSQRT28PDZr:
7065 case VRSQRT28PDZrb:
7066 case VRSQRT28PDZrbk:
7067 case VRSQRT28PDZrbkz:
7068 case VRSQRT28PDZrk:
7069 case VRSQRT28PDZrkz:
7070 return true;
7071 }
7072 return false;
7073}
7074
7075bool isVFNMADD132PH(unsigned Opcode) {
7076 switch (Opcode) {
7077 case VFNMADD132PHZ128m:
7078 case VFNMADD132PHZ128mb:
7079 case VFNMADD132PHZ128mbk:
7080 case VFNMADD132PHZ128mbkz:
7081 case VFNMADD132PHZ128mk:
7082 case VFNMADD132PHZ128mkz:
7083 case VFNMADD132PHZ128r:
7084 case VFNMADD132PHZ128rk:
7085 case VFNMADD132PHZ128rkz:
7086 case VFNMADD132PHZ256m:
7087 case VFNMADD132PHZ256mb:
7088 case VFNMADD132PHZ256mbk:
7089 case VFNMADD132PHZ256mbkz:
7090 case VFNMADD132PHZ256mk:
7091 case VFNMADD132PHZ256mkz:
7092 case VFNMADD132PHZ256r:
7093 case VFNMADD132PHZ256rk:
7094 case VFNMADD132PHZ256rkz:
7095 case VFNMADD132PHZm:
7096 case VFNMADD132PHZmb:
7097 case VFNMADD132PHZmbk:
7098 case VFNMADD132PHZmbkz:
7099 case VFNMADD132PHZmk:
7100 case VFNMADD132PHZmkz:
7101 case VFNMADD132PHZr:
7102 case VFNMADD132PHZrb:
7103 case VFNMADD132PHZrbk:
7104 case VFNMADD132PHZrbkz:
7105 case VFNMADD132PHZrk:
7106 case VFNMADD132PHZrkz:
7107 return true;
7108 }
7109 return false;
7110}
7111
7112bool isVPMACSSWW(unsigned Opcode) {
7113 switch (Opcode) {
7114 case VPMACSSWWrm:
7115 case VPMACSSWWrr:
7116 return true;
7117 }
7118 return false;
7119}
7120
7121bool isXSTORE(unsigned Opcode) {
7122 return Opcode == XSTORE;
7123}
7124
7125bool isVPROTQ(unsigned Opcode) {
7126 switch (Opcode) {
7127 case VPROTQmi:
7128 case VPROTQmr:
7129 case VPROTQri:
7130 case VPROTQrm:
7131 case VPROTQrr:
7132 case VPROTQrr_REV:
7133 return true;
7134 }
7135 return false;
7136}
7137
7138bool isVPHADDBD(unsigned Opcode) {
7139 switch (Opcode) {
7140 case VPHADDBDrm:
7141 case VPHADDBDrr:
7142 return true;
7143 }
7144 return false;
7145}
7146
7147bool isVPMAXSB(unsigned Opcode) {
7148 switch (Opcode) {
7149 case VPMAXSBYrm:
7150 case VPMAXSBYrr:
7151 case VPMAXSBZ128rm:
7152 case VPMAXSBZ128rmk:
7153 case VPMAXSBZ128rmkz:
7154 case VPMAXSBZ128rr:
7155 case VPMAXSBZ128rrk:
7156 case VPMAXSBZ128rrkz:
7157 case VPMAXSBZ256rm:
7158 case VPMAXSBZ256rmk:
7159 case VPMAXSBZ256rmkz:
7160 case VPMAXSBZ256rr:
7161 case VPMAXSBZ256rrk:
7162 case VPMAXSBZ256rrkz:
7163 case VPMAXSBZrm:
7164 case VPMAXSBZrmk:
7165 case VPMAXSBZrmkz:
7166 case VPMAXSBZrr:
7167 case VPMAXSBZrrk:
7168 case VPMAXSBZrrkz:
7169 case VPMAXSBrm:
7170 case VPMAXSBrr:
7171 return true;
7172 }
7173 return false;
7174}
7175
7176bool isVMOVDQU8(unsigned Opcode) {
7177 switch (Opcode) {
7178 case VMOVDQU8Z128mr:
7179 case VMOVDQU8Z128mrk:
7180 case VMOVDQU8Z128rm:
7181 case VMOVDQU8Z128rmk:
7182 case VMOVDQU8Z128rmkz:
7183 case VMOVDQU8Z128rr:
7184 case VMOVDQU8Z128rr_REV:
7185 case VMOVDQU8Z128rrk:
7186 case VMOVDQU8Z128rrk_REV:
7187 case VMOVDQU8Z128rrkz:
7188 case VMOVDQU8Z128rrkz_REV:
7189 case VMOVDQU8Z256mr:
7190 case VMOVDQU8Z256mrk:
7191 case VMOVDQU8Z256rm:
7192 case VMOVDQU8Z256rmk:
7193 case VMOVDQU8Z256rmkz:
7194 case VMOVDQU8Z256rr:
7195 case VMOVDQU8Z256rr_REV:
7196 case VMOVDQU8Z256rrk:
7197 case VMOVDQU8Z256rrk_REV:
7198 case VMOVDQU8Z256rrkz:
7199 case VMOVDQU8Z256rrkz_REV:
7200 case VMOVDQU8Zmr:
7201 case VMOVDQU8Zmrk:
7202 case VMOVDQU8Zrm:
7203 case VMOVDQU8Zrmk:
7204 case VMOVDQU8Zrmkz:
7205 case VMOVDQU8Zrr:
7206 case VMOVDQU8Zrr_REV:
7207 case VMOVDQU8Zrrk:
7208 case VMOVDQU8Zrrk_REV:
7209 case VMOVDQU8Zrrkz:
7210 case VMOVDQU8Zrrkz_REV:
7211 return true;
7212 }
7213 return false;
7214}
7215
7216bool isVPMOVSXWD(unsigned Opcode) {
7217 switch (Opcode) {
7218 case VPMOVSXWDYrm:
7219 case VPMOVSXWDYrr:
7220 case VPMOVSXWDZ128rm:
7221 case VPMOVSXWDZ128rmk:
7222 case VPMOVSXWDZ128rmkz:
7223 case VPMOVSXWDZ128rr:
7224 case VPMOVSXWDZ128rrk:
7225 case VPMOVSXWDZ128rrkz:
7226 case VPMOVSXWDZ256rm:
7227 case VPMOVSXWDZ256rmk:
7228 case VPMOVSXWDZ256rmkz:
7229 case VPMOVSXWDZ256rr:
7230 case VPMOVSXWDZ256rrk:
7231 case VPMOVSXWDZ256rrkz:
7232 case VPMOVSXWDZrm:
7233 case VPMOVSXWDZrmk:
7234 case VPMOVSXWDZrmkz:
7235 case VPMOVSXWDZrr:
7236 case VPMOVSXWDZrrk:
7237 case VPMOVSXWDZrrkz:
7238 case VPMOVSXWDrm:
7239 case VPMOVSXWDrr:
7240 return true;
7241 }
7242 return false;
7243}
7244
7245bool isVMINMAXPD(unsigned Opcode) {
7246 switch (Opcode) {
7247 case VMINMAXPDZ128rmbi:
7248 case VMINMAXPDZ128rmbik:
7249 case VMINMAXPDZ128rmbikz:
7250 case VMINMAXPDZ128rmi:
7251 case VMINMAXPDZ128rmik:
7252 case VMINMAXPDZ128rmikz:
7253 case VMINMAXPDZ128rri:
7254 case VMINMAXPDZ128rrik:
7255 case VMINMAXPDZ128rrikz:
7256 case VMINMAXPDZ256rmbi:
7257 case VMINMAXPDZ256rmbik:
7258 case VMINMAXPDZ256rmbikz:
7259 case VMINMAXPDZ256rmi:
7260 case VMINMAXPDZ256rmik:
7261 case VMINMAXPDZ256rmikz:
7262 case VMINMAXPDZ256rri:
7263 case VMINMAXPDZ256rrik:
7264 case VMINMAXPDZ256rrikz:
7265 case VMINMAXPDZrmbi:
7266 case VMINMAXPDZrmbik:
7267 case VMINMAXPDZrmbikz:
7268 case VMINMAXPDZrmi:
7269 case VMINMAXPDZrmik:
7270 case VMINMAXPDZrmikz:
7271 case VMINMAXPDZrri:
7272 case VMINMAXPDZrrib:
7273 case VMINMAXPDZrribk:
7274 case VMINMAXPDZrribkz:
7275 case VMINMAXPDZrrik:
7276 case VMINMAXPDZrrikz:
7277 return true;
7278 }
7279 return false;
7280}
7281
7282bool isSHA256RNDS2(unsigned Opcode) {
7283 switch (Opcode) {
7284 case SHA256RNDS2rm:
7285 case SHA256RNDS2rr:
7286 return true;
7287 }
7288 return false;
7289}
7290
7291bool isKANDB(unsigned Opcode) {
7292 return Opcode == KANDBkk;
7293}
7294
7295bool isTPAUSE(unsigned Opcode) {
7296 return Opcode == TPAUSE;
7297}
7298
7299bool isPUSH(unsigned Opcode) {
7300 switch (Opcode) {
7301 case PUSH16i:
7302 case PUSH16i8:
7303 case PUSH16r:
7304 case PUSH16rmm:
7305 case PUSH16rmr:
7306 case PUSH32i:
7307 case PUSH32i8:
7308 case PUSH32r:
7309 case PUSH32rmm:
7310 case PUSH32rmr:
7311 case PUSH64i32:
7312 case PUSH64i8:
7313 case PUSH64r:
7314 case PUSH64rmm:
7315 case PUSH64rmr:
7316 case PUSHCS16:
7317 case PUSHCS32:
7318 case PUSHDS16:
7319 case PUSHDS32:
7320 case PUSHES16:
7321 case PUSHES32:
7322 case PUSHFS16:
7323 case PUSHFS32:
7324 case PUSHFS64:
7325 case PUSHGS16:
7326 case PUSHGS32:
7327 case PUSHGS64:
7328 case PUSHSS16:
7329 case PUSHSS32:
7330 return true;
7331 }
7332 return false;
7333}
7334
7335bool isVRNDSCALESS(unsigned Opcode) {
7336 switch (Opcode) {
7337 case VRNDSCALESSZrmi_Int:
7338 case VRNDSCALESSZrmik_Int:
7339 case VRNDSCALESSZrmikz_Int:
7340 case VRNDSCALESSZrri_Int:
7341 case VRNDSCALESSZrrib_Int:
7342 case VRNDSCALESSZrribk_Int:
7343 case VRNDSCALESSZrribkz_Int:
7344 case VRNDSCALESSZrrik_Int:
7345 case VRNDSCALESSZrrikz_Int:
7346 return true;
7347 }
7348 return false;
7349}
7350
7351bool isVRNDSCALEBF16(unsigned Opcode) {
7352 switch (Opcode) {
7353 case VRNDSCALEBF16Z128rmbi:
7354 case VRNDSCALEBF16Z128rmbik:
7355 case VRNDSCALEBF16Z128rmbikz:
7356 case VRNDSCALEBF16Z128rmi:
7357 case VRNDSCALEBF16Z128rmik:
7358 case VRNDSCALEBF16Z128rmikz:
7359 case VRNDSCALEBF16Z128rri:
7360 case VRNDSCALEBF16Z128rrik:
7361 case VRNDSCALEBF16Z128rrikz:
7362 case VRNDSCALEBF16Z256rmbi:
7363 case VRNDSCALEBF16Z256rmbik:
7364 case VRNDSCALEBF16Z256rmbikz:
7365 case VRNDSCALEBF16Z256rmi:
7366 case VRNDSCALEBF16Z256rmik:
7367 case VRNDSCALEBF16Z256rmikz:
7368 case VRNDSCALEBF16Z256rri:
7369 case VRNDSCALEBF16Z256rrik:
7370 case VRNDSCALEBF16Z256rrikz:
7371 case VRNDSCALEBF16Zrmbi:
7372 case VRNDSCALEBF16Zrmbik:
7373 case VRNDSCALEBF16Zrmbikz:
7374 case VRNDSCALEBF16Zrmi:
7375 case VRNDSCALEBF16Zrmik:
7376 case VRNDSCALEBF16Zrmikz:
7377 case VRNDSCALEBF16Zrri:
7378 case VRNDSCALEBF16Zrrik:
7379 case VRNDSCALEBF16Zrrikz:
7380 return true;
7381 }
7382 return false;
7383}
7384
7385bool isVPCMPISTRI(unsigned Opcode) {
7386 switch (Opcode) {
7387 case VPCMPISTRIrmi:
7388 case VPCMPISTRIrri:
7389 return true;
7390 }
7391 return false;
7392}
7393
7394bool isSTGI(unsigned Opcode) {
7395 return Opcode == STGI;
7396}
7397
7398bool isSBB(unsigned Opcode) {
7399 switch (Opcode) {
7400 case SBB16i16:
7401 case SBB16mi:
7402 case SBB16mi8:
7403 case SBB16mi8_EVEX:
7404 case SBB16mi8_ND:
7405 case SBB16mi_EVEX:
7406 case SBB16mi_ND:
7407 case SBB16mr:
7408 case SBB16mr_EVEX:
7409 case SBB16mr_ND:
7410 case SBB16ri:
7411 case SBB16ri8:
7412 case SBB16ri8_EVEX:
7413 case SBB16ri8_ND:
7414 case SBB16ri_EVEX:
7415 case SBB16ri_ND:
7416 case SBB16rm:
7417 case SBB16rm_EVEX:
7418 case SBB16rm_ND:
7419 case SBB16rr:
7420 case SBB16rr_EVEX:
7421 case SBB16rr_EVEX_REV:
7422 case SBB16rr_ND:
7423 case SBB16rr_ND_REV:
7424 case SBB16rr_REV:
7425 case SBB32i32:
7426 case SBB32mi:
7427 case SBB32mi8:
7428 case SBB32mi8_EVEX:
7429 case SBB32mi8_ND:
7430 case SBB32mi_EVEX:
7431 case SBB32mi_ND:
7432 case SBB32mr:
7433 case SBB32mr_EVEX:
7434 case SBB32mr_ND:
7435 case SBB32ri:
7436 case SBB32ri8:
7437 case SBB32ri8_EVEX:
7438 case SBB32ri8_ND:
7439 case SBB32ri_EVEX:
7440 case SBB32ri_ND:
7441 case SBB32rm:
7442 case SBB32rm_EVEX:
7443 case SBB32rm_ND:
7444 case SBB32rr:
7445 case SBB32rr_EVEX:
7446 case SBB32rr_EVEX_REV:
7447 case SBB32rr_ND:
7448 case SBB32rr_ND_REV:
7449 case SBB32rr_REV:
7450 case SBB64i32:
7451 case SBB64mi32:
7452 case SBB64mi32_EVEX:
7453 case SBB64mi32_ND:
7454 case SBB64mi8:
7455 case SBB64mi8_EVEX:
7456 case SBB64mi8_ND:
7457 case SBB64mr:
7458 case SBB64mr_EVEX:
7459 case SBB64mr_ND:
7460 case SBB64ri32:
7461 case SBB64ri32_EVEX:
7462 case SBB64ri32_ND:
7463 case SBB64ri8:
7464 case SBB64ri8_EVEX:
7465 case SBB64ri8_ND:
7466 case SBB64rm:
7467 case SBB64rm_EVEX:
7468 case SBB64rm_ND:
7469 case SBB64rr:
7470 case SBB64rr_EVEX:
7471 case SBB64rr_EVEX_REV:
7472 case SBB64rr_ND:
7473 case SBB64rr_ND_REV:
7474 case SBB64rr_REV:
7475 case SBB8i8:
7476 case SBB8mi:
7477 case SBB8mi8:
7478 case SBB8mi_EVEX:
7479 case SBB8mi_ND:
7480 case SBB8mr:
7481 case SBB8mr_EVEX:
7482 case SBB8mr_ND:
7483 case SBB8ri:
7484 case SBB8ri8:
7485 case SBB8ri_EVEX:
7486 case SBB8ri_ND:
7487 case SBB8rm:
7488 case SBB8rm_EVEX:
7489 case SBB8rm_ND:
7490 case SBB8rr:
7491 case SBB8rr_EVEX:
7492 case SBB8rr_EVEX_REV:
7493 case SBB8rr_ND:
7494 case SBB8rr_ND_REV:
7495 case SBB8rr_REV:
7496 return true;
7497 }
7498 return false;
7499}
7500
7501bool isBLCS(unsigned Opcode) {
7502 switch (Opcode) {
7503 case BLCS32rm:
7504 case BLCS32rr:
7505 case BLCS64rm:
7506 case BLCS64rr:
7507 return true;
7508 }
7509 return false;
7510}
7511
7512bool isVCVTSD2SH(unsigned Opcode) {
7513 switch (Opcode) {
7514 case VCVTSD2SHZrm_Int:
7515 case VCVTSD2SHZrmk_Int:
7516 case VCVTSD2SHZrmkz_Int:
7517 case VCVTSD2SHZrr_Int:
7518 case VCVTSD2SHZrrb_Int:
7519 case VCVTSD2SHZrrbk_Int:
7520 case VCVTSD2SHZrrbkz_Int:
7521 case VCVTSD2SHZrrk_Int:
7522 case VCVTSD2SHZrrkz_Int:
7523 return true;
7524 }
7525 return false;
7526}
7527
7528bool isVPERMW(unsigned Opcode) {
7529 switch (Opcode) {
7530 case VPERMWZ128rm:
7531 case VPERMWZ128rmk:
7532 case VPERMWZ128rmkz:
7533 case VPERMWZ128rr:
7534 case VPERMWZ128rrk:
7535 case VPERMWZ128rrkz:
7536 case VPERMWZ256rm:
7537 case VPERMWZ256rmk:
7538 case VPERMWZ256rmkz:
7539 case VPERMWZ256rr:
7540 case VPERMWZ256rrk:
7541 case VPERMWZ256rrkz:
7542 case VPERMWZrm:
7543 case VPERMWZrmk:
7544 case VPERMWZrmkz:
7545 case VPERMWZrr:
7546 case VPERMWZrrk:
7547 case VPERMWZrrkz:
7548 return true;
7549 }
7550 return false;
7551}
7552
7553bool isXRESLDTRK(unsigned Opcode) {
7554 return Opcode == XRESLDTRK;
7555}
7556
7557bool isAESENC256KL(unsigned Opcode) {
7558 return Opcode == AESENC256KL;
7559}
7560
7561bool isVGATHERDPD(unsigned Opcode) {
7562 switch (Opcode) {
7563 case VGATHERDPDYrm:
7564 case VGATHERDPDZ128rm:
7565 case VGATHERDPDZ256rm:
7566 case VGATHERDPDZrm:
7567 case VGATHERDPDrm:
7568 return true;
7569 }
7570 return false;
7571}
7572
7573bool isHRESET(unsigned Opcode) {
7574 return Opcode == HRESET;
7575}
7576
7577bool isVFMSUBADD231PD(unsigned Opcode) {
7578 switch (Opcode) {
7579 case VFMSUBADD231PDYm:
7580 case VFMSUBADD231PDYr:
7581 case VFMSUBADD231PDZ128m:
7582 case VFMSUBADD231PDZ128mb:
7583 case VFMSUBADD231PDZ128mbk:
7584 case VFMSUBADD231PDZ128mbkz:
7585 case VFMSUBADD231PDZ128mk:
7586 case VFMSUBADD231PDZ128mkz:
7587 case VFMSUBADD231PDZ128r:
7588 case VFMSUBADD231PDZ128rk:
7589 case VFMSUBADD231PDZ128rkz:
7590 case VFMSUBADD231PDZ256m:
7591 case VFMSUBADD231PDZ256mb:
7592 case VFMSUBADD231PDZ256mbk:
7593 case VFMSUBADD231PDZ256mbkz:
7594 case VFMSUBADD231PDZ256mk:
7595 case VFMSUBADD231PDZ256mkz:
7596 case VFMSUBADD231PDZ256r:
7597 case VFMSUBADD231PDZ256rk:
7598 case VFMSUBADD231PDZ256rkz:
7599 case VFMSUBADD231PDZm:
7600 case VFMSUBADD231PDZmb:
7601 case VFMSUBADD231PDZmbk:
7602 case VFMSUBADD231PDZmbkz:
7603 case VFMSUBADD231PDZmk:
7604 case VFMSUBADD231PDZmkz:
7605 case VFMSUBADD231PDZr:
7606 case VFMSUBADD231PDZrb:
7607 case VFMSUBADD231PDZrbk:
7608 case VFMSUBADD231PDZrbkz:
7609 case VFMSUBADD231PDZrk:
7610 case VFMSUBADD231PDZrkz:
7611 case VFMSUBADD231PDm:
7612 case VFMSUBADD231PDr:
7613 return true;
7614 }
7615 return false;
7616}
7617
7618bool isVFRCZSS(unsigned Opcode) {
7619 switch (Opcode) {
7620 case VFRCZSSrm:
7621 case VFRCZSSrr:
7622 return true;
7623 }
7624 return false;
7625}
7626
7627bool isMINPS(unsigned Opcode) {
7628 switch (Opcode) {
7629 case MINPSrm:
7630 case MINPSrr:
7631 return true;
7632 }
7633 return false;
7634}
7635
7636bool isFPREM1(unsigned Opcode) {
7637 return Opcode == FPREM1;
7638}
7639
7640bool isVPCMPUB(unsigned Opcode) {
7641 switch (Opcode) {
7642 case VPCMPUBZ128rmi:
7643 case VPCMPUBZ128rmik:
7644 case VPCMPUBZ128rri:
7645 case VPCMPUBZ128rrik:
7646 case VPCMPUBZ256rmi:
7647 case VPCMPUBZ256rmik:
7648 case VPCMPUBZ256rri:
7649 case VPCMPUBZ256rrik:
7650 case VPCMPUBZrmi:
7651 case VPCMPUBZrmik:
7652 case VPCMPUBZrri:
7653 case VPCMPUBZrrik:
7654 return true;
7655 }
7656 return false;
7657}
7658
7659bool isVSQRTPD(unsigned Opcode) {
7660 switch (Opcode) {
7661 case VSQRTPDYm:
7662 case VSQRTPDYr:
7663 case VSQRTPDZ128m:
7664 case VSQRTPDZ128mb:
7665 case VSQRTPDZ128mbk:
7666 case VSQRTPDZ128mbkz:
7667 case VSQRTPDZ128mk:
7668 case VSQRTPDZ128mkz:
7669 case VSQRTPDZ128r:
7670 case VSQRTPDZ128rk:
7671 case VSQRTPDZ128rkz:
7672 case VSQRTPDZ256m:
7673 case VSQRTPDZ256mb:
7674 case VSQRTPDZ256mbk:
7675 case VSQRTPDZ256mbkz:
7676 case VSQRTPDZ256mk:
7677 case VSQRTPDZ256mkz:
7678 case VSQRTPDZ256r:
7679 case VSQRTPDZ256rk:
7680 case VSQRTPDZ256rkz:
7681 case VSQRTPDZm:
7682 case VSQRTPDZmb:
7683 case VSQRTPDZmbk:
7684 case VSQRTPDZmbkz:
7685 case VSQRTPDZmk:
7686 case VSQRTPDZmkz:
7687 case VSQRTPDZr:
7688 case VSQRTPDZrb:
7689 case VSQRTPDZrbk:
7690 case VSQRTPDZrbkz:
7691 case VSQRTPDZrk:
7692 case VSQRTPDZrkz:
7693 case VSQRTPDm:
7694 case VSQRTPDr:
7695 return true;
7696 }
7697 return false;
7698}
7699
7700bool isVFRCZPS(unsigned Opcode) {
7701 switch (Opcode) {
7702 case VFRCZPSYrm:
7703 case VFRCZPSYrr:
7704 case VFRCZPSrm:
7705 case VFRCZPSrr:
7706 return true;
7707 }
7708 return false;
7709}
7710
7711bool isVFNMADD213SS(unsigned Opcode) {
7712 switch (Opcode) {
7713 case VFNMADD213SSZm_Int:
7714 case VFNMADD213SSZmk_Int:
7715 case VFNMADD213SSZmkz_Int:
7716 case VFNMADD213SSZr_Int:
7717 case VFNMADD213SSZrb_Int:
7718 case VFNMADD213SSZrbk_Int:
7719 case VFNMADD213SSZrbkz_Int:
7720 case VFNMADD213SSZrk_Int:
7721 case VFNMADD213SSZrkz_Int:
7722 case VFNMADD213SSm_Int:
7723 case VFNMADD213SSr_Int:
7724 return true;
7725 }
7726 return false;
7727}
7728
7729bool isVPMOVDW(unsigned Opcode) {
7730 switch (Opcode) {
7731 case VPMOVDWZ128mr:
7732 case VPMOVDWZ128mrk:
7733 case VPMOVDWZ128rr:
7734 case VPMOVDWZ128rrk:
7735 case VPMOVDWZ128rrkz:
7736 case VPMOVDWZ256mr:
7737 case VPMOVDWZ256mrk:
7738 case VPMOVDWZ256rr:
7739 case VPMOVDWZ256rrk:
7740 case VPMOVDWZ256rrkz:
7741 case VPMOVDWZmr:
7742 case VPMOVDWZmrk:
7743 case VPMOVDWZrr:
7744 case VPMOVDWZrrk:
7745 case VPMOVDWZrrkz:
7746 return true;
7747 }
7748 return false;
7749}
7750
7751bool isVCVTPH2HF8S(unsigned Opcode) {
7752 switch (Opcode) {
7753 case VCVTPH2HF8SZ128rm:
7754 case VCVTPH2HF8SZ128rmb:
7755 case VCVTPH2HF8SZ128rmbk:
7756 case VCVTPH2HF8SZ128rmbkz:
7757 case VCVTPH2HF8SZ128rmk:
7758 case VCVTPH2HF8SZ128rmkz:
7759 case VCVTPH2HF8SZ128rr:
7760 case VCVTPH2HF8SZ128rrk:
7761 case VCVTPH2HF8SZ128rrkz:
7762 case VCVTPH2HF8SZ256rm:
7763 case VCVTPH2HF8SZ256rmb:
7764 case VCVTPH2HF8SZ256rmbk:
7765 case VCVTPH2HF8SZ256rmbkz:
7766 case VCVTPH2HF8SZ256rmk:
7767 case VCVTPH2HF8SZ256rmkz:
7768 case VCVTPH2HF8SZ256rr:
7769 case VCVTPH2HF8SZ256rrk:
7770 case VCVTPH2HF8SZ256rrkz:
7771 case VCVTPH2HF8SZrm:
7772 case VCVTPH2HF8SZrmb:
7773 case VCVTPH2HF8SZrmbk:
7774 case VCVTPH2HF8SZrmbkz:
7775 case VCVTPH2HF8SZrmk:
7776 case VCVTPH2HF8SZrmkz:
7777 case VCVTPH2HF8SZrr:
7778 case VCVTPH2HF8SZrrk:
7779 case VCVTPH2HF8SZrrkz:
7780 return true;
7781 }
7782 return false;
7783}
7784
7785bool isVPSHRDVQ(unsigned Opcode) {
7786 switch (Opcode) {
7787 case VPSHRDVQZ128m:
7788 case VPSHRDVQZ128mb:
7789 case VPSHRDVQZ128mbk:
7790 case VPSHRDVQZ128mbkz:
7791 case VPSHRDVQZ128mk:
7792 case VPSHRDVQZ128mkz:
7793 case VPSHRDVQZ128r:
7794 case VPSHRDVQZ128rk:
7795 case VPSHRDVQZ128rkz:
7796 case VPSHRDVQZ256m:
7797 case VPSHRDVQZ256mb:
7798 case VPSHRDVQZ256mbk:
7799 case VPSHRDVQZ256mbkz:
7800 case VPSHRDVQZ256mk:
7801 case VPSHRDVQZ256mkz:
7802 case VPSHRDVQZ256r:
7803 case VPSHRDVQZ256rk:
7804 case VPSHRDVQZ256rkz:
7805 case VPSHRDVQZm:
7806 case VPSHRDVQZmb:
7807 case VPSHRDVQZmbk:
7808 case VPSHRDVQZmbkz:
7809 case VPSHRDVQZmk:
7810 case VPSHRDVQZmkz:
7811 case VPSHRDVQZr:
7812 case VPSHRDVQZrk:
7813 case VPSHRDVQZrkz:
7814 return true;
7815 }
7816 return false;
7817}
7818
7819bool isVBROADCASTSD(unsigned Opcode) {
7820 switch (Opcode) {
7821 case VBROADCASTSDYrm:
7822 case VBROADCASTSDYrr:
7823 case VBROADCASTSDZ256rm:
7824 case VBROADCASTSDZ256rmk:
7825 case VBROADCASTSDZ256rmkz:
7826 case VBROADCASTSDZ256rr:
7827 case VBROADCASTSDZ256rrk:
7828 case VBROADCASTSDZ256rrkz:
7829 case VBROADCASTSDZrm:
7830 case VBROADCASTSDZrmk:
7831 case VBROADCASTSDZrmkz:
7832 case VBROADCASTSDZrr:
7833 case VBROADCASTSDZrrk:
7834 case VBROADCASTSDZrrkz:
7835 return true;
7836 }
7837 return false;
7838}
7839
7840bool isVSHUFPD(unsigned Opcode) {
7841 switch (Opcode) {
7842 case VSHUFPDYrmi:
7843 case VSHUFPDYrri:
7844 case VSHUFPDZ128rmbi:
7845 case VSHUFPDZ128rmbik:
7846 case VSHUFPDZ128rmbikz:
7847 case VSHUFPDZ128rmi:
7848 case VSHUFPDZ128rmik:
7849 case VSHUFPDZ128rmikz:
7850 case VSHUFPDZ128rri:
7851 case VSHUFPDZ128rrik:
7852 case VSHUFPDZ128rrikz:
7853 case VSHUFPDZ256rmbi:
7854 case VSHUFPDZ256rmbik:
7855 case VSHUFPDZ256rmbikz:
7856 case VSHUFPDZ256rmi:
7857 case VSHUFPDZ256rmik:
7858 case VSHUFPDZ256rmikz:
7859 case VSHUFPDZ256rri:
7860 case VSHUFPDZ256rrik:
7861 case VSHUFPDZ256rrikz:
7862 case VSHUFPDZrmbi:
7863 case VSHUFPDZrmbik:
7864 case VSHUFPDZrmbikz:
7865 case VSHUFPDZrmi:
7866 case VSHUFPDZrmik:
7867 case VSHUFPDZrmikz:
7868 case VSHUFPDZrri:
7869 case VSHUFPDZrrik:
7870 case VSHUFPDZrrikz:
7871 case VSHUFPDrmi:
7872 case VSHUFPDrri:
7873 return true;
7874 }
7875 return false;
7876}
7877
7878bool isVPSUBSW(unsigned Opcode) {
7879 switch (Opcode) {
7880 case VPSUBSWYrm:
7881 case VPSUBSWYrr:
7882 case VPSUBSWZ128rm:
7883 case VPSUBSWZ128rmk:
7884 case VPSUBSWZ128rmkz:
7885 case VPSUBSWZ128rr:
7886 case VPSUBSWZ128rrk:
7887 case VPSUBSWZ128rrkz:
7888 case VPSUBSWZ256rm:
7889 case VPSUBSWZ256rmk:
7890 case VPSUBSWZ256rmkz:
7891 case VPSUBSWZ256rr:
7892 case VPSUBSWZ256rrk:
7893 case VPSUBSWZ256rrkz:
7894 case VPSUBSWZrm:
7895 case VPSUBSWZrmk:
7896 case VPSUBSWZrmkz:
7897 case VPSUBSWZrr:
7898 case VPSUBSWZrrk:
7899 case VPSUBSWZrrkz:
7900 case VPSUBSWrm:
7901 case VPSUBSWrr:
7902 return true;
7903 }
7904 return false;
7905}
7906
7907bool isKUNPCKBW(unsigned Opcode) {
7908 return Opcode == KUNPCKBWkk;
7909}
7910
7911bool isVPBLENDD(unsigned Opcode) {
7912 switch (Opcode) {
7913 case VPBLENDDYrmi:
7914 case VPBLENDDYrri:
7915 case VPBLENDDrmi:
7916 case VPBLENDDrri:
7917 return true;
7918 }
7919 return false;
7920}
7921
7922bool isUNPCKHPD(unsigned Opcode) {
7923 switch (Opcode) {
7924 case UNPCKHPDrm:
7925 case UNPCKHPDrr:
7926 return true;
7927 }
7928 return false;
7929}
7930
7931bool isVFNMADD231SD(unsigned Opcode) {
7932 switch (Opcode) {
7933 case VFNMADD231SDZm_Int:
7934 case VFNMADD231SDZmk_Int:
7935 case VFNMADD231SDZmkz_Int:
7936 case VFNMADD231SDZr_Int:
7937 case VFNMADD231SDZrb_Int:
7938 case VFNMADD231SDZrbk_Int:
7939 case VFNMADD231SDZrbkz_Int:
7940 case VFNMADD231SDZrk_Int:
7941 case VFNMADD231SDZrkz_Int:
7942 case VFNMADD231SDm_Int:
7943 case VFNMADD231SDr_Int:
7944 return true;
7945 }
7946 return false;
7947}
7948
7949bool isVPBROADCASTMW2D(unsigned Opcode) {
7950 switch (Opcode) {
7951 case VPBROADCASTMW2DZ128rr:
7952 case VPBROADCASTMW2DZ256rr:
7953 case VPBROADCASTMW2DZrr:
7954 return true;
7955 }
7956 return false;
7957}
7958
7959bool isVPMULTISHIFTQB(unsigned Opcode) {
7960 switch (Opcode) {
7961 case VPMULTISHIFTQBZ128rm:
7962 case VPMULTISHIFTQBZ128rmb:
7963 case VPMULTISHIFTQBZ128rmbk:
7964 case VPMULTISHIFTQBZ128rmbkz:
7965 case VPMULTISHIFTQBZ128rmk:
7966 case VPMULTISHIFTQBZ128rmkz:
7967 case VPMULTISHIFTQBZ128rr:
7968 case VPMULTISHIFTQBZ128rrk:
7969 case VPMULTISHIFTQBZ128rrkz:
7970 case VPMULTISHIFTQBZ256rm:
7971 case VPMULTISHIFTQBZ256rmb:
7972 case VPMULTISHIFTQBZ256rmbk:
7973 case VPMULTISHIFTQBZ256rmbkz:
7974 case VPMULTISHIFTQBZ256rmk:
7975 case VPMULTISHIFTQBZ256rmkz:
7976 case VPMULTISHIFTQBZ256rr:
7977 case VPMULTISHIFTQBZ256rrk:
7978 case VPMULTISHIFTQBZ256rrkz:
7979 case VPMULTISHIFTQBZrm:
7980 case VPMULTISHIFTQBZrmb:
7981 case VPMULTISHIFTQBZrmbk:
7982 case VPMULTISHIFTQBZrmbkz:
7983 case VPMULTISHIFTQBZrmk:
7984 case VPMULTISHIFTQBZrmkz:
7985 case VPMULTISHIFTQBZrr:
7986 case VPMULTISHIFTQBZrrk:
7987 case VPMULTISHIFTQBZrrkz:
7988 return true;
7989 }
7990 return false;
7991}
7992
7993bool isVP2INTERSECTQ(unsigned Opcode) {
7994 switch (Opcode) {
7995 case VP2INTERSECTQZ128rm:
7996 case VP2INTERSECTQZ128rmb:
7997 case VP2INTERSECTQZ128rr:
7998 case VP2INTERSECTQZ256rm:
7999 case VP2INTERSECTQZ256rmb:
8000 case VP2INTERSECTQZ256rr:
8001 case VP2INTERSECTQZrm:
8002 case VP2INTERSECTQZrmb:
8003 case VP2INTERSECTQZrr:
8004 return true;
8005 }
8006 return false;
8007}
8008
8009bool isVFNMSUB132BF16(unsigned Opcode) {
8010 switch (Opcode) {
8011 case VFNMSUB132BF16Z128m:
8012 case VFNMSUB132BF16Z128mb:
8013 case VFNMSUB132BF16Z128mbk:
8014 case VFNMSUB132BF16Z128mbkz:
8015 case VFNMSUB132BF16Z128mk:
8016 case VFNMSUB132BF16Z128mkz:
8017 case VFNMSUB132BF16Z128r:
8018 case VFNMSUB132BF16Z128rk:
8019 case VFNMSUB132BF16Z128rkz:
8020 case VFNMSUB132BF16Z256m:
8021 case VFNMSUB132BF16Z256mb:
8022 case VFNMSUB132BF16Z256mbk:
8023 case VFNMSUB132BF16Z256mbkz:
8024 case VFNMSUB132BF16Z256mk:
8025 case VFNMSUB132BF16Z256mkz:
8026 case VFNMSUB132BF16Z256r:
8027 case VFNMSUB132BF16Z256rk:
8028 case VFNMSUB132BF16Z256rkz:
8029 case VFNMSUB132BF16Zm:
8030 case VFNMSUB132BF16Zmb:
8031 case VFNMSUB132BF16Zmbk:
8032 case VFNMSUB132BF16Zmbkz:
8033 case VFNMSUB132BF16Zmk:
8034 case VFNMSUB132BF16Zmkz:
8035 case VFNMSUB132BF16Zr:
8036 case VFNMSUB132BF16Zrk:
8037 case VFNMSUB132BF16Zrkz:
8038 return true;
8039 }
8040 return false;
8041}
8042
8043bool isTTCMMIMFP16PS(unsigned Opcode) {
8044 return Opcode == TTCMMIMFP16PS;
8045}
8046
8047bool isVFMADD213BF16(unsigned Opcode) {
8048 switch (Opcode) {
8049 case VFMADD213BF16Z128m:
8050 case VFMADD213BF16Z128mb:
8051 case VFMADD213BF16Z128mbk:
8052 case VFMADD213BF16Z128mbkz:
8053 case VFMADD213BF16Z128mk:
8054 case VFMADD213BF16Z128mkz:
8055 case VFMADD213BF16Z128r:
8056 case VFMADD213BF16Z128rk:
8057 case VFMADD213BF16Z128rkz:
8058 case VFMADD213BF16Z256m:
8059 case VFMADD213BF16Z256mb:
8060 case VFMADD213BF16Z256mbk:
8061 case VFMADD213BF16Z256mbkz:
8062 case VFMADD213BF16Z256mk:
8063 case VFMADD213BF16Z256mkz:
8064 case VFMADD213BF16Z256r:
8065 case VFMADD213BF16Z256rk:
8066 case VFMADD213BF16Z256rkz:
8067 case VFMADD213BF16Zm:
8068 case VFMADD213BF16Zmb:
8069 case VFMADD213BF16Zmbk:
8070 case VFMADD213BF16Zmbkz:
8071 case VFMADD213BF16Zmk:
8072 case VFMADD213BF16Zmkz:
8073 case VFMADD213BF16Zr:
8074 case VFMADD213BF16Zrk:
8075 case VFMADD213BF16Zrkz:
8076 return true;
8077 }
8078 return false;
8079}
8080
8081bool isVPUNPCKHWD(unsigned Opcode) {
8082 switch (Opcode) {
8083 case VPUNPCKHWDYrm:
8084 case VPUNPCKHWDYrr:
8085 case VPUNPCKHWDZ128rm:
8086 case VPUNPCKHWDZ128rmk:
8087 case VPUNPCKHWDZ128rmkz:
8088 case VPUNPCKHWDZ128rr:
8089 case VPUNPCKHWDZ128rrk:
8090 case VPUNPCKHWDZ128rrkz:
8091 case VPUNPCKHWDZ256rm:
8092 case VPUNPCKHWDZ256rmk:
8093 case VPUNPCKHWDZ256rmkz:
8094 case VPUNPCKHWDZ256rr:
8095 case VPUNPCKHWDZ256rrk:
8096 case VPUNPCKHWDZ256rrkz:
8097 case VPUNPCKHWDZrm:
8098 case VPUNPCKHWDZrmk:
8099 case VPUNPCKHWDZrmkz:
8100 case VPUNPCKHWDZrr:
8101 case VPUNPCKHWDZrrk:
8102 case VPUNPCKHWDZrrkz:
8103 case VPUNPCKHWDrm:
8104 case VPUNPCKHWDrr:
8105 return true;
8106 }
8107 return false;
8108}
8109
8110bool isVPERM2F128(unsigned Opcode) {
8111 switch (Opcode) {
8112 case VPERM2F128rmi:
8113 case VPERM2F128rri:
8114 return true;
8115 }
8116 return false;
8117}
8118
8119bool isINSD(unsigned Opcode) {
8120 return Opcode == INSL;
8121}
8122
8123bool isLFS(unsigned Opcode) {
8124 switch (Opcode) {
8125 case LFS16rm:
8126 case LFS32rm:
8127 case LFS64rm:
8128 return true;
8129 }
8130 return false;
8131}
8132
8133bool isFMULP(unsigned Opcode) {
8134 return Opcode == MUL_FPrST0;
8135}
8136
8137bool isCWD(unsigned Opcode) {
8138 return Opcode == CWD;
8139}
8140
8141bool isVDIVSS(unsigned Opcode) {
8142 switch (Opcode) {
8143 case VDIVSSZrm_Int:
8144 case VDIVSSZrmk_Int:
8145 case VDIVSSZrmkz_Int:
8146 case VDIVSSZrr_Int:
8147 case VDIVSSZrrb_Int:
8148 case VDIVSSZrrbk_Int:
8149 case VDIVSSZrrbkz_Int:
8150 case VDIVSSZrrk_Int:
8151 case VDIVSSZrrkz_Int:
8152 case VDIVSSrm_Int:
8153 case VDIVSSrr_Int:
8154 return true;
8155 }
8156 return false;
8157}
8158
8159bool isVPSRLQ(unsigned Opcode) {
8160 switch (Opcode) {
8161 case VPSRLQYri:
8162 case VPSRLQYrm:
8163 case VPSRLQYrr:
8164 case VPSRLQZ128mbi:
8165 case VPSRLQZ128mbik:
8166 case VPSRLQZ128mbikz:
8167 case VPSRLQZ128mi:
8168 case VPSRLQZ128mik:
8169 case VPSRLQZ128mikz:
8170 case VPSRLQZ128ri:
8171 case VPSRLQZ128rik:
8172 case VPSRLQZ128rikz:
8173 case VPSRLQZ128rm:
8174 case VPSRLQZ128rmk:
8175 case VPSRLQZ128rmkz:
8176 case VPSRLQZ128rr:
8177 case VPSRLQZ128rrk:
8178 case VPSRLQZ128rrkz:
8179 case VPSRLQZ256mbi:
8180 case VPSRLQZ256mbik:
8181 case VPSRLQZ256mbikz:
8182 case VPSRLQZ256mi:
8183 case VPSRLQZ256mik:
8184 case VPSRLQZ256mikz:
8185 case VPSRLQZ256ri:
8186 case VPSRLQZ256rik:
8187 case VPSRLQZ256rikz:
8188 case VPSRLQZ256rm:
8189 case VPSRLQZ256rmk:
8190 case VPSRLQZ256rmkz:
8191 case VPSRLQZ256rr:
8192 case VPSRLQZ256rrk:
8193 case VPSRLQZ256rrkz:
8194 case VPSRLQZmbi:
8195 case VPSRLQZmbik:
8196 case VPSRLQZmbikz:
8197 case VPSRLQZmi:
8198 case VPSRLQZmik:
8199 case VPSRLQZmikz:
8200 case VPSRLQZri:
8201 case VPSRLQZrik:
8202 case VPSRLQZrikz:
8203 case VPSRLQZrm:
8204 case VPSRLQZrmk:
8205 case VPSRLQZrmkz:
8206 case VPSRLQZrr:
8207 case VPSRLQZrrk:
8208 case VPSRLQZrrkz:
8209 case VPSRLQri:
8210 case VPSRLQrm:
8211 case VPSRLQrr:
8212 return true;
8213 }
8214 return false;
8215}
8216
8217bool isFSQRT(unsigned Opcode) {
8218 return Opcode == SQRT_F;
8219}
8220
8221bool isJRCXZ(unsigned Opcode) {
8222 return Opcode == JRCXZ;
8223}
8224
8225bool isVPMOVMSKB(unsigned Opcode) {
8226 switch (Opcode) {
8227 case VPMOVMSKBYrr:
8228 case VPMOVMSKBrr:
8229 return true;
8230 }
8231 return false;
8232}
8233
8234bool isAESDEC256KL(unsigned Opcode) {
8235 return Opcode == AESDEC256KL;
8236}
8237
8238bool isFLDENV(unsigned Opcode) {
8239 return Opcode == FLDENVm;
8240}
8241
8242bool isVPHSUBWD(unsigned Opcode) {
8243 switch (Opcode) {
8244 case VPHSUBWDrm:
8245 case VPHSUBWDrr:
8246 return true;
8247 }
8248 return false;
8249}
8250
8251bool isWBNOINVD(unsigned Opcode) {
8252 return Opcode == WBNOINVD;
8253}
8254
8255bool isVEXPANDPD(unsigned Opcode) {
8256 switch (Opcode) {
8257 case VEXPANDPDZ128rm:
8258 case VEXPANDPDZ128rmk:
8259 case VEXPANDPDZ128rmkz:
8260 case VEXPANDPDZ128rr:
8261 case VEXPANDPDZ128rrk:
8262 case VEXPANDPDZ128rrkz:
8263 case VEXPANDPDZ256rm:
8264 case VEXPANDPDZ256rmk:
8265 case VEXPANDPDZ256rmkz:
8266 case VEXPANDPDZ256rr:
8267 case VEXPANDPDZ256rrk:
8268 case VEXPANDPDZ256rrkz:
8269 case VEXPANDPDZrm:
8270 case VEXPANDPDZrmk:
8271 case VEXPANDPDZrmkz:
8272 case VEXPANDPDZrr:
8273 case VEXPANDPDZrrk:
8274 case VEXPANDPDZrrkz:
8275 return true;
8276 }
8277 return false;
8278}
8279
8280bool isFYL2XP1(unsigned Opcode) {
8281 return Opcode == FYL2XP1;
8282}
8283
8284bool isPREFETCHT2(unsigned Opcode) {
8285 return Opcode == PREFETCHT2;
8286}
8287
8288bool isVPDPBSUDS(unsigned Opcode) {
8289 switch (Opcode) {
8290 case VPDPBSUDSYrm:
8291 case VPDPBSUDSYrr:
8292 case VPDPBSUDSZ128m:
8293 case VPDPBSUDSZ128mb:
8294 case VPDPBSUDSZ128mbk:
8295 case VPDPBSUDSZ128mbkz:
8296 case VPDPBSUDSZ128mk:
8297 case VPDPBSUDSZ128mkz:
8298 case VPDPBSUDSZ128r:
8299 case VPDPBSUDSZ128rk:
8300 case VPDPBSUDSZ128rkz:
8301 case VPDPBSUDSZ256m:
8302 case VPDPBSUDSZ256mb:
8303 case VPDPBSUDSZ256mbk:
8304 case VPDPBSUDSZ256mbkz:
8305 case VPDPBSUDSZ256mk:
8306 case VPDPBSUDSZ256mkz:
8307 case VPDPBSUDSZ256r:
8308 case VPDPBSUDSZ256rk:
8309 case VPDPBSUDSZ256rkz:
8310 case VPDPBSUDSZm:
8311 case VPDPBSUDSZmb:
8312 case VPDPBSUDSZmbk:
8313 case VPDPBSUDSZmbkz:
8314 case VPDPBSUDSZmk:
8315 case VPDPBSUDSZmkz:
8316 case VPDPBSUDSZr:
8317 case VPDPBSUDSZrk:
8318 case VPDPBSUDSZrkz:
8319 case VPDPBSUDSrm:
8320 case VPDPBSUDSrr:
8321 return true;
8322 }
8323 return false;
8324}
8325
8326bool isVSHA512MSG2(unsigned Opcode) {
8327 return Opcode == VSHA512MSG2rr;
8328}
8329
8330bool isPMULHUW(unsigned Opcode) {
8331 switch (Opcode) {
8332 case MMX_PMULHUWrm:
8333 case MMX_PMULHUWrr:
8334 case PMULHUWrm:
8335 case PMULHUWrr:
8336 return true;
8337 }
8338 return false;
8339}
8340
8341bool isKANDNB(unsigned Opcode) {
8342 return Opcode == KANDNBkk;
8343}
8344
8345bool isVCVTUW2PH(unsigned Opcode) {
8346 switch (Opcode) {
8347 case VCVTUW2PHZ128rm:
8348 case VCVTUW2PHZ128rmb:
8349 case VCVTUW2PHZ128rmbk:
8350 case VCVTUW2PHZ128rmbkz:
8351 case VCVTUW2PHZ128rmk:
8352 case VCVTUW2PHZ128rmkz:
8353 case VCVTUW2PHZ128rr:
8354 case VCVTUW2PHZ128rrk:
8355 case VCVTUW2PHZ128rrkz:
8356 case VCVTUW2PHZ256rm:
8357 case VCVTUW2PHZ256rmb:
8358 case VCVTUW2PHZ256rmbk:
8359 case VCVTUW2PHZ256rmbkz:
8360 case VCVTUW2PHZ256rmk:
8361 case VCVTUW2PHZ256rmkz:
8362 case VCVTUW2PHZ256rr:
8363 case VCVTUW2PHZ256rrk:
8364 case VCVTUW2PHZ256rrkz:
8365 case VCVTUW2PHZrm:
8366 case VCVTUW2PHZrmb:
8367 case VCVTUW2PHZrmbk:
8368 case VCVTUW2PHZrmbkz:
8369 case VCVTUW2PHZrmk:
8370 case VCVTUW2PHZrmkz:
8371 case VCVTUW2PHZrr:
8372 case VCVTUW2PHZrrb:
8373 case VCVTUW2PHZrrbk:
8374 case VCVTUW2PHZrrbkz:
8375 case VCVTUW2PHZrrk:
8376 case VCVTUW2PHZrrkz:
8377 return true;
8378 }
8379 return false;
8380}
8381
8382bool isAESDECWIDE256KL(unsigned Opcode) {
8383 return Opcode == AESDECWIDE256KL;
8384}
8385
8386bool isVPGATHERDD(unsigned Opcode) {
8387 switch (Opcode) {
8388 case VPGATHERDDYrm:
8389 case VPGATHERDDZ128rm:
8390 case VPGATHERDDZ256rm:
8391 case VPGATHERDDZrm:
8392 case VPGATHERDDrm:
8393 return true;
8394 }
8395 return false;
8396}
8397
8398bool isVREDUCESH(unsigned Opcode) {
8399 switch (Opcode) {
8400 case VREDUCESHZrmi:
8401 case VREDUCESHZrmik:
8402 case VREDUCESHZrmikz:
8403 case VREDUCESHZrri:
8404 case VREDUCESHZrrib:
8405 case VREDUCESHZrribk:
8406 case VREDUCESHZrribkz:
8407 case VREDUCESHZrrik:
8408 case VREDUCESHZrrikz:
8409 return true;
8410 }
8411 return false;
8412}
8413
8414bool isPOPFQ(unsigned Opcode) {
8415 return Opcode == POPF64;
8416}
8417
8418bool isPAVGUSB(unsigned Opcode) {
8419 switch (Opcode) {
8420 case PAVGUSBrm:
8421 case PAVGUSBrr:
8422 return true;
8423 }
8424 return false;
8425}
8426
8427bool isVALIGND(unsigned Opcode) {
8428 switch (Opcode) {
8429 case VALIGNDZ128rmbi:
8430 case VALIGNDZ128rmbik:
8431 case VALIGNDZ128rmbikz:
8432 case VALIGNDZ128rmi:
8433 case VALIGNDZ128rmik:
8434 case VALIGNDZ128rmikz:
8435 case VALIGNDZ128rri:
8436 case VALIGNDZ128rrik:
8437 case VALIGNDZ128rrikz:
8438 case VALIGNDZ256rmbi:
8439 case VALIGNDZ256rmbik:
8440 case VALIGNDZ256rmbikz:
8441 case VALIGNDZ256rmi:
8442 case VALIGNDZ256rmik:
8443 case VALIGNDZ256rmikz:
8444 case VALIGNDZ256rri:
8445 case VALIGNDZ256rrik:
8446 case VALIGNDZ256rrikz:
8447 case VALIGNDZrmbi:
8448 case VALIGNDZrmbik:
8449 case VALIGNDZrmbikz:
8450 case VALIGNDZrmi:
8451 case VALIGNDZrmik:
8452 case VALIGNDZrmikz:
8453 case VALIGNDZrri:
8454 case VALIGNDZrrik:
8455 case VALIGNDZrrikz:
8456 return true;
8457 }
8458 return false;
8459}
8460
8461bool isVPHMINPOSUW(unsigned Opcode) {
8462 switch (Opcode) {
8463 case VPHMINPOSUWrm:
8464 case VPHMINPOSUWrr:
8465 return true;
8466 }
8467 return false;
8468}
8469
8470bool isLIDTD(unsigned Opcode) {
8471 return Opcode == LIDT32m;
8472}
8473
8474bool isVPERMT2PD(unsigned Opcode) {
8475 switch (Opcode) {
8476 case VPERMT2PDZ128rm:
8477 case VPERMT2PDZ128rmb:
8478 case VPERMT2PDZ128rmbk:
8479 case VPERMT2PDZ128rmbkz:
8480 case VPERMT2PDZ128rmk:
8481 case VPERMT2PDZ128rmkz:
8482 case VPERMT2PDZ128rr:
8483 case VPERMT2PDZ128rrk:
8484 case VPERMT2PDZ128rrkz:
8485 case VPERMT2PDZ256rm:
8486 case VPERMT2PDZ256rmb:
8487 case VPERMT2PDZ256rmbk:
8488 case VPERMT2PDZ256rmbkz:
8489 case VPERMT2PDZ256rmk:
8490 case VPERMT2PDZ256rmkz:
8491 case VPERMT2PDZ256rr:
8492 case VPERMT2PDZ256rrk:
8493 case VPERMT2PDZ256rrkz:
8494 case VPERMT2PDZrm:
8495 case VPERMT2PDZrmb:
8496 case VPERMT2PDZrmbk:
8497 case VPERMT2PDZrmbkz:
8498 case VPERMT2PDZrmk:
8499 case VPERMT2PDZrmkz:
8500 case VPERMT2PDZrr:
8501 case VPERMT2PDZrrk:
8502 case VPERMT2PDZrrkz:
8503 return true;
8504 }
8505 return false;
8506}
8507
8508bool isVMLAUNCH(unsigned Opcode) {
8509 return Opcode == VMLAUNCH;
8510}
8511
8512bool isVPXORQ(unsigned Opcode) {
8513 switch (Opcode) {
8514 case VPXORQZ128rm:
8515 case VPXORQZ128rmb:
8516 case VPXORQZ128rmbk:
8517 case VPXORQZ128rmbkz:
8518 case VPXORQZ128rmk:
8519 case VPXORQZ128rmkz:
8520 case VPXORQZ128rr:
8521 case VPXORQZ128rrk:
8522 case VPXORQZ128rrkz:
8523 case VPXORQZ256rm:
8524 case VPXORQZ256rmb:
8525 case VPXORQZ256rmbk:
8526 case VPXORQZ256rmbkz:
8527 case VPXORQZ256rmk:
8528 case VPXORQZ256rmkz:
8529 case VPXORQZ256rr:
8530 case VPXORQZ256rrk:
8531 case VPXORQZ256rrkz:
8532 case VPXORQZrm:
8533 case VPXORQZrmb:
8534 case VPXORQZrmbk:
8535 case VPXORQZrmbkz:
8536 case VPXORQZrmk:
8537 case VPXORQZrmkz:
8538 case VPXORQZrr:
8539 case VPXORQZrrk:
8540 case VPXORQZrrkz:
8541 return true;
8542 }
8543 return false;
8544}
8545
8546bool isMOVNTDQ(unsigned Opcode) {
8547 return Opcode == MOVNTDQmr;
8548}
8549
8550bool isPOP2P(unsigned Opcode) {
8551 return Opcode == POP2P;
8552}
8553
8554bool isVADDPD(unsigned Opcode) {
8555 switch (Opcode) {
8556 case VADDPDYrm:
8557 case VADDPDYrr:
8558 case VADDPDZ128rm:
8559 case VADDPDZ128rmb:
8560 case VADDPDZ128rmbk:
8561 case VADDPDZ128rmbkz:
8562 case VADDPDZ128rmk:
8563 case VADDPDZ128rmkz:
8564 case VADDPDZ128rr:
8565 case VADDPDZ128rrk:
8566 case VADDPDZ128rrkz:
8567 case VADDPDZ256rm:
8568 case VADDPDZ256rmb:
8569 case VADDPDZ256rmbk:
8570 case VADDPDZ256rmbkz:
8571 case VADDPDZ256rmk:
8572 case VADDPDZ256rmkz:
8573 case VADDPDZ256rr:
8574 case VADDPDZ256rrk:
8575 case VADDPDZ256rrkz:
8576 case VADDPDZrm:
8577 case VADDPDZrmb:
8578 case VADDPDZrmbk:
8579 case VADDPDZrmbkz:
8580 case VADDPDZrmk:
8581 case VADDPDZrmkz:
8582 case VADDPDZrr:
8583 case VADDPDZrrb:
8584 case VADDPDZrrbk:
8585 case VADDPDZrrbkz:
8586 case VADDPDZrrk:
8587 case VADDPDZrrkz:
8588 case VADDPDrm:
8589 case VADDPDrr:
8590 return true;
8591 }
8592 return false;
8593}
8594
8595bool isSMSW(unsigned Opcode) {
8596 switch (Opcode) {
8597 case SMSW16m:
8598 case SMSW16r:
8599 case SMSW32r:
8600 case SMSW64r:
8601 return true;
8602 }
8603 return false;
8604}
8605
8606bool isVEXP2PD(unsigned Opcode) {
8607 switch (Opcode) {
8608 case VEXP2PDZm:
8609 case VEXP2PDZmb:
8610 case VEXP2PDZmbk:
8611 case VEXP2PDZmbkz:
8612 case VEXP2PDZmk:
8613 case VEXP2PDZmkz:
8614 case VEXP2PDZr:
8615 case VEXP2PDZrb:
8616 case VEXP2PDZrbk:
8617 case VEXP2PDZrbkz:
8618 case VEXP2PDZrk:
8619 case VEXP2PDZrkz:
8620 return true;
8621 }
8622 return false;
8623}
8624
8625bool isPMULUDQ(unsigned Opcode) {
8626 switch (Opcode) {
8627 case MMX_PMULUDQrm:
8628 case MMX_PMULUDQrr:
8629 case PMULUDQrm:
8630 case PMULUDQrr:
8631 return true;
8632 }
8633 return false;
8634}
8635
8636bool isIRET(unsigned Opcode) {
8637 return Opcode == IRET16;
8638}
8639
8640bool isMULPS(unsigned Opcode) {
8641 switch (Opcode) {
8642 case MULPSrm:
8643 case MULPSrr:
8644 return true;
8645 }
8646 return false;
8647}
8648
8649bool isTDPBF8PS(unsigned Opcode) {
8650 return Opcode == TDPBF8PS;
8651}
8652
8653bool isVFNMSUBPD(unsigned Opcode) {
8654 switch (Opcode) {
8655 case VFNMSUBPD4Ymr:
8656 case VFNMSUBPD4Yrm:
8657 case VFNMSUBPD4Yrr:
8658 case VFNMSUBPD4Yrr_REV:
8659 case VFNMSUBPD4mr:
8660 case VFNMSUBPD4rm:
8661 case VFNMSUBPD4rr:
8662 case VFNMSUBPD4rr_REV:
8663 return true;
8664 }
8665 return false;
8666}
8667
8668bool isPHADDW(unsigned Opcode) {
8669 switch (Opcode) {
8670 case MMX_PHADDWrm:
8671 case MMX_PHADDWrr:
8672 case PHADDWrm:
8673 case PHADDWrr:
8674 return true;
8675 }
8676 return false;
8677}
8678
8679bool isRDSEED(unsigned Opcode) {
8680 switch (Opcode) {
8681 case RDSEED16r:
8682 case RDSEED32r:
8683 case RDSEED64r:
8684 return true;
8685 }
8686 return false;
8687}
8688
8689bool isVPSHLW(unsigned Opcode) {
8690 switch (Opcode) {
8691 case VPSHLWmr:
8692 case VPSHLWrm:
8693 case VPSHLWrr:
8694 case VPSHLWrr_REV:
8695 return true;
8696 }
8697 return false;
8698}
8699
8700bool isRMPUPDATE(unsigned Opcode) {
8701 return Opcode == RMPUPDATE;
8702}
8703
8704bool isVFMADD231PH(unsigned Opcode) {
8705 switch (Opcode) {
8706 case VFMADD231PHZ128m:
8707 case VFMADD231PHZ128mb:
8708 case VFMADD231PHZ128mbk:
8709 case VFMADD231PHZ128mbkz:
8710 case VFMADD231PHZ128mk:
8711 case VFMADD231PHZ128mkz:
8712 case VFMADD231PHZ128r:
8713 case VFMADD231PHZ128rk:
8714 case VFMADD231PHZ128rkz:
8715 case VFMADD231PHZ256m:
8716 case VFMADD231PHZ256mb:
8717 case VFMADD231PHZ256mbk:
8718 case VFMADD231PHZ256mbkz:
8719 case VFMADD231PHZ256mk:
8720 case VFMADD231PHZ256mkz:
8721 case VFMADD231PHZ256r:
8722 case VFMADD231PHZ256rk:
8723 case VFMADD231PHZ256rkz:
8724 case VFMADD231PHZm:
8725 case VFMADD231PHZmb:
8726 case VFMADD231PHZmbk:
8727 case VFMADD231PHZmbkz:
8728 case VFMADD231PHZmk:
8729 case VFMADD231PHZmkz:
8730 case VFMADD231PHZr:
8731 case VFMADD231PHZrb:
8732 case VFMADD231PHZrbk:
8733 case VFMADD231PHZrbkz:
8734 case VFMADD231PHZrk:
8735 case VFMADD231PHZrkz:
8736 return true;
8737 }
8738 return false;
8739}
8740
8741bool isVPSHAD(unsigned Opcode) {
8742 switch (Opcode) {
8743 case VPSHADmr:
8744 case VPSHADrm:
8745 case VPSHADrr:
8746 case VPSHADrr_REV:
8747 return true;
8748 }
8749 return false;
8750}
8751
8752bool isCLWB(unsigned Opcode) {
8753 return Opcode == CLWB;
8754}
8755
8756bool isPSUBUSB(unsigned Opcode) {
8757 switch (Opcode) {
8758 case MMX_PSUBUSBrm:
8759 case MMX_PSUBUSBrr:
8760 case PSUBUSBrm:
8761 case PSUBUSBrr:
8762 return true;
8763 }
8764 return false;
8765}
8766
8767bool isVCVTTSD2USI(unsigned Opcode) {
8768 switch (Opcode) {
8769 case VCVTTSD2USI64Zrm_Int:
8770 case VCVTTSD2USI64Zrr_Int:
8771 case VCVTTSD2USI64Zrrb_Int:
8772 case VCVTTSD2USIZrm_Int:
8773 case VCVTTSD2USIZrr_Int:
8774 case VCVTTSD2USIZrrb_Int:
8775 return true;
8776 }
8777 return false;
8778}
8779
8780bool isVEXTRACTPS(unsigned Opcode) {
8781 switch (Opcode) {
8782 case VEXTRACTPSZmri:
8783 case VEXTRACTPSZrri:
8784 case VEXTRACTPSmri:
8785 case VEXTRACTPSrri:
8786 return true;
8787 }
8788 return false;
8789}
8790
8791bool isMOVLPD(unsigned Opcode) {
8792 switch (Opcode) {
8793 case MOVLPDmr:
8794 case MOVLPDrm:
8795 return true;
8796 }
8797 return false;
8798}
8799
8800bool isLGDTD(unsigned Opcode) {
8801 return Opcode == LGDT32m;
8802}
8803
8804bool isVPBROADCASTMB2Q(unsigned Opcode) {
8805 switch (Opcode) {
8806 case VPBROADCASTMB2QZ128rr:
8807 case VPBROADCASTMB2QZ256rr:
8808 case VPBROADCASTMB2QZrr:
8809 return true;
8810 }
8811 return false;
8812}
8813
8814bool isOUT(unsigned Opcode) {
8815 switch (Opcode) {
8816 case OUT16ir:
8817 case OUT16rr:
8818 case OUT32ir:
8819 case OUT32rr:
8820 case OUT8ir:
8821 case OUT8rr:
8822 return true;
8823 }
8824 return false;
8825}
8826
8827bool isVMSAVE(unsigned Opcode) {
8828 switch (Opcode) {
8829 case VMSAVE32:
8830 case VMSAVE64:
8831 return true;
8832 }
8833 return false;
8834}
8835
8836bool isVCVTQQ2PD(unsigned Opcode) {
8837 switch (Opcode) {
8838 case VCVTQQ2PDZ128rm:
8839 case VCVTQQ2PDZ128rmb:
8840 case VCVTQQ2PDZ128rmbk:
8841 case VCVTQQ2PDZ128rmbkz:
8842 case VCVTQQ2PDZ128rmk:
8843 case VCVTQQ2PDZ128rmkz:
8844 case VCVTQQ2PDZ128rr:
8845 case VCVTQQ2PDZ128rrk:
8846 case VCVTQQ2PDZ128rrkz:
8847 case VCVTQQ2PDZ256rm:
8848 case VCVTQQ2PDZ256rmb:
8849 case VCVTQQ2PDZ256rmbk:
8850 case VCVTQQ2PDZ256rmbkz:
8851 case VCVTQQ2PDZ256rmk:
8852 case VCVTQQ2PDZ256rmkz:
8853 case VCVTQQ2PDZ256rr:
8854 case VCVTQQ2PDZ256rrk:
8855 case VCVTQQ2PDZ256rrkz:
8856 case VCVTQQ2PDZrm:
8857 case VCVTQQ2PDZrmb:
8858 case VCVTQQ2PDZrmbk:
8859 case VCVTQQ2PDZrmbkz:
8860 case VCVTQQ2PDZrmk:
8861 case VCVTQQ2PDZrmkz:
8862 case VCVTQQ2PDZrr:
8863 case VCVTQQ2PDZrrb:
8864 case VCVTQQ2PDZrrbk:
8865 case VCVTQQ2PDZrrbkz:
8866 case VCVTQQ2PDZrrk:
8867 case VCVTQQ2PDZrrkz:
8868 return true;
8869 }
8870 return false;
8871}
8872
8873bool isVFMADD213PH(unsigned Opcode) {
8874 switch (Opcode) {
8875 case VFMADD213PHZ128m:
8876 case VFMADD213PHZ128mb:
8877 case VFMADD213PHZ128mbk:
8878 case VFMADD213PHZ128mbkz:
8879 case VFMADD213PHZ128mk:
8880 case VFMADD213PHZ128mkz:
8881 case VFMADD213PHZ128r:
8882 case VFMADD213PHZ128rk:
8883 case VFMADD213PHZ128rkz:
8884 case VFMADD213PHZ256m:
8885 case VFMADD213PHZ256mb:
8886 case VFMADD213PHZ256mbk:
8887 case VFMADD213PHZ256mbkz:
8888 case VFMADD213PHZ256mk:
8889 case VFMADD213PHZ256mkz:
8890 case VFMADD213PHZ256r:
8891 case VFMADD213PHZ256rk:
8892 case VFMADD213PHZ256rkz:
8893 case VFMADD213PHZm:
8894 case VFMADD213PHZmb:
8895 case VFMADD213PHZmbk:
8896 case VFMADD213PHZmbkz:
8897 case VFMADD213PHZmk:
8898 case VFMADD213PHZmkz:
8899 case VFMADD213PHZr:
8900 case VFMADD213PHZrb:
8901 case VFMADD213PHZrbk:
8902 case VFMADD213PHZrbkz:
8903 case VFMADD213PHZrk:
8904 case VFMADD213PHZrkz:
8905 return true;
8906 }
8907 return false;
8908}
8909
8910bool isFCMOVBE(unsigned Opcode) {
8911 return Opcode == CMOVBE_F;
8912}
8913
8914bool isMOVSHDUP(unsigned Opcode) {
8915 switch (Opcode) {
8916 case MOVSHDUPrm:
8917 case MOVSHDUPrr:
8918 return true;
8919 }
8920 return false;
8921}
8922
8923bool isVPMOVUSQB(unsigned Opcode) {
8924 switch (Opcode) {
8925 case VPMOVUSQBZ128mr:
8926 case VPMOVUSQBZ128mrk:
8927 case VPMOVUSQBZ128rr:
8928 case VPMOVUSQBZ128rrk:
8929 case VPMOVUSQBZ128rrkz:
8930 case VPMOVUSQBZ256mr:
8931 case VPMOVUSQBZ256mrk:
8932 case VPMOVUSQBZ256rr:
8933 case VPMOVUSQBZ256rrk:
8934 case VPMOVUSQBZ256rrkz:
8935 case VPMOVUSQBZmr:
8936 case VPMOVUSQBZmrk:
8937 case VPMOVUSQBZrr:
8938 case VPMOVUSQBZrrk:
8939 case VPMOVUSQBZrrkz:
8940 return true;
8941 }
8942 return false;
8943}
8944
8945bool isFIST(unsigned Opcode) {
8946 switch (Opcode) {
8947 case IST_F16m:
8948 case IST_F32m:
8949 return true;
8950 }
8951 return false;
8952}
8953
8954bool isHADDPD(unsigned Opcode) {
8955 switch (Opcode) {
8956 case HADDPDrm:
8957 case HADDPDrr:
8958 return true;
8959 }
8960 return false;
8961}
8962
8963bool isPACKSSWB(unsigned Opcode) {
8964 switch (Opcode) {
8965 case MMX_PACKSSWBrm:
8966 case MMX_PACKSSWBrr:
8967 case PACKSSWBrm:
8968 case PACKSSWBrr:
8969 return true;
8970 }
8971 return false;
8972}
8973
8974bool isVPMACSSDQH(unsigned Opcode) {
8975 switch (Opcode) {
8976 case VPMACSSDQHrm:
8977 case VPMACSSDQHrr:
8978 return true;
8979 }
8980 return false;
8981}
8982
8983bool isVFNMSUB132SD(unsigned Opcode) {
8984 switch (Opcode) {
8985 case VFNMSUB132SDZm_Int:
8986 case VFNMSUB132SDZmk_Int:
8987 case VFNMSUB132SDZmkz_Int:
8988 case VFNMSUB132SDZr_Int:
8989 case VFNMSUB132SDZrb_Int:
8990 case VFNMSUB132SDZrbk_Int:
8991 case VFNMSUB132SDZrbkz_Int:
8992 case VFNMSUB132SDZrk_Int:
8993 case VFNMSUB132SDZrkz_Int:
8994 case VFNMSUB132SDm_Int:
8995 case VFNMSUB132SDr_Int:
8996 return true;
8997 }
8998 return false;
8999}
9000
9001bool isVPMASKMOVQ(unsigned Opcode) {
9002 switch (Opcode) {
9003 case VPMASKMOVQYmr:
9004 case VPMASKMOVQYrm:
9005 case VPMASKMOVQmr:
9006 case VPMASKMOVQrm:
9007 return true;
9008 }
9009 return false;
9010}
9011
9012bool isVCOMPRESSPD(unsigned Opcode) {
9013 switch (Opcode) {
9014 case VCOMPRESSPDZ128mr:
9015 case VCOMPRESSPDZ128mrk:
9016 case VCOMPRESSPDZ128rr:
9017 case VCOMPRESSPDZ128rrk:
9018 case VCOMPRESSPDZ128rrkz:
9019 case VCOMPRESSPDZ256mr:
9020 case VCOMPRESSPDZ256mrk:
9021 case VCOMPRESSPDZ256rr:
9022 case VCOMPRESSPDZ256rrk:
9023 case VCOMPRESSPDZ256rrkz:
9024 case VCOMPRESSPDZmr:
9025 case VCOMPRESSPDZmrk:
9026 case VCOMPRESSPDZrr:
9027 case VCOMPRESSPDZrrk:
9028 case VCOMPRESSPDZrrkz:
9029 return true;
9030 }
9031 return false;
9032}
9033
9034bool isVFMADD213SS(unsigned Opcode) {
9035 switch (Opcode) {
9036 case VFMADD213SSZm_Int:
9037 case VFMADD213SSZmk_Int:
9038 case VFMADD213SSZmkz_Int:
9039 case VFMADD213SSZr_Int:
9040 case VFMADD213SSZrb_Int:
9041 case VFMADD213SSZrbk_Int:
9042 case VFMADD213SSZrbkz_Int:
9043 case VFMADD213SSZrk_Int:
9044 case VFMADD213SSZrkz_Int:
9045 case VFMADD213SSm_Int:
9046 case VFMADD213SSr_Int:
9047 return true;
9048 }
9049 return false;
9050}
9051
9052bool isVPCMPQ(unsigned Opcode) {
9053 switch (Opcode) {
9054 case VPCMPQZ128rmbi:
9055 case VPCMPQZ128rmbik:
9056 case VPCMPQZ128rmi:
9057 case VPCMPQZ128rmik:
9058 case VPCMPQZ128rri:
9059 case VPCMPQZ128rrik:
9060 case VPCMPQZ256rmbi:
9061 case VPCMPQZ256rmbik:
9062 case VPCMPQZ256rmi:
9063 case VPCMPQZ256rmik:
9064 case VPCMPQZ256rri:
9065 case VPCMPQZ256rrik:
9066 case VPCMPQZrmbi:
9067 case VPCMPQZrmbik:
9068 case VPCMPQZrmi:
9069 case VPCMPQZrmik:
9070 case VPCMPQZrri:
9071 case VPCMPQZrrik:
9072 return true;
9073 }
9074 return false;
9075}
9076
9077bool isVADDSH(unsigned Opcode) {
9078 switch (Opcode) {
9079 case VADDSHZrm_Int:
9080 case VADDSHZrmk_Int:
9081 case VADDSHZrmkz_Int:
9082 case VADDSHZrr_Int:
9083 case VADDSHZrrb_Int:
9084 case VADDSHZrrbk_Int:
9085 case VADDSHZrrbkz_Int:
9086 case VADDSHZrrk_Int:
9087 case VADDSHZrrkz_Int:
9088 return true;
9089 }
9090 return false;
9091}
9092
9093bool isVFNMADDSD(unsigned Opcode) {
9094 switch (Opcode) {
9095 case VFNMADDSD4mr:
9096 case VFNMADDSD4rm:
9097 case VFNMADDSD4rr:
9098 case VFNMADDSD4rr_REV:
9099 return true;
9100 }
9101 return false;
9102}
9103
9104bool isUMWAIT(unsigned Opcode) {
9105 return Opcode == UMWAIT;
9106}
9107
9108bool isVPUNPCKHDQ(unsigned Opcode) {
9109 switch (Opcode) {
9110 case VPUNPCKHDQYrm:
9111 case VPUNPCKHDQYrr:
9112 case VPUNPCKHDQZ128rm:
9113 case VPUNPCKHDQZ128rmb:
9114 case VPUNPCKHDQZ128rmbk:
9115 case VPUNPCKHDQZ128rmbkz:
9116 case VPUNPCKHDQZ128rmk:
9117 case VPUNPCKHDQZ128rmkz:
9118 case VPUNPCKHDQZ128rr:
9119 case VPUNPCKHDQZ128rrk:
9120 case VPUNPCKHDQZ128rrkz:
9121 case VPUNPCKHDQZ256rm:
9122 case VPUNPCKHDQZ256rmb:
9123 case VPUNPCKHDQZ256rmbk:
9124 case VPUNPCKHDQZ256rmbkz:
9125 case VPUNPCKHDQZ256rmk:
9126 case VPUNPCKHDQZ256rmkz:
9127 case VPUNPCKHDQZ256rr:
9128 case VPUNPCKHDQZ256rrk:
9129 case VPUNPCKHDQZ256rrkz:
9130 case VPUNPCKHDQZrm:
9131 case VPUNPCKHDQZrmb:
9132 case VPUNPCKHDQZrmbk:
9133 case VPUNPCKHDQZrmbkz:
9134 case VPUNPCKHDQZrmk:
9135 case VPUNPCKHDQZrmkz:
9136 case VPUNPCKHDQZrr:
9137 case VPUNPCKHDQZrrk:
9138 case VPUNPCKHDQZrrkz:
9139 case VPUNPCKHDQrm:
9140 case VPUNPCKHDQrr:
9141 return true;
9142 }
9143 return false;
9144}
9145
9146bool isLCALL(unsigned Opcode) {
9147 switch (Opcode) {
9148 case FARCALL16i:
9149 case FARCALL16m:
9150 case FARCALL32i:
9151 case FARCALL64m:
9152 return true;
9153 }
9154 return false;
9155}
9156
9157bool isAESDEC128KL(unsigned Opcode) {
9158 return Opcode == AESDEC128KL;
9159}
9160
9161bool isVSUBPS(unsigned Opcode) {
9162 switch (Opcode) {
9163 case VSUBPSYrm:
9164 case VSUBPSYrr:
9165 case VSUBPSZ128rm:
9166 case VSUBPSZ128rmb:
9167 case VSUBPSZ128rmbk:
9168 case VSUBPSZ128rmbkz:
9169 case VSUBPSZ128rmk:
9170 case VSUBPSZ128rmkz:
9171 case VSUBPSZ128rr:
9172 case VSUBPSZ128rrk:
9173 case VSUBPSZ128rrkz:
9174 case VSUBPSZ256rm:
9175 case VSUBPSZ256rmb:
9176 case VSUBPSZ256rmbk:
9177 case VSUBPSZ256rmbkz:
9178 case VSUBPSZ256rmk:
9179 case VSUBPSZ256rmkz:
9180 case VSUBPSZ256rr:
9181 case VSUBPSZ256rrk:
9182 case VSUBPSZ256rrkz:
9183 case VSUBPSZrm:
9184 case VSUBPSZrmb:
9185 case VSUBPSZrmbk:
9186 case VSUBPSZrmbkz:
9187 case VSUBPSZrmk:
9188 case VSUBPSZrmkz:
9189 case VSUBPSZrr:
9190 case VSUBPSZrrb:
9191 case VSUBPSZrrbk:
9192 case VSUBPSZrrbkz:
9193 case VSUBPSZrrk:
9194 case VSUBPSZrrkz:
9195 case VSUBPSrm:
9196 case VSUBPSrr:
9197 return true;
9198 }
9199 return false;
9200}
9201
9202bool isFSTP(unsigned Opcode) {
9203 switch (Opcode) {
9204 case ST_FP32m:
9205 case ST_FP64m:
9206 case ST_FP80m:
9207 case ST_FPrr:
9208 return true;
9209 }
9210 return false;
9211}
9212
9213bool isVCVTUDQ2PD(unsigned Opcode) {
9214 switch (Opcode) {
9215 case VCVTUDQ2PDZ128rm:
9216 case VCVTUDQ2PDZ128rmb:
9217 case VCVTUDQ2PDZ128rmbk:
9218 case VCVTUDQ2PDZ128rmbkz:
9219 case VCVTUDQ2PDZ128rmk:
9220 case VCVTUDQ2PDZ128rmkz:
9221 case VCVTUDQ2PDZ128rr:
9222 case VCVTUDQ2PDZ128rrk:
9223 case VCVTUDQ2PDZ128rrkz:
9224 case VCVTUDQ2PDZ256rm:
9225 case VCVTUDQ2PDZ256rmb:
9226 case VCVTUDQ2PDZ256rmbk:
9227 case VCVTUDQ2PDZ256rmbkz:
9228 case VCVTUDQ2PDZ256rmk:
9229 case VCVTUDQ2PDZ256rmkz:
9230 case VCVTUDQ2PDZ256rr:
9231 case VCVTUDQ2PDZ256rrk:
9232 case VCVTUDQ2PDZ256rrkz:
9233 case VCVTUDQ2PDZrm:
9234 case VCVTUDQ2PDZrmb:
9235 case VCVTUDQ2PDZrmbk:
9236 case VCVTUDQ2PDZrmbkz:
9237 case VCVTUDQ2PDZrmk:
9238 case VCVTUDQ2PDZrmkz:
9239 case VCVTUDQ2PDZrr:
9240 case VCVTUDQ2PDZrrk:
9241 case VCVTUDQ2PDZrrkz:
9242 return true;
9243 }
9244 return false;
9245}
9246
9247bool isVPMOVSWB(unsigned Opcode) {
9248 switch (Opcode) {
9249 case VPMOVSWBZ128mr:
9250 case VPMOVSWBZ128mrk:
9251 case VPMOVSWBZ128rr:
9252 case VPMOVSWBZ128rrk:
9253 case VPMOVSWBZ128rrkz:
9254 case VPMOVSWBZ256mr:
9255 case VPMOVSWBZ256mrk:
9256 case VPMOVSWBZ256rr:
9257 case VPMOVSWBZ256rrk:
9258 case VPMOVSWBZ256rrkz:
9259 case VPMOVSWBZmr:
9260 case VPMOVSWBZmrk:
9261 case VPMOVSWBZrr:
9262 case VPMOVSWBZrrk:
9263 case VPMOVSWBZrrkz:
9264 return true;
9265 }
9266 return false;
9267}
9268
9269bool isVPANDNQ(unsigned Opcode) {
9270 switch (Opcode) {
9271 case VPANDNQZ128rm:
9272 case VPANDNQZ128rmb:
9273 case VPANDNQZ128rmbk:
9274 case VPANDNQZ128rmbkz:
9275 case VPANDNQZ128rmk:
9276 case VPANDNQZ128rmkz:
9277 case VPANDNQZ128rr:
9278 case VPANDNQZ128rrk:
9279 case VPANDNQZ128rrkz:
9280 case VPANDNQZ256rm:
9281 case VPANDNQZ256rmb:
9282 case VPANDNQZ256rmbk:
9283 case VPANDNQZ256rmbkz:
9284 case VPANDNQZ256rmk:
9285 case VPANDNQZ256rmkz:
9286 case VPANDNQZ256rr:
9287 case VPANDNQZ256rrk:
9288 case VPANDNQZ256rrkz:
9289 case VPANDNQZrm:
9290 case VPANDNQZrmb:
9291 case VPANDNQZrmbk:
9292 case VPANDNQZrmbkz:
9293 case VPANDNQZrmk:
9294 case VPANDNQZrmkz:
9295 case VPANDNQZrr:
9296 case VPANDNQZrrk:
9297 case VPANDNQZrrkz:
9298 return true;
9299 }
9300 return false;
9301}
9302
9303bool isSYSENTER(unsigned Opcode) {
9304 return Opcode == SYSENTER;
9305}
9306
9307bool isVPHADDWD(unsigned Opcode) {
9308 switch (Opcode) {
9309 case VPHADDWDrm:
9310 case VPHADDWDrr:
9311 return true;
9312 }
9313 return false;
9314}
9315
9316bool isVMOVHPD(unsigned Opcode) {
9317 switch (Opcode) {
9318 case VMOVHPDZ128mr:
9319 case VMOVHPDZ128rm:
9320 case VMOVHPDmr:
9321 case VMOVHPDrm:
9322 return true;
9323 }
9324 return false;
9325}
9326
9327bool isMOVHPD(unsigned Opcode) {
9328 switch (Opcode) {
9329 case MOVHPDmr:
9330 case MOVHPDrm:
9331 return true;
9332 }
9333 return false;
9334}
9335
9336bool isVDIVPH(unsigned Opcode) {
9337 switch (Opcode) {
9338 case VDIVPHZ128rm:
9339 case VDIVPHZ128rmb:
9340 case VDIVPHZ128rmbk:
9341 case VDIVPHZ128rmbkz:
9342 case VDIVPHZ128rmk:
9343 case VDIVPHZ128rmkz:
9344 case VDIVPHZ128rr:
9345 case VDIVPHZ128rrk:
9346 case VDIVPHZ128rrkz:
9347 case VDIVPHZ256rm:
9348 case VDIVPHZ256rmb:
9349 case VDIVPHZ256rmbk:
9350 case VDIVPHZ256rmbkz:
9351 case VDIVPHZ256rmk:
9352 case VDIVPHZ256rmkz:
9353 case VDIVPHZ256rr:
9354 case VDIVPHZ256rrk:
9355 case VDIVPHZ256rrkz:
9356 case VDIVPHZrm:
9357 case VDIVPHZrmb:
9358 case VDIVPHZrmbk:
9359 case VDIVPHZrmbkz:
9360 case VDIVPHZrmk:
9361 case VDIVPHZrmkz:
9362 case VDIVPHZrr:
9363 case VDIVPHZrrb:
9364 case VDIVPHZrrbk:
9365 case VDIVPHZrrbkz:
9366 case VDIVPHZrrk:
9367 case VDIVPHZrrkz:
9368 return true;
9369 }
9370 return false;
9371}
9372
9373bool isFFREE(unsigned Opcode) {
9374 return Opcode == FFREE;
9375}
9376
9377bool isVGATHERPF1DPS(unsigned Opcode) {
9378 return Opcode == VGATHERPF1DPSm;
9379}
9380
9381bool isVFNMADD231PD(unsigned Opcode) {
9382 switch (Opcode) {
9383 case VFNMADD231PDYm:
9384 case VFNMADD231PDYr:
9385 case VFNMADD231PDZ128m:
9386 case VFNMADD231PDZ128mb:
9387 case VFNMADD231PDZ128mbk:
9388 case VFNMADD231PDZ128mbkz:
9389 case VFNMADD231PDZ128mk:
9390 case VFNMADD231PDZ128mkz:
9391 case VFNMADD231PDZ128r:
9392 case VFNMADD231PDZ128rk:
9393 case VFNMADD231PDZ128rkz:
9394 case VFNMADD231PDZ256m:
9395 case VFNMADD231PDZ256mb:
9396 case VFNMADD231PDZ256mbk:
9397 case VFNMADD231PDZ256mbkz:
9398 case VFNMADD231PDZ256mk:
9399 case VFNMADD231PDZ256mkz:
9400 case VFNMADD231PDZ256r:
9401 case VFNMADD231PDZ256rk:
9402 case VFNMADD231PDZ256rkz:
9403 case VFNMADD231PDZm:
9404 case VFNMADD231PDZmb:
9405 case VFNMADD231PDZmbk:
9406 case VFNMADD231PDZmbkz:
9407 case VFNMADD231PDZmk:
9408 case VFNMADD231PDZmkz:
9409 case VFNMADD231PDZr:
9410 case VFNMADD231PDZrb:
9411 case VFNMADD231PDZrbk:
9412 case VFNMADD231PDZrbkz:
9413 case VFNMADD231PDZrk:
9414 case VFNMADD231PDZrkz:
9415 case VFNMADD231PDm:
9416 case VFNMADD231PDr:
9417 return true;
9418 }
9419 return false;
9420}
9421
9422bool isVFCMULCPH(unsigned Opcode) {
9423 switch (Opcode) {
9424 case VFCMULCPHZ128rm:
9425 case VFCMULCPHZ128rmb:
9426 case VFCMULCPHZ128rmbk:
9427 case VFCMULCPHZ128rmbkz:
9428 case VFCMULCPHZ128rmk:
9429 case VFCMULCPHZ128rmkz:
9430 case VFCMULCPHZ128rr:
9431 case VFCMULCPHZ128rrk:
9432 case VFCMULCPHZ128rrkz:
9433 case VFCMULCPHZ256rm:
9434 case VFCMULCPHZ256rmb:
9435 case VFCMULCPHZ256rmbk:
9436 case VFCMULCPHZ256rmbkz:
9437 case VFCMULCPHZ256rmk:
9438 case VFCMULCPHZ256rmkz:
9439 case VFCMULCPHZ256rr:
9440 case VFCMULCPHZ256rrk:
9441 case VFCMULCPHZ256rrkz:
9442 case VFCMULCPHZrm:
9443 case VFCMULCPHZrmb:
9444 case VFCMULCPHZrmbk:
9445 case VFCMULCPHZrmbkz:
9446 case VFCMULCPHZrmk:
9447 case VFCMULCPHZrmkz:
9448 case VFCMULCPHZrr:
9449 case VFCMULCPHZrrb:
9450 case VFCMULCPHZrrbk:
9451 case VFCMULCPHZrrbkz:
9452 case VFCMULCPHZrrk:
9453 case VFCMULCPHZrrkz:
9454 return true;
9455 }
9456 return false;
9457}
9458
9459bool isVPADDD(unsigned Opcode) {
9460 switch (Opcode) {
9461 case VPADDDYrm:
9462 case VPADDDYrr:
9463 case VPADDDZ128rm:
9464 case VPADDDZ128rmb:
9465 case VPADDDZ128rmbk:
9466 case VPADDDZ128rmbkz:
9467 case VPADDDZ128rmk:
9468 case VPADDDZ128rmkz:
9469 case VPADDDZ128rr:
9470 case VPADDDZ128rrk:
9471 case VPADDDZ128rrkz:
9472 case VPADDDZ256rm:
9473 case VPADDDZ256rmb:
9474 case VPADDDZ256rmbk:
9475 case VPADDDZ256rmbkz:
9476 case VPADDDZ256rmk:
9477 case VPADDDZ256rmkz:
9478 case VPADDDZ256rr:
9479 case VPADDDZ256rrk:
9480 case VPADDDZ256rrkz:
9481 case VPADDDZrm:
9482 case VPADDDZrmb:
9483 case VPADDDZrmbk:
9484 case VPADDDZrmbkz:
9485 case VPADDDZrmk:
9486 case VPADDDZrmkz:
9487 case VPADDDZrr:
9488 case VPADDDZrrk:
9489 case VPADDDZrrkz:
9490 case VPADDDrm:
9491 case VPADDDrr:
9492 return true;
9493 }
9494 return false;
9495}
9496
9497bool isVSM3MSG2(unsigned Opcode) {
9498 switch (Opcode) {
9499 case VSM3MSG2rm:
9500 case VSM3MSG2rr:
9501 return true;
9502 }
9503 return false;
9504}
9505
9506bool isVPCOMUQ(unsigned Opcode) {
9507 switch (Opcode) {
9508 case VPCOMUQmi:
9509 case VPCOMUQri:
9510 return true;
9511 }
9512 return false;
9513}
9514
9515bool isVERR(unsigned Opcode) {
9516 switch (Opcode) {
9517 case VERRm:
9518 case VERRr:
9519 return true;
9520 }
9521 return false;
9522}
9523
9524bool isKORTESTQ(unsigned Opcode) {
9525 return Opcode == KORTESTQkk;
9526}
9527
9528bool isVFMSUB132SD(unsigned Opcode) {
9529 switch (Opcode) {
9530 case VFMSUB132SDZm_Int:
9531 case VFMSUB132SDZmk_Int:
9532 case VFMSUB132SDZmkz_Int:
9533 case VFMSUB132SDZr_Int:
9534 case VFMSUB132SDZrb_Int:
9535 case VFMSUB132SDZrbk_Int:
9536 case VFMSUB132SDZrbkz_Int:
9537 case VFMSUB132SDZrk_Int:
9538 case VFMSUB132SDZrkz_Int:
9539 case VFMSUB132SDm_Int:
9540 case VFMSUB132SDr_Int:
9541 return true;
9542 }
9543 return false;
9544}
9545
9546bool isTILEZERO(unsigned Opcode) {
9547 return Opcode == TILEZERO;
9548}
9549
9550bool isPFADD(unsigned Opcode) {
9551 switch (Opcode) {
9552 case PFADDrm:
9553 case PFADDrr:
9554 return true;
9555 }
9556 return false;
9557}
9558
9559bool isVCVTSI2SD(unsigned Opcode) {
9560 switch (Opcode) {
9561 case VCVTSI2SDZrm_Int:
9562 case VCVTSI2SDZrr_Int:
9563 case VCVTSI2SDrm_Int:
9564 case VCVTSI2SDrr_Int:
9565 case VCVTSI642SDZrm_Int:
9566 case VCVTSI642SDZrr_Int:
9567 case VCVTSI642SDZrrb_Int:
9568 case VCVTSI642SDrm_Int:
9569 case VCVTSI642SDrr_Int:
9570 return true;
9571 }
9572 return false;
9573}
9574
9575bool isTILELOADDRS(unsigned Opcode) {
9576 switch (Opcode) {
9577 case TILELOADDRS:
9578 case TILELOADDRS_EVEX:
9579 return true;
9580 }
9581 return false;
9582}
9583
9584bool isVSTMXCSR(unsigned Opcode) {
9585 return Opcode == VSTMXCSR;
9586}
9587
9588bool isVCVTTSH2SI(unsigned Opcode) {
9589 switch (Opcode) {
9590 case VCVTTSH2SI64Zrm_Int:
9591 case VCVTTSH2SI64Zrr_Int:
9592 case VCVTTSH2SI64Zrrb_Int:
9593 case VCVTTSH2SIZrm_Int:
9594 case VCVTTSH2SIZrr_Int:
9595 case VCVTTSH2SIZrrb_Int:
9596 return true;
9597 }
9598 return false;
9599}
9600
9601bool isRET(unsigned Opcode) {
9602 switch (Opcode) {
9603 case RET16:
9604 case RET32:
9605 case RET64:
9606 case RETI16:
9607 case RETI32:
9608 case RETI64:
9609 return true;
9610 }
9611 return false;
9612}
9613
9614bool isLZCNT(unsigned Opcode) {
9615 switch (Opcode) {
9616 case LZCNT16rm:
9617 case LZCNT16rm_EVEX:
9618 case LZCNT16rm_NF:
9619 case LZCNT16rr:
9620 case LZCNT16rr_EVEX:
9621 case LZCNT16rr_NF:
9622 case LZCNT32rm:
9623 case LZCNT32rm_EVEX:
9624 case LZCNT32rm_NF:
9625 case LZCNT32rr:
9626 case LZCNT32rr_EVEX:
9627 case LZCNT32rr_NF:
9628 case LZCNT64rm:
9629 case LZCNT64rm_EVEX:
9630 case LZCNT64rm_NF:
9631 case LZCNT64rr:
9632 case LZCNT64rr_EVEX:
9633 case LZCNT64rr_NF:
9634 return true;
9635 }
9636 return false;
9637}
9638
9639bool isMULPD(unsigned Opcode) {
9640 switch (Opcode) {
9641 case MULPDrm:
9642 case MULPDrr:
9643 return true;
9644 }
9645 return false;
9646}
9647
9648bool isVBROADCASTI32X2(unsigned Opcode) {
9649 switch (Opcode) {
9650 case VBROADCASTI32X2Z128rm:
9651 case VBROADCASTI32X2Z128rmk:
9652 case VBROADCASTI32X2Z128rmkz:
9653 case VBROADCASTI32X2Z128rr:
9654 case VBROADCASTI32X2Z128rrk:
9655 case VBROADCASTI32X2Z128rrkz:
9656 case VBROADCASTI32X2Z256rm:
9657 case VBROADCASTI32X2Z256rmk:
9658 case VBROADCASTI32X2Z256rmkz:
9659 case VBROADCASTI32X2Z256rr:
9660 case VBROADCASTI32X2Z256rrk:
9661 case VBROADCASTI32X2Z256rrkz:
9662 case VBROADCASTI32X2Zrm:
9663 case VBROADCASTI32X2Zrmk:
9664 case VBROADCASTI32X2Zrmkz:
9665 case VBROADCASTI32X2Zrr:
9666 case VBROADCASTI32X2Zrrk:
9667 case VBROADCASTI32X2Zrrkz:
9668 return true;
9669 }
9670 return false;
9671}
9672
9673bool isVCVTPH2W(unsigned Opcode) {
9674 switch (Opcode) {
9675 case VCVTPH2WZ128rm:
9676 case VCVTPH2WZ128rmb:
9677 case VCVTPH2WZ128rmbk:
9678 case VCVTPH2WZ128rmbkz:
9679 case VCVTPH2WZ128rmk:
9680 case VCVTPH2WZ128rmkz:
9681 case VCVTPH2WZ128rr:
9682 case VCVTPH2WZ128rrk:
9683 case VCVTPH2WZ128rrkz:
9684 case VCVTPH2WZ256rm:
9685 case VCVTPH2WZ256rmb:
9686 case VCVTPH2WZ256rmbk:
9687 case VCVTPH2WZ256rmbkz:
9688 case VCVTPH2WZ256rmk:
9689 case VCVTPH2WZ256rmkz:
9690 case VCVTPH2WZ256rr:
9691 case VCVTPH2WZ256rrk:
9692 case VCVTPH2WZ256rrkz:
9693 case VCVTPH2WZrm:
9694 case VCVTPH2WZrmb:
9695 case VCVTPH2WZrmbk:
9696 case VCVTPH2WZrmbkz:
9697 case VCVTPH2WZrmk:
9698 case VCVTPH2WZrmkz:
9699 case VCVTPH2WZrr:
9700 case VCVTPH2WZrrb:
9701 case VCVTPH2WZrrbk:
9702 case VCVTPH2WZrrbkz:
9703 case VCVTPH2WZrrk:
9704 case VCVTPH2WZrrkz:
9705 return true;
9706 }
9707 return false;
9708}
9709
9710bool isCQO(unsigned Opcode) {
9711 return Opcode == CQO;
9712}
9713
9714bool isFSUBR(unsigned Opcode) {
9715 switch (Opcode) {
9716 case SUBR_F32m:
9717 case SUBR_F64m:
9718 case SUBR_FST0r:
9719 case SUBR_FrST0:
9720 return true;
9721 }
9722 return false;
9723}
9724
9725bool isDPPD(unsigned Opcode) {
9726 switch (Opcode) {
9727 case DPPDrmi:
9728 case DPPDrri:
9729 return true;
9730 }
9731 return false;
9732}
9733
9734bool isFCOS(unsigned Opcode) {
9735 return Opcode == FCOS;
9736}
9737
9738bool isXSAVES(unsigned Opcode) {
9739 return Opcode == XSAVES;
9740}
9741
9742bool isTZCNT(unsigned Opcode) {
9743 switch (Opcode) {
9744 case TZCNT16rm:
9745 case TZCNT16rm_EVEX:
9746 case TZCNT16rm_NF:
9747 case TZCNT16rr:
9748 case TZCNT16rr_EVEX:
9749 case TZCNT16rr_NF:
9750 case TZCNT32rm:
9751 case TZCNT32rm_EVEX:
9752 case TZCNT32rm_NF:
9753 case TZCNT32rr:
9754 case TZCNT32rr_EVEX:
9755 case TZCNT32rr_NF:
9756 case TZCNT64rm:
9757 case TZCNT64rm_EVEX:
9758 case TZCNT64rm_NF:
9759 case TZCNT64rr:
9760 case TZCNT64rr_EVEX:
9761 case TZCNT64rr_NF:
9762 return true;
9763 }
9764 return false;
9765}
9766
9767bool isLJMP(unsigned Opcode) {
9768 switch (Opcode) {
9769 case FARJMP16i:
9770 case FARJMP16m:
9771 case FARJMP32i:
9772 case FARJMP64m:
9773 return true;
9774 }
9775 return false;
9776}
9777
9778bool isCMOVCC(unsigned Opcode) {
9779 switch (Opcode) {
9780 case CMOV16rm:
9781 case CMOV16rm_ND:
9782 case CMOV16rr:
9783 case CMOV16rr_ND:
9784 case CMOV32rm:
9785 case CMOV32rm_ND:
9786 case CMOV32rr:
9787 case CMOV32rr_ND:
9788 case CMOV64rm:
9789 case CMOV64rm_ND:
9790 case CMOV64rr:
9791 case CMOV64rr_ND:
9792 return true;
9793 }
9794 return false;
9795}
9796
9797bool isVCVTBIASPH2HF8(unsigned Opcode) {
9798 switch (Opcode) {
9799 case VCVTBIASPH2HF8Z128rm:
9800 case VCVTBIASPH2HF8Z128rmb:
9801 case VCVTBIASPH2HF8Z128rmbk:
9802 case VCVTBIASPH2HF8Z128rmbkz:
9803 case VCVTBIASPH2HF8Z128rmk:
9804 case VCVTBIASPH2HF8Z128rmkz:
9805 case VCVTBIASPH2HF8Z128rr:
9806 case VCVTBIASPH2HF8Z128rrk:
9807 case VCVTBIASPH2HF8Z128rrkz:
9808 case VCVTBIASPH2HF8Z256rm:
9809 case VCVTBIASPH2HF8Z256rmb:
9810 case VCVTBIASPH2HF8Z256rmbk:
9811 case VCVTBIASPH2HF8Z256rmbkz:
9812 case VCVTBIASPH2HF8Z256rmk:
9813 case VCVTBIASPH2HF8Z256rmkz:
9814 case VCVTBIASPH2HF8Z256rr:
9815 case VCVTBIASPH2HF8Z256rrk:
9816 case VCVTBIASPH2HF8Z256rrkz:
9817 case VCVTBIASPH2HF8Zrm:
9818 case VCVTBIASPH2HF8Zrmb:
9819 case VCVTBIASPH2HF8Zrmbk:
9820 case VCVTBIASPH2HF8Zrmbkz:
9821 case VCVTBIASPH2HF8Zrmk:
9822 case VCVTBIASPH2HF8Zrmkz:
9823 case VCVTBIASPH2HF8Zrr:
9824 case VCVTBIASPH2HF8Zrrk:
9825 case VCVTBIASPH2HF8Zrrkz:
9826 return true;
9827 }
9828 return false;
9829}
9830
9831bool isINVEPT(unsigned Opcode) {
9832 switch (Opcode) {
9833 case INVEPT32:
9834 case INVEPT64:
9835 case INVEPT64_EVEX:
9836 return true;
9837 }
9838 return false;
9839}
9840
9841bool isADDSUBPD(unsigned Opcode) {
9842 switch (Opcode) {
9843 case ADDSUBPDrm:
9844 case ADDSUBPDrr:
9845 return true;
9846 }
9847 return false;
9848}
9849
9850bool isVMOVSHDUP(unsigned Opcode) {
9851 switch (Opcode) {
9852 case VMOVSHDUPYrm:
9853 case VMOVSHDUPYrr:
9854 case VMOVSHDUPZ128rm:
9855 case VMOVSHDUPZ128rmk:
9856 case VMOVSHDUPZ128rmkz:
9857 case VMOVSHDUPZ128rr:
9858 case VMOVSHDUPZ128rrk:
9859 case VMOVSHDUPZ128rrkz:
9860 case VMOVSHDUPZ256rm:
9861 case VMOVSHDUPZ256rmk:
9862 case VMOVSHDUPZ256rmkz:
9863 case VMOVSHDUPZ256rr:
9864 case VMOVSHDUPZ256rrk:
9865 case VMOVSHDUPZ256rrkz:
9866 case VMOVSHDUPZrm:
9867 case VMOVSHDUPZrmk:
9868 case VMOVSHDUPZrmkz:
9869 case VMOVSHDUPZrr:
9870 case VMOVSHDUPZrrk:
9871 case VMOVSHDUPZrrkz:
9872 case VMOVSHDUPrm:
9873 case VMOVSHDUPrr:
9874 return true;
9875 }
9876 return false;
9877}
9878
9879bool isKSHIFTRD(unsigned Opcode) {
9880 return Opcode == KSHIFTRDki;
9881}
9882
9883bool isVCVTSS2SD(unsigned Opcode) {
9884 switch (Opcode) {
9885 case VCVTSS2SDZrm_Int:
9886 case VCVTSS2SDZrmk_Int:
9887 case VCVTSS2SDZrmkz_Int:
9888 case VCVTSS2SDZrr_Int:
9889 case VCVTSS2SDZrrb_Int:
9890 case VCVTSS2SDZrrbk_Int:
9891 case VCVTSS2SDZrrbkz_Int:
9892 case VCVTSS2SDZrrk_Int:
9893 case VCVTSS2SDZrrkz_Int:
9894 case VCVTSS2SDrm_Int:
9895 case VCVTSS2SDrr_Int:
9896 return true;
9897 }
9898 return false;
9899}
9900
9901bool isPADDQ(unsigned Opcode) {
9902 switch (Opcode) {
9903 case MMX_PADDQrm:
9904 case MMX_PADDQrr:
9905 case PADDQrm:
9906 case PADDQrr:
9907 return true;
9908 }
9909 return false;
9910}
9911
9912bool isVEXTRACTI64X4(unsigned Opcode) {
9913 switch (Opcode) {
9914 case VEXTRACTI64X4Zmri:
9915 case VEXTRACTI64X4Zmrik:
9916 case VEXTRACTI64X4Zrri:
9917 case VEXTRACTI64X4Zrrik:
9918 case VEXTRACTI64X4Zrrikz:
9919 return true;
9920 }
9921 return false;
9922}
9923
9924bool isVFMSUB231SS(unsigned Opcode) {
9925 switch (Opcode) {
9926 case VFMSUB231SSZm_Int:
9927 case VFMSUB231SSZmk_Int:
9928 case VFMSUB231SSZmkz_Int:
9929 case VFMSUB231SSZr_Int:
9930 case VFMSUB231SSZrb_Int:
9931 case VFMSUB231SSZrbk_Int:
9932 case VFMSUB231SSZrbkz_Int:
9933 case VFMSUB231SSZrk_Int:
9934 case VFMSUB231SSZrkz_Int:
9935 case VFMSUB231SSm_Int:
9936 case VFMSUB231SSr_Int:
9937 return true;
9938 }
9939 return false;
9940}
9941
9942bool isVPCMPEQB(unsigned Opcode) {
9943 switch (Opcode) {
9944 case VPCMPEQBYrm:
9945 case VPCMPEQBYrr:
9946 case VPCMPEQBZ128rm:
9947 case VPCMPEQBZ128rmk:
9948 case VPCMPEQBZ128rr:
9949 case VPCMPEQBZ128rrk:
9950 case VPCMPEQBZ256rm:
9951 case VPCMPEQBZ256rmk:
9952 case VPCMPEQBZ256rr:
9953 case VPCMPEQBZ256rrk:
9954 case VPCMPEQBZrm:
9955 case VPCMPEQBZrmk:
9956 case VPCMPEQBZrr:
9957 case VPCMPEQBZrrk:
9958 case VPCMPEQBrm:
9959 case VPCMPEQBrr:
9960 return true;
9961 }
9962 return false;
9963}
9964
9965bool isVPTERNLOGD(unsigned Opcode) {
9966 switch (Opcode) {
9967 case VPTERNLOGDZ128rmbi:
9968 case VPTERNLOGDZ128rmbik:
9969 case VPTERNLOGDZ128rmbikz:
9970 case VPTERNLOGDZ128rmi:
9971 case VPTERNLOGDZ128rmik:
9972 case VPTERNLOGDZ128rmikz:
9973 case VPTERNLOGDZ128rri:
9974 case VPTERNLOGDZ128rrik:
9975 case VPTERNLOGDZ128rrikz:
9976 case VPTERNLOGDZ256rmbi:
9977 case VPTERNLOGDZ256rmbik:
9978 case VPTERNLOGDZ256rmbikz:
9979 case VPTERNLOGDZ256rmi:
9980 case VPTERNLOGDZ256rmik:
9981 case VPTERNLOGDZ256rmikz:
9982 case VPTERNLOGDZ256rri:
9983 case VPTERNLOGDZ256rrik:
9984 case VPTERNLOGDZ256rrikz:
9985 case VPTERNLOGDZrmbi:
9986 case VPTERNLOGDZrmbik:
9987 case VPTERNLOGDZrmbikz:
9988 case VPTERNLOGDZrmi:
9989 case VPTERNLOGDZrmik:
9990 case VPTERNLOGDZrmikz:
9991 case VPTERNLOGDZrri:
9992 case VPTERNLOGDZrrik:
9993 case VPTERNLOGDZrrikz:
9994 return true;
9995 }
9996 return false;
9997}
9998
9999bool isLEA(unsigned Opcode) {
10000 switch (Opcode) {
10001 case LEA16r:
10002 case LEA32r:
10003 case LEA64_32r:
10004 case LEA64r:
10005 return true;
10006 }
10007 return false;
10008}
10009
10010bool isPSUBB(unsigned Opcode) {
10011 switch (Opcode) {
10012 case MMX_PSUBBrm:
10013 case MMX_PSUBBrr:
10014 case PSUBBrm:
10015 case PSUBBrr:
10016 return true;
10017 }
10018 return false;
10019}
10020
10021bool isKADDQ(unsigned Opcode) {
10022 return Opcode == KADDQkk;
10023}
10024
10025bool isMOVSX(unsigned Opcode) {
10026 switch (Opcode) {
10027 case MOVSX16rm16:
10028 case MOVSX16rm8:
10029 case MOVSX16rr16:
10030 case MOVSX16rr8:
10031 case MOVSX32rm16:
10032 case MOVSX32rm8:
10033 case MOVSX32rr16:
10034 case MOVSX32rr8:
10035 case MOVSX64rm16:
10036 case MOVSX64rm8:
10037 case MOVSX64rr16:
10038 case MOVSX64rr8:
10039 return true;
10040 }
10041 return false;
10042}
10043
10044bool isVALIGNQ(unsigned Opcode) {
10045 switch (Opcode) {
10046 case VALIGNQZ128rmbi:
10047 case VALIGNQZ128rmbik:
10048 case VALIGNQZ128rmbikz:
10049 case VALIGNQZ128rmi:
10050 case VALIGNQZ128rmik:
10051 case VALIGNQZ128rmikz:
10052 case VALIGNQZ128rri:
10053 case VALIGNQZ128rrik:
10054 case VALIGNQZ128rrikz:
10055 case VALIGNQZ256rmbi:
10056 case VALIGNQZ256rmbik:
10057 case VALIGNQZ256rmbikz:
10058 case VALIGNQZ256rmi:
10059 case VALIGNQZ256rmik:
10060 case VALIGNQZ256rmikz:
10061 case VALIGNQZ256rri:
10062 case VALIGNQZ256rrik:
10063 case VALIGNQZ256rrikz:
10064 case VALIGNQZrmbi:
10065 case VALIGNQZrmbik:
10066 case VALIGNQZrmbikz:
10067 case VALIGNQZrmi:
10068 case VALIGNQZrmik:
10069 case VALIGNQZrmikz:
10070 case VALIGNQZrri:
10071 case VALIGNQZrrik:
10072 case VALIGNQZrrikz:
10073 return true;
10074 }
10075 return false;
10076}
10077
10078bool isVCVTNE2PS2BF16(unsigned Opcode) {
10079 switch (Opcode) {
10080 case VCVTNE2PS2BF16Z128rm:
10081 case VCVTNE2PS2BF16Z128rmb:
10082 case VCVTNE2PS2BF16Z128rmbk:
10083 case VCVTNE2PS2BF16Z128rmbkz:
10084 case VCVTNE2PS2BF16Z128rmk:
10085 case VCVTNE2PS2BF16Z128rmkz:
10086 case VCVTNE2PS2BF16Z128rr:
10087 case VCVTNE2PS2BF16Z128rrk:
10088 case VCVTNE2PS2BF16Z128rrkz:
10089 case VCVTNE2PS2BF16Z256rm:
10090 case VCVTNE2PS2BF16Z256rmb:
10091 case VCVTNE2PS2BF16Z256rmbk:
10092 case VCVTNE2PS2BF16Z256rmbkz:
10093 case VCVTNE2PS2BF16Z256rmk:
10094 case VCVTNE2PS2BF16Z256rmkz:
10095 case VCVTNE2PS2BF16Z256rr:
10096 case VCVTNE2PS2BF16Z256rrk:
10097 case VCVTNE2PS2BF16Z256rrkz:
10098 case VCVTNE2PS2BF16Zrm:
10099 case VCVTNE2PS2BF16Zrmb:
10100 case VCVTNE2PS2BF16Zrmbk:
10101 case VCVTNE2PS2BF16Zrmbkz:
10102 case VCVTNE2PS2BF16Zrmk:
10103 case VCVTNE2PS2BF16Zrmkz:
10104 case VCVTNE2PS2BF16Zrr:
10105 case VCVTNE2PS2BF16Zrrk:
10106 case VCVTNE2PS2BF16Zrrkz:
10107 return true;
10108 }
10109 return false;
10110}
10111
10112bool isVPSRAW(unsigned Opcode) {
10113 switch (Opcode) {
10114 case VPSRAWYri:
10115 case VPSRAWYrm:
10116 case VPSRAWYrr:
10117 case VPSRAWZ128mi:
10118 case VPSRAWZ128mik:
10119 case VPSRAWZ128mikz:
10120 case VPSRAWZ128ri:
10121 case VPSRAWZ128rik:
10122 case VPSRAWZ128rikz:
10123 case VPSRAWZ128rm:
10124 case VPSRAWZ128rmk:
10125 case VPSRAWZ128rmkz:
10126 case VPSRAWZ128rr:
10127 case VPSRAWZ128rrk:
10128 case VPSRAWZ128rrkz:
10129 case VPSRAWZ256mi:
10130 case VPSRAWZ256mik:
10131 case VPSRAWZ256mikz:
10132 case VPSRAWZ256ri:
10133 case VPSRAWZ256rik:
10134 case VPSRAWZ256rikz:
10135 case VPSRAWZ256rm:
10136 case VPSRAWZ256rmk:
10137 case VPSRAWZ256rmkz:
10138 case VPSRAWZ256rr:
10139 case VPSRAWZ256rrk:
10140 case VPSRAWZ256rrkz:
10141 case VPSRAWZmi:
10142 case VPSRAWZmik:
10143 case VPSRAWZmikz:
10144 case VPSRAWZri:
10145 case VPSRAWZrik:
10146 case VPSRAWZrikz:
10147 case VPSRAWZrm:
10148 case VPSRAWZrmk:
10149 case VPSRAWZrmkz:
10150 case VPSRAWZrr:
10151 case VPSRAWZrrk:
10152 case VPSRAWZrrkz:
10153 case VPSRAWri:
10154 case VPSRAWrm:
10155 case VPSRAWrr:
10156 return true;
10157 }
10158 return false;
10159}
10160
10161bool isVFMSUBADD231PH(unsigned Opcode) {
10162 switch (Opcode) {
10163 case VFMSUBADD231PHZ128m:
10164 case VFMSUBADD231PHZ128mb:
10165 case VFMSUBADD231PHZ128mbk:
10166 case VFMSUBADD231PHZ128mbkz:
10167 case VFMSUBADD231PHZ128mk:
10168 case VFMSUBADD231PHZ128mkz:
10169 case VFMSUBADD231PHZ128r:
10170 case VFMSUBADD231PHZ128rk:
10171 case VFMSUBADD231PHZ128rkz:
10172 case VFMSUBADD231PHZ256m:
10173 case VFMSUBADD231PHZ256mb:
10174 case VFMSUBADD231PHZ256mbk:
10175 case VFMSUBADD231PHZ256mbkz:
10176 case VFMSUBADD231PHZ256mk:
10177 case VFMSUBADD231PHZ256mkz:
10178 case VFMSUBADD231PHZ256r:
10179 case VFMSUBADD231PHZ256rk:
10180 case VFMSUBADD231PHZ256rkz:
10181 case VFMSUBADD231PHZm:
10182 case VFMSUBADD231PHZmb:
10183 case VFMSUBADD231PHZmbk:
10184 case VFMSUBADD231PHZmbkz:
10185 case VFMSUBADD231PHZmk:
10186 case VFMSUBADD231PHZmkz:
10187 case VFMSUBADD231PHZr:
10188 case VFMSUBADD231PHZrb:
10189 case VFMSUBADD231PHZrbk:
10190 case VFMSUBADD231PHZrbkz:
10191 case VFMSUBADD231PHZrk:
10192 case VFMSUBADD231PHZrkz:
10193 return true;
10194 }
10195 return false;
10196}
10197
10198bool isCVTDQ2PS(unsigned Opcode) {
10199 switch (Opcode) {
10200 case CVTDQ2PSrm:
10201 case CVTDQ2PSrr:
10202 return true;
10203 }
10204 return false;
10205}
10206
10207bool isFBLD(unsigned Opcode) {
10208 return Opcode == FBLDm;
10209}
10210
10211bool isLMSW(unsigned Opcode) {
10212 switch (Opcode) {
10213 case LMSW16m:
10214 case LMSW16r:
10215 return true;
10216 }
10217 return false;
10218}
10219
10220bool isWRMSR(unsigned Opcode) {
10221 return Opcode == WRMSR;
10222}
10223
10224bool isMINSS(unsigned Opcode) {
10225 switch (Opcode) {
10226 case MINSSrm_Int:
10227 case MINSSrr_Int:
10228 return true;
10229 }
10230 return false;
10231}
10232
10233bool isFSCALE(unsigned Opcode) {
10234 return Opcode == FSCALE;
10235}
10236
10237bool isVFNMADD213SH(unsigned Opcode) {
10238 switch (Opcode) {
10239 case VFNMADD213SHZm_Int:
10240 case VFNMADD213SHZmk_Int:
10241 case VFNMADD213SHZmkz_Int:
10242 case VFNMADD213SHZr_Int:
10243 case VFNMADD213SHZrb_Int:
10244 case VFNMADD213SHZrbk_Int:
10245 case VFNMADD213SHZrbkz_Int:
10246 case VFNMADD213SHZrk_Int:
10247 case VFNMADD213SHZrkz_Int:
10248 return true;
10249 }
10250 return false;
10251}
10252
10253bool isIMULZU(unsigned Opcode) {
10254 switch (Opcode) {
10255 case IMULZU16rmi:
10256 case IMULZU16rmi8:
10257 case IMULZU16rri:
10258 case IMULZU16rri8:
10259 case IMULZU32rmi:
10260 case IMULZU32rmi8:
10261 case IMULZU32rri:
10262 case IMULZU32rri8:
10263 case IMULZU64rmi32:
10264 case IMULZU64rmi8:
10265 case IMULZU64rri32:
10266 case IMULZU64rri8:
10267 return true;
10268 }
10269 return false;
10270}
10271
10272bool isVPHADDUBD(unsigned Opcode) {
10273 switch (Opcode) {
10274 case VPHADDUBDrm:
10275 case VPHADDUBDrr:
10276 return true;
10277 }
10278 return false;
10279}
10280
10281bool isRDSSPQ(unsigned Opcode) {
10282 return Opcode == RDSSPQ;
10283}
10284
10285bool isVCVTBF162IBS(unsigned Opcode) {
10286 switch (Opcode) {
10287 case VCVTBF162IBSZ128rm:
10288 case VCVTBF162IBSZ128rmb:
10289 case VCVTBF162IBSZ128rmbk:
10290 case VCVTBF162IBSZ128rmbkz:
10291 case VCVTBF162IBSZ128rmk:
10292 case VCVTBF162IBSZ128rmkz:
10293 case VCVTBF162IBSZ128rr:
10294 case VCVTBF162IBSZ128rrk:
10295 case VCVTBF162IBSZ128rrkz:
10296 case VCVTBF162IBSZ256rm:
10297 case VCVTBF162IBSZ256rmb:
10298 case VCVTBF162IBSZ256rmbk:
10299 case VCVTBF162IBSZ256rmbkz:
10300 case VCVTBF162IBSZ256rmk:
10301 case VCVTBF162IBSZ256rmkz:
10302 case VCVTBF162IBSZ256rr:
10303 case VCVTBF162IBSZ256rrk:
10304 case VCVTBF162IBSZ256rrkz:
10305 case VCVTBF162IBSZrm:
10306 case VCVTBF162IBSZrmb:
10307 case VCVTBF162IBSZrmbk:
10308 case VCVTBF162IBSZrmbkz:
10309 case VCVTBF162IBSZrmk:
10310 case VCVTBF162IBSZrmkz:
10311 case VCVTBF162IBSZrr:
10312 case VCVTBF162IBSZrrk:
10313 case VCVTBF162IBSZrrkz:
10314 return true;
10315 }
10316 return false;
10317}
10318
10319bool isLGDT(unsigned Opcode) {
10320 return Opcode == LGDT64m;
10321}
10322
10323bool isVPSHLDVD(unsigned Opcode) {
10324 switch (Opcode) {
10325 case VPSHLDVDZ128m:
10326 case VPSHLDVDZ128mb:
10327 case VPSHLDVDZ128mbk:
10328 case VPSHLDVDZ128mbkz:
10329 case VPSHLDVDZ128mk:
10330 case VPSHLDVDZ128mkz:
10331 case VPSHLDVDZ128r:
10332 case VPSHLDVDZ128rk:
10333 case VPSHLDVDZ128rkz:
10334 case VPSHLDVDZ256m:
10335 case VPSHLDVDZ256mb:
10336 case VPSHLDVDZ256mbk:
10337 case VPSHLDVDZ256mbkz:
10338 case VPSHLDVDZ256mk:
10339 case VPSHLDVDZ256mkz:
10340 case VPSHLDVDZ256r:
10341 case VPSHLDVDZ256rk:
10342 case VPSHLDVDZ256rkz:
10343 case VPSHLDVDZm:
10344 case VPSHLDVDZmb:
10345 case VPSHLDVDZmbk:
10346 case VPSHLDVDZmbkz:
10347 case VPSHLDVDZmk:
10348 case VPSHLDVDZmkz:
10349 case VPSHLDVDZr:
10350 case VPSHLDVDZrk:
10351 case VPSHLDVDZrkz:
10352 return true;
10353 }
10354 return false;
10355}
10356
10357bool isPFCMPGT(unsigned Opcode) {
10358 switch (Opcode) {
10359 case PFCMPGTrm:
10360 case PFCMPGTrr:
10361 return true;
10362 }
10363 return false;
10364}
10365
10366bool isVRNDSCALEPH(unsigned Opcode) {
10367 switch (Opcode) {
10368 case VRNDSCALEPHZ128rmbi:
10369 case VRNDSCALEPHZ128rmbik:
10370 case VRNDSCALEPHZ128rmbikz:
10371 case VRNDSCALEPHZ128rmi:
10372 case VRNDSCALEPHZ128rmik:
10373 case VRNDSCALEPHZ128rmikz:
10374 case VRNDSCALEPHZ128rri:
10375 case VRNDSCALEPHZ128rrik:
10376 case VRNDSCALEPHZ128rrikz:
10377 case VRNDSCALEPHZ256rmbi:
10378 case VRNDSCALEPHZ256rmbik:
10379 case VRNDSCALEPHZ256rmbikz:
10380 case VRNDSCALEPHZ256rmi:
10381 case VRNDSCALEPHZ256rmik:
10382 case VRNDSCALEPHZ256rmikz:
10383 case VRNDSCALEPHZ256rri:
10384 case VRNDSCALEPHZ256rrik:
10385 case VRNDSCALEPHZ256rrikz:
10386 case VRNDSCALEPHZrmbi:
10387 case VRNDSCALEPHZrmbik:
10388 case VRNDSCALEPHZrmbikz:
10389 case VRNDSCALEPHZrmi:
10390 case VRNDSCALEPHZrmik:
10391 case VRNDSCALEPHZrmikz:
10392 case VRNDSCALEPHZrri:
10393 case VRNDSCALEPHZrrib:
10394 case VRNDSCALEPHZrribk:
10395 case VRNDSCALEPHZrribkz:
10396 case VRNDSCALEPHZrrik:
10397 case VRNDSCALEPHZrrikz:
10398 return true;
10399 }
10400 return false;
10401}
10402
10403bool isJCXZ(unsigned Opcode) {
10404 return Opcode == JCXZ;
10405}
10406
10407bool isVPMOVZXBW(unsigned Opcode) {
10408 switch (Opcode) {
10409 case VPMOVZXBWYrm:
10410 case VPMOVZXBWYrr:
10411 case VPMOVZXBWZ128rm:
10412 case VPMOVZXBWZ128rmk:
10413 case VPMOVZXBWZ128rmkz:
10414 case VPMOVZXBWZ128rr:
10415 case VPMOVZXBWZ128rrk:
10416 case VPMOVZXBWZ128rrkz:
10417 case VPMOVZXBWZ256rm:
10418 case VPMOVZXBWZ256rmk:
10419 case VPMOVZXBWZ256rmkz:
10420 case VPMOVZXBWZ256rr:
10421 case VPMOVZXBWZ256rrk:
10422 case VPMOVZXBWZ256rrkz:
10423 case VPMOVZXBWZrm:
10424 case VPMOVZXBWZrmk:
10425 case VPMOVZXBWZrmkz:
10426 case VPMOVZXBWZrr:
10427 case VPMOVZXBWZrrk:
10428 case VPMOVZXBWZrrkz:
10429 case VPMOVZXBWrm:
10430 case VPMOVZXBWrr:
10431 return true;
10432 }
10433 return false;
10434}
10435
10436bool isVFMADDSUB231PD(unsigned Opcode) {
10437 switch (Opcode) {
10438 case VFMADDSUB231PDYm:
10439 case VFMADDSUB231PDYr:
10440 case VFMADDSUB231PDZ128m:
10441 case VFMADDSUB231PDZ128mb:
10442 case VFMADDSUB231PDZ128mbk:
10443 case VFMADDSUB231PDZ128mbkz:
10444 case VFMADDSUB231PDZ128mk:
10445 case VFMADDSUB231PDZ128mkz:
10446 case VFMADDSUB231PDZ128r:
10447 case VFMADDSUB231PDZ128rk:
10448 case VFMADDSUB231PDZ128rkz:
10449 case VFMADDSUB231PDZ256m:
10450 case VFMADDSUB231PDZ256mb:
10451 case VFMADDSUB231PDZ256mbk:
10452 case VFMADDSUB231PDZ256mbkz:
10453 case VFMADDSUB231PDZ256mk:
10454 case VFMADDSUB231PDZ256mkz:
10455 case VFMADDSUB231PDZ256r:
10456 case VFMADDSUB231PDZ256rk:
10457 case VFMADDSUB231PDZ256rkz:
10458 case VFMADDSUB231PDZm:
10459 case VFMADDSUB231PDZmb:
10460 case VFMADDSUB231PDZmbk:
10461 case VFMADDSUB231PDZmbkz:
10462 case VFMADDSUB231PDZmk:
10463 case VFMADDSUB231PDZmkz:
10464 case VFMADDSUB231PDZr:
10465 case VFMADDSUB231PDZrb:
10466 case VFMADDSUB231PDZrbk:
10467 case VFMADDSUB231PDZrbkz:
10468 case VFMADDSUB231PDZrk:
10469 case VFMADDSUB231PDZrkz:
10470 case VFMADDSUB231PDm:
10471 case VFMADDSUB231PDr:
10472 return true;
10473 }
10474 return false;
10475}
10476
10477bool isVBLENDMPD(unsigned Opcode) {
10478 switch (Opcode) {
10479 case VBLENDMPDZ128rm:
10480 case VBLENDMPDZ128rmb:
10481 case VBLENDMPDZ128rmbk:
10482 case VBLENDMPDZ128rmbkz:
10483 case VBLENDMPDZ128rmk:
10484 case VBLENDMPDZ128rmkz:
10485 case VBLENDMPDZ128rr:
10486 case VBLENDMPDZ128rrk:
10487 case VBLENDMPDZ128rrkz:
10488 case VBLENDMPDZ256rm:
10489 case VBLENDMPDZ256rmb:
10490 case VBLENDMPDZ256rmbk:
10491 case VBLENDMPDZ256rmbkz:
10492 case VBLENDMPDZ256rmk:
10493 case VBLENDMPDZ256rmkz:
10494 case VBLENDMPDZ256rr:
10495 case VBLENDMPDZ256rrk:
10496 case VBLENDMPDZ256rrkz:
10497 case VBLENDMPDZrm:
10498 case VBLENDMPDZrmb:
10499 case VBLENDMPDZrmbk:
10500 case VBLENDMPDZrmbkz:
10501 case VBLENDMPDZrmk:
10502 case VBLENDMPDZrmkz:
10503 case VBLENDMPDZrr:
10504 case VBLENDMPDZrrk:
10505 case VBLENDMPDZrrkz:
10506 return true;
10507 }
10508 return false;
10509}
10510
10511bool isHSUBPS(unsigned Opcode) {
10512 switch (Opcode) {
10513 case HSUBPSrm:
10514 case HSUBPSrr:
10515 return true;
10516 }
10517 return false;
10518}
10519
10520bool isPREFETCHIT0(unsigned Opcode) {
10521 return Opcode == PREFETCHIT0;
10522}
10523
10524bool isKTESTD(unsigned Opcode) {
10525 return Opcode == KTESTDkk;
10526}
10527
10528bool isVCVTNEOPH2PS(unsigned Opcode) {
10529 switch (Opcode) {
10530 case VCVTNEOPH2PSYrm:
10531 case VCVTNEOPH2PSrm:
10532 return true;
10533 }
10534 return false;
10535}
10536
10537bool isVBLENDVPD(unsigned Opcode) {
10538 switch (Opcode) {
10539 case VBLENDVPDYrmr:
10540 case VBLENDVPDYrrr:
10541 case VBLENDVPDrmr:
10542 case VBLENDVPDrrr:
10543 return true;
10544 }
10545 return false;
10546}
10547
10548bool isVCVTSS2USI(unsigned Opcode) {
10549 switch (Opcode) {
10550 case VCVTSS2USI64Zrm_Int:
10551 case VCVTSS2USI64Zrr_Int:
10552 case VCVTSS2USI64Zrrb_Int:
10553 case VCVTSS2USIZrm_Int:
10554 case VCVTSS2USIZrr_Int:
10555 case VCVTSS2USIZrrb_Int:
10556 return true;
10557 }
10558 return false;
10559}
10560
10561bool isVCVTTPS2DQS(unsigned Opcode) {
10562 switch (Opcode) {
10563 case VCVTTPS2DQSZ128rm:
10564 case VCVTTPS2DQSZ128rmb:
10565 case VCVTTPS2DQSZ128rmbk:
10566 case VCVTTPS2DQSZ128rmbkz:
10567 case VCVTTPS2DQSZ128rmk:
10568 case VCVTTPS2DQSZ128rmkz:
10569 case VCVTTPS2DQSZ128rr:
10570 case VCVTTPS2DQSZ128rrk:
10571 case VCVTTPS2DQSZ128rrkz:
10572 case VCVTTPS2DQSZ256rm:
10573 case VCVTTPS2DQSZ256rmb:
10574 case VCVTTPS2DQSZ256rmbk:
10575 case VCVTTPS2DQSZ256rmbkz:
10576 case VCVTTPS2DQSZ256rmk:
10577 case VCVTTPS2DQSZ256rmkz:
10578 case VCVTTPS2DQSZ256rr:
10579 case VCVTTPS2DQSZ256rrk:
10580 case VCVTTPS2DQSZ256rrkz:
10581 case VCVTTPS2DQSZrm:
10582 case VCVTTPS2DQSZrmb:
10583 case VCVTTPS2DQSZrmbk:
10584 case VCVTTPS2DQSZrmbkz:
10585 case VCVTTPS2DQSZrmk:
10586 case VCVTTPS2DQSZrmkz:
10587 case VCVTTPS2DQSZrr:
10588 case VCVTTPS2DQSZrrb:
10589 case VCVTTPS2DQSZrrbk:
10590 case VCVTTPS2DQSZrrbkz:
10591 case VCVTTPS2DQSZrrk:
10592 case VCVTTPS2DQSZrrkz:
10593 return true;
10594 }
10595 return false;
10596}
10597
10598bool isVPANDD(unsigned Opcode) {
10599 switch (Opcode) {
10600 case VPANDDZ128rm:
10601 case VPANDDZ128rmb:
10602 case VPANDDZ128rmbk:
10603 case VPANDDZ128rmbkz:
10604 case VPANDDZ128rmk:
10605 case VPANDDZ128rmkz:
10606 case VPANDDZ128rr:
10607 case VPANDDZ128rrk:
10608 case VPANDDZ128rrkz:
10609 case VPANDDZ256rm:
10610 case VPANDDZ256rmb:
10611 case VPANDDZ256rmbk:
10612 case VPANDDZ256rmbkz:
10613 case VPANDDZ256rmk:
10614 case VPANDDZ256rmkz:
10615 case VPANDDZ256rr:
10616 case VPANDDZ256rrk:
10617 case VPANDDZ256rrkz:
10618 case VPANDDZrm:
10619 case VPANDDZrmb:
10620 case VPANDDZrmbk:
10621 case VPANDDZrmbkz:
10622 case VPANDDZrmk:
10623 case VPANDDZrmkz:
10624 case VPANDDZrr:
10625 case VPANDDZrrk:
10626 case VPANDDZrrkz:
10627 return true;
10628 }
10629 return false;
10630}
10631
10632bool isPMINSW(unsigned Opcode) {
10633 switch (Opcode) {
10634 case MMX_PMINSWrm:
10635 case MMX_PMINSWrr:
10636 case PMINSWrm:
10637 case PMINSWrr:
10638 return true;
10639 }
10640 return false;
10641}
10642
10643bool isSTAC(unsigned Opcode) {
10644 return Opcode == STAC;
10645}
10646
10647bool isVFMSUB213PS(unsigned Opcode) {
10648 switch (Opcode) {
10649 case VFMSUB213PSYm:
10650 case VFMSUB213PSYr:
10651 case VFMSUB213PSZ128m:
10652 case VFMSUB213PSZ128mb:
10653 case VFMSUB213PSZ128mbk:
10654 case VFMSUB213PSZ128mbkz:
10655 case VFMSUB213PSZ128mk:
10656 case VFMSUB213PSZ128mkz:
10657 case VFMSUB213PSZ128r:
10658 case VFMSUB213PSZ128rk:
10659 case VFMSUB213PSZ128rkz:
10660 case VFMSUB213PSZ256m:
10661 case VFMSUB213PSZ256mb:
10662 case VFMSUB213PSZ256mbk:
10663 case VFMSUB213PSZ256mbkz:
10664 case VFMSUB213PSZ256mk:
10665 case VFMSUB213PSZ256mkz:
10666 case VFMSUB213PSZ256r:
10667 case VFMSUB213PSZ256rk:
10668 case VFMSUB213PSZ256rkz:
10669 case VFMSUB213PSZm:
10670 case VFMSUB213PSZmb:
10671 case VFMSUB213PSZmbk:
10672 case VFMSUB213PSZmbkz:
10673 case VFMSUB213PSZmk:
10674 case VFMSUB213PSZmkz:
10675 case VFMSUB213PSZr:
10676 case VFMSUB213PSZrb:
10677 case VFMSUB213PSZrbk:
10678 case VFMSUB213PSZrbkz:
10679 case VFMSUB213PSZrk:
10680 case VFMSUB213PSZrkz:
10681 case VFMSUB213PSm:
10682 case VFMSUB213PSr:
10683 return true;
10684 }
10685 return false;
10686}
10687
10688bool isPOPAL(unsigned Opcode) {
10689 return Opcode == POPA32;
10690}
10691
10692bool isVCVTPS2UQQ(unsigned Opcode) {
10693 switch (Opcode) {
10694 case VCVTPS2UQQZ128rm:
10695 case VCVTPS2UQQZ128rmb:
10696 case VCVTPS2UQQZ128rmbk:
10697 case VCVTPS2UQQZ128rmbkz:
10698 case VCVTPS2UQQZ128rmk:
10699 case VCVTPS2UQQZ128rmkz:
10700 case VCVTPS2UQQZ128rr:
10701 case VCVTPS2UQQZ128rrk:
10702 case VCVTPS2UQQZ128rrkz:
10703 case VCVTPS2UQQZ256rm:
10704 case VCVTPS2UQQZ256rmb:
10705 case VCVTPS2UQQZ256rmbk:
10706 case VCVTPS2UQQZ256rmbkz:
10707 case VCVTPS2UQQZ256rmk:
10708 case VCVTPS2UQQZ256rmkz:
10709 case VCVTPS2UQQZ256rr:
10710 case VCVTPS2UQQZ256rrk:
10711 case VCVTPS2UQQZ256rrkz:
10712 case VCVTPS2UQQZrm:
10713 case VCVTPS2UQQZrmb:
10714 case VCVTPS2UQQZrmbk:
10715 case VCVTPS2UQQZrmbkz:
10716 case VCVTPS2UQQZrmk:
10717 case VCVTPS2UQQZrmkz:
10718 case VCVTPS2UQQZrr:
10719 case VCVTPS2UQQZrrb:
10720 case VCVTPS2UQQZrrbk:
10721 case VCVTPS2UQQZrrbkz:
10722 case VCVTPS2UQQZrrk:
10723 case VCVTPS2UQQZrrkz:
10724 return true;
10725 }
10726 return false;
10727}
10728
10729bool isRDRAND(unsigned Opcode) {
10730 switch (Opcode) {
10731 case RDRAND16r:
10732 case RDRAND32r:
10733 case RDRAND64r:
10734 return true;
10735 }
10736 return false;
10737}
10738
10739bool isJCC(unsigned Opcode) {
10740 switch (Opcode) {
10741 case JCC_1:
10742 case JCC_2:
10743 case JCC_4:
10744 return true;
10745 }
10746 return false;
10747}
10748
10749bool isVPMINSQ(unsigned Opcode) {
10750 switch (Opcode) {
10751 case VPMINSQZ128rm:
10752 case VPMINSQZ128rmb:
10753 case VPMINSQZ128rmbk:
10754 case VPMINSQZ128rmbkz:
10755 case VPMINSQZ128rmk:
10756 case VPMINSQZ128rmkz:
10757 case VPMINSQZ128rr:
10758 case VPMINSQZ128rrk:
10759 case VPMINSQZ128rrkz:
10760 case VPMINSQZ256rm:
10761 case VPMINSQZ256rmb:
10762 case VPMINSQZ256rmbk:
10763 case VPMINSQZ256rmbkz:
10764 case VPMINSQZ256rmk:
10765 case VPMINSQZ256rmkz:
10766 case VPMINSQZ256rr:
10767 case VPMINSQZ256rrk:
10768 case VPMINSQZ256rrkz:
10769 case VPMINSQZrm:
10770 case VPMINSQZrmb:
10771 case VPMINSQZrmbk:
10772 case VPMINSQZrmbkz:
10773 case VPMINSQZrmk:
10774 case VPMINSQZrmkz:
10775 case VPMINSQZrr:
10776 case VPMINSQZrrk:
10777 case VPMINSQZrrkz:
10778 return true;
10779 }
10780 return false;
10781}
10782
10783bool isVADDSD(unsigned Opcode) {
10784 switch (Opcode) {
10785 case VADDSDZrm_Int:
10786 case VADDSDZrmk_Int:
10787 case VADDSDZrmkz_Int:
10788 case VADDSDZrr_Int:
10789 case VADDSDZrrb_Int:
10790 case VADDSDZrrbk_Int:
10791 case VADDSDZrrbkz_Int:
10792 case VADDSDZrrk_Int:
10793 case VADDSDZrrkz_Int:
10794 case VADDSDrm_Int:
10795 case VADDSDrr_Int:
10796 return true;
10797 }
10798 return false;
10799}
10800
10801bool isDPPS(unsigned Opcode) {
10802 switch (Opcode) {
10803 case DPPSrmi:
10804 case DPPSrri:
10805 return true;
10806 }
10807 return false;
10808}
10809
10810bool isPINSRQ(unsigned Opcode) {
10811 switch (Opcode) {
10812 case PINSRQrmi:
10813 case PINSRQrri:
10814 return true;
10815 }
10816 return false;
10817}
10818
10819bool isVUCOMISS(unsigned Opcode) {
10820 switch (Opcode) {
10821 case VUCOMISSZrm:
10822 case VUCOMISSZrr:
10823 case VUCOMISSZrrb:
10824 case VUCOMISSrm:
10825 case VUCOMISSrr:
10826 return true;
10827 }
10828 return false;
10829}
10830
10831bool isVPDPWSUD(unsigned Opcode) {
10832 switch (Opcode) {
10833 case VPDPWSUDYrm:
10834 case VPDPWSUDYrr:
10835 case VPDPWSUDZ128m:
10836 case VPDPWSUDZ128mb:
10837 case VPDPWSUDZ128mbk:
10838 case VPDPWSUDZ128mbkz:
10839 case VPDPWSUDZ128mk:
10840 case VPDPWSUDZ128mkz:
10841 case VPDPWSUDZ128r:
10842 case VPDPWSUDZ128rk:
10843 case VPDPWSUDZ128rkz:
10844 case VPDPWSUDZ256m:
10845 case VPDPWSUDZ256mb:
10846 case VPDPWSUDZ256mbk:
10847 case VPDPWSUDZ256mbkz:
10848 case VPDPWSUDZ256mk:
10849 case VPDPWSUDZ256mkz:
10850 case VPDPWSUDZ256r:
10851 case VPDPWSUDZ256rk:
10852 case VPDPWSUDZ256rkz:
10853 case VPDPWSUDZm:
10854 case VPDPWSUDZmb:
10855 case VPDPWSUDZmbk:
10856 case VPDPWSUDZmbkz:
10857 case VPDPWSUDZmk:
10858 case VPDPWSUDZmkz:
10859 case VPDPWSUDZr:
10860 case VPDPWSUDZrk:
10861 case VPDPWSUDZrkz:
10862 case VPDPWSUDrm:
10863 case VPDPWSUDrr:
10864 return true;
10865 }
10866 return false;
10867}
10868
10869bool isKANDNW(unsigned Opcode) {
10870 return Opcode == KANDNWkk;
10871}
10872
10873bool isAOR(unsigned Opcode) {
10874 switch (Opcode) {
10875 case AOR32mr:
10876 case AOR32mr_EVEX:
10877 case AOR64mr:
10878 case AOR64mr_EVEX:
10879 return true;
10880 }
10881 return false;
10882}
10883
10884bool isPMAXUB(unsigned Opcode) {
10885 switch (Opcode) {
10886 case MMX_PMAXUBrm:
10887 case MMX_PMAXUBrr:
10888 case PMAXUBrm:
10889 case PMAXUBrr:
10890 return true;
10891 }
10892 return false;
10893}
10894
10895bool isANDNPD(unsigned Opcode) {
10896 switch (Opcode) {
10897 case ANDNPDrm:
10898 case ANDNPDrr:
10899 return true;
10900 }
10901 return false;
10902}
10903
10904bool isINVPCID(unsigned Opcode) {
10905 switch (Opcode) {
10906 case INVPCID32:
10907 case INVPCID64:
10908 case INVPCID64_EVEX:
10909 return true;
10910 }
10911 return false;
10912}
10913
10914bool isRDGSBASE(unsigned Opcode) {
10915 switch (Opcode) {
10916 case RDGSBASE:
10917 case RDGSBASE64:
10918 return true;
10919 }
10920 return false;
10921}
10922
10923bool isVPMOVSQD(unsigned Opcode) {
10924 switch (Opcode) {
10925 case VPMOVSQDZ128mr:
10926 case VPMOVSQDZ128mrk:
10927 case VPMOVSQDZ128rr:
10928 case VPMOVSQDZ128rrk:
10929 case VPMOVSQDZ128rrkz:
10930 case VPMOVSQDZ256mr:
10931 case VPMOVSQDZ256mrk:
10932 case VPMOVSQDZ256rr:
10933 case VPMOVSQDZ256rrk:
10934 case VPMOVSQDZ256rrkz:
10935 case VPMOVSQDZmr:
10936 case VPMOVSQDZmrk:
10937 case VPMOVSQDZrr:
10938 case VPMOVSQDZrrk:
10939 case VPMOVSQDZrrkz:
10940 return true;
10941 }
10942 return false;
10943}
10944
10945bool isBT(unsigned Opcode) {
10946 switch (Opcode) {
10947 case BT16mi8:
10948 case BT16mr:
10949 case BT16ri8:
10950 case BT16rr:
10951 case BT32mi8:
10952 case BT32mr:
10953 case BT32ri8:
10954 case BT32rr:
10955 case BT64mi8:
10956 case BT64mr:
10957 case BT64ri8:
10958 case BT64rr:
10959 return true;
10960 }
10961 return false;
10962}
10963
10964bool isVPROLVQ(unsigned Opcode) {
10965 switch (Opcode) {
10966 case VPROLVQZ128rm:
10967 case VPROLVQZ128rmb:
10968 case VPROLVQZ128rmbk:
10969 case VPROLVQZ128rmbkz:
10970 case VPROLVQZ128rmk:
10971 case VPROLVQZ128rmkz:
10972 case VPROLVQZ128rr:
10973 case VPROLVQZ128rrk:
10974 case VPROLVQZ128rrkz:
10975 case VPROLVQZ256rm:
10976 case VPROLVQZ256rmb:
10977 case VPROLVQZ256rmbk:
10978 case VPROLVQZ256rmbkz:
10979 case VPROLVQZ256rmk:
10980 case VPROLVQZ256rmkz:
10981 case VPROLVQZ256rr:
10982 case VPROLVQZ256rrk:
10983 case VPROLVQZ256rrkz:
10984 case VPROLVQZrm:
10985 case VPROLVQZrmb:
10986 case VPROLVQZrmbk:
10987 case VPROLVQZrmbkz:
10988 case VPROLVQZrmk:
10989 case VPROLVQZrmkz:
10990 case VPROLVQZrr:
10991 case VPROLVQZrrk:
10992 case VPROLVQZrrkz:
10993 return true;
10994 }
10995 return false;
10996}
10997
10998bool isVFMADDSUB132PD(unsigned Opcode) {
10999 switch (Opcode) {
11000 case VFMADDSUB132PDYm:
11001 case VFMADDSUB132PDYr:
11002 case VFMADDSUB132PDZ128m:
11003 case VFMADDSUB132PDZ128mb:
11004 case VFMADDSUB132PDZ128mbk:
11005 case VFMADDSUB132PDZ128mbkz:
11006 case VFMADDSUB132PDZ128mk:
11007 case VFMADDSUB132PDZ128mkz:
11008 case VFMADDSUB132PDZ128r:
11009 case VFMADDSUB132PDZ128rk:
11010 case VFMADDSUB132PDZ128rkz:
11011 case VFMADDSUB132PDZ256m:
11012 case VFMADDSUB132PDZ256mb:
11013 case VFMADDSUB132PDZ256mbk:
11014 case VFMADDSUB132PDZ256mbkz:
11015 case VFMADDSUB132PDZ256mk:
11016 case VFMADDSUB132PDZ256mkz:
11017 case VFMADDSUB132PDZ256r:
11018 case VFMADDSUB132PDZ256rk:
11019 case VFMADDSUB132PDZ256rkz:
11020 case VFMADDSUB132PDZm:
11021 case VFMADDSUB132PDZmb:
11022 case VFMADDSUB132PDZmbk:
11023 case VFMADDSUB132PDZmbkz:
11024 case VFMADDSUB132PDZmk:
11025 case VFMADDSUB132PDZmkz:
11026 case VFMADDSUB132PDZr:
11027 case VFMADDSUB132PDZrb:
11028 case VFMADDSUB132PDZrbk:
11029 case VFMADDSUB132PDZrbkz:
11030 case VFMADDSUB132PDZrk:
11031 case VFMADDSUB132PDZrkz:
11032 case VFMADDSUB132PDm:
11033 case VFMADDSUB132PDr:
11034 return true;
11035 }
11036 return false;
11037}
11038
11039bool isRORX(unsigned Opcode) {
11040 switch (Opcode) {
11041 case RORX32mi:
11042 case RORX32mi_EVEX:
11043 case RORX32ri:
11044 case RORX32ri_EVEX:
11045 case RORX64mi:
11046 case RORX64mi_EVEX:
11047 case RORX64ri:
11048 case RORX64ri_EVEX:
11049 return true;
11050 }
11051 return false;
11052}
11053
11054bool isPADDUSW(unsigned Opcode) {
11055 switch (Opcode) {
11056 case MMX_PADDUSWrm:
11057 case MMX_PADDUSWrr:
11058 case PADDUSWrm:
11059 case PADDUSWrr:
11060 return true;
11061 }
11062 return false;
11063}
11064
11065bool isPFNACC(unsigned Opcode) {
11066 switch (Opcode) {
11067 case PFNACCrm:
11068 case PFNACCrr:
11069 return true;
11070 }
11071 return false;
11072}
11073
11074bool isAND(unsigned Opcode) {
11075 switch (Opcode) {
11076 case AND16i16:
11077 case AND16mi:
11078 case AND16mi8:
11079 case AND16mi8_EVEX:
11080 case AND16mi8_ND:
11081 case AND16mi8_NF:
11082 case AND16mi8_NF_ND:
11083 case AND16mi_EVEX:
11084 case AND16mi_ND:
11085 case AND16mi_NF:
11086 case AND16mi_NF_ND:
11087 case AND16mr:
11088 case AND16mr_EVEX:
11089 case AND16mr_ND:
11090 case AND16mr_NF:
11091 case AND16mr_NF_ND:
11092 case AND16ri:
11093 case AND16ri8:
11094 case AND16ri8_EVEX:
11095 case AND16ri8_ND:
11096 case AND16ri8_NF:
11097 case AND16ri8_NF_ND:
11098 case AND16ri_EVEX:
11099 case AND16ri_ND:
11100 case AND16ri_NF:
11101 case AND16ri_NF_ND:
11102 case AND16rm:
11103 case AND16rm_EVEX:
11104 case AND16rm_ND:
11105 case AND16rm_NF:
11106 case AND16rm_NF_ND:
11107 case AND16rr:
11108 case AND16rr_EVEX:
11109 case AND16rr_EVEX_REV:
11110 case AND16rr_ND:
11111 case AND16rr_ND_REV:
11112 case AND16rr_NF:
11113 case AND16rr_NF_ND:
11114 case AND16rr_NF_ND_REV:
11115 case AND16rr_NF_REV:
11116 case AND16rr_REV:
11117 case AND32i32:
11118 case AND32mi:
11119 case AND32mi8:
11120 case AND32mi8_EVEX:
11121 case AND32mi8_ND:
11122 case AND32mi8_NF:
11123 case AND32mi8_NF_ND:
11124 case AND32mi_EVEX:
11125 case AND32mi_ND:
11126 case AND32mi_NF:
11127 case AND32mi_NF_ND:
11128 case AND32mr:
11129 case AND32mr_EVEX:
11130 case AND32mr_ND:
11131 case AND32mr_NF:
11132 case AND32mr_NF_ND:
11133 case AND32ri:
11134 case AND32ri8:
11135 case AND32ri8_EVEX:
11136 case AND32ri8_ND:
11137 case AND32ri8_NF:
11138 case AND32ri8_NF_ND:
11139 case AND32ri_EVEX:
11140 case AND32ri_ND:
11141 case AND32ri_NF:
11142 case AND32ri_NF_ND:
11143 case AND32rm:
11144 case AND32rm_EVEX:
11145 case AND32rm_ND:
11146 case AND32rm_NF:
11147 case AND32rm_NF_ND:
11148 case AND32rr:
11149 case AND32rr_EVEX:
11150 case AND32rr_EVEX_REV:
11151 case AND32rr_ND:
11152 case AND32rr_ND_REV:
11153 case AND32rr_NF:
11154 case AND32rr_NF_ND:
11155 case AND32rr_NF_ND_REV:
11156 case AND32rr_NF_REV:
11157 case AND32rr_REV:
11158 case AND64i32:
11159 case AND64mi32:
11160 case AND64mi32_EVEX:
11161 case AND64mi32_ND:
11162 case AND64mi32_NF:
11163 case AND64mi32_NF_ND:
11164 case AND64mi8:
11165 case AND64mi8_EVEX:
11166 case AND64mi8_ND:
11167 case AND64mi8_NF:
11168 case AND64mi8_NF_ND:
11169 case AND64mr:
11170 case AND64mr_EVEX:
11171 case AND64mr_ND:
11172 case AND64mr_NF:
11173 case AND64mr_NF_ND:
11174 case AND64ri32:
11175 case AND64ri32_EVEX:
11176 case AND64ri32_ND:
11177 case AND64ri32_NF:
11178 case AND64ri32_NF_ND:
11179 case AND64ri8:
11180 case AND64ri8_EVEX:
11181 case AND64ri8_ND:
11182 case AND64ri8_NF:
11183 case AND64ri8_NF_ND:
11184 case AND64rm:
11185 case AND64rm_EVEX:
11186 case AND64rm_ND:
11187 case AND64rm_NF:
11188 case AND64rm_NF_ND:
11189 case AND64rr:
11190 case AND64rr_EVEX:
11191 case AND64rr_EVEX_REV:
11192 case AND64rr_ND:
11193 case AND64rr_ND_REV:
11194 case AND64rr_NF:
11195 case AND64rr_NF_ND:
11196 case AND64rr_NF_ND_REV:
11197 case AND64rr_NF_REV:
11198 case AND64rr_REV:
11199 case AND8i8:
11200 case AND8mi:
11201 case AND8mi8:
11202 case AND8mi_EVEX:
11203 case AND8mi_ND:
11204 case AND8mi_NF:
11205 case AND8mi_NF_ND:
11206 case AND8mr:
11207 case AND8mr_EVEX:
11208 case AND8mr_ND:
11209 case AND8mr_NF:
11210 case AND8mr_NF_ND:
11211 case AND8ri:
11212 case AND8ri8:
11213 case AND8ri_EVEX:
11214 case AND8ri_ND:
11215 case AND8ri_NF:
11216 case AND8ri_NF_ND:
11217 case AND8rm:
11218 case AND8rm_EVEX:
11219 case AND8rm_ND:
11220 case AND8rm_NF:
11221 case AND8rm_NF_ND:
11222 case AND8rr:
11223 case AND8rr_EVEX:
11224 case AND8rr_EVEX_REV:
11225 case AND8rr_ND:
11226 case AND8rr_ND_REV:
11227 case AND8rr_NF:
11228 case AND8rr_NF_ND:
11229 case AND8rr_NF_ND_REV:
11230 case AND8rr_NF_REV:
11231 case AND8rr_REV:
11232 return true;
11233 }
11234 return false;
11235}
11236
11237bool isPSLLQ(unsigned Opcode) {
11238 switch (Opcode) {
11239 case MMX_PSLLQri:
11240 case MMX_PSLLQrm:
11241 case MMX_PSLLQrr:
11242 case PSLLQri:
11243 case PSLLQrm:
11244 case PSLLQrr:
11245 return true;
11246 }
11247 return false;
11248}
11249
11250bool isVFMSUB132PH(unsigned Opcode) {
11251 switch (Opcode) {
11252 case VFMSUB132PHZ128m:
11253 case VFMSUB132PHZ128mb:
11254 case VFMSUB132PHZ128mbk:
11255 case VFMSUB132PHZ128mbkz:
11256 case VFMSUB132PHZ128mk:
11257 case VFMSUB132PHZ128mkz:
11258 case VFMSUB132PHZ128r:
11259 case VFMSUB132PHZ128rk:
11260 case VFMSUB132PHZ128rkz:
11261 case VFMSUB132PHZ256m:
11262 case VFMSUB132PHZ256mb:
11263 case VFMSUB132PHZ256mbk:
11264 case VFMSUB132PHZ256mbkz:
11265 case VFMSUB132PHZ256mk:
11266 case VFMSUB132PHZ256mkz:
11267 case VFMSUB132PHZ256r:
11268 case VFMSUB132PHZ256rk:
11269 case VFMSUB132PHZ256rkz:
11270 case VFMSUB132PHZm:
11271 case VFMSUB132PHZmb:
11272 case VFMSUB132PHZmbk:
11273 case VFMSUB132PHZmbkz:
11274 case VFMSUB132PHZmk:
11275 case VFMSUB132PHZmkz:
11276 case VFMSUB132PHZr:
11277 case VFMSUB132PHZrb:
11278 case VFMSUB132PHZrbk:
11279 case VFMSUB132PHZrbkz:
11280 case VFMSUB132PHZrk:
11281 case VFMSUB132PHZrkz:
11282 return true;
11283 }
11284 return false;
11285}
11286
11287bool isXSAVE(unsigned Opcode) {
11288 return Opcode == XSAVE;
11289}
11290
11291bool isKNOTQ(unsigned Opcode) {
11292 return Opcode == KNOTQkk;
11293}
11294
11295bool isXTEST(unsigned Opcode) {
11296 return Opcode == XTEST;
11297}
11298
11299bool isVINSERTPS(unsigned Opcode) {
11300 switch (Opcode) {
11301 case VINSERTPSZrmi:
11302 case VINSERTPSZrri:
11303 case VINSERTPSrmi:
11304 case VINSERTPSrri:
11305 return true;
11306 }
11307 return false;
11308}
11309
11310bool isXSAVEOPT(unsigned Opcode) {
11311 return Opcode == XSAVEOPT;
11312}
11313
11314bool isLDS(unsigned Opcode) {
11315 switch (Opcode) {
11316 case LDS16rm:
11317 case LDS32rm:
11318 return true;
11319 }
11320 return false;
11321}
11322
11323bool isVFMADDSUB213PD(unsigned Opcode) {
11324 switch (Opcode) {
11325 case VFMADDSUB213PDYm:
11326 case VFMADDSUB213PDYr:
11327 case VFMADDSUB213PDZ128m:
11328 case VFMADDSUB213PDZ128mb:
11329 case VFMADDSUB213PDZ128mbk:
11330 case VFMADDSUB213PDZ128mbkz:
11331 case VFMADDSUB213PDZ128mk:
11332 case VFMADDSUB213PDZ128mkz:
11333 case VFMADDSUB213PDZ128r:
11334 case VFMADDSUB213PDZ128rk:
11335 case VFMADDSUB213PDZ128rkz:
11336 case VFMADDSUB213PDZ256m:
11337 case VFMADDSUB213PDZ256mb:
11338 case VFMADDSUB213PDZ256mbk:
11339 case VFMADDSUB213PDZ256mbkz:
11340 case VFMADDSUB213PDZ256mk:
11341 case VFMADDSUB213PDZ256mkz:
11342 case VFMADDSUB213PDZ256r:
11343 case VFMADDSUB213PDZ256rk:
11344 case VFMADDSUB213PDZ256rkz:
11345 case VFMADDSUB213PDZm:
11346 case VFMADDSUB213PDZmb:
11347 case VFMADDSUB213PDZmbk:
11348 case VFMADDSUB213PDZmbkz:
11349 case VFMADDSUB213PDZmk:
11350 case VFMADDSUB213PDZmkz:
11351 case VFMADDSUB213PDZr:
11352 case VFMADDSUB213PDZrb:
11353 case VFMADDSUB213PDZrbk:
11354 case VFMADDSUB213PDZrbkz:
11355 case VFMADDSUB213PDZrk:
11356 case VFMADDSUB213PDZrkz:
11357 case VFMADDSUB213PDm:
11358 case VFMADDSUB213PDr:
11359 return true;
11360 }
11361 return false;
11362}
11363
11364bool isVINSERTF32X4(unsigned Opcode) {
11365 switch (Opcode) {
11366 case VINSERTF32X4Z256rmi:
11367 case VINSERTF32X4Z256rmik:
11368 case VINSERTF32X4Z256rmikz:
11369 case VINSERTF32X4Z256rri:
11370 case VINSERTF32X4Z256rrik:
11371 case VINSERTF32X4Z256rrikz:
11372 case VINSERTF32X4Zrmi:
11373 case VINSERTF32X4Zrmik:
11374 case VINSERTF32X4Zrmikz:
11375 case VINSERTF32X4Zrri:
11376 case VINSERTF32X4Zrrik:
11377 case VINSERTF32X4Zrrikz:
11378 return true;
11379 }
11380 return false;
11381}
11382
11383bool isVRSQRTPS(unsigned Opcode) {
11384 switch (Opcode) {
11385 case VRSQRTPSYm:
11386 case VRSQRTPSYr:
11387 case VRSQRTPSm:
11388 case VRSQRTPSr:
11389 return true;
11390 }
11391 return false;
11392}
11393
11394bool isVSUBPH(unsigned Opcode) {
11395 switch (Opcode) {
11396 case VSUBPHZ128rm:
11397 case VSUBPHZ128rmb:
11398 case VSUBPHZ128rmbk:
11399 case VSUBPHZ128rmbkz:
11400 case VSUBPHZ128rmk:
11401 case VSUBPHZ128rmkz:
11402 case VSUBPHZ128rr:
11403 case VSUBPHZ128rrk:
11404 case VSUBPHZ128rrkz:
11405 case VSUBPHZ256rm:
11406 case VSUBPHZ256rmb:
11407 case VSUBPHZ256rmbk:
11408 case VSUBPHZ256rmbkz:
11409 case VSUBPHZ256rmk:
11410 case VSUBPHZ256rmkz:
11411 case VSUBPHZ256rr:
11412 case VSUBPHZ256rrk:
11413 case VSUBPHZ256rrkz:
11414 case VSUBPHZrm:
11415 case VSUBPHZrmb:
11416 case VSUBPHZrmbk:
11417 case VSUBPHZrmbkz:
11418 case VSUBPHZrmk:
11419 case VSUBPHZrmkz:
11420 case VSUBPHZrr:
11421 case VSUBPHZrrb:
11422 case VSUBPHZrrbk:
11423 case VSUBPHZrrbkz:
11424 case VSUBPHZrrk:
11425 case VSUBPHZrrkz:
11426 return true;
11427 }
11428 return false;
11429}
11430
11431bool isPMOVSXBW(unsigned Opcode) {
11432 switch (Opcode) {
11433 case PMOVSXBWrm:
11434 case PMOVSXBWrr:
11435 return true;
11436 }
11437 return false;
11438}
11439
11440bool isVPSRLDQ(unsigned Opcode) {
11441 switch (Opcode) {
11442 case VPSRLDQYri:
11443 case VPSRLDQZ128mi:
11444 case VPSRLDQZ128ri:
11445 case VPSRLDQZ256mi:
11446 case VPSRLDQZ256ri:
11447 case VPSRLDQZmi:
11448 case VPSRLDQZri:
11449 case VPSRLDQri:
11450 return true;
11451 }
11452 return false;
11453}
11454
11455bool isADC(unsigned Opcode) {
11456 switch (Opcode) {
11457 case ADC16i16:
11458 case ADC16mi:
11459 case ADC16mi8:
11460 case ADC16mi8_EVEX:
11461 case ADC16mi8_ND:
11462 case ADC16mi_EVEX:
11463 case ADC16mi_ND:
11464 case ADC16mr:
11465 case ADC16mr_EVEX:
11466 case ADC16mr_ND:
11467 case ADC16ri:
11468 case ADC16ri8:
11469 case ADC16ri8_EVEX:
11470 case ADC16ri8_ND:
11471 case ADC16ri_EVEX:
11472 case ADC16ri_ND:
11473 case ADC16rm:
11474 case ADC16rm_EVEX:
11475 case ADC16rm_ND:
11476 case ADC16rr:
11477 case ADC16rr_EVEX:
11478 case ADC16rr_EVEX_REV:
11479 case ADC16rr_ND:
11480 case ADC16rr_ND_REV:
11481 case ADC16rr_REV:
11482 case ADC32i32:
11483 case ADC32mi:
11484 case ADC32mi8:
11485 case ADC32mi8_EVEX:
11486 case ADC32mi8_ND:
11487 case ADC32mi_EVEX:
11488 case ADC32mi_ND:
11489 case ADC32mr:
11490 case ADC32mr_EVEX:
11491 case ADC32mr_ND:
11492 case ADC32ri:
11493 case ADC32ri8:
11494 case ADC32ri8_EVEX:
11495 case ADC32ri8_ND:
11496 case ADC32ri_EVEX:
11497 case ADC32ri_ND:
11498 case ADC32rm:
11499 case ADC32rm_EVEX:
11500 case ADC32rm_ND:
11501 case ADC32rr:
11502 case ADC32rr_EVEX:
11503 case ADC32rr_EVEX_REV:
11504 case ADC32rr_ND:
11505 case ADC32rr_ND_REV:
11506 case ADC32rr_REV:
11507 case ADC64i32:
11508 case ADC64mi32:
11509 case ADC64mi32_EVEX:
11510 case ADC64mi32_ND:
11511 case ADC64mi8:
11512 case ADC64mi8_EVEX:
11513 case ADC64mi8_ND:
11514 case ADC64mr:
11515 case ADC64mr_EVEX:
11516 case ADC64mr_ND:
11517 case ADC64ri32:
11518 case ADC64ri32_EVEX:
11519 case ADC64ri32_ND:
11520 case ADC64ri8:
11521 case ADC64ri8_EVEX:
11522 case ADC64ri8_ND:
11523 case ADC64rm:
11524 case ADC64rm_EVEX:
11525 case ADC64rm_ND:
11526 case ADC64rr:
11527 case ADC64rr_EVEX:
11528 case ADC64rr_EVEX_REV:
11529 case ADC64rr_ND:
11530 case ADC64rr_ND_REV:
11531 case ADC64rr_REV:
11532 case ADC8i8:
11533 case ADC8mi:
11534 case ADC8mi8:
11535 case ADC8mi_EVEX:
11536 case ADC8mi_ND:
11537 case ADC8mr:
11538 case ADC8mr_EVEX:
11539 case ADC8mr_ND:
11540 case ADC8ri:
11541 case ADC8ri8:
11542 case ADC8ri_EVEX:
11543 case ADC8ri_ND:
11544 case ADC8rm:
11545 case ADC8rm_EVEX:
11546 case ADC8rm_ND:
11547 case ADC8rr:
11548 case ADC8rr_EVEX:
11549 case ADC8rr_EVEX_REV:
11550 case ADC8rr_ND:
11551 case ADC8rr_ND_REV:
11552 case ADC8rr_REV:
11553 return true;
11554 }
11555 return false;
11556}
11557
11558bool isPHADDD(unsigned Opcode) {
11559 switch (Opcode) {
11560 case MMX_PHADDDrm:
11561 case MMX_PHADDDrr:
11562 case PHADDDrm:
11563 case PHADDDrr:
11564 return true;
11565 }
11566 return false;
11567}
11568
11569bool isVDPPHPS(unsigned Opcode) {
11570 switch (Opcode) {
11571 case VDPPHPSZ128m:
11572 case VDPPHPSZ128mb:
11573 case VDPPHPSZ128mbk:
11574 case VDPPHPSZ128mbkz:
11575 case VDPPHPSZ128mk:
11576 case VDPPHPSZ128mkz:
11577 case VDPPHPSZ128r:
11578 case VDPPHPSZ128rk:
11579 case VDPPHPSZ128rkz:
11580 case VDPPHPSZ256m:
11581 case VDPPHPSZ256mb:
11582 case VDPPHPSZ256mbk:
11583 case VDPPHPSZ256mbkz:
11584 case VDPPHPSZ256mk:
11585 case VDPPHPSZ256mkz:
11586 case VDPPHPSZ256r:
11587 case VDPPHPSZ256rk:
11588 case VDPPHPSZ256rkz:
11589 case VDPPHPSZm:
11590 case VDPPHPSZmb:
11591 case VDPPHPSZmbk:
11592 case VDPPHPSZmbkz:
11593 case VDPPHPSZmk:
11594 case VDPPHPSZmkz:
11595 case VDPPHPSZr:
11596 case VDPPHPSZrk:
11597 case VDPPHPSZrkz:
11598 return true;
11599 }
11600 return false;
11601}
11602
11603bool isVMINPH(unsigned Opcode) {
11604 switch (Opcode) {
11605 case VMINPHZ128rm:
11606 case VMINPHZ128rmb:
11607 case VMINPHZ128rmbk:
11608 case VMINPHZ128rmbkz:
11609 case VMINPHZ128rmk:
11610 case VMINPHZ128rmkz:
11611 case VMINPHZ128rr:
11612 case VMINPHZ128rrk:
11613 case VMINPHZ128rrkz:
11614 case VMINPHZ256rm:
11615 case VMINPHZ256rmb:
11616 case VMINPHZ256rmbk:
11617 case VMINPHZ256rmbkz:
11618 case VMINPHZ256rmk:
11619 case VMINPHZ256rmkz:
11620 case VMINPHZ256rr:
11621 case VMINPHZ256rrk:
11622 case VMINPHZ256rrkz:
11623 case VMINPHZrm:
11624 case VMINPHZrmb:
11625 case VMINPHZrmbk:
11626 case VMINPHZrmbkz:
11627 case VMINPHZrmk:
11628 case VMINPHZrmkz:
11629 case VMINPHZrr:
11630 case VMINPHZrrb:
11631 case VMINPHZrrbk:
11632 case VMINPHZrrbkz:
11633 case VMINPHZrrk:
11634 case VMINPHZrrkz:
11635 return true;
11636 }
11637 return false;
11638}
11639
11640bool isVMINSD(unsigned Opcode) {
11641 switch (Opcode) {
11642 case VMINSDZrm_Int:
11643 case VMINSDZrmk_Int:
11644 case VMINSDZrmkz_Int:
11645 case VMINSDZrr_Int:
11646 case VMINSDZrrb_Int:
11647 case VMINSDZrrbk_Int:
11648 case VMINSDZrrbkz_Int:
11649 case VMINSDZrrk_Int:
11650 case VMINSDZrrkz_Int:
11651 case VMINSDrm_Int:
11652 case VMINSDrr_Int:
11653 return true;
11654 }
11655 return false;
11656}
11657
11658bool isVROUNDPD(unsigned Opcode) {
11659 switch (Opcode) {
11660 case VROUNDPDYmi:
11661 case VROUNDPDYri:
11662 case VROUNDPDmi:
11663 case VROUNDPDri:
11664 return true;
11665 }
11666 return false;
11667}
11668
11669bool isVFCMADDCPH(unsigned Opcode) {
11670 switch (Opcode) {
11671 case VFCMADDCPHZ128m:
11672 case VFCMADDCPHZ128mb:
11673 case VFCMADDCPHZ128mbk:
11674 case VFCMADDCPHZ128mbkz:
11675 case VFCMADDCPHZ128mk:
11676 case VFCMADDCPHZ128mkz:
11677 case VFCMADDCPHZ128r:
11678 case VFCMADDCPHZ128rk:
11679 case VFCMADDCPHZ128rkz:
11680 case VFCMADDCPHZ256m:
11681 case VFCMADDCPHZ256mb:
11682 case VFCMADDCPHZ256mbk:
11683 case VFCMADDCPHZ256mbkz:
11684 case VFCMADDCPHZ256mk:
11685 case VFCMADDCPHZ256mkz:
11686 case VFCMADDCPHZ256r:
11687 case VFCMADDCPHZ256rk:
11688 case VFCMADDCPHZ256rkz:
11689 case VFCMADDCPHZm:
11690 case VFCMADDCPHZmb:
11691 case VFCMADDCPHZmbk:
11692 case VFCMADDCPHZmbkz:
11693 case VFCMADDCPHZmk:
11694 case VFCMADDCPHZmkz:
11695 case VFCMADDCPHZr:
11696 case VFCMADDCPHZrb:
11697 case VFCMADDCPHZrbk:
11698 case VFCMADDCPHZrbkz:
11699 case VFCMADDCPHZrk:
11700 case VFCMADDCPHZrkz:
11701 return true;
11702 }
11703 return false;
11704}
11705
11706bool isINCSSPQ(unsigned Opcode) {
11707 return Opcode == INCSSPQ;
11708}
11709
11710bool isVPUNPCKLDQ(unsigned Opcode) {
11711 switch (Opcode) {
11712 case VPUNPCKLDQYrm:
11713 case VPUNPCKLDQYrr:
11714 case VPUNPCKLDQZ128rm:
11715 case VPUNPCKLDQZ128rmb:
11716 case VPUNPCKLDQZ128rmbk:
11717 case VPUNPCKLDQZ128rmbkz:
11718 case VPUNPCKLDQZ128rmk:
11719 case VPUNPCKLDQZ128rmkz:
11720 case VPUNPCKLDQZ128rr:
11721 case VPUNPCKLDQZ128rrk:
11722 case VPUNPCKLDQZ128rrkz:
11723 case VPUNPCKLDQZ256rm:
11724 case VPUNPCKLDQZ256rmb:
11725 case VPUNPCKLDQZ256rmbk:
11726 case VPUNPCKLDQZ256rmbkz:
11727 case VPUNPCKLDQZ256rmk:
11728 case VPUNPCKLDQZ256rmkz:
11729 case VPUNPCKLDQZ256rr:
11730 case VPUNPCKLDQZ256rrk:
11731 case VPUNPCKLDQZ256rrkz:
11732 case VPUNPCKLDQZrm:
11733 case VPUNPCKLDQZrmb:
11734 case VPUNPCKLDQZrmbk:
11735 case VPUNPCKLDQZrmbkz:
11736 case VPUNPCKLDQZrmk:
11737 case VPUNPCKLDQZrmkz:
11738 case VPUNPCKLDQZrr:
11739 case VPUNPCKLDQZrrk:
11740 case VPUNPCKLDQZrrkz:
11741 case VPUNPCKLDQrm:
11742 case VPUNPCKLDQrr:
11743 return true;
11744 }
11745 return false;
11746}
11747
11748bool isVMINSH(unsigned Opcode) {
11749 switch (Opcode) {
11750 case VMINSHZrm_Int:
11751 case VMINSHZrmk_Int:
11752 case VMINSHZrmkz_Int:
11753 case VMINSHZrr_Int:
11754 case VMINSHZrrb_Int:
11755 case VMINSHZrrbk_Int:
11756 case VMINSHZrrbkz_Int:
11757 case VMINSHZrrk_Int:
11758 case VMINSHZrrkz_Int:
11759 return true;
11760 }
11761 return false;
11762}
11763
11764bool isINSERTQ(unsigned Opcode) {
11765 switch (Opcode) {
11766 case INSERTQ:
11767 case INSERTQI:
11768 return true;
11769 }
11770 return false;
11771}
11772
11773bool isBLCI(unsigned Opcode) {
11774 switch (Opcode) {
11775 case BLCI32rm:
11776 case BLCI32rr:
11777 case BLCI64rm:
11778 case BLCI64rr:
11779 return true;
11780 }
11781 return false;
11782}
11783
11784bool isHLT(unsigned Opcode) {
11785 return Opcode == HLT;
11786}
11787
11788bool isVPCOMUW(unsigned Opcode) {
11789 switch (Opcode) {
11790 case VPCOMUWmi:
11791 case VPCOMUWri:
11792 return true;
11793 }
11794 return false;
11795}
11796
11797bool isVPMOVSXDQ(unsigned Opcode) {
11798 switch (Opcode) {
11799 case VPMOVSXDQYrm:
11800 case VPMOVSXDQYrr:
11801 case VPMOVSXDQZ128rm:
11802 case VPMOVSXDQZ128rmk:
11803 case VPMOVSXDQZ128rmkz:
11804 case VPMOVSXDQZ128rr:
11805 case VPMOVSXDQZ128rrk:
11806 case VPMOVSXDQZ128rrkz:
11807 case VPMOVSXDQZ256rm:
11808 case VPMOVSXDQZ256rmk:
11809 case VPMOVSXDQZ256rmkz:
11810 case VPMOVSXDQZ256rr:
11811 case VPMOVSXDQZ256rrk:
11812 case VPMOVSXDQZ256rrkz:
11813 case VPMOVSXDQZrm:
11814 case VPMOVSXDQZrmk:
11815 case VPMOVSXDQZrmkz:
11816 case VPMOVSXDQZrr:
11817 case VPMOVSXDQZrrk:
11818 case VPMOVSXDQZrrkz:
11819 case VPMOVSXDQrm:
11820 case VPMOVSXDQrr:
11821 return true;
11822 }
11823 return false;
11824}
11825
11826bool isVFNMSUB231PS(unsigned Opcode) {
11827 switch (Opcode) {
11828 case VFNMSUB231PSYm:
11829 case VFNMSUB231PSYr:
11830 case VFNMSUB231PSZ128m:
11831 case VFNMSUB231PSZ128mb:
11832 case VFNMSUB231PSZ128mbk:
11833 case VFNMSUB231PSZ128mbkz:
11834 case VFNMSUB231PSZ128mk:
11835 case VFNMSUB231PSZ128mkz:
11836 case VFNMSUB231PSZ128r:
11837 case VFNMSUB231PSZ128rk:
11838 case VFNMSUB231PSZ128rkz:
11839 case VFNMSUB231PSZ256m:
11840 case VFNMSUB231PSZ256mb:
11841 case VFNMSUB231PSZ256mbk:
11842 case VFNMSUB231PSZ256mbkz:
11843 case VFNMSUB231PSZ256mk:
11844 case VFNMSUB231PSZ256mkz:
11845 case VFNMSUB231PSZ256r:
11846 case VFNMSUB231PSZ256rk:
11847 case VFNMSUB231PSZ256rkz:
11848 case VFNMSUB231PSZm:
11849 case VFNMSUB231PSZmb:
11850 case VFNMSUB231PSZmbk:
11851 case VFNMSUB231PSZmbkz:
11852 case VFNMSUB231PSZmk:
11853 case VFNMSUB231PSZmkz:
11854 case VFNMSUB231PSZr:
11855 case VFNMSUB231PSZrb:
11856 case VFNMSUB231PSZrbk:
11857 case VFNMSUB231PSZrbkz:
11858 case VFNMSUB231PSZrk:
11859 case VFNMSUB231PSZrkz:
11860 case VFNMSUB231PSm:
11861 case VFNMSUB231PSr:
11862 return true;
11863 }
11864 return false;
11865}
11866
11867bool isVFNMSUB213SH(unsigned Opcode) {
11868 switch (Opcode) {
11869 case VFNMSUB213SHZm_Int:
11870 case VFNMSUB213SHZmk_Int:
11871 case VFNMSUB213SHZmkz_Int:
11872 case VFNMSUB213SHZr_Int:
11873 case VFNMSUB213SHZrb_Int:
11874 case VFNMSUB213SHZrbk_Int:
11875 case VFNMSUB213SHZrbkz_Int:
11876 case VFNMSUB213SHZrk_Int:
11877 case VFNMSUB213SHZrkz_Int:
11878 return true;
11879 }
11880 return false;
11881}
11882
11883bool isVCVTTPD2UQQ(unsigned Opcode) {
11884 switch (Opcode) {
11885 case VCVTTPD2UQQZ128rm:
11886 case VCVTTPD2UQQZ128rmb:
11887 case VCVTTPD2UQQZ128rmbk:
11888 case VCVTTPD2UQQZ128rmbkz:
11889 case VCVTTPD2UQQZ128rmk:
11890 case VCVTTPD2UQQZ128rmkz:
11891 case VCVTTPD2UQQZ128rr:
11892 case VCVTTPD2UQQZ128rrk:
11893 case VCVTTPD2UQQZ128rrkz:
11894 case VCVTTPD2UQQZ256rm:
11895 case VCVTTPD2UQQZ256rmb:
11896 case VCVTTPD2UQQZ256rmbk:
11897 case VCVTTPD2UQQZ256rmbkz:
11898 case VCVTTPD2UQQZ256rmk:
11899 case VCVTTPD2UQQZ256rmkz:
11900 case VCVTTPD2UQQZ256rr:
11901 case VCVTTPD2UQQZ256rrk:
11902 case VCVTTPD2UQQZ256rrkz:
11903 case VCVTTPD2UQQZrm:
11904 case VCVTTPD2UQQZrmb:
11905 case VCVTTPD2UQQZrmbk:
11906 case VCVTTPD2UQQZrmbkz:
11907 case VCVTTPD2UQQZrmk:
11908 case VCVTTPD2UQQZrmkz:
11909 case VCVTTPD2UQQZrr:
11910 case VCVTTPD2UQQZrrb:
11911 case VCVTTPD2UQQZrrbk:
11912 case VCVTTPD2UQQZrrbkz:
11913 case VCVTTPD2UQQZrrk:
11914 case VCVTTPD2UQQZrrkz:
11915 return true;
11916 }
11917 return false;
11918}
11919
11920bool isSQRTSS(unsigned Opcode) {
11921 switch (Opcode) {
11922 case SQRTSSm_Int:
11923 case SQRTSSr_Int:
11924 return true;
11925 }
11926 return false;
11927}
11928
11929bool isIMUL(unsigned Opcode) {
11930 switch (Opcode) {
11931 case IMUL16m:
11932 case IMUL16m_EVEX:
11933 case IMUL16m_NF:
11934 case IMUL16r:
11935 case IMUL16r_EVEX:
11936 case IMUL16r_NF:
11937 case IMUL16rm:
11938 case IMUL16rm_EVEX:
11939 case IMUL16rm_ND:
11940 case IMUL16rm_NF:
11941 case IMUL16rm_NF_ND:
11942 case IMUL16rmi:
11943 case IMUL16rmi8:
11944 case IMUL16rmi8_EVEX:
11945 case IMUL16rmi8_NF:
11946 case IMUL16rmi_EVEX:
11947 case IMUL16rmi_NF:
11948 case IMUL16rr:
11949 case IMUL16rr_EVEX:
11950 case IMUL16rr_ND:
11951 case IMUL16rr_NF:
11952 case IMUL16rr_NF_ND:
11953 case IMUL16rri:
11954 case IMUL16rri8:
11955 case IMUL16rri8_EVEX:
11956 case IMUL16rri8_NF:
11957 case IMUL16rri_EVEX:
11958 case IMUL16rri_NF:
11959 case IMUL32m:
11960 case IMUL32m_EVEX:
11961 case IMUL32m_NF:
11962 case IMUL32r:
11963 case IMUL32r_EVEX:
11964 case IMUL32r_NF:
11965 case IMUL32rm:
11966 case IMUL32rm_EVEX:
11967 case IMUL32rm_ND:
11968 case IMUL32rm_NF:
11969 case IMUL32rm_NF_ND:
11970 case IMUL32rmi:
11971 case IMUL32rmi8:
11972 case IMUL32rmi8_EVEX:
11973 case IMUL32rmi8_NF:
11974 case IMUL32rmi_EVEX:
11975 case IMUL32rmi_NF:
11976 case IMUL32rr:
11977 case IMUL32rr_EVEX:
11978 case IMUL32rr_ND:
11979 case IMUL32rr_NF:
11980 case IMUL32rr_NF_ND:
11981 case IMUL32rri:
11982 case IMUL32rri8:
11983 case IMUL32rri8_EVEX:
11984 case IMUL32rri8_NF:
11985 case IMUL32rri_EVEX:
11986 case IMUL32rri_NF:
11987 case IMUL64m:
11988 case IMUL64m_EVEX:
11989 case IMUL64m_NF:
11990 case IMUL64r:
11991 case IMUL64r_EVEX:
11992 case IMUL64r_NF:
11993 case IMUL64rm:
11994 case IMUL64rm_EVEX:
11995 case IMUL64rm_ND:
11996 case IMUL64rm_NF:
11997 case IMUL64rm_NF_ND:
11998 case IMUL64rmi32:
11999 case IMUL64rmi32_EVEX:
12000 case IMUL64rmi32_NF:
12001 case IMUL64rmi8:
12002 case IMUL64rmi8_EVEX:
12003 case IMUL64rmi8_NF:
12004 case IMUL64rr:
12005 case IMUL64rr_EVEX:
12006 case IMUL64rr_ND:
12007 case IMUL64rr_NF:
12008 case IMUL64rr_NF_ND:
12009 case IMUL64rri32:
12010 case IMUL64rri32_EVEX:
12011 case IMUL64rri32_NF:
12012 case IMUL64rri8:
12013 case IMUL64rri8_EVEX:
12014 case IMUL64rri8_NF:
12015 case IMUL8m:
12016 case IMUL8m_EVEX:
12017 case IMUL8m_NF:
12018 case IMUL8r:
12019 case IMUL8r_EVEX:
12020 case IMUL8r_NF:
12021 return true;
12022 }
12023 return false;
12024}
12025
12026bool isVCVTSS2SI(unsigned Opcode) {
12027 switch (Opcode) {
12028 case VCVTSS2SI64Zrm_Int:
12029 case VCVTSS2SI64Zrr_Int:
12030 case VCVTSS2SI64Zrrb_Int:
12031 case VCVTSS2SI64rm_Int:
12032 case VCVTSS2SI64rr_Int:
12033 case VCVTSS2SIZrm_Int:
12034 case VCVTSS2SIZrr_Int:
12035 case VCVTSS2SIZrrb_Int:
12036 case VCVTSS2SIrm_Int:
12037 case VCVTSS2SIrr_Int:
12038 return true;
12039 }
12040 return false;
12041}
12042
12043bool isPUSHAW(unsigned Opcode) {
12044 return Opcode == PUSHA16;
12045}
12046
12047bool isSTOSD(unsigned Opcode) {
12048 return Opcode == STOSL;
12049}
12050
12051bool isPSRLDQ(unsigned Opcode) {
12052 return Opcode == PSRLDQri;
12053}
12054
12055bool isVSCATTERQPS(unsigned Opcode) {
12056 switch (Opcode) {
12057 case VSCATTERQPSZ128mr:
12058 case VSCATTERQPSZ256mr:
12059 case VSCATTERQPSZmr:
12060 return true;
12061 }
12062 return false;
12063}
12064
12065bool isFIDIV(unsigned Opcode) {
12066 switch (Opcode) {
12067 case DIV_FI16m:
12068 case DIV_FI32m:
12069 return true;
12070 }
12071 return false;
12072}
12073
12074bool isVFMSUB213PD(unsigned Opcode) {
12075 switch (Opcode) {
12076 case VFMSUB213PDYm:
12077 case VFMSUB213PDYr:
12078 case VFMSUB213PDZ128m:
12079 case VFMSUB213PDZ128mb:
12080 case VFMSUB213PDZ128mbk:
12081 case VFMSUB213PDZ128mbkz:
12082 case VFMSUB213PDZ128mk:
12083 case VFMSUB213PDZ128mkz:
12084 case VFMSUB213PDZ128r:
12085 case VFMSUB213PDZ128rk:
12086 case VFMSUB213PDZ128rkz:
12087 case VFMSUB213PDZ256m:
12088 case VFMSUB213PDZ256mb:
12089 case VFMSUB213PDZ256mbk:
12090 case VFMSUB213PDZ256mbkz:
12091 case VFMSUB213PDZ256mk:
12092 case VFMSUB213PDZ256mkz:
12093 case VFMSUB213PDZ256r:
12094 case VFMSUB213PDZ256rk:
12095 case VFMSUB213PDZ256rkz:
12096 case VFMSUB213PDZm:
12097 case VFMSUB213PDZmb:
12098 case VFMSUB213PDZmbk:
12099 case VFMSUB213PDZmbkz:
12100 case VFMSUB213PDZmk:
12101 case VFMSUB213PDZmkz:
12102 case VFMSUB213PDZr:
12103 case VFMSUB213PDZrb:
12104 case VFMSUB213PDZrbk:
12105 case VFMSUB213PDZrbkz:
12106 case VFMSUB213PDZrk:
12107 case VFMSUB213PDZrkz:
12108 case VFMSUB213PDm:
12109 case VFMSUB213PDr:
12110 return true;
12111 }
12112 return false;
12113}
12114
12115bool isVFMADDSUB231PH(unsigned Opcode) {
12116 switch (Opcode) {
12117 case VFMADDSUB231PHZ128m:
12118 case VFMADDSUB231PHZ128mb:
12119 case VFMADDSUB231PHZ128mbk:
12120 case VFMADDSUB231PHZ128mbkz:
12121 case VFMADDSUB231PHZ128mk:
12122 case VFMADDSUB231PHZ128mkz:
12123 case VFMADDSUB231PHZ128r:
12124 case VFMADDSUB231PHZ128rk:
12125 case VFMADDSUB231PHZ128rkz:
12126 case VFMADDSUB231PHZ256m:
12127 case VFMADDSUB231PHZ256mb:
12128 case VFMADDSUB231PHZ256mbk:
12129 case VFMADDSUB231PHZ256mbkz:
12130 case VFMADDSUB231PHZ256mk:
12131 case VFMADDSUB231PHZ256mkz:
12132 case VFMADDSUB231PHZ256r:
12133 case VFMADDSUB231PHZ256rk:
12134 case VFMADDSUB231PHZ256rkz:
12135 case VFMADDSUB231PHZm:
12136 case VFMADDSUB231PHZmb:
12137 case VFMADDSUB231PHZmbk:
12138 case VFMADDSUB231PHZmbkz:
12139 case VFMADDSUB231PHZmk:
12140 case VFMADDSUB231PHZmkz:
12141 case VFMADDSUB231PHZr:
12142 case VFMADDSUB231PHZrb:
12143 case VFMADDSUB231PHZrbk:
12144 case VFMADDSUB231PHZrbkz:
12145 case VFMADDSUB231PHZrk:
12146 case VFMADDSUB231PHZrkz:
12147 return true;
12148 }
12149 return false;
12150}
12151
12152bool isTDCALL(unsigned Opcode) {
12153 return Opcode == TDCALL;
12154}
12155
12156bool isPVALIDATE(unsigned Opcode) {
12157 switch (Opcode) {
12158 case PVALIDATE32:
12159 case PVALIDATE64:
12160 return true;
12161 }
12162 return false;
12163}
12164
12165bool isVPSHUFLW(unsigned Opcode) {
12166 switch (Opcode) {
12167 case VPSHUFLWYmi:
12168 case VPSHUFLWYri:
12169 case VPSHUFLWZ128mi:
12170 case VPSHUFLWZ128mik:
12171 case VPSHUFLWZ128mikz:
12172 case VPSHUFLWZ128ri:
12173 case VPSHUFLWZ128rik:
12174 case VPSHUFLWZ128rikz:
12175 case VPSHUFLWZ256mi:
12176 case VPSHUFLWZ256mik:
12177 case VPSHUFLWZ256mikz:
12178 case VPSHUFLWZ256ri:
12179 case VPSHUFLWZ256rik:
12180 case VPSHUFLWZ256rikz:
12181 case VPSHUFLWZmi:
12182 case VPSHUFLWZmik:
12183 case VPSHUFLWZmikz:
12184 case VPSHUFLWZri:
12185 case VPSHUFLWZrik:
12186 case VPSHUFLWZrikz:
12187 case VPSHUFLWmi:
12188 case VPSHUFLWri:
12189 return true;
12190 }
12191 return false;
12192}
12193
12194bool isPCLMULQDQ(unsigned Opcode) {
12195 switch (Opcode) {
12196 case PCLMULQDQrmi:
12197 case PCLMULQDQrri:
12198 return true;
12199 }
12200 return false;
12201}
12202
12203bool isCMPXCHG8B(unsigned Opcode) {
12204 return Opcode == CMPXCHG8B;
12205}
12206
12207bool isVPMOVM2B(unsigned Opcode) {
12208 switch (Opcode) {
12209 case VPMOVM2BZ128rk:
12210 case VPMOVM2BZ256rk:
12211 case VPMOVM2BZrk:
12212 return true;
12213 }
12214 return false;
12215}
12216
12217bool isVCVTUDQ2PH(unsigned Opcode) {
12218 switch (Opcode) {
12219 case VCVTUDQ2PHZ128rm:
12220 case VCVTUDQ2PHZ128rmb:
12221 case VCVTUDQ2PHZ128rmbk:
12222 case VCVTUDQ2PHZ128rmbkz:
12223 case VCVTUDQ2PHZ128rmk:
12224 case VCVTUDQ2PHZ128rmkz:
12225 case VCVTUDQ2PHZ128rr:
12226 case VCVTUDQ2PHZ128rrk:
12227 case VCVTUDQ2PHZ128rrkz:
12228 case VCVTUDQ2PHZ256rm:
12229 case VCVTUDQ2PHZ256rmb:
12230 case VCVTUDQ2PHZ256rmbk:
12231 case VCVTUDQ2PHZ256rmbkz:
12232 case VCVTUDQ2PHZ256rmk:
12233 case VCVTUDQ2PHZ256rmkz:
12234 case VCVTUDQ2PHZ256rr:
12235 case VCVTUDQ2PHZ256rrk:
12236 case VCVTUDQ2PHZ256rrkz:
12237 case VCVTUDQ2PHZrm:
12238 case VCVTUDQ2PHZrmb:
12239 case VCVTUDQ2PHZrmbk:
12240 case VCVTUDQ2PHZrmbkz:
12241 case VCVTUDQ2PHZrmk:
12242 case VCVTUDQ2PHZrmkz:
12243 case VCVTUDQ2PHZrr:
12244 case VCVTUDQ2PHZrrb:
12245 case VCVTUDQ2PHZrrbk:
12246 case VCVTUDQ2PHZrrbkz:
12247 case VCVTUDQ2PHZrrk:
12248 case VCVTUDQ2PHZrrkz:
12249 return true;
12250 }
12251 return false;
12252}
12253
12254bool isPEXTRQ(unsigned Opcode) {
12255 switch (Opcode) {
12256 case PEXTRQmri:
12257 case PEXTRQrri:
12258 return true;
12259 }
12260 return false;
12261}
12262
12263bool isXCRYPTCTR(unsigned Opcode) {
12264 return Opcode == XCRYPTCTR;
12265}
12266
12267bool isVREDUCEPH(unsigned Opcode) {
12268 switch (Opcode) {
12269 case VREDUCEPHZ128rmbi:
12270 case VREDUCEPHZ128rmbik:
12271 case VREDUCEPHZ128rmbikz:
12272 case VREDUCEPHZ128rmi:
12273 case VREDUCEPHZ128rmik:
12274 case VREDUCEPHZ128rmikz:
12275 case VREDUCEPHZ128rri:
12276 case VREDUCEPHZ128rrik:
12277 case VREDUCEPHZ128rrikz:
12278 case VREDUCEPHZ256rmbi:
12279 case VREDUCEPHZ256rmbik:
12280 case VREDUCEPHZ256rmbikz:
12281 case VREDUCEPHZ256rmi:
12282 case VREDUCEPHZ256rmik:
12283 case VREDUCEPHZ256rmikz:
12284 case VREDUCEPHZ256rri:
12285 case VREDUCEPHZ256rrik:
12286 case VREDUCEPHZ256rrikz:
12287 case VREDUCEPHZrmbi:
12288 case VREDUCEPHZrmbik:
12289 case VREDUCEPHZrmbikz:
12290 case VREDUCEPHZrmi:
12291 case VREDUCEPHZrmik:
12292 case VREDUCEPHZrmikz:
12293 case VREDUCEPHZrri:
12294 case VREDUCEPHZrrib:
12295 case VREDUCEPHZrribk:
12296 case VREDUCEPHZrribkz:
12297 case VREDUCEPHZrrik:
12298 case VREDUCEPHZrrikz:
12299 return true;
12300 }
12301 return false;
12302}
12303
12304bool isUCOMISD(unsigned Opcode) {
12305 switch (Opcode) {
12306 case UCOMISDrm:
12307 case UCOMISDrr:
12308 return true;
12309 }
12310 return false;
12311}
12312
12313bool isOUTSD(unsigned Opcode) {
12314 return Opcode == OUTSL;
12315}
12316
12317bool isSUBSS(unsigned Opcode) {
12318 switch (Opcode) {
12319 case SUBSSrm_Int:
12320 case SUBSSrr_Int:
12321 return true;
12322 }
12323 return false;
12324}
12325
12326bool isVFMSUBPS(unsigned Opcode) {
12327 switch (Opcode) {
12328 case VFMSUBPS4Ymr:
12329 case VFMSUBPS4Yrm:
12330 case VFMSUBPS4Yrr:
12331 case VFMSUBPS4Yrr_REV:
12332 case VFMSUBPS4mr:
12333 case VFMSUBPS4rm:
12334 case VFMSUBPS4rr:
12335 case VFMSUBPS4rr_REV:
12336 return true;
12337 }
12338 return false;
12339}
12340
12341bool isVPBLENDW(unsigned Opcode) {
12342 switch (Opcode) {
12343 case VPBLENDWYrmi:
12344 case VPBLENDWYrri:
12345 case VPBLENDWrmi:
12346 case VPBLENDWrri:
12347 return true;
12348 }
12349 return false;
12350}
12351
12352bool isBZHI(unsigned Opcode) {
12353 switch (Opcode) {
12354 case BZHI32rm:
12355 case BZHI32rm_EVEX:
12356 case BZHI32rm_NF:
12357 case BZHI32rr:
12358 case BZHI32rr_EVEX:
12359 case BZHI32rr_NF:
12360 case BZHI64rm:
12361 case BZHI64rm_EVEX:
12362 case BZHI64rm_NF:
12363 case BZHI64rr:
12364 case BZHI64rr_EVEX:
12365 case BZHI64rr_NF:
12366 return true;
12367 }
12368 return false;
12369}
12370
12371bool isVPRORVD(unsigned Opcode) {
12372 switch (Opcode) {
12373 case VPRORVDZ128rm:
12374 case VPRORVDZ128rmb:
12375 case VPRORVDZ128rmbk:
12376 case VPRORVDZ128rmbkz:
12377 case VPRORVDZ128rmk:
12378 case VPRORVDZ128rmkz:
12379 case VPRORVDZ128rr:
12380 case VPRORVDZ128rrk:
12381 case VPRORVDZ128rrkz:
12382 case VPRORVDZ256rm:
12383 case VPRORVDZ256rmb:
12384 case VPRORVDZ256rmbk:
12385 case VPRORVDZ256rmbkz:
12386 case VPRORVDZ256rmk:
12387 case VPRORVDZ256rmkz:
12388 case VPRORVDZ256rr:
12389 case VPRORVDZ256rrk:
12390 case VPRORVDZ256rrkz:
12391 case VPRORVDZrm:
12392 case VPRORVDZrmb:
12393 case VPRORVDZrmbk:
12394 case VPRORVDZrmbkz:
12395 case VPRORVDZrmk:
12396 case VPRORVDZrmkz:
12397 case VPRORVDZrr:
12398 case VPRORVDZrrk:
12399 case VPRORVDZrrkz:
12400 return true;
12401 }
12402 return false;
12403}
12404
12405bool isRMPQUERY(unsigned Opcode) {
12406 return Opcode == RMPQUERY;
12407}
12408
12409bool isVPEXPANDB(unsigned Opcode) {
12410 switch (Opcode) {
12411 case VPEXPANDBZ128rm:
12412 case VPEXPANDBZ128rmk:
12413 case VPEXPANDBZ128rmkz:
12414 case VPEXPANDBZ128rr:
12415 case VPEXPANDBZ128rrk:
12416 case VPEXPANDBZ128rrkz:
12417 case VPEXPANDBZ256rm:
12418 case VPEXPANDBZ256rmk:
12419 case VPEXPANDBZ256rmkz:
12420 case VPEXPANDBZ256rr:
12421 case VPEXPANDBZ256rrk:
12422 case VPEXPANDBZ256rrkz:
12423 case VPEXPANDBZrm:
12424 case VPEXPANDBZrmk:
12425 case VPEXPANDBZrmkz:
12426 case VPEXPANDBZrr:
12427 case VPEXPANDBZrrk:
12428 case VPEXPANDBZrrkz:
12429 return true;
12430 }
12431 return false;
12432}
12433
12434bool isVPSCATTERDQ(unsigned Opcode) {
12435 switch (Opcode) {
12436 case VPSCATTERDQZ128mr:
12437 case VPSCATTERDQZ256mr:
12438 case VPSCATTERDQZmr:
12439 return true;
12440 }
12441 return false;
12442}
12443
12444bool isPSMASH(unsigned Opcode) {
12445 return Opcode == PSMASH;
12446}
12447
12448bool isVPSHLDQ(unsigned Opcode) {
12449 switch (Opcode) {
12450 case VPSHLDQZ128rmbi:
12451 case VPSHLDQZ128rmbik:
12452 case VPSHLDQZ128rmbikz:
12453 case VPSHLDQZ128rmi:
12454 case VPSHLDQZ128rmik:
12455 case VPSHLDQZ128rmikz:
12456 case VPSHLDQZ128rri:
12457 case VPSHLDQZ128rrik:
12458 case VPSHLDQZ128rrikz:
12459 case VPSHLDQZ256rmbi:
12460 case VPSHLDQZ256rmbik:
12461 case VPSHLDQZ256rmbikz:
12462 case VPSHLDQZ256rmi:
12463 case VPSHLDQZ256rmik:
12464 case VPSHLDQZ256rmikz:
12465 case VPSHLDQZ256rri:
12466 case VPSHLDQZ256rrik:
12467 case VPSHLDQZ256rrikz:
12468 case VPSHLDQZrmbi:
12469 case VPSHLDQZrmbik:
12470 case VPSHLDQZrmbikz:
12471 case VPSHLDQZrmi:
12472 case VPSHLDQZrmik:
12473 case VPSHLDQZrmikz:
12474 case VPSHLDQZrri:
12475 case VPSHLDQZrrik:
12476 case VPSHLDQZrrikz:
12477 return true;
12478 }
12479 return false;
12480}
12481
12482bool isVSCATTERPF1DPD(unsigned Opcode) {
12483 return Opcode == VSCATTERPF1DPDm;
12484}
12485
12486bool isMONTMUL(unsigned Opcode) {
12487 return Opcode == MONTMUL;
12488}
12489
12490bool isVCVTPH2UQQ(unsigned Opcode) {
12491 switch (Opcode) {
12492 case VCVTPH2UQQZ128rm:
12493 case VCVTPH2UQQZ128rmb:
12494 case VCVTPH2UQQZ128rmbk:
12495 case VCVTPH2UQQZ128rmbkz:
12496 case VCVTPH2UQQZ128rmk:
12497 case VCVTPH2UQQZ128rmkz:
12498 case VCVTPH2UQQZ128rr:
12499 case VCVTPH2UQQZ128rrk:
12500 case VCVTPH2UQQZ128rrkz:
12501 case VCVTPH2UQQZ256rm:
12502 case VCVTPH2UQQZ256rmb:
12503 case VCVTPH2UQQZ256rmbk:
12504 case VCVTPH2UQQZ256rmbkz:
12505 case VCVTPH2UQQZ256rmk:
12506 case VCVTPH2UQQZ256rmkz:
12507 case VCVTPH2UQQZ256rr:
12508 case VCVTPH2UQQZ256rrk:
12509 case VCVTPH2UQQZ256rrkz:
12510 case VCVTPH2UQQZrm:
12511 case VCVTPH2UQQZrmb:
12512 case VCVTPH2UQQZrmbk:
12513 case VCVTPH2UQQZrmbkz:
12514 case VCVTPH2UQQZrmk:
12515 case VCVTPH2UQQZrmkz:
12516 case VCVTPH2UQQZrr:
12517 case VCVTPH2UQQZrrb:
12518 case VCVTPH2UQQZrrbk:
12519 case VCVTPH2UQQZrrbkz:
12520 case VCVTPH2UQQZrrk:
12521 case VCVTPH2UQQZrrkz:
12522 return true;
12523 }
12524 return false;
12525}
12526
12527bool isPSLLD(unsigned Opcode) {
12528 switch (Opcode) {
12529 case MMX_PSLLDri:
12530 case MMX_PSLLDrm:
12531 case MMX_PSLLDrr:
12532 case PSLLDri:
12533 case PSLLDrm:
12534 case PSLLDrr:
12535 return true;
12536 }
12537 return false;
12538}
12539
12540bool isSAR(unsigned Opcode) {
12541 switch (Opcode) {
12542 case SAR16m1:
12543 case SAR16m1_EVEX:
12544 case SAR16m1_ND:
12545 case SAR16m1_NF:
12546 case SAR16m1_NF_ND:
12547 case SAR16mCL:
12548 case SAR16mCL_EVEX:
12549 case SAR16mCL_ND:
12550 case SAR16mCL_NF:
12551 case SAR16mCL_NF_ND:
12552 case SAR16mi:
12553 case SAR16mi_EVEX:
12554 case SAR16mi_ND:
12555 case SAR16mi_NF:
12556 case SAR16mi_NF_ND:
12557 case SAR16r1:
12558 case SAR16r1_EVEX:
12559 case SAR16r1_ND:
12560 case SAR16r1_NF:
12561 case SAR16r1_NF_ND:
12562 case SAR16rCL:
12563 case SAR16rCL_EVEX:
12564 case SAR16rCL_ND:
12565 case SAR16rCL_NF:
12566 case SAR16rCL_NF_ND:
12567 case SAR16ri:
12568 case SAR16ri_EVEX:
12569 case SAR16ri_ND:
12570 case SAR16ri_NF:
12571 case SAR16ri_NF_ND:
12572 case SAR32m1:
12573 case SAR32m1_EVEX:
12574 case SAR32m1_ND:
12575 case SAR32m1_NF:
12576 case SAR32m1_NF_ND:
12577 case SAR32mCL:
12578 case SAR32mCL_EVEX:
12579 case SAR32mCL_ND:
12580 case SAR32mCL_NF:
12581 case SAR32mCL_NF_ND:
12582 case SAR32mi:
12583 case SAR32mi_EVEX:
12584 case SAR32mi_ND:
12585 case SAR32mi_NF:
12586 case SAR32mi_NF_ND:
12587 case SAR32r1:
12588 case SAR32r1_EVEX:
12589 case SAR32r1_ND:
12590 case SAR32r1_NF:
12591 case SAR32r1_NF_ND:
12592 case SAR32rCL:
12593 case SAR32rCL_EVEX:
12594 case SAR32rCL_ND:
12595 case SAR32rCL_NF:
12596 case SAR32rCL_NF_ND:
12597 case SAR32ri:
12598 case SAR32ri_EVEX:
12599 case SAR32ri_ND:
12600 case SAR32ri_NF:
12601 case SAR32ri_NF_ND:
12602 case SAR64m1:
12603 case SAR64m1_EVEX:
12604 case SAR64m1_ND:
12605 case SAR64m1_NF:
12606 case SAR64m1_NF_ND:
12607 case SAR64mCL:
12608 case SAR64mCL_EVEX:
12609 case SAR64mCL_ND:
12610 case SAR64mCL_NF:
12611 case SAR64mCL_NF_ND:
12612 case SAR64mi:
12613 case SAR64mi_EVEX:
12614 case SAR64mi_ND:
12615 case SAR64mi_NF:
12616 case SAR64mi_NF_ND:
12617 case SAR64r1:
12618 case SAR64r1_EVEX:
12619 case SAR64r1_ND:
12620 case SAR64r1_NF:
12621 case SAR64r1_NF_ND:
12622 case SAR64rCL:
12623 case SAR64rCL_EVEX:
12624 case SAR64rCL_ND:
12625 case SAR64rCL_NF:
12626 case SAR64rCL_NF_ND:
12627 case SAR64ri:
12628 case SAR64ri_EVEX:
12629 case SAR64ri_ND:
12630 case SAR64ri_NF:
12631 case SAR64ri_NF_ND:
12632 case SAR8m1:
12633 case SAR8m1_EVEX:
12634 case SAR8m1_ND:
12635 case SAR8m1_NF:
12636 case SAR8m1_NF_ND:
12637 case SAR8mCL:
12638 case SAR8mCL_EVEX:
12639 case SAR8mCL_ND:
12640 case SAR8mCL_NF:
12641 case SAR8mCL_NF_ND:
12642 case SAR8mi:
12643 case SAR8mi_EVEX:
12644 case SAR8mi_ND:
12645 case SAR8mi_NF:
12646 case SAR8mi_NF_ND:
12647 case SAR8r1:
12648 case SAR8r1_EVEX:
12649 case SAR8r1_ND:
12650 case SAR8r1_NF:
12651 case SAR8r1_NF_ND:
12652 case SAR8rCL:
12653 case SAR8rCL_EVEX:
12654 case SAR8rCL_ND:
12655 case SAR8rCL_NF:
12656 case SAR8rCL_NF_ND:
12657 case SAR8ri:
12658 case SAR8ri_EVEX:
12659 case SAR8ri_ND:
12660 case SAR8ri_NF:
12661 case SAR8ri_NF_ND:
12662 return true;
12663 }
12664 return false;
12665}
12666
12667bool isLDTILECFG(unsigned Opcode) {
12668 switch (Opcode) {
12669 case LDTILECFG:
12670 case LDTILECFG_EVEX:
12671 return true;
12672 }
12673 return false;
12674}
12675
12676bool isPMINUB(unsigned Opcode) {
12677 switch (Opcode) {
12678 case MMX_PMINUBrm:
12679 case MMX_PMINUBrr:
12680 case PMINUBrm:
12681 case PMINUBrr:
12682 return true;
12683 }
12684 return false;
12685}
12686
12687bool isVCVTNEEBF162PS(unsigned Opcode) {
12688 switch (Opcode) {
12689 case VCVTNEEBF162PSYrm:
12690 case VCVTNEEBF162PSrm:
12691 return true;
12692 }
12693 return false;
12694}
12695
12696bool isMOVDIR64B(unsigned Opcode) {
12697 switch (Opcode) {
12698 case MOVDIR64B16:
12699 case MOVDIR64B32:
12700 case MOVDIR64B32_EVEX:
12701 case MOVDIR64B64:
12702 case MOVDIR64B64_EVEX:
12703 return true;
12704 }
12705 return false;
12706}
12707
12708bool isSTR(unsigned Opcode) {
12709 switch (Opcode) {
12710 case STR16r:
12711 case STR32r:
12712 case STR64r:
12713 case STRm:
12714 return true;
12715 }
12716 return false;
12717}
12718
12719bool isKANDNQ(unsigned Opcode) {
12720 return Opcode == KANDNQkk;
12721}
12722
12723bool isBSF(unsigned Opcode) {
12724 switch (Opcode) {
12725 case BSF16rm:
12726 case BSF16rr:
12727 case BSF32rm:
12728 case BSF32rr:
12729 case BSF64rm:
12730 case BSF64rr:
12731 return true;
12732 }
12733 return false;
12734}
12735
12736bool isVPDPBUUDS(unsigned Opcode) {
12737 switch (Opcode) {
12738 case VPDPBUUDSYrm:
12739 case VPDPBUUDSYrr:
12740 case VPDPBUUDSZ128m:
12741 case VPDPBUUDSZ128mb:
12742 case VPDPBUUDSZ128mbk:
12743 case VPDPBUUDSZ128mbkz:
12744 case VPDPBUUDSZ128mk:
12745 case VPDPBUUDSZ128mkz:
12746 case VPDPBUUDSZ128r:
12747 case VPDPBUUDSZ128rk:
12748 case VPDPBUUDSZ128rkz:
12749 case VPDPBUUDSZ256m:
12750 case VPDPBUUDSZ256mb:
12751 case VPDPBUUDSZ256mbk:
12752 case VPDPBUUDSZ256mbkz:
12753 case VPDPBUUDSZ256mk:
12754 case VPDPBUUDSZ256mkz:
12755 case VPDPBUUDSZ256r:
12756 case VPDPBUUDSZ256rk:
12757 case VPDPBUUDSZ256rkz:
12758 case VPDPBUUDSZm:
12759 case VPDPBUUDSZmb:
12760 case VPDPBUUDSZmbk:
12761 case VPDPBUUDSZmbkz:
12762 case VPDPBUUDSZmk:
12763 case VPDPBUUDSZmkz:
12764 case VPDPBUUDSZr:
12765 case VPDPBUUDSZrk:
12766 case VPDPBUUDSZrkz:
12767 case VPDPBUUDSrm:
12768 case VPDPBUUDSrr:
12769 return true;
12770 }
12771 return false;
12772}
12773
12774bool isINCSSPD(unsigned Opcode) {
12775 return Opcode == INCSSPD;
12776}
12777
12778bool isSQRTPS(unsigned Opcode) {
12779 switch (Opcode) {
12780 case SQRTPSm:
12781 case SQRTPSr:
12782 return true;
12783 }
12784 return false;
12785}
12786
12787bool isTTRANSPOSED(unsigned Opcode) {
12788 return Opcode == TTRANSPOSED;
12789}
12790
12791bool isCMPXCHG(unsigned Opcode) {
12792 switch (Opcode) {
12793 case CMPXCHG16rm:
12794 case CMPXCHG16rr:
12795 case CMPXCHG32rm:
12796 case CMPXCHG32rr:
12797 case CMPXCHG64rm:
12798 case CMPXCHG64rr:
12799 case CMPXCHG8rm:
12800 case CMPXCHG8rr:
12801 return true;
12802 }
12803 return false;
12804}
12805
12806bool isVPSIGNW(unsigned Opcode) {
12807 switch (Opcode) {
12808 case VPSIGNWYrm:
12809 case VPSIGNWYrr:
12810 case VPSIGNWrm:
12811 case VPSIGNWrr:
12812 return true;
12813 }
12814 return false;
12815}
12816
12817bool isVCOMISBF16(unsigned Opcode) {
12818 switch (Opcode) {
12819 case VCOMISBF16Zrm:
12820 case VCOMISBF16Zrr:
12821 return true;
12822 }
12823 return false;
12824}
12825
12826bool isLES(unsigned Opcode) {
12827 switch (Opcode) {
12828 case LES16rm:
12829 case LES32rm:
12830 return true;
12831 }
12832 return false;
12833}
12834
12835bool isCVTSS2SI(unsigned Opcode) {
12836 switch (Opcode) {
12837 case CVTSS2SI64rm_Int:
12838 case CVTSS2SI64rr_Int:
12839 case CVTSS2SIrm_Int:
12840 case CVTSS2SIrr_Int:
12841 return true;
12842 }
12843 return false;
12844}
12845
12846bool isVPMOVUSWB(unsigned Opcode) {
12847 switch (Opcode) {
12848 case VPMOVUSWBZ128mr:
12849 case VPMOVUSWBZ128mrk:
12850 case VPMOVUSWBZ128rr:
12851 case VPMOVUSWBZ128rrk:
12852 case VPMOVUSWBZ128rrkz:
12853 case VPMOVUSWBZ256mr:
12854 case VPMOVUSWBZ256mrk:
12855 case VPMOVUSWBZ256rr:
12856 case VPMOVUSWBZ256rrk:
12857 case VPMOVUSWBZ256rrkz:
12858 case VPMOVUSWBZmr:
12859 case VPMOVUSWBZmrk:
12860 case VPMOVUSWBZrr:
12861 case VPMOVUSWBZrrk:
12862 case VPMOVUSWBZrrkz:
12863 return true;
12864 }
12865 return false;
12866}
12867
12868bool isFCOMPI(unsigned Opcode) {
12869 return Opcode == COM_FIPr;
12870}
12871
12872bool isPUNPCKHWD(unsigned Opcode) {
12873 switch (Opcode) {
12874 case MMX_PUNPCKHWDrm:
12875 case MMX_PUNPCKHWDrr:
12876 case PUNPCKHWDrm:
12877 case PUNPCKHWDrr:
12878 return true;
12879 }
12880 return false;
12881}
12882
12883bool isPFACC(unsigned Opcode) {
12884 switch (Opcode) {
12885 case PFACCrm:
12886 case PFACCrr:
12887 return true;
12888 }
12889 return false;
12890}
12891
12892bool isVPTESTNMW(unsigned Opcode) {
12893 switch (Opcode) {
12894 case VPTESTNMWZ128rm:
12895 case VPTESTNMWZ128rmk:
12896 case VPTESTNMWZ128rr:
12897 case VPTESTNMWZ128rrk:
12898 case VPTESTNMWZ256rm:
12899 case VPTESTNMWZ256rmk:
12900 case VPTESTNMWZ256rr:
12901 case VPTESTNMWZ256rrk:
12902 case VPTESTNMWZrm:
12903 case VPTESTNMWZrmk:
12904 case VPTESTNMWZrr:
12905 case VPTESTNMWZrrk:
12906 return true;
12907 }
12908 return false;
12909}
12910
12911bool isVPMULDQ(unsigned Opcode) {
12912 switch (Opcode) {
12913 case VPMULDQYrm:
12914 case VPMULDQYrr:
12915 case VPMULDQZ128rm:
12916 case VPMULDQZ128rmb:
12917 case VPMULDQZ128rmbk:
12918 case VPMULDQZ128rmbkz:
12919 case VPMULDQZ128rmk:
12920 case VPMULDQZ128rmkz:
12921 case VPMULDQZ128rr:
12922 case VPMULDQZ128rrk:
12923 case VPMULDQZ128rrkz:
12924 case VPMULDQZ256rm:
12925 case VPMULDQZ256rmb:
12926 case VPMULDQZ256rmbk:
12927 case VPMULDQZ256rmbkz:
12928 case VPMULDQZ256rmk:
12929 case VPMULDQZ256rmkz:
12930 case VPMULDQZ256rr:
12931 case VPMULDQZ256rrk:
12932 case VPMULDQZ256rrkz:
12933 case VPMULDQZrm:
12934 case VPMULDQZrmb:
12935 case VPMULDQZrmbk:
12936 case VPMULDQZrmbkz:
12937 case VPMULDQZrmk:
12938 case VPMULDQZrmkz:
12939 case VPMULDQZrr:
12940 case VPMULDQZrrk:
12941 case VPMULDQZrrkz:
12942 case VPMULDQrm:
12943 case VPMULDQrr:
12944 return true;
12945 }
12946 return false;
12947}
12948
12949bool isSHRX(unsigned Opcode) {
12950 switch (Opcode) {
12951 case SHRX32rm:
12952 case SHRX32rm_EVEX:
12953 case SHRX32rr:
12954 case SHRX32rr_EVEX:
12955 case SHRX64rm:
12956 case SHRX64rm_EVEX:
12957 case SHRX64rr:
12958 case SHRX64rr_EVEX:
12959 return true;
12960 }
12961 return false;
12962}
12963
12964bool isKXORQ(unsigned Opcode) {
12965 return Opcode == KXORQkk;
12966}
12967
12968bool isVGETEXPSD(unsigned Opcode) {
12969 switch (Opcode) {
12970 case VGETEXPSDZm:
12971 case VGETEXPSDZmk:
12972 case VGETEXPSDZmkz:
12973 case VGETEXPSDZr:
12974 case VGETEXPSDZrb:
12975 case VGETEXPSDZrbk:
12976 case VGETEXPSDZrbkz:
12977 case VGETEXPSDZrk:
12978 case VGETEXPSDZrkz:
12979 return true;
12980 }
12981 return false;
12982}
12983
12984bool isV4FNMADDPS(unsigned Opcode) {
12985 switch (Opcode) {
12986 case V4FNMADDPSrm:
12987 case V4FNMADDPSrmk:
12988 case V4FNMADDPSrmkz:
12989 return true;
12990 }
12991 return false;
12992}
12993
12994bool isVFNMSUB231SD(unsigned Opcode) {
12995 switch (Opcode) {
12996 case VFNMSUB231SDZm_Int:
12997 case VFNMSUB231SDZmk_Int:
12998 case VFNMSUB231SDZmkz_Int:
12999 case VFNMSUB231SDZr_Int:
13000 case VFNMSUB231SDZrb_Int:
13001 case VFNMSUB231SDZrbk_Int:
13002 case VFNMSUB231SDZrbkz_Int:
13003 case VFNMSUB231SDZrk_Int:
13004 case VFNMSUB231SDZrkz_Int:
13005 case VFNMSUB231SDm_Int:
13006 case VFNMSUB231SDr_Int:
13007 return true;
13008 }
13009 return false;
13010}
13011
13012bool isVPSHLD(unsigned Opcode) {
13013 switch (Opcode) {
13014 case VPSHLDmr:
13015 case VPSHLDrm:
13016 case VPSHLDrr:
13017 case VPSHLDrr_REV:
13018 return true;
13019 }
13020 return false;
13021}
13022
13023bool isPAVGB(unsigned Opcode) {
13024 switch (Opcode) {
13025 case MMX_PAVGBrm:
13026 case MMX_PAVGBrr:
13027 case PAVGBrm:
13028 case PAVGBrr:
13029 return true;
13030 }
13031 return false;
13032}
13033
13034bool isPMOVZXBD(unsigned Opcode) {
13035 switch (Opcode) {
13036 case PMOVZXBDrm:
13037 case PMOVZXBDrr:
13038 return true;
13039 }
13040 return false;
13041}
13042
13043bool isKORTESTW(unsigned Opcode) {
13044 return Opcode == KORTESTWkk;
13045}
13046
13047bool isVSHUFPS(unsigned Opcode) {
13048 switch (Opcode) {
13049 case VSHUFPSYrmi:
13050 case VSHUFPSYrri:
13051 case VSHUFPSZ128rmbi:
13052 case VSHUFPSZ128rmbik:
13053 case VSHUFPSZ128rmbikz:
13054 case VSHUFPSZ128rmi:
13055 case VSHUFPSZ128rmik:
13056 case VSHUFPSZ128rmikz:
13057 case VSHUFPSZ128rri:
13058 case VSHUFPSZ128rrik:
13059 case VSHUFPSZ128rrikz:
13060 case VSHUFPSZ256rmbi:
13061 case VSHUFPSZ256rmbik:
13062 case VSHUFPSZ256rmbikz:
13063 case VSHUFPSZ256rmi:
13064 case VSHUFPSZ256rmik:
13065 case VSHUFPSZ256rmikz:
13066 case VSHUFPSZ256rri:
13067 case VSHUFPSZ256rrik:
13068 case VSHUFPSZ256rrikz:
13069 case VSHUFPSZrmbi:
13070 case VSHUFPSZrmbik:
13071 case VSHUFPSZrmbikz:
13072 case VSHUFPSZrmi:
13073 case VSHUFPSZrmik:
13074 case VSHUFPSZrmikz:
13075 case VSHUFPSZrri:
13076 case VSHUFPSZrrik:
13077 case VSHUFPSZrrikz:
13078 case VSHUFPSrmi:
13079 case VSHUFPSrri:
13080 return true;
13081 }
13082 return false;
13083}
13084
13085bool isAESENCWIDE128KL(unsigned Opcode) {
13086 return Opcode == AESENCWIDE128KL;
13087}
13088
13089bool isVPXORD(unsigned Opcode) {
13090 switch (Opcode) {
13091 case VPXORDZ128rm:
13092 case VPXORDZ128rmb:
13093 case VPXORDZ128rmbk:
13094 case VPXORDZ128rmbkz:
13095 case VPXORDZ128rmk:
13096 case VPXORDZ128rmkz:
13097 case VPXORDZ128rr:
13098 case VPXORDZ128rrk:
13099 case VPXORDZ128rrkz:
13100 case VPXORDZ256rm:
13101 case VPXORDZ256rmb:
13102 case VPXORDZ256rmbk:
13103 case VPXORDZ256rmbkz:
13104 case VPXORDZ256rmk:
13105 case VPXORDZ256rmkz:
13106 case VPXORDZ256rr:
13107 case VPXORDZ256rrk:
13108 case VPXORDZ256rrkz:
13109 case VPXORDZrm:
13110 case VPXORDZrmb:
13111 case VPXORDZrmbk:
13112 case VPXORDZrmbkz:
13113 case VPXORDZrmk:
13114 case VPXORDZrmkz:
13115 case VPXORDZrr:
13116 case VPXORDZrrk:
13117 case VPXORDZrrkz:
13118 return true;
13119 }
13120 return false;
13121}
13122
13123bool isVPSHAW(unsigned Opcode) {
13124 switch (Opcode) {
13125 case VPSHAWmr:
13126 case VPSHAWrm:
13127 case VPSHAWrr:
13128 case VPSHAWrr_REV:
13129 return true;
13130 }
13131 return false;
13132}
13133
13134bool isVFMSUB132BF16(unsigned Opcode) {
13135 switch (Opcode) {
13136 case VFMSUB132BF16Z128m:
13137 case VFMSUB132BF16Z128mb:
13138 case VFMSUB132BF16Z128mbk:
13139 case VFMSUB132BF16Z128mbkz:
13140 case VFMSUB132BF16Z128mk:
13141 case VFMSUB132BF16Z128mkz:
13142 case VFMSUB132BF16Z128r:
13143 case VFMSUB132BF16Z128rk:
13144 case VFMSUB132BF16Z128rkz:
13145 case VFMSUB132BF16Z256m:
13146 case VFMSUB132BF16Z256mb:
13147 case VFMSUB132BF16Z256mbk:
13148 case VFMSUB132BF16Z256mbkz:
13149 case VFMSUB132BF16Z256mk:
13150 case VFMSUB132BF16Z256mkz:
13151 case VFMSUB132BF16Z256r:
13152 case VFMSUB132BF16Z256rk:
13153 case VFMSUB132BF16Z256rkz:
13154 case VFMSUB132BF16Zm:
13155 case VFMSUB132BF16Zmb:
13156 case VFMSUB132BF16Zmbk:
13157 case VFMSUB132BF16Zmbkz:
13158 case VFMSUB132BF16Zmk:
13159 case VFMSUB132BF16Zmkz:
13160 case VFMSUB132BF16Zr:
13161 case VFMSUB132BF16Zrk:
13162 case VFMSUB132BF16Zrkz:
13163 return true;
13164 }
13165 return false;
13166}
13167
13168bool isVPERMT2B(unsigned Opcode) {
13169 switch (Opcode) {
13170 case VPERMT2BZ128rm:
13171 case VPERMT2BZ128rmk:
13172 case VPERMT2BZ128rmkz:
13173 case VPERMT2BZ128rr:
13174 case VPERMT2BZ128rrk:
13175 case VPERMT2BZ128rrkz:
13176 case VPERMT2BZ256rm:
13177 case VPERMT2BZ256rmk:
13178 case VPERMT2BZ256rmkz:
13179 case VPERMT2BZ256rr:
13180 case VPERMT2BZ256rrk:
13181 case VPERMT2BZ256rrkz:
13182 case VPERMT2BZrm:
13183 case VPERMT2BZrmk:
13184 case VPERMT2BZrmkz:
13185 case VPERMT2BZrr:
13186 case VPERMT2BZrrk:
13187 case VPERMT2BZrrkz:
13188 return true;
13189 }
13190 return false;
13191}
13192
13193bool isVFMADD213PD(unsigned Opcode) {
13194 switch (Opcode) {
13195 case VFMADD213PDYm:
13196 case VFMADD213PDYr:
13197 case VFMADD213PDZ128m:
13198 case VFMADD213PDZ128mb:
13199 case VFMADD213PDZ128mbk:
13200 case VFMADD213PDZ128mbkz:
13201 case VFMADD213PDZ128mk:
13202 case VFMADD213PDZ128mkz:
13203 case VFMADD213PDZ128r:
13204 case VFMADD213PDZ128rk:
13205 case VFMADD213PDZ128rkz:
13206 case VFMADD213PDZ256m:
13207 case VFMADD213PDZ256mb:
13208 case VFMADD213PDZ256mbk:
13209 case VFMADD213PDZ256mbkz:
13210 case VFMADD213PDZ256mk:
13211 case VFMADD213PDZ256mkz:
13212 case VFMADD213PDZ256r:
13213 case VFMADD213PDZ256rk:
13214 case VFMADD213PDZ256rkz:
13215 case VFMADD213PDZm:
13216 case VFMADD213PDZmb:
13217 case VFMADD213PDZmbk:
13218 case VFMADD213PDZmbkz:
13219 case VFMADD213PDZmk:
13220 case VFMADD213PDZmkz:
13221 case VFMADD213PDZr:
13222 case VFMADD213PDZrb:
13223 case VFMADD213PDZrbk:
13224 case VFMADD213PDZrbkz:
13225 case VFMADD213PDZrk:
13226 case VFMADD213PDZrkz:
13227 case VFMADD213PDm:
13228 case VFMADD213PDr:
13229 return true;
13230 }
13231 return false;
13232}
13233
13234bool isVPGATHERQD(unsigned Opcode) {
13235 switch (Opcode) {
13236 case VPGATHERQDYrm:
13237 case VPGATHERQDZ128rm:
13238 case VPGATHERQDZ256rm:
13239 case VPGATHERQDZrm:
13240 case VPGATHERQDrm:
13241 return true;
13242 }
13243 return false;
13244}
13245
13246bool isVFNMSUB213BF16(unsigned Opcode) {
13247 switch (Opcode) {
13248 case VFNMSUB213BF16Z128m:
13249 case VFNMSUB213BF16Z128mb:
13250 case VFNMSUB213BF16Z128mbk:
13251 case VFNMSUB213BF16Z128mbkz:
13252 case VFNMSUB213BF16Z128mk:
13253 case VFNMSUB213BF16Z128mkz:
13254 case VFNMSUB213BF16Z128r:
13255 case VFNMSUB213BF16Z128rk:
13256 case VFNMSUB213BF16Z128rkz:
13257 case VFNMSUB213BF16Z256m:
13258 case VFNMSUB213BF16Z256mb:
13259 case VFNMSUB213BF16Z256mbk:
13260 case VFNMSUB213BF16Z256mbkz:
13261 case VFNMSUB213BF16Z256mk:
13262 case VFNMSUB213BF16Z256mkz:
13263 case VFNMSUB213BF16Z256r:
13264 case VFNMSUB213BF16Z256rk:
13265 case VFNMSUB213BF16Z256rkz:
13266 case VFNMSUB213BF16Zm:
13267 case VFNMSUB213BF16Zmb:
13268 case VFNMSUB213BF16Zmbk:
13269 case VFNMSUB213BF16Zmbkz:
13270 case VFNMSUB213BF16Zmk:
13271 case VFNMSUB213BF16Zmkz:
13272 case VFNMSUB213BF16Zr:
13273 case VFNMSUB213BF16Zrk:
13274 case VFNMSUB213BF16Zrkz:
13275 return true;
13276 }
13277 return false;
13278}
13279
13280bool isVCVTPS2IBS(unsigned Opcode) {
13281 switch (Opcode) {
13282 case VCVTPS2IBSZ128rm:
13283 case VCVTPS2IBSZ128rmb:
13284 case VCVTPS2IBSZ128rmbk:
13285 case VCVTPS2IBSZ128rmbkz:
13286 case VCVTPS2IBSZ128rmk:
13287 case VCVTPS2IBSZ128rmkz:
13288 case VCVTPS2IBSZ128rr:
13289 case VCVTPS2IBSZ128rrk:
13290 case VCVTPS2IBSZ128rrkz:
13291 case VCVTPS2IBSZ256rm:
13292 case VCVTPS2IBSZ256rmb:
13293 case VCVTPS2IBSZ256rmbk:
13294 case VCVTPS2IBSZ256rmbkz:
13295 case VCVTPS2IBSZ256rmk:
13296 case VCVTPS2IBSZ256rmkz:
13297 case VCVTPS2IBSZ256rr:
13298 case VCVTPS2IBSZ256rrk:
13299 case VCVTPS2IBSZ256rrkz:
13300 case VCVTPS2IBSZrm:
13301 case VCVTPS2IBSZrmb:
13302 case VCVTPS2IBSZrmbk:
13303 case VCVTPS2IBSZrmbkz:
13304 case VCVTPS2IBSZrmk:
13305 case VCVTPS2IBSZrmkz:
13306 case VCVTPS2IBSZrr:
13307 case VCVTPS2IBSZrrb:
13308 case VCVTPS2IBSZrrbk:
13309 case VCVTPS2IBSZrrbkz:
13310 case VCVTPS2IBSZrrk:
13311 case VCVTPS2IBSZrrkz:
13312 return true;
13313 }
13314 return false;
13315}
13316
13317bool isVPCMPGTW(unsigned Opcode) {
13318 switch (Opcode) {
13319 case VPCMPGTWYrm:
13320 case VPCMPGTWYrr:
13321 case VPCMPGTWZ128rm:
13322 case VPCMPGTWZ128rmk:
13323 case VPCMPGTWZ128rr:
13324 case VPCMPGTWZ128rrk:
13325 case VPCMPGTWZ256rm:
13326 case VPCMPGTWZ256rmk:
13327 case VPCMPGTWZ256rr:
13328 case VPCMPGTWZ256rrk:
13329 case VPCMPGTWZrm:
13330 case VPCMPGTWZrmk:
13331 case VPCMPGTWZrr:
13332 case VPCMPGTWZrrk:
13333 case VPCMPGTWrm:
13334 case VPCMPGTWrr:
13335 return true;
13336 }
13337 return false;
13338}
13339
13340bool isVMOVRSB(unsigned Opcode) {
13341 switch (Opcode) {
13342 case VMOVRSBZ128m:
13343 case VMOVRSBZ128mk:
13344 case VMOVRSBZ128mkz:
13345 case VMOVRSBZ256m:
13346 case VMOVRSBZ256mk:
13347 case VMOVRSBZ256mkz:
13348 case VMOVRSBZm:
13349 case VMOVRSBZmk:
13350 case VMOVRSBZmkz:
13351 return true;
13352 }
13353 return false;
13354}
13355
13356bool isVGETMANTSH(unsigned Opcode) {
13357 switch (Opcode) {
13358 case VGETMANTSHZrmi:
13359 case VGETMANTSHZrmik:
13360 case VGETMANTSHZrmikz:
13361 case VGETMANTSHZrri:
13362 case VGETMANTSHZrrib:
13363 case VGETMANTSHZrribk:
13364 case VGETMANTSHZrribkz:
13365 case VGETMANTSHZrrik:
13366 case VGETMANTSHZrrikz:
13367 return true;
13368 }
13369 return false;
13370}
13371
13372bool isVANDPS(unsigned Opcode) {
13373 switch (Opcode) {
13374 case VANDPSYrm:
13375 case VANDPSYrr:
13376 case VANDPSZ128rm:
13377 case VANDPSZ128rmb:
13378 case VANDPSZ128rmbk:
13379 case VANDPSZ128rmbkz:
13380 case VANDPSZ128rmk:
13381 case VANDPSZ128rmkz:
13382 case VANDPSZ128rr:
13383 case VANDPSZ128rrk:
13384 case VANDPSZ128rrkz:
13385 case VANDPSZ256rm:
13386 case VANDPSZ256rmb:
13387 case VANDPSZ256rmbk:
13388 case VANDPSZ256rmbkz:
13389 case VANDPSZ256rmk:
13390 case VANDPSZ256rmkz:
13391 case VANDPSZ256rr:
13392 case VANDPSZ256rrk:
13393 case VANDPSZ256rrkz:
13394 case VANDPSZrm:
13395 case VANDPSZrmb:
13396 case VANDPSZrmbk:
13397 case VANDPSZrmbkz:
13398 case VANDPSZrmk:
13399 case VANDPSZrmkz:
13400 case VANDPSZrr:
13401 case VANDPSZrrk:
13402 case VANDPSZrrkz:
13403 case VANDPSrm:
13404 case VANDPSrr:
13405 return true;
13406 }
13407 return false;
13408}
13409
13410bool isVDIVPS(unsigned Opcode) {
13411 switch (Opcode) {
13412 case VDIVPSYrm:
13413 case VDIVPSYrr:
13414 case VDIVPSZ128rm:
13415 case VDIVPSZ128rmb:
13416 case VDIVPSZ128rmbk:
13417 case VDIVPSZ128rmbkz:
13418 case VDIVPSZ128rmk:
13419 case VDIVPSZ128rmkz:
13420 case VDIVPSZ128rr:
13421 case VDIVPSZ128rrk:
13422 case VDIVPSZ128rrkz:
13423 case VDIVPSZ256rm:
13424 case VDIVPSZ256rmb:
13425 case VDIVPSZ256rmbk:
13426 case VDIVPSZ256rmbkz:
13427 case VDIVPSZ256rmk:
13428 case VDIVPSZ256rmkz:
13429 case VDIVPSZ256rr:
13430 case VDIVPSZ256rrk:
13431 case VDIVPSZ256rrkz:
13432 case VDIVPSZrm:
13433 case VDIVPSZrmb:
13434 case VDIVPSZrmbk:
13435 case VDIVPSZrmbkz:
13436 case VDIVPSZrmk:
13437 case VDIVPSZrmkz:
13438 case VDIVPSZrr:
13439 case VDIVPSZrrb:
13440 case VDIVPSZrrbk:
13441 case VDIVPSZrrbkz:
13442 case VDIVPSZrrk:
13443 case VDIVPSZrrkz:
13444 case VDIVPSrm:
13445 case VDIVPSrr:
13446 return true;
13447 }
13448 return false;
13449}
13450
13451bool isVANDNPS(unsigned Opcode) {
13452 switch (Opcode) {
13453 case VANDNPSYrm:
13454 case VANDNPSYrr:
13455 case VANDNPSZ128rm:
13456 case VANDNPSZ128rmb:
13457 case VANDNPSZ128rmbk:
13458 case VANDNPSZ128rmbkz:
13459 case VANDNPSZ128rmk:
13460 case VANDNPSZ128rmkz:
13461 case VANDNPSZ128rr:
13462 case VANDNPSZ128rrk:
13463 case VANDNPSZ128rrkz:
13464 case VANDNPSZ256rm:
13465 case VANDNPSZ256rmb:
13466 case VANDNPSZ256rmbk:
13467 case VANDNPSZ256rmbkz:
13468 case VANDNPSZ256rmk:
13469 case VANDNPSZ256rmkz:
13470 case VANDNPSZ256rr:
13471 case VANDNPSZ256rrk:
13472 case VANDNPSZ256rrkz:
13473 case VANDNPSZrm:
13474 case VANDNPSZrmb:
13475 case VANDNPSZrmbk:
13476 case VANDNPSZrmbkz:
13477 case VANDNPSZrmk:
13478 case VANDNPSZrmkz:
13479 case VANDNPSZrr:
13480 case VANDNPSZrrk:
13481 case VANDNPSZrrkz:
13482 case VANDNPSrm:
13483 case VANDNPSrr:
13484 return true;
13485 }
13486 return false;
13487}
13488
13489bool isVPBROADCASTW(unsigned Opcode) {
13490 switch (Opcode) {
13491 case VPBROADCASTWYrm:
13492 case VPBROADCASTWYrr:
13493 case VPBROADCASTWZ128rm:
13494 case VPBROADCASTWZ128rmk:
13495 case VPBROADCASTWZ128rmkz:
13496 case VPBROADCASTWZ128rr:
13497 case VPBROADCASTWZ128rrk:
13498 case VPBROADCASTWZ128rrkz:
13499 case VPBROADCASTWZ256rm:
13500 case VPBROADCASTWZ256rmk:
13501 case VPBROADCASTWZ256rmkz:
13502 case VPBROADCASTWZ256rr:
13503 case VPBROADCASTWZ256rrk:
13504 case VPBROADCASTWZ256rrkz:
13505 case VPBROADCASTWZrm:
13506 case VPBROADCASTWZrmk:
13507 case VPBROADCASTWZrmkz:
13508 case VPBROADCASTWZrr:
13509 case VPBROADCASTWZrrk:
13510 case VPBROADCASTWZrrkz:
13511 case VPBROADCASTWrZ128rr:
13512 case VPBROADCASTWrZ128rrk:
13513 case VPBROADCASTWrZ128rrkz:
13514 case VPBROADCASTWrZ256rr:
13515 case VPBROADCASTWrZ256rrk:
13516 case VPBROADCASTWrZ256rrkz:
13517 case VPBROADCASTWrZrr:
13518 case VPBROADCASTWrZrrk:
13519 case VPBROADCASTWrZrrkz:
13520 case VPBROADCASTWrm:
13521 case VPBROADCASTWrr:
13522 return true;
13523 }
13524 return false;
13525}
13526
13527bool isFLDL2T(unsigned Opcode) {
13528 return Opcode == FLDL2T;
13529}
13530
13531bool isVPERMB(unsigned Opcode) {
13532 switch (Opcode) {
13533 case VPERMBZ128rm:
13534 case VPERMBZ128rmk:
13535 case VPERMBZ128rmkz:
13536 case VPERMBZ128rr:
13537 case VPERMBZ128rrk:
13538 case VPERMBZ128rrkz:
13539 case VPERMBZ256rm:
13540 case VPERMBZ256rmk:
13541 case VPERMBZ256rmkz:
13542 case VPERMBZ256rr:
13543 case VPERMBZ256rrk:
13544 case VPERMBZ256rrkz:
13545 case VPERMBZrm:
13546 case VPERMBZrmk:
13547 case VPERMBZrmkz:
13548 case VPERMBZrr:
13549 case VPERMBZrrk:
13550 case VPERMBZrrkz:
13551 return true;
13552 }
13553 return false;
13554}
13555
13556bool isFCMOVNBE(unsigned Opcode) {
13557 return Opcode == CMOVNBE_F;
13558}
13559
13560bool isVCVTTPH2W(unsigned Opcode) {
13561 switch (Opcode) {
13562 case VCVTTPH2WZ128rm:
13563 case VCVTTPH2WZ128rmb:
13564 case VCVTTPH2WZ128rmbk:
13565 case VCVTTPH2WZ128rmbkz:
13566 case VCVTTPH2WZ128rmk:
13567 case VCVTTPH2WZ128rmkz:
13568 case VCVTTPH2WZ128rr:
13569 case VCVTTPH2WZ128rrk:
13570 case VCVTTPH2WZ128rrkz:
13571 case VCVTTPH2WZ256rm:
13572 case VCVTTPH2WZ256rmb:
13573 case VCVTTPH2WZ256rmbk:
13574 case VCVTTPH2WZ256rmbkz:
13575 case VCVTTPH2WZ256rmk:
13576 case VCVTTPH2WZ256rmkz:
13577 case VCVTTPH2WZ256rr:
13578 case VCVTTPH2WZ256rrk:
13579 case VCVTTPH2WZ256rrkz:
13580 case VCVTTPH2WZrm:
13581 case VCVTTPH2WZrmb:
13582 case VCVTTPH2WZrmbk:
13583 case VCVTTPH2WZrmbkz:
13584 case VCVTTPH2WZrmk:
13585 case VCVTTPH2WZrmkz:
13586 case VCVTTPH2WZrr:
13587 case VCVTTPH2WZrrb:
13588 case VCVTTPH2WZrrbk:
13589 case VCVTTPH2WZrrbkz:
13590 case VCVTTPH2WZrrk:
13591 case VCVTTPH2WZrrkz:
13592 return true;
13593 }
13594 return false;
13595}
13596
13597bool isPMOVZXBQ(unsigned Opcode) {
13598 switch (Opcode) {
13599 case PMOVZXBQrm:
13600 case PMOVZXBQrr:
13601 return true;
13602 }
13603 return false;
13604}
13605
13606bool isT2RPNTLVWZ0RS(unsigned Opcode) {
13607 switch (Opcode) {
13608 case T2RPNTLVWZ0RS:
13609 case T2RPNTLVWZ0RS_EVEX:
13610 return true;
13611 }
13612 return false;
13613}
13614
13615bool isPF2ID(unsigned Opcode) {
13616 switch (Opcode) {
13617 case PF2IDrm:
13618 case PF2IDrr:
13619 return true;
13620 }
13621 return false;
13622}
13623
13624bool isVFNMADD132PD(unsigned Opcode) {
13625 switch (Opcode) {
13626 case VFNMADD132PDYm:
13627 case VFNMADD132PDYr:
13628 case VFNMADD132PDZ128m:
13629 case VFNMADD132PDZ128mb:
13630 case VFNMADD132PDZ128mbk:
13631 case VFNMADD132PDZ128mbkz:
13632 case VFNMADD132PDZ128mk:
13633 case VFNMADD132PDZ128mkz:
13634 case VFNMADD132PDZ128r:
13635 case VFNMADD132PDZ128rk:
13636 case VFNMADD132PDZ128rkz:
13637 case VFNMADD132PDZ256m:
13638 case VFNMADD132PDZ256mb:
13639 case VFNMADD132PDZ256mbk:
13640 case VFNMADD132PDZ256mbkz:
13641 case VFNMADD132PDZ256mk:
13642 case VFNMADD132PDZ256mkz:
13643 case VFNMADD132PDZ256r:
13644 case VFNMADD132PDZ256rk:
13645 case VFNMADD132PDZ256rkz:
13646 case VFNMADD132PDZm:
13647 case VFNMADD132PDZmb:
13648 case VFNMADD132PDZmbk:
13649 case VFNMADD132PDZmbkz:
13650 case VFNMADD132PDZmk:
13651 case VFNMADD132PDZmkz:
13652 case VFNMADD132PDZr:
13653 case VFNMADD132PDZrb:
13654 case VFNMADD132PDZrbk:
13655 case VFNMADD132PDZrbkz:
13656 case VFNMADD132PDZrk:
13657 case VFNMADD132PDZrkz:
13658 case VFNMADD132PDm:
13659 case VFNMADD132PDr:
13660 return true;
13661 }
13662 return false;
13663}
13664
13665bool isPMULHRSW(unsigned Opcode) {
13666 switch (Opcode) {
13667 case MMX_PMULHRSWrm:
13668 case MMX_PMULHRSWrr:
13669 case PMULHRSWrm:
13670 case PMULHRSWrr:
13671 return true;
13672 }
13673 return false;
13674}
13675
13676bool isKADDD(unsigned Opcode) {
13677 return Opcode == KADDDkk;
13678}
13679
13680bool isVFNMSUB132SH(unsigned Opcode) {
13681 switch (Opcode) {
13682 case VFNMSUB132SHZm_Int:
13683 case VFNMSUB132SHZmk_Int:
13684 case VFNMSUB132SHZmkz_Int:
13685 case VFNMSUB132SHZr_Int:
13686 case VFNMSUB132SHZrb_Int:
13687 case VFNMSUB132SHZrbk_Int:
13688 case VFNMSUB132SHZrbkz_Int:
13689 case VFNMSUB132SHZrk_Int:
13690 case VFNMSUB132SHZrkz_Int:
13691 return true;
13692 }
13693 return false;
13694}
13695
13696bool isUIRET(unsigned Opcode) {
13697 return Opcode == UIRET;
13698}
13699
13700bool isBSR(unsigned Opcode) {
13701 switch (Opcode) {
13702 case BSR16rm:
13703 case BSR16rr:
13704 case BSR32rm:
13705 case BSR32rr:
13706 case BSR64rm:
13707 case BSR64rr:
13708 return true;
13709 }
13710 return false;
13711}
13712
13713bool isPCMPEQQ(unsigned Opcode) {
13714 switch (Opcode) {
13715 case PCMPEQQrm:
13716 case PCMPEQQrr:
13717 return true;
13718 }
13719 return false;
13720}
13721
13722bool isCDQ(unsigned Opcode) {
13723 return Opcode == CDQ;
13724}
13725
13726bool isPMAXSW(unsigned Opcode) {
13727 switch (Opcode) {
13728 case MMX_PMAXSWrm:
13729 case MMX_PMAXSWrr:
13730 case PMAXSWrm:
13731 case PMAXSWrr:
13732 return true;
13733 }
13734 return false;
13735}
13736
13737bool isSIDTD(unsigned Opcode) {
13738 return Opcode == SIDT32m;
13739}
13740
13741bool isVCVTPS2PHX(unsigned Opcode) {
13742 switch (Opcode) {
13743 case VCVTPS2PHXZ128rm:
13744 case VCVTPS2PHXZ128rmb:
13745 case VCVTPS2PHXZ128rmbk:
13746 case VCVTPS2PHXZ128rmbkz:
13747 case VCVTPS2PHXZ128rmk:
13748 case VCVTPS2PHXZ128rmkz:
13749 case VCVTPS2PHXZ128rr:
13750 case VCVTPS2PHXZ128rrk:
13751 case VCVTPS2PHXZ128rrkz:
13752 case VCVTPS2PHXZ256rm:
13753 case VCVTPS2PHXZ256rmb:
13754 case VCVTPS2PHXZ256rmbk:
13755 case VCVTPS2PHXZ256rmbkz:
13756 case VCVTPS2PHXZ256rmk:
13757 case VCVTPS2PHXZ256rmkz:
13758 case VCVTPS2PHXZ256rr:
13759 case VCVTPS2PHXZ256rrk:
13760 case VCVTPS2PHXZ256rrkz:
13761 case VCVTPS2PHXZrm:
13762 case VCVTPS2PHXZrmb:
13763 case VCVTPS2PHXZrmbk:
13764 case VCVTPS2PHXZrmbkz:
13765 case VCVTPS2PHXZrmk:
13766 case VCVTPS2PHXZrmkz:
13767 case VCVTPS2PHXZrr:
13768 case VCVTPS2PHXZrrb:
13769 case VCVTPS2PHXZrrbk:
13770 case VCVTPS2PHXZrrbkz:
13771 case VCVTPS2PHXZrrk:
13772 case VCVTPS2PHXZrrkz:
13773 return true;
13774 }
13775 return false;
13776}
13777
13778bool isVPSLLVQ(unsigned Opcode) {
13779 switch (Opcode) {
13780 case VPSLLVQYrm:
13781 case VPSLLVQYrr:
13782 case VPSLLVQZ128rm:
13783 case VPSLLVQZ128rmb:
13784 case VPSLLVQZ128rmbk:
13785 case VPSLLVQZ128rmbkz:
13786 case VPSLLVQZ128rmk:
13787 case VPSLLVQZ128rmkz:
13788 case VPSLLVQZ128rr:
13789 case VPSLLVQZ128rrk:
13790 case VPSLLVQZ128rrkz:
13791 case VPSLLVQZ256rm:
13792 case VPSLLVQZ256rmb:
13793 case VPSLLVQZ256rmbk:
13794 case VPSLLVQZ256rmbkz:
13795 case VPSLLVQZ256rmk:
13796 case VPSLLVQZ256rmkz:
13797 case VPSLLVQZ256rr:
13798 case VPSLLVQZ256rrk:
13799 case VPSLLVQZ256rrkz:
13800 case VPSLLVQZrm:
13801 case VPSLLVQZrmb:
13802 case VPSLLVQZrmbk:
13803 case VPSLLVQZrmbkz:
13804 case VPSLLVQZrmk:
13805 case VPSLLVQZrmkz:
13806 case VPSLLVQZrr:
13807 case VPSLLVQZrrk:
13808 case VPSLLVQZrrkz:
13809 case VPSLLVQrm:
13810 case VPSLLVQrr:
13811 return true;
13812 }
13813 return false;
13814}
13815
13816bool isMOVQ(unsigned Opcode) {
13817 switch (Opcode) {
13818 case MMX_MOVD64from64mr:
13819 case MMX_MOVD64from64rr:
13820 case MMX_MOVD64to64rm:
13821 case MMX_MOVD64to64rr:
13822 case MMX_MOVQ64mr:
13823 case MMX_MOVQ64rm:
13824 case MMX_MOVQ64rr:
13825 case MMX_MOVQ64rr_REV:
13826 case MOV64toPQIrm:
13827 case MOV64toPQIrr:
13828 case MOVPQI2QImr:
13829 case MOVPQI2QIrr:
13830 case MOVPQIto64mr:
13831 case MOVPQIto64rr:
13832 case MOVQI2PQIrm:
13833 case MOVZPQILo2PQIrr:
13834 return true;
13835 }
13836 return false;
13837}
13838
13839bool isVCMPBF16(unsigned Opcode) {
13840 switch (Opcode) {
13841 case VCMPBF16Z128rmbi:
13842 case VCMPBF16Z128rmbik:
13843 case VCMPBF16Z128rmi:
13844 case VCMPBF16Z128rmik:
13845 case VCMPBF16Z128rri:
13846 case VCMPBF16Z128rrik:
13847 case VCMPBF16Z256rmbi:
13848 case VCMPBF16Z256rmbik:
13849 case VCMPBF16Z256rmi:
13850 case VCMPBF16Z256rmik:
13851 case VCMPBF16Z256rri:
13852 case VCMPBF16Z256rrik:
13853 case VCMPBF16Zrmbi:
13854 case VCMPBF16Zrmbik:
13855 case VCMPBF16Zrmi:
13856 case VCMPBF16Zrmik:
13857 case VCMPBF16Zrri:
13858 case VCMPBF16Zrrik:
13859 return true;
13860 }
13861 return false;
13862}
13863
13864bool isPREFETCH(unsigned Opcode) {
13865 return Opcode == PREFETCH;
13866}
13867
13868bool isCLRSSBSY(unsigned Opcode) {
13869 return Opcode == CLRSSBSY;
13870}
13871
13872bool isTCVTROWPS2PHL(unsigned Opcode) {
13873 switch (Opcode) {
13874 case TCVTROWPS2PHLrre:
13875 case TCVTROWPS2PHLrri:
13876 return true;
13877 }
13878 return false;
13879}
13880
13881bool isPSHUFW(unsigned Opcode) {
13882 switch (Opcode) {
13883 case MMX_PSHUFWmi:
13884 case MMX_PSHUFWri:
13885 return true;
13886 }
13887 return false;
13888}
13889
13890bool isVPDPWSUDS(unsigned Opcode) {
13891 switch (Opcode) {
13892 case VPDPWSUDSYrm:
13893 case VPDPWSUDSYrr:
13894 case VPDPWSUDSZ128m:
13895 case VPDPWSUDSZ128mb:
13896 case VPDPWSUDSZ128mbk:
13897 case VPDPWSUDSZ128mbkz:
13898 case VPDPWSUDSZ128mk:
13899 case VPDPWSUDSZ128mkz:
13900 case VPDPWSUDSZ128r:
13901 case VPDPWSUDSZ128rk:
13902 case VPDPWSUDSZ128rkz:
13903 case VPDPWSUDSZ256m:
13904 case VPDPWSUDSZ256mb:
13905 case VPDPWSUDSZ256mbk:
13906 case VPDPWSUDSZ256mbkz:
13907 case VPDPWSUDSZ256mk:
13908 case VPDPWSUDSZ256mkz:
13909 case VPDPWSUDSZ256r:
13910 case VPDPWSUDSZ256rk:
13911 case VPDPWSUDSZ256rkz:
13912 case VPDPWSUDSZm:
13913 case VPDPWSUDSZmb:
13914 case VPDPWSUDSZmbk:
13915 case VPDPWSUDSZmbkz:
13916 case VPDPWSUDSZmk:
13917 case VPDPWSUDSZmkz:
13918 case VPDPWSUDSZr:
13919 case VPDPWSUDSZrk:
13920 case VPDPWSUDSZrkz:
13921 case VPDPWSUDSrm:
13922 case VPDPWSUDSrr:
13923 return true;
13924 }
13925 return false;
13926}
13927
13928bool isVPMOVSXBQ(unsigned Opcode) {
13929 switch (Opcode) {
13930 case VPMOVSXBQYrm:
13931 case VPMOVSXBQYrr:
13932 case VPMOVSXBQZ128rm:
13933 case VPMOVSXBQZ128rmk:
13934 case VPMOVSXBQZ128rmkz:
13935 case VPMOVSXBQZ128rr:
13936 case VPMOVSXBQZ128rrk:
13937 case VPMOVSXBQZ128rrkz:
13938 case VPMOVSXBQZ256rm:
13939 case VPMOVSXBQZ256rmk:
13940 case VPMOVSXBQZ256rmkz:
13941 case VPMOVSXBQZ256rr:
13942 case VPMOVSXBQZ256rrk:
13943 case VPMOVSXBQZ256rrkz:
13944 case VPMOVSXBQZrm:
13945 case VPMOVSXBQZrmk:
13946 case VPMOVSXBQZrmkz:
13947 case VPMOVSXBQZrr:
13948 case VPMOVSXBQZrrk:
13949 case VPMOVSXBQZrrkz:
13950 case VPMOVSXBQrm:
13951 case VPMOVSXBQrr:
13952 return true;
13953 }
13954 return false;
13955}
13956
13957bool isFICOMP(unsigned Opcode) {
13958 switch (Opcode) {
13959 case FICOMP16m:
13960 case FICOMP32m:
13961 return true;
13962 }
13963 return false;
13964}
13965
13966bool isVLDMXCSR(unsigned Opcode) {
13967 return Opcode == VLDMXCSR;
13968}
13969
13970bool isVPSUBUSW(unsigned Opcode) {
13971 switch (Opcode) {
13972 case VPSUBUSWYrm:
13973 case VPSUBUSWYrr:
13974 case VPSUBUSWZ128rm:
13975 case VPSUBUSWZ128rmk:
13976 case VPSUBUSWZ128rmkz:
13977 case VPSUBUSWZ128rr:
13978 case VPSUBUSWZ128rrk:
13979 case VPSUBUSWZ128rrkz:
13980 case VPSUBUSWZ256rm:
13981 case VPSUBUSWZ256rmk:
13982 case VPSUBUSWZ256rmkz:
13983 case VPSUBUSWZ256rr:
13984 case VPSUBUSWZ256rrk:
13985 case VPSUBUSWZ256rrkz:
13986 case VPSUBUSWZrm:
13987 case VPSUBUSWZrmk:
13988 case VPSUBUSWZrmkz:
13989 case VPSUBUSWZrr:
13990 case VPSUBUSWZrrk:
13991 case VPSUBUSWZrrkz:
13992 case VPSUBUSWrm:
13993 case VPSUBUSWrr:
13994 return true;
13995 }
13996 return false;
13997}
13998
13999bool isVFNMSUB132SS(unsigned Opcode) {
14000 switch (Opcode) {
14001 case VFNMSUB132SSZm_Int:
14002 case VFNMSUB132SSZmk_Int:
14003 case VFNMSUB132SSZmkz_Int:
14004 case VFNMSUB132SSZr_Int:
14005 case VFNMSUB132SSZrb_Int:
14006 case VFNMSUB132SSZrbk_Int:
14007 case VFNMSUB132SSZrbkz_Int:
14008 case VFNMSUB132SSZrk_Int:
14009 case VFNMSUB132SSZrkz_Int:
14010 case VFNMSUB132SSm_Int:
14011 case VFNMSUB132SSr_Int:
14012 return true;
14013 }
14014 return false;
14015}
14016
14017bool isRETF(unsigned Opcode) {
14018 switch (Opcode) {
14019 case LRET16:
14020 case LRET32:
14021 case LRETI16:
14022 case LRETI32:
14023 return true;
14024 }
14025 return false;
14026}
14027
14028bool isKMOVQ(unsigned Opcode) {
14029 switch (Opcode) {
14030 case KMOVQkk:
14031 case KMOVQkk_EVEX:
14032 case KMOVQkm:
14033 case KMOVQkm_EVEX:
14034 case KMOVQkr:
14035 case KMOVQkr_EVEX:
14036 case KMOVQmk:
14037 case KMOVQmk_EVEX:
14038 case KMOVQrk:
14039 case KMOVQrk_EVEX:
14040 return true;
14041 }
14042 return false;
14043}
14044
14045bool isVPADDUSW(unsigned Opcode) {
14046 switch (Opcode) {
14047 case VPADDUSWYrm:
14048 case VPADDUSWYrr:
14049 case VPADDUSWZ128rm:
14050 case VPADDUSWZ128rmk:
14051 case VPADDUSWZ128rmkz:
14052 case VPADDUSWZ128rr:
14053 case VPADDUSWZ128rrk:
14054 case VPADDUSWZ128rrkz:
14055 case VPADDUSWZ256rm:
14056 case VPADDUSWZ256rmk:
14057 case VPADDUSWZ256rmkz:
14058 case VPADDUSWZ256rr:
14059 case VPADDUSWZ256rrk:
14060 case VPADDUSWZ256rrkz:
14061 case VPADDUSWZrm:
14062 case VPADDUSWZrmk:
14063 case VPADDUSWZrmkz:
14064 case VPADDUSWZrr:
14065 case VPADDUSWZrrk:
14066 case VPADDUSWZrrkz:
14067 case VPADDUSWrm:
14068 case VPADDUSWrr:
14069 return true;
14070 }
14071 return false;
14072}
14073
14074bool isPACKSSDW(unsigned Opcode) {
14075 switch (Opcode) {
14076 case MMX_PACKSSDWrm:
14077 case MMX_PACKSSDWrr:
14078 case PACKSSDWrm:
14079 case PACKSSDWrr:
14080 return true;
14081 }
14082 return false;
14083}
14084
14085bool isUMONITOR(unsigned Opcode) {
14086 switch (Opcode) {
14087 case UMONITOR16:
14088 case UMONITOR32:
14089 case UMONITOR64:
14090 return true;
14091 }
14092 return false;
14093}
14094
14095bool isENQCMDS(unsigned Opcode) {
14096 switch (Opcode) {
14097 case ENQCMDS16:
14098 case ENQCMDS32:
14099 case ENQCMDS32_EVEX:
14100 case ENQCMDS64:
14101 case ENQCMDS64_EVEX:
14102 return true;
14103 }
14104 return false;
14105}
14106
14107bool isVCOMXSD(unsigned Opcode) {
14108 switch (Opcode) {
14109 case VCOMXSDZrm_Int:
14110 case VCOMXSDZrr_Int:
14111 case VCOMXSDZrrb_Int:
14112 return true;
14113 }
14114 return false;
14115}
14116
14117bool isVPMAXSQ(unsigned Opcode) {
14118 switch (Opcode) {
14119 case VPMAXSQZ128rm:
14120 case VPMAXSQZ128rmb:
14121 case VPMAXSQZ128rmbk:
14122 case VPMAXSQZ128rmbkz:
14123 case VPMAXSQZ128rmk:
14124 case VPMAXSQZ128rmkz:
14125 case VPMAXSQZ128rr:
14126 case VPMAXSQZ128rrk:
14127 case VPMAXSQZ128rrkz:
14128 case VPMAXSQZ256rm:
14129 case VPMAXSQZ256rmb:
14130 case VPMAXSQZ256rmbk:
14131 case VPMAXSQZ256rmbkz:
14132 case VPMAXSQZ256rmk:
14133 case VPMAXSQZ256rmkz:
14134 case VPMAXSQZ256rr:
14135 case VPMAXSQZ256rrk:
14136 case VPMAXSQZ256rrkz:
14137 case VPMAXSQZrm:
14138 case VPMAXSQZrmb:
14139 case VPMAXSQZrmbk:
14140 case VPMAXSQZrmbkz:
14141 case VPMAXSQZrmk:
14142 case VPMAXSQZrmkz:
14143 case VPMAXSQZrr:
14144 case VPMAXSQZrrk:
14145 case VPMAXSQZrrkz:
14146 return true;
14147 }
14148 return false;
14149}
14150
14151bool isVFMSUB213BF16(unsigned Opcode) {
14152 switch (Opcode) {
14153 case VFMSUB213BF16Z128m:
14154 case VFMSUB213BF16Z128mb:
14155 case VFMSUB213BF16Z128mbk:
14156 case VFMSUB213BF16Z128mbkz:
14157 case VFMSUB213BF16Z128mk:
14158 case VFMSUB213BF16Z128mkz:
14159 case VFMSUB213BF16Z128r:
14160 case VFMSUB213BF16Z128rk:
14161 case VFMSUB213BF16Z128rkz:
14162 case VFMSUB213BF16Z256m:
14163 case VFMSUB213BF16Z256mb:
14164 case VFMSUB213BF16Z256mbk:
14165 case VFMSUB213BF16Z256mbkz:
14166 case VFMSUB213BF16Z256mk:
14167 case VFMSUB213BF16Z256mkz:
14168 case VFMSUB213BF16Z256r:
14169 case VFMSUB213BF16Z256rk:
14170 case VFMSUB213BF16Z256rkz:
14171 case VFMSUB213BF16Zm:
14172 case VFMSUB213BF16Zmb:
14173 case VFMSUB213BF16Zmbk:
14174 case VFMSUB213BF16Zmbkz:
14175 case VFMSUB213BF16Zmk:
14176 case VFMSUB213BF16Zmkz:
14177 case VFMSUB213BF16Zr:
14178 case VFMSUB213BF16Zrk:
14179 case VFMSUB213BF16Zrkz:
14180 return true;
14181 }
14182 return false;
14183}
14184
14185bool isVPERMT2Q(unsigned Opcode) {
14186 switch (Opcode) {
14187 case VPERMT2QZ128rm:
14188 case VPERMT2QZ128rmb:
14189 case VPERMT2QZ128rmbk:
14190 case VPERMT2QZ128rmbkz:
14191 case VPERMT2QZ128rmk:
14192 case VPERMT2QZ128rmkz:
14193 case VPERMT2QZ128rr:
14194 case VPERMT2QZ128rrk:
14195 case VPERMT2QZ128rrkz:
14196 case VPERMT2QZ256rm:
14197 case VPERMT2QZ256rmb:
14198 case VPERMT2QZ256rmbk:
14199 case VPERMT2QZ256rmbkz:
14200 case VPERMT2QZ256rmk:
14201 case VPERMT2QZ256rmkz:
14202 case VPERMT2QZ256rr:
14203 case VPERMT2QZ256rrk:
14204 case VPERMT2QZ256rrkz:
14205 case VPERMT2QZrm:
14206 case VPERMT2QZrmb:
14207 case VPERMT2QZrmbk:
14208 case VPERMT2QZrmbkz:
14209 case VPERMT2QZrmk:
14210 case VPERMT2QZrmkz:
14211 case VPERMT2QZrr:
14212 case VPERMT2QZrrk:
14213 case VPERMT2QZrrkz:
14214 return true;
14215 }
14216 return false;
14217}
14218
14219bool isFDECSTP(unsigned Opcode) {
14220 return Opcode == FDECSTP;
14221}
14222
14223bool isVPTESTMQ(unsigned Opcode) {
14224 switch (Opcode) {
14225 case VPTESTMQZ128rm:
14226 case VPTESTMQZ128rmb:
14227 case VPTESTMQZ128rmbk:
14228 case VPTESTMQZ128rmk:
14229 case VPTESTMQZ128rr:
14230 case VPTESTMQZ128rrk:
14231 case VPTESTMQZ256rm:
14232 case VPTESTMQZ256rmb:
14233 case VPTESTMQZ256rmbk:
14234 case VPTESTMQZ256rmk:
14235 case VPTESTMQZ256rr:
14236 case VPTESTMQZ256rrk:
14237 case VPTESTMQZrm:
14238 case VPTESTMQZrmb:
14239 case VPTESTMQZrmbk:
14240 case VPTESTMQZrmk:
14241 case VPTESTMQZrr:
14242 case VPTESTMQZrrk:
14243 return true;
14244 }
14245 return false;
14246}
14247
14248bool isVRCP14PD(unsigned Opcode) {
14249 switch (Opcode) {
14250 case VRCP14PDZ128m:
14251 case VRCP14PDZ128mb:
14252 case VRCP14PDZ128mbk:
14253 case VRCP14PDZ128mbkz:
14254 case VRCP14PDZ128mk:
14255 case VRCP14PDZ128mkz:
14256 case VRCP14PDZ128r:
14257 case VRCP14PDZ128rk:
14258 case VRCP14PDZ128rkz:
14259 case VRCP14PDZ256m:
14260 case VRCP14PDZ256mb:
14261 case VRCP14PDZ256mbk:
14262 case VRCP14PDZ256mbkz:
14263 case VRCP14PDZ256mk:
14264 case VRCP14PDZ256mkz:
14265 case VRCP14PDZ256r:
14266 case VRCP14PDZ256rk:
14267 case VRCP14PDZ256rkz:
14268 case VRCP14PDZm:
14269 case VRCP14PDZmb:
14270 case VRCP14PDZmbk:
14271 case VRCP14PDZmbkz:
14272 case VRCP14PDZmk:
14273 case VRCP14PDZmkz:
14274 case VRCP14PDZr:
14275 case VRCP14PDZrk:
14276 case VRCP14PDZrkz:
14277 return true;
14278 }
14279 return false;
14280}
14281
14282bool isARPL(unsigned Opcode) {
14283 switch (Opcode) {
14284 case ARPL16mr:
14285 case ARPL16rr:
14286 return true;
14287 }
14288 return false;
14289}
14290
14291bool isVFMSUB213SD(unsigned Opcode) {
14292 switch (Opcode) {
14293 case VFMSUB213SDZm_Int:
14294 case VFMSUB213SDZmk_Int:
14295 case VFMSUB213SDZmkz_Int:
14296 case VFMSUB213SDZr_Int:
14297 case VFMSUB213SDZrb_Int:
14298 case VFMSUB213SDZrbk_Int:
14299 case VFMSUB213SDZrbkz_Int:
14300 case VFMSUB213SDZrk_Int:
14301 case VFMSUB213SDZrkz_Int:
14302 case VFMSUB213SDm_Int:
14303 case VFMSUB213SDr_Int:
14304 return true;
14305 }
14306 return false;
14307}
14308
14309bool isJMPABS(unsigned Opcode) {
14310 return Opcode == JMPABS64i;
14311}
14312
14313bool isVUNPCKHPS(unsigned Opcode) {
14314 switch (Opcode) {
14315 case VUNPCKHPSYrm:
14316 case VUNPCKHPSYrr:
14317 case VUNPCKHPSZ128rm:
14318 case VUNPCKHPSZ128rmb:
14319 case VUNPCKHPSZ128rmbk:
14320 case VUNPCKHPSZ128rmbkz:
14321 case VUNPCKHPSZ128rmk:
14322 case VUNPCKHPSZ128rmkz:
14323 case VUNPCKHPSZ128rr:
14324 case VUNPCKHPSZ128rrk:
14325 case VUNPCKHPSZ128rrkz:
14326 case VUNPCKHPSZ256rm:
14327 case VUNPCKHPSZ256rmb:
14328 case VUNPCKHPSZ256rmbk:
14329 case VUNPCKHPSZ256rmbkz:
14330 case VUNPCKHPSZ256rmk:
14331 case VUNPCKHPSZ256rmkz:
14332 case VUNPCKHPSZ256rr:
14333 case VUNPCKHPSZ256rrk:
14334 case VUNPCKHPSZ256rrkz:
14335 case VUNPCKHPSZrm:
14336 case VUNPCKHPSZrmb:
14337 case VUNPCKHPSZrmbk:
14338 case VUNPCKHPSZrmbkz:
14339 case VUNPCKHPSZrmk:
14340 case VUNPCKHPSZrmkz:
14341 case VUNPCKHPSZrr:
14342 case VUNPCKHPSZrrk:
14343 case VUNPCKHPSZrrkz:
14344 case VUNPCKHPSrm:
14345 case VUNPCKHPSrr:
14346 return true;
14347 }
14348 return false;
14349}
14350
14351bool isVFNMADDSS(unsigned Opcode) {
14352 switch (Opcode) {
14353 case VFNMADDSS4mr:
14354 case VFNMADDSS4rm:
14355 case VFNMADDSS4rr:
14356 case VFNMADDSS4rr_REV:
14357 return true;
14358 }
14359 return false;
14360}
14361
14362bool isSIDT(unsigned Opcode) {
14363 return Opcode == SIDT64m;
14364}
14365
14366bool isVPCMPGTB(unsigned Opcode) {
14367 switch (Opcode) {
14368 case VPCMPGTBYrm:
14369 case VPCMPGTBYrr:
14370 case VPCMPGTBZ128rm:
14371 case VPCMPGTBZ128rmk:
14372 case VPCMPGTBZ128rr:
14373 case VPCMPGTBZ128rrk:
14374 case VPCMPGTBZ256rm:
14375 case VPCMPGTBZ256rmk:
14376 case VPCMPGTBZ256rr:
14377 case VPCMPGTBZ256rrk:
14378 case VPCMPGTBZrm:
14379 case VPCMPGTBZrmk:
14380 case VPCMPGTBZrr:
14381 case VPCMPGTBZrrk:
14382 case VPCMPGTBrm:
14383 case VPCMPGTBrr:
14384 return true;
14385 }
14386 return false;
14387}
14388
14389bool isVPRORD(unsigned Opcode) {
14390 switch (Opcode) {
14391 case VPRORDZ128mbi:
14392 case VPRORDZ128mbik:
14393 case VPRORDZ128mbikz:
14394 case VPRORDZ128mi:
14395 case VPRORDZ128mik:
14396 case VPRORDZ128mikz:
14397 case VPRORDZ128ri:
14398 case VPRORDZ128rik:
14399 case VPRORDZ128rikz:
14400 case VPRORDZ256mbi:
14401 case VPRORDZ256mbik:
14402 case VPRORDZ256mbikz:
14403 case VPRORDZ256mi:
14404 case VPRORDZ256mik:
14405 case VPRORDZ256mikz:
14406 case VPRORDZ256ri:
14407 case VPRORDZ256rik:
14408 case VPRORDZ256rikz:
14409 case VPRORDZmbi:
14410 case VPRORDZmbik:
14411 case VPRORDZmbikz:
14412 case VPRORDZmi:
14413 case VPRORDZmik:
14414 case VPRORDZmikz:
14415 case VPRORDZri:
14416 case VPRORDZrik:
14417 case VPRORDZrikz:
14418 return true;
14419 }
14420 return false;
14421}
14422
14423bool isVSUBSS(unsigned Opcode) {
14424 switch (Opcode) {
14425 case VSUBSSZrm_Int:
14426 case VSUBSSZrmk_Int:
14427 case VSUBSSZrmkz_Int:
14428 case VSUBSSZrr_Int:
14429 case VSUBSSZrrb_Int:
14430 case VSUBSSZrrbk_Int:
14431 case VSUBSSZrrbkz_Int:
14432 case VSUBSSZrrk_Int:
14433 case VSUBSSZrrkz_Int:
14434 case VSUBSSrm_Int:
14435 case VSUBSSrr_Int:
14436 return true;
14437 }
14438 return false;
14439}
14440
14441bool isPUSHFQ(unsigned Opcode) {
14442 return Opcode == PUSHF64;
14443}
14444
14445bool isVCVTHF82PH(unsigned Opcode) {
14446 switch (Opcode) {
14447 case VCVTHF82PHZ128rm:
14448 case VCVTHF82PHZ128rmk:
14449 case VCVTHF82PHZ128rmkz:
14450 case VCVTHF82PHZ128rr:
14451 case VCVTHF82PHZ128rrk:
14452 case VCVTHF82PHZ128rrkz:
14453 case VCVTHF82PHZ256rm:
14454 case VCVTHF82PHZ256rmk:
14455 case VCVTHF82PHZ256rmkz:
14456 case VCVTHF82PHZ256rr:
14457 case VCVTHF82PHZ256rrk:
14458 case VCVTHF82PHZ256rrkz:
14459 case VCVTHF82PHZrm:
14460 case VCVTHF82PHZrmk:
14461 case VCVTHF82PHZrmkz:
14462 case VCVTHF82PHZrr:
14463 case VCVTHF82PHZrrk:
14464 case VCVTHF82PHZrrkz:
14465 return true;
14466 }
14467 return false;
14468}
14469
14470bool isVPCLMULQDQ(unsigned Opcode) {
14471 switch (Opcode) {
14472 case VPCLMULQDQYrmi:
14473 case VPCLMULQDQYrri:
14474 case VPCLMULQDQZ128rmi:
14475 case VPCLMULQDQZ128rri:
14476 case VPCLMULQDQZ256rmi:
14477 case VPCLMULQDQZ256rri:
14478 case VPCLMULQDQZrmi:
14479 case VPCLMULQDQZrri:
14480 case VPCLMULQDQrmi:
14481 case VPCLMULQDQrri:
14482 return true;
14483 }
14484 return false;
14485}
14486
14487bool isVPADDUSB(unsigned Opcode) {
14488 switch (Opcode) {
14489 case VPADDUSBYrm:
14490 case VPADDUSBYrr:
14491 case VPADDUSBZ128rm:
14492 case VPADDUSBZ128rmk:
14493 case VPADDUSBZ128rmkz:
14494 case VPADDUSBZ128rr:
14495 case VPADDUSBZ128rrk:
14496 case VPADDUSBZ128rrkz:
14497 case VPADDUSBZ256rm:
14498 case VPADDUSBZ256rmk:
14499 case VPADDUSBZ256rmkz:
14500 case VPADDUSBZ256rr:
14501 case VPADDUSBZ256rrk:
14502 case VPADDUSBZ256rrkz:
14503 case VPADDUSBZrm:
14504 case VPADDUSBZrmk:
14505 case VPADDUSBZrmkz:
14506 case VPADDUSBZrr:
14507 case VPADDUSBZrrk:
14508 case VPADDUSBZrrkz:
14509 case VPADDUSBrm:
14510 case VPADDUSBrr:
14511 return true;
14512 }
14513 return false;
14514}
14515
14516bool isVPCMPD(unsigned Opcode) {
14517 switch (Opcode) {
14518 case VPCMPDZ128rmbi:
14519 case VPCMPDZ128rmbik:
14520 case VPCMPDZ128rmi:
14521 case VPCMPDZ128rmik:
14522 case VPCMPDZ128rri:
14523 case VPCMPDZ128rrik:
14524 case VPCMPDZ256rmbi:
14525 case VPCMPDZ256rmbik:
14526 case VPCMPDZ256rmi:
14527 case VPCMPDZ256rmik:
14528 case VPCMPDZ256rri:
14529 case VPCMPDZ256rrik:
14530 case VPCMPDZrmbi:
14531 case VPCMPDZrmbik:
14532 case VPCMPDZrmi:
14533 case VPCMPDZrmik:
14534 case VPCMPDZrri:
14535 case VPCMPDZrrik:
14536 return true;
14537 }
14538 return false;
14539}
14540
14541bool isMOVSD(unsigned Opcode) {
14542 switch (Opcode) {
14543 case MOVSDmr:
14544 case MOVSDrm:
14545 case MOVSDrr:
14546 case MOVSDrr_REV:
14547 case MOVSL:
14548 return true;
14549 }
14550 return false;
14551}
14552
14553bool isPSUBUSW(unsigned Opcode) {
14554 switch (Opcode) {
14555 case MMX_PSUBUSWrm:
14556 case MMX_PSUBUSWrr:
14557 case PSUBUSWrm:
14558 case PSUBUSWrr:
14559 return true;
14560 }
14561 return false;
14562}
14563
14564bool isVFMSUBADD132PS(unsigned Opcode) {
14565 switch (Opcode) {
14566 case VFMSUBADD132PSYm:
14567 case VFMSUBADD132PSYr:
14568 case VFMSUBADD132PSZ128m:
14569 case VFMSUBADD132PSZ128mb:
14570 case VFMSUBADD132PSZ128mbk:
14571 case VFMSUBADD132PSZ128mbkz:
14572 case VFMSUBADD132PSZ128mk:
14573 case VFMSUBADD132PSZ128mkz:
14574 case VFMSUBADD132PSZ128r:
14575 case VFMSUBADD132PSZ128rk:
14576 case VFMSUBADD132PSZ128rkz:
14577 case VFMSUBADD132PSZ256m:
14578 case VFMSUBADD132PSZ256mb:
14579 case VFMSUBADD132PSZ256mbk:
14580 case VFMSUBADD132PSZ256mbkz:
14581 case VFMSUBADD132PSZ256mk:
14582 case VFMSUBADD132PSZ256mkz:
14583 case VFMSUBADD132PSZ256r:
14584 case VFMSUBADD132PSZ256rk:
14585 case VFMSUBADD132PSZ256rkz:
14586 case VFMSUBADD132PSZm:
14587 case VFMSUBADD132PSZmb:
14588 case VFMSUBADD132PSZmbk:
14589 case VFMSUBADD132PSZmbkz:
14590 case VFMSUBADD132PSZmk:
14591 case VFMSUBADD132PSZmkz:
14592 case VFMSUBADD132PSZr:
14593 case VFMSUBADD132PSZrb:
14594 case VFMSUBADD132PSZrbk:
14595 case VFMSUBADD132PSZrbkz:
14596 case VFMSUBADD132PSZrk:
14597 case VFMSUBADD132PSZrkz:
14598 case VFMSUBADD132PSm:
14599 case VFMSUBADD132PSr:
14600 return true;
14601 }
14602 return false;
14603}
14604
14605bool isMOVMSKPS(unsigned Opcode) {
14606 return Opcode == MOVMSKPSrr;
14607}
14608
14609bool isVFIXUPIMMSS(unsigned Opcode) {
14610 switch (Opcode) {
14611 case VFIXUPIMMSSZrmi:
14612 case VFIXUPIMMSSZrmik:
14613 case VFIXUPIMMSSZrmikz:
14614 case VFIXUPIMMSSZrri:
14615 case VFIXUPIMMSSZrrib:
14616 case VFIXUPIMMSSZrribk:
14617 case VFIXUPIMMSSZrribkz:
14618 case VFIXUPIMMSSZrrik:
14619 case VFIXUPIMMSSZrrikz:
14620 return true;
14621 }
14622 return false;
14623}
14624
14625bool isMFENCE(unsigned Opcode) {
14626 return Opcode == MFENCE;
14627}
14628
14629bool isFTST(unsigned Opcode) {
14630 return Opcode == TST_F;
14631}
14632
14633bool isVPMADDWD(unsigned Opcode) {
14634 switch (Opcode) {
14635 case VPMADDWDYrm:
14636 case VPMADDWDYrr:
14637 case VPMADDWDZ128rm:
14638 case VPMADDWDZ128rmk:
14639 case VPMADDWDZ128rmkz:
14640 case VPMADDWDZ128rr:
14641 case VPMADDWDZ128rrk:
14642 case VPMADDWDZ128rrkz:
14643 case VPMADDWDZ256rm:
14644 case VPMADDWDZ256rmk:
14645 case VPMADDWDZ256rmkz:
14646 case VPMADDWDZ256rr:
14647 case VPMADDWDZ256rrk:
14648 case VPMADDWDZ256rrkz:
14649 case VPMADDWDZrm:
14650 case VPMADDWDZrmk:
14651 case VPMADDWDZrmkz:
14652 case VPMADDWDZrr:
14653 case VPMADDWDZrrk:
14654 case VPMADDWDZrrkz:
14655 case VPMADDWDrm:
14656 case VPMADDWDrr:
14657 return true;
14658 }
14659 return false;
14660}
14661
14662bool isPOP(unsigned Opcode) {
14663 switch (Opcode) {
14664 case POP16r:
14665 case POP16rmm:
14666 case POP16rmr:
14667 case POP32r:
14668 case POP32rmm:
14669 case POP32rmr:
14670 case POP64r:
14671 case POP64rmm:
14672 case POP64rmr:
14673 case POPDS16:
14674 case POPDS32:
14675 case POPES16:
14676 case POPES32:
14677 case POPFS16:
14678 case POPFS32:
14679 case POPFS64:
14680 case POPGS16:
14681 case POPGS32:
14682 case POPGS64:
14683 case POPSS16:
14684 case POPSS32:
14685 return true;
14686 }
14687 return false;
14688}
14689
14690bool isPSUBW(unsigned Opcode) {
14691 switch (Opcode) {
14692 case MMX_PSUBWrm:
14693 case MMX_PSUBWrr:
14694 case PSUBWrm:
14695 case PSUBWrr:
14696 return true;
14697 }
14698 return false;
14699}
14700
14701bool isBSWAP(unsigned Opcode) {
14702 switch (Opcode) {
14703 case BSWAP16r_BAD:
14704 case BSWAP32r:
14705 case BSWAP64r:
14706 return true;
14707 }
14708 return false;
14709}
14710
14711bool isPFMIN(unsigned Opcode) {
14712 switch (Opcode) {
14713 case PFMINrm:
14714 case PFMINrr:
14715 return true;
14716 }
14717 return false;
14718}
14719
14720bool isVFPCLASSPD(unsigned Opcode) {
14721 switch (Opcode) {
14722 case VFPCLASSPDZ128mbi:
14723 case VFPCLASSPDZ128mbik:
14724 case VFPCLASSPDZ128mi:
14725 case VFPCLASSPDZ128mik:
14726 case VFPCLASSPDZ128ri:
14727 case VFPCLASSPDZ128rik:
14728 case VFPCLASSPDZ256mbi:
14729 case VFPCLASSPDZ256mbik:
14730 case VFPCLASSPDZ256mi:
14731 case VFPCLASSPDZ256mik:
14732 case VFPCLASSPDZ256ri:
14733 case VFPCLASSPDZ256rik:
14734 case VFPCLASSPDZmbi:
14735 case VFPCLASSPDZmbik:
14736 case VFPCLASSPDZmi:
14737 case VFPCLASSPDZmik:
14738 case VFPCLASSPDZri:
14739 case VFPCLASSPDZrik:
14740 return true;
14741 }
14742 return false;
14743}
14744
14745bool isVPSHRDVD(unsigned Opcode) {
14746 switch (Opcode) {
14747 case VPSHRDVDZ128m:
14748 case VPSHRDVDZ128mb:
14749 case VPSHRDVDZ128mbk:
14750 case VPSHRDVDZ128mbkz:
14751 case VPSHRDVDZ128mk:
14752 case VPSHRDVDZ128mkz:
14753 case VPSHRDVDZ128r:
14754 case VPSHRDVDZ128rk:
14755 case VPSHRDVDZ128rkz:
14756 case VPSHRDVDZ256m:
14757 case VPSHRDVDZ256mb:
14758 case VPSHRDVDZ256mbk:
14759 case VPSHRDVDZ256mbkz:
14760 case VPSHRDVDZ256mk:
14761 case VPSHRDVDZ256mkz:
14762 case VPSHRDVDZ256r:
14763 case VPSHRDVDZ256rk:
14764 case VPSHRDVDZ256rkz:
14765 case VPSHRDVDZm:
14766 case VPSHRDVDZmb:
14767 case VPSHRDVDZmbk:
14768 case VPSHRDVDZmbkz:
14769 case VPSHRDVDZmk:
14770 case VPSHRDVDZmkz:
14771 case VPSHRDVDZr:
14772 case VPSHRDVDZrk:
14773 case VPSHRDVDZrkz:
14774 return true;
14775 }
14776 return false;
14777}
14778
14779bool isPADDW(unsigned Opcode) {
14780 switch (Opcode) {
14781 case MMX_PADDWrm:
14782 case MMX_PADDWrr:
14783 case PADDWrm:
14784 case PADDWrr:
14785 return true;
14786 }
14787 return false;
14788}
14789
14790bool isT2RPNTLVWZ1(unsigned Opcode) {
14791 switch (Opcode) {
14792 case T2RPNTLVWZ1:
14793 case T2RPNTLVWZ1_EVEX:
14794 return true;
14795 }
14796 return false;
14797}
14798
14799bool isCVTSI2SD(unsigned Opcode) {
14800 switch (Opcode) {
14801 case CVTSI2SDrm_Int:
14802 case CVTSI2SDrr_Int:
14803 case CVTSI642SDrm_Int:
14804 case CVTSI642SDrr_Int:
14805 return true;
14806 }
14807 return false;
14808}
14809
14810bool isENQCMD(unsigned Opcode) {
14811 switch (Opcode) {
14812 case ENQCMD16:
14813 case ENQCMD32:
14814 case ENQCMD32_EVEX:
14815 case ENQCMD64:
14816 case ENQCMD64_EVEX:
14817 return true;
14818 }
14819 return false;
14820}
14821
14822bool isXSHA1(unsigned Opcode) {
14823 return Opcode == XSHA1;
14824}
14825
14826bool isVFNMADD132SD(unsigned Opcode) {
14827 switch (Opcode) {
14828 case VFNMADD132SDZm_Int:
14829 case VFNMADD132SDZmk_Int:
14830 case VFNMADD132SDZmkz_Int:
14831 case VFNMADD132SDZr_Int:
14832 case VFNMADD132SDZrb_Int:
14833 case VFNMADD132SDZrbk_Int:
14834 case VFNMADD132SDZrbkz_Int:
14835 case VFNMADD132SDZrk_Int:
14836 case VFNMADD132SDZrkz_Int:
14837 case VFNMADD132SDm_Int:
14838 case VFNMADD132SDr_Int:
14839 return true;
14840 }
14841 return false;
14842}
14843
14844bool isMOVZX(unsigned Opcode) {
14845 switch (Opcode) {
14846 case MOVZX16rm16:
14847 case MOVZX16rm8:
14848 case MOVZX16rr16:
14849 case MOVZX16rr8:
14850 case MOVZX32rm16:
14851 case MOVZX32rm8:
14852 case MOVZX32rr16:
14853 case MOVZX32rr8:
14854 case MOVZX64rm16:
14855 case MOVZX64rm8:
14856 case MOVZX64rr16:
14857 case MOVZX64rr8:
14858 return true;
14859 }
14860 return false;
14861}
14862
14863bool isVFIXUPIMMSD(unsigned Opcode) {
14864 switch (Opcode) {
14865 case VFIXUPIMMSDZrmi:
14866 case VFIXUPIMMSDZrmik:
14867 case VFIXUPIMMSDZrmikz:
14868 case VFIXUPIMMSDZrri:
14869 case VFIXUPIMMSDZrrib:
14870 case VFIXUPIMMSDZrribk:
14871 case VFIXUPIMMSDZrribkz:
14872 case VFIXUPIMMSDZrrik:
14873 case VFIXUPIMMSDZrrikz:
14874 return true;
14875 }
14876 return false;
14877}
14878
14879bool isT2RPNTLVWZ0RST1(unsigned Opcode) {
14880 switch (Opcode) {
14881 case T2RPNTLVWZ0RST1:
14882 case T2RPNTLVWZ0RST1_EVEX:
14883 return true;
14884 }
14885 return false;
14886}
14887
14888bool isINVD(unsigned Opcode) {
14889 return Opcode == INVD;
14890}
14891
14892bool isVFIXUPIMMPS(unsigned Opcode) {
14893 switch (Opcode) {
14894 case VFIXUPIMMPSZ128rmbi:
14895 case VFIXUPIMMPSZ128rmbik:
14896 case VFIXUPIMMPSZ128rmbikz:
14897 case VFIXUPIMMPSZ128rmi:
14898 case VFIXUPIMMPSZ128rmik:
14899 case VFIXUPIMMPSZ128rmikz:
14900 case VFIXUPIMMPSZ128rri:
14901 case VFIXUPIMMPSZ128rrik:
14902 case VFIXUPIMMPSZ128rrikz:
14903 case VFIXUPIMMPSZ256rmbi:
14904 case VFIXUPIMMPSZ256rmbik:
14905 case VFIXUPIMMPSZ256rmbikz:
14906 case VFIXUPIMMPSZ256rmi:
14907 case VFIXUPIMMPSZ256rmik:
14908 case VFIXUPIMMPSZ256rmikz:
14909 case VFIXUPIMMPSZ256rri:
14910 case VFIXUPIMMPSZ256rrik:
14911 case VFIXUPIMMPSZ256rrikz:
14912 case VFIXUPIMMPSZrmbi:
14913 case VFIXUPIMMPSZrmbik:
14914 case VFIXUPIMMPSZrmbikz:
14915 case VFIXUPIMMPSZrmi:
14916 case VFIXUPIMMPSZrmik:
14917 case VFIXUPIMMPSZrmikz:
14918 case VFIXUPIMMPSZrri:
14919 case VFIXUPIMMPSZrrib:
14920 case VFIXUPIMMPSZrribk:
14921 case VFIXUPIMMPSZrribkz:
14922 case VFIXUPIMMPSZrrik:
14923 case VFIXUPIMMPSZrrikz:
14924 return true;
14925 }
14926 return false;
14927}
14928
14929bool isMOVDQU(unsigned Opcode) {
14930 switch (Opcode) {
14931 case MOVDQUmr:
14932 case MOVDQUrm:
14933 case MOVDQUrr:
14934 case MOVDQUrr_REV:
14935 return true;
14936 }
14937 return false;
14938}
14939
14940bool isVFPCLASSPS(unsigned Opcode) {
14941 switch (Opcode) {
14942 case VFPCLASSPSZ128mbi:
14943 case VFPCLASSPSZ128mbik:
14944 case VFPCLASSPSZ128mi:
14945 case VFPCLASSPSZ128mik:
14946 case VFPCLASSPSZ128ri:
14947 case VFPCLASSPSZ128rik:
14948 case VFPCLASSPSZ256mbi:
14949 case VFPCLASSPSZ256mbik:
14950 case VFPCLASSPSZ256mi:
14951 case VFPCLASSPSZ256mik:
14952 case VFPCLASSPSZ256ri:
14953 case VFPCLASSPSZ256rik:
14954 case VFPCLASSPSZmbi:
14955 case VFPCLASSPSZmbik:
14956 case VFPCLASSPSZmi:
14957 case VFPCLASSPSZmik:
14958 case VFPCLASSPSZri:
14959 case VFPCLASSPSZrik:
14960 return true;
14961 }
14962 return false;
14963}
14964
14965bool isMOVSQ(unsigned Opcode) {
14966 return Opcode == MOVSQ;
14967}
14968
14969bool isAESDECWIDE128KL(unsigned Opcode) {
14970 return Opcode == AESDECWIDE128KL;
14971}
14972
14973bool isROUNDSS(unsigned Opcode) {
14974 switch (Opcode) {
14975 case ROUNDSSmi_Int:
14976 case ROUNDSSri_Int:
14977 return true;
14978 }
14979 return false;
14980}
14981
14982bool isVPERMILPS(unsigned Opcode) {
14983 switch (Opcode) {
14984 case VPERMILPSYmi:
14985 case VPERMILPSYri:
14986 case VPERMILPSYrm:
14987 case VPERMILPSYrr:
14988 case VPERMILPSZ128mbi:
14989 case VPERMILPSZ128mbik:
14990 case VPERMILPSZ128mbikz:
14991 case VPERMILPSZ128mi:
14992 case VPERMILPSZ128mik:
14993 case VPERMILPSZ128mikz:
14994 case VPERMILPSZ128ri:
14995 case VPERMILPSZ128rik:
14996 case VPERMILPSZ128rikz:
14997 case VPERMILPSZ128rm:
14998 case VPERMILPSZ128rmb:
14999 case VPERMILPSZ128rmbk:
15000 case VPERMILPSZ128rmbkz:
15001 case VPERMILPSZ128rmk:
15002 case VPERMILPSZ128rmkz:
15003 case VPERMILPSZ128rr:
15004 case VPERMILPSZ128rrk:
15005 case VPERMILPSZ128rrkz:
15006 case VPERMILPSZ256mbi:
15007 case VPERMILPSZ256mbik:
15008 case VPERMILPSZ256mbikz:
15009 case VPERMILPSZ256mi:
15010 case VPERMILPSZ256mik:
15011 case VPERMILPSZ256mikz:
15012 case VPERMILPSZ256ri:
15013 case VPERMILPSZ256rik:
15014 case VPERMILPSZ256rikz:
15015 case VPERMILPSZ256rm:
15016 case VPERMILPSZ256rmb:
15017 case VPERMILPSZ256rmbk:
15018 case VPERMILPSZ256rmbkz:
15019 case VPERMILPSZ256rmk:
15020 case VPERMILPSZ256rmkz:
15021 case VPERMILPSZ256rr:
15022 case VPERMILPSZ256rrk:
15023 case VPERMILPSZ256rrkz:
15024 case VPERMILPSZmbi:
15025 case VPERMILPSZmbik:
15026 case VPERMILPSZmbikz:
15027 case VPERMILPSZmi:
15028 case VPERMILPSZmik:
15029 case VPERMILPSZmikz:
15030 case VPERMILPSZri:
15031 case VPERMILPSZrik:
15032 case VPERMILPSZrikz:
15033 case VPERMILPSZrm:
15034 case VPERMILPSZrmb:
15035 case VPERMILPSZrmbk:
15036 case VPERMILPSZrmbkz:
15037 case VPERMILPSZrmk:
15038 case VPERMILPSZrmkz:
15039 case VPERMILPSZrr:
15040 case VPERMILPSZrrk:
15041 case VPERMILPSZrrkz:
15042 case VPERMILPSmi:
15043 case VPERMILPSri:
15044 case VPERMILPSrm:
15045 case VPERMILPSrr:
15046 return true;
15047 }
15048 return false;
15049}
15050
15051bool isVPMOVW2M(unsigned Opcode) {
15052 switch (Opcode) {
15053 case VPMOVW2MZ128kr:
15054 case VPMOVW2MZ256kr:
15055 case VPMOVW2MZkr:
15056 return true;
15057 }
15058 return false;
15059}
15060
15061bool isVMULSD(unsigned Opcode) {
15062 switch (Opcode) {
15063 case VMULSDZrm_Int:
15064 case VMULSDZrmk_Int:
15065 case VMULSDZrmkz_Int:
15066 case VMULSDZrr_Int:
15067 case VMULSDZrrb_Int:
15068 case VMULSDZrrbk_Int:
15069 case VMULSDZrrbkz_Int:
15070 case VMULSDZrrk_Int:
15071 case VMULSDZrrkz_Int:
15072 case VMULSDrm_Int:
15073 case VMULSDrr_Int:
15074 return true;
15075 }
15076 return false;
15077}
15078
15079bool isVPERMI2W(unsigned Opcode) {
15080 switch (Opcode) {
15081 case VPERMI2WZ128rm:
15082 case VPERMI2WZ128rmk:
15083 case VPERMI2WZ128rmkz:
15084 case VPERMI2WZ128rr:
15085 case VPERMI2WZ128rrk:
15086 case VPERMI2WZ128rrkz:
15087 case VPERMI2WZ256rm:
15088 case VPERMI2WZ256rmk:
15089 case VPERMI2WZ256rmkz:
15090 case VPERMI2WZ256rr:
15091 case VPERMI2WZ256rrk:
15092 case VPERMI2WZ256rrkz:
15093 case VPERMI2WZrm:
15094 case VPERMI2WZrmk:
15095 case VPERMI2WZrmkz:
15096 case VPERMI2WZrr:
15097 case VPERMI2WZrrk:
15098 case VPERMI2WZrrkz:
15099 return true;
15100 }
15101 return false;
15102}
15103
15104bool isVPSHUFB(unsigned Opcode) {
15105 switch (Opcode) {
15106 case VPSHUFBYrm:
15107 case VPSHUFBYrr:
15108 case VPSHUFBZ128rm:
15109 case VPSHUFBZ128rmk:
15110 case VPSHUFBZ128rmkz:
15111 case VPSHUFBZ128rr:
15112 case VPSHUFBZ128rrk:
15113 case VPSHUFBZ128rrkz:
15114 case VPSHUFBZ256rm:
15115 case VPSHUFBZ256rmk:
15116 case VPSHUFBZ256rmkz:
15117 case VPSHUFBZ256rr:
15118 case VPSHUFBZ256rrk:
15119 case VPSHUFBZ256rrkz:
15120 case VPSHUFBZrm:
15121 case VPSHUFBZrmk:
15122 case VPSHUFBZrmkz:
15123 case VPSHUFBZrr:
15124 case VPSHUFBZrrk:
15125 case VPSHUFBZrrkz:
15126 case VPSHUFBrm:
15127 case VPSHUFBrr:
15128 return true;
15129 }
15130 return false;
15131}
15132
15133bool isFST(unsigned Opcode) {
15134 switch (Opcode) {
15135 case ST_F32m:
15136 case ST_F64m:
15137 case ST_Frr:
15138 return true;
15139 }
15140 return false;
15141}
15142
15143bool isVPHSUBW(unsigned Opcode) {
15144 switch (Opcode) {
15145 case VPHSUBWYrm:
15146 case VPHSUBWYrr:
15147 case VPHSUBWrm:
15148 case VPHSUBWrr:
15149 return true;
15150 }
15151 return false;
15152}
15153
15154bool isVREDUCESS(unsigned Opcode) {
15155 switch (Opcode) {
15156 case VREDUCESSZrmi:
15157 case VREDUCESSZrmik:
15158 case VREDUCESSZrmikz:
15159 case VREDUCESSZrri:
15160 case VREDUCESSZrrib:
15161 case VREDUCESSZrribk:
15162 case VREDUCESSZrribkz:
15163 case VREDUCESSZrrik:
15164 case VREDUCESSZrrikz:
15165 return true;
15166 }
15167 return false;
15168}
15169
15170bool isFRNDINT(unsigned Opcode) {
15171 return Opcode == FRNDINT;
15172}
15173
15174bool isSHR(unsigned Opcode) {
15175 switch (Opcode) {
15176 case SHR16m1:
15177 case SHR16m1_EVEX:
15178 case SHR16m1_ND:
15179 case SHR16m1_NF:
15180 case SHR16m1_NF_ND:
15181 case SHR16mCL:
15182 case SHR16mCL_EVEX:
15183 case SHR16mCL_ND:
15184 case SHR16mCL_NF:
15185 case SHR16mCL_NF_ND:
15186 case SHR16mi:
15187 case SHR16mi_EVEX:
15188 case SHR16mi_ND:
15189 case SHR16mi_NF:
15190 case SHR16mi_NF_ND:
15191 case SHR16r1:
15192 case SHR16r1_EVEX:
15193 case SHR16r1_ND:
15194 case SHR16r1_NF:
15195 case SHR16r1_NF_ND:
15196 case SHR16rCL:
15197 case SHR16rCL_EVEX:
15198 case SHR16rCL_ND:
15199 case SHR16rCL_NF:
15200 case SHR16rCL_NF_ND:
15201 case SHR16ri:
15202 case SHR16ri_EVEX:
15203 case SHR16ri_ND:
15204 case SHR16ri_NF:
15205 case SHR16ri_NF_ND:
15206 case SHR32m1:
15207 case SHR32m1_EVEX:
15208 case SHR32m1_ND:
15209 case SHR32m1_NF:
15210 case SHR32m1_NF_ND:
15211 case SHR32mCL:
15212 case SHR32mCL_EVEX:
15213 case SHR32mCL_ND:
15214 case SHR32mCL_NF:
15215 case SHR32mCL_NF_ND:
15216 case SHR32mi:
15217 case SHR32mi_EVEX:
15218 case SHR32mi_ND:
15219 case SHR32mi_NF:
15220 case SHR32mi_NF_ND:
15221 case SHR32r1:
15222 case SHR32r1_EVEX:
15223 case SHR32r1_ND:
15224 case SHR32r1_NF:
15225 case SHR32r1_NF_ND:
15226 case SHR32rCL:
15227 case SHR32rCL_EVEX:
15228 case SHR32rCL_ND:
15229 case SHR32rCL_NF:
15230 case SHR32rCL_NF_ND:
15231 case SHR32ri:
15232 case SHR32ri_EVEX:
15233 case SHR32ri_ND:
15234 case SHR32ri_NF:
15235 case SHR32ri_NF_ND:
15236 case SHR64m1:
15237 case SHR64m1_EVEX:
15238 case SHR64m1_ND:
15239 case SHR64m1_NF:
15240 case SHR64m1_NF_ND:
15241 case SHR64mCL:
15242 case SHR64mCL_EVEX:
15243 case SHR64mCL_ND:
15244 case SHR64mCL_NF:
15245 case SHR64mCL_NF_ND:
15246 case SHR64mi:
15247 case SHR64mi_EVEX:
15248 case SHR64mi_ND:
15249 case SHR64mi_NF:
15250 case SHR64mi_NF_ND:
15251 case SHR64r1:
15252 case SHR64r1_EVEX:
15253 case SHR64r1_ND:
15254 case SHR64r1_NF:
15255 case SHR64r1_NF_ND:
15256 case SHR64rCL:
15257 case SHR64rCL_EVEX:
15258 case SHR64rCL_ND:
15259 case SHR64rCL_NF:
15260 case SHR64rCL_NF_ND:
15261 case SHR64ri:
15262 case SHR64ri_EVEX:
15263 case SHR64ri_ND:
15264 case SHR64ri_NF:
15265 case SHR64ri_NF_ND:
15266 case SHR8m1:
15267 case SHR8m1_EVEX:
15268 case SHR8m1_ND:
15269 case SHR8m1_NF:
15270 case SHR8m1_NF_ND:
15271 case SHR8mCL:
15272 case SHR8mCL_EVEX:
15273 case SHR8mCL_ND:
15274 case SHR8mCL_NF:
15275 case SHR8mCL_NF_ND:
15276 case SHR8mi:
15277 case SHR8mi_EVEX:
15278 case SHR8mi_ND:
15279 case SHR8mi_NF:
15280 case SHR8mi_NF_ND:
15281 case SHR8r1:
15282 case SHR8r1_EVEX:
15283 case SHR8r1_ND:
15284 case SHR8r1_NF:
15285 case SHR8r1_NF_ND:
15286 case SHR8rCL:
15287 case SHR8rCL_EVEX:
15288 case SHR8rCL_ND:
15289 case SHR8rCL_NF:
15290 case SHR8rCL_NF_ND:
15291 case SHR8ri:
15292 case SHR8ri_EVEX:
15293 case SHR8ri_ND:
15294 case SHR8ri_NF:
15295 case SHR8ri_NF_ND:
15296 return true;
15297 }
15298 return false;
15299}
15300
15301bool isLOOPNE(unsigned Opcode) {
15302 return Opcode == LOOPNE;
15303}
15304
15305bool isVCVTTPH2UQQ(unsigned Opcode) {
15306 switch (Opcode) {
15307 case VCVTTPH2UQQZ128rm:
15308 case VCVTTPH2UQQZ128rmb:
15309 case VCVTTPH2UQQZ128rmbk:
15310 case VCVTTPH2UQQZ128rmbkz:
15311 case VCVTTPH2UQQZ128rmk:
15312 case VCVTTPH2UQQZ128rmkz:
15313 case VCVTTPH2UQQZ128rr:
15314 case VCVTTPH2UQQZ128rrk:
15315 case VCVTTPH2UQQZ128rrkz:
15316 case VCVTTPH2UQQZ256rm:
15317 case VCVTTPH2UQQZ256rmb:
15318 case VCVTTPH2UQQZ256rmbk:
15319 case VCVTTPH2UQQZ256rmbkz:
15320 case VCVTTPH2UQQZ256rmk:
15321 case VCVTTPH2UQQZ256rmkz:
15322 case VCVTTPH2UQQZ256rr:
15323 case VCVTTPH2UQQZ256rrk:
15324 case VCVTTPH2UQQZ256rrkz:
15325 case VCVTTPH2UQQZrm:
15326 case VCVTTPH2UQQZrmb:
15327 case VCVTTPH2UQQZrmbk:
15328 case VCVTTPH2UQQZrmbkz:
15329 case VCVTTPH2UQQZrmk:
15330 case VCVTTPH2UQQZrmkz:
15331 case VCVTTPH2UQQZrr:
15332 case VCVTTPH2UQQZrrb:
15333 case VCVTTPH2UQQZrrbk:
15334 case VCVTTPH2UQQZrrbkz:
15335 case VCVTTPH2UQQZrrk:
15336 case VCVTTPH2UQQZrrkz:
15337 return true;
15338 }
15339 return false;
15340}
15341
15342bool isSHA1NEXTE(unsigned Opcode) {
15343 switch (Opcode) {
15344 case SHA1NEXTErm:
15345 case SHA1NEXTErr:
15346 return true;
15347 }
15348 return false;
15349}
15350
15351bool isVFMADD132SD(unsigned Opcode) {
15352 switch (Opcode) {
15353 case VFMADD132SDZm_Int:
15354 case VFMADD132SDZmk_Int:
15355 case VFMADD132SDZmkz_Int:
15356 case VFMADD132SDZr_Int:
15357 case VFMADD132SDZrb_Int:
15358 case VFMADD132SDZrbk_Int:
15359 case VFMADD132SDZrbkz_Int:
15360 case VFMADD132SDZrk_Int:
15361 case VFMADD132SDZrkz_Int:
15362 case VFMADD132SDm_Int:
15363 case VFMADD132SDr_Int:
15364 return true;
15365 }
15366 return false;
15367}
15368
15369bool isPSRAW(unsigned Opcode) {
15370 switch (Opcode) {
15371 case MMX_PSRAWri:
15372 case MMX_PSRAWrm:
15373 case MMX_PSRAWrr:
15374 case PSRAWri:
15375 case PSRAWrm:
15376 case PSRAWrr:
15377 return true;
15378 }
15379 return false;
15380}
15381
15382bool isVPBROADCASTQ(unsigned Opcode) {
15383 switch (Opcode) {
15384 case VPBROADCASTQYrm:
15385 case VPBROADCASTQYrr:
15386 case VPBROADCASTQZ128rm:
15387 case VPBROADCASTQZ128rmk:
15388 case VPBROADCASTQZ128rmkz:
15389 case VPBROADCASTQZ128rr:
15390 case VPBROADCASTQZ128rrk:
15391 case VPBROADCASTQZ128rrkz:
15392 case VPBROADCASTQZ256rm:
15393 case VPBROADCASTQZ256rmk:
15394 case VPBROADCASTQZ256rmkz:
15395 case VPBROADCASTQZ256rr:
15396 case VPBROADCASTQZ256rrk:
15397 case VPBROADCASTQZ256rrkz:
15398 case VPBROADCASTQZrm:
15399 case VPBROADCASTQZrmk:
15400 case VPBROADCASTQZrmkz:
15401 case VPBROADCASTQZrr:
15402 case VPBROADCASTQZrrk:
15403 case VPBROADCASTQZrrkz:
15404 case VPBROADCASTQrZ128rr:
15405 case VPBROADCASTQrZ128rrk:
15406 case VPBROADCASTQrZ128rrkz:
15407 case VPBROADCASTQrZ256rr:
15408 case VPBROADCASTQrZ256rrk:
15409 case VPBROADCASTQrZ256rrkz:
15410 case VPBROADCASTQrZrr:
15411 case VPBROADCASTQrZrrk:
15412 case VPBROADCASTQrZrrkz:
15413 case VPBROADCASTQrm:
15414 case VPBROADCASTQrr:
15415 return true;
15416 }
15417 return false;
15418}
15419
15420bool isCLC(unsigned Opcode) {
15421 return Opcode == CLC;
15422}
15423
15424bool isPOPAW(unsigned Opcode) {
15425 return Opcode == POPA16;
15426}
15427
15428bool isTCMMIMFP16PS(unsigned Opcode) {
15429 return Opcode == TCMMIMFP16PS;
15430}
15431
15432bool isVCVTTPS2UQQ(unsigned Opcode) {
15433 switch (Opcode) {
15434 case VCVTTPS2UQQZ128rm:
15435 case VCVTTPS2UQQZ128rmb:
15436 case VCVTTPS2UQQZ128rmbk:
15437 case VCVTTPS2UQQZ128rmbkz:
15438 case VCVTTPS2UQQZ128rmk:
15439 case VCVTTPS2UQQZ128rmkz:
15440 case VCVTTPS2UQQZ128rr:
15441 case VCVTTPS2UQQZ128rrk:
15442 case VCVTTPS2UQQZ128rrkz:
15443 case VCVTTPS2UQQZ256rm:
15444 case VCVTTPS2UQQZ256rmb:
15445 case VCVTTPS2UQQZ256rmbk:
15446 case VCVTTPS2UQQZ256rmbkz:
15447 case VCVTTPS2UQQZ256rmk:
15448 case VCVTTPS2UQQZ256rmkz:
15449 case VCVTTPS2UQQZ256rr:
15450 case VCVTTPS2UQQZ256rrk:
15451 case VCVTTPS2UQQZ256rrkz:
15452 case VCVTTPS2UQQZrm:
15453 case VCVTTPS2UQQZrmb:
15454 case VCVTTPS2UQQZrmbk:
15455 case VCVTTPS2UQQZrmbkz:
15456 case VCVTTPS2UQQZrmk:
15457 case VCVTTPS2UQQZrmkz:
15458 case VCVTTPS2UQQZrr:
15459 case VCVTTPS2UQQZrrb:
15460 case VCVTTPS2UQQZrrbk:
15461 case VCVTTPS2UQQZrrbkz:
15462 case VCVTTPS2UQQZrrk:
15463 case VCVTTPS2UQQZrrkz:
15464 return true;
15465 }
15466 return false;
15467}
15468
15469bool isVCVTQQ2PH(unsigned Opcode) {
15470 switch (Opcode) {
15471 case VCVTQQ2PHZ128rm:
15472 case VCVTQQ2PHZ128rmb:
15473 case VCVTQQ2PHZ128rmbk:
15474 case VCVTQQ2PHZ128rmbkz:
15475 case VCVTQQ2PHZ128rmk:
15476 case VCVTQQ2PHZ128rmkz:
15477 case VCVTQQ2PHZ128rr:
15478 case VCVTQQ2PHZ128rrk:
15479 case VCVTQQ2PHZ128rrkz:
15480 case VCVTQQ2PHZ256rm:
15481 case VCVTQQ2PHZ256rmb:
15482 case VCVTQQ2PHZ256rmbk:
15483 case VCVTQQ2PHZ256rmbkz:
15484 case VCVTQQ2PHZ256rmk:
15485 case VCVTQQ2PHZ256rmkz:
15486 case VCVTQQ2PHZ256rr:
15487 case VCVTQQ2PHZ256rrk:
15488 case VCVTQQ2PHZ256rrkz:
15489 case VCVTQQ2PHZrm:
15490 case VCVTQQ2PHZrmb:
15491 case VCVTQQ2PHZrmbk:
15492 case VCVTQQ2PHZrmbkz:
15493 case VCVTQQ2PHZrmk:
15494 case VCVTQQ2PHZrmkz:
15495 case VCVTQQ2PHZrr:
15496 case VCVTQQ2PHZrrb:
15497 case VCVTQQ2PHZrrbk:
15498 case VCVTQQ2PHZrrbkz:
15499 case VCVTQQ2PHZrrk:
15500 case VCVTQQ2PHZrrkz:
15501 return true;
15502 }
15503 return false;
15504}
15505
15506bool isVMOVUPD(unsigned Opcode) {
15507 switch (Opcode) {
15508 case VMOVUPDYmr:
15509 case VMOVUPDYrm:
15510 case VMOVUPDYrr:
15511 case VMOVUPDYrr_REV:
15512 case VMOVUPDZ128mr:
15513 case VMOVUPDZ128mrk:
15514 case VMOVUPDZ128rm:
15515 case VMOVUPDZ128rmk:
15516 case VMOVUPDZ128rmkz:
15517 case VMOVUPDZ128rr:
15518 case VMOVUPDZ128rr_REV:
15519 case VMOVUPDZ128rrk:
15520 case VMOVUPDZ128rrk_REV:
15521 case VMOVUPDZ128rrkz:
15522 case VMOVUPDZ128rrkz_REV:
15523 case VMOVUPDZ256mr:
15524 case VMOVUPDZ256mrk:
15525 case VMOVUPDZ256rm:
15526 case VMOVUPDZ256rmk:
15527 case VMOVUPDZ256rmkz:
15528 case VMOVUPDZ256rr:
15529 case VMOVUPDZ256rr_REV:
15530 case VMOVUPDZ256rrk:
15531 case VMOVUPDZ256rrk_REV:
15532 case VMOVUPDZ256rrkz:
15533 case VMOVUPDZ256rrkz_REV:
15534 case VMOVUPDZmr:
15535 case VMOVUPDZmrk:
15536 case VMOVUPDZrm:
15537 case VMOVUPDZrmk:
15538 case VMOVUPDZrmkz:
15539 case VMOVUPDZrr:
15540 case VMOVUPDZrr_REV:
15541 case VMOVUPDZrrk:
15542 case VMOVUPDZrrk_REV:
15543 case VMOVUPDZrrkz:
15544 case VMOVUPDZrrkz_REV:
15545 case VMOVUPDmr:
15546 case VMOVUPDrm:
15547 case VMOVUPDrr:
15548 case VMOVUPDrr_REV:
15549 return true;
15550 }
15551 return false;
15552}
15553
15554bool isFPTAN(unsigned Opcode) {
15555 return Opcode == FPTAN;
15556}
15557
15558bool isVMASKMOVPD(unsigned Opcode) {
15559 switch (Opcode) {
15560 case VMASKMOVPDYmr:
15561 case VMASKMOVPDYrm:
15562 case VMASKMOVPDmr:
15563 case VMASKMOVPDrm:
15564 return true;
15565 }
15566 return false;
15567}
15568
15569bool isVMOVLHPS(unsigned Opcode) {
15570 switch (Opcode) {
15571 case VMOVLHPSZrr:
15572 case VMOVLHPSrr:
15573 return true;
15574 }
15575 return false;
15576}
15577
15578bool isAESKEYGENASSIST(unsigned Opcode) {
15579 switch (Opcode) {
15580 case AESKEYGENASSIST128rm:
15581 case AESKEYGENASSIST128rr:
15582 return true;
15583 }
15584 return false;
15585}
15586
15587bool isXSAVEOPT64(unsigned Opcode) {
15588 return Opcode == XSAVEOPT64;
15589}
15590
15591bool isXSAVEC(unsigned Opcode) {
15592 return Opcode == XSAVEC;
15593}
15594
15595bool isVPLZCNTQ(unsigned Opcode) {
15596 switch (Opcode) {
15597 case VPLZCNTQZ128rm:
15598 case VPLZCNTQZ128rmb:
15599 case VPLZCNTQZ128rmbk:
15600 case VPLZCNTQZ128rmbkz:
15601 case VPLZCNTQZ128rmk:
15602 case VPLZCNTQZ128rmkz:
15603 case VPLZCNTQZ128rr:
15604 case VPLZCNTQZ128rrk:
15605 case VPLZCNTQZ128rrkz:
15606 case VPLZCNTQZ256rm:
15607 case VPLZCNTQZ256rmb:
15608 case VPLZCNTQZ256rmbk:
15609 case VPLZCNTQZ256rmbkz:
15610 case VPLZCNTQZ256rmk:
15611 case VPLZCNTQZ256rmkz:
15612 case VPLZCNTQZ256rr:
15613 case VPLZCNTQZ256rrk:
15614 case VPLZCNTQZ256rrkz:
15615 case VPLZCNTQZrm:
15616 case VPLZCNTQZrmb:
15617 case VPLZCNTQZrmbk:
15618 case VPLZCNTQZrmbkz:
15619 case VPLZCNTQZrmk:
15620 case VPLZCNTQZrmkz:
15621 case VPLZCNTQZrr:
15622 case VPLZCNTQZrrk:
15623 case VPLZCNTQZrrkz:
15624 return true;
15625 }
15626 return false;
15627}
15628
15629bool isVPSUBW(unsigned Opcode) {
15630 switch (Opcode) {
15631 case VPSUBWYrm:
15632 case VPSUBWYrr:
15633 case VPSUBWZ128rm:
15634 case VPSUBWZ128rmk:
15635 case VPSUBWZ128rmkz:
15636 case VPSUBWZ128rr:
15637 case VPSUBWZ128rrk:
15638 case VPSUBWZ128rrkz:
15639 case VPSUBWZ256rm:
15640 case VPSUBWZ256rmk:
15641 case VPSUBWZ256rmkz:
15642 case VPSUBWZ256rr:
15643 case VPSUBWZ256rrk:
15644 case VPSUBWZ256rrkz:
15645 case VPSUBWZrm:
15646 case VPSUBWZrmk:
15647 case VPSUBWZrmkz:
15648 case VPSUBWZrr:
15649 case VPSUBWZrrk:
15650 case VPSUBWZrrkz:
15651 case VPSUBWrm:
15652 case VPSUBWrr:
15653 return true;
15654 }
15655 return false;
15656}
15657
15658bool isCMPCCXADD(unsigned Opcode) {
15659 switch (Opcode) {
15660 case CMPCCXADDmr32:
15661 case CMPCCXADDmr32_EVEX:
15662 case CMPCCXADDmr64:
15663 case CMPCCXADDmr64_EVEX:
15664 return true;
15665 }
15666 return false;
15667}
15668
15669bool isVFMSUBADD213PH(unsigned Opcode) {
15670 switch (Opcode) {
15671 case VFMSUBADD213PHZ128m:
15672 case VFMSUBADD213PHZ128mb:
15673 case VFMSUBADD213PHZ128mbk:
15674 case VFMSUBADD213PHZ128mbkz:
15675 case VFMSUBADD213PHZ128mk:
15676 case VFMSUBADD213PHZ128mkz:
15677 case VFMSUBADD213PHZ128r:
15678 case VFMSUBADD213PHZ128rk:
15679 case VFMSUBADD213PHZ128rkz:
15680 case VFMSUBADD213PHZ256m:
15681 case VFMSUBADD213PHZ256mb:
15682 case VFMSUBADD213PHZ256mbk:
15683 case VFMSUBADD213PHZ256mbkz:
15684 case VFMSUBADD213PHZ256mk:
15685 case VFMSUBADD213PHZ256mkz:
15686 case VFMSUBADD213PHZ256r:
15687 case VFMSUBADD213PHZ256rk:
15688 case VFMSUBADD213PHZ256rkz:
15689 case VFMSUBADD213PHZm:
15690 case VFMSUBADD213PHZmb:
15691 case VFMSUBADD213PHZmbk:
15692 case VFMSUBADD213PHZmbkz:
15693 case VFMSUBADD213PHZmk:
15694 case VFMSUBADD213PHZmkz:
15695 case VFMSUBADD213PHZr:
15696 case VFMSUBADD213PHZrb:
15697 case VFMSUBADD213PHZrbk:
15698 case VFMSUBADD213PHZrbkz:
15699 case VFMSUBADD213PHZrk:
15700 case VFMSUBADD213PHZrkz:
15701 return true;
15702 }
15703 return false;
15704}
15705
15706bool isVFMADDSUBPD(unsigned Opcode) {
15707 switch (Opcode) {
15708 case VFMADDSUBPD4Ymr:
15709 case VFMADDSUBPD4Yrm:
15710 case VFMADDSUBPD4Yrr:
15711 case VFMADDSUBPD4Yrr_REV:
15712 case VFMADDSUBPD4mr:
15713 case VFMADDSUBPD4rm:
15714 case VFMADDSUBPD4rr:
15715 case VFMADDSUBPD4rr_REV:
15716 return true;
15717 }
15718 return false;
15719}
15720
15721bool isVPMINSW(unsigned Opcode) {
15722 switch (Opcode) {
15723 case VPMINSWYrm:
15724 case VPMINSWYrr:
15725 case VPMINSWZ128rm:
15726 case VPMINSWZ128rmk:
15727 case VPMINSWZ128rmkz:
15728 case VPMINSWZ128rr:
15729 case VPMINSWZ128rrk:
15730 case VPMINSWZ128rrkz:
15731 case VPMINSWZ256rm:
15732 case VPMINSWZ256rmk:
15733 case VPMINSWZ256rmkz:
15734 case VPMINSWZ256rr:
15735 case VPMINSWZ256rrk:
15736 case VPMINSWZ256rrkz:
15737 case VPMINSWZrm:
15738 case VPMINSWZrmk:
15739 case VPMINSWZrmkz:
15740 case VPMINSWZrr:
15741 case VPMINSWZrrk:
15742 case VPMINSWZrrkz:
15743 case VPMINSWrm:
15744 case VPMINSWrr:
15745 return true;
15746 }
15747 return false;
15748}
15749
15750bool isVFNMSUB132PS(unsigned Opcode) {
15751 switch (Opcode) {
15752 case VFNMSUB132PSYm:
15753 case VFNMSUB132PSYr:
15754 case VFNMSUB132PSZ128m:
15755 case VFNMSUB132PSZ128mb:
15756 case VFNMSUB132PSZ128mbk:
15757 case VFNMSUB132PSZ128mbkz:
15758 case VFNMSUB132PSZ128mk:
15759 case VFNMSUB132PSZ128mkz:
15760 case VFNMSUB132PSZ128r:
15761 case VFNMSUB132PSZ128rk:
15762 case VFNMSUB132PSZ128rkz:
15763 case VFNMSUB132PSZ256m:
15764 case VFNMSUB132PSZ256mb:
15765 case VFNMSUB132PSZ256mbk:
15766 case VFNMSUB132PSZ256mbkz:
15767 case VFNMSUB132PSZ256mk:
15768 case VFNMSUB132PSZ256mkz:
15769 case VFNMSUB132PSZ256r:
15770 case VFNMSUB132PSZ256rk:
15771 case VFNMSUB132PSZ256rkz:
15772 case VFNMSUB132PSZm:
15773 case VFNMSUB132PSZmb:
15774 case VFNMSUB132PSZmbk:
15775 case VFNMSUB132PSZmbkz:
15776 case VFNMSUB132PSZmk:
15777 case VFNMSUB132PSZmkz:
15778 case VFNMSUB132PSZr:
15779 case VFNMSUB132PSZrb:
15780 case VFNMSUB132PSZrbk:
15781 case VFNMSUB132PSZrbkz:
15782 case VFNMSUB132PSZrk:
15783 case VFNMSUB132PSZrkz:
15784 case VFNMSUB132PSm:
15785 case VFNMSUB132PSr:
15786 return true;
15787 }
15788 return false;
15789}
15790
15791bool isVMOVAPS(unsigned Opcode) {
15792 switch (Opcode) {
15793 case VMOVAPSYmr:
15794 case VMOVAPSYrm:
15795 case VMOVAPSYrr:
15796 case VMOVAPSYrr_REV:
15797 case VMOVAPSZ128mr:
15798 case VMOVAPSZ128mrk:
15799 case VMOVAPSZ128rm:
15800 case VMOVAPSZ128rmk:
15801 case VMOVAPSZ128rmkz:
15802 case VMOVAPSZ128rr:
15803 case VMOVAPSZ128rr_REV:
15804 case VMOVAPSZ128rrk:
15805 case VMOVAPSZ128rrk_REV:
15806 case VMOVAPSZ128rrkz:
15807 case VMOVAPSZ128rrkz_REV:
15808 case VMOVAPSZ256mr:
15809 case VMOVAPSZ256mrk:
15810 case VMOVAPSZ256rm:
15811 case VMOVAPSZ256rmk:
15812 case VMOVAPSZ256rmkz:
15813 case VMOVAPSZ256rr:
15814 case VMOVAPSZ256rr_REV:
15815 case VMOVAPSZ256rrk:
15816 case VMOVAPSZ256rrk_REV:
15817 case VMOVAPSZ256rrkz:
15818 case VMOVAPSZ256rrkz_REV:
15819 case VMOVAPSZmr:
15820 case VMOVAPSZmrk:
15821 case VMOVAPSZrm:
15822 case VMOVAPSZrmk:
15823 case VMOVAPSZrmkz:
15824 case VMOVAPSZrr:
15825 case VMOVAPSZrr_REV:
15826 case VMOVAPSZrrk:
15827 case VMOVAPSZrrk_REV:
15828 case VMOVAPSZrrkz:
15829 case VMOVAPSZrrkz_REV:
15830 case VMOVAPSmr:
15831 case VMOVAPSrm:
15832 case VMOVAPSrr:
15833 case VMOVAPSrr_REV:
15834 return true;
15835 }
15836 return false;
15837}
15838
15839bool isVPEXTRQ(unsigned Opcode) {
15840 switch (Opcode) {
15841 case VPEXTRQZmri:
15842 case VPEXTRQZrri:
15843 case VPEXTRQmri:
15844 case VPEXTRQrri:
15845 return true;
15846 }
15847 return false;
15848}
15849
15850bool isVSCALEFSH(unsigned Opcode) {
15851 switch (Opcode) {
15852 case VSCALEFSHZrm:
15853 case VSCALEFSHZrmk:
15854 case VSCALEFSHZrmkz:
15855 case VSCALEFSHZrr:
15856 case VSCALEFSHZrrb_Int:
15857 case VSCALEFSHZrrbk_Int:
15858 case VSCALEFSHZrrbkz_Int:
15859 case VSCALEFSHZrrk:
15860 case VSCALEFSHZrrkz:
15861 return true;
15862 }
15863 return false;
15864}
15865
15866bool isVCVTPD2PS(unsigned Opcode) {
15867 switch (Opcode) {
15868 case VCVTPD2PSYrm:
15869 case VCVTPD2PSYrr:
15870 case VCVTPD2PSZ128rm:
15871 case VCVTPD2PSZ128rmb:
15872 case VCVTPD2PSZ128rmbk:
15873 case VCVTPD2PSZ128rmbkz:
15874 case VCVTPD2PSZ128rmk:
15875 case VCVTPD2PSZ128rmkz:
15876 case VCVTPD2PSZ128rr:
15877 case VCVTPD2PSZ128rrk:
15878 case VCVTPD2PSZ128rrkz:
15879 case VCVTPD2PSZ256rm:
15880 case VCVTPD2PSZ256rmb:
15881 case VCVTPD2PSZ256rmbk:
15882 case VCVTPD2PSZ256rmbkz:
15883 case VCVTPD2PSZ256rmk:
15884 case VCVTPD2PSZ256rmkz:
15885 case VCVTPD2PSZ256rr:
15886 case VCVTPD2PSZ256rrk:
15887 case VCVTPD2PSZ256rrkz:
15888 case VCVTPD2PSZrm:
15889 case VCVTPD2PSZrmb:
15890 case VCVTPD2PSZrmbk:
15891 case VCVTPD2PSZrmbkz:
15892 case VCVTPD2PSZrmk:
15893 case VCVTPD2PSZrmkz:
15894 case VCVTPD2PSZrr:
15895 case VCVTPD2PSZrrb:
15896 case VCVTPD2PSZrrbk:
15897 case VCVTPD2PSZrrbkz:
15898 case VCVTPD2PSZrrk:
15899 case VCVTPD2PSZrrkz:
15900 case VCVTPD2PSrm:
15901 case VCVTPD2PSrr:
15902 return true;
15903 }
15904 return false;
15905}
15906
15907bool isCLGI(unsigned Opcode) {
15908 return Opcode == CLGI;
15909}
15910
15911bool isVAESDEC(unsigned Opcode) {
15912 switch (Opcode) {
15913 case VAESDECYrm:
15914 case VAESDECYrr:
15915 case VAESDECZ128rm:
15916 case VAESDECZ128rr:
15917 case VAESDECZ256rm:
15918 case VAESDECZ256rr:
15919 case VAESDECZrm:
15920 case VAESDECZrr:
15921 case VAESDECrm:
15922 case VAESDECrr:
15923 return true;
15924 }
15925 return false;
15926}
15927
15928bool isPFMUL(unsigned Opcode) {
15929 switch (Opcode) {
15930 case PFMULrm:
15931 case PFMULrr:
15932 return true;
15933 }
15934 return false;
15935}
15936
15937bool isVCVTBIASPH2BF8S(unsigned Opcode) {
15938 switch (Opcode) {
15939 case VCVTBIASPH2BF8SZ128rm:
15940 case VCVTBIASPH2BF8SZ128rmb:
15941 case VCVTBIASPH2BF8SZ128rmbk:
15942 case VCVTBIASPH2BF8SZ128rmbkz:
15943 case VCVTBIASPH2BF8SZ128rmk:
15944 case VCVTBIASPH2BF8SZ128rmkz:
15945 case VCVTBIASPH2BF8SZ128rr:
15946 case VCVTBIASPH2BF8SZ128rrk:
15947 case VCVTBIASPH2BF8SZ128rrkz:
15948 case VCVTBIASPH2BF8SZ256rm:
15949 case VCVTBIASPH2BF8SZ256rmb:
15950 case VCVTBIASPH2BF8SZ256rmbk:
15951 case VCVTBIASPH2BF8SZ256rmbkz:
15952 case VCVTBIASPH2BF8SZ256rmk:
15953 case VCVTBIASPH2BF8SZ256rmkz:
15954 case VCVTBIASPH2BF8SZ256rr:
15955 case VCVTBIASPH2BF8SZ256rrk:
15956 case VCVTBIASPH2BF8SZ256rrkz:
15957 case VCVTBIASPH2BF8SZrm:
15958 case VCVTBIASPH2BF8SZrmb:
15959 case VCVTBIASPH2BF8SZrmbk:
15960 case VCVTBIASPH2BF8SZrmbkz:
15961 case VCVTBIASPH2BF8SZrmk:
15962 case VCVTBIASPH2BF8SZrmkz:
15963 case VCVTBIASPH2BF8SZrr:
15964 case VCVTBIASPH2BF8SZrrk:
15965 case VCVTBIASPH2BF8SZrrkz:
15966 return true;
15967 }
15968 return false;
15969}
15970
15971bool isMOVDIRI(unsigned Opcode) {
15972 switch (Opcode) {
15973 case MOVDIRI32:
15974 case MOVDIRI32_EVEX:
15975 case MOVDIRI64:
15976 case MOVDIRI64_EVEX:
15977 return true;
15978 }
15979 return false;
15980}
15981
15982bool isSHUFPS(unsigned Opcode) {
15983 switch (Opcode) {
15984 case SHUFPSrmi:
15985 case SHUFPSrri:
15986 return true;
15987 }
15988 return false;
15989}
15990
15991bool isVFNMSUB231SS(unsigned Opcode) {
15992 switch (Opcode) {
15993 case VFNMSUB231SSZm_Int:
15994 case VFNMSUB231SSZmk_Int:
15995 case VFNMSUB231SSZmkz_Int:
15996 case VFNMSUB231SSZr_Int:
15997 case VFNMSUB231SSZrb_Int:
15998 case VFNMSUB231SSZrbk_Int:
15999 case VFNMSUB231SSZrbkz_Int:
16000 case VFNMSUB231SSZrk_Int:
16001 case VFNMSUB231SSZrkz_Int:
16002 case VFNMSUB231SSm_Int:
16003 case VFNMSUB231SSr_Int:
16004 return true;
16005 }
16006 return false;
16007}
16008
16009bool isVMWRITE(unsigned Opcode) {
16010 switch (Opcode) {
16011 case VMWRITE32rm:
16012 case VMWRITE32rr:
16013 case VMWRITE64rm:
16014 case VMWRITE64rr:
16015 return true;
16016 }
16017 return false;
16018}
16019
16020bool isVINSERTF128(unsigned Opcode) {
16021 switch (Opcode) {
16022 case VINSERTF128rmi:
16023 case VINSERTF128rri:
16024 return true;
16025 }
16026 return false;
16027}
16028
16029bool isFISUBR(unsigned Opcode) {
16030 switch (Opcode) {
16031 case SUBR_FI16m:
16032 case SUBR_FI32m:
16033 return true;
16034 }
16035 return false;
16036}
16037
16038bool isVINSERTI32X4(unsigned Opcode) {
16039 switch (Opcode) {
16040 case VINSERTI32X4Z256rmi:
16041 case VINSERTI32X4Z256rmik:
16042 case VINSERTI32X4Z256rmikz:
16043 case VINSERTI32X4Z256rri:
16044 case VINSERTI32X4Z256rrik:
16045 case VINSERTI32X4Z256rrikz:
16046 case VINSERTI32X4Zrmi:
16047 case VINSERTI32X4Zrmik:
16048 case VINSERTI32X4Zrmikz:
16049 case VINSERTI32X4Zrri:
16050 case VINSERTI32X4Zrrik:
16051 case VINSERTI32X4Zrrikz:
16052 return true;
16053 }
16054 return false;
16055}
16056
16057bool isVPSLLDQ(unsigned Opcode) {
16058 switch (Opcode) {
16059 case VPSLLDQYri:
16060 case VPSLLDQZ128mi:
16061 case VPSLLDQZ128ri:
16062 case VPSLLDQZ256mi:
16063 case VPSLLDQZ256ri:
16064 case VPSLLDQZmi:
16065 case VPSLLDQZri:
16066 case VPSLLDQri:
16067 return true;
16068 }
16069 return false;
16070}
16071
16072bool isPOPCNT(unsigned Opcode) {
16073 switch (Opcode) {
16074 case POPCNT16rm:
16075 case POPCNT16rm_EVEX:
16076 case POPCNT16rm_NF:
16077 case POPCNT16rr:
16078 case POPCNT16rr_EVEX:
16079 case POPCNT16rr_NF:
16080 case POPCNT32rm:
16081 case POPCNT32rm_EVEX:
16082 case POPCNT32rm_NF:
16083 case POPCNT32rr:
16084 case POPCNT32rr_EVEX:
16085 case POPCNT32rr_NF:
16086 case POPCNT64rm:
16087 case POPCNT64rm_EVEX:
16088 case POPCNT64rm_NF:
16089 case POPCNT64rr:
16090 case POPCNT64rr_EVEX:
16091 case POPCNT64rr_NF:
16092 return true;
16093 }
16094 return false;
16095}
16096
16097bool isVXORPD(unsigned Opcode) {
16098 switch (Opcode) {
16099 case VXORPDYrm:
16100 case VXORPDYrr:
16101 case VXORPDZ128rm:
16102 case VXORPDZ128rmb:
16103 case VXORPDZ128rmbk:
16104 case VXORPDZ128rmbkz:
16105 case VXORPDZ128rmk:
16106 case VXORPDZ128rmkz:
16107 case VXORPDZ128rr:
16108 case VXORPDZ128rrk:
16109 case VXORPDZ128rrkz:
16110 case VXORPDZ256rm:
16111 case VXORPDZ256rmb:
16112 case VXORPDZ256rmbk:
16113 case VXORPDZ256rmbkz:
16114 case VXORPDZ256rmk:
16115 case VXORPDZ256rmkz:
16116 case VXORPDZ256rr:
16117 case VXORPDZ256rrk:
16118 case VXORPDZ256rrkz:
16119 case VXORPDZrm:
16120 case VXORPDZrmb:
16121 case VXORPDZrmbk:
16122 case VXORPDZrmbkz:
16123 case VXORPDZrmk:
16124 case VXORPDZrmkz:
16125 case VXORPDZrr:
16126 case VXORPDZrrk:
16127 case VXORPDZrrkz:
16128 case VXORPDrm:
16129 case VXORPDrr:
16130 return true;
16131 }
16132 return false;
16133}
16134
16135bool isXLATB(unsigned Opcode) {
16136 return Opcode == XLAT;
16137}
16138
16139bool isDIV(unsigned Opcode) {
16140 switch (Opcode) {
16141 case DIV16m:
16142 case DIV16m_EVEX:
16143 case DIV16m_NF:
16144 case DIV16r:
16145 case DIV16r_EVEX:
16146 case DIV16r_NF:
16147 case DIV32m:
16148 case DIV32m_EVEX:
16149 case DIV32m_NF:
16150 case DIV32r:
16151 case DIV32r_EVEX:
16152 case DIV32r_NF:
16153 case DIV64m:
16154 case DIV64m_EVEX:
16155 case DIV64m_NF:
16156 case DIV64r:
16157 case DIV64r_EVEX:
16158 case DIV64r_NF:
16159 case DIV8m:
16160 case DIV8m_EVEX:
16161 case DIV8m_NF:
16162 case DIV8r:
16163 case DIV8r_EVEX:
16164 case DIV8r_NF:
16165 return true;
16166 }
16167 return false;
16168}
16169
16170bool isVPSHLDVQ(unsigned Opcode) {
16171 switch (Opcode) {
16172 case VPSHLDVQZ128m:
16173 case VPSHLDVQZ128mb:
16174 case VPSHLDVQZ128mbk:
16175 case VPSHLDVQZ128mbkz:
16176 case VPSHLDVQZ128mk:
16177 case VPSHLDVQZ128mkz:
16178 case VPSHLDVQZ128r:
16179 case VPSHLDVQZ128rk:
16180 case VPSHLDVQZ128rkz:
16181 case VPSHLDVQZ256m:
16182 case VPSHLDVQZ256mb:
16183 case VPSHLDVQZ256mbk:
16184 case VPSHLDVQZ256mbkz:
16185 case VPSHLDVQZ256mk:
16186 case VPSHLDVQZ256mkz:
16187 case VPSHLDVQZ256r:
16188 case VPSHLDVQZ256rk:
16189 case VPSHLDVQZ256rkz:
16190 case VPSHLDVQZm:
16191 case VPSHLDVQZmb:
16192 case VPSHLDVQZmbk:
16193 case VPSHLDVQZmbkz:
16194 case VPSHLDVQZmk:
16195 case VPSHLDVQZmkz:
16196 case VPSHLDVQZr:
16197 case VPSHLDVQZrk:
16198 case VPSHLDVQZrkz:
16199 return true;
16200 }
16201 return false;
16202}
16203
16204bool isMOVDDUP(unsigned Opcode) {
16205 switch (Opcode) {
16206 case MOVDDUPrm:
16207 case MOVDDUPrr:
16208 return true;
16209 }
16210 return false;
16211}
16212
16213bool isVMOVDQU64(unsigned Opcode) {
16214 switch (Opcode) {
16215 case VMOVDQU64Z128mr:
16216 case VMOVDQU64Z128mrk:
16217 case VMOVDQU64Z128rm:
16218 case VMOVDQU64Z128rmk:
16219 case VMOVDQU64Z128rmkz:
16220 case VMOVDQU64Z128rr:
16221 case VMOVDQU64Z128rr_REV:
16222 case VMOVDQU64Z128rrk:
16223 case VMOVDQU64Z128rrk_REV:
16224 case VMOVDQU64Z128rrkz:
16225 case VMOVDQU64Z128rrkz_REV:
16226 case VMOVDQU64Z256mr:
16227 case VMOVDQU64Z256mrk:
16228 case VMOVDQU64Z256rm:
16229 case VMOVDQU64Z256rmk:
16230 case VMOVDQU64Z256rmkz:
16231 case VMOVDQU64Z256rr:
16232 case VMOVDQU64Z256rr_REV:
16233 case VMOVDQU64Z256rrk:
16234 case VMOVDQU64Z256rrk_REV:
16235 case VMOVDQU64Z256rrkz:
16236 case VMOVDQU64Z256rrkz_REV:
16237 case VMOVDQU64Zmr:
16238 case VMOVDQU64Zmrk:
16239 case VMOVDQU64Zrm:
16240 case VMOVDQU64Zrmk:
16241 case VMOVDQU64Zrmkz:
16242 case VMOVDQU64Zrr:
16243 case VMOVDQU64Zrr_REV:
16244 case VMOVDQU64Zrrk:
16245 case VMOVDQU64Zrrk_REV:
16246 case VMOVDQU64Zrrkz:
16247 case VMOVDQU64Zrrkz_REV:
16248 return true;
16249 }
16250 return false;
16251}
16252
16253bool isVPCOMPRESSQ(unsigned Opcode) {
16254 switch (Opcode) {
16255 case VPCOMPRESSQZ128mr:
16256 case VPCOMPRESSQZ128mrk:
16257 case VPCOMPRESSQZ128rr:
16258 case VPCOMPRESSQZ128rrk:
16259 case VPCOMPRESSQZ128rrkz:
16260 case VPCOMPRESSQZ256mr:
16261 case VPCOMPRESSQZ256mrk:
16262 case VPCOMPRESSQZ256rr:
16263 case VPCOMPRESSQZ256rrk:
16264 case VPCOMPRESSQZ256rrkz:
16265 case VPCOMPRESSQZmr:
16266 case VPCOMPRESSQZmrk:
16267 case VPCOMPRESSQZrr:
16268 case VPCOMPRESSQZrrk:
16269 case VPCOMPRESSQZrrkz:
16270 return true;
16271 }
16272 return false;
16273}
16274
16275bool isVFMSUBADD132PD(unsigned Opcode) {
16276 switch (Opcode) {
16277 case VFMSUBADD132PDYm:
16278 case VFMSUBADD132PDYr:
16279 case VFMSUBADD132PDZ128m:
16280 case VFMSUBADD132PDZ128mb:
16281 case VFMSUBADD132PDZ128mbk:
16282 case VFMSUBADD132PDZ128mbkz:
16283 case VFMSUBADD132PDZ128mk:
16284 case VFMSUBADD132PDZ128mkz:
16285 case VFMSUBADD132PDZ128r:
16286 case VFMSUBADD132PDZ128rk:
16287 case VFMSUBADD132PDZ128rkz:
16288 case VFMSUBADD132PDZ256m:
16289 case VFMSUBADD132PDZ256mb:
16290 case VFMSUBADD132PDZ256mbk:
16291 case VFMSUBADD132PDZ256mbkz:
16292 case VFMSUBADD132PDZ256mk:
16293 case VFMSUBADD132PDZ256mkz:
16294 case VFMSUBADD132PDZ256r:
16295 case VFMSUBADD132PDZ256rk:
16296 case VFMSUBADD132PDZ256rkz:
16297 case VFMSUBADD132PDZm:
16298 case VFMSUBADD132PDZmb:
16299 case VFMSUBADD132PDZmbk:
16300 case VFMSUBADD132PDZmbkz:
16301 case VFMSUBADD132PDZmk:
16302 case VFMSUBADD132PDZmkz:
16303 case VFMSUBADD132PDZr:
16304 case VFMSUBADD132PDZrb:
16305 case VFMSUBADD132PDZrbk:
16306 case VFMSUBADD132PDZrbkz:
16307 case VFMSUBADD132PDZrk:
16308 case VFMSUBADD132PDZrkz:
16309 case VFMSUBADD132PDm:
16310 case VFMSUBADD132PDr:
16311 return true;
16312 }
16313 return false;
16314}
16315
16316bool isADDSD(unsigned Opcode) {
16317 switch (Opcode) {
16318 case ADDSDrm_Int:
16319 case ADDSDrr_Int:
16320 return true;
16321 }
16322 return false;
16323}
16324
16325bool isBLENDPD(unsigned Opcode) {
16326 switch (Opcode) {
16327 case BLENDPDrmi:
16328 case BLENDPDrri:
16329 return true;
16330 }
16331 return false;
16332}
16333
16334bool isVPERMILPD(unsigned Opcode) {
16335 switch (Opcode) {
16336 case VPERMILPDYmi:
16337 case VPERMILPDYri:
16338 case VPERMILPDYrm:
16339 case VPERMILPDYrr:
16340 case VPERMILPDZ128mbi:
16341 case VPERMILPDZ128mbik:
16342 case VPERMILPDZ128mbikz:
16343 case VPERMILPDZ128mi:
16344 case VPERMILPDZ128mik:
16345 case VPERMILPDZ128mikz:
16346 case VPERMILPDZ128ri:
16347 case VPERMILPDZ128rik:
16348 case VPERMILPDZ128rikz:
16349 case VPERMILPDZ128rm:
16350 case VPERMILPDZ128rmb:
16351 case VPERMILPDZ128rmbk:
16352 case VPERMILPDZ128rmbkz:
16353 case VPERMILPDZ128rmk:
16354 case VPERMILPDZ128rmkz:
16355 case VPERMILPDZ128rr:
16356 case VPERMILPDZ128rrk:
16357 case VPERMILPDZ128rrkz:
16358 case VPERMILPDZ256mbi:
16359 case VPERMILPDZ256mbik:
16360 case VPERMILPDZ256mbikz:
16361 case VPERMILPDZ256mi:
16362 case VPERMILPDZ256mik:
16363 case VPERMILPDZ256mikz:
16364 case VPERMILPDZ256ri:
16365 case VPERMILPDZ256rik:
16366 case VPERMILPDZ256rikz:
16367 case VPERMILPDZ256rm:
16368 case VPERMILPDZ256rmb:
16369 case VPERMILPDZ256rmbk:
16370 case VPERMILPDZ256rmbkz:
16371 case VPERMILPDZ256rmk:
16372 case VPERMILPDZ256rmkz:
16373 case VPERMILPDZ256rr:
16374 case VPERMILPDZ256rrk:
16375 case VPERMILPDZ256rrkz:
16376 case VPERMILPDZmbi:
16377 case VPERMILPDZmbik:
16378 case VPERMILPDZmbikz:
16379 case VPERMILPDZmi:
16380 case VPERMILPDZmik:
16381 case VPERMILPDZmikz:
16382 case VPERMILPDZri:
16383 case VPERMILPDZrik:
16384 case VPERMILPDZrikz:
16385 case VPERMILPDZrm:
16386 case VPERMILPDZrmb:
16387 case VPERMILPDZrmbk:
16388 case VPERMILPDZrmbkz:
16389 case VPERMILPDZrmk:
16390 case VPERMILPDZrmkz:
16391 case VPERMILPDZrr:
16392 case VPERMILPDZrrk:
16393 case VPERMILPDZrrkz:
16394 case VPERMILPDmi:
16395 case VPERMILPDri:
16396 case VPERMILPDrm:
16397 case VPERMILPDrr:
16398 return true;
16399 }
16400 return false;
16401}
16402
16403bool isPMADDUBSW(unsigned Opcode) {
16404 switch (Opcode) {
16405 case MMX_PMADDUBSWrm:
16406 case MMX_PMADDUBSWrr:
16407 case PMADDUBSWrm:
16408 case PMADDUBSWrr:
16409 return true;
16410 }
16411 return false;
16412}
16413
16414bool isPOPFD(unsigned Opcode) {
16415 return Opcode == POPF32;
16416}
16417
16418bool isCMPSW(unsigned Opcode) {
16419 return Opcode == CMPSW;
16420}
16421
16422bool isLDMXCSR(unsigned Opcode) {
16423 return Opcode == LDMXCSR;
16424}
16425
16426bool isVMULPS(unsigned Opcode) {
16427 switch (Opcode) {
16428 case VMULPSYrm:
16429 case VMULPSYrr:
16430 case VMULPSZ128rm:
16431 case VMULPSZ128rmb:
16432 case VMULPSZ128rmbk:
16433 case VMULPSZ128rmbkz:
16434 case VMULPSZ128rmk:
16435 case VMULPSZ128rmkz:
16436 case VMULPSZ128rr:
16437 case VMULPSZ128rrk:
16438 case VMULPSZ128rrkz:
16439 case VMULPSZ256rm:
16440 case VMULPSZ256rmb:
16441 case VMULPSZ256rmbk:
16442 case VMULPSZ256rmbkz:
16443 case VMULPSZ256rmk:
16444 case VMULPSZ256rmkz:
16445 case VMULPSZ256rr:
16446 case VMULPSZ256rrk:
16447 case VMULPSZ256rrkz:
16448 case VMULPSZrm:
16449 case VMULPSZrmb:
16450 case VMULPSZrmbk:
16451 case VMULPSZrmbkz:
16452 case VMULPSZrmk:
16453 case VMULPSZrmkz:
16454 case VMULPSZrr:
16455 case VMULPSZrrb:
16456 case VMULPSZrrbk:
16457 case VMULPSZrrbkz:
16458 case VMULPSZrrk:
16459 case VMULPSZrrkz:
16460 case VMULPSrm:
16461 case VMULPSrr:
16462 return true;
16463 }
16464 return false;
16465}
16466
16467bool isVROUNDSD(unsigned Opcode) {
16468 switch (Opcode) {
16469 case VROUNDSDmi_Int:
16470 case VROUNDSDri_Int:
16471 return true;
16472 }
16473 return false;
16474}
16475
16476bool isVFMADD132PD(unsigned Opcode) {
16477 switch (Opcode) {
16478 case VFMADD132PDYm:
16479 case VFMADD132PDYr:
16480 case VFMADD132PDZ128m:
16481 case VFMADD132PDZ128mb:
16482 case VFMADD132PDZ128mbk:
16483 case VFMADD132PDZ128mbkz:
16484 case VFMADD132PDZ128mk:
16485 case VFMADD132PDZ128mkz:
16486 case VFMADD132PDZ128r:
16487 case VFMADD132PDZ128rk:
16488 case VFMADD132PDZ128rkz:
16489 case VFMADD132PDZ256m:
16490 case VFMADD132PDZ256mb:
16491 case VFMADD132PDZ256mbk:
16492 case VFMADD132PDZ256mbkz:
16493 case VFMADD132PDZ256mk:
16494 case VFMADD132PDZ256mkz:
16495 case VFMADD132PDZ256r:
16496 case VFMADD132PDZ256rk:
16497 case VFMADD132PDZ256rkz:
16498 case VFMADD132PDZm:
16499 case VFMADD132PDZmb:
16500 case VFMADD132PDZmbk:
16501 case VFMADD132PDZmbkz:
16502 case VFMADD132PDZmk:
16503 case VFMADD132PDZmkz:
16504 case VFMADD132PDZr:
16505 case VFMADD132PDZrb:
16506 case VFMADD132PDZrbk:
16507 case VFMADD132PDZrbkz:
16508 case VFMADD132PDZrk:
16509 case VFMADD132PDZrkz:
16510 case VFMADD132PDm:
16511 case VFMADD132PDr:
16512 return true;
16513 }
16514 return false;
16515}
16516
16517bool isVPANDQ(unsigned Opcode) {
16518 switch (Opcode) {
16519 case VPANDQZ128rm:
16520 case VPANDQZ128rmb:
16521 case VPANDQZ128rmbk:
16522 case VPANDQZ128rmbkz:
16523 case VPANDQZ128rmk:
16524 case VPANDQZ128rmkz:
16525 case VPANDQZ128rr:
16526 case VPANDQZ128rrk:
16527 case VPANDQZ128rrkz:
16528 case VPANDQZ256rm:
16529 case VPANDQZ256rmb:
16530 case VPANDQZ256rmbk:
16531 case VPANDQZ256rmbkz:
16532 case VPANDQZ256rmk:
16533 case VPANDQZ256rmkz:
16534 case VPANDQZ256rr:
16535 case VPANDQZ256rrk:
16536 case VPANDQZ256rrkz:
16537 case VPANDQZrm:
16538 case VPANDQZrmb:
16539 case VPANDQZrmbk:
16540 case VPANDQZrmbkz:
16541 case VPANDQZrmk:
16542 case VPANDQZrmkz:
16543 case VPANDQZrr:
16544 case VPANDQZrrk:
16545 case VPANDQZrrkz:
16546 return true;
16547 }
16548 return false;
16549}
16550
16551bool isVPSRAQ(unsigned Opcode) {
16552 switch (Opcode) {
16553 case VPSRAQZ128mbi:
16554 case VPSRAQZ128mbik:
16555 case VPSRAQZ128mbikz:
16556 case VPSRAQZ128mi:
16557 case VPSRAQZ128mik:
16558 case VPSRAQZ128mikz:
16559 case VPSRAQZ128ri:
16560 case VPSRAQZ128rik:
16561 case VPSRAQZ128rikz:
16562 case VPSRAQZ128rm:
16563 case VPSRAQZ128rmk:
16564 case VPSRAQZ128rmkz:
16565 case VPSRAQZ128rr:
16566 case VPSRAQZ128rrk:
16567 case VPSRAQZ128rrkz:
16568 case VPSRAQZ256mbi:
16569 case VPSRAQZ256mbik:
16570 case VPSRAQZ256mbikz:
16571 case VPSRAQZ256mi:
16572 case VPSRAQZ256mik:
16573 case VPSRAQZ256mikz:
16574 case VPSRAQZ256ri:
16575 case VPSRAQZ256rik:
16576 case VPSRAQZ256rikz:
16577 case VPSRAQZ256rm:
16578 case VPSRAQZ256rmk:
16579 case VPSRAQZ256rmkz:
16580 case VPSRAQZ256rr:
16581 case VPSRAQZ256rrk:
16582 case VPSRAQZ256rrkz:
16583 case VPSRAQZmbi:
16584 case VPSRAQZmbik:
16585 case VPSRAQZmbikz:
16586 case VPSRAQZmi:
16587 case VPSRAQZmik:
16588 case VPSRAQZmikz:
16589 case VPSRAQZri:
16590 case VPSRAQZrik:
16591 case VPSRAQZrikz:
16592 case VPSRAQZrm:
16593 case VPSRAQZrmk:
16594 case VPSRAQZrmkz:
16595 case VPSRAQZrr:
16596 case VPSRAQZrrk:
16597 case VPSRAQZrrkz:
16598 return true;
16599 }
16600 return false;
16601}
16602
16603bool isVCOMISD(unsigned Opcode) {
16604 switch (Opcode) {
16605 case VCOMISDZrm:
16606 case VCOMISDZrr:
16607 case VCOMISDZrrb:
16608 case VCOMISDrm:
16609 case VCOMISDrr:
16610 return true;
16611 }
16612 return false;
16613}
16614
16615bool isVCVTBIASPH2BF8(unsigned Opcode) {
16616 switch (Opcode) {
16617 case VCVTBIASPH2BF8Z128rm:
16618 case VCVTBIASPH2BF8Z128rmb:
16619 case VCVTBIASPH2BF8Z128rmbk:
16620 case VCVTBIASPH2BF8Z128rmbkz:
16621 case VCVTBIASPH2BF8Z128rmk:
16622 case VCVTBIASPH2BF8Z128rmkz:
16623 case VCVTBIASPH2BF8Z128rr:
16624 case VCVTBIASPH2BF8Z128rrk:
16625 case VCVTBIASPH2BF8Z128rrkz:
16626 case VCVTBIASPH2BF8Z256rm:
16627 case VCVTBIASPH2BF8Z256rmb:
16628 case VCVTBIASPH2BF8Z256rmbk:
16629 case VCVTBIASPH2BF8Z256rmbkz:
16630 case VCVTBIASPH2BF8Z256rmk:
16631 case VCVTBIASPH2BF8Z256rmkz:
16632 case VCVTBIASPH2BF8Z256rr:
16633 case VCVTBIASPH2BF8Z256rrk:
16634 case VCVTBIASPH2BF8Z256rrkz:
16635 case VCVTBIASPH2BF8Zrm:
16636 case VCVTBIASPH2BF8Zrmb:
16637 case VCVTBIASPH2BF8Zrmbk:
16638 case VCVTBIASPH2BF8Zrmbkz:
16639 case VCVTBIASPH2BF8Zrmk:
16640 case VCVTBIASPH2BF8Zrmkz:
16641 case VCVTBIASPH2BF8Zrr:
16642 case VCVTBIASPH2BF8Zrrk:
16643 case VCVTBIASPH2BF8Zrrkz:
16644 return true;
16645 }
16646 return false;
16647}
16648
16649bool isFFREEP(unsigned Opcode) {
16650 return Opcode == FFREEP;
16651}
16652
16653bool isT2RPNTLVWZ1RS(unsigned Opcode) {
16654 switch (Opcode) {
16655 case T2RPNTLVWZ1RS:
16656 case T2RPNTLVWZ1RS_EVEX:
16657 return true;
16658 }
16659 return false;
16660}
16661
16662bool isVCMPPD(unsigned Opcode) {
16663 switch (Opcode) {
16664 case VCMPPDYrmi:
16665 case VCMPPDYrri:
16666 case VCMPPDZ128rmbi:
16667 case VCMPPDZ128rmbik:
16668 case VCMPPDZ128rmi:
16669 case VCMPPDZ128rmik:
16670 case VCMPPDZ128rri:
16671 case VCMPPDZ128rrik:
16672 case VCMPPDZ256rmbi:
16673 case VCMPPDZ256rmbik:
16674 case VCMPPDZ256rmi:
16675 case VCMPPDZ256rmik:
16676 case VCMPPDZ256rri:
16677 case VCMPPDZ256rrik:
16678 case VCMPPDZrmbi:
16679 case VCMPPDZrmbik:
16680 case VCMPPDZrmi:
16681 case VCMPPDZrmik:
16682 case VCMPPDZrri:
16683 case VCMPPDZrrib:
16684 case VCMPPDZrribk:
16685 case VCMPPDZrrik:
16686 case VCMPPDrmi:
16687 case VCMPPDrri:
16688 return true;
16689 }
16690 return false;
16691}
16692
16693bool isVFNMADD213PD(unsigned Opcode) {
16694 switch (Opcode) {
16695 case VFNMADD213PDYm:
16696 case VFNMADD213PDYr:
16697 case VFNMADD213PDZ128m:
16698 case VFNMADD213PDZ128mb:
16699 case VFNMADD213PDZ128mbk:
16700 case VFNMADD213PDZ128mbkz:
16701 case VFNMADD213PDZ128mk:
16702 case VFNMADD213PDZ128mkz:
16703 case VFNMADD213PDZ128r:
16704 case VFNMADD213PDZ128rk:
16705 case VFNMADD213PDZ128rkz:
16706 case VFNMADD213PDZ256m:
16707 case VFNMADD213PDZ256mb:
16708 case VFNMADD213PDZ256mbk:
16709 case VFNMADD213PDZ256mbkz:
16710 case VFNMADD213PDZ256mk:
16711 case VFNMADD213PDZ256mkz:
16712 case VFNMADD213PDZ256r:
16713 case VFNMADD213PDZ256rk:
16714 case VFNMADD213PDZ256rkz:
16715 case VFNMADD213PDZm:
16716 case VFNMADD213PDZmb:
16717 case VFNMADD213PDZmbk:
16718 case VFNMADD213PDZmbkz:
16719 case VFNMADD213PDZmk:
16720 case VFNMADD213PDZmkz:
16721 case VFNMADD213PDZr:
16722 case VFNMADD213PDZrb:
16723 case VFNMADD213PDZrbk:
16724 case VFNMADD213PDZrbkz:
16725 case VFNMADD213PDZrk:
16726 case VFNMADD213PDZrkz:
16727 case VFNMADD213PDm:
16728 case VFNMADD213PDr:
16729 return true;
16730 }
16731 return false;
16732}
16733
16734bool isVFNMSUB132PH(unsigned Opcode) {
16735 switch (Opcode) {
16736 case VFNMSUB132PHZ128m:
16737 case VFNMSUB132PHZ128mb:
16738 case VFNMSUB132PHZ128mbk:
16739 case VFNMSUB132PHZ128mbkz:
16740 case VFNMSUB132PHZ128mk:
16741 case VFNMSUB132PHZ128mkz:
16742 case VFNMSUB132PHZ128r:
16743 case VFNMSUB132PHZ128rk:
16744 case VFNMSUB132PHZ128rkz:
16745 case VFNMSUB132PHZ256m:
16746 case VFNMSUB132PHZ256mb:
16747 case VFNMSUB132PHZ256mbk:
16748 case VFNMSUB132PHZ256mbkz:
16749 case VFNMSUB132PHZ256mk:
16750 case VFNMSUB132PHZ256mkz:
16751 case VFNMSUB132PHZ256r:
16752 case VFNMSUB132PHZ256rk:
16753 case VFNMSUB132PHZ256rkz:
16754 case VFNMSUB132PHZm:
16755 case VFNMSUB132PHZmb:
16756 case VFNMSUB132PHZmbk:
16757 case VFNMSUB132PHZmbkz:
16758 case VFNMSUB132PHZmk:
16759 case VFNMSUB132PHZmkz:
16760 case VFNMSUB132PHZr:
16761 case VFNMSUB132PHZrb:
16762 case VFNMSUB132PHZrbk:
16763 case VFNMSUB132PHZrbkz:
16764 case VFNMSUB132PHZrk:
16765 case VFNMSUB132PHZrkz:
16766 return true;
16767 }
16768 return false;
16769}
16770
16771bool isVPHADDBW(unsigned Opcode) {
16772 switch (Opcode) {
16773 case VPHADDBWrm:
16774 case VPHADDBWrr:
16775 return true;
16776 }
16777 return false;
16778}
16779
16780bool isVPPERM(unsigned Opcode) {
16781 switch (Opcode) {
16782 case VPPERMrmr:
16783 case VPPERMrrm:
16784 case VPPERMrrr:
16785 case VPPERMrrr_REV:
16786 return true;
16787 }
16788 return false;
16789}
16790
16791bool isVCVTPS2PD(unsigned Opcode) {
16792 switch (Opcode) {
16793 case VCVTPS2PDYrm:
16794 case VCVTPS2PDYrr:
16795 case VCVTPS2PDZ128rm:
16796 case VCVTPS2PDZ128rmb:
16797 case VCVTPS2PDZ128rmbk:
16798 case VCVTPS2PDZ128rmbkz:
16799 case VCVTPS2PDZ128rmk:
16800 case VCVTPS2PDZ128rmkz:
16801 case VCVTPS2PDZ128rr:
16802 case VCVTPS2PDZ128rrk:
16803 case VCVTPS2PDZ128rrkz:
16804 case VCVTPS2PDZ256rm:
16805 case VCVTPS2PDZ256rmb:
16806 case VCVTPS2PDZ256rmbk:
16807 case VCVTPS2PDZ256rmbkz:
16808 case VCVTPS2PDZ256rmk:
16809 case VCVTPS2PDZ256rmkz:
16810 case VCVTPS2PDZ256rr:
16811 case VCVTPS2PDZ256rrk:
16812 case VCVTPS2PDZ256rrkz:
16813 case VCVTPS2PDZrm:
16814 case VCVTPS2PDZrmb:
16815 case VCVTPS2PDZrmbk:
16816 case VCVTPS2PDZrmbkz:
16817 case VCVTPS2PDZrmk:
16818 case VCVTPS2PDZrmkz:
16819 case VCVTPS2PDZrr:
16820 case VCVTPS2PDZrrb:
16821 case VCVTPS2PDZrrbk:
16822 case VCVTPS2PDZrrbkz:
16823 case VCVTPS2PDZrrk:
16824 case VCVTPS2PDZrrkz:
16825 case VCVTPS2PDrm:
16826 case VCVTPS2PDrr:
16827 return true;
16828 }
16829 return false;
16830}
16831
16832bool isCBW(unsigned Opcode) {
16833 return Opcode == CBW;
16834}
16835
16836bool isVMOVUPS(unsigned Opcode) {
16837 switch (Opcode) {
16838 case VMOVUPSYmr:
16839 case VMOVUPSYrm:
16840 case VMOVUPSYrr:
16841 case VMOVUPSYrr_REV:
16842 case VMOVUPSZ128mr:
16843 case VMOVUPSZ128mrk:
16844 case VMOVUPSZ128rm:
16845 case VMOVUPSZ128rmk:
16846 case VMOVUPSZ128rmkz:
16847 case VMOVUPSZ128rr:
16848 case VMOVUPSZ128rr_REV:
16849 case VMOVUPSZ128rrk:
16850 case VMOVUPSZ128rrk_REV:
16851 case VMOVUPSZ128rrkz:
16852 case VMOVUPSZ128rrkz_REV:
16853 case VMOVUPSZ256mr:
16854 case VMOVUPSZ256mrk:
16855 case VMOVUPSZ256rm:
16856 case VMOVUPSZ256rmk:
16857 case VMOVUPSZ256rmkz:
16858 case VMOVUPSZ256rr:
16859 case VMOVUPSZ256rr_REV:
16860 case VMOVUPSZ256rrk:
16861 case VMOVUPSZ256rrk_REV:
16862 case VMOVUPSZ256rrkz:
16863 case VMOVUPSZ256rrkz_REV:
16864 case VMOVUPSZmr:
16865 case VMOVUPSZmrk:
16866 case VMOVUPSZrm:
16867 case VMOVUPSZrmk:
16868 case VMOVUPSZrmkz:
16869 case VMOVUPSZrr:
16870 case VMOVUPSZrr_REV:
16871 case VMOVUPSZrrk:
16872 case VMOVUPSZrrk_REV:
16873 case VMOVUPSZrrkz:
16874 case VMOVUPSZrrkz_REV:
16875 case VMOVUPSmr:
16876 case VMOVUPSrm:
16877 case VMOVUPSrr:
16878 case VMOVUPSrr_REV:
16879 return true;
16880 }
16881 return false;
16882}
16883
16884bool isVPMAXUQ(unsigned Opcode) {
16885 switch (Opcode) {
16886 case VPMAXUQZ128rm:
16887 case VPMAXUQZ128rmb:
16888 case VPMAXUQZ128rmbk:
16889 case VPMAXUQZ128rmbkz:
16890 case VPMAXUQZ128rmk:
16891 case VPMAXUQZ128rmkz:
16892 case VPMAXUQZ128rr:
16893 case VPMAXUQZ128rrk:
16894 case VPMAXUQZ128rrkz:
16895 case VPMAXUQZ256rm:
16896 case VPMAXUQZ256rmb:
16897 case VPMAXUQZ256rmbk:
16898 case VPMAXUQZ256rmbkz:
16899 case VPMAXUQZ256rmk:
16900 case VPMAXUQZ256rmkz:
16901 case VPMAXUQZ256rr:
16902 case VPMAXUQZ256rrk:
16903 case VPMAXUQZ256rrkz:
16904 case VPMAXUQZrm:
16905 case VPMAXUQZrmb:
16906 case VPMAXUQZrmbk:
16907 case VPMAXUQZrmbkz:
16908 case VPMAXUQZrmk:
16909 case VPMAXUQZrmkz:
16910 case VPMAXUQZrr:
16911 case VPMAXUQZrrk:
16912 case VPMAXUQZrrkz:
16913 return true;
16914 }
16915 return false;
16916}
16917
16918bool isWRSSQ(unsigned Opcode) {
16919 switch (Opcode) {
16920 case WRSSQ:
16921 case WRSSQ_EVEX:
16922 return true;
16923 }
16924 return false;
16925}
16926
16927bool isPACKUSDW(unsigned Opcode) {
16928 switch (Opcode) {
16929 case PACKUSDWrm:
16930 case PACKUSDWrr:
16931 return true;
16932 }
16933 return false;
16934}
16935
16936bool isVCVTTBF162IBS(unsigned Opcode) {
16937 switch (Opcode) {
16938 case VCVTTBF162IBSZ128rm:
16939 case VCVTTBF162IBSZ128rmb:
16940 case VCVTTBF162IBSZ128rmbk:
16941 case VCVTTBF162IBSZ128rmbkz:
16942 case VCVTTBF162IBSZ128rmk:
16943 case VCVTTBF162IBSZ128rmkz:
16944 case VCVTTBF162IBSZ128rr:
16945 case VCVTTBF162IBSZ128rrk:
16946 case VCVTTBF162IBSZ128rrkz:
16947 case VCVTTBF162IBSZ256rm:
16948 case VCVTTBF162IBSZ256rmb:
16949 case VCVTTBF162IBSZ256rmbk:
16950 case VCVTTBF162IBSZ256rmbkz:
16951 case VCVTTBF162IBSZ256rmk:
16952 case VCVTTBF162IBSZ256rmkz:
16953 case VCVTTBF162IBSZ256rr:
16954 case VCVTTBF162IBSZ256rrk:
16955 case VCVTTBF162IBSZ256rrkz:
16956 case VCVTTBF162IBSZrm:
16957 case VCVTTBF162IBSZrmb:
16958 case VCVTTBF162IBSZrmbk:
16959 case VCVTTBF162IBSZrmbkz:
16960 case VCVTTBF162IBSZrmk:
16961 case VCVTTBF162IBSZrmkz:
16962 case VCVTTBF162IBSZrr:
16963 case VCVTTBF162IBSZrrk:
16964 case VCVTTBF162IBSZrrkz:
16965 return true;
16966 }
16967 return false;
16968}
16969
16970bool isXBEGIN(unsigned Opcode) {
16971 switch (Opcode) {
16972 case XBEGIN_2:
16973 case XBEGIN_4:
16974 return true;
16975 }
16976 return false;
16977}
16978
16979bool isVCVTPD2UQQ(unsigned Opcode) {
16980 switch (Opcode) {
16981 case VCVTPD2UQQZ128rm:
16982 case VCVTPD2UQQZ128rmb:
16983 case VCVTPD2UQQZ128rmbk:
16984 case VCVTPD2UQQZ128rmbkz:
16985 case VCVTPD2UQQZ128rmk:
16986 case VCVTPD2UQQZ128rmkz:
16987 case VCVTPD2UQQZ128rr:
16988 case VCVTPD2UQQZ128rrk:
16989 case VCVTPD2UQQZ128rrkz:
16990 case VCVTPD2UQQZ256rm:
16991 case VCVTPD2UQQZ256rmb:
16992 case VCVTPD2UQQZ256rmbk:
16993 case VCVTPD2UQQZ256rmbkz:
16994 case VCVTPD2UQQZ256rmk:
16995 case VCVTPD2UQQZ256rmkz:
16996 case VCVTPD2UQQZ256rr:
16997 case VCVTPD2UQQZ256rrk:
16998 case VCVTPD2UQQZ256rrkz:
16999 case VCVTPD2UQQZrm:
17000 case VCVTPD2UQQZrmb:
17001 case VCVTPD2UQQZrmbk:
17002 case VCVTPD2UQQZrmbkz:
17003 case VCVTPD2UQQZrmk:
17004 case VCVTPD2UQQZrmkz:
17005 case VCVTPD2UQQZrr:
17006 case VCVTPD2UQQZrrb:
17007 case VCVTPD2UQQZrrbk:
17008 case VCVTPD2UQQZrrbkz:
17009 case VCVTPD2UQQZrrk:
17010 case VCVTPD2UQQZrrkz:
17011 return true;
17012 }
17013 return false;
17014}
17015
17016bool isFCMOVB(unsigned Opcode) {
17017 return Opcode == CMOVB_F;
17018}
17019
17020bool isNOP(unsigned Opcode) {
17021 switch (Opcode) {
17022 case NOOP:
17023 case NOOPL:
17024 case NOOPLr:
17025 case NOOPQ:
17026 case NOOPQr:
17027 case NOOPW:
17028 case NOOPWr:
17029 return true;
17030 }
17031 return false;
17032}
17033
17034bool isVPABSQ(unsigned Opcode) {
17035 switch (Opcode) {
17036 case VPABSQZ128rm:
17037 case VPABSQZ128rmb:
17038 case VPABSQZ128rmbk:
17039 case VPABSQZ128rmbkz:
17040 case VPABSQZ128rmk:
17041 case VPABSQZ128rmkz:
17042 case VPABSQZ128rr:
17043 case VPABSQZ128rrk:
17044 case VPABSQZ128rrkz:
17045 case VPABSQZ256rm:
17046 case VPABSQZ256rmb:
17047 case VPABSQZ256rmbk:
17048 case VPABSQZ256rmbkz:
17049 case VPABSQZ256rmk:
17050 case VPABSQZ256rmkz:
17051 case VPABSQZ256rr:
17052 case VPABSQZ256rrk:
17053 case VPABSQZ256rrkz:
17054 case VPABSQZrm:
17055 case VPABSQZrmb:
17056 case VPABSQZrmbk:
17057 case VPABSQZrmbkz:
17058 case VPABSQZrmk:
17059 case VPABSQZrmkz:
17060 case VPABSQZrr:
17061 case VPABSQZrrk:
17062 case VPABSQZrrkz:
17063 return true;
17064 }
17065 return false;
17066}
17067
17068bool isVTESTPS(unsigned Opcode) {
17069 switch (Opcode) {
17070 case VTESTPSYrm:
17071 case VTESTPSYrr:
17072 case VTESTPSrm:
17073 case VTESTPSrr:
17074 return true;
17075 }
17076 return false;
17077}
17078
17079bool isPHSUBW(unsigned Opcode) {
17080 switch (Opcode) {
17081 case MMX_PHSUBWrm:
17082 case MMX_PHSUBWrr:
17083 case PHSUBWrm:
17084 case PHSUBWrr:
17085 return true;
17086 }
17087 return false;
17088}
17089
17090bool isPUSH2P(unsigned Opcode) {
17091 return Opcode == PUSH2P;
17092}
17093
17094bool isFISTTP(unsigned Opcode) {
17095 switch (Opcode) {
17096 case ISTT_FP16m:
17097 case ISTT_FP32m:
17098 case ISTT_FP64m:
17099 return true;
17100 }
17101 return false;
17102}
17103
17104bool isCFCMOVCC(unsigned Opcode) {
17105 switch (Opcode) {
17106 case CFCMOV16mr:
17107 case CFCMOV16rm:
17108 case CFCMOV16rm_ND:
17109 case CFCMOV16rr:
17110 case CFCMOV16rr_ND:
17111 case CFCMOV16rr_REV:
17112 case CFCMOV32mr:
17113 case CFCMOV32rm:
17114 case CFCMOV32rm_ND:
17115 case CFCMOV32rr:
17116 case CFCMOV32rr_ND:
17117 case CFCMOV32rr_REV:
17118 case CFCMOV64mr:
17119 case CFCMOV64rm:
17120 case CFCMOV64rm_ND:
17121 case CFCMOV64rr:
17122 case CFCMOV64rr_ND:
17123 case CFCMOV64rr_REV:
17124 return true;
17125 }
17126 return false;
17127}
17128
17129bool isVPINSRD(unsigned Opcode) {
17130 switch (Opcode) {
17131 case VPINSRDZrmi:
17132 case VPINSRDZrri:
17133 case VPINSRDrmi:
17134 case VPINSRDrri:
17135 return true;
17136 }
17137 return false;
17138}
17139
17140bool isPCMPESTRM(unsigned Opcode) {
17141 switch (Opcode) {
17142 case PCMPESTRMrmi:
17143 case PCMPESTRMrri:
17144 return true;
17145 }
17146 return false;
17147}
17148
17149bool isVFNMSUB213PS(unsigned Opcode) {
17150 switch (Opcode) {
17151 case VFNMSUB213PSYm:
17152 case VFNMSUB213PSYr:
17153 case VFNMSUB213PSZ128m:
17154 case VFNMSUB213PSZ128mb:
17155 case VFNMSUB213PSZ128mbk:
17156 case VFNMSUB213PSZ128mbkz:
17157 case VFNMSUB213PSZ128mk:
17158 case VFNMSUB213PSZ128mkz:
17159 case VFNMSUB213PSZ128r:
17160 case VFNMSUB213PSZ128rk:
17161 case VFNMSUB213PSZ128rkz:
17162 case VFNMSUB213PSZ256m:
17163 case VFNMSUB213PSZ256mb:
17164 case VFNMSUB213PSZ256mbk:
17165 case VFNMSUB213PSZ256mbkz:
17166 case VFNMSUB213PSZ256mk:
17167 case VFNMSUB213PSZ256mkz:
17168 case VFNMSUB213PSZ256r:
17169 case VFNMSUB213PSZ256rk:
17170 case VFNMSUB213PSZ256rkz:
17171 case VFNMSUB213PSZm:
17172 case VFNMSUB213PSZmb:
17173 case VFNMSUB213PSZmbk:
17174 case VFNMSUB213PSZmbkz:
17175 case VFNMSUB213PSZmk:
17176 case VFNMSUB213PSZmkz:
17177 case VFNMSUB213PSZr:
17178 case VFNMSUB213PSZrb:
17179 case VFNMSUB213PSZrbk:
17180 case VFNMSUB213PSZrbkz:
17181 case VFNMSUB213PSZrk:
17182 case VFNMSUB213PSZrkz:
17183 case VFNMSUB213PSm:
17184 case VFNMSUB213PSr:
17185 return true;
17186 }
17187 return false;
17188}
17189
17190bool isPHSUBD(unsigned Opcode) {
17191 switch (Opcode) {
17192 case MMX_PHSUBDrm:
17193 case MMX_PHSUBDrr:
17194 case PHSUBDrm:
17195 case PHSUBDrr:
17196 return true;
17197 }
17198 return false;
17199}
17200
17201bool isVCVTTPD2DQS(unsigned Opcode) {
17202 switch (Opcode) {
17203 case VCVTTPD2DQSZ128rm:
17204 case VCVTTPD2DQSZ128rmb:
17205 case VCVTTPD2DQSZ128rmbk:
17206 case VCVTTPD2DQSZ128rmbkz:
17207 case VCVTTPD2DQSZ128rmk:
17208 case VCVTTPD2DQSZ128rmkz:
17209 case VCVTTPD2DQSZ128rr:
17210 case VCVTTPD2DQSZ128rrk:
17211 case VCVTTPD2DQSZ128rrkz:
17212 case VCVTTPD2DQSZ256rm:
17213 case VCVTTPD2DQSZ256rmb:
17214 case VCVTTPD2DQSZ256rmbk:
17215 case VCVTTPD2DQSZ256rmbkz:
17216 case VCVTTPD2DQSZ256rmk:
17217 case VCVTTPD2DQSZ256rmkz:
17218 case VCVTTPD2DQSZ256rr:
17219 case VCVTTPD2DQSZ256rrb:
17220 case VCVTTPD2DQSZ256rrbk:
17221 case VCVTTPD2DQSZ256rrbkz:
17222 case VCVTTPD2DQSZ256rrk:
17223 case VCVTTPD2DQSZ256rrkz:
17224 case VCVTTPD2DQSZrm:
17225 case VCVTTPD2DQSZrmb:
17226 case VCVTTPD2DQSZrmbk:
17227 case VCVTTPD2DQSZrmbkz:
17228 case VCVTTPD2DQSZrmk:
17229 case VCVTTPD2DQSZrmkz:
17230 case VCVTTPD2DQSZrr:
17231 case VCVTTPD2DQSZrrb:
17232 case VCVTTPD2DQSZrrbk:
17233 case VCVTTPD2DQSZrrbkz:
17234 case VCVTTPD2DQSZrrk:
17235 case VCVTTPD2DQSZrrkz:
17236 return true;
17237 }
17238 return false;
17239}
17240
17241bool isSLDT(unsigned Opcode) {
17242 switch (Opcode) {
17243 case SLDT16m:
17244 case SLDT16r:
17245 case SLDT32r:
17246 case SLDT64r:
17247 return true;
17248 }
17249 return false;
17250}
17251
17252bool isVHADDPS(unsigned Opcode) {
17253 switch (Opcode) {
17254 case VHADDPSYrm:
17255 case VHADDPSYrr:
17256 case VHADDPSrm:
17257 case VHADDPSrr:
17258 return true;
17259 }
17260 return false;
17261}
17262
17263bool isVMOVNTDQ(unsigned Opcode) {
17264 switch (Opcode) {
17265 case VMOVNTDQYmr:
17266 case VMOVNTDQZ128mr:
17267 case VMOVNTDQZ256mr:
17268 case VMOVNTDQZmr:
17269 case VMOVNTDQmr:
17270 return true;
17271 }
17272 return false;
17273}
17274
17275bool isVPMINSD(unsigned Opcode) {
17276 switch (Opcode) {
17277 case VPMINSDYrm:
17278 case VPMINSDYrr:
17279 case VPMINSDZ128rm:
17280 case VPMINSDZ128rmb:
17281 case VPMINSDZ128rmbk:
17282 case VPMINSDZ128rmbkz:
17283 case VPMINSDZ128rmk:
17284 case VPMINSDZ128rmkz:
17285 case VPMINSDZ128rr:
17286 case VPMINSDZ128rrk:
17287 case VPMINSDZ128rrkz:
17288 case VPMINSDZ256rm:
17289 case VPMINSDZ256rmb:
17290 case VPMINSDZ256rmbk:
17291 case VPMINSDZ256rmbkz:
17292 case VPMINSDZ256rmk:
17293 case VPMINSDZ256rmkz:
17294 case VPMINSDZ256rr:
17295 case VPMINSDZ256rrk:
17296 case VPMINSDZ256rrkz:
17297 case VPMINSDZrm:
17298 case VPMINSDZrmb:
17299 case VPMINSDZrmbk:
17300 case VPMINSDZrmbkz:
17301 case VPMINSDZrmk:
17302 case VPMINSDZrmkz:
17303 case VPMINSDZrr:
17304 case VPMINSDZrrk:
17305 case VPMINSDZrrkz:
17306 case VPMINSDrm:
17307 case VPMINSDrr:
17308 return true;
17309 }
17310 return false;
17311}
17312
17313bool isVFRCZSD(unsigned Opcode) {
17314 switch (Opcode) {
17315 case VFRCZSDrm:
17316 case VFRCZSDrr:
17317 return true;
17318 }
17319 return false;
17320}
17321
17322bool isVPTESTMW(unsigned Opcode) {
17323 switch (Opcode) {
17324 case VPTESTMWZ128rm:
17325 case VPTESTMWZ128rmk:
17326 case VPTESTMWZ128rr:
17327 case VPTESTMWZ128rrk:
17328 case VPTESTMWZ256rm:
17329 case VPTESTMWZ256rmk:
17330 case VPTESTMWZ256rr:
17331 case VPTESTMWZ256rrk:
17332 case VPTESTMWZrm:
17333 case VPTESTMWZrmk:
17334 case VPTESTMWZrr:
17335 case VPTESTMWZrrk:
17336 return true;
17337 }
17338 return false;
17339}
17340
17341bool isVPMOVZXWD(unsigned Opcode) {
17342 switch (Opcode) {
17343 case VPMOVZXWDYrm:
17344 case VPMOVZXWDYrr:
17345 case VPMOVZXWDZ128rm:
17346 case VPMOVZXWDZ128rmk:
17347 case VPMOVZXWDZ128rmkz:
17348 case VPMOVZXWDZ128rr:
17349 case VPMOVZXWDZ128rrk:
17350 case VPMOVZXWDZ128rrkz:
17351 case VPMOVZXWDZ256rm:
17352 case VPMOVZXWDZ256rmk:
17353 case VPMOVZXWDZ256rmkz:
17354 case VPMOVZXWDZ256rr:
17355 case VPMOVZXWDZ256rrk:
17356 case VPMOVZXWDZ256rrkz:
17357 case VPMOVZXWDZrm:
17358 case VPMOVZXWDZrmk:
17359 case VPMOVZXWDZrmkz:
17360 case VPMOVZXWDZrr:
17361 case VPMOVZXWDZrrk:
17362 case VPMOVZXWDZrrkz:
17363 case VPMOVZXWDrm:
17364 case VPMOVZXWDrr:
17365 return true;
17366 }
17367 return false;
17368}
17369
17370bool isPSADBW(unsigned Opcode) {
17371 switch (Opcode) {
17372 case MMX_PSADBWrm:
17373 case MMX_PSADBWrr:
17374 case PSADBWrm:
17375 case PSADBWrr:
17376 return true;
17377 }
17378 return false;
17379}
17380
17381bool isVCVTSD2SI(unsigned Opcode) {
17382 switch (Opcode) {
17383 case VCVTSD2SI64Zrm_Int:
17384 case VCVTSD2SI64Zrr_Int:
17385 case VCVTSD2SI64Zrrb_Int:
17386 case VCVTSD2SI64rm_Int:
17387 case VCVTSD2SI64rr_Int:
17388 case VCVTSD2SIZrm_Int:
17389 case VCVTSD2SIZrr_Int:
17390 case VCVTSD2SIZrrb_Int:
17391 case VCVTSD2SIrm_Int:
17392 case VCVTSD2SIrr_Int:
17393 return true;
17394 }
17395 return false;
17396}
17397
17398bool isVMAXPH(unsigned Opcode) {
17399 switch (Opcode) {
17400 case VMAXPHZ128rm:
17401 case VMAXPHZ128rmb:
17402 case VMAXPHZ128rmbk:
17403 case VMAXPHZ128rmbkz:
17404 case VMAXPHZ128rmk:
17405 case VMAXPHZ128rmkz:
17406 case VMAXPHZ128rr:
17407 case VMAXPHZ128rrk:
17408 case VMAXPHZ128rrkz:
17409 case VMAXPHZ256rm:
17410 case VMAXPHZ256rmb:
17411 case VMAXPHZ256rmbk:
17412 case VMAXPHZ256rmbkz:
17413 case VMAXPHZ256rmk:
17414 case VMAXPHZ256rmkz:
17415 case VMAXPHZ256rr:
17416 case VMAXPHZ256rrk:
17417 case VMAXPHZ256rrkz:
17418 case VMAXPHZrm:
17419 case VMAXPHZrmb:
17420 case VMAXPHZrmbk:
17421 case VMAXPHZrmbkz:
17422 case VMAXPHZrmk:
17423 case VMAXPHZrmkz:
17424 case VMAXPHZrr:
17425 case VMAXPHZrrb:
17426 case VMAXPHZrrbk:
17427 case VMAXPHZrrbkz:
17428 case VMAXPHZrrk:
17429 case VMAXPHZrrkz:
17430 return true;
17431 }
17432 return false;
17433}
17434
17435bool isLODSB(unsigned Opcode) {
17436 return Opcode == LODSB;
17437}
17438
17439bool isPHMINPOSUW(unsigned Opcode) {
17440 switch (Opcode) {
17441 case PHMINPOSUWrm:
17442 case PHMINPOSUWrr:
17443 return true;
17444 }
17445 return false;
17446}
17447
17448bool isVPROLVD(unsigned Opcode) {
17449 switch (Opcode) {
17450 case VPROLVDZ128rm:
17451 case VPROLVDZ128rmb:
17452 case VPROLVDZ128rmbk:
17453 case VPROLVDZ128rmbkz:
17454 case VPROLVDZ128rmk:
17455 case VPROLVDZ128rmkz:
17456 case VPROLVDZ128rr:
17457 case VPROLVDZ128rrk:
17458 case VPROLVDZ128rrkz:
17459 case VPROLVDZ256rm:
17460 case VPROLVDZ256rmb:
17461 case VPROLVDZ256rmbk:
17462 case VPROLVDZ256rmbkz:
17463 case VPROLVDZ256rmk:
17464 case VPROLVDZ256rmkz:
17465 case VPROLVDZ256rr:
17466 case VPROLVDZ256rrk:
17467 case VPROLVDZ256rrkz:
17468 case VPROLVDZrm:
17469 case VPROLVDZrmb:
17470 case VPROLVDZrmbk:
17471 case VPROLVDZrmbkz:
17472 case VPROLVDZrmk:
17473 case VPROLVDZrmkz:
17474 case VPROLVDZrr:
17475 case VPROLVDZrrk:
17476 case VPROLVDZrrkz:
17477 return true;
17478 }
17479 return false;
17480}
17481
17482bool isWRFSBASE(unsigned Opcode) {
17483 switch (Opcode) {
17484 case WRFSBASE:
17485 case WRFSBASE64:
17486 return true;
17487 }
17488 return false;
17489}
17490
17491bool isVRSQRT14PS(unsigned Opcode) {
17492 switch (Opcode) {
17493 case VRSQRT14PSZ128m:
17494 case VRSQRT14PSZ128mb:
17495 case VRSQRT14PSZ128mbk:
17496 case VRSQRT14PSZ128mbkz:
17497 case VRSQRT14PSZ128mk:
17498 case VRSQRT14PSZ128mkz:
17499 case VRSQRT14PSZ128r:
17500 case VRSQRT14PSZ128rk:
17501 case VRSQRT14PSZ128rkz:
17502 case VRSQRT14PSZ256m:
17503 case VRSQRT14PSZ256mb:
17504 case VRSQRT14PSZ256mbk:
17505 case VRSQRT14PSZ256mbkz:
17506 case VRSQRT14PSZ256mk:
17507 case VRSQRT14PSZ256mkz:
17508 case VRSQRT14PSZ256r:
17509 case VRSQRT14PSZ256rk:
17510 case VRSQRT14PSZ256rkz:
17511 case VRSQRT14PSZm:
17512 case VRSQRT14PSZmb:
17513 case VRSQRT14PSZmbk:
17514 case VRSQRT14PSZmbkz:
17515 case VRSQRT14PSZmk:
17516 case VRSQRT14PSZmkz:
17517 case VRSQRT14PSZr:
17518 case VRSQRT14PSZrk:
17519 case VRSQRT14PSZrkz:
17520 return true;
17521 }
17522 return false;
17523}
17524
17525bool isVPHSUBDQ(unsigned Opcode) {
17526 switch (Opcode) {
17527 case VPHSUBDQrm:
17528 case VPHSUBDQrr:
17529 return true;
17530 }
17531 return false;
17532}
17533
17534bool isIRETD(unsigned Opcode) {
17535 return Opcode == IRET32;
17536}
17537
17538bool isVMOVRSD(unsigned Opcode) {
17539 switch (Opcode) {
17540 case VMOVRSDZ128m:
17541 case VMOVRSDZ128mk:
17542 case VMOVRSDZ128mkz:
17543 case VMOVRSDZ256m:
17544 case VMOVRSDZ256mk:
17545 case VMOVRSDZ256mkz:
17546 case VMOVRSDZm:
17547 case VMOVRSDZmk:
17548 case VMOVRSDZmkz:
17549 return true;
17550 }
17551 return false;
17552}
17553
17554bool isCVTSI2SS(unsigned Opcode) {
17555 switch (Opcode) {
17556 case CVTSI2SSrm_Int:
17557 case CVTSI2SSrr_Int:
17558 case CVTSI642SSrm_Int:
17559 case CVTSI642SSrr_Int:
17560 return true;
17561 }
17562 return false;
17563}
17564
17565bool isVPMULHRSW(unsigned Opcode) {
17566 switch (Opcode) {
17567 case VPMULHRSWYrm:
17568 case VPMULHRSWYrr:
17569 case VPMULHRSWZ128rm:
17570 case VPMULHRSWZ128rmk:
17571 case VPMULHRSWZ128rmkz:
17572 case VPMULHRSWZ128rr:
17573 case VPMULHRSWZ128rrk:
17574 case VPMULHRSWZ128rrkz:
17575 case VPMULHRSWZ256rm:
17576 case VPMULHRSWZ256rmk:
17577 case VPMULHRSWZ256rmkz:
17578 case VPMULHRSWZ256rr:
17579 case VPMULHRSWZ256rrk:
17580 case VPMULHRSWZ256rrkz:
17581 case VPMULHRSWZrm:
17582 case VPMULHRSWZrmk:
17583 case VPMULHRSWZrmkz:
17584 case VPMULHRSWZrr:
17585 case VPMULHRSWZrrk:
17586 case VPMULHRSWZrrkz:
17587 case VPMULHRSWrm:
17588 case VPMULHRSWrr:
17589 return true;
17590 }
17591 return false;
17592}
17593
17594bool isPI2FD(unsigned Opcode) {
17595 switch (Opcode) {
17596 case PI2FDrm:
17597 case PI2FDrr:
17598 return true;
17599 }
17600 return false;
17601}
17602
17603bool isGF2P8AFFINEQB(unsigned Opcode) {
17604 switch (Opcode) {
17605 case GF2P8AFFINEQBrmi:
17606 case GF2P8AFFINEQBrri:
17607 return true;
17608 }
17609 return false;
17610}
17611
17612bool isPAND(unsigned Opcode) {
17613 switch (Opcode) {
17614 case MMX_PANDrm:
17615 case MMX_PANDrr:
17616 case PANDrm:
17617 case PANDrr:
17618 return true;
17619 }
17620 return false;
17621}
17622
17623bool isVFNMSUB231SH(unsigned Opcode) {
17624 switch (Opcode) {
17625 case VFNMSUB231SHZm_Int:
17626 case VFNMSUB231SHZmk_Int:
17627 case VFNMSUB231SHZmkz_Int:
17628 case VFNMSUB231SHZr_Int:
17629 case VFNMSUB231SHZrb_Int:
17630 case VFNMSUB231SHZrbk_Int:
17631 case VFNMSUB231SHZrbkz_Int:
17632 case VFNMSUB231SHZrk_Int:
17633 case VFNMSUB231SHZrkz_Int:
17634 return true;
17635 }
17636 return false;
17637}
17638
17639bool isVCVTPH2BF8(unsigned Opcode) {
17640 switch (Opcode) {
17641 case VCVTPH2BF8Z128rm:
17642 case VCVTPH2BF8Z128rmb:
17643 case VCVTPH2BF8Z128rmbk:
17644 case VCVTPH2BF8Z128rmbkz:
17645 case VCVTPH2BF8Z128rmk:
17646 case VCVTPH2BF8Z128rmkz:
17647 case VCVTPH2BF8Z128rr:
17648 case VCVTPH2BF8Z128rrk:
17649 case VCVTPH2BF8Z128rrkz:
17650 case VCVTPH2BF8Z256rm:
17651 case VCVTPH2BF8Z256rmb:
17652 case VCVTPH2BF8Z256rmbk:
17653 case VCVTPH2BF8Z256rmbkz:
17654 case VCVTPH2BF8Z256rmk:
17655 case VCVTPH2BF8Z256rmkz:
17656 case VCVTPH2BF8Z256rr:
17657 case VCVTPH2BF8Z256rrk:
17658 case VCVTPH2BF8Z256rrkz:
17659 case VCVTPH2BF8Zrm:
17660 case VCVTPH2BF8Zrmb:
17661 case VCVTPH2BF8Zrmbk:
17662 case VCVTPH2BF8Zrmbkz:
17663 case VCVTPH2BF8Zrmk:
17664 case VCVTPH2BF8Zrmkz:
17665 case VCVTPH2BF8Zrr:
17666 case VCVTPH2BF8Zrrk:
17667 case VCVTPH2BF8Zrrkz:
17668 return true;
17669 }
17670 return false;
17671}
17672
17673bool isVMOVHLPS(unsigned Opcode) {
17674 switch (Opcode) {
17675 case VMOVHLPSZrr:
17676 case VMOVHLPSrr:
17677 return true;
17678 }
17679 return false;
17680}
17681
17682bool isPEXTRB(unsigned Opcode) {
17683 switch (Opcode) {
17684 case PEXTRBmri:
17685 case PEXTRBrri:
17686 return true;
17687 }
17688 return false;
17689}
17690
17691bool isVMMCALL(unsigned Opcode) {
17692 return Opcode == VMMCALL;
17693}
17694
17695bool isKNOTD(unsigned Opcode) {
17696 return Opcode == KNOTDkk;
17697}
17698
17699bool isVCVTSH2SS(unsigned Opcode) {
17700 switch (Opcode) {
17701 case VCVTSH2SSZrm_Int:
17702 case VCVTSH2SSZrmk_Int:
17703 case VCVTSH2SSZrmkz_Int:
17704 case VCVTSH2SSZrr_Int:
17705 case VCVTSH2SSZrrb_Int:
17706 case VCVTSH2SSZrrbk_Int:
17707 case VCVTSH2SSZrrbkz_Int:
17708 case VCVTSH2SSZrrk_Int:
17709 case VCVTSH2SSZrrkz_Int:
17710 return true;
17711 }
17712 return false;
17713}
17714
17715bool isVPUNPCKLQDQ(unsigned Opcode) {
17716 switch (Opcode) {
17717 case VPUNPCKLQDQYrm:
17718 case VPUNPCKLQDQYrr:
17719 case VPUNPCKLQDQZ128rm:
17720 case VPUNPCKLQDQZ128rmb:
17721 case VPUNPCKLQDQZ128rmbk:
17722 case VPUNPCKLQDQZ128rmbkz:
17723 case VPUNPCKLQDQZ128rmk:
17724 case VPUNPCKLQDQZ128rmkz:
17725 case VPUNPCKLQDQZ128rr:
17726 case VPUNPCKLQDQZ128rrk:
17727 case VPUNPCKLQDQZ128rrkz:
17728 case VPUNPCKLQDQZ256rm:
17729 case VPUNPCKLQDQZ256rmb:
17730 case VPUNPCKLQDQZ256rmbk:
17731 case VPUNPCKLQDQZ256rmbkz:
17732 case VPUNPCKLQDQZ256rmk:
17733 case VPUNPCKLQDQZ256rmkz:
17734 case VPUNPCKLQDQZ256rr:
17735 case VPUNPCKLQDQZ256rrk:
17736 case VPUNPCKLQDQZ256rrkz:
17737 case VPUNPCKLQDQZrm:
17738 case VPUNPCKLQDQZrmb:
17739 case VPUNPCKLQDQZrmbk:
17740 case VPUNPCKLQDQZrmbkz:
17741 case VPUNPCKLQDQZrmk:
17742 case VPUNPCKLQDQZrmkz:
17743 case VPUNPCKLQDQZrr:
17744 case VPUNPCKLQDQZrrk:
17745 case VPUNPCKLQDQZrrkz:
17746 case VPUNPCKLQDQrm:
17747 case VPUNPCKLQDQrr:
17748 return true;
17749 }
17750 return false;
17751}
17752
17753bool isVPERMIL2PS(unsigned Opcode) {
17754 switch (Opcode) {
17755 case VPERMIL2PSYmr:
17756 case VPERMIL2PSYrm:
17757 case VPERMIL2PSYrr:
17758 case VPERMIL2PSYrr_REV:
17759 case VPERMIL2PSmr:
17760 case VPERMIL2PSrm:
17761 case VPERMIL2PSrr:
17762 case VPERMIL2PSrr_REV:
17763 return true;
17764 }
17765 return false;
17766}
17767
17768bool isVPCMPGTD(unsigned Opcode) {
17769 switch (Opcode) {
17770 case VPCMPGTDYrm:
17771 case VPCMPGTDYrr:
17772 case VPCMPGTDZ128rm:
17773 case VPCMPGTDZ128rmb:
17774 case VPCMPGTDZ128rmbk:
17775 case VPCMPGTDZ128rmk:
17776 case VPCMPGTDZ128rr:
17777 case VPCMPGTDZ128rrk:
17778 case VPCMPGTDZ256rm:
17779 case VPCMPGTDZ256rmb:
17780 case VPCMPGTDZ256rmbk:
17781 case VPCMPGTDZ256rmk:
17782 case VPCMPGTDZ256rr:
17783 case VPCMPGTDZ256rrk:
17784 case VPCMPGTDZrm:
17785 case VPCMPGTDZrmb:
17786 case VPCMPGTDZrmbk:
17787 case VPCMPGTDZrmk:
17788 case VPCMPGTDZrr:
17789 case VPCMPGTDZrrk:
17790 case VPCMPGTDrm:
17791 case VPCMPGTDrr:
17792 return true;
17793 }
17794 return false;
17795}
17796
17797bool isCMPXCHG16B(unsigned Opcode) {
17798 return Opcode == CMPXCHG16B;
17799}
17800
17801bool isTDPHF8PS(unsigned Opcode) {
17802 return Opcode == TDPHF8PS;
17803}
17804
17805bool isVZEROUPPER(unsigned Opcode) {
17806 return Opcode == VZEROUPPER;
17807}
17808
17809bool isMOVAPS(unsigned Opcode) {
17810 switch (Opcode) {
17811 case MOVAPSmr:
17812 case MOVAPSrm:
17813 case MOVAPSrr:
17814 case MOVAPSrr_REV:
17815 return true;
17816 }
17817 return false;
17818}
17819
17820bool isVPCMPW(unsigned Opcode) {
17821 switch (Opcode) {
17822 case VPCMPWZ128rmi:
17823 case VPCMPWZ128rmik:
17824 case VPCMPWZ128rri:
17825 case VPCMPWZ128rrik:
17826 case VPCMPWZ256rmi:
17827 case VPCMPWZ256rmik:
17828 case VPCMPWZ256rri:
17829 case VPCMPWZ256rrik:
17830 case VPCMPWZrmi:
17831 case VPCMPWZrmik:
17832 case VPCMPWZrri:
17833 case VPCMPWZrrik:
17834 return true;
17835 }
17836 return false;
17837}
17838
17839bool isFUCOMPP(unsigned Opcode) {
17840 return Opcode == UCOM_FPPr;
17841}
17842
17843bool isXSETBV(unsigned Opcode) {
17844 return Opcode == XSETBV;
17845}
17846
17847bool isSLWPCB(unsigned Opcode) {
17848 switch (Opcode) {
17849 case SLWPCB:
17850 case SLWPCB64:
17851 return true;
17852 }
17853 return false;
17854}
17855
17856bool isSCASW(unsigned Opcode) {
17857 return Opcode == SCASW;
17858}
17859
17860bool isFCMOVNE(unsigned Opcode) {
17861 return Opcode == CMOVNE_F;
17862}
17863
17864bool isPBNDKB(unsigned Opcode) {
17865 return Opcode == PBNDKB;
17866}
17867
17868bool isVPMULLD(unsigned Opcode) {
17869 switch (Opcode) {
17870 case VPMULLDYrm:
17871 case VPMULLDYrr:
17872 case VPMULLDZ128rm:
17873 case VPMULLDZ128rmb:
17874 case VPMULLDZ128rmbk:
17875 case VPMULLDZ128rmbkz:
17876 case VPMULLDZ128rmk:
17877 case VPMULLDZ128rmkz:
17878 case VPMULLDZ128rr:
17879 case VPMULLDZ128rrk:
17880 case VPMULLDZ128rrkz:
17881 case VPMULLDZ256rm:
17882 case VPMULLDZ256rmb:
17883 case VPMULLDZ256rmbk:
17884 case VPMULLDZ256rmbkz:
17885 case VPMULLDZ256rmk:
17886 case VPMULLDZ256rmkz:
17887 case VPMULLDZ256rr:
17888 case VPMULLDZ256rrk:
17889 case VPMULLDZ256rrkz:
17890 case VPMULLDZrm:
17891 case VPMULLDZrmb:
17892 case VPMULLDZrmbk:
17893 case VPMULLDZrmbkz:
17894 case VPMULLDZrmk:
17895 case VPMULLDZrmkz:
17896 case VPMULLDZrr:
17897 case VPMULLDZrrk:
17898 case VPMULLDZrrkz:
17899 case VPMULLDrm:
17900 case VPMULLDrr:
17901 return true;
17902 }
17903 return false;
17904}
17905
17906bool isVP4DPWSSDS(unsigned Opcode) {
17907 switch (Opcode) {
17908 case VP4DPWSSDSrm:
17909 case VP4DPWSSDSrmk:
17910 case VP4DPWSSDSrmkz:
17911 return true;
17912 }
17913 return false;
17914}
17915
17916bool isVCVT2PH2HF8(unsigned Opcode) {
17917 switch (Opcode) {
17918 case VCVT2PH2HF8Z128rm:
17919 case VCVT2PH2HF8Z128rmb:
17920 case VCVT2PH2HF8Z128rmbk:
17921 case VCVT2PH2HF8Z128rmbkz:
17922 case VCVT2PH2HF8Z128rmk:
17923 case VCVT2PH2HF8Z128rmkz:
17924 case VCVT2PH2HF8Z128rr:
17925 case VCVT2PH2HF8Z128rrk:
17926 case VCVT2PH2HF8Z128rrkz:
17927 case VCVT2PH2HF8Z256rm:
17928 case VCVT2PH2HF8Z256rmb:
17929 case VCVT2PH2HF8Z256rmbk:
17930 case VCVT2PH2HF8Z256rmbkz:
17931 case VCVT2PH2HF8Z256rmk:
17932 case VCVT2PH2HF8Z256rmkz:
17933 case VCVT2PH2HF8Z256rr:
17934 case VCVT2PH2HF8Z256rrk:
17935 case VCVT2PH2HF8Z256rrkz:
17936 case VCVT2PH2HF8Zrm:
17937 case VCVT2PH2HF8Zrmb:
17938 case VCVT2PH2HF8Zrmbk:
17939 case VCVT2PH2HF8Zrmbkz:
17940 case VCVT2PH2HF8Zrmk:
17941 case VCVT2PH2HF8Zrmkz:
17942 case VCVT2PH2HF8Zrr:
17943 case VCVT2PH2HF8Zrrk:
17944 case VCVT2PH2HF8Zrrkz:
17945 return true;
17946 }
17947 return false;
17948}
17949
17950bool isPINSRW(unsigned Opcode) {
17951 switch (Opcode) {
17952 case MMX_PINSRWrmi:
17953 case MMX_PINSRWrri:
17954 case PINSRWrmi:
17955 case PINSRWrri:
17956 return true;
17957 }
17958 return false;
17959}
17960
17961bool isVCVTSI2SH(unsigned Opcode) {
17962 switch (Opcode) {
17963 case VCVTSI2SHZrm_Int:
17964 case VCVTSI2SHZrr_Int:
17965 case VCVTSI2SHZrrb_Int:
17966 case VCVTSI642SHZrm_Int:
17967 case VCVTSI642SHZrr_Int:
17968 case VCVTSI642SHZrrb_Int:
17969 return true;
17970 }
17971 return false;
17972}
17973
17974bool isVINSERTF32X8(unsigned Opcode) {
17975 switch (Opcode) {
17976 case VINSERTF32X8Zrmi:
17977 case VINSERTF32X8Zrmik:
17978 case VINSERTF32X8Zrmikz:
17979 case VINSERTF32X8Zrri:
17980 case VINSERTF32X8Zrrik:
17981 case VINSERTF32X8Zrrikz:
17982 return true;
17983 }
17984 return false;
17985}
17986
17987bool isKSHIFTLB(unsigned Opcode) {
17988 return Opcode == KSHIFTLBki;
17989}
17990
17991bool isSEAMOPS(unsigned Opcode) {
17992 return Opcode == SEAMOPS;
17993}
17994
17995bool isVPMULUDQ(unsigned Opcode) {
17996 switch (Opcode) {
17997 case VPMULUDQYrm:
17998 case VPMULUDQYrr:
17999 case VPMULUDQZ128rm:
18000 case VPMULUDQZ128rmb:
18001 case VPMULUDQZ128rmbk:
18002 case VPMULUDQZ128rmbkz:
18003 case VPMULUDQZ128rmk:
18004 case VPMULUDQZ128rmkz:
18005 case VPMULUDQZ128rr:
18006 case VPMULUDQZ128rrk:
18007 case VPMULUDQZ128rrkz:
18008 case VPMULUDQZ256rm:
18009 case VPMULUDQZ256rmb:
18010 case VPMULUDQZ256rmbk:
18011 case VPMULUDQZ256rmbkz:
18012 case VPMULUDQZ256rmk:
18013 case VPMULUDQZ256rmkz:
18014 case VPMULUDQZ256rr:
18015 case VPMULUDQZ256rrk:
18016 case VPMULUDQZ256rrkz:
18017 case VPMULUDQZrm:
18018 case VPMULUDQZrmb:
18019 case VPMULUDQZrmbk:
18020 case VPMULUDQZrmbkz:
18021 case VPMULUDQZrmk:
18022 case VPMULUDQZrmkz:
18023 case VPMULUDQZrr:
18024 case VPMULUDQZrrk:
18025 case VPMULUDQZrrkz:
18026 case VPMULUDQrm:
18027 case VPMULUDQrr:
18028 return true;
18029 }
18030 return false;
18031}
18032
18033bool isVPMOVSQB(unsigned Opcode) {
18034 switch (Opcode) {
18035 case VPMOVSQBZ128mr:
18036 case VPMOVSQBZ128mrk:
18037 case VPMOVSQBZ128rr:
18038 case VPMOVSQBZ128rrk:
18039 case VPMOVSQBZ128rrkz:
18040 case VPMOVSQBZ256mr:
18041 case VPMOVSQBZ256mrk:
18042 case VPMOVSQBZ256rr:
18043 case VPMOVSQBZ256rrk:
18044 case VPMOVSQBZ256rrkz:
18045 case VPMOVSQBZmr:
18046 case VPMOVSQBZmrk:
18047 case VPMOVSQBZrr:
18048 case VPMOVSQBZrrk:
18049 case VPMOVSQBZrrkz:
18050 return true;
18051 }
18052 return false;
18053}
18054
18055bool isVPTESTMD(unsigned Opcode) {
18056 switch (Opcode) {
18057 case VPTESTMDZ128rm:
18058 case VPTESTMDZ128rmb:
18059 case VPTESTMDZ128rmbk:
18060 case VPTESTMDZ128rmk:
18061 case VPTESTMDZ128rr:
18062 case VPTESTMDZ128rrk:
18063 case VPTESTMDZ256rm:
18064 case VPTESTMDZ256rmb:
18065 case VPTESTMDZ256rmbk:
18066 case VPTESTMDZ256rmk:
18067 case VPTESTMDZ256rr:
18068 case VPTESTMDZ256rrk:
18069 case VPTESTMDZrm:
18070 case VPTESTMDZrmb:
18071 case VPTESTMDZrmbk:
18072 case VPTESTMDZrmk:
18073 case VPTESTMDZrr:
18074 case VPTESTMDZrrk:
18075 return true;
18076 }
18077 return false;
18078}
18079
18080bool isVPHADDDQ(unsigned Opcode) {
18081 switch (Opcode) {
18082 case VPHADDDQrm:
18083 case VPHADDDQrr:
18084 return true;
18085 }
18086 return false;
18087}
18088
18089bool isKUNPCKDQ(unsigned Opcode) {
18090 return Opcode == KUNPCKDQkk;
18091}
18092
18093bool isT1MSKC(unsigned Opcode) {
18094 switch (Opcode) {
18095 case T1MSKC32rm:
18096 case T1MSKC32rr:
18097 case T1MSKC64rm:
18098 case T1MSKC64rr:
18099 return true;
18100 }
18101 return false;
18102}
18103
18104bool isVPCOMB(unsigned Opcode) {
18105 switch (Opcode) {
18106 case VPCOMBmi:
18107 case VPCOMBri:
18108 return true;
18109 }
18110 return false;
18111}
18112
18113bool isVBLENDPS(unsigned Opcode) {
18114 switch (Opcode) {
18115 case VBLENDPSYrmi:
18116 case VBLENDPSYrri:
18117 case VBLENDPSrmi:
18118 case VBLENDPSrri:
18119 return true;
18120 }
18121 return false;
18122}
18123
18124bool isPTWRITE(unsigned Opcode) {
18125 switch (Opcode) {
18126 case PTWRITE64m:
18127 case PTWRITE64r:
18128 case PTWRITEm:
18129 case PTWRITEr:
18130 return true;
18131 }
18132 return false;
18133}
18134
18135bool isVCVTPH2BF8S(unsigned Opcode) {
18136 switch (Opcode) {
18137 case VCVTPH2BF8SZ128rm:
18138 case VCVTPH2BF8SZ128rmb:
18139 case VCVTPH2BF8SZ128rmbk:
18140 case VCVTPH2BF8SZ128rmbkz:
18141 case VCVTPH2BF8SZ128rmk:
18142 case VCVTPH2BF8SZ128rmkz:
18143 case VCVTPH2BF8SZ128rr:
18144 case VCVTPH2BF8SZ128rrk:
18145 case VCVTPH2BF8SZ128rrkz:
18146 case VCVTPH2BF8SZ256rm:
18147 case VCVTPH2BF8SZ256rmb:
18148 case VCVTPH2BF8SZ256rmbk:
18149 case VCVTPH2BF8SZ256rmbkz:
18150 case VCVTPH2BF8SZ256rmk:
18151 case VCVTPH2BF8SZ256rmkz:
18152 case VCVTPH2BF8SZ256rr:
18153 case VCVTPH2BF8SZ256rrk:
18154 case VCVTPH2BF8SZ256rrkz:
18155 case VCVTPH2BF8SZrm:
18156 case VCVTPH2BF8SZrmb:
18157 case VCVTPH2BF8SZrmbk:
18158 case VCVTPH2BF8SZrmbkz:
18159 case VCVTPH2BF8SZrmk:
18160 case VCVTPH2BF8SZrmkz:
18161 case VCVTPH2BF8SZrr:
18162 case VCVTPH2BF8SZrrk:
18163 case VCVTPH2BF8SZrrkz:
18164 return true;
18165 }
18166 return false;
18167}
18168
18169bool isCVTPS2PI(unsigned Opcode) {
18170 switch (Opcode) {
18171 case MMX_CVTPS2PIrm:
18172 case MMX_CVTPS2PIrr:
18173 return true;
18174 }
18175 return false;
18176}
18177
18178bool isVPROTD(unsigned Opcode) {
18179 switch (Opcode) {
18180 case VPROTDmi:
18181 case VPROTDmr:
18182 case VPROTDri:
18183 case VPROTDrm:
18184 case VPROTDrr:
18185 case VPROTDrr_REV:
18186 return true;
18187 }
18188 return false;
18189}
18190
18191bool isCALL(unsigned Opcode) {
18192 switch (Opcode) {
18193 case CALL16m:
18194 case CALL16r:
18195 case CALL32m:
18196 case CALL32r:
18197 case CALL64m:
18198 case CALL64pcrel32:
18199 case CALL64r:
18200 case CALLpcrel16:
18201 case CALLpcrel32:
18202 case FARCALL32m:
18203 return true;
18204 }
18205 return false;
18206}
18207
18208bool isTILELOADDRST1(unsigned Opcode) {
18209 switch (Opcode) {
18210 case TILELOADDRST1:
18211 case TILELOADDRST1_EVEX:
18212 return true;
18213 }
18214 return false;
18215}
18216
18217bool isVPERMPS(unsigned Opcode) {
18218 switch (Opcode) {
18219 case VPERMPSYrm:
18220 case VPERMPSYrr:
18221 case VPERMPSZ256rm:
18222 case VPERMPSZ256rmb:
18223 case VPERMPSZ256rmbk:
18224 case VPERMPSZ256rmbkz:
18225 case VPERMPSZ256rmk:
18226 case VPERMPSZ256rmkz:
18227 case VPERMPSZ256rr:
18228 case VPERMPSZ256rrk:
18229 case VPERMPSZ256rrkz:
18230 case VPERMPSZrm:
18231 case VPERMPSZrmb:
18232 case VPERMPSZrmbk:
18233 case VPERMPSZrmbkz:
18234 case VPERMPSZrmk:
18235 case VPERMPSZrmkz:
18236 case VPERMPSZrr:
18237 case VPERMPSZrrk:
18238 case VPERMPSZrrkz:
18239 return true;
18240 }
18241 return false;
18242}
18243
18244bool isVPSHUFBITQMB(unsigned Opcode) {
18245 switch (Opcode) {
18246 case VPSHUFBITQMBZ128rm:
18247 case VPSHUFBITQMBZ128rmk:
18248 case VPSHUFBITQMBZ128rr:
18249 case VPSHUFBITQMBZ128rrk:
18250 case VPSHUFBITQMBZ256rm:
18251 case VPSHUFBITQMBZ256rmk:
18252 case VPSHUFBITQMBZ256rr:
18253 case VPSHUFBITQMBZ256rrk:
18254 case VPSHUFBITQMBZrm:
18255 case VPSHUFBITQMBZrmk:
18256 case VPSHUFBITQMBZrr:
18257 case VPSHUFBITQMBZrrk:
18258 return true;
18259 }
18260 return false;
18261}
18262
18263bool isVMOVSLDUP(unsigned Opcode) {
18264 switch (Opcode) {
18265 case VMOVSLDUPYrm:
18266 case VMOVSLDUPYrr:
18267 case VMOVSLDUPZ128rm:
18268 case VMOVSLDUPZ128rmk:
18269 case VMOVSLDUPZ128rmkz:
18270 case VMOVSLDUPZ128rr:
18271 case VMOVSLDUPZ128rrk:
18272 case VMOVSLDUPZ128rrkz:
18273 case VMOVSLDUPZ256rm:
18274 case VMOVSLDUPZ256rmk:
18275 case VMOVSLDUPZ256rmkz:
18276 case VMOVSLDUPZ256rr:
18277 case VMOVSLDUPZ256rrk:
18278 case VMOVSLDUPZ256rrkz:
18279 case VMOVSLDUPZrm:
18280 case VMOVSLDUPZrmk:
18281 case VMOVSLDUPZrmkz:
18282 case VMOVSLDUPZrr:
18283 case VMOVSLDUPZrrk:
18284 case VMOVSLDUPZrrkz:
18285 case VMOVSLDUPrm:
18286 case VMOVSLDUPrr:
18287 return true;
18288 }
18289 return false;
18290}
18291
18292bool isINVLPGA(unsigned Opcode) {
18293 switch (Opcode) {
18294 case INVLPGA32:
18295 case INVLPGA64:
18296 return true;
18297 }
18298 return false;
18299}
18300
18301bool isVCVTPH2QQ(unsigned Opcode) {
18302 switch (Opcode) {
18303 case VCVTPH2QQZ128rm:
18304 case VCVTPH2QQZ128rmb:
18305 case VCVTPH2QQZ128rmbk:
18306 case VCVTPH2QQZ128rmbkz:
18307 case VCVTPH2QQZ128rmk:
18308 case VCVTPH2QQZ128rmkz:
18309 case VCVTPH2QQZ128rr:
18310 case VCVTPH2QQZ128rrk:
18311 case VCVTPH2QQZ128rrkz:
18312 case VCVTPH2QQZ256rm:
18313 case VCVTPH2QQZ256rmb:
18314 case VCVTPH2QQZ256rmbk:
18315 case VCVTPH2QQZ256rmbkz:
18316 case VCVTPH2QQZ256rmk:
18317 case VCVTPH2QQZ256rmkz:
18318 case VCVTPH2QQZ256rr:
18319 case VCVTPH2QQZ256rrk:
18320 case VCVTPH2QQZ256rrkz:
18321 case VCVTPH2QQZrm:
18322 case VCVTPH2QQZrmb:
18323 case VCVTPH2QQZrmbk:
18324 case VCVTPH2QQZrmbkz:
18325 case VCVTPH2QQZrmk:
18326 case VCVTPH2QQZrmkz:
18327 case VCVTPH2QQZrr:
18328 case VCVTPH2QQZrrb:
18329 case VCVTPH2QQZrrbk:
18330 case VCVTPH2QQZrrbkz:
18331 case VCVTPH2QQZrrk:
18332 case VCVTPH2QQZrrkz:
18333 return true;
18334 }
18335 return false;
18336}
18337
18338bool isADD(unsigned Opcode) {
18339 switch (Opcode) {
18340 case ADD16i16:
18341 case ADD16mi:
18342 case ADD16mi8:
18343 case ADD16mi8_EVEX:
18344 case ADD16mi8_ND:
18345 case ADD16mi8_NF:
18346 case ADD16mi8_NF_ND:
18347 case ADD16mi_EVEX:
18348 case ADD16mi_ND:
18349 case ADD16mi_NF:
18350 case ADD16mi_NF_ND:
18351 case ADD16mr:
18352 case ADD16mr_EVEX:
18353 case ADD16mr_ND:
18354 case ADD16mr_NF:
18355 case ADD16mr_NF_ND:
18356 case ADD16ri:
18357 case ADD16ri8:
18358 case ADD16ri8_EVEX:
18359 case ADD16ri8_ND:
18360 case ADD16ri8_NF:
18361 case ADD16ri8_NF_ND:
18362 case ADD16ri_EVEX:
18363 case ADD16ri_ND:
18364 case ADD16ri_NF:
18365 case ADD16ri_NF_ND:
18366 case ADD16rm:
18367 case ADD16rm_EVEX:
18368 case ADD16rm_ND:
18369 case ADD16rm_NF:
18370 case ADD16rm_NF_ND:
18371 case ADD16rr:
18372 case ADD16rr_EVEX:
18373 case ADD16rr_EVEX_REV:
18374 case ADD16rr_ND:
18375 case ADD16rr_ND_REV:
18376 case ADD16rr_NF:
18377 case ADD16rr_NF_ND:
18378 case ADD16rr_NF_ND_REV:
18379 case ADD16rr_NF_REV:
18380 case ADD16rr_REV:
18381 case ADD32i32:
18382 case ADD32mi:
18383 case ADD32mi8:
18384 case ADD32mi8_EVEX:
18385 case ADD32mi8_ND:
18386 case ADD32mi8_NF:
18387 case ADD32mi8_NF_ND:
18388 case ADD32mi_EVEX:
18389 case ADD32mi_ND:
18390 case ADD32mi_NF:
18391 case ADD32mi_NF_ND:
18392 case ADD32mr:
18393 case ADD32mr_EVEX:
18394 case ADD32mr_ND:
18395 case ADD32mr_NF:
18396 case ADD32mr_NF_ND:
18397 case ADD32ri:
18398 case ADD32ri8:
18399 case ADD32ri8_EVEX:
18400 case ADD32ri8_ND:
18401 case ADD32ri8_NF:
18402 case ADD32ri8_NF_ND:
18403 case ADD32ri_EVEX:
18404 case ADD32ri_ND:
18405 case ADD32ri_NF:
18406 case ADD32ri_NF_ND:
18407 case ADD32rm:
18408 case ADD32rm_EVEX:
18409 case ADD32rm_ND:
18410 case ADD32rm_NF:
18411 case ADD32rm_NF_ND:
18412 case ADD32rr:
18413 case ADD32rr_EVEX:
18414 case ADD32rr_EVEX_REV:
18415 case ADD32rr_ND:
18416 case ADD32rr_ND_REV:
18417 case ADD32rr_NF:
18418 case ADD32rr_NF_ND:
18419 case ADD32rr_NF_ND_REV:
18420 case ADD32rr_NF_REV:
18421 case ADD32rr_REV:
18422 case ADD64i32:
18423 case ADD64mi32:
18424 case ADD64mi32_EVEX:
18425 case ADD64mi32_ND:
18426 case ADD64mi32_NF:
18427 case ADD64mi32_NF_ND:
18428 case ADD64mi8:
18429 case ADD64mi8_EVEX:
18430 case ADD64mi8_ND:
18431 case ADD64mi8_NF:
18432 case ADD64mi8_NF_ND:
18433 case ADD64mr:
18434 case ADD64mr_EVEX:
18435 case ADD64mr_ND:
18436 case ADD64mr_NF:
18437 case ADD64mr_NF_ND:
18438 case ADD64ri32:
18439 case ADD64ri32_EVEX:
18440 case ADD64ri32_ND:
18441 case ADD64ri32_NF:
18442 case ADD64ri32_NF_ND:
18443 case ADD64ri8:
18444 case ADD64ri8_EVEX:
18445 case ADD64ri8_ND:
18446 case ADD64ri8_NF:
18447 case ADD64ri8_NF_ND:
18448 case ADD64rm:
18449 case ADD64rm_EVEX:
18450 case ADD64rm_ND:
18451 case ADD64rm_NF:
18452 case ADD64rm_NF_ND:
18453 case ADD64rr:
18454 case ADD64rr_EVEX:
18455 case ADD64rr_EVEX_REV:
18456 case ADD64rr_ND:
18457 case ADD64rr_ND_REV:
18458 case ADD64rr_NF:
18459 case ADD64rr_NF_ND:
18460 case ADD64rr_NF_ND_REV:
18461 case ADD64rr_NF_REV:
18462 case ADD64rr_REV:
18463 case ADD8i8:
18464 case ADD8mi:
18465 case ADD8mi8:
18466 case ADD8mi_EVEX:
18467 case ADD8mi_ND:
18468 case ADD8mi_NF:
18469 case ADD8mi_NF_ND:
18470 case ADD8mr:
18471 case ADD8mr_EVEX:
18472 case ADD8mr_ND:
18473 case ADD8mr_NF:
18474 case ADD8mr_NF_ND:
18475 case ADD8ri:
18476 case ADD8ri8:
18477 case ADD8ri_EVEX:
18478 case ADD8ri_ND:
18479 case ADD8ri_NF:
18480 case ADD8ri_NF_ND:
18481 case ADD8rm:
18482 case ADD8rm_EVEX:
18483 case ADD8rm_ND:
18484 case ADD8rm_NF:
18485 case ADD8rm_NF_ND:
18486 case ADD8rr:
18487 case ADD8rr_EVEX:
18488 case ADD8rr_EVEX_REV:
18489 case ADD8rr_ND:
18490 case ADD8rr_ND_REV:
18491 case ADD8rr_NF:
18492 case ADD8rr_NF_ND:
18493 case ADD8rr_NF_ND_REV:
18494 case ADD8rr_NF_REV:
18495 case ADD8rr_REV:
18496 return true;
18497 }
18498 return false;
18499}
18500
18501bool isPSUBSW(unsigned Opcode) {
18502 switch (Opcode) {
18503 case MMX_PSUBSWrm:
18504 case MMX_PSUBSWrr:
18505 case PSUBSWrm:
18506 case PSUBSWrr:
18507 return true;
18508 }
18509 return false;
18510}
18511
18512bool isSIDTW(unsigned Opcode) {
18513 return Opcode == SIDT16m;
18514}
18515
18516bool isVFNMADD231PH(unsigned Opcode) {
18517 switch (Opcode) {
18518 case VFNMADD231PHZ128m:
18519 case VFNMADD231PHZ128mb:
18520 case VFNMADD231PHZ128mbk:
18521 case VFNMADD231PHZ128mbkz:
18522 case VFNMADD231PHZ128mk:
18523 case VFNMADD231PHZ128mkz:
18524 case VFNMADD231PHZ128r:
18525 case VFNMADD231PHZ128rk:
18526 case VFNMADD231PHZ128rkz:
18527 case VFNMADD231PHZ256m:
18528 case VFNMADD231PHZ256mb:
18529 case VFNMADD231PHZ256mbk:
18530 case VFNMADD231PHZ256mbkz:
18531 case VFNMADD231PHZ256mk:
18532 case VFNMADD231PHZ256mkz:
18533 case VFNMADD231PHZ256r:
18534 case VFNMADD231PHZ256rk:
18535 case VFNMADD231PHZ256rkz:
18536 case VFNMADD231PHZm:
18537 case VFNMADD231PHZmb:
18538 case VFNMADD231PHZmbk:
18539 case VFNMADD231PHZmbkz:
18540 case VFNMADD231PHZmk:
18541 case VFNMADD231PHZmkz:
18542 case VFNMADD231PHZr:
18543 case VFNMADD231PHZrb:
18544 case VFNMADD231PHZrbk:
18545 case VFNMADD231PHZrbkz:
18546 case VFNMADD231PHZrk:
18547 case VFNMADD231PHZrkz:
18548 return true;
18549 }
18550 return false;
18551}
18552
18553bool isVEXTRACTF64X2(unsigned Opcode) {
18554 switch (Opcode) {
18555 case VEXTRACTF64X2Z256mri:
18556 case VEXTRACTF64X2Z256mrik:
18557 case VEXTRACTF64X2Z256rri:
18558 case VEXTRACTF64X2Z256rrik:
18559 case VEXTRACTF64X2Z256rrikz:
18560 case VEXTRACTF64X2Zmri:
18561 case VEXTRACTF64X2Zmrik:
18562 case VEXTRACTF64X2Zrri:
18563 case VEXTRACTF64X2Zrrik:
18564 case VEXTRACTF64X2Zrrikz:
18565 return true;
18566 }
18567 return false;
18568}
18569
18570bool isFCOMI(unsigned Opcode) {
18571 return Opcode == COM_FIr;
18572}
18573
18574bool isRSM(unsigned Opcode) {
18575 return Opcode == RSM;
18576}
18577
18578bool isVPCOMUD(unsigned Opcode) {
18579 switch (Opcode) {
18580 case VPCOMUDmi:
18581 case VPCOMUDri:
18582 return true;
18583 }
18584 return false;
18585}
18586
18587bool isVPMOVZXBQ(unsigned Opcode) {
18588 switch (Opcode) {
18589 case VPMOVZXBQYrm:
18590 case VPMOVZXBQYrr:
18591 case VPMOVZXBQZ128rm:
18592 case VPMOVZXBQZ128rmk:
18593 case VPMOVZXBQZ128rmkz:
18594 case VPMOVZXBQZ128rr:
18595 case VPMOVZXBQZ128rrk:
18596 case VPMOVZXBQZ128rrkz:
18597 case VPMOVZXBQZ256rm:
18598 case VPMOVZXBQZ256rmk:
18599 case VPMOVZXBQZ256rmkz:
18600 case VPMOVZXBQZ256rr:
18601 case VPMOVZXBQZ256rrk:
18602 case VPMOVZXBQZ256rrkz:
18603 case VPMOVZXBQZrm:
18604 case VPMOVZXBQZrmk:
18605 case VPMOVZXBQZrmkz:
18606 case VPMOVZXBQZrr:
18607 case VPMOVZXBQZrrk:
18608 case VPMOVZXBQZrrkz:
18609 case VPMOVZXBQrm:
18610 case VPMOVZXBQrr:
18611 return true;
18612 }
18613 return false;
18614}
18615
18616bool isUWRMSR(unsigned Opcode) {
18617 switch (Opcode) {
18618 case UWRMSRir:
18619 case UWRMSRir_EVEX:
18620 case UWRMSRrr:
18621 case UWRMSRrr_EVEX:
18622 return true;
18623 }
18624 return false;
18625}
18626
18627bool isLGS(unsigned Opcode) {
18628 switch (Opcode) {
18629 case LGS16rm:
18630 case LGS32rm:
18631 case LGS64rm:
18632 return true;
18633 }
18634 return false;
18635}
18636
18637bool isVMOVNTPD(unsigned Opcode) {
18638 switch (Opcode) {
18639 case VMOVNTPDYmr:
18640 case VMOVNTPDZ128mr:
18641 case VMOVNTPDZ256mr:
18642 case VMOVNTPDZmr:
18643 case VMOVNTPDmr:
18644 return true;
18645 }
18646 return false;
18647}
18648
18649bool isRDPRU(unsigned Opcode) {
18650 return Opcode == RDPRU;
18651}
18652
18653bool isVPUNPCKHBW(unsigned Opcode) {
18654 switch (Opcode) {
18655 case VPUNPCKHBWYrm:
18656 case VPUNPCKHBWYrr:
18657 case VPUNPCKHBWZ128rm:
18658 case VPUNPCKHBWZ128rmk:
18659 case VPUNPCKHBWZ128rmkz:
18660 case VPUNPCKHBWZ128rr:
18661 case VPUNPCKHBWZ128rrk:
18662 case VPUNPCKHBWZ128rrkz:
18663 case VPUNPCKHBWZ256rm:
18664 case VPUNPCKHBWZ256rmk:
18665 case VPUNPCKHBWZ256rmkz:
18666 case VPUNPCKHBWZ256rr:
18667 case VPUNPCKHBWZ256rrk:
18668 case VPUNPCKHBWZ256rrkz:
18669 case VPUNPCKHBWZrm:
18670 case VPUNPCKHBWZrmk:
18671 case VPUNPCKHBWZrmkz:
18672 case VPUNPCKHBWZrr:
18673 case VPUNPCKHBWZrrk:
18674 case VPUNPCKHBWZrrkz:
18675 case VPUNPCKHBWrm:
18676 case VPUNPCKHBWrr:
18677 return true;
18678 }
18679 return false;
18680}
18681
18682bool isVUCOMXSD(unsigned Opcode) {
18683 switch (Opcode) {
18684 case VUCOMXSDZrm_Int:
18685 case VUCOMXSDZrr_Int:
18686 case VUCOMXSDZrrb_Int:
18687 return true;
18688 }
18689 return false;
18690}
18691
18692bool isANDN(unsigned Opcode) {
18693 switch (Opcode) {
18694 case ANDN32rm:
18695 case ANDN32rm_EVEX:
18696 case ANDN32rm_NF:
18697 case ANDN32rr:
18698 case ANDN32rr_EVEX:
18699 case ANDN32rr_NF:
18700 case ANDN64rm:
18701 case ANDN64rm_EVEX:
18702 case ANDN64rm_NF:
18703 case ANDN64rr:
18704 case ANDN64rr_EVEX:
18705 case ANDN64rr_NF:
18706 return true;
18707 }
18708 return false;
18709}
18710
18711bool isVCVTTPH2UW(unsigned Opcode) {
18712 switch (Opcode) {
18713 case VCVTTPH2UWZ128rm:
18714 case VCVTTPH2UWZ128rmb:
18715 case VCVTTPH2UWZ128rmbk:
18716 case VCVTTPH2UWZ128rmbkz:
18717 case VCVTTPH2UWZ128rmk:
18718 case VCVTTPH2UWZ128rmkz:
18719 case VCVTTPH2UWZ128rr:
18720 case VCVTTPH2UWZ128rrk:
18721 case VCVTTPH2UWZ128rrkz:
18722 case VCVTTPH2UWZ256rm:
18723 case VCVTTPH2UWZ256rmb:
18724 case VCVTTPH2UWZ256rmbk:
18725 case VCVTTPH2UWZ256rmbkz:
18726 case VCVTTPH2UWZ256rmk:
18727 case VCVTTPH2UWZ256rmkz:
18728 case VCVTTPH2UWZ256rr:
18729 case VCVTTPH2UWZ256rrk:
18730 case VCVTTPH2UWZ256rrkz:
18731 case VCVTTPH2UWZrm:
18732 case VCVTTPH2UWZrmb:
18733 case VCVTTPH2UWZrmbk:
18734 case VCVTTPH2UWZrmbkz:
18735 case VCVTTPH2UWZrmk:
18736 case VCVTTPH2UWZrmkz:
18737 case VCVTTPH2UWZrr:
18738 case VCVTTPH2UWZrrb:
18739 case VCVTTPH2UWZrrbk:
18740 case VCVTTPH2UWZrrbkz:
18741 case VCVTTPH2UWZrrk:
18742 case VCVTTPH2UWZrrkz:
18743 return true;
18744 }
18745 return false;
18746}
18747
18748bool isVMFUNC(unsigned Opcode) {
18749 return Opcode == VMFUNC;
18750}
18751
18752bool isT2RPNTLVWZ0(unsigned Opcode) {
18753 switch (Opcode) {
18754 case T2RPNTLVWZ0:
18755 case T2RPNTLVWZ0_EVEX:
18756 return true;
18757 }
18758 return false;
18759}
18760
18761bool isFIMUL(unsigned Opcode) {
18762 switch (Opcode) {
18763 case MUL_FI16m:
18764 case MUL_FI32m:
18765 return true;
18766 }
18767 return false;
18768}
18769
18770bool isBLCFILL(unsigned Opcode) {
18771 switch (Opcode) {
18772 case BLCFILL32rm:
18773 case BLCFILL32rr:
18774 case BLCFILL64rm:
18775 case BLCFILL64rr:
18776 return true;
18777 }
18778 return false;
18779}
18780
18781bool isVGATHERPF0DPS(unsigned Opcode) {
18782 return Opcode == VGATHERPF0DPSm;
18783}
18784
18785bool isVFMSUBADD231PS(unsigned Opcode) {
18786 switch (Opcode) {
18787 case VFMSUBADD231PSYm:
18788 case VFMSUBADD231PSYr:
18789 case VFMSUBADD231PSZ128m:
18790 case VFMSUBADD231PSZ128mb:
18791 case VFMSUBADD231PSZ128mbk:
18792 case VFMSUBADD231PSZ128mbkz:
18793 case VFMSUBADD231PSZ128mk:
18794 case VFMSUBADD231PSZ128mkz:
18795 case VFMSUBADD231PSZ128r:
18796 case VFMSUBADD231PSZ128rk:
18797 case VFMSUBADD231PSZ128rkz:
18798 case VFMSUBADD231PSZ256m:
18799 case VFMSUBADD231PSZ256mb:
18800 case VFMSUBADD231PSZ256mbk:
18801 case VFMSUBADD231PSZ256mbkz:
18802 case VFMSUBADD231PSZ256mk:
18803 case VFMSUBADD231PSZ256mkz:
18804 case VFMSUBADD231PSZ256r:
18805 case VFMSUBADD231PSZ256rk:
18806 case VFMSUBADD231PSZ256rkz:
18807 case VFMSUBADD231PSZm:
18808 case VFMSUBADD231PSZmb:
18809 case VFMSUBADD231PSZmbk:
18810 case VFMSUBADD231PSZmbkz:
18811 case VFMSUBADD231PSZmk:
18812 case VFMSUBADD231PSZmkz:
18813 case VFMSUBADD231PSZr:
18814 case VFMSUBADD231PSZrb:
18815 case VFMSUBADD231PSZrbk:
18816 case VFMSUBADD231PSZrbkz:
18817 case VFMSUBADD231PSZrk:
18818 case VFMSUBADD231PSZrkz:
18819 case VFMSUBADD231PSm:
18820 case VFMSUBADD231PSr:
18821 return true;
18822 }
18823 return false;
18824}
18825
18826bool isVREDUCESD(unsigned Opcode) {
18827 switch (Opcode) {
18828 case VREDUCESDZrmi:
18829 case VREDUCESDZrmik:
18830 case VREDUCESDZrmikz:
18831 case VREDUCESDZrri:
18832 case VREDUCESDZrrib:
18833 case VREDUCESDZrribk:
18834 case VREDUCESDZrribkz:
18835 case VREDUCESDZrrik:
18836 case VREDUCESDZrrikz:
18837 return true;
18838 }
18839 return false;
18840}
18841
18842bool isVCOMXSH(unsigned Opcode) {
18843 switch (Opcode) {
18844 case VCOMXSHZrm_Int:
18845 case VCOMXSHZrr_Int:
18846 case VCOMXSHZrrb_Int:
18847 return true;
18848 }
18849 return false;
18850}
18851
18852bool isVXORPS(unsigned Opcode) {
18853 switch (Opcode) {
18854 case VXORPSYrm:
18855 case VXORPSYrr:
18856 case VXORPSZ128rm:
18857 case VXORPSZ128rmb:
18858 case VXORPSZ128rmbk:
18859 case VXORPSZ128rmbkz:
18860 case VXORPSZ128rmk:
18861 case VXORPSZ128rmkz:
18862 case VXORPSZ128rr:
18863 case VXORPSZ128rrk:
18864 case VXORPSZ128rrkz:
18865 case VXORPSZ256rm:
18866 case VXORPSZ256rmb:
18867 case VXORPSZ256rmbk:
18868 case VXORPSZ256rmbkz:
18869 case VXORPSZ256rmk:
18870 case VXORPSZ256rmkz:
18871 case VXORPSZ256rr:
18872 case VXORPSZ256rrk:
18873 case VXORPSZ256rrkz:
18874 case VXORPSZrm:
18875 case VXORPSZrmb:
18876 case VXORPSZrmbk:
18877 case VXORPSZrmbkz:
18878 case VXORPSZrmk:
18879 case VXORPSZrmkz:
18880 case VXORPSZrr:
18881 case VXORPSZrrk:
18882 case VXORPSZrrkz:
18883 case VXORPSrm:
18884 case VXORPSrr:
18885 return true;
18886 }
18887 return false;
18888}
18889
18890bool isPSWAPD(unsigned Opcode) {
18891 switch (Opcode) {
18892 case PSWAPDrm:
18893 case PSWAPDrr:
18894 return true;
18895 }
18896 return false;
18897}
18898
18899bool isPMAXSD(unsigned Opcode) {
18900 switch (Opcode) {
18901 case PMAXSDrm:
18902 case PMAXSDrr:
18903 return true;
18904 }
18905 return false;
18906}
18907
18908bool isVCMPSS(unsigned Opcode) {
18909 switch (Opcode) {
18910 case VCMPSSZrmi_Int:
18911 case VCMPSSZrmik_Int:
18912 case VCMPSSZrri_Int:
18913 case VCMPSSZrrib_Int:
18914 case VCMPSSZrribk_Int:
18915 case VCMPSSZrrik_Int:
18916 case VCMPSSrmi_Int:
18917 case VCMPSSrri_Int:
18918 return true;
18919 }
18920 return false;
18921}
18922
18923bool isEXTRACTPS(unsigned Opcode) {
18924 switch (Opcode) {
18925 case EXTRACTPSmri:
18926 case EXTRACTPSrri:
18927 return true;
18928 }
18929 return false;
18930}
18931
18932bool isVPMOVZXBD(unsigned Opcode) {
18933 switch (Opcode) {
18934 case VPMOVZXBDYrm:
18935 case VPMOVZXBDYrr:
18936 case VPMOVZXBDZ128rm:
18937 case VPMOVZXBDZ128rmk:
18938 case VPMOVZXBDZ128rmkz:
18939 case VPMOVZXBDZ128rr:
18940 case VPMOVZXBDZ128rrk:
18941 case VPMOVZXBDZ128rrkz:
18942 case VPMOVZXBDZ256rm:
18943 case VPMOVZXBDZ256rmk:
18944 case VPMOVZXBDZ256rmkz:
18945 case VPMOVZXBDZ256rr:
18946 case VPMOVZXBDZ256rrk:
18947 case VPMOVZXBDZ256rrkz:
18948 case VPMOVZXBDZrm:
18949 case VPMOVZXBDZrmk:
18950 case VPMOVZXBDZrmkz:
18951 case VPMOVZXBDZrr:
18952 case VPMOVZXBDZrrk:
18953 case VPMOVZXBDZrrkz:
18954 case VPMOVZXBDrm:
18955 case VPMOVZXBDrr:
18956 return true;
18957 }
18958 return false;
18959}
18960
18961bool isOUTSW(unsigned Opcode) {
18962 return Opcode == OUTSW;
18963}
18964
18965bool isKORTESTB(unsigned Opcode) {
18966 return Opcode == KORTESTBkk;
18967}
18968
18969bool isVREDUCEPS(unsigned Opcode) {
18970 switch (Opcode) {
18971 case VREDUCEPSZ128rmbi:
18972 case VREDUCEPSZ128rmbik:
18973 case VREDUCEPSZ128rmbikz:
18974 case VREDUCEPSZ128rmi:
18975 case VREDUCEPSZ128rmik:
18976 case VREDUCEPSZ128rmikz:
18977 case VREDUCEPSZ128rri:
18978 case VREDUCEPSZ128rrik:
18979 case VREDUCEPSZ128rrikz:
18980 case VREDUCEPSZ256rmbi:
18981 case VREDUCEPSZ256rmbik:
18982 case VREDUCEPSZ256rmbikz:
18983 case VREDUCEPSZ256rmi:
18984 case VREDUCEPSZ256rmik:
18985 case VREDUCEPSZ256rmikz:
18986 case VREDUCEPSZ256rri:
18987 case VREDUCEPSZ256rrik:
18988 case VREDUCEPSZ256rrikz:
18989 case VREDUCEPSZrmbi:
18990 case VREDUCEPSZrmbik:
18991 case VREDUCEPSZrmbikz:
18992 case VREDUCEPSZrmi:
18993 case VREDUCEPSZrmik:
18994 case VREDUCEPSZrmikz:
18995 case VREDUCEPSZrri:
18996 case VREDUCEPSZrrib:
18997 case VREDUCEPSZrribk:
18998 case VREDUCEPSZrribkz:
18999 case VREDUCEPSZrrik:
19000 case VREDUCEPSZrrikz:
19001 return true;
19002 }
19003 return false;
19004}
19005
19006bool isPEXTRW(unsigned Opcode) {
19007 switch (Opcode) {
19008 case MMX_PEXTRWrri:
19009 case PEXTRWmri:
19010 case PEXTRWrri:
19011 case PEXTRWrri_REV:
19012 return true;
19013 }
19014 return false;
19015}
19016
19017bool isFNINIT(unsigned Opcode) {
19018 return Opcode == FNINIT;
19019}
19020
19021bool isVCVTPH2IBS(unsigned Opcode) {
19022 switch (Opcode) {
19023 case VCVTPH2IBSZ128rm:
19024 case VCVTPH2IBSZ128rmb:
19025 case VCVTPH2IBSZ128rmbk:
19026 case VCVTPH2IBSZ128rmbkz:
19027 case VCVTPH2IBSZ128rmk:
19028 case VCVTPH2IBSZ128rmkz:
19029 case VCVTPH2IBSZ128rr:
19030 case VCVTPH2IBSZ128rrk:
19031 case VCVTPH2IBSZ128rrkz:
19032 case VCVTPH2IBSZ256rm:
19033 case VCVTPH2IBSZ256rmb:
19034 case VCVTPH2IBSZ256rmbk:
19035 case VCVTPH2IBSZ256rmbkz:
19036 case VCVTPH2IBSZ256rmk:
19037 case VCVTPH2IBSZ256rmkz:
19038 case VCVTPH2IBSZ256rr:
19039 case VCVTPH2IBSZ256rrk:
19040 case VCVTPH2IBSZ256rrkz:
19041 case VCVTPH2IBSZrm:
19042 case VCVTPH2IBSZrmb:
19043 case VCVTPH2IBSZrmbk:
19044 case VCVTPH2IBSZrmbkz:
19045 case VCVTPH2IBSZrmk:
19046 case VCVTPH2IBSZrmkz:
19047 case VCVTPH2IBSZrr:
19048 case VCVTPH2IBSZrrb:
19049 case VCVTPH2IBSZrrbk:
19050 case VCVTPH2IBSZrrbkz:
19051 case VCVTPH2IBSZrrk:
19052 case VCVTPH2IBSZrrkz:
19053 return true;
19054 }
19055 return false;
19056}
19057
19058bool isROL(unsigned Opcode) {
19059 switch (Opcode) {
19060 case ROL16m1:
19061 case ROL16m1_EVEX:
19062 case ROL16m1_ND:
19063 case ROL16m1_NF:
19064 case ROL16m1_NF_ND:
19065 case ROL16mCL:
19066 case ROL16mCL_EVEX:
19067 case ROL16mCL_ND:
19068 case ROL16mCL_NF:
19069 case ROL16mCL_NF_ND:
19070 case ROL16mi:
19071 case ROL16mi_EVEX:
19072 case ROL16mi_ND:
19073 case ROL16mi_NF:
19074 case ROL16mi_NF_ND:
19075 case ROL16r1:
19076 case ROL16r1_EVEX:
19077 case ROL16r1_ND:
19078 case ROL16r1_NF:
19079 case ROL16r1_NF_ND:
19080 case ROL16rCL:
19081 case ROL16rCL_EVEX:
19082 case ROL16rCL_ND:
19083 case ROL16rCL_NF:
19084 case ROL16rCL_NF_ND:
19085 case ROL16ri:
19086 case ROL16ri_EVEX:
19087 case ROL16ri_ND:
19088 case ROL16ri_NF:
19089 case ROL16ri_NF_ND:
19090 case ROL32m1:
19091 case ROL32m1_EVEX:
19092 case ROL32m1_ND:
19093 case ROL32m1_NF:
19094 case ROL32m1_NF_ND:
19095 case ROL32mCL:
19096 case ROL32mCL_EVEX:
19097 case ROL32mCL_ND:
19098 case ROL32mCL_NF:
19099 case ROL32mCL_NF_ND:
19100 case ROL32mi:
19101 case ROL32mi_EVEX:
19102 case ROL32mi_ND:
19103 case ROL32mi_NF:
19104 case ROL32mi_NF_ND:
19105 case ROL32r1:
19106 case ROL32r1_EVEX:
19107 case ROL32r1_ND:
19108 case ROL32r1_NF:
19109 case ROL32r1_NF_ND:
19110 case ROL32rCL:
19111 case ROL32rCL_EVEX:
19112 case ROL32rCL_ND:
19113 case ROL32rCL_NF:
19114 case ROL32rCL_NF_ND:
19115 case ROL32ri:
19116 case ROL32ri_EVEX:
19117 case ROL32ri_ND:
19118 case ROL32ri_NF:
19119 case ROL32ri_NF_ND:
19120 case ROL64m1:
19121 case ROL64m1_EVEX:
19122 case ROL64m1_ND:
19123 case ROL64m1_NF:
19124 case ROL64m1_NF_ND:
19125 case ROL64mCL:
19126 case ROL64mCL_EVEX:
19127 case ROL64mCL_ND:
19128 case ROL64mCL_NF:
19129 case ROL64mCL_NF_ND:
19130 case ROL64mi:
19131 case ROL64mi_EVEX:
19132 case ROL64mi_ND:
19133 case ROL64mi_NF:
19134 case ROL64mi_NF_ND:
19135 case ROL64r1:
19136 case ROL64r1_EVEX:
19137 case ROL64r1_ND:
19138 case ROL64r1_NF:
19139 case ROL64r1_NF_ND:
19140 case ROL64rCL:
19141 case ROL64rCL_EVEX:
19142 case ROL64rCL_ND:
19143 case ROL64rCL_NF:
19144 case ROL64rCL_NF_ND:
19145 case ROL64ri:
19146 case ROL64ri_EVEX:
19147 case ROL64ri_ND:
19148 case ROL64ri_NF:
19149 case ROL64ri_NF_ND:
19150 case ROL8m1:
19151 case ROL8m1_EVEX:
19152 case ROL8m1_ND:
19153 case ROL8m1_NF:
19154 case ROL8m1_NF_ND:
19155 case ROL8mCL:
19156 case ROL8mCL_EVEX:
19157 case ROL8mCL_ND:
19158 case ROL8mCL_NF:
19159 case ROL8mCL_NF_ND:
19160 case ROL8mi:
19161 case ROL8mi_EVEX:
19162 case ROL8mi_ND:
19163 case ROL8mi_NF:
19164 case ROL8mi_NF_ND:
19165 case ROL8r1:
19166 case ROL8r1_EVEX:
19167 case ROL8r1_ND:
19168 case ROL8r1_NF:
19169 case ROL8r1_NF_ND:
19170 case ROL8rCL:
19171 case ROL8rCL_EVEX:
19172 case ROL8rCL_ND:
19173 case ROL8rCL_NF:
19174 case ROL8rCL_NF_ND:
19175 case ROL8ri:
19176 case ROL8ri_EVEX:
19177 case ROL8ri_ND:
19178 case ROL8ri_NF:
19179 case ROL8ri_NF_ND:
19180 return true;
19181 }
19182 return false;
19183}
19184
19185bool isVCVTPS2QQ(unsigned Opcode) {
19186 switch (Opcode) {
19187 case VCVTPS2QQZ128rm:
19188 case VCVTPS2QQZ128rmb:
19189 case VCVTPS2QQZ128rmbk:
19190 case VCVTPS2QQZ128rmbkz:
19191 case VCVTPS2QQZ128rmk:
19192 case VCVTPS2QQZ128rmkz:
19193 case VCVTPS2QQZ128rr:
19194 case VCVTPS2QQZ128rrk:
19195 case VCVTPS2QQZ128rrkz:
19196 case VCVTPS2QQZ256rm:
19197 case VCVTPS2QQZ256rmb:
19198 case VCVTPS2QQZ256rmbk:
19199 case VCVTPS2QQZ256rmbkz:
19200 case VCVTPS2QQZ256rmk:
19201 case VCVTPS2QQZ256rmkz:
19202 case VCVTPS2QQZ256rr:
19203 case VCVTPS2QQZ256rrk:
19204 case VCVTPS2QQZ256rrkz:
19205 case VCVTPS2QQZrm:
19206 case VCVTPS2QQZrmb:
19207 case VCVTPS2QQZrmbk:
19208 case VCVTPS2QQZrmbkz:
19209 case VCVTPS2QQZrmk:
19210 case VCVTPS2QQZrmkz:
19211 case VCVTPS2QQZrr:
19212 case VCVTPS2QQZrrb:
19213 case VCVTPS2QQZrrbk:
19214 case VCVTPS2QQZrrbkz:
19215 case VCVTPS2QQZrrk:
19216 case VCVTPS2QQZrrkz:
19217 return true;
19218 }
19219 return false;
19220}
19221
19222bool isVGETMANTPH(unsigned Opcode) {
19223 switch (Opcode) {
19224 case VGETMANTPHZ128rmbi:
19225 case VGETMANTPHZ128rmbik:
19226 case VGETMANTPHZ128rmbikz:
19227 case VGETMANTPHZ128rmi:
19228 case VGETMANTPHZ128rmik:
19229 case VGETMANTPHZ128rmikz:
19230 case VGETMANTPHZ128rri:
19231 case VGETMANTPHZ128rrik:
19232 case VGETMANTPHZ128rrikz:
19233 case VGETMANTPHZ256rmbi:
19234 case VGETMANTPHZ256rmbik:
19235 case VGETMANTPHZ256rmbikz:
19236 case VGETMANTPHZ256rmi:
19237 case VGETMANTPHZ256rmik:
19238 case VGETMANTPHZ256rmikz:
19239 case VGETMANTPHZ256rri:
19240 case VGETMANTPHZ256rrik:
19241 case VGETMANTPHZ256rrikz:
19242 case VGETMANTPHZrmbi:
19243 case VGETMANTPHZrmbik:
19244 case VGETMANTPHZrmbikz:
19245 case VGETMANTPHZrmi:
19246 case VGETMANTPHZrmik:
19247 case VGETMANTPHZrmikz:
19248 case VGETMANTPHZrri:
19249 case VGETMANTPHZrrib:
19250 case VGETMANTPHZrribk:
19251 case VGETMANTPHZrribkz:
19252 case VGETMANTPHZrrik:
19253 case VGETMANTPHZrrikz:
19254 return true;
19255 }
19256 return false;
19257}
19258
19259bool isPUNPCKLDQ(unsigned Opcode) {
19260 switch (Opcode) {
19261 case MMX_PUNPCKLDQrm:
19262 case MMX_PUNPCKLDQrr:
19263 case PUNPCKLDQrm:
19264 case PUNPCKLDQrr:
19265 return true;
19266 }
19267 return false;
19268}
19269
19270bool isPADDD(unsigned Opcode) {
19271 switch (Opcode) {
19272 case MMX_PADDDrm:
19273 case MMX_PADDDrr:
19274 case PADDDrm:
19275 case PADDDrr:
19276 return true;
19277 }
19278 return false;
19279}
19280
19281bool isVPSLLD(unsigned Opcode) {
19282 switch (Opcode) {
19283 case VPSLLDYri:
19284 case VPSLLDYrm:
19285 case VPSLLDYrr:
19286 case VPSLLDZ128mbi:
19287 case VPSLLDZ128mbik:
19288 case VPSLLDZ128mbikz:
19289 case VPSLLDZ128mi:
19290 case VPSLLDZ128mik:
19291 case VPSLLDZ128mikz:
19292 case VPSLLDZ128ri:
19293 case VPSLLDZ128rik:
19294 case VPSLLDZ128rikz:
19295 case VPSLLDZ128rm:
19296 case VPSLLDZ128rmk:
19297 case VPSLLDZ128rmkz:
19298 case VPSLLDZ128rr:
19299 case VPSLLDZ128rrk:
19300 case VPSLLDZ128rrkz:
19301 case VPSLLDZ256mbi:
19302 case VPSLLDZ256mbik:
19303 case VPSLLDZ256mbikz:
19304 case VPSLLDZ256mi:
19305 case VPSLLDZ256mik:
19306 case VPSLLDZ256mikz:
19307 case VPSLLDZ256ri:
19308 case VPSLLDZ256rik:
19309 case VPSLLDZ256rikz:
19310 case VPSLLDZ256rm:
19311 case VPSLLDZ256rmk:
19312 case VPSLLDZ256rmkz:
19313 case VPSLLDZ256rr:
19314 case VPSLLDZ256rrk:
19315 case VPSLLDZ256rrkz:
19316 case VPSLLDZmbi:
19317 case VPSLLDZmbik:
19318 case VPSLLDZmbikz:
19319 case VPSLLDZmi:
19320 case VPSLLDZmik:
19321 case VPSLLDZmikz:
19322 case VPSLLDZri:
19323 case VPSLLDZrik:
19324 case VPSLLDZrikz:
19325 case VPSLLDZrm:
19326 case VPSLLDZrmk:
19327 case VPSLLDZrmkz:
19328 case VPSLLDZrr:
19329 case VPSLLDZrrk:
19330 case VPSLLDZrrkz:
19331 case VPSLLDri:
19332 case VPSLLDrm:
19333 case VPSLLDrr:
19334 return true;
19335 }
19336 return false;
19337}
19338
19339bool isPFCMPGE(unsigned Opcode) {
19340 switch (Opcode) {
19341 case PFCMPGErm:
19342 case PFCMPGErr:
19343 return true;
19344 }
19345 return false;
19346}
19347
19348bool isVGETMANTBF16(unsigned Opcode) {
19349 switch (Opcode) {
19350 case VGETMANTBF16Z128rmbi:
19351 case VGETMANTBF16Z128rmbik:
19352 case VGETMANTBF16Z128rmbikz:
19353 case VGETMANTBF16Z128rmi:
19354 case VGETMANTBF16Z128rmik:
19355 case VGETMANTBF16Z128rmikz:
19356 case VGETMANTBF16Z128rri:
19357 case VGETMANTBF16Z128rrik:
19358 case VGETMANTBF16Z128rrikz:
19359 case VGETMANTBF16Z256rmbi:
19360 case VGETMANTBF16Z256rmbik:
19361 case VGETMANTBF16Z256rmbikz:
19362 case VGETMANTBF16Z256rmi:
19363 case VGETMANTBF16Z256rmik:
19364 case VGETMANTBF16Z256rmikz:
19365 case VGETMANTBF16Z256rri:
19366 case VGETMANTBF16Z256rrik:
19367 case VGETMANTBF16Z256rrikz:
19368 case VGETMANTBF16Zrmbi:
19369 case VGETMANTBF16Zrmbik:
19370 case VGETMANTBF16Zrmbikz:
19371 case VGETMANTBF16Zrmi:
19372 case VGETMANTBF16Zrmik:
19373 case VGETMANTBF16Zrmikz:
19374 case VGETMANTBF16Zrri:
19375 case VGETMANTBF16Zrrik:
19376 case VGETMANTBF16Zrrikz:
19377 return true;
19378 }
19379 return false;
19380}
19381
19382bool isVSUBBF16(unsigned Opcode) {
19383 switch (Opcode) {
19384 case VSUBBF16Z128rm:
19385 case VSUBBF16Z128rmb:
19386 case VSUBBF16Z128rmbk:
19387 case VSUBBF16Z128rmbkz:
19388 case VSUBBF16Z128rmk:
19389 case VSUBBF16Z128rmkz:
19390 case VSUBBF16Z128rr:
19391 case VSUBBF16Z128rrk:
19392 case VSUBBF16Z128rrkz:
19393 case VSUBBF16Z256rm:
19394 case VSUBBF16Z256rmb:
19395 case VSUBBF16Z256rmbk:
19396 case VSUBBF16Z256rmbkz:
19397 case VSUBBF16Z256rmk:
19398 case VSUBBF16Z256rmkz:
19399 case VSUBBF16Z256rr:
19400 case VSUBBF16Z256rrk:
19401 case VSUBBF16Z256rrkz:
19402 case VSUBBF16Zrm:
19403 case VSUBBF16Zrmb:
19404 case VSUBBF16Zrmbk:
19405 case VSUBBF16Zrmbkz:
19406 case VSUBBF16Zrmk:
19407 case VSUBBF16Zrmkz:
19408 case VSUBBF16Zrr:
19409 case VSUBBF16Zrrk:
19410 case VSUBBF16Zrrkz:
19411 return true;
19412 }
19413 return false;
19414}
19415
19416bool isVPMOVM2D(unsigned Opcode) {
19417 switch (Opcode) {
19418 case VPMOVM2DZ128rk:
19419 case VPMOVM2DZ256rk:
19420 case VPMOVM2DZrk:
19421 return true;
19422 }
19423 return false;
19424}
19425
19426bool isVCVTTSS2USIS(unsigned Opcode) {
19427 switch (Opcode) {
19428 case VCVTTSS2USI64Srm_Int:
19429 case VCVTTSS2USI64Srr_Int:
19430 case VCVTTSS2USI64Srrb_Int:
19431 case VCVTTSS2USISrm_Int:
19432 case VCVTTSS2USISrr_Int:
19433 case VCVTTSS2USISrrb_Int:
19434 return true;
19435 }
19436 return false;
19437}
19438
19439bool isVHSUBPS(unsigned Opcode) {
19440 switch (Opcode) {
19441 case VHSUBPSYrm:
19442 case VHSUBPSYrr:
19443 case VHSUBPSrm:
19444 case VHSUBPSrr:
19445 return true;
19446 }
19447 return false;
19448}
19449
19450bool isENDBR32(unsigned Opcode) {
19451 return Opcode == ENDBR32;
19452}
19453
19454bool isMOVSXD(unsigned Opcode) {
19455 switch (Opcode) {
19456 case MOVSX16rm32:
19457 case MOVSX16rr32:
19458 case MOVSX32rm32:
19459 case MOVSX32rr32:
19460 case MOVSX64rm32:
19461 case MOVSX64rr32:
19462 return true;
19463 }
19464 return false;
19465}
19466
19467bool isPSIGND(unsigned Opcode) {
19468 switch (Opcode) {
19469 case MMX_PSIGNDrm:
19470 case MMX_PSIGNDrr:
19471 case PSIGNDrm:
19472 case PSIGNDrr:
19473 return true;
19474 }
19475 return false;
19476}
19477
19478bool isVPTEST(unsigned Opcode) {
19479 switch (Opcode) {
19480 case VPTESTYrm:
19481 case VPTESTYrr:
19482 case VPTESTrm:
19483 case VPTESTrr:
19484 return true;
19485 }
19486 return false;
19487}
19488
19489bool isVPDPWUSD(unsigned Opcode) {
19490 switch (Opcode) {
19491 case VPDPWUSDYrm:
19492 case VPDPWUSDYrr:
19493 case VPDPWUSDZ128m:
19494 case VPDPWUSDZ128mb:
19495 case VPDPWUSDZ128mbk:
19496 case VPDPWUSDZ128mbkz:
19497 case VPDPWUSDZ128mk:
19498 case VPDPWUSDZ128mkz:
19499 case VPDPWUSDZ128r:
19500 case VPDPWUSDZ128rk:
19501 case VPDPWUSDZ128rkz:
19502 case VPDPWUSDZ256m:
19503 case VPDPWUSDZ256mb:
19504 case VPDPWUSDZ256mbk:
19505 case VPDPWUSDZ256mbkz:
19506 case VPDPWUSDZ256mk:
19507 case VPDPWUSDZ256mkz:
19508 case VPDPWUSDZ256r:
19509 case VPDPWUSDZ256rk:
19510 case VPDPWUSDZ256rkz:
19511 case VPDPWUSDZm:
19512 case VPDPWUSDZmb:
19513 case VPDPWUSDZmbk:
19514 case VPDPWUSDZmbkz:
19515 case VPDPWUSDZmk:
19516 case VPDPWUSDZmkz:
19517 case VPDPWUSDZr:
19518 case VPDPWUSDZrk:
19519 case VPDPWUSDZrkz:
19520 case VPDPWUSDrm:
19521 case VPDPWUSDrr:
19522 return true;
19523 }
19524 return false;
19525}
19526
19527bool isHSUBPD(unsigned Opcode) {
19528 switch (Opcode) {
19529 case HSUBPDrm:
19530 case HSUBPDrr:
19531 return true;
19532 }
19533 return false;
19534}
19535
19536bool isADCX(unsigned Opcode) {
19537 switch (Opcode) {
19538 case ADCX32rm:
19539 case ADCX32rm_EVEX:
19540 case ADCX32rm_ND:
19541 case ADCX32rr:
19542 case ADCX32rr_EVEX:
19543 case ADCX32rr_ND:
19544 case ADCX64rm:
19545 case ADCX64rm_EVEX:
19546 case ADCX64rm_ND:
19547 case ADCX64rr:
19548 case ADCX64rr_EVEX:
19549 case ADCX64rr_ND:
19550 return true;
19551 }
19552 return false;
19553}
19554
19555bool isCVTTPD2PI(unsigned Opcode) {
19556 switch (Opcode) {
19557 case MMX_CVTTPD2PIrm:
19558 case MMX_CVTTPD2PIrr:
19559 return true;
19560 }
19561 return false;
19562}
19563
19564bool isPDEP(unsigned Opcode) {
19565 switch (Opcode) {
19566 case PDEP32rm:
19567 case PDEP32rm_EVEX:
19568 case PDEP32rr:
19569 case PDEP32rr_EVEX:
19570 case PDEP64rm:
19571 case PDEP64rm_EVEX:
19572 case PDEP64rr:
19573 case PDEP64rr_EVEX:
19574 return true;
19575 }
19576 return false;
19577}
19578
19579bool isTDPBUSD(unsigned Opcode) {
19580 return Opcode == TDPBUSD;
19581}
19582
19583bool isVCVTBIASPH2HF8S(unsigned Opcode) {
19584 switch (Opcode) {
19585 case VCVTBIASPH2HF8SZ128rm:
19586 case VCVTBIASPH2HF8SZ128rmb:
19587 case VCVTBIASPH2HF8SZ128rmbk:
19588 case VCVTBIASPH2HF8SZ128rmbkz:
19589 case VCVTBIASPH2HF8SZ128rmk:
19590 case VCVTBIASPH2HF8SZ128rmkz:
19591 case VCVTBIASPH2HF8SZ128rr:
19592 case VCVTBIASPH2HF8SZ128rrk:
19593 case VCVTBIASPH2HF8SZ128rrkz:
19594 case VCVTBIASPH2HF8SZ256rm:
19595 case VCVTBIASPH2HF8SZ256rmb:
19596 case VCVTBIASPH2HF8SZ256rmbk:
19597 case VCVTBIASPH2HF8SZ256rmbkz:
19598 case VCVTBIASPH2HF8SZ256rmk:
19599 case VCVTBIASPH2HF8SZ256rmkz:
19600 case VCVTBIASPH2HF8SZ256rr:
19601 case VCVTBIASPH2HF8SZ256rrk:
19602 case VCVTBIASPH2HF8SZ256rrkz:
19603 case VCVTBIASPH2HF8SZrm:
19604 case VCVTBIASPH2HF8SZrmb:
19605 case VCVTBIASPH2HF8SZrmbk:
19606 case VCVTBIASPH2HF8SZrmbkz:
19607 case VCVTBIASPH2HF8SZrmk:
19608 case VCVTBIASPH2HF8SZrmkz:
19609 case VCVTBIASPH2HF8SZrr:
19610 case VCVTBIASPH2HF8SZrrk:
19611 case VCVTBIASPH2HF8SZrrkz:
19612 return true;
19613 }
19614 return false;
19615}
19616
19617bool isVBROADCASTI32X4(unsigned Opcode) {
19618 switch (Opcode) {
19619 case VBROADCASTI32X4Z256rm:
19620 case VBROADCASTI32X4Z256rmk:
19621 case VBROADCASTI32X4Z256rmkz:
19622 case VBROADCASTI32X4Zrm:
19623 case VBROADCASTI32X4Zrmk:
19624 case VBROADCASTI32X4Zrmkz:
19625 return true;
19626 }
19627 return false;
19628}
19629
19630bool isVCVTPH2UDQ(unsigned Opcode) {
19631 switch (Opcode) {
19632 case VCVTPH2UDQZ128rm:
19633 case VCVTPH2UDQZ128rmb:
19634 case VCVTPH2UDQZ128rmbk:
19635 case VCVTPH2UDQZ128rmbkz:
19636 case VCVTPH2UDQZ128rmk:
19637 case VCVTPH2UDQZ128rmkz:
19638 case VCVTPH2UDQZ128rr:
19639 case VCVTPH2UDQZ128rrk:
19640 case VCVTPH2UDQZ128rrkz:
19641 case VCVTPH2UDQZ256rm:
19642 case VCVTPH2UDQZ256rmb:
19643 case VCVTPH2UDQZ256rmbk:
19644 case VCVTPH2UDQZ256rmbkz:
19645 case VCVTPH2UDQZ256rmk:
19646 case VCVTPH2UDQZ256rmkz:
19647 case VCVTPH2UDQZ256rr:
19648 case VCVTPH2UDQZ256rrk:
19649 case VCVTPH2UDQZ256rrkz:
19650 case VCVTPH2UDQZrm:
19651 case VCVTPH2UDQZrmb:
19652 case VCVTPH2UDQZrmbk:
19653 case VCVTPH2UDQZrmbkz:
19654 case VCVTPH2UDQZrmk:
19655 case VCVTPH2UDQZrmkz:
19656 case VCVTPH2UDQZrr:
19657 case VCVTPH2UDQZrrb:
19658 case VCVTPH2UDQZrrbk:
19659 case VCVTPH2UDQZrrbkz:
19660 case VCVTPH2UDQZrrk:
19661 case VCVTPH2UDQZrrkz:
19662 return true;
19663 }
19664 return false;
19665}
19666
19667bool isVPHADDW(unsigned Opcode) {
19668 switch (Opcode) {
19669 case VPHADDWYrm:
19670 case VPHADDWYrr:
19671 case VPHADDWrm:
19672 case VPHADDWrr:
19673 return true;
19674 }
19675 return false;
19676}
19677
19678bool isFLDL2E(unsigned Opcode) {
19679 return Opcode == FLDL2E;
19680}
19681
19682bool isCLZERO(unsigned Opcode) {
19683 switch (Opcode) {
19684 case CLZERO32r:
19685 case CLZERO64r:
19686 return true;
19687 }
19688 return false;
19689}
19690
19691bool isPBLENDW(unsigned Opcode) {
19692 switch (Opcode) {
19693 case PBLENDWrmi:
19694 case PBLENDWrri:
19695 return true;
19696 }
19697 return false;
19698}
19699
19700bool isVCVTBF162IUBS(unsigned Opcode) {
19701 switch (Opcode) {
19702 case VCVTBF162IUBSZ128rm:
19703 case VCVTBF162IUBSZ128rmb:
19704 case VCVTBF162IUBSZ128rmbk:
19705 case VCVTBF162IUBSZ128rmbkz:
19706 case VCVTBF162IUBSZ128rmk:
19707 case VCVTBF162IUBSZ128rmkz:
19708 case VCVTBF162IUBSZ128rr:
19709 case VCVTBF162IUBSZ128rrk:
19710 case VCVTBF162IUBSZ128rrkz:
19711 case VCVTBF162IUBSZ256rm:
19712 case VCVTBF162IUBSZ256rmb:
19713 case VCVTBF162IUBSZ256rmbk:
19714 case VCVTBF162IUBSZ256rmbkz:
19715 case VCVTBF162IUBSZ256rmk:
19716 case VCVTBF162IUBSZ256rmkz:
19717 case VCVTBF162IUBSZ256rr:
19718 case VCVTBF162IUBSZ256rrk:
19719 case VCVTBF162IUBSZ256rrkz:
19720 case VCVTBF162IUBSZrm:
19721 case VCVTBF162IUBSZrmb:
19722 case VCVTBF162IUBSZrmbk:
19723 case VCVTBF162IUBSZrmbkz:
19724 case VCVTBF162IUBSZrmk:
19725 case VCVTBF162IUBSZrmkz:
19726 case VCVTBF162IUBSZrr:
19727 case VCVTBF162IUBSZrrk:
19728 case VCVTBF162IUBSZrrkz:
19729 return true;
19730 }
19731 return false;
19732}
19733
19734bool isVCVTSH2USI(unsigned Opcode) {
19735 switch (Opcode) {
19736 case VCVTSH2USI64Zrm_Int:
19737 case VCVTSH2USI64Zrr_Int:
19738 case VCVTSH2USI64Zrrb_Int:
19739 case VCVTSH2USIZrm_Int:
19740 case VCVTSH2USIZrr_Int:
19741 case VCVTSH2USIZrrb_Int:
19742 return true;
19743 }
19744 return false;
19745}
19746
19747bool isVANDPD(unsigned Opcode) {
19748 switch (Opcode) {
19749 case VANDPDYrm:
19750 case VANDPDYrr:
19751 case VANDPDZ128rm:
19752 case VANDPDZ128rmb:
19753 case VANDPDZ128rmbk:
19754 case VANDPDZ128rmbkz:
19755 case VANDPDZ128rmk:
19756 case VANDPDZ128rmkz:
19757 case VANDPDZ128rr:
19758 case VANDPDZ128rrk:
19759 case VANDPDZ128rrkz:
19760 case VANDPDZ256rm:
19761 case VANDPDZ256rmb:
19762 case VANDPDZ256rmbk:
19763 case VANDPDZ256rmbkz:
19764 case VANDPDZ256rmk:
19765 case VANDPDZ256rmkz:
19766 case VANDPDZ256rr:
19767 case VANDPDZ256rrk:
19768 case VANDPDZ256rrkz:
19769 case VANDPDZrm:
19770 case VANDPDZrmb:
19771 case VANDPDZrmbk:
19772 case VANDPDZrmbkz:
19773 case VANDPDZrmk:
19774 case VANDPDZrmkz:
19775 case VANDPDZrr:
19776 case VANDPDZrrk:
19777 case VANDPDZrrkz:
19778 case VANDPDrm:
19779 case VANDPDrr:
19780 return true;
19781 }
19782 return false;
19783}
19784
19785bool isBEXTR(unsigned Opcode) {
19786 switch (Opcode) {
19787 case BEXTR32rm:
19788 case BEXTR32rm_EVEX:
19789 case BEXTR32rm_NF:
19790 case BEXTR32rr:
19791 case BEXTR32rr_EVEX:
19792 case BEXTR32rr_NF:
19793 case BEXTR64rm:
19794 case BEXTR64rm_EVEX:
19795 case BEXTR64rm_NF:
19796 case BEXTR64rr:
19797 case BEXTR64rr_EVEX:
19798 case BEXTR64rr_NF:
19799 case BEXTRI32mi:
19800 case BEXTRI32ri:
19801 case BEXTRI64mi:
19802 case BEXTRI64ri:
19803 return true;
19804 }
19805 return false;
19806}
19807
19808bool isSTD(unsigned Opcode) {
19809 return Opcode == STD;
19810}
19811
19812bool isVAESKEYGENASSIST(unsigned Opcode) {
19813 switch (Opcode) {
19814 case VAESKEYGENASSIST128rm:
19815 case VAESKEYGENASSIST128rr:
19816 return true;
19817 }
19818 return false;
19819}
19820
19821bool isCMPSD(unsigned Opcode) {
19822 switch (Opcode) {
19823 case CMPSDrmi_Int:
19824 case CMPSDrri_Int:
19825 case CMPSL:
19826 return true;
19827 }
19828 return false;
19829}
19830
19831bool isMOVSS(unsigned Opcode) {
19832 switch (Opcode) {
19833 case MOVSSmr:
19834 case MOVSSrm:
19835 case MOVSSrr:
19836 case MOVSSrr_REV:
19837 return true;
19838 }
19839 return false;
19840}
19841
19842bool isVCVTUQQ2PD(unsigned Opcode) {
19843 switch (Opcode) {
19844 case VCVTUQQ2PDZ128rm:
19845 case VCVTUQQ2PDZ128rmb:
19846 case VCVTUQQ2PDZ128rmbk:
19847 case VCVTUQQ2PDZ128rmbkz:
19848 case VCVTUQQ2PDZ128rmk:
19849 case VCVTUQQ2PDZ128rmkz:
19850 case VCVTUQQ2PDZ128rr:
19851 case VCVTUQQ2PDZ128rrk:
19852 case VCVTUQQ2PDZ128rrkz:
19853 case VCVTUQQ2PDZ256rm:
19854 case VCVTUQQ2PDZ256rmb:
19855 case VCVTUQQ2PDZ256rmbk:
19856 case VCVTUQQ2PDZ256rmbkz:
19857 case VCVTUQQ2PDZ256rmk:
19858 case VCVTUQQ2PDZ256rmkz:
19859 case VCVTUQQ2PDZ256rr:
19860 case VCVTUQQ2PDZ256rrk:
19861 case VCVTUQQ2PDZ256rrkz:
19862 case VCVTUQQ2PDZrm:
19863 case VCVTUQQ2PDZrmb:
19864 case VCVTUQQ2PDZrmbk:
19865 case VCVTUQQ2PDZrmbkz:
19866 case VCVTUQQ2PDZrmk:
19867 case VCVTUQQ2PDZrmkz:
19868 case VCVTUQQ2PDZrr:
19869 case VCVTUQQ2PDZrrb:
19870 case VCVTUQQ2PDZrrbk:
19871 case VCVTUQQ2PDZrrbkz:
19872 case VCVTUQQ2PDZrrk:
19873 case VCVTUQQ2PDZrrkz:
19874 return true;
19875 }
19876 return false;
19877}
19878
19879bool isVEXTRACTI32X4(unsigned Opcode) {
19880 switch (Opcode) {
19881 case VEXTRACTI32X4Z256mri:
19882 case VEXTRACTI32X4Z256mrik:
19883 case VEXTRACTI32X4Z256rri:
19884 case VEXTRACTI32X4Z256rrik:
19885 case VEXTRACTI32X4Z256rrikz:
19886 case VEXTRACTI32X4Zmri:
19887 case VEXTRACTI32X4Zmrik:
19888 case VEXTRACTI32X4Zrri:
19889 case VEXTRACTI32X4Zrrik:
19890 case VEXTRACTI32X4Zrrikz:
19891 return true;
19892 }
19893 return false;
19894}
19895
19896bool isFLDCW(unsigned Opcode) {
19897 return Opcode == FLDCW16m;
19898}
19899
19900bool isINSW(unsigned Opcode) {
19901 return Opcode == INSW;
19902}
19903
19904bool isRDPID(unsigned Opcode) {
19905 switch (Opcode) {
19906 case RDPID32:
19907 case RDPID64:
19908 return true;
19909 }
19910 return false;
19911}
19912
19913bool isVUCOMXSS(unsigned Opcode) {
19914 switch (Opcode) {
19915 case VUCOMXSSZrm_Int:
19916 case VUCOMXSSZrr_Int:
19917 case VUCOMXSSZrrb_Int:
19918 return true;
19919 }
19920 return false;
19921}
19922
19923bool isKANDQ(unsigned Opcode) {
19924 return Opcode == KANDQkk;
19925}
19926
19927bool isV4FMADDPS(unsigned Opcode) {
19928 switch (Opcode) {
19929 case V4FMADDPSrm:
19930 case V4FMADDPSrmk:
19931 case V4FMADDPSrmkz:
19932 return true;
19933 }
19934 return false;
19935}
19936
19937bool isPMOVZXWQ(unsigned Opcode) {
19938 switch (Opcode) {
19939 case PMOVZXWQrm:
19940 case PMOVZXWQrr:
19941 return true;
19942 }
19943 return false;
19944}
19945
19946bool isVFPCLASSSD(unsigned Opcode) {
19947 switch (Opcode) {
19948 case VFPCLASSSDZmi:
19949 case VFPCLASSSDZmik:
19950 case VFPCLASSSDZri:
19951 case VFPCLASSSDZrik:
19952 return true;
19953 }
19954 return false;
19955}
19956
19957bool isBLENDPS(unsigned Opcode) {
19958 switch (Opcode) {
19959 case BLENDPSrmi:
19960 case BLENDPSrri:
19961 return true;
19962 }
19963 return false;
19964}
19965
19966bool isVPACKSSDW(unsigned Opcode) {
19967 switch (Opcode) {
19968 case VPACKSSDWYrm:
19969 case VPACKSSDWYrr:
19970 case VPACKSSDWZ128rm:
19971 case VPACKSSDWZ128rmb:
19972 case VPACKSSDWZ128rmbk:
19973 case VPACKSSDWZ128rmbkz:
19974 case VPACKSSDWZ128rmk:
19975 case VPACKSSDWZ128rmkz:
19976 case VPACKSSDWZ128rr:
19977 case VPACKSSDWZ128rrk:
19978 case VPACKSSDWZ128rrkz:
19979 case VPACKSSDWZ256rm:
19980 case VPACKSSDWZ256rmb:
19981 case VPACKSSDWZ256rmbk:
19982 case VPACKSSDWZ256rmbkz:
19983 case VPACKSSDWZ256rmk:
19984 case VPACKSSDWZ256rmkz:
19985 case VPACKSSDWZ256rr:
19986 case VPACKSSDWZ256rrk:
19987 case VPACKSSDWZ256rrkz:
19988 case VPACKSSDWZrm:
19989 case VPACKSSDWZrmb:
19990 case VPACKSSDWZrmbk:
19991 case VPACKSSDWZrmbkz:
19992 case VPACKSSDWZrmk:
19993 case VPACKSSDWZrmkz:
19994 case VPACKSSDWZrr:
19995 case VPACKSSDWZrrk:
19996 case VPACKSSDWZrrkz:
19997 case VPACKSSDWrm:
19998 case VPACKSSDWrr:
19999 return true;
20000 }
20001 return false;
20002}
20003
20004bool isVPINSRW(unsigned Opcode) {
20005 switch (Opcode) {
20006 case VPINSRWZrmi:
20007 case VPINSRWZrri:
20008 case VPINSRWrmi:
20009 case VPINSRWrri:
20010 return true;
20011 }
20012 return false;
20013}
20014
20015bool isFXAM(unsigned Opcode) {
20016 return Opcode == XAM_F;
20017}
20018
20019bool isVMINMAXBF16(unsigned Opcode) {
20020 switch (Opcode) {
20021 case VMINMAXBF16Z128rmbi:
20022 case VMINMAXBF16Z128rmbik:
20023 case VMINMAXBF16Z128rmbikz:
20024 case VMINMAXBF16Z128rmi:
20025 case VMINMAXBF16Z128rmik:
20026 case VMINMAXBF16Z128rmikz:
20027 case VMINMAXBF16Z128rri:
20028 case VMINMAXBF16Z128rrik:
20029 case VMINMAXBF16Z128rrikz:
20030 case VMINMAXBF16Z256rmbi:
20031 case VMINMAXBF16Z256rmbik:
20032 case VMINMAXBF16Z256rmbikz:
20033 case VMINMAXBF16Z256rmi:
20034 case VMINMAXBF16Z256rmik:
20035 case VMINMAXBF16Z256rmikz:
20036 case VMINMAXBF16Z256rri:
20037 case VMINMAXBF16Z256rrik:
20038 case VMINMAXBF16Z256rrikz:
20039 case VMINMAXBF16Zrmbi:
20040 case VMINMAXBF16Zrmbik:
20041 case VMINMAXBF16Zrmbikz:
20042 case VMINMAXBF16Zrmi:
20043 case VMINMAXBF16Zrmik:
20044 case VMINMAXBF16Zrmikz:
20045 case VMINMAXBF16Zrri:
20046 case VMINMAXBF16Zrrik:
20047 case VMINMAXBF16Zrrikz:
20048 return true;
20049 }
20050 return false;
20051}
20052
20053bool isVSHUFF64X2(unsigned Opcode) {
20054 switch (Opcode) {
20055 case VSHUFF64X2Z256rmbi:
20056 case VSHUFF64X2Z256rmbik:
20057 case VSHUFF64X2Z256rmbikz:
20058 case VSHUFF64X2Z256rmi:
20059 case VSHUFF64X2Z256rmik:
20060 case VSHUFF64X2Z256rmikz:
20061 case VSHUFF64X2Z256rri:
20062 case VSHUFF64X2Z256rrik:
20063 case VSHUFF64X2Z256rrikz:
20064 case VSHUFF64X2Zrmbi:
20065 case VSHUFF64X2Zrmbik:
20066 case VSHUFF64X2Zrmbikz:
20067 case VSHUFF64X2Zrmi:
20068 case VSHUFF64X2Zrmik:
20069 case VSHUFF64X2Zrmikz:
20070 case VSHUFF64X2Zrri:
20071 case VSHUFF64X2Zrrik:
20072 case VSHUFF64X2Zrrikz:
20073 return true;
20074 }
20075 return false;
20076}
20077
20078bool isVPACKUSWB(unsigned Opcode) {
20079 switch (Opcode) {
20080 case VPACKUSWBYrm:
20081 case VPACKUSWBYrr:
20082 case VPACKUSWBZ128rm:
20083 case VPACKUSWBZ128rmk:
20084 case VPACKUSWBZ128rmkz:
20085 case VPACKUSWBZ128rr:
20086 case VPACKUSWBZ128rrk:
20087 case VPACKUSWBZ128rrkz:
20088 case VPACKUSWBZ256rm:
20089 case VPACKUSWBZ256rmk:
20090 case VPACKUSWBZ256rmkz:
20091 case VPACKUSWBZ256rr:
20092 case VPACKUSWBZ256rrk:
20093 case VPACKUSWBZ256rrkz:
20094 case VPACKUSWBZrm:
20095 case VPACKUSWBZrmk:
20096 case VPACKUSWBZrmkz:
20097 case VPACKUSWBZrr:
20098 case VPACKUSWBZrrk:
20099 case VPACKUSWBZrrkz:
20100 case VPACKUSWBrm:
20101 case VPACKUSWBrr:
20102 return true;
20103 }
20104 return false;
20105}
20106
20107bool isVRSQRT28SS(unsigned Opcode) {
20108 switch (Opcode) {
20109 case VRSQRT28SSZm:
20110 case VRSQRT28SSZmk:
20111 case VRSQRT28SSZmkz:
20112 case VRSQRT28SSZr:
20113 case VRSQRT28SSZrb:
20114 case VRSQRT28SSZrbk:
20115 case VRSQRT28SSZrbkz:
20116 case VRSQRT28SSZrk:
20117 case VRSQRT28SSZrkz:
20118 return true;
20119 }
20120 return false;
20121}
20122
20123bool isGETSEC(unsigned Opcode) {
20124 return Opcode == GETSEC;
20125}
20126
20127bool isVEXTRACTF64X4(unsigned Opcode) {
20128 switch (Opcode) {
20129 case VEXTRACTF64X4Zmri:
20130 case VEXTRACTF64X4Zmrik:
20131 case VEXTRACTF64X4Zrri:
20132 case VEXTRACTF64X4Zrrik:
20133 case VEXTRACTF64X4Zrrikz:
20134 return true;
20135 }
20136 return false;
20137}
20138
20139bool isVPHSUBBW(unsigned Opcode) {
20140 switch (Opcode) {
20141 case VPHSUBBWrm:
20142 case VPHSUBBWrr:
20143 return true;
20144 }
20145 return false;
20146}
20147
20148bool isBLSR(unsigned Opcode) {
20149 switch (Opcode) {
20150 case BLSR32rm:
20151 case BLSR32rm_EVEX:
20152 case BLSR32rm_NF:
20153 case BLSR32rr:
20154 case BLSR32rr_EVEX:
20155 case BLSR32rr_NF:
20156 case BLSR64rm:
20157 case BLSR64rm_EVEX:
20158 case BLSR64rm_NF:
20159 case BLSR64rr:
20160 case BLSR64rr_EVEX:
20161 case BLSR64rr_NF:
20162 return true;
20163 }
20164 return false;
20165}
20166
20167bool isFILD(unsigned Opcode) {
20168 switch (Opcode) {
20169 case ILD_F16m:
20170 case ILD_F32m:
20171 case ILD_F64m:
20172 return true;
20173 }
20174 return false;
20175}
20176
20177bool isRETFQ(unsigned Opcode) {
20178 switch (Opcode) {
20179 case LRET64:
20180 case LRETI64:
20181 return true;
20182 }
20183 return false;
20184}
20185
20186bool isVADDSS(unsigned Opcode) {
20187 switch (Opcode) {
20188 case VADDSSZrm_Int:
20189 case VADDSSZrmk_Int:
20190 case VADDSSZrmkz_Int:
20191 case VADDSSZrr_Int:
20192 case VADDSSZrrb_Int:
20193 case VADDSSZrrbk_Int:
20194 case VADDSSZrrbkz_Int:
20195 case VADDSSZrrk_Int:
20196 case VADDSSZrrkz_Int:
20197 case VADDSSrm_Int:
20198 case VADDSSrr_Int:
20199 return true;
20200 }
20201 return false;
20202}
20203
20204bool isCOMISS(unsigned Opcode) {
20205 switch (Opcode) {
20206 case COMISSrm:
20207 case COMISSrr:
20208 return true;
20209 }
20210 return false;
20211}
20212
20213bool isCLI(unsigned Opcode) {
20214 return Opcode == CLI;
20215}
20216
20217bool isVERW(unsigned Opcode) {
20218 switch (Opcode) {
20219 case VERWm:
20220 case VERWr:
20221 return true;
20222 }
20223 return false;
20224}
20225
20226bool isBTC(unsigned Opcode) {
20227 switch (Opcode) {
20228 case BTC16mi8:
20229 case BTC16mr:
20230 case BTC16ri8:
20231 case BTC16rr:
20232 case BTC32mi8:
20233 case BTC32mr:
20234 case BTC32ri8:
20235 case BTC32rr:
20236 case BTC64mi8:
20237 case BTC64mr:
20238 case BTC64ri8:
20239 case BTC64rr:
20240 return true;
20241 }
20242 return false;
20243}
20244
20245bool isVPHADDUBQ(unsigned Opcode) {
20246 switch (Opcode) {
20247 case VPHADDUBQrm:
20248 case VPHADDUBQrr:
20249 return true;
20250 }
20251 return false;
20252}
20253
20254bool isVPORQ(unsigned Opcode) {
20255 switch (Opcode) {
20256 case VPORQZ128rm:
20257 case VPORQZ128rmb:
20258 case VPORQZ128rmbk:
20259 case VPORQZ128rmbkz:
20260 case VPORQZ128rmk:
20261 case VPORQZ128rmkz:
20262 case VPORQZ128rr:
20263 case VPORQZ128rrk:
20264 case VPORQZ128rrkz:
20265 case VPORQZ256rm:
20266 case VPORQZ256rmb:
20267 case VPORQZ256rmbk:
20268 case VPORQZ256rmbkz:
20269 case VPORQZ256rmk:
20270 case VPORQZ256rmkz:
20271 case VPORQZ256rr:
20272 case VPORQZ256rrk:
20273 case VPORQZ256rrkz:
20274 case VPORQZrm:
20275 case VPORQZrmb:
20276 case VPORQZrmbk:
20277 case VPORQZrmbkz:
20278 case VPORQZrmk:
20279 case VPORQZrmkz:
20280 case VPORQZrr:
20281 case VPORQZrrk:
20282 case VPORQZrrkz:
20283 return true;
20284 }
20285 return false;
20286}
20287
20288bool isORPD(unsigned Opcode) {
20289 switch (Opcode) {
20290 case ORPDrm:
20291 case ORPDrr:
20292 return true;
20293 }
20294 return false;
20295}
20296
20297bool isVMOVSS(unsigned Opcode) {
20298 switch (Opcode) {
20299 case VMOVSSZmr:
20300 case VMOVSSZmrk:
20301 case VMOVSSZrm:
20302 case VMOVSSZrmk:
20303 case VMOVSSZrmkz:
20304 case VMOVSSZrr:
20305 case VMOVSSZrr_REV:
20306 case VMOVSSZrrk:
20307 case VMOVSSZrrk_REV:
20308 case VMOVSSZrrkz:
20309 case VMOVSSZrrkz_REV:
20310 case VMOVSSmr:
20311 case VMOVSSrm:
20312 case VMOVSSrr:
20313 case VMOVSSrr_REV:
20314 return true;
20315 }
20316 return false;
20317}
20318
20319bool isVPSUBD(unsigned Opcode) {
20320 switch (Opcode) {
20321 case VPSUBDYrm:
20322 case VPSUBDYrr:
20323 case VPSUBDZ128rm:
20324 case VPSUBDZ128rmb:
20325 case VPSUBDZ128rmbk:
20326 case VPSUBDZ128rmbkz:
20327 case VPSUBDZ128rmk:
20328 case VPSUBDZ128rmkz:
20329 case VPSUBDZ128rr:
20330 case VPSUBDZ128rrk:
20331 case VPSUBDZ128rrkz:
20332 case VPSUBDZ256rm:
20333 case VPSUBDZ256rmb:
20334 case VPSUBDZ256rmbk:
20335 case VPSUBDZ256rmbkz:
20336 case VPSUBDZ256rmk:
20337 case VPSUBDZ256rmkz:
20338 case VPSUBDZ256rr:
20339 case VPSUBDZ256rrk:
20340 case VPSUBDZ256rrkz:
20341 case VPSUBDZrm:
20342 case VPSUBDZrmb:
20343 case VPSUBDZrmbk:
20344 case VPSUBDZrmbkz:
20345 case VPSUBDZrmk:
20346 case VPSUBDZrmkz:
20347 case VPSUBDZrr:
20348 case VPSUBDZrrk:
20349 case VPSUBDZrrkz:
20350 case VPSUBDrm:
20351 case VPSUBDrr:
20352 return true;
20353 }
20354 return false;
20355}
20356
20357bool isVGATHERPF1QPD(unsigned Opcode) {
20358 return Opcode == VGATHERPF1QPDm;
20359}
20360
20361bool isENCODEKEY256(unsigned Opcode) {
20362 return Opcode == ENCODEKEY256;
20363}
20364
20365bool isGF2P8AFFINEINVQB(unsigned Opcode) {
20366 switch (Opcode) {
20367 case GF2P8AFFINEINVQBrmi:
20368 case GF2P8AFFINEINVQBrri:
20369 return true;
20370 }
20371 return false;
20372}
20373
20374bool isXRSTOR64(unsigned Opcode) {
20375 return Opcode == XRSTOR64;
20376}
20377
20378bool isKANDW(unsigned Opcode) {
20379 return Opcode == KANDWkk;
20380}
20381
20382bool isLODSQ(unsigned Opcode) {
20383 return Opcode == LODSQ;
20384}
20385
20386bool isVMOVRSW(unsigned Opcode) {
20387 switch (Opcode) {
20388 case VMOVRSWZ128m:
20389 case VMOVRSWZ128mk:
20390 case VMOVRSWZ128mkz:
20391 case VMOVRSWZ256m:
20392 case VMOVRSWZ256mk:
20393 case VMOVRSWZ256mkz:
20394 case VMOVRSWZm:
20395 case VMOVRSWZmk:
20396 case VMOVRSWZmkz:
20397 return true;
20398 }
20399 return false;
20400}
20401
20402bool isVSUBSH(unsigned Opcode) {
20403 switch (Opcode) {
20404 case VSUBSHZrm_Int:
20405 case VSUBSHZrmk_Int:
20406 case VSUBSHZrmkz_Int:
20407 case VSUBSHZrr_Int:
20408 case VSUBSHZrrb_Int:
20409 case VSUBSHZrrbk_Int:
20410 case VSUBSHZrrbkz_Int:
20411 case VSUBSHZrrk_Int:
20412 case VSUBSHZrrkz_Int:
20413 return true;
20414 }
20415 return false;
20416}
20417
20418bool isLSS(unsigned Opcode) {
20419 switch (Opcode) {
20420 case LSS16rm:
20421 case LSS32rm:
20422 case LSS64rm:
20423 return true;
20424 }
20425 return false;
20426}
20427
20428bool isPMOVSXBQ(unsigned Opcode) {
20429 switch (Opcode) {
20430 case PMOVSXBQrm:
20431 case PMOVSXBQrr:
20432 return true;
20433 }
20434 return false;
20435}
20436
20437bool isVCVTTSD2SIS(unsigned Opcode) {
20438 switch (Opcode) {
20439 case VCVTTSD2SI64Srm_Int:
20440 case VCVTTSD2SI64Srr_Int:
20441 case VCVTTSD2SI64Srrb_Int:
20442 case VCVTTSD2SISrm_Int:
20443 case VCVTTSD2SISrr_Int:
20444 case VCVTTSD2SISrrb_Int:
20445 return true;
20446 }
20447 return false;
20448}
20449
20450bool isVCMPSH(unsigned Opcode) {
20451 switch (Opcode) {
20452 case VCMPSHZrmi_Int:
20453 case VCMPSHZrmik_Int:
20454 case VCMPSHZrri_Int:
20455 case VCMPSHZrrib_Int:
20456 case VCMPSHZrribk_Int:
20457 case VCMPSHZrrik_Int:
20458 return true;
20459 }
20460 return false;
20461}
20462
20463bool isVFMADD132PS(unsigned Opcode) {
20464 switch (Opcode) {
20465 case VFMADD132PSYm:
20466 case VFMADD132PSYr:
20467 case VFMADD132PSZ128m:
20468 case VFMADD132PSZ128mb:
20469 case VFMADD132PSZ128mbk:
20470 case VFMADD132PSZ128mbkz:
20471 case VFMADD132PSZ128mk:
20472 case VFMADD132PSZ128mkz:
20473 case VFMADD132PSZ128r:
20474 case VFMADD132PSZ128rk:
20475 case VFMADD132PSZ128rkz:
20476 case VFMADD132PSZ256m:
20477 case VFMADD132PSZ256mb:
20478 case VFMADD132PSZ256mbk:
20479 case VFMADD132PSZ256mbkz:
20480 case VFMADD132PSZ256mk:
20481 case VFMADD132PSZ256mkz:
20482 case VFMADD132PSZ256r:
20483 case VFMADD132PSZ256rk:
20484 case VFMADD132PSZ256rkz:
20485 case VFMADD132PSZm:
20486 case VFMADD132PSZmb:
20487 case VFMADD132PSZmbk:
20488 case VFMADD132PSZmbkz:
20489 case VFMADD132PSZmk:
20490 case VFMADD132PSZmkz:
20491 case VFMADD132PSZr:
20492 case VFMADD132PSZrb:
20493 case VFMADD132PSZrbk:
20494 case VFMADD132PSZrbkz:
20495 case VFMADD132PSZrk:
20496 case VFMADD132PSZrkz:
20497 case VFMADD132PSm:
20498 case VFMADD132PSr:
20499 return true;
20500 }
20501 return false;
20502}
20503
20504bool isVPACKSSWB(unsigned Opcode) {
20505 switch (Opcode) {
20506 case VPACKSSWBYrm:
20507 case VPACKSSWBYrr:
20508 case VPACKSSWBZ128rm:
20509 case VPACKSSWBZ128rmk:
20510 case VPACKSSWBZ128rmkz:
20511 case VPACKSSWBZ128rr:
20512 case VPACKSSWBZ128rrk:
20513 case VPACKSSWBZ128rrkz:
20514 case VPACKSSWBZ256rm:
20515 case VPACKSSWBZ256rmk:
20516 case VPACKSSWBZ256rmkz:
20517 case VPACKSSWBZ256rr:
20518 case VPACKSSWBZ256rrk:
20519 case VPACKSSWBZ256rrkz:
20520 case VPACKSSWBZrm:
20521 case VPACKSSWBZrmk:
20522 case VPACKSSWBZrmkz:
20523 case VPACKSSWBZrr:
20524 case VPACKSSWBZrrk:
20525 case VPACKSSWBZrrkz:
20526 case VPACKSSWBrm:
20527 case VPACKSSWBrr:
20528 return true;
20529 }
20530 return false;
20531}
20532
20533bool isPCMPGTQ(unsigned Opcode) {
20534 switch (Opcode) {
20535 case PCMPGTQrm:
20536 case PCMPGTQrr:
20537 return true;
20538 }
20539 return false;
20540}
20541
20542bool isVFMADD132SH(unsigned Opcode) {
20543 switch (Opcode) {
20544 case VFMADD132SHZm_Int:
20545 case VFMADD132SHZmk_Int:
20546 case VFMADD132SHZmkz_Int:
20547 case VFMADD132SHZr_Int:
20548 case VFMADD132SHZrb_Int:
20549 case VFMADD132SHZrbk_Int:
20550 case VFMADD132SHZrbkz_Int:
20551 case VFMADD132SHZrk_Int:
20552 case VFMADD132SHZrkz_Int:
20553 return true;
20554 }
20555 return false;
20556}
20557
20558bool isVCVTUQQ2PH(unsigned Opcode) {
20559 switch (Opcode) {
20560 case VCVTUQQ2PHZ128rm:
20561 case VCVTUQQ2PHZ128rmb:
20562 case VCVTUQQ2PHZ128rmbk:
20563 case VCVTUQQ2PHZ128rmbkz:
20564 case VCVTUQQ2PHZ128rmk:
20565 case VCVTUQQ2PHZ128rmkz:
20566 case VCVTUQQ2PHZ128rr:
20567 case VCVTUQQ2PHZ128rrk:
20568 case VCVTUQQ2PHZ128rrkz:
20569 case VCVTUQQ2PHZ256rm:
20570 case VCVTUQQ2PHZ256rmb:
20571 case VCVTUQQ2PHZ256rmbk:
20572 case VCVTUQQ2PHZ256rmbkz:
20573 case VCVTUQQ2PHZ256rmk:
20574 case VCVTUQQ2PHZ256rmkz:
20575 case VCVTUQQ2PHZ256rr:
20576 case VCVTUQQ2PHZ256rrk:
20577 case VCVTUQQ2PHZ256rrkz:
20578 case VCVTUQQ2PHZrm:
20579 case VCVTUQQ2PHZrmb:
20580 case VCVTUQQ2PHZrmbk:
20581 case VCVTUQQ2PHZrmbkz:
20582 case VCVTUQQ2PHZrmk:
20583 case VCVTUQQ2PHZrmkz:
20584 case VCVTUQQ2PHZrr:
20585 case VCVTUQQ2PHZrrb:
20586 case VCVTUQQ2PHZrrbk:
20587 case VCVTUQQ2PHZrrbkz:
20588 case VCVTUQQ2PHZrrk:
20589 case VCVTUQQ2PHZrrkz:
20590 return true;
20591 }
20592 return false;
20593}
20594
20595bool isVCVTQQ2PS(unsigned Opcode) {
20596 switch (Opcode) {
20597 case VCVTQQ2PSZ128rm:
20598 case VCVTQQ2PSZ128rmb:
20599 case VCVTQQ2PSZ128rmbk:
20600 case VCVTQQ2PSZ128rmbkz:
20601 case VCVTQQ2PSZ128rmk:
20602 case VCVTQQ2PSZ128rmkz:
20603 case VCVTQQ2PSZ128rr:
20604 case VCVTQQ2PSZ128rrk:
20605 case VCVTQQ2PSZ128rrkz:
20606 case VCVTQQ2PSZ256rm:
20607 case VCVTQQ2PSZ256rmb:
20608 case VCVTQQ2PSZ256rmbk:
20609 case VCVTQQ2PSZ256rmbkz:
20610 case VCVTQQ2PSZ256rmk:
20611 case VCVTQQ2PSZ256rmkz:
20612 case VCVTQQ2PSZ256rr:
20613 case VCVTQQ2PSZ256rrk:
20614 case VCVTQQ2PSZ256rrkz:
20615 case VCVTQQ2PSZrm:
20616 case VCVTQQ2PSZrmb:
20617 case VCVTQQ2PSZrmbk:
20618 case VCVTQQ2PSZrmbkz:
20619 case VCVTQQ2PSZrmk:
20620 case VCVTQQ2PSZrmkz:
20621 case VCVTQQ2PSZrr:
20622 case VCVTQQ2PSZrrb:
20623 case VCVTQQ2PSZrrbk:
20624 case VCVTQQ2PSZrrbkz:
20625 case VCVTQQ2PSZrrk:
20626 case VCVTQQ2PSZrrkz:
20627 return true;
20628 }
20629 return false;
20630}
20631
20632bool isVCVTTSS2USI(unsigned Opcode) {
20633 switch (Opcode) {
20634 case VCVTTSS2USI64Zrm_Int:
20635 case VCVTTSS2USI64Zrr_Int:
20636 case VCVTTSS2USI64Zrrb_Int:
20637 case VCVTTSS2USIZrm_Int:
20638 case VCVTTSS2USIZrr_Int:
20639 case VCVTTSS2USIZrrb_Int:
20640 return true;
20641 }
20642 return false;
20643}
20644
20645bool isVPMOVM2Q(unsigned Opcode) {
20646 switch (Opcode) {
20647 case VPMOVM2QZ128rk:
20648 case VPMOVM2QZ256rk:
20649 case VPMOVM2QZrk:
20650 return true;
20651 }
20652 return false;
20653}
20654
20655bool isVMOVD(unsigned Opcode) {
20656 switch (Opcode) {
20657 case VMOVDI2PDIZrm:
20658 case VMOVDI2PDIZrr:
20659 case VMOVDI2PDIrm:
20660 case VMOVDI2PDIrr:
20661 case VMOVPDI2DIZmr:
20662 case VMOVPDI2DIZrr:
20663 case VMOVPDI2DImr:
20664 case VMOVPDI2DIrr:
20665 case VMOVZPDILo2PDIZmr:
20666 case VMOVZPDILo2PDIZrm:
20667 case VMOVZPDILo2PDIZrr:
20668 case VMOVZPDILo2PDIZrr2:
20669 return true;
20670 }
20671 return false;
20672}
20673
20674bool isVCVTTPS2QQS(unsigned Opcode) {
20675 switch (Opcode) {
20676 case VCVTTPS2QQSZ128rm:
20677 case VCVTTPS2QQSZ128rmb:
20678 case VCVTTPS2QQSZ128rmbk:
20679 case VCVTTPS2QQSZ128rmbkz:
20680 case VCVTTPS2QQSZ128rmk:
20681 case VCVTTPS2QQSZ128rmkz:
20682 case VCVTTPS2QQSZ128rr:
20683 case VCVTTPS2QQSZ128rrk:
20684 case VCVTTPS2QQSZ128rrkz:
20685 case VCVTTPS2QQSZ256rm:
20686 case VCVTTPS2QQSZ256rmb:
20687 case VCVTTPS2QQSZ256rmbk:
20688 case VCVTTPS2QQSZ256rmbkz:
20689 case VCVTTPS2QQSZ256rmk:
20690 case VCVTTPS2QQSZ256rmkz:
20691 case VCVTTPS2QQSZ256rr:
20692 case VCVTTPS2QQSZ256rrb:
20693 case VCVTTPS2QQSZ256rrbk:
20694 case VCVTTPS2QQSZ256rrbkz:
20695 case VCVTTPS2QQSZ256rrk:
20696 case VCVTTPS2QQSZ256rrkz:
20697 case VCVTTPS2QQSZrm:
20698 case VCVTTPS2QQSZrmb:
20699 case VCVTTPS2QQSZrmbk:
20700 case VCVTTPS2QQSZrmbkz:
20701 case VCVTTPS2QQSZrmk:
20702 case VCVTTPS2QQSZrmkz:
20703 case VCVTTPS2QQSZrr:
20704 case VCVTTPS2QQSZrrb:
20705 case VCVTTPS2QQSZrrbk:
20706 case VCVTTPS2QQSZrrbkz:
20707 case VCVTTPS2QQSZrrk:
20708 case VCVTTPS2QQSZrrkz:
20709 return true;
20710 }
20711 return false;
20712}
20713
20714bool isVSQRTBF16(unsigned Opcode) {
20715 switch (Opcode) {
20716 case VSQRTBF16Z128m:
20717 case VSQRTBF16Z128mb:
20718 case VSQRTBF16Z128mbk:
20719 case VSQRTBF16Z128mbkz:
20720 case VSQRTBF16Z128mk:
20721 case VSQRTBF16Z128mkz:
20722 case VSQRTBF16Z128r:
20723 case VSQRTBF16Z128rk:
20724 case VSQRTBF16Z128rkz:
20725 case VSQRTBF16Z256m:
20726 case VSQRTBF16Z256mb:
20727 case VSQRTBF16Z256mbk:
20728 case VSQRTBF16Z256mbkz:
20729 case VSQRTBF16Z256mk:
20730 case VSQRTBF16Z256mkz:
20731 case VSQRTBF16Z256r:
20732 case VSQRTBF16Z256rk:
20733 case VSQRTBF16Z256rkz:
20734 case VSQRTBF16Zm:
20735 case VSQRTBF16Zmb:
20736 case VSQRTBF16Zmbk:
20737 case VSQRTBF16Zmbkz:
20738 case VSQRTBF16Zmk:
20739 case VSQRTBF16Zmkz:
20740 case VSQRTBF16Zr:
20741 case VSQRTBF16Zrk:
20742 case VSQRTBF16Zrkz:
20743 return true;
20744 }
20745 return false;
20746}
20747
20748bool isVFPCLASSPH(unsigned Opcode) {
20749 switch (Opcode) {
20750 case VFPCLASSPHZ128mbi:
20751 case VFPCLASSPHZ128mbik:
20752 case VFPCLASSPHZ128mi:
20753 case VFPCLASSPHZ128mik:
20754 case VFPCLASSPHZ128ri:
20755 case VFPCLASSPHZ128rik:
20756 case VFPCLASSPHZ256mbi:
20757 case VFPCLASSPHZ256mbik:
20758 case VFPCLASSPHZ256mi:
20759 case VFPCLASSPHZ256mik:
20760 case VFPCLASSPHZ256ri:
20761 case VFPCLASSPHZ256rik:
20762 case VFPCLASSPHZmbi:
20763 case VFPCLASSPHZmbik:
20764 case VFPCLASSPHZmi:
20765 case VFPCLASSPHZmik:
20766 case VFPCLASSPHZri:
20767 case VFPCLASSPHZrik:
20768 return true;
20769 }
20770 return false;
20771}
20772
20773bool isVCVTSS2SH(unsigned Opcode) {
20774 switch (Opcode) {
20775 case VCVTSS2SHZrm_Int:
20776 case VCVTSS2SHZrmk_Int:
20777 case VCVTSS2SHZrmkz_Int:
20778 case VCVTSS2SHZrr_Int:
20779 case VCVTSS2SHZrrb_Int:
20780 case VCVTSS2SHZrrbk_Int:
20781 case VCVTSS2SHZrrbkz_Int:
20782 case VCVTSS2SHZrrk_Int:
20783 case VCVTSS2SHZrrkz_Int:
20784 return true;
20785 }
20786 return false;
20787}
20788
20789bool isSCASB(unsigned Opcode) {
20790 return Opcode == SCASB;
20791}
20792
20793bool isPSRLD(unsigned Opcode) {
20794 switch (Opcode) {
20795 case MMX_PSRLDri:
20796 case MMX_PSRLDrm:
20797 case MMX_PSRLDrr:
20798 case PSRLDri:
20799 case PSRLDrm:
20800 case PSRLDrr:
20801 return true;
20802 }
20803 return false;
20804}
20805
20806bool isVADDPH(unsigned Opcode) {
20807 switch (Opcode) {
20808 case VADDPHZ128rm:
20809 case VADDPHZ128rmb:
20810 case VADDPHZ128rmbk:
20811 case VADDPHZ128rmbkz:
20812 case VADDPHZ128rmk:
20813 case VADDPHZ128rmkz:
20814 case VADDPHZ128rr:
20815 case VADDPHZ128rrk:
20816 case VADDPHZ128rrkz:
20817 case VADDPHZ256rm:
20818 case VADDPHZ256rmb:
20819 case VADDPHZ256rmbk:
20820 case VADDPHZ256rmbkz:
20821 case VADDPHZ256rmk:
20822 case VADDPHZ256rmkz:
20823 case VADDPHZ256rr:
20824 case VADDPHZ256rrk:
20825 case VADDPHZ256rrkz:
20826 case VADDPHZrm:
20827 case VADDPHZrmb:
20828 case VADDPHZrmbk:
20829 case VADDPHZrmbkz:
20830 case VADDPHZrmk:
20831 case VADDPHZrmkz:
20832 case VADDPHZrr:
20833 case VADDPHZrrb:
20834 case VADDPHZrrbk:
20835 case VADDPHZrrbkz:
20836 case VADDPHZrrk:
20837 case VADDPHZrrkz:
20838 return true;
20839 }
20840 return false;
20841}
20842
20843bool isFSUB(unsigned Opcode) {
20844 switch (Opcode) {
20845 case SUB_F32m:
20846 case SUB_F64m:
20847 case SUB_FST0r:
20848 case SUB_FrST0:
20849 return true;
20850 }
20851 return false;
20852}
20853
20854bool isVCVTTPH2IBS(unsigned Opcode) {
20855 switch (Opcode) {
20856 case VCVTTPH2IBSZ128rm:
20857 case VCVTTPH2IBSZ128rmb:
20858 case VCVTTPH2IBSZ128rmbk:
20859 case VCVTTPH2IBSZ128rmbkz:
20860 case VCVTTPH2IBSZ128rmk:
20861 case VCVTTPH2IBSZ128rmkz:
20862 case VCVTTPH2IBSZ128rr:
20863 case VCVTTPH2IBSZ128rrk:
20864 case VCVTTPH2IBSZ128rrkz:
20865 case VCVTTPH2IBSZ256rm:
20866 case VCVTTPH2IBSZ256rmb:
20867 case VCVTTPH2IBSZ256rmbk:
20868 case VCVTTPH2IBSZ256rmbkz:
20869 case VCVTTPH2IBSZ256rmk:
20870 case VCVTTPH2IBSZ256rmkz:
20871 case VCVTTPH2IBSZ256rr:
20872 case VCVTTPH2IBSZ256rrk:
20873 case VCVTTPH2IBSZ256rrkz:
20874 case VCVTTPH2IBSZrm:
20875 case VCVTTPH2IBSZrmb:
20876 case VCVTTPH2IBSZrmbk:
20877 case VCVTTPH2IBSZrmbkz:
20878 case VCVTTPH2IBSZrmk:
20879 case VCVTTPH2IBSZrmkz:
20880 case VCVTTPH2IBSZrr:
20881 case VCVTTPH2IBSZrrb:
20882 case VCVTTPH2IBSZrrbk:
20883 case VCVTTPH2IBSZrrbkz:
20884 case VCVTTPH2IBSZrrk:
20885 case VCVTTPH2IBSZrrkz:
20886 return true;
20887 }
20888 return false;
20889}
20890
20891bool isVEXTRACTI64X2(unsigned Opcode) {
20892 switch (Opcode) {
20893 case VEXTRACTI64X2Z256mri:
20894 case VEXTRACTI64X2Z256mrik:
20895 case VEXTRACTI64X2Z256rri:
20896 case VEXTRACTI64X2Z256rrik:
20897 case VEXTRACTI64X2Z256rrikz:
20898 case VEXTRACTI64X2Zmri:
20899 case VEXTRACTI64X2Zmrik:
20900 case VEXTRACTI64X2Zrri:
20901 case VEXTRACTI64X2Zrrik:
20902 case VEXTRACTI64X2Zrrikz:
20903 return true;
20904 }
20905 return false;
20906}
20907
20908bool isPMINUW(unsigned Opcode) {
20909 switch (Opcode) {
20910 case PMINUWrm:
20911 case PMINUWrr:
20912 return true;
20913 }
20914 return false;
20915}
20916
20917bool isPSUBSB(unsigned Opcode) {
20918 switch (Opcode) {
20919 case MMX_PSUBSBrm:
20920 case MMX_PSUBSBrr:
20921 case PSUBSBrm:
20922 case PSUBSBrr:
20923 return true;
20924 }
20925 return false;
20926}
20927
20928bool isVCVT2PS2PHX(unsigned Opcode) {
20929 switch (Opcode) {
20930 case VCVT2PS2PHXZ128rm:
20931 case VCVT2PS2PHXZ128rmb:
20932 case VCVT2PS2PHXZ128rmbk:
20933 case VCVT2PS2PHXZ128rmbkz:
20934 case VCVT2PS2PHXZ128rmk:
20935 case VCVT2PS2PHXZ128rmkz:
20936 case VCVT2PS2PHXZ128rr:
20937 case VCVT2PS2PHXZ128rrk:
20938 case VCVT2PS2PHXZ128rrkz:
20939 case VCVT2PS2PHXZ256rm:
20940 case VCVT2PS2PHXZ256rmb:
20941 case VCVT2PS2PHXZ256rmbk:
20942 case VCVT2PS2PHXZ256rmbkz:
20943 case VCVT2PS2PHXZ256rmk:
20944 case VCVT2PS2PHXZ256rmkz:
20945 case VCVT2PS2PHXZ256rr:
20946 case VCVT2PS2PHXZ256rrk:
20947 case VCVT2PS2PHXZ256rrkz:
20948 case VCVT2PS2PHXZrm:
20949 case VCVT2PS2PHXZrmb:
20950 case VCVT2PS2PHXZrmbk:
20951 case VCVT2PS2PHXZrmbkz:
20952 case VCVT2PS2PHXZrmk:
20953 case VCVT2PS2PHXZrmkz:
20954 case VCVT2PS2PHXZrr:
20955 case VCVT2PS2PHXZrrb:
20956 case VCVT2PS2PHXZrrbk:
20957 case VCVT2PS2PHXZrrbkz:
20958 case VCVT2PS2PHXZrrk:
20959 case VCVT2PS2PHXZrrkz:
20960 return true;
20961 }
20962 return false;
20963}
20964
20965bool isVPCMPEQD(unsigned Opcode) {
20966 switch (Opcode) {
20967 case VPCMPEQDYrm:
20968 case VPCMPEQDYrr:
20969 case VPCMPEQDZ128rm:
20970 case VPCMPEQDZ128rmb:
20971 case VPCMPEQDZ128rmbk:
20972 case VPCMPEQDZ128rmk:
20973 case VPCMPEQDZ128rr:
20974 case VPCMPEQDZ128rrk:
20975 case VPCMPEQDZ256rm:
20976 case VPCMPEQDZ256rmb:
20977 case VPCMPEQDZ256rmbk:
20978 case VPCMPEQDZ256rmk:
20979 case VPCMPEQDZ256rr:
20980 case VPCMPEQDZ256rrk:
20981 case VPCMPEQDZrm:
20982 case VPCMPEQDZrmb:
20983 case VPCMPEQDZrmbk:
20984 case VPCMPEQDZrmk:
20985 case VPCMPEQDZrr:
20986 case VPCMPEQDZrrk:
20987 case VPCMPEQDrm:
20988 case VPCMPEQDrr:
20989 return true;
20990 }
20991 return false;
20992}
20993
20994bool isVPSCATTERQD(unsigned Opcode) {
20995 switch (Opcode) {
20996 case VPSCATTERQDZ128mr:
20997 case VPSCATTERQDZ256mr:
20998 case VPSCATTERQDZmr:
20999 return true;
21000 }
21001 return false;
21002}
21003
21004bool isVPSHLDD(unsigned Opcode) {
21005 switch (Opcode) {
21006 case VPSHLDDZ128rmbi:
21007 case VPSHLDDZ128rmbik:
21008 case VPSHLDDZ128rmbikz:
21009 case VPSHLDDZ128rmi:
21010 case VPSHLDDZ128rmik:
21011 case VPSHLDDZ128rmikz:
21012 case VPSHLDDZ128rri:
21013 case VPSHLDDZ128rrik:
21014 case VPSHLDDZ128rrikz:
21015 case VPSHLDDZ256rmbi:
21016 case VPSHLDDZ256rmbik:
21017 case VPSHLDDZ256rmbikz:
21018 case VPSHLDDZ256rmi:
21019 case VPSHLDDZ256rmik:
21020 case VPSHLDDZ256rmikz:
21021 case VPSHLDDZ256rri:
21022 case VPSHLDDZ256rrik:
21023 case VPSHLDDZ256rrikz:
21024 case VPSHLDDZrmbi:
21025 case VPSHLDDZrmbik:
21026 case VPSHLDDZrmbikz:
21027 case VPSHLDDZrmi:
21028 case VPSHLDDZrmik:
21029 case VPSHLDDZrmikz:
21030 case VPSHLDDZrri:
21031 case VPSHLDDZrrik:
21032 case VPSHLDDZrrikz:
21033 return true;
21034 }
21035 return false;
21036}
21037
21038bool isKXNORB(unsigned Opcode) {
21039 return Opcode == KXNORBkk;
21040}
21041
21042bool isLDDQU(unsigned Opcode) {
21043 return Opcode == LDDQUrm;
21044}
21045
21046bool isMASKMOVQ(unsigned Opcode) {
21047 switch (Opcode) {
21048 case MMX_MASKMOVQ:
21049 case MMX_MASKMOVQ64:
21050 return true;
21051 }
21052 return false;
21053}
21054
21055bool isPABSW(unsigned Opcode) {
21056 switch (Opcode) {
21057 case MMX_PABSWrm:
21058 case MMX_PABSWrr:
21059 case PABSWrm:
21060 case PABSWrr:
21061 return true;
21062 }
21063 return false;
21064}
21065
21066bool isVPROLD(unsigned Opcode) {
21067 switch (Opcode) {
21068 case VPROLDZ128mbi:
21069 case VPROLDZ128mbik:
21070 case VPROLDZ128mbikz:
21071 case VPROLDZ128mi:
21072 case VPROLDZ128mik:
21073 case VPROLDZ128mikz:
21074 case VPROLDZ128ri:
21075 case VPROLDZ128rik:
21076 case VPROLDZ128rikz:
21077 case VPROLDZ256mbi:
21078 case VPROLDZ256mbik:
21079 case VPROLDZ256mbikz:
21080 case VPROLDZ256mi:
21081 case VPROLDZ256mik:
21082 case VPROLDZ256mikz:
21083 case VPROLDZ256ri:
21084 case VPROLDZ256rik:
21085 case VPROLDZ256rikz:
21086 case VPROLDZmbi:
21087 case VPROLDZmbik:
21088 case VPROLDZmbikz:
21089 case VPROLDZmi:
21090 case VPROLDZmik:
21091 case VPROLDZmikz:
21092 case VPROLDZri:
21093 case VPROLDZrik:
21094 case VPROLDZrikz:
21095 return true;
21096 }
21097 return false;
21098}
21099
21100bool isVPCOMQ(unsigned Opcode) {
21101 switch (Opcode) {
21102 case VPCOMQmi:
21103 case VPCOMQri:
21104 return true;
21105 }
21106 return false;
21107}
21108
21109bool isVSCATTERDPD(unsigned Opcode) {
21110 switch (Opcode) {
21111 case VSCATTERDPDZ128mr:
21112 case VSCATTERDPDZ256mr:
21113 case VSCATTERDPDZmr:
21114 return true;
21115 }
21116 return false;
21117}
21118
21119bool isFXRSTOR(unsigned Opcode) {
21120 return Opcode == FXRSTOR;
21121}
21122
21123bool isVPCMPUW(unsigned Opcode) {
21124 switch (Opcode) {
21125 case VPCMPUWZ128rmi:
21126 case VPCMPUWZ128rmik:
21127 case VPCMPUWZ128rri:
21128 case VPCMPUWZ128rrik:
21129 case VPCMPUWZ256rmi:
21130 case VPCMPUWZ256rmik:
21131 case VPCMPUWZ256rri:
21132 case VPCMPUWZ256rrik:
21133 case VPCMPUWZrmi:
21134 case VPCMPUWZrmik:
21135 case VPCMPUWZrri:
21136 case VPCMPUWZrrik:
21137 return true;
21138 }
21139 return false;
21140}
21141
21142bool isWBINVD(unsigned Opcode) {
21143 return Opcode == WBINVD;
21144}
21145
21146bool isVCVTTPD2UDQ(unsigned Opcode) {
21147 switch (Opcode) {
21148 case VCVTTPD2UDQZ128rm:
21149 case VCVTTPD2UDQZ128rmb:
21150 case VCVTTPD2UDQZ128rmbk:
21151 case VCVTTPD2UDQZ128rmbkz:
21152 case VCVTTPD2UDQZ128rmk:
21153 case VCVTTPD2UDQZ128rmkz:
21154 case VCVTTPD2UDQZ128rr:
21155 case VCVTTPD2UDQZ128rrk:
21156 case VCVTTPD2UDQZ128rrkz:
21157 case VCVTTPD2UDQZ256rm:
21158 case VCVTTPD2UDQZ256rmb:
21159 case VCVTTPD2UDQZ256rmbk:
21160 case VCVTTPD2UDQZ256rmbkz:
21161 case VCVTTPD2UDQZ256rmk:
21162 case VCVTTPD2UDQZ256rmkz:
21163 case VCVTTPD2UDQZ256rr:
21164 case VCVTTPD2UDQZ256rrk:
21165 case VCVTTPD2UDQZ256rrkz:
21166 case VCVTTPD2UDQZrm:
21167 case VCVTTPD2UDQZrmb:
21168 case VCVTTPD2UDQZrmbk:
21169 case VCVTTPD2UDQZrmbkz:
21170 case VCVTTPD2UDQZrmk:
21171 case VCVTTPD2UDQZrmkz:
21172 case VCVTTPD2UDQZrr:
21173 case VCVTTPD2UDQZrrb:
21174 case VCVTTPD2UDQZrrbk:
21175 case VCVTTPD2UDQZrrbkz:
21176 case VCVTTPD2UDQZrrk:
21177 case VCVTTPD2UDQZrrkz:
21178 return true;
21179 }
21180 return false;
21181}
21182
21183bool isERETU(unsigned Opcode) {
21184 return Opcode == ERETU;
21185}
21186
21187bool isPFRCPIT2(unsigned Opcode) {
21188 switch (Opcode) {
21189 case PFRCPIT2rm:
21190 case PFRCPIT2rr:
21191 return true;
21192 }
21193 return false;
21194}
21195
21196bool isTTCMMRLFP16PS(unsigned Opcode) {
21197 return Opcode == TTCMMRLFP16PS;
21198}
21199
21200bool isVPERMT2W(unsigned Opcode) {
21201 switch (Opcode) {
21202 case VPERMT2WZ128rm:
21203 case VPERMT2WZ128rmk:
21204 case VPERMT2WZ128rmkz:
21205 case VPERMT2WZ128rr:
21206 case VPERMT2WZ128rrk:
21207 case VPERMT2WZ128rrkz:
21208 case VPERMT2WZ256rm:
21209 case VPERMT2WZ256rmk:
21210 case VPERMT2WZ256rmkz:
21211 case VPERMT2WZ256rr:
21212 case VPERMT2WZ256rrk:
21213 case VPERMT2WZ256rrkz:
21214 case VPERMT2WZrm:
21215 case VPERMT2WZrmk:
21216 case VPERMT2WZrmkz:
21217 case VPERMT2WZrr:
21218 case VPERMT2WZrrk:
21219 case VPERMT2WZrrkz:
21220 return true;
21221 }
21222 return false;
21223}
21224
21225bool isVEXTRACTF32X4(unsigned Opcode) {
21226 switch (Opcode) {
21227 case VEXTRACTF32X4Z256mri:
21228 case VEXTRACTF32X4Z256mrik:
21229 case VEXTRACTF32X4Z256rri:
21230 case VEXTRACTF32X4Z256rrik:
21231 case VEXTRACTF32X4Z256rrikz:
21232 case VEXTRACTF32X4Zmri:
21233 case VEXTRACTF32X4Zmrik:
21234 case VEXTRACTF32X4Zrri:
21235 case VEXTRACTF32X4Zrrik:
21236 case VEXTRACTF32X4Zrrikz:
21237 return true;
21238 }
21239 return false;
21240}
21241
21242bool isVGATHERPF0DPD(unsigned Opcode) {
21243 return Opcode == VGATHERPF0DPDm;
21244}
21245
21246bool isVBROADCASTF32X2(unsigned Opcode) {
21247 switch (Opcode) {
21248 case VBROADCASTF32X2Z256rm:
21249 case VBROADCASTF32X2Z256rmk:
21250 case VBROADCASTF32X2Z256rmkz:
21251 case VBROADCASTF32X2Z256rr:
21252 case VBROADCASTF32X2Z256rrk:
21253 case VBROADCASTF32X2Z256rrkz:
21254 case VBROADCASTF32X2Zrm:
21255 case VBROADCASTF32X2Zrmk:
21256 case VBROADCASTF32X2Zrmkz:
21257 case VBROADCASTF32X2Zrr:
21258 case VBROADCASTF32X2Zrrk:
21259 case VBROADCASTF32X2Zrrkz:
21260 return true;
21261 }
21262 return false;
21263}
21264
21265bool isVRCP14SD(unsigned Opcode) {
21266 switch (Opcode) {
21267 case VRCP14SDZrm:
21268 case VRCP14SDZrmk:
21269 case VRCP14SDZrmkz:
21270 case VRCP14SDZrr:
21271 case VRCP14SDZrrk:
21272 case VRCP14SDZrrkz:
21273 return true;
21274 }
21275 return false;
21276}
21277
21278bool isPABSD(unsigned Opcode) {
21279 switch (Opcode) {
21280 case MMX_PABSDrm:
21281 case MMX_PABSDrr:
21282 case PABSDrm:
21283 case PABSDrr:
21284 return true;
21285 }
21286 return false;
21287}
21288
21289bool isLAHF(unsigned Opcode) {
21290 return Opcode == LAHF;
21291}
21292
21293bool isPINSRB(unsigned Opcode) {
21294 switch (Opcode) {
21295 case PINSRBrmi:
21296 case PINSRBrri:
21297 return true;
21298 }
21299 return false;
21300}
21301
21302bool isSKINIT(unsigned Opcode) {
21303 return Opcode == SKINIT;
21304}
21305
21306bool isENTER(unsigned Opcode) {
21307 return Opcode == ENTER;
21308}
21309
21310bool isVCVTSI2SS(unsigned Opcode) {
21311 switch (Opcode) {
21312 case VCVTSI2SSZrm_Int:
21313 case VCVTSI2SSZrr_Int:
21314 case VCVTSI2SSZrrb_Int:
21315 case VCVTSI2SSrm_Int:
21316 case VCVTSI2SSrr_Int:
21317 case VCVTSI642SSZrm_Int:
21318 case VCVTSI642SSZrr_Int:
21319 case VCVTSI642SSZrrb_Int:
21320 case VCVTSI642SSrm_Int:
21321 case VCVTSI642SSrr_Int:
21322 return true;
21323 }
21324 return false;
21325}
21326
21327bool isVFMADD231PD(unsigned Opcode) {
21328 switch (Opcode) {
21329 case VFMADD231PDYm:
21330 case VFMADD231PDYr:
21331 case VFMADD231PDZ128m:
21332 case VFMADD231PDZ128mb:
21333 case VFMADD231PDZ128mbk:
21334 case VFMADD231PDZ128mbkz:
21335 case VFMADD231PDZ128mk:
21336 case VFMADD231PDZ128mkz:
21337 case VFMADD231PDZ128r:
21338 case VFMADD231PDZ128rk:
21339 case VFMADD231PDZ128rkz:
21340 case VFMADD231PDZ256m:
21341 case VFMADD231PDZ256mb:
21342 case VFMADD231PDZ256mbk:
21343 case VFMADD231PDZ256mbkz:
21344 case VFMADD231PDZ256mk:
21345 case VFMADD231PDZ256mkz:
21346 case VFMADD231PDZ256r:
21347 case VFMADD231PDZ256rk:
21348 case VFMADD231PDZ256rkz:
21349 case VFMADD231PDZm:
21350 case VFMADD231PDZmb:
21351 case VFMADD231PDZmbk:
21352 case VFMADD231PDZmbkz:
21353 case VFMADD231PDZmk:
21354 case VFMADD231PDZmkz:
21355 case VFMADD231PDZr:
21356 case VFMADD231PDZrb:
21357 case VFMADD231PDZrbk:
21358 case VFMADD231PDZrbkz:
21359 case VFMADD231PDZrk:
21360 case VFMADD231PDZrkz:
21361 case VFMADD231PDm:
21362 case VFMADD231PDr:
21363 return true;
21364 }
21365 return false;
21366}
21367
21368bool isLOADIWKEY(unsigned Opcode) {
21369 return Opcode == LOADIWKEY;
21370}
21371
21372bool isVMOVNTDQA(unsigned Opcode) {
21373 switch (Opcode) {
21374 case VMOVNTDQAYrm:
21375 case VMOVNTDQAZ128rm:
21376 case VMOVNTDQAZ256rm:
21377 case VMOVNTDQAZrm:
21378 case VMOVNTDQArm:
21379 return true;
21380 }
21381 return false;
21382}
21383
21384bool isVPERMT2PS(unsigned Opcode) {
21385 switch (Opcode) {
21386 case VPERMT2PSZ128rm:
21387 case VPERMT2PSZ128rmb:
21388 case VPERMT2PSZ128rmbk:
21389 case VPERMT2PSZ128rmbkz:
21390 case VPERMT2PSZ128rmk:
21391 case VPERMT2PSZ128rmkz:
21392 case VPERMT2PSZ128rr:
21393 case VPERMT2PSZ128rrk:
21394 case VPERMT2PSZ128rrkz:
21395 case VPERMT2PSZ256rm:
21396 case VPERMT2PSZ256rmb:
21397 case VPERMT2PSZ256rmbk:
21398 case VPERMT2PSZ256rmbkz:
21399 case VPERMT2PSZ256rmk:
21400 case VPERMT2PSZ256rmkz:
21401 case VPERMT2PSZ256rr:
21402 case VPERMT2PSZ256rrk:
21403 case VPERMT2PSZ256rrkz:
21404 case VPERMT2PSZrm:
21405 case VPERMT2PSZrmb:
21406 case VPERMT2PSZrmbk:
21407 case VPERMT2PSZrmbkz:
21408 case VPERMT2PSZrmk:
21409 case VPERMT2PSZrmkz:
21410 case VPERMT2PSZrr:
21411 case VPERMT2PSZrrk:
21412 case VPERMT2PSZrrkz:
21413 return true;
21414 }
21415 return false;
21416}
21417
21418bool isPUSHF(unsigned Opcode) {
21419 return Opcode == PUSHF16;
21420}
21421
21422bool isMPSADBW(unsigned Opcode) {
21423 switch (Opcode) {
21424 case MPSADBWrmi:
21425 case MPSADBWrri:
21426 return true;
21427 }
21428 return false;
21429}
21430
21431bool isVMINMAXSH(unsigned Opcode) {
21432 switch (Opcode) {
21433 case VMINMAXSHrmi_Int:
21434 case VMINMAXSHrmik_Int:
21435 case VMINMAXSHrmikz_Int:
21436 case VMINMAXSHrri_Int:
21437 case VMINMAXSHrrib_Int:
21438 case VMINMAXSHrribk_Int:
21439 case VMINMAXSHrribkz_Int:
21440 case VMINMAXSHrrik_Int:
21441 case VMINMAXSHrrikz_Int:
21442 return true;
21443 }
21444 return false;
21445}
21446
21447bool isVRSQRT14SS(unsigned Opcode) {
21448 switch (Opcode) {
21449 case VRSQRT14SSZrm:
21450 case VRSQRT14SSZrmk:
21451 case VRSQRT14SSZrmkz:
21452 case VRSQRT14SSZrr:
21453 case VRSQRT14SSZrrk:
21454 case VRSQRT14SSZrrkz:
21455 return true;
21456 }
21457 return false;
21458}
21459
21460bool isVCVTDQ2PD(unsigned Opcode) {
21461 switch (Opcode) {
21462 case VCVTDQ2PDYrm:
21463 case VCVTDQ2PDYrr:
21464 case VCVTDQ2PDZ128rm:
21465 case VCVTDQ2PDZ128rmb:
21466 case VCVTDQ2PDZ128rmbk:
21467 case VCVTDQ2PDZ128rmbkz:
21468 case VCVTDQ2PDZ128rmk:
21469 case VCVTDQ2PDZ128rmkz:
21470 case VCVTDQ2PDZ128rr:
21471 case VCVTDQ2PDZ128rrk:
21472 case VCVTDQ2PDZ128rrkz:
21473 case VCVTDQ2PDZ256rm:
21474 case VCVTDQ2PDZ256rmb:
21475 case VCVTDQ2PDZ256rmbk:
21476 case VCVTDQ2PDZ256rmbkz:
21477 case VCVTDQ2PDZ256rmk:
21478 case VCVTDQ2PDZ256rmkz:
21479 case VCVTDQ2PDZ256rr:
21480 case VCVTDQ2PDZ256rrk:
21481 case VCVTDQ2PDZ256rrkz:
21482 case VCVTDQ2PDZrm:
21483 case VCVTDQ2PDZrmb:
21484 case VCVTDQ2PDZrmbk:
21485 case VCVTDQ2PDZrmbkz:
21486 case VCVTDQ2PDZrmk:
21487 case VCVTDQ2PDZrmkz:
21488 case VCVTDQ2PDZrr:
21489 case VCVTDQ2PDZrrk:
21490 case VCVTDQ2PDZrrkz:
21491 case VCVTDQ2PDrm:
21492 case VCVTDQ2PDrr:
21493 return true;
21494 }
21495 return false;
21496}
21497
21498bool isVORPS(unsigned Opcode) {
21499 switch (Opcode) {
21500 case VORPSYrm:
21501 case VORPSYrr:
21502 case VORPSZ128rm:
21503 case VORPSZ128rmb:
21504 case VORPSZ128rmbk:
21505 case VORPSZ128rmbkz:
21506 case VORPSZ128rmk:
21507 case VORPSZ128rmkz:
21508 case VORPSZ128rr:
21509 case VORPSZ128rrk:
21510 case VORPSZ128rrkz:
21511 case VORPSZ256rm:
21512 case VORPSZ256rmb:
21513 case VORPSZ256rmbk:
21514 case VORPSZ256rmbkz:
21515 case VORPSZ256rmk:
21516 case VORPSZ256rmkz:
21517 case VORPSZ256rr:
21518 case VORPSZ256rrk:
21519 case VORPSZ256rrkz:
21520 case VORPSZrm:
21521 case VORPSZrmb:
21522 case VORPSZrmbk:
21523 case VORPSZrmbkz:
21524 case VORPSZrmk:
21525 case VORPSZrmkz:
21526 case VORPSZrr:
21527 case VORPSZrrk:
21528 case VORPSZrrkz:
21529 case VORPSrm:
21530 case VORPSrr:
21531 return true;
21532 }
21533 return false;
21534}
21535
21536bool isVPEXPANDQ(unsigned Opcode) {
21537 switch (Opcode) {
21538 case VPEXPANDQZ128rm:
21539 case VPEXPANDQZ128rmk:
21540 case VPEXPANDQZ128rmkz:
21541 case VPEXPANDQZ128rr:
21542 case VPEXPANDQZ128rrk:
21543 case VPEXPANDQZ128rrkz:
21544 case VPEXPANDQZ256rm:
21545 case VPEXPANDQZ256rmk:
21546 case VPEXPANDQZ256rmkz:
21547 case VPEXPANDQZ256rr:
21548 case VPEXPANDQZ256rrk:
21549 case VPEXPANDQZ256rrkz:
21550 case VPEXPANDQZrm:
21551 case VPEXPANDQZrmk:
21552 case VPEXPANDQZrmkz:
21553 case VPEXPANDQZrr:
21554 case VPEXPANDQZrrk:
21555 case VPEXPANDQZrrkz:
21556 return true;
21557 }
21558 return false;
21559}
21560
21561bool isVPSHRDD(unsigned Opcode) {
21562 switch (Opcode) {
21563 case VPSHRDDZ128rmbi:
21564 case VPSHRDDZ128rmbik:
21565 case VPSHRDDZ128rmbikz:
21566 case VPSHRDDZ128rmi:
21567 case VPSHRDDZ128rmik:
21568 case VPSHRDDZ128rmikz:
21569 case VPSHRDDZ128rri:
21570 case VPSHRDDZ128rrik:
21571 case VPSHRDDZ128rrikz:
21572 case VPSHRDDZ256rmbi:
21573 case VPSHRDDZ256rmbik:
21574 case VPSHRDDZ256rmbikz:
21575 case VPSHRDDZ256rmi:
21576 case VPSHRDDZ256rmik:
21577 case VPSHRDDZ256rmikz:
21578 case VPSHRDDZ256rri:
21579 case VPSHRDDZ256rrik:
21580 case VPSHRDDZ256rrikz:
21581 case VPSHRDDZrmbi:
21582 case VPSHRDDZrmbik:
21583 case VPSHRDDZrmbikz:
21584 case VPSHRDDZrmi:
21585 case VPSHRDDZrmik:
21586 case VPSHRDDZrmikz:
21587 case VPSHRDDZrri:
21588 case VPSHRDDZrrik:
21589 case VPSHRDDZrrikz:
21590 return true;
21591 }
21592 return false;
21593}
21594
21595bool isTDPBSSD(unsigned Opcode) {
21596 return Opcode == TDPBSSD;
21597}
21598
21599bool isTESTUI(unsigned Opcode) {
21600 return Opcode == TESTUI;
21601}
21602
21603bool isVFMADDPD(unsigned Opcode) {
21604 switch (Opcode) {
21605 case VFMADDPD4Ymr:
21606 case VFMADDPD4Yrm:
21607 case VFMADDPD4Yrr:
21608 case VFMADDPD4Yrr_REV:
21609 case VFMADDPD4mr:
21610 case VFMADDPD4rm:
21611 case VFMADDPD4rr:
21612 case VFMADDPD4rr_REV:
21613 return true;
21614 }
21615 return false;
21616}
21617
21618bool isVPANDND(unsigned Opcode) {
21619 switch (Opcode) {
21620 case VPANDNDZ128rm:
21621 case VPANDNDZ128rmb:
21622 case VPANDNDZ128rmbk:
21623 case VPANDNDZ128rmbkz:
21624 case VPANDNDZ128rmk:
21625 case VPANDNDZ128rmkz:
21626 case VPANDNDZ128rr:
21627 case VPANDNDZ128rrk:
21628 case VPANDNDZ128rrkz:
21629 case VPANDNDZ256rm:
21630 case VPANDNDZ256rmb:
21631 case VPANDNDZ256rmbk:
21632 case VPANDNDZ256rmbkz:
21633 case VPANDNDZ256rmk:
21634 case VPANDNDZ256rmkz:
21635 case VPANDNDZ256rr:
21636 case VPANDNDZ256rrk:
21637 case VPANDNDZ256rrkz:
21638 case VPANDNDZrm:
21639 case VPANDNDZrmb:
21640 case VPANDNDZrmbk:
21641 case VPANDNDZrmbkz:
21642 case VPANDNDZrmk:
21643 case VPANDNDZrmkz:
21644 case VPANDNDZrr:
21645 case VPANDNDZrrk:
21646 case VPANDNDZrrkz:
21647 return true;
21648 }
21649 return false;
21650}
21651
21652bool isVPMOVSDB(unsigned Opcode) {
21653 switch (Opcode) {
21654 case VPMOVSDBZ128mr:
21655 case VPMOVSDBZ128mrk:
21656 case VPMOVSDBZ128rr:
21657 case VPMOVSDBZ128rrk:
21658 case VPMOVSDBZ128rrkz:
21659 case VPMOVSDBZ256mr:
21660 case VPMOVSDBZ256mrk:
21661 case VPMOVSDBZ256rr:
21662 case VPMOVSDBZ256rrk:
21663 case VPMOVSDBZ256rrkz:
21664 case VPMOVSDBZmr:
21665 case VPMOVSDBZmrk:
21666 case VPMOVSDBZrr:
21667 case VPMOVSDBZrrk:
21668 case VPMOVSDBZrrkz:
21669 return true;
21670 }
21671 return false;
21672}
21673
21674bool isVPBROADCASTB(unsigned Opcode) {
21675 switch (Opcode) {
21676 case VPBROADCASTBYrm:
21677 case VPBROADCASTBYrr:
21678 case VPBROADCASTBZ128rm:
21679 case VPBROADCASTBZ128rmk:
21680 case VPBROADCASTBZ128rmkz:
21681 case VPBROADCASTBZ128rr:
21682 case VPBROADCASTBZ128rrk:
21683 case VPBROADCASTBZ128rrkz:
21684 case VPBROADCASTBZ256rm:
21685 case VPBROADCASTBZ256rmk:
21686 case VPBROADCASTBZ256rmkz:
21687 case VPBROADCASTBZ256rr:
21688 case VPBROADCASTBZ256rrk:
21689 case VPBROADCASTBZ256rrkz:
21690 case VPBROADCASTBZrm:
21691 case VPBROADCASTBZrmk:
21692 case VPBROADCASTBZrmkz:
21693 case VPBROADCASTBZrr:
21694 case VPBROADCASTBZrrk:
21695 case VPBROADCASTBZrrkz:
21696 case VPBROADCASTBrZ128rr:
21697 case VPBROADCASTBrZ128rrk:
21698 case VPBROADCASTBrZ128rrkz:
21699 case VPBROADCASTBrZ256rr:
21700 case VPBROADCASTBrZ256rrk:
21701 case VPBROADCASTBrZ256rrkz:
21702 case VPBROADCASTBrZrr:
21703 case VPBROADCASTBrZrrk:
21704 case VPBROADCASTBrZrrkz:
21705 case VPBROADCASTBrm:
21706 case VPBROADCASTBrr:
21707 return true;
21708 }
21709 return false;
21710}
21711
21712bool isCVTPI2PD(unsigned Opcode) {
21713 switch (Opcode) {
21714 case MMX_CVTPI2PDrm:
21715 case MMX_CVTPI2PDrr:
21716 return true;
21717 }
21718 return false;
21719}
21720
21721bool isVPERMI2B(unsigned Opcode) {
21722 switch (Opcode) {
21723 case VPERMI2BZ128rm:
21724 case VPERMI2BZ128rmk:
21725 case VPERMI2BZ128rmkz:
21726 case VPERMI2BZ128rr:
21727 case VPERMI2BZ128rrk:
21728 case VPERMI2BZ128rrkz:
21729 case VPERMI2BZ256rm:
21730 case VPERMI2BZ256rmk:
21731 case VPERMI2BZ256rmkz:
21732 case VPERMI2BZ256rr:
21733 case VPERMI2BZ256rrk:
21734 case VPERMI2BZ256rrkz:
21735 case VPERMI2BZrm:
21736 case VPERMI2BZrmk:
21737 case VPERMI2BZrmkz:
21738 case VPERMI2BZrr:
21739 case VPERMI2BZrrk:
21740 case VPERMI2BZrrkz:
21741 return true;
21742 }
21743 return false;
21744}
21745
21746bool isVPMINSB(unsigned Opcode) {
21747 switch (Opcode) {
21748 case VPMINSBYrm:
21749 case VPMINSBYrr:
21750 case VPMINSBZ128rm:
21751 case VPMINSBZ128rmk:
21752 case VPMINSBZ128rmkz:
21753 case VPMINSBZ128rr:
21754 case VPMINSBZ128rrk:
21755 case VPMINSBZ128rrkz:
21756 case VPMINSBZ256rm:
21757 case VPMINSBZ256rmk:
21758 case VPMINSBZ256rmkz:
21759 case VPMINSBZ256rr:
21760 case VPMINSBZ256rrk:
21761 case VPMINSBZ256rrkz:
21762 case VPMINSBZrm:
21763 case VPMINSBZrmk:
21764 case VPMINSBZrmkz:
21765 case VPMINSBZrr:
21766 case VPMINSBZrrk:
21767 case VPMINSBZrrkz:
21768 case VPMINSBrm:
21769 case VPMINSBrr:
21770 return true;
21771 }
21772 return false;
21773}
21774
21775bool isLAR(unsigned Opcode) {
21776 switch (Opcode) {
21777 case LAR16rm:
21778 case LAR16rr:
21779 case LAR32rm:
21780 case LAR32rr:
21781 case LAR64rm:
21782 case LAR64rr:
21783 return true;
21784 }
21785 return false;
21786}
21787
21788bool isINVLPGB(unsigned Opcode) {
21789 switch (Opcode) {
21790 case INVLPGB32:
21791 case INVLPGB64:
21792 return true;
21793 }
21794 return false;
21795}
21796
21797bool isTLBSYNC(unsigned Opcode) {
21798 return Opcode == TLBSYNC;
21799}
21800
21801bool isFDIVP(unsigned Opcode) {
21802 return Opcode == DIV_FPrST0;
21803}
21804
21805bool isVPSRLW(unsigned Opcode) {
21806 switch (Opcode) {
21807 case VPSRLWYri:
21808 case VPSRLWYrm:
21809 case VPSRLWYrr:
21810 case VPSRLWZ128mi:
21811 case VPSRLWZ128mik:
21812 case VPSRLWZ128mikz:
21813 case VPSRLWZ128ri:
21814 case VPSRLWZ128rik:
21815 case VPSRLWZ128rikz:
21816 case VPSRLWZ128rm:
21817 case VPSRLWZ128rmk:
21818 case VPSRLWZ128rmkz:
21819 case VPSRLWZ128rr:
21820 case VPSRLWZ128rrk:
21821 case VPSRLWZ128rrkz:
21822 case VPSRLWZ256mi:
21823 case VPSRLWZ256mik:
21824 case VPSRLWZ256mikz:
21825 case VPSRLWZ256ri:
21826 case VPSRLWZ256rik:
21827 case VPSRLWZ256rikz:
21828 case VPSRLWZ256rm:
21829 case VPSRLWZ256rmk:
21830 case VPSRLWZ256rmkz:
21831 case VPSRLWZ256rr:
21832 case VPSRLWZ256rrk:
21833 case VPSRLWZ256rrkz:
21834 case VPSRLWZmi:
21835 case VPSRLWZmik:
21836 case VPSRLWZmikz:
21837 case VPSRLWZri:
21838 case VPSRLWZrik:
21839 case VPSRLWZrikz:
21840 case VPSRLWZrm:
21841 case VPSRLWZrmk:
21842 case VPSRLWZrmkz:
21843 case VPSRLWZrr:
21844 case VPSRLWZrrk:
21845 case VPSRLWZrrkz:
21846 case VPSRLWri:
21847 case VPSRLWrm:
21848 case VPSRLWrr:
21849 return true;
21850 }
21851 return false;
21852}
21853
21854bool isVRCP28SS(unsigned Opcode) {
21855 switch (Opcode) {
21856 case VRCP28SSZm:
21857 case VRCP28SSZmk:
21858 case VRCP28SSZmkz:
21859 case VRCP28SSZr:
21860 case VRCP28SSZrb:
21861 case VRCP28SSZrbk:
21862 case VRCP28SSZrbkz:
21863 case VRCP28SSZrk:
21864 case VRCP28SSZrkz:
21865 return true;
21866 }
21867 return false;
21868}
21869
21870bool isVMOVHPS(unsigned Opcode) {
21871 switch (Opcode) {
21872 case VMOVHPSZ128mr:
21873 case VMOVHPSZ128rm:
21874 case VMOVHPSmr:
21875 case VMOVHPSrm:
21876 return true;
21877 }
21878 return false;
21879}
21880
21881bool isVPMACSSDD(unsigned Opcode) {
21882 switch (Opcode) {
21883 case VPMACSSDDrm:
21884 case VPMACSSDDrr:
21885 return true;
21886 }
21887 return false;
21888}
21889
21890bool isPEXT(unsigned Opcode) {
21891 switch (Opcode) {
21892 case PEXT32rm:
21893 case PEXT32rm_EVEX:
21894 case PEXT32rr:
21895 case PEXT32rr_EVEX:
21896 case PEXT64rm:
21897 case PEXT64rm_EVEX:
21898 case PEXT64rr:
21899 case PEXT64rr_EVEX:
21900 return true;
21901 }
21902 return false;
21903}
21904
21905bool isVMAXBF16(unsigned Opcode) {
21906 switch (Opcode) {
21907 case VMAXBF16Z128rm:
21908 case VMAXBF16Z128rmb:
21909 case VMAXBF16Z128rmbk:
21910 case VMAXBF16Z128rmbkz:
21911 case VMAXBF16Z128rmk:
21912 case VMAXBF16Z128rmkz:
21913 case VMAXBF16Z128rr:
21914 case VMAXBF16Z128rrk:
21915 case VMAXBF16Z128rrkz:
21916 case VMAXBF16Z256rm:
21917 case VMAXBF16Z256rmb:
21918 case VMAXBF16Z256rmbk:
21919 case VMAXBF16Z256rmbkz:
21920 case VMAXBF16Z256rmk:
21921 case VMAXBF16Z256rmkz:
21922 case VMAXBF16Z256rr:
21923 case VMAXBF16Z256rrk:
21924 case VMAXBF16Z256rrkz:
21925 case VMAXBF16Zrm:
21926 case VMAXBF16Zrmb:
21927 case VMAXBF16Zrmbk:
21928 case VMAXBF16Zrmbkz:
21929 case VMAXBF16Zrmk:
21930 case VMAXBF16Zrmkz:
21931 case VMAXBF16Zrr:
21932 case VMAXBF16Zrrk:
21933 case VMAXBF16Zrrkz:
21934 return true;
21935 }
21936 return false;
21937}
21938
21939bool isVRSQRT14SD(unsigned Opcode) {
21940 switch (Opcode) {
21941 case VRSQRT14SDZrm:
21942 case VRSQRT14SDZrmk:
21943 case VRSQRT14SDZrmkz:
21944 case VRSQRT14SDZrr:
21945 case VRSQRT14SDZrrk:
21946 case VRSQRT14SDZrrkz:
21947 return true;
21948 }
21949 return false;
21950}
21951
21952bool isVPDPWSSD(unsigned Opcode) {
21953 switch (Opcode) {
21954 case VPDPWSSDYrm:
21955 case VPDPWSSDYrr:
21956 case VPDPWSSDZ128m:
21957 case VPDPWSSDZ128mb:
21958 case VPDPWSSDZ128mbk:
21959 case VPDPWSSDZ128mbkz:
21960 case VPDPWSSDZ128mk:
21961 case VPDPWSSDZ128mkz:
21962 case VPDPWSSDZ128r:
21963 case VPDPWSSDZ128rk:
21964 case VPDPWSSDZ128rkz:
21965 case VPDPWSSDZ256m:
21966 case VPDPWSSDZ256mb:
21967 case VPDPWSSDZ256mbk:
21968 case VPDPWSSDZ256mbkz:
21969 case VPDPWSSDZ256mk:
21970 case VPDPWSSDZ256mkz:
21971 case VPDPWSSDZ256r:
21972 case VPDPWSSDZ256rk:
21973 case VPDPWSSDZ256rkz:
21974 case VPDPWSSDZm:
21975 case VPDPWSSDZmb:
21976 case VPDPWSSDZmbk:
21977 case VPDPWSSDZmbkz:
21978 case VPDPWSSDZmk:
21979 case VPDPWSSDZmkz:
21980 case VPDPWSSDZr:
21981 case VPDPWSSDZrk:
21982 case VPDPWSSDZrkz:
21983 case VPDPWSSDrm:
21984 case VPDPWSSDrr:
21985 return true;
21986 }
21987 return false;
21988}
21989
21990bool isVFMSUB231SD(unsigned Opcode) {
21991 switch (Opcode) {
21992 case VFMSUB231SDZm_Int:
21993 case VFMSUB231SDZmk_Int:
21994 case VFMSUB231SDZmkz_Int:
21995 case VFMSUB231SDZr_Int:
21996 case VFMSUB231SDZrb_Int:
21997 case VFMSUB231SDZrbk_Int:
21998 case VFMSUB231SDZrbkz_Int:
21999 case VFMSUB231SDZrk_Int:
22000 case VFMSUB231SDZrkz_Int:
22001 case VFMSUB231SDm_Int:
22002 case VFMSUB231SDr_Int:
22003 return true;
22004 }
22005 return false;
22006}
22007
22008bool isVPMOVZXWQ(unsigned Opcode) {
22009 switch (Opcode) {
22010 case VPMOVZXWQYrm:
22011 case VPMOVZXWQYrr:
22012 case VPMOVZXWQZ128rm:
22013 case VPMOVZXWQZ128rmk:
22014 case VPMOVZXWQZ128rmkz:
22015 case VPMOVZXWQZ128rr:
22016 case VPMOVZXWQZ128rrk:
22017 case VPMOVZXWQZ128rrkz:
22018 case VPMOVZXWQZ256rm:
22019 case VPMOVZXWQZ256rmk:
22020 case VPMOVZXWQZ256rmkz:
22021 case VPMOVZXWQZ256rr:
22022 case VPMOVZXWQZ256rrk:
22023 case VPMOVZXWQZ256rrkz:
22024 case VPMOVZXWQZrm:
22025 case VPMOVZXWQZrmk:
22026 case VPMOVZXWQZrmkz:
22027 case VPMOVZXWQZrr:
22028 case VPMOVZXWQZrrk:
22029 case VPMOVZXWQZrrkz:
22030 case VPMOVZXWQrm:
22031 case VPMOVZXWQrr:
22032 return true;
22033 }
22034 return false;
22035}
22036
22037bool isVMOVDQA(unsigned Opcode) {
22038 switch (Opcode) {
22039 case VMOVDQAYmr:
22040 case VMOVDQAYrm:
22041 case VMOVDQAYrr:
22042 case VMOVDQAYrr_REV:
22043 case VMOVDQAmr:
22044 case VMOVDQArm:
22045 case VMOVDQArr:
22046 case VMOVDQArr_REV:
22047 return true;
22048 }
22049 return false;
22050}
22051
22052bool isVFNMSUB213SD(unsigned Opcode) {
22053 switch (Opcode) {
22054 case VFNMSUB213SDZm_Int:
22055 case VFNMSUB213SDZmk_Int:
22056 case VFNMSUB213SDZmkz_Int:
22057 case VFNMSUB213SDZr_Int:
22058 case VFNMSUB213SDZrb_Int:
22059 case VFNMSUB213SDZrbk_Int:
22060 case VFNMSUB213SDZrbkz_Int:
22061 case VFNMSUB213SDZrk_Int:
22062 case VFNMSUB213SDZrkz_Int:
22063 case VFNMSUB213SDm_Int:
22064 case VFNMSUB213SDr_Int:
22065 return true;
22066 }
22067 return false;
22068}
22069
22070bool isVMINPS(unsigned Opcode) {
22071 switch (Opcode) {
22072 case VMINPSYrm:
22073 case VMINPSYrr:
22074 case VMINPSZ128rm:
22075 case VMINPSZ128rmb:
22076 case VMINPSZ128rmbk:
22077 case VMINPSZ128rmbkz:
22078 case VMINPSZ128rmk:
22079 case VMINPSZ128rmkz:
22080 case VMINPSZ128rr:
22081 case VMINPSZ128rrk:
22082 case VMINPSZ128rrkz:
22083 case VMINPSZ256rm:
22084 case VMINPSZ256rmb:
22085 case VMINPSZ256rmbk:
22086 case VMINPSZ256rmbkz:
22087 case VMINPSZ256rmk:
22088 case VMINPSZ256rmkz:
22089 case VMINPSZ256rr:
22090 case VMINPSZ256rrk:
22091 case VMINPSZ256rrkz:
22092 case VMINPSZrm:
22093 case VMINPSZrmb:
22094 case VMINPSZrmbk:
22095 case VMINPSZrmbkz:
22096 case VMINPSZrmk:
22097 case VMINPSZrmkz:
22098 case VMINPSZrr:
22099 case VMINPSZrrb:
22100 case VMINPSZrrbk:
22101 case VMINPSZrrbkz:
22102 case VMINPSZrrk:
22103 case VMINPSZrrkz:
22104 case VMINPSrm:
22105 case VMINPSrr:
22106 return true;
22107 }
22108 return false;
22109}
22110
22111bool isVFMSUB231PS(unsigned Opcode) {
22112 switch (Opcode) {
22113 case VFMSUB231PSYm:
22114 case VFMSUB231PSYr:
22115 case VFMSUB231PSZ128m:
22116 case VFMSUB231PSZ128mb:
22117 case VFMSUB231PSZ128mbk:
22118 case VFMSUB231PSZ128mbkz:
22119 case VFMSUB231PSZ128mk:
22120 case VFMSUB231PSZ128mkz:
22121 case VFMSUB231PSZ128r:
22122 case VFMSUB231PSZ128rk:
22123 case VFMSUB231PSZ128rkz:
22124 case VFMSUB231PSZ256m:
22125 case VFMSUB231PSZ256mb:
22126 case VFMSUB231PSZ256mbk:
22127 case VFMSUB231PSZ256mbkz:
22128 case VFMSUB231PSZ256mk:
22129 case VFMSUB231PSZ256mkz:
22130 case VFMSUB231PSZ256r:
22131 case VFMSUB231PSZ256rk:
22132 case VFMSUB231PSZ256rkz:
22133 case VFMSUB231PSZm:
22134 case VFMSUB231PSZmb:
22135 case VFMSUB231PSZmbk:
22136 case VFMSUB231PSZmbkz:
22137 case VFMSUB231PSZmk:
22138 case VFMSUB231PSZmkz:
22139 case VFMSUB231PSZr:
22140 case VFMSUB231PSZrb:
22141 case VFMSUB231PSZrbk:
22142 case VFMSUB231PSZrbkz:
22143 case VFMSUB231PSZrk:
22144 case VFMSUB231PSZrkz:
22145 case VFMSUB231PSm:
22146 case VFMSUB231PSr:
22147 return true;
22148 }
22149 return false;
22150}
22151
22152bool isVPCOMPRESSB(unsigned Opcode) {
22153 switch (Opcode) {
22154 case VPCOMPRESSBZ128mr:
22155 case VPCOMPRESSBZ128mrk:
22156 case VPCOMPRESSBZ128rr:
22157 case VPCOMPRESSBZ128rrk:
22158 case VPCOMPRESSBZ128rrkz:
22159 case VPCOMPRESSBZ256mr:
22160 case VPCOMPRESSBZ256mrk:
22161 case VPCOMPRESSBZ256rr:
22162 case VPCOMPRESSBZ256rrk:
22163 case VPCOMPRESSBZ256rrkz:
22164 case VPCOMPRESSBZmr:
22165 case VPCOMPRESSBZmrk:
22166 case VPCOMPRESSBZrr:
22167 case VPCOMPRESSBZrrk:
22168 case VPCOMPRESSBZrrkz:
22169 return true;
22170 }
22171 return false;
22172}
22173
22174bool isVPCMPEQQ(unsigned Opcode) {
22175 switch (Opcode) {
22176 case VPCMPEQQYrm:
22177 case VPCMPEQQYrr:
22178 case VPCMPEQQZ128rm:
22179 case VPCMPEQQZ128rmb:
22180 case VPCMPEQQZ128rmbk:
22181 case VPCMPEQQZ128rmk:
22182 case VPCMPEQQZ128rr:
22183 case VPCMPEQQZ128rrk:
22184 case VPCMPEQQZ256rm:
22185 case VPCMPEQQZ256rmb:
22186 case VPCMPEQQZ256rmbk:
22187 case VPCMPEQQZ256rmk:
22188 case VPCMPEQQZ256rr:
22189 case VPCMPEQQZ256rrk:
22190 case VPCMPEQQZrm:
22191 case VPCMPEQQZrmb:
22192 case VPCMPEQQZrmbk:
22193 case VPCMPEQQZrmk:
22194 case VPCMPEQQZrr:
22195 case VPCMPEQQZrrk:
22196 case VPCMPEQQrm:
22197 case VPCMPEQQrr:
22198 return true;
22199 }
22200 return false;
22201}
22202
22203bool isVRCPSS(unsigned Opcode) {
22204 switch (Opcode) {
22205 case VRCPSSm_Int:
22206 case VRCPSSr_Int:
22207 return true;
22208 }
22209 return false;
22210}
22211
22212bool isVSCATTERPF1DPS(unsigned Opcode) {
22213 return Opcode == VSCATTERPF1DPSm;
22214}
22215
22216bool isVPHADDUBW(unsigned Opcode) {
22217 switch (Opcode) {
22218 case VPHADDUBWrm:
22219 case VPHADDUBWrr:
22220 return true;
22221 }
22222 return false;
22223}
22224
22225bool isXORPD(unsigned Opcode) {
22226 switch (Opcode) {
22227 case XORPDrm:
22228 case XORPDrr:
22229 return true;
22230 }
22231 return false;
22232}
22233
22234bool isVPSCATTERQQ(unsigned Opcode) {
22235 switch (Opcode) {
22236 case VPSCATTERQQZ128mr:
22237 case VPSCATTERQQZ256mr:
22238 case VPSCATTERQQZmr:
22239 return true;
22240 }
22241 return false;
22242}
22243
22244bool isVCVTW2PH(unsigned Opcode) {
22245 switch (Opcode) {
22246 case VCVTW2PHZ128rm:
22247 case VCVTW2PHZ128rmb:
22248 case VCVTW2PHZ128rmbk:
22249 case VCVTW2PHZ128rmbkz:
22250 case VCVTW2PHZ128rmk:
22251 case VCVTW2PHZ128rmkz:
22252 case VCVTW2PHZ128rr:
22253 case VCVTW2PHZ128rrk:
22254 case VCVTW2PHZ128rrkz:
22255 case VCVTW2PHZ256rm:
22256 case VCVTW2PHZ256rmb:
22257 case VCVTW2PHZ256rmbk:
22258 case VCVTW2PHZ256rmbkz:
22259 case VCVTW2PHZ256rmk:
22260 case VCVTW2PHZ256rmkz:
22261 case VCVTW2PHZ256rr:
22262 case VCVTW2PHZ256rrk:
22263 case VCVTW2PHZ256rrkz:
22264 case VCVTW2PHZrm:
22265 case VCVTW2PHZrmb:
22266 case VCVTW2PHZrmbk:
22267 case VCVTW2PHZrmbkz:
22268 case VCVTW2PHZrmk:
22269 case VCVTW2PHZrmkz:
22270 case VCVTW2PHZrr:
22271 case VCVTW2PHZrrb:
22272 case VCVTW2PHZrrbk:
22273 case VCVTW2PHZrrbkz:
22274 case VCVTW2PHZrrk:
22275 case VCVTW2PHZrrkz:
22276 return true;
22277 }
22278 return false;
22279}
22280
22281bool isVFMADDCPH(unsigned Opcode) {
22282 switch (Opcode) {
22283 case VFMADDCPHZ128m:
22284 case VFMADDCPHZ128mb:
22285 case VFMADDCPHZ128mbk:
22286 case VFMADDCPHZ128mbkz:
22287 case VFMADDCPHZ128mk:
22288 case VFMADDCPHZ128mkz:
22289 case VFMADDCPHZ128r:
22290 case VFMADDCPHZ128rk:
22291 case VFMADDCPHZ128rkz:
22292 case VFMADDCPHZ256m:
22293 case VFMADDCPHZ256mb:
22294 case VFMADDCPHZ256mbk:
22295 case VFMADDCPHZ256mbkz:
22296 case VFMADDCPHZ256mk:
22297 case VFMADDCPHZ256mkz:
22298 case VFMADDCPHZ256r:
22299 case VFMADDCPHZ256rk:
22300 case VFMADDCPHZ256rkz:
22301 case VFMADDCPHZm:
22302 case VFMADDCPHZmb:
22303 case VFMADDCPHZmbk:
22304 case VFMADDCPHZmbkz:
22305 case VFMADDCPHZmk:
22306 case VFMADDCPHZmkz:
22307 case VFMADDCPHZr:
22308 case VFMADDCPHZrb:
22309 case VFMADDCPHZrbk:
22310 case VFMADDCPHZrbkz:
22311 case VFMADDCPHZrk:
22312 case VFMADDCPHZrkz:
22313 return true;
22314 }
22315 return false;
22316}
22317
22318bool isVSUBPD(unsigned Opcode) {
22319 switch (Opcode) {
22320 case VSUBPDYrm:
22321 case VSUBPDYrr:
22322 case VSUBPDZ128rm:
22323 case VSUBPDZ128rmb:
22324 case VSUBPDZ128rmbk:
22325 case VSUBPDZ128rmbkz:
22326 case VSUBPDZ128rmk:
22327 case VSUBPDZ128rmkz:
22328 case VSUBPDZ128rr:
22329 case VSUBPDZ128rrk:
22330 case VSUBPDZ128rrkz:
22331 case VSUBPDZ256rm:
22332 case VSUBPDZ256rmb:
22333 case VSUBPDZ256rmbk:
22334 case VSUBPDZ256rmbkz:
22335 case VSUBPDZ256rmk:
22336 case VSUBPDZ256rmkz:
22337 case VSUBPDZ256rr:
22338 case VSUBPDZ256rrk:
22339 case VSUBPDZ256rrkz:
22340 case VSUBPDZrm:
22341 case VSUBPDZrmb:
22342 case VSUBPDZrmbk:
22343 case VSUBPDZrmbkz:
22344 case VSUBPDZrmk:
22345 case VSUBPDZrmkz:
22346 case VSUBPDZrr:
22347 case VSUBPDZrrb:
22348 case VSUBPDZrrbk:
22349 case VSUBPDZrrbkz:
22350 case VSUBPDZrrk:
22351 case VSUBPDZrrkz:
22352 case VSUBPDrm:
22353 case VSUBPDrr:
22354 return true;
22355 }
22356 return false;
22357}
22358
22359bool isVPACKUSDW(unsigned Opcode) {
22360 switch (Opcode) {
22361 case VPACKUSDWYrm:
22362 case VPACKUSDWYrr:
22363 case VPACKUSDWZ128rm:
22364 case VPACKUSDWZ128rmb:
22365 case VPACKUSDWZ128rmbk:
22366 case VPACKUSDWZ128rmbkz:
22367 case VPACKUSDWZ128rmk:
22368 case VPACKUSDWZ128rmkz:
22369 case VPACKUSDWZ128rr:
22370 case VPACKUSDWZ128rrk:
22371 case VPACKUSDWZ128rrkz:
22372 case VPACKUSDWZ256rm:
22373 case VPACKUSDWZ256rmb:
22374 case VPACKUSDWZ256rmbk:
22375 case VPACKUSDWZ256rmbkz:
22376 case VPACKUSDWZ256rmk:
22377 case VPACKUSDWZ256rmkz:
22378 case VPACKUSDWZ256rr:
22379 case VPACKUSDWZ256rrk:
22380 case VPACKUSDWZ256rrkz:
22381 case VPACKUSDWZrm:
22382 case VPACKUSDWZrmb:
22383 case VPACKUSDWZrmbk:
22384 case VPACKUSDWZrmbkz:
22385 case VPACKUSDWZrmk:
22386 case VPACKUSDWZrmkz:
22387 case VPACKUSDWZrr:
22388 case VPACKUSDWZrrk:
22389 case VPACKUSDWZrrkz:
22390 case VPACKUSDWrm:
22391 case VPACKUSDWrr:
22392 return true;
22393 }
22394 return false;
22395}
22396
22397bool isVSCALEFSS(unsigned Opcode) {
22398 switch (Opcode) {
22399 case VSCALEFSSZrm:
22400 case VSCALEFSSZrmk:
22401 case VSCALEFSSZrmkz:
22402 case VSCALEFSSZrr:
22403 case VSCALEFSSZrrb_Int:
22404 case VSCALEFSSZrrbk_Int:
22405 case VSCALEFSSZrrbkz_Int:
22406 case VSCALEFSSZrrk:
22407 case VSCALEFSSZrrkz:
22408 return true;
22409 }
22410 return false;
22411}
22412
22413bool isAESIMC(unsigned Opcode) {
22414 switch (Opcode) {
22415 case AESIMCrm:
22416 case AESIMCrr:
22417 return true;
22418 }
22419 return false;
22420}
22421
22422bool isVRCP28PS(unsigned Opcode) {
22423 switch (Opcode) {
22424 case VRCP28PSZm:
22425 case VRCP28PSZmb:
22426 case VRCP28PSZmbk:
22427 case VRCP28PSZmbkz:
22428 case VRCP28PSZmk:
22429 case VRCP28PSZmkz:
22430 case VRCP28PSZr:
22431 case VRCP28PSZrb:
22432 case VRCP28PSZrbk:
22433 case VRCP28PSZrbkz:
22434 case VRCP28PSZrk:
22435 case VRCP28PSZrkz:
22436 return true;
22437 }
22438 return false;
22439}
22440
22441bool isAAND(unsigned Opcode) {
22442 switch (Opcode) {
22443 case AAND32mr:
22444 case AAND32mr_EVEX:
22445 case AAND64mr:
22446 case AAND64mr_EVEX:
22447 return true;
22448 }
22449 return false;
22450}
22451
22452bool isDAA(unsigned Opcode) {
22453 return Opcode == DAA;
22454}
22455
22456bool isVCVTPD2UDQ(unsigned Opcode) {
22457 switch (Opcode) {
22458 case VCVTPD2UDQZ128rm:
22459 case VCVTPD2UDQZ128rmb:
22460 case VCVTPD2UDQZ128rmbk:
22461 case VCVTPD2UDQZ128rmbkz:
22462 case VCVTPD2UDQZ128rmk:
22463 case VCVTPD2UDQZ128rmkz:
22464 case VCVTPD2UDQZ128rr:
22465 case VCVTPD2UDQZ128rrk:
22466 case VCVTPD2UDQZ128rrkz:
22467 case VCVTPD2UDQZ256rm:
22468 case VCVTPD2UDQZ256rmb:
22469 case VCVTPD2UDQZ256rmbk:
22470 case VCVTPD2UDQZ256rmbkz:
22471 case VCVTPD2UDQZ256rmk:
22472 case VCVTPD2UDQZ256rmkz:
22473 case VCVTPD2UDQZ256rr:
22474 case VCVTPD2UDQZ256rrk:
22475 case VCVTPD2UDQZ256rrkz:
22476 case VCVTPD2UDQZrm:
22477 case VCVTPD2UDQZrmb:
22478 case VCVTPD2UDQZrmbk:
22479 case VCVTPD2UDQZrmbkz:
22480 case VCVTPD2UDQZrmk:
22481 case VCVTPD2UDQZrmkz:
22482 case VCVTPD2UDQZrr:
22483 case VCVTPD2UDQZrrb:
22484 case VCVTPD2UDQZrrbk:
22485 case VCVTPD2UDQZrrbkz:
22486 case VCVTPD2UDQZrrk:
22487 case VCVTPD2UDQZrrkz:
22488 return true;
22489 }
22490 return false;
22491}
22492
22493bool isKTESTW(unsigned Opcode) {
22494 return Opcode == KTESTWkk;
22495}
22496
22497bool isVPADDQ(unsigned Opcode) {
22498 switch (Opcode) {
22499 case VPADDQYrm:
22500 case VPADDQYrr:
22501 case VPADDQZ128rm:
22502 case VPADDQZ128rmb:
22503 case VPADDQZ128rmbk:
22504 case VPADDQZ128rmbkz:
22505 case VPADDQZ128rmk:
22506 case VPADDQZ128rmkz:
22507 case VPADDQZ128rr:
22508 case VPADDQZ128rrk:
22509 case VPADDQZ128rrkz:
22510 case VPADDQZ256rm:
22511 case VPADDQZ256rmb:
22512 case VPADDQZ256rmbk:
22513 case VPADDQZ256rmbkz:
22514 case VPADDQZ256rmk:
22515 case VPADDQZ256rmkz:
22516 case VPADDQZ256rr:
22517 case VPADDQZ256rrk:
22518 case VPADDQZ256rrkz:
22519 case VPADDQZrm:
22520 case VPADDQZrmb:
22521 case VPADDQZrmbk:
22522 case VPADDQZrmbkz:
22523 case VPADDQZrmk:
22524 case VPADDQZrmkz:
22525 case VPADDQZrr:
22526 case VPADDQZrrk:
22527 case VPADDQZrrkz:
22528 case VPADDQrm:
22529 case VPADDQrr:
22530 return true;
22531 }
22532 return false;
22533}
22534
22535bool isPALIGNR(unsigned Opcode) {
22536 switch (Opcode) {
22537 case MMX_PALIGNRrmi:
22538 case MMX_PALIGNRrri:
22539 case PALIGNRrmi:
22540 case PALIGNRrri:
22541 return true;
22542 }
22543 return false;
22544}
22545
22546bool isPMAXUW(unsigned Opcode) {
22547 switch (Opcode) {
22548 case PMAXUWrm:
22549 case PMAXUWrr:
22550 return true;
22551 }
22552 return false;
22553}
22554
22555bool isVFMADDSD(unsigned Opcode) {
22556 switch (Opcode) {
22557 case VFMADDSD4mr:
22558 case VFMADDSD4rm:
22559 case VFMADDSD4rr:
22560 case VFMADDSD4rr_REV:
22561 return true;
22562 }
22563 return false;
22564}
22565
22566bool isPFMAX(unsigned Opcode) {
22567 switch (Opcode) {
22568 case PFMAXrm:
22569 case PFMAXrr:
22570 return true;
22571 }
22572 return false;
22573}
22574
22575bool isVPOR(unsigned Opcode) {
22576 switch (Opcode) {
22577 case VPORYrm:
22578 case VPORYrr:
22579 case VPORrm:
22580 case VPORrr:
22581 return true;
22582 }
22583 return false;
22584}
22585
22586bool isVPSUBB(unsigned Opcode) {
22587 switch (Opcode) {
22588 case VPSUBBYrm:
22589 case VPSUBBYrr:
22590 case VPSUBBZ128rm:
22591 case VPSUBBZ128rmk:
22592 case VPSUBBZ128rmkz:
22593 case VPSUBBZ128rr:
22594 case VPSUBBZ128rrk:
22595 case VPSUBBZ128rrkz:
22596 case VPSUBBZ256rm:
22597 case VPSUBBZ256rmk:
22598 case VPSUBBZ256rmkz:
22599 case VPSUBBZ256rr:
22600 case VPSUBBZ256rrk:
22601 case VPSUBBZ256rrkz:
22602 case VPSUBBZrm:
22603 case VPSUBBZrmk:
22604 case VPSUBBZrmkz:
22605 case VPSUBBZrr:
22606 case VPSUBBZrrk:
22607 case VPSUBBZrrkz:
22608 case VPSUBBrm:
22609 case VPSUBBrr:
22610 return true;
22611 }
22612 return false;
22613}
22614
22615bool isVPAVGB(unsigned Opcode) {
22616 switch (Opcode) {
22617 case VPAVGBYrm:
22618 case VPAVGBYrr:
22619 case VPAVGBZ128rm:
22620 case VPAVGBZ128rmk:
22621 case VPAVGBZ128rmkz:
22622 case VPAVGBZ128rr:
22623 case VPAVGBZ128rrk:
22624 case VPAVGBZ128rrkz:
22625 case VPAVGBZ256rm:
22626 case VPAVGBZ256rmk:
22627 case VPAVGBZ256rmkz:
22628 case VPAVGBZ256rr:
22629 case VPAVGBZ256rrk:
22630 case VPAVGBZ256rrkz:
22631 case VPAVGBZrm:
22632 case VPAVGBZrmk:
22633 case VPAVGBZrmkz:
22634 case VPAVGBZrr:
22635 case VPAVGBZrrk:
22636 case VPAVGBZrrkz:
22637 case VPAVGBrm:
22638 case VPAVGBrr:
22639 return true;
22640 }
22641 return false;
22642}
22643
22644bool isINSB(unsigned Opcode) {
22645 return Opcode == INSB;
22646}
22647
22648bool isFYL2X(unsigned Opcode) {
22649 return Opcode == FYL2X;
22650}
22651
22652bool isVFNMSUB132PD(unsigned Opcode) {
22653 switch (Opcode) {
22654 case VFNMSUB132PDYm:
22655 case VFNMSUB132PDYr:
22656 case VFNMSUB132PDZ128m:
22657 case VFNMSUB132PDZ128mb:
22658 case VFNMSUB132PDZ128mbk:
22659 case VFNMSUB132PDZ128mbkz:
22660 case VFNMSUB132PDZ128mk:
22661 case VFNMSUB132PDZ128mkz:
22662 case VFNMSUB132PDZ128r:
22663 case VFNMSUB132PDZ128rk:
22664 case VFNMSUB132PDZ128rkz:
22665 case VFNMSUB132PDZ256m:
22666 case VFNMSUB132PDZ256mb:
22667 case VFNMSUB132PDZ256mbk:
22668 case VFNMSUB132PDZ256mbkz:
22669 case VFNMSUB132PDZ256mk:
22670 case VFNMSUB132PDZ256mkz:
22671 case VFNMSUB132PDZ256r:
22672 case VFNMSUB132PDZ256rk:
22673 case VFNMSUB132PDZ256rkz:
22674 case VFNMSUB132PDZm:
22675 case VFNMSUB132PDZmb:
22676 case VFNMSUB132PDZmbk:
22677 case VFNMSUB132PDZmbkz:
22678 case VFNMSUB132PDZmk:
22679 case VFNMSUB132PDZmkz:
22680 case VFNMSUB132PDZr:
22681 case VFNMSUB132PDZrb:
22682 case VFNMSUB132PDZrbk:
22683 case VFNMSUB132PDZrbkz:
22684 case VFNMSUB132PDZrk:
22685 case VFNMSUB132PDZrkz:
22686 case VFNMSUB132PDm:
22687 case VFNMSUB132PDr:
22688 return true;
22689 }
22690 return false;
22691}
22692
22693bool isVFNMSUBPS(unsigned Opcode) {
22694 switch (Opcode) {
22695 case VFNMSUBPS4Ymr:
22696 case VFNMSUBPS4Yrm:
22697 case VFNMSUBPS4Yrr:
22698 case VFNMSUBPS4Yrr_REV:
22699 case VFNMSUBPS4mr:
22700 case VFNMSUBPS4rm:
22701 case VFNMSUBPS4rr:
22702 case VFNMSUBPS4rr_REV:
22703 return true;
22704 }
22705 return false;
22706}
22707
22708bool isVFMADD231PS(unsigned Opcode) {
22709 switch (Opcode) {
22710 case VFMADD231PSYm:
22711 case VFMADD231PSYr:
22712 case VFMADD231PSZ128m:
22713 case VFMADD231PSZ128mb:
22714 case VFMADD231PSZ128mbk:
22715 case VFMADD231PSZ128mbkz:
22716 case VFMADD231PSZ128mk:
22717 case VFMADD231PSZ128mkz:
22718 case VFMADD231PSZ128r:
22719 case VFMADD231PSZ128rk:
22720 case VFMADD231PSZ128rkz:
22721 case VFMADD231PSZ256m:
22722 case VFMADD231PSZ256mb:
22723 case VFMADD231PSZ256mbk:
22724 case VFMADD231PSZ256mbkz:
22725 case VFMADD231PSZ256mk:
22726 case VFMADD231PSZ256mkz:
22727 case VFMADD231PSZ256r:
22728 case VFMADD231PSZ256rk:
22729 case VFMADD231PSZ256rkz:
22730 case VFMADD231PSZm:
22731 case VFMADD231PSZmb:
22732 case VFMADD231PSZmbk:
22733 case VFMADD231PSZmbkz:
22734 case VFMADD231PSZmk:
22735 case VFMADD231PSZmkz:
22736 case VFMADD231PSZr:
22737 case VFMADD231PSZrb:
22738 case VFMADD231PSZrbk:
22739 case VFMADD231PSZrbkz:
22740 case VFMADD231PSZrk:
22741 case VFMADD231PSZrkz:
22742 case VFMADD231PSm:
22743 case VFMADD231PSr:
22744 return true;
22745 }
22746 return false;
22747}
22748
22749bool isVCVTTSS2SI(unsigned Opcode) {
22750 switch (Opcode) {
22751 case VCVTTSS2SI64Zrm_Int:
22752 case VCVTTSS2SI64Zrr_Int:
22753 case VCVTTSS2SI64Zrrb_Int:
22754 case VCVTTSS2SI64rm_Int:
22755 case VCVTTSS2SI64rr_Int:
22756 case VCVTTSS2SIZrm_Int:
22757 case VCVTTSS2SIZrr_Int:
22758 case VCVTTSS2SIZrrb_Int:
22759 case VCVTTSS2SIrm_Int:
22760 case VCVTTSS2SIrr_Int:
22761 return true;
22762 }
22763 return false;
22764}
22765
22766bool isTCMMRLFP16PS(unsigned Opcode) {
22767 return Opcode == TCMMRLFP16PS;
22768}
22769
22770bool isFCOMPP(unsigned Opcode) {
22771 return Opcode == FCOMPP;
22772}
22773
22774bool isMOVD(unsigned Opcode) {
22775 switch (Opcode) {
22776 case MMX_MOVD64grr:
22777 case MMX_MOVD64mr:
22778 case MMX_MOVD64rm:
22779 case MMX_MOVD64rr:
22780 case MOVDI2PDIrm:
22781 case MOVDI2PDIrr:
22782 case MOVPDI2DImr:
22783 case MOVPDI2DIrr:
22784 return true;
22785 }
22786 return false;
22787}
22788
22789bool isMOVBE(unsigned Opcode) {
22790 switch (Opcode) {
22791 case MOVBE16mr:
22792 case MOVBE16mr_EVEX:
22793 case MOVBE16rm:
22794 case MOVBE16rm_EVEX:
22795 case MOVBE16rr:
22796 case MOVBE16rr_REV:
22797 case MOVBE32mr:
22798 case MOVBE32mr_EVEX:
22799 case MOVBE32rm:
22800 case MOVBE32rm_EVEX:
22801 case MOVBE32rr:
22802 case MOVBE32rr_REV:
22803 case MOVBE64mr:
22804 case MOVBE64mr_EVEX:
22805 case MOVBE64rm:
22806 case MOVBE64rm_EVEX:
22807 case MOVBE64rr:
22808 case MOVBE64rr_REV:
22809 return true;
22810 }
22811 return false;
22812}
22813
22814bool isVP2INTERSECTD(unsigned Opcode) {
22815 switch (Opcode) {
22816 case VP2INTERSECTDZ128rm:
22817 case VP2INTERSECTDZ128rmb:
22818 case VP2INTERSECTDZ128rr:
22819 case VP2INTERSECTDZ256rm:
22820 case VP2INTERSECTDZ256rmb:
22821 case VP2INTERSECTDZ256rr:
22822 case VP2INTERSECTDZrm:
22823 case VP2INTERSECTDZrmb:
22824 case VP2INTERSECTDZrr:
22825 return true;
22826 }
22827 return false;
22828}
22829
22830bool isVPMULLQ(unsigned Opcode) {
22831 switch (Opcode) {
22832 case VPMULLQZ128rm:
22833 case VPMULLQZ128rmb:
22834 case VPMULLQZ128rmbk:
22835 case VPMULLQZ128rmbkz:
22836 case VPMULLQZ128rmk:
22837 case VPMULLQZ128rmkz:
22838 case VPMULLQZ128rr:
22839 case VPMULLQZ128rrk:
22840 case VPMULLQZ128rrkz:
22841 case VPMULLQZ256rm:
22842 case VPMULLQZ256rmb:
22843 case VPMULLQZ256rmbk:
22844 case VPMULLQZ256rmbkz:
22845 case VPMULLQZ256rmk:
22846 case VPMULLQZ256rmkz:
22847 case VPMULLQZ256rr:
22848 case VPMULLQZ256rrk:
22849 case VPMULLQZ256rrkz:
22850 case VPMULLQZrm:
22851 case VPMULLQZrmb:
22852 case VPMULLQZrmbk:
22853 case VPMULLQZrmbkz:
22854 case VPMULLQZrmk:
22855 case VPMULLQZrmkz:
22856 case VPMULLQZrr:
22857 case VPMULLQZrrk:
22858 case VPMULLQZrrkz:
22859 return true;
22860 }
22861 return false;
22862}
22863
22864bool isVSCALEFPS(unsigned Opcode) {
22865 switch (Opcode) {
22866 case VSCALEFPSZ128rm:
22867 case VSCALEFPSZ128rmb:
22868 case VSCALEFPSZ128rmbk:
22869 case VSCALEFPSZ128rmbkz:
22870 case VSCALEFPSZ128rmk:
22871 case VSCALEFPSZ128rmkz:
22872 case VSCALEFPSZ128rr:
22873 case VSCALEFPSZ128rrk:
22874 case VSCALEFPSZ128rrkz:
22875 case VSCALEFPSZ256rm:
22876 case VSCALEFPSZ256rmb:
22877 case VSCALEFPSZ256rmbk:
22878 case VSCALEFPSZ256rmbkz:
22879 case VSCALEFPSZ256rmk:
22880 case VSCALEFPSZ256rmkz:
22881 case VSCALEFPSZ256rr:
22882 case VSCALEFPSZ256rrk:
22883 case VSCALEFPSZ256rrkz:
22884 case VSCALEFPSZrm:
22885 case VSCALEFPSZrmb:
22886 case VSCALEFPSZrmbk:
22887 case VSCALEFPSZrmbkz:
22888 case VSCALEFPSZrmk:
22889 case VSCALEFPSZrmkz:
22890 case VSCALEFPSZrr:
22891 case VSCALEFPSZrrb:
22892 case VSCALEFPSZrrbk:
22893 case VSCALEFPSZrrbkz:
22894 case VSCALEFPSZrrk:
22895 case VSCALEFPSZrrkz:
22896 return true;
22897 }
22898 return false;
22899}
22900
22901bool isVPMACSDQH(unsigned Opcode) {
22902 switch (Opcode) {
22903 case VPMACSDQHrm:
22904 case VPMACSDQHrr:
22905 return true;
22906 }
22907 return false;
22908}
22909
22910bool isVPTESTNMD(unsigned Opcode) {
22911 switch (Opcode) {
22912 case VPTESTNMDZ128rm:
22913 case VPTESTNMDZ128rmb:
22914 case VPTESTNMDZ128rmbk:
22915 case VPTESTNMDZ128rmk:
22916 case VPTESTNMDZ128rr:
22917 case VPTESTNMDZ128rrk:
22918 case VPTESTNMDZ256rm:
22919 case VPTESTNMDZ256rmb:
22920 case VPTESTNMDZ256rmbk:
22921 case VPTESTNMDZ256rmk:
22922 case VPTESTNMDZ256rr:
22923 case VPTESTNMDZ256rrk:
22924 case VPTESTNMDZrm:
22925 case VPTESTNMDZrmb:
22926 case VPTESTNMDZrmbk:
22927 case VPTESTNMDZrmk:
22928 case VPTESTNMDZrr:
22929 case VPTESTNMDZrrk:
22930 return true;
22931 }
22932 return false;
22933}
22934
22935bool isFCOMP(unsigned Opcode) {
22936 switch (Opcode) {
22937 case COMP_FST0r:
22938 case FCOMP32m:
22939 case FCOMP64m:
22940 return true;
22941 }
22942 return false;
22943}
22944
22945bool isPREFETCHWT1(unsigned Opcode) {
22946 return Opcode == PREFETCHWT1;
22947}
22948
22949bool isVCMPSD(unsigned Opcode) {
22950 switch (Opcode) {
22951 case VCMPSDZrmi_Int:
22952 case VCMPSDZrmik_Int:
22953 case VCMPSDZrri_Int:
22954 case VCMPSDZrrib_Int:
22955 case VCMPSDZrribk_Int:
22956 case VCMPSDZrrik_Int:
22957 case VCMPSDrmi_Int:
22958 case VCMPSDrri_Int:
22959 return true;
22960 }
22961 return false;
22962}
22963
22964bool isSGDTD(unsigned Opcode) {
22965 return Opcode == SGDT32m;
22966}
22967
22968bool isWRUSSD(unsigned Opcode) {
22969 switch (Opcode) {
22970 case WRUSSD:
22971 case WRUSSD_EVEX:
22972 return true;
22973 }
22974 return false;
22975}
22976
22977bool isFSUBP(unsigned Opcode) {
22978 return Opcode == SUB_FPrST0;
22979}
22980
22981bool isVUNPCKLPS(unsigned Opcode) {
22982 switch (Opcode) {
22983 case VUNPCKLPSYrm:
22984 case VUNPCKLPSYrr:
22985 case VUNPCKLPSZ128rm:
22986 case VUNPCKLPSZ128rmb:
22987 case VUNPCKLPSZ128rmbk:
22988 case VUNPCKLPSZ128rmbkz:
22989 case VUNPCKLPSZ128rmk:
22990 case VUNPCKLPSZ128rmkz:
22991 case VUNPCKLPSZ128rr:
22992 case VUNPCKLPSZ128rrk:
22993 case VUNPCKLPSZ128rrkz:
22994 case VUNPCKLPSZ256rm:
22995 case VUNPCKLPSZ256rmb:
22996 case VUNPCKLPSZ256rmbk:
22997 case VUNPCKLPSZ256rmbkz:
22998 case VUNPCKLPSZ256rmk:
22999 case VUNPCKLPSZ256rmkz:
23000 case VUNPCKLPSZ256rr:
23001 case VUNPCKLPSZ256rrk:
23002 case VUNPCKLPSZ256rrkz:
23003 case VUNPCKLPSZrm:
23004 case VUNPCKLPSZrmb:
23005 case VUNPCKLPSZrmbk:
23006 case VUNPCKLPSZrmbkz:
23007 case VUNPCKLPSZrmk:
23008 case VUNPCKLPSZrmkz:
23009 case VUNPCKLPSZrr:
23010 case VUNPCKLPSZrrk:
23011 case VUNPCKLPSZrrkz:
23012 case VUNPCKLPSrm:
23013 case VUNPCKLPSrr:
23014 return true;
23015 }
23016 return false;
23017}
23018
23019bool isVFNMSUB213SS(unsigned Opcode) {
23020 switch (Opcode) {
23021 case VFNMSUB213SSZm_Int:
23022 case VFNMSUB213SSZmk_Int:
23023 case VFNMSUB213SSZmkz_Int:
23024 case VFNMSUB213SSZr_Int:
23025 case VFNMSUB213SSZrb_Int:
23026 case VFNMSUB213SSZrbk_Int:
23027 case VFNMSUB213SSZrbkz_Int:
23028 case VFNMSUB213SSZrk_Int:
23029 case VFNMSUB213SSZrkz_Int:
23030 case VFNMSUB213SSm_Int:
23031 case VFNMSUB213SSr_Int:
23032 return true;
23033 }
23034 return false;
23035}
23036
23037bool isROUNDPD(unsigned Opcode) {
23038 switch (Opcode) {
23039 case ROUNDPDmi:
23040 case ROUNDPDri:
23041 return true;
23042 }
23043 return false;
23044}
23045
23046bool isVPMAXSW(unsigned Opcode) {
23047 switch (Opcode) {
23048 case VPMAXSWYrm:
23049 case VPMAXSWYrr:
23050 case VPMAXSWZ128rm:
23051 case VPMAXSWZ128rmk:
23052 case VPMAXSWZ128rmkz:
23053 case VPMAXSWZ128rr:
23054 case VPMAXSWZ128rrk:
23055 case VPMAXSWZ128rrkz:
23056 case VPMAXSWZ256rm:
23057 case VPMAXSWZ256rmk:
23058 case VPMAXSWZ256rmkz:
23059 case VPMAXSWZ256rr:
23060 case VPMAXSWZ256rrk:
23061 case VPMAXSWZ256rrkz:
23062 case VPMAXSWZrm:
23063 case VPMAXSWZrmk:
23064 case VPMAXSWZrmkz:
23065 case VPMAXSWZrr:
23066 case VPMAXSWZrrk:
23067 case VPMAXSWZrrkz:
23068 case VPMAXSWrm:
23069 case VPMAXSWrr:
23070 return true;
23071 }
23072 return false;
23073}
23074
23075bool isVCVTTPH2DQ(unsigned Opcode) {
23076 switch (Opcode) {
23077 case VCVTTPH2DQZ128rm:
23078 case VCVTTPH2DQZ128rmb:
23079 case VCVTTPH2DQZ128rmbk:
23080 case VCVTTPH2DQZ128rmbkz:
23081 case VCVTTPH2DQZ128rmk:
23082 case VCVTTPH2DQZ128rmkz:
23083 case VCVTTPH2DQZ128rr:
23084 case VCVTTPH2DQZ128rrk:
23085 case VCVTTPH2DQZ128rrkz:
23086 case VCVTTPH2DQZ256rm:
23087 case VCVTTPH2DQZ256rmb:
23088 case VCVTTPH2DQZ256rmbk:
23089 case VCVTTPH2DQZ256rmbkz:
23090 case VCVTTPH2DQZ256rmk:
23091 case VCVTTPH2DQZ256rmkz:
23092 case VCVTTPH2DQZ256rr:
23093 case VCVTTPH2DQZ256rrk:
23094 case VCVTTPH2DQZ256rrkz:
23095 case VCVTTPH2DQZrm:
23096 case VCVTTPH2DQZrmb:
23097 case VCVTTPH2DQZrmbk:
23098 case VCVTTPH2DQZrmbkz:
23099 case VCVTTPH2DQZrmk:
23100 case VCVTTPH2DQZrmkz:
23101 case VCVTTPH2DQZrr:
23102 case VCVTTPH2DQZrrb:
23103 case VCVTTPH2DQZrrbk:
23104 case VCVTTPH2DQZrrbkz:
23105 case VCVTTPH2DQZrrk:
23106 case VCVTTPH2DQZrrkz:
23107 return true;
23108 }
23109 return false;
23110}
23111
23112bool isVPUNPCKLWD(unsigned Opcode) {
23113 switch (Opcode) {
23114 case VPUNPCKLWDYrm:
23115 case VPUNPCKLWDYrr:
23116 case VPUNPCKLWDZ128rm:
23117 case VPUNPCKLWDZ128rmk:
23118 case VPUNPCKLWDZ128rmkz:
23119 case VPUNPCKLWDZ128rr:
23120 case VPUNPCKLWDZ128rrk:
23121 case VPUNPCKLWDZ128rrkz:
23122 case VPUNPCKLWDZ256rm:
23123 case VPUNPCKLWDZ256rmk:
23124 case VPUNPCKLWDZ256rmkz:
23125 case VPUNPCKLWDZ256rr:
23126 case VPUNPCKLWDZ256rrk:
23127 case VPUNPCKLWDZ256rrkz:
23128 case VPUNPCKLWDZrm:
23129 case VPUNPCKLWDZrmk:
23130 case VPUNPCKLWDZrmkz:
23131 case VPUNPCKLWDZrr:
23132 case VPUNPCKLWDZrrk:
23133 case VPUNPCKLWDZrrkz:
23134 case VPUNPCKLWDrm:
23135 case VPUNPCKLWDrr:
23136 return true;
23137 }
23138 return false;
23139}
23140
23141bool isKSHIFTLD(unsigned Opcode) {
23142 return Opcode == KSHIFTLDki;
23143}
23144
23145bool isTCVTROWPS2BF16H(unsigned Opcode) {
23146 switch (Opcode) {
23147 case TCVTROWPS2BF16Hrre:
23148 case TCVTROWPS2BF16Hrri:
23149 return true;
23150 }
23151 return false;
23152}
23153
23154bool isVFMADD231SD(unsigned Opcode) {
23155 switch (Opcode) {
23156 case VFMADD231SDZm_Int:
23157 case VFMADD231SDZmk_Int:
23158 case VFMADD231SDZmkz_Int:
23159 case VFMADD231SDZr_Int:
23160 case VFMADD231SDZrb_Int:
23161 case VFMADD231SDZrbk_Int:
23162 case VFMADD231SDZrbkz_Int:
23163 case VFMADD231SDZrk_Int:
23164 case VFMADD231SDZrkz_Int:
23165 case VFMADD231SDm_Int:
23166 case VFMADD231SDr_Int:
23167 return true;
23168 }
23169 return false;
23170}
23171
23172bool isADDPS(unsigned Opcode) {
23173 switch (Opcode) {
23174 case ADDPSrm:
23175 case ADDPSrr:
23176 return true;
23177 }
23178 return false;
23179}
23180
23181bool isVPSLLVD(unsigned Opcode) {
23182 switch (Opcode) {
23183 case VPSLLVDYrm:
23184 case VPSLLVDYrr:
23185 case VPSLLVDZ128rm:
23186 case VPSLLVDZ128rmb:
23187 case VPSLLVDZ128rmbk:
23188 case VPSLLVDZ128rmbkz:
23189 case VPSLLVDZ128rmk:
23190 case VPSLLVDZ128rmkz:
23191 case VPSLLVDZ128rr:
23192 case VPSLLVDZ128rrk:
23193 case VPSLLVDZ128rrkz:
23194 case VPSLLVDZ256rm:
23195 case VPSLLVDZ256rmb:
23196 case VPSLLVDZ256rmbk:
23197 case VPSLLVDZ256rmbkz:
23198 case VPSLLVDZ256rmk:
23199 case VPSLLVDZ256rmkz:
23200 case VPSLLVDZ256rr:
23201 case VPSLLVDZ256rrk:
23202 case VPSLLVDZ256rrkz:
23203 case VPSLLVDZrm:
23204 case VPSLLVDZrmb:
23205 case VPSLLVDZrmbk:
23206 case VPSLLVDZrmbkz:
23207 case VPSLLVDZrmk:
23208 case VPSLLVDZrmkz:
23209 case VPSLLVDZrr:
23210 case VPSLLVDZrrk:
23211 case VPSLLVDZrrkz:
23212 case VPSLLVDrm:
23213 case VPSLLVDrr:
23214 return true;
23215 }
23216 return false;
23217}
23218
23219bool isVFNMADD132SH(unsigned Opcode) {
23220 switch (Opcode) {
23221 case VFNMADD132SHZm_Int:
23222 case VFNMADD132SHZmk_Int:
23223 case VFNMADD132SHZmkz_Int:
23224 case VFNMADD132SHZr_Int:
23225 case VFNMADD132SHZrb_Int:
23226 case VFNMADD132SHZrbk_Int:
23227 case VFNMADD132SHZrbkz_Int:
23228 case VFNMADD132SHZrk_Int:
23229 case VFNMADD132SHZrkz_Int:
23230 return true;
23231 }
23232 return false;
23233}
23234
23235bool isVMOVNTPS(unsigned Opcode) {
23236 switch (Opcode) {
23237 case VMOVNTPSYmr:
23238 case VMOVNTPSZ128mr:
23239 case VMOVNTPSZ256mr:
23240 case VMOVNTPSZmr:
23241 case VMOVNTPSmr:
23242 return true;
23243 }
23244 return false;
23245}
23246
23247bool isVCVTPD2DQ(unsigned Opcode) {
23248 switch (Opcode) {
23249 case VCVTPD2DQYrm:
23250 case VCVTPD2DQYrr:
23251 case VCVTPD2DQZ128rm:
23252 case VCVTPD2DQZ128rmb:
23253 case VCVTPD2DQZ128rmbk:
23254 case VCVTPD2DQZ128rmbkz:
23255 case VCVTPD2DQZ128rmk:
23256 case VCVTPD2DQZ128rmkz:
23257 case VCVTPD2DQZ128rr:
23258 case VCVTPD2DQZ128rrk:
23259 case VCVTPD2DQZ128rrkz:
23260 case VCVTPD2DQZ256rm:
23261 case VCVTPD2DQZ256rmb:
23262 case VCVTPD2DQZ256rmbk:
23263 case VCVTPD2DQZ256rmbkz:
23264 case VCVTPD2DQZ256rmk:
23265 case VCVTPD2DQZ256rmkz:
23266 case VCVTPD2DQZ256rr:
23267 case VCVTPD2DQZ256rrk:
23268 case VCVTPD2DQZ256rrkz:
23269 case VCVTPD2DQZrm:
23270 case VCVTPD2DQZrmb:
23271 case VCVTPD2DQZrmbk:
23272 case VCVTPD2DQZrmbkz:
23273 case VCVTPD2DQZrmk:
23274 case VCVTPD2DQZrmkz:
23275 case VCVTPD2DQZrr:
23276 case VCVTPD2DQZrrb:
23277 case VCVTPD2DQZrrbk:
23278 case VCVTPD2DQZrrbkz:
23279 case VCVTPD2DQZrrk:
23280 case VCVTPD2DQZrrkz:
23281 case VCVTPD2DQrm:
23282 case VCVTPD2DQrr:
23283 return true;
23284 }
23285 return false;
23286}
23287
23288bool isVPXOR(unsigned Opcode) {
23289 switch (Opcode) {
23290 case VPXORYrm:
23291 case VPXORYrr:
23292 case VPXORrm:
23293 case VPXORrr:
23294 return true;
23295 }
23296 return false;
23297}
23298
23299bool isSTMXCSR(unsigned Opcode) {
23300 return Opcode == STMXCSR;
23301}
23302
23303bool isVRCP14SS(unsigned Opcode) {
23304 switch (Opcode) {
23305 case VRCP14SSZrm:
23306 case VRCP14SSZrmk:
23307 case VRCP14SSZrmkz:
23308 case VRCP14SSZrr:
23309 case VRCP14SSZrrk:
23310 case VRCP14SSZrrkz:
23311 return true;
23312 }
23313 return false;
23314}
23315
23316bool isUD2(unsigned Opcode) {
23317 return Opcode == TRAP;
23318}
23319
23320bool isVPOPCNTW(unsigned Opcode) {
23321 switch (Opcode) {
23322 case VPOPCNTWZ128rm:
23323 case VPOPCNTWZ128rmk:
23324 case VPOPCNTWZ128rmkz:
23325 case VPOPCNTWZ128rr:
23326 case VPOPCNTWZ128rrk:
23327 case VPOPCNTWZ128rrkz:
23328 case VPOPCNTWZ256rm:
23329 case VPOPCNTWZ256rmk:
23330 case VPOPCNTWZ256rmkz:
23331 case VPOPCNTWZ256rr:
23332 case VPOPCNTWZ256rrk:
23333 case VPOPCNTWZ256rrkz:
23334 case VPOPCNTWZrm:
23335 case VPOPCNTWZrmk:
23336 case VPOPCNTWZrmkz:
23337 case VPOPCNTWZrr:
23338 case VPOPCNTWZrrk:
23339 case VPOPCNTWZrrkz:
23340 return true;
23341 }
23342 return false;
23343}
23344
23345bool isVRSQRTSH(unsigned Opcode) {
23346 switch (Opcode) {
23347 case VRSQRTSHZrm:
23348 case VRSQRTSHZrmk:
23349 case VRSQRTSHZrmkz:
23350 case VRSQRTSHZrr:
23351 case VRSQRTSHZrrk:
23352 case VRSQRTSHZrrkz:
23353 return true;
23354 }
23355 return false;
23356}
23357
23358bool isVSCATTERPF0DPD(unsigned Opcode) {
23359 return Opcode == VSCATTERPF0DPDm;
23360}
23361
23362bool isVFMADDPS(unsigned Opcode) {
23363 switch (Opcode) {
23364 case VFMADDPS4Ymr:
23365 case VFMADDPS4Yrm:
23366 case VFMADDPS4Yrr:
23367 case VFMADDPS4Yrr_REV:
23368 case VFMADDPS4mr:
23369 case VFMADDPS4rm:
23370 case VFMADDPS4rr:
23371 case VFMADDPS4rr_REV:
23372 return true;
23373 }
23374 return false;
23375}
23376
23377bool isXSAVEC64(unsigned Opcode) {
23378 return Opcode == XSAVEC64;
23379}
23380
23381bool isVPMADDUBSW(unsigned Opcode) {
23382 switch (Opcode) {
23383 case VPMADDUBSWYrm:
23384 case VPMADDUBSWYrr:
23385 case VPMADDUBSWZ128rm:
23386 case VPMADDUBSWZ128rmk:
23387 case VPMADDUBSWZ128rmkz:
23388 case VPMADDUBSWZ128rr:
23389 case VPMADDUBSWZ128rrk:
23390 case VPMADDUBSWZ128rrkz:
23391 case VPMADDUBSWZ256rm:
23392 case VPMADDUBSWZ256rmk:
23393 case VPMADDUBSWZ256rmkz:
23394 case VPMADDUBSWZ256rr:
23395 case VPMADDUBSWZ256rrk:
23396 case VPMADDUBSWZ256rrkz:
23397 case VPMADDUBSWZrm:
23398 case VPMADDUBSWZrmk:
23399 case VPMADDUBSWZrmkz:
23400 case VPMADDUBSWZrr:
23401 case VPMADDUBSWZrrk:
23402 case VPMADDUBSWZrrkz:
23403 case VPMADDUBSWrm:
23404 case VPMADDUBSWrr:
23405 return true;
23406 }
23407 return false;
23408}
23409
23410bool isVPMOVZXDQ(unsigned Opcode) {
23411 switch (Opcode) {
23412 case VPMOVZXDQYrm:
23413 case VPMOVZXDQYrr:
23414 case VPMOVZXDQZ128rm:
23415 case VPMOVZXDQZ128rmk:
23416 case VPMOVZXDQZ128rmkz:
23417 case VPMOVZXDQZ128rr:
23418 case VPMOVZXDQZ128rrk:
23419 case VPMOVZXDQZ128rrkz:
23420 case VPMOVZXDQZ256rm:
23421 case VPMOVZXDQZ256rmk:
23422 case VPMOVZXDQZ256rmkz:
23423 case VPMOVZXDQZ256rr:
23424 case VPMOVZXDQZ256rrk:
23425 case VPMOVZXDQZ256rrkz:
23426 case VPMOVZXDQZrm:
23427 case VPMOVZXDQZrmk:
23428 case VPMOVZXDQZrmkz:
23429 case VPMOVZXDQZrr:
23430 case VPMOVZXDQZrrk:
23431 case VPMOVZXDQZrrkz:
23432 case VPMOVZXDQrm:
23433 case VPMOVZXDQrr:
23434 return true;
23435 }
23436 return false;
23437}
23438
23439bool isVRCP14PS(unsigned Opcode) {
23440 switch (Opcode) {
23441 case VRCP14PSZ128m:
23442 case VRCP14PSZ128mb:
23443 case VRCP14PSZ128mbk:
23444 case VRCP14PSZ128mbkz:
23445 case VRCP14PSZ128mk:
23446 case VRCP14PSZ128mkz:
23447 case VRCP14PSZ128r:
23448 case VRCP14PSZ128rk:
23449 case VRCP14PSZ128rkz:
23450 case VRCP14PSZ256m:
23451 case VRCP14PSZ256mb:
23452 case VRCP14PSZ256mbk:
23453 case VRCP14PSZ256mbkz:
23454 case VRCP14PSZ256mk:
23455 case VRCP14PSZ256mkz:
23456 case VRCP14PSZ256r:
23457 case VRCP14PSZ256rk:
23458 case VRCP14PSZ256rkz:
23459 case VRCP14PSZm:
23460 case VRCP14PSZmb:
23461 case VRCP14PSZmbk:
23462 case VRCP14PSZmbkz:
23463 case VRCP14PSZmk:
23464 case VRCP14PSZmkz:
23465 case VRCP14PSZr:
23466 case VRCP14PSZrk:
23467 case VRCP14PSZrkz:
23468 return true;
23469 }
23470 return false;
23471}
23472
23473bool isTCONJTCMMIMFP16PS(unsigned Opcode) {
23474 return Opcode == TCONJTCMMIMFP16PS;
23475}
23476
23477bool isVSQRTSH(unsigned Opcode) {
23478 switch (Opcode) {
23479 case VSQRTSHZm_Int:
23480 case VSQRTSHZmk_Int:
23481 case VSQRTSHZmkz_Int:
23482 case VSQRTSHZr_Int:
23483 case VSQRTSHZrb_Int:
23484 case VSQRTSHZrbk_Int:
23485 case VSQRTSHZrbkz_Int:
23486 case VSQRTSHZrk_Int:
23487 case VSQRTSHZrkz_Int:
23488 return true;
23489 }
23490 return false;
23491}
23492
23493bool isTCVTROWD2PS(unsigned Opcode) {
23494 switch (Opcode) {
23495 case TCVTROWD2PSrre:
23496 case TCVTROWD2PSrri:
23497 return true;
23498 }
23499 return false;
23500}
23501
23502bool isLOOP(unsigned Opcode) {
23503 return Opcode == LOOP;
23504}
23505
23506bool isSTUI(unsigned Opcode) {
23507 return Opcode == STUI;
23508}
23509
23510bool isVCVTTPS2UDQ(unsigned Opcode) {
23511 switch (Opcode) {
23512 case VCVTTPS2UDQZ128rm:
23513 case VCVTTPS2UDQZ128rmb:
23514 case VCVTTPS2UDQZ128rmbk:
23515 case VCVTTPS2UDQZ128rmbkz:
23516 case VCVTTPS2UDQZ128rmk:
23517 case VCVTTPS2UDQZ128rmkz:
23518 case VCVTTPS2UDQZ128rr:
23519 case VCVTTPS2UDQZ128rrk:
23520 case VCVTTPS2UDQZ128rrkz:
23521 case VCVTTPS2UDQZ256rm:
23522 case VCVTTPS2UDQZ256rmb:
23523 case VCVTTPS2UDQZ256rmbk:
23524 case VCVTTPS2UDQZ256rmbkz:
23525 case VCVTTPS2UDQZ256rmk:
23526 case VCVTTPS2UDQZ256rmkz:
23527 case VCVTTPS2UDQZ256rr:
23528 case VCVTTPS2UDQZ256rrk:
23529 case VCVTTPS2UDQZ256rrkz:
23530 case VCVTTPS2UDQZrm:
23531 case VCVTTPS2UDQZrmb:
23532 case VCVTTPS2UDQZrmbk:
23533 case VCVTTPS2UDQZrmbkz:
23534 case VCVTTPS2UDQZrmk:
23535 case VCVTTPS2UDQZrmkz:
23536 case VCVTTPS2UDQZrr:
23537 case VCVTTPS2UDQZrrb:
23538 case VCVTTPS2UDQZrrbk:
23539 case VCVTTPS2UDQZrrbkz:
23540 case VCVTTPS2UDQZrrk:
23541 case VCVTTPS2UDQZrrkz:
23542 return true;
23543 }
23544 return false;
23545}
23546
23547bool isVCOMPRESSPS(unsigned Opcode) {
23548 switch (Opcode) {
23549 case VCOMPRESSPSZ128mr:
23550 case VCOMPRESSPSZ128mrk:
23551 case VCOMPRESSPSZ128rr:
23552 case VCOMPRESSPSZ128rrk:
23553 case VCOMPRESSPSZ128rrkz:
23554 case VCOMPRESSPSZ256mr:
23555 case VCOMPRESSPSZ256mrk:
23556 case VCOMPRESSPSZ256rr:
23557 case VCOMPRESSPSZ256rrk:
23558 case VCOMPRESSPSZ256rrkz:
23559 case VCOMPRESSPSZmr:
23560 case VCOMPRESSPSZmrk:
23561 case VCOMPRESSPSZrr:
23562 case VCOMPRESSPSZrrk:
23563 case VCOMPRESSPSZrrkz:
23564 return true;
23565 }
23566 return false;
23567}
23568
23569bool isTTDPBF16PS(unsigned Opcode) {
23570 return Opcode == TTDPBF16PS;
23571}
23572
23573bool isVCVTTBF162IUBS(unsigned Opcode) {
23574 switch (Opcode) {
23575 case VCVTTBF162IUBSZ128rm:
23576 case VCVTTBF162IUBSZ128rmb:
23577 case VCVTTBF162IUBSZ128rmbk:
23578 case VCVTTBF162IUBSZ128rmbkz:
23579 case VCVTTBF162IUBSZ128rmk:
23580 case VCVTTBF162IUBSZ128rmkz:
23581 case VCVTTBF162IUBSZ128rr:
23582 case VCVTTBF162IUBSZ128rrk:
23583 case VCVTTBF162IUBSZ128rrkz:
23584 case VCVTTBF162IUBSZ256rm:
23585 case VCVTTBF162IUBSZ256rmb:
23586 case VCVTTBF162IUBSZ256rmbk:
23587 case VCVTTBF162IUBSZ256rmbkz:
23588 case VCVTTBF162IUBSZ256rmk:
23589 case VCVTTBF162IUBSZ256rmkz:
23590 case VCVTTBF162IUBSZ256rr:
23591 case VCVTTBF162IUBSZ256rrk:
23592 case VCVTTBF162IUBSZ256rrkz:
23593 case VCVTTBF162IUBSZrm:
23594 case VCVTTBF162IUBSZrmb:
23595 case VCVTTBF162IUBSZrmbk:
23596 case VCVTTBF162IUBSZrmbkz:
23597 case VCVTTBF162IUBSZrmk:
23598 case VCVTTBF162IUBSZrmkz:
23599 case VCVTTBF162IUBSZrr:
23600 case VCVTTBF162IUBSZrrk:
23601 case VCVTTBF162IUBSZrrkz:
23602 return true;
23603 }
23604 return false;
23605}
23606
23607bool isVPADDW(unsigned Opcode) {
23608 switch (Opcode) {
23609 case VPADDWYrm:
23610 case VPADDWYrr:
23611 case VPADDWZ128rm:
23612 case VPADDWZ128rmk:
23613 case VPADDWZ128rmkz:
23614 case VPADDWZ128rr:
23615 case VPADDWZ128rrk:
23616 case VPADDWZ128rrkz:
23617 case VPADDWZ256rm:
23618 case VPADDWZ256rmk:
23619 case VPADDWZ256rmkz:
23620 case VPADDWZ256rr:
23621 case VPADDWZ256rrk:
23622 case VPADDWZ256rrkz:
23623 case VPADDWZrm:
23624 case VPADDWZrmk:
23625 case VPADDWZrmkz:
23626 case VPADDWZrr:
23627 case VPADDWZrrk:
23628 case VPADDWZrrkz:
23629 case VPADDWrm:
23630 case VPADDWrr:
23631 return true;
23632 }
23633 return false;
23634}
23635
23636bool isVRNDSCALEPS(unsigned Opcode) {
23637 switch (Opcode) {
23638 case VRNDSCALEPSZ128rmbi:
23639 case VRNDSCALEPSZ128rmbik:
23640 case VRNDSCALEPSZ128rmbikz:
23641 case VRNDSCALEPSZ128rmi:
23642 case VRNDSCALEPSZ128rmik:
23643 case VRNDSCALEPSZ128rmikz:
23644 case VRNDSCALEPSZ128rri:
23645 case VRNDSCALEPSZ128rrik:
23646 case VRNDSCALEPSZ128rrikz:
23647 case VRNDSCALEPSZ256rmbi:
23648 case VRNDSCALEPSZ256rmbik:
23649 case VRNDSCALEPSZ256rmbikz:
23650 case VRNDSCALEPSZ256rmi:
23651 case VRNDSCALEPSZ256rmik:
23652 case VRNDSCALEPSZ256rmikz:
23653 case VRNDSCALEPSZ256rri:
23654 case VRNDSCALEPSZ256rrik:
23655 case VRNDSCALEPSZ256rrikz:
23656 case VRNDSCALEPSZrmbi:
23657 case VRNDSCALEPSZrmbik:
23658 case VRNDSCALEPSZrmbikz:
23659 case VRNDSCALEPSZrmi:
23660 case VRNDSCALEPSZrmik:
23661 case VRNDSCALEPSZrmikz:
23662 case VRNDSCALEPSZrri:
23663 case VRNDSCALEPSZrrib:
23664 case VRNDSCALEPSZrribk:
23665 case VRNDSCALEPSZrribkz:
23666 case VRNDSCALEPSZrrik:
23667 case VRNDSCALEPSZrrikz:
23668 return true;
23669 }
23670 return false;
23671}
23672
23673bool isVPSIGND(unsigned Opcode) {
23674 switch (Opcode) {
23675 case VPSIGNDYrm:
23676 case VPSIGNDYrr:
23677 case VPSIGNDrm:
23678 case VPSIGNDrr:
23679 return true;
23680 }
23681 return false;
23682}
23683
23684bool isXABORT(unsigned Opcode) {
23685 return Opcode == XABORT;
23686}
23687
23688bool isVPHADDUWD(unsigned Opcode) {
23689 switch (Opcode) {
23690 case VPHADDUWDrm:
23691 case VPHADDUWDrr:
23692 return true;
23693 }
23694 return false;
23695}
23696
23697bool isT2RPNTLVWZ1T1(unsigned Opcode) {
23698 switch (Opcode) {
23699 case T2RPNTLVWZ1T1:
23700 case T2RPNTLVWZ1T1_EVEX:
23701 return true;
23702 }
23703 return false;
23704}
23705
23706bool isVCVT2PH2HF8S(unsigned Opcode) {
23707 switch (Opcode) {
23708 case VCVT2PH2HF8SZ128rm:
23709 case VCVT2PH2HF8SZ128rmb:
23710 case VCVT2PH2HF8SZ128rmbk:
23711 case VCVT2PH2HF8SZ128rmbkz:
23712 case VCVT2PH2HF8SZ128rmk:
23713 case VCVT2PH2HF8SZ128rmkz:
23714 case VCVT2PH2HF8SZ128rr:
23715 case VCVT2PH2HF8SZ128rrk:
23716 case VCVT2PH2HF8SZ128rrkz:
23717 case VCVT2PH2HF8SZ256rm:
23718 case VCVT2PH2HF8SZ256rmb:
23719 case VCVT2PH2HF8SZ256rmbk:
23720 case VCVT2PH2HF8SZ256rmbkz:
23721 case VCVT2PH2HF8SZ256rmk:
23722 case VCVT2PH2HF8SZ256rmkz:
23723 case VCVT2PH2HF8SZ256rr:
23724 case VCVT2PH2HF8SZ256rrk:
23725 case VCVT2PH2HF8SZ256rrkz:
23726 case VCVT2PH2HF8SZrm:
23727 case VCVT2PH2HF8SZrmb:
23728 case VCVT2PH2HF8SZrmbk:
23729 case VCVT2PH2HF8SZrmbkz:
23730 case VCVT2PH2HF8SZrmk:
23731 case VCVT2PH2HF8SZrmkz:
23732 case VCVT2PH2HF8SZrr:
23733 case VCVT2PH2HF8SZrrk:
23734 case VCVT2PH2HF8SZrrkz:
23735 return true;
23736 }
23737 return false;
23738}
23739
23740bool isVDBPSADBW(unsigned Opcode) {
23741 switch (Opcode) {
23742 case VDBPSADBWZ128rmi:
23743 case VDBPSADBWZ128rmik:
23744 case VDBPSADBWZ128rmikz:
23745 case VDBPSADBWZ128rri:
23746 case VDBPSADBWZ128rrik:
23747 case VDBPSADBWZ128rrikz:
23748 case VDBPSADBWZ256rmi:
23749 case VDBPSADBWZ256rmik:
23750 case VDBPSADBWZ256rmikz:
23751 case VDBPSADBWZ256rri:
23752 case VDBPSADBWZ256rrik:
23753 case VDBPSADBWZ256rrikz:
23754 case VDBPSADBWZrmi:
23755 case VDBPSADBWZrmik:
23756 case VDBPSADBWZrmikz:
23757 case VDBPSADBWZrri:
23758 case VDBPSADBWZrrik:
23759 case VDBPSADBWZrrikz:
23760 return true;
23761 }
23762 return false;
23763}
23764
23765bool isPSLLW(unsigned Opcode) {
23766 switch (Opcode) {
23767 case MMX_PSLLWri:
23768 case MMX_PSLLWrm:
23769 case MMX_PSLLWrr:
23770 case PSLLWri:
23771 case PSLLWrm:
23772 case PSLLWrr:
23773 return true;
23774 }
23775 return false;
23776}
23777
23778bool isVPMOVQD(unsigned Opcode) {
23779 switch (Opcode) {
23780 case VPMOVQDZ128mr:
23781 case VPMOVQDZ128mrk:
23782 case VPMOVQDZ128rr:
23783 case VPMOVQDZ128rrk:
23784 case VPMOVQDZ128rrkz:
23785 case VPMOVQDZ256mr:
23786 case VPMOVQDZ256mrk:
23787 case VPMOVQDZ256rr:
23788 case VPMOVQDZ256rrk:
23789 case VPMOVQDZ256rrkz:
23790 case VPMOVQDZmr:
23791 case VPMOVQDZmrk:
23792 case VPMOVQDZrr:
23793 case VPMOVQDZrrk:
23794 case VPMOVQDZrrkz:
23795 return true;
23796 }
23797 return false;
23798}
23799
23800bool isVINSERTI64X4(unsigned Opcode) {
23801 switch (Opcode) {
23802 case VINSERTI64X4Zrmi:
23803 case VINSERTI64X4Zrmik:
23804 case VINSERTI64X4Zrmikz:
23805 case VINSERTI64X4Zrri:
23806 case VINSERTI64X4Zrrik:
23807 case VINSERTI64X4Zrrikz:
23808 return true;
23809 }
23810 return false;
23811}
23812
23813bool isVPERMI2PS(unsigned Opcode) {
23814 switch (Opcode) {
23815 case VPERMI2PSZ128rm:
23816 case VPERMI2PSZ128rmb:
23817 case VPERMI2PSZ128rmbk:
23818 case VPERMI2PSZ128rmbkz:
23819 case VPERMI2PSZ128rmk:
23820 case VPERMI2PSZ128rmkz:
23821 case VPERMI2PSZ128rr:
23822 case VPERMI2PSZ128rrk:
23823 case VPERMI2PSZ128rrkz:
23824 case VPERMI2PSZ256rm:
23825 case VPERMI2PSZ256rmb:
23826 case VPERMI2PSZ256rmbk:
23827 case VPERMI2PSZ256rmbkz:
23828 case VPERMI2PSZ256rmk:
23829 case VPERMI2PSZ256rmkz:
23830 case VPERMI2PSZ256rr:
23831 case VPERMI2PSZ256rrk:
23832 case VPERMI2PSZ256rrkz:
23833 case VPERMI2PSZrm:
23834 case VPERMI2PSZrmb:
23835 case VPERMI2PSZrmbk:
23836 case VPERMI2PSZrmbkz:
23837 case VPERMI2PSZrmk:
23838 case VPERMI2PSZrmkz:
23839 case VPERMI2PSZrr:
23840 case VPERMI2PSZrrk:
23841 case VPERMI2PSZrrkz:
23842 return true;
23843 }
23844 return false;
23845}
23846
23847bool isVMULPH(unsigned Opcode) {
23848 switch (Opcode) {
23849 case VMULPHZ128rm:
23850 case VMULPHZ128rmb:
23851 case VMULPHZ128rmbk:
23852 case VMULPHZ128rmbkz:
23853 case VMULPHZ128rmk:
23854 case VMULPHZ128rmkz:
23855 case VMULPHZ128rr:
23856 case VMULPHZ128rrk:
23857 case VMULPHZ128rrkz:
23858 case VMULPHZ256rm:
23859 case VMULPHZ256rmb:
23860 case VMULPHZ256rmbk:
23861 case VMULPHZ256rmbkz:
23862 case VMULPHZ256rmk:
23863 case VMULPHZ256rmkz:
23864 case VMULPHZ256rr:
23865 case VMULPHZ256rrk:
23866 case VMULPHZ256rrkz:
23867 case VMULPHZrm:
23868 case VMULPHZrmb:
23869 case VMULPHZrmbk:
23870 case VMULPHZrmbkz:
23871 case VMULPHZrmk:
23872 case VMULPHZrmkz:
23873 case VMULPHZrr:
23874 case VMULPHZrrb:
23875 case VMULPHZrrbk:
23876 case VMULPHZrrbkz:
23877 case VMULPHZrrk:
23878 case VMULPHZrrkz:
23879 return true;
23880 }
23881 return false;
23882}
23883
23884bool isVPCMPUQ(unsigned Opcode) {
23885 switch (Opcode) {
23886 case VPCMPUQZ128rmbi:
23887 case VPCMPUQZ128rmbik:
23888 case VPCMPUQZ128rmi:
23889 case VPCMPUQZ128rmik:
23890 case VPCMPUQZ128rri:
23891 case VPCMPUQZ128rrik:
23892 case VPCMPUQZ256rmbi:
23893 case VPCMPUQZ256rmbik:
23894 case VPCMPUQZ256rmi:
23895 case VPCMPUQZ256rmik:
23896 case VPCMPUQZ256rri:
23897 case VPCMPUQZ256rrik:
23898 case VPCMPUQZrmbi:
23899 case VPCMPUQZrmbik:
23900 case VPCMPUQZrmi:
23901 case VPCMPUQZrmik:
23902 case VPCMPUQZrri:
23903 case VPCMPUQZrrik:
23904 return true;
23905 }
23906 return false;
23907}
23908
23909bool isVCVTUSI2SD(unsigned Opcode) {
23910 switch (Opcode) {
23911 case VCVTUSI2SDZrm_Int:
23912 case VCVTUSI2SDZrr_Int:
23913 case VCVTUSI642SDZrm_Int:
23914 case VCVTUSI642SDZrr_Int:
23915 case VCVTUSI642SDZrrb_Int:
23916 return true;
23917 }
23918 return false;
23919}
23920
23921bool isKXNORW(unsigned Opcode) {
23922 return Opcode == KXNORWkk;
23923}
23924
23925bool isBLCIC(unsigned Opcode) {
23926 switch (Opcode) {
23927 case BLCIC32rm:
23928 case BLCIC32rr:
23929 case BLCIC64rm:
23930 case BLCIC64rr:
23931 return true;
23932 }
23933 return false;
23934}
23935
23936bool isVFNMADD213SD(unsigned Opcode) {
23937 switch (Opcode) {
23938 case VFNMADD213SDZm_Int:
23939 case VFNMADD213SDZmk_Int:
23940 case VFNMADD213SDZmkz_Int:
23941 case VFNMADD213SDZr_Int:
23942 case VFNMADD213SDZrb_Int:
23943 case VFNMADD213SDZrbk_Int:
23944 case VFNMADD213SDZrbkz_Int:
23945 case VFNMADD213SDZrk_Int:
23946 case VFNMADD213SDZrkz_Int:
23947 case VFNMADD213SDm_Int:
23948 case VFNMADD213SDr_Int:
23949 return true;
23950 }
23951 return false;
23952}
23953
23954bool isVPMACSWW(unsigned Opcode) {
23955 switch (Opcode) {
23956 case VPMACSWWrm:
23957 case VPMACSWWrr:
23958 return true;
23959 }
23960 return false;
23961}
23962
23963bool isVMOVLPS(unsigned Opcode) {
23964 switch (Opcode) {
23965 case VMOVLPSZ128mr:
23966 case VMOVLPSZ128rm:
23967 case VMOVLPSmr:
23968 case VMOVLPSrm:
23969 return true;
23970 }
23971 return false;
23972}
23973
23974bool isPCONFIG(unsigned Opcode) {
23975 return Opcode == PCONFIG;
23976}
23977
23978bool isPANDN(unsigned Opcode) {
23979 switch (Opcode) {
23980 case MMX_PANDNrm:
23981 case MMX_PANDNrr:
23982 case PANDNrm:
23983 case PANDNrr:
23984 return true;
23985 }
23986 return false;
23987}
23988
23989bool isVGETEXPPD(unsigned Opcode) {
23990 switch (Opcode) {
23991 case VGETEXPPDZ128m:
23992 case VGETEXPPDZ128mb:
23993 case VGETEXPPDZ128mbk:
23994 case VGETEXPPDZ128mbkz:
23995 case VGETEXPPDZ128mk:
23996 case VGETEXPPDZ128mkz:
23997 case VGETEXPPDZ128r:
23998 case VGETEXPPDZ128rk:
23999 case VGETEXPPDZ128rkz:
24000 case VGETEXPPDZ256m:
24001 case VGETEXPPDZ256mb:
24002 case VGETEXPPDZ256mbk:
24003 case VGETEXPPDZ256mbkz:
24004 case VGETEXPPDZ256mk:
24005 case VGETEXPPDZ256mkz:
24006 case VGETEXPPDZ256r:
24007 case VGETEXPPDZ256rk:
24008 case VGETEXPPDZ256rkz:
24009 case VGETEXPPDZm:
24010 case VGETEXPPDZmb:
24011 case VGETEXPPDZmbk:
24012 case VGETEXPPDZmbkz:
24013 case VGETEXPPDZmk:
24014 case VGETEXPPDZmkz:
24015 case VGETEXPPDZr:
24016 case VGETEXPPDZrb:
24017 case VGETEXPPDZrbk:
24018 case VGETEXPPDZrbkz:
24019 case VGETEXPPDZrk:
24020 case VGETEXPPDZrkz:
24021 return true;
24022 }
24023 return false;
24024}
24025
24026bool isVPSRLVQ(unsigned Opcode) {
24027 switch (Opcode) {
24028 case VPSRLVQYrm:
24029 case VPSRLVQYrr:
24030 case VPSRLVQZ128rm:
24031 case VPSRLVQZ128rmb:
24032 case VPSRLVQZ128rmbk:
24033 case VPSRLVQZ128rmbkz:
24034 case VPSRLVQZ128rmk:
24035 case VPSRLVQZ128rmkz:
24036 case VPSRLVQZ128rr:
24037 case VPSRLVQZ128rrk:
24038 case VPSRLVQZ128rrkz:
24039 case VPSRLVQZ256rm:
24040 case VPSRLVQZ256rmb:
24041 case VPSRLVQZ256rmbk:
24042 case VPSRLVQZ256rmbkz:
24043 case VPSRLVQZ256rmk:
24044 case VPSRLVQZ256rmkz:
24045 case VPSRLVQZ256rr:
24046 case VPSRLVQZ256rrk:
24047 case VPSRLVQZ256rrkz:
24048 case VPSRLVQZrm:
24049 case VPSRLVQZrmb:
24050 case VPSRLVQZrmbk:
24051 case VPSRLVQZrmbkz:
24052 case VPSRLVQZrmk:
24053 case VPSRLVQZrmkz:
24054 case VPSRLVQZrr:
24055 case VPSRLVQZrrk:
24056 case VPSRLVQZrrkz:
24057 case VPSRLVQrm:
24058 case VPSRLVQrr:
24059 return true;
24060 }
24061 return false;
24062}
24063
24064bool isUD1(unsigned Opcode) {
24065 switch (Opcode) {
24066 case UD1Lm:
24067 case UD1Lr:
24068 case UD1Qm:
24069 case UD1Qr:
24070 case UD1Wm:
24071 case UD1Wr:
24072 return true;
24073 }
24074 return false;
24075}
24076
24077bool isPMAXSB(unsigned Opcode) {
24078 switch (Opcode) {
24079 case PMAXSBrm:
24080 case PMAXSBrr:
24081 return true;
24082 }
24083 return false;
24084}
24085
24086bool isVPROLQ(unsigned Opcode) {
24087 switch (Opcode) {
24088 case VPROLQZ128mbi:
24089 case VPROLQZ128mbik:
24090 case VPROLQZ128mbikz:
24091 case VPROLQZ128mi:
24092 case VPROLQZ128mik:
24093 case VPROLQZ128mikz:
24094 case VPROLQZ128ri:
24095 case VPROLQZ128rik:
24096 case VPROLQZ128rikz:
24097 case VPROLQZ256mbi:
24098 case VPROLQZ256mbik:
24099 case VPROLQZ256mbikz:
24100 case VPROLQZ256mi:
24101 case VPROLQZ256mik:
24102 case VPROLQZ256mikz:
24103 case VPROLQZ256ri:
24104 case VPROLQZ256rik:
24105 case VPROLQZ256rikz:
24106 case VPROLQZmbi:
24107 case VPROLQZmbik:
24108 case VPROLQZmbikz:
24109 case VPROLQZmi:
24110 case VPROLQZmik:
24111 case VPROLQZmikz:
24112 case VPROLQZri:
24113 case VPROLQZrik:
24114 case VPROLQZrikz:
24115 return true;
24116 }
24117 return false;
24118}
24119
24120bool isVSCATTERPF1QPD(unsigned Opcode) {
24121 return Opcode == VSCATTERPF1QPDm;
24122}
24123
24124bool isVPSRLD(unsigned Opcode) {
24125 switch (Opcode) {
24126 case VPSRLDYri:
24127 case VPSRLDYrm:
24128 case VPSRLDYrr:
24129 case VPSRLDZ128mbi:
24130 case VPSRLDZ128mbik:
24131 case VPSRLDZ128mbikz:
24132 case VPSRLDZ128mi:
24133 case VPSRLDZ128mik:
24134 case VPSRLDZ128mikz:
24135 case VPSRLDZ128ri:
24136 case VPSRLDZ128rik:
24137 case VPSRLDZ128rikz:
24138 case VPSRLDZ128rm:
24139 case VPSRLDZ128rmk:
24140 case VPSRLDZ128rmkz:
24141 case VPSRLDZ128rr:
24142 case VPSRLDZ128rrk:
24143 case VPSRLDZ128rrkz:
24144 case VPSRLDZ256mbi:
24145 case VPSRLDZ256mbik:
24146 case VPSRLDZ256mbikz:
24147 case VPSRLDZ256mi:
24148 case VPSRLDZ256mik:
24149 case VPSRLDZ256mikz:
24150 case VPSRLDZ256ri:
24151 case VPSRLDZ256rik:
24152 case VPSRLDZ256rikz:
24153 case VPSRLDZ256rm:
24154 case VPSRLDZ256rmk:
24155 case VPSRLDZ256rmkz:
24156 case VPSRLDZ256rr:
24157 case VPSRLDZ256rrk:
24158 case VPSRLDZ256rrkz:
24159 case VPSRLDZmbi:
24160 case VPSRLDZmbik:
24161 case VPSRLDZmbikz:
24162 case VPSRLDZmi:
24163 case VPSRLDZmik:
24164 case VPSRLDZmikz:
24165 case VPSRLDZri:
24166 case VPSRLDZrik:
24167 case VPSRLDZrikz:
24168 case VPSRLDZrm:
24169 case VPSRLDZrmk:
24170 case VPSRLDZrmkz:
24171 case VPSRLDZrr:
24172 case VPSRLDZrrk:
24173 case VPSRLDZrrkz:
24174 case VPSRLDri:
24175 case VPSRLDrm:
24176 case VPSRLDrr:
24177 return true;
24178 }
24179 return false;
24180}
24181
24182bool isINT3(unsigned Opcode) {
24183 return Opcode == INT3;
24184}
24185
24186bool isXRSTORS64(unsigned Opcode) {
24187 return Opcode == XRSTORS64;
24188}
24189
24190bool isCVTSD2SI(unsigned Opcode) {
24191 switch (Opcode) {
24192 case CVTSD2SI64rm_Int:
24193 case CVTSD2SI64rr_Int:
24194 case CVTSD2SIrm_Int:
24195 case CVTSD2SIrr_Int:
24196 return true;
24197 }
24198 return false;
24199}
24200
24201bool isVMAXSS(unsigned Opcode) {
24202 switch (Opcode) {
24203 case VMAXSSZrm_Int:
24204 case VMAXSSZrmk_Int:
24205 case VMAXSSZrmkz_Int:
24206 case VMAXSSZrr_Int:
24207 case VMAXSSZrrb_Int:
24208 case VMAXSSZrrbk_Int:
24209 case VMAXSSZrrbkz_Int:
24210 case VMAXSSZrrk_Int:
24211 case VMAXSSZrrkz_Int:
24212 case VMAXSSrm_Int:
24213 case VMAXSSrr_Int:
24214 return true;
24215 }
24216 return false;
24217}
24218
24219bool isVPMINUB(unsigned Opcode) {
24220 switch (Opcode) {
24221 case VPMINUBYrm:
24222 case VPMINUBYrr:
24223 case VPMINUBZ128rm:
24224 case VPMINUBZ128rmk:
24225 case VPMINUBZ128rmkz:
24226 case VPMINUBZ128rr:
24227 case VPMINUBZ128rrk:
24228 case VPMINUBZ128rrkz:
24229 case VPMINUBZ256rm:
24230 case VPMINUBZ256rmk:
24231 case VPMINUBZ256rmkz:
24232 case VPMINUBZ256rr:
24233 case VPMINUBZ256rrk:
24234 case VPMINUBZ256rrkz:
24235 case VPMINUBZrm:
24236 case VPMINUBZrmk:
24237 case VPMINUBZrmkz:
24238 case VPMINUBZrr:
24239 case VPMINUBZrrk:
24240 case VPMINUBZrrkz:
24241 case VPMINUBrm:
24242 case VPMINUBrr:
24243 return true;
24244 }
24245 return false;
24246}
24247
24248bool isKXNORQ(unsigned Opcode) {
24249 return Opcode == KXNORQkk;
24250}
24251
24252bool isFLD(unsigned Opcode) {
24253 switch (Opcode) {
24254 case LD_F32m:
24255 case LD_F64m:
24256 case LD_F80m:
24257 case LD_Frr:
24258 return true;
24259 }
24260 return false;
24261}
24262
24263bool isVSHUFI32X4(unsigned Opcode) {
24264 switch (Opcode) {
24265 case VSHUFI32X4Z256rmbi:
24266 case VSHUFI32X4Z256rmbik:
24267 case VSHUFI32X4Z256rmbikz:
24268 case VSHUFI32X4Z256rmi:
24269 case VSHUFI32X4Z256rmik:
24270 case VSHUFI32X4Z256rmikz:
24271 case VSHUFI32X4Z256rri:
24272 case VSHUFI32X4Z256rrik:
24273 case VSHUFI32X4Z256rrikz:
24274 case VSHUFI32X4Zrmbi:
24275 case VSHUFI32X4Zrmbik:
24276 case VSHUFI32X4Zrmbikz:
24277 case VSHUFI32X4Zrmi:
24278 case VSHUFI32X4Zrmik:
24279 case VSHUFI32X4Zrmikz:
24280 case VSHUFI32X4Zrri:
24281 case VSHUFI32X4Zrrik:
24282 case VSHUFI32X4Zrrikz:
24283 return true;
24284 }
24285 return false;
24286}
24287
24288bool isSAHF(unsigned Opcode) {
24289 return Opcode == SAHF;
24290}
24291
24292bool isPFRSQRT(unsigned Opcode) {
24293 switch (Opcode) {
24294 case PFRSQRTrm:
24295 case PFRSQRTrr:
24296 return true;
24297 }
24298 return false;
24299}
24300
24301bool isSHRD(unsigned Opcode) {
24302 switch (Opcode) {
24303 case SHRD16mrCL:
24304 case SHRD16mrCL_EVEX:
24305 case SHRD16mrCL_ND:
24306 case SHRD16mrCL_NF:
24307 case SHRD16mrCL_NF_ND:
24308 case SHRD16mri8:
24309 case SHRD16mri8_EVEX:
24310 case SHRD16mri8_ND:
24311 case SHRD16mri8_NF:
24312 case SHRD16mri8_NF_ND:
24313 case SHRD16rrCL:
24314 case SHRD16rrCL_EVEX:
24315 case SHRD16rrCL_ND:
24316 case SHRD16rrCL_NF:
24317 case SHRD16rrCL_NF_ND:
24318 case SHRD16rri8:
24319 case SHRD16rri8_EVEX:
24320 case SHRD16rri8_ND:
24321 case SHRD16rri8_NF:
24322 case SHRD16rri8_NF_ND:
24323 case SHRD32mrCL:
24324 case SHRD32mrCL_EVEX:
24325 case SHRD32mrCL_ND:
24326 case SHRD32mrCL_NF:
24327 case SHRD32mrCL_NF_ND:
24328 case SHRD32mri8:
24329 case SHRD32mri8_EVEX:
24330 case SHRD32mri8_ND:
24331 case SHRD32mri8_NF:
24332 case SHRD32mri8_NF_ND:
24333 case SHRD32rrCL:
24334 case SHRD32rrCL_EVEX:
24335 case SHRD32rrCL_ND:
24336 case SHRD32rrCL_NF:
24337 case SHRD32rrCL_NF_ND:
24338 case SHRD32rri8:
24339 case SHRD32rri8_EVEX:
24340 case SHRD32rri8_ND:
24341 case SHRD32rri8_NF:
24342 case SHRD32rri8_NF_ND:
24343 case SHRD64mrCL:
24344 case SHRD64mrCL_EVEX:
24345 case SHRD64mrCL_ND:
24346 case SHRD64mrCL_NF:
24347 case SHRD64mrCL_NF_ND:
24348 case SHRD64mri8:
24349 case SHRD64mri8_EVEX:
24350 case SHRD64mri8_ND:
24351 case SHRD64mri8_NF:
24352 case SHRD64mri8_NF_ND:
24353 case SHRD64rrCL:
24354 case SHRD64rrCL_EVEX:
24355 case SHRD64rrCL_ND:
24356 case SHRD64rrCL_NF:
24357 case SHRD64rrCL_NF_ND:
24358 case SHRD64rri8:
24359 case SHRD64rri8_EVEX:
24360 case SHRD64rri8_ND:
24361 case SHRD64rri8_NF:
24362 case SHRD64rri8_NF_ND:
24363 return true;
24364 }
24365 return false;
24366}
24367
24368bool isSYSEXIT(unsigned Opcode) {
24369 return Opcode == SYSEXIT;
24370}
24371
24372bool isXSAVE64(unsigned Opcode) {
24373 return Opcode == XSAVE64;
24374}
24375
24376bool isVPMAXSD(unsigned Opcode) {
24377 switch (Opcode) {
24378 case VPMAXSDYrm:
24379 case VPMAXSDYrr:
24380 case VPMAXSDZ128rm:
24381 case VPMAXSDZ128rmb:
24382 case VPMAXSDZ128rmbk:
24383 case VPMAXSDZ128rmbkz:
24384 case VPMAXSDZ128rmk:
24385 case VPMAXSDZ128rmkz:
24386 case VPMAXSDZ128rr:
24387 case VPMAXSDZ128rrk:
24388 case VPMAXSDZ128rrkz:
24389 case VPMAXSDZ256rm:
24390 case VPMAXSDZ256rmb:
24391 case VPMAXSDZ256rmbk:
24392 case VPMAXSDZ256rmbkz:
24393 case VPMAXSDZ256rmk:
24394 case VPMAXSDZ256rmkz:
24395 case VPMAXSDZ256rr:
24396 case VPMAXSDZ256rrk:
24397 case VPMAXSDZ256rrkz:
24398 case VPMAXSDZrm:
24399 case VPMAXSDZrmb:
24400 case VPMAXSDZrmbk:
24401 case VPMAXSDZrmbkz:
24402 case VPMAXSDZrmk:
24403 case VPMAXSDZrmkz:
24404 case VPMAXSDZrr:
24405 case VPMAXSDZrrk:
24406 case VPMAXSDZrrkz:
24407 case VPMAXSDrm:
24408 case VPMAXSDrr:
24409 return true;
24410 }
24411 return false;
24412}
24413
24414bool isCVTTSD2SI(unsigned Opcode) {
24415 switch (Opcode) {
24416 case CVTTSD2SI64rm_Int:
24417 case CVTTSD2SI64rr_Int:
24418 case CVTTSD2SIrm_Int:
24419 case CVTTSD2SIrr_Int:
24420 return true;
24421 }
24422 return false;
24423}
24424
24425bool isVCVTTSS2SIS(unsigned Opcode) {
24426 switch (Opcode) {
24427 case VCVTTSS2SI64Srm_Int:
24428 case VCVTTSS2SI64Srr_Int:
24429 case VCVTTSS2SI64Srrb_Int:
24430 case VCVTTSS2SISrm_Int:
24431 case VCVTTSS2SISrr_Int:
24432 case VCVTTSS2SISrrb_Int:
24433 return true;
24434 }
24435 return false;
24436}
24437
24438bool isPMOVMSKB(unsigned Opcode) {
24439 switch (Opcode) {
24440 case MMX_PMOVMSKBrr:
24441 case PMOVMSKBrr:
24442 return true;
24443 }
24444 return false;
24445}
24446
24447bool isVRANGEPS(unsigned Opcode) {
24448 switch (Opcode) {
24449 case VRANGEPSZ128rmbi:
24450 case VRANGEPSZ128rmbik:
24451 case VRANGEPSZ128rmbikz:
24452 case VRANGEPSZ128rmi:
24453 case VRANGEPSZ128rmik:
24454 case VRANGEPSZ128rmikz:
24455 case VRANGEPSZ128rri:
24456 case VRANGEPSZ128rrik:
24457 case VRANGEPSZ128rrikz:
24458 case VRANGEPSZ256rmbi:
24459 case VRANGEPSZ256rmbik:
24460 case VRANGEPSZ256rmbikz:
24461 case VRANGEPSZ256rmi:
24462 case VRANGEPSZ256rmik:
24463 case VRANGEPSZ256rmikz:
24464 case VRANGEPSZ256rri:
24465 case VRANGEPSZ256rrik:
24466 case VRANGEPSZ256rrikz:
24467 case VRANGEPSZrmbi:
24468 case VRANGEPSZrmbik:
24469 case VRANGEPSZrmbikz:
24470 case VRANGEPSZrmi:
24471 case VRANGEPSZrmik:
24472 case VRANGEPSZrmikz:
24473 case VRANGEPSZrri:
24474 case VRANGEPSZrrib:
24475 case VRANGEPSZrribk:
24476 case VRANGEPSZrribkz:
24477 case VRANGEPSZrrik:
24478 case VRANGEPSZrrikz:
24479 return true;
24480 }
24481 return false;
24482}
24483
24484bool isVADDSUBPS(unsigned Opcode) {
24485 switch (Opcode) {
24486 case VADDSUBPSYrm:
24487 case VADDSUBPSYrr:
24488 case VADDSUBPSrm:
24489 case VADDSUBPSrr:
24490 return true;
24491 }
24492 return false;
24493}
24494
24495bool isVBROADCASTI128(unsigned Opcode) {
24496 return Opcode == VBROADCASTI128rm;
24497}
24498
24499bool isPADDUSB(unsigned Opcode) {
24500 switch (Opcode) {
24501 case MMX_PADDUSBrm:
24502 case MMX_PADDUSBrr:
24503 case PADDUSBrm:
24504 case PADDUSBrr:
24505 return true;
24506 }
24507 return false;
24508}
24509
24510bool isENCODEKEY128(unsigned Opcode) {
24511 return Opcode == ENCODEKEY128;
24512}
24513
24514bool isOR(unsigned Opcode) {
24515 switch (Opcode) {
24516 case OR16i16:
24517 case OR16mi:
24518 case OR16mi8:
24519 case OR16mi8_EVEX:
24520 case OR16mi8_ND:
24521 case OR16mi8_NF:
24522 case OR16mi8_NF_ND:
24523 case OR16mi_EVEX:
24524 case OR16mi_ND:
24525 case OR16mi_NF:
24526 case OR16mi_NF_ND:
24527 case OR16mr:
24528 case OR16mr_EVEX:
24529 case OR16mr_ND:
24530 case OR16mr_NF:
24531 case OR16mr_NF_ND:
24532 case OR16ri:
24533 case OR16ri8:
24534 case OR16ri8_EVEX:
24535 case OR16ri8_ND:
24536 case OR16ri8_NF:
24537 case OR16ri8_NF_ND:
24538 case OR16ri_EVEX:
24539 case OR16ri_ND:
24540 case OR16ri_NF:
24541 case OR16ri_NF_ND:
24542 case OR16rm:
24543 case OR16rm_EVEX:
24544 case OR16rm_ND:
24545 case OR16rm_NF:
24546 case OR16rm_NF_ND:
24547 case OR16rr:
24548 case OR16rr_EVEX:
24549 case OR16rr_EVEX_REV:
24550 case OR16rr_ND:
24551 case OR16rr_ND_REV:
24552 case OR16rr_NF:
24553 case OR16rr_NF_ND:
24554 case OR16rr_NF_ND_REV:
24555 case OR16rr_NF_REV:
24556 case OR16rr_REV:
24557 case OR32i32:
24558 case OR32mi:
24559 case OR32mi8:
24560 case OR32mi8_EVEX:
24561 case OR32mi8_ND:
24562 case OR32mi8_NF:
24563 case OR32mi8_NF_ND:
24564 case OR32mi_EVEX:
24565 case OR32mi_ND:
24566 case OR32mi_NF:
24567 case OR32mi_NF_ND:
24568 case OR32mr:
24569 case OR32mr_EVEX:
24570 case OR32mr_ND:
24571 case OR32mr_NF:
24572 case OR32mr_NF_ND:
24573 case OR32ri:
24574 case OR32ri8:
24575 case OR32ri8_EVEX:
24576 case OR32ri8_ND:
24577 case OR32ri8_NF:
24578 case OR32ri8_NF_ND:
24579 case OR32ri_EVEX:
24580 case OR32ri_ND:
24581 case OR32ri_NF:
24582 case OR32ri_NF_ND:
24583 case OR32rm:
24584 case OR32rm_EVEX:
24585 case OR32rm_ND:
24586 case OR32rm_NF:
24587 case OR32rm_NF_ND:
24588 case OR32rr:
24589 case OR32rr_EVEX:
24590 case OR32rr_EVEX_REV:
24591 case OR32rr_ND:
24592 case OR32rr_ND_REV:
24593 case OR32rr_NF:
24594 case OR32rr_NF_ND:
24595 case OR32rr_NF_ND_REV:
24596 case OR32rr_NF_REV:
24597 case OR32rr_REV:
24598 case OR64i32:
24599 case OR64mi32:
24600 case OR64mi32_EVEX:
24601 case OR64mi32_ND:
24602 case OR64mi32_NF:
24603 case OR64mi32_NF_ND:
24604 case OR64mi8:
24605 case OR64mi8_EVEX:
24606 case OR64mi8_ND:
24607 case OR64mi8_NF:
24608 case OR64mi8_NF_ND:
24609 case OR64mr:
24610 case OR64mr_EVEX:
24611 case OR64mr_ND:
24612 case OR64mr_NF:
24613 case OR64mr_NF_ND:
24614 case OR64ri32:
24615 case OR64ri32_EVEX:
24616 case OR64ri32_ND:
24617 case OR64ri32_NF:
24618 case OR64ri32_NF_ND:
24619 case OR64ri8:
24620 case OR64ri8_EVEX:
24621 case OR64ri8_ND:
24622 case OR64ri8_NF:
24623 case OR64ri8_NF_ND:
24624 case OR64rm:
24625 case OR64rm_EVEX:
24626 case OR64rm_ND:
24627 case OR64rm_NF:
24628 case OR64rm_NF_ND:
24629 case OR64rr:
24630 case OR64rr_EVEX:
24631 case OR64rr_EVEX_REV:
24632 case OR64rr_ND:
24633 case OR64rr_ND_REV:
24634 case OR64rr_NF:
24635 case OR64rr_NF_ND:
24636 case OR64rr_NF_ND_REV:
24637 case OR64rr_NF_REV:
24638 case OR64rr_REV:
24639 case OR8i8:
24640 case OR8mi:
24641 case OR8mi8:
24642 case OR8mi_EVEX:
24643 case OR8mi_ND:
24644 case OR8mi_NF:
24645 case OR8mi_NF_ND:
24646 case OR8mr:
24647 case OR8mr_EVEX:
24648 case OR8mr_ND:
24649 case OR8mr_NF:
24650 case OR8mr_NF_ND:
24651 case OR8ri:
24652 case OR8ri8:
24653 case OR8ri_EVEX:
24654 case OR8ri_ND:
24655 case OR8ri_NF:
24656 case OR8ri_NF_ND:
24657 case OR8rm:
24658 case OR8rm_EVEX:
24659 case OR8rm_ND:
24660 case OR8rm_NF:
24661 case OR8rm_NF_ND:
24662 case OR8rr:
24663 case OR8rr_EVEX:
24664 case OR8rr_EVEX_REV:
24665 case OR8rr_ND:
24666 case OR8rr_ND_REV:
24667 case OR8rr_NF:
24668 case OR8rr_NF_ND:
24669 case OR8rr_NF_ND_REV:
24670 case OR8rr_NF_REV:
24671 case OR8rr_REV:
24672 return true;
24673 }
24674 return false;
24675}
24676
24677bool isSTOSW(unsigned Opcode) {
24678 return Opcode == STOSW;
24679}
24680
24681bool isVCVTTPD2UQQS(unsigned Opcode) {
24682 switch (Opcode) {
24683 case VCVTTPD2UQQSZ128rm:
24684 case VCVTTPD2UQQSZ128rmb:
24685 case VCVTTPD2UQQSZ128rmbk:
24686 case VCVTTPD2UQQSZ128rmbkz:
24687 case VCVTTPD2UQQSZ128rmk:
24688 case VCVTTPD2UQQSZ128rmkz:
24689 case VCVTTPD2UQQSZ128rr:
24690 case VCVTTPD2UQQSZ128rrk:
24691 case VCVTTPD2UQQSZ128rrkz:
24692 case VCVTTPD2UQQSZ256rm:
24693 case VCVTTPD2UQQSZ256rmb:
24694 case VCVTTPD2UQQSZ256rmbk:
24695 case VCVTTPD2UQQSZ256rmbkz:
24696 case VCVTTPD2UQQSZ256rmk:
24697 case VCVTTPD2UQQSZ256rmkz:
24698 case VCVTTPD2UQQSZ256rr:
24699 case VCVTTPD2UQQSZ256rrb:
24700 case VCVTTPD2UQQSZ256rrbk:
24701 case VCVTTPD2UQQSZ256rrbkz:
24702 case VCVTTPD2UQQSZ256rrk:
24703 case VCVTTPD2UQQSZ256rrkz:
24704 case VCVTTPD2UQQSZrm:
24705 case VCVTTPD2UQQSZrmb:
24706 case VCVTTPD2UQQSZrmbk:
24707 case VCVTTPD2UQQSZrmbkz:
24708 case VCVTTPD2UQQSZrmk:
24709 case VCVTTPD2UQQSZrmkz:
24710 case VCVTTPD2UQQSZrr:
24711 case VCVTTPD2UQQSZrrb:
24712 case VCVTTPD2UQQSZrrbk:
24713 case VCVTTPD2UQQSZrrbkz:
24714 case VCVTTPD2UQQSZrrk:
24715 case VCVTTPD2UQQSZrrkz:
24716 return true;
24717 }
24718 return false;
24719}
24720
24721bool isPAVGW(unsigned Opcode) {
24722 switch (Opcode) {
24723 case MMX_PAVGWrm:
24724 case MMX_PAVGWrr:
24725 case PAVGWrm:
24726 case PAVGWrr:
24727 return true;
24728 }
24729 return false;
24730}
24731
24732bool isVCVTPD2PH(unsigned Opcode) {
24733 switch (Opcode) {
24734 case VCVTPD2PHZ128rm:
24735 case VCVTPD2PHZ128rmb:
24736 case VCVTPD2PHZ128rmbk:
24737 case VCVTPD2PHZ128rmbkz:
24738 case VCVTPD2PHZ128rmk:
24739 case VCVTPD2PHZ128rmkz:
24740 case VCVTPD2PHZ128rr:
24741 case VCVTPD2PHZ128rrk:
24742 case VCVTPD2PHZ128rrkz:
24743 case VCVTPD2PHZ256rm:
24744 case VCVTPD2PHZ256rmb:
24745 case VCVTPD2PHZ256rmbk:
24746 case VCVTPD2PHZ256rmbkz:
24747 case VCVTPD2PHZ256rmk:
24748 case VCVTPD2PHZ256rmkz:
24749 case VCVTPD2PHZ256rr:
24750 case VCVTPD2PHZ256rrk:
24751 case VCVTPD2PHZ256rrkz:
24752 case VCVTPD2PHZrm:
24753 case VCVTPD2PHZrmb:
24754 case VCVTPD2PHZrmbk:
24755 case VCVTPD2PHZrmbkz:
24756 case VCVTPD2PHZrmk:
24757 case VCVTPD2PHZrmkz:
24758 case VCVTPD2PHZrr:
24759 case VCVTPD2PHZrrb:
24760 case VCVTPD2PHZrrbk:
24761 case VCVTPD2PHZrrbkz:
24762 case VCVTPD2PHZrrk:
24763 case VCVTPD2PHZrrkz:
24764 return true;
24765 }
24766 return false;
24767}
24768
24769bool isSHLX(unsigned Opcode) {
24770 switch (Opcode) {
24771 case SHLX32rm:
24772 case SHLX32rm_EVEX:
24773 case SHLX32rr:
24774 case SHLX32rr_EVEX:
24775 case SHLX64rm:
24776 case SHLX64rm_EVEX:
24777 case SHLX64rr:
24778 case SHLX64rr_EVEX:
24779 return true;
24780 }
24781 return false;
24782}
24783
24784bool isVCVTSH2SD(unsigned Opcode) {
24785 switch (Opcode) {
24786 case VCVTSH2SDZrm_Int:
24787 case VCVTSH2SDZrmk_Int:
24788 case VCVTSH2SDZrmkz_Int:
24789 case VCVTSH2SDZrr_Int:
24790 case VCVTSH2SDZrrb_Int:
24791 case VCVTSH2SDZrrbk_Int:
24792 case VCVTSH2SDZrrbkz_Int:
24793 case VCVTSH2SDZrrk_Int:
24794 case VCVTSH2SDZrrkz_Int:
24795 return true;
24796 }
24797 return false;
24798}
24799
24800bool isVFMADD231SS(unsigned Opcode) {
24801 switch (Opcode) {
24802 case VFMADD231SSZm_Int:
24803 case VFMADD231SSZmk_Int:
24804 case VFMADD231SSZmkz_Int:
24805 case VFMADD231SSZr_Int:
24806 case VFMADD231SSZrb_Int:
24807 case VFMADD231SSZrbk_Int:
24808 case VFMADD231SSZrbkz_Int:
24809 case VFMADD231SSZrk_Int:
24810 case VFMADD231SSZrkz_Int:
24811 case VFMADD231SSm_Int:
24812 case VFMADD231SSr_Int:
24813 return true;
24814 }
24815 return false;
24816}
24817
24818bool isMOVNTSD(unsigned Opcode) {
24819 return Opcode == MOVNTSD;
24820}
24821
24822bool isFLDPI(unsigned Opcode) {
24823 return Opcode == FLDPI;
24824}
24825
24826bool isVCVTUSI2SS(unsigned Opcode) {
24827 switch (Opcode) {
24828 case VCVTUSI2SSZrm_Int:
24829 case VCVTUSI2SSZrr_Int:
24830 case VCVTUSI2SSZrrb_Int:
24831 case VCVTUSI642SSZrm_Int:
24832 case VCVTUSI642SSZrr_Int:
24833 case VCVTUSI642SSZrrb_Int:
24834 return true;
24835 }
24836 return false;
24837}
24838
24839bool isPMOVSXBD(unsigned Opcode) {
24840 switch (Opcode) {
24841 case PMOVSXBDrm:
24842 case PMOVSXBDrr:
24843 return true;
24844 }
24845 return false;
24846}
24847
24848bool isVPRORVQ(unsigned Opcode) {
24849 switch (Opcode) {
24850 case VPRORVQZ128rm:
24851 case VPRORVQZ128rmb:
24852 case VPRORVQZ128rmbk:
24853 case VPRORVQZ128rmbkz:
24854 case VPRORVQZ128rmk:
24855 case VPRORVQZ128rmkz:
24856 case VPRORVQZ128rr:
24857 case VPRORVQZ128rrk:
24858 case VPRORVQZ128rrkz:
24859 case VPRORVQZ256rm:
24860 case VPRORVQZ256rmb:
24861 case VPRORVQZ256rmbk:
24862 case VPRORVQZ256rmbkz:
24863 case VPRORVQZ256rmk:
24864 case VPRORVQZ256rmkz:
24865 case VPRORVQZ256rr:
24866 case VPRORVQZ256rrk:
24867 case VPRORVQZ256rrkz:
24868 case VPRORVQZrm:
24869 case VPRORVQZrmb:
24870 case VPRORVQZrmbk:
24871 case VPRORVQZrmbkz:
24872 case VPRORVQZrmk:
24873 case VPRORVQZrmkz:
24874 case VPRORVQZrr:
24875 case VPRORVQZrrk:
24876 case VPRORVQZrrkz:
24877 return true;
24878 }
24879 return false;
24880}
24881
24882bool isVPERMT2D(unsigned Opcode) {
24883 switch (Opcode) {
24884 case VPERMT2DZ128rm:
24885 case VPERMT2DZ128rmb:
24886 case VPERMT2DZ128rmbk:
24887 case VPERMT2DZ128rmbkz:
24888 case VPERMT2DZ128rmk:
24889 case VPERMT2DZ128rmkz:
24890 case VPERMT2DZ128rr:
24891 case VPERMT2DZ128rrk:
24892 case VPERMT2DZ128rrkz:
24893 case VPERMT2DZ256rm:
24894 case VPERMT2DZ256rmb:
24895 case VPERMT2DZ256rmbk:
24896 case VPERMT2DZ256rmbkz:
24897 case VPERMT2DZ256rmk:
24898 case VPERMT2DZ256rmkz:
24899 case VPERMT2DZ256rr:
24900 case VPERMT2DZ256rrk:
24901 case VPERMT2DZ256rrkz:
24902 case VPERMT2DZrm:
24903 case VPERMT2DZrmb:
24904 case VPERMT2DZrmbk:
24905 case VPERMT2DZrmbkz:
24906 case VPERMT2DZrmk:
24907 case VPERMT2DZrmkz:
24908 case VPERMT2DZrr:
24909 case VPERMT2DZrrk:
24910 case VPERMT2DZrrkz:
24911 return true;
24912 }
24913 return false;
24914}
24915
24916bool isADDSS(unsigned Opcode) {
24917 switch (Opcode) {
24918 case ADDSSrm_Int:
24919 case ADDSSrr_Int:
24920 return true;
24921 }
24922 return false;
24923}
24924
24925bool isAADD(unsigned Opcode) {
24926 switch (Opcode) {
24927 case AADD32mr:
24928 case AADD32mr_EVEX:
24929 case AADD64mr:
24930 case AADD64mr_EVEX:
24931 return true;
24932 }
24933 return false;
24934}
24935
24936bool isVPSRLVW(unsigned Opcode) {
24937 switch (Opcode) {
24938 case VPSRLVWZ128rm:
24939 case VPSRLVWZ128rmk:
24940 case VPSRLVWZ128rmkz:
24941 case VPSRLVWZ128rr:
24942 case VPSRLVWZ128rrk:
24943 case VPSRLVWZ128rrkz:
24944 case VPSRLVWZ256rm:
24945 case VPSRLVWZ256rmk:
24946 case VPSRLVWZ256rmkz:
24947 case VPSRLVWZ256rr:
24948 case VPSRLVWZ256rrk:
24949 case VPSRLVWZ256rrkz:
24950 case VPSRLVWZrm:
24951 case VPSRLVWZrmk:
24952 case VPSRLVWZrmkz:
24953 case VPSRLVWZrr:
24954 case VPSRLVWZrrk:
24955 case VPSRLVWZrrkz:
24956 return true;
24957 }
24958 return false;
24959}
24960
24961bool isVRSQRTPH(unsigned Opcode) {
24962 switch (Opcode) {
24963 case VRSQRTPHZ128m:
24964 case VRSQRTPHZ128mb:
24965 case VRSQRTPHZ128mbk:
24966 case VRSQRTPHZ128mbkz:
24967 case VRSQRTPHZ128mk:
24968 case VRSQRTPHZ128mkz:
24969 case VRSQRTPHZ128r:
24970 case VRSQRTPHZ128rk:
24971 case VRSQRTPHZ128rkz:
24972 case VRSQRTPHZ256m:
24973 case VRSQRTPHZ256mb:
24974 case VRSQRTPHZ256mbk:
24975 case VRSQRTPHZ256mbkz:
24976 case VRSQRTPHZ256mk:
24977 case VRSQRTPHZ256mkz:
24978 case VRSQRTPHZ256r:
24979 case VRSQRTPHZ256rk:
24980 case VRSQRTPHZ256rkz:
24981 case VRSQRTPHZm:
24982 case VRSQRTPHZmb:
24983 case VRSQRTPHZmbk:
24984 case VRSQRTPHZmbkz:
24985 case VRSQRTPHZmk:
24986 case VRSQRTPHZmkz:
24987 case VRSQRTPHZr:
24988 case VRSQRTPHZrk:
24989 case VRSQRTPHZrkz:
24990 return true;
24991 }
24992 return false;
24993}
24994
24995bool isVLDDQU(unsigned Opcode) {
24996 switch (Opcode) {
24997 case VLDDQUYrm:
24998 case VLDDQUrm:
24999 return true;
25000 }
25001 return false;
25002}
25003
25004bool isKMOVD(unsigned Opcode) {
25005 switch (Opcode) {
25006 case KMOVDkk:
25007 case KMOVDkk_EVEX:
25008 case KMOVDkm:
25009 case KMOVDkm_EVEX:
25010 case KMOVDkr:
25011 case KMOVDkr_EVEX:
25012 case KMOVDmk:
25013 case KMOVDmk_EVEX:
25014 case KMOVDrk:
25015 case KMOVDrk_EVEX:
25016 return true;
25017 }
25018 return false;
25019}
25020
25021bool isENCLV(unsigned Opcode) {
25022 return Opcode == ENCLV;
25023}
25024
25025bool isENCLU(unsigned Opcode) {
25026 return Opcode == ENCLU;
25027}
25028
25029bool isPREFETCHT1(unsigned Opcode) {
25030 return Opcode == PREFETCHT1;
25031}
25032
25033bool isRSQRTPS(unsigned Opcode) {
25034 switch (Opcode) {
25035 case RSQRTPSm:
25036 case RSQRTPSr:
25037 return true;
25038 }
25039 return false;
25040}
25041
25042bool isVCVTTSH2USI(unsigned Opcode) {
25043 switch (Opcode) {
25044 case VCVTTSH2USI64Zrm_Int:
25045 case VCVTTSH2USI64Zrr_Int:
25046 case VCVTTSH2USI64Zrrb_Int:
25047 case VCVTTSH2USIZrm_Int:
25048 case VCVTTSH2USIZrr_Int:
25049 case VCVTTSH2USIZrrb_Int:
25050 return true;
25051 }
25052 return false;
25053}
25054
25055bool isPADDB(unsigned Opcode) {
25056 switch (Opcode) {
25057 case MMX_PADDBrm:
25058 case MMX_PADDBrr:
25059 case PADDBrm:
25060 case PADDBrr:
25061 return true;
25062 }
25063 return false;
25064}
25065
25066bool isVMASKMOVDQU(unsigned Opcode) {
25067 return Opcode == VMASKMOVDQU64;
25068}
25069
25070bool isPUNPCKLBW(unsigned Opcode) {
25071 switch (Opcode) {
25072 case MMX_PUNPCKLBWrm:
25073 case MMX_PUNPCKLBWrr:
25074 case PUNPCKLBWrm:
25075 case PUNPCKLBWrr:
25076 return true;
25077 }
25078 return false;
25079}
25080
25081bool isMOV(unsigned Opcode) {
25082 switch (Opcode) {
25083 case MOV16ao16:
25084 case MOV16ao32:
25085 case MOV16mi:
25086 case MOV16mr:
25087 case MOV16ms:
25088 case MOV16o16a:
25089 case MOV16o32a:
25090 case MOV16ri:
25091 case MOV16ri_alt:
25092 case MOV16rm:
25093 case MOV16rr:
25094 case MOV16rr_REV:
25095 case MOV16rs:
25096 case MOV16sm:
25097 case MOV16sr:
25098 case MOV32ao16:
25099 case MOV32ao32:
25100 case MOV32cr:
25101 case MOV32dr:
25102 case MOV32mi:
25103 case MOV32mr:
25104 case MOV32o16a:
25105 case MOV32o32a:
25106 case MOV32rc:
25107 case MOV32rd:
25108 case MOV32ri:
25109 case MOV32ri_alt:
25110 case MOV32rm:
25111 case MOV32rr:
25112 case MOV32rr_REV:
25113 case MOV32rs:
25114 case MOV32sr:
25115 case MOV64ao32:
25116 case MOV64cr:
25117 case MOV64dr:
25118 case MOV64mi32:
25119 case MOV64mr:
25120 case MOV64o32a:
25121 case MOV64rc:
25122 case MOV64rd:
25123 case MOV64ri32:
25124 case MOV64rm:
25125 case MOV64rr:
25126 case MOV64rr_REV:
25127 case MOV64rs:
25128 case MOV64sr:
25129 case MOV8ao16:
25130 case MOV8ao32:
25131 case MOV8mi:
25132 case MOV8mr:
25133 case MOV8o16a:
25134 case MOV8o32a:
25135 case MOV8ri:
25136 case MOV8ri_alt:
25137 case MOV8rm:
25138 case MOV8rr:
25139 case MOV8rr_REV:
25140 return true;
25141 }
25142 return false;
25143}
25144
25145bool isVCVTTPH2IUBS(unsigned Opcode) {
25146 switch (Opcode) {
25147 case VCVTTPH2IUBSZ128rm:
25148 case VCVTTPH2IUBSZ128rmb:
25149 case VCVTTPH2IUBSZ128rmbk:
25150 case VCVTTPH2IUBSZ128rmbkz:
25151 case VCVTTPH2IUBSZ128rmk:
25152 case VCVTTPH2IUBSZ128rmkz:
25153 case VCVTTPH2IUBSZ128rr:
25154 case VCVTTPH2IUBSZ128rrk:
25155 case VCVTTPH2IUBSZ128rrkz:
25156 case VCVTTPH2IUBSZ256rm:
25157 case VCVTTPH2IUBSZ256rmb:
25158 case VCVTTPH2IUBSZ256rmbk:
25159 case VCVTTPH2IUBSZ256rmbkz:
25160 case VCVTTPH2IUBSZ256rmk:
25161 case VCVTTPH2IUBSZ256rmkz:
25162 case VCVTTPH2IUBSZ256rr:
25163 case VCVTTPH2IUBSZ256rrk:
25164 case VCVTTPH2IUBSZ256rrkz:
25165 case VCVTTPH2IUBSZrm:
25166 case VCVTTPH2IUBSZrmb:
25167 case VCVTTPH2IUBSZrmbk:
25168 case VCVTTPH2IUBSZrmbkz:
25169 case VCVTTPH2IUBSZrmk:
25170 case VCVTTPH2IUBSZrmkz:
25171 case VCVTTPH2IUBSZrr:
25172 case VCVTTPH2IUBSZrrb:
25173 case VCVTTPH2IUBSZrrbk:
25174 case VCVTTPH2IUBSZrrbkz:
25175 case VCVTTPH2IUBSZrrk:
25176 case VCVTTPH2IUBSZrrkz:
25177 return true;
25178 }
25179 return false;
25180}
25181
25182bool isMUL(unsigned Opcode) {
25183 switch (Opcode) {
25184 case MUL16m:
25185 case MUL16m_EVEX:
25186 case MUL16m_NF:
25187 case MUL16r:
25188 case MUL16r_EVEX:
25189 case MUL16r_NF:
25190 case MUL32m:
25191 case MUL32m_EVEX:
25192 case MUL32m_NF:
25193 case MUL32r:
25194 case MUL32r_EVEX:
25195 case MUL32r_NF:
25196 case MUL64m:
25197 case MUL64m_EVEX:
25198 case MUL64m_NF:
25199 case MUL64r:
25200 case MUL64r_EVEX:
25201 case MUL64r_NF:
25202 case MUL8m:
25203 case MUL8m_EVEX:
25204 case MUL8m_NF:
25205 case MUL8r:
25206 case MUL8r_EVEX:
25207 case MUL8r_NF:
25208 return true;
25209 }
25210 return false;
25211}
25212
25213bool isRCL(unsigned Opcode) {
25214 switch (Opcode) {
25215 case RCL16m1:
25216 case RCL16m1_EVEX:
25217 case RCL16m1_ND:
25218 case RCL16mCL:
25219 case RCL16mCL_EVEX:
25220 case RCL16mCL_ND:
25221 case RCL16mi:
25222 case RCL16mi_EVEX:
25223 case RCL16mi_ND:
25224 case RCL16r1:
25225 case RCL16r1_EVEX:
25226 case RCL16r1_ND:
25227 case RCL16rCL:
25228 case RCL16rCL_EVEX:
25229 case RCL16rCL_ND:
25230 case RCL16ri:
25231 case RCL16ri_EVEX:
25232 case RCL16ri_ND:
25233 case RCL32m1:
25234 case RCL32m1_EVEX:
25235 case RCL32m1_ND:
25236 case RCL32mCL:
25237 case RCL32mCL_EVEX:
25238 case RCL32mCL_ND:
25239 case RCL32mi:
25240 case RCL32mi_EVEX:
25241 case RCL32mi_ND:
25242 case RCL32r1:
25243 case RCL32r1_EVEX:
25244 case RCL32r1_ND:
25245 case RCL32rCL:
25246 case RCL32rCL_EVEX:
25247 case RCL32rCL_ND:
25248 case RCL32ri:
25249 case RCL32ri_EVEX:
25250 case RCL32ri_ND:
25251 case RCL64m1:
25252 case RCL64m1_EVEX:
25253 case RCL64m1_ND:
25254 case RCL64mCL:
25255 case RCL64mCL_EVEX:
25256 case RCL64mCL_ND:
25257 case RCL64mi:
25258 case RCL64mi_EVEX:
25259 case RCL64mi_ND:
25260 case RCL64r1:
25261 case RCL64r1_EVEX:
25262 case RCL64r1_ND:
25263 case RCL64rCL:
25264 case RCL64rCL_EVEX:
25265 case RCL64rCL_ND:
25266 case RCL64ri:
25267 case RCL64ri_EVEX:
25268 case RCL64ri_ND:
25269 case RCL8m1:
25270 case RCL8m1_EVEX:
25271 case RCL8m1_ND:
25272 case RCL8mCL:
25273 case RCL8mCL_EVEX:
25274 case RCL8mCL_ND:
25275 case RCL8mi:
25276 case RCL8mi_EVEX:
25277 case RCL8mi_ND:
25278 case RCL8r1:
25279 case RCL8r1_EVEX:
25280 case RCL8r1_ND:
25281 case RCL8rCL:
25282 case RCL8rCL_EVEX:
25283 case RCL8rCL_ND:
25284 case RCL8ri:
25285 case RCL8ri_EVEX:
25286 case RCL8ri_ND:
25287 return true;
25288 }
25289 return false;
25290}
25291
25292bool isVRCPSH(unsigned Opcode) {
25293 switch (Opcode) {
25294 case VRCPSHZrm:
25295 case VRCPSHZrmk:
25296 case VRCPSHZrmkz:
25297 case VRCPSHZrr:
25298 case VRCPSHZrrk:
25299 case VRCPSHZrrkz:
25300 return true;
25301 }
25302 return false;
25303}
25304
25305bool isPFCMPEQ(unsigned Opcode) {
25306 switch (Opcode) {
25307 case PFCMPEQrm:
25308 case PFCMPEQrr:
25309 return true;
25310 }
25311 return false;
25312}
25313
25314bool isMONITOR(unsigned Opcode) {
25315 switch (Opcode) {
25316 case MONITOR32rrr:
25317 case MONITOR64rrr:
25318 return true;
25319 }
25320 return false;
25321}
25322
25323bool isFDIVR(unsigned Opcode) {
25324 switch (Opcode) {
25325 case DIVR_F32m:
25326 case DIVR_F64m:
25327 case DIVR_FST0r:
25328 case DIVR_FrST0:
25329 return true;
25330 }
25331 return false;
25332}
25333
25334bool isPMINSD(unsigned Opcode) {
25335 switch (Opcode) {
25336 case PMINSDrm:
25337 case PMINSDrr:
25338 return true;
25339 }
25340 return false;
25341}
25342
25343bool isPFRCP(unsigned Opcode) {
25344 switch (Opcode) {
25345 case PFRCPrm:
25346 case PFRCPrr:
25347 return true;
25348 }
25349 return false;
25350}
25351
25352bool isKTESTQ(unsigned Opcode) {
25353 return Opcode == KTESTQkk;
25354}
25355
25356bool isVCVTTPD2DQ(unsigned Opcode) {
25357 switch (Opcode) {
25358 case VCVTTPD2DQYrm:
25359 case VCVTTPD2DQYrr:
25360 case VCVTTPD2DQZ128rm:
25361 case VCVTTPD2DQZ128rmb:
25362 case VCVTTPD2DQZ128rmbk:
25363 case VCVTTPD2DQZ128rmbkz:
25364 case VCVTTPD2DQZ128rmk:
25365 case VCVTTPD2DQZ128rmkz:
25366 case VCVTTPD2DQZ128rr:
25367 case VCVTTPD2DQZ128rrk:
25368 case VCVTTPD2DQZ128rrkz:
25369 case VCVTTPD2DQZ256rm:
25370 case VCVTTPD2DQZ256rmb:
25371 case VCVTTPD2DQZ256rmbk:
25372 case VCVTTPD2DQZ256rmbkz:
25373 case VCVTTPD2DQZ256rmk:
25374 case VCVTTPD2DQZ256rmkz:
25375 case VCVTTPD2DQZ256rr:
25376 case VCVTTPD2DQZ256rrk:
25377 case VCVTTPD2DQZ256rrkz:
25378 case VCVTTPD2DQZrm:
25379 case VCVTTPD2DQZrmb:
25380 case VCVTTPD2DQZrmbk:
25381 case VCVTTPD2DQZrmbkz:
25382 case VCVTTPD2DQZrmk:
25383 case VCVTTPD2DQZrmkz:
25384 case VCVTTPD2DQZrr:
25385 case VCVTTPD2DQZrrb:
25386 case VCVTTPD2DQZrrbk:
25387 case VCVTTPD2DQZrrbkz:
25388 case VCVTTPD2DQZrrk:
25389 case VCVTTPD2DQZrrkz:
25390 case VCVTTPD2DQrm:
25391 case VCVTTPD2DQrr:
25392 return true;
25393 }
25394 return false;
25395}
25396
25397bool isVSHUFF32X4(unsigned Opcode) {
25398 switch (Opcode) {
25399 case VSHUFF32X4Z256rmbi:
25400 case VSHUFF32X4Z256rmbik:
25401 case VSHUFF32X4Z256rmbikz:
25402 case VSHUFF32X4Z256rmi:
25403 case VSHUFF32X4Z256rmik:
25404 case VSHUFF32X4Z256rmikz:
25405 case VSHUFF32X4Z256rri:
25406 case VSHUFF32X4Z256rrik:
25407 case VSHUFF32X4Z256rrikz:
25408 case VSHUFF32X4Zrmbi:
25409 case VSHUFF32X4Zrmbik:
25410 case VSHUFF32X4Zrmbikz:
25411 case VSHUFF32X4Zrmi:
25412 case VSHUFF32X4Zrmik:
25413 case VSHUFF32X4Zrmikz:
25414 case VSHUFF32X4Zrri:
25415 case VSHUFF32X4Zrrik:
25416 case VSHUFF32X4Zrrikz:
25417 return true;
25418 }
25419 return false;
25420}
25421
25422bool isVPSLLVW(unsigned Opcode) {
25423 switch (Opcode) {
25424 case VPSLLVWZ128rm:
25425 case VPSLLVWZ128rmk:
25426 case VPSLLVWZ128rmkz:
25427 case VPSLLVWZ128rr:
25428 case VPSLLVWZ128rrk:
25429 case VPSLLVWZ128rrkz:
25430 case VPSLLVWZ256rm:
25431 case VPSLLVWZ256rmk:
25432 case VPSLLVWZ256rmkz:
25433 case VPSLLVWZ256rr:
25434 case VPSLLVWZ256rrk:
25435 case VPSLLVWZ256rrkz:
25436 case VPSLLVWZrm:
25437 case VPSLLVWZrmk:
25438 case VPSLLVWZrmkz:
25439 case VPSLLVWZrr:
25440 case VPSLLVWZrrk:
25441 case VPSLLVWZrrkz:
25442 return true;
25443 }
25444 return false;
25445}
25446
25447bool isTDPBSUD(unsigned Opcode) {
25448 return Opcode == TDPBSUD;
25449}
25450
25451bool isVPMINUQ(unsigned Opcode) {
25452 switch (Opcode) {
25453 case VPMINUQZ128rm:
25454 case VPMINUQZ128rmb:
25455 case VPMINUQZ128rmbk:
25456 case VPMINUQZ128rmbkz:
25457 case VPMINUQZ128rmk:
25458 case VPMINUQZ128rmkz:
25459 case VPMINUQZ128rr:
25460 case VPMINUQZ128rrk:
25461 case VPMINUQZ128rrkz:
25462 case VPMINUQZ256rm:
25463 case VPMINUQZ256rmb:
25464 case VPMINUQZ256rmbk:
25465 case VPMINUQZ256rmbkz:
25466 case VPMINUQZ256rmk:
25467 case VPMINUQZ256rmkz:
25468 case VPMINUQZ256rr:
25469 case VPMINUQZ256rrk:
25470 case VPMINUQZ256rrkz:
25471 case VPMINUQZrm:
25472 case VPMINUQZrmb:
25473 case VPMINUQZrmbk:
25474 case VPMINUQZrmbkz:
25475 case VPMINUQZrmk:
25476 case VPMINUQZrmkz:
25477 case VPMINUQZrr:
25478 case VPMINUQZrrk:
25479 case VPMINUQZrrkz:
25480 return true;
25481 }
25482 return false;
25483}
25484
25485bool isFIADD(unsigned Opcode) {
25486 switch (Opcode) {
25487 case ADD_FI16m:
25488 case ADD_FI32m:
25489 return true;
25490 }
25491 return false;
25492}
25493
25494bool isFCMOVNU(unsigned Opcode) {
25495 return Opcode == CMOVNP_F;
25496}
25497
25498bool isVHSUBPD(unsigned Opcode) {
25499 switch (Opcode) {
25500 case VHSUBPDYrm:
25501 case VHSUBPDYrr:
25502 case VHSUBPDrm:
25503 case VHSUBPDrr:
25504 return true;
25505 }
25506 return false;
25507}
25508
25509bool isKSHIFTRQ(unsigned Opcode) {
25510 return Opcode == KSHIFTRQki;
25511}
25512
25513bool isMOVUPS(unsigned Opcode) {
25514 switch (Opcode) {
25515 case MOVUPSmr:
25516 case MOVUPSrm:
25517 case MOVUPSrr:
25518 case MOVUPSrr_REV:
25519 return true;
25520 }
25521 return false;
25522}
25523
25524bool isVMCALL(unsigned Opcode) {
25525 return Opcode == VMCALL;
25526}
25527
25528bool isXADD(unsigned Opcode) {
25529 switch (Opcode) {
25530 case XADD16rm:
25531 case XADD16rr:
25532 case XADD32rm:
25533 case XADD32rr:
25534 case XADD64rm:
25535 case XADD64rr:
25536 case XADD8rm:
25537 case XADD8rr:
25538 return true;
25539 }
25540 return false;
25541}
25542
25543bool isXRSTOR(unsigned Opcode) {
25544 return Opcode == XRSTOR;
25545}
25546
25547bool isVGATHERPF1DPD(unsigned Opcode) {
25548 return Opcode == VGATHERPF1DPDm;
25549}
25550
25551bool isRCR(unsigned Opcode) {
25552 switch (Opcode) {
25553 case RCR16m1:
25554 case RCR16m1_EVEX:
25555 case RCR16m1_ND:
25556 case RCR16mCL:
25557 case RCR16mCL_EVEX:
25558 case RCR16mCL_ND:
25559 case RCR16mi:
25560 case RCR16mi_EVEX:
25561 case RCR16mi_ND:
25562 case RCR16r1:
25563 case RCR16r1_EVEX:
25564 case RCR16r1_ND:
25565 case RCR16rCL:
25566 case RCR16rCL_EVEX:
25567 case RCR16rCL_ND:
25568 case RCR16ri:
25569 case RCR16ri_EVEX:
25570 case RCR16ri_ND:
25571 case RCR32m1:
25572 case RCR32m1_EVEX:
25573 case RCR32m1_ND:
25574 case RCR32mCL:
25575 case RCR32mCL_EVEX:
25576 case RCR32mCL_ND:
25577 case RCR32mi:
25578 case RCR32mi_EVEX:
25579 case RCR32mi_ND:
25580 case RCR32r1:
25581 case RCR32r1_EVEX:
25582 case RCR32r1_ND:
25583 case RCR32rCL:
25584 case RCR32rCL_EVEX:
25585 case RCR32rCL_ND:
25586 case RCR32ri:
25587 case RCR32ri_EVEX:
25588 case RCR32ri_ND:
25589 case RCR64m1:
25590 case RCR64m1_EVEX:
25591 case RCR64m1_ND:
25592 case RCR64mCL:
25593 case RCR64mCL_EVEX:
25594 case RCR64mCL_ND:
25595 case RCR64mi:
25596 case RCR64mi_EVEX:
25597 case RCR64mi_ND:
25598 case RCR64r1:
25599 case RCR64r1_EVEX:
25600 case RCR64r1_ND:
25601 case RCR64rCL:
25602 case RCR64rCL_EVEX:
25603 case RCR64rCL_ND:
25604 case RCR64ri:
25605 case RCR64ri_EVEX:
25606 case RCR64ri_ND:
25607 case RCR8m1:
25608 case RCR8m1_EVEX:
25609 case RCR8m1_ND:
25610 case RCR8mCL:
25611 case RCR8mCL_EVEX:
25612 case RCR8mCL_ND:
25613 case RCR8mi:
25614 case RCR8mi_EVEX:
25615 case RCR8mi_ND:
25616 case RCR8r1:
25617 case RCR8r1_EVEX:
25618 case RCR8r1_ND:
25619 case RCR8rCL:
25620 case RCR8rCL_EVEX:
25621 case RCR8rCL_ND:
25622 case RCR8ri:
25623 case RCR8ri_EVEX:
25624 case RCR8ri_ND:
25625 return true;
25626 }
25627 return false;
25628}
25629
25630bool isFNSTCW(unsigned Opcode) {
25631 return Opcode == FNSTCW16m;
25632}
25633
25634bool isVPMOVSDW(unsigned Opcode) {
25635 switch (Opcode) {
25636 case VPMOVSDWZ128mr:
25637 case VPMOVSDWZ128mrk:
25638 case VPMOVSDWZ128rr:
25639 case VPMOVSDWZ128rrk:
25640 case VPMOVSDWZ128rrkz:
25641 case VPMOVSDWZ256mr:
25642 case VPMOVSDWZ256mrk:
25643 case VPMOVSDWZ256rr:
25644 case VPMOVSDWZ256rrk:
25645 case VPMOVSDWZ256rrkz:
25646 case VPMOVSDWZmr:
25647 case VPMOVSDWZmrk:
25648 case VPMOVSDWZrr:
25649 case VPMOVSDWZrrk:
25650 case VPMOVSDWZrrkz:
25651 return true;
25652 }
25653 return false;
25654}
25655
25656bool isVFMSUB132SH(unsigned Opcode) {
25657 switch (Opcode) {
25658 case VFMSUB132SHZm_Int:
25659 case VFMSUB132SHZmk_Int:
25660 case VFMSUB132SHZmkz_Int:
25661 case VFMSUB132SHZr_Int:
25662 case VFMSUB132SHZrb_Int:
25663 case VFMSUB132SHZrbk_Int:
25664 case VFMSUB132SHZrbkz_Int:
25665 case VFMSUB132SHZrk_Int:
25666 case VFMSUB132SHZrkz_Int:
25667 return true;
25668 }
25669 return false;
25670}
25671
25672bool isVPCONFLICTQ(unsigned Opcode) {
25673 switch (Opcode) {
25674 case VPCONFLICTQZ128rm:
25675 case VPCONFLICTQZ128rmb:
25676 case VPCONFLICTQZ128rmbk:
25677 case VPCONFLICTQZ128rmbkz:
25678 case VPCONFLICTQZ128rmk:
25679 case VPCONFLICTQZ128rmkz:
25680 case VPCONFLICTQZ128rr:
25681 case VPCONFLICTQZ128rrk:
25682 case VPCONFLICTQZ128rrkz:
25683 case VPCONFLICTQZ256rm:
25684 case VPCONFLICTQZ256rmb:
25685 case VPCONFLICTQZ256rmbk:
25686 case VPCONFLICTQZ256rmbkz:
25687 case VPCONFLICTQZ256rmk:
25688 case VPCONFLICTQZ256rmkz:
25689 case VPCONFLICTQZ256rr:
25690 case VPCONFLICTQZ256rrk:
25691 case VPCONFLICTQZ256rrkz:
25692 case VPCONFLICTQZrm:
25693 case VPCONFLICTQZrmb:
25694 case VPCONFLICTQZrmbk:
25695 case VPCONFLICTQZrmbkz:
25696 case VPCONFLICTQZrmk:
25697 case VPCONFLICTQZrmkz:
25698 case VPCONFLICTQZrr:
25699 case VPCONFLICTQZrrk:
25700 case VPCONFLICTQZrrkz:
25701 return true;
25702 }
25703 return false;
25704}
25705
25706bool isSWAPGS(unsigned Opcode) {
25707 return Opcode == SWAPGS;
25708}
25709
25710bool isVPMOVQ2M(unsigned Opcode) {
25711 switch (Opcode) {
25712 case VPMOVQ2MZ128kr:
25713 case VPMOVQ2MZ256kr:
25714 case VPMOVQ2MZkr:
25715 return true;
25716 }
25717 return false;
25718}
25719
25720bool isVPSRAVW(unsigned Opcode) {
25721 switch (Opcode) {
25722 case VPSRAVWZ128rm:
25723 case VPSRAVWZ128rmk:
25724 case VPSRAVWZ128rmkz:
25725 case VPSRAVWZ128rr:
25726 case VPSRAVWZ128rrk:
25727 case VPSRAVWZ128rrkz:
25728 case VPSRAVWZ256rm:
25729 case VPSRAVWZ256rmk:
25730 case VPSRAVWZ256rmkz:
25731 case VPSRAVWZ256rr:
25732 case VPSRAVWZ256rrk:
25733 case VPSRAVWZ256rrkz:
25734 case VPSRAVWZrm:
25735 case VPSRAVWZrmk:
25736 case VPSRAVWZrmkz:
25737 case VPSRAVWZrr:
25738 case VPSRAVWZrrk:
25739 case VPSRAVWZrrkz:
25740 return true;
25741 }
25742 return false;
25743}
25744
25745bool isMOVDQA(unsigned Opcode) {
25746 switch (Opcode) {
25747 case MOVDQAmr:
25748 case MOVDQArm:
25749 case MOVDQArr:
25750 case MOVDQArr_REV:
25751 return true;
25752 }
25753 return false;
25754}
25755
25756bool isDIVSD(unsigned Opcode) {
25757 switch (Opcode) {
25758 case DIVSDrm_Int:
25759 case DIVSDrr_Int:
25760 return true;
25761 }
25762 return false;
25763}
25764
25765bool isPCMPGTB(unsigned Opcode) {
25766 switch (Opcode) {
25767 case MMX_PCMPGTBrm:
25768 case MMX_PCMPGTBrr:
25769 case PCMPGTBrm:
25770 case PCMPGTBrr:
25771 return true;
25772 }
25773 return false;
25774}
25775
25776bool isSHA256MSG2(unsigned Opcode) {
25777 switch (Opcode) {
25778 case SHA256MSG2rm:
25779 case SHA256MSG2rr:
25780 return true;
25781 }
25782 return false;
25783}
25784
25785bool isTTMMULTF32PS(unsigned Opcode) {
25786 return Opcode == TTMMULTF32PS;
25787}
25788
25789bool isKXORW(unsigned Opcode) {
25790 return Opcode == KXORWkk;
25791}
25792
25793bool isLIDTW(unsigned Opcode) {
25794 return Opcode == LIDT16m;
25795}
25796
25797bool isPMULHW(unsigned Opcode) {
25798 switch (Opcode) {
25799 case MMX_PMULHWrm:
25800 case MMX_PMULHWrr:
25801 case PMULHWrm:
25802 case PMULHWrr:
25803 return true;
25804 }
25805 return false;
25806}
25807
25808bool isVAESENCLAST(unsigned Opcode) {
25809 switch (Opcode) {
25810 case VAESENCLASTYrm:
25811 case VAESENCLASTYrr:
25812 case VAESENCLASTZ128rm:
25813 case VAESENCLASTZ128rr:
25814 case VAESENCLASTZ256rm:
25815 case VAESENCLASTZ256rr:
25816 case VAESENCLASTZrm:
25817 case VAESENCLASTZrr:
25818 case VAESENCLASTrm:
25819 case VAESENCLASTrr:
25820 return true;
25821 }
25822 return false;
25823}
25824
25825bool isVINSERTI32X8(unsigned Opcode) {
25826 switch (Opcode) {
25827 case VINSERTI32X8Zrmi:
25828 case VINSERTI32X8Zrmik:
25829 case VINSERTI32X8Zrmikz:
25830 case VINSERTI32X8Zrri:
25831 case VINSERTI32X8Zrrik:
25832 case VINSERTI32X8Zrrikz:
25833 return true;
25834 }
25835 return false;
25836}
25837
25838bool isVRCPPS(unsigned Opcode) {
25839 switch (Opcode) {
25840 case VRCPPSYm:
25841 case VRCPPSYr:
25842 case VRCPPSm:
25843 case VRCPPSr:
25844 return true;
25845 }
25846 return false;
25847}
25848
25849bool isVRSQRTBF16(unsigned Opcode) {
25850 switch (Opcode) {
25851 case VRSQRTBF16Z128m:
25852 case VRSQRTBF16Z128mb:
25853 case VRSQRTBF16Z128mbk:
25854 case VRSQRTBF16Z128mbkz:
25855 case VRSQRTBF16Z128mk:
25856 case VRSQRTBF16Z128mkz:
25857 case VRSQRTBF16Z128r:
25858 case VRSQRTBF16Z128rk:
25859 case VRSQRTBF16Z128rkz:
25860 case VRSQRTBF16Z256m:
25861 case VRSQRTBF16Z256mb:
25862 case VRSQRTBF16Z256mbk:
25863 case VRSQRTBF16Z256mbkz:
25864 case VRSQRTBF16Z256mk:
25865 case VRSQRTBF16Z256mkz:
25866 case VRSQRTBF16Z256r:
25867 case VRSQRTBF16Z256rk:
25868 case VRSQRTBF16Z256rkz:
25869 case VRSQRTBF16Zm:
25870 case VRSQRTBF16Zmb:
25871 case VRSQRTBF16Zmbk:
25872 case VRSQRTBF16Zmbkz:
25873 case VRSQRTBF16Zmk:
25874 case VRSQRTBF16Zmkz:
25875 case VRSQRTBF16Zr:
25876 case VRSQRTBF16Zrk:
25877 case VRSQRTBF16Zrkz:
25878 return true;
25879 }
25880 return false;
25881}
25882
25883bool isVGATHERQPS(unsigned Opcode) {
25884 switch (Opcode) {
25885 case VGATHERQPSYrm:
25886 case VGATHERQPSZ128rm:
25887 case VGATHERQPSZ256rm:
25888 case VGATHERQPSZrm:
25889 case VGATHERQPSrm:
25890 return true;
25891 }
25892 return false;
25893}
25894
25895bool isCTESTCC(unsigned Opcode) {
25896 switch (Opcode) {
25897 case CTEST16mi:
25898 case CTEST16mr:
25899 case CTEST16ri:
25900 case CTEST16rr:
25901 case CTEST32mi:
25902 case CTEST32mr:
25903 case CTEST32ri:
25904 case CTEST32rr:
25905 case CTEST64mi32:
25906 case CTEST64mr:
25907 case CTEST64ri32:
25908 case CTEST64rr:
25909 case CTEST8mi:
25910 case CTEST8mr:
25911 case CTEST8ri:
25912 case CTEST8rr:
25913 return true;
25914 }
25915 return false;
25916}
25917
25918bool isPMADDWD(unsigned Opcode) {
25919 switch (Opcode) {
25920 case MMX_PMADDWDrm:
25921 case MMX_PMADDWDrr:
25922 case PMADDWDrm:
25923 case PMADDWDrr:
25924 return true;
25925 }
25926 return false;
25927}
25928
25929bool isUCOMISS(unsigned Opcode) {
25930 switch (Opcode) {
25931 case UCOMISSrm:
25932 case UCOMISSrr:
25933 return true;
25934 }
25935 return false;
25936}
25937
25938bool isXGETBV(unsigned Opcode) {
25939 return Opcode == XGETBV;
25940}
25941
25942bool isVCVTPD2QQ(unsigned Opcode) {
25943 switch (Opcode) {
25944 case VCVTPD2QQZ128rm:
25945 case VCVTPD2QQZ128rmb:
25946 case VCVTPD2QQZ128rmbk:
25947 case VCVTPD2QQZ128rmbkz:
25948 case VCVTPD2QQZ128rmk:
25949 case VCVTPD2QQZ128rmkz:
25950 case VCVTPD2QQZ128rr:
25951 case VCVTPD2QQZ128rrk:
25952 case VCVTPD2QQZ128rrkz:
25953 case VCVTPD2QQZ256rm:
25954 case VCVTPD2QQZ256rmb:
25955 case VCVTPD2QQZ256rmbk:
25956 case VCVTPD2QQZ256rmbkz:
25957 case VCVTPD2QQZ256rmk:
25958 case VCVTPD2QQZ256rmkz:
25959 case VCVTPD2QQZ256rr:
25960 case VCVTPD2QQZ256rrk:
25961 case VCVTPD2QQZ256rrkz:
25962 case VCVTPD2QQZrm:
25963 case VCVTPD2QQZrmb:
25964 case VCVTPD2QQZrmbk:
25965 case VCVTPD2QQZrmbkz:
25966 case VCVTPD2QQZrmk:
25967 case VCVTPD2QQZrmkz:
25968 case VCVTPD2QQZrr:
25969 case VCVTPD2QQZrrb:
25970 case VCVTPD2QQZrrbk:
25971 case VCVTPD2QQZrrbkz:
25972 case VCVTPD2QQZrrk:
25973 case VCVTPD2QQZrrkz:
25974 return true;
25975 }
25976 return false;
25977}
25978
25979bool isVGETEXPPS(unsigned Opcode) {
25980 switch (Opcode) {
25981 case VGETEXPPSZ128m:
25982 case VGETEXPPSZ128mb:
25983 case VGETEXPPSZ128mbk:
25984 case VGETEXPPSZ128mbkz:
25985 case VGETEXPPSZ128mk:
25986 case VGETEXPPSZ128mkz:
25987 case VGETEXPPSZ128r:
25988 case VGETEXPPSZ128rk:
25989 case VGETEXPPSZ128rkz:
25990 case VGETEXPPSZ256m:
25991 case VGETEXPPSZ256mb:
25992 case VGETEXPPSZ256mbk:
25993 case VGETEXPPSZ256mbkz:
25994 case VGETEXPPSZ256mk:
25995 case VGETEXPPSZ256mkz:
25996 case VGETEXPPSZ256r:
25997 case VGETEXPPSZ256rk:
25998 case VGETEXPPSZ256rkz:
25999 case VGETEXPPSZm:
26000 case VGETEXPPSZmb:
26001 case VGETEXPPSZmbk:
26002 case VGETEXPPSZmbkz:
26003 case VGETEXPPSZmk:
26004 case VGETEXPPSZmkz:
26005 case VGETEXPPSZr:
26006 case VGETEXPPSZrb:
26007 case VGETEXPPSZrbk:
26008 case VGETEXPPSZrbkz:
26009 case VGETEXPPSZrk:
26010 case VGETEXPPSZrkz:
26011 return true;
26012 }
26013 return false;
26014}
26015
26016bool isFISTP(unsigned Opcode) {
26017 switch (Opcode) {
26018 case IST_FP16m:
26019 case IST_FP32m:
26020 case IST_FP64m:
26021 return true;
26022 }
26023 return false;
26024}
26025
26026bool isVINSERTF64X4(unsigned Opcode) {
26027 switch (Opcode) {
26028 case VINSERTF64X4Zrmi:
26029 case VINSERTF64X4Zrmik:
26030 case VINSERTF64X4Zrmikz:
26031 case VINSERTF64X4Zrri:
26032 case VINSERTF64X4Zrrik:
26033 case VINSERTF64X4Zrrikz:
26034 return true;
26035 }
26036 return false;
26037}
26038
26039bool isVMOVDQU16(unsigned Opcode) {
26040 switch (Opcode) {
26041 case VMOVDQU16Z128mr:
26042 case VMOVDQU16Z128mrk:
26043 case VMOVDQU16Z128rm:
26044 case VMOVDQU16Z128rmk:
26045 case VMOVDQU16Z128rmkz:
26046 case VMOVDQU16Z128rr:
26047 case VMOVDQU16Z128rr_REV:
26048 case VMOVDQU16Z128rrk:
26049 case VMOVDQU16Z128rrk_REV:
26050 case VMOVDQU16Z128rrkz:
26051 case VMOVDQU16Z128rrkz_REV:
26052 case VMOVDQU16Z256mr:
26053 case VMOVDQU16Z256mrk:
26054 case VMOVDQU16Z256rm:
26055 case VMOVDQU16Z256rmk:
26056 case VMOVDQU16Z256rmkz:
26057 case VMOVDQU16Z256rr:
26058 case VMOVDQU16Z256rr_REV:
26059 case VMOVDQU16Z256rrk:
26060 case VMOVDQU16Z256rrk_REV:
26061 case VMOVDQU16Z256rrkz:
26062 case VMOVDQU16Z256rrkz_REV:
26063 case VMOVDQU16Zmr:
26064 case VMOVDQU16Zmrk:
26065 case VMOVDQU16Zrm:
26066 case VMOVDQU16Zrmk:
26067 case VMOVDQU16Zrmkz:
26068 case VMOVDQU16Zrr:
26069 case VMOVDQU16Zrr_REV:
26070 case VMOVDQU16Zrrk:
26071 case VMOVDQU16Zrrk_REV:
26072 case VMOVDQU16Zrrkz:
26073 case VMOVDQU16Zrrkz_REV:
26074 return true;
26075 }
26076 return false;
26077}
26078
26079bool isVFMADD132PH(unsigned Opcode) {
26080 switch (Opcode) {
26081 case VFMADD132PHZ128m:
26082 case VFMADD132PHZ128mb:
26083 case VFMADD132PHZ128mbk:
26084 case VFMADD132PHZ128mbkz:
26085 case VFMADD132PHZ128mk:
26086 case VFMADD132PHZ128mkz:
26087 case VFMADD132PHZ128r:
26088 case VFMADD132PHZ128rk:
26089 case VFMADD132PHZ128rkz:
26090 case VFMADD132PHZ256m:
26091 case VFMADD132PHZ256mb:
26092 case VFMADD132PHZ256mbk:
26093 case VFMADD132PHZ256mbkz:
26094 case VFMADD132PHZ256mk:
26095 case VFMADD132PHZ256mkz:
26096 case VFMADD132PHZ256r:
26097 case VFMADD132PHZ256rk:
26098 case VFMADD132PHZ256rkz:
26099 case VFMADD132PHZm:
26100 case VFMADD132PHZmb:
26101 case VFMADD132PHZmbk:
26102 case VFMADD132PHZmbkz:
26103 case VFMADD132PHZmk:
26104 case VFMADD132PHZmkz:
26105 case VFMADD132PHZr:
26106 case VFMADD132PHZrb:
26107 case VFMADD132PHZrbk:
26108 case VFMADD132PHZrbkz:
26109 case VFMADD132PHZrk:
26110 case VFMADD132PHZrkz:
26111 return true;
26112 }
26113 return false;
26114}
26115
26116bool isVFMSUBADD213PS(unsigned Opcode) {
26117 switch (Opcode) {
26118 case VFMSUBADD213PSYm:
26119 case VFMSUBADD213PSYr:
26120 case VFMSUBADD213PSZ128m:
26121 case VFMSUBADD213PSZ128mb:
26122 case VFMSUBADD213PSZ128mbk:
26123 case VFMSUBADD213PSZ128mbkz:
26124 case VFMSUBADD213PSZ128mk:
26125 case VFMSUBADD213PSZ128mkz:
26126 case VFMSUBADD213PSZ128r:
26127 case VFMSUBADD213PSZ128rk:
26128 case VFMSUBADD213PSZ128rkz:
26129 case VFMSUBADD213PSZ256m:
26130 case VFMSUBADD213PSZ256mb:
26131 case VFMSUBADD213PSZ256mbk:
26132 case VFMSUBADD213PSZ256mbkz:
26133 case VFMSUBADD213PSZ256mk:
26134 case VFMSUBADD213PSZ256mkz:
26135 case VFMSUBADD213PSZ256r:
26136 case VFMSUBADD213PSZ256rk:
26137 case VFMSUBADD213PSZ256rkz:
26138 case VFMSUBADD213PSZm:
26139 case VFMSUBADD213PSZmb:
26140 case VFMSUBADD213PSZmbk:
26141 case VFMSUBADD213PSZmbkz:
26142 case VFMSUBADD213PSZmk:
26143 case VFMSUBADD213PSZmkz:
26144 case VFMSUBADD213PSZr:
26145 case VFMSUBADD213PSZrb:
26146 case VFMSUBADD213PSZrbk:
26147 case VFMSUBADD213PSZrbkz:
26148 case VFMSUBADD213PSZrk:
26149 case VFMSUBADD213PSZrkz:
26150 case VFMSUBADD213PSm:
26151 case VFMSUBADD213PSr:
26152 return true;
26153 }
26154 return false;
26155}
26156
26157bool isVMOVDQU32(unsigned Opcode) {
26158 switch (Opcode) {
26159 case VMOVDQU32Z128mr:
26160 case VMOVDQU32Z128mrk:
26161 case VMOVDQU32Z128rm:
26162 case VMOVDQU32Z128rmk:
26163 case VMOVDQU32Z128rmkz:
26164 case VMOVDQU32Z128rr:
26165 case VMOVDQU32Z128rr_REV:
26166 case VMOVDQU32Z128rrk:
26167 case VMOVDQU32Z128rrk_REV:
26168 case VMOVDQU32Z128rrkz:
26169 case VMOVDQU32Z128rrkz_REV:
26170 case VMOVDQU32Z256mr:
26171 case VMOVDQU32Z256mrk:
26172 case VMOVDQU32Z256rm:
26173 case VMOVDQU32Z256rmk:
26174 case VMOVDQU32Z256rmkz:
26175 case VMOVDQU32Z256rr:
26176 case VMOVDQU32Z256rr_REV:
26177 case VMOVDQU32Z256rrk:
26178 case VMOVDQU32Z256rrk_REV:
26179 case VMOVDQU32Z256rrkz:
26180 case VMOVDQU32Z256rrkz_REV:
26181 case VMOVDQU32Zmr:
26182 case VMOVDQU32Zmrk:
26183 case VMOVDQU32Zrm:
26184 case VMOVDQU32Zrmk:
26185 case VMOVDQU32Zrmkz:
26186 case VMOVDQU32Zrr:
26187 case VMOVDQU32Zrr_REV:
26188 case VMOVDQU32Zrrk:
26189 case VMOVDQU32Zrrk_REV:
26190 case VMOVDQU32Zrrkz:
26191 case VMOVDQU32Zrrkz_REV:
26192 return true;
26193 }
26194 return false;
26195}
26196
26197bool isFUCOM(unsigned Opcode) {
26198 return Opcode == UCOM_Fr;
26199}
26200
26201bool isVFNMADD213BF16(unsigned Opcode) {
26202 switch (Opcode) {
26203 case VFNMADD213BF16Z128m:
26204 case VFNMADD213BF16Z128mb:
26205 case VFNMADD213BF16Z128mbk:
26206 case VFNMADD213BF16Z128mbkz:
26207 case VFNMADD213BF16Z128mk:
26208 case VFNMADD213BF16Z128mkz:
26209 case VFNMADD213BF16Z128r:
26210 case VFNMADD213BF16Z128rk:
26211 case VFNMADD213BF16Z128rkz:
26212 case VFNMADD213BF16Z256m:
26213 case VFNMADD213BF16Z256mb:
26214 case VFNMADD213BF16Z256mbk:
26215 case VFNMADD213BF16Z256mbkz:
26216 case VFNMADD213BF16Z256mk:
26217 case VFNMADD213BF16Z256mkz:
26218 case VFNMADD213BF16Z256r:
26219 case VFNMADD213BF16Z256rk:
26220 case VFNMADD213BF16Z256rkz:
26221 case VFNMADD213BF16Zm:
26222 case VFNMADD213BF16Zmb:
26223 case VFNMADD213BF16Zmbk:
26224 case VFNMADD213BF16Zmbkz:
26225 case VFNMADD213BF16Zmk:
26226 case VFNMADD213BF16Zmkz:
26227 case VFNMADD213BF16Zr:
26228 case VFNMADD213BF16Zrk:
26229 case VFNMADD213BF16Zrkz:
26230 return true;
26231 }
26232 return false;
26233}
26234
26235bool isHADDPS(unsigned Opcode) {
26236 switch (Opcode) {
26237 case HADDPSrm:
26238 case HADDPSrr:
26239 return true;
26240 }
26241 return false;
26242}
26243
26244bool isCMP(unsigned Opcode) {
26245 switch (Opcode) {
26246 case CMP16i16:
26247 case CMP16mi:
26248 case CMP16mi8:
26249 case CMP16mr:
26250 case CMP16ri:
26251 case CMP16ri8:
26252 case CMP16rm:
26253 case CMP16rr:
26254 case CMP16rr_REV:
26255 case CMP32i32:
26256 case CMP32mi:
26257 case CMP32mi8:
26258 case CMP32mr:
26259 case CMP32ri:
26260 case CMP32ri8:
26261 case CMP32rm:
26262 case CMP32rr:
26263 case CMP32rr_REV:
26264 case CMP64i32:
26265 case CMP64mi32:
26266 case CMP64mi8:
26267 case CMP64mr:
26268 case CMP64ri32:
26269 case CMP64ri8:
26270 case CMP64rm:
26271 case CMP64rr:
26272 case CMP64rr_REV:
26273 case CMP8i8:
26274 case CMP8mi:
26275 case CMP8mi8:
26276 case CMP8mr:
26277 case CMP8ri:
26278 case CMP8ri8:
26279 case CMP8rm:
26280 case CMP8rr:
26281 case CMP8rr_REV:
26282 return true;
26283 }
26284 return false;
26285}
26286
26287bool isCVTTPS2PI(unsigned Opcode) {
26288 switch (Opcode) {
26289 case MMX_CVTTPS2PIrm:
26290 case MMX_CVTTPS2PIrr:
26291 return true;
26292 }
26293 return false;
26294}
26295
26296bool isIRETQ(unsigned Opcode) {
26297 return Opcode == IRET64;
26298}
26299
26300bool isPF2IW(unsigned Opcode) {
26301 switch (Opcode) {
26302 case PF2IWrm:
26303 case PF2IWrr:
26304 return true;
26305 }
26306 return false;
26307}
26308
26309bool isPSHUFD(unsigned Opcode) {
26310 switch (Opcode) {
26311 case PSHUFDmi:
26312 case PSHUFDri:
26313 return true;
26314 }
26315 return false;
26316}
26317
26318bool isVDPPD(unsigned Opcode) {
26319 switch (Opcode) {
26320 case VDPPDrmi:
26321 case VDPPDrri:
26322 return true;
26323 }
26324 return false;
26325}
26326
26327bool isPSHUFHW(unsigned Opcode) {
26328 switch (Opcode) {
26329 case PSHUFHWmi:
26330 case PSHUFHWri:
26331 return true;
26332 }
26333 return false;
26334}
26335
26336bool isRMPADJUST(unsigned Opcode) {
26337 return Opcode == RMPADJUST;
26338}
26339
26340bool isPI2FW(unsigned Opcode) {
26341 switch (Opcode) {
26342 case PI2FWrm:
26343 case PI2FWrr:
26344 return true;
26345 }
26346 return false;
26347}
26348
26349bool isVCVTTPH2QQ(unsigned Opcode) {
26350 switch (Opcode) {
26351 case VCVTTPH2QQZ128rm:
26352 case VCVTTPH2QQZ128rmb:
26353 case VCVTTPH2QQZ128rmbk:
26354 case VCVTTPH2QQZ128rmbkz:
26355 case VCVTTPH2QQZ128rmk:
26356 case VCVTTPH2QQZ128rmkz:
26357 case VCVTTPH2QQZ128rr:
26358 case VCVTTPH2QQZ128rrk:
26359 case VCVTTPH2QQZ128rrkz:
26360 case VCVTTPH2QQZ256rm:
26361 case VCVTTPH2QQZ256rmb:
26362 case VCVTTPH2QQZ256rmbk:
26363 case VCVTTPH2QQZ256rmbkz:
26364 case VCVTTPH2QQZ256rmk:
26365 case VCVTTPH2QQZ256rmkz:
26366 case VCVTTPH2QQZ256rr:
26367 case VCVTTPH2QQZ256rrk:
26368 case VCVTTPH2QQZ256rrkz:
26369 case VCVTTPH2QQZrm:
26370 case VCVTTPH2QQZrmb:
26371 case VCVTTPH2QQZrmbk:
26372 case VCVTTPH2QQZrmbkz:
26373 case VCVTTPH2QQZrmk:
26374 case VCVTTPH2QQZrmkz:
26375 case VCVTTPH2QQZrr:
26376 case VCVTTPH2QQZrrb:
26377 case VCVTTPH2QQZrrbk:
26378 case VCVTTPH2QQZrrbkz:
26379 case VCVTTPH2QQZrrk:
26380 case VCVTTPH2QQZrrkz:
26381 return true;
26382 }
26383 return false;
26384}
26385
26386bool isDIVPD(unsigned Opcode) {
26387 switch (Opcode) {
26388 case DIVPDrm:
26389 case DIVPDrr:
26390 return true;
26391 }
26392 return false;
26393}
26394
26395bool isCLFLUSH(unsigned Opcode) {
26396 return Opcode == CLFLUSH;
26397}
26398
26399bool isVPMINUW(unsigned Opcode) {
26400 switch (Opcode) {
26401 case VPMINUWYrm:
26402 case VPMINUWYrr:
26403 case VPMINUWZ128rm:
26404 case VPMINUWZ128rmk:
26405 case VPMINUWZ128rmkz:
26406 case VPMINUWZ128rr:
26407 case VPMINUWZ128rrk:
26408 case VPMINUWZ128rrkz:
26409 case VPMINUWZ256rm:
26410 case VPMINUWZ256rmk:
26411 case VPMINUWZ256rmkz:
26412 case VPMINUWZ256rr:
26413 case VPMINUWZ256rrk:
26414 case VPMINUWZ256rrkz:
26415 case VPMINUWZrm:
26416 case VPMINUWZrmk:
26417 case VPMINUWZrmkz:
26418 case VPMINUWZrr:
26419 case VPMINUWZrrk:
26420 case VPMINUWZrrkz:
26421 case VPMINUWrm:
26422 case VPMINUWrr:
26423 return true;
26424 }
26425 return false;
26426}
26427
26428bool isIN(unsigned Opcode) {
26429 switch (Opcode) {
26430 case IN16ri:
26431 case IN16rr:
26432 case IN32ri:
26433 case IN32rr:
26434 case IN8ri:
26435 case IN8rr:
26436 return true;
26437 }
26438 return false;
26439}
26440
26441bool isWRPKRU(unsigned Opcode) {
26442 return Opcode == WRPKRUr;
26443}
26444
26445bool isINSERTPS(unsigned Opcode) {
26446 switch (Opcode) {
26447 case INSERTPSrmi:
26448 case INSERTPSrri:
26449 return true;
26450 }
26451 return false;
26452}
26453
26454bool isAAM(unsigned Opcode) {
26455 return Opcode == AAM8i8;
26456}
26457
26458bool isVPHADDUDQ(unsigned Opcode) {
26459 switch (Opcode) {
26460 case VPHADDUDQrm:
26461 case VPHADDUDQrr:
26462 return true;
26463 }
26464 return false;
26465}
26466
26467bool isVSHA512MSG1(unsigned Opcode) {
26468 return Opcode == VSHA512MSG1rr;
26469}
26470
26471bool isDIVPS(unsigned Opcode) {
26472 switch (Opcode) {
26473 case DIVPSrm:
26474 case DIVPSrr:
26475 return true;
26476 }
26477 return false;
26478}
26479
26480bool isKNOTB(unsigned Opcode) {
26481 return Opcode == KNOTBkk;
26482}
26483
26484bool isBLSFILL(unsigned Opcode) {
26485 switch (Opcode) {
26486 case BLSFILL32rm:
26487 case BLSFILL32rr:
26488 case BLSFILL64rm:
26489 case BLSFILL64rr:
26490 return true;
26491 }
26492 return false;
26493}
26494
26495bool isVPCMPGTQ(unsigned Opcode) {
26496 switch (Opcode) {
26497 case VPCMPGTQYrm:
26498 case VPCMPGTQYrr:
26499 case VPCMPGTQZ128rm:
26500 case VPCMPGTQZ128rmb:
26501 case VPCMPGTQZ128rmbk:
26502 case VPCMPGTQZ128rmk:
26503 case VPCMPGTQZ128rr:
26504 case VPCMPGTQZ128rrk:
26505 case VPCMPGTQZ256rm:
26506 case VPCMPGTQZ256rmb:
26507 case VPCMPGTQZ256rmbk:
26508 case VPCMPGTQZ256rmk:
26509 case VPCMPGTQZ256rr:
26510 case VPCMPGTQZ256rrk:
26511 case VPCMPGTQZrm:
26512 case VPCMPGTQZrmb:
26513 case VPCMPGTQZrmbk:
26514 case VPCMPGTQZrmk:
26515 case VPCMPGTQZrr:
26516 case VPCMPGTQZrrk:
26517 case VPCMPGTQrm:
26518 case VPCMPGTQrr:
26519 return true;
26520 }
26521 return false;
26522}
26523
26524bool isMINSD(unsigned Opcode) {
26525 switch (Opcode) {
26526 case MINSDrm_Int:
26527 case MINSDrr_Int:
26528 return true;
26529 }
26530 return false;
26531}
26532
26533bool isFPREM(unsigned Opcode) {
26534 return Opcode == FPREM;
26535}
26536
26537bool isVPUNPCKHQDQ(unsigned Opcode) {
26538 switch (Opcode) {
26539 case VPUNPCKHQDQYrm:
26540 case VPUNPCKHQDQYrr:
26541 case VPUNPCKHQDQZ128rm:
26542 case VPUNPCKHQDQZ128rmb:
26543 case VPUNPCKHQDQZ128rmbk:
26544 case VPUNPCKHQDQZ128rmbkz:
26545 case VPUNPCKHQDQZ128rmk:
26546 case VPUNPCKHQDQZ128rmkz:
26547 case VPUNPCKHQDQZ128rr:
26548 case VPUNPCKHQDQZ128rrk:
26549 case VPUNPCKHQDQZ128rrkz:
26550 case VPUNPCKHQDQZ256rm:
26551 case VPUNPCKHQDQZ256rmb:
26552 case VPUNPCKHQDQZ256rmbk:
26553 case VPUNPCKHQDQZ256rmbkz:
26554 case VPUNPCKHQDQZ256rmk:
26555 case VPUNPCKHQDQZ256rmkz:
26556 case VPUNPCKHQDQZ256rr:
26557 case VPUNPCKHQDQZ256rrk:
26558 case VPUNPCKHQDQZ256rrkz:
26559 case VPUNPCKHQDQZrm:
26560 case VPUNPCKHQDQZrmb:
26561 case VPUNPCKHQDQZrmbk:
26562 case VPUNPCKHQDQZrmbkz:
26563 case VPUNPCKHQDQZrmk:
26564 case VPUNPCKHQDQZrmkz:
26565 case VPUNPCKHQDQZrr:
26566 case VPUNPCKHQDQZrrk:
26567 case VPUNPCKHQDQZrrkz:
26568 case VPUNPCKHQDQrm:
26569 case VPUNPCKHQDQrr:
26570 return true;
26571 }
26572 return false;
26573}
26574
26575bool isMINPD(unsigned Opcode) {
26576 switch (Opcode) {
26577 case MINPDrm:
26578 case MINPDrr:
26579 return true;
26580 }
26581 return false;
26582}
26583
26584bool isVCVTTPD2QQ(unsigned Opcode) {
26585 switch (Opcode) {
26586 case VCVTTPD2QQZ128rm:
26587 case VCVTTPD2QQZ128rmb:
26588 case VCVTTPD2QQZ128rmbk:
26589 case VCVTTPD2QQZ128rmbkz:
26590 case VCVTTPD2QQZ128rmk:
26591 case VCVTTPD2QQZ128rmkz:
26592 case VCVTTPD2QQZ128rr:
26593 case VCVTTPD2QQZ128rrk:
26594 case VCVTTPD2QQZ128rrkz:
26595 case VCVTTPD2QQZ256rm:
26596 case VCVTTPD2QQZ256rmb:
26597 case VCVTTPD2QQZ256rmbk:
26598 case VCVTTPD2QQZ256rmbkz:
26599 case VCVTTPD2QQZ256rmk:
26600 case VCVTTPD2QQZ256rmkz:
26601 case VCVTTPD2QQZ256rr:
26602 case VCVTTPD2QQZ256rrk:
26603 case VCVTTPD2QQZ256rrkz:
26604 case VCVTTPD2QQZrm:
26605 case VCVTTPD2QQZrmb:
26606 case VCVTTPD2QQZrmbk:
26607 case VCVTTPD2QQZrmbkz:
26608 case VCVTTPD2QQZrmk:
26609 case VCVTTPD2QQZrmkz:
26610 case VCVTTPD2QQZrr:
26611 case VCVTTPD2QQZrrb:
26612 case VCVTTPD2QQZrrbk:
26613 case VCVTTPD2QQZrrbkz:
26614 case VCVTTPD2QQZrrk:
26615 case VCVTTPD2QQZrrkz:
26616 return true;
26617 }
26618 return false;
26619}
26620
26621bool isVFMSUBPD(unsigned Opcode) {
26622 switch (Opcode) {
26623 case VFMSUBPD4Ymr:
26624 case VFMSUBPD4Yrm:
26625 case VFMSUBPD4Yrr:
26626 case VFMSUBPD4Yrr_REV:
26627 case VFMSUBPD4mr:
26628 case VFMSUBPD4rm:
26629 case VFMSUBPD4rr:
26630 case VFMSUBPD4rr_REV:
26631 return true;
26632 }
26633 return false;
26634}
26635
26636bool isV4FMADDSS(unsigned Opcode) {
26637 switch (Opcode) {
26638 case V4FMADDSSrm:
26639 case V4FMADDSSrmk:
26640 case V4FMADDSSrmkz:
26641 return true;
26642 }
26643 return false;
26644}
26645
26646bool isCPUID(unsigned Opcode) {
26647 return Opcode == CPUID;
26648}
26649
26650bool isSETCC(unsigned Opcode) {
26651 switch (Opcode) {
26652 case SETCCm:
26653 case SETCCm_EVEX:
26654 case SETCCr:
26655 case SETCCr_EVEX:
26656 return true;
26657 }
26658 return false;
26659}
26660
26661bool isVPDPWUUD(unsigned Opcode) {
26662 switch (Opcode) {
26663 case VPDPWUUDYrm:
26664 case VPDPWUUDYrr:
26665 case VPDPWUUDZ128m:
26666 case VPDPWUUDZ128mb:
26667 case VPDPWUUDZ128mbk:
26668 case VPDPWUUDZ128mbkz:
26669 case VPDPWUUDZ128mk:
26670 case VPDPWUUDZ128mkz:
26671 case VPDPWUUDZ128r:
26672 case VPDPWUUDZ128rk:
26673 case VPDPWUUDZ128rkz:
26674 case VPDPWUUDZ256m:
26675 case VPDPWUUDZ256mb:
26676 case VPDPWUUDZ256mbk:
26677 case VPDPWUUDZ256mbkz:
26678 case VPDPWUUDZ256mk:
26679 case VPDPWUUDZ256mkz:
26680 case VPDPWUUDZ256r:
26681 case VPDPWUUDZ256rk:
26682 case VPDPWUUDZ256rkz:
26683 case VPDPWUUDZm:
26684 case VPDPWUUDZmb:
26685 case VPDPWUUDZmbk:
26686 case VPDPWUUDZmbkz:
26687 case VPDPWUUDZmk:
26688 case VPDPWUUDZmkz:
26689 case VPDPWUUDZr:
26690 case VPDPWUUDZrk:
26691 case VPDPWUUDZrkz:
26692 case VPDPWUUDrm:
26693 case VPDPWUUDrr:
26694 return true;
26695 }
26696 return false;
26697}
26698
26699bool isVCVTTPS2IUBS(unsigned Opcode) {
26700 switch (Opcode) {
26701 case VCVTTPS2IUBSZ128rm:
26702 case VCVTTPS2IUBSZ128rmb:
26703 case VCVTTPS2IUBSZ128rmbk:
26704 case VCVTTPS2IUBSZ128rmbkz:
26705 case VCVTTPS2IUBSZ128rmk:
26706 case VCVTTPS2IUBSZ128rmkz:
26707 case VCVTTPS2IUBSZ128rr:
26708 case VCVTTPS2IUBSZ128rrk:
26709 case VCVTTPS2IUBSZ128rrkz:
26710 case VCVTTPS2IUBSZ256rm:
26711 case VCVTTPS2IUBSZ256rmb:
26712 case VCVTTPS2IUBSZ256rmbk:
26713 case VCVTTPS2IUBSZ256rmbkz:
26714 case VCVTTPS2IUBSZ256rmk:
26715 case VCVTTPS2IUBSZ256rmkz:
26716 case VCVTTPS2IUBSZ256rr:
26717 case VCVTTPS2IUBSZ256rrk:
26718 case VCVTTPS2IUBSZ256rrkz:
26719 case VCVTTPS2IUBSZrm:
26720 case VCVTTPS2IUBSZrmb:
26721 case VCVTTPS2IUBSZrmbk:
26722 case VCVTTPS2IUBSZrmbkz:
26723 case VCVTTPS2IUBSZrmk:
26724 case VCVTTPS2IUBSZrmkz:
26725 case VCVTTPS2IUBSZrr:
26726 case VCVTTPS2IUBSZrrb:
26727 case VCVTTPS2IUBSZrrbk:
26728 case VCVTTPS2IUBSZrrbkz:
26729 case VCVTTPS2IUBSZrrk:
26730 case VCVTTPS2IUBSZrrkz:
26731 return true;
26732 }
26733 return false;
26734}
26735
26736bool isPMOVSXDQ(unsigned Opcode) {
26737 switch (Opcode) {
26738 case PMOVSXDQrm:
26739 case PMOVSXDQrr:
26740 return true;
26741 }
26742 return false;
26743}
26744
26745bool isMWAIT(unsigned Opcode) {
26746 return Opcode == MWAITrr;
26747}
26748
26749bool isVPEXTRB(unsigned Opcode) {
26750 switch (Opcode) {
26751 case VPEXTRBZmri:
26752 case VPEXTRBZrri:
26753 case VPEXTRBmri:
26754 case VPEXTRBrri:
26755 return true;
26756 }
26757 return false;
26758}
26759
26760bool isINVVPID(unsigned Opcode) {
26761 switch (Opcode) {
26762 case INVVPID32:
26763 case INVVPID64:
26764 case INVVPID64_EVEX:
26765 return true;
26766 }
26767 return false;
26768}
26769
26770bool isVPSHUFD(unsigned Opcode) {
26771 switch (Opcode) {
26772 case VPSHUFDYmi:
26773 case VPSHUFDYri:
26774 case VPSHUFDZ128mbi:
26775 case VPSHUFDZ128mbik:
26776 case VPSHUFDZ128mbikz:
26777 case VPSHUFDZ128mi:
26778 case VPSHUFDZ128mik:
26779 case VPSHUFDZ128mikz:
26780 case VPSHUFDZ128ri:
26781 case VPSHUFDZ128rik:
26782 case VPSHUFDZ128rikz:
26783 case VPSHUFDZ256mbi:
26784 case VPSHUFDZ256mbik:
26785 case VPSHUFDZ256mbikz:
26786 case VPSHUFDZ256mi:
26787 case VPSHUFDZ256mik:
26788 case VPSHUFDZ256mikz:
26789 case VPSHUFDZ256ri:
26790 case VPSHUFDZ256rik:
26791 case VPSHUFDZ256rikz:
26792 case VPSHUFDZmbi:
26793 case VPSHUFDZmbik:
26794 case VPSHUFDZmbikz:
26795 case VPSHUFDZmi:
26796 case VPSHUFDZmik:
26797 case VPSHUFDZmikz:
26798 case VPSHUFDZri:
26799 case VPSHUFDZrik:
26800 case VPSHUFDZrikz:
26801 case VPSHUFDmi:
26802 case VPSHUFDri:
26803 return true;
26804 }
26805 return false;
26806}
26807
26808bool isVMINBF16(unsigned Opcode) {
26809 switch (Opcode) {
26810 case VMINBF16Z128rm:
26811 case VMINBF16Z128rmb:
26812 case VMINBF16Z128rmbk:
26813 case VMINBF16Z128rmbkz:
26814 case VMINBF16Z128rmk:
26815 case VMINBF16Z128rmkz:
26816 case VMINBF16Z128rr:
26817 case VMINBF16Z128rrk:
26818 case VMINBF16Z128rrkz:
26819 case VMINBF16Z256rm:
26820 case VMINBF16Z256rmb:
26821 case VMINBF16Z256rmbk:
26822 case VMINBF16Z256rmbkz:
26823 case VMINBF16Z256rmk:
26824 case VMINBF16Z256rmkz:
26825 case VMINBF16Z256rr:
26826 case VMINBF16Z256rrk:
26827 case VMINBF16Z256rrkz:
26828 case VMINBF16Zrm:
26829 case VMINBF16Zrmb:
26830 case VMINBF16Zrmbk:
26831 case VMINBF16Zrmbkz:
26832 case VMINBF16Zrmk:
26833 case VMINBF16Zrmkz:
26834 case VMINBF16Zrr:
26835 case VMINBF16Zrrk:
26836 case VMINBF16Zrrkz:
26837 return true;
26838 }
26839 return false;
26840}
26841
26842bool isMOVLPS(unsigned Opcode) {
26843 switch (Opcode) {
26844 case MOVLPSmr:
26845 case MOVLPSrm:
26846 return true;
26847 }
26848 return false;
26849}
26850
26851bool isVBLENDMPS(unsigned Opcode) {
26852 switch (Opcode) {
26853 case VBLENDMPSZ128rm:
26854 case VBLENDMPSZ128rmb:
26855 case VBLENDMPSZ128rmbk:
26856 case VBLENDMPSZ128rmbkz:
26857 case VBLENDMPSZ128rmk:
26858 case VBLENDMPSZ128rmkz:
26859 case VBLENDMPSZ128rr:
26860 case VBLENDMPSZ128rrk:
26861 case VBLENDMPSZ128rrkz:
26862 case VBLENDMPSZ256rm:
26863 case VBLENDMPSZ256rmb:
26864 case VBLENDMPSZ256rmbk:
26865 case VBLENDMPSZ256rmbkz:
26866 case VBLENDMPSZ256rmk:
26867 case VBLENDMPSZ256rmkz:
26868 case VBLENDMPSZ256rr:
26869 case VBLENDMPSZ256rrk:
26870 case VBLENDMPSZ256rrkz:
26871 case VBLENDMPSZrm:
26872 case VBLENDMPSZrmb:
26873 case VBLENDMPSZrmbk:
26874 case VBLENDMPSZrmbkz:
26875 case VBLENDMPSZrmk:
26876 case VBLENDMPSZrmkz:
26877 case VBLENDMPSZrr:
26878 case VBLENDMPSZrrk:
26879 case VBLENDMPSZrrkz:
26880 return true;
26881 }
26882 return false;
26883}
26884
26885bool isPMULLW(unsigned Opcode) {
26886 switch (Opcode) {
26887 case MMX_PMULLWrm:
26888 case MMX_PMULLWrr:
26889 case PMULLWrm:
26890 case PMULLWrr:
26891 return true;
26892 }
26893 return false;
26894}
26895
26896bool isVCVTSH2SI(unsigned Opcode) {
26897 switch (Opcode) {
26898 case VCVTSH2SI64Zrm_Int:
26899 case VCVTSH2SI64Zrr_Int:
26900 case VCVTSH2SI64Zrrb_Int:
26901 case VCVTSH2SIZrm_Int:
26902 case VCVTSH2SIZrr_Int:
26903 case VCVTSH2SIZrrb_Int:
26904 return true;
26905 }
26906 return false;
26907}
26908
26909bool isVPMOVSXWQ(unsigned Opcode) {
26910 switch (Opcode) {
26911 case VPMOVSXWQYrm:
26912 case VPMOVSXWQYrr:
26913 case VPMOVSXWQZ128rm:
26914 case VPMOVSXWQZ128rmk:
26915 case VPMOVSXWQZ128rmkz:
26916 case VPMOVSXWQZ128rr:
26917 case VPMOVSXWQZ128rrk:
26918 case VPMOVSXWQZ128rrkz:
26919 case VPMOVSXWQZ256rm:
26920 case VPMOVSXWQZ256rmk:
26921 case VPMOVSXWQZ256rmkz:
26922 case VPMOVSXWQZ256rr:
26923 case VPMOVSXWQZ256rrk:
26924 case VPMOVSXWQZ256rrkz:
26925 case VPMOVSXWQZrm:
26926 case VPMOVSXWQZrmk:
26927 case VPMOVSXWQZrmkz:
26928 case VPMOVSXWQZrr:
26929 case VPMOVSXWQZrrk:
26930 case VPMOVSXWQZrrkz:
26931 case VPMOVSXWQrm:
26932 case VPMOVSXWQrr:
26933 return true;
26934 }
26935 return false;
26936}
26937
26938bool isFNSTENV(unsigned Opcode) {
26939 return Opcode == FSTENVm;
26940}
26941
26942bool isVCVT2PH2BF8(unsigned Opcode) {
26943 switch (Opcode) {
26944 case VCVT2PH2BF8Z128rm:
26945 case VCVT2PH2BF8Z128rmb:
26946 case VCVT2PH2BF8Z128rmbk:
26947 case VCVT2PH2BF8Z128rmbkz:
26948 case VCVT2PH2BF8Z128rmk:
26949 case VCVT2PH2BF8Z128rmkz:
26950 case VCVT2PH2BF8Z128rr:
26951 case VCVT2PH2BF8Z128rrk:
26952 case VCVT2PH2BF8Z128rrkz:
26953 case VCVT2PH2BF8Z256rm:
26954 case VCVT2PH2BF8Z256rmb:
26955 case VCVT2PH2BF8Z256rmbk:
26956 case VCVT2PH2BF8Z256rmbkz:
26957 case VCVT2PH2BF8Z256rmk:
26958 case VCVT2PH2BF8Z256rmkz:
26959 case VCVT2PH2BF8Z256rr:
26960 case VCVT2PH2BF8Z256rrk:
26961 case VCVT2PH2BF8Z256rrkz:
26962 case VCVT2PH2BF8Zrm:
26963 case VCVT2PH2BF8Zrmb:
26964 case VCVT2PH2BF8Zrmbk:
26965 case VCVT2PH2BF8Zrmbkz:
26966 case VCVT2PH2BF8Zrmk:
26967 case VCVT2PH2BF8Zrmkz:
26968 case VCVT2PH2BF8Zrr:
26969 case VCVT2PH2BF8Zrrk:
26970 case VCVT2PH2BF8Zrrkz:
26971 return true;
26972 }
26973 return false;
26974}
26975
26976bool isVPERMI2PD(unsigned Opcode) {
26977 switch (Opcode) {
26978 case VPERMI2PDZ128rm:
26979 case VPERMI2PDZ128rmb:
26980 case VPERMI2PDZ128rmbk:
26981 case VPERMI2PDZ128rmbkz:
26982 case VPERMI2PDZ128rmk:
26983 case VPERMI2PDZ128rmkz:
26984 case VPERMI2PDZ128rr:
26985 case VPERMI2PDZ128rrk:
26986 case VPERMI2PDZ128rrkz:
26987 case VPERMI2PDZ256rm:
26988 case VPERMI2PDZ256rmb:
26989 case VPERMI2PDZ256rmbk:
26990 case VPERMI2PDZ256rmbkz:
26991 case VPERMI2PDZ256rmk:
26992 case VPERMI2PDZ256rmkz:
26993 case VPERMI2PDZ256rr:
26994 case VPERMI2PDZ256rrk:
26995 case VPERMI2PDZ256rrkz:
26996 case VPERMI2PDZrm:
26997 case VPERMI2PDZrmb:
26998 case VPERMI2PDZrmbk:
26999 case VPERMI2PDZrmbkz:
27000 case VPERMI2PDZrmk:
27001 case VPERMI2PDZrmkz:
27002 case VPERMI2PDZrr:
27003 case VPERMI2PDZrrk:
27004 case VPERMI2PDZrrkz:
27005 return true;
27006 }
27007 return false;
27008}
27009
27010bool isMAXSS(unsigned Opcode) {
27011 switch (Opcode) {
27012 case MAXSSrm_Int:
27013 case MAXSSrr_Int:
27014 return true;
27015 }
27016 return false;
27017}
27018
27019bool isCWDE(unsigned Opcode) {
27020 return Opcode == CWDE;
27021}
27022
27023bool isVBROADCASTI32X8(unsigned Opcode) {
27024 switch (Opcode) {
27025 case VBROADCASTI32X8Zrm:
27026 case VBROADCASTI32X8Zrmk:
27027 case VBROADCASTI32X8Zrmkz:
27028 return true;
27029 }
27030 return false;
27031}
27032
27033bool isINT(unsigned Opcode) {
27034 return Opcode == INT;
27035}
27036
27037bool isENCLS(unsigned Opcode) {
27038 return Opcode == ENCLS;
27039}
27040
27041bool isMOVNTQ(unsigned Opcode) {
27042 return Opcode == MMX_MOVNTQmr;
27043}
27044
27045bool isVDIVSH(unsigned Opcode) {
27046 switch (Opcode) {
27047 case VDIVSHZrm_Int:
27048 case VDIVSHZrmk_Int:
27049 case VDIVSHZrmkz_Int:
27050 case VDIVSHZrr_Int:
27051 case VDIVSHZrrb_Int:
27052 case VDIVSHZrrbk_Int:
27053 case VDIVSHZrrbkz_Int:
27054 case VDIVSHZrrk_Int:
27055 case VDIVSHZrrkz_Int:
27056 return true;
27057 }
27058 return false;
27059}
27060
27061bool isMOVHLPS(unsigned Opcode) {
27062 return Opcode == MOVHLPSrr;
27063}
27064
27065bool isVPMASKMOVD(unsigned Opcode) {
27066 switch (Opcode) {
27067 case VPMASKMOVDYmr:
27068 case VPMASKMOVDYrm:
27069 case VPMASKMOVDmr:
27070 case VPMASKMOVDrm:
27071 return true;
27072 }
27073 return false;
27074}
27075
27076bool isVMOVSD(unsigned Opcode) {
27077 switch (Opcode) {
27078 case VMOVSDZmr:
27079 case VMOVSDZmrk:
27080 case VMOVSDZrm:
27081 case VMOVSDZrmk:
27082 case VMOVSDZrmkz:
27083 case VMOVSDZrr:
27084 case VMOVSDZrr_REV:
27085 case VMOVSDZrrk:
27086 case VMOVSDZrrk_REV:
27087 case VMOVSDZrrkz:
27088 case VMOVSDZrrkz_REV:
27089 case VMOVSDmr:
27090 case VMOVSDrm:
27091 case VMOVSDrr:
27092 case VMOVSDrr_REV:
27093 return true;
27094 }
27095 return false;
27096}
27097
27098bool isVPMINUD(unsigned Opcode) {
27099 switch (Opcode) {
27100 case VPMINUDYrm:
27101 case VPMINUDYrr:
27102 case VPMINUDZ128rm:
27103 case VPMINUDZ128rmb:
27104 case VPMINUDZ128rmbk:
27105 case VPMINUDZ128rmbkz:
27106 case VPMINUDZ128rmk:
27107 case VPMINUDZ128rmkz:
27108 case VPMINUDZ128rr:
27109 case VPMINUDZ128rrk:
27110 case VPMINUDZ128rrkz:
27111 case VPMINUDZ256rm:
27112 case VPMINUDZ256rmb:
27113 case VPMINUDZ256rmbk:
27114 case VPMINUDZ256rmbkz:
27115 case VPMINUDZ256rmk:
27116 case VPMINUDZ256rmkz:
27117 case VPMINUDZ256rr:
27118 case VPMINUDZ256rrk:
27119 case VPMINUDZ256rrkz:
27120 case VPMINUDZrm:
27121 case VPMINUDZrmb:
27122 case VPMINUDZrmbk:
27123 case VPMINUDZrmbkz:
27124 case VPMINUDZrmk:
27125 case VPMINUDZrmkz:
27126 case VPMINUDZrr:
27127 case VPMINUDZrrk:
27128 case VPMINUDZrrkz:
27129 case VPMINUDrm:
27130 case VPMINUDrr:
27131 return true;
27132 }
27133 return false;
27134}
27135
27136bool isVPCMPISTRM(unsigned Opcode) {
27137 switch (Opcode) {
27138 case VPCMPISTRMrmi:
27139 case VPCMPISTRMrri:
27140 return true;
27141 }
27142 return false;
27143}
27144
27145bool isVGETMANTSD(unsigned Opcode) {
27146 switch (Opcode) {
27147 case VGETMANTSDZrmi:
27148 case VGETMANTSDZrmik:
27149 case VGETMANTSDZrmikz:
27150 case VGETMANTSDZrri:
27151 case VGETMANTSDZrrib:
27152 case VGETMANTSDZrribk:
27153 case VGETMANTSDZrribkz:
27154 case VGETMANTSDZrrik:
27155 case VGETMANTSDZrrikz:
27156 return true;
27157 }
27158 return false;
27159}
27160
27161bool isKSHIFTRW(unsigned Opcode) {
27162 return Opcode == KSHIFTRWki;
27163}
27164
27165bool isAESDECLAST(unsigned Opcode) {
27166 switch (Opcode) {
27167 case AESDECLASTrm:
27168 case AESDECLASTrr:
27169 return true;
27170 }
27171 return false;
27172}
27173
27174bool isVFNMSUB231BF16(unsigned Opcode) {
27175 switch (Opcode) {
27176 case VFNMSUB231BF16Z128m:
27177 case VFNMSUB231BF16Z128mb:
27178 case VFNMSUB231BF16Z128mbk:
27179 case VFNMSUB231BF16Z128mbkz:
27180 case VFNMSUB231BF16Z128mk:
27181 case VFNMSUB231BF16Z128mkz:
27182 case VFNMSUB231BF16Z128r:
27183 case VFNMSUB231BF16Z128rk:
27184 case VFNMSUB231BF16Z128rkz:
27185 case VFNMSUB231BF16Z256m:
27186 case VFNMSUB231BF16Z256mb:
27187 case VFNMSUB231BF16Z256mbk:
27188 case VFNMSUB231BF16Z256mbkz:
27189 case VFNMSUB231BF16Z256mk:
27190 case VFNMSUB231BF16Z256mkz:
27191 case VFNMSUB231BF16Z256r:
27192 case VFNMSUB231BF16Z256rk:
27193 case VFNMSUB231BF16Z256rkz:
27194 case VFNMSUB231BF16Zm:
27195 case VFNMSUB231BF16Zmb:
27196 case VFNMSUB231BF16Zmbk:
27197 case VFNMSUB231BF16Zmbkz:
27198 case VFNMSUB231BF16Zmk:
27199 case VFNMSUB231BF16Zmkz:
27200 case VFNMSUB231BF16Zr:
27201 case VFNMSUB231BF16Zrk:
27202 case VFNMSUB231BF16Zrkz:
27203 return true;
27204 }
27205 return false;
27206}
27207
27208bool isVMPTRST(unsigned Opcode) {
27209 return Opcode == VMPTRSTm;
27210}
27211
27212bool isLLDT(unsigned Opcode) {
27213 switch (Opcode) {
27214 case LLDT16m:
27215 case LLDT16r:
27216 return true;
27217 }
27218 return false;
27219}
27220
27221bool isVPTESTMB(unsigned Opcode) {
27222 switch (Opcode) {
27223 case VPTESTMBZ128rm:
27224 case VPTESTMBZ128rmk:
27225 case VPTESTMBZ128rr:
27226 case VPTESTMBZ128rrk:
27227 case VPTESTMBZ256rm:
27228 case VPTESTMBZ256rmk:
27229 case VPTESTMBZ256rr:
27230 case VPTESTMBZ256rrk:
27231 case VPTESTMBZrm:
27232 case VPTESTMBZrmk:
27233 case VPTESTMBZrr:
27234 case VPTESTMBZrrk:
27235 return true;
27236 }
27237 return false;
27238}
27239
27240bool isMOVSB(unsigned Opcode) {
27241 return Opcode == MOVSB;
27242}
27243
27244bool isTILELOADD(unsigned Opcode) {
27245 switch (Opcode) {
27246 case TILELOADD:
27247 case TILELOADD_EVEX:
27248 return true;
27249 }
27250 return false;
27251}
27252
27253bool isKTESTB(unsigned Opcode) {
27254 return Opcode == KTESTBkk;
27255}
27256
27257bool isMOVUPD(unsigned Opcode) {
27258 switch (Opcode) {
27259 case MOVUPDmr:
27260 case MOVUPDrm:
27261 case MOVUPDrr:
27262 case MOVUPDrr_REV:
27263 return true;
27264 }
27265 return false;
27266}
27267
27268bool isLKGS(unsigned Opcode) {
27269 switch (Opcode) {
27270 case LKGS16m:
27271 case LKGS16r:
27272 return true;
27273 }
27274 return false;
27275}
27276
27277bool isSGDTW(unsigned Opcode) {
27278 return Opcode == SGDT16m;
27279}
27280
27281bool isDIVSS(unsigned Opcode) {
27282 switch (Opcode) {
27283 case DIVSSrm_Int:
27284 case DIVSSrr_Int:
27285 return true;
27286 }
27287 return false;
27288}
27289
27290bool isPUNPCKHQDQ(unsigned Opcode) {
27291 switch (Opcode) {
27292 case PUNPCKHQDQrm:
27293 case PUNPCKHQDQrr:
27294 return true;
27295 }
27296 return false;
27297}
27298
27299bool isVFMADD213SD(unsigned Opcode) {
27300 switch (Opcode) {
27301 case VFMADD213SDZm_Int:
27302 case VFMADD213SDZmk_Int:
27303 case VFMADD213SDZmkz_Int:
27304 case VFMADD213SDZr_Int:
27305 case VFMADD213SDZrb_Int:
27306 case VFMADD213SDZrbk_Int:
27307 case VFMADD213SDZrbkz_Int:
27308 case VFMADD213SDZrk_Int:
27309 case VFMADD213SDZrkz_Int:
27310 case VFMADD213SDm_Int:
27311 case VFMADD213SDr_Int:
27312 return true;
27313 }
27314 return false;
27315}
27316
27317bool isKXORD(unsigned Opcode) {
27318 return Opcode == KXORDkk;
27319}
27320
27321bool isVPMOVB2M(unsigned Opcode) {
27322 switch (Opcode) {
27323 case VPMOVB2MZ128kr:
27324 case VPMOVB2MZ256kr:
27325 case VPMOVB2MZkr:
27326 return true;
27327 }
27328 return false;
27329}
27330
27331bool isVMREAD(unsigned Opcode) {
27332 switch (Opcode) {
27333 case VMREAD32mr:
27334 case VMREAD32rr:
27335 case VMREAD64mr:
27336 case VMREAD64rr:
27337 return true;
27338 }
27339 return false;
27340}
27341
27342bool isVPDPWSSDS(unsigned Opcode) {
27343 switch (Opcode) {
27344 case VPDPWSSDSYrm:
27345 case VPDPWSSDSYrr:
27346 case VPDPWSSDSZ128m:
27347 case VPDPWSSDSZ128mb:
27348 case VPDPWSSDSZ128mbk:
27349 case VPDPWSSDSZ128mbkz:
27350 case VPDPWSSDSZ128mk:
27351 case VPDPWSSDSZ128mkz:
27352 case VPDPWSSDSZ128r:
27353 case VPDPWSSDSZ128rk:
27354 case VPDPWSSDSZ128rkz:
27355 case VPDPWSSDSZ256m:
27356 case VPDPWSSDSZ256mb:
27357 case VPDPWSSDSZ256mbk:
27358 case VPDPWSSDSZ256mbkz:
27359 case VPDPWSSDSZ256mk:
27360 case VPDPWSSDSZ256mkz:
27361 case VPDPWSSDSZ256r:
27362 case VPDPWSSDSZ256rk:
27363 case VPDPWSSDSZ256rkz:
27364 case VPDPWSSDSZm:
27365 case VPDPWSSDSZmb:
27366 case VPDPWSSDSZmbk:
27367 case VPDPWSSDSZmbkz:
27368 case VPDPWSSDSZmk:
27369 case VPDPWSSDSZmkz:
27370 case VPDPWSSDSZr:
27371 case VPDPWSSDSZrk:
27372 case VPDPWSSDSZrkz:
27373 case VPDPWSSDSrm:
27374 case VPDPWSSDSrr:
27375 return true;
27376 }
27377 return false;
27378}
27379
27380bool isTILERELEASE(unsigned Opcode) {
27381 return Opcode == TILERELEASE;
27382}
27383
27384bool isVUCOMXSH(unsigned Opcode) {
27385 switch (Opcode) {
27386 case VUCOMXSHZrm_Int:
27387 case VUCOMXSHZrr_Int:
27388 case VUCOMXSHZrrb_Int:
27389 return true;
27390 }
27391 return false;
27392}
27393
27394bool isCLFLUSHOPT(unsigned Opcode) {
27395 return Opcode == CLFLUSHOPT;
27396}
27397
27398bool isDAS(unsigned Opcode) {
27399 return Opcode == DAS;
27400}
27401
27402bool isVSCALEFPH(unsigned Opcode) {
27403 switch (Opcode) {
27404 case VSCALEFPHZ128rm:
27405 case VSCALEFPHZ128rmb:
27406 case VSCALEFPHZ128rmbk:
27407 case VSCALEFPHZ128rmbkz:
27408 case VSCALEFPHZ128rmk:
27409 case VSCALEFPHZ128rmkz:
27410 case VSCALEFPHZ128rr:
27411 case VSCALEFPHZ128rrk:
27412 case VSCALEFPHZ128rrkz:
27413 case VSCALEFPHZ256rm:
27414 case VSCALEFPHZ256rmb:
27415 case VSCALEFPHZ256rmbk:
27416 case VSCALEFPHZ256rmbkz:
27417 case VSCALEFPHZ256rmk:
27418 case VSCALEFPHZ256rmkz:
27419 case VSCALEFPHZ256rr:
27420 case VSCALEFPHZ256rrk:
27421 case VSCALEFPHZ256rrkz:
27422 case VSCALEFPHZrm:
27423 case VSCALEFPHZrmb:
27424 case VSCALEFPHZrmbk:
27425 case VSCALEFPHZrmbkz:
27426 case VSCALEFPHZrmk:
27427 case VSCALEFPHZrmkz:
27428 case VSCALEFPHZrr:
27429 case VSCALEFPHZrrb:
27430 case VSCALEFPHZrrbk:
27431 case VSCALEFPHZrrbkz:
27432 case VSCALEFPHZrrk:
27433 case VSCALEFPHZrrkz:
27434 return true;
27435 }
27436 return false;
27437}
27438
27439bool isVSUBSD(unsigned Opcode) {
27440 switch (Opcode) {
27441 case VSUBSDZrm_Int:
27442 case VSUBSDZrmk_Int:
27443 case VSUBSDZrmkz_Int:
27444 case VSUBSDZrr_Int:
27445 case VSUBSDZrrb_Int:
27446 case VSUBSDZrrbk_Int:
27447 case VSUBSDZrrbkz_Int:
27448 case VSUBSDZrrk_Int:
27449 case VSUBSDZrrkz_Int:
27450 case VSUBSDrm_Int:
27451 case VSUBSDrr_Int:
27452 return true;
27453 }
27454 return false;
27455}
27456
27457bool isVCOMISS(unsigned Opcode) {
27458 switch (Opcode) {
27459 case VCOMISSZrm:
27460 case VCOMISSZrr:
27461 case VCOMISSZrrb:
27462 case VCOMISSrm:
27463 case VCOMISSrr:
27464 return true;
27465 }
27466 return false;
27467}
27468
27469bool isVMULBF16(unsigned Opcode) {
27470 switch (Opcode) {
27471 case VMULBF16Z128rm:
27472 case VMULBF16Z128rmb:
27473 case VMULBF16Z128rmbk:
27474 case VMULBF16Z128rmbkz:
27475 case VMULBF16Z128rmk:
27476 case VMULBF16Z128rmkz:
27477 case VMULBF16Z128rr:
27478 case VMULBF16Z128rrk:
27479 case VMULBF16Z128rrkz:
27480 case VMULBF16Z256rm:
27481 case VMULBF16Z256rmb:
27482 case VMULBF16Z256rmbk:
27483 case VMULBF16Z256rmbkz:
27484 case VMULBF16Z256rmk:
27485 case VMULBF16Z256rmkz:
27486 case VMULBF16Z256rr:
27487 case VMULBF16Z256rrk:
27488 case VMULBF16Z256rrkz:
27489 case VMULBF16Zrm:
27490 case VMULBF16Zrmb:
27491 case VMULBF16Zrmbk:
27492 case VMULBF16Zrmbkz:
27493 case VMULBF16Zrmk:
27494 case VMULBF16Zrmkz:
27495 case VMULBF16Zrr:
27496 case VMULBF16Zrrk:
27497 case VMULBF16Zrrkz:
27498 return true;
27499 }
27500 return false;
27501}
27502
27503bool isORPS(unsigned Opcode) {
27504 switch (Opcode) {
27505 case ORPSrm:
27506 case ORPSrr:
27507 return true;
27508 }
27509 return false;
27510}
27511
27512bool isTDPFP16PS(unsigned Opcode) {
27513 return Opcode == TDPFP16PS;
27514}
27515
27516bool isVMAXPD(unsigned Opcode) {
27517 switch (Opcode) {
27518 case VMAXPDYrm:
27519 case VMAXPDYrr:
27520 case VMAXPDZ128rm:
27521 case VMAXPDZ128rmb:
27522 case VMAXPDZ128rmbk:
27523 case VMAXPDZ128rmbkz:
27524 case VMAXPDZ128rmk:
27525 case VMAXPDZ128rmkz:
27526 case VMAXPDZ128rr:
27527 case VMAXPDZ128rrk:
27528 case VMAXPDZ128rrkz:
27529 case VMAXPDZ256rm:
27530 case VMAXPDZ256rmb:
27531 case VMAXPDZ256rmbk:
27532 case VMAXPDZ256rmbkz:
27533 case VMAXPDZ256rmk:
27534 case VMAXPDZ256rmkz:
27535 case VMAXPDZ256rr:
27536 case VMAXPDZ256rrk:
27537 case VMAXPDZ256rrkz:
27538 case VMAXPDZrm:
27539 case VMAXPDZrmb:
27540 case VMAXPDZrmbk:
27541 case VMAXPDZrmbkz:
27542 case VMAXPDZrmk:
27543 case VMAXPDZrmkz:
27544 case VMAXPDZrr:
27545 case VMAXPDZrrb:
27546 case VMAXPDZrrbk:
27547 case VMAXPDZrrbkz:
27548 case VMAXPDZrrk:
27549 case VMAXPDZrrkz:
27550 case VMAXPDrm:
27551 case VMAXPDrr:
27552 return true;
27553 }
27554 return false;
27555}
27556
27557bool isVPMOVWB(unsigned Opcode) {
27558 switch (Opcode) {
27559 case VPMOVWBZ128mr:
27560 case VPMOVWBZ128mrk:
27561 case VPMOVWBZ128rr:
27562 case VPMOVWBZ128rrk:
27563 case VPMOVWBZ128rrkz:
27564 case VPMOVWBZ256mr:
27565 case VPMOVWBZ256mrk:
27566 case VPMOVWBZ256rr:
27567 case VPMOVWBZ256rrk:
27568 case VPMOVWBZ256rrkz:
27569 case VPMOVWBZmr:
27570 case VPMOVWBZmrk:
27571 case VPMOVWBZrr:
27572 case VPMOVWBZrrk:
27573 case VPMOVWBZrrkz:
27574 return true;
27575 }
27576 return false;
27577}
27578
27579bool isVEXP2PS(unsigned Opcode) {
27580 switch (Opcode) {
27581 case VEXP2PSZm:
27582 case VEXP2PSZmb:
27583 case VEXP2PSZmbk:
27584 case VEXP2PSZmbkz:
27585 case VEXP2PSZmk:
27586 case VEXP2PSZmkz:
27587 case VEXP2PSZr:
27588 case VEXP2PSZrb:
27589 case VEXP2PSZrbk:
27590 case VEXP2PSZrbkz:
27591 case VEXP2PSZrk:
27592 case VEXP2PSZrkz:
27593 return true;
27594 }
27595 return false;
27596}
27597
27598bool isVPGATHERDQ(unsigned Opcode) {
27599 switch (Opcode) {
27600 case VPGATHERDQYrm:
27601 case VPGATHERDQZ128rm:
27602 case VPGATHERDQZ256rm:
27603 case VPGATHERDQZrm:
27604 case VPGATHERDQrm:
27605 return true;
27606 }
27607 return false;
27608}
27609
27610bool isVPSRAVQ(unsigned Opcode) {
27611 switch (Opcode) {
27612 case VPSRAVQZ128rm:
27613 case VPSRAVQZ128rmb:
27614 case VPSRAVQZ128rmbk:
27615 case VPSRAVQZ128rmbkz:
27616 case VPSRAVQZ128rmk:
27617 case VPSRAVQZ128rmkz:
27618 case VPSRAVQZ128rr:
27619 case VPSRAVQZ128rrk:
27620 case VPSRAVQZ128rrkz:
27621 case VPSRAVQZ256rm:
27622 case VPSRAVQZ256rmb:
27623 case VPSRAVQZ256rmbk:
27624 case VPSRAVQZ256rmbkz:
27625 case VPSRAVQZ256rmk:
27626 case VPSRAVQZ256rmkz:
27627 case VPSRAVQZ256rr:
27628 case VPSRAVQZ256rrk:
27629 case VPSRAVQZ256rrkz:
27630 case VPSRAVQZrm:
27631 case VPSRAVQZrmb:
27632 case VPSRAVQZrmbk:
27633 case VPSRAVQZrmbkz:
27634 case VPSRAVQZrmk:
27635 case VPSRAVQZrmkz:
27636 case VPSRAVQZrr:
27637 case VPSRAVQZrrk:
27638 case VPSRAVQZrrkz:
27639 return true;
27640 }
27641 return false;
27642}
27643
27644bool isPCMPISTRI(unsigned Opcode) {
27645 switch (Opcode) {
27646 case PCMPISTRIrmi:
27647 case PCMPISTRIrri:
27648 return true;
27649 }
27650 return false;
27651}
27652
27653bool isVFMSUB231PD(unsigned Opcode) {
27654 switch (Opcode) {
27655 case VFMSUB231PDYm:
27656 case VFMSUB231PDYr:
27657 case VFMSUB231PDZ128m:
27658 case VFMSUB231PDZ128mb:
27659 case VFMSUB231PDZ128mbk:
27660 case VFMSUB231PDZ128mbkz:
27661 case VFMSUB231PDZ128mk:
27662 case VFMSUB231PDZ128mkz:
27663 case VFMSUB231PDZ128r:
27664 case VFMSUB231PDZ128rk:
27665 case VFMSUB231PDZ128rkz:
27666 case VFMSUB231PDZ256m:
27667 case VFMSUB231PDZ256mb:
27668 case VFMSUB231PDZ256mbk:
27669 case VFMSUB231PDZ256mbkz:
27670 case VFMSUB231PDZ256mk:
27671 case VFMSUB231PDZ256mkz:
27672 case VFMSUB231PDZ256r:
27673 case VFMSUB231PDZ256rk:
27674 case VFMSUB231PDZ256rkz:
27675 case VFMSUB231PDZm:
27676 case VFMSUB231PDZmb:
27677 case VFMSUB231PDZmbk:
27678 case VFMSUB231PDZmbkz:
27679 case VFMSUB231PDZmk:
27680 case VFMSUB231PDZmkz:
27681 case VFMSUB231PDZr:
27682 case VFMSUB231PDZrb:
27683 case VFMSUB231PDZrbk:
27684 case VFMSUB231PDZrbkz:
27685 case VFMSUB231PDZrk:
27686 case VFMSUB231PDZrkz:
27687 case VFMSUB231PDm:
27688 case VFMSUB231PDr:
27689 return true;
27690 }
27691 return false;
27692}
27693
27694bool isRDMSR(unsigned Opcode) {
27695 switch (Opcode) {
27696 case RDMSR:
27697 case RDMSRri:
27698 case RDMSRri_EVEX:
27699 return true;
27700 }
27701 return false;
27702}
27703
27704bool isKORTESTD(unsigned Opcode) {
27705 return Opcode == KORTESTDkk;
27706}
27707
27708bool isVPBLENDMW(unsigned Opcode) {
27709 switch (Opcode) {
27710 case VPBLENDMWZ128rm:
27711 case VPBLENDMWZ128rmk:
27712 case VPBLENDMWZ128rmkz:
27713 case VPBLENDMWZ128rr:
27714 case VPBLENDMWZ128rrk:
27715 case VPBLENDMWZ128rrkz:
27716 case VPBLENDMWZ256rm:
27717 case VPBLENDMWZ256rmk:
27718 case VPBLENDMWZ256rmkz:
27719 case VPBLENDMWZ256rr:
27720 case VPBLENDMWZ256rrk:
27721 case VPBLENDMWZ256rrkz:
27722 case VPBLENDMWZrm:
27723 case VPBLENDMWZrmk:
27724 case VPBLENDMWZrmkz:
27725 case VPBLENDMWZrr:
27726 case VPBLENDMWZrrk:
27727 case VPBLENDMWZrrkz:
27728 return true;
27729 }
27730 return false;
27731}
27732
27733bool isPSHUFB(unsigned Opcode) {
27734 switch (Opcode) {
27735 case MMX_PSHUFBrm:
27736 case MMX_PSHUFBrr:
27737 case PSHUFBrm:
27738 case PSHUFBrr:
27739 return true;
27740 }
27741 return false;
27742}
27743
27744bool isVDPBF16PS(unsigned Opcode) {
27745 switch (Opcode) {
27746 case VDPBF16PSZ128m:
27747 case VDPBF16PSZ128mb:
27748 case VDPBF16PSZ128mbk:
27749 case VDPBF16PSZ128mbkz:
27750 case VDPBF16PSZ128mk:
27751 case VDPBF16PSZ128mkz:
27752 case VDPBF16PSZ128r:
27753 case VDPBF16PSZ128rk:
27754 case VDPBF16PSZ128rkz:
27755 case VDPBF16PSZ256m:
27756 case VDPBF16PSZ256mb:
27757 case VDPBF16PSZ256mbk:
27758 case VDPBF16PSZ256mbkz:
27759 case VDPBF16PSZ256mk:
27760 case VDPBF16PSZ256mkz:
27761 case VDPBF16PSZ256r:
27762 case VDPBF16PSZ256rk:
27763 case VDPBF16PSZ256rkz:
27764 case VDPBF16PSZm:
27765 case VDPBF16PSZmb:
27766 case VDPBF16PSZmbk:
27767 case VDPBF16PSZmbkz:
27768 case VDPBF16PSZmk:
27769 case VDPBF16PSZmkz:
27770 case VDPBF16PSZr:
27771 case VDPBF16PSZrk:
27772 case VDPBF16PSZrkz:
27773 return true;
27774 }
27775 return false;
27776}
27777
27778bool isTDPBF16PS(unsigned Opcode) {
27779 return Opcode == TDPBF16PS;
27780}
27781
27782bool isFCMOVE(unsigned Opcode) {
27783 return Opcode == CMOVE_F;
27784}
27785
27786bool isVFMADD231BF16(unsigned Opcode) {
27787 switch (Opcode) {
27788 case VFMADD231BF16Z128m:
27789 case VFMADD231BF16Z128mb:
27790 case VFMADD231BF16Z128mbk:
27791 case VFMADD231BF16Z128mbkz:
27792 case VFMADD231BF16Z128mk:
27793 case VFMADD231BF16Z128mkz:
27794 case VFMADD231BF16Z128r:
27795 case VFMADD231BF16Z128rk:
27796 case VFMADD231BF16Z128rkz:
27797 case VFMADD231BF16Z256m:
27798 case VFMADD231BF16Z256mb:
27799 case VFMADD231BF16Z256mbk:
27800 case VFMADD231BF16Z256mbkz:
27801 case VFMADD231BF16Z256mk:
27802 case VFMADD231BF16Z256mkz:
27803 case VFMADD231BF16Z256r:
27804 case VFMADD231BF16Z256rk:
27805 case VFMADD231BF16Z256rkz:
27806 case VFMADD231BF16Zm:
27807 case VFMADD231BF16Zmb:
27808 case VFMADD231BF16Zmbk:
27809 case VFMADD231BF16Zmbkz:
27810 case VFMADD231BF16Zmk:
27811 case VFMADD231BF16Zmkz:
27812 case VFMADD231BF16Zr:
27813 case VFMADD231BF16Zrk:
27814 case VFMADD231BF16Zrkz:
27815 return true;
27816 }
27817 return false;
27818}
27819
27820bool isCMPSS(unsigned Opcode) {
27821 switch (Opcode) {
27822 case CMPSSrmi_Int:
27823 case CMPSSrri_Int:
27824 return true;
27825 }
27826 return false;
27827}
27828
27829bool isMASKMOVDQU(unsigned Opcode) {
27830 switch (Opcode) {
27831 case MASKMOVDQU:
27832 case MASKMOVDQU64:
27833 return true;
27834 }
27835 return false;
27836}
27837
27838bool isVPDPWUSDS(unsigned Opcode) {
27839 switch (Opcode) {
27840 case VPDPWUSDSYrm:
27841 case VPDPWUSDSYrr:
27842 case VPDPWUSDSZ128m:
27843 case VPDPWUSDSZ128mb:
27844 case VPDPWUSDSZ128mbk:
27845 case VPDPWUSDSZ128mbkz:
27846 case VPDPWUSDSZ128mk:
27847 case VPDPWUSDSZ128mkz:
27848 case VPDPWUSDSZ128r:
27849 case VPDPWUSDSZ128rk:
27850 case VPDPWUSDSZ128rkz:
27851 case VPDPWUSDSZ256m:
27852 case VPDPWUSDSZ256mb:
27853 case VPDPWUSDSZ256mbk:
27854 case VPDPWUSDSZ256mbkz:
27855 case VPDPWUSDSZ256mk:
27856 case VPDPWUSDSZ256mkz:
27857 case VPDPWUSDSZ256r:
27858 case VPDPWUSDSZ256rk:
27859 case VPDPWUSDSZ256rkz:
27860 case VPDPWUSDSZm:
27861 case VPDPWUSDSZmb:
27862 case VPDPWUSDSZmbk:
27863 case VPDPWUSDSZmbkz:
27864 case VPDPWUSDSZmk:
27865 case VPDPWUSDSZmkz:
27866 case VPDPWUSDSZr:
27867 case VPDPWUSDSZrk:
27868 case VPDPWUSDSZrkz:
27869 case VPDPWUSDSrm:
27870 case VPDPWUSDSrr:
27871 return true;
27872 }
27873 return false;
27874}
27875
27876bool isSARX(unsigned Opcode) {
27877 switch (Opcode) {
27878 case SARX32rm:
27879 case SARX32rm_EVEX:
27880 case SARX32rr:
27881 case SARX32rr_EVEX:
27882 case SARX64rm:
27883 case SARX64rm_EVEX:
27884 case SARX64rr:
27885 case SARX64rr_EVEX:
27886 return true;
27887 }
27888 return false;
27889}
27890
27891bool isSGDT(unsigned Opcode) {
27892 return Opcode == SGDT64m;
27893}
27894
27895bool isVFMULCPH(unsigned Opcode) {
27896 switch (Opcode) {
27897 case VFMULCPHZ128rm:
27898 case VFMULCPHZ128rmb:
27899 case VFMULCPHZ128rmbk:
27900 case VFMULCPHZ128rmbkz:
27901 case VFMULCPHZ128rmk:
27902 case VFMULCPHZ128rmkz:
27903 case VFMULCPHZ128rr:
27904 case VFMULCPHZ128rrk:
27905 case VFMULCPHZ128rrkz:
27906 case VFMULCPHZ256rm:
27907 case VFMULCPHZ256rmb:
27908 case VFMULCPHZ256rmbk:
27909 case VFMULCPHZ256rmbkz:
27910 case VFMULCPHZ256rmk:
27911 case VFMULCPHZ256rmkz:
27912 case VFMULCPHZ256rr:
27913 case VFMULCPHZ256rrk:
27914 case VFMULCPHZ256rrkz:
27915 case VFMULCPHZrm:
27916 case VFMULCPHZrmb:
27917 case VFMULCPHZrmbk:
27918 case VFMULCPHZrmbkz:
27919 case VFMULCPHZrmk:
27920 case VFMULCPHZrmkz:
27921 case VFMULCPHZrr:
27922 case VFMULCPHZrrb:
27923 case VFMULCPHZrrbk:
27924 case VFMULCPHZrrbkz:
27925 case VFMULCPHZrrk:
27926 case VFMULCPHZrrkz:
27927 return true;
27928 }
27929 return false;
27930}
27931
27932bool isURDMSR(unsigned Opcode) {
27933 switch (Opcode) {
27934 case URDMSRri:
27935 case URDMSRri_EVEX:
27936 case URDMSRrr:
27937 case URDMSRrr_EVEX:
27938 return true;
27939 }
27940 return false;
27941}
27942
27943bool isKUNPCKWD(unsigned Opcode) {
27944 return Opcode == KUNPCKWDkk;
27945}
27946
27947bool isVSCALEFBF16(unsigned Opcode) {
27948 switch (Opcode) {
27949 case VSCALEFBF16Z128rm:
27950 case VSCALEFBF16Z128rmb:
27951 case VSCALEFBF16Z128rmbk:
27952 case VSCALEFBF16Z128rmbkz:
27953 case VSCALEFBF16Z128rmk:
27954 case VSCALEFBF16Z128rmkz:
27955 case VSCALEFBF16Z128rr:
27956 case VSCALEFBF16Z128rrk:
27957 case VSCALEFBF16Z128rrkz:
27958 case VSCALEFBF16Z256rm:
27959 case VSCALEFBF16Z256rmb:
27960 case VSCALEFBF16Z256rmbk:
27961 case VSCALEFBF16Z256rmbkz:
27962 case VSCALEFBF16Z256rmk:
27963 case VSCALEFBF16Z256rmkz:
27964 case VSCALEFBF16Z256rr:
27965 case VSCALEFBF16Z256rrk:
27966 case VSCALEFBF16Z256rrkz:
27967 case VSCALEFBF16Zrm:
27968 case VSCALEFBF16Zrmb:
27969 case VSCALEFBF16Zrmbk:
27970 case VSCALEFBF16Zrmbkz:
27971 case VSCALEFBF16Zrmk:
27972 case VSCALEFBF16Zrmkz:
27973 case VSCALEFBF16Zrr:
27974 case VSCALEFBF16Zrrk:
27975 case VSCALEFBF16Zrrkz:
27976 return true;
27977 }
27978 return false;
27979}
27980
27981bool isCVTPS2PD(unsigned Opcode) {
27982 switch (Opcode) {
27983 case CVTPS2PDrm:
27984 case CVTPS2PDrr:
27985 return true;
27986 }
27987 return false;
27988}
27989
27990bool isFBSTP(unsigned Opcode) {
27991 return Opcode == FBSTPm;
27992}
27993
27994bool isPSUBQ(unsigned Opcode) {
27995 switch (Opcode) {
27996 case MMX_PSUBQrm:
27997 case MMX_PSUBQrr:
27998 case PSUBQrm:
27999 case PSUBQrr:
28000 return true;
28001 }
28002 return false;
28003}
28004
28005bool isFXSAVE64(unsigned Opcode) {
28006 return Opcode == FXSAVE64;
28007}
28008
28009bool isKMOVW(unsigned Opcode) {
28010 switch (Opcode) {
28011 case KMOVWkk:
28012 case KMOVWkk_EVEX:
28013 case KMOVWkm:
28014 case KMOVWkm_EVEX:
28015 case KMOVWkr:
28016 case KMOVWkr_EVEX:
28017 case KMOVWmk:
28018 case KMOVWmk_EVEX:
28019 case KMOVWrk:
28020 case KMOVWrk_EVEX:
28021 return true;
28022 }
28023 return false;
28024}
28025
28026bool isBTS(unsigned Opcode) {
28027 switch (Opcode) {
28028 case BTS16mi8:
28029 case BTS16mr:
28030 case BTS16ri8:
28031 case BTS16rr:
28032 case BTS32mi8:
28033 case BTS32mr:
28034 case BTS32ri8:
28035 case BTS32rr:
28036 case BTS64mi8:
28037 case BTS64mr:
28038 case BTS64ri8:
28039 case BTS64rr:
28040 return true;
28041 }
28042 return false;
28043}
28044
28045bool isVPHADDBQ(unsigned Opcode) {
28046 switch (Opcode) {
28047 case VPHADDBQrm:
28048 case VPHADDBQrr:
28049 return true;
28050 }
28051 return false;
28052}
28053
28054bool isFRSTOR(unsigned Opcode) {
28055 return Opcode == FRSTORm;
28056}
28057
28058bool isVFMSUB132PD(unsigned Opcode) {
28059 switch (Opcode) {
28060 case VFMSUB132PDYm:
28061 case VFMSUB132PDYr:
28062 case VFMSUB132PDZ128m:
28063 case VFMSUB132PDZ128mb:
28064 case VFMSUB132PDZ128mbk:
28065 case VFMSUB132PDZ128mbkz:
28066 case VFMSUB132PDZ128mk:
28067 case VFMSUB132PDZ128mkz:
28068 case VFMSUB132PDZ128r:
28069 case VFMSUB132PDZ128rk:
28070 case VFMSUB132PDZ128rkz:
28071 case VFMSUB132PDZ256m:
28072 case VFMSUB132PDZ256mb:
28073 case VFMSUB132PDZ256mbk:
28074 case VFMSUB132PDZ256mbkz:
28075 case VFMSUB132PDZ256mk:
28076 case VFMSUB132PDZ256mkz:
28077 case VFMSUB132PDZ256r:
28078 case VFMSUB132PDZ256rk:
28079 case VFMSUB132PDZ256rkz:
28080 case VFMSUB132PDZm:
28081 case VFMSUB132PDZmb:
28082 case VFMSUB132PDZmbk:
28083 case VFMSUB132PDZmbkz:
28084 case VFMSUB132PDZmk:
28085 case VFMSUB132PDZmkz:
28086 case VFMSUB132PDZr:
28087 case VFMSUB132PDZrb:
28088 case VFMSUB132PDZrbk:
28089 case VFMSUB132PDZrbkz:
28090 case VFMSUB132PDZrk:
28091 case VFMSUB132PDZrkz:
28092 case VFMSUB132PDm:
28093 case VFMSUB132PDr:
28094 return true;
28095 }
28096 return false;
28097}
28098
28099bool isPMULLD(unsigned Opcode) {
28100 switch (Opcode) {
28101 case PMULLDrm:
28102 case PMULLDrr:
28103 return true;
28104 }
28105 return false;
28106}
28107
28108bool isSHA1MSG2(unsigned Opcode) {
28109 switch (Opcode) {
28110 case SHA1MSG2rm:
28111 case SHA1MSG2rr:
28112 return true;
28113 }
28114 return false;
28115}
28116
28117bool isJECXZ(unsigned Opcode) {
28118 return Opcode == JECXZ;
28119}
28120
28121bool isVCVTUDQ2PS(unsigned Opcode) {
28122 switch (Opcode) {
28123 case VCVTUDQ2PSZ128rm:
28124 case VCVTUDQ2PSZ128rmb:
28125 case VCVTUDQ2PSZ128rmbk:
28126 case VCVTUDQ2PSZ128rmbkz:
28127 case VCVTUDQ2PSZ128rmk:
28128 case VCVTUDQ2PSZ128rmkz:
28129 case VCVTUDQ2PSZ128rr:
28130 case VCVTUDQ2PSZ128rrk:
28131 case VCVTUDQ2PSZ128rrkz:
28132 case VCVTUDQ2PSZ256rm:
28133 case VCVTUDQ2PSZ256rmb:
28134 case VCVTUDQ2PSZ256rmbk:
28135 case VCVTUDQ2PSZ256rmbkz:
28136 case VCVTUDQ2PSZ256rmk:
28137 case VCVTUDQ2PSZ256rmkz:
28138 case VCVTUDQ2PSZ256rr:
28139 case VCVTUDQ2PSZ256rrk:
28140 case VCVTUDQ2PSZ256rrkz:
28141 case VCVTUDQ2PSZrm:
28142 case VCVTUDQ2PSZrmb:
28143 case VCVTUDQ2PSZrmbk:
28144 case VCVTUDQ2PSZrmbkz:
28145 case VCVTUDQ2PSZrmk:
28146 case VCVTUDQ2PSZrmkz:
28147 case VCVTUDQ2PSZrr:
28148 case VCVTUDQ2PSZrrb:
28149 case VCVTUDQ2PSZrrbk:
28150 case VCVTUDQ2PSZrrbkz:
28151 case VCVTUDQ2PSZrrk:
28152 case VCVTUDQ2PSZrrkz:
28153 return true;
28154 }
28155 return false;
28156}
28157
28158bool isAESENC(unsigned Opcode) {
28159 switch (Opcode) {
28160 case AESENCrm:
28161 case AESENCrr:
28162 return true;
28163 }
28164 return false;
28165}
28166
28167bool isVMINMAXPS(unsigned Opcode) {
28168 switch (Opcode) {
28169 case VMINMAXPSZ128rmbi:
28170 case VMINMAXPSZ128rmbik:
28171 case VMINMAXPSZ128rmbikz:
28172 case VMINMAXPSZ128rmi:
28173 case VMINMAXPSZ128rmik:
28174 case VMINMAXPSZ128rmikz:
28175 case VMINMAXPSZ128rri:
28176 case VMINMAXPSZ128rrik:
28177 case VMINMAXPSZ128rrikz:
28178 case VMINMAXPSZ256rmbi:
28179 case VMINMAXPSZ256rmbik:
28180 case VMINMAXPSZ256rmbikz:
28181 case VMINMAXPSZ256rmi:
28182 case VMINMAXPSZ256rmik:
28183 case VMINMAXPSZ256rmikz:
28184 case VMINMAXPSZ256rri:
28185 case VMINMAXPSZ256rrik:
28186 case VMINMAXPSZ256rrikz:
28187 case VMINMAXPSZrmbi:
28188 case VMINMAXPSZrmbik:
28189 case VMINMAXPSZrmbikz:
28190 case VMINMAXPSZrmi:
28191 case VMINMAXPSZrmik:
28192 case VMINMAXPSZrmikz:
28193 case VMINMAXPSZrri:
28194 case VMINMAXPSZrrib:
28195 case VMINMAXPSZrribk:
28196 case VMINMAXPSZrribkz:
28197 case VMINMAXPSZrrik:
28198 case VMINMAXPSZrrikz:
28199 return true;
28200 }
28201 return false;
28202}
28203
28204bool isPSIGNW(unsigned Opcode) {
28205 switch (Opcode) {
28206 case MMX_PSIGNWrm:
28207 case MMX_PSIGNWrr:
28208 case PSIGNWrm:
28209 case PSIGNWrr:
28210 return true;
28211 }
28212 return false;
28213}
28214
28215bool isUNPCKLPD(unsigned Opcode) {
28216 switch (Opcode) {
28217 case UNPCKLPDrm:
28218 case UNPCKLPDrr:
28219 return true;
28220 }
28221 return false;
28222}
28223
28224bool isPUSHP(unsigned Opcode) {
28225 return Opcode == PUSHP64r;
28226}
28227
28228bool isBLSI(unsigned Opcode) {
28229 switch (Opcode) {
28230 case BLSI32rm:
28231 case BLSI32rm_EVEX:
28232 case BLSI32rm_NF:
28233 case BLSI32rr:
28234 case BLSI32rr_EVEX:
28235 case BLSI32rr_NF:
28236 case BLSI64rm:
28237 case BLSI64rm_EVEX:
28238 case BLSI64rm_NF:
28239 case BLSI64rr:
28240 case BLSI64rr_EVEX:
28241 case BLSI64rr_NF:
28242 return true;
28243 }
28244 return false;
28245}
28246
28247bool isVPTESTNMB(unsigned Opcode) {
28248 switch (Opcode) {
28249 case VPTESTNMBZ128rm:
28250 case VPTESTNMBZ128rmk:
28251 case VPTESTNMBZ128rr:
28252 case VPTESTNMBZ128rrk:
28253 case VPTESTNMBZ256rm:
28254 case VPTESTNMBZ256rmk:
28255 case VPTESTNMBZ256rr:
28256 case VPTESTNMBZ256rrk:
28257 case VPTESTNMBZrm:
28258 case VPTESTNMBZrmk:
28259 case VPTESTNMBZrr:
28260 case VPTESTNMBZrrk:
28261 return true;
28262 }
28263 return false;
28264}
28265
28266bool isWRUSSQ(unsigned Opcode) {
28267 switch (Opcode) {
28268 case WRUSSQ:
28269 case WRUSSQ_EVEX:
28270 return true;
28271 }
28272 return false;
28273}
28274
28275bool isVGF2P8MULB(unsigned Opcode) {
28276 switch (Opcode) {
28277 case VGF2P8MULBYrm:
28278 case VGF2P8MULBYrr:
28279 case VGF2P8MULBZ128rm:
28280 case VGF2P8MULBZ128rmk:
28281 case VGF2P8MULBZ128rmkz:
28282 case VGF2P8MULBZ128rr:
28283 case VGF2P8MULBZ128rrk:
28284 case VGF2P8MULBZ128rrkz:
28285 case VGF2P8MULBZ256rm:
28286 case VGF2P8MULBZ256rmk:
28287 case VGF2P8MULBZ256rmkz:
28288 case VGF2P8MULBZ256rr:
28289 case VGF2P8MULBZ256rrk:
28290 case VGF2P8MULBZ256rrkz:
28291 case VGF2P8MULBZrm:
28292 case VGF2P8MULBZrmk:
28293 case VGF2P8MULBZrmkz:
28294 case VGF2P8MULBZrr:
28295 case VGF2P8MULBZrrk:
28296 case VGF2P8MULBZrrkz:
28297 case VGF2P8MULBrm:
28298 case VGF2P8MULBrr:
28299 return true;
28300 }
28301 return false;
28302}
28303
28304bool isVPUNPCKLBW(unsigned Opcode) {
28305 switch (Opcode) {
28306 case VPUNPCKLBWYrm:
28307 case VPUNPCKLBWYrr:
28308 case VPUNPCKLBWZ128rm:
28309 case VPUNPCKLBWZ128rmk:
28310 case VPUNPCKLBWZ128rmkz:
28311 case VPUNPCKLBWZ128rr:
28312 case VPUNPCKLBWZ128rrk:
28313 case VPUNPCKLBWZ128rrkz:
28314 case VPUNPCKLBWZ256rm:
28315 case VPUNPCKLBWZ256rmk:
28316 case VPUNPCKLBWZ256rmkz:
28317 case VPUNPCKLBWZ256rr:
28318 case VPUNPCKLBWZ256rrk:
28319 case VPUNPCKLBWZ256rrkz:
28320 case VPUNPCKLBWZrm:
28321 case VPUNPCKLBWZrmk:
28322 case VPUNPCKLBWZrmkz:
28323 case VPUNPCKLBWZrr:
28324 case VPUNPCKLBWZrrk:
28325 case VPUNPCKLBWZrrkz:
28326 case VPUNPCKLBWrm:
28327 case VPUNPCKLBWrr:
28328 return true;
28329 }
28330 return false;
28331}
28332
28333bool isVRANGESD(unsigned Opcode) {
28334 switch (Opcode) {
28335 case VRANGESDZrmi:
28336 case VRANGESDZrmik:
28337 case VRANGESDZrmikz:
28338 case VRANGESDZrri:
28339 case VRANGESDZrrib:
28340 case VRANGESDZrribk:
28341 case VRANGESDZrribkz:
28342 case VRANGESDZrrik:
28343 case VRANGESDZrrikz:
28344 return true;
28345 }
28346 return false;
28347}
28348
28349bool isCLD(unsigned Opcode) {
28350 return Opcode == CLD;
28351}
28352
28353bool isVSCALEFPD(unsigned Opcode) {
28354 switch (Opcode) {
28355 case VSCALEFPDZ128rm:
28356 case VSCALEFPDZ128rmb:
28357 case VSCALEFPDZ128rmbk:
28358 case VSCALEFPDZ128rmbkz:
28359 case VSCALEFPDZ128rmk:
28360 case VSCALEFPDZ128rmkz:
28361 case VSCALEFPDZ128rr:
28362 case VSCALEFPDZ128rrk:
28363 case VSCALEFPDZ128rrkz:
28364 case VSCALEFPDZ256rm:
28365 case VSCALEFPDZ256rmb:
28366 case VSCALEFPDZ256rmbk:
28367 case VSCALEFPDZ256rmbkz:
28368 case VSCALEFPDZ256rmk:
28369 case VSCALEFPDZ256rmkz:
28370 case VSCALEFPDZ256rr:
28371 case VSCALEFPDZ256rrk:
28372 case VSCALEFPDZ256rrkz:
28373 case VSCALEFPDZrm:
28374 case VSCALEFPDZrmb:
28375 case VSCALEFPDZrmbk:
28376 case VSCALEFPDZrmbkz:
28377 case VSCALEFPDZrmk:
28378 case VSCALEFPDZrmkz:
28379 case VSCALEFPDZrr:
28380 case VSCALEFPDZrrb:
28381 case VSCALEFPDZrrbk:
28382 case VSCALEFPDZrrbkz:
28383 case VSCALEFPDZrrk:
28384 case VSCALEFPDZrrkz:
28385 return true;
28386 }
28387 return false;
28388}
28389
28390bool isVCOMXSS(unsigned Opcode) {
28391 switch (Opcode) {
28392 case VCOMXSSZrm_Int:
28393 case VCOMXSSZrr_Int:
28394 case VCOMXSSZrrb_Int:
28395 return true;
28396 }
28397 return false;
28398}
28399
28400bool isVPERMQ(unsigned Opcode) {
28401 switch (Opcode) {
28402 case VPERMQYmi:
28403 case VPERMQYri:
28404 case VPERMQZ256mbi:
28405 case VPERMQZ256mbik:
28406 case VPERMQZ256mbikz:
28407 case VPERMQZ256mi:
28408 case VPERMQZ256mik:
28409 case VPERMQZ256mikz:
28410 case VPERMQZ256ri:
28411 case VPERMQZ256rik:
28412 case VPERMQZ256rikz:
28413 case VPERMQZ256rm:
28414 case VPERMQZ256rmb:
28415 case VPERMQZ256rmbk:
28416 case VPERMQZ256rmbkz:
28417 case VPERMQZ256rmk:
28418 case VPERMQZ256rmkz:
28419 case VPERMQZ256rr:
28420 case VPERMQZ256rrk:
28421 case VPERMQZ256rrkz:
28422 case VPERMQZmbi:
28423 case VPERMQZmbik:
28424 case VPERMQZmbikz:
28425 case VPERMQZmi:
28426 case VPERMQZmik:
28427 case VPERMQZmikz:
28428 case VPERMQZri:
28429 case VPERMQZrik:
28430 case VPERMQZrikz:
28431 case VPERMQZrm:
28432 case VPERMQZrmb:
28433 case VPERMQZrmbk:
28434 case VPERMQZrmbkz:
28435 case VPERMQZrmk:
28436 case VPERMQZrmkz:
28437 case VPERMQZrr:
28438 case VPERMQZrrk:
28439 case VPERMQZrrkz:
28440 return true;
28441 }
28442 return false;
28443}
28444
28445bool isVPSHLDVW(unsigned Opcode) {
28446 switch (Opcode) {
28447 case VPSHLDVWZ128m:
28448 case VPSHLDVWZ128mk:
28449 case VPSHLDVWZ128mkz:
28450 case VPSHLDVWZ128r:
28451 case VPSHLDVWZ128rk:
28452 case VPSHLDVWZ128rkz:
28453 case VPSHLDVWZ256m:
28454 case VPSHLDVWZ256mk:
28455 case VPSHLDVWZ256mkz:
28456 case VPSHLDVWZ256r:
28457 case VPSHLDVWZ256rk:
28458 case VPSHLDVWZ256rkz:
28459 case VPSHLDVWZm:
28460 case VPSHLDVWZmk:
28461 case VPSHLDVWZmkz:
28462 case VPSHLDVWZr:
28463 case VPSHLDVWZrk:
28464 case VPSHLDVWZrkz:
28465 return true;
28466 }
28467 return false;
28468}
28469
28470bool isROR(unsigned Opcode) {
28471 switch (Opcode) {
28472 case ROR16m1:
28473 case ROR16m1_EVEX:
28474 case ROR16m1_ND:
28475 case ROR16m1_NF:
28476 case ROR16m1_NF_ND:
28477 case ROR16mCL:
28478 case ROR16mCL_EVEX:
28479 case ROR16mCL_ND:
28480 case ROR16mCL_NF:
28481 case ROR16mCL_NF_ND:
28482 case ROR16mi:
28483 case ROR16mi_EVEX:
28484 case ROR16mi_ND:
28485 case ROR16mi_NF:
28486 case ROR16mi_NF_ND:
28487 case ROR16r1:
28488 case ROR16r1_EVEX:
28489 case ROR16r1_ND:
28490 case ROR16r1_NF:
28491 case ROR16r1_NF_ND:
28492 case ROR16rCL:
28493 case ROR16rCL_EVEX:
28494 case ROR16rCL_ND:
28495 case ROR16rCL_NF:
28496 case ROR16rCL_NF_ND:
28497 case ROR16ri:
28498 case ROR16ri_EVEX:
28499 case ROR16ri_ND:
28500 case ROR16ri_NF:
28501 case ROR16ri_NF_ND:
28502 case ROR32m1:
28503 case ROR32m1_EVEX:
28504 case ROR32m1_ND:
28505 case ROR32m1_NF:
28506 case ROR32m1_NF_ND:
28507 case ROR32mCL:
28508 case ROR32mCL_EVEX:
28509 case ROR32mCL_ND:
28510 case ROR32mCL_NF:
28511 case ROR32mCL_NF_ND:
28512 case ROR32mi:
28513 case ROR32mi_EVEX:
28514 case ROR32mi_ND:
28515 case ROR32mi_NF:
28516 case ROR32mi_NF_ND:
28517 case ROR32r1:
28518 case ROR32r1_EVEX:
28519 case ROR32r1_ND:
28520 case ROR32r1_NF:
28521 case ROR32r1_NF_ND:
28522 case ROR32rCL:
28523 case ROR32rCL_EVEX:
28524 case ROR32rCL_ND:
28525 case ROR32rCL_NF:
28526 case ROR32rCL_NF_ND:
28527 case ROR32ri:
28528 case ROR32ri_EVEX:
28529 case ROR32ri_ND:
28530 case ROR32ri_NF:
28531 case ROR32ri_NF_ND:
28532 case ROR64m1:
28533 case ROR64m1_EVEX:
28534 case ROR64m1_ND:
28535 case ROR64m1_NF:
28536 case ROR64m1_NF_ND:
28537 case ROR64mCL:
28538 case ROR64mCL_EVEX:
28539 case ROR64mCL_ND:
28540 case ROR64mCL_NF:
28541 case ROR64mCL_NF_ND:
28542 case ROR64mi:
28543 case ROR64mi_EVEX:
28544 case ROR64mi_ND:
28545 case ROR64mi_NF:
28546 case ROR64mi_NF_ND:
28547 case ROR64r1:
28548 case ROR64r1_EVEX:
28549 case ROR64r1_ND:
28550 case ROR64r1_NF:
28551 case ROR64r1_NF_ND:
28552 case ROR64rCL:
28553 case ROR64rCL_EVEX:
28554 case ROR64rCL_ND:
28555 case ROR64rCL_NF:
28556 case ROR64rCL_NF_ND:
28557 case ROR64ri:
28558 case ROR64ri_EVEX:
28559 case ROR64ri_ND:
28560 case ROR64ri_NF:
28561 case ROR64ri_NF_ND:
28562 case ROR8m1:
28563 case ROR8m1_EVEX:
28564 case ROR8m1_ND:
28565 case ROR8m1_NF:
28566 case ROR8m1_NF_ND:
28567 case ROR8mCL:
28568 case ROR8mCL_EVEX:
28569 case ROR8mCL_ND:
28570 case ROR8mCL_NF:
28571 case ROR8mCL_NF_ND:
28572 case ROR8mi:
28573 case ROR8mi_EVEX:
28574 case ROR8mi_ND:
28575 case ROR8mi_NF:
28576 case ROR8mi_NF_ND:
28577 case ROR8r1:
28578 case ROR8r1_EVEX:
28579 case ROR8r1_ND:
28580 case ROR8r1_NF:
28581 case ROR8r1_NF_ND:
28582 case ROR8rCL:
28583 case ROR8rCL_EVEX:
28584 case ROR8rCL_ND:
28585 case ROR8rCL_NF:
28586 case ROR8rCL_NF_ND:
28587 case ROR8ri:
28588 case ROR8ri_EVEX:
28589 case ROR8ri_ND:
28590 case ROR8ri_NF:
28591 case ROR8ri_NF_ND:
28592 return true;
28593 }
28594 return false;
28595}
28596
28597bool isVFMADDSUB132PH(unsigned Opcode) {
28598 switch (Opcode) {
28599 case VFMADDSUB132PHZ128m:
28600 case VFMADDSUB132PHZ128mb:
28601 case VFMADDSUB132PHZ128mbk:
28602 case VFMADDSUB132PHZ128mbkz:
28603 case VFMADDSUB132PHZ128mk:
28604 case VFMADDSUB132PHZ128mkz:
28605 case VFMADDSUB132PHZ128r:
28606 case VFMADDSUB132PHZ128rk:
28607 case VFMADDSUB132PHZ128rkz:
28608 case VFMADDSUB132PHZ256m:
28609 case VFMADDSUB132PHZ256mb:
28610 case VFMADDSUB132PHZ256mbk:
28611 case VFMADDSUB132PHZ256mbkz:
28612 case VFMADDSUB132PHZ256mk:
28613 case VFMADDSUB132PHZ256mkz:
28614 case VFMADDSUB132PHZ256r:
28615 case VFMADDSUB132PHZ256rk:
28616 case VFMADDSUB132PHZ256rkz:
28617 case VFMADDSUB132PHZm:
28618 case VFMADDSUB132PHZmb:
28619 case VFMADDSUB132PHZmbk:
28620 case VFMADDSUB132PHZmbkz:
28621 case VFMADDSUB132PHZmk:
28622 case VFMADDSUB132PHZmkz:
28623 case VFMADDSUB132PHZr:
28624 case VFMADDSUB132PHZrb:
28625 case VFMADDSUB132PHZrbk:
28626 case VFMADDSUB132PHZrbkz:
28627 case VFMADDSUB132PHZrk:
28628 case VFMADDSUB132PHZrkz:
28629 return true;
28630 }
28631 return false;
28632}
28633
28634bool isDEC(unsigned Opcode) {
28635 switch (Opcode) {
28636 case DEC16m:
28637 case DEC16m_EVEX:
28638 case DEC16m_ND:
28639 case DEC16m_NF:
28640 case DEC16m_NF_ND:
28641 case DEC16r:
28642 case DEC16r_EVEX:
28643 case DEC16r_ND:
28644 case DEC16r_NF:
28645 case DEC16r_NF_ND:
28646 case DEC16r_alt:
28647 case DEC32m:
28648 case DEC32m_EVEX:
28649 case DEC32m_ND:
28650 case DEC32m_NF:
28651 case DEC32m_NF_ND:
28652 case DEC32r:
28653 case DEC32r_EVEX:
28654 case DEC32r_ND:
28655 case DEC32r_NF:
28656 case DEC32r_NF_ND:
28657 case DEC32r_alt:
28658 case DEC64m:
28659 case DEC64m_EVEX:
28660 case DEC64m_ND:
28661 case DEC64m_NF:
28662 case DEC64m_NF_ND:
28663 case DEC64r:
28664 case DEC64r_EVEX:
28665 case DEC64r_ND:
28666 case DEC64r_NF:
28667 case DEC64r_NF_ND:
28668 case DEC8m:
28669 case DEC8m_EVEX:
28670 case DEC8m_ND:
28671 case DEC8m_NF:
28672 case DEC8m_NF_ND:
28673 case DEC8r:
28674 case DEC8r_EVEX:
28675 case DEC8r_ND:
28676 case DEC8r_NF:
28677 case DEC8r_NF_ND:
28678 return true;
28679 }
28680 return false;
28681}
28682
28683bool isVGETEXPSH(unsigned Opcode) {
28684 switch (Opcode) {
28685 case VGETEXPSHZm:
28686 case VGETEXPSHZmk:
28687 case VGETEXPSHZmkz:
28688 case VGETEXPSHZr:
28689 case VGETEXPSHZrb:
28690 case VGETEXPSHZrbk:
28691 case VGETEXPSHZrbkz:
28692 case VGETEXPSHZrk:
28693 case VGETEXPSHZrkz:
28694 return true;
28695 }
28696 return false;
28697}
28698
28699bool isAESDEC(unsigned Opcode) {
28700 switch (Opcode) {
28701 case AESDECrm:
28702 case AESDECrr:
28703 return true;
28704 }
28705 return false;
28706}
28707
28708bool isKORD(unsigned Opcode) {
28709 return Opcode == KORDkk;
28710}
28711
28712bool isVPMULHW(unsigned Opcode) {
28713 switch (Opcode) {
28714 case VPMULHWYrm:
28715 case VPMULHWYrr:
28716 case VPMULHWZ128rm:
28717 case VPMULHWZ128rmk:
28718 case VPMULHWZ128rmkz:
28719 case VPMULHWZ128rr:
28720 case VPMULHWZ128rrk:
28721 case VPMULHWZ128rrkz:
28722 case VPMULHWZ256rm:
28723 case VPMULHWZ256rmk:
28724 case VPMULHWZ256rmkz:
28725 case VPMULHWZ256rr:
28726 case VPMULHWZ256rrk:
28727 case VPMULHWZ256rrkz:
28728 case VPMULHWZrm:
28729 case VPMULHWZrmk:
28730 case VPMULHWZrmkz:
28731 case VPMULHWZrr:
28732 case VPMULHWZrrk:
28733 case VPMULHWZrrkz:
28734 case VPMULHWrm:
28735 case VPMULHWrr:
28736 return true;
28737 }
28738 return false;
28739}
28740
28741bool isTILELOADDT1(unsigned Opcode) {
28742 switch (Opcode) {
28743 case TILELOADDT1:
28744 case TILELOADDT1_EVEX:
28745 return true;
28746 }
28747 return false;
28748}
28749
28750bool isVMASKMOVPS(unsigned Opcode) {
28751 switch (Opcode) {
28752 case VMASKMOVPSYmr:
28753 case VMASKMOVPSYrm:
28754 case VMASKMOVPSmr:
28755 case VMASKMOVPSrm:
28756 return true;
28757 }
28758 return false;
28759}
28760
28761bool isPMOVZXDQ(unsigned Opcode) {
28762 switch (Opcode) {
28763 case PMOVZXDQrm:
28764 case PMOVZXDQrr:
28765 return true;
28766 }
28767 return false;
28768}
28769
28770bool isVCVTPS2PH(unsigned Opcode) {
28771 switch (Opcode) {
28772 case VCVTPS2PHYmr:
28773 case VCVTPS2PHYrr:
28774 case VCVTPS2PHZ128mr:
28775 case VCVTPS2PHZ128mrk:
28776 case VCVTPS2PHZ128rr:
28777 case VCVTPS2PHZ128rrk:
28778 case VCVTPS2PHZ128rrkz:
28779 case VCVTPS2PHZ256mr:
28780 case VCVTPS2PHZ256mrk:
28781 case VCVTPS2PHZ256rr:
28782 case VCVTPS2PHZ256rrk:
28783 case VCVTPS2PHZ256rrkz:
28784 case VCVTPS2PHZmr:
28785 case VCVTPS2PHZmrk:
28786 case VCVTPS2PHZrr:
28787 case VCVTPS2PHZrrb:
28788 case VCVTPS2PHZrrbk:
28789 case VCVTPS2PHZrrbkz:
28790 case VCVTPS2PHZrrk:
28791 case VCVTPS2PHZrrkz:
28792 case VCVTPS2PHmr:
28793 case VCVTPS2PHrr:
28794 return true;
28795 }
28796 return false;
28797}
28798
28799bool isCVTDQ2PD(unsigned Opcode) {
28800 switch (Opcode) {
28801 case CVTDQ2PDrm:
28802 case CVTDQ2PDrr:
28803 return true;
28804 }
28805 return false;
28806}
28807
28808bool isVCVTSD2SS(unsigned Opcode) {
28809 switch (Opcode) {
28810 case VCVTSD2SSZrm_Int:
28811 case VCVTSD2SSZrmk_Int:
28812 case VCVTSD2SSZrmkz_Int:
28813 case VCVTSD2SSZrr_Int:
28814 case VCVTSD2SSZrrb_Int:
28815 case VCVTSD2SSZrrbk_Int:
28816 case VCVTSD2SSZrrbkz_Int:
28817 case VCVTSD2SSZrrk_Int:
28818 case VCVTSD2SSZrrkz_Int:
28819 case VCVTSD2SSrm_Int:
28820 case VCVTSD2SSrr_Int:
28821 return true;
28822 }
28823 return false;
28824}
28825
28826bool isVFMSUB213PH(unsigned Opcode) {
28827 switch (Opcode) {
28828 case VFMSUB213PHZ128m:
28829 case VFMSUB213PHZ128mb:
28830 case VFMSUB213PHZ128mbk:
28831 case VFMSUB213PHZ128mbkz:
28832 case VFMSUB213PHZ128mk:
28833 case VFMSUB213PHZ128mkz:
28834 case VFMSUB213PHZ128r:
28835 case VFMSUB213PHZ128rk:
28836 case VFMSUB213PHZ128rkz:
28837 case VFMSUB213PHZ256m:
28838 case VFMSUB213PHZ256mb:
28839 case VFMSUB213PHZ256mbk:
28840 case VFMSUB213PHZ256mbkz:
28841 case VFMSUB213PHZ256mk:
28842 case VFMSUB213PHZ256mkz:
28843 case VFMSUB213PHZ256r:
28844 case VFMSUB213PHZ256rk:
28845 case VFMSUB213PHZ256rkz:
28846 case VFMSUB213PHZm:
28847 case VFMSUB213PHZmb:
28848 case VFMSUB213PHZmbk:
28849 case VFMSUB213PHZmbkz:
28850 case VFMSUB213PHZmk:
28851 case VFMSUB213PHZmkz:
28852 case VFMSUB213PHZr:
28853 case VFMSUB213PHZrb:
28854 case VFMSUB213PHZrbk:
28855 case VFMSUB213PHZrbkz:
28856 case VFMSUB213PHZrk:
28857 case VFMSUB213PHZrkz:
28858 return true;
28859 }
28860 return false;
28861}
28862
28863bool isVPROTB(unsigned Opcode) {
28864 switch (Opcode) {
28865 case VPROTBmi:
28866 case VPROTBmr:
28867 case VPROTBri:
28868 case VPROTBrm:
28869 case VPROTBrr:
28870 case VPROTBrr_REV:
28871 return true;
28872 }
28873 return false;
28874}
28875
28876bool isPINSRD(unsigned Opcode) {
28877 switch (Opcode) {
28878 case PINSRDrmi:
28879 case PINSRDrri:
28880 return true;
28881 }
28882 return false;
28883}
28884
28885bool isVMXON(unsigned Opcode) {
28886 return Opcode == VMXON;
28887}
28888
28889bool isVFCMULCSH(unsigned Opcode) {
28890 switch (Opcode) {
28891 case VFCMULCSHZrm:
28892 case VFCMULCSHZrmk:
28893 case VFCMULCSHZrmkz:
28894 case VFCMULCSHZrr:
28895 case VFCMULCSHZrrb:
28896 case VFCMULCSHZrrbk:
28897 case VFCMULCSHZrrbkz:
28898 case VFCMULCSHZrrk:
28899 case VFCMULCSHZrrkz:
28900 return true;
28901 }
28902 return false;
28903}
28904
28905bool isVFMULCSH(unsigned Opcode) {
28906 switch (Opcode) {
28907 case VFMULCSHZrm:
28908 case VFMULCSHZrmk:
28909 case VFMULCSHZrmkz:
28910 case VFMULCSHZrr:
28911 case VFMULCSHZrrb:
28912 case VFMULCSHZrrbk:
28913 case VFMULCSHZrrbkz:
28914 case VFMULCSHZrrk:
28915 case VFMULCSHZrrkz:
28916 return true;
28917 }
28918 return false;
28919}
28920
28921bool isVRANGEPD(unsigned Opcode) {
28922 switch (Opcode) {
28923 case VRANGEPDZ128rmbi:
28924 case VRANGEPDZ128rmbik:
28925 case VRANGEPDZ128rmbikz:
28926 case VRANGEPDZ128rmi:
28927 case VRANGEPDZ128rmik:
28928 case VRANGEPDZ128rmikz:
28929 case VRANGEPDZ128rri:
28930 case VRANGEPDZ128rrik:
28931 case VRANGEPDZ128rrikz:
28932 case VRANGEPDZ256rmbi:
28933 case VRANGEPDZ256rmbik:
28934 case VRANGEPDZ256rmbikz:
28935 case VRANGEPDZ256rmi:
28936 case VRANGEPDZ256rmik:
28937 case VRANGEPDZ256rmikz:
28938 case VRANGEPDZ256rri:
28939 case VRANGEPDZ256rrik:
28940 case VRANGEPDZ256rrikz:
28941 case VRANGEPDZrmbi:
28942 case VRANGEPDZrmbik:
28943 case VRANGEPDZrmbikz:
28944 case VRANGEPDZrmi:
28945 case VRANGEPDZrmik:
28946 case VRANGEPDZrmikz:
28947 case VRANGEPDZrri:
28948 case VRANGEPDZrrib:
28949 case VRANGEPDZrribk:
28950 case VRANGEPDZrribkz:
28951 case VRANGEPDZrrik:
28952 case VRANGEPDZrrikz:
28953 return true;
28954 }
28955 return false;
28956}
28957
28958bool isCMC(unsigned Opcode) {
28959 return Opcode == CMC;
28960}
28961
28962bool isVFNMADD231BF16(unsigned Opcode) {
28963 switch (Opcode) {
28964 case VFNMADD231BF16Z128m:
28965 case VFNMADD231BF16Z128mb:
28966 case VFNMADD231BF16Z128mbk:
28967 case VFNMADD231BF16Z128mbkz:
28968 case VFNMADD231BF16Z128mk:
28969 case VFNMADD231BF16Z128mkz:
28970 case VFNMADD231BF16Z128r:
28971 case VFNMADD231BF16Z128rk:
28972 case VFNMADD231BF16Z128rkz:
28973 case VFNMADD231BF16Z256m:
28974 case VFNMADD231BF16Z256mb:
28975 case VFNMADD231BF16Z256mbk:
28976 case VFNMADD231BF16Z256mbkz:
28977 case VFNMADD231BF16Z256mk:
28978 case VFNMADD231BF16Z256mkz:
28979 case VFNMADD231BF16Z256r:
28980 case VFNMADD231BF16Z256rk:
28981 case VFNMADD231BF16Z256rkz:
28982 case VFNMADD231BF16Zm:
28983 case VFNMADD231BF16Zmb:
28984 case VFNMADD231BF16Zmbk:
28985 case VFNMADD231BF16Zmbkz:
28986 case VFNMADD231BF16Zmk:
28987 case VFNMADD231BF16Zmkz:
28988 case VFNMADD231BF16Zr:
28989 case VFNMADD231BF16Zrk:
28990 case VFNMADD231BF16Zrkz:
28991 return true;
28992 }
28993 return false;
28994}
28995
28996bool isSHA256MSG1(unsigned Opcode) {
28997 switch (Opcode) {
28998 case SHA256MSG1rm:
28999 case SHA256MSG1rr:
29000 return true;
29001 }
29002 return false;
29003}
29004
29005bool isFLD1(unsigned Opcode) {
29006 return Opcode == LD_F1;
29007}
29008
29009bool isCMPPS(unsigned Opcode) {
29010 switch (Opcode) {
29011 case CMPPSrmi:
29012 case CMPPSrri:
29013 return true;
29014 }
29015 return false;
29016}
29017
29018bool isVPAVGW(unsigned Opcode) {
29019 switch (Opcode) {
29020 case VPAVGWYrm:
29021 case VPAVGWYrr:
29022 case VPAVGWZ128rm:
29023 case VPAVGWZ128rmk:
29024 case VPAVGWZ128rmkz:
29025 case VPAVGWZ128rr:
29026 case VPAVGWZ128rrk:
29027 case VPAVGWZ128rrkz:
29028 case VPAVGWZ256rm:
29029 case VPAVGWZ256rmk:
29030 case VPAVGWZ256rmkz:
29031 case VPAVGWZ256rr:
29032 case VPAVGWZ256rrk:
29033 case VPAVGWZ256rrkz:
29034 case VPAVGWZrm:
29035 case VPAVGWZrmk:
29036 case VPAVGWZrmkz:
29037 case VPAVGWZrr:
29038 case VPAVGWZrrk:
29039 case VPAVGWZrrkz:
29040 case VPAVGWrm:
29041 case VPAVGWrr:
29042 return true;
29043 }
29044 return false;
29045}
29046
29047bool isVFMADD213SH(unsigned Opcode) {
29048 switch (Opcode) {
29049 case VFMADD213SHZm_Int:
29050 case VFMADD213SHZmk_Int:
29051 case VFMADD213SHZmkz_Int:
29052 case VFMADD213SHZr_Int:
29053 case VFMADD213SHZrb_Int:
29054 case VFMADD213SHZrbk_Int:
29055 case VFMADD213SHZrbkz_Int:
29056 case VFMADD213SHZrk_Int:
29057 case VFMADD213SHZrkz_Int:
29058 return true;
29059 }
29060 return false;
29061}
29062
29063bool isTTDPFP16PS(unsigned Opcode) {
29064 return Opcode == TTDPFP16PS;
29065}
29066
29067bool isVPINSRQ(unsigned Opcode) {
29068 switch (Opcode) {
29069 case VPINSRQZrmi:
29070 case VPINSRQZrri:
29071 case VPINSRQrmi:
29072 case VPINSRQrri:
29073 return true;
29074 }
29075 return false;
29076}
29077
29078bool isMOVABS(unsigned Opcode) {
29079 switch (Opcode) {
29080 case MOV16ao64:
29081 case MOV16o64a:
29082 case MOV32ao64:
29083 case MOV32o64a:
29084 case MOV64ao64:
29085 case MOV64o64a:
29086 case MOV64ri:
29087 case MOV8ao64:
29088 case MOV8o64a:
29089 return true;
29090 }
29091 return false;
29092}
29093
29094bool isVPSHAQ(unsigned Opcode) {
29095 switch (Opcode) {
29096 case VPSHAQmr:
29097 case VPSHAQrm:
29098 case VPSHAQrr:
29099 case VPSHAQrr_REV:
29100 return true;
29101 }
29102 return false;
29103}
29104
29105bool isRDTSCP(unsigned Opcode) {
29106 return Opcode == RDTSCP;
29107}
29108
29109bool isVFNMADD231SS(unsigned Opcode) {
29110 switch (Opcode) {
29111 case VFNMADD231SSZm_Int:
29112 case VFNMADD231SSZmk_Int:
29113 case VFNMADD231SSZmkz_Int:
29114 case VFNMADD231SSZr_Int:
29115 case VFNMADD231SSZrb_Int:
29116 case VFNMADD231SSZrbk_Int:
29117 case VFNMADD231SSZrbkz_Int:
29118 case VFNMADD231SSZrk_Int:
29119 case VFNMADD231SSZrkz_Int:
29120 case VFNMADD231SSm_Int:
29121 case VFNMADD231SSr_Int:
29122 return true;
29123 }
29124 return false;
29125}
29126
29127bool isTEST(unsigned Opcode) {
29128 switch (Opcode) {
29129 case TEST16i16:
29130 case TEST16mi:
29131 case TEST16mr:
29132 case TEST16ri:
29133 case TEST16rr:
29134 case TEST32i32:
29135 case TEST32mi:
29136 case TEST32mr:
29137 case TEST32ri:
29138 case TEST32rr:
29139 case TEST64i32:
29140 case TEST64mi32:
29141 case TEST64mr:
29142 case TEST64ri32:
29143 case TEST64rr:
29144 case TEST8i8:
29145 case TEST8mi:
29146 case TEST8mr:
29147 case TEST8ri:
29148 case TEST8rr:
29149 return true;
29150 }
29151 return false;
29152}
29153
29154bool isVPERMD(unsigned Opcode) {
29155 switch (Opcode) {
29156 case VPERMDYrm:
29157 case VPERMDYrr:
29158 case VPERMDZ256rm:
29159 case VPERMDZ256rmb:
29160 case VPERMDZ256rmbk:
29161 case VPERMDZ256rmbkz:
29162 case VPERMDZ256rmk:
29163 case VPERMDZ256rmkz:
29164 case VPERMDZ256rr:
29165 case VPERMDZ256rrk:
29166 case VPERMDZ256rrkz:
29167 case VPERMDZrm:
29168 case VPERMDZrmb:
29169 case VPERMDZrmbk:
29170 case VPERMDZrmbkz:
29171 case VPERMDZrmk:
29172 case VPERMDZrmkz:
29173 case VPERMDZrr:
29174 case VPERMDZrrk:
29175 case VPERMDZrrkz:
29176 return true;
29177 }
29178 return false;
29179}
29180
29181bool isVBCSTNESH2PS(unsigned Opcode) {
29182 switch (Opcode) {
29183 case VBCSTNESH2PSYrm:
29184 case VBCSTNESH2PSrm:
29185 return true;
29186 }
29187 return false;
29188}
29189
29190bool isVGATHERPF0QPD(unsigned Opcode) {
29191 return Opcode == VGATHERPF0QPDm;
29192}
29193
29194bool isVPERM2I128(unsigned Opcode) {
29195 switch (Opcode) {
29196 case VPERM2I128rmi:
29197 case VPERM2I128rri:
29198 return true;
29199 }
29200 return false;
29201}
29202
29203bool isVMPSADBW(unsigned Opcode) {
29204 switch (Opcode) {
29205 case VMPSADBWYrmi:
29206 case VMPSADBWYrri:
29207 case VMPSADBWZ128rmi:
29208 case VMPSADBWZ128rmik:
29209 case VMPSADBWZ128rmikz:
29210 case VMPSADBWZ128rri:
29211 case VMPSADBWZ128rrik:
29212 case VMPSADBWZ128rrikz:
29213 case VMPSADBWZ256rmi:
29214 case VMPSADBWZ256rmik:
29215 case VMPSADBWZ256rmikz:
29216 case VMPSADBWZ256rri:
29217 case VMPSADBWZ256rrik:
29218 case VMPSADBWZ256rrikz:
29219 case VMPSADBWZrmi:
29220 case VMPSADBWZrmik:
29221 case VMPSADBWZrmikz:
29222 case VMPSADBWZrri:
29223 case VMPSADBWZrrik:
29224 case VMPSADBWZrrikz:
29225 case VMPSADBWrmi:
29226 case VMPSADBWrri:
29227 return true;
29228 }
29229 return false;
29230}
29231
29232bool isVFNMSUB231PD(unsigned Opcode) {
29233 switch (Opcode) {
29234 case VFNMSUB231PDYm:
29235 case VFNMSUB231PDYr:
29236 case VFNMSUB231PDZ128m:
29237 case VFNMSUB231PDZ128mb:
29238 case VFNMSUB231PDZ128mbk:
29239 case VFNMSUB231PDZ128mbkz:
29240 case VFNMSUB231PDZ128mk:
29241 case VFNMSUB231PDZ128mkz:
29242 case VFNMSUB231PDZ128r:
29243 case VFNMSUB231PDZ128rk:
29244 case VFNMSUB231PDZ128rkz:
29245 case VFNMSUB231PDZ256m:
29246 case VFNMSUB231PDZ256mb:
29247 case VFNMSUB231PDZ256mbk:
29248 case VFNMSUB231PDZ256mbkz:
29249 case VFNMSUB231PDZ256mk:
29250 case VFNMSUB231PDZ256mkz:
29251 case VFNMSUB231PDZ256r:
29252 case VFNMSUB231PDZ256rk:
29253 case VFNMSUB231PDZ256rkz:
29254 case VFNMSUB231PDZm:
29255 case VFNMSUB231PDZmb:
29256 case VFNMSUB231PDZmbk:
29257 case VFNMSUB231PDZmbkz:
29258 case VFNMSUB231PDZmk:
29259 case VFNMSUB231PDZmkz:
29260 case VFNMSUB231PDZr:
29261 case VFNMSUB231PDZrb:
29262 case VFNMSUB231PDZrbk:
29263 case VFNMSUB231PDZrbkz:
29264 case VFNMSUB231PDZrk:
29265 case VFNMSUB231PDZrkz:
29266 case VFNMSUB231PDm:
29267 case VFNMSUB231PDr:
29268 return true;
29269 }
29270 return false;
29271}
29272
29273bool isPADDSB(unsigned Opcode) {
29274 switch (Opcode) {
29275 case MMX_PADDSBrm:
29276 case MMX_PADDSBrr:
29277 case PADDSBrm:
29278 case PADDSBrr:
29279 return true;
29280 }
29281 return false;
29282}
29283
29284bool isMWAITX(unsigned Opcode) {
29285 return Opcode == MWAITXrrr;
29286}
29287
29288bool isMONITORX(unsigned Opcode) {
29289 switch (Opcode) {
29290 case MONITORX32rrr:
29291 case MONITORX64rrr:
29292 return true;
29293 }
29294 return false;
29295}
29296
29297bool isVPEXPANDD(unsigned Opcode) {
29298 switch (Opcode) {
29299 case VPEXPANDDZ128rm:
29300 case VPEXPANDDZ128rmk:
29301 case VPEXPANDDZ128rmkz:
29302 case VPEXPANDDZ128rr:
29303 case VPEXPANDDZ128rrk:
29304 case VPEXPANDDZ128rrkz:
29305 case VPEXPANDDZ256rm:
29306 case VPEXPANDDZ256rmk:
29307 case VPEXPANDDZ256rmkz:
29308 case VPEXPANDDZ256rr:
29309 case VPEXPANDDZ256rrk:
29310 case VPEXPANDDZ256rrkz:
29311 case VPEXPANDDZrm:
29312 case VPEXPANDDZrmk:
29313 case VPEXPANDDZrmkz:
29314 case VPEXPANDDZrr:
29315 case VPEXPANDDZrrk:
29316 case VPEXPANDDZrrkz:
29317 return true;
29318 }
29319 return false;
29320}
29321
29322bool isVFRCZPD(unsigned Opcode) {
29323 switch (Opcode) {
29324 case VFRCZPDYrm:
29325 case VFRCZPDYrr:
29326 case VFRCZPDrm:
29327 case VFRCZPDrr:
29328 return true;
29329 }
29330 return false;
29331}
29332
29333bool isVRCPPH(unsigned Opcode) {
29334 switch (Opcode) {
29335 case VRCPPHZ128m:
29336 case VRCPPHZ128mb:
29337 case VRCPPHZ128mbk:
29338 case VRCPPHZ128mbkz:
29339 case VRCPPHZ128mk:
29340 case VRCPPHZ128mkz:
29341 case VRCPPHZ128r:
29342 case VRCPPHZ128rk:
29343 case VRCPPHZ128rkz:
29344 case VRCPPHZ256m:
29345 case VRCPPHZ256mb:
29346 case VRCPPHZ256mbk:
29347 case VRCPPHZ256mbkz:
29348 case VRCPPHZ256mk:
29349 case VRCPPHZ256mkz:
29350 case VRCPPHZ256r:
29351 case VRCPPHZ256rk:
29352 case VRCPPHZ256rkz:
29353 case VRCPPHZm:
29354 case VRCPPHZmb:
29355 case VRCPPHZmbk:
29356 case VRCPPHZmbkz:
29357 case VRCPPHZmk:
29358 case VRCPPHZmkz:
29359 case VRCPPHZr:
29360 case VRCPPHZrk:
29361 case VRCPPHZrkz:
29362 return true;
29363 }
29364 return false;
29365}
29366
29367bool isFEMMS(unsigned Opcode) {
29368 return Opcode == FEMMS;
29369}
29370
29371bool isVSCATTERQPD(unsigned Opcode) {
29372 switch (Opcode) {
29373 case VSCATTERQPDZ128mr:
29374 case VSCATTERQPDZ256mr:
29375 case VSCATTERQPDZmr:
29376 return true;
29377 }
29378 return false;
29379}
29380
29381bool isVMOVW(unsigned Opcode) {
29382 switch (Opcode) {
29383 case VMOVSH2Wrr:
29384 case VMOVSHtoW64rr:
29385 case VMOVW2SHrr:
29386 case VMOVW64toSHrr:
29387 case VMOVWmr:
29388 case VMOVWrm:
29389 case VMOVZPWILo2PWIZmr:
29390 case VMOVZPWILo2PWIZrm:
29391 case VMOVZPWILo2PWIZrr:
29392 case VMOVZPWILo2PWIZrr2:
29393 return true;
29394 }
29395 return false;
29396}
29397
29398bool isVPBROADCASTD(unsigned Opcode) {
29399 switch (Opcode) {
29400 case VPBROADCASTDYrm:
29401 case VPBROADCASTDYrr:
29402 case VPBROADCASTDZ128rm:
29403 case VPBROADCASTDZ128rmk:
29404 case VPBROADCASTDZ128rmkz:
29405 case VPBROADCASTDZ128rr:
29406 case VPBROADCASTDZ128rrk:
29407 case VPBROADCASTDZ128rrkz:
29408 case VPBROADCASTDZ256rm:
29409 case VPBROADCASTDZ256rmk:
29410 case VPBROADCASTDZ256rmkz:
29411 case VPBROADCASTDZ256rr:
29412 case VPBROADCASTDZ256rrk:
29413 case VPBROADCASTDZ256rrkz:
29414 case VPBROADCASTDZrm:
29415 case VPBROADCASTDZrmk:
29416 case VPBROADCASTDZrmkz:
29417 case VPBROADCASTDZrr:
29418 case VPBROADCASTDZrrk:
29419 case VPBROADCASTDZrrkz:
29420 case VPBROADCASTDrZ128rr:
29421 case VPBROADCASTDrZ128rrk:
29422 case VPBROADCASTDrZ128rrkz:
29423 case VPBROADCASTDrZ256rr:
29424 case VPBROADCASTDrZ256rrk:
29425 case VPBROADCASTDrZ256rrkz:
29426 case VPBROADCASTDrZrr:
29427 case VPBROADCASTDrZrrk:
29428 case VPBROADCASTDrZrrkz:
29429 case VPBROADCASTDrm:
29430 case VPBROADCASTDrr:
29431 return true;
29432 }
29433 return false;
29434}
29435
29436bool isSTOSB(unsigned Opcode) {
29437 return Opcode == STOSB;
29438}
29439
29440bool isFUCOMI(unsigned Opcode) {
29441 return Opcode == UCOM_FIr;
29442}
29443
29444bool isVBROADCASTI64X4(unsigned Opcode) {
29445 switch (Opcode) {
29446 case VBROADCASTI64X4Zrm:
29447 case VBROADCASTI64X4Zrmk:
29448 case VBROADCASTI64X4Zrmkz:
29449 return true;
29450 }
29451 return false;
29452}
29453
29454bool isFCMOVU(unsigned Opcode) {
29455 return Opcode == CMOVP_F;
29456}
29457
29458bool isPSHUFLW(unsigned Opcode) {
29459 switch (Opcode) {
29460 case PSHUFLWmi:
29461 case PSHUFLWri:
29462 return true;
29463 }
29464 return false;
29465}
29466
29467bool isCVTPI2PS(unsigned Opcode) {
29468 switch (Opcode) {
29469 case MMX_CVTPI2PSrm:
29470 case MMX_CVTPI2PSrr:
29471 return true;
29472 }
29473 return false;
29474}
29475
29476bool isVCVTTPD2UDQS(unsigned Opcode) {
29477 switch (Opcode) {
29478 case VCVTTPD2UDQSZ128rm:
29479 case VCVTTPD2UDQSZ128rmb:
29480 case VCVTTPD2UDQSZ128rmbk:
29481 case VCVTTPD2UDQSZ128rmbkz:
29482 case VCVTTPD2UDQSZ128rmk:
29483 case VCVTTPD2UDQSZ128rmkz:
29484 case VCVTTPD2UDQSZ128rr:
29485 case VCVTTPD2UDQSZ128rrk:
29486 case VCVTTPD2UDQSZ128rrkz:
29487 case VCVTTPD2UDQSZ256rm:
29488 case VCVTTPD2UDQSZ256rmb:
29489 case VCVTTPD2UDQSZ256rmbk:
29490 case VCVTTPD2UDQSZ256rmbkz:
29491 case VCVTTPD2UDQSZ256rmk:
29492 case VCVTTPD2UDQSZ256rmkz:
29493 case VCVTTPD2UDQSZ256rr:
29494 case VCVTTPD2UDQSZ256rrb:
29495 case VCVTTPD2UDQSZ256rrbk:
29496 case VCVTTPD2UDQSZ256rrbkz:
29497 case VCVTTPD2UDQSZ256rrk:
29498 case VCVTTPD2UDQSZ256rrkz:
29499 case VCVTTPD2UDQSZrm:
29500 case VCVTTPD2UDQSZrmb:
29501 case VCVTTPD2UDQSZrmbk:
29502 case VCVTTPD2UDQSZrmbkz:
29503 case VCVTTPD2UDQSZrmk:
29504 case VCVTTPD2UDQSZrmkz:
29505 case VCVTTPD2UDQSZrr:
29506 case VCVTTPD2UDQSZrrb:
29507 case VCVTTPD2UDQSZrrbk:
29508 case VCVTTPD2UDQSZrrbkz:
29509 case VCVTTPD2UDQSZrrk:
29510 case VCVTTPD2UDQSZrrkz:
29511 return true;
29512 }
29513 return false;
29514}
29515
29516bool isSYSCALL(unsigned Opcode) {
29517 return Opcode == SYSCALL;
29518}
29519
29520bool isVFMADD231SH(unsigned Opcode) {
29521 switch (Opcode) {
29522 case VFMADD231SHZm_Int:
29523 case VFMADD231SHZmk_Int:
29524 case VFMADD231SHZmkz_Int:
29525 case VFMADD231SHZr_Int:
29526 case VFMADD231SHZrb_Int:
29527 case VFMADD231SHZrbk_Int:
29528 case VFMADD231SHZrbkz_Int:
29529 case VFMADD231SHZrk_Int:
29530 case VFMADD231SHZrkz_Int:
29531 return true;
29532 }
29533 return false;
29534}
29535
29536bool isPMOVZXBW(unsigned Opcode) {
29537 switch (Opcode) {
29538 case PMOVZXBWrm:
29539 case PMOVZXBWrr:
29540 return true;
29541 }
29542 return false;
29543}
29544
29545bool isVPOPCNTB(unsigned Opcode) {
29546 switch (Opcode) {
29547 case VPOPCNTBZ128rm:
29548 case VPOPCNTBZ128rmk:
29549 case VPOPCNTBZ128rmkz:
29550 case VPOPCNTBZ128rr:
29551 case VPOPCNTBZ128rrk:
29552 case VPOPCNTBZ128rrkz:
29553 case VPOPCNTBZ256rm:
29554 case VPOPCNTBZ256rmk:
29555 case VPOPCNTBZ256rmkz:
29556 case VPOPCNTBZ256rr:
29557 case VPOPCNTBZ256rrk:
29558 case VPOPCNTBZ256rrkz:
29559 case VPOPCNTBZrm:
29560 case VPOPCNTBZrmk:
29561 case VPOPCNTBZrmkz:
29562 case VPOPCNTBZrr:
29563 case VPOPCNTBZrrk:
29564 case VPOPCNTBZrrkz:
29565 return true;
29566 }
29567 return false;
29568}
29569
29570bool isVCVTDQ2PS(unsigned Opcode) {
29571 switch (Opcode) {
29572 case VCVTDQ2PSYrm:
29573 case VCVTDQ2PSYrr:
29574 case VCVTDQ2PSZ128rm:
29575 case VCVTDQ2PSZ128rmb:
29576 case VCVTDQ2PSZ128rmbk:
29577 case VCVTDQ2PSZ128rmbkz:
29578 case VCVTDQ2PSZ128rmk:
29579 case VCVTDQ2PSZ128rmkz:
29580 case VCVTDQ2PSZ128rr:
29581 case VCVTDQ2PSZ128rrk:
29582 case VCVTDQ2PSZ128rrkz:
29583 case VCVTDQ2PSZ256rm:
29584 case VCVTDQ2PSZ256rmb:
29585 case VCVTDQ2PSZ256rmbk:
29586 case VCVTDQ2PSZ256rmbkz:
29587 case VCVTDQ2PSZ256rmk:
29588 case VCVTDQ2PSZ256rmkz:
29589 case VCVTDQ2PSZ256rr:
29590 case VCVTDQ2PSZ256rrk:
29591 case VCVTDQ2PSZ256rrkz:
29592 case VCVTDQ2PSZrm:
29593 case VCVTDQ2PSZrmb:
29594 case VCVTDQ2PSZrmbk:
29595 case VCVTDQ2PSZrmbkz:
29596 case VCVTDQ2PSZrmk:
29597 case VCVTDQ2PSZrmkz:
29598 case VCVTDQ2PSZrr:
29599 case VCVTDQ2PSZrrb:
29600 case VCVTDQ2PSZrrbk:
29601 case VCVTDQ2PSZrrbkz:
29602 case VCVTDQ2PSZrrk:
29603 case VCVTDQ2PSZrrkz:
29604 case VCVTDQ2PSrm:
29605 case VCVTDQ2PSrr:
29606 return true;
29607 }
29608 return false;
29609}
29610
29611bool isPSUBD(unsigned Opcode) {
29612 switch (Opcode) {
29613 case MMX_PSUBDrm:
29614 case MMX_PSUBDrr:
29615 case PSUBDrm:
29616 case PSUBDrr:
29617 return true;
29618 }
29619 return false;
29620}
29621
29622bool isVPCMPEQW(unsigned Opcode) {
29623 switch (Opcode) {
29624 case VPCMPEQWYrm:
29625 case VPCMPEQWYrr:
29626 case VPCMPEQWZ128rm:
29627 case VPCMPEQWZ128rmk:
29628 case VPCMPEQWZ128rr:
29629 case VPCMPEQWZ128rrk:
29630 case VPCMPEQWZ256rm:
29631 case VPCMPEQWZ256rmk:
29632 case VPCMPEQWZ256rr:
29633 case VPCMPEQWZ256rrk:
29634 case VPCMPEQWZrm:
29635 case VPCMPEQWZrmk:
29636 case VPCMPEQWZrr:
29637 case VPCMPEQWZrrk:
29638 case VPCMPEQWrm:
29639 case VPCMPEQWrr:
29640 return true;
29641 }
29642 return false;
29643}
29644
29645bool isMOVSW(unsigned Opcode) {
29646 return Opcode == MOVSW;
29647}
29648
29649bool isVSM3RNDS2(unsigned Opcode) {
29650 switch (Opcode) {
29651 case VSM3RNDS2rmi:
29652 case VSM3RNDS2rri:
29653 return true;
29654 }
29655 return false;
29656}
29657
29658bool isVPMOVUSQD(unsigned Opcode) {
29659 switch (Opcode) {
29660 case VPMOVUSQDZ128mr:
29661 case VPMOVUSQDZ128mrk:
29662 case VPMOVUSQDZ128rr:
29663 case VPMOVUSQDZ128rrk:
29664 case VPMOVUSQDZ128rrkz:
29665 case VPMOVUSQDZ256mr:
29666 case VPMOVUSQDZ256mrk:
29667 case VPMOVUSQDZ256rr:
29668 case VPMOVUSQDZ256rrk:
29669 case VPMOVUSQDZ256rrkz:
29670 case VPMOVUSQDZmr:
29671 case VPMOVUSQDZmrk:
29672 case VPMOVUSQDZrr:
29673 case VPMOVUSQDZrrk:
29674 case VPMOVUSQDZrrkz:
29675 return true;
29676 }
29677 return false;
29678}
29679
29680bool isCVTTPD2DQ(unsigned Opcode) {
29681 switch (Opcode) {
29682 case CVTTPD2DQrm:
29683 case CVTTPD2DQrr:
29684 return true;
29685 }
29686 return false;
29687}
29688
29689bool isVPEXPANDW(unsigned Opcode) {
29690 switch (Opcode) {
29691 case VPEXPANDWZ128rm:
29692 case VPEXPANDWZ128rmk:
29693 case VPEXPANDWZ128rmkz:
29694 case VPEXPANDWZ128rr:
29695 case VPEXPANDWZ128rrk:
29696 case VPEXPANDWZ128rrkz:
29697 case VPEXPANDWZ256rm:
29698 case VPEXPANDWZ256rmk:
29699 case VPEXPANDWZ256rmkz:
29700 case VPEXPANDWZ256rr:
29701 case VPEXPANDWZ256rrk:
29702 case VPEXPANDWZ256rrkz:
29703 case VPEXPANDWZrm:
29704 case VPEXPANDWZrmk:
29705 case VPEXPANDWZrmkz:
29706 case VPEXPANDWZrr:
29707 case VPEXPANDWZrrk:
29708 case VPEXPANDWZrrkz:
29709 return true;
29710 }
29711 return false;
29712}
29713
29714bool isVUCOMISH(unsigned Opcode) {
29715 switch (Opcode) {
29716 case VUCOMISHZrm:
29717 case VUCOMISHZrr:
29718 case VUCOMISHZrrb:
29719 return true;
29720 }
29721 return false;
29722}
29723
29724bool isVZEROALL(unsigned Opcode) {
29725 return Opcode == VZEROALL;
29726}
29727
29728bool isVPAND(unsigned Opcode) {
29729 switch (Opcode) {
29730 case VPANDYrm:
29731 case VPANDYrr:
29732 case VPANDrm:
29733 case VPANDrr:
29734 return true;
29735 }
29736 return false;
29737}
29738
29739bool isPMULDQ(unsigned Opcode) {
29740 switch (Opcode) {
29741 case PMULDQrm:
29742 case PMULDQrr:
29743 return true;
29744 }
29745 return false;
29746}
29747
29748bool isVPSHUFHW(unsigned Opcode) {
29749 switch (Opcode) {
29750 case VPSHUFHWYmi:
29751 case VPSHUFHWYri:
29752 case VPSHUFHWZ128mi:
29753 case VPSHUFHWZ128mik:
29754 case VPSHUFHWZ128mikz:
29755 case VPSHUFHWZ128ri:
29756 case VPSHUFHWZ128rik:
29757 case VPSHUFHWZ128rikz:
29758 case VPSHUFHWZ256mi:
29759 case VPSHUFHWZ256mik:
29760 case VPSHUFHWZ256mikz:
29761 case VPSHUFHWZ256ri:
29762 case VPSHUFHWZ256rik:
29763 case VPSHUFHWZ256rikz:
29764 case VPSHUFHWZmi:
29765 case VPSHUFHWZmik:
29766 case VPSHUFHWZmikz:
29767 case VPSHUFHWZri:
29768 case VPSHUFHWZrik:
29769 case VPSHUFHWZrikz:
29770 case VPSHUFHWmi:
29771 case VPSHUFHWri:
29772 return true;
29773 }
29774 return false;
29775}
29776
29777bool isVPALIGNR(unsigned Opcode) {
29778 switch (Opcode) {
29779 case VPALIGNRYrmi:
29780 case VPALIGNRYrri:
29781 case VPALIGNRZ128rmi:
29782 case VPALIGNRZ128rmik:
29783 case VPALIGNRZ128rmikz:
29784 case VPALIGNRZ128rri:
29785 case VPALIGNRZ128rrik:
29786 case VPALIGNRZ128rrikz:
29787 case VPALIGNRZ256rmi:
29788 case VPALIGNRZ256rmik:
29789 case VPALIGNRZ256rmikz:
29790 case VPALIGNRZ256rri:
29791 case VPALIGNRZ256rrik:
29792 case VPALIGNRZ256rrikz:
29793 case VPALIGNRZrmi:
29794 case VPALIGNRZrmik:
29795 case VPALIGNRZrmikz:
29796 case VPALIGNRZrri:
29797 case VPALIGNRZrrik:
29798 case VPALIGNRZrrikz:
29799 case VPALIGNRrmi:
29800 case VPALIGNRrri:
29801 return true;
29802 }
29803 return false;
29804}
29805
29806bool isSQRTSD(unsigned Opcode) {
29807 switch (Opcode) {
29808 case SQRTSDm_Int:
29809 case SQRTSDr_Int:
29810 return true;
29811 }
29812 return false;
29813}
29814
29815bool isVCVTTPH2UDQ(unsigned Opcode) {
29816 switch (Opcode) {
29817 case VCVTTPH2UDQZ128rm:
29818 case VCVTTPH2UDQZ128rmb:
29819 case VCVTTPH2UDQZ128rmbk:
29820 case VCVTTPH2UDQZ128rmbkz:
29821 case VCVTTPH2UDQZ128rmk:
29822 case VCVTTPH2UDQZ128rmkz:
29823 case VCVTTPH2UDQZ128rr:
29824 case VCVTTPH2UDQZ128rrk:
29825 case VCVTTPH2UDQZ128rrkz:
29826 case VCVTTPH2UDQZ256rm:
29827 case VCVTTPH2UDQZ256rmb:
29828 case VCVTTPH2UDQZ256rmbk:
29829 case VCVTTPH2UDQZ256rmbkz:
29830 case VCVTTPH2UDQZ256rmk:
29831 case VCVTTPH2UDQZ256rmkz:
29832 case VCVTTPH2UDQZ256rr:
29833 case VCVTTPH2UDQZ256rrk:
29834 case VCVTTPH2UDQZ256rrkz:
29835 case VCVTTPH2UDQZrm:
29836 case VCVTTPH2UDQZrmb:
29837 case VCVTTPH2UDQZrmbk:
29838 case VCVTTPH2UDQZrmbkz:
29839 case VCVTTPH2UDQZrmk:
29840 case VCVTTPH2UDQZrmkz:
29841 case VCVTTPH2UDQZrr:
29842 case VCVTTPH2UDQZrrb:
29843 case VCVTTPH2UDQZrrbk:
29844 case VCVTTPH2UDQZrrbkz:
29845 case VCVTTPH2UDQZrrk:
29846 case VCVTTPH2UDQZrrkz:
29847 return true;
29848 }
29849 return false;
29850}
29851
29852bool isVGETEXPPH(unsigned Opcode) {
29853 switch (Opcode) {
29854 case VGETEXPPHZ128m:
29855 case VGETEXPPHZ128mb:
29856 case VGETEXPPHZ128mbk:
29857 case VGETEXPPHZ128mbkz:
29858 case VGETEXPPHZ128mk:
29859 case VGETEXPPHZ128mkz:
29860 case VGETEXPPHZ128r:
29861 case VGETEXPPHZ128rk:
29862 case VGETEXPPHZ128rkz:
29863 case VGETEXPPHZ256m:
29864 case VGETEXPPHZ256mb:
29865 case VGETEXPPHZ256mbk:
29866 case VGETEXPPHZ256mbkz:
29867 case VGETEXPPHZ256mk:
29868 case VGETEXPPHZ256mkz:
29869 case VGETEXPPHZ256r:
29870 case VGETEXPPHZ256rk:
29871 case VGETEXPPHZ256rkz:
29872 case VGETEXPPHZm:
29873 case VGETEXPPHZmb:
29874 case VGETEXPPHZmbk:
29875 case VGETEXPPHZmbkz:
29876 case VGETEXPPHZmk:
29877 case VGETEXPPHZmkz:
29878 case VGETEXPPHZr:
29879 case VGETEXPPHZrb:
29880 case VGETEXPPHZrbk:
29881 case VGETEXPPHZrbkz:
29882 case VGETEXPPHZrk:
29883 case VGETEXPPHZrkz:
29884 return true;
29885 }
29886 return false;
29887}
29888
29889bool isADDPD(unsigned Opcode) {
29890 switch (Opcode) {
29891 case ADDPDrm:
29892 case ADDPDrr:
29893 return true;
29894 }
29895 return false;
29896}
29897
29898bool isVFNMADDPD(unsigned Opcode) {
29899 switch (Opcode) {
29900 case VFNMADDPD4Ymr:
29901 case VFNMADDPD4Yrm:
29902 case VFNMADDPD4Yrr:
29903 case VFNMADDPD4Yrr_REV:
29904 case VFNMADDPD4mr:
29905 case VFNMADDPD4rm:
29906 case VFNMADDPD4rr:
29907 case VFNMADDPD4rr_REV:
29908 return true;
29909 }
29910 return false;
29911}
29912
29913bool isSTTILECFG(unsigned Opcode) {
29914 switch (Opcode) {
29915 case STTILECFG:
29916 case STTILECFG_EVEX:
29917 return true;
29918 }
29919 return false;
29920}
29921
29922bool isVMINPD(unsigned Opcode) {
29923 switch (Opcode) {
29924 case VMINPDYrm:
29925 case VMINPDYrr:
29926 case VMINPDZ128rm:
29927 case VMINPDZ128rmb:
29928 case VMINPDZ128rmbk:
29929 case VMINPDZ128rmbkz:
29930 case VMINPDZ128rmk:
29931 case VMINPDZ128rmkz:
29932 case VMINPDZ128rr:
29933 case VMINPDZ128rrk:
29934 case VMINPDZ128rrkz:
29935 case VMINPDZ256rm:
29936 case VMINPDZ256rmb:
29937 case VMINPDZ256rmbk:
29938 case VMINPDZ256rmbkz:
29939 case VMINPDZ256rmk:
29940 case VMINPDZ256rmkz:
29941 case VMINPDZ256rr:
29942 case VMINPDZ256rrk:
29943 case VMINPDZ256rrkz:
29944 case VMINPDZrm:
29945 case VMINPDZrmb:
29946 case VMINPDZrmbk:
29947 case VMINPDZrmbkz:
29948 case VMINPDZrmk:
29949 case VMINPDZrmkz:
29950 case VMINPDZrr:
29951 case VMINPDZrrb:
29952 case VMINPDZrrbk:
29953 case VMINPDZrrbkz:
29954 case VMINPDZrrk:
29955 case VMINPDZrrkz:
29956 case VMINPDrm:
29957 case VMINPDrr:
29958 return true;
29959 }
29960 return false;
29961}
29962
29963bool isSHA1RNDS4(unsigned Opcode) {
29964 switch (Opcode) {
29965 case SHA1RNDS4rmi:
29966 case SHA1RNDS4rri:
29967 return true;
29968 }
29969 return false;
29970}
29971
29972bool isPBLENDVB(unsigned Opcode) {
29973 switch (Opcode) {
29974 case PBLENDVBrm0:
29975 case PBLENDVBrr0:
29976 return true;
29977 }
29978 return false;
29979}
29980
29981bool isVBROADCASTF128(unsigned Opcode) {
29982 return Opcode == VBROADCASTF128rm;
29983}
29984
29985bool isVPSHRDQ(unsigned Opcode) {
29986 switch (Opcode) {
29987 case VPSHRDQZ128rmbi:
29988 case VPSHRDQZ128rmbik:
29989 case VPSHRDQZ128rmbikz:
29990 case VPSHRDQZ128rmi:
29991 case VPSHRDQZ128rmik:
29992 case VPSHRDQZ128rmikz:
29993 case VPSHRDQZ128rri:
29994 case VPSHRDQZ128rrik:
29995 case VPSHRDQZ128rrikz:
29996 case VPSHRDQZ256rmbi:
29997 case VPSHRDQZ256rmbik:
29998 case VPSHRDQZ256rmbikz:
29999 case VPSHRDQZ256rmi:
30000 case VPSHRDQZ256rmik:
30001 case VPSHRDQZ256rmikz:
30002 case VPSHRDQZ256rri:
30003 case VPSHRDQZ256rrik:
30004 case VPSHRDQZ256rrikz:
30005 case VPSHRDQZrmbi:
30006 case VPSHRDQZrmbik:
30007 case VPSHRDQZrmbikz:
30008 case VPSHRDQZrmi:
30009 case VPSHRDQZrmik:
30010 case VPSHRDQZrmikz:
30011 case VPSHRDQZrri:
30012 case VPSHRDQZrrik:
30013 case VPSHRDQZrrikz:
30014 return true;
30015 }
30016 return false;
30017}
30018
30019bool isVAESIMC(unsigned Opcode) {
30020 switch (Opcode) {
30021 case VAESIMCrm:
30022 case VAESIMCrr:
30023 return true;
30024 }
30025 return false;
30026}
30027
30028bool isCOMISD(unsigned Opcode) {
30029 switch (Opcode) {
30030 case COMISDrm:
30031 case COMISDrr:
30032 return true;
30033 }
30034 return false;
30035}
30036
30037bool isVMOVSH(unsigned Opcode) {
30038 switch (Opcode) {
30039 case VMOVSHZmr:
30040 case VMOVSHZmrk:
30041 case VMOVSHZrm:
30042 case VMOVSHZrmk:
30043 case VMOVSHZrmkz:
30044 case VMOVSHZrr:
30045 case VMOVSHZrr_REV:
30046 case VMOVSHZrrk:
30047 case VMOVSHZrrk_REV:
30048 case VMOVSHZrrkz:
30049 case VMOVSHZrrkz_REV:
30050 return true;
30051 }
30052 return false;
30053}
30054
30055bool isPFSUBR(unsigned Opcode) {
30056 switch (Opcode) {
30057 case PFSUBRrm:
30058 case PFSUBRrr:
30059 return true;
30060 }
30061 return false;
30062}
30063
30064bool isRDSSPD(unsigned Opcode) {
30065 return Opcode == RDSSPD;
30066}
30067
30068bool isWAIT(unsigned Opcode) {
30069 return Opcode == WAIT;
30070}
30071
30072bool isVFPCLASSSS(unsigned Opcode) {
30073 switch (Opcode) {
30074 case VFPCLASSSSZmi:
30075 case VFPCLASSSSZmik:
30076 case VFPCLASSSSZri:
30077 case VFPCLASSSSZrik:
30078 return true;
30079 }
30080 return false;
30081}
30082
30083bool isPCMPGTD(unsigned Opcode) {
30084 switch (Opcode) {
30085 case MMX_PCMPGTDrm:
30086 case MMX_PCMPGTDrr:
30087 case PCMPGTDrm:
30088 case PCMPGTDrr:
30089 return true;
30090 }
30091 return false;
30092}
30093
30094bool isVGATHERPF0QPS(unsigned Opcode) {
30095 return Opcode == VGATHERPF0QPSm;
30096}
30097
30098bool isBLENDVPS(unsigned Opcode) {
30099 switch (Opcode) {
30100 case BLENDVPSrm0:
30101 case BLENDVPSrr0:
30102 return true;
30103 }
30104 return false;
30105}
30106
30107bool isVBROADCASTF32X4(unsigned Opcode) {
30108 switch (Opcode) {
30109 case VBROADCASTF32X4Z256rm:
30110 case VBROADCASTF32X4Z256rmk:
30111 case VBROADCASTF32X4Z256rmkz:
30112 case VBROADCASTF32X4Zrm:
30113 case VBROADCASTF32X4Zrmk:
30114 case VBROADCASTF32X4Zrmkz:
30115 return true;
30116 }
30117 return false;
30118}
30119
30120bool isVPMADD52LUQ(unsigned Opcode) {
30121 switch (Opcode) {
30122 case VPMADD52LUQYrm:
30123 case VPMADD52LUQYrr:
30124 case VPMADD52LUQZ128m:
30125 case VPMADD52LUQZ128mb:
30126 case VPMADD52LUQZ128mbk:
30127 case VPMADD52LUQZ128mbkz:
30128 case VPMADD52LUQZ128mk:
30129 case VPMADD52LUQZ128mkz:
30130 case VPMADD52LUQZ128r:
30131 case VPMADD52LUQZ128rk:
30132 case VPMADD52LUQZ128rkz:
30133 case VPMADD52LUQZ256m:
30134 case VPMADD52LUQZ256mb:
30135 case VPMADD52LUQZ256mbk:
30136 case VPMADD52LUQZ256mbkz:
30137 case VPMADD52LUQZ256mk:
30138 case VPMADD52LUQZ256mkz:
30139 case VPMADD52LUQZ256r:
30140 case VPMADD52LUQZ256rk:
30141 case VPMADD52LUQZ256rkz:
30142 case VPMADD52LUQZm:
30143 case VPMADD52LUQZmb:
30144 case VPMADD52LUQZmbk:
30145 case VPMADD52LUQZmbkz:
30146 case VPMADD52LUQZmk:
30147 case VPMADD52LUQZmkz:
30148 case VPMADD52LUQZr:
30149 case VPMADD52LUQZrk:
30150 case VPMADD52LUQZrkz:
30151 case VPMADD52LUQrm:
30152 case VPMADD52LUQrr:
30153 return true;
30154 }
30155 return false;
30156}
30157
30158bool isVMOVLPD(unsigned Opcode) {
30159 switch (Opcode) {
30160 case VMOVLPDZ128mr:
30161 case VMOVLPDZ128rm:
30162 case VMOVLPDmr:
30163 case VMOVLPDrm:
30164 return true;
30165 }
30166 return false;
30167}
30168
30169bool isVMOVQ(unsigned Opcode) {
30170 switch (Opcode) {
30171 case VMOV64toPQIZrm:
30172 case VMOV64toPQIZrr:
30173 case VMOV64toPQIrm:
30174 case VMOV64toPQIrr:
30175 case VMOVPQI2QIZmr:
30176 case VMOVPQI2QIZrr:
30177 case VMOVPQI2QImr:
30178 case VMOVPQI2QIrr:
30179 case VMOVPQIto64Zmr:
30180 case VMOVPQIto64Zrr:
30181 case VMOVPQIto64mr:
30182 case VMOVPQIto64rr:
30183 case VMOVQI2PQIZrm:
30184 case VMOVQI2PQIrm:
30185 case VMOVZPQILo2PQIZrr:
30186 case VMOVZPQILo2PQIrr:
30187 return true;
30188 }
30189 return false;
30190}
30191
30192bool isVMOVDQU(unsigned Opcode) {
30193 switch (Opcode) {
30194 case VMOVDQUYmr:
30195 case VMOVDQUYrm:
30196 case VMOVDQUYrr:
30197 case VMOVDQUYrr_REV:
30198 case VMOVDQUmr:
30199 case VMOVDQUrm:
30200 case VMOVDQUrr:
30201 case VMOVDQUrr_REV:
30202 return true;
30203 }
30204 return false;
30205}
30206
30207bool isAESENC128KL(unsigned Opcode) {
30208 return Opcode == AESENC128KL;
30209}
30210
30211bool isVFMADDSUB231PS(unsigned Opcode) {
30212 switch (Opcode) {
30213 case VFMADDSUB231PSYm:
30214 case VFMADDSUB231PSYr:
30215 case VFMADDSUB231PSZ128m:
30216 case VFMADDSUB231PSZ128mb:
30217 case VFMADDSUB231PSZ128mbk:
30218 case VFMADDSUB231PSZ128mbkz:
30219 case VFMADDSUB231PSZ128mk:
30220 case VFMADDSUB231PSZ128mkz:
30221 case VFMADDSUB231PSZ128r:
30222 case VFMADDSUB231PSZ128rk:
30223 case VFMADDSUB231PSZ128rkz:
30224 case VFMADDSUB231PSZ256m:
30225 case VFMADDSUB231PSZ256mb:
30226 case VFMADDSUB231PSZ256mbk:
30227 case VFMADDSUB231PSZ256mbkz:
30228 case VFMADDSUB231PSZ256mk:
30229 case VFMADDSUB231PSZ256mkz:
30230 case VFMADDSUB231PSZ256r:
30231 case VFMADDSUB231PSZ256rk:
30232 case VFMADDSUB231PSZ256rkz:
30233 case VFMADDSUB231PSZm:
30234 case VFMADDSUB231PSZmb:
30235 case VFMADDSUB231PSZmbk:
30236 case VFMADDSUB231PSZmbkz:
30237 case VFMADDSUB231PSZmk:
30238 case VFMADDSUB231PSZmkz:
30239 case VFMADDSUB231PSZr:
30240 case VFMADDSUB231PSZrb:
30241 case VFMADDSUB231PSZrbk:
30242 case VFMADDSUB231PSZrbkz:
30243 case VFMADDSUB231PSZrk:
30244 case VFMADDSUB231PSZrkz:
30245 case VFMADDSUB231PSm:
30246 case VFMADDSUB231PSr:
30247 return true;
30248 }
30249 return false;
30250}
30251
30252bool isVFNMSUB213PD(unsigned Opcode) {
30253 switch (Opcode) {
30254 case VFNMSUB213PDYm:
30255 case VFNMSUB213PDYr:
30256 case VFNMSUB213PDZ128m:
30257 case VFNMSUB213PDZ128mb:
30258 case VFNMSUB213PDZ128mbk:
30259 case VFNMSUB213PDZ128mbkz:
30260 case VFNMSUB213PDZ128mk:
30261 case VFNMSUB213PDZ128mkz:
30262 case VFNMSUB213PDZ128r:
30263 case VFNMSUB213PDZ128rk:
30264 case VFNMSUB213PDZ128rkz:
30265 case VFNMSUB213PDZ256m:
30266 case VFNMSUB213PDZ256mb:
30267 case VFNMSUB213PDZ256mbk:
30268 case VFNMSUB213PDZ256mbkz:
30269 case VFNMSUB213PDZ256mk:
30270 case VFNMSUB213PDZ256mkz:
30271 case VFNMSUB213PDZ256r:
30272 case VFNMSUB213PDZ256rk:
30273 case VFNMSUB213PDZ256rkz:
30274 case VFNMSUB213PDZm:
30275 case VFNMSUB213PDZmb:
30276 case VFNMSUB213PDZmbk:
30277 case VFNMSUB213PDZmbkz:
30278 case VFNMSUB213PDZmk:
30279 case VFNMSUB213PDZmkz:
30280 case VFNMSUB213PDZr:
30281 case VFNMSUB213PDZrb:
30282 case VFNMSUB213PDZrbk:
30283 case VFNMSUB213PDZrbkz:
30284 case VFNMSUB213PDZrk:
30285 case VFNMSUB213PDZrkz:
30286 case VFNMSUB213PDm:
30287 case VFNMSUB213PDr:
30288 return true;
30289 }
30290 return false;
30291}
30292
30293bool isVPCONFLICTD(unsigned Opcode) {
30294 switch (Opcode) {
30295 case VPCONFLICTDZ128rm:
30296 case VPCONFLICTDZ128rmb:
30297 case VPCONFLICTDZ128rmbk:
30298 case VPCONFLICTDZ128rmbkz:
30299 case VPCONFLICTDZ128rmk:
30300 case VPCONFLICTDZ128rmkz:
30301 case VPCONFLICTDZ128rr:
30302 case VPCONFLICTDZ128rrk:
30303 case VPCONFLICTDZ128rrkz:
30304 case VPCONFLICTDZ256rm:
30305 case VPCONFLICTDZ256rmb:
30306 case VPCONFLICTDZ256rmbk:
30307 case VPCONFLICTDZ256rmbkz:
30308 case VPCONFLICTDZ256rmk:
30309 case VPCONFLICTDZ256rmkz:
30310 case VPCONFLICTDZ256rr:
30311 case VPCONFLICTDZ256rrk:
30312 case VPCONFLICTDZ256rrkz:
30313 case VPCONFLICTDZrm:
30314 case VPCONFLICTDZrmb:
30315 case VPCONFLICTDZrmbk:
30316 case VPCONFLICTDZrmbkz:
30317 case VPCONFLICTDZrmk:
30318 case VPCONFLICTDZrmkz:
30319 case VPCONFLICTDZrr:
30320 case VPCONFLICTDZrrk:
30321 case VPCONFLICTDZrrkz:
30322 return true;
30323 }
30324 return false;
30325}
30326
30327bool isVFMADDSUB213PH(unsigned Opcode) {
30328 switch (Opcode) {
30329 case VFMADDSUB213PHZ128m:
30330 case VFMADDSUB213PHZ128mb:
30331 case VFMADDSUB213PHZ128mbk:
30332 case VFMADDSUB213PHZ128mbkz:
30333 case VFMADDSUB213PHZ128mk:
30334 case VFMADDSUB213PHZ128mkz:
30335 case VFMADDSUB213PHZ128r:
30336 case VFMADDSUB213PHZ128rk:
30337 case VFMADDSUB213PHZ128rkz:
30338 case VFMADDSUB213PHZ256m:
30339 case VFMADDSUB213PHZ256mb:
30340 case VFMADDSUB213PHZ256mbk:
30341 case VFMADDSUB213PHZ256mbkz:
30342 case VFMADDSUB213PHZ256mk:
30343 case VFMADDSUB213PHZ256mkz:
30344 case VFMADDSUB213PHZ256r:
30345 case VFMADDSUB213PHZ256rk:
30346 case VFMADDSUB213PHZ256rkz:
30347 case VFMADDSUB213PHZm:
30348 case VFMADDSUB213PHZmb:
30349 case VFMADDSUB213PHZmbk:
30350 case VFMADDSUB213PHZmbkz:
30351 case VFMADDSUB213PHZmk:
30352 case VFMADDSUB213PHZmkz:
30353 case VFMADDSUB213PHZr:
30354 case VFMADDSUB213PHZrb:
30355 case VFMADDSUB213PHZrbk:
30356 case VFMADDSUB213PHZrbkz:
30357 case VFMADDSUB213PHZrk:
30358 case VFMADDSUB213PHZrkz:
30359 return true;
30360 }
30361 return false;
30362}
30363
30364bool isVPHSUBSW(unsigned Opcode) {
30365 switch (Opcode) {
30366 case VPHSUBSWYrm:
30367 case VPHSUBSWYrr:
30368 case VPHSUBSWrm:
30369 case VPHSUBSWrr:
30370 return true;
30371 }
30372 return false;
30373}
30374
30375bool isPUNPCKHDQ(unsigned Opcode) {
30376 switch (Opcode) {
30377 case MMX_PUNPCKHDQrm:
30378 case MMX_PUNPCKHDQrr:
30379 case PUNPCKHDQrm:
30380 case PUNPCKHDQrr:
30381 return true;
30382 }
30383 return false;
30384}
30385
30386bool isVSHUFI64X2(unsigned Opcode) {
30387 switch (Opcode) {
30388 case VSHUFI64X2Z256rmbi:
30389 case VSHUFI64X2Z256rmbik:
30390 case VSHUFI64X2Z256rmbikz:
30391 case VSHUFI64X2Z256rmi:
30392 case VSHUFI64X2Z256rmik:
30393 case VSHUFI64X2Z256rmikz:
30394 case VSHUFI64X2Z256rri:
30395 case VSHUFI64X2Z256rrik:
30396 case VSHUFI64X2Z256rrikz:
30397 case VSHUFI64X2Zrmbi:
30398 case VSHUFI64X2Zrmbik:
30399 case VSHUFI64X2Zrmbikz:
30400 case VSHUFI64X2Zrmi:
30401 case VSHUFI64X2Zrmik:
30402 case VSHUFI64X2Zrmikz:
30403 case VSHUFI64X2Zrri:
30404 case VSHUFI64X2Zrrik:
30405 case VSHUFI64X2Zrrikz:
30406 return true;
30407 }
30408 return false;
30409}
30410
30411bool isVFMSUBSD(unsigned Opcode) {
30412 switch (Opcode) {
30413 case VFMSUBSD4mr:
30414 case VFMSUBSD4rm:
30415 case VFMSUBSD4rr:
30416 case VFMSUBSD4rr_REV:
30417 return true;
30418 }
30419 return false;
30420}
30421
30422bool isVPORD(unsigned Opcode) {
30423 switch (Opcode) {
30424 case VPORDZ128rm:
30425 case VPORDZ128rmb:
30426 case VPORDZ128rmbk:
30427 case VPORDZ128rmbkz:
30428 case VPORDZ128rmk:
30429 case VPORDZ128rmkz:
30430 case VPORDZ128rr:
30431 case VPORDZ128rrk:
30432 case VPORDZ128rrkz:
30433 case VPORDZ256rm:
30434 case VPORDZ256rmb:
30435 case VPORDZ256rmbk:
30436 case VPORDZ256rmbkz:
30437 case VPORDZ256rmk:
30438 case VPORDZ256rmkz:
30439 case VPORDZ256rr:
30440 case VPORDZ256rrk:
30441 case VPORDZ256rrkz:
30442 case VPORDZrm:
30443 case VPORDZrmb:
30444 case VPORDZrmbk:
30445 case VPORDZrmbkz:
30446 case VPORDZrmk:
30447 case VPORDZrmkz:
30448 case VPORDZrr:
30449 case VPORDZrrk:
30450 case VPORDZrrkz:
30451 return true;
30452 }
30453 return false;
30454}
30455
30456bool isRCPPS(unsigned Opcode) {
30457 switch (Opcode) {
30458 case RCPPSm:
30459 case RCPPSr:
30460 return true;
30461 }
30462 return false;
30463}
30464
30465bool isVEXTRACTI128(unsigned Opcode) {
30466 switch (Opcode) {
30467 case VEXTRACTI128mri:
30468 case VEXTRACTI128rri:
30469 return true;
30470 }
30471 return false;
30472}
30473
30474bool isVCVT2PH2BF8S(unsigned Opcode) {
30475 switch (Opcode) {
30476 case VCVT2PH2BF8SZ128rm:
30477 case VCVT2PH2BF8SZ128rmb:
30478 case VCVT2PH2BF8SZ128rmbk:
30479 case VCVT2PH2BF8SZ128rmbkz:
30480 case VCVT2PH2BF8SZ128rmk:
30481 case VCVT2PH2BF8SZ128rmkz:
30482 case VCVT2PH2BF8SZ128rr:
30483 case VCVT2PH2BF8SZ128rrk:
30484 case VCVT2PH2BF8SZ128rrkz:
30485 case VCVT2PH2BF8SZ256rm:
30486 case VCVT2PH2BF8SZ256rmb:
30487 case VCVT2PH2BF8SZ256rmbk:
30488 case VCVT2PH2BF8SZ256rmbkz:
30489 case VCVT2PH2BF8SZ256rmk:
30490 case VCVT2PH2BF8SZ256rmkz:
30491 case VCVT2PH2BF8SZ256rr:
30492 case VCVT2PH2BF8SZ256rrk:
30493 case VCVT2PH2BF8SZ256rrkz:
30494 case VCVT2PH2BF8SZrm:
30495 case VCVT2PH2BF8SZrmb:
30496 case VCVT2PH2BF8SZrmbk:
30497 case VCVT2PH2BF8SZrmbkz:
30498 case VCVT2PH2BF8SZrmk:
30499 case VCVT2PH2BF8SZrmkz:
30500 case VCVT2PH2BF8SZrr:
30501 case VCVT2PH2BF8SZrrk:
30502 case VCVT2PH2BF8SZrrkz:
30503 return true;
30504 }
30505 return false;
30506}
30507
30508bool isVPSHRDVW(unsigned Opcode) {
30509 switch (Opcode) {
30510 case VPSHRDVWZ128m:
30511 case VPSHRDVWZ128mk:
30512 case VPSHRDVWZ128mkz:
30513 case VPSHRDVWZ128r:
30514 case VPSHRDVWZ128rk:
30515 case VPSHRDVWZ128rkz:
30516 case VPSHRDVWZ256m:
30517 case VPSHRDVWZ256mk:
30518 case VPSHRDVWZ256mkz:
30519 case VPSHRDVWZ256r:
30520 case VPSHRDVWZ256rk:
30521 case VPSHRDVWZ256rkz:
30522 case VPSHRDVWZm:
30523 case VPSHRDVWZmk:
30524 case VPSHRDVWZmkz:
30525 case VPSHRDVWZr:
30526 case VPSHRDVWZrk:
30527 case VPSHRDVWZrkz:
30528 return true;
30529 }
30530 return false;
30531}
30532
30533bool isVUNPCKLPD(unsigned Opcode) {
30534 switch (Opcode) {
30535 case VUNPCKLPDYrm:
30536 case VUNPCKLPDYrr:
30537 case VUNPCKLPDZ128rm:
30538 case VUNPCKLPDZ128rmb:
30539 case VUNPCKLPDZ128rmbk:
30540 case VUNPCKLPDZ128rmbkz:
30541 case VUNPCKLPDZ128rmk:
30542 case VUNPCKLPDZ128rmkz:
30543 case VUNPCKLPDZ128rr:
30544 case VUNPCKLPDZ128rrk:
30545 case VUNPCKLPDZ128rrkz:
30546 case VUNPCKLPDZ256rm:
30547 case VUNPCKLPDZ256rmb:
30548 case VUNPCKLPDZ256rmbk:
30549 case VUNPCKLPDZ256rmbkz:
30550 case VUNPCKLPDZ256rmk:
30551 case VUNPCKLPDZ256rmkz:
30552 case VUNPCKLPDZ256rr:
30553 case VUNPCKLPDZ256rrk:
30554 case VUNPCKLPDZ256rrkz:
30555 case VUNPCKLPDZrm:
30556 case VUNPCKLPDZrmb:
30557 case VUNPCKLPDZrmbk:
30558 case VUNPCKLPDZrmbkz:
30559 case VUNPCKLPDZrmk:
30560 case VUNPCKLPDZrmkz:
30561 case VUNPCKLPDZrr:
30562 case VUNPCKLPDZrrk:
30563 case VUNPCKLPDZrrkz:
30564 case VUNPCKLPDrm:
30565 case VUNPCKLPDrr:
30566 return true;
30567 }
30568 return false;
30569}
30570
30571bool isVPSRAVD(unsigned Opcode) {
30572 switch (Opcode) {
30573 case VPSRAVDYrm:
30574 case VPSRAVDYrr:
30575 case VPSRAVDZ128rm:
30576 case VPSRAVDZ128rmb:
30577 case VPSRAVDZ128rmbk:
30578 case VPSRAVDZ128rmbkz:
30579 case VPSRAVDZ128rmk:
30580 case VPSRAVDZ128rmkz:
30581 case VPSRAVDZ128rr:
30582 case VPSRAVDZ128rrk:
30583 case VPSRAVDZ128rrkz:
30584 case VPSRAVDZ256rm:
30585 case VPSRAVDZ256rmb:
30586 case VPSRAVDZ256rmbk:
30587 case VPSRAVDZ256rmbkz:
30588 case VPSRAVDZ256rmk:
30589 case VPSRAVDZ256rmkz:
30590 case VPSRAVDZ256rr:
30591 case VPSRAVDZ256rrk:
30592 case VPSRAVDZ256rrkz:
30593 case VPSRAVDZrm:
30594 case VPSRAVDZrmb:
30595 case VPSRAVDZrmbk:
30596 case VPSRAVDZrmbkz:
30597 case VPSRAVDZrmk:
30598 case VPSRAVDZrmkz:
30599 case VPSRAVDZrr:
30600 case VPSRAVDZrrk:
30601 case VPSRAVDZrrkz:
30602 case VPSRAVDrm:
30603 case VPSRAVDrr:
30604 return true;
30605 }
30606 return false;
30607}
30608
30609bool isVMULSH(unsigned Opcode) {
30610 switch (Opcode) {
30611 case VMULSHZrm_Int:
30612 case VMULSHZrmk_Int:
30613 case VMULSHZrmkz_Int:
30614 case VMULSHZrr_Int:
30615 case VMULSHZrrb_Int:
30616 case VMULSHZrrbk_Int:
30617 case VMULSHZrrbkz_Int:
30618 case VMULSHZrrk_Int:
30619 case VMULSHZrrkz_Int:
30620 return true;
30621 }
30622 return false;
30623}
30624
30625bool isMOVNTSS(unsigned Opcode) {
30626 return Opcode == MOVNTSS;
30627}
30628
30629bool isSTI(unsigned Opcode) {
30630 return Opcode == STI;
30631}
30632
30633bool isVSM4RNDS4(unsigned Opcode) {
30634 switch (Opcode) {
30635 case VSM4RNDS4Yrm:
30636 case VSM4RNDS4Yrr:
30637 case VSM4RNDS4Z128rm:
30638 case VSM4RNDS4Z128rr:
30639 case VSM4RNDS4Z256rm:
30640 case VSM4RNDS4Z256rr:
30641 case VSM4RNDS4Zrm:
30642 case VSM4RNDS4Zrr:
30643 case VSM4RNDS4rm:
30644 case VSM4RNDS4rr:
30645 return true;
30646 }
30647 return false;
30648}
30649
30650bool isVMCLEAR(unsigned Opcode) {
30651 return Opcode == VMCLEARm;
30652}
30653
30654bool isVPMADD52HUQ(unsigned Opcode) {
30655 switch (Opcode) {
30656 case VPMADD52HUQYrm:
30657 case VPMADD52HUQYrr:
30658 case VPMADD52HUQZ128m:
30659 case VPMADD52HUQZ128mb:
30660 case VPMADD52HUQZ128mbk:
30661 case VPMADD52HUQZ128mbkz:
30662 case VPMADD52HUQZ128mk:
30663 case VPMADD52HUQZ128mkz:
30664 case VPMADD52HUQZ128r:
30665 case VPMADD52HUQZ128rk:
30666 case VPMADD52HUQZ128rkz:
30667 case VPMADD52HUQZ256m:
30668 case VPMADD52HUQZ256mb:
30669 case VPMADD52HUQZ256mbk:
30670 case VPMADD52HUQZ256mbkz:
30671 case VPMADD52HUQZ256mk:
30672 case VPMADD52HUQZ256mkz:
30673 case VPMADD52HUQZ256r:
30674 case VPMADD52HUQZ256rk:
30675 case VPMADD52HUQZ256rkz:
30676 case VPMADD52HUQZm:
30677 case VPMADD52HUQZmb:
30678 case VPMADD52HUQZmbk:
30679 case VPMADD52HUQZmbkz:
30680 case VPMADD52HUQZmk:
30681 case VPMADD52HUQZmkz:
30682 case VPMADD52HUQZr:
30683 case VPMADD52HUQZrk:
30684 case VPMADD52HUQZrkz:
30685 case VPMADD52HUQrm:
30686 case VPMADD52HUQrr:
30687 return true;
30688 }
30689 return false;
30690}
30691
30692bool isLIDT(unsigned Opcode) {
30693 return Opcode == LIDT64m;
30694}
30695
30696bool isPUSH2(unsigned Opcode) {
30697 return Opcode == PUSH2;
30698}
30699
30700bool isVCVTPS2IUBS(unsigned Opcode) {
30701 switch (Opcode) {
30702 case VCVTPS2IUBSZ128rm:
30703 case VCVTPS2IUBSZ128rmb:
30704 case VCVTPS2IUBSZ128rmbk:
30705 case VCVTPS2IUBSZ128rmbkz:
30706 case VCVTPS2IUBSZ128rmk:
30707 case VCVTPS2IUBSZ128rmkz:
30708 case VCVTPS2IUBSZ128rr:
30709 case VCVTPS2IUBSZ128rrk:
30710 case VCVTPS2IUBSZ128rrkz:
30711 case VCVTPS2IUBSZ256rm:
30712 case VCVTPS2IUBSZ256rmb:
30713 case VCVTPS2IUBSZ256rmbk:
30714 case VCVTPS2IUBSZ256rmbkz:
30715 case VCVTPS2IUBSZ256rmk:
30716 case VCVTPS2IUBSZ256rmkz:
30717 case VCVTPS2IUBSZ256rr:
30718 case VCVTPS2IUBSZ256rrk:
30719 case VCVTPS2IUBSZ256rrkz:
30720 case VCVTPS2IUBSZrm:
30721 case VCVTPS2IUBSZrmb:
30722 case VCVTPS2IUBSZrmbk:
30723 case VCVTPS2IUBSZrmbkz:
30724 case VCVTPS2IUBSZrmk:
30725 case VCVTPS2IUBSZrmkz:
30726 case VCVTPS2IUBSZrr:
30727 case VCVTPS2IUBSZrrb:
30728 case VCVTPS2IUBSZrrbk:
30729 case VCVTPS2IUBSZrrbkz:
30730 case VCVTPS2IUBSZrrk:
30731 case VCVTPS2IUBSZrrkz:
30732 return true;
30733 }
30734 return false;
30735}
30736
30737bool isRDPKRU(unsigned Opcode) {
30738 return Opcode == RDPKRUr;
30739}
30740
30741bool isVPCMPB(unsigned Opcode) {
30742 switch (Opcode) {
30743 case VPCMPBZ128rmi:
30744 case VPCMPBZ128rmik:
30745 case VPCMPBZ128rri:
30746 case VPCMPBZ128rrik:
30747 case VPCMPBZ256rmi:
30748 case VPCMPBZ256rmik:
30749 case VPCMPBZ256rri:
30750 case VPCMPBZ256rrik:
30751 case VPCMPBZrmi:
30752 case VPCMPBZrmik:
30753 case VPCMPBZrri:
30754 case VPCMPBZrrik:
30755 return true;
30756 }
30757 return false;
30758}
30759
30760bool isVFMSUB231BF16(unsigned Opcode) {
30761 switch (Opcode) {
30762 case VFMSUB231BF16Z128m:
30763 case VFMSUB231BF16Z128mb:
30764 case VFMSUB231BF16Z128mbk:
30765 case VFMSUB231BF16Z128mbkz:
30766 case VFMSUB231BF16Z128mk:
30767 case VFMSUB231BF16Z128mkz:
30768 case VFMSUB231BF16Z128r:
30769 case VFMSUB231BF16Z128rk:
30770 case VFMSUB231BF16Z128rkz:
30771 case VFMSUB231BF16Z256m:
30772 case VFMSUB231BF16Z256mb:
30773 case VFMSUB231BF16Z256mbk:
30774 case VFMSUB231BF16Z256mbkz:
30775 case VFMSUB231BF16Z256mk:
30776 case VFMSUB231BF16Z256mkz:
30777 case VFMSUB231BF16Z256r:
30778 case VFMSUB231BF16Z256rk:
30779 case VFMSUB231BF16Z256rkz:
30780 case VFMSUB231BF16Zm:
30781 case VFMSUB231BF16Zmb:
30782 case VFMSUB231BF16Zmbk:
30783 case VFMSUB231BF16Zmbkz:
30784 case VFMSUB231BF16Zmk:
30785 case VFMSUB231BF16Zmkz:
30786 case VFMSUB231BF16Zr:
30787 case VFMSUB231BF16Zrk:
30788 case VFMSUB231BF16Zrkz:
30789 return true;
30790 }
30791 return false;
30792}
30793
30794bool isFINCSTP(unsigned Opcode) {
30795 return Opcode == FINCSTP;
30796}
30797
30798bool isKORQ(unsigned Opcode) {
30799 return Opcode == KORQkk;
30800}
30801
30802bool isXCRYPTCBC(unsigned Opcode) {
30803 return Opcode == XCRYPTCBC;
30804}
30805
30806bool isRDPMC(unsigned Opcode) {
30807 return Opcode == RDPMC;
30808}
30809
30810bool isMOVMSKPD(unsigned Opcode) {
30811 return Opcode == MOVMSKPDrr;
30812}
30813
30814bool isVFMSUB231SH(unsigned Opcode) {
30815 switch (Opcode) {
30816 case VFMSUB231SHZm_Int:
30817 case VFMSUB231SHZmk_Int:
30818 case VFMSUB231SHZmkz_Int:
30819 case VFMSUB231SHZr_Int:
30820 case VFMSUB231SHZrb_Int:
30821 case VFMSUB231SHZrbk_Int:
30822 case VFMSUB231SHZrbkz_Int:
30823 case VFMSUB231SHZrk_Int:
30824 case VFMSUB231SHZrkz_Int:
30825 return true;
30826 }
30827 return false;
30828}
30829
30830bool isVEXTRACTF128(unsigned Opcode) {
30831 switch (Opcode) {
30832 case VEXTRACTF128mri:
30833 case VEXTRACTF128rri:
30834 return true;
30835 }
30836 return false;
30837}
30838
30839bool isVPSHLB(unsigned Opcode) {
30840 switch (Opcode) {
30841 case VPSHLBmr:
30842 case VPSHLBrm:
30843 case VPSHLBrr:
30844 case VPSHLBrr_REV:
30845 return true;
30846 }
30847 return false;
30848}
30849
30850bool isXSAVES64(unsigned Opcode) {
30851 return Opcode == XSAVES64;
30852}
30853
30854bool isSHL(unsigned Opcode) {
30855 switch (Opcode) {
30856 case SHL16m1:
30857 case SHL16m1_EVEX:
30858 case SHL16m1_ND:
30859 case SHL16m1_NF:
30860 case SHL16m1_NF_ND:
30861 case SHL16mCL:
30862 case SHL16mCL_EVEX:
30863 case SHL16mCL_ND:
30864 case SHL16mCL_NF:
30865 case SHL16mCL_NF_ND:
30866 case SHL16mi:
30867 case SHL16mi_EVEX:
30868 case SHL16mi_ND:
30869 case SHL16mi_NF:
30870 case SHL16mi_NF_ND:
30871 case SHL16r1:
30872 case SHL16r1_EVEX:
30873 case SHL16r1_ND:
30874 case SHL16r1_NF:
30875 case SHL16r1_NF_ND:
30876 case SHL16rCL:
30877 case SHL16rCL_EVEX:
30878 case SHL16rCL_ND:
30879 case SHL16rCL_NF:
30880 case SHL16rCL_NF_ND:
30881 case SHL16ri:
30882 case SHL16ri_EVEX:
30883 case SHL16ri_ND:
30884 case SHL16ri_NF:
30885 case SHL16ri_NF_ND:
30886 case SHL32m1:
30887 case SHL32m1_EVEX:
30888 case SHL32m1_ND:
30889 case SHL32m1_NF:
30890 case SHL32m1_NF_ND:
30891 case SHL32mCL:
30892 case SHL32mCL_EVEX:
30893 case SHL32mCL_ND:
30894 case SHL32mCL_NF:
30895 case SHL32mCL_NF_ND:
30896 case SHL32mi:
30897 case SHL32mi_EVEX:
30898 case SHL32mi_ND:
30899 case SHL32mi_NF:
30900 case SHL32mi_NF_ND:
30901 case SHL32r1:
30902 case SHL32r1_EVEX:
30903 case SHL32r1_ND:
30904 case SHL32r1_NF:
30905 case SHL32r1_NF_ND:
30906 case SHL32rCL:
30907 case SHL32rCL_EVEX:
30908 case SHL32rCL_ND:
30909 case SHL32rCL_NF:
30910 case SHL32rCL_NF_ND:
30911 case SHL32ri:
30912 case SHL32ri_EVEX:
30913 case SHL32ri_ND:
30914 case SHL32ri_NF:
30915 case SHL32ri_NF_ND:
30916 case SHL64m1:
30917 case SHL64m1_EVEX:
30918 case SHL64m1_ND:
30919 case SHL64m1_NF:
30920 case SHL64m1_NF_ND:
30921 case SHL64mCL:
30922 case SHL64mCL_EVEX:
30923 case SHL64mCL_ND:
30924 case SHL64mCL_NF:
30925 case SHL64mCL_NF_ND:
30926 case SHL64mi:
30927 case SHL64mi_EVEX:
30928 case SHL64mi_ND:
30929 case SHL64mi_NF:
30930 case SHL64mi_NF_ND:
30931 case SHL64r1:
30932 case SHL64r1_EVEX:
30933 case SHL64r1_ND:
30934 case SHL64r1_NF:
30935 case SHL64r1_NF_ND:
30936 case SHL64rCL:
30937 case SHL64rCL_EVEX:
30938 case SHL64rCL_ND:
30939 case SHL64rCL_NF:
30940 case SHL64rCL_NF_ND:
30941 case SHL64ri:
30942 case SHL64ri_EVEX:
30943 case SHL64ri_ND:
30944 case SHL64ri_NF:
30945 case SHL64ri_NF_ND:
30946 case SHL8m1:
30947 case SHL8m1_EVEX:
30948 case SHL8m1_ND:
30949 case SHL8m1_NF:
30950 case SHL8m1_NF_ND:
30951 case SHL8mCL:
30952 case SHL8mCL_EVEX:
30953 case SHL8mCL_ND:
30954 case SHL8mCL_NF:
30955 case SHL8mCL_NF_ND:
30956 case SHL8mi:
30957 case SHL8mi_EVEX:
30958 case SHL8mi_ND:
30959 case SHL8mi_NF:
30960 case SHL8mi_NF_ND:
30961 case SHL8r1:
30962 case SHL8r1_EVEX:
30963 case SHL8r1_ND:
30964 case SHL8r1_NF:
30965 case SHL8r1_NF_ND:
30966 case SHL8rCL:
30967 case SHL8rCL_EVEX:
30968 case SHL8rCL_ND:
30969 case SHL8rCL_NF:
30970 case SHL8rCL_NF_ND:
30971 case SHL8ri:
30972 case SHL8ri_EVEX:
30973 case SHL8ri_ND:
30974 case SHL8ri_NF:
30975 case SHL8ri_NF_ND:
30976 return true;
30977 }
30978 return false;
30979}
30980
30981bool isAXOR(unsigned Opcode) {
30982 switch (Opcode) {
30983 case AXOR32mr:
30984 case AXOR32mr_EVEX:
30985 case AXOR64mr:
30986 case AXOR64mr_EVEX:
30987 return true;
30988 }
30989 return false;
30990}
30991
30992bool isVINSERTI64X2(unsigned Opcode) {
30993 switch (Opcode) {
30994 case VINSERTI64X2Z256rmi:
30995 case VINSERTI64X2Z256rmik:
30996 case VINSERTI64X2Z256rmikz:
30997 case VINSERTI64X2Z256rri:
30998 case VINSERTI64X2Z256rrik:
30999 case VINSERTI64X2Z256rrikz:
31000 case VINSERTI64X2Zrmi:
31001 case VINSERTI64X2Zrmik:
31002 case VINSERTI64X2Zrmikz:
31003 case VINSERTI64X2Zrri:
31004 case VINSERTI64X2Zrrik:
31005 case VINSERTI64X2Zrrikz:
31006 return true;
31007 }
31008 return false;
31009}
31010
31011bool isSYSRETQ(unsigned Opcode) {
31012 return Opcode == SYSRET64;
31013}
31014
31015bool isVSCATTERPF0QPD(unsigned Opcode) {
31016 return Opcode == VSCATTERPF0QPDm;
31017}
31018
31019bool isVFMSUB213SH(unsigned Opcode) {
31020 switch (Opcode) {
31021 case VFMSUB213SHZm_Int:
31022 case VFMSUB213SHZmk_Int:
31023 case VFMSUB213SHZmkz_Int:
31024 case VFMSUB213SHZr_Int:
31025 case VFMSUB213SHZrb_Int:
31026 case VFMSUB213SHZrbk_Int:
31027 case VFMSUB213SHZrbkz_Int:
31028 case VFMSUB213SHZrk_Int:
31029 case VFMSUB213SHZrkz_Int:
31030 return true;
31031 }
31032 return false;
31033}
31034
31035bool isVPMOVQW(unsigned Opcode) {
31036 switch (Opcode) {
31037 case VPMOVQWZ128mr:
31038 case VPMOVQWZ128mrk:
31039 case VPMOVQWZ128rr:
31040 case VPMOVQWZ128rrk:
31041 case VPMOVQWZ128rrkz:
31042 case VPMOVQWZ256mr:
31043 case VPMOVQWZ256mrk:
31044 case VPMOVQWZ256rr:
31045 case VPMOVQWZ256rrk:
31046 case VPMOVQWZ256rrkz:
31047 case VPMOVQWZmr:
31048 case VPMOVQWZmrk:
31049 case VPMOVQWZrr:
31050 case VPMOVQWZrrk:
31051 case VPMOVQWZrrkz:
31052 return true;
31053 }
31054 return false;
31055}
31056
31057bool isVREDUCEPD(unsigned Opcode) {
31058 switch (Opcode) {
31059 case VREDUCEPDZ128rmbi:
31060 case VREDUCEPDZ128rmbik:
31061 case VREDUCEPDZ128rmbikz:
31062 case VREDUCEPDZ128rmi:
31063 case VREDUCEPDZ128rmik:
31064 case VREDUCEPDZ128rmikz:
31065 case VREDUCEPDZ128rri:
31066 case VREDUCEPDZ128rrik:
31067 case VREDUCEPDZ128rrikz:
31068 case VREDUCEPDZ256rmbi:
31069 case VREDUCEPDZ256rmbik:
31070 case VREDUCEPDZ256rmbikz:
31071 case VREDUCEPDZ256rmi:
31072 case VREDUCEPDZ256rmik:
31073 case VREDUCEPDZ256rmikz:
31074 case VREDUCEPDZ256rri:
31075 case VREDUCEPDZ256rrik:
31076 case VREDUCEPDZ256rrikz:
31077 case VREDUCEPDZrmbi:
31078 case VREDUCEPDZrmbik:
31079 case VREDUCEPDZrmbikz:
31080 case VREDUCEPDZrmi:
31081 case VREDUCEPDZrmik:
31082 case VREDUCEPDZrmikz:
31083 case VREDUCEPDZrri:
31084 case VREDUCEPDZrrib:
31085 case VREDUCEPDZrribk:
31086 case VREDUCEPDZrribkz:
31087 case VREDUCEPDZrrik:
31088 case VREDUCEPDZrrikz:
31089 return true;
31090 }
31091 return false;
31092}
31093
31094bool isNOT(unsigned Opcode) {
31095 switch (Opcode) {
31096 case NOT16m:
31097 case NOT16m_EVEX:
31098 case NOT16m_ND:
31099 case NOT16r:
31100 case NOT16r_EVEX:
31101 case NOT16r_ND:
31102 case NOT32m:
31103 case NOT32m_EVEX:
31104 case NOT32m_ND:
31105 case NOT32r:
31106 case NOT32r_EVEX:
31107 case NOT32r_ND:
31108 case NOT64m:
31109 case NOT64m_EVEX:
31110 case NOT64m_ND:
31111 case NOT64r:
31112 case NOT64r_EVEX:
31113 case NOT64r_ND:
31114 case NOT8m:
31115 case NOT8m_EVEX:
31116 case NOT8m_ND:
31117 case NOT8r:
31118 case NOT8r_EVEX:
31119 case NOT8r_ND:
31120 return true;
31121 }
31122 return false;
31123}
31124
31125bool isLWPINS(unsigned Opcode) {
31126 switch (Opcode) {
31127 case LWPINS32rmi:
31128 case LWPINS32rri:
31129 case LWPINS64rmi:
31130 case LWPINS64rri:
31131 return true;
31132 }
31133 return false;
31134}
31135
31136bool isVSCATTERDPS(unsigned Opcode) {
31137 switch (Opcode) {
31138 case VSCATTERDPSZ128mr:
31139 case VSCATTERDPSZ256mr:
31140 case VSCATTERDPSZmr:
31141 return true;
31142 }
31143 return false;
31144}
31145
31146bool isVPMOVM2W(unsigned Opcode) {
31147 switch (Opcode) {
31148 case VPMOVM2WZ128rk:
31149 case VPMOVM2WZ256rk:
31150 case VPMOVM2WZrk:
31151 return true;
31152 }
31153 return false;
31154}
31155
31156bool isVFNMADD132PS(unsigned Opcode) {
31157 switch (Opcode) {
31158 case VFNMADD132PSYm:
31159 case VFNMADD132PSYr:
31160 case VFNMADD132PSZ128m:
31161 case VFNMADD132PSZ128mb:
31162 case VFNMADD132PSZ128mbk:
31163 case VFNMADD132PSZ128mbkz:
31164 case VFNMADD132PSZ128mk:
31165 case VFNMADD132PSZ128mkz:
31166 case VFNMADD132PSZ128r:
31167 case VFNMADD132PSZ128rk:
31168 case VFNMADD132PSZ128rkz:
31169 case VFNMADD132PSZ256m:
31170 case VFNMADD132PSZ256mb:
31171 case VFNMADD132PSZ256mbk:
31172 case VFNMADD132PSZ256mbkz:
31173 case VFNMADD132PSZ256mk:
31174 case VFNMADD132PSZ256mkz:
31175 case VFNMADD132PSZ256r:
31176 case VFNMADD132PSZ256rk:
31177 case VFNMADD132PSZ256rkz:
31178 case VFNMADD132PSZm:
31179 case VFNMADD132PSZmb:
31180 case VFNMADD132PSZmbk:
31181 case VFNMADD132PSZmbkz:
31182 case VFNMADD132PSZmk:
31183 case VFNMADD132PSZmkz:
31184 case VFNMADD132PSZr:
31185 case VFNMADD132PSZrb:
31186 case VFNMADD132PSZrbk:
31187 case VFNMADD132PSZrbkz:
31188 case VFNMADD132PSZrk:
31189 case VFNMADD132PSZrkz:
31190 case VFNMADD132PSm:
31191 case VFNMADD132PSr:
31192 return true;
31193 }
31194 return false;
31195}
31196
31197bool isMOVNTPS(unsigned Opcode) {
31198 return Opcode == MOVNTPSmr;
31199}
31200
31201bool isVRSQRTSS(unsigned Opcode) {
31202 switch (Opcode) {
31203 case VRSQRTSSm_Int:
31204 case VRSQRTSSr_Int:
31205 return true;
31206 }
31207 return false;
31208}
31209
31210bool isKMOVB(unsigned Opcode) {
31211 switch (Opcode) {
31212 case KMOVBkk:
31213 case KMOVBkk_EVEX:
31214 case KMOVBkm:
31215 case KMOVBkm_EVEX:
31216 case KMOVBkr:
31217 case KMOVBkr_EVEX:
31218 case KMOVBmk:
31219 case KMOVBmk_EVEX:
31220 case KMOVBrk:
31221 case KMOVBrk_EVEX:
31222 return true;
31223 }
31224 return false;
31225}
31226
31227bool isCVTSD2SS(unsigned Opcode) {
31228 switch (Opcode) {
31229 case CVTSD2SSrm_Int:
31230 case CVTSD2SSrr_Int:
31231 return true;
31232 }
31233 return false;
31234}
31235
31236bool isVBROADCASTF64X2(unsigned Opcode) {
31237 switch (Opcode) {
31238 case VBROADCASTF64X2Z256rm:
31239 case VBROADCASTF64X2Z256rmk:
31240 case VBROADCASTF64X2Z256rmkz:
31241 case VBROADCASTF64X2Zrm:
31242 case VBROADCASTF64X2Zrmk:
31243 case VBROADCASTF64X2Zrmkz:
31244 return true;
31245 }
31246 return false;
31247}
31248
31249bool isMOVNTPD(unsigned Opcode) {
31250 return Opcode == MOVNTPDmr;
31251}
31252
31253bool isMAXSD(unsigned Opcode) {
31254 switch (Opcode) {
31255 case MAXSDrm_Int:
31256 case MAXSDrr_Int:
31257 return true;
31258 }
31259 return false;
31260}
31261
31262bool isCMPPD(unsigned Opcode) {
31263 switch (Opcode) {
31264 case CMPPDrmi:
31265 case CMPPDrri:
31266 return true;
31267 }
31268 return false;
31269}
31270
31271bool isVPCMPESTRM(unsigned Opcode) {
31272 switch (Opcode) {
31273 case VPCMPESTRMrmi:
31274 case VPCMPESTRMrri:
31275 return true;
31276 }
31277 return false;
31278}
31279
31280bool isVFMSUB132PS(unsigned Opcode) {
31281 switch (Opcode) {
31282 case VFMSUB132PSYm:
31283 case VFMSUB132PSYr:
31284 case VFMSUB132PSZ128m:
31285 case VFMSUB132PSZ128mb:
31286 case VFMSUB132PSZ128mbk:
31287 case VFMSUB132PSZ128mbkz:
31288 case VFMSUB132PSZ128mk:
31289 case VFMSUB132PSZ128mkz:
31290 case VFMSUB132PSZ128r:
31291 case VFMSUB132PSZ128rk:
31292 case VFMSUB132PSZ128rkz:
31293 case VFMSUB132PSZ256m:
31294 case VFMSUB132PSZ256mb:
31295 case VFMSUB132PSZ256mbk:
31296 case VFMSUB132PSZ256mbkz:
31297 case VFMSUB132PSZ256mk:
31298 case VFMSUB132PSZ256mkz:
31299 case VFMSUB132PSZ256r:
31300 case VFMSUB132PSZ256rk:
31301 case VFMSUB132PSZ256rkz:
31302 case VFMSUB132PSZm:
31303 case VFMSUB132PSZmb:
31304 case VFMSUB132PSZmbk:
31305 case VFMSUB132PSZmbkz:
31306 case VFMSUB132PSZmk:
31307 case VFMSUB132PSZmkz:
31308 case VFMSUB132PSZr:
31309 case VFMSUB132PSZrb:
31310 case VFMSUB132PSZrbk:
31311 case VFMSUB132PSZrbkz:
31312 case VFMSUB132PSZrk:
31313 case VFMSUB132PSZrkz:
31314 case VFMSUB132PSm:
31315 case VFMSUB132PSr:
31316 return true;
31317 }
31318 return false;
31319}
31320
31321bool isVCOMISH(unsigned Opcode) {
31322 switch (Opcode) {
31323 case VCOMISHZrm:
31324 case VCOMISHZrr:
31325 case VCOMISHZrrb:
31326 return true;
31327 }
31328 return false;
31329}
31330
31331bool isF2XM1(unsigned Opcode) {
31332 return Opcode == F2XM1;
31333}
31334
31335bool isVDIVBF16(unsigned Opcode) {
31336 switch (Opcode) {
31337 case VDIVBF16Z128rm:
31338 case VDIVBF16Z128rmb:
31339 case VDIVBF16Z128rmbk:
31340 case VDIVBF16Z128rmbkz:
31341 case VDIVBF16Z128rmk:
31342 case VDIVBF16Z128rmkz:
31343 case VDIVBF16Z128rr:
31344 case VDIVBF16Z128rrk:
31345 case VDIVBF16Z128rrkz:
31346 case VDIVBF16Z256rm:
31347 case VDIVBF16Z256rmb:
31348 case VDIVBF16Z256rmbk:
31349 case VDIVBF16Z256rmbkz:
31350 case VDIVBF16Z256rmk:
31351 case VDIVBF16Z256rmkz:
31352 case VDIVBF16Z256rr:
31353 case VDIVBF16Z256rrk:
31354 case VDIVBF16Z256rrkz:
31355 case VDIVBF16Zrm:
31356 case VDIVBF16Zrmb:
31357 case VDIVBF16Zrmbk:
31358 case VDIVBF16Zrmbkz:
31359 case VDIVBF16Zrmk:
31360 case VDIVBF16Zrmkz:
31361 case VDIVBF16Zrr:
31362 case VDIVBF16Zrrk:
31363 case VDIVBF16Zrrkz:
31364 return true;
31365 }
31366 return false;
31367}
31368
31369bool isSQRTPD(unsigned Opcode) {
31370 switch (Opcode) {
31371 case SQRTPDm:
31372 case SQRTPDr:
31373 return true;
31374 }
31375 return false;
31376}
31377
31378bool isVFMSUBADDPS(unsigned Opcode) {
31379 switch (Opcode) {
31380 case VFMSUBADDPS4Ymr:
31381 case VFMSUBADDPS4Yrm:
31382 case VFMSUBADDPS4Yrr:
31383 case VFMSUBADDPS4Yrr_REV:
31384 case VFMSUBADDPS4mr:
31385 case VFMSUBADDPS4rm:
31386 case VFMSUBADDPS4rr:
31387 case VFMSUBADDPS4rr_REV:
31388 return true;
31389 }
31390 return false;
31391}
31392
31393bool isFXTRACT(unsigned Opcode) {
31394 return Opcode == FXTRACT;
31395}
31396
31397bool isVP4DPWSSD(unsigned Opcode) {
31398 switch (Opcode) {
31399 case VP4DPWSSDrm:
31400 case VP4DPWSSDrmk:
31401 case VP4DPWSSDrmkz:
31402 return true;
31403 }
31404 return false;
31405}
31406
31407bool isTDPBHF8PS(unsigned Opcode) {
31408 return Opcode == TDPBHF8PS;
31409}
31410
31411bool isVFMSUBADDPD(unsigned Opcode) {
31412 switch (Opcode) {
31413 case VFMSUBADDPD4Ymr:
31414 case VFMSUBADDPD4Yrm:
31415 case VFMSUBADDPD4Yrr:
31416 case VFMSUBADDPD4Yrr_REV:
31417 case VFMSUBADDPD4mr:
31418 case VFMSUBADDPD4rm:
31419 case VFMSUBADDPD4rr:
31420 case VFMSUBADDPD4rr_REV:
31421 return true;
31422 }
31423 return false;
31424}
31425
31426bool isVBCSTNEBF162PS(unsigned Opcode) {
31427 switch (Opcode) {
31428 case VBCSTNEBF162PSYrm:
31429 case VBCSTNEBF162PSrm:
31430 return true;
31431 }
31432 return false;
31433}
31434
31435bool isVPGATHERQQ(unsigned Opcode) {
31436 switch (Opcode) {
31437 case VPGATHERQQYrm:
31438 case VPGATHERQQZ128rm:
31439 case VPGATHERQQZ256rm:
31440 case VPGATHERQQZrm:
31441 case VPGATHERQQrm:
31442 return true;
31443 }
31444 return false;
31445}
31446
31447bool isPCMPEQB(unsigned Opcode) {
31448 switch (Opcode) {
31449 case MMX_PCMPEQBrm:
31450 case MMX_PCMPEQBrr:
31451 case PCMPEQBrm:
31452 case PCMPEQBrr:
31453 return true;
31454 }
31455 return false;
31456}
31457
31458bool isTILESTORED(unsigned Opcode) {
31459 switch (Opcode) {
31460 case TILESTORED:
31461 case TILESTORED_EVEX:
31462 return true;
31463 }
31464 return false;
31465}
31466
31467bool isBLSMSK(unsigned Opcode) {
31468 switch (Opcode) {
31469 case BLSMSK32rm:
31470 case BLSMSK32rm_EVEX:
31471 case BLSMSK32rm_NF:
31472 case BLSMSK32rr:
31473 case BLSMSK32rr_EVEX:
31474 case BLSMSK32rr_NF:
31475 case BLSMSK64rm:
31476 case BLSMSK64rm_EVEX:
31477 case BLSMSK64rm_NF:
31478 case BLSMSK64rr:
31479 case BLSMSK64rr_EVEX:
31480 case BLSMSK64rr_NF:
31481 return true;
31482 }
31483 return false;
31484}
31485
31486bool isVCVTTPS2DQ(unsigned Opcode) {
31487 switch (Opcode) {
31488 case VCVTTPS2DQYrm:
31489 case VCVTTPS2DQYrr:
31490 case VCVTTPS2DQZ128rm:
31491 case VCVTTPS2DQZ128rmb:
31492 case VCVTTPS2DQZ128rmbk:
31493 case VCVTTPS2DQZ128rmbkz:
31494 case VCVTTPS2DQZ128rmk:
31495 case VCVTTPS2DQZ128rmkz:
31496 case VCVTTPS2DQZ128rr:
31497 case VCVTTPS2DQZ128rrk:
31498 case VCVTTPS2DQZ128rrkz:
31499 case VCVTTPS2DQZ256rm:
31500 case VCVTTPS2DQZ256rmb:
31501 case VCVTTPS2DQZ256rmbk:
31502 case VCVTTPS2DQZ256rmbkz:
31503 case VCVTTPS2DQZ256rmk:
31504 case VCVTTPS2DQZ256rmkz:
31505 case VCVTTPS2DQZ256rr:
31506 case VCVTTPS2DQZ256rrk:
31507 case VCVTTPS2DQZ256rrkz:
31508 case VCVTTPS2DQZrm:
31509 case VCVTTPS2DQZrmb:
31510 case VCVTTPS2DQZrmbk:
31511 case VCVTTPS2DQZrmbkz:
31512 case VCVTTPS2DQZrmk:
31513 case VCVTTPS2DQZrmkz:
31514 case VCVTTPS2DQZrr:
31515 case VCVTTPS2DQZrrb:
31516 case VCVTTPS2DQZrrbk:
31517 case VCVTTPS2DQZrrbkz:
31518 case VCVTTPS2DQZrrk:
31519 case VCVTTPS2DQZrrkz:
31520 case VCVTTPS2DQrm:
31521 case VCVTTPS2DQrr:
31522 return true;
31523 }
31524 return false;
31525}
31526
31527bool isVRNDSCALEPD(unsigned Opcode) {
31528 switch (Opcode) {
31529 case VRNDSCALEPDZ128rmbi:
31530 case VRNDSCALEPDZ128rmbik:
31531 case VRNDSCALEPDZ128rmbikz:
31532 case VRNDSCALEPDZ128rmi:
31533 case VRNDSCALEPDZ128rmik:
31534 case VRNDSCALEPDZ128rmikz:
31535 case VRNDSCALEPDZ128rri:
31536 case VRNDSCALEPDZ128rrik:
31537 case VRNDSCALEPDZ128rrikz:
31538 case VRNDSCALEPDZ256rmbi:
31539 case VRNDSCALEPDZ256rmbik:
31540 case VRNDSCALEPDZ256rmbikz:
31541 case VRNDSCALEPDZ256rmi:
31542 case VRNDSCALEPDZ256rmik:
31543 case VRNDSCALEPDZ256rmikz:
31544 case VRNDSCALEPDZ256rri:
31545 case VRNDSCALEPDZ256rrik:
31546 case VRNDSCALEPDZ256rrikz:
31547 case VRNDSCALEPDZrmbi:
31548 case VRNDSCALEPDZrmbik:
31549 case VRNDSCALEPDZrmbikz:
31550 case VRNDSCALEPDZrmi:
31551 case VRNDSCALEPDZrmik:
31552 case VRNDSCALEPDZrmikz:
31553 case VRNDSCALEPDZrri:
31554 case VRNDSCALEPDZrrib:
31555 case VRNDSCALEPDZrribk:
31556 case VRNDSCALEPDZrribkz:
31557 case VRNDSCALEPDZrrik:
31558 case VRNDSCALEPDZrrikz:
31559 return true;
31560 }
31561 return false;
31562}
31563
31564bool isVFPCLASSBF16(unsigned Opcode) {
31565 switch (Opcode) {
31566 case VFPCLASSBF16Z128mbi:
31567 case VFPCLASSBF16Z128mbik:
31568 case VFPCLASSBF16Z128mi:
31569 case VFPCLASSBF16Z128mik:
31570 case VFPCLASSBF16Z128ri:
31571 case VFPCLASSBF16Z128rik:
31572 case VFPCLASSBF16Z256mbi:
31573 case VFPCLASSBF16Z256mbik:
31574 case VFPCLASSBF16Z256mi:
31575 case VFPCLASSBF16Z256mik:
31576 case VFPCLASSBF16Z256ri:
31577 case VFPCLASSBF16Z256rik:
31578 case VFPCLASSBF16Zmbi:
31579 case VFPCLASSBF16Zmbik:
31580 case VFPCLASSBF16Zmi:
31581 case VFPCLASSBF16Zmik:
31582 case VFPCLASSBF16Zri:
31583 case VFPCLASSBF16Zrik:
31584 return true;
31585 }
31586 return false;
31587}
31588
31589bool isVMLOAD(unsigned Opcode) {
31590 switch (Opcode) {
31591 case VMLOAD32:
31592 case VMLOAD64:
31593 return true;
31594 }
31595 return false;
31596}
31597
31598bool isVPTERNLOGQ(unsigned Opcode) {
31599 switch (Opcode) {
31600 case VPTERNLOGQZ128rmbi:
31601 case VPTERNLOGQZ128rmbik:
31602 case VPTERNLOGQZ128rmbikz:
31603 case VPTERNLOGQZ128rmi:
31604 case VPTERNLOGQZ128rmik:
31605 case VPTERNLOGQZ128rmikz:
31606 case VPTERNLOGQZ128rri:
31607 case VPTERNLOGQZ128rrik:
31608 case VPTERNLOGQZ128rrikz:
31609 case VPTERNLOGQZ256rmbi:
31610 case VPTERNLOGQZ256rmbik:
31611 case VPTERNLOGQZ256rmbikz:
31612 case VPTERNLOGQZ256rmi:
31613 case VPTERNLOGQZ256rmik:
31614 case VPTERNLOGQZ256rmikz:
31615 case VPTERNLOGQZ256rri:
31616 case VPTERNLOGQZ256rrik:
31617 case VPTERNLOGQZ256rrikz:
31618 case VPTERNLOGQZrmbi:
31619 case VPTERNLOGQZrmbik:
31620 case VPTERNLOGQZrmbikz:
31621 case VPTERNLOGQZrmi:
31622 case VPTERNLOGQZrmik:
31623 case VPTERNLOGQZrmikz:
31624 case VPTERNLOGQZrri:
31625 case VPTERNLOGQZrrik:
31626 case VPTERNLOGQZrrikz:
31627 return true;
31628 }
31629 return false;
31630}
31631
31632bool isKXNORD(unsigned Opcode) {
31633 return Opcode == KXNORDkk;
31634}
31635
31636bool isFXSAVE(unsigned Opcode) {
31637 return Opcode == FXSAVE;
31638}
31639
31640bool isVUNPCKHPD(unsigned Opcode) {
31641 switch (Opcode) {
31642 case VUNPCKHPDYrm:
31643 case VUNPCKHPDYrr:
31644 case VUNPCKHPDZ128rm:
31645 case VUNPCKHPDZ128rmb:
31646 case VUNPCKHPDZ128rmbk:
31647 case VUNPCKHPDZ128rmbkz:
31648 case VUNPCKHPDZ128rmk:
31649 case VUNPCKHPDZ128rmkz:
31650 case VUNPCKHPDZ128rr:
31651 case VUNPCKHPDZ128rrk:
31652 case VUNPCKHPDZ128rrkz:
31653 case VUNPCKHPDZ256rm:
31654 case VUNPCKHPDZ256rmb:
31655 case VUNPCKHPDZ256rmbk:
31656 case VUNPCKHPDZ256rmbkz:
31657 case VUNPCKHPDZ256rmk:
31658 case VUNPCKHPDZ256rmkz:
31659 case VUNPCKHPDZ256rr:
31660 case VUNPCKHPDZ256rrk:
31661 case VUNPCKHPDZ256rrkz:
31662 case VUNPCKHPDZrm:
31663 case VUNPCKHPDZrmb:
31664 case VUNPCKHPDZrmbk:
31665 case VUNPCKHPDZrmbkz:
31666 case VUNPCKHPDZrmk:
31667 case VUNPCKHPDZrmkz:
31668 case VUNPCKHPDZrr:
31669 case VUNPCKHPDZrrk:
31670 case VUNPCKHPDZrrkz:
31671 case VUNPCKHPDrm:
31672 case VUNPCKHPDrr:
31673 return true;
31674 }
31675 return false;
31676}
31677
31678bool isCVTPS2DQ(unsigned Opcode) {
31679 switch (Opcode) {
31680 case CVTPS2DQrm:
31681 case CVTPS2DQrr:
31682 return true;
31683 }
31684 return false;
31685}
31686
31687bool isTMMULTF32PS(unsigned Opcode) {
31688 return Opcode == TMMULTF32PS;
31689}
31690
31691bool isVFMSUB213SS(unsigned Opcode) {
31692 switch (Opcode) {
31693 case VFMSUB213SSZm_Int:
31694 case VFMSUB213SSZmk_Int:
31695 case VFMSUB213SSZmkz_Int:
31696 case VFMSUB213SSZr_Int:
31697 case VFMSUB213SSZrb_Int:
31698 case VFMSUB213SSZrbk_Int:
31699 case VFMSUB213SSZrbkz_Int:
31700 case VFMSUB213SSZrk_Int:
31701 case VFMSUB213SSZrkz_Int:
31702 case VFMSUB213SSm_Int:
31703 case VFMSUB213SSr_Int:
31704 return true;
31705 }
31706 return false;
31707}
31708
31709bool isVPOPCNTD(unsigned Opcode) {
31710 switch (Opcode) {
31711 case VPOPCNTDZ128rm:
31712 case VPOPCNTDZ128rmb:
31713 case VPOPCNTDZ128rmbk:
31714 case VPOPCNTDZ128rmbkz:
31715 case VPOPCNTDZ128rmk:
31716 case VPOPCNTDZ128rmkz:
31717 case VPOPCNTDZ128rr:
31718 case VPOPCNTDZ128rrk:
31719 case VPOPCNTDZ128rrkz:
31720 case VPOPCNTDZ256rm:
31721 case VPOPCNTDZ256rmb:
31722 case VPOPCNTDZ256rmbk:
31723 case VPOPCNTDZ256rmbkz:
31724 case VPOPCNTDZ256rmk:
31725 case VPOPCNTDZ256rmkz:
31726 case VPOPCNTDZ256rr:
31727 case VPOPCNTDZ256rrk:
31728 case VPOPCNTDZ256rrkz:
31729 case VPOPCNTDZrm:
31730 case VPOPCNTDZrmb:
31731 case VPOPCNTDZrmbk:
31732 case VPOPCNTDZrmbkz:
31733 case VPOPCNTDZrmk:
31734 case VPOPCNTDZrmkz:
31735 case VPOPCNTDZrr:
31736 case VPOPCNTDZrrk:
31737 case VPOPCNTDZrrkz:
31738 return true;
31739 }
31740 return false;
31741}
31742
31743bool isSALC(unsigned Opcode) {
31744 return Opcode == SALC;
31745}
31746
31747bool isV4FNMADDSS(unsigned Opcode) {
31748 switch (Opcode) {
31749 case V4FNMADDSSrm:
31750 case V4FNMADDSSrmk:
31751 case V4FNMADDSSrmkz:
31752 return true;
31753 }
31754 return false;
31755}
31756
31757bool isXCRYPTOFB(unsigned Opcode) {
31758 return Opcode == XCRYPTOFB;
31759}
31760
31761bool isVORPD(unsigned Opcode) {
31762 switch (Opcode) {
31763 case VORPDYrm:
31764 case VORPDYrr:
31765 case VORPDZ128rm:
31766 case VORPDZ128rmb:
31767 case VORPDZ128rmbk:
31768 case VORPDZ128rmbkz:
31769 case VORPDZ128rmk:
31770 case VORPDZ128rmkz:
31771 case VORPDZ128rr:
31772 case VORPDZ128rrk:
31773 case VORPDZ128rrkz:
31774 case VORPDZ256rm:
31775 case VORPDZ256rmb:
31776 case VORPDZ256rmbk:
31777 case VORPDZ256rmbkz:
31778 case VORPDZ256rmk:
31779 case VORPDZ256rmkz:
31780 case VORPDZ256rr:
31781 case VORPDZ256rrk:
31782 case VORPDZ256rrkz:
31783 case VORPDZrm:
31784 case VORPDZrmb:
31785 case VORPDZrmbk:
31786 case VORPDZrmbkz:
31787 case VORPDZrmk:
31788 case VORPDZrmkz:
31789 case VORPDZrr:
31790 case VORPDZrrk:
31791 case VORPDZrrkz:
31792 case VORPDrm:
31793 case VORPDrr:
31794 return true;
31795 }
31796 return false;
31797}
31798
31799bool isLSL(unsigned Opcode) {
31800 switch (Opcode) {
31801 case LSL16rm:
31802 case LSL16rr:
31803 case LSL32rm:
31804 case LSL32rr:
31805 case LSL64rm:
31806 case LSL64rr:
31807 return true;
31808 }
31809 return false;
31810}
31811
31812bool isXCRYPTCFB(unsigned Opcode) {
31813 return Opcode == XCRYPTCFB;
31814}
31815
31816bool isVGETEXPSS(unsigned Opcode) {
31817 switch (Opcode) {
31818 case VGETEXPSSZm:
31819 case VGETEXPSSZmk:
31820 case VGETEXPSSZmkz:
31821 case VGETEXPSSZr:
31822 case VGETEXPSSZrb:
31823 case VGETEXPSSZrbk:
31824 case VGETEXPSSZrbkz:
31825 case VGETEXPSSZrk:
31826 case VGETEXPSSZrkz:
31827 return true;
31828 }
31829 return false;
31830}
31831
31832bool isPSLLDQ(unsigned Opcode) {
31833 return Opcode == PSLLDQri;
31834}
31835
31836bool isVPDPBUUD(unsigned Opcode) {
31837 switch (Opcode) {
31838 case VPDPBUUDYrm:
31839 case VPDPBUUDYrr:
31840 case VPDPBUUDZ128m:
31841 case VPDPBUUDZ128mb:
31842 case VPDPBUUDZ128mbk:
31843 case VPDPBUUDZ128mbkz:
31844 case VPDPBUUDZ128mk:
31845 case VPDPBUUDZ128mkz:
31846 case VPDPBUUDZ128r:
31847 case VPDPBUUDZ128rk:
31848 case VPDPBUUDZ128rkz:
31849 case VPDPBUUDZ256m:
31850 case VPDPBUUDZ256mb:
31851 case VPDPBUUDZ256mbk:
31852 case VPDPBUUDZ256mbkz:
31853 case VPDPBUUDZ256mk:
31854 case VPDPBUUDZ256mkz:
31855 case VPDPBUUDZ256r:
31856 case VPDPBUUDZ256rk:
31857 case VPDPBUUDZ256rkz:
31858 case VPDPBUUDZm:
31859 case VPDPBUUDZmb:
31860 case VPDPBUUDZmbk:
31861 case VPDPBUUDZmbkz:
31862 case VPDPBUUDZmk:
31863 case VPDPBUUDZmkz:
31864 case VPDPBUUDZr:
31865 case VPDPBUUDZrk:
31866 case VPDPBUUDZrkz:
31867 case VPDPBUUDrm:
31868 case VPDPBUUDrr:
31869 return true;
31870 }
31871 return false;
31872}
31873
31874bool isVMXOFF(unsigned Opcode) {
31875 return Opcode == VMXOFF;
31876}
31877
31878bool isBLSIC(unsigned Opcode) {
31879 switch (Opcode) {
31880 case BLSIC32rm:
31881 case BLSIC32rr:
31882 case BLSIC64rm:
31883 case BLSIC64rr:
31884 return true;
31885 }
31886 return false;
31887}
31888
31889bool isMOVLHPS(unsigned Opcode) {
31890 return Opcode == MOVLHPSrr;
31891}
31892
31893bool isVMOVRSQ(unsigned Opcode) {
31894 switch (Opcode) {
31895 case VMOVRSQZ128m:
31896 case VMOVRSQZ128mk:
31897 case VMOVRSQZ128mkz:
31898 case VMOVRSQZ256m:
31899 case VMOVRSQZ256mk:
31900 case VMOVRSQZ256mkz:
31901 case VMOVRSQZm:
31902 case VMOVRSQZmk:
31903 case VMOVRSQZmkz:
31904 return true;
31905 }
31906 return false;
31907}
31908
31909bool isVFNMSUBSD(unsigned Opcode) {
31910 switch (Opcode) {
31911 case VFNMSUBSD4mr:
31912 case VFNMSUBSD4rm:
31913 case VFNMSUBSD4rr:
31914 case VFNMSUBSD4rr_REV:
31915 return true;
31916 }
31917 return false;
31918}
31919
31920bool isVCVTPH2IUBS(unsigned Opcode) {
31921 switch (Opcode) {
31922 case VCVTPH2IUBSZ128rm:
31923 case VCVTPH2IUBSZ128rmb:
31924 case VCVTPH2IUBSZ128rmbk:
31925 case VCVTPH2IUBSZ128rmbkz:
31926 case VCVTPH2IUBSZ128rmk:
31927 case VCVTPH2IUBSZ128rmkz:
31928 case VCVTPH2IUBSZ128rr:
31929 case VCVTPH2IUBSZ128rrk:
31930 case VCVTPH2IUBSZ128rrkz:
31931 case VCVTPH2IUBSZ256rm:
31932 case VCVTPH2IUBSZ256rmb:
31933 case VCVTPH2IUBSZ256rmbk:
31934 case VCVTPH2IUBSZ256rmbkz:
31935 case VCVTPH2IUBSZ256rmk:
31936 case VCVTPH2IUBSZ256rmkz:
31937 case VCVTPH2IUBSZ256rr:
31938 case VCVTPH2IUBSZ256rrk:
31939 case VCVTPH2IUBSZ256rrkz:
31940 case VCVTPH2IUBSZrm:
31941 case VCVTPH2IUBSZrmb:
31942 case VCVTPH2IUBSZrmbk:
31943 case VCVTPH2IUBSZrmbkz:
31944 case VCVTPH2IUBSZrmk:
31945 case VCVTPH2IUBSZrmkz:
31946 case VCVTPH2IUBSZrr:
31947 case VCVTPH2IUBSZrrb:
31948 case VCVTPH2IUBSZrrbk:
31949 case VCVTPH2IUBSZrrbkz:
31950 case VCVTPH2IUBSZrrk:
31951 case VCVTPH2IUBSZrrkz:
31952 return true;
31953 }
31954 return false;
31955}
31956
31957bool isVFPCLASSSH(unsigned Opcode) {
31958 switch (Opcode) {
31959 case VFPCLASSSHZmi:
31960 case VFPCLASSSHZmik:
31961 case VFPCLASSSHZri:
31962 case VFPCLASSSHZrik:
31963 return true;
31964 }
31965 return false;
31966}
31967
31968bool isVPSHLQ(unsigned Opcode) {
31969 switch (Opcode) {
31970 case VPSHLQmr:
31971 case VPSHLQrm:
31972 case VPSHLQrr:
31973 case VPSHLQrr_REV:
31974 return true;
31975 }
31976 return false;
31977}
31978
31979bool isVROUNDPS(unsigned Opcode) {
31980 switch (Opcode) {
31981 case VROUNDPSYmi:
31982 case VROUNDPSYri:
31983 case VROUNDPSmi:
31984 case VROUNDPSri:
31985 return true;
31986 }
31987 return false;
31988}
31989
31990bool isVSCATTERPF0QPS(unsigned Opcode) {
31991 return Opcode == VSCATTERPF0QPSm;
31992}
31993
31994bool isERETS(unsigned Opcode) {
31995 return Opcode == ERETS;
31996}
31997
31998bool isVPERMI2D(unsigned Opcode) {
31999 switch (Opcode) {
32000 case VPERMI2DZ128rm:
32001 case VPERMI2DZ128rmb:
32002 case VPERMI2DZ128rmbk:
32003 case VPERMI2DZ128rmbkz:
32004 case VPERMI2DZ128rmk:
32005 case VPERMI2DZ128rmkz:
32006 case VPERMI2DZ128rr:
32007 case VPERMI2DZ128rrk:
32008 case VPERMI2DZ128rrkz:
32009 case VPERMI2DZ256rm:
32010 case VPERMI2DZ256rmb:
32011 case VPERMI2DZ256rmbk:
32012 case VPERMI2DZ256rmbkz:
32013 case VPERMI2DZ256rmk:
32014 case VPERMI2DZ256rmkz:
32015 case VPERMI2DZ256rr:
32016 case VPERMI2DZ256rrk:
32017 case VPERMI2DZ256rrkz:
32018 case VPERMI2DZrm:
32019 case VPERMI2DZrmb:
32020 case VPERMI2DZrmbk:
32021 case VPERMI2DZrmbkz:
32022 case VPERMI2DZrmk:
32023 case VPERMI2DZrmkz:
32024 case VPERMI2DZrr:
32025 case VPERMI2DZrrk:
32026 case VPERMI2DZrrkz:
32027 return true;
32028 }
32029 return false;
32030}
32031
32032bool isFUCOMP(unsigned Opcode) {
32033 return Opcode == UCOM_FPr;
32034}
32035
32036bool isVCVTTPS2QQ(unsigned Opcode) {
32037 switch (Opcode) {
32038 case VCVTTPS2QQZ128rm:
32039 case VCVTTPS2QQZ128rmb:
32040 case VCVTTPS2QQZ128rmbk:
32041 case VCVTTPS2QQZ128rmbkz:
32042 case VCVTTPS2QQZ128rmk:
32043 case VCVTTPS2QQZ128rmkz:
32044 case VCVTTPS2QQZ128rr:
32045 case VCVTTPS2QQZ128rrk:
32046 case VCVTTPS2QQZ128rrkz:
32047 case VCVTTPS2QQZ256rm:
32048 case VCVTTPS2QQZ256rmb:
32049 case VCVTTPS2QQZ256rmbk:
32050 case VCVTTPS2QQZ256rmbkz:
32051 case VCVTTPS2QQZ256rmk:
32052 case VCVTTPS2QQZ256rmkz:
32053 case VCVTTPS2QQZ256rr:
32054 case VCVTTPS2QQZ256rrk:
32055 case VCVTTPS2QQZ256rrkz:
32056 case VCVTTPS2QQZrm:
32057 case VCVTTPS2QQZrmb:
32058 case VCVTTPS2QQZrmbk:
32059 case VCVTTPS2QQZrmbkz:
32060 case VCVTTPS2QQZrmk:
32061 case VCVTTPS2QQZrmkz:
32062 case VCVTTPS2QQZrr:
32063 case VCVTTPS2QQZrrb:
32064 case VCVTTPS2QQZrrbk:
32065 case VCVTTPS2QQZrrbkz:
32066 case VCVTTPS2QQZrrk:
32067 case VCVTTPS2QQZrrkz:
32068 return true;
32069 }
32070 return false;
32071}
32072
32073bool isPUSHFD(unsigned Opcode) {
32074 return Opcode == PUSHF32;
32075}
32076
32077bool isKORB(unsigned Opcode) {
32078 return Opcode == KORBkk;
32079}
32080
32081bool isVRCP28PD(unsigned Opcode) {
32082 switch (Opcode) {
32083 case VRCP28PDZm:
32084 case VRCP28PDZmb:
32085 case VRCP28PDZmbk:
32086 case VRCP28PDZmbkz:
32087 case VRCP28PDZmk:
32088 case VRCP28PDZmkz:
32089 case VRCP28PDZr:
32090 case VRCP28PDZrb:
32091 case VRCP28PDZrbk:
32092 case VRCP28PDZrbkz:
32093 case VRCP28PDZrk:
32094 case VRCP28PDZrkz:
32095 return true;
32096 }
32097 return false;
32098}
32099
32100bool isVPABSD(unsigned Opcode) {
32101 switch (Opcode) {
32102 case VPABSDYrm:
32103 case VPABSDYrr:
32104 case VPABSDZ128rm:
32105 case VPABSDZ128rmb:
32106 case VPABSDZ128rmbk:
32107 case VPABSDZ128rmbkz:
32108 case VPABSDZ128rmk:
32109 case VPABSDZ128rmkz:
32110 case VPABSDZ128rr:
32111 case VPABSDZ128rrk:
32112 case VPABSDZ128rrkz:
32113 case VPABSDZ256rm:
32114 case VPABSDZ256rmb:
32115 case VPABSDZ256rmbk:
32116 case VPABSDZ256rmbkz:
32117 case VPABSDZ256rmk:
32118 case VPABSDZ256rmkz:
32119 case VPABSDZ256rr:
32120 case VPABSDZ256rrk:
32121 case VPABSDZ256rrkz:
32122 case VPABSDZrm:
32123 case VPABSDZrmb:
32124 case VPABSDZrmbk:
32125 case VPABSDZrmbkz:
32126 case VPABSDZrmk:
32127 case VPABSDZrmkz:
32128 case VPABSDZrr:
32129 case VPABSDZrrk:
32130 case VPABSDZrrkz:
32131 case VPABSDrm:
32132 case VPABSDrr:
32133 return true;
32134 }
32135 return false;
32136}
32137
32138bool isVROUNDSS(unsigned Opcode) {
32139 switch (Opcode) {
32140 case VROUNDSSmi_Int:
32141 case VROUNDSSri_Int:
32142 return true;
32143 }
32144 return false;
32145}
32146
32147bool isVCVTSD2USI(unsigned Opcode) {
32148 switch (Opcode) {
32149 case VCVTSD2USI64Zrm_Int:
32150 case VCVTSD2USI64Zrr_Int:
32151 case VCVTSD2USI64Zrrb_Int:
32152 case VCVTSD2USIZrm_Int:
32153 case VCVTSD2USIZrr_Int:
32154 case VCVTSD2USIZrrb_Int:
32155 return true;
32156 }
32157 return false;
32158}
32159
32160bool isVPABSB(unsigned Opcode) {
32161 switch (Opcode) {
32162 case VPABSBYrm:
32163 case VPABSBYrr:
32164 case VPABSBZ128rm:
32165 case VPABSBZ128rmk:
32166 case VPABSBZ128rmkz:
32167 case VPABSBZ128rr:
32168 case VPABSBZ128rrk:
32169 case VPABSBZ128rrkz:
32170 case VPABSBZ256rm:
32171 case VPABSBZ256rmk:
32172 case VPABSBZ256rmkz:
32173 case VPABSBZ256rr:
32174 case VPABSBZ256rrk:
32175 case VPABSBZ256rrkz:
32176 case VPABSBZrm:
32177 case VPABSBZrmk:
32178 case VPABSBZrmkz:
32179 case VPABSBZrr:
32180 case VPABSBZrrk:
32181 case VPABSBZrrkz:
32182 case VPABSBrm:
32183 case VPABSBrr:
32184 return true;
32185 }
32186 return false;
32187}
32188
32189bool isPMAXUD(unsigned Opcode) {
32190 switch (Opcode) {
32191 case PMAXUDrm:
32192 case PMAXUDrr:
32193 return true;
32194 }
32195 return false;
32196}
32197
32198bool isVPMULHUW(unsigned Opcode) {
32199 switch (Opcode) {
32200 case VPMULHUWYrm:
32201 case VPMULHUWYrr:
32202 case VPMULHUWZ128rm:
32203 case VPMULHUWZ128rmk:
32204 case VPMULHUWZ128rmkz:
32205 case VPMULHUWZ128rr:
32206 case VPMULHUWZ128rrk:
32207 case VPMULHUWZ128rrkz:
32208 case VPMULHUWZ256rm:
32209 case VPMULHUWZ256rmk:
32210 case VPMULHUWZ256rmkz:
32211 case VPMULHUWZ256rr:
32212 case VPMULHUWZ256rrk:
32213 case VPMULHUWZ256rrkz:
32214 case VPMULHUWZrm:
32215 case VPMULHUWZrmk:
32216 case VPMULHUWZrmkz:
32217 case VPMULHUWZrr:
32218 case VPMULHUWZrrk:
32219 case VPMULHUWZrrkz:
32220 case VPMULHUWrm:
32221 case VPMULHUWrr:
32222 return true;
32223 }
32224 return false;
32225}
32226
32227bool isVPERMPD(unsigned Opcode) {
32228 switch (Opcode) {
32229 case VPERMPDYmi:
32230 case VPERMPDYri:
32231 case VPERMPDZ256mbi:
32232 case VPERMPDZ256mbik:
32233 case VPERMPDZ256mbikz:
32234 case VPERMPDZ256mi:
32235 case VPERMPDZ256mik:
32236 case VPERMPDZ256mikz:
32237 case VPERMPDZ256ri:
32238 case VPERMPDZ256rik:
32239 case VPERMPDZ256rikz:
32240 case VPERMPDZ256rm:
32241 case VPERMPDZ256rmb:
32242 case VPERMPDZ256rmbk:
32243 case VPERMPDZ256rmbkz:
32244 case VPERMPDZ256rmk:
32245 case VPERMPDZ256rmkz:
32246 case VPERMPDZ256rr:
32247 case VPERMPDZ256rrk:
32248 case VPERMPDZ256rrkz:
32249 case VPERMPDZmbi:
32250 case VPERMPDZmbik:
32251 case VPERMPDZmbikz:
32252 case VPERMPDZmi:
32253 case VPERMPDZmik:
32254 case VPERMPDZmikz:
32255 case VPERMPDZri:
32256 case VPERMPDZrik:
32257 case VPERMPDZrikz:
32258 case VPERMPDZrm:
32259 case VPERMPDZrmb:
32260 case VPERMPDZrmbk:
32261 case VPERMPDZrmbkz:
32262 case VPERMPDZrmk:
32263 case VPERMPDZrmkz:
32264 case VPERMPDZrr:
32265 case VPERMPDZrrk:
32266 case VPERMPDZrrkz:
32267 return true;
32268 }
32269 return false;
32270}
32271
32272bool isFCHS(unsigned Opcode) {
32273 return Opcode == CHS_F;
32274}
32275
32276bool isVPBLENDMB(unsigned Opcode) {
32277 switch (Opcode) {
32278 case VPBLENDMBZ128rm:
32279 case VPBLENDMBZ128rmk:
32280 case VPBLENDMBZ128rmkz:
32281 case VPBLENDMBZ128rr:
32282 case VPBLENDMBZ128rrk:
32283 case VPBLENDMBZ128rrkz:
32284 case VPBLENDMBZ256rm:
32285 case VPBLENDMBZ256rmk:
32286 case VPBLENDMBZ256rmkz:
32287 case VPBLENDMBZ256rr:
32288 case VPBLENDMBZ256rrk:
32289 case VPBLENDMBZ256rrkz:
32290 case VPBLENDMBZrm:
32291 case VPBLENDMBZrmk:
32292 case VPBLENDMBZrmkz:
32293 case VPBLENDMBZrr:
32294 case VPBLENDMBZrrk:
32295 case VPBLENDMBZrrkz:
32296 return true;
32297 }
32298 return false;
32299}
32300
32301bool isVGETMANTSS(unsigned Opcode) {
32302 switch (Opcode) {
32303 case VGETMANTSSZrmi:
32304 case VGETMANTSSZrmik:
32305 case VGETMANTSSZrmikz:
32306 case VGETMANTSSZrri:
32307 case VGETMANTSSZrrib:
32308 case VGETMANTSSZrribk:
32309 case VGETMANTSSZrribkz:
32310 case VGETMANTSSZrrik:
32311 case VGETMANTSSZrrikz:
32312 return true;
32313 }
32314 return false;
32315}
32316
32317bool isVPSLLW(unsigned Opcode) {
32318 switch (Opcode) {
32319 case VPSLLWYri:
32320 case VPSLLWYrm:
32321 case VPSLLWYrr:
32322 case VPSLLWZ128mi:
32323 case VPSLLWZ128mik:
32324 case VPSLLWZ128mikz:
32325 case VPSLLWZ128ri:
32326 case VPSLLWZ128rik:
32327 case VPSLLWZ128rikz:
32328 case VPSLLWZ128rm:
32329 case VPSLLWZ128rmk:
32330 case VPSLLWZ128rmkz:
32331 case VPSLLWZ128rr:
32332 case VPSLLWZ128rrk:
32333 case VPSLLWZ128rrkz:
32334 case VPSLLWZ256mi:
32335 case VPSLLWZ256mik:
32336 case VPSLLWZ256mikz:
32337 case VPSLLWZ256ri:
32338 case VPSLLWZ256rik:
32339 case VPSLLWZ256rikz:
32340 case VPSLLWZ256rm:
32341 case VPSLLWZ256rmk:
32342 case VPSLLWZ256rmkz:
32343 case VPSLLWZ256rr:
32344 case VPSLLWZ256rrk:
32345 case VPSLLWZ256rrkz:
32346 case VPSLLWZmi:
32347 case VPSLLWZmik:
32348 case VPSLLWZmikz:
32349 case VPSLLWZri:
32350 case VPSLLWZrik:
32351 case VPSLLWZrikz:
32352 case VPSLLWZrm:
32353 case VPSLLWZrmk:
32354 case VPSLLWZrmkz:
32355 case VPSLLWZrr:
32356 case VPSLLWZrrk:
32357 case VPSLLWZrrkz:
32358 case VPSLLWri:
32359 case VPSLLWrm:
32360 case VPSLLWrr:
32361 return true;
32362 }
32363 return false;
32364}
32365
32366bool isVDIVPD(unsigned Opcode) {
32367 switch (Opcode) {
32368 case VDIVPDYrm:
32369 case VDIVPDYrr:
32370 case VDIVPDZ128rm:
32371 case VDIVPDZ128rmb:
32372 case VDIVPDZ128rmbk:
32373 case VDIVPDZ128rmbkz:
32374 case VDIVPDZ128rmk:
32375 case VDIVPDZ128rmkz:
32376 case VDIVPDZ128rr:
32377 case VDIVPDZ128rrk:
32378 case VDIVPDZ128rrkz:
32379 case VDIVPDZ256rm:
32380 case VDIVPDZ256rmb:
32381 case VDIVPDZ256rmbk:
32382 case VDIVPDZ256rmbkz:
32383 case VDIVPDZ256rmk:
32384 case VDIVPDZ256rmkz:
32385 case VDIVPDZ256rr:
32386 case VDIVPDZ256rrk:
32387 case VDIVPDZ256rrkz:
32388 case VDIVPDZrm:
32389 case VDIVPDZrmb:
32390 case VDIVPDZrmbk:
32391 case VDIVPDZrmbkz:
32392 case VDIVPDZrmk:
32393 case VDIVPDZrmkz:
32394 case VDIVPDZrr:
32395 case VDIVPDZrrb:
32396 case VDIVPDZrrbk:
32397 case VDIVPDZrrbkz:
32398 case VDIVPDZrrk:
32399 case VDIVPDZrrkz:
32400 case VDIVPDrm:
32401 case VDIVPDrr:
32402 return true;
32403 }
32404 return false;
32405}
32406
32407bool isBLCMSK(unsigned Opcode) {
32408 switch (Opcode) {
32409 case BLCMSK32rm:
32410 case BLCMSK32rr:
32411 case BLCMSK64rm:
32412 case BLCMSK64rr:
32413 return true;
32414 }
32415 return false;
32416}
32417
32418bool isFDIV(unsigned Opcode) {
32419 switch (Opcode) {
32420 case DIV_F32m:
32421 case DIV_F64m:
32422 case DIV_FST0r:
32423 case DIV_FrST0:
32424 return true;
32425 }
32426 return false;
32427}
32428
32429bool isRSQRTSS(unsigned Opcode) {
32430 switch (Opcode) {
32431 case RSQRTSSm_Int:
32432 case RSQRTSSr_Int:
32433 return true;
32434 }
32435 return false;
32436}
32437
32438bool isPOR(unsigned Opcode) {
32439 switch (Opcode) {
32440 case MMX_PORrm:
32441 case MMX_PORrr:
32442 case PORrm:
32443 case PORrr:
32444 return true;
32445 }
32446 return false;
32447}
32448
32449bool isVMOVDQA32(unsigned Opcode) {
32450 switch (Opcode) {
32451 case VMOVDQA32Z128mr:
32452 case VMOVDQA32Z128mrk:
32453 case VMOVDQA32Z128rm:
32454 case VMOVDQA32Z128rmk:
32455 case VMOVDQA32Z128rmkz:
32456 case VMOVDQA32Z128rr:
32457 case VMOVDQA32Z128rr_REV:
32458 case VMOVDQA32Z128rrk:
32459 case VMOVDQA32Z128rrk_REV:
32460 case VMOVDQA32Z128rrkz:
32461 case VMOVDQA32Z128rrkz_REV:
32462 case VMOVDQA32Z256mr:
32463 case VMOVDQA32Z256mrk:
32464 case VMOVDQA32Z256rm:
32465 case VMOVDQA32Z256rmk:
32466 case VMOVDQA32Z256rmkz:
32467 case VMOVDQA32Z256rr:
32468 case VMOVDQA32Z256rr_REV:
32469 case VMOVDQA32Z256rrk:
32470 case VMOVDQA32Z256rrk_REV:
32471 case VMOVDQA32Z256rrkz:
32472 case VMOVDQA32Z256rrkz_REV:
32473 case VMOVDQA32Zmr:
32474 case VMOVDQA32Zmrk:
32475 case VMOVDQA32Zrm:
32476 case VMOVDQA32Zrmk:
32477 case VMOVDQA32Zrmkz:
32478 case VMOVDQA32Zrr:
32479 case VMOVDQA32Zrr_REV:
32480 case VMOVDQA32Zrrk:
32481 case VMOVDQA32Zrrk_REV:
32482 case VMOVDQA32Zrrkz:
32483 case VMOVDQA32Zrrkz_REV:
32484 return true;
32485 }
32486 return false;
32487}
32488
32489bool isVPHADDUWQ(unsigned Opcode) {
32490 switch (Opcode) {
32491 case VPHADDUWQrm:
32492 case VPHADDUWQrr:
32493 return true;
32494 }
32495 return false;
32496}
32497
32498bool isPSRAD(unsigned Opcode) {
32499 switch (Opcode) {
32500 case MMX_PSRADri:
32501 case MMX_PSRADrm:
32502 case MMX_PSRADrr:
32503 case PSRADri:
32504 case PSRADrm:
32505 case PSRADrr:
32506 return true;
32507 }
32508 return false;
32509}
32510
32511bool isPREFETCHW(unsigned Opcode) {
32512 return Opcode == PREFETCHW;
32513}
32514
32515bool isFIDIVR(unsigned Opcode) {
32516 switch (Opcode) {
32517 case DIVR_FI16m:
32518 case DIVR_FI32m:
32519 return true;
32520 }
32521 return false;
32522}
32523
32524bool isMOVHPS(unsigned Opcode) {
32525 switch (Opcode) {
32526 case MOVHPSmr:
32527 case MOVHPSrm:
32528 return true;
32529 }
32530 return false;
32531}
32532
32533bool isVFNMSUB231PH(unsigned Opcode) {
32534 switch (Opcode) {
32535 case VFNMSUB231PHZ128m:
32536 case VFNMSUB231PHZ128mb:
32537 case VFNMSUB231PHZ128mbk:
32538 case VFNMSUB231PHZ128mbkz:
32539 case VFNMSUB231PHZ128mk:
32540 case VFNMSUB231PHZ128mkz:
32541 case VFNMSUB231PHZ128r:
32542 case VFNMSUB231PHZ128rk:
32543 case VFNMSUB231PHZ128rkz:
32544 case VFNMSUB231PHZ256m:
32545 case VFNMSUB231PHZ256mb:
32546 case VFNMSUB231PHZ256mbk:
32547 case VFNMSUB231PHZ256mbkz:
32548 case VFNMSUB231PHZ256mk:
32549 case VFNMSUB231PHZ256mkz:
32550 case VFNMSUB231PHZ256r:
32551 case VFNMSUB231PHZ256rk:
32552 case VFNMSUB231PHZ256rkz:
32553 case VFNMSUB231PHZm:
32554 case VFNMSUB231PHZmb:
32555 case VFNMSUB231PHZmbk:
32556 case VFNMSUB231PHZmbkz:
32557 case VFNMSUB231PHZmk:
32558 case VFNMSUB231PHZmkz:
32559 case VFNMSUB231PHZr:
32560 case VFNMSUB231PHZrb:
32561 case VFNMSUB231PHZrbk:
32562 case VFNMSUB231PHZrbkz:
32563 case VFNMSUB231PHZrk:
32564 case VFNMSUB231PHZrkz:
32565 return true;
32566 }
32567 return false;
32568}
32569
32570bool isUNPCKLPS(unsigned Opcode) {
32571 switch (Opcode) {
32572 case UNPCKLPSrm:
32573 case UNPCKLPSrr:
32574 return true;
32575 }
32576 return false;
32577}
32578
32579bool isVPSIGNB(unsigned Opcode) {
32580 switch (Opcode) {
32581 case VPSIGNBYrm:
32582 case VPSIGNBYrr:
32583 case VPSIGNBrm:
32584 case VPSIGNBrr:
32585 return true;
32586 }
32587 return false;
32588}
32589
32590bool isSAVEPREVSSP(unsigned Opcode) {
32591 return Opcode == SAVEPREVSSP;
32592}
32593
32594bool isVSCALEFSD(unsigned Opcode) {
32595 switch (Opcode) {
32596 case VSCALEFSDZrm:
32597 case VSCALEFSDZrmk:
32598 case VSCALEFSDZrmkz:
32599 case VSCALEFSDZrr:
32600 case VSCALEFSDZrrb_Int:
32601 case VSCALEFSDZrrbk_Int:
32602 case VSCALEFSDZrrbkz_Int:
32603 case VSCALEFSDZrrk:
32604 case VSCALEFSDZrrkz:
32605 return true;
32606 }
32607 return false;
32608}
32609
32610bool isFSIN(unsigned Opcode) {
32611 return Opcode == FSIN;
32612}
32613
32614bool isSCASQ(unsigned Opcode) {
32615 return Opcode == SCASQ;
32616}
32617
32618bool isVCVTTPD2QQS(unsigned Opcode) {
32619 switch (Opcode) {
32620 case VCVTTPD2QQSZ128rm:
32621 case VCVTTPD2QQSZ128rmb:
32622 case VCVTTPD2QQSZ128rmbk:
32623 case VCVTTPD2QQSZ128rmbkz:
32624 case VCVTTPD2QQSZ128rmk:
32625 case VCVTTPD2QQSZ128rmkz:
32626 case VCVTTPD2QQSZ128rr:
32627 case VCVTTPD2QQSZ128rrk:
32628 case VCVTTPD2QQSZ128rrkz:
32629 case VCVTTPD2QQSZ256rm:
32630 case VCVTTPD2QQSZ256rmb:
32631 case VCVTTPD2QQSZ256rmbk:
32632 case VCVTTPD2QQSZ256rmbkz:
32633 case VCVTTPD2QQSZ256rmk:
32634 case VCVTTPD2QQSZ256rmkz:
32635 case VCVTTPD2QQSZ256rr:
32636 case VCVTTPD2QQSZ256rrb:
32637 case VCVTTPD2QQSZ256rrbk:
32638 case VCVTTPD2QQSZ256rrbkz:
32639 case VCVTTPD2QQSZ256rrk:
32640 case VCVTTPD2QQSZ256rrkz:
32641 case VCVTTPD2QQSZrm:
32642 case VCVTTPD2QQSZrmb:
32643 case VCVTTPD2QQSZrmbk:
32644 case VCVTTPD2QQSZrmbkz:
32645 case VCVTTPD2QQSZrmk:
32646 case VCVTTPD2QQSZrmkz:
32647 case VCVTTPD2QQSZrr:
32648 case VCVTTPD2QQSZrrb:
32649 case VCVTTPD2QQSZrrbk:
32650 case VCVTTPD2QQSZrrbkz:
32651 case VCVTTPD2QQSZrrk:
32652 case VCVTTPD2QQSZrrkz:
32653 return true;
32654 }
32655 return false;
32656}
32657
32658bool isPCMPGTW(unsigned Opcode) {
32659 switch (Opcode) {
32660 case MMX_PCMPGTWrm:
32661 case MMX_PCMPGTWrr:
32662 case PCMPGTWrm:
32663 case PCMPGTWrr:
32664 return true;
32665 }
32666 return false;
32667}
32668
32669bool isMULX(unsigned Opcode) {
32670 switch (Opcode) {
32671 case MULX32rm:
32672 case MULX32rm_EVEX:
32673 case MULX32rr:
32674 case MULX32rr_EVEX:
32675 case MULX64rm:
32676 case MULX64rm_EVEX:
32677 case MULX64rr:
32678 case MULX64rr_EVEX:
32679 return true;
32680 }
32681 return false;
32682}
32683
32684bool isVPMAXUW(unsigned Opcode) {
32685 switch (Opcode) {
32686 case VPMAXUWYrm:
32687 case VPMAXUWYrr:
32688 case VPMAXUWZ128rm:
32689 case VPMAXUWZ128rmk:
32690 case VPMAXUWZ128rmkz:
32691 case VPMAXUWZ128rr:
32692 case VPMAXUWZ128rrk:
32693 case VPMAXUWZ128rrkz:
32694 case VPMAXUWZ256rm:
32695 case VPMAXUWZ256rmk:
32696 case VPMAXUWZ256rmkz:
32697 case VPMAXUWZ256rr:
32698 case VPMAXUWZ256rrk:
32699 case VPMAXUWZ256rrkz:
32700 case VPMAXUWZrm:
32701 case VPMAXUWZrmk:
32702 case VPMAXUWZrmkz:
32703 case VPMAXUWZrr:
32704 case VPMAXUWZrrk:
32705 case VPMAXUWZrrkz:
32706 case VPMAXUWrm:
32707 case VPMAXUWrr:
32708 return true;
32709 }
32710 return false;
32711}
32712
32713bool isPAUSE(unsigned Opcode) {
32714 return Opcode == PAUSE;
32715}
32716
32717bool isMOVQ2DQ(unsigned Opcode) {
32718 return Opcode == MMX_MOVQ2DQrr;
32719}
32720
32721bool isVPSUBQ(unsigned Opcode) {
32722 switch (Opcode) {
32723 case VPSUBQYrm:
32724 case VPSUBQYrr:
32725 case VPSUBQZ128rm:
32726 case VPSUBQZ128rmb:
32727 case VPSUBQZ128rmbk:
32728 case VPSUBQZ128rmbkz:
32729 case VPSUBQZ128rmk:
32730 case VPSUBQZ128rmkz:
32731 case VPSUBQZ128rr:
32732 case VPSUBQZ128rrk:
32733 case VPSUBQZ128rrkz:
32734 case VPSUBQZ256rm:
32735 case VPSUBQZ256rmb:
32736 case VPSUBQZ256rmbk:
32737 case VPSUBQZ256rmbkz:
32738 case VPSUBQZ256rmk:
32739 case VPSUBQZ256rmkz:
32740 case VPSUBQZ256rr:
32741 case VPSUBQZ256rrk:
32742 case VPSUBQZ256rrkz:
32743 case VPSUBQZrm:
32744 case VPSUBQZrmb:
32745 case VPSUBQZrmbk:
32746 case VPSUBQZrmbkz:
32747 case VPSUBQZrmk:
32748 case VPSUBQZrmkz:
32749 case VPSUBQZrr:
32750 case VPSUBQZrrk:
32751 case VPSUBQZrrkz:
32752 case VPSUBQrm:
32753 case VPSUBQrr:
32754 return true;
32755 }
32756 return false;
32757}
32758
32759bool isVPABSW(unsigned Opcode) {
32760 switch (Opcode) {
32761 case VPABSWYrm:
32762 case VPABSWYrr:
32763 case VPABSWZ128rm:
32764 case VPABSWZ128rmk:
32765 case VPABSWZ128rmkz:
32766 case VPABSWZ128rr:
32767 case VPABSWZ128rrk:
32768 case VPABSWZ128rrkz:
32769 case VPABSWZ256rm:
32770 case VPABSWZ256rmk:
32771 case VPABSWZ256rmkz:
32772 case VPABSWZ256rr:
32773 case VPABSWZ256rrk:
32774 case VPABSWZ256rrkz:
32775 case VPABSWZrm:
32776 case VPABSWZrmk:
32777 case VPABSWZrmkz:
32778 case VPABSWZrr:
32779 case VPABSWZrrk:
32780 case VPABSWZrrkz:
32781 case VPABSWrm:
32782 case VPABSWrr:
32783 return true;
32784 }
32785 return false;
32786}
32787
32788bool isVPCOMPRESSD(unsigned Opcode) {
32789 switch (Opcode) {
32790 case VPCOMPRESSDZ128mr:
32791 case VPCOMPRESSDZ128mrk:
32792 case VPCOMPRESSDZ128rr:
32793 case VPCOMPRESSDZ128rrk:
32794 case VPCOMPRESSDZ128rrkz:
32795 case VPCOMPRESSDZ256mr:
32796 case VPCOMPRESSDZ256mrk:
32797 case VPCOMPRESSDZ256rr:
32798 case VPCOMPRESSDZ256rrk:
32799 case VPCOMPRESSDZ256rrkz:
32800 case VPCOMPRESSDZmr:
32801 case VPCOMPRESSDZmrk:
32802 case VPCOMPRESSDZrr:
32803 case VPCOMPRESSDZrrk:
32804 case VPCOMPRESSDZrrkz:
32805 return true;
32806 }
32807 return false;
32808}
32809
32810bool isVPMOVUSQW(unsigned Opcode) {
32811 switch (Opcode) {
32812 case VPMOVUSQWZ128mr:
32813 case VPMOVUSQWZ128mrk:
32814 case VPMOVUSQWZ128rr:
32815 case VPMOVUSQWZ128rrk:
32816 case VPMOVUSQWZ128rrkz:
32817 case VPMOVUSQWZ256mr:
32818 case VPMOVUSQWZ256mrk:
32819 case VPMOVUSQWZ256rr:
32820 case VPMOVUSQWZ256rrk:
32821 case VPMOVUSQWZ256rrkz:
32822 case VPMOVUSQWZmr:
32823 case VPMOVUSQWZmrk:
32824 case VPMOVUSQWZrr:
32825 case VPMOVUSQWZrrk:
32826 case VPMOVUSQWZrrkz:
32827 return true;
32828 }
32829 return false;
32830}
32831
32832bool isBLENDVPD(unsigned Opcode) {
32833 switch (Opcode) {
32834 case BLENDVPDrm0:
32835 case BLENDVPDrr0:
32836 return true;
32837 }
32838 return false;
32839}
32840
32841bool isVFNMADD132BF16(unsigned Opcode) {
32842 switch (Opcode) {
32843 case VFNMADD132BF16Z128m:
32844 case VFNMADD132BF16Z128mb:
32845 case VFNMADD132BF16Z128mbk:
32846 case VFNMADD132BF16Z128mbkz:
32847 case VFNMADD132BF16Z128mk:
32848 case VFNMADD132BF16Z128mkz:
32849 case VFNMADD132BF16Z128r:
32850 case VFNMADD132BF16Z128rk:
32851 case VFNMADD132BF16Z128rkz:
32852 case VFNMADD132BF16Z256m:
32853 case VFNMADD132BF16Z256mb:
32854 case VFNMADD132BF16Z256mbk:
32855 case VFNMADD132BF16Z256mbkz:
32856 case VFNMADD132BF16Z256mk:
32857 case VFNMADD132BF16Z256mkz:
32858 case VFNMADD132BF16Z256r:
32859 case VFNMADD132BF16Z256rk:
32860 case VFNMADD132BF16Z256rkz:
32861 case VFNMADD132BF16Zm:
32862 case VFNMADD132BF16Zmb:
32863 case VFNMADD132BF16Zmbk:
32864 case VFNMADD132BF16Zmbkz:
32865 case VFNMADD132BF16Zmk:
32866 case VFNMADD132BF16Zmkz:
32867 case VFNMADD132BF16Zr:
32868 case VFNMADD132BF16Zrk:
32869 case VFNMADD132BF16Zrkz:
32870 return true;
32871 }
32872 return false;
32873}
32874
32875bool isVPMOVQB(unsigned Opcode) {
32876 switch (Opcode) {
32877 case VPMOVQBZ128mr:
32878 case VPMOVQBZ128mrk:
32879 case VPMOVQBZ128rr:
32880 case VPMOVQBZ128rrk:
32881 case VPMOVQBZ128rrkz:
32882 case VPMOVQBZ256mr:
32883 case VPMOVQBZ256mrk:
32884 case VPMOVQBZ256rr:
32885 case VPMOVQBZ256rrk:
32886 case VPMOVQBZ256rrkz:
32887 case VPMOVQBZmr:
32888 case VPMOVQBZmrk:
32889 case VPMOVQBZrr:
32890 case VPMOVQBZrrk:
32891 case VPMOVQBZrrkz:
32892 return true;
32893 }
32894 return false;
32895}
32896
32897bool isVBLENDVPS(unsigned Opcode) {
32898 switch (Opcode) {
32899 case VBLENDVPSYrmr:
32900 case VBLENDVPSYrrr:
32901 case VBLENDVPSrmr:
32902 case VBLENDVPSrrr:
32903 return true;
32904 }
32905 return false;
32906}
32907
32908bool isKSHIFTLQ(unsigned Opcode) {
32909 return Opcode == KSHIFTLQki;
32910}
32911
32912bool isPMOVSXWD(unsigned Opcode) {
32913 switch (Opcode) {
32914 case PMOVSXWDrm:
32915 case PMOVSXWDrr:
32916 return true;
32917 }
32918 return false;
32919}
32920
32921bool isPHSUBSW(unsigned Opcode) {
32922 switch (Opcode) {
32923 case MMX_PHSUBSWrm:
32924 case MMX_PHSUBSWrr:
32925 case PHSUBSWrm:
32926 case PHSUBSWrr:
32927 return true;
32928 }
32929 return false;
32930}
32931
32932bool isPSRLQ(unsigned Opcode) {
32933 switch (Opcode) {
32934 case MMX_PSRLQri:
32935 case MMX_PSRLQrm:
32936 case MMX_PSRLQrr:
32937 case PSRLQri:
32938 case PSRLQrm:
32939 case PSRLQrr:
32940 return true;
32941 }
32942 return false;
32943}
32944
32945bool isVCVTPH2DQ(unsigned Opcode) {
32946 switch (Opcode) {
32947 case VCVTPH2DQZ128rm:
32948 case VCVTPH2DQZ128rmb:
32949 case VCVTPH2DQZ128rmbk:
32950 case VCVTPH2DQZ128rmbkz:
32951 case VCVTPH2DQZ128rmk:
32952 case VCVTPH2DQZ128rmkz:
32953 case VCVTPH2DQZ128rr:
32954 case VCVTPH2DQZ128rrk:
32955 case VCVTPH2DQZ128rrkz:
32956 case VCVTPH2DQZ256rm:
32957 case VCVTPH2DQZ256rmb:
32958 case VCVTPH2DQZ256rmbk:
32959 case VCVTPH2DQZ256rmbkz:
32960 case VCVTPH2DQZ256rmk:
32961 case VCVTPH2DQZ256rmkz:
32962 case VCVTPH2DQZ256rr:
32963 case VCVTPH2DQZ256rrk:
32964 case VCVTPH2DQZ256rrkz:
32965 case VCVTPH2DQZrm:
32966 case VCVTPH2DQZrmb:
32967 case VCVTPH2DQZrmbk:
32968 case VCVTPH2DQZrmbkz:
32969 case VCVTPH2DQZrmk:
32970 case VCVTPH2DQZrmkz:
32971 case VCVTPH2DQZrr:
32972 case VCVTPH2DQZrrb:
32973 case VCVTPH2DQZrrbk:
32974 case VCVTPH2DQZrrbkz:
32975 case VCVTPH2DQZrrk:
32976 case VCVTPH2DQZrrkz:
32977 return true;
32978 }
32979 return false;
32980}
32981
32982bool isFISUB(unsigned Opcode) {
32983 switch (Opcode) {
32984 case SUB_FI16m:
32985 case SUB_FI32m:
32986 return true;
32987 }
32988 return false;
32989}
32990
32991bool isVCVTPS2UDQ(unsigned Opcode) {
32992 switch (Opcode) {
32993 case VCVTPS2UDQZ128rm:
32994 case VCVTPS2UDQZ128rmb:
32995 case VCVTPS2UDQZ128rmbk:
32996 case VCVTPS2UDQZ128rmbkz:
32997 case VCVTPS2UDQZ128rmk:
32998 case VCVTPS2UDQZ128rmkz:
32999 case VCVTPS2UDQZ128rr:
33000 case VCVTPS2UDQZ128rrk:
33001 case VCVTPS2UDQZ128rrkz:
33002 case VCVTPS2UDQZ256rm:
33003 case VCVTPS2UDQZ256rmb:
33004 case VCVTPS2UDQZ256rmbk:
33005 case VCVTPS2UDQZ256rmbkz:
33006 case VCVTPS2UDQZ256rmk:
33007 case VCVTPS2UDQZ256rmkz:
33008 case VCVTPS2UDQZ256rr:
33009 case VCVTPS2UDQZ256rrk:
33010 case VCVTPS2UDQZ256rrkz:
33011 case VCVTPS2UDQZrm:
33012 case VCVTPS2UDQZrmb:
33013 case VCVTPS2UDQZrmbk:
33014 case VCVTPS2UDQZrmbkz:
33015 case VCVTPS2UDQZrmk:
33016 case VCVTPS2UDQZrmkz:
33017 case VCVTPS2UDQZrr:
33018 case VCVTPS2UDQZrrb:
33019 case VCVTPS2UDQZrrbk:
33020 case VCVTPS2UDQZrrbkz:
33021 case VCVTPS2UDQZrrk:
33022 case VCVTPS2UDQZrrkz:
33023 return true;
33024 }
33025 return false;
33026}
33027
33028bool isVMOVDDUP(unsigned Opcode) {
33029 switch (Opcode) {
33030 case VMOVDDUPYrm:
33031 case VMOVDDUPYrr:
33032 case VMOVDDUPZ128rm:
33033 case VMOVDDUPZ128rmk:
33034 case VMOVDDUPZ128rmkz:
33035 case VMOVDDUPZ128rr:
33036 case VMOVDDUPZ128rrk:
33037 case VMOVDDUPZ128rrkz:
33038 case VMOVDDUPZ256rm:
33039 case VMOVDDUPZ256rmk:
33040 case VMOVDDUPZ256rmkz:
33041 case VMOVDDUPZ256rr:
33042 case VMOVDDUPZ256rrk:
33043 case VMOVDDUPZ256rrkz:
33044 case VMOVDDUPZrm:
33045 case VMOVDDUPZrmk:
33046 case VMOVDDUPZrmkz:
33047 case VMOVDDUPZrr:
33048 case VMOVDDUPZrrk:
33049 case VMOVDDUPZrrkz:
33050 case VMOVDDUPrm:
33051 case VMOVDDUPrr:
33052 return true;
33053 }
33054 return false;
33055}
33056
33057bool isPCMPEQD(unsigned Opcode) {
33058 switch (Opcode) {
33059 case MMX_PCMPEQDrm:
33060 case MMX_PCMPEQDrr:
33061 case PCMPEQDrm:
33062 case PCMPEQDrr:
33063 return true;
33064 }
33065 return false;
33066}
33067
33068bool isVRSQRT28SD(unsigned Opcode) {
33069 switch (Opcode) {
33070 case VRSQRT28SDZm:
33071 case VRSQRT28SDZmk:
33072 case VRSQRT28SDZmkz:
33073 case VRSQRT28SDZr:
33074 case VRSQRT28SDZrb:
33075 case VRSQRT28SDZrbk:
33076 case VRSQRT28SDZrbkz:
33077 case VRSQRT28SDZrk:
33078 case VRSQRT28SDZrkz:
33079 return true;
33080 }
33081 return false;
33082}
33083
33084bool isTDPHBF8PS(unsigned Opcode) {
33085 return Opcode == TDPHBF8PS;
33086}
33087
33088bool isLODSW(unsigned Opcode) {
33089 return Opcode == LODSW;
33090}
33091
33092bool isVPOPCNTQ(unsigned Opcode) {
33093 switch (Opcode) {
33094 case VPOPCNTQZ128rm:
33095 case VPOPCNTQZ128rmb:
33096 case VPOPCNTQZ128rmbk:
33097 case VPOPCNTQZ128rmbkz:
33098 case VPOPCNTQZ128rmk:
33099 case VPOPCNTQZ128rmkz:
33100 case VPOPCNTQZ128rr:
33101 case VPOPCNTQZ128rrk:
33102 case VPOPCNTQZ128rrkz:
33103 case VPOPCNTQZ256rm:
33104 case VPOPCNTQZ256rmb:
33105 case VPOPCNTQZ256rmbk:
33106 case VPOPCNTQZ256rmbkz:
33107 case VPOPCNTQZ256rmk:
33108 case VPOPCNTQZ256rmkz:
33109 case VPOPCNTQZ256rr:
33110 case VPOPCNTQZ256rrk:
33111 case VPOPCNTQZ256rrkz:
33112 case VPOPCNTQZrm:
33113 case VPOPCNTQZrmb:
33114 case VPOPCNTQZrmbk:
33115 case VPOPCNTQZrmbkz:
33116 case VPOPCNTQZrmk:
33117 case VPOPCNTQZrmkz:
33118 case VPOPCNTQZrr:
33119 case VPOPCNTQZrrk:
33120 case VPOPCNTQZrrkz:
33121 return true;
33122 }
33123 return false;
33124}
33125
33126bool isKSHIFTRB(unsigned Opcode) {
33127 return Opcode == KSHIFTRBki;
33128}
33129
33130bool isVFNMADDPS(unsigned Opcode) {
33131 switch (Opcode) {
33132 case VFNMADDPS4Ymr:
33133 case VFNMADDPS4Yrm:
33134 case VFNMADDPS4Yrr:
33135 case VFNMADDPS4Yrr_REV:
33136 case VFNMADDPS4mr:
33137 case VFNMADDPS4rm:
33138 case VFNMADDPS4rr:
33139 case VFNMADDPS4rr_REV:
33140 return true;
33141 }
33142 return false;
33143}
33144
33145bool isCCMPCC(unsigned Opcode) {
33146 switch (Opcode) {
33147 case CCMP16mi:
33148 case CCMP16mi8:
33149 case CCMP16mr:
33150 case CCMP16ri:
33151 case CCMP16ri8:
33152 case CCMP16rm:
33153 case CCMP16rr:
33154 case CCMP16rr_REV:
33155 case CCMP32mi:
33156 case CCMP32mi8:
33157 case CCMP32mr:
33158 case CCMP32ri:
33159 case CCMP32ri8:
33160 case CCMP32rm:
33161 case CCMP32rr:
33162 case CCMP32rr_REV:
33163 case CCMP64mi32:
33164 case CCMP64mi8:
33165 case CCMP64mr:
33166 case CCMP64ri32:
33167 case CCMP64ri8:
33168 case CCMP64rm:
33169 case CCMP64rr:
33170 case CCMP64rr_REV:
33171 case CCMP8mi:
33172 case CCMP8mr:
33173 case CCMP8ri:
33174 case CCMP8rm:
33175 case CCMP8rr:
33176 case CCMP8rr_REV:
33177 return true;
33178 }
33179 return false;
33180}
33181
33182bool isFXRSTOR64(unsigned Opcode) {
33183 return Opcode == FXRSTOR64;
33184}
33185
33186bool isVFMSUBADD213PD(unsigned Opcode) {
33187 switch (Opcode) {
33188 case VFMSUBADD213PDYm:
33189 case VFMSUBADD213PDYr:
33190 case VFMSUBADD213PDZ128m:
33191 case VFMSUBADD213PDZ128mb:
33192 case VFMSUBADD213PDZ128mbk:
33193 case VFMSUBADD213PDZ128mbkz:
33194 case VFMSUBADD213PDZ128mk:
33195 case VFMSUBADD213PDZ128mkz:
33196 case VFMSUBADD213PDZ128r:
33197 case VFMSUBADD213PDZ128rk:
33198 case VFMSUBADD213PDZ128rkz:
33199 case VFMSUBADD213PDZ256m:
33200 case VFMSUBADD213PDZ256mb:
33201 case VFMSUBADD213PDZ256mbk:
33202 case VFMSUBADD213PDZ256mbkz:
33203 case VFMSUBADD213PDZ256mk:
33204 case VFMSUBADD213PDZ256mkz:
33205 case VFMSUBADD213PDZ256r:
33206 case VFMSUBADD213PDZ256rk:
33207 case VFMSUBADD213PDZ256rkz:
33208 case VFMSUBADD213PDZm:
33209 case VFMSUBADD213PDZmb:
33210 case VFMSUBADD213PDZmbk:
33211 case VFMSUBADD213PDZmbkz:
33212 case VFMSUBADD213PDZmk:
33213 case VFMSUBADD213PDZmkz:
33214 case VFMSUBADD213PDZr:
33215 case VFMSUBADD213PDZrb:
33216 case VFMSUBADD213PDZrbk:
33217 case VFMSUBADD213PDZrbkz:
33218 case VFMSUBADD213PDZrk:
33219 case VFMSUBADD213PDZrkz:
33220 case VFMSUBADD213PDm:
33221 case VFMSUBADD213PDr:
33222 return true;
33223 }
33224 return false;
33225}
33226
33227bool isVSQRTPH(unsigned Opcode) {
33228 switch (Opcode) {
33229 case VSQRTPHZ128m:
33230 case VSQRTPHZ128mb:
33231 case VSQRTPHZ128mbk:
33232 case VSQRTPHZ128mbkz:
33233 case VSQRTPHZ128mk:
33234 case VSQRTPHZ128mkz:
33235 case VSQRTPHZ128r:
33236 case VSQRTPHZ128rk:
33237 case VSQRTPHZ128rkz:
33238 case VSQRTPHZ256m:
33239 case VSQRTPHZ256mb:
33240 case VSQRTPHZ256mbk:
33241 case VSQRTPHZ256mbkz:
33242 case VSQRTPHZ256mk:
33243 case VSQRTPHZ256mkz:
33244 case VSQRTPHZ256r:
33245 case VSQRTPHZ256rk:
33246 case VSQRTPHZ256rkz:
33247 case VSQRTPHZm:
33248 case VSQRTPHZmb:
33249 case VSQRTPHZmbk:
33250 case VSQRTPHZmbkz:
33251 case VSQRTPHZmk:
33252 case VSQRTPHZmkz:
33253 case VSQRTPHZr:
33254 case VSQRTPHZrb:
33255 case VSQRTPHZrbk:
33256 case VSQRTPHZrbkz:
33257 case VSQRTPHZrk:
33258 case VSQRTPHZrkz:
33259 return true;
33260 }
33261 return false;
33262}
33263
33264bool isPOPF(unsigned Opcode) {
33265 return Opcode == POPF16;
33266}
33267
33268bool isVPSUBUSB(unsigned Opcode) {
33269 switch (Opcode) {
33270 case VPSUBUSBYrm:
33271 case VPSUBUSBYrr:
33272 case VPSUBUSBZ128rm:
33273 case VPSUBUSBZ128rmk:
33274 case VPSUBUSBZ128rmkz:
33275 case VPSUBUSBZ128rr:
33276 case VPSUBUSBZ128rrk:
33277 case VPSUBUSBZ128rrkz:
33278 case VPSUBUSBZ256rm:
33279 case VPSUBUSBZ256rmk:
33280 case VPSUBUSBZ256rmkz:
33281 case VPSUBUSBZ256rr:
33282 case VPSUBUSBZ256rrk:
33283 case VPSUBUSBZ256rrkz:
33284 case VPSUBUSBZrm:
33285 case VPSUBUSBZrmk:
33286 case VPSUBUSBZrmkz:
33287 case VPSUBUSBZrr:
33288 case VPSUBUSBZrrk:
33289 case VPSUBUSBZrrkz:
33290 case VPSUBUSBrm:
33291 case VPSUBUSBrr:
33292 return true;
33293 }
33294 return false;
33295}
33296
33297bool isTCVTROWPS2BF16L(unsigned Opcode) {
33298 switch (Opcode) {
33299 case TCVTROWPS2BF16Lrre:
33300 case TCVTROWPS2BF16Lrri:
33301 return true;
33302 }
33303 return false;
33304}
33305
33306bool isPREFETCHIT1(unsigned Opcode) {
33307 return Opcode == PREFETCHIT1;
33308}
33309
33310bool isVPADDSW(unsigned Opcode) {
33311 switch (Opcode) {
33312 case VPADDSWYrm:
33313 case VPADDSWYrr:
33314 case VPADDSWZ128rm:
33315 case VPADDSWZ128rmk:
33316 case VPADDSWZ128rmkz:
33317 case VPADDSWZ128rr:
33318 case VPADDSWZ128rrk:
33319 case VPADDSWZ128rrkz:
33320 case VPADDSWZ256rm:
33321 case VPADDSWZ256rmk:
33322 case VPADDSWZ256rmkz:
33323 case VPADDSWZ256rr:
33324 case VPADDSWZ256rrk:
33325 case VPADDSWZ256rrkz:
33326 case VPADDSWZrm:
33327 case VPADDSWZrmk:
33328 case VPADDSWZrmkz:
33329 case VPADDSWZrr:
33330 case VPADDSWZrrk:
33331 case VPADDSWZrrkz:
33332 case VPADDSWrm:
33333 case VPADDSWrr:
33334 return true;
33335 }
33336 return false;
33337}
33338
33339bool isVADDSUBPD(unsigned Opcode) {
33340 switch (Opcode) {
33341 case VADDSUBPDYrm:
33342 case VADDSUBPDYrr:
33343 case VADDSUBPDrm:
33344 case VADDSUBPDrr:
33345 return true;
33346 }
33347 return false;
33348}
33349
33350bool isKANDD(unsigned Opcode) {
33351 return Opcode == KANDDkk;
33352}
33353
33354bool isOUTSB(unsigned Opcode) {
33355 return Opcode == OUTSB;
33356}
33357
33358bool isPREFETCHRST2(unsigned Opcode) {
33359 return Opcode == PREFETCHRST2;
33360}
33361
33362bool isFNSTSW(unsigned Opcode) {
33363 switch (Opcode) {
33364 case FNSTSW16r:
33365 case FNSTSWm:
33366 return true;
33367 }
33368 return false;
33369}
33370
33371bool isPMINSB(unsigned Opcode) {
33372 switch (Opcode) {
33373 case PMINSBrm:
33374 case PMINSBrr:
33375 return true;
33376 }
33377 return false;
33378}
33379
33380#endif // GET_X86_MNEMONIC_TABLES_CPP
33381
33382} // end namespace X86
33383} // end namespace llvm