1//===--- SystemZ.cpp - Implement SystemZ target feature support -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements SystemZ TargetInfo objects.
10//
11//===----------------------------------------------------------------------===//
12
13#include "SystemZ.h"
14#include "clang/Basic/Builtins.h"
15#include "clang/Basic/LangOptions.h"
16#include "clang/Basic/MacroBuilder.h"
17#include "clang/Basic/TargetBuiltins.h"
18#include "llvm/ADT/StringExtras.h"
19#include "llvm/ADT/StringSwitch.h"
20
21using namespace clang;
22using namespace clang::targets;
23
24static constexpr int NumBuiltins =
25 clang::SystemZ::LastTSBuiltin - Builtin::FirstTSBuiltin;
26
27static constexpr llvm::StringTable BuiltinStrings =
28 CLANG_BUILTIN_STR_TABLE_START
29#define BUILTIN CLANG_BUILTIN_STR_TABLE
30#define TARGET_BUILTIN CLANG_TARGET_BUILTIN_STR_TABLE
31#include "clang/Basic/BuiltinsSystemZ.def"
32 ;
33
34static constexpr auto BuiltinInfos = Builtin::MakeInfos<NumBuiltins>(Infos: {
35#define BUILTIN CLANG_BUILTIN_ENTRY
36#define TARGET_BUILTIN CLANG_TARGET_BUILTIN_ENTRY
37#include "clang/Basic/BuiltinsSystemZ.def"
38});
39
40const char *const SystemZTargetInfo::GCCRegNames[] = {
41 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
42 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
43 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7",
44 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15",
45 /*ap*/"", "cc", /*fp*/"", /*rp*/"", "a0", "a1",
46 "v16", "v18", "v20", "v22", "v17", "v19", "v21", "v23",
47 "v24", "v26", "v28", "v30", "v25", "v27", "v29", "v31"
48};
49
50const TargetInfo::AddlRegName GCCAddlRegNames[] = {
51 {.Names: {"v0"}, .RegNum: 16}, {.Names: {"v2"}, .RegNum: 17}, {.Names: {"v4"}, .RegNum: 18}, {.Names: {"v6"}, .RegNum: 19},
52 {.Names: {"v1"}, .RegNum: 20}, {.Names: {"v3"}, .RegNum: 21}, {.Names: {"v5"}, .RegNum: 22}, {.Names: {"v7"}, .RegNum: 23},
53 {.Names: {"v8"}, .RegNum: 24}, {.Names: {"v10"}, .RegNum: 25}, {.Names: {"v12"}, .RegNum: 26}, {.Names: {"v14"}, .RegNum: 27},
54 {.Names: {"v9"}, .RegNum: 28}, {.Names: {"v11"}, .RegNum: 29}, {.Names: {"v13"}, .RegNum: 30}, {.Names: {"v15"}, .RegNum: 31}
55};
56
57ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const {
58 return llvm::ArrayRef(GCCRegNames);
59}
60
61ArrayRef<TargetInfo::AddlRegName> SystemZTargetInfo::getGCCAddlRegNames() const {
62 return llvm::ArrayRef(GCCAddlRegNames);
63}
64
65bool SystemZTargetInfo::validateAsmConstraint(
66 const char *&Name, TargetInfo::ConstraintInfo &Info) const {
67 switch (*Name) {
68 default:
69 return false;
70
71 case 'Z':
72 switch (Name[1]) {
73 default:
74 return false;
75 case 'Q': // Address with base and unsigned 12-bit displacement
76 case 'R': // Likewise, plus an index
77 case 'S': // Address with base and signed 20-bit displacement
78 case 'T': // Likewise, plus an index
79 break;
80 }
81 [[fallthrough]];
82 case 'a': // Address register
83 case 'd': // Data register (equivalent to 'r')
84 case 'f': // Floating-point register
85 case 'v': // Vector register
86 Info.setAllowsRegister();
87 return true;
88
89 case 'I': // Unsigned 8-bit constant
90 case 'J': // Unsigned 12-bit constant
91 case 'K': // Signed 16-bit constant
92 case 'L': // Signed 20-bit displacement (on all targets we support)
93 case 'M': // 0x7fffffff
94 return true;
95
96 case 'Q': // Memory with base and unsigned 12-bit displacement
97 case 'R': // Likewise, plus an index
98 case 'S': // Memory with base and signed 20-bit displacement
99 case 'T': // Likewise, plus an index
100 Info.setAllowsMemory();
101 return true;
102 }
103}
104
105struct ISANameRevision {
106 llvm::StringLiteral Name;
107 int ISARevisionID;
108};
109static constexpr ISANameRevision ISARevisions[] = {
110 {.Name: {"arch8"}, .ISARevisionID: 8}, {.Name: {"z10"}, .ISARevisionID: 8},
111 {.Name: {"arch9"}, .ISARevisionID: 9}, {.Name: {"z196"}, .ISARevisionID: 9},
112 {.Name: {"arch10"}, .ISARevisionID: 10}, {.Name: {"zEC12"}, .ISARevisionID: 10},
113 {.Name: {"arch11"}, .ISARevisionID: 11}, {.Name: {"z13"}, .ISARevisionID: 11},
114 {.Name: {"arch12"}, .ISARevisionID: 12}, {.Name: {"z14"}, .ISARevisionID: 12},
115 {.Name: {"arch13"}, .ISARevisionID: 13}, {.Name: {"z15"}, .ISARevisionID: 13},
116 {.Name: {"arch14"}, .ISARevisionID: 14}, {.Name: {"z16"}, .ISARevisionID: 14},
117 {.Name: {"arch15"}, .ISARevisionID: 15}, {.Name: {"z17"}, .ISARevisionID: 15},
118};
119
120int SystemZTargetInfo::getISARevision(StringRef Name) const {
121 const auto Rev =
122 llvm::find_if(Range: ISARevisions, P: [Name](const ISANameRevision &CR) {
123 return CR.Name == Name;
124 });
125 if (Rev == std::end(arr: ISARevisions))
126 return -1;
127 return Rev->ISARevisionID;
128}
129
130void SystemZTargetInfo::fillValidCPUList(
131 SmallVectorImpl<StringRef> &Values) const {
132 for (const ISANameRevision &Rev : ISARevisions)
133 Values.push_back(Elt: Rev.Name);
134}
135
136bool SystemZTargetInfo::hasFeature(StringRef Feature) const {
137 return llvm::StringSwitch<bool>(Feature)
138 .Case(S: "systemz", Value: true)
139 .Case(S: "arch8", Value: ISARevision >= 8)
140 .Case(S: "arch9", Value: ISARevision >= 9)
141 .Case(S: "arch10", Value: ISARevision >= 10)
142 .Case(S: "arch11", Value: ISARevision >= 11)
143 .Case(S: "arch12", Value: ISARevision >= 12)
144 .Case(S: "arch13", Value: ISARevision >= 13)
145 .Case(S: "arch14", Value: ISARevision >= 14)
146 .Case(S: "arch15", Value: ISARevision >= 15)
147 .Case(S: "htm", Value: HasTransactionalExecution)
148 .Case(S: "vx", Value: HasVector)
149 .Default(Value: false);
150}
151
152unsigned SystemZTargetInfo::getMinGlobalAlign(uint64_t Size,
153 bool HasNonWeakDef) const {
154 // Don't enforce the minimum alignment on an external or weak symbol if
155 // -munaligned-symbols is passed.
156 if (UnalignedSymbols && !HasNonWeakDef)
157 return 0;
158
159 return MinGlobalAlign;
160}
161
162void SystemZTargetInfo::getTargetDefines(const LangOptions &Opts,
163 MacroBuilder &Builder) const {
164 Builder.defineMacro(Name: "__s390__");
165 Builder.defineMacro(Name: "__s390x__");
166 Builder.defineMacro(Name: "__zarch__");
167 Builder.defineMacro(Name: "__LONG_DOUBLE_128__");
168
169 Builder.defineMacro(Name: "__ARCH__", Value: Twine(ISARevision));
170
171 Builder.defineMacro(Name: "__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
172 Builder.defineMacro(Name: "__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
173 Builder.defineMacro(Name: "__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
174 Builder.defineMacro(Name: "__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
175
176 if (HasTransactionalExecution)
177 Builder.defineMacro(Name: "__HTM__");
178 if (HasVector)
179 Builder.defineMacro(Name: "__VX__");
180 if (Opts.ZVector)
181 Builder.defineMacro(Name: "__VEC__", Value: "10305");
182
183 /* Set __TARGET_LIB__ only if a value was given. If no value was given */
184 /* we rely on the LE headers to define __TARGET_LIB__. */
185 if (!getTriple().getOSVersion().empty()) {
186 llvm::VersionTuple V = getTriple().getOSVersion();
187 // Create string with form: 0xPVRRMMMM, where P=4
188 std::string Str("0x");
189 unsigned int Librel = 0x40000000;
190 Librel |= V.getMajor() << 24;
191 Librel |= V.getMinor().value_or(u: 1) << 16;
192 Librel |= V.getSubminor().value_or(u: 0);
193 Str += llvm::utohexstr(X: Librel);
194
195 Builder.defineMacro(Name: "__TARGET_LIB__", Value: Str.c_str());
196 }
197}
198
199llvm::SmallVector<Builtin::InfosShard>
200SystemZTargetInfo::getTargetBuiltins() const {
201 return {{.Strings: &BuiltinStrings, .Infos: BuiltinInfos}};
202}
203