1//===- llvm/CodeGen/MachineRegisterInfo.h -----------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the MachineRegisterInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H
14#define LLVM_CODEGEN_MACHINEREGISTERINFO_H
15
16#include "llvm/ADT/ArrayRef.h"
17#include "llvm/ADT/BitVector.h"
18#include "llvm/ADT/IndexedMap.h"
19#include "llvm/ADT/PointerUnion.h"
20#include "llvm/ADT/SmallPtrSet.h"
21#include "llvm/ADT/SmallVector.h"
22#include "llvm/ADT/StringSet.h"
23#include "llvm/ADT/iterator_range.h"
24#include "llvm/CodeGen/MachineBasicBlock.h"
25#include "llvm/CodeGen/MachineFunction.h"
26#include "llvm/CodeGen/MachineInstr.h"
27#include "llvm/CodeGen/MachineInstrBundle.h"
28#include "llvm/CodeGen/MachineOperand.h"
29#include "llvm/CodeGen/RegisterBank.h"
30#include "llvm/CodeGen/TargetRegisterInfo.h"
31#include "llvm/CodeGen/TargetSubtargetInfo.h"
32#include "llvm/MC/LaneBitmask.h"
33#include "llvm/Support/Compiler.h"
34#include <cassert>
35#include <cstddef>
36#include <cstdint>
37#include <iterator>
38#include <memory>
39#include <utility>
40#include <vector>
41
42namespace llvm {
43
44class PSetIterator;
45
46/// Convenient type to represent either a register class or a register bank.
47using RegClassOrRegBank =
48 PointerUnion<const TargetRegisterClass *, const RegisterBank *>;
49
50/// MachineRegisterInfo - Keep track of information for virtual and physical
51/// registers, including vreg register classes, use/def chains for registers,
52/// etc.
53class MachineRegisterInfo {
54public:
55 class LLVM_ABI Delegate {
56 virtual void anchor();
57
58 public:
59 virtual ~Delegate() = default;
60
61 virtual void MRI_NoteNewVirtualRegister(Register Reg) = 0;
62 virtual void MRI_NoteCloneVirtualRegister(Register NewReg,
63 Register SrcReg) {
64 MRI_NoteNewVirtualRegister(Reg: NewReg);
65 }
66 };
67
68private:
69 MachineFunction *MF;
70 SmallPtrSet<Delegate *, 1> TheDelegates;
71
72 /// True if subregister liveness is tracked.
73 const bool TracksSubRegLiveness;
74
75 /// VRegInfo - Information we keep for each virtual register.
76 ///
77 /// Each element in this list contains the register class of the vreg and the
78 /// start of the use/def list for the register.
79 IndexedMap<std::pair<RegClassOrRegBank, MachineOperand *>,
80 VirtReg2IndexFunctor>
81 VRegInfo;
82
83 /// Map for recovering vreg name from vreg number.
84 /// This map is used by the MIR Printer.
85 IndexedMap<std::string, VirtReg2IndexFunctor> VReg2Name;
86
87 /// StringSet that is used to unique vreg names.
88 StringSet<> VRegNames;
89
90 /// The flag is true upon \p UpdatedCSRs initialization
91 /// and false otherwise.
92 bool IsUpdatedCSRsInitialized = false;
93
94 /// Contains the updated callee saved register list.
95 /// As opposed to the static list defined in register info,
96 /// all registers that were disabled are removed from the list.
97 SmallVector<MCPhysReg, 16> UpdatedCSRs;
98
99 /// RegAllocHints - This vector records register allocation hints for
100 /// virtual registers. For each virtual register, it keeps a pair of hint
101 /// type and hints vector making up the allocation hints. Only the first
102 /// hint may be target specific, and in that case this is reflected by the
103 /// first member of the pair being non-zero. If the hinted register is
104 /// virtual, it means the allocator should prefer the physical register
105 /// allocated to it if any.
106 IndexedMap<std::pair<unsigned, SmallVector<Register, 4>>,
107 VirtReg2IndexFunctor>
108 RegAllocHints;
109
110 /// PhysRegUseDefLists - This is an array of the head of the use/def list for
111 /// physical registers.
112 std::unique_ptr<MachineOperand *[]> PhysRegUseDefLists;
113
114 /// getRegUseDefListHead - Return the head pointer for the register use/def
115 /// list for the specified virtual or physical register.
116 MachineOperand *&getRegUseDefListHead(Register RegNo) {
117 if (RegNo.isVirtual())
118 return VRegInfo[RegNo.id()].second;
119 return PhysRegUseDefLists[RegNo.id()];
120 }
121
122 MachineOperand *getRegUseDefListHead(Register RegNo) const {
123 if (RegNo.isVirtual())
124 return VRegInfo[RegNo.id()].second;
125 return PhysRegUseDefLists[RegNo.id()];
126 }
127
128 /// Get the next element in the use-def chain.
129 static MachineOperand *getNextOperandForReg(const MachineOperand *MO) {
130 assert(MO && MO->isReg() && "This is not a register operand!");
131 return MO->Contents.Reg.Next;
132 }
133
134 /// UsedPhysRegMask - Additional used physregs including aliases.
135 /// This bit vector represents all the registers clobbered by function calls.
136 BitVector UsedPhysRegMask;
137
138 /// ReservedRegs - This is a bit vector of reserved registers. The target
139 /// may change its mind about which registers should be reserved. This
140 /// vector is the frozen set of reserved registers when register allocation
141 /// started.
142 BitVector ReservedRegs;
143
144 using VRegToTypeMap = IndexedMap<LLT, VirtReg2IndexFunctor>;
145 /// Map generic virtual registers to their low-level type.
146 VRegToTypeMap VRegToType;
147
148 /// Keep track of the physical registers that are live in to the function.
149 /// Live in values are typically arguments in registers. LiveIn values are
150 /// allowed to have virtual registers associated with them, stored in the
151 /// second element.
152 std::vector<std::pair<MCRegister, Register>> LiveIns;
153
154public:
155 LLVM_ABI explicit MachineRegisterInfo(MachineFunction *MF);
156 MachineRegisterInfo(const MachineRegisterInfo &) = delete;
157 MachineRegisterInfo &operator=(const MachineRegisterInfo &) = delete;
158
159 const TargetRegisterInfo *getTargetRegisterInfo() const {
160 return MF->getSubtarget().getRegisterInfo();
161 }
162
163 void resetDelegate(Delegate *delegate) {
164 // Ensure another delegate does not take over unless the current
165 // delegate first unattaches itself.
166 assert(TheDelegates.count(delegate) &&
167 "Only an existing delegate can perform reset!");
168 TheDelegates.erase(Ptr: delegate);
169 }
170
171 void addDelegate(Delegate *delegate) {
172 assert(delegate && !TheDelegates.count(delegate) &&
173 "Attempted to add null delegate, or to change it without "
174 "first resetting it!");
175
176 TheDelegates.insert(Ptr: delegate);
177 }
178
179 void noteNewVirtualRegister(Register Reg) {
180 for (auto *TheDelegate : TheDelegates)
181 TheDelegate->MRI_NoteNewVirtualRegister(Reg);
182 }
183
184 void noteCloneVirtualRegister(Register NewReg, Register SrcReg) {
185 for (auto *TheDelegate : TheDelegates)
186 TheDelegate->MRI_NoteCloneVirtualRegister(NewReg, SrcReg);
187 }
188
189 const MachineFunction &getMF() const { return *MF; }
190
191 //===--------------------------------------------------------------------===//
192 // Function State
193 //===--------------------------------------------------------------------===//
194
195 // isSSA - Returns true when the machine function is in SSA form. Early
196 // passes require the machine function to be in SSA form where every virtual
197 // register has a single defining instruction.
198 //
199 // The TwoAddressInstructionPass and PHIElimination passes take the machine
200 // function out of SSA form when they introduce multiple defs per virtual
201 // register.
202 bool isSSA() const { return MF->getProperties().hasIsSSA(); }
203
204 // leaveSSA - Indicates that the machine function is no longer in SSA form.
205 void leaveSSA() { MF->getProperties().resetIsSSA(); }
206
207 /// tracksLiveness - Returns true when tracking register liveness accurately.
208 /// (see MachineFUnctionProperties::Property description for details)
209 bool tracksLiveness() const {
210 return MF->getProperties().hasTracksLiveness();
211 }
212
213 /// invalidateLiveness - Indicates that register liveness is no longer being
214 /// tracked accurately.
215 ///
216 /// This should be called by late passes that invalidate the liveness
217 /// information.
218 void invalidateLiveness() { MF->getProperties().resetTracksLiveness(); }
219
220 /// Returns true if liveness for register class @p RC should be tracked at
221 /// the subregister level.
222 bool shouldTrackSubRegLiveness(const TargetRegisterClass &RC) const {
223 return subRegLivenessEnabled() && RC.HasDisjunctSubRegs;
224 }
225 bool shouldTrackSubRegLiveness(Register VReg) const {
226 assert(VReg.isVirtual() && "Must pass a VReg");
227 const TargetRegisterClass *RC = getRegClassOrNull(Reg: VReg);
228 return LLVM_LIKELY(RC) ? shouldTrackSubRegLiveness(RC: *RC) : false;
229 }
230 bool subRegLivenessEnabled() const {
231 return TracksSubRegLiveness;
232 }
233
234 //===--------------------------------------------------------------------===//
235 // Register Info
236 //===--------------------------------------------------------------------===//
237
238 /// Returns true if the updated CSR list was initialized and false otherwise.
239 bool isUpdatedCSRsInitialized() const { return IsUpdatedCSRsInitialized; }
240
241 /// Disables the register from the list of CSRs.
242 /// I.e. the register will not appear as part of the CSR mask.
243 /// \see UpdatedCalleeSavedRegs.
244 LLVM_ABI void disableCalleeSavedRegister(MCRegister Reg);
245
246 /// Returns list of callee saved registers.
247 /// The function returns the updated CSR list (after taking into account
248 /// registers that are disabled from the CSR list).
249 LLVM_ABI const MCPhysReg *getCalleeSavedRegs() const;
250
251 /// Sets the updated Callee Saved Registers list.
252 /// Notice that it will override ant previously disabled/saved CSRs.
253 LLVM_ABI void setCalleeSavedRegs(ArrayRef<MCPhysReg> CSRs);
254
255 // Strictly for use by MachineInstr.cpp.
256 LLVM_ABI void addRegOperandToUseList(MachineOperand *MO);
257
258 // Strictly for use by MachineInstr.cpp.
259 LLVM_ABI void removeRegOperandFromUseList(MachineOperand *MO);
260
261 // Strictly for use by MachineInstr.cpp.
262 LLVM_ABI void moveOperands(MachineOperand *Dst, MachineOperand *Src,
263 unsigned NumOps);
264
265 /// Verify the sanity of the use list for Reg.
266 LLVM_ABI void verifyUseList(Register Reg) const;
267
268 /// Verify the use list of all registers.
269 LLVM_ABI void verifyUseLists() const;
270
271 /// reg_begin/reg_end - Provide iteration support to walk over all definitions
272 /// and uses of a register within the MachineFunction that corresponds to this
273 /// MachineRegisterInfo object.
274 template <bool Uses, bool Defs, bool SkipDebug, bool ByOperand, bool ByInstr>
275 class defusechain_iterator;
276 template <bool Uses, bool Defs, bool SkipDebug, bool ByInstr>
277 class defusechain_instr_iterator;
278
279 // Make it a friend so it can access getNextOperandForReg().
280 template <bool, bool, bool, bool, bool> friend class defusechain_iterator;
281 template <bool, bool, bool, bool> friend class defusechain_instr_iterator;
282
283 /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified
284 /// register.
285 using reg_iterator = defusechain_iterator<true, true, false, true, false>;
286 reg_iterator reg_begin(Register RegNo) const {
287 return reg_iterator(getRegUseDefListHead(RegNo));
288 }
289 static reg_iterator reg_end() { return reg_iterator(nullptr); }
290
291 inline iterator_range<reg_iterator> reg_operands(Register Reg) const {
292 return make_range(x: reg_begin(RegNo: Reg), y: reg_end());
293 }
294
295 /// reg_instr_iterator/reg_instr_begin/reg_instr_end - Walk all defs and uses
296 /// of the specified register, stepping by MachineInstr.
297 using reg_instr_iterator =
298 defusechain_instr_iterator<true, true, false, /*ByInstr=*/true>;
299 reg_instr_iterator reg_instr_begin(Register RegNo) const {
300 return reg_instr_iterator(getRegUseDefListHead(RegNo));
301 }
302 static reg_instr_iterator reg_instr_end() {
303 return reg_instr_iterator(nullptr);
304 }
305
306 inline iterator_range<reg_instr_iterator>
307 reg_instructions(Register Reg) const {
308 return make_range(x: reg_instr_begin(RegNo: Reg), y: reg_instr_end());
309 }
310
311 /// reg_bundle_iterator/reg_bundle_begin/reg_bundle_end - Walk all defs and uses
312 /// of the specified register, stepping by bundle.
313 using reg_bundle_iterator =
314 defusechain_instr_iterator<true, true, false, /*ByInstr=*/false>;
315 reg_bundle_iterator reg_bundle_begin(Register RegNo) const {
316 return reg_bundle_iterator(getRegUseDefListHead(RegNo));
317 }
318 static reg_bundle_iterator reg_bundle_end() {
319 return reg_bundle_iterator(nullptr);
320 }
321
322 inline iterator_range<reg_bundle_iterator> reg_bundles(Register Reg) const {
323 return make_range(x: reg_bundle_begin(RegNo: Reg), y: reg_bundle_end());
324 }
325
326 /// reg_empty - Return true if there are no instructions using or defining the
327 /// specified register (it may be live-in).
328 bool reg_empty(Register RegNo) const { return reg_begin(RegNo) == reg_end(); }
329
330 /// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses
331 /// of the specified register, skipping those marked as Debug.
332 using reg_nodbg_iterator =
333 defusechain_iterator<true, true, true, true, false>;
334 reg_nodbg_iterator reg_nodbg_begin(Register RegNo) const {
335 return reg_nodbg_iterator(getRegUseDefListHead(RegNo));
336 }
337 static reg_nodbg_iterator reg_nodbg_end() {
338 return reg_nodbg_iterator(nullptr);
339 }
340
341 inline iterator_range<reg_nodbg_iterator>
342 reg_nodbg_operands(Register Reg) const {
343 return make_range(x: reg_nodbg_begin(RegNo: Reg), y: reg_nodbg_end());
344 }
345
346 /// reg_instr_nodbg_iterator/reg_instr_nodbg_begin/reg_instr_nodbg_end - Walk
347 /// all defs and uses of the specified register, stepping by MachineInstr,
348 /// skipping those marked as Debug.
349 using reg_instr_nodbg_iterator =
350 defusechain_instr_iterator<true, true, true, /*ByInstr=*/true>;
351 reg_instr_nodbg_iterator reg_instr_nodbg_begin(Register RegNo) const {
352 return reg_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
353 }
354 static reg_instr_nodbg_iterator reg_instr_nodbg_end() {
355 return reg_instr_nodbg_iterator(nullptr);
356 }
357
358 inline iterator_range<reg_instr_nodbg_iterator>
359 reg_nodbg_instructions(Register Reg) const {
360 return make_range(x: reg_instr_nodbg_begin(RegNo: Reg), y: reg_instr_nodbg_end());
361 }
362
363 /// reg_bundle_nodbg_iterator/reg_bundle_nodbg_begin/reg_bundle_nodbg_end - Walk
364 /// all defs and uses of the specified register, stepping by bundle,
365 /// skipping those marked as Debug.
366 using reg_bundle_nodbg_iterator =
367 defusechain_instr_iterator<true, true, true, /*ByInstr=*/false>;
368 reg_bundle_nodbg_iterator reg_bundle_nodbg_begin(Register RegNo) const {
369 return reg_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
370 }
371 static reg_bundle_nodbg_iterator reg_bundle_nodbg_end() {
372 return reg_bundle_nodbg_iterator(nullptr);
373 }
374
375 inline iterator_range<reg_bundle_nodbg_iterator>
376 reg_nodbg_bundles(Register Reg) const {
377 return make_range(x: reg_bundle_nodbg_begin(RegNo: Reg), y: reg_bundle_nodbg_end());
378 }
379
380 /// reg_nodbg_empty - Return true if the only instructions using or defining
381 /// Reg are Debug instructions.
382 bool reg_nodbg_empty(Register RegNo) const {
383 return reg_nodbg_begin(RegNo) == reg_nodbg_end();
384 }
385
386 /// def_iterator/def_begin/def_end - Walk all defs of the specified register.
387 using def_iterator = defusechain_iterator<false, true, false, true, false>;
388 def_iterator def_begin(Register RegNo) const {
389 return def_iterator(getRegUseDefListHead(RegNo));
390 }
391 static def_iterator def_end() { return def_iterator(nullptr); }
392
393 inline iterator_range<def_iterator> def_operands(Register Reg) const {
394 return make_range(x: def_begin(RegNo: Reg), y: def_end());
395 }
396
397 /// def_instr_iterator/def_instr_begin/def_instr_end - Walk all defs of the
398 /// specified register, stepping by MachineInst.
399 using def_instr_iterator =
400 defusechain_instr_iterator<false, true, false, /*ByInstr=*/true>;
401 def_instr_iterator def_instr_begin(Register RegNo) const {
402 return def_instr_iterator(getRegUseDefListHead(RegNo));
403 }
404 static def_instr_iterator def_instr_end() {
405 return def_instr_iterator(nullptr);
406 }
407
408 inline iterator_range<def_instr_iterator>
409 def_instructions(Register Reg) const {
410 return make_range(x: def_instr_begin(RegNo: Reg), y: def_instr_end());
411 }
412
413 /// def_bundle_iterator/def_bundle_begin/def_bundle_end - Walk all defs of the
414 /// specified register, stepping by bundle.
415 using def_bundle_iterator =
416 defusechain_instr_iterator<false, true, false, /*ByInstr=*/false>;
417 def_bundle_iterator def_bundle_begin(Register RegNo) const {
418 return def_bundle_iterator(getRegUseDefListHead(RegNo));
419 }
420 static def_bundle_iterator def_bundle_end() {
421 return def_bundle_iterator(nullptr);
422 }
423
424 inline iterator_range<def_bundle_iterator> def_bundles(Register Reg) const {
425 return make_range(x: def_bundle_begin(RegNo: Reg), y: def_bundle_end());
426 }
427
428 /// def_empty - Return true if there are no instructions defining the
429 /// specified register (it may be live-in).
430 bool def_empty(Register RegNo) const { return def_begin(RegNo) == def_end(); }
431
432 StringRef getVRegName(Register Reg) const {
433 return VReg2Name.inBounds(n: Reg) ? StringRef(VReg2Name[Reg]) : "";
434 }
435
436 void insertVRegByName(StringRef Name, Register Reg) {
437 assert((Name.empty() || !VRegNames.contains(Name)) &&
438 "Named VRegs Must be Unique.");
439 if (!Name.empty()) {
440 VRegNames.insert(key: Name);
441 VReg2Name.grow(n: Reg);
442 VReg2Name[Reg] = Name.str();
443 }
444 }
445
446 /// Return true if there is exactly one operand defining the specified
447 /// register.
448 bool hasOneDef(Register RegNo) const {
449 return hasSingleElement(C: def_operands(Reg: RegNo));
450 }
451
452 /// Returns the defining operand if there is exactly one operand defining the
453 /// specified register, otherwise nullptr.
454 MachineOperand *getOneDef(Register Reg) const {
455 def_iterator DI = def_begin(RegNo: Reg);
456 if (DI == def_end()) // No defs.
457 return nullptr;
458
459 def_iterator OneDef = DI;
460 if (++DI == def_end())
461 return &*OneDef;
462 return nullptr; // Multiple defs.
463 }
464
465 /// use_iterator/use_begin/use_end - Walk all uses of the specified register.
466 using use_iterator = defusechain_iterator<true, false, false, true, false>;
467 use_iterator use_begin(Register RegNo) const {
468 return use_iterator(getRegUseDefListHead(RegNo));
469 }
470 static use_iterator use_end() { return use_iterator(nullptr); }
471
472 inline iterator_range<use_iterator> use_operands(Register Reg) const {
473 return make_range(x: use_begin(RegNo: Reg), y: use_end());
474 }
475
476 /// use_instr_iterator/use_instr_begin/use_instr_end - Walk all uses of the
477 /// specified register, stepping by MachineInstr.
478 using use_instr_iterator =
479 defusechain_instr_iterator<true, false, false, /*ByInstr=*/true>;
480 use_instr_iterator use_instr_begin(Register RegNo) const {
481 return use_instr_iterator(getRegUseDefListHead(RegNo));
482 }
483 static use_instr_iterator use_instr_end() {
484 return use_instr_iterator(nullptr);
485 }
486
487 inline iterator_range<use_instr_iterator>
488 use_instructions(Register Reg) const {
489 return make_range(x: use_instr_begin(RegNo: Reg), y: use_instr_end());
490 }
491
492 /// use_bundle_iterator/use_bundle_begin/use_bundle_end - Walk all uses of the
493 /// specified register, stepping by bundle.
494 using use_bundle_iterator =
495 defusechain_instr_iterator<true, false, false, /*ByInstr=*/false>;
496 use_bundle_iterator use_bundle_begin(Register RegNo) const {
497 return use_bundle_iterator(getRegUseDefListHead(RegNo));
498 }
499 static use_bundle_iterator use_bundle_end() {
500 return use_bundle_iterator(nullptr);
501 }
502
503 inline iterator_range<use_bundle_iterator> use_bundles(Register Reg) const {
504 return make_range(x: use_bundle_begin(RegNo: Reg), y: use_bundle_end());
505 }
506
507 /// use_empty - Return true if there are no instructions using the specified
508 /// register.
509 bool use_empty(Register RegNo) const { return use_begin(RegNo) == use_end(); }
510
511 /// hasOneUse - Return true if there is exactly one instruction using the
512 /// specified register.
513 bool hasOneUse(Register RegNo) const {
514 return hasSingleElement(C: use_operands(Reg: RegNo));
515 }
516
517 /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the
518 /// specified register, skipping those marked as Debug.
519 using use_nodbg_iterator =
520 defusechain_iterator<true, false, true, true, false>;
521 use_nodbg_iterator use_nodbg_begin(Register RegNo) const {
522 return use_nodbg_iterator(getRegUseDefListHead(RegNo));
523 }
524 static use_nodbg_iterator use_nodbg_end() {
525 return use_nodbg_iterator(nullptr);
526 }
527
528 inline iterator_range<use_nodbg_iterator>
529 use_nodbg_operands(Register Reg) const {
530 return make_range(x: use_nodbg_begin(RegNo: Reg), y: use_nodbg_end());
531 }
532
533 /// use_instr_nodbg_iterator/use_instr_nodbg_begin/use_instr_nodbg_end - Walk
534 /// all uses of the specified register, stepping by MachineInstr, skipping
535 /// those marked as Debug.
536 using use_instr_nodbg_iterator =
537 defusechain_instr_iterator<true, false, true, /*ByInstr=*/true>;
538 use_instr_nodbg_iterator use_instr_nodbg_begin(Register RegNo) const {
539 return use_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
540 }
541 static use_instr_nodbg_iterator use_instr_nodbg_end() {
542 return use_instr_nodbg_iterator(nullptr);
543 }
544
545 inline iterator_range<use_instr_nodbg_iterator>
546 use_nodbg_instructions(Register Reg) const {
547 return make_range(x: use_instr_nodbg_begin(RegNo: Reg), y: use_instr_nodbg_end());
548 }
549
550 /// use_bundle_nodbg_iterator/use_bundle_nodbg_begin/use_bundle_nodbg_end - Walk
551 /// all uses of the specified register, stepping by bundle, skipping
552 /// those marked as Debug.
553 using use_bundle_nodbg_iterator =
554 defusechain_instr_iterator<true, false, true, /*ByInstr=*/false>;
555 use_bundle_nodbg_iterator use_bundle_nodbg_begin(Register RegNo) const {
556 return use_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
557 }
558 static use_bundle_nodbg_iterator use_bundle_nodbg_end() {
559 return use_bundle_nodbg_iterator(nullptr);
560 }
561
562 inline iterator_range<use_bundle_nodbg_iterator>
563 use_nodbg_bundles(Register Reg) const {
564 return make_range(x: use_bundle_nodbg_begin(RegNo: Reg), y: use_bundle_nodbg_end());
565 }
566
567 /// use_nodbg_empty - Return true if there are no non-Debug instructions
568 /// using the specified register.
569 bool use_nodbg_empty(Register RegNo) const {
570 return use_nodbg_begin(RegNo) == use_nodbg_end();
571 }
572
573 /// hasOneNonDBGUse - Return true if there is exactly one non-Debug
574 /// use of the specified register.
575 LLVM_ABI bool hasOneNonDBGUse(Register RegNo) const;
576
577 /// hasOneNonDBGUse - Return true if there is exactly one non-Debug
578 /// instruction using the specified register. Said instruction may have
579 /// multiple uses.
580 LLVM_ABI bool hasOneNonDBGUser(Register RegNo) const;
581
582 /// If the register has a single non-Debug instruction using the specified
583 /// register, returns it; otherwise returns nullptr.
584 LLVM_ABI MachineInstr *getOneNonDBGUser(Register RegNo) const;
585
586 /// hasAtMostUses - Return true if the given register has at most \p MaxUsers
587 /// non-debug user instructions.
588 LLVM_ABI bool hasAtMostUserInstrs(Register Reg, unsigned MaxUsers) const;
589
590 /// replaceRegWith - Replace all instances of FromReg with ToReg in the
591 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
592 /// except that it also changes any definitions of the register as well.
593 ///
594 /// Note that it is usually necessary to first constrain ToReg's register
595 /// class and register bank to match the FromReg constraints using one of the
596 /// methods:
597 ///
598 /// constrainRegClass(ToReg, getRegClass(FromReg))
599 /// constrainRegAttrs(ToReg, FromReg)
600 /// RegisterBankInfo::constrainGenericRegister(ToReg,
601 /// *MRI.getRegClass(FromReg), MRI)
602 ///
603 /// These functions will return a falsy result if the virtual registers have
604 /// incompatible constraints.
605 ///
606 /// Note that if ToReg is a physical register the function will replace and
607 /// apply sub registers to ToReg in order to obtain a final/proper physical
608 /// register.
609 LLVM_ABI void replaceRegWith(Register FromReg, Register ToReg);
610
611 /// getVRegDef - Return the machine instr that defines the specified virtual
612 /// register or null if none is found. This assumes that the code is in SSA
613 /// form, so there should only be one definition.
614 LLVM_ABI MachineInstr *getVRegDef(Register Reg) const;
615
616 /// getUniqueVRegDef - Return the unique machine instr that defines the
617 /// specified virtual register or null if none is found. If there are
618 /// multiple definitions or no definition, return null.
619 LLVM_ABI MachineInstr *getUniqueVRegDef(Register Reg) const;
620
621 /// clearKillFlags - Iterate over all the uses of the given register and
622 /// clear the kill flag from the MachineOperand. This function is used by
623 /// optimization passes which extend register lifetimes and need only
624 /// preserve conservative kill flag information.
625 LLVM_ABI void clearKillFlags(Register Reg) const;
626
627 LLVM_ABI void dumpUses(Register RegNo) const;
628
629 /// Returns true if PhysReg is unallocatable and constant throughout the
630 /// function. Writing to a constant register has no effect.
631 LLVM_ABI bool isConstantPhysReg(MCRegister PhysReg) const;
632
633 /// Get an iterator over the pressure sets affected by the given physical or
634 /// virtual register. If RegUnit is physical, it must be a register unit (from
635 /// MCRegUnitIterator).
636 PSetIterator getPressureSets(Register RegUnit) const;
637
638 //===--------------------------------------------------------------------===//
639 // Virtual Register Info
640 //===--------------------------------------------------------------------===//
641
642 /// Return the register class of the specified virtual register.
643 /// This shouldn't be used directly unless \p Reg has a register class.
644 /// \see getRegClassOrNull when this might happen.
645 const TargetRegisterClass *getRegClass(Register Reg) const {
646 assert(isa<const TargetRegisterClass *>(VRegInfo[Reg.id()].first) &&
647 "Register class not set, wrong accessor");
648 return cast<const TargetRegisterClass *>(Val: VRegInfo[Reg.id()].first);
649 }
650
651 /// Return the register class of \p Reg, or null if Reg has not been assigned
652 /// a register class yet.
653 ///
654 /// \note A null register class can only happen when these two
655 /// conditions are met:
656 /// 1. Generic virtual registers are created.
657 /// 2. The machine function has not completely been through the
658 /// instruction selection process.
659 /// None of this condition is possible without GlobalISel for now.
660 /// In other words, if GlobalISel is not used or if the query happens after
661 /// the select pass, using getRegClass is safe.
662 const TargetRegisterClass *getRegClassOrNull(Register Reg) const {
663 const RegClassOrRegBank &Val = VRegInfo[Reg].first;
664 return dyn_cast_if_present<const TargetRegisterClass *>(Val);
665 }
666
667 /// Return the register bank of \p Reg.
668 /// This shouldn't be used directly unless \p Reg has a register bank.
669 const RegisterBank *getRegBank(Register Reg) const {
670 return cast<const RegisterBank *>(Val: VRegInfo[Reg.id()].first);
671 }
672
673 /// Return the register bank of \p Reg, or null if Reg has not been assigned
674 /// a register bank or has been assigned a register class.
675 /// \note It is possible to get the register bank from the register class via
676 /// RegisterBankInfo::getRegBankFromRegClass.
677 const RegisterBank *getRegBankOrNull(Register Reg) const {
678 const RegClassOrRegBank &Val = VRegInfo[Reg].first;
679 return dyn_cast_if_present<const RegisterBank *>(Val);
680 }
681
682 /// Return the register bank or register class of \p Reg.
683 /// \note Before the register bank gets assigned (i.e., before the
684 /// RegBankSelect pass) \p Reg may not have either.
685 const RegClassOrRegBank &getRegClassOrRegBank(Register Reg) const {
686 return VRegInfo[Reg].first;
687 }
688
689 /// setRegClass - Set the register class of the specified virtual register.
690 LLVM_ABI void setRegClass(Register Reg, const TargetRegisterClass *RC);
691
692 /// Set the register bank to \p RegBank for \p Reg.
693 LLVM_ABI void setRegBank(Register Reg, const RegisterBank &RegBank);
694
695 void setRegClassOrRegBank(Register Reg,
696 const RegClassOrRegBank &RCOrRB){
697 VRegInfo[Reg].first = RCOrRB;
698 }
699
700 /// constrainRegClass - Constrain the register class of the specified virtual
701 /// register to be a common subclass of RC and the current register class,
702 /// but only if the new class has at least MinNumRegs registers. Return the
703 /// new register class, or NULL if no such class exists.
704 /// This should only be used when the constraint is known to be trivial, like
705 /// GR32 -> GR32_NOSP. Beware of increasing register pressure.
706 ///
707 /// \note Assumes that the register has a register class assigned.
708 /// Use RegisterBankInfo::constrainGenericRegister in GlobalISel's
709 /// InstructionSelect pass and constrainRegAttrs in every other pass,
710 /// including non-select passes of GlobalISel, instead.
711 LLVM_ABI const TargetRegisterClass *
712 constrainRegClass(Register Reg, const TargetRegisterClass *RC,
713 unsigned MinNumRegs = 0);
714
715 /// Constrain the register class or the register bank of the virtual register
716 /// \p Reg (and low-level type) to be a common subclass or a common bank of
717 /// both registers provided respectively (and a common low-level type). Do
718 /// nothing if any of the attributes (classes, banks, or low-level types) of
719 /// the registers are deemed incompatible, or if the resulting register will
720 /// have a class smaller than before and of size less than \p MinNumRegs.
721 /// Return true if such register attributes exist, false otherwise.
722 ///
723 /// \note Use this method instead of constrainRegClass and
724 /// RegisterBankInfo::constrainGenericRegister everywhere but SelectionDAG
725 /// ISel / FastISel and GlobalISel's InstructionSelect pass respectively.
726 LLVM_ABI bool constrainRegAttrs(Register Reg, Register ConstrainingReg,
727 unsigned MinNumRegs = 0);
728
729 /// recomputeRegClass - Try to find a legal super-class of Reg's register
730 /// class that still satisfies the constraints from the instructions using
731 /// Reg. Returns true if Reg was upgraded.
732 ///
733 /// This method can be used after constraints have been removed from a
734 /// virtual register, for example after removing instructions or splitting
735 /// the live range.
736 LLVM_ABI bool recomputeRegClass(Register Reg);
737
738 /// createVirtualRegister - Create and return a new virtual register in the
739 /// function with the specified register class.
740 LLVM_ABI Register createVirtualRegister(const TargetRegisterClass *RegClass,
741 StringRef Name = "");
742
743 /// All attributes(register class or bank and low-level type) a virtual
744 /// register can have.
745 struct VRegAttrs {
746 RegClassOrRegBank RCOrRB;
747 LLT Ty;
748 };
749
750 /// Returns register class or bank and low level type of \p Reg. Always safe
751 /// to use. Special values are returned when \p Reg does not have some of the
752 /// attributes.
753 VRegAttrs getVRegAttrs(Register Reg) const {
754 return {.RCOrRB: getRegClassOrRegBank(Reg), .Ty: getType(Reg)};
755 }
756
757 /// Create and return a new virtual register in the function with the
758 /// specified register attributes(register class or bank and low level type).
759 LLVM_ABI Register createVirtualRegister(VRegAttrs RegAttr,
760 StringRef Name = "");
761
762 /// Create and return a new virtual register in the function with the same
763 /// attributes as the given register.
764 LLVM_ABI Register cloneVirtualRegister(Register VReg, StringRef Name = "");
765
766 /// Get the low-level type of \p Reg or LLT{} if Reg is not a generic
767 /// (target independent) virtual register.
768 LLT getType(Register Reg) const {
769 if (Reg.isVirtual() && VRegToType.inBounds(n: Reg))
770 return VRegToType[Reg];
771 return LLT{};
772 }
773
774 /// Set the low-level type of \p VReg to \p Ty.
775 LLVM_ABI void setType(Register VReg, LLT Ty);
776
777 /// Create and return a new generic virtual register with low-level
778 /// type \p Ty.
779 LLVM_ABI Register createGenericVirtualRegister(LLT Ty, StringRef Name = "");
780
781 /// Remove all types associated to virtual registers (after instruction
782 /// selection and constraining of all generic virtual registers).
783 LLVM_ABI void clearVirtRegTypes();
784
785 /// Creates a new virtual register that has no register class, register bank
786 /// or size assigned yet. This is only allowed to be used
787 /// temporarily while constructing machine instructions. Most operations are
788 /// undefined on an incomplete register until one of setRegClass(),
789 /// setRegBank() or setSize() has been called on it.
790 LLVM_ABI Register createIncompleteVirtualRegister(StringRef Name = "");
791
792 /// getNumVirtRegs - Return the number of virtual registers created.
793 unsigned getNumVirtRegs() const { return VRegInfo.size(); }
794
795 /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
796 LLVM_ABI void clearVirtRegs();
797
798 /// setRegAllocationHint - Specify a register allocation hint for the
799 /// specified virtual register. This is typically used by target, and in case
800 /// of an earlier hint it will be overwritten.
801 void setRegAllocationHint(Register VReg, unsigned Type, Register PrefReg) {
802 assert(VReg.isVirtual());
803 RegAllocHints.grow(n: Register::index2VirtReg(Index: getNumVirtRegs()));
804 auto &Hint = RegAllocHints[VReg];
805 Hint.first = Type;
806 Hint.second.clear();
807 Hint.second.push_back(Elt: PrefReg);
808 }
809
810 /// addRegAllocationHint - Add a register allocation hint to the hints
811 /// vector for VReg.
812 void addRegAllocationHint(Register VReg, Register PrefReg) {
813 assert(VReg.isVirtual());
814 RegAllocHints.grow(n: Register::index2VirtReg(Index: getNumVirtRegs()));
815 RegAllocHints[VReg].second.push_back(Elt: PrefReg);
816 }
817
818 /// Specify the preferred (target independent) register allocation hint for
819 /// the specified virtual register.
820 void setSimpleHint(Register VReg, Register PrefReg) {
821 setRegAllocationHint(VReg, /*Type=*/Type: 0, PrefReg);
822 }
823
824 void clearSimpleHint(Register VReg) {
825 assert (!RegAllocHints[VReg].first &&
826 "Expected to clear a non-target hint!");
827 if (RegAllocHints.inBounds(n: VReg))
828 RegAllocHints[VReg].second.clear();
829 }
830
831 /// getRegAllocationHint - Return the register allocation hint for the
832 /// specified virtual register. If there are many hints, this returns the
833 /// one with the greatest weight.
834 std::pair<unsigned, Register> getRegAllocationHint(Register VReg) const {
835 assert(VReg.isVirtual());
836 if (!RegAllocHints.inBounds(n: VReg))
837 return {0, Register()};
838 auto &Hint = RegAllocHints[VReg.id()];
839 Register BestHint = (Hint.second.size() ? Hint.second[0] : Register());
840 return {Hint.first, BestHint};
841 }
842
843 /// getSimpleHint - same as getRegAllocationHint except it will only return
844 /// a target independent hint.
845 Register getSimpleHint(Register VReg) const {
846 assert(VReg.isVirtual());
847 std::pair<unsigned, Register> Hint = getRegAllocationHint(VReg);
848 return Hint.first ? Register() : Hint.second;
849 }
850
851 /// getRegAllocationHints - Return a reference to the vector of all
852 /// register allocation hints for VReg.
853 const std::pair<unsigned, SmallVector<Register, 4>> *
854 getRegAllocationHints(Register VReg) const {
855 assert(VReg.isVirtual());
856 return RegAllocHints.inBounds(n: VReg) ? &RegAllocHints[VReg] : nullptr;
857 }
858
859 /// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the
860 /// specified register as undefined which causes the DBG_VALUE to be
861 /// deleted during LiveDebugVariables analysis.
862 LLVM_ABI void markUsesInDebugValueAsUndef(Register Reg) const;
863
864 /// updateDbgUsersToReg - Update a collection of debug instructions
865 /// to refer to the designated register.
866 void updateDbgUsersToReg(MCRegister OldReg, MCRegister NewReg,
867 ArrayRef<MachineInstr *> Users) const {
868 // If this operand is a register, check whether it overlaps with OldReg.
869 // If it does, replace with NewReg.
870 auto UpdateOp = [this, &NewReg, &OldReg](MachineOperand &Op) {
871 if (Op.isReg() &&
872 getTargetRegisterInfo()->regsOverlap(RegA: Op.getReg(), RegB: OldReg))
873 Op.setReg(NewReg);
874 };
875
876 // Iterate through (possibly several) operands to DBG_VALUEs and update
877 // each. For DBG_PHIs, only one operand will be present.
878 for (MachineInstr *MI : Users) {
879 if (MI->isDebugValue()) {
880 for (auto &Op : MI->debug_operands())
881 UpdateOp(Op);
882 assert(MI->hasDebugOperandForReg(NewReg) &&
883 "Expected debug value to have some overlap with OldReg");
884 } else if (MI->isDebugPHI()) {
885 UpdateOp(MI->getOperand(i: 0));
886 } else {
887 llvm_unreachable("Non-DBG_VALUE, Non-DBG_PHI debug instr updated");
888 }
889 }
890 }
891
892 /// Return true if the specified register is modified in this function.
893 /// This checks that no defining machine operands exist for the register or
894 /// any of its aliases. Definitions found on functions marked noreturn are
895 /// ignored, to consider them pass 'true' for optional parameter
896 /// SkipNoReturnDef. The register is also considered modified when it is set
897 /// in the UsedPhysRegMask.
898 LLVM_ABI bool isPhysRegModified(MCRegister PhysReg,
899 bool SkipNoReturnDef = false) const;
900
901 /// Return true if the specified register is modified or read in this
902 /// function. This checks that no machine operands exist for the register or
903 /// any of its aliases. If SkipRegMaskTest is false, the register is
904 /// considered used when it is set in the UsedPhysRegMask.
905 LLVM_ABI bool isPhysRegUsed(MCRegister PhysReg,
906 bool SkipRegMaskTest = false) const;
907
908 /// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
909 /// This corresponds to the bit mask attached to register mask operands.
910 void addPhysRegsUsedFromRegMask(const uint32_t *RegMask) {
911 UsedPhysRegMask.setBitsNotInMask(Mask: RegMask);
912 }
913
914 const BitVector &getUsedPhysRegsMask() const { return UsedPhysRegMask; }
915
916 //===--------------------------------------------------------------------===//
917 // Reserved Register Info
918 //===--------------------------------------------------------------------===//
919 //
920 // The set of reserved registers must be invariant during register
921 // allocation. For example, the target cannot suddenly decide it needs a
922 // frame pointer when the register allocator has already used the frame
923 // pointer register for something else.
924 //
925 // These methods can be used by target hooks like hasFP() to avoid changing
926 // the reserved register set during register allocation.
927
928 /// freezeReservedRegs - Called by the register allocator to freeze the set
929 /// of reserved registers before allocation begins.
930 LLVM_ABI void freezeReservedRegs();
931
932 /// reserveReg -- Mark a register as reserved so checks like isAllocatable
933 /// will not suggest using it. This should not be used during the middle
934 /// of a function walk, or when liveness info is available.
935 void reserveReg(MCRegister PhysReg, const TargetRegisterInfo *TRI) {
936 assert(reservedRegsFrozen() &&
937 "Reserved registers haven't been frozen yet. ");
938 MCRegAliasIterator R(PhysReg, TRI, true);
939
940 for (; R.isValid(); ++R)
941 ReservedRegs.set((*R).id());
942 }
943
944 /// reservedRegsFrozen - Returns true after freezeReservedRegs() was called
945 /// to ensure the set of reserved registers stays constant.
946 bool reservedRegsFrozen() const {
947 return !ReservedRegs.empty();
948 }
949
950 /// canReserveReg - Returns true if PhysReg can be used as a reserved
951 /// register. Any register can be reserved before freezeReservedRegs() is
952 /// called.
953 bool canReserveReg(MCRegister PhysReg) const {
954 return !reservedRegsFrozen() || ReservedRegs.test(Idx: PhysReg.id());
955 }
956
957 /// getReservedRegs - Returns a reference to the frozen set of reserved
958 /// registers. This method should always be preferred to calling
959 /// TRI::getReservedRegs() when possible.
960 const BitVector &getReservedRegs() const {
961 assert(reservedRegsFrozen() &&
962 "Reserved registers haven't been frozen yet. "
963 "Use TRI::getReservedRegs().");
964 return ReservedRegs;
965 }
966
967 /// isReserved - Returns true when PhysReg is a reserved register.
968 ///
969 /// Reserved registers may belong to an allocatable register class, but the
970 /// target has explicitly requested that they are not used.
971 bool isReserved(MCRegister PhysReg) const {
972 return getReservedRegs().test(Idx: PhysReg.id());
973 }
974
975 /// Returns true when the given register unit is considered reserved.
976 ///
977 /// Register units are considered reserved when for at least one of their
978 /// root registers, the root register and all super registers are reserved.
979 /// This currently iterates the register hierarchy and may be slower than
980 /// expected.
981 LLVM_ABI bool isReservedRegUnit(unsigned Unit) const;
982
983 /// isAllocatable - Returns true when PhysReg belongs to an allocatable
984 /// register class and it hasn't been reserved.
985 ///
986 /// Allocatable registers may show up in the allocation order of some virtual
987 /// register, so a register allocator needs to track its liveness and
988 /// availability.
989 bool isAllocatable(MCRegister PhysReg) const {
990 return getTargetRegisterInfo()->isInAllocatableClass(RegNo: PhysReg) &&
991 !isReserved(PhysReg);
992 }
993
994 //===--------------------------------------------------------------------===//
995 // LiveIn Management
996 //===--------------------------------------------------------------------===//
997
998 /// addLiveIn - Add the specified register as a live-in. Note that it
999 /// is an error to add the same register to the same set more than once.
1000 void addLiveIn(MCRegister Reg, Register vreg = Register()) {
1001 LiveIns.push_back(x: std::make_pair(x&: Reg, y&: vreg));
1002 }
1003
1004 // Iteration support for the live-ins set. It's kept in sorted order
1005 // by register number.
1006 using livein_iterator =
1007 std::vector<std::pair<MCRegister,Register>>::const_iterator;
1008 livein_iterator livein_begin() const { return LiveIns.begin(); }
1009 livein_iterator livein_end() const { return LiveIns.end(); }
1010 bool livein_empty() const { return LiveIns.empty(); }
1011
1012 ArrayRef<std::pair<MCRegister, Register>> liveins() const {
1013 return LiveIns;
1014 }
1015
1016 LLVM_ABI bool isLiveIn(Register Reg) const;
1017
1018 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
1019 /// corresponding live-in physical register.
1020 LLVM_ABI MCRegister getLiveInPhysReg(Register VReg) const;
1021
1022 /// getLiveInVirtReg - If PReg is a live-in physical register, return the
1023 /// corresponding live-in virtual register.
1024 LLVM_ABI Register getLiveInVirtReg(MCRegister PReg) const;
1025
1026 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
1027 /// into the given entry block.
1028 LLVM_ABI void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
1029 const TargetRegisterInfo &TRI,
1030 const TargetInstrInfo &TII);
1031
1032 /// Returns a mask covering all bits that can appear in lane masks of
1033 /// subregisters of the virtual register @p Reg.
1034 LLVM_ABI LaneBitmask getMaxLaneMaskForVReg(Register Reg) const;
1035
1036 /// defusechain_iterator - This class provides iterator support for machine
1037 /// operands in the function that use or define a specific register. If
1038 /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
1039 /// returns defs. If neither are true then you are silly and it always
1040 /// returns end(). If SkipDebug is true it skips uses marked Debug
1041 /// when incrementing.
1042 template <bool ReturnUses, bool ReturnDefs, bool SkipDebug, bool ByOperand,
1043 bool ByInstr>
1044 class defusechain_iterator {
1045 friend class MachineRegisterInfo;
1046 static_assert(!ByOperand || !ByInstr,
1047 "ByOperand and ByInstr are mutually exclusive");
1048
1049 public:
1050 using iterator_category = std::forward_iterator_tag;
1051 using value_type = MachineOperand;
1052 using difference_type = std::ptrdiff_t;
1053 using pointer = value_type *;
1054 using reference = value_type &;
1055
1056 private:
1057 MachineOperand *Op = nullptr;
1058
1059 explicit defusechain_iterator(MachineOperand *op) : Op(op) {
1060 // If the first node isn't one we're interested in, advance to one that
1061 // we are interested in.
1062 if (op) {
1063 if ((!ReturnUses && op->isUse()) ||
1064 (!ReturnDefs && op->isDef()) ||
1065 (SkipDebug && op->isDebug()))
1066 advance();
1067 }
1068 }
1069
1070 void advance() {
1071 assert(Op && "Cannot increment end iterator!");
1072 Op = getNextOperandForReg(MO: Op);
1073
1074 // All defs come before the uses, so stop def_iterator early.
1075 if (!ReturnUses) {
1076 if (Op) {
1077 if (Op->isUse())
1078 Op = nullptr;
1079 else
1080 assert(!Op->isDebug() && "Can't have debug defs");
1081 }
1082 } else {
1083 // If this is an operand we don't care about, skip it.
1084 while (Op && ((!ReturnDefs && Op->isDef()) ||
1085 (SkipDebug && Op->isDebug())))
1086 Op = getNextOperandForReg(MO: Op);
1087 }
1088 }
1089
1090 public:
1091 defusechain_iterator() = default;
1092
1093 bool operator==(const defusechain_iterator &x) const {
1094 return Op == x.Op;
1095 }
1096 bool operator!=(const defusechain_iterator &x) const {
1097 return !operator==(x);
1098 }
1099
1100 // Iterator traversal: forward iteration only
1101 defusechain_iterator &operator++() { // Preincrement
1102 assert(Op && "Cannot increment end iterator!");
1103 if (ByOperand)
1104 advance();
1105 else if (ByInstr) {
1106 MachineInstr *P = Op->getParent();
1107 do {
1108 advance();
1109 } while (Op && Op->getParent() == P);
1110 } else {
1111 MachineBasicBlock::instr_iterator P =
1112 getBundleStart(I: Op->getParent()->getIterator());
1113 do {
1114 advance();
1115 } while (Op && getBundleStart(I: Op->getParent()->getIterator()) == P);
1116 }
1117
1118 return *this;
1119 }
1120 defusechain_iterator operator++(int) { // Postincrement
1121 defusechain_iterator tmp = *this; ++*this; return tmp;
1122 }
1123
1124 /// getOperandNo - Return the operand # of this MachineOperand in its
1125 /// MachineInstr.
1126 unsigned getOperandNo() const {
1127 assert(Op && "Cannot dereference end iterator!");
1128 return Op - &Op->getParent()->getOperand(i: 0);
1129 }
1130
1131 // Retrieve a reference to the current operand.
1132 MachineOperand &operator*() const {
1133 assert(Op && "Cannot dereference end iterator!");
1134 return *Op;
1135 }
1136
1137 MachineOperand *operator->() const {
1138 assert(Op && "Cannot dereference end iterator!");
1139 return Op;
1140 }
1141 };
1142
1143 /// defusechain_iterator - This class provides iterator support for machine
1144 /// operands in the function that use or define a specific register. If
1145 /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
1146 /// returns defs. If neither are true then you are silly and it always
1147 /// returns end(). If SkipDebug is true it skips uses marked Debug
1148 /// when incrementing.
1149 template <bool ReturnUses, bool ReturnDefs, bool SkipDebug, bool ByInstr>
1150 class defusechain_instr_iterator {
1151 friend class MachineRegisterInfo;
1152
1153 public:
1154 using iterator_category = std::forward_iterator_tag;
1155 using value_type = MachineInstr;
1156 using difference_type = std::ptrdiff_t;
1157 using pointer = value_type *;
1158 using reference = value_type &;
1159
1160 private:
1161 MachineOperand *Op = nullptr;
1162
1163 explicit defusechain_instr_iterator(MachineOperand *op) : Op(op) {
1164 // If the first node isn't one we're interested in, advance to one that
1165 // we are interested in.
1166 if (op) {
1167 if ((!ReturnUses && op->isUse()) ||
1168 (!ReturnDefs && op->isDef()) ||
1169 (SkipDebug && op->isDebug()))
1170 advance();
1171 }
1172 }
1173
1174 void advance() {
1175 assert(Op && "Cannot increment end iterator!");
1176 Op = getNextOperandForReg(MO: Op);
1177
1178 // All defs come before the uses, so stop def_iterator early.
1179 if (!ReturnUses) {
1180 if (Op) {
1181 if (Op->isUse())
1182 Op = nullptr;
1183 else
1184 assert(!Op->isDebug() && "Can't have debug defs");
1185 }
1186 } else {
1187 // If this is an operand we don't care about, skip it.
1188 while (Op && ((!ReturnDefs && Op->isDef()) ||
1189 (SkipDebug && Op->isDebug())))
1190 Op = getNextOperandForReg(MO: Op);
1191 }
1192 }
1193
1194 public:
1195 defusechain_instr_iterator() = default;
1196
1197 bool operator==(const defusechain_instr_iterator &x) const {
1198 return Op == x.Op;
1199 }
1200 bool operator!=(const defusechain_instr_iterator &x) const {
1201 return !operator==(x);
1202 }
1203
1204 // Iterator traversal: forward iteration only
1205 defusechain_instr_iterator &operator++() { // Preincrement
1206 assert(Op && "Cannot increment end iterator!");
1207 if (ByInstr) {
1208 MachineInstr *P = Op->getParent();
1209 do {
1210 advance();
1211 } while (Op && Op->getParent() == P);
1212 } else {
1213 MachineBasicBlock::instr_iterator P =
1214 getBundleStart(I: Op->getParent()->getIterator());
1215 do {
1216 advance();
1217 } while (Op && getBundleStart(I: Op->getParent()->getIterator()) == P);
1218 }
1219
1220 return *this;
1221 }
1222 defusechain_instr_iterator operator++(int) { // Postincrement
1223 defusechain_instr_iterator tmp = *this; ++*this; return tmp;
1224 }
1225
1226 // Retrieve a reference to the current operand.
1227 MachineInstr &operator*() const {
1228 assert(Op && "Cannot dereference end iterator!");
1229 if (!ByInstr)
1230 return *getBundleStart(I: Op->getParent()->getIterator());
1231 return *Op->getParent();
1232 }
1233
1234 MachineInstr *operator->() const { return &operator*(); }
1235 };
1236};
1237
1238/// Iterate over the pressure sets affected by the given physical or virtual
1239/// register. If Reg is physical, it must be a register unit (from
1240/// MCRegUnitIterator).
1241class PSetIterator {
1242 const int *PSet = nullptr;
1243 unsigned Weight = 0;
1244
1245public:
1246 PSetIterator() = default;
1247
1248 PSetIterator(Register RegUnit, const MachineRegisterInfo *MRI) {
1249 const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();
1250 if (RegUnit.isVirtual()) {
1251 const TargetRegisterClass *RC = MRI->getRegClass(Reg: RegUnit);
1252 PSet = TRI->getRegClassPressureSets(RC);
1253 Weight = TRI->getRegClassWeight(RC).RegWeight;
1254 } else {
1255 PSet = TRI->getRegUnitPressureSets(RegUnit);
1256 Weight = TRI->getRegUnitWeight(RegUnit);
1257 }
1258 if (*PSet == -1)
1259 PSet = nullptr;
1260 }
1261
1262 bool isValid() const { return PSet; }
1263
1264 unsigned getWeight() const { return Weight; }
1265
1266 unsigned operator*() const { return *PSet; }
1267
1268 void operator++() {
1269 assert(isValid() && "Invalid PSetIterator.");
1270 ++PSet;
1271 if (*PSet == -1)
1272 PSet = nullptr;
1273 }
1274};
1275
1276inline PSetIterator
1277MachineRegisterInfo::getPressureSets(Register RegUnit) const {
1278 return PSetIterator(RegUnit, this);
1279}
1280
1281} // end namespace llvm
1282
1283#endif // LLVM_CODEGEN_MACHINEREGISTERINFO_H
1284