1//===---------------------- ProcessImplicitDefs.cpp -----------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "llvm/ADT/SetVector.h"
10#include "llvm/Analysis/AliasAnalysis.h"
11#include "llvm/CodeGen/MachineFunctionPass.h"
12#include "llvm/CodeGen/MachineInstr.h"
13#include "llvm/CodeGen/MachineRegisterInfo.h"
14#include "llvm/CodeGen/TargetInstrInfo.h"
15#include "llvm/CodeGen/TargetSubtargetInfo.h"
16#include "llvm/InitializePasses.h"
17#include "llvm/Pass.h"
18#include "llvm/PassRegistry.h"
19#include "llvm/Support/Debug.h"
20#include "llvm/Support/raw_ostream.h"
21
22using namespace llvm;
23
24#define DEBUG_TYPE "processimpdefs"
25
26namespace {
27/// Process IMPLICIT_DEF instructions and make sure there is one implicit_def
28/// for each use. Add isUndef marker to implicit_def defs and their uses.
29class ProcessImplicitDefs : public MachineFunctionPass {
30 const TargetInstrInfo *TII = nullptr;
31 const TargetRegisterInfo *TRI = nullptr;
32 MachineRegisterInfo *MRI = nullptr;
33
34 SmallSetVector<MachineInstr*, 16> WorkList;
35
36 void processImplicitDef(MachineInstr *MI);
37 bool canTurnIntoImplicitDef(MachineInstr *MI);
38
39public:
40 static char ID;
41
42 ProcessImplicitDefs() : MachineFunctionPass(ID) {
43 initializeProcessImplicitDefsPass(*PassRegistry::getPassRegistry());
44 }
45
46 void getAnalysisUsage(AnalysisUsage &au) const override;
47
48 bool runOnMachineFunction(MachineFunction &MF) override;
49
50 MachineFunctionProperties getRequiredProperties() const override {
51 return MachineFunctionProperties().setIsSSA();
52 }
53};
54} // end anonymous namespace
55
56char ProcessImplicitDefs::ID = 0;
57char &llvm::ProcessImplicitDefsID = ProcessImplicitDefs::ID;
58
59INITIALIZE_PASS(ProcessImplicitDefs, DEBUG_TYPE,
60 "Process Implicit Definitions", false, false)
61
62void ProcessImplicitDefs::getAnalysisUsage(AnalysisUsage &AU) const {
63 AU.setPreservesCFG();
64 AU.addPreserved<AAResultsWrapperPass>();
65 MachineFunctionPass::getAnalysisUsage(AU);
66}
67
68bool ProcessImplicitDefs::canTurnIntoImplicitDef(MachineInstr *MI) {
69 if (!MI->isCopyLike() &&
70 !MI->isInsertSubreg() &&
71 !MI->isRegSequence() &&
72 !MI->isPHI())
73 return false;
74 for (const MachineOperand &MO : MI->all_uses())
75 if (MO.readsReg())
76 return false;
77 return true;
78}
79
80void ProcessImplicitDefs::processImplicitDef(MachineInstr *MI) {
81 LLVM_DEBUG(dbgs() << "Processing " << *MI);
82 Register Reg = MI->getOperand(i: 0).getReg();
83
84 if (Reg.isVirtual()) {
85 // For virtual registers, mark all uses as <undef>, and convert users to
86 // implicit-def when possible.
87 for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
88 MO.setIsUndef();
89 MachineInstr *UserMI = MO.getParent();
90 if (!canTurnIntoImplicitDef(MI: UserMI))
91 continue;
92 LLVM_DEBUG(dbgs() << "Converting to IMPLICIT_DEF: " << *UserMI);
93 UserMI->setDesc(TII->get(Opcode: TargetOpcode::IMPLICIT_DEF));
94 WorkList.insert(X: UserMI);
95 }
96 MI->eraseFromParent();
97 return;
98 }
99
100 // This is a physreg implicit-def.
101 // Look for the first instruction to use or define an alias.
102 MachineBasicBlock::instr_iterator UserMI = MI->getIterator();
103 MachineBasicBlock::instr_iterator UserE = MI->getParent()->instr_end();
104 bool Found = false;
105 for (++UserMI; UserMI != UserE; ++UserMI) {
106 for (MachineOperand &MO : UserMI->operands()) {
107 if (!MO.isReg())
108 continue;
109 Register UserReg = MO.getReg();
110 if (!UserReg.isPhysical() || !TRI->regsOverlap(RegA: Reg, RegB: UserReg))
111 continue;
112 // UserMI uses or redefines Reg. Set <undef> flags on all uses.
113 Found = true;
114 if (MO.isUse())
115 MO.setIsUndef();
116 }
117 if (Found)
118 break;
119 }
120
121 // If we found the using MI, we can erase the IMPLICIT_DEF.
122 if (Found) {
123 LLVM_DEBUG(dbgs() << "Physreg user: " << *UserMI);
124 MI->eraseFromParent();
125 return;
126 }
127
128 // Using instr wasn't found, it could be in another block.
129 // Leave the physreg IMPLICIT_DEF, but trim any extra operands.
130 for (unsigned i = MI->getNumOperands() - 1; i; --i)
131 MI->removeOperand(OpNo: i);
132 LLVM_DEBUG(dbgs() << "Keeping physreg: " << *MI);
133}
134
135/// processImplicitDefs - Process IMPLICIT_DEF instructions and turn them into
136/// <undef> operands.
137bool ProcessImplicitDefs::runOnMachineFunction(MachineFunction &MF) {
138
139 LLVM_DEBUG(dbgs() << "********** PROCESS IMPLICIT DEFS **********\n"
140 << "********** Function: " << MF.getName() << '\n');
141
142 bool Changed = false;
143
144 TII = MF.getSubtarget().getInstrInfo();
145 TRI = MF.getSubtarget().getRegisterInfo();
146 MRI = &MF.getRegInfo();
147 assert(WorkList.empty() && "Inconsistent worklist state");
148
149 for (MachineBasicBlock &MBB : MF) {
150 // Scan the basic block for implicit defs.
151 for (MachineInstr &MI : MBB)
152 if (MI.isImplicitDef())
153 WorkList.insert(X: &MI);
154
155 if (WorkList.empty())
156 continue;
157
158 LLVM_DEBUG(dbgs() << printMBBReference(MBB) << " has " << WorkList.size()
159 << " implicit defs.\n");
160 Changed = true;
161
162 // Drain the WorkList to recursively process any new implicit defs.
163 do processImplicitDef(MI: WorkList.pop_back_val());
164 while (!WorkList.empty());
165 }
166 return Changed;
167}
168