1//===---------------------------- Context.cpp -------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9///
10/// This file defines a class for holding ownership of various simulated
11/// hardware units. A Context also provides a utility routine for constructing
12/// a default out-of-order pipeline with fetch, dispatch, execute, and retire
13/// stages.
14///
15//===----------------------------------------------------------------------===//
16
17#include "llvm/MCA/Context.h"
18#include "llvm/MCA/HardwareUnits/RegisterFile.h"
19#include "llvm/MCA/HardwareUnits/RetireControlUnit.h"
20#include "llvm/MCA/HardwareUnits/Scheduler.h"
21#include "llvm/MCA/Stages/DispatchStage.h"
22#include "llvm/MCA/Stages/EntryStage.h"
23#include "llvm/MCA/Stages/ExecuteStage.h"
24#include "llvm/MCA/Stages/InOrderIssueStage.h"
25#include "llvm/MCA/Stages/MicroOpQueueStage.h"
26#include "llvm/MCA/Stages/RetireStage.h"
27
28namespace llvm {
29namespace mca {
30
31std::unique_ptr<Pipeline>
32Context::createDefaultPipeline(const PipelineOptions &Opts, SourceMgr &SrcMgr,
33 CustomBehaviour &CB) {
34 const MCSchedModel &SM = STI.getSchedModel();
35
36 if (!SM.isOutOfOrder())
37 return createInOrderPipeline(Opts, SrcMgr, CB);
38
39 // Create the hardware units defining the backend.
40 auto RCU = std::make_unique<RetireControlUnit>(args: SM);
41 auto PRF = std::make_unique<RegisterFile>(args: SM, args: MRI, args: Opts.RegisterFileSize);
42 auto LSU = std::make_unique<LSUnit>(args: SM, args: Opts.LoadQueueSize,
43 args: Opts.StoreQueueSize, args: Opts.AssumeNoAlias);
44 auto HWS = std::make_unique<Scheduler>(args: SM, args&: *LSU);
45
46 // Create the pipeline stages.
47 auto Fetch = std::make_unique<EntryStage>(args&: SrcMgr);
48 auto Dispatch =
49 std::make_unique<DispatchStage>(args: STI, args: MRI, args: Opts.DispatchWidth, args&: *RCU, args&: *PRF);
50 auto Execute =
51 std::make_unique<ExecuteStage>(args&: *HWS, args: Opts.EnableBottleneckAnalysis);
52 auto Retire = std::make_unique<RetireStage>(args&: *RCU, args&: *PRF, args&: *LSU);
53
54 // Pass the ownership of all the hardware units to this Context.
55 addHardwareUnit(H: std::move(RCU));
56 addHardwareUnit(H: std::move(PRF));
57 addHardwareUnit(H: std::move(LSU));
58 addHardwareUnit(H: std::move(HWS));
59
60 // Build the pipeline.
61 auto StagePipeline = std::make_unique<Pipeline>();
62 StagePipeline->appendStage(S: std::move(Fetch));
63 if (Opts.MicroOpQueueSize)
64 StagePipeline->appendStage(S: std::make_unique<MicroOpQueueStage>(
65 args: Opts.MicroOpQueueSize, args: Opts.DecodersThroughput));
66 StagePipeline->appendStage(S: std::move(Dispatch));
67 StagePipeline->appendStage(S: std::move(Execute));
68 StagePipeline->appendStage(S: std::move(Retire));
69 return StagePipeline;
70}
71
72std::unique_ptr<Pipeline>
73Context::createInOrderPipeline(const PipelineOptions &Opts, SourceMgr &SrcMgr,
74 CustomBehaviour &CB) {
75 const MCSchedModel &SM = STI.getSchedModel();
76 auto PRF = std::make_unique<RegisterFile>(args: SM, args: MRI, args: Opts.RegisterFileSize);
77 auto LSU = std::make_unique<LSUnit>(args: SM, args: Opts.LoadQueueSize,
78 args: Opts.StoreQueueSize, args: Opts.AssumeNoAlias);
79
80 // Create the pipeline stages.
81 auto Entry = std::make_unique<EntryStage>(args&: SrcMgr);
82 auto InOrderIssue = std::make_unique<InOrderIssueStage>(args: STI, args&: *PRF, args&: CB, args&: *LSU);
83 auto StagePipeline = std::make_unique<Pipeline>();
84
85 // Pass the ownership of all the hardware units to this Context.
86 addHardwareUnit(H: std::move(PRF));
87 addHardwareUnit(H: std::move(LSU));
88
89 // Build the pipeline.
90 StagePipeline->appendStage(S: std::move(Entry));
91 StagePipeline->appendStage(S: std::move(InOrderIssue));
92 return StagePipeline;
93}
94
95} // namespace mca
96} // namespace llvm
97