1//===---------------------------- Context.h ---------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9///
10/// This file defines a class for holding ownership of various simulated
11/// hardware units. A Context also provides a utility routine for constructing
12/// a default out-of-order pipeline with fetch, dispatch, execute, and retire
13/// stages.
14///
15//===----------------------------------------------------------------------===//
16
17#ifndef LLVM_MCA_CONTEXT_H
18#define LLVM_MCA_CONTEXT_H
19
20#include "llvm/MC/MCRegisterInfo.h"
21#include "llvm/MC/MCSubtargetInfo.h"
22#include "llvm/MCA/CustomBehaviour.h"
23#include "llvm/MCA/HardwareUnits/HardwareUnit.h"
24#include "llvm/MCA/Pipeline.h"
25#include "llvm/MCA/SourceMgr.h"
26#include "llvm/Support/Compiler.h"
27#include <memory>
28
29namespace llvm {
30namespace mca {
31
32/// This is a convenience struct to hold the parameters necessary for creating
33/// the pre-built "default" out-of-order pipeline.
34struct PipelineOptions {
35 PipelineOptions(unsigned UOPQSize, unsigned DecThr, unsigned DW, unsigned RFS,
36 unsigned LQS, unsigned SQS, bool NoAlias,
37 bool ShouldEnableBottleneckAnalysis = false)
38 : MicroOpQueueSize(UOPQSize), DecodersThroughput(DecThr),
39 DispatchWidth(DW), RegisterFileSize(RFS), LoadQueueSize(LQS),
40 StoreQueueSize(SQS), AssumeNoAlias(NoAlias),
41 EnableBottleneckAnalysis(ShouldEnableBottleneckAnalysis) {}
42 unsigned MicroOpQueueSize;
43 unsigned DecodersThroughput; // Instructions per cycle.
44 unsigned DispatchWidth;
45 unsigned RegisterFileSize;
46 unsigned LoadQueueSize;
47 unsigned StoreQueueSize;
48 bool AssumeNoAlias;
49 bool EnableBottleneckAnalysis;
50};
51
52class Context {
53 SmallVector<std::unique_ptr<HardwareUnit>, 4> Hardware;
54 const MCRegisterInfo &MRI;
55 const MCSubtargetInfo &STI;
56
57public:
58 Context(const MCRegisterInfo &R, const MCSubtargetInfo &S) : MRI(R), STI(S) {}
59 Context(const Context &C) = delete;
60 Context &operator=(const Context &C) = delete;
61
62 const MCRegisterInfo &getMCRegisterInfo() const { return MRI; }
63 const MCSubtargetInfo &getMCSubtargetInfo() const { return STI; }
64
65 void addHardwareUnit(std::unique_ptr<HardwareUnit> H) {
66 Hardware.push_back(Elt: std::move(H));
67 }
68
69 /// Construct a basic pipeline for simulating an out-of-order pipeline.
70 /// This pipeline consists of Fetch, Dispatch, Execute, and Retire stages.
71 LLVM_ABI std::unique_ptr<Pipeline>
72 createDefaultPipeline(const PipelineOptions &Opts, SourceMgr &SrcMgr,
73 CustomBehaviour &CB);
74
75 /// Construct a basic pipeline for simulating an in-order pipeline.
76 /// This pipeline consists of Fetch, InOrderIssue, and Retire stages.
77 LLVM_ABI std::unique_ptr<Pipeline>
78 createInOrderPipeline(const PipelineOptions &Opts, SourceMgr &SrcMgr,
79 CustomBehaviour &CB);
80};
81
82} // namespace mca
83} // namespace llvm
84#endif // LLVM_MCA_CONTEXT_H
85