1//===- AMDGPUGenRegisterBankInfo.def -----------------------------*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file defines all the static objects used by AMDGPURegisterBankInfo.
10/// \todo This should be generated by TableGen.
11//===----------------------------------------------------------------------===//
12
13namespace llvm {
14namespace AMDGPU {
15
16enum PartialMappingIdx {
17 None = - 1,
18 PM_SGPR1 = 1,
19 PM_SGPR16 = 5,
20 PM_SGPR32 = 6,
21 PM_SGPR64 = 7,
22 PM_SGPR128 = 8,
23 PM_SGPR256 = 9,
24 PM_SGPR512 = 10,
25 PM_SGPR1024 = 11,
26 PM_VGPR1 = 12,
27 PM_VGPR16 = 16,
28 PM_VGPR32 = 17,
29 PM_VGPR64 = 18,
30 PM_VGPR128 = 19,
31 PM_VGPR256 = 20,
32 PM_VGPR512 = 21,
33 PM_VGPR1024 = 22,
34 PM_SGPR96 = 23,
35 PM_VGPR96 = 24,
36 PM_AGPR96 = 25,
37 PM_SGPR288 = 26,
38 PM_VGPR288 = 27,
39 PM_AGPR288 = 28,
40 PM_SGPR320 = 29,
41 PM_VGPR320 = 30,
42 PM_AGPR320 = 31,
43 PM_SGPR352 = 32,
44 PM_VGPR352 = 33,
45 PM_AGPR352 = 34,
46 PM_SGPR384 = 35,
47 PM_VGPR384 = 36,
48 PM_AGPR384 = 37,
49 PM_AGPR32 = 38,
50 PM_AGPR64 = 39,
51 PM_AGPR128 = 40,
52 PM_AGPR256 = 41,
53 PM_AGPR512 = 42,
54 PM_AGPR1024 = 43
55};
56
57const RegisterBankInfo::PartialMapping PartMappings[] {
58 // StartIdx, Length, RegBank
59 {0, 1, VCCRegBank},
60
61 {0, 1, SGPRRegBank}, // SGPR begin
62 {0, 16, SGPRRegBank},
63 {0, 32, SGPRRegBank},
64 {0, 64, SGPRRegBank},
65 {0, 128, SGPRRegBank},
66 {0, 256, SGPRRegBank},
67 {0, 512, SGPRRegBank},
68 {0, 1024, SGPRRegBank},
69
70 {0, 1, VGPRRegBank}, // VGPR begin
71 {0, 16, VGPRRegBank},
72 {0, 32, VGPRRegBank},
73 {0, 64, VGPRRegBank},
74 {0, 128, VGPRRegBank},
75 {0, 256, VGPRRegBank},
76 {0, 512, VGPRRegBank},
77 {0, 1024, VGPRRegBank},
78 {0, 96, SGPRRegBank},
79 {0, 96, VGPRRegBank},
80 {0, 96, AGPRRegBank},
81 {0, 288, SGPRRegBank},
82 {0, 288, VGPRRegBank},
83 {0, 288, AGPRRegBank},
84 {0, 320, SGPRRegBank},
85 {0, 320, VGPRRegBank},
86 {0, 320, AGPRRegBank},
87 {0, 352, SGPRRegBank},
88 {0, 352, VGPRRegBank},
89 {0, 352, AGPRRegBank},
90 {0, 384, SGPRRegBank},
91 {0, 384, VGPRRegBank},
92 {0, 384, AGPRRegBank},
93
94 {0, 32, AGPRRegBank}, // AGPR begin
95 {0, 64, AGPRRegBank},
96 {0, 128, AGPRRegBank},
97 {0, 256, AGPRRegBank},
98 {0, 512, AGPRRegBank},
99 {0, 1024, AGPRRegBank}
100};
101
102const RegisterBankInfo::ValueMapping ValMappings[] {
103 // VCC
104 {&PartMappings[0], 1},
105
106 // SGPRs
107 {&PartMappings[1], 1}, // 1
108 {nullptr, 0}, // Illegal power of 2 sizes
109 {nullptr, 0},
110 {nullptr, 0},
111 {&PartMappings[2], 1}, // 16
112 {&PartMappings[3], 1}, // 32
113 {&PartMappings[4], 1}, // 64
114 {&PartMappings[5], 1}, // 128
115 {&PartMappings[6], 1}, // 256
116 {&PartMappings[7], 1}, // 512
117 {&PartMappings[8], 1}, // 1024
118
119 // VGPRs
120 {&PartMappings[9], 1}, // 1
121 {nullptr, 0},
122 {nullptr, 0},
123 {nullptr, 0},
124 {&PartMappings[10], 1}, // 16
125 {&PartMappings[11], 1}, // 32
126 {&PartMappings[12], 1}, // 64
127 {&PartMappings[13], 1}, // 128
128 {&PartMappings[14], 1}, // 256
129 {&PartMappings[15], 1}, // 512
130 {&PartMappings[16], 1}, // 1024
131 {&PartMappings[17], 1},
132 {&PartMappings[18], 1},
133 {&PartMappings[19], 1},
134 {&PartMappings[20], 1},
135 {&PartMappings[21], 1},
136 {&PartMappings[22], 1},
137 {&PartMappings[23], 1},
138 {&PartMappings[24], 1},
139 {&PartMappings[25], 1},
140 {&PartMappings[26], 1},
141 {&PartMappings[27], 1},
142 {&PartMappings[28], 1},
143 {&PartMappings[29], 1},
144 {&PartMappings[30], 1},
145 {&PartMappings[31], 1},
146
147 // AGPRs
148 {nullptr, 0},
149 {nullptr, 0},
150 {nullptr, 0},
151 {nullptr, 0},
152 {nullptr, 0},
153 {&PartMappings[32], 1}, // 32
154 {&PartMappings[33], 1}, // 64
155 {&PartMappings[34], 1}, // 128
156 {&PartMappings[35], 1}, // 256
157 {&PartMappings[36], 1}, // 512
158 {&PartMappings[37], 1} // 1024
159};
160
161const RegisterBankInfo::PartialMapping SGPROnly64BreakDown[] {
162 {0, 32, SGPRRegBank}, // 32-bit op
163 {0, 32, SGPRRegBank}, // 2x32-bit op
164 {32, 32, SGPRRegBank},
165 {0, 64, SGPRRegBank}, // <2x32-bit> op
166
167 {0, 32, VGPRRegBank}, // 32-bit op
168 {0, 32, VGPRRegBank}, // 2x32-bit op
169 {32, 32, VGPRRegBank},
170};
171
172
173// For some instructions which can operate 64-bit only for the scalar
174// version. Otherwise, these need to be split into 2 32-bit operations.
175const RegisterBankInfo::ValueMapping ValMappingsSGPR64OnlyVGPR32[] {
176 /*32-bit sgpr*/ {&SGPROnly64BreakDown[0], 1},
177 /*2 x 32-bit sgpr*/ {&SGPROnly64BreakDown[1], 2},
178 /*64-bit sgpr */ {&SGPROnly64BreakDown[3], 1},
179
180 /*32-bit vgpr*/ {&SGPROnly64BreakDown[4], 1},
181 /*2 x 32-bit vgpr*/ {&SGPROnly64BreakDown[5], 2}
182};
183
184enum ValueMappingIdx {
185 SGPRStartIdx = 1,
186 VGPRStartIdx = 12,
187 AGPRStartIdx = 38
188};
189
190const RegisterBankInfo::ValueMapping *getValueMapping(unsigned BankID,
191 unsigned Size) {
192 unsigned Idx;
193 switch (Size) {
194 case 1:
195 if (BankID == AMDGPU::VCCRegBankID)
196 return &ValMappings[0];
197
198 Idx = BankID == AMDGPU::SGPRRegBankID ? PM_SGPR1 : PM_VGPR1;
199 break;
200 case 96:
201 switch (BankID) {
202 case AMDGPU::VGPRRegBankID:
203 Idx = PM_VGPR96;
204 break;
205 case AMDGPU::SGPRRegBankID:
206 Idx = PM_SGPR96;
207 break;
208 case AMDGPU::AGPRRegBankID:
209 Idx = PM_AGPR96;
210 break;
211 default: llvm_unreachable("Invalid register bank");
212 }
213 break;
214 case 288:
215 switch (BankID) {
216 case AMDGPU::VGPRRegBankID:
217 Idx = PM_VGPR288;
218 break;
219 case AMDGPU::SGPRRegBankID:
220 Idx = PM_SGPR288;
221 break;
222 case AMDGPU::AGPRRegBankID:
223 Idx = PM_AGPR288;
224 break;
225 default: llvm_unreachable("Invalid register bank");
226 }
227 break;
228 case 320:
229 switch (BankID) {
230 case AMDGPU::VGPRRegBankID:
231 Idx = PM_VGPR320;
232 break;
233 case AMDGPU::SGPRRegBankID:
234 Idx = PM_SGPR320;
235 break;
236 case AMDGPU::AGPRRegBankID:
237 Idx = PM_AGPR320;
238 break;
239 default: llvm_unreachable("Invalid register bank");
240 }
241 break;
242 case 352:
243 switch (BankID) {
244 case AMDGPU::VGPRRegBankID:
245 Idx = PM_VGPR352;
246 break;
247 case AMDGPU::SGPRRegBankID:
248 Idx = PM_SGPR352;
249 break;
250 case AMDGPU::AGPRRegBankID:
251 Idx = PM_AGPR352;
252 break;
253 default: llvm_unreachable("Invalid register bank");
254 }
255 break;
256 case 384:
257 switch (BankID) {
258 case AMDGPU::VGPRRegBankID:
259 Idx = PM_VGPR384;
260 break;
261 case AMDGPU::SGPRRegBankID:
262 Idx = PM_SGPR384;
263 break;
264 case AMDGPU::AGPRRegBankID:
265 Idx = PM_AGPR384;
266 break;
267 default: llvm_unreachable("Invalid register bank");
268 }
269 break;
270 default:
271 switch (BankID) {
272 case AMDGPU::VGPRRegBankID:
273 Idx = VGPRStartIdx;
274 break;
275 case AMDGPU::SGPRRegBankID:
276 Idx = SGPRStartIdx;
277 break;
278 case AMDGPU::AGPRRegBankID:
279 Idx = AGPRStartIdx;
280 break;
281 default: llvm_unreachable("Invalid register bank");
282 }
283 Idx += Log2_32_Ceil(Value: Size);
284 break;
285 }
286
287 assert(Idx < std::size(ValMappings));
288 assert(Log2_32_Ceil(Size) == Log2_32_Ceil(ValMappings[Idx].BreakDown->Length));
289 assert(BankID == ValMappings[Idx].BreakDown->RegBank->getID());
290
291 return &ValMappings[Idx];
292}
293
294const RegisterBankInfo::ValueMapping *getValueMappingSGPR64Only(unsigned BankID,
295 unsigned Size) {
296 if (Size != 64)
297 return getValueMapping(BankID, Size);
298
299 if (BankID == AMDGPU::VGPRRegBankID)
300 return &ValMappingsSGPR64OnlyVGPR32[4];
301
302 assert(BankID == AMDGPU::SGPRRegBankID);
303 return &ValMappingsSGPR64OnlyVGPR32[2];
304}
305
306/// Split any 64-bit value into 2 32-bit pieces. Unlike
307/// getValueMappingSGPR64Only, this splits both VGPRs and SGPRs.
308const RegisterBankInfo::ValueMapping *getValueMappingSplit64(unsigned BankID,
309 unsigned Size) {
310 assert(Size == 64);
311 if (BankID == AMDGPU::VGPRRegBankID)
312 return &ValMappingsSGPR64OnlyVGPR32[4];
313
314 assert(BankID == AMDGPU::SGPRRegBankID);
315 return &ValMappingsSGPR64OnlyVGPR32[1];
316}
317
318
319} // End AMDGPU namespace.
320} // End llvm namespace.
321