1//===-- AMDGPUPALMetadata.cpp - Accumulate and print AMDGPU PAL metadata -===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10///
11/// This class has methods called by AMDGPUAsmPrinter to accumulate and print
12/// the PAL metadata.
13//
14//===----------------------------------------------------------------------===//
15//
16
17#include "AMDGPUPALMetadata.h"
18#include "AMDGPUPTNote.h"
19#include "SIDefines.h"
20#include "llvm/BinaryFormat/ELF.h"
21#include "llvm/IR/Constants.h"
22#include "llvm/IR/Module.h"
23#include "llvm/MC/MCExpr.h"
24#include "llvm/Support/AMDGPUMetadata.h"
25#include "llvm/Support/EndianStream.h"
26#include "llvm/Support/VersionTuple.h"
27
28using namespace llvm;
29using namespace llvm::AMDGPU;
30
31// Return the PAL metadata hardware shader stage name.
32static const char *getStageName(CallingConv::ID CC) {
33 switch (CC) {
34 case CallingConv::AMDGPU_PS:
35 return ".ps";
36 case CallingConv::AMDGPU_VS:
37 return ".vs";
38 case CallingConv::AMDGPU_GS:
39 return ".gs";
40 case CallingConv::AMDGPU_ES:
41 return ".es";
42 case CallingConv::AMDGPU_HS:
43 return ".hs";
44 case CallingConv::AMDGPU_LS:
45 return ".ls";
46 case CallingConv::AMDGPU_Gfx:
47 llvm_unreachable("Callable shader has no hardware stage");
48 default:
49 return ".cs";
50 }
51}
52
53// Read the PAL metadata from IR metadata, where it was put by the frontend.
54void AMDGPUPALMetadata::readFromIR(Module &M) {
55 auto *NamedMD = M.getNamedMetadata(Name: "amdgpu.pal.metadata.msgpack");
56 if (NamedMD && NamedMD->getNumOperands()) {
57 // This is the new msgpack format for metadata. It is a NamedMD containing
58 // an MDTuple containing an MDString containing the msgpack data.
59 BlobType = ELF::NT_AMDGPU_METADATA;
60 auto *MDN = dyn_cast<MDTuple>(Val: NamedMD->getOperand(i: 0));
61 if (MDN && MDN->getNumOperands()) {
62 if (auto *MDS = dyn_cast<MDString>(Val: MDN->getOperand(I: 0)))
63 setFromMsgPackBlob(MDS->getString());
64 }
65 return;
66 }
67 BlobType = ELF::NT_AMD_PAL_METADATA;
68 NamedMD = M.getNamedMetadata(Name: "amdgpu.pal.metadata");
69 if (!NamedMD || !NamedMD->getNumOperands()) {
70 // Emit msgpack metadata by default
71 BlobType = ELF::NT_AMDGPU_METADATA;
72 return;
73 }
74 // This is the old reg=value pair format for metadata. It is a NamedMD
75 // containing an MDTuple containing a number of MDNodes each of which is an
76 // integer value, and each two integer values forms a key=value pair that we
77 // store as Registers[key]=value in the map.
78 auto *Tuple = dyn_cast<MDTuple>(Val: NamedMD->getOperand(i: 0));
79 if (!Tuple)
80 return;
81 for (unsigned I = 0, E = Tuple->getNumOperands() & -2; I != E; I += 2) {
82 auto *Key = mdconst::dyn_extract<ConstantInt>(MD: Tuple->getOperand(I));
83 auto *Val = mdconst::dyn_extract<ConstantInt>(MD: Tuple->getOperand(I: I + 1));
84 if (!Key || !Val)
85 continue;
86 setRegister(Reg: Key->getZExtValue(), Val: Val->getZExtValue());
87 }
88}
89
90// Set PAL metadata from a binary blob from the applicable .note record.
91// Returns false if bad format. Blob must remain valid for the lifetime of the
92// Metadata.
93bool AMDGPUPALMetadata::setFromBlob(unsigned Type, StringRef Blob) {
94 BlobType = Type;
95 if (Type == ELF::NT_AMD_PAL_METADATA)
96 return setFromLegacyBlob(Blob);
97 return setFromMsgPackBlob(Blob);
98}
99
100// Set PAL metadata from legacy (array of key=value pairs) blob.
101bool AMDGPUPALMetadata::setFromLegacyBlob(StringRef Blob) {
102 const auto *Data = reinterpret_cast<const uint32_t *>(Blob.data());
103 for (unsigned I = 0; I != Blob.size() / sizeof(uint32_t) / 2; ++I)
104 setRegister(Reg: Data[I * 2], Val: Data[I * 2 + 1]);
105 return true;
106}
107
108// Set PAL metadata from msgpack blob.
109bool AMDGPUPALMetadata::setFromMsgPackBlob(StringRef Blob) {
110 return MsgPackDoc.readFromBlob(Blob, /*Multi=*/false);
111}
112
113// Given the calling convention, calculate the register number for rsrc1. In
114// principle the register number could change in future hardware, but we know
115// it is the same for gfx6-9 (except that LS and ES don't exist on gfx9), so
116// we can use fixed values.
117static unsigned getRsrc1Reg(CallingConv::ID CC) {
118 switch (CC) {
119 default:
120 return PALMD::R_2E12_COMPUTE_PGM_RSRC1;
121 case CallingConv::AMDGPU_LS:
122 return PALMD::R_2D4A_SPI_SHADER_PGM_RSRC1_LS;
123 case CallingConv::AMDGPU_HS:
124 return PALMD::R_2D0A_SPI_SHADER_PGM_RSRC1_HS;
125 case CallingConv::AMDGPU_ES:
126 return PALMD::R_2CCA_SPI_SHADER_PGM_RSRC1_ES;
127 case CallingConv::AMDGPU_GS:
128 return PALMD::R_2C8A_SPI_SHADER_PGM_RSRC1_GS;
129 case CallingConv::AMDGPU_VS:
130 return PALMD::R_2C4A_SPI_SHADER_PGM_RSRC1_VS;
131 case CallingConv::AMDGPU_PS:
132 return PALMD::R_2C0A_SPI_SHADER_PGM_RSRC1_PS;
133 }
134}
135
136// Calculate the PAL metadata key for *S_SCRATCH_SIZE. It can be used
137// with a constant offset to access any non-register shader-specific PAL
138// metadata key.
139static unsigned getScratchSizeKey(CallingConv::ID CC) {
140 switch (CC) {
141 case CallingConv::AMDGPU_PS:
142 return PALMD::Key::PS_SCRATCH_SIZE;
143 case CallingConv::AMDGPU_VS:
144 return PALMD::Key::VS_SCRATCH_SIZE;
145 case CallingConv::AMDGPU_GS:
146 return PALMD::Key::GS_SCRATCH_SIZE;
147 case CallingConv::AMDGPU_ES:
148 return PALMD::Key::ES_SCRATCH_SIZE;
149 case CallingConv::AMDGPU_HS:
150 return PALMD::Key::HS_SCRATCH_SIZE;
151 case CallingConv::AMDGPU_LS:
152 return PALMD::Key::LS_SCRATCH_SIZE;
153 default:
154 return PALMD::Key::CS_SCRATCH_SIZE;
155 }
156}
157
158// Set the rsrc1 register in the metadata for a particular shader stage.
159// In fact this ORs the value into any previous setting of the register.
160void AMDGPUPALMetadata::setRsrc1(CallingConv::ID CC, unsigned Val) {
161 setRegister(Reg: getRsrc1Reg(CC), Val);
162}
163
164void AMDGPUPALMetadata::setRsrc1(CallingConv::ID CC, const MCExpr *Val,
165 MCContext &Ctx) {
166 setRegister(Reg: getRsrc1Reg(CC), Val, Ctx);
167}
168
169// Set the rsrc2 register in the metadata for a particular shader stage.
170// In fact this ORs the value into any previous setting of the register.
171void AMDGPUPALMetadata::setRsrc2(CallingConv::ID CC, unsigned Val) {
172 setRegister(Reg: getRsrc1Reg(CC) + 1, Val);
173}
174
175void AMDGPUPALMetadata::setRsrc2(CallingConv::ID CC, const MCExpr *Val,
176 MCContext &Ctx) {
177 setRegister(Reg: getRsrc1Reg(CC) + 1, Val, Ctx);
178}
179
180// Set the SPI_PS_INPUT_ENA register in the metadata.
181// In fact this ORs the value into any previous setting of the register.
182void AMDGPUPALMetadata::setSpiPsInputEna(unsigned Val) {
183 setRegister(Reg: PALMD::R_A1B3_SPI_PS_INPUT_ENA, Val);
184}
185
186// Set the SPI_PS_INPUT_ADDR register in the metadata.
187// In fact this ORs the value into any previous setting of the register.
188void AMDGPUPALMetadata::setSpiPsInputAddr(unsigned Val) {
189 setRegister(Reg: PALMD::R_A1B4_SPI_PS_INPUT_ADDR, Val);
190}
191
192// Get a register from the metadata, or 0 if not currently set.
193unsigned AMDGPUPALMetadata::getRegister(unsigned Reg) {
194 auto Regs = getRegisters();
195 auto It = Regs.find(Key: MsgPackDoc.getNode(V: Reg));
196 if (It == Regs.end())
197 return 0;
198 auto N = It->second;
199 if (N.getKind() != msgpack::Type::UInt)
200 return 0;
201 return N.getUInt();
202}
203
204// Set a register in the metadata.
205// In fact this ORs the value into any previous setting of the register.
206void AMDGPUPALMetadata::setRegister(unsigned Reg, unsigned Val) {
207 if (!isLegacy()) {
208 // In the new MsgPack format, ignore register numbered >= 0x10000000. It
209 // is a PAL ABI pseudo-register in the old non-MsgPack format.
210 if (Reg >= 0x10000000)
211 return;
212 }
213 auto &N = getRegisters()[MsgPackDoc.getNode(V: Reg)];
214 if (N.getKind() == msgpack::Type::UInt)
215 Val |= N.getUInt();
216 N = N.getDocument()->getNode(V: Val);
217}
218
219// Set a register in the metadata.
220// In fact this ORs the value into any previous setting of the register.
221void AMDGPUPALMetadata::setRegister(unsigned Reg, const MCExpr *Val,
222 MCContext &Ctx) {
223 if (!isLegacy()) {
224 // In the new MsgPack format, ignore register numbered >= 0x10000000. It
225 // is a PAL ABI pseudo-register in the old non-MsgPack format.
226 if (Reg >= 0x10000000)
227 return;
228 }
229 auto &N = getRegisters()[MsgPackDoc.getNode(V: Reg)];
230 auto [ExprIt, Inserted] = REM.try_emplace(Key: Reg);
231
232 if (!Inserted) {
233 Val = MCBinaryExpr::createOr(LHS: Val, RHS: ExprIt->getSecond(), Ctx);
234 // This conditional may be redundant most of the time, but the alternate
235 // setRegister(unsigned, unsigned) could've been called while the
236 // conditional returns true (i.e., Reg exists in REM).
237 if (N.getKind() == msgpack::Type::UInt) {
238 const MCExpr *NExpr = MCConstantExpr::create(Value: N.getUInt(), Ctx);
239 Val = MCBinaryExpr::createOr(LHS: Val, RHS: NExpr, Ctx);
240 }
241 } else if (N.getKind() == msgpack::Type::UInt) {
242 const MCExpr *NExpr = MCConstantExpr::create(Value: N.getUInt(), Ctx);
243 Val = MCBinaryExpr::createOr(LHS: Val, RHS: NExpr, Ctx);
244 } else {
245 // Default to uint64_t 0 so additional calls to setRegister will allow
246 // propagate ORs.
247 N = (uint64_t)0;
248 }
249 ExprIt->second = Val;
250 DelayedExprs.assignDocNode(DN&: N, Type: msgpack::Type::UInt, ExprValue: Val);
251}
252
253// Set the entry point name for one shader.
254void AMDGPUPALMetadata::setEntryPoint(unsigned CC, StringRef Name) {
255 if (isLegacy())
256 return;
257 // Msgpack format.
258 // Entry point is updated to .entry_point_symbol and is set to the function
259 // name
260 getHwStage(CC)[".entry_point_symbol"] =
261 MsgPackDoc.getNode(V: Name, /*Copy=*/true);
262
263 // For PAL version 3.6 and above, entry_point is no longer required.
264 if (getPALVersion() < VersionTuple(3, 6)) {
265 // Set .entry_point which is defined to be _amdgpu_<stage>_main and
266 // _amdgpu_cs_main for non-shader functions.
267 SmallString<16> EPName("_amdgpu_");
268 raw_svector_ostream EPNameOS(EPName);
269 EPNameOS << getStageName(CC) + 1 << "_main";
270 getHwStage(CC)[".entry_point"] =
271 MsgPackDoc.getNode(V: EPNameOS.str(), /*Copy=*/true);
272 }
273}
274
275// Set the number of used vgprs in the metadata. This is an optional
276// advisory record for logging etc; wave dispatch actually uses the rsrc1
277// register for the shader stage to determine the number of vgprs to
278// allocate.
279void AMDGPUPALMetadata::setNumUsedVgprs(CallingConv::ID CC, unsigned Val) {
280 if (isLegacy()) {
281 // Old non-msgpack format.
282 unsigned NumUsedVgprsKey = getScratchSizeKey(CC) +
283 PALMD::Key::VS_NUM_USED_VGPRS -
284 PALMD::Key::VS_SCRATCH_SIZE;
285 setRegister(Reg: NumUsedVgprsKey, Val);
286 return;
287 }
288 // Msgpack format.
289 getHwStage(CC)[".vgpr_count"] = MsgPackDoc.getNode(V: Val);
290}
291
292void AMDGPUPALMetadata::setNumUsedVgprs(CallingConv::ID CC, const MCExpr *Val,
293 MCContext &Ctx) {
294 if (isLegacy()) {
295 // Old non-msgpack format.
296 unsigned NumUsedVgprsKey = getScratchSizeKey(CC) +
297 PALMD::Key::VS_NUM_USED_VGPRS -
298 PALMD::Key::VS_SCRATCH_SIZE;
299 setRegister(Reg: NumUsedVgprsKey, Val, Ctx);
300 return;
301 }
302 // Msgpack format.
303 setHwStage(CC, field: ".vgpr_count", Type: msgpack::Type::UInt, Val);
304}
305
306// Set the number of used agprs in the metadata.
307void AMDGPUPALMetadata::setNumUsedAgprs(CallingConv::ID CC, unsigned Val) {
308 getHwStage(CC)[".agpr_count"] = Val;
309}
310
311void AMDGPUPALMetadata::setNumUsedAgprs(unsigned CC, const MCExpr *Val) {
312 setHwStage(CC, field: ".agpr_count", Type: msgpack::Type::UInt, Val);
313}
314
315// Set the number of used sgprs in the metadata. This is an optional advisory
316// record for logging etc; wave dispatch actually uses the rsrc1 register for
317// the shader stage to determine the number of sgprs to allocate.
318void AMDGPUPALMetadata::setNumUsedSgprs(CallingConv::ID CC, unsigned Val) {
319 if (isLegacy()) {
320 // Old non-msgpack format.
321 unsigned NumUsedSgprsKey = getScratchSizeKey(CC) +
322 PALMD::Key::VS_NUM_USED_SGPRS -
323 PALMD::Key::VS_SCRATCH_SIZE;
324 setRegister(Reg: NumUsedSgprsKey, Val);
325 return;
326 }
327 // Msgpack format.
328 getHwStage(CC)[".sgpr_count"] = MsgPackDoc.getNode(V: Val);
329}
330
331void AMDGPUPALMetadata::setNumUsedSgprs(unsigned CC, const MCExpr *Val,
332 MCContext &Ctx) {
333 if (isLegacy()) {
334 // Old non-msgpack format.
335 unsigned NumUsedSgprsKey = getScratchSizeKey(CC) +
336 PALMD::Key::VS_NUM_USED_SGPRS -
337 PALMD::Key::VS_SCRATCH_SIZE;
338 setRegister(Reg: NumUsedSgprsKey, Val, Ctx);
339 return;
340 }
341 // Msgpack format.
342 setHwStage(CC, field: ".sgpr_count", Type: msgpack::Type::UInt, Val);
343}
344
345// Set the scratch size in the metadata.
346void AMDGPUPALMetadata::setScratchSize(CallingConv::ID CC, unsigned Val) {
347 if (isLegacy()) {
348 // Old non-msgpack format.
349 setRegister(Reg: getScratchSizeKey(CC), Val);
350 return;
351 }
352 // Msgpack format.
353 getHwStage(CC)[".scratch_memory_size"] = MsgPackDoc.getNode(V: Val);
354}
355
356void AMDGPUPALMetadata::setScratchSize(unsigned CC, const MCExpr *Val,
357 MCContext &Ctx) {
358 if (isLegacy()) {
359 // Old non-msgpack format.
360 setRegister(Reg: getScratchSizeKey(CC), Val, Ctx);
361 return;
362 }
363 // Msgpack format.
364 setHwStage(CC, field: ".scratch_memory_size", Type: msgpack::Type::UInt, Val);
365}
366
367// Set the stack frame size of a function in the metadata.
368void AMDGPUPALMetadata::setFunctionScratchSize(StringRef FnName, unsigned Val) {
369 auto Node = getShaderFunction(Name: FnName);
370 Node[".stack_frame_size_in_bytes"] = MsgPackDoc.getNode(V: Val);
371 Node[".backend_stack_size"] = MsgPackDoc.getNode(V: Val);
372}
373
374// Set the amount of LDS used in bytes in the metadata.
375void AMDGPUPALMetadata::setFunctionLdsSize(StringRef FnName, unsigned Val) {
376 auto Node = getShaderFunction(Name: FnName);
377 Node[".lds_size"] = MsgPackDoc.getNode(V: Val);
378}
379
380// Set the number of used vgprs in the metadata.
381void AMDGPUPALMetadata::setFunctionNumUsedVgprs(StringRef FnName,
382 unsigned Val) {
383 auto Node = getShaderFunction(Name: FnName);
384 Node[".vgpr_count"] = MsgPackDoc.getNode(V: Val);
385}
386
387void AMDGPUPALMetadata::setFunctionNumUsedVgprs(StringRef FnName,
388 const MCExpr *Val) {
389 auto Node = getShaderFunction(Name: FnName);
390 DelayedExprs.assignDocNode(DN&: Node[".vgpr_count"], Type: msgpack::Type::UInt, ExprValue: Val);
391}
392
393// Set the number of used vgprs in the metadata.
394void AMDGPUPALMetadata::setFunctionNumUsedSgprs(StringRef FnName,
395 unsigned Val) {
396 auto Node = getShaderFunction(Name: FnName);
397 Node[".sgpr_count"] = MsgPackDoc.getNode(V: Val);
398}
399
400void AMDGPUPALMetadata::setFunctionNumUsedSgprs(StringRef FnName,
401 const MCExpr *Val) {
402 auto Node = getShaderFunction(Name: FnName);
403 DelayedExprs.assignDocNode(DN&: Node[".sgpr_count"], Type: msgpack::Type::UInt, ExprValue: Val);
404}
405
406// Set the hardware register bit in PAL metadata to enable wave32 on the
407// shader of the given calling convention.
408void AMDGPUPALMetadata::setWave32(unsigned CC) {
409 switch (CC) {
410 case CallingConv::AMDGPU_HS:
411 setRegister(Reg: PALMD::R_A2D5_VGT_SHADER_STAGES_EN, S_028B54_HS_W32_EN(1));
412 break;
413 case CallingConv::AMDGPU_GS:
414 setRegister(Reg: PALMD::R_A2D5_VGT_SHADER_STAGES_EN, S_028B54_GS_W32_EN(1));
415 break;
416 case CallingConv::AMDGPU_VS:
417 setRegister(Reg: PALMD::R_A2D5_VGT_SHADER_STAGES_EN, S_028B54_VS_W32_EN(1));
418 break;
419 case CallingConv::AMDGPU_PS:
420 setRegister(Reg: PALMD::R_A1B6_SPI_PS_IN_CONTROL, S_0286D8_PS_W32_EN(1));
421 break;
422 case CallingConv::AMDGPU_CS:
423 setRegister(Reg: PALMD::R_2E00_COMPUTE_DISPATCH_INITIATOR,
424 S_00B800_CS_W32_EN(1));
425 break;
426 }
427}
428
429// Convert a register number to name, for display by toString().
430// Returns nullptr if none.
431static const char *getRegisterName(unsigned RegNum) {
432 // Table of registers.
433 static const struct RegInfo {
434 unsigned Num;
435 const char *Name;
436 } RegInfoTable[] = {
437 // Registers that code generation sets/modifies metadata for.
438 {.Num: PALMD::R_2C4A_SPI_SHADER_PGM_RSRC1_VS, .Name: "SPI_SHADER_PGM_RSRC1_VS"},
439 {.Num: PALMD::R_2C4A_SPI_SHADER_PGM_RSRC1_VS + 1, .Name: "SPI_SHADER_PGM_RSRC2_VS"},
440 {.Num: PALMD::R_2D4A_SPI_SHADER_PGM_RSRC1_LS, .Name: "SPI_SHADER_PGM_RSRC1_LS"},
441 {.Num: PALMD::R_2D4A_SPI_SHADER_PGM_RSRC1_LS + 1, .Name: "SPI_SHADER_PGM_RSRC2_LS"},
442 {.Num: PALMD::R_2D0A_SPI_SHADER_PGM_RSRC1_HS, .Name: "SPI_SHADER_PGM_RSRC1_HS"},
443 {.Num: PALMD::R_2D0A_SPI_SHADER_PGM_RSRC1_HS + 1, .Name: "SPI_SHADER_PGM_RSRC2_HS"},
444 {.Num: PALMD::R_2CCA_SPI_SHADER_PGM_RSRC1_ES, .Name: "SPI_SHADER_PGM_RSRC1_ES"},
445 {.Num: PALMD::R_2CCA_SPI_SHADER_PGM_RSRC1_ES + 1, .Name: "SPI_SHADER_PGM_RSRC2_ES"},
446 {.Num: PALMD::R_2C8A_SPI_SHADER_PGM_RSRC1_GS, .Name: "SPI_SHADER_PGM_RSRC1_GS"},
447 {.Num: PALMD::R_2C8A_SPI_SHADER_PGM_RSRC1_GS + 1, .Name: "SPI_SHADER_PGM_RSRC2_GS"},
448 {.Num: PALMD::R_2E00_COMPUTE_DISPATCH_INITIATOR, .Name: "COMPUTE_DISPATCH_INITIATOR"},
449 {.Num: PALMD::R_2E12_COMPUTE_PGM_RSRC1, .Name: "COMPUTE_PGM_RSRC1"},
450 {.Num: PALMD::R_2E12_COMPUTE_PGM_RSRC1 + 1, .Name: "COMPUTE_PGM_RSRC2"},
451 {.Num: PALMD::R_2C0A_SPI_SHADER_PGM_RSRC1_PS, .Name: "SPI_SHADER_PGM_RSRC1_PS"},
452 {.Num: PALMD::R_2C0A_SPI_SHADER_PGM_RSRC1_PS + 1, .Name: "SPI_SHADER_PGM_RSRC2_PS"},
453 {.Num: PALMD::R_A1B3_SPI_PS_INPUT_ENA, .Name: "SPI_PS_INPUT_ENA"},
454 {.Num: PALMD::R_A1B4_SPI_PS_INPUT_ADDR, .Name: "SPI_PS_INPUT_ADDR"},
455 {.Num: PALMD::R_A1B6_SPI_PS_IN_CONTROL, .Name: "SPI_PS_IN_CONTROL"},
456 {.Num: PALMD::R_A2D5_VGT_SHADER_STAGES_EN, .Name: "VGT_SHADER_STAGES_EN"},
457
458 // Registers not known to code generation.
459 {.Num: 0x2c07, .Name: "SPI_SHADER_PGM_RSRC3_PS"},
460 {.Num: 0x2c46, .Name: "SPI_SHADER_PGM_RSRC3_VS"},
461 {.Num: 0x2c87, .Name: "SPI_SHADER_PGM_RSRC3_GS"},
462 {.Num: 0x2cc7, .Name: "SPI_SHADER_PGM_RSRC3_ES"},
463 {.Num: 0x2d07, .Name: "SPI_SHADER_PGM_RSRC3_HS"},
464 {.Num: 0x2d47, .Name: "SPI_SHADER_PGM_RSRC3_LS"},
465
466 {.Num: 0xa1c3, .Name: "SPI_SHADER_POS_FORMAT"},
467 {.Num: 0xa1b1, .Name: "SPI_VS_OUT_CONFIG"},
468 {.Num: 0xa207, .Name: "PA_CL_VS_OUT_CNTL"},
469 {.Num: 0xa204, .Name: "PA_CL_CLIP_CNTL"},
470 {.Num: 0xa206, .Name: "PA_CL_VTE_CNTL"},
471 {.Num: 0xa2f9, .Name: "PA_SU_VTX_CNTL"},
472 {.Num: 0xa293, .Name: "PA_SC_MODE_CNTL_1"},
473 {.Num: 0xa2a1, .Name: "VGT_PRIMITIVEID_EN"},
474 {.Num: 0x2c81, .Name: "SPI_SHADER_PGM_RSRC4_GS"},
475 {.Num: 0x2e18, .Name: "COMPUTE_TMPRING_SIZE"},
476 {.Num: 0xa1b5, .Name: "SPI_INTERP_CONTROL_0"},
477 {.Num: 0xa1ba, .Name: "SPI_TMPRING_SIZE"},
478 {.Num: 0xa1c4, .Name: "SPI_SHADER_Z_FORMAT"},
479 {.Num: 0xa1c5, .Name: "SPI_SHADER_COL_FORMAT"},
480 {.Num: 0xa203, .Name: "DB_SHADER_CONTROL"},
481 {.Num: 0xa08f, .Name: "CB_SHADER_MASK"},
482 {.Num: 0xa191, .Name: "SPI_PS_INPUT_CNTL_0"},
483 {.Num: 0xa192, .Name: "SPI_PS_INPUT_CNTL_1"},
484 {.Num: 0xa193, .Name: "SPI_PS_INPUT_CNTL_2"},
485 {.Num: 0xa194, .Name: "SPI_PS_INPUT_CNTL_3"},
486 {.Num: 0xa195, .Name: "SPI_PS_INPUT_CNTL_4"},
487 {.Num: 0xa196, .Name: "SPI_PS_INPUT_CNTL_5"},
488 {.Num: 0xa197, .Name: "SPI_PS_INPUT_CNTL_6"},
489 {.Num: 0xa198, .Name: "SPI_PS_INPUT_CNTL_7"},
490 {.Num: 0xa199, .Name: "SPI_PS_INPUT_CNTL_8"},
491 {.Num: 0xa19a, .Name: "SPI_PS_INPUT_CNTL_9"},
492 {.Num: 0xa19b, .Name: "SPI_PS_INPUT_CNTL_10"},
493 {.Num: 0xa19c, .Name: "SPI_PS_INPUT_CNTL_11"},
494 {.Num: 0xa19d, .Name: "SPI_PS_INPUT_CNTL_12"},
495 {.Num: 0xa19e, .Name: "SPI_PS_INPUT_CNTL_13"},
496 {.Num: 0xa19f, .Name: "SPI_PS_INPUT_CNTL_14"},
497 {.Num: 0xa1a0, .Name: "SPI_PS_INPUT_CNTL_15"},
498 {.Num: 0xa1a1, .Name: "SPI_PS_INPUT_CNTL_16"},
499 {.Num: 0xa1a2, .Name: "SPI_PS_INPUT_CNTL_17"},
500 {.Num: 0xa1a3, .Name: "SPI_PS_INPUT_CNTL_18"},
501 {.Num: 0xa1a4, .Name: "SPI_PS_INPUT_CNTL_19"},
502 {.Num: 0xa1a5, .Name: "SPI_PS_INPUT_CNTL_20"},
503 {.Num: 0xa1a6, .Name: "SPI_PS_INPUT_CNTL_21"},
504 {.Num: 0xa1a7, .Name: "SPI_PS_INPUT_CNTL_22"},
505 {.Num: 0xa1a8, .Name: "SPI_PS_INPUT_CNTL_23"},
506 {.Num: 0xa1a9, .Name: "SPI_PS_INPUT_CNTL_24"},
507 {.Num: 0xa1aa, .Name: "SPI_PS_INPUT_CNTL_25"},
508 {.Num: 0xa1ab, .Name: "SPI_PS_INPUT_CNTL_26"},
509 {.Num: 0xa1ac, .Name: "SPI_PS_INPUT_CNTL_27"},
510 {.Num: 0xa1ad, .Name: "SPI_PS_INPUT_CNTL_28"},
511 {.Num: 0xa1ae, .Name: "SPI_PS_INPUT_CNTL_29"},
512 {.Num: 0xa1af, .Name: "SPI_PS_INPUT_CNTL_30"},
513 {.Num: 0xa1b0, .Name: "SPI_PS_INPUT_CNTL_31"},
514
515 {.Num: 0xa2ce, .Name: "VGT_GS_MAX_VERT_OUT"},
516 {.Num: 0xa2ab, .Name: "VGT_ESGS_RING_ITEMSIZE"},
517 {.Num: 0xa290, .Name: "VGT_GS_MODE"},
518 {.Num: 0xa291, .Name: "VGT_GS_ONCHIP_CNTL"},
519 {.Num: 0xa2d7, .Name: "VGT_GS_VERT_ITEMSIZE"},
520 {.Num: 0xa2d8, .Name: "VGT_GS_VERT_ITEMSIZE_1"},
521 {.Num: 0xa2d9, .Name: "VGT_GS_VERT_ITEMSIZE_2"},
522 {.Num: 0xa2da, .Name: "VGT_GS_VERT_ITEMSIZE_3"},
523 {.Num: 0xa298, .Name: "VGT_GSVS_RING_OFFSET_1"},
524 {.Num: 0xa299, .Name: "VGT_GSVS_RING_OFFSET_2"},
525 {.Num: 0xa29a, .Name: "VGT_GSVS_RING_OFFSET_3"},
526
527 {.Num: 0xa2e4, .Name: "VGT_GS_INSTANCE_CNT"},
528 {.Num: 0xa297, .Name: "VGT_GS_PER_VS"},
529 {.Num: 0xa29b, .Name: "VGT_GS_OUT_PRIM_TYPE"},
530 {.Num: 0xa2ac, .Name: "VGT_GSVS_RING_ITEMSIZE"},
531
532 {.Num: 0xa2ad, .Name: "VGT_REUSE_OFF"},
533 {.Num: 0xa1b8, .Name: "SPI_BARYC_CNTL"},
534
535 {.Num: 0x2c4c, .Name: "SPI_SHADER_USER_DATA_VS_0"},
536 {.Num: 0x2c4d, .Name: "SPI_SHADER_USER_DATA_VS_1"},
537 {.Num: 0x2c4e, .Name: "SPI_SHADER_USER_DATA_VS_2"},
538 {.Num: 0x2c4f, .Name: "SPI_SHADER_USER_DATA_VS_3"},
539 {.Num: 0x2c50, .Name: "SPI_SHADER_USER_DATA_VS_4"},
540 {.Num: 0x2c51, .Name: "SPI_SHADER_USER_DATA_VS_5"},
541 {.Num: 0x2c52, .Name: "SPI_SHADER_USER_DATA_VS_6"},
542 {.Num: 0x2c53, .Name: "SPI_SHADER_USER_DATA_VS_7"},
543 {.Num: 0x2c54, .Name: "SPI_SHADER_USER_DATA_VS_8"},
544 {.Num: 0x2c55, .Name: "SPI_SHADER_USER_DATA_VS_9"},
545 {.Num: 0x2c56, .Name: "SPI_SHADER_USER_DATA_VS_10"},
546 {.Num: 0x2c57, .Name: "SPI_SHADER_USER_DATA_VS_11"},
547 {.Num: 0x2c58, .Name: "SPI_SHADER_USER_DATA_VS_12"},
548 {.Num: 0x2c59, .Name: "SPI_SHADER_USER_DATA_VS_13"},
549 {.Num: 0x2c5a, .Name: "SPI_SHADER_USER_DATA_VS_14"},
550 {.Num: 0x2c5b, .Name: "SPI_SHADER_USER_DATA_VS_15"},
551 {.Num: 0x2c5c, .Name: "SPI_SHADER_USER_DATA_VS_16"},
552 {.Num: 0x2c5d, .Name: "SPI_SHADER_USER_DATA_VS_17"},
553 {.Num: 0x2c5e, .Name: "SPI_SHADER_USER_DATA_VS_18"},
554 {.Num: 0x2c5f, .Name: "SPI_SHADER_USER_DATA_VS_19"},
555 {.Num: 0x2c60, .Name: "SPI_SHADER_USER_DATA_VS_20"},
556 {.Num: 0x2c61, .Name: "SPI_SHADER_USER_DATA_VS_21"},
557 {.Num: 0x2c62, .Name: "SPI_SHADER_USER_DATA_VS_22"},
558 {.Num: 0x2c63, .Name: "SPI_SHADER_USER_DATA_VS_23"},
559 {.Num: 0x2c64, .Name: "SPI_SHADER_USER_DATA_VS_24"},
560 {.Num: 0x2c65, .Name: "SPI_SHADER_USER_DATA_VS_25"},
561 {.Num: 0x2c66, .Name: "SPI_SHADER_USER_DATA_VS_26"},
562 {.Num: 0x2c67, .Name: "SPI_SHADER_USER_DATA_VS_27"},
563 {.Num: 0x2c68, .Name: "SPI_SHADER_USER_DATA_VS_28"},
564 {.Num: 0x2c69, .Name: "SPI_SHADER_USER_DATA_VS_29"},
565 {.Num: 0x2c6a, .Name: "SPI_SHADER_USER_DATA_VS_30"},
566 {.Num: 0x2c6b, .Name: "SPI_SHADER_USER_DATA_VS_31"},
567
568 {.Num: 0x2c8c, .Name: "SPI_SHADER_USER_DATA_GS_0"},
569 {.Num: 0x2c8d, .Name: "SPI_SHADER_USER_DATA_GS_1"},
570 {.Num: 0x2c8e, .Name: "SPI_SHADER_USER_DATA_GS_2"},
571 {.Num: 0x2c8f, .Name: "SPI_SHADER_USER_DATA_GS_3"},
572 {.Num: 0x2c90, .Name: "SPI_SHADER_USER_DATA_GS_4"},
573 {.Num: 0x2c91, .Name: "SPI_SHADER_USER_DATA_GS_5"},
574 {.Num: 0x2c92, .Name: "SPI_SHADER_USER_DATA_GS_6"},
575 {.Num: 0x2c93, .Name: "SPI_SHADER_USER_DATA_GS_7"},
576 {.Num: 0x2c94, .Name: "SPI_SHADER_USER_DATA_GS_8"},
577 {.Num: 0x2c95, .Name: "SPI_SHADER_USER_DATA_GS_9"},
578 {.Num: 0x2c96, .Name: "SPI_SHADER_USER_DATA_GS_10"},
579 {.Num: 0x2c97, .Name: "SPI_SHADER_USER_DATA_GS_11"},
580 {.Num: 0x2c98, .Name: "SPI_SHADER_USER_DATA_GS_12"},
581 {.Num: 0x2c99, .Name: "SPI_SHADER_USER_DATA_GS_13"},
582 {.Num: 0x2c9a, .Name: "SPI_SHADER_USER_DATA_GS_14"},
583 {.Num: 0x2c9b, .Name: "SPI_SHADER_USER_DATA_GS_15"},
584 {.Num: 0x2c9c, .Name: "SPI_SHADER_USER_DATA_GS_16"},
585 {.Num: 0x2c9d, .Name: "SPI_SHADER_USER_DATA_GS_17"},
586 {.Num: 0x2c9e, .Name: "SPI_SHADER_USER_DATA_GS_18"},
587 {.Num: 0x2c9f, .Name: "SPI_SHADER_USER_DATA_GS_19"},
588 {.Num: 0x2ca0, .Name: "SPI_SHADER_USER_DATA_GS_20"},
589 {.Num: 0x2ca1, .Name: "SPI_SHADER_USER_DATA_GS_21"},
590 {.Num: 0x2ca2, .Name: "SPI_SHADER_USER_DATA_GS_22"},
591 {.Num: 0x2ca3, .Name: "SPI_SHADER_USER_DATA_GS_23"},
592 {.Num: 0x2ca4, .Name: "SPI_SHADER_USER_DATA_GS_24"},
593 {.Num: 0x2ca5, .Name: "SPI_SHADER_USER_DATA_GS_25"},
594 {.Num: 0x2ca6, .Name: "SPI_SHADER_USER_DATA_GS_26"},
595 {.Num: 0x2ca7, .Name: "SPI_SHADER_USER_DATA_GS_27"},
596 {.Num: 0x2ca8, .Name: "SPI_SHADER_USER_DATA_GS_28"},
597 {.Num: 0x2ca9, .Name: "SPI_SHADER_USER_DATA_GS_29"},
598 {.Num: 0x2caa, .Name: "SPI_SHADER_USER_DATA_GS_30"},
599 {.Num: 0x2cab, .Name: "SPI_SHADER_USER_DATA_GS_31"},
600
601 {.Num: 0x2ccc, .Name: "SPI_SHADER_USER_DATA_ES_0"},
602 {.Num: 0x2ccd, .Name: "SPI_SHADER_USER_DATA_ES_1"},
603 {.Num: 0x2cce, .Name: "SPI_SHADER_USER_DATA_ES_2"},
604 {.Num: 0x2ccf, .Name: "SPI_SHADER_USER_DATA_ES_3"},
605 {.Num: 0x2cd0, .Name: "SPI_SHADER_USER_DATA_ES_4"},
606 {.Num: 0x2cd1, .Name: "SPI_SHADER_USER_DATA_ES_5"},
607 {.Num: 0x2cd2, .Name: "SPI_SHADER_USER_DATA_ES_6"},
608 {.Num: 0x2cd3, .Name: "SPI_SHADER_USER_DATA_ES_7"},
609 {.Num: 0x2cd4, .Name: "SPI_SHADER_USER_DATA_ES_8"},
610 {.Num: 0x2cd5, .Name: "SPI_SHADER_USER_DATA_ES_9"},
611 {.Num: 0x2cd6, .Name: "SPI_SHADER_USER_DATA_ES_10"},
612 {.Num: 0x2cd7, .Name: "SPI_SHADER_USER_DATA_ES_11"},
613 {.Num: 0x2cd8, .Name: "SPI_SHADER_USER_DATA_ES_12"},
614 {.Num: 0x2cd9, .Name: "SPI_SHADER_USER_DATA_ES_13"},
615 {.Num: 0x2cda, .Name: "SPI_SHADER_USER_DATA_ES_14"},
616 {.Num: 0x2cdb, .Name: "SPI_SHADER_USER_DATA_ES_15"},
617 {.Num: 0x2cdc, .Name: "SPI_SHADER_USER_DATA_ES_16"},
618 {.Num: 0x2cdd, .Name: "SPI_SHADER_USER_DATA_ES_17"},
619 {.Num: 0x2cde, .Name: "SPI_SHADER_USER_DATA_ES_18"},
620 {.Num: 0x2cdf, .Name: "SPI_SHADER_USER_DATA_ES_19"},
621 {.Num: 0x2ce0, .Name: "SPI_SHADER_USER_DATA_ES_20"},
622 {.Num: 0x2ce1, .Name: "SPI_SHADER_USER_DATA_ES_21"},
623 {.Num: 0x2ce2, .Name: "SPI_SHADER_USER_DATA_ES_22"},
624 {.Num: 0x2ce3, .Name: "SPI_SHADER_USER_DATA_ES_23"},
625 {.Num: 0x2ce4, .Name: "SPI_SHADER_USER_DATA_ES_24"},
626 {.Num: 0x2ce5, .Name: "SPI_SHADER_USER_DATA_ES_25"},
627 {.Num: 0x2ce6, .Name: "SPI_SHADER_USER_DATA_ES_26"},
628 {.Num: 0x2ce7, .Name: "SPI_SHADER_USER_DATA_ES_27"},
629 {.Num: 0x2ce8, .Name: "SPI_SHADER_USER_DATA_ES_28"},
630 {.Num: 0x2ce9, .Name: "SPI_SHADER_USER_DATA_ES_29"},
631 {.Num: 0x2cea, .Name: "SPI_SHADER_USER_DATA_ES_30"},
632 {.Num: 0x2ceb, .Name: "SPI_SHADER_USER_DATA_ES_31"},
633
634 {.Num: 0x2c0c, .Name: "SPI_SHADER_USER_DATA_PS_0"},
635 {.Num: 0x2c0d, .Name: "SPI_SHADER_USER_DATA_PS_1"},
636 {.Num: 0x2c0e, .Name: "SPI_SHADER_USER_DATA_PS_2"},
637 {.Num: 0x2c0f, .Name: "SPI_SHADER_USER_DATA_PS_3"},
638 {.Num: 0x2c10, .Name: "SPI_SHADER_USER_DATA_PS_4"},
639 {.Num: 0x2c11, .Name: "SPI_SHADER_USER_DATA_PS_5"},
640 {.Num: 0x2c12, .Name: "SPI_SHADER_USER_DATA_PS_6"},
641 {.Num: 0x2c13, .Name: "SPI_SHADER_USER_DATA_PS_7"},
642 {.Num: 0x2c14, .Name: "SPI_SHADER_USER_DATA_PS_8"},
643 {.Num: 0x2c15, .Name: "SPI_SHADER_USER_DATA_PS_9"},
644 {.Num: 0x2c16, .Name: "SPI_SHADER_USER_DATA_PS_10"},
645 {.Num: 0x2c17, .Name: "SPI_SHADER_USER_DATA_PS_11"},
646 {.Num: 0x2c18, .Name: "SPI_SHADER_USER_DATA_PS_12"},
647 {.Num: 0x2c19, .Name: "SPI_SHADER_USER_DATA_PS_13"},
648 {.Num: 0x2c1a, .Name: "SPI_SHADER_USER_DATA_PS_14"},
649 {.Num: 0x2c1b, .Name: "SPI_SHADER_USER_DATA_PS_15"},
650 {.Num: 0x2c1c, .Name: "SPI_SHADER_USER_DATA_PS_16"},
651 {.Num: 0x2c1d, .Name: "SPI_SHADER_USER_DATA_PS_17"},
652 {.Num: 0x2c1e, .Name: "SPI_SHADER_USER_DATA_PS_18"},
653 {.Num: 0x2c1f, .Name: "SPI_SHADER_USER_DATA_PS_19"},
654 {.Num: 0x2c20, .Name: "SPI_SHADER_USER_DATA_PS_20"},
655 {.Num: 0x2c21, .Name: "SPI_SHADER_USER_DATA_PS_21"},
656 {.Num: 0x2c22, .Name: "SPI_SHADER_USER_DATA_PS_22"},
657 {.Num: 0x2c23, .Name: "SPI_SHADER_USER_DATA_PS_23"},
658 {.Num: 0x2c24, .Name: "SPI_SHADER_USER_DATA_PS_24"},
659 {.Num: 0x2c25, .Name: "SPI_SHADER_USER_DATA_PS_25"},
660 {.Num: 0x2c26, .Name: "SPI_SHADER_USER_DATA_PS_26"},
661 {.Num: 0x2c27, .Name: "SPI_SHADER_USER_DATA_PS_27"},
662 {.Num: 0x2c28, .Name: "SPI_SHADER_USER_DATA_PS_28"},
663 {.Num: 0x2c29, .Name: "SPI_SHADER_USER_DATA_PS_29"},
664 {.Num: 0x2c2a, .Name: "SPI_SHADER_USER_DATA_PS_30"},
665 {.Num: 0x2c2b, .Name: "SPI_SHADER_USER_DATA_PS_31"},
666
667 {.Num: 0x2e40, .Name: "COMPUTE_USER_DATA_0"},
668 {.Num: 0x2e41, .Name: "COMPUTE_USER_DATA_1"},
669 {.Num: 0x2e42, .Name: "COMPUTE_USER_DATA_2"},
670 {.Num: 0x2e43, .Name: "COMPUTE_USER_DATA_3"},
671 {.Num: 0x2e44, .Name: "COMPUTE_USER_DATA_4"},
672 {.Num: 0x2e45, .Name: "COMPUTE_USER_DATA_5"},
673 {.Num: 0x2e46, .Name: "COMPUTE_USER_DATA_6"},
674 {.Num: 0x2e47, .Name: "COMPUTE_USER_DATA_7"},
675 {.Num: 0x2e48, .Name: "COMPUTE_USER_DATA_8"},
676 {.Num: 0x2e49, .Name: "COMPUTE_USER_DATA_9"},
677 {.Num: 0x2e4a, .Name: "COMPUTE_USER_DATA_10"},
678 {.Num: 0x2e4b, .Name: "COMPUTE_USER_DATA_11"},
679 {.Num: 0x2e4c, .Name: "COMPUTE_USER_DATA_12"},
680 {.Num: 0x2e4d, .Name: "COMPUTE_USER_DATA_13"},
681 {.Num: 0x2e4e, .Name: "COMPUTE_USER_DATA_14"},
682 {.Num: 0x2e4f, .Name: "COMPUTE_USER_DATA_15"},
683
684 {.Num: 0x2e07, .Name: "COMPUTE_NUM_THREAD_X"},
685 {.Num: 0x2e08, .Name: "COMPUTE_NUM_THREAD_Y"},
686 {.Num: 0x2e09, .Name: "COMPUTE_NUM_THREAD_Z"},
687 {.Num: 0xa2db, .Name: "VGT_TF_PARAM"},
688 {.Num: 0xa2d6, .Name: "VGT_LS_HS_CONFIG"},
689 {.Num: 0xa287, .Name: "VGT_HOS_MIN_TESS_LEVEL"},
690 {.Num: 0xa286, .Name: "VGT_HOS_MAX_TESS_LEVEL"},
691 {.Num: 0xa2f8, .Name: "PA_SC_AA_CONFIG"},
692 {.Num: 0xa310, .Name: "PA_SC_SHADER_CONTROL"},
693 {.Num: 0xa313, .Name: "PA_SC_CONSERVATIVE_RASTERIZATION_CNTL"},
694
695 {.Num: 0x2d0c, .Name: "SPI_SHADER_USER_DATA_HS_0"},
696 {.Num: 0x2d0d, .Name: "SPI_SHADER_USER_DATA_HS_1"},
697 {.Num: 0x2d0e, .Name: "SPI_SHADER_USER_DATA_HS_2"},
698 {.Num: 0x2d0f, .Name: "SPI_SHADER_USER_DATA_HS_3"},
699 {.Num: 0x2d10, .Name: "SPI_SHADER_USER_DATA_HS_4"},
700 {.Num: 0x2d11, .Name: "SPI_SHADER_USER_DATA_HS_5"},
701 {.Num: 0x2d12, .Name: "SPI_SHADER_USER_DATA_HS_6"},
702 {.Num: 0x2d13, .Name: "SPI_SHADER_USER_DATA_HS_7"},
703 {.Num: 0x2d14, .Name: "SPI_SHADER_USER_DATA_HS_8"},
704 {.Num: 0x2d15, .Name: "SPI_SHADER_USER_DATA_HS_9"},
705 {.Num: 0x2d16, .Name: "SPI_SHADER_USER_DATA_HS_10"},
706 {.Num: 0x2d17, .Name: "SPI_SHADER_USER_DATA_HS_11"},
707 {.Num: 0x2d18, .Name: "SPI_SHADER_USER_DATA_HS_12"},
708 {.Num: 0x2d19, .Name: "SPI_SHADER_USER_DATA_HS_13"},
709 {.Num: 0x2d1a, .Name: "SPI_SHADER_USER_DATA_HS_14"},
710 {.Num: 0x2d1b, .Name: "SPI_SHADER_USER_DATA_HS_15"},
711 {.Num: 0x2d1c, .Name: "SPI_SHADER_USER_DATA_HS_16"},
712 {.Num: 0x2d1d, .Name: "SPI_SHADER_USER_DATA_HS_17"},
713 {.Num: 0x2d1e, .Name: "SPI_SHADER_USER_DATA_HS_18"},
714 {.Num: 0x2d1f, .Name: "SPI_SHADER_USER_DATA_HS_19"},
715 {.Num: 0x2d20, .Name: "SPI_SHADER_USER_DATA_HS_20"},
716 {.Num: 0x2d21, .Name: "SPI_SHADER_USER_DATA_HS_21"},
717 {.Num: 0x2d22, .Name: "SPI_SHADER_USER_DATA_HS_22"},
718 {.Num: 0x2d23, .Name: "SPI_SHADER_USER_DATA_HS_23"},
719 {.Num: 0x2d24, .Name: "SPI_SHADER_USER_DATA_HS_24"},
720 {.Num: 0x2d25, .Name: "SPI_SHADER_USER_DATA_HS_25"},
721 {.Num: 0x2d26, .Name: "SPI_SHADER_USER_DATA_HS_26"},
722 {.Num: 0x2d27, .Name: "SPI_SHADER_USER_DATA_HS_27"},
723 {.Num: 0x2d28, .Name: "SPI_SHADER_USER_DATA_HS_28"},
724 {.Num: 0x2d29, .Name: "SPI_SHADER_USER_DATA_HS_29"},
725 {.Num: 0x2d2a, .Name: "SPI_SHADER_USER_DATA_HS_30"},
726 {.Num: 0x2d2b, .Name: "SPI_SHADER_USER_DATA_HS_31"},
727
728 {.Num: 0x2d4c, .Name: "SPI_SHADER_USER_DATA_LS_0"},
729 {.Num: 0x2d4d, .Name: "SPI_SHADER_USER_DATA_LS_1"},
730 {.Num: 0x2d4e, .Name: "SPI_SHADER_USER_DATA_LS_2"},
731 {.Num: 0x2d4f, .Name: "SPI_SHADER_USER_DATA_LS_3"},
732 {.Num: 0x2d50, .Name: "SPI_SHADER_USER_DATA_LS_4"},
733 {.Num: 0x2d51, .Name: "SPI_SHADER_USER_DATA_LS_5"},
734 {.Num: 0x2d52, .Name: "SPI_SHADER_USER_DATA_LS_6"},
735 {.Num: 0x2d53, .Name: "SPI_SHADER_USER_DATA_LS_7"},
736 {.Num: 0x2d54, .Name: "SPI_SHADER_USER_DATA_LS_8"},
737 {.Num: 0x2d55, .Name: "SPI_SHADER_USER_DATA_LS_9"},
738 {.Num: 0x2d56, .Name: "SPI_SHADER_USER_DATA_LS_10"},
739 {.Num: 0x2d57, .Name: "SPI_SHADER_USER_DATA_LS_11"},
740 {.Num: 0x2d58, .Name: "SPI_SHADER_USER_DATA_LS_12"},
741 {.Num: 0x2d59, .Name: "SPI_SHADER_USER_DATA_LS_13"},
742 {.Num: 0x2d5a, .Name: "SPI_SHADER_USER_DATA_LS_14"},
743 {.Num: 0x2d5b, .Name: "SPI_SHADER_USER_DATA_LS_15"},
744
745 {.Num: 0xa2aa, .Name: "IA_MULTI_VGT_PARAM"},
746 {.Num: 0xa2a5, .Name: "VGT_GS_MAX_PRIMS_PER_SUBGROUP"},
747 {.Num: 0xa2e6, .Name: "VGT_STRMOUT_BUFFER_CONFIG"},
748 {.Num: 0xa2e5, .Name: "VGT_STRMOUT_CONFIG"},
749 {.Num: 0xa2b5, .Name: "VGT_STRMOUT_VTX_STRIDE_0"},
750 {.Num: 0xa2b9, .Name: "VGT_STRMOUT_VTX_STRIDE_1"},
751 {.Num: 0xa2bd, .Name: "VGT_STRMOUT_VTX_STRIDE_2"},
752 {.Num: 0xa2c1, .Name: "VGT_STRMOUT_VTX_STRIDE_3"},
753 {.Num: 0xa316, .Name: "VGT_VERTEX_REUSE_BLOCK_CNTL"},
754
755 {.Num: 0x2e28, .Name: "COMPUTE_PGM_RSRC3"},
756 {.Num: 0x2e2a, .Name: "COMPUTE_SHADER_CHKSUM"},
757 {.Num: 0x2e24, .Name: "COMPUTE_USER_ACCUM_0"},
758 {.Num: 0x2e25, .Name: "COMPUTE_USER_ACCUM_1"},
759 {.Num: 0x2e26, .Name: "COMPUTE_USER_ACCUM_2"},
760 {.Num: 0x2e27, .Name: "COMPUTE_USER_ACCUM_3"},
761 {.Num: 0xa1ff, .Name: "GE_MAX_OUTPUT_PER_SUBGROUP"},
762 {.Num: 0xa2d3, .Name: "GE_NGG_SUBGRP_CNTL"},
763 {.Num: 0xc25f, .Name: "GE_STEREO_CNTL"},
764 {.Num: 0xc262, .Name: "GE_USER_VGPR_EN"},
765 {.Num: 0xc258, .Name: "IA_MULTI_VGT_PARAM_PIPED"},
766 {.Num: 0xa210, .Name: "PA_STEREO_CNTL"},
767 {.Num: 0xa1c2, .Name: "SPI_SHADER_IDX_FORMAT"},
768 {.Num: 0x2c80, .Name: "SPI_SHADER_PGM_CHKSUM_GS"},
769 {.Num: 0x2d00, .Name: "SPI_SHADER_PGM_CHKSUM_HS"},
770 {.Num: 0x2c06, .Name: "SPI_SHADER_PGM_CHKSUM_PS"},
771 {.Num: 0x2c45, .Name: "SPI_SHADER_PGM_CHKSUM_VS"},
772 {.Num: 0x2c88, .Name: "SPI_SHADER_PGM_LO_GS"},
773 {.Num: 0x2cb2, .Name: "SPI_SHADER_USER_ACCUM_ESGS_0"},
774 {.Num: 0x2cb3, .Name: "SPI_SHADER_USER_ACCUM_ESGS_1"},
775 {.Num: 0x2cb4, .Name: "SPI_SHADER_USER_ACCUM_ESGS_2"},
776 {.Num: 0x2cb5, .Name: "SPI_SHADER_USER_ACCUM_ESGS_3"},
777 {.Num: 0x2d32, .Name: "SPI_SHADER_USER_ACCUM_LSHS_0"},
778 {.Num: 0x2d33, .Name: "SPI_SHADER_USER_ACCUM_LSHS_1"},
779 {.Num: 0x2d34, .Name: "SPI_SHADER_USER_ACCUM_LSHS_2"},
780 {.Num: 0x2d35, .Name: "SPI_SHADER_USER_ACCUM_LSHS_3"},
781 {.Num: 0x2c32, .Name: "SPI_SHADER_USER_ACCUM_PS_0"},
782 {.Num: 0x2c33, .Name: "SPI_SHADER_USER_ACCUM_PS_1"},
783 {.Num: 0x2c34, .Name: "SPI_SHADER_USER_ACCUM_PS_2"},
784 {.Num: 0x2c35, .Name: "SPI_SHADER_USER_ACCUM_PS_3"},
785 {.Num: 0x2c72, .Name: "SPI_SHADER_USER_ACCUM_VS_0"},
786 {.Num: 0x2c73, .Name: "SPI_SHADER_USER_ACCUM_VS_1"},
787 {.Num: 0x2c74, .Name: "SPI_SHADER_USER_ACCUM_VS_2"},
788 {.Num: 0x2c75, .Name: "SPI_SHADER_USER_ACCUM_VS_3"},
789
790 {.Num: 0, .Name: nullptr}};
791 const auto *Entry = RegInfoTable;
792 for (; Entry->Num && Entry->Num != RegNum; ++Entry)
793 ;
794 return Entry->Name;
795}
796
797// Convert the accumulated PAL metadata into an asm directive.
798void AMDGPUPALMetadata::toString(std::string &String) {
799 String.clear();
800 if (!BlobType)
801 return;
802 ResolvedAll = DelayedExprs.resolveDelayedExpressions();
803 raw_string_ostream Stream(String);
804 if (isLegacy()) {
805 if (MsgPackDoc.getRoot().getKind() == msgpack::Type::Nil)
806 return;
807 // Old linear reg=val format.
808 Stream << '\t' << AMDGPU::PALMD::AssemblerDirective << ' ';
809 auto Regs = getRegisters();
810 for (auto I = Regs.begin(), E = Regs.end(); I != E; ++I) {
811 if (I != Regs.begin())
812 Stream << ',';
813 unsigned Reg = I->first.getUInt();
814 unsigned Val = I->second.getUInt();
815 Stream << "0x" << Twine::utohexstr(Val: Reg) << ",0x" << Twine::utohexstr(Val);
816 }
817 Stream << '\n';
818 return;
819 }
820
821 // New msgpack-based format -- output as YAML (with unsigned numbers in hex),
822 // but first change the registers map to use names.
823 MsgPackDoc.setHexMode();
824 auto &RegsObj = refRegisters();
825 auto OrigRegs = RegsObj.getMap();
826 RegsObj = MsgPackDoc.getMapNode();
827 for (auto I : OrigRegs) {
828 auto Key = I.first;
829 if (const char *RegName = getRegisterName(RegNum: Key.getUInt())) {
830 std::string KeyName = Key.toString();
831 KeyName += " (";
832 KeyName += RegName;
833 KeyName += ')';
834 Key = MsgPackDoc.getNode(V: KeyName, /*Copy=*/true);
835 }
836 RegsObj.getMap()[Key] = I.second;
837 }
838
839 // Output as YAML.
840 Stream << '\t' << AMDGPU::PALMD::AssemblerDirectiveBegin << '\n';
841 MsgPackDoc.toYAML(OS&: Stream);
842 Stream << '\t' << AMDGPU::PALMD::AssemblerDirectiveEnd << '\n';
843
844 // Restore original registers map.
845 RegsObj = OrigRegs;
846}
847
848// Convert the accumulated PAL metadata into a binary blob for writing as
849// a .note record of the specified AMD type. Returns an empty blob if
850// there is no PAL metadata,
851void AMDGPUPALMetadata::toBlob(unsigned Type, std::string &Blob) {
852 ResolvedAll = DelayedExprs.resolveDelayedExpressions();
853 if (Type == ELF::NT_AMD_PAL_METADATA)
854 toLegacyBlob(Blob);
855 else if (Type)
856 toMsgPackBlob(Blob);
857}
858
859void AMDGPUPALMetadata::toLegacyBlob(std::string &Blob) {
860 Blob.clear();
861 auto Registers = getRegisters();
862 if (Registers.getMap().empty())
863 return;
864 raw_string_ostream OS(Blob);
865 support::endian::Writer EW(OS, llvm::endianness::little);
866 for (auto I : Registers.getMap()) {
867 EW.write(Val: uint32_t(I.first.getUInt()));
868 EW.write(Val: uint32_t(I.second.getUInt()));
869 }
870}
871
872void AMDGPUPALMetadata::toMsgPackBlob(std::string &Blob) {
873 Blob.clear();
874 MsgPackDoc.writeToBlob(Blob);
875}
876
877// Set PAL metadata from YAML text. Returns false if failed.
878bool AMDGPUPALMetadata::setFromString(StringRef S) {
879 BlobType = ELF::NT_AMDGPU_METADATA;
880 if (!MsgPackDoc.fromYAML(S))
881 return false;
882
883 // In the registers map, some keys may be of the form "0xa191
884 // (SPI_PS_INPUT_CNTL_0)", in which case the YAML input code made it a
885 // string. We need to turn it into a number.
886 auto &RegsObj = refRegisters();
887 auto OrigRegs = RegsObj;
888 RegsObj = MsgPackDoc.getMapNode();
889 Registers = RegsObj.getMap();
890 bool Ok = true;
891 for (auto I : OrigRegs.getMap()) {
892 auto Key = I.first;
893 if (Key.getKind() == msgpack::Type::String) {
894 StringRef S = Key.getString();
895 uint64_t Val;
896 if (S.consumeInteger(Radix: 0, Result&: Val)) {
897 Ok = false;
898 errs() << "Unrecognized PAL metadata register key '" << S << "'\n";
899 continue;
900 }
901 Key = MsgPackDoc.getNode(V: Val);
902 }
903 Registers.getMap()[Key] = I.second;
904 }
905 return Ok;
906}
907
908// Reference (create if necessary) the node for the registers map.
909msgpack::DocNode &AMDGPUPALMetadata::refRegisters() {
910 auto &N =
911 MsgPackDoc.getRoot()
912 .getMap(/*Convert=*/true)[MsgPackDoc.getNode(V: "amdpal.pipelines")]
913 .getArray(/*Convert=*/true)[0]
914 .getMap(/*Convert=*/true)[MsgPackDoc.getNode(V: ".registers")];
915 N.getMap(/*Convert=*/true);
916 return N;
917}
918
919// Get (create if necessary) the registers map.
920msgpack::MapDocNode AMDGPUPALMetadata::getRegisters() {
921 if (Registers.isEmpty())
922 Registers = refRegisters();
923 return Registers.getMap();
924}
925
926// Reference (create if necessary) the node for the shader functions map.
927msgpack::DocNode &AMDGPUPALMetadata::refShaderFunctions() {
928 auto &N =
929 MsgPackDoc.getRoot()
930 .getMap(/*Convert=*/true)[MsgPackDoc.getNode(V: "amdpal.pipelines")]
931 .getArray(/*Convert=*/true)[0]
932 .getMap(/*Convert=*/true)[MsgPackDoc.getNode(V: ".shader_functions")];
933 N.getMap(/*Convert=*/true);
934 return N;
935}
936
937// Get (create if necessary) the shader functions map.
938msgpack::MapDocNode AMDGPUPALMetadata::getShaderFunctions() {
939 if (ShaderFunctions.isEmpty())
940 ShaderFunctions = refShaderFunctions();
941 return ShaderFunctions.getMap();
942}
943
944// Get (create if necessary) a function in the shader functions map.
945msgpack::MapDocNode AMDGPUPALMetadata::getShaderFunction(StringRef Name) {
946 auto Functions = getShaderFunctions();
947 return Functions[Name].getMap(/*Convert=*/true);
948}
949
950msgpack::DocNode &AMDGPUPALMetadata::refComputeRegisters() {
951 auto &N =
952 MsgPackDoc.getRoot()
953 .getMap(/*Convert=*/true)[MsgPackDoc.getNode(V: "amdpal.pipelines")]
954 .getArray(/*Convert=*/true)[0]
955 .getMap(/*Convert=*/true)[MsgPackDoc.getNode(V: ".compute_registers")];
956 N.getMap(/*Convert=*/true);
957 return N;
958}
959
960msgpack::MapDocNode AMDGPUPALMetadata::getComputeRegisters() {
961 if (ComputeRegisters.isEmpty())
962 ComputeRegisters = refComputeRegisters();
963 return ComputeRegisters.getMap();
964}
965
966msgpack::DocNode &AMDGPUPALMetadata::refGraphicsRegisters() {
967 auto &N =
968 MsgPackDoc.getRoot()
969 .getMap(/*Convert=*/true)[MsgPackDoc.getNode(V: "amdpal.pipelines")]
970 .getArray(/*Convert=*/true)[0]
971 .getMap(/*Convert=*/true)[MsgPackDoc.getNode(V: ".graphics_registers")];
972 N.getMap(/*Convert=*/true);
973 return N;
974}
975
976msgpack::MapDocNode AMDGPUPALMetadata::getGraphicsRegisters() {
977 if (GraphicsRegisters.isEmpty())
978 GraphicsRegisters = refGraphicsRegisters();
979 return GraphicsRegisters.getMap();
980}
981
982msgpack::DocNode &AMDGPUPALMetadata::refHwStage() {
983 auto &N =
984 MsgPackDoc.getRoot()
985 .getMap(/*Convert=*/true)[MsgPackDoc.getNode(V: "amdpal.pipelines")]
986 .getArray(/*Convert=*/true)[0]
987 .getMap(/*Convert=*/true)[MsgPackDoc.getNode(V: ".hardware_stages")];
988 N.getMap(/*Convert=*/true);
989 return N;
990}
991
992// Get (create if necessary) the .hardware_stages entry for the given calling
993// convention.
994msgpack::MapDocNode AMDGPUPALMetadata::getHwStage(unsigned CC) {
995 if (HwStages.isEmpty())
996 HwStages = refHwStage();
997 return HwStages.getMap()[getStageName(CC)].getMap(/*Convert=*/true);
998}
999
1000// Get .note record vendor name of metadata blob to be emitted.
1001const char *AMDGPUPALMetadata::getVendor() const {
1002 return isLegacy() ? ElfNote::NoteNameV2 : ElfNote::NoteNameV3;
1003}
1004
1005// Get .note record type of metadata blob to be emitted:
1006// ELF::NT_AMD_PAL_METADATA (legacy key=val format), or
1007// ELF::NT_AMDGPU_METADATA (MsgPack format), or
1008// 0 (no PAL metadata).
1009unsigned AMDGPUPALMetadata::getType() const {
1010 return BlobType;
1011}
1012
1013// Return whether the blob type is legacy PAL metadata.
1014bool AMDGPUPALMetadata::isLegacy() const {
1015 return BlobType == ELF::NT_AMD_PAL_METADATA;
1016}
1017
1018// Set legacy PAL metadata format.
1019void AMDGPUPALMetadata::setLegacy() {
1020 BlobType = ELF::NT_AMD_PAL_METADATA;
1021}
1022
1023// Erase all PAL metadata.
1024void AMDGPUPALMetadata::reset() {
1025 MsgPackDoc.clear();
1026 REM.clear();
1027 DelayedExprs.clear();
1028 Registers = MsgPackDoc.getEmptyNode();
1029 HwStages = MsgPackDoc.getEmptyNode();
1030 ShaderFunctions = MsgPackDoc.getEmptyNode();
1031}
1032
1033bool AMDGPUPALMetadata::resolvedAllMCExpr() {
1034 return ResolvedAll && DelayedExprs.empty();
1035}
1036
1037unsigned AMDGPUPALMetadata::getPALVersion(unsigned idx) {
1038 assert(idx < 2 &&
1039 "illegal index to PAL version - should be 0 (major) or 1 (minor)");
1040 if (!VersionChecked) {
1041 if (Version.isEmpty()) {
1042 auto &M = MsgPackDoc.getRoot().getMap(/*Convert=*/true);
1043 auto I = M.find(Key: MsgPackDoc.getNode(V: "amdpal.version"));
1044 if (I != M.end())
1045 Version = I->second;
1046 }
1047 VersionChecked = true;
1048 }
1049 if (Version.isEmpty())
1050 // Default to 2.6 if there's no version info
1051 return idx ? 6 : 2;
1052 return Version.getArray()[idx].getUInt();
1053}
1054
1055unsigned AMDGPUPALMetadata::getPALMajorVersion() { return getPALVersion(idx: 0); }
1056
1057unsigned AMDGPUPALMetadata::getPALMinorVersion() { return getPALVersion(idx: 1); }
1058
1059VersionTuple AMDGPUPALMetadata::getPALVersion() {
1060 return VersionTuple(getPALVersion(idx: 0), getPALVersion(idx: 1));
1061}
1062
1063// Set the field in a given .hardware_stages entry
1064void AMDGPUPALMetadata::setHwStage(unsigned CC, StringRef field, unsigned Val) {
1065 getHwStage(CC)[field] = Val;
1066}
1067
1068void AMDGPUPALMetadata::setHwStage(unsigned CC, StringRef field, bool Val) {
1069 getHwStage(CC)[field] = Val;
1070}
1071
1072void AMDGPUPALMetadata::setHwStage(unsigned CC, StringRef field,
1073 msgpack::Type Type, const MCExpr *Val) {
1074 DelayedExprs.assignDocNode(DN&: getHwStage(CC)[field], Type, ExprValue: Val);
1075}
1076
1077void AMDGPUPALMetadata::setComputeRegisters(StringRef field, unsigned Val) {
1078 getComputeRegisters()[field] = Val;
1079}
1080
1081void AMDGPUPALMetadata::setComputeRegisters(StringRef field, bool Val) {
1082 getComputeRegisters()[field] = Val;
1083}
1084
1085msgpack::DocNode *AMDGPUPALMetadata::refComputeRegister(StringRef field) {
1086 auto M = getComputeRegisters();
1087 auto I = M.find(Key: field);
1088 return I == M.end() ? nullptr : &I->second;
1089}
1090
1091bool AMDGPUPALMetadata::checkComputeRegisters(StringRef field, unsigned Val) {
1092 if (auto *N = refComputeRegister(field))
1093 return N->getUInt() == Val;
1094 return false;
1095}
1096
1097bool AMDGPUPALMetadata::checkComputeRegisters(StringRef field, bool Val) {
1098 if (auto *N = refComputeRegister(field))
1099 return N->getBool() == Val;
1100 return false;
1101}
1102
1103void AMDGPUPALMetadata::setGraphicsRegisters(StringRef field, unsigned Val) {
1104 getGraphicsRegisters()[field] = Val;
1105}
1106
1107void AMDGPUPALMetadata::setGraphicsRegisters(StringRef field, bool Val) {
1108 getGraphicsRegisters()[field] = Val;
1109}
1110
1111void AMDGPUPALMetadata::setGraphicsRegisters(StringRef field1, StringRef field2,
1112 unsigned Val) {
1113 getGraphicsRegisters()[field1].getMap(Convert: true)[field2] = Val;
1114}
1115
1116void AMDGPUPALMetadata::setGraphicsRegisters(StringRef field1, StringRef field2,
1117 bool Val) {
1118 getGraphicsRegisters()[field1].getMap(Convert: true)[field2] = Val;
1119}
1120