1//===-- ARMTargetMachine.h - Define TargetMachine for ARM -------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares the ARM specific subclass of TargetMachine.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H
14#define LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H
15
16#include "ARMSubtarget.h"
17#include "llvm/ADT/StringMap.h"
18#include "llvm/ADT/StringRef.h"
19#include "llvm/Analysis/TargetTransformInfo.h"
20#include "llvm/CodeGen/CodeGenTargetMachineImpl.h"
21#include "llvm/Support/CodeGen.h"
22#include "llvm/Target/TargetMachine.h"
23#include "llvm/TargetParser/ARMTargetParser.h"
24#include <memory>
25#include <optional>
26
27namespace llvm {
28
29class ARMBaseTargetMachine : public CodeGenTargetMachineImpl {
30public:
31 ARM::ARMABI TargetABI;
32
33protected:
34 std::unique_ptr<TargetLoweringObjectFile> TLOF;
35 bool isLittle;
36 mutable StringMap<std::unique_ptr<ARMSubtarget>> SubtargetMap;
37
38 /// Reset internal state.
39 void reset() override;
40
41public:
42 ARMBaseTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
43 StringRef FS, const TargetOptions &Options,
44 std::optional<Reloc::Model> RM,
45 std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
46 bool isLittle);
47 ~ARMBaseTargetMachine() override;
48
49 const ARMSubtarget *getSubtargetImpl(const Function &F) const override;
50 // DO NOT IMPLEMENT: There is no such thing as a valid default subtarget,
51 // subtargets are per-function entities based on the target-specific
52 // attributes of each function.
53 const ARMSubtarget *getSubtargetImpl() const = delete;
54 bool isLittleEndian() const { return isLittle; }
55
56 TargetTransformInfo getTargetTransformInfo(const Function &F) const override;
57
58 // Pass Pipeline Configuration
59 TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
60
61 TargetLoweringObjectFile *getObjFileLowering() const override {
62 return TLOF.get();
63 }
64
65 bool isAPCS_ABI() const {
66 assert(TargetABI != ARM::ARM_ABI_UNKNOWN);
67 return TargetABI == ARM::ARM_ABI_APCS;
68 }
69
70 bool isAAPCS_ABI() const {
71 assert(TargetABI != ARM::ARM_ABI_UNKNOWN);
72 return TargetABI == ARM::ARM_ABI_AAPCS || TargetABI == ARM::ARM_ABI_AAPCS16;
73 }
74
75 bool isAAPCS16_ABI() const {
76 assert(TargetABI != ARM::ARM_ABI_UNKNOWN);
77 return TargetABI == ARM::ARM_ABI_AAPCS16;
78 }
79
80 bool isTargetHardFloat() const {
81 return TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
82 TargetTriple.getEnvironment() == Triple::GNUEABIHFT64 ||
83 TargetTriple.getEnvironment() == Triple::MuslEABIHF ||
84 TargetTriple.getEnvironment() == Triple::EABIHF ||
85 (TargetTriple.isOSBinFormatMachO() &&
86 TargetTriple.getSubArch() == Triple::ARMSubArch_v7em) ||
87 TargetTriple.isOSWindows() || TargetABI == ARM::ARM_ABI_AAPCS16;
88 }
89
90 bool targetSchedulesPostRAScheduling() const override { return true; };
91
92 MachineFunctionInfo *
93 createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
94 const TargetSubtargetInfo *STI) const override;
95
96 /// Returns true if a cast between SrcAS and DestAS is a noop.
97 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
98 // Addrspacecasts are always noops.
99 return true;
100 }
101
102 yaml::MachineFunctionInfo *createDefaultFuncInfoYAML() const override;
103 yaml::MachineFunctionInfo *
104 convertFuncInfoToYAML(const MachineFunction &MF) const override;
105 bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &,
106 PerFunctionMIParsingState &PFS,
107 SMDiagnostic &Error,
108 SMRange &SourceRange) const override;
109 ScheduleDAGInstrs *
110 createMachineScheduler(MachineSchedContext *C) const override;
111 ScheduleDAGInstrs *
112 createPostMachineScheduler(MachineSchedContext *C) const override;
113};
114
115/// ARM/Thumb little endian target machine.
116///
117class ARMLETargetMachine : public ARMBaseTargetMachine {
118public:
119 ARMLETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
120 StringRef FS, const TargetOptions &Options,
121 std::optional<Reloc::Model> RM,
122 std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
123 bool JIT);
124};
125
126/// ARM/Thumb big endian target machine.
127///
128class ARMBETargetMachine : public ARMBaseTargetMachine {
129public:
130 ARMBETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
131 StringRef FS, const TargetOptions &Options,
132 std::optional<Reloc::Model> RM,
133 std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
134 bool JIT);
135};
136
137} // end namespace llvm
138
139#endif // LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H
140