1//===---- MipsISelDAGToDAG.h - A Dag to Dag Inst Selector for Mips --------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines an instruction selector for the MIPS target.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_MIPS_MIPSISELDAGTODAG_H
14#define LLVM_LIB_TARGET_MIPS_MIPSISELDAGTODAG_H
15
16#include "Mips.h"
17#include "MipsSubtarget.h"
18#include "MipsTargetMachine.h"
19#include "llvm/CodeGen/SelectionDAGISel.h"
20
21//===----------------------------------------------------------------------===//
22// Instruction Selector Implementation
23//===----------------------------------------------------------------------===//
24
25//===----------------------------------------------------------------------===//
26// MipsDAGToDAGISel - MIPS specific code to select MIPS machine
27// instructions for SelectionDAG operations.
28//===----------------------------------------------------------------------===//
29namespace llvm {
30
31class MipsDAGToDAGISel : public SelectionDAGISel {
32public:
33 MipsDAGToDAGISel() = delete;
34
35 explicit MipsDAGToDAGISel(MipsTargetMachine &TM, CodeGenOptLevel OL)
36 : SelectionDAGISel(TM, OL), Subtarget(nullptr) {}
37
38 bool runOnMachineFunction(MachineFunction &MF) override;
39
40protected:
41 SDNode *getGlobalBaseReg();
42
43 /// Keep a pointer to the MipsSubtarget around so that we can make the right
44 /// decision when generating code for different targets.
45 const MipsSubtarget *Subtarget;
46
47private:
48 // Include the pieces autogenerated from the target description.
49 #include "MipsGenDAGISel.inc"
50
51 // Complex Pattern.
52 /// (reg + imm).
53 virtual bool selectAddrRegImm(SDValue Addr, SDValue &Base,
54 SDValue &Offset) const;
55
56 /// Fall back on this function if all else fails.
57 virtual bool selectAddrDefault(SDValue Addr, SDValue &Base,
58 SDValue &Offset) const;
59
60 /// Match integer address pattern.
61 virtual bool selectIntAddr(SDValue Addr, SDValue &Base,
62 SDValue &Offset) const;
63
64 virtual bool selectIntAddr11MM(SDValue Addr, SDValue &Base,
65 SDValue &Offset) const;
66
67 virtual bool selectIntAddr12MM(SDValue Addr, SDValue &Base,
68 SDValue &Offset) const;
69
70 virtual bool selectIntAddr16MM(SDValue Addr, SDValue &Base,
71 SDValue &Offset) const;
72
73 virtual bool selectIntAddrLSL2MM(SDValue Addr, SDValue &Base,
74 SDValue &Offset) const;
75
76 /// Match addr+simm10 and addr
77 virtual bool selectIntAddrSImm10(SDValue Addr, SDValue &Base,
78 SDValue &Offset) const;
79
80 virtual bool selectIntAddrSImm10Lsl1(SDValue Addr, SDValue &Base,
81 SDValue &Offset) const;
82
83 virtual bool selectIntAddrSImm10Lsl2(SDValue Addr, SDValue &Base,
84 SDValue &Offset) const;
85
86 virtual bool selectIntAddrSImm10Lsl3(SDValue Addr, SDValue &Base,
87 SDValue &Offset) const;
88
89 virtual bool selectAddr16(SDValue Addr, SDValue &Base, SDValue &Offset);
90 virtual bool selectAddr16SP(SDValue Addr, SDValue &Base, SDValue &Offset);
91
92 /// Select constant vector splats.
93 virtual bool selectVSplat(SDNode *N, APInt &Imm,
94 unsigned MinSizeInBits) const;
95 virtual bool selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed,
96 unsigned ImmBitSize) const;
97 /// Select constant vector splats whose value fits in a uimm<Bits>.
98 template <unsigned Bits>
99 bool selectVSplatUimm(SDValue N, SDValue &Imm) const {
100 return selectVSplatCommon(N, Imm, Signed: false, ImmBitSize: Bits);
101 }
102 /// Select constant vector splats whose value fits in a simm<Bits>.
103 template <unsigned Bits>
104 bool selectVSplatSimm(SDValue N, SDValue &Imm) const {
105 return selectVSplatCommon(N, Imm, Signed: true, ImmBitSize: Bits);
106 }
107 /// Select constant vector splats whose value is a power of 2.
108 virtual bool selectVSplatUimmPow2(SDValue N, SDValue &Imm) const;
109 /// Select constant vector splats whose value is the inverse of a
110 /// power of 2.
111 virtual bool selectVSplatUimmInvPow2(SDValue N, SDValue &Imm) const;
112 /// Select constant vector splats whose value is a run of set bits
113 /// ending at the most significant bit
114 virtual bool selectVSplatMaskL(SDValue N, SDValue &Imm) const;
115 /// Select constant vector splats whose value is a run of set bits
116 /// starting at bit zero.
117 virtual bool selectVSplatMaskR(SDValue N, SDValue &Imm) const;
118
119 /// Select constant vector splats whose value is 1.
120 virtual bool selectVSplatImmEq1(SDValue N) const;
121
122 /// Convert vector addition with vector subtraction if that allows to encode
123 /// constant as an immediate and thus avoid extra 'ldi' instruction.
124 /// add X, <-1, -1...> --> sub X, <1, 1...>
125 bool selectVecAddAsVecSubIfProfitable(SDNode *Node);
126
127 void Select(SDNode *N) override;
128
129 virtual bool trySelect(SDNode *Node) = 0;
130
131 // getImm - Return a target constant with the specified value.
132 inline SDValue getImm(const SDNode *Node, uint64_t Imm) {
133 return CurDAG->getTargetConstant(Val: Imm, DL: SDLoc(Node), VT: Node->getValueType(ResNo: 0));
134 }
135
136 inline SDValue getSignedImm(const SDNode *Node, int64_t Imm) {
137 return CurDAG->getSignedTargetConstant(Val: Imm, DL: SDLoc(Node),
138 VT: Node->getValueType(ResNo: 0));
139 }
140
141 virtual void processFunctionAfterISel(MachineFunction &MF) = 0;
142
143 bool SelectInlineAsmMemoryOperand(const SDValue &Op,
144 InlineAsm::ConstraintCode ConstraintID,
145 std::vector<SDValue> &OutOps) override;
146 bool isUnneededShiftMask(SDNode *N, unsigned ShAmtBits) const;
147};
148
149class MipsDAGToDAGISelLegacy : public SelectionDAGISelLegacy {
150public:
151 static char ID;
152 MipsDAGToDAGISelLegacy(std::unique_ptr<SelectionDAGISel> S);
153 void getAnalysisUsage(AnalysisUsage &AU) const override;
154};
155}
156
157#endif
158