1//===-- RISCVRegisterInfo.h - RISC-V Register Information Impl --*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the RISC-V implementation of the TargetRegisterInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_RISCV_RISCVREGISTERINFO_H
14#define LLVM_LIB_TARGET_RISCV_RISCVREGISTERINFO_H
15
16#include "llvm/CodeGen/TargetRegisterInfo.h"
17#include "llvm/TargetParser/RISCVTargetParser.h"
18
19#define GET_REGINFO_HEADER
20#include "RISCVGenRegisterInfo.inc"
21
22namespace llvm {
23
24namespace RISCVRI {
25enum : uint8_t {
26 // The IsVRegClass value of this RegisterClass.
27 IsVRegClassShift = 0,
28 IsVRegClassShiftMask = 0b1 << IsVRegClassShift,
29 // The VLMul value of this RegisterClass. This value is valid iff IsVRegClass
30 // is true.
31 VLMulShift = IsVRegClassShift + 1,
32 VLMulShiftMask = 0b11 << VLMulShift,
33
34 // The NF value of this RegisterClass. This value is valid iff IsVRegClass is
35 // true.
36 NFShift = VLMulShift + 2,
37 NFShiftMask = 0b111 << NFShift,
38};
39
40/// \returns the IsVRegClass for the register class.
41static inline bool isVRegClass(uint8_t TSFlags) {
42 return (TSFlags & IsVRegClassShiftMask) >> IsVRegClassShift;
43}
44
45/// \returns the LMUL for the register class.
46static inline RISCVVType::VLMUL getLMul(uint8_t TSFlags) {
47 return static_cast<RISCVVType::VLMUL>((TSFlags & VLMulShiftMask) >>
48 VLMulShift);
49}
50
51/// \returns the NF for the register class.
52static inline unsigned getNF(uint8_t TSFlags) {
53 return static_cast<unsigned>((TSFlags & NFShiftMask) >> NFShift) + 1;
54}
55} // namespace RISCVRI
56
57struct RISCVRegisterInfo : public RISCVGenRegisterInfo {
58
59 RISCVRegisterInfo(unsigned HwMode);
60
61 const uint32_t *getCallPreservedMask(const MachineFunction &MF,
62 CallingConv::ID) const override;
63
64 unsigned getCSRFirstUseCost() const override {
65 // The cost will be compared against BlockFrequency where entry has the
66 // value of 1 << 14. A value of 5 will choose to spill or split cold
67 // path instead of using a callee-saved register.
68 return 5;
69 }
70
71 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
72
73 const MCPhysReg *getIPRACSRegs(const MachineFunction *MF) const override;
74
75 BitVector getReservedRegs(const MachineFunction &MF) const override;
76 bool isAsmClobberable(const MachineFunction &MF,
77 MCRegister PhysReg) const override;
78
79 const uint32_t *getNoPreservedMask() const override;
80
81 // Update DestReg to have the value SrcReg plus an offset. This is
82 // used during frame layout, and we may need to ensure that if we
83 // split the offset internally that the DestReg is always aligned,
84 // assuming that source reg was.
85 void adjustReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator II,
86 const DebugLoc &DL, Register DestReg, Register SrcReg,
87 StackOffset Offset, MachineInstr::MIFlag Flag,
88 MaybeAlign RequiredAlign) const;
89
90 bool eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
91 unsigned FIOperandNum,
92 RegScavenger *RS = nullptr) const override;
93
94 bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override;
95
96 bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
97
98 bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg,
99 int64_t Offset) const override;
100
101 Register materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx,
102 int64_t Offset) const override;
103
104 void resolveFrameIndex(MachineInstr &MI, Register BaseReg,
105 int64_t Offset) const override;
106
107 int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
108 int Idx) const override;
109
110 void lowerVSPILL(MachineBasicBlock::iterator II) const;
111 void lowerVRELOAD(MachineBasicBlock::iterator II) const;
112
113 Register getFrameRegister(const MachineFunction &MF) const override;
114
115 StringRef getRegAsmName(MCRegister Reg) const override;
116
117 bool requiresRegisterScavenging(const MachineFunction &MF) const override {
118 return true;
119 }
120
121 bool requiresFrameIndexScavenging(const MachineFunction &MF) const override {
122 return true;
123 }
124
125 const TargetRegisterClass *
126 getPointerRegClass(const MachineFunction &MF,
127 unsigned Kind = 0) const override {
128 return &RISCV::GPRRegClass;
129 }
130
131 const TargetRegisterClass *
132 getLargestLegalSuperClass(const TargetRegisterClass *RC,
133 const MachineFunction &) const override;
134
135 void getOffsetOpcodes(const StackOffset &Offset,
136 SmallVectorImpl<uint64_t> &Ops) const override;
137
138 unsigned getRegisterCostTableIndex(const MachineFunction &MF) const override;
139
140 float getSpillWeightScaleFactor(const TargetRegisterClass *RC) const override;
141
142 bool getRegAllocationHints(Register VirtReg, ArrayRef<MCPhysReg> Order,
143 SmallVectorImpl<MCPhysReg> &Hints,
144 const MachineFunction &MF, const VirtRegMap *VRM,
145 const LiveRegMatrix *Matrix) const override;
146
147 static bool isVRRegClass(const TargetRegisterClass *RC) {
148 return RISCVRI::isVRegClass(TSFlags: RC->TSFlags) &&
149 RISCVRI::getNF(TSFlags: RC->TSFlags) == 1;
150 }
151
152 static bool isVRNRegClass(const TargetRegisterClass *RC) {
153 return RISCVRI::isVRegClass(TSFlags: RC->TSFlags) && RISCVRI::getNF(TSFlags: RC->TSFlags) > 1;
154 }
155
156 static bool isRVVRegClass(const TargetRegisterClass *RC) {
157 return RISCVRI::isVRegClass(TSFlags: RC->TSFlags);
158 }
159};
160} // namespace llvm
161
162#endif
163